+#include "net_conf.h"
+#include "mx_wifi.h"
+#include "core/mx_wifi_hci.h"
+#include "core/mx_wifi_slip.h"
+
+#define DEBUG_UART_DATA (0)
+
+#if DEBUG_UART_DATA
+void debug_print(int8_t *prefix, uint8_t *data, uint16_t len)
+{
+ if (NULL != data)
+ {
+ printf("%s[%d]:\n", prefix, len);
+ for (int32_t i = 0; i < len; i++)
+ {
+ printf(" %02x", data[i]);
+ }
+ printf("\n");
+ }
+}
+#else
+#define debug_print(...)
+#endif /* DEBUG_UART_DATA */
+
+#if (MX_WIFI_USE_SPI == 0)
+
+/* Private define ------------------------------------------------------------*/
+#define MX_WIFI_HW_RESET() \
+ do {\
+ HAL_GPIO_WritePin(MXCHIP_RESET_GPIO_Port, MXCHIP_RESET_Pin, GPIO_PIN_RESET);\
+ HAL_Delay(100);\
+ HAL_GPIO_WritePin(MXCHIP_RESET_GPIO_Port, MXCHIP_RESET_Pin, GPIO_PIN_SET);\
+ HAL_Delay(1200);\
+ } while(0);
+
+
+void HWInterfaceReceivedPollTask(void const *argument);
+
+
+/* Private variables ---------------------------------------------------------*/
+extern UART_HandleTypeDef MXCHIP_UART;
+static UART_HandleTypeDef *mx_uart = &MXCHIP_UART;
+
+static MX_WIFIObject_t MxWifiObj;
+static uint8_t ch;
+static SEM_DECLARE(uart_recv_sem);
+
+static void MX_WIFI_IO_DELAY(uint32_t ms);
+static int8_t MX_WIFI_UART_Init(uint16_t mode);
+static int8_t MX_WIFI_UART_DeInit(void);
+static uint16_t MX_WIFI_UART_SendData(uint8_t *pdata, uint16_t len);
+static uint16_t MX_WIFI_UART_ReceiveData(uint8_t *pdata, uint16_t request_len);
+
+static void MX_WIFI_IO_DELAY(uint32_t ms)
+{
+#if MX_WIFI_USE_CMSIS_OS
+ osDelay(ms);
+#else
+ HAL_Delay(ms);
+#endif /* MX_WIFI_USE_CMSIS_OS */
+}
+
+
+/**
+ * @brief Initialize the UART
+ * @param None
+ * @retval None
+ */
+static int8_t MX_WIFI_UART_Init(uint16_t mode)
+{
+ int8_t rc = 0;
+
+ if (MX_WIFI_RESET == mode)
+ {
+ MX_WIFI_HW_RESET();
+ }
+ else
+ {
+
+ HAL_UART_Receive_IT(mx_uart, &ch, 1);
+
+ SEM_INIT(uart_recv_sem, 1);
+
+ THREAD_DECLARE(MX_WIFI_UARTRecvThreadId);
+
+ if (THREAD_OK == THREAD_INIT(MX_WIFI_UARTRecvThreadId,
+ HWInterfaceReceivedPollTask, NULL,
+ 200, osPriorityAboveNormal))
+ {
+ rc = MX_WIFI_STATUS_OK;
+ }
+ else
+ {
+ rc = MX_WIFI_STATUS_ERROR;
+ }
+ }
+ return rc;
+}
+
+/**
+ * @brief Deinitialize the UART
+ * @param None
+ * @retval None
+ */
+static int8_t MX_WIFI_UART_DeInit(void)
+{
+ int8_t rc = 0;
+ THREAD_DEINIT(MX_WIFI_UARTRecvThreadId);
+ SEM_DEINIT(uart_recv_sem);
+
+ if (HAL_UART_DeInit(mx_uart) != HAL_OK)
+ {
+ /* Error_Handler(); */
+ while (1);
+ }
+ return rc;
+}
+
+/**
+ * @brief Rx Callback when new data is received on the UART.
+ * @param UartHandle: Uart handle receiving the data.
+ * @retval None.
+ */
+static uint32_t circular_uart_rd = 0;
+static uint32_t circular_uart_wr = 0;
+static uint8_t circular_uart_buffer[MX_CIRCULAR_UART_RX_BUFFER_SIZE];
+
+/* sending data byte per byte to HCI would be very unefficient in term of */
+/* MCU cycles, bufferizing whole MTU is too costly, need to allocate a */
+/* while MTU buffer size and perform copy , so find a compromise */
+/* using a circular buffer approach and sending data by segment of Half */
+/* Buffer */
+void MXchip_UART_RxCpltCallback(UART_HandleTypeDef *UartHandle)
+{
+ static uint32_t circular_uart_pending_data_len = 0;
+
+ circular_uart_buffer[circular_uart_wr++] = ch;
+ circular_uart_pending_data_len++;
+ /* rewrap write index for circular index */
+ if (MX_CIRCULAR_UART_RX_BUFFER_SIZE == circular_uart_wr)
+ {
+ circular_uart_wr = 0;
+ }
+
+ if (circular_uart_wr == circular_uart_rd)
+ {
+ /* This should not happen , or we run out of buffer and data are lost */
+ while (1);
+ }
+
+ /* circular buffer is half full, so time to signal data to HCI */
+ if ((MX_CIRCULAR_UART_RX_BUFFER_SIZE / 2) == circular_uart_pending_data_len)
+ {
+ SEM_SIGNAL(uart_recv_sem);
+ circular_uart_pending_data_len = 0;
+ }
+
+ if (0 != circular_uart_pending_data_len)
+ {
+ /** use the SLIP_END character to signal data to next stage,
+ * to avoid waiting for other data that would never come
+ * in fact it should be possible to use UART nativer HW support for such detection/management.
+ */
+ if (SLIP_END == ch)
+ {
+ SEM_SIGNAL(uart_recv_sem);
+ circular_uart_pending_data_len = 0;
+ }
+ }
+
+ /* fire again request to get a new byte */
+ HAL_UART_Receive_IT(UartHandle, &ch, 1);
+}
+
+
+void process_txrx_poll(uint32_t timeout)
+{
+ /* waiting for having data received on SPI */
+ if (SEM_OK == SEM_WAIT(uart_recv_sem, timeout, NULL))
+ {
+ /* this a volatile so copy it to a local one to avoid any issues */
+ uint32_t wr = circular_uart_wr;
+ uint32_t rd = circular_uart_rd;
+ if (wr != rd)
+ {
+ /* wr pointer has reloop , so send the two segments */
+ do
+ {
+ mx_buf_t *nbuf = NULL;
+ nbuf = slip_input_byte(circular_uart_buffer[rd]);
+ if (NULL != nbuf)
+ {
+ debug_print("URX", MX_NET_BUFFER_PAYLOAD(nbuf), MX_NET_BUFFER_GET_PAYLOAD_SIZE(nbuf));
+ mx_wifi_hci_input(nbuf);
+ }
+ rd = rd + 1;
+ if (MX_CIRCULAR_UART_RX_BUFFER_SIZE == rd)
+ {
+ rd = 0;
+ }
+ } while (rd != wr);
+ circular_uart_rd = wr;
+ }
+ }
+}
+
+
+void HWInterfaceReceivedPollTask(void const *argument)
+{
+ while (true)
+ {
+ process_txrx_poll(WAIT_FOREVER);
+ }
+}
+
+
+/**
+ * @brief Send wifi Data through UART
+ * @param pdata : pointer to data
+ * @param len : Data length
+ * @retval Length of sent data
+ */
+static uint16_t MX_WIFI_UART_SendData(uint8_t *pdata, uint16_t len)
+{
+ uint16_t rc = len;
+ debug_print("UTX", pdata, len);
+
+ if (HAL_UART_Transmit(mx_uart, pdata, len, 200) != HAL_OK)
+ {
+ rc = 0;
+ }
+ return rc;
+}
+
+static uint16_t MX_WIFI_UART_ReceiveData(uint8_t *pdata, uint16_t request_len)
+{
+ uint16_t len = request_len;
+
+ if (HAL_UART_Receive(mx_uart, pdata, len, 100) != HAL_OK)
+ {
+ len = 0;
+ }
+
+ return len;
+}
+
+/**
+ * @brief probe function to register wifi to connectivity framwotk
+ * @param None
+ * @retval None
+ */
+int32_t mxwifi_probe(void **ll_drv_context)
+{
+ if (MX_WIFI_RegisterBusIO(&MxWifiObj,
+ MX_WIFI_UART_Init,
+ MX_WIFI_UART_DeInit,
+ MX_WIFI_IO_DELAY,
+ MX_WIFI_UART_SendData,
+ MX_WIFI_UART_ReceiveData) == 0)
+ {
+ *ll_drv_context = &MxWifiObj;
+ return 0;
+ }
+
+ return -1;
+}
+
+MX_WIFIObject_t *wifi_obj_get(void)
+{
+ return &MxWifiObj;
+}
+#endif /* MX_WIFI_USE_SPI */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/mx_wifi/mx_wifi.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/mx_wifi/mx_wifi.c
new file mode 100644
index 00000000..f798a8c5
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/mx_wifi/mx_wifi.c
@@ -0,0 +1,3249 @@
+/**
+ ******************************************************************************
+ * @file mx_wifi.c
+ * @author MCD Application Team
+ * @brief Host driver API of MXCHIP Wi-Fi component.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "mx_wifi.h"
+#include "core/mx_wifi_ipc.h"
+
+/* Private defines -----------------------------------------------------------*/
+
+/* debug log function */
+#ifdef MX_WIFI_API_DEBUG
+#define DEBUG_LOG(M, ...) (void) printf((M), ##__VA_ARGS__)
+#else
+#define DEBUG_LOG(M, ...)
+#endif /* MX_WIFI_API_DEBUG */
+
+#define MX_HTONL(A) ((((uint32_t)(A) & 0xff000000U) >> 24) | \
+ (((uint32_t)(A) & 0x00ff0000U) >> 8) | \
+ (((uint32_t)(A) & 0x0000ff00U) << 8) | \
+ (((uint32_t)(A) & 0x000000ffU) << 24))
+
+#define MX_NTOHL MX_HTONL
+
+
+#define MX_IN_RANGE(c, lo, up) (((c) >= (lo)) && ((c) <= (up)))
+#define MX_IS_PRINT(c) (MX_IN_RANGE((c), 0x20, 0x7f))
+#define MX_ISDIGIT(c) (MX_IN_RANGE((c), '0', '9'))
+#define MX_ISXDIGIT(c) (MX_ISDIGIT(c) || MX_IN_RANGE((c), 'a', 'f') || MX_IN_RANGE((c), 'A', 'F'))
+#define MX_ISLOWER(c) (MX_IN_RANGE((c), 'a', 'z'))
+#define MX_ISSPACE(c) (((c) == ' ')\
+ || ((c) == '\f') || ((c) == '\n') || ((c) == '\r') || ((c) == '\t') || ((c) == '\v'))
+
+#if 0
+/* select function file descriptions */
+fd_set mc_select_rfds;
+fd_set mc_select_wfds;
+fd_set mc_select_efds;
+int32_t mc_select_ret_value;
+#endif /* 0 */
+
+MX_STAT_DECLARE();
+void _MX_WIFI_RecvThread(THREAD_CONTEXT_TYPE context);
+
+/* Private data types -----------------------------------------------*/
+typedef struct mx_in_addr
+{
+ uint32_t s_addr;
+} mx_in_addr_t;
+
+typedef struct
+{
+ uint32_t addr;
+} mx_ip4_addr_t;
+
+typedef mx_ip4_addr_t mx_ip_addr_t;
+
+
+
+#define MX_SIN_ZERO_LEN 8
+typedef struct mx_sockaddr_in
+{
+ uint8_t sin_len;
+ uint8_t sin_family;
+ uint16_t sin_port;
+ mx_in_addr_t sin_addr;
+ int8_t sin_zero[MX_SIN_ZERO_LEN];
+} mx_sockaddr_in_t;
+
+
+/* Private functions ---------------------------------------------------------*/
+static int32_t mx_aton(const int8_t *ptr, mx_ip_addr_t *addr);
+static int32_t mx_aton_r(const int8_t *cp);
+static int8_t *mx_ntoa(const mx_ip4_addr_t *addr);
+
+/**
+ * @brief Function description
+ * @param Params
+ * @retval socket status
+ */
+
+static int32_t mx_aton(const int8_t *ptr, mx_ip_addr_t *addr)
+{
+ uint32_t val = 0;
+ uint32_t base;
+ int8_t c0;
+ const int8_t *cp = ptr;
+ uint32_t parts[4];
+ uint32_t *pp = parts;
+ int32_t ret = 1;
+ int32_t done;
+
+ c0 = *cp;
+ done = 0;
+ for (;;)
+ {
+ /*
+ * Collect number up to ``.''.
+ * Values are specified as for C:
+ * 0x=hex, 0=octal, 1-9=decimal.
+ */
+ if (done == 1)
+ {
+ break;
+ }
+
+ if (!MX_ISDIGIT(c0))
+ {
+ ret = 0;
+ done = 1;
+ }
+ else
+ {
+ val = 0;
+ base = 10;
+ if (c0 == '0')
+ {
+ ++cp;
+ c0 = (int8_t) * cp;
+ if ((c0 == (int8_t) 'x') || (c0 == (int8_t) 'X'))
+ {
+ base = 16;
+ ++cp;
+ c0 = (int8_t) * cp;
+ }
+ else
+ {
+ base = 8;
+ }
+ }
+
+ for (;;)
+ {
+ if (MX_ISDIGIT(c0))
+ {
+ val = (val * base) + (uint32_t)c0 - (uint32_t) '0';
+ ++cp;
+ c0 = (int8_t) * cp;
+ }
+ else if ((base == 16U) && MX_ISXDIGIT(c0))
+ {
+ val = (val << 4) | ((uint32_t)c0 + 10U - (uint32_t)(MX_ISLOWER(c0) ? 'a' : 'A'));
+ ++cp;
+ c0 = (int8_t) * cp;
+ }
+ else
+ {
+ break;
+ }
+ }
+
+ if (c0 == '.')
+ {
+ /*
+ * Internet format:
+ * a.b.c.d
+ * a.b.c (with c treated as 16 bits)
+ * a.b (with b treated as 24 bits)
+ */
+ if (pp >= (parts + 3))
+ {
+ ret = 0;
+ done = 1;
+ }
+ else
+ {
+ *pp = val;
+ pp++;
+ ++cp;
+ c0 = (int8_t) * cp;
+ }
+ }
+ else
+ {
+ done = 1;
+ }
+ }
+ }
+ /*
+ * Check for trailing characters.
+ */
+ if ((c0 != (int8_t)'\0') && (MX_ISSPACE((c0)) == false))
+ {
+ ret = 0;
+ }
+ else
+
+ /*
+ * Concoct the address according to
+ * the number of parts specified.
+ */
+ {
+ switch (pp - parts + 1)
+ {
+ case 0:
+ ret = 0; /* initial nondigit */
+ break;
+
+ case 1: /* a -- 32 bits */
+ break;
+
+ case 2: /* a.b -- 8.24 bits */
+ if (val > 0xffffffUL)
+ {
+ ret = 0;
+ }
+ val |= parts[0] << 24;
+ break;
+
+ case 3: /* a.b.c -- 8.8.16 bits */
+ if (val > 0xffffU)
+ {
+ ret = 0;
+ break;
+ }
+ val |= (parts[0] << 24) | (parts[1] << 16);
+ break;
+
+ case 4: /* a.b.c.d -- 8.8.8.8 bits */
+ if (val > 0xffU)
+ {
+ ret = 0;
+ break;
+ }
+ val |= (parts[0] << 24) | (parts[1] << 16) | (parts[2] << 8);
+ break;
+
+ default:
+ ret = 0;
+ break;
+ }
+ }
+
+ if (ret == 1)
+ {
+ if (addr != NULL)
+ {
+ addr->addr = MX_HTONL(val);
+ }
+ }
+ return ret;
+}
+
+
+
+
+static int32_t mx_aton_r(const int8_t *cp)
+{
+ mx_ip_addr_t val;
+ int32_t ret;
+ val.addr = 0;
+ if (mx_aton(cp, &val) != 0)
+ {
+ ret = (int32_t) val.addr;
+ }
+ else
+ {
+ ret = 0;
+ }
+ return (ret);
+}
+
+
+
+/**
+ * @brief Register physical interface IO operation function
+ * @param Obj mxchip wifi object
+ * @param IO_Init IO init function
+ * @param IO_DeInit IO deinit function
+ * @param IO_Delay IO delay function
+ * @param IO_Send IO send function
+ * @param IO_Receive IO recv function
+ * @return MX_WIFI_STATUS_T status code
+ */
+MX_WIFI_STATUS_T MX_WIFI_RegisterBusIO(MX_WIFIObject_t *Obj,
+ IO_Init_Func IO_Init,
+ IO_DeInit_Func IO_DeInit,
+ IO_Delay_Func IO_Delay,
+ IO_Send_Func IO_Send,
+ IO_Receive_Func IO_Receive)
+{
+ MX_WIFI_STATUS_T rc;
+
+ if ((NULL == Obj) || (NULL == IO_Init) || (NULL == IO_DeInit) || (NULL == IO_Send) || \
+ (NULL == IO_Receive) || (NULL == IO_Delay))
+ {
+ rc = MX_WIFI_STATUS_ERROR;
+ }
+ else
+ {
+ Obj->fops.IO_Init = IO_Init;
+ Obj->fops.IO_DeInit = IO_DeInit;
+ Obj->fops.IO_Send = IO_Send;
+ Obj->fops.IO_Receive = IO_Receive;
+ Obj->fops.IO_Delay = IO_Delay;
+ rc = MX_WIFI_STATUS_OK;
+ }
+ return rc;
+}
+
+/**
+ * @brief reset wifi module by hardware
+ * @param Obj wifi object
+ * @return MX_WIFI_STATUS_T status
+ */
+MX_WIFI_STATUS_T MX_WIFI_HardResetModule(MX_WIFIObject_t *Obj)
+{
+ MX_WIFI_STATUS_T rc;
+ int32_t ret;
+
+
+ MX_STAT_INIT();
+
+ if (NULL == Obj)
+ {
+ rc = MX_WIFI_STATUS_ERROR;
+ }
+ else
+ {
+ /* reset Wi-Fi by reset pin */
+ ret = Obj->fops.IO_Init(MX_WIFI_RESET);
+ if ((int32_t)0 == ret)
+ {
+ rc = MX_WIFI_STATUS_OK;
+ }
+ else
+ {
+ rc = MX_WIFI_STATUS_ERROR;
+ }
+ }
+
+ return rc;
+}
+
+/**
+ * @brief set timeout for mxchip wifi API
+ * @param Obj wifi object
+ * @param Timeout timeout in ms
+ * @return MX_WIFI_STATUS_T status
+ */
+MX_WIFI_STATUS_T MX_WIFI_SetTimeout(MX_WIFIObject_t *Obj, uint32_t Timeout)
+{
+ MX_WIFI_STATUS_T rc;
+
+ if (NULL == Obj)
+ {
+ rc = MX_WIFI_STATUS_ERROR;
+ }
+ else
+ {
+ Obj->Runtime.Timeout = Timeout;
+ rc = MX_WIFI_STATUS_OK;
+ }
+ return rc;
+}
+
+/*
+ * run with RTOS
+ */
+
+
+/**
+ * @brief wifi stat recv thread for RTOS
+ * @param argument thread arguments
+ */
+void _MX_WIFI_RecvThread(THREAD_CONTEXT_TYPE context)
+{
+ MX_WIFIObject_t *Obj = wifi_obj_get();
+
+ if (NULL != Obj)
+ {
+ while (true)
+ {
+ (void)MX_WIFI_IO_YIELD(Obj, 500);
+ }
+ }
+ /* Delete the Thread */
+ THREAD_TERMINATE();
+}
+
+
+THREAD_DECLARE(MX_WIFI_RecvThreadId);
+
+/**
+ * @brief wifi init
+ * @param Obj wifi object
+ * @return MX_WIFI_STATUS_T status
+ */
+MX_WIFI_STATUS_T MX_WIFI_Init(MX_WIFIObject_t *Obj)
+{
+ MX_WIFI_STATUS_T ret = MX_WIFI_STATUS_ERROR;
+ uint16_t rparams_size;
+
+ if (NULL == Obj)
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ if (Obj->Runtime.interfaces == 0u)
+ {
+ LOCK_INIT(Obj->lockcmd);
+
+ /* 0. set cmd timeout */
+ Obj->Runtime.Timeout = MX_WIFI_CMD_TIMEOUT;
+
+ /* 1. init wifi low level IO(UART/SPI) */
+ (void)(Obj->fops.IO_Init(MX_WIFI_INIT));
+ {
+ /* 2. init wifi ipc */
+ if (MIPC_CODE_SUCCESS == mipc_init(Obj->fops.IO_Send))
+ {
+
+ /* 2a start thread for RTOS implementation */
+
+ if (THREAD_OK != THREAD_INIT(MX_WIFI_RecvThreadId, _MX_WIFI_RecvThread, NULL,
+ MX_WIFI_RECEIVED_THREAD_STACK_SIZE,
+ MX_WIFI_RECEIVED_THREAD_PRIORITY))
+ {
+ ret = MX_WIFI_STATUS_ERROR;
+ }
+ else
+ {
+ /* 3. get version */
+ (void)memset(&(Obj->SysInfo.FW_Rev[0]), 0, MX_WIFI_FW_REV_SIZE);
+ rparams_size = MX_WIFI_FW_REV_SIZE;
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_SYS_VERSION_CMD,
+ NULL, 0,
+ &(Obj->SysInfo.FW_Rev[0]),
+ &rparams_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ (void)strncpy((char *)(Obj->SysInfo.Product_Name),
+ MX_WIFI_PRODUCT_NAME, MX_WIFI_PRODUCT_NAME_SIZE);
+ (void)strncpy((char *)(Obj->SysInfo.Product_ID),
+ MX_WIFI_PRODUCT_ID, MX_WIFI_PRODUCT_ID_SIZE);
+
+ /* 4. get MAC */
+ (void)memset(&(Obj->SysInfo.MAC[0]), 0, MX_WIFI_MAC_SIZE);
+ rparams_size = MX_WIFI_MAC_SIZE;
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_WIFI_GET_MAC_CMD,
+ NULL, 0,
+ &(Obj->SysInfo.MAC[0]),
+ &rparams_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ ret = MX_WIFI_STATUS_OK;
+ Obj->Runtime.interfaces++;
+ } /* get MAC */
+ } /* get version */
+ }
+ }
+ }
+ }
+ else
+ {
+ Obj->Runtime.interfaces++;
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * @brief wifi deinit
+ * @param Obj wifi object
+ * @return MX_WIFI_STATUS_T
+ */
+MX_WIFI_STATUS_T MX_WIFI_DeInit(MX_WIFIObject_t *Obj)
+{
+ MX_WIFI_STATUS_T ret;
+
+ if (NULL == Obj)
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ if (Obj->Runtime.interfaces == 1u)
+ {
+ (void) THREAD_DEINIT(MX_WIFI_RecvThreadId);
+ (void)mipc_deinit();
+ Obj->fops.IO_DeInit();
+ ret = MX_WIFI_STATUS_OK;
+ Obj->Runtime.interfaces--;
+ }
+ else
+ {
+ ret = MX_WIFI_STATUS_OK;
+ if (Obj->Runtime.interfaces > 0u)
+ {
+ Obj->Runtime.interfaces--;
+ }
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * @brief wifi data yield
+ * @param Obj wifi object
+ * @param timeout timetou in ms
+ * @return MX_WIFI_STATUS_T status
+ */
+MX_WIFI_STATUS_T MX_WIFI_IO_YIELD(MX_WIFIObject_t *Obj, uint32_t timeout)
+{
+ MX_WIFI_STATUS_T ret = MX_WIFI_STATUS_OK;
+ if (NULL != Obj)
+ {
+ mipc_poll(timeout);
+ }
+ return ret;
+}
+
+/**
+ * @brief wifi software reboot
+ * @param Obj wifi object
+ * @return MX_WIFI_STATUS_T status
+ */
+MX_WIFI_STATUS_T MX_WIFI_ResetModule(MX_WIFIObject_t *Obj)
+{
+ MX_WIFI_STATUS_T ret = MX_WIFI_STATUS_ERROR;
+
+ if (NULL == Obj)
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_SYS_REBOOT_CMD, NULL, 0,
+ NULL, 0, MX_WIFI_CMD_TIMEOUT))
+ {
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+ return ret;
+}
+
+/**
+ * @brief wifi factory reset
+ * @param Obj wifi object
+ * @return MX_WIFI_STATUS_T
+ */
+MX_WIFI_STATUS_T MX_WIFI_ResetToFactoryDefault(MX_WIFIObject_t *Obj)
+{
+ MX_WIFI_STATUS_T ret = MX_WIFI_STATUS_ERROR;
+
+ if (NULL == Obj)
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_SYS_RESET_CMD, NULL, 0,
+ NULL, 0, MX_WIFI_CMD_TIMEOUT))
+ {
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+ return ret;
+}
+
+/**
+ * @brief wifi get firmware version
+ * @param Obj wifi object
+ * @param version buffer to get version
+ * @param size buffer size
+ * @return MX_WIFI_STATUS_T status
+ */
+MX_WIFI_STATUS_T MX_WIFI_GetVersion(MX_WIFIObject_t *Obj, uint8_t *version, uint32_t size)
+{
+ MX_WIFI_STATUS_T ret = MX_WIFI_STATUS_ERROR;
+ uint16_t rparams_size;
+
+ if ((NULL == Obj) || (NULL == version) || (size > (uint32_t)MX_WIFI_FW_REV_SIZE) \
+ || ((uint32_t)0 == size))
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ (void)memset(&(Obj->SysInfo.FW_Rev[0]), 0, MX_WIFI_FW_REV_SIZE);
+ rparams_size = MX_WIFI_FW_REV_SIZE;
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_SYS_VERSION_CMD, NULL, 0,
+ &(Obj->SysInfo.FW_Rev[0]),
+ &rparams_size, MX_WIFI_CMD_TIMEOUT))
+ {
+ (void)memcpy(version, &(Obj->SysInfo.FW_Rev[0]), MX_WIFI_FW_REV_SIZE);
+ ret = MX_WIFI_STATUS_OK;
+ }
+
+ }
+ return ret;
+}
+
+/**
+ * @brief wifi get MAC address
+ * @param Obj wifi object
+ * @param mac buffer to get MAC address (6 bytes)
+ * @return MX_WIFI_STATUS_T status
+ */
+MX_WIFI_STATUS_T MX_WIFI_GetMACAddress(MX_WIFIObject_t *Obj, uint8_t *mac)
+{
+ MX_WIFI_STATUS_T ret;
+
+ if ((NULL == Obj) || (NULL == mac))
+ {
+ ret = MX_WIFI_STATUS_ERROR;
+ }
+ else
+ {
+ (void)memcpy(mac, Obj->SysInfo.MAC, MX_WIFI_MAC_SIZE);
+ ret = MX_WIFI_STATUS_OK;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief wifi scan start
+ * @param Obj wifi object
+ * @param scan_mode scan mode
+ * @param ssid ssid to scan
+ * @param len max number to scan
+ * @return MX_WIFI_STATUS_T status
+ */
+MX_WIFI_STATUS_T MX_WIFI_Scan(MX_WIFIObject_t *Obj, mc_wifi_scan_mode_t scan_mode,
+ char *ssid, int32_t len)
+{
+ MX_WIFI_STATUS_T ret = MX_WIFI_STATUS_ERROR;
+ wifi_scan_cparams_t cparams;
+ wifi_scan_rparams_t *rparams_p = (wifi_scan_rparams_t *)(&(Obj->Runtime.scan_result[0]));
+ uint16_t rparams_size;
+
+ if ((NULL == Obj) || (((mc_wifi_scan_mode_t)MC_SCAN_ACTIVE == scan_mode) &&
+ ((NULL == ssid) || (len <= 0) || (len > 32))))
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ memset(&cparams, 0, sizeof(cparams));
+ memcpy(&(cparams.ssid[0]), ssid, len);
+ rparams_size = MX_WIFI_SCAN_BUF_SIZE;
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_WIFI_SCAN_CMD,
+ (uint8_t *)&cparams, sizeof(cparams),
+ (uint8_t *)rparams_p, &rparams_size,
+ MX_WIFI_SCAN_TIMEOUT))
+ {
+ Obj->Runtime.scan_number = rparams_p->num;
+ memcpy(&(Obj->Runtime.scan_result[0]), &(rparams_p->ap[0]),
+ Obj->Runtime.scan_number * sizeof(mwifi_ap_info_t));
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+ return ret;
+}
+
+/**
+ * @brief get wifi scan result
+ * @param Obj wifi object
+ * @param results buffer to get scan result
+ * @param number max ap number to get
+ * @return int8_t ap number got
+ */
+int8_t MX_WIFI_Get_scan_result(MX_WIFIObject_t *Obj, uint8_t *results, uint8_t number)
+{
+ int8_t copy_number;
+
+ if ((NULL == Obj) || (NULL == results) || ((uint8_t)0 == number))
+ {
+ copy_number = 0;
+ }
+ else
+ {
+ copy_number = (int8_t)(MIN(Obj->Runtime.scan_number, number));
+ (void)memcpy(results, Obj->Runtime.scan_result, (size_t)copy_number * sizeof(mwifi_ap_info_t));
+ }
+ return copy_number;
+}
+
+/**
+ * @brief register wifi station status event callback
+ * @param Obj wifi object
+ * @param cb callback function
+ * @param arg callback argument
+ * @return MX_WIFI_STATUS_T status
+ */
+MX_WIFI_STATUS_T MX_WIFI_RegisterStatusCallback(MX_WIFIObject_t *Obj,
+ mx_wifi_status_callback_t cb,
+ void *arg)
+{
+ MX_WIFI_STATUS_T rc;
+
+ if (NULL == Obj)
+ {
+ rc = MX_WIFI_STATUS_ERROR;
+ }
+ else
+ {
+ Obj->Runtime.status_cb[0] = cb;
+ Obj->Runtime.callback_arg[0] = arg;
+ rc = MX_WIFI_STATUS_OK;
+ }
+ return rc;
+}
+
+/**
+ * @brief unregister wifi station event callback function
+ * @param Obj wifi object
+ * @return MX_WIFI_STATUS_T status
+ */
+MX_WIFI_STATUS_T MX_WIFI_UnRegisterStatusCallback(MX_WIFIObject_t *Obj)
+{
+ MX_WIFI_STATUS_T rc;
+
+ if (NULL == Obj)
+ {
+ rc = MX_WIFI_STATUS_ERROR;
+ }
+ else
+ {
+ Obj->Runtime.status_cb[0] = NULL;
+ Obj->Runtime.callback_arg[0] = NULL;
+ rc = MX_WIFI_STATUS_OK;
+ }
+ return rc;
+}
+
+/**
+ * @brief register wifi event callback for station or AP mode
+ * @param Obj wifi object
+ * @param cb callback function
+ * @param arg callback argument
+ * @param interface wifi mode
+ * @return MX_WIFI_STATUS_T status
+ */
+MX_WIFI_STATUS_T MX_WIFI_RegisterStatusCallback_if(MX_WIFIObject_t *Obj,
+ mx_wifi_status_callback_t cb,
+ void *arg,
+ mwifi_if_t interface)
+{
+ MX_WIFI_STATUS_T rc;
+
+ if (NULL == Obj)
+ {
+ rc = MX_WIFI_STATUS_ERROR;
+ }
+ else
+ {
+ if ((mwifi_if_t)MC_SOFTAP == interface)
+ {
+ Obj->Runtime.status_cb[1] = cb;
+ Obj->Runtime.callback_arg[1] = arg;
+ }
+ else
+ {
+ Obj->Runtime.status_cb[0] = cb;
+ Obj->Runtime.callback_arg[0] = arg;
+ }
+ rc = MX_WIFI_STATUS_OK;
+
+ }
+ return rc;
+}
+
+/**
+ * @brief register wifi event callback for station or AP mode
+ * @param Obj wifi object
+ * @param interface wifi mode
+ * @return MX_WIFI_STATUS_T
+ */
+MX_WIFI_STATUS_T MX_WIFI_UnRegisterStatusCallback_if(MX_WIFIObject_t *Obj, mwifi_if_t interface)
+{
+ MX_WIFI_STATUS_T rc;
+
+ if (NULL == Obj)
+ {
+ rc = MX_WIFI_STATUS_ERROR;
+ }
+ else
+ {
+ if ((mwifi_if_t)MC_SOFTAP == interface)
+ {
+ Obj->Runtime.status_cb[1] = NULL;
+ Obj->Runtime.callback_arg[1] = NULL;
+ }
+ else
+ {
+ Obj->Runtime.status_cb[0] = NULL;
+ Obj->Runtime.callback_arg[0] = NULL;
+ }
+ rc = MX_WIFI_STATUS_OK;
+ }
+ return rc;
+}
+
+
+static int8_t *mx_ntoa(const mx_ip4_addr_t *addr)
+{
+ uint32_t MX_S_ADDR;
+ uint8_t val;
+ int8_t inv[3];
+ uint8_t *ap;
+ uint8_t rem;
+ uint8_t i;
+ int32_t len = 0;
+ int8_t *buf_ret;
+ static int8_t buf[16];
+
+ MX_S_ADDR = addr->addr;
+
+ ap = (uint8_t *)&MX_S_ADDR;
+ for (uint8_t n = 0; n < (uint8_t) 4; n++)
+ {
+ i = 0;
+ val = ap[n];
+ do
+ {
+ rem = val % 10U;
+ val /= 10U;
+ inv[i] = (int8_t)'0' + rem;
+ i++;
+ } while (val != 0U);
+
+ while (i != 0U)
+ {
+ i--;
+ if (len < 16)
+ {
+ buf[len] = inv[i];
+ len++;
+ }
+ }
+
+ if ((n < 3U) && (len < 16))
+ {
+ buf[len] = (int8_t) '.';
+ len++;
+ }
+ }
+
+ if (len < 16)
+ {
+ buf[len] = (int8_t) '\0';
+ buf_ret = buf;
+
+ }
+ else
+ {
+ buf_ret = (int8_t *) "000.000.000.000";
+ }
+
+ return buf_ret;
+}
+
+
+/**
+ * @brief wifi connect to an AP
+ * @param Obj wifi object
+ * @param SSID ssid of AP
+ * @param Password password of AP
+ * @param SecType security type (not used, auto)
+ * @return MX_WIFI_STATUS_T status
+ */
+MX_WIFI_STATUS_T MX_WIFI_Connect(MX_WIFIObject_t *Obj, const char *SSID,
+ const char *Password, MX_WIFI_SecurityType_t SecType)
+{
+ MX_WIFI_STATUS_T ret = MX_WIFI_STATUS_ERROR;
+ wifi_connect_cparams_t cparams;
+ int32_t status = MIPC_CODE_ERROR;
+ uint16_t rparams_size;
+ mwifi_ip_attr_t ip_attr;
+ mx_ip4_addr_t net_ipaddr;
+
+ (void)SecType;
+
+ if ((NULL == Obj) || (NULL == SSID) || (strlen(SSID) > (uint32_t)MX_MAX_SSID_LEN)
+ || (NULL == Password) || (strlen(Password) > (uint32_t)MX_MAX_KEY_LEN))
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ strncpy((char *)cparams.ssid, SSID, MX_MAX_SSID_LEN);
+ strncpy((char *)cparams.key, Password, MX_MAX_KEY_LEN);
+ cparams.key_len = strlen(Password);
+ cparams.use_attr = 0;
+ cparams.use_ip = 0;
+
+ if ((uint8_t)0 == Obj->NetSettings.DHCP_IsEnabled)
+ {
+ (void)memset(&ip_attr, 0, sizeof(mwifi_ip_attr_t));
+ (void)memcpy(&net_ipaddr, Obj->NetSettings.IP_Addr, 4);
+ (void)memcpy(ip_attr.localip, mx_ntoa(&net_ipaddr), MX_MAX_IP_LEN);
+ (void)memcpy(&net_ipaddr, Obj->NetSettings.IP_Mask, 4);
+ (void)memcpy(ip_attr.netmask, mx_ntoa(&net_ipaddr), MX_MAX_IP_LEN);
+ (void)memcpy(&net_ipaddr, Obj->NetSettings.Gateway_Addr, 4);
+ (void)memcpy(ip_attr.gateway, mx_ntoa(&net_ipaddr), MX_MAX_IP_LEN);
+ (void)memcpy(&net_ipaddr, Obj->NetSettings.DNS1, 4);
+ (void)memcpy(ip_attr.dnserver, mx_ntoa(&net_ipaddr), MX_MAX_IP_LEN);
+ cparams.use_ip = 1;
+ memcpy(&(cparams.ip), &ip_attr, sizeof(cparams.ip));
+ }
+
+ rparams_size = sizeof(status);
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_WIFI_CONNECT_CMD,
+ (uint8_t *)&cparams, sizeof(cparams),
+ (uint8_t *)&status, &rparams_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ if (MIPC_CODE_SUCCESS == status)
+ {
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+
+ }
+ return ret;
+}
+
+/**
+ * @brief connect to an AP with WAP-E
+ * @param Obj wifi object
+ * @param SSID ssid of AP
+ * @param Identity identity of client
+ * @param Password password of client
+ * @param attr EAP attribute
+ * @param ip ip attribute
+ * @return MX_WIFI_STATUS_T status
+ */
+MX_WIFI_STATUS_T MX_WIFI_EAP_Connect(MX_WIFIObject_t *Obj, const char *SSID,
+ const char *Identity, const char *Password,
+ mwifi_eap_attr_t *attr, mwifi_ip_attr_t *ip)
+{
+ MX_WIFI_STATUS_T ret = MX_WIFI_STATUS_OK;
+
+#if 0
+ lib_ipc_eap_attr_t ipc_eap_attr;
+
+ if ((NULL == Obj) || (NULL == SSID) || (strlen(SSID) > (uint32_t)MX_MAX_SSID_LEN) || \
+ (NULL == Identity) || (strlen(Identity) > (uint32_t)MX_MAX_IDENTITY_LEN) || \
+ (NULL == Password) || (strlen(Password) > (uint32_t)MX_MAX_KEY_LEN))
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ if (!MX_WIFI_LOCK((Obj)))
+ {
+ ret = MX_WIFI_STATUS_TIMEOUT;
+ }
+ else
+ {
+ (void)memset(&ipc_eap_attr, 0, sizeof(ipc_eap_attr));
+
+ if (NULL != attr)
+ {
+ /* just set eap type here, rootca/cert/key set by specifical API */
+ if (((uint8_t)EAP_TYPE_TLS != attr->eap_type) && ((uint8_t)EAP_TYPE_TTLS != attr->eap_type) &&
+ ((uint8_t)EAP_TYPE_PEAP != attr->eap_type))
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ ipc_eap_attr.eap_type = attr->eap_type;
+
+ if (NULL != attr->rootca)
+ {
+ if (MIPC_CODE_SUCCESS != wifi_eap_set_rootca_cmd(attr->rootca, strlen(attr->rootca)))
+ {
+ ret = MX_WIFI_STATUS_ERROR;
+ }
+ }
+
+ if ((MX_WIFI_STATUS_OK == ret) && (NULL != attr->client_cert))
+ {
+ if (MIPC_CODE_SUCCESS != wifi_eap_set_client_cert_cmd(attr->client_cert, strlen(attr->client_cert)))
+ {
+ ret = MX_WIFI_STATUS_ERROR;
+ }
+ }
+
+ if ((MX_WIFI_STATUS_OK == ret) && (NULL != attr->client_key))
+ {
+ if (MIPC_CODE_SUCCESS != wifi_eap_set_client_key_cmd(attr->client_key, strlen(attr->client_key)))
+ {
+ ret = MX_WIFI_STATUS_ERROR;
+ }
+ }
+ }
+ }
+ else
+ {
+ ipc_eap_attr.eap_type = (uint8_t)EAP_TYPE_PEAP; /* default eap type */
+ }
+
+ if (MX_WIFI_STATUS_OK == ret)
+ {
+ if (MIPC_CODE_SUCCESS != wifi_eap_connect_cmd(SSID, (int32_t)strlen(SSID),
+ Identity, (int32_t)strlen(Identity),
+ Password, (int32_t)strlen(Password),
+ &ipc_eap_attr, sizeof(ipc_eap_attr),
+ ip, (NULL != ip) ? sizeof(mwifi_ip_attr_t) : 0u))
+ {
+ ret = MX_WIFI_STATUS_ERROR;
+ }
+ }
+
+ (void)MX_WIFI_UNLOCK((Obj));
+ }
+ }
+#endif /* 0 */
+
+ return ret;
+}
+
+/**
+ * @brief wifi station disconnect
+ * @param Obj wifi object
+ * @return MX_WIFI_STATUS_T status
+ */
+MX_WIFI_STATUS_T MX_WIFI_Disconnect(MX_WIFIObject_t *Obj)
+{
+ MX_WIFI_STATUS_T ret = MX_WIFI_STATUS_ERROR;
+ int32_t status = MIPC_CODE_ERROR;
+ uint16_t rparams_size;
+
+ if (NULL == Obj)
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ rparams_size = sizeof(status);
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_WIFI_DISCONNECT_CMD, NULL, 0,
+ (uint8_t *)&status, &rparams_size,
+ 15000)) /* disconnect max timeout 15s */
+ {
+ if (MIPC_CODE_SUCCESS == status)
+ {
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+ }
+ return ret;
+}
+
+/**
+ * @brief connect AP with WPS
+ * @param Obj wifi object
+ * @return MX_WIFI_STATUS_T status
+ */
+MX_WIFI_STATUS_T MX_WIFI_WPS_Connect(MX_WIFIObject_t *Obj)
+{
+ MX_WIFI_STATUS_T ret = MX_WIFI_STATUS_ERROR;
+
+#if 0
+ int32_t ret_flag = MIPC_RET_FLAG_CLR;
+ int32_t addr_ret_val;
+ int32_t addr_ret_flag;
+ int32_t *p_addr_ret_val;
+ int32_t *p_addr_ret_flag;
+
+ if (NULL != Obj)
+ {
+ p_addr_ret_val = &ret;
+ p_addr_ret_flag = &ret_flag;
+ (void)memcpy(&addr_ret_val, &p_addr_ret_val, sizeof(addr_ret_val));
+ (void)memcpy(&addr_ret_flag, &p_addr_ret_flag, sizeof(addr_ret_flag));
+ if (MIPC_CODE_SUCCESS == wifi_wps_connect_cmd(addr_ret_val, addr_ret_flag))
+ {
+ if (MIPC_CODE_SUCCESS == mipc_poll(&ret_flag, &ret, Obj->Runtime.Timeout))
+ {
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+ }
+#endif /* 0 */
+
+ return ret;
+}
+
+/**
+ * @brief stop connecting to an AP with WPS
+ * @param Obj wifi object
+ * @return MX_WIFI_STATUS_T status
+ */
+MX_WIFI_STATUS_T MX_WIFI_WPS_Stop(MX_WIFIObject_t *Obj)
+{
+ MX_WIFI_STATUS_T ret = MX_WIFI_STATUS_ERROR;
+
+#if 0
+ int32_t ret_flag = MIPC_RET_FLAG_CLR;
+ int32_t addr_ret_val;
+ int32_t addr_ret_flag;
+ int32_t *p_addr_ret_val;
+ int32_t *p_addr_ret_flag;
+
+ if (NULL != Obj)
+ {
+ p_addr_ret_val = &ret;
+ p_addr_ret_flag = &ret_flag;
+ (void)memcpy(&addr_ret_val, &p_addr_ret_val, sizeof(addr_ret_val));
+ (void)memcpy(&addr_ret_flag, &p_addr_ret_flag, sizeof(addr_ret_flag));
+ if (MIPC_CODE_SUCCESS == wifi_wps_stop_cmd(addr_ret_val, addr_ret_flag))
+ {
+ if (MIPC_CODE_SUCCESS == mipc_poll(&ret_flag, &ret, Obj->Runtime.Timeout))
+ {
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+ }
+#endif /* 0 */
+
+ return ret;
+}
+
+/**
+ * @brief get wifi station connect status
+ * @param Obj wifi object
+ * @return int8_t 1 -- connected, 0 -- not connected
+ */
+int8_t MX_WIFI_IsConnected(MX_WIFIObject_t *Obj)
+{
+ int8_t ret = 0;
+ wifi_get_linkinof_rparams_t rparams;
+ uint16_t rparams_size = sizeof(rparams);
+ rparams.status = MIPC_CODE_ERROR;
+ if (NULL != Obj)
+ {
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_WIFI_GET_LINKINFO_CMD, NULL, 0,
+ (uint8_t *)&rparams, &rparams_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ if (MIPC_CODE_SUCCESS == rparams.status)
+ {
+ Obj->NetSettings.IsConnected = rparams.info.is_connected;
+ ret = Obj->NetSettings.IsConnected;
+ }
+ }
+ }
+ return ret;
+}
+
+/**
+ * @brief get wifi IPv4 address
+ * @param Obj wifi object
+ * @param ipaddr address buffer
+ * @param wifi_if wifi interface
+ * @return MX_WIFI_STATUS_T status
+ */
+MX_WIFI_STATUS_T MX_WIFI_GetIPAddress(MX_WIFIObject_t *Obj, uint8_t *ipaddr, mwifi_if_t wifi_if)
+{
+ MX_WIFI_STATUS_T ret = MX_WIFI_STATUS_ERROR;
+ wifi_get_ip_rparams_t rparams;
+ uint16_t rparams_size = sizeof(rparams);
+ int32_t ip;
+ int32_t netmask;
+ int32_t gw;
+ int32_t dns;
+
+ rparams.status = MIPC_CODE_ERROR;
+
+ if (NULL != Obj)
+ {
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_WIFI_GET_IP_CMD,
+ (uint8_t *)&wifi_if, sizeof(wifi_if),
+ (uint8_t *)&rparams, &rparams_size,
+ 1000))
+ {
+ if (MIPC_CODE_SUCCESS == rparams.status)
+ {
+ ip = mx_aton_r((int8_t const *) & (rparams.ip.localip[0]));
+ memcpy(&(Obj->NetSettings.IP_Addr[0]), &ip, 4);
+
+ netmask = mx_aton_r((int8_t const *) & (rparams.ip.netmask[0]));
+ memcpy(&(Obj->NetSettings.IP_Mask[0]), &netmask, 4);
+
+ gw = mx_aton_r((int8_t const *) & (rparams.ip.gateway[0]));
+ memcpy(&(Obj->NetSettings.Gateway_Addr[0]), &gw, 4);
+
+ dns = mx_aton_r((int8_t const *) & (rparams.ip.dnserver[0]));
+ memcpy(&(Obj->NetSettings.DNS1[0]), &dns, 4);
+
+ (void)memcpy(ipaddr, Obj->NetSettings.IP_Addr, 4);
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+ }
+ return ret;
+}
+
+/**
+ * @brief get wifi IPv6 address info
+ * @param Obj wifi object
+ * @param ipaddr6 ipv6 address buffer
+ * @param addr_num ipv6 address index (0,1,2)
+ * @param wifi_if wifi interface
+ * @return MX_WIFI_STATUS_T status
+ */
+MX_WIFI_STATUS_T MX_WIFI_GetIP6Address(MX_WIFIObject_t *Obj, uint8_t *ipaddr6, int32_t addr_num, mwifi_if_t wifi_if)
+{
+ MX_WIFI_STATUS_T ret = MX_WIFI_STATUS_ERROR;
+
+#if 0
+ int32_t ret_flag = MIPC_RET_FLAG_CLR;
+ int32_t addr_ret_flag;
+ int32_t *p_addr_ret_flag;
+
+ if ((NULL != Obj) && (NULL != ipaddr6) && (addr_num < 3) && (addr_num >= 0))
+ {
+ p_addr_ret_flag = &ret_flag;
+ (void)memcpy(&addr_ret_flag, &p_addr_ret_flag, sizeof(addr_ret_flag));
+ if (MIPC_CODE_SUCCESS == wifi_get_ip6_addr_cmd((int32_t)addr_num, (int32_t)wifi_if, addr_ret_flag))
+ {
+ if (MIPC_CODE_SUCCESS == mipc_poll(&ret_flag, NULL, Obj->Runtime.Timeout))
+ {
+ (void)memcpy(ipaddr6, Obj->NetSettings.IP6_Addr[addr_num], 16);
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+ }
+#endif /* 0 */
+
+ return ret;
+}
+
+/**
+ * @brief Get the local IPv6 address state of the wifi module.
+ * @param Obj: pointer to module handle
+ * @param addr_num: index of the IPv6 address (index: 0/1/2).
+ * @param wifi_if: wifi mode(station or softap).
+ * @retval IPV6 address State, error if < 0
+ */
+int32_t MX_WIFI_GetIP6AddressState(MX_WIFIObject_t *Obj, int32_t addr_num, mwifi_if_t wifi_if)
+{
+ int32_t state = MX_WIFI_STATUS_ERROR;
+
+#if 0
+ int32_t ret_flag = MIPC_RET_FLAG_CLR;
+ int32_t addr_ret_flag;
+ int32_t *p_addr_ret_flag;
+
+ if ((NULL != Obj) && (addr_num < 3) && (addr_num >= 0))
+ {
+ p_addr_ret_flag = &ret_flag;
+ (void)memcpy(&addr_ret_flag, &p_addr_ret_flag, sizeof(addr_ret_flag));
+ if (MIPC_CODE_SUCCESS == wifi_get_ip6_state_cmd((int32_t)addr_num, (int32_t)wifi_if, addr_ret_flag))
+ {
+ if (MIPC_CODE_SUCCESS == mipc_poll(&ret_flag, NULL, Obj->Runtime.Timeout))
+ {
+ state = Obj->NetSettings.IP6_state[addr_num];
+ }
+ }
+ }
+#endif /* 0 */
+
+ return state;
+}
+
+/*
+* SoftAP
+ */
+
+/**
+ * @brief Start softAP(miniAP) mode
+ * @param Obj: pointer to module handle
+ * @param ap_settings: softAP settings.
+ * @retval Operation Status.
+ */
+MX_WIFI_STATUS_T MX_WIFI_StartAP(MX_WIFIObject_t *Obj, MX_WIFI_APSettings_t *ap_settings)
+{
+ MX_WIFI_STATUS_T ret = MX_WIFI_STATUS_ERROR;
+ wifi_softap_start_cparams_t cparams;
+ int32_t status = MIPC_CODE_ERROR;
+ uint16_t rparams_size = sizeof(status);
+
+ if ((NULL == Obj) || (NULL == ap_settings))
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ memcpy((char *)cparams.ssid, ap_settings->SSID, sizeof(cparams.ssid));
+ memcpy((char *)cparams.key, ap_settings->pswd, sizeof(cparams.key));
+ cparams.channel = ap_settings->channel;
+ memcpy(&(cparams.ip), &(ap_settings->ip), sizeof(cparams.ip));
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_WIFI_SOFTAP_START_CMD,
+ (uint8_t *)&cparams, sizeof(cparams),
+ (uint8_t *)&status, &rparams_size,
+ 3000))
+ {
+ if (MIPC_CODE_SUCCESS == status)
+ {
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+ }
+ return ret;
+}
+
+/**
+ * @brief Stop softAP(miniAP) mode
+ * @param Obj: pointer to module handle
+ * @retval Operation Status.
+ */
+MX_WIFI_STATUS_T MX_WIFI_StopAP(MX_WIFIObject_t *Obj)
+{
+ MX_WIFI_STATUS_T ret = MX_WIFI_STATUS_ERROR;
+ int32_t status = MIPC_CODE_ERROR;
+ uint16_t out_size = sizeof(status);
+
+ if (NULL != Obj)
+ {
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_WIFI_SOFTAP_STOP_CMD, NULL, 0,
+ (uint8_t *)&status, &out_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ if (MIPC_CODE_SUCCESS == status)
+ {
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+ }
+ return ret;
+}
+
+#if MX_WIFI_NETWORK_BYPASS_MODE == 0
+/**
+ * @brief Create a socket.
+ * @param Obj: pointer to module handle
+ * @param domain: socket domain
+ * @param type: socket type
+ * @param protocol: socket protocol
+ * @retval Socket file descriptor, return < 1 if failed.
+ */
+int32_t MX_WIFI_Socket_create(MX_WIFIObject_t *Obj, int32_t domain, int32_t type, int32_t protocol)
+{
+ int32_t ret_fd = -1;
+ socket_create_cparams_t cp;
+ socket_create_rparams_t rp;
+ uint16_t out_size = sizeof(rp);
+
+ if (NULL != Obj)
+ {
+ cp.domain = domain;
+ cp.type = type;
+ cp.protocol = protocol;
+ memset(&rp, 0, sizeof(rp));
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_SOCKET_CREATE_CMD,
+ (uint8_t *)&cp, sizeof(cp),
+ (uint8_t *)&rp, &out_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ ret_fd = rp.fd;
+ }
+ }
+
+ return ret_fd;
+}
+
+/**
+ * @brief Set option for a socket
+ * @param Obj: pointer to module handle
+ * @param sockfd: socket fd
+ * @param level: option level
+ * @param optname: option to set
+ * @param optvalue: value buffer for the option
+ * @param optlen: length of the option value
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_Socket_setsockopt(MX_WIFIObject_t *Obj, int32_t sockfd, int32_t level,
+ int32_t optname, const void *optvalue, int32_t optlen)
+{
+ int32_t ret = MX_WIFI_STATUS_ERROR;
+ socket_setsockopt_cparams_t cp;
+ socket_setsockopt_rparams_t rp;
+ uint16_t out_size = sizeof(rp);
+
+ rp.status = MIPC_CODE_ERROR;
+ if ((NULL == Obj) || (sockfd < 0) || (NULL == optvalue) || (optlen <= 0))
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ cp.socket = sockfd;
+ cp.level = level;
+ cp.optname = optname;
+ cp.optlen = optlen > sizeof(cp.optval) ? sizeof(cp.optval) : optlen;
+ memcpy(&(cp.optval[0]), optvalue, cp.optlen);
+ memset(&rp, 0, sizeof(rp));
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_SOCKET_SETSOCKOPT_CMD,
+ (uint8_t *)&cp, sizeof(cp),
+ (uint8_t *)&rp, &out_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ if (rp.status == MIPC_CODE_SUCCESS)
+ {
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+ }
+ return ret;
+}
+
+/**
+ * @brief Get option of a socket.
+ * @param Obj: pointer to module handle
+ * @param sockfd: socket fd
+ * @param level: option level
+ * @param optname: option to set
+ * @param optvalue: buffer pointer of value of the option
+ * @param optlen: buffer pointer of length of the option value
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_Socket_getsockopt(MX_WIFIObject_t *Obj, int32_t sockfd, int32_t level,
+ int32_t optname, void *optvalue, uint32_t *optlen)
+{
+ int32_t ret = MX_WIFI_STATUS_ERROR;
+ socket_getsockopt_cparams_t cp;
+ socket_getsockopt_rparams_t rp;
+ uint16_t out_size = sizeof(rp);
+ rp.status = MIPC_CODE_ERROR;
+
+ if ((NULL == Obj) || (sockfd < 0) || (NULL == optvalue) || (NULL == optlen))
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ cp.socket = sockfd;
+ cp.level = level;
+ cp.optname = optname;
+ memset(&rp, 0, sizeof(rp));
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_SOCKET_GETSOCKOPT_CMD,
+ (uint8_t *)&cp, sizeof(cp),
+ (uint8_t *)&rp, &out_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ if (rp.status == MIPC_CODE_SUCCESS)
+ {
+ *optlen = (rp.optlen > (*optlen)) ? (*optlen) : rp.optlen;
+ memcpy(optvalue, &(rp.optval[0]), *optlen);
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+ }
+ return ret;
+}
+
+/**
+ * @brief Bind a socket.
+ * @param Obj: pointer to module handle
+ * @param sockfd: socket fd
+ * @param addr: socket address
+ * @param addrlen: address length
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_Socket_bind(MX_WIFIObject_t *Obj, int32_t sockfd,
+ const struct sockaddr *addr, int32_t addrlen)
+{
+ int32_t ret = MX_WIFI_STATUS_ERROR;
+ socket_bind_cparams_t cp;
+ socket_bind_rparams_t rp;
+ uint16_t out_size = sizeof(rp);
+ rp.status = MIPC_CODE_ERROR;
+
+ if ((NULL == Obj) || (sockfd < 0) || (NULL == addr) || (addrlen <= 0))
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ cp.socket = sockfd;
+ memcpy(&(cp.addr), addr, sizeof(cp.addr));
+ cp.length = addrlen;
+ memset(&rp, 0, sizeof(rp));
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_SOCKET_BIND_CMD,
+ (uint8_t *)&cp, sizeof(cp),
+ (uint8_t *)&rp, &out_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ if (rp.status == MIPC_CODE_SUCCESS)
+ {
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+ }
+ return ret;
+}
+
+/**
+ * @brief Listen a socket.
+ * @param Obj: pointer to module handle
+ * @param sockfd: socket fd
+ * @param backlog: max number to queued.
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_Socket_listen(MX_WIFIObject_t *Obj, int32_t sockfd, int32_t backlog)
+{
+ int32_t ret = MX_WIFI_STATUS_ERROR;
+ socket_listen_cparams_t cp;
+ socket_listen_rparams_t rp;
+ uint16_t rp_size = sizeof(rp);
+ rp.status = MIPC_CODE_ERROR;
+
+ if ((NULL == Obj) || (sockfd < 0))
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ cp.socket = sockfd;
+ cp.n = backlog;
+ memset(&rp, 0, sizeof(rp));
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_SOCKET_LISTEN_CMD,
+ (uint8_t *)&cp, sizeof(cp),
+ (uint8_t *)&rp, &rp_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ if (rp.status == MIPC_CODE_SUCCESS)
+ {
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+ }
+ return ret;
+}
+
+/**
+ * @brief Accept a socket.
+ * @param Obj: pointer to module handle
+ * @param sockfd: socket fd
+ * @param addr: client address
+ * @param addrlen: length of client address
+ * @retval Accepted client socket fd, return < 0 if failed.
+ */
+int32_t MX_WIFI_Socket_accept(MX_WIFIObject_t *Obj, int32_t sockfd,
+ struct sockaddr *addr, uint32_t *addrlen)
+{
+ int32_t ret_fd = -1;
+ socket_accept_cparams_t cp;
+ socket_accept_rparams_t rp;
+ uint16_t rp_size = sizeof(rp);
+ rp.socket = -1;
+
+ if ((NULL == Obj) || (sockfd < 0) || (NULL == addr) || (NULL == addrlen))
+ {
+ ret_fd = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ cp.socket = sockfd;
+ memset(&rp, 0, sizeof(rp));
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_SOCKET_ACCEPT_CMD,
+ (uint8_t *)&cp, sizeof(cp),
+ (uint8_t *)&rp, &rp_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ if (rp.socket >= 0)
+ {
+ memcpy(addr, &(rp.addr), sizeof(rp.addr));
+ *addrlen = rp.length;
+ ret_fd = rp.socket;
+ }
+ }
+ }
+ return ret_fd;
+}
+
+/**
+ * @brief Socket connect.
+ * @param Obj: pointer to module handle
+ * @param sockfd: socket fd
+ * @param addr: client address
+ * @param addrlen: length of client address
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_Socket_connect(MX_WIFIObject_t *Obj, int32_t sockfd,
+ const struct sockaddr *addr, int32_t addrlen)
+{
+ int32_t ret = MX_WIFI_STATUS_ERROR;
+ socket_connect_cparams_t cp;
+ socket_connect_rparams_t rp;
+ uint16_t out_size = sizeof(rp);
+ rp.status = MIPC_CODE_ERROR;
+
+ if ((NULL == Obj) || (sockfd < 0) || (NULL == addr) || (addrlen <= 0))
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ cp.socket = sockfd;
+ memcpy(&(cp.addr), addr, sizeof(cp.addr));
+ cp.length = addrlen;
+ memset(&rp, 0, sizeof(rp));
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_SOCKET_CONNECT_CMD,
+ (uint8_t *)&cp, sizeof(cp),
+ (uint8_t *)&rp, &out_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ if (rp.status == MIPC_CODE_SUCCESS)
+ {
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+ }
+ return ret;
+}
+
+/**
+ * @brief Socket shutdown.
+ * @param Obj: pointer to module handle
+ * @param sockfd: socket fd
+ * @param mode: shutdown mode:
+ * 0 Stop receiving data for this socket;
+ * 1 Stop trying to transmit data from this socket
+ * 2 Stop all transmit from this socket
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_Socket_shutdown(MX_WIFIObject_t *Obj, int32_t sockfd, int32_t mode)
+{
+ int32_t ret = MX_WIFI_STATUS_ERROR;
+ socket_shutdown_cparams_t cp;
+ socket_shutdown_rparams_t rp;
+ uint16_t out_size = sizeof(rp);
+ rp.status = MIPC_CODE_ERROR;
+
+ if ((NULL == Obj) || (sockfd < 0))
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ cp.filedes = sockfd;
+ cp.how = mode;
+ memset(&rp, 0, sizeof(rp));
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_SOCKET_SHUTDOWN_CMD,
+ (uint8_t *)&cp, sizeof(cp),
+ (uint8_t *)&rp, &out_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ if (rp.status == MIPC_CODE_SUCCESS)
+ {
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+ }
+ return ret;
+}
+
+/**
+ * @brief Socket close.
+ * @param Obj: pointer to module handle
+ * @param sockfd: socket fd
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_Socket_close(MX_WIFIObject_t *Obj, int32_t sockfd)
+{
+ int32_t ret = MX_WIFI_STATUS_ERROR;
+ socket_close_cparams_t cp;
+ socket_close_rparams_t rp;
+ uint16_t out_size = sizeof(rp);
+ rp.status = MIPC_CODE_ERROR;
+
+ if ((NULL == Obj) || (sockfd < 0))
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ cp.filedes = sockfd;
+ memset(&rp, 0, sizeof(rp));
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_SOCKET_CLOSE_CMD,
+ (uint8_t *)&cp, sizeof(cp),
+ (uint8_t *)&rp, &out_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ if (rp.status == MIPC_CODE_SUCCESS)
+ {
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+ }
+ return ret;
+}
+
+/**
+ * @brief Socket send.
+ * @param Obj: pointer to module handle
+ * @param sockfd: socket fd
+ * @param buf: send data buffer
+ * @param len: length of send data
+ * @param flags: zero for MXOS
+ * @retval Number of bytes sent, return < 0 if failed.
+ */
+int32_t MX_WIFI_Socket_send(MX_WIFIObject_t *Obj, int32_t sockfd, uint8_t *buf,
+ int32_t len, int32_t flags)
+{
+ int32_t ret = -1;
+ socket_send_cparams_t *cp;
+ uint16_t cp_size;
+ socket_send_rparams_t rp;
+ uint16_t rp_size = sizeof(rp);
+ int32_t datalen;
+
+ if ((NULL == Obj) || (sockfd < 0) || (NULL == buf) || (len <= 0))
+ {
+ ret = -1;
+ }
+ else
+ {
+ if ((len + sizeof(socket_send_cparams_t) - 1) > MX_WIFI_IPC_PAYLOAD_SIZE)
+ {
+ datalen = (MX_WIFI_IPC_PAYLOAD_SIZE - (sizeof(socket_send_cparams_t) - 1));
+ }
+ else
+ {
+ datalen = len;
+ }
+ rp.sent = 0;
+ cp_size = (sizeof(socket_send_cparams_t) - 1 + datalen);
+ cp = (socket_send_cparams_t *)MX_WIFI_MALLOC(cp_size);
+ if (NULL != cp)
+ {
+ cp->socket = sockfd;
+ memcpy(&(cp->buffer[0]), buf, datalen);
+ cp->size = datalen;
+ cp->flags = flags;
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_SOCKET_SEND_CMD,
+ (uint8_t *)cp, cp_size,
+ (uint8_t *)&rp, &rp_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ ret = rp.sent;
+ }
+ MX_WIFI_FREE(cp);
+ }
+ }
+ return ret;
+}
+
+/**
+ * @brief Socket sendto.
+ * @param Obj: pointer to module handle
+ * @param sockfd: socket fd
+ * @param buf: send data buffer
+ * @param len: length of send data
+ * @param flags: zero for MXOS
+ * @param toaddr: address to send
+ * @param toaddrlen: length of address to send
+ * @retval Number of bytes sent, return < 0 if failed.
+ */
+int32_t MX_WIFI_Socket_sendto(MX_WIFIObject_t *Obj, int32_t sockfd, uint8_t *buf,
+ int32_t len, int32_t flags,
+ struct sockaddr *toaddr, int32_t toaddrlen)
+{
+ int32_t ret = -1;
+ socket_sendto_cparams_t *cp;
+ uint16_t cp_size;
+ socket_sendto_rparams_t rp;
+ uint16_t rp_size = sizeof(rp);
+ int32_t datalen;
+
+ if ((NULL == Obj) || (sockfd < 0) || (NULL == buf) || (len <= 0) || (NULL == toaddr) || (toaddrlen <= 0))
+ {
+ ret = -1;
+ }
+ else
+ {
+ if ((len + sizeof(socket_sendto_cparams_t) - 1) > MX_WIFI_IPC_PAYLOAD_SIZE)
+ {
+ datalen = (MX_WIFI_IPC_PAYLOAD_SIZE - (sizeof(socket_sendto_cparams_t) - 1));
+ }
+ else
+ {
+ datalen = len;
+ }
+ cp_size = (sizeof(socket_sendto_cparams_t) - 1 + datalen);
+ cp = (socket_sendto_cparams_t *)MX_WIFI_MALLOC(cp_size);
+ if (NULL != cp)
+ {
+ rp.sent = 0;
+ cp->socket = sockfd;
+ memcpy(&(cp->buffer[0]), buf, datalen);
+ cp->size = datalen;
+ cp->flags = flags;
+ memcpy(&(cp->addr), toaddr, sizeof(cp->addr));
+ cp->length = toaddrlen;
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_SOCKET_SENDTO_CMD,
+ (uint8_t *)cp, cp_size,
+ (uint8_t *)&rp, &rp_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ ret = rp.sent;
+ }
+ MX_WIFI_FREE(cp);
+ }
+ }
+ return ret;
+}
+
+/**
+ * @brief Socket recv.
+ * @param Obj: pointer to module handle
+ * @param sockfd: socket fd
+ * @param buf: recv buffer
+ * @param len: length of recv buffer
+ * @param flags: zero for MXOS
+ * @retval Number of bytes received, return < 0 if failed.
+ */
+int32_t MX_WIFI_Socket_recv(MX_WIFIObject_t *Obj, int32_t sockfd, uint8_t *buf,
+ int32_t len, int32_t flags)
+{
+ int32_t ret = -1;
+ socket_recv_cparams_t cp;
+ socket_recv_rparams_t *rp;
+ uint16_t rp_size;
+ int32_t datalen;
+
+ if ((NULL == Obj) || (sockfd < 0) || (NULL == buf) || (len <= 0))
+ {
+ ret = -1;
+ }
+ else
+ {
+ ret = 0;
+ if ((len + sizeof(socket_recv_rparams_t) - 1) > MX_WIFI_IPC_PAYLOAD_SIZE)
+ {
+ datalen = (MX_WIFI_IPC_PAYLOAD_SIZE - (sizeof(socket_recv_rparams_t) - 1));
+ }
+ else
+ {
+ datalen = len;
+ }
+ rp_size = (sizeof(socket_recv_rparams_t) - 1 + datalen);
+ rp = (socket_recv_rparams_t *)MX_WIFI_MALLOC(rp_size);
+ if (NULL != rp)
+ {
+ rp->received = 0;
+ cp.socket = sockfd;
+ cp.size = datalen;
+ cp.flags = flags;
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_SOCKET_RECV_CMD,
+ (uint8_t *)&cp, sizeof(cp),
+ (uint8_t *)rp, &rp_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ if ((rp->received <= datalen) && (rp->received > 0))
+ {
+ memcpy(buf, &(rp->buffer[0]), rp->received);
+ }
+ ret = rp->received;
+ }
+ MX_WIFI_FREE(rp);
+ }
+ }
+ return ret;
+}
+
+/**
+ * @brief Socket recvfrom.
+ * @param Obj: pointer to module handle
+ * @param sockfd: socket fd
+ * @param buf: recv buffer
+ * @param len: length of recv buffer
+ * @param fromaddr: address of the data source
+ * @param fromaddrlen: length of address of the data source
+ * @param flags: zero for MXOS
+ * @retval Number of bytes received, return < 0 if failed.
+ */
+int32_t MX_WIFI_Socket_recvfrom(MX_WIFIObject_t *Obj, int32_t sockfd, uint8_t *buf,
+ int32_t len, int32_t flags,
+ struct sockaddr *fromaddr, uint32_t *fromaddrlen)
+{
+ int32_t ret = -1;
+ socket_recvfrom_cparams_t cp;
+ socket_recvfrom_rparams_t *rp;
+ uint16_t rp_size;
+ int32_t datalen;
+
+ if ((NULL == Obj) || (sockfd < 0) || (NULL == buf) || (len <= 0) || (NULL == fromaddr) \
+ || (NULL == fromaddrlen))
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ ret = 0;
+ if ((len + sizeof(socket_recvfrom_rparams_t) - 1) > MX_WIFI_IPC_PAYLOAD_SIZE)
+ {
+ datalen = (MX_WIFI_IPC_PAYLOAD_SIZE - (sizeof(socket_recvfrom_rparams_t) - 1));
+ }
+ else
+ {
+ datalen = len;
+ }
+ rp_size = (sizeof(socket_recvfrom_rparams_t) - 1 + datalen);
+ rp = (socket_recvfrom_rparams_t *)MX_WIFI_MALLOC(rp_size);
+ if (NULL != rp)
+ {
+ rp->received = 0;
+ cp.socket = sockfd;
+ cp.size = datalen;
+ cp.flags = flags;
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_SOCKET_RECVFROM_CMD,
+ (uint8_t *)&cp, sizeof(cp),
+ (uint8_t *)rp, &rp_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ if ((rp->received <= datalen) && (rp->received > 0))
+ {
+ memcpy(buf, &(rp->buffer[0]), rp->received);
+ ret = rp->received;
+ memcpy(fromaddr, &(rp->addr), sizeof(rp->addr));
+ *fromaddrlen = rp->length;
+ }
+ }
+ MX_WIFI_FREE(rp);
+ }
+ }
+ return ret;
+}
+
+/**
+ * @brief Gethostbyname, only for IPv4 address.
+ * @param Obj: pointer to module handle
+ * @param addr: address of the host
+ * @param name: hostname
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_Socket_gethostbyname(MX_WIFIObject_t *Obj, struct sockaddr *addr, char *name)
+{
+ int32_t ret = MX_WIFI_STATUS_ERROR;
+ mx_sockaddr_in_t addr_in;
+ socket_gethostbyname_cparams_t cp;
+ socket_gethostbyname_rparams_t rp;
+ uint16_t rp_size = sizeof(rp);
+ rp.status = MIPC_CODE_ERROR;
+
+ if ((NULL == Obj) || (NULL == addr) || (NULL == name) || (strlen(name) > (uint32_t)MX_MAX_DNSNAME_LEN))
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ uint32_t msize;
+ memset(&cp, 0, sizeof(cp));
+ msize = MIN(sizeof(cp.name), strlen(name) + 1);
+ memcpy(&(cp.name[0]), name, msize);
+ memset(&rp, 0, sizeof(rp));
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_SOCKET_GETHOSTBYNAME_CMD,
+ (uint8_t *)&cp, sizeof(cp),
+ (uint8_t *)&rp, &rp_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ if (rp.status == MIPC_CODE_SUCCESS)
+ {
+ addr_in.sin_addr.s_addr = rp.s_addr;
+ addr_in.sin_family = AF_INET;
+ addr_in.sin_len = sizeof(addr_in);
+ memcpy(addr, &addr_in, sizeof(struct sockaddr));
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+ }
+ return ret;
+}
+
+/**
+ * @brief Ping a host, only for IPv4 address.
+ * @param Obj: pointer to module handle
+ * @param addr: hostname
+ * @param count: ping max count
+ * @param delay: ping delay in millisecond
+ * @param response: response time array of ping result
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_Socket_ping(MX_WIFIObject_t *Obj, const char *hostname,
+ int32_t count, int32_t delay, int32_t response[])
+{
+ int32_t ret = MX_WIFI_STATUS_ERROR;
+ wifi_ping_cparams_t cp;
+ int32_t ping_resp[1 + MX_WIFI_PING_MAX];
+ wifi_ping_rparams_t *rp;
+ uint16_t rp_size = sizeof(ping_resp);
+ int32_t i = 0;
+
+ if ((NULL == Obj) || (NULL == hostname) || (count <= 0))
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ int32_t msize;
+ memset(&cp, 0, sizeof(cp));
+ msize = MIN(sizeof(cp.hostname), strlen(hostname) + 1);
+ memcpy(&(cp.hostname[0]), hostname, msize);
+ cp.count = count;
+ cp.delay_ms = delay;
+ memset(ping_resp, 0, sizeof(ping_resp));
+ rp = (wifi_ping_rparams_t *)&ping_resp;
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_WIFI_PING_CMD,
+ (uint8_t *)&cp, sizeof(cp),
+ (uint8_t *)rp, &rp_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ if (rp->num > 0)
+ {
+ for (i = 0; i < rp->num; i++)
+ {
+ response[i] = rp->delay_ms[i];
+ }
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+ }
+ return ret;
+}
+
+#if 0
+/**
+ * @brief Get IPv4/v6 address info by nodename.
+ * @param Obj: pointer to module handle
+ * @param nodename: descriptive name or address string of the host
+ * @param servname: not used, set NULL
+ * @param hints: structure containing input values that set socktype and protocol
+ * @param res: buf to store the result (set to NULL on failure)
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_Socket_getaddrinfo(MX_WIFIObject_t *Obj, const char *nodename, const char *servname,
+ const struct addrinfo *hints, struct mc_addrinfo *res)
+{
+ int32_t ret = MX_WIFI_STATUS_ERROR;
+ int32_t ret_flag = MIPC_RET_FLAG_CLR;
+ int32_t addr_ret_val;
+ int32_t addr_ret_flag;
+ int32_t *p_addr_ret_val;
+ int32_t *p_addr_ret_flag;
+
+ if ((NULL == Obj) || (NULL == nodename) || (NULL == hints) || (NULL == res))
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ p_addr_ret_val = &ret;
+ p_addr_ret_flag = &ret_flag;
+ (void)memcpy(&addr_ret_val, &p_addr_ret_val, sizeof(addr_ret_val));
+ (void)memcpy(&addr_ret_flag, &p_addr_ret_flag, sizeof(addr_ret_flag));
+ if (MIPC_CODE_SUCCESS == socket_getaddrinfo_cmd(nodename, (int32_t)strlen(nodename),
+ servname, (int32_t)strlen(servname),
+ (void *)hints, sizeof(struct addrinfo), (int)res,
+ addr_ret_val, addr_ret_flag))
+ {
+ if (MIPC_CODE_SUCCESS == mipc_poll(&ret_flag, NULL, Obj->Runtime.Timeout))
+ {
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+ }
+ return ret;
+}
+
+/**
+ * @brief Monitor multiple file descriptors for sockets
+ * @attention Never doing operations in different threads
+ * @param Obj: pointer to module handle
+ * @param nfds: is the highest-numbered file descriptor in any of the three
+ * sets, plus 1
+ * @param readfds: A file descriptor sets will be watched to see if characters
+ * become available for reading
+ * @param writefds: A file descriptor sets will be watched to see if a write
+ * will not block.
+ * @param exceptfds: A file descriptor sets will be watched for exceptions.
+ * @param timeout: The timeout argument specifies the interval that select()
+ * should block waiting for a file descriptor to become ready.
+ * If timeout is NULL (no timeout), select() can block until API timeout.
+ * @retval On success, return the number of file descriptors contained in the
+ * three returned descriptor sets (that is, the total number of bits
+ * that are set in readfds, writefds, exceptfds) which may be zero if
+ * the timeout expires before anything interesting happens. On error,
+ * -1 is returned, the file descriptor sets are unmodified, and timeout
+ * becomes undefined.
+ */
+int32_t MX_WIFI_Socket_select(MX_WIFIObject_t *Obj, int32_t nfds, fd_set *readfds, fd_set *writefds,
+ fd_set *exceptfds, struct mc_timeval *timeout)
+{
+ int32_t ret = -1; /* error */
+ int32_t ret_flag = MIPC_RET_FLAG_CLR;
+ int32_t *p_ret_flag;
+ int32_t addr_ret_flag;
+
+ if ((NULL != Obj) && (nfds > 0) && ((NULL != readfds) || (NULL != writefds) || (NULL != exceptfds)))
+ {
+ p_ret_flag = &ret_flag;
+ (void)memcpy(&addr_ret_flag, &p_ret_flag, sizeof(addr_ret_flag));
+ if (MIPC_CODE_SUCCESS == socket_select_cmd(nfds, readfds, sizeof(fd_set),
+ writefds, sizeof(fd_set),
+ exceptfds, sizeof(fd_set),
+ timeout, sizeof(struct mc_timeval),
+ addr_ret_flag))
+ {
+ if (MIPC_CODE_SUCCESS == mipc_poll(&ret_flag, NULL, 200))
+ {
+ ret = mc_select_ret_value;
+ if (ret > 0)
+ {
+ if (readfds)
+ {
+ (void)memcpy(readfds, &mc_select_rfds, sizeof(fd_set));
+ }
+ if (writefds)
+ {
+ (void)memcpy(writefds, &mc_select_wfds, sizeof(fd_set));
+ }
+ if (exceptfds)
+ {
+ (void)memcpy(exceptfds, &mc_select_efds, sizeof(fd_set));
+ }
+ }
+ mc_select_ret_value = -1;
+ }
+ }
+ }
+ return ret;
+}
+#endif /* 0 */
+
+/**
+ * @brief socket getpeername.
+ * @param Obj: pointer to module handle
+ * @param sockfd: socket fd
+ * @param addr: address buffer
+ * @param addrlen: size of address buffer
+ * @retval get address of peer socket, return < 0 if failed.
+ */
+int32_t MX_WIFI_Socket_getpeername(MX_WIFIObject_t *Obj, int32_t sockfd, struct sockaddr *addr, uint32_t *addrlen)
+{
+ int32_t ret = -1;
+ socket_getpeername_cparams_t cp;
+ socket_getpeername_rparams_t rp;
+ uint16_t rp_size = sizeof(rp);
+
+ if ((NULL == Obj) || (sockfd < 0) || (NULL == addr) || (NULL == addrlen) || (*addrlen <= 0))
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ cp.s = sockfd;
+ memset(&rp, 0, sizeof(rp));
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_SOCKET_GETPEERNAME_CMD,
+ (uint8_t *)&cp, sizeof(cp),
+ (uint8_t *)&rp, &rp_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ if (MIPC_CODE_SUCCESS == rp.status)
+ {
+ memcpy(addr, &(rp.name), sizeof(rp.name));
+ *addrlen = rp.namelen;
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+ }
+ return ret;
+}
+
+/**
+ * @brief socket getsockname.
+ * @param Obj: pointer to module handle
+ * @param sockfd: socket fd
+ * @param addr: address buffer
+ * @param addrlen: size of address buffer
+ * @retval get address of local socket, return < 0 if failed.
+ */
+int32_t MX_WIFI_Socket_getsockname(MX_WIFIObject_t *Obj, int32_t sockfd, struct sockaddr *addr, uint32_t *addrlen)
+{
+ int32_t ret = -1;
+ socket_getsockname_cparams_t cp;
+ socket_getsockname_rparams_t rp;
+ uint16_t rp_size = sizeof(rp);
+ rp.status = MIPC_CODE_ERROR;
+
+ if ((NULL == Obj) || (sockfd < 0) || (NULL == addr) || (NULL == addrlen) || (*addrlen <= 0))
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ cp.s = sockfd;
+ memset(&rp, 0, sizeof(rp));
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_SOCKET_GETSOCKNAME_CMD,
+ (uint8_t *)&cp, sizeof(cp),
+ (uint8_t *)&rp, &rp_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ if (MIPC_CODE_SUCCESS == rp.status)
+ {
+ memcpy(addr, &(rp.name), sizeof(rp.name));
+ *addrlen = rp.namelen;
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+ }
+ return ret;
+}
+
+/* mDNS */
+
+/**
+ * @brief start mDNS service.
+ * @param Obj: pointer to module handle
+ * @param domain: domain of service
+ * @param name: hostname
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_MDNS_start(MX_WIFIObject_t *Obj, const char *domain, char *hostname)
+{
+ int32_t ret = MX_WIFI_STATUS_ERROR;
+ mdns_start_cparams_t cparams;
+ int32_t status;
+ uint16_t out_size = sizeof(status);
+ status = MIPC_CODE_ERROR;
+
+ if (NULL == Obj)
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ memset(&cparams, 0, sizeof(cparams));
+ memcpy(&(cparams.domain[0]), domain, sizeof(cparams.domain));
+ memcpy(&(cparams.hostname[0]), hostname, sizeof(cparams.hostname));
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_MDNS_START_CMD,
+ (uint8_t *)&cparams, sizeof(cparams),
+ (uint8_t *)&status, &out_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ if (MIPC_CODE_SUCCESS == status)
+ {
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * @brief stop mDNS service.
+ * @param Obj: pointer to module handle
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_MDNS_stop(MX_WIFIObject_t *Obj)
+{
+ int32_t ret = MX_WIFI_STATUS_ERROR;
+ int32_t status = MIPC_CODE_ERROR;
+ uint16_t rparams_size;
+
+ if (NULL == Obj)
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ rparams_size = sizeof(status);
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_MDNS_STOP_CMD, NULL, 0,
+ (uint8_t *)&status, &rparams_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ if (MIPC_CODE_SUCCESS == status)
+ {
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+ }
+ return ret;
+}
+
+/**
+ * @brief announce a service.
+ * @param Obj: pointer to module handle
+ * @param service: service to announce
+ * @param interface: wifi interface
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_MDNS_announce_service(MX_WIFIObject_t *Obj,
+ struct mc_mdns_service *service, mwifi_if_t interface)
+{
+ int32_t ret = MX_WIFI_STATUS_ERROR;
+ mdns_announce_cparams_t cparams;
+ int32_t status = MIPC_CODE_ERROR;
+ uint16_t out_size = sizeof(status);
+
+ if ((NULL == Obj) || (NULL == service))
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ memset(&cparams, 0, sizeof(cparams));
+ cparams.iface = interface;
+ memcpy(&(cparams.service_data), service, sizeof(cparams.service_data));
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_MDNS_ANNOUNCE_CMD,
+ (uint8_t *)&cparams, sizeof(cparams),
+ (uint8_t *)&status, &out_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ if (MIPC_CODE_SUCCESS == status)
+ {
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * @brief deannounce a service.
+ * @param Obj: pointer to module handle
+ * @param service: service to deannounce
+ * @param interface: wifi interface
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_MDNS_deannounce_service(MX_WIFIObject_t *Obj,
+ struct mc_mdns_service *service,
+ mwifi_if_t interface)
+{
+ int32_t ret = MX_WIFI_STATUS_ERROR;
+ mdns_deannounce_cparams_t cparams;
+ int32_t status = MIPC_CODE_ERROR;
+ uint16_t out_size = sizeof(status);
+
+ if ((NULL == Obj) || (NULL == service))
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ memset(&cparams, 0, sizeof(cparams));
+ cparams.iface = interface;
+ memcpy(&(cparams.service_data), service, sizeof(cparams.service_data));
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_MDNS_DEANNOUNCE_CMD,
+ (uint8_t *)&cparams, sizeof(cparams),
+ (uint8_t *)&status, &out_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ if (MIPC_CODE_SUCCESS == status)
+ {
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * @brief deannounce all services.
+ * @param Obj: pointer to module handle
+ * @param interface: wifi interface
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_MDNS_deannounce_service_all(MX_WIFIObject_t *Obj, mwifi_if_t interface)
+{
+ int32_t ret = MX_WIFI_STATUS_ERROR;
+ mdns_deannounce_all_cparams_t cparams;
+ int32_t status = MIPC_CODE_ERROR;
+ uint16_t out_size = sizeof(status);
+
+ if (NULL == Obj)
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ memset(&cparams, 0, sizeof(cparams));
+ cparams.iface = interface;
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_MDNS_DEANNOUNCE_ALL_CMD,
+ (uint8_t *)&cparams, sizeof(cparams),
+ (uint8_t *)&status, &out_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ if (MIPC_CODE_SUCCESS == status)
+ {
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Send interface state change event to mdns
+ * @param Obj: pointer to module handle
+ * @param interface: wifi interface
+ * @param state: state event, valid interface state from \ref iface_state
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_MDNS_iface_state_change(MX_WIFIObject_t *Obj, mwifi_if_t interface,
+ enum iface_state state)
+{
+ int32_t ret = MX_WIFI_STATUS_ERROR;
+ mdns_iface_state_change_cparams_t cparams;
+ int32_t status = MIPC_CODE_ERROR;
+ uint16_t out_size = sizeof(status);
+
+ if (NULL == Obj)
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ memset(&cparams, 0, sizeof(cparams));
+ cparams.iface = interface;
+ cparams.state = state;
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_MDNS_IFACE_STATE_CHANGE_CMD,
+ (uint8_t *)&cparams, sizeof(cparams),
+ (uint8_t *)&status, &out_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ if (MIPC_CODE_SUCCESS == status)
+ {
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Set new host name, use mdns_iface_state_change(interface, REANNOUNCE) to anounce
+ * the new host name.
+ * @param Obj: pointer to module handle
+ * @param hostname: new hostname
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_MDNS_set_hostname(MX_WIFIObject_t *Obj, char *hostname)
+{
+ int32_t ret = MX_WIFI_STATUS_ERROR;
+ mdns_set_hostname_cparams_t cparams;
+ int32_t status = MIPC_CODE_ERROR;
+ uint16_t out_size = sizeof(status);
+
+ if (NULL == Obj)
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ memset(&cparams, 0, sizeof(cparams));
+ strncpy(cparams.hostname, hostname, MDNS_MAX_LABEL_LEN);
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_MDNS_SET_HOSTNAME_CMD,
+ (uint8_t *)&cparams, sizeof(cparams),
+ (uint8_t *)&status, &out_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ if (MIPC_CODE_SUCCESS == status)
+ {
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+ }
+ return ret;
+}
+
+/**
+ * @brief sets the TXT record field for a given mDNS service.
+ * @param Obj: pointer to module handle
+ * @param service: mDNS service
+ * @param keyvals: new txt record string
+ * @param separator: the separator used to separate individual key value pairs
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_MDNS_set_txt_rec(MX_WIFIObject_t *Obj, struct mc_mdns_service *service, char *keyvals,
+ char separator)
+{
+ int32_t ret = MX_WIFI_STATUS_ERROR;
+ mdns_set_txt_rec_cparams_t cparams;
+ int32_t status = MIPC_CODE_ERROR;
+ uint16_t out_size = sizeof(status);
+
+ if (NULL == Obj)
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ memset(&cparams, 0, sizeof(cparams));
+ memcpy(&(cparams.service_data), service, sizeof(cparams.service_data));
+ strncpy(cparams.keyvals, keyvals, MDNS_MAX_KEYVAL_LEN);
+ cparams.separator = separator;
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_MDNS_SET_TXT_REC_CMD,
+ (uint8_t *)&cparams, sizeof(cparams),
+ (uint8_t *)&status, &out_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ if (MIPC_CODE_SUCCESS == status)
+ {
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+ }
+ return ret;
+}
+
+/* TLS */
+
+/**
+ * @brief set the TLS protocol version.
+ * @param Obj: pointer to module handle
+ * @param version: TLS protocol version
+ * @retval Operation Status.
+ * @note This function should be called before TLS is ready to function (before
+ * mtls_connect and mtls_accept is called by application ).
+ */
+int32_t MX_WIFI_TLS_set_ver(MX_WIFIObject_t *Obj, mtls_ver_t version)
+{
+ int32_t ret = MX_WIFI_STATUS_ERROR;
+ tls_set_ver_cparams_t cp;
+ tls_set_ver_rparams_t rp;
+ uint16_t out_size = sizeof(rp);
+
+ if ((NULL == Obj))
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ cp.version = version;
+ memset(&rp, 0, sizeof(rp));
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_TLS_SET_VER_CMD,
+ (uint8_t *)&cp, sizeof(cp),
+ (uint8_t *)&rp, &out_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ if (MIPC_CODE_SUCCESS == rp.ret)
+ {
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * @brief TLS set client certificate
+ * @param Obj: pointer to module handle
+ * @param client_cert: Point to buffer of client cert.
+ * @param cert_len: length of the client cert.
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_TLS_set_clientCertificate(MX_WIFIObject_t *Obj, uint8_t *client_cert, uint16_t cert_len)
+{
+ int32_t ret = MX_WIFI_STATUS_ERROR;
+ tls_set_client_cert_cparams_t *cp;
+ uint16_t cp_size;
+ tls_set_client_cert_rparams_t rp;
+ uint16_t out_size = sizeof(rp);
+
+ cp_size = sizeof(tls_set_client_cert_cparams_t) -1 + cert_len;
+ if ((NULL == Obj) || (NULL == client_cert) || (cert_len == (uint16_t)0)
+ || (cp_size > (uint16_t)(MX_WIFI_IPC_PAYLOAD_SIZE)))
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ cp = (tls_set_client_cert_cparams_t *)MX_WIFI_MALLOC(cp_size);
+ if (NULL != cp)
+ {
+ memset(cp, 0, cp_size);
+ cp->cert_pem_size = cert_len;
+ cp->private_key_pem_size = 0;
+ memcpy(&(cp->cert_data[0]), client_cert, cert_len);
+ memset(&rp, 0, sizeof(rp));
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_TLS_SET_CLIENT_CERT_CMD,
+ (uint8_t *)cp, cp_size,
+ (uint8_t *)&rp, &out_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ if (MIPC_CODE_SUCCESS == rp.ret)
+ {
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+ MX_WIFI_FREE(cp);
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * @brief TLS set client private key
+ * @param Obj: pointer to module handle
+ * @param client_private_key: Point to buffer of client private key.
+ * @param key_len: length of the client cert.
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_TLS_set_clientPrivateKey(MX_WIFIObject_t *Obj, uint8_t *client_private_key, uint16_t key_len)
+{
+ int32_t ret = MX_WIFI_STATUS_ERROR;
+ tls_set_client_cert_cparams_t *cp;
+ uint16_t cp_size;
+ tls_set_client_cert_rparams_t rp;
+ uint16_t out_size = sizeof(rp);
+
+ cp_size = sizeof(tls_set_client_cert_cparams_t) -1 + key_len;
+ if ((NULL == Obj) || (NULL == client_private_key) || (key_len == (uint16_t)0)
+ || (cp_size > (uint16_t)(MX_WIFI_IPC_PAYLOAD_SIZE)))
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ cp = (tls_set_client_cert_cparams_t *)MX_WIFI_MALLOC(cp_size);
+ if (NULL != cp)
+ {
+ memset(cp, 0, cp_size);
+ cp->cert_pem_size = 0;
+ cp->private_key_pem_size = key_len;
+ memcpy(&(cp->cert_data[0]), client_private_key, key_len);
+ memset(&rp, 0, sizeof(rp));
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_TLS_SET_CLIENT_CERT_CMD,
+ (uint8_t *)cp, cp_size,
+ (uint8_t *)&rp, &out_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ if (MIPC_CODE_SUCCESS == rp.ret)
+ {
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+ MX_WIFI_FREE(cp);
+ }
+ }
+ return ret;
+}
+
+/**
+ * @brief TLS client create a TLS connection.
+ * @param Obj: pointer to module handle
+ * @details This function is called on the client side and initiates an TLS/TLS handshake with a
+ * server. When this function is called, the underlying communication channel has already
+ * been set up. This function is called after TCP 3-way handshake finished.
+ * @param domain: Specifies a communication domain
+ * @param type: Specifies the communication semantics.
+ * @param protocol: specifies a particular protocol to be used with the socket.
+ * @param addr: Point to the target address to be connected
+ * @param addrlen: containing the size of the buffer pointed to by addr
+ * @param ca: pointer to the CA certificate string, used to verify server's certificate.
+ * @param calen: the string length of ca. 0=do not verify server's certificate.
+ * @retval return the TLS context pointer on success or NULL for fail.
+ */
+int32_t MX_WIFI_TLS_connect(MX_WIFIObject_t *Obj, int32_t domain, int32_t type, int32_t protocol,
+ const struct sockaddr *addr, int32_t addrlen, char *ca, int32_t calen)
+{
+ int32_t ret = MX_WIFI_STATUS_ERROR;
+ (void)domain;
+ (void)type;
+ (void)protocol;
+
+ if ((NULL == Obj) || (NULL == addr) || (addrlen <= 0))
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ ret = MX_WIFI_TLS_connect_sni(Obj, NULL, 0, addr, addrlen, ca, calen);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief TLS client create a TLS connection with SNI.
+ * @param Obj: pointer to module handle
+ * @details This function is called on the client side and initiates an TLS/TLS handshake with a
+ * server. When this function is called, the underlying communication channel has already
+ * been set up. This function is called after TCP 3-way handshake finished.
+ * @param sni_servername: Specifies the SNI server name
+ * @param sni_servername_len: Specifies the SNI server name length, max size MX_TLS_SNI_SERVERNAME_SIZE
+ * @param addr: Point to the target address to be connected
+ * @param addrlen: containing the size of the buffer pointed to by addr
+ * @param ca: pointer to the CA certificate string, used to verify server's certificate.
+ * @param calen: the string length of ca. 0=do not verify server's certificate.
+ * @retval return the TLS context pointer on success or NULL for fail.
+ */
+int32_t MX_WIFI_TLS_connect_sni(MX_WIFIObject_t *Obj, const char *sni_servername, int32_t sni_servername_len,
+ const struct sockaddr *addr, int32_t addrlen, char *ca, int32_t calen)
+{
+ int32_t ret = MX_WIFI_STATUS_ERROR;
+ tls_connect_sni_cparams_t *cp;
+ uint16_t cp_size;
+ tls_connect_sni_rparams_t rp;
+ uint16_t out_size = sizeof(rp);
+
+ cp_size = sizeof(tls_connect_sni_cparams_t) -1 + calen;
+ if ((NULL == Obj) || (NULL == addr) || (addrlen <= 0) || (cp_size > (uint16_t)(MX_WIFI_IPC_PAYLOAD_SIZE)))
+ {
+ ret = 0; /* null for MX_WIFI_STATUS_PARAM_ERROR */
+ }
+ else
+ {
+ rp.tls = NULL;
+ cp = (tls_connect_sni_cparams_t *)MX_WIFI_MALLOC(cp_size);
+ if (NULL != cp)
+ {
+ memset(cp, 0, cp_size);
+ if ((sni_servername_len > 0) && (NULL != sni_servername))
+ {
+ strncpy(&(cp->sni_servername[0]), sni_servername, sizeof(cp->sni_servername));
+ }
+ memcpy(&(cp->addr), addr, sizeof(cp->addr));
+ cp->length = addrlen;
+ cp->calen = calen;
+ if ((calen > 0) && (NULL != ca))
+ {
+ memcpy(&(cp->ca[0]), ca, calen);
+ }
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_TLS_CONNECT_SNI_CMD,
+ (uint8_t *)cp, cp_size,
+ (uint8_t *)&rp, &out_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ if (NULL == rp.tls)
+ {
+ ret = 0; /* NULL */
+ }
+ else
+ {
+ ret = (int32_t)rp.tls;
+ }
+ }
+ MX_WIFI_FREE(cp);
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * @brief TLS send data
+ * @param Obj: pointer to module handle
+ * @param tls: Point to the TLS context.
+ * @param data: Point to data to send.
+ * @param len: data length.
+ * @retval On success, return the number of bytes sent.
+ * On error, error code (< 0) is returned.
+ */
+int32_t MX_WIFI_TLS_send(MX_WIFIObject_t *Obj, mtls_t tls, void *data, int32_t len)
+{
+ int32_t ret = -1;
+ tls_send_cparams_t *cp;
+ uint16_t cp_size;
+ tls_send_rparams_t rp;
+ uint16_t rp_size = sizeof(rp);
+ int32_t datalen;
+
+ if ((NULL == Obj) || (NULL == tls) || (NULL == data) || (len <= 0))
+ {
+ ret = -1;
+ }
+ else
+ {
+ rp.sent = 0;
+ if ((len + sizeof(tls_send_cparams_t) - 1) > MX_WIFI_IPC_PAYLOAD_SIZE)
+ {
+ datalen = (MX_WIFI_IPC_PAYLOAD_SIZE - (sizeof(tls_send_cparams_t) - 1));
+ }
+ else
+ {
+ datalen = len;
+ }
+ cp_size = (sizeof(tls_send_cparams_t) - 1 + datalen);
+ cp = (tls_send_cparams_t *)MX_WIFI_MALLOC(cp_size);
+ if (NULL != cp)
+ {
+ cp->tls = tls;
+ memcpy(&(cp->buffer[0]), data, datalen);
+ cp->size = datalen;
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_TLS_SEND_CMD,
+ (uint8_t *)cp, cp_size,
+ (uint8_t *)&rp, &rp_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ ret = rp.sent;
+ }
+ MX_WIFI_FREE(cp);
+ }
+ }
+ return ret;
+}
+
+/**
+ * @brief TLS redeive data
+ * @param Obj: pointer to module handle
+ * @param tls: Point to the TLS context.
+ * @param data: Point to buffer to receive TLS data.
+ * @param len: max receive buffer length.
+ * @retval On success, return the number of bytes received.
+ * On error, error code (< 0) is returned.
+ */
+int32_t MX_WIFI_TLS_recv(MX_WIFIObject_t *Obj, mtls_t tls, void *buf, int32_t len)
+{
+ int32_t ret = -1;
+ tls_recv_cparams_t cp;
+ tls_recv_rparams_t *rp;
+ uint16_t rp_size;
+ int32_t datalen;
+
+ if ((NULL == Obj) || (NULL == tls) || (NULL == buf) || (len <= 0))
+ {
+ ret = -1;
+ }
+ else
+ {
+ ret = 0;
+ if ((len + sizeof(tls_recv_rparams_t) - 1) > MX_WIFI_IPC_PAYLOAD_SIZE)
+ {
+ datalen = (MX_WIFI_IPC_PAYLOAD_SIZE - (sizeof(tls_recv_rparams_t) - 1));
+ }
+ else
+ {
+ datalen = len;
+ }
+ rp_size = (sizeof(tls_recv_rparams_t) - 1 + datalen);
+ rp = (tls_recv_rparams_t *)MX_WIFI_MALLOC(rp_size);
+ if (NULL != rp)
+ {
+ rp->received = 0;
+ cp.tls = tls;
+ cp.size = datalen;
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_TLS_RECV_CMD,
+ (uint8_t *)&cp, sizeof(cp),
+ (uint8_t *)rp, &rp_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ if ((rp->received <= datalen) && (rp->received > 0))
+ {
+ memcpy(buf, &(rp->buffer[0]), rp->received);
+ }
+ ret = rp->received;
+ }
+ MX_WIFI_FREE(rp);
+ }
+ }
+ return ret;
+}
+
+/**
+ * @brief Close the TLS session, release resource.
+ * @param Obj: pointer to module handle
+ * @param tls: Point to the TLS context.
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_TLS_close(MX_WIFIObject_t *Obj, mtls_t tls)
+{
+ int32_t ret = MX_WIFI_STATUS_ERROR;
+ tls_close_cparams_t cp;
+ tls_close_rparams_t rp;
+ uint16_t out_size = sizeof(rp);
+
+ if ((NULL == Obj) || (NULL == tls))
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ cp.tls = tls;
+ memset(&rp, 0, sizeof(rp));
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_TLS_CLOSE_CMD,
+ (uint8_t *)&cp, sizeof(cp),
+ (uint8_t *)&rp, &out_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ if (rp.ret == MIPC_CODE_SUCCESS)
+ {
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+ }
+ return ret;
+}
+
+/**
+ * @brief Set TLS nonblock mode.
+ * @param Obj: pointer to module handle
+ * @param tls: Point to the TLS context.
+ * @param nonblock: true - nonblock, false - block
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_TLS_set_nonblock(MX_WIFIObject_t *Obj, mtls_t tls, int32_t nonblock)
+{
+ int32_t ret = MX_WIFI_STATUS_ERROR;
+ tls_set_nonblock_cparams_t cp;
+ tls_set_nonblock_rparams_t rp;
+ uint16_t out_size = sizeof(rp);
+
+ if ((NULL == Obj) || (NULL == tls))
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ cp.tls = tls;
+ cp.nonblock = nonblock;
+ memset(&rp, 0, sizeof(rp));
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_TLS_SET_NONBLOCK_CMD,
+ (uint8_t *)&cp, sizeof(cp),
+ (uint8_t *)&rp, &out_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ if (rp.ret == MIPC_CODE_SUCCESS)
+ {
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+ }
+ return ret;
+}
+
+/**
+ * @brief Start webserver.
+ * @param Obj: pointer to module handle
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_Webserver_start(MX_WIFIObject_t *Obj)
+{
+ int32_t ret = MX_WIFI_STATUS_ERROR;
+
+#if 0
+ int32_t ret_flag = MIPC_RET_FLAG_CLR;
+ int32_t addr_ret_val;
+ int32_t addr_ret_flag;
+ int32_t *p_addr_ret_val;
+ int32_t *p_addr_ret_flag;
+
+ if (NULL == Obj)
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ p_addr_ret_val = &ret;
+ p_addr_ret_flag = &ret_flag;
+ (void)memcpy(&addr_ret_val, &p_addr_ret_val, sizeof(addr_ret_val));
+ (void)memcpy(&addr_ret_flag, &p_addr_ret_flag, sizeof(addr_ret_flag));
+ if (MIPC_CODE_SUCCESS == web_start_cmd(addr_ret_val, addr_ret_flag))
+ {
+ if (MIPC_CODE_SUCCESS == mipc_poll(&ret_flag, &ret, Obj->Runtime.Timeout))
+ {
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+ }
+#endif /* 0 */
+
+ return ret;
+}
+
+/**
+ * @brief Stop webserver.
+ * @param Obj: pointer to module handle
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_Webserver_stop(MX_WIFIObject_t *Obj)
+{
+ int32_t ret = MX_WIFI_STATUS_ERROR;
+
+#if 0
+ int32_t ret_flag = MIPC_RET_FLAG_CLR;
+ int32_t addr_ret_val;
+ int32_t addr_ret_flag;
+ int32_t *p_addr_ret_val;
+ int32_t *p_addr_ret_flag;
+
+ if (NULL == Obj)
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ p_addr_ret_val = &ret;
+ p_addr_ret_flag = &ret_flag;
+ (void)memcpy(&addr_ret_val, &p_addr_ret_val, sizeof(addr_ret_val));
+ (void)memcpy(&addr_ret_flag, &p_addr_ret_flag, sizeof(addr_ret_flag));
+ if (MIPC_CODE_SUCCESS == web_stop_cmd(addr_ret_val, addr_ret_flag))
+ {
+ if (MIPC_CODE_SUCCESS == mipc_poll(&ret_flag, &ret, Obj->Runtime.Timeout))
+ {
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+ }
+#endif /* 0 */
+
+ return ret;
+}
+
+/**
+ * @brief Start FOTA.
+ * @param Obj: pointer to module handle
+ * @param url: HTTP/HTTPS url of bin file to update
+ * @param md5: MD5 string(32Bytes) of bin file to update
+ * @param ota_status_callback: callback function for ota status
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_FOTA_start(MX_WIFIObject_t *Obj, const char *url, const char *md5,
+ mx_wifi_fota_status_cb_t fota_status_callback, uint32_t user_args)
+{
+ int32_t ret = MX_WIFI_STATUS_ERROR;
+
+#if 0
+ int32_t ret_flag = MIPC_RET_FLAG_CLR;
+ int32_t addr_ret_val;
+ int32_t addr_ret_flag;
+ int32_t *p_addr_ret_val;
+ int32_t *p_addr_ret_flag;
+
+ if ((NULL == Obj) || (NULL == url) || (NULL == md5))
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ if (NULL != fota_status_callback)
+ {
+ Obj->Runtime.fota_status_cb = fota_status_callback;
+ Obj->Runtime.fota_user_args = user_args;
+ }
+ else
+ {
+ Obj->Runtime.fota_status_cb = NULL;
+ Obj->Runtime.fota_user_args = 0;
+ }
+
+ p_addr_ret_val = &ret;
+ p_addr_ret_flag = &ret_flag;
+ (void)memcpy(&addr_ret_val, &p_addr_ret_val, sizeof(addr_ret_val));
+ (void)memcpy(&addr_ret_flag, &p_addr_ret_flag, sizeof(addr_ret_flag));
+ if (MIPC_CODE_SUCCESS == fota_start_cmd(url, (int32_t)strlen(url), md5, (int32_t)strlen(md5),
+ addr_ret_val, addr_ret_flag))
+ {
+ if (MIPC_CODE_SUCCESS == mipc_poll(&ret_flag, &ret, Obj->Runtime.Timeout))
+ {
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+ }
+#endif /* 0 */
+
+ return ret;
+}
+
+#else /* MX_WIFI_NETWORK_BYPASS_MODE */
+
+/**
+ * @brief Set network bypass mode
+ * @param Obj: pointer to module handle
+ * @param enable: 0=disable, 1=enable
+ * @param netlink_input_callbck: input data callback function
+ * @param user_args: user arguments for callback function
+ * @retval Operation Status.
+ */
+MX_WIFI_STATUS_T MX_WIFI_Network_bypass_mode_set(MX_WIFIObject_t *Obj, int32_t enable,
+ mx_wifi_netlink_input_cb_t netlink_input_callbck,
+ void *user_args)
+{
+ int32_t ret = MX_WIFI_STATUS_ERROR;
+ wifi_bypass_set_cparams_t cparams;
+ int32_t status = MIPC_CODE_ERROR;
+ uint16_t out_size = sizeof(status);
+
+ if (NULL == Obj)
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ if ((NULL != netlink_input_callbck) && (1 == enable))
+ {
+ Obj->Runtime.netlink_input_cb = netlink_input_callbck;
+ Obj->Runtime.netlink_user_args = user_args;
+ }
+ else
+ {
+ Obj->Runtime.netlink_input_cb = NULL;
+ Obj->Runtime.netlink_user_args = NULL;
+ }
+
+ cparams.mode = enable;
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_WIFI_BYPASS_SET_CMD,
+ (uint8_t *)&cparams, sizeof(cparams),
+ (uint8_t *)&status, &out_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ if (MIPC_CODE_SUCCESS == status)
+ {
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+ }
+ return ret;
+}
+
+/**
+ * @brief Network bypass mode data output
+ * @param Obj: pointer to module handle
+ * @param pbuf: pbuf data to send
+ * @param size: pbuf size
+ * @param data: pbuf payload
+ * @param len: payload len
+ * @param interface: STATION_IDX, SOFTAP_IDX(not supported now)
+ * @retval Operation Status.
+ */
+MX_WIFI_STATUS_T MX_WIFI_Network_bypass_netlink_output(MX_WIFIObject_t *Obj, void *data,
+ int32_t len,
+ int32_t interface)
+{
+ int32_t ret = MX_WIFI_STATUS_ERROR;
+ wifi_bypass_out_cparams_t *cparams;
+ uint16_t cparams_size;
+ int32_t status = MIPC_CODE_ERROR;
+ uint16_t rparams_size = sizeof(status);
+
+ if ((NULL == Obj) || (len <= 0) || \
+ (((int32_t)STATION_IDX != interface) && ((int32_t)SOFTAP_IDX != interface)))
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ cparams_size = sizeof(wifi_bypass_out_cparams_t) + len;
+ if (cparams_size > MX_WIFI_IPC_PAYLOAD_SIZE)
+ {
+ len = MX_WIFI_IPC_PAYLOAD_SIZE - sizeof(wifi_bypass_out_cparams_t);
+ }
+#if MX_WIFI_TX_BUFFER_NO_COPY
+ /* structure of data buffer must support head room provision to add information in from of data payload */
+ cparams = (wifi_bypass_out_cparams_t *)((uint8_t *)data - sizeof(wifi_bypass_out_cparams_t));
+#else
+ cparams = (wifi_bypass_out_cparams_t *)MX_WIFI_MALLOC(len + sizeof(wifi_bypass_out_cparams_t));
+#endif /* MX_WIFI_TX_BUFFER_NO_COPY */
+
+ if (NULL != cparams)
+ {
+ cparams->idx = interface;
+ cparams->data_len = len;
+
+#if MX_WIFI_TX_BUFFER_NO_COPY == 0
+ /* copy the whole payload */
+ uint8_t *dst;
+ dst = (uint8_t *)cparams + sizeof(wifi_bypass_out_cparams_t);
+ memcpy(dst, data, len);
+#endif /* MX_WIFI_TX_BUFFER_NO_COPY */
+
+ if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_WIFI_BYPASS_OUT_CMD,
+ (uint8_t *)cparams, cparams_size,
+ (uint8_t *)&status, &rparams_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ if (MIPC_CODE_SUCCESS == status)
+ {
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+#if MX_WIFI_TX_BUFFER_NO_COPY == 0
+ MX_WIFI_FREE(cparams);
+#endif /* MX_WIFI_TX_BUFFER_NO_COPY */
+ }
+ else
+ {
+ /* no memory */
+ DEBUG_LOG("No memory!!!\n");
+ }
+ }
+
+ return ret;
+}
+#endif /* MX_WIFI_NETWORK_BYPASS_MODE */
+
+/**
+ * @brief set powersave onoff for wifi station mode.
+ * @param Obj: pointer to module handle
+ * @param ps_onoff: 0 -- powersave off, 1 -- powersave on
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_station_powersave(MX_WIFIObject_t *Obj, int32_t ps_onoff)
+{
+ int32_t ret = MX_WIFI_STATUS_ERROR;
+ uint16_t mipc_ps_cmd;
+ int32_t status = MIPC_CODE_ERROR;
+ uint16_t out_size = sizeof(status);
+
+ if (NULL == Obj)
+ {
+ ret = MX_WIFI_STATUS_PARAM_ERROR;
+ }
+ else
+ {
+ if (ps_onoff)
+ {
+ mipc_ps_cmd = MIPC_API_WIFI_PS_ON_CMD;
+ }
+ else
+ {
+ mipc_ps_cmd = MIPC_API_WIFI_PS_OFF_CMD;
+ }
+ if (MIPC_CODE_SUCCESS == mipc_request(mipc_ps_cmd, NULL, 0,
+ (uint8_t *)&status, &out_size,
+ MX_WIFI_CMD_TIMEOUT))
+ {
+ if (MIPC_CODE_SUCCESS == status)
+ {
+ ret = MX_WIFI_STATUS_OK;
+ }
+ }
+ }
+ return ret;
+}
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/mx_wifi/mx_wifi.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/mx_wifi/mx_wifi.h
new file mode 100644
index 00000000..e7aba01f
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/mx_wifi/mx_wifi.h
@@ -0,0 +1,1510 @@
+/**
+ ******************************************************************************
+ * @file mx_wifi.h
+ * @author MCD Application Team
+ * @brief Header for mx_wifi.c module
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef MX_WIFI_H
+#define MX_WIFI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "mx_wifi_conf.h"
+
+
+/**
+ * @defgroup MX_WIFI Wi-Fi_API
+ * @brief Driver API on STM32 for MXCHIP Wi-Fi module, see mx_wifi.h
+ * @{ **
+ */
+
+/* API version V2.1.8 */
+#define MX_WIFI_API_VERSION_MAJ (2)
+#define MX_WIFI_API_VERSION_SUB (1)
+#define MX_WIFI_API_VERSION_REV (10)
+
+/*******************************************************************************
+ * MXCHIP Wi-Fi Module Defines
+ ******************************************************************************/
+/* common defines */
+#define MX_MAX_IP_LEN (16)
+#define MX_MAX_SSID_LEN (32)
+#define MX_MAX_KEY_LEN (64)
+#define MX_MAX_BSSID_LEN (6)
+#define MX_MAX_DNSNAME_LEN (253)
+#define MX_MAX_IDENTITY_LEN (32)
+#define MX_TLS_SNI_SERVERNAME_SIZE (128)
+#define MX_SERVICE_NAME_SIZE (255)
+#define MC_WIFI_INTERFACE_NUM (2)
+#define MX_WIFI_PING_MAX (10)
+
+#define MX_WIFI_SCAN_TIMEOUT (5000)
+
+/**
+ * @brief Wi-Fi mode
+ */
+enum
+{
+ MC_SOFTAP, /**< wifi softap mode. */
+ MC_STATION /**< wifi station mode. */
+};
+
+typedef uint8_t mwifi_if_t; /**< wifi mode. */
+
+/**
+ * @brief Wi-Fi scan mode
+ */
+enum
+{
+ MC_SCAN_PASSIVE = 0, /**< wifi passive scan mode. */
+ MC_SCAN_ACTIVE = 1 /**< wifi active scan mode. */
+};
+
+typedef uint8_t mc_wifi_scan_mode_t; /**< wifi scan mode. */
+
+/**
+ * @brief Wi-Fi ip address info
+ */
+typedef struct
+{
+ char localip[MX_MAX_IP_LEN]; /**< lcoal ip address */
+ char netmask[MX_MAX_IP_LEN]; /**< netmask */
+ char gateway[MX_MAX_IP_LEN]; /**< gateway ip address */
+ char dnserver[MX_MAX_IP_LEN]; /**< dns server ip address */
+} mwifi_ip_attr_t; /**< wifi ip address info. */
+
+/**
+ * @brief Wi-Fi EAP type
+ */
+typedef enum
+{
+ EAP_TYPE_TLS = 13, /* RFC 2716 */
+ EAP_TYPE_TTLS = 21, /* RFC 5281 */
+ EAP_TYPE_PEAP = 25 /* draft-josefsson-pppext-eap-tls-eap-06.txt */
+} EapType;
+
+/**
+ * @brief Wi-Fi EAP info
+ */
+typedef struct
+{
+ uint8_t eap_type; /* support: EAP_TYPE_PEAP, EAP_TYPE_TTLS, EAP_TYPE_TLS */
+ const char *rootca; /* the EAP server rootca. NULL for don't check the server's certificate */
+ const char *client_cert; /* client cert, only need this if the server need check the client's certificate,
+ such as EAP_TYPE_TLS mode. */
+ const char *client_key; /* client private key. DONOT support encrypted key. */
+} mwifi_eap_attr_t;
+
+/*******************************************************************************
+ * STM32Cube Driver API Defines
+ ******************************************************************************/
+/* status code */
+#define MX_WIFI_STATUS_OK (0) /**< status code success. */
+#define MX_WIFI_STATUS_ERROR (-1) /**< status code common error. */
+#define MX_WIFI_STATUS_TIMEOUT (-2) /**< status code timeout. */
+#define MX_WIFI_STATUS_IO_ERROR (-3) /**< status code I/O error. */
+#define MX_WIFI_STATUS_PARAM_ERROR (-4) /**< status code bad argument error. */
+#define MX_WIFI_STATUS_T int32_t /**< status code. */
+
+/* macro */
+#define MX_WIFI_MAC_SIZE (6) /**< max length of MAC address. */
+#define MX_WIFI_SCAN_BUF_SIZE (2000) /**< max size of scan buffer. */
+
+#define MIN(a, b) ( ((a) < (b)) ? (a) : (b)) /**< helper function: get minimum. */
+
+#if 0
+/* IPv6 address states. */
+#define IP6_ADDR_INVALID 0x00
+#define IP6_ADDR_TENTATIVE 0x08
+#define IP6_ADDR_TENTATIVE_1 0x09 /* 1 probe sent */
+#define IP6_ADDR_TENTATIVE_2 0x0a /* 2 probes sent */
+#define IP6_ADDR_TENTATIVE_3 0x0b /* 3 probes sent */
+#define IP6_ADDR_TENTATIVE_4 0x0c /* 4 probes sent */
+#define IP6_ADDR_TENTATIVE_5 0x0d /* 5 probes sent */
+#define IP6_ADDR_TENTATIVE_6 0x0e /* 6 probes sent */
+#define IP6_ADDR_TENTATIVE_7 0x0f /* 7 probes sent */
+#define IP6_ADDR_VALID 0x10
+#define IP6_ADDR_PREFERRED 0x30
+#define IP6_ADDR_DEPRECATED 0x50
+#endif /* 0 */
+
+/*
+#define ip6_addr_isinvalid(addr_state) (addr_state == IP6_ADDR_INVALID)
+#define ip6_addr_istentative(addr_state) (addr_state & IP6_ADDR_TENTATIVE)
+#define ip6_addr_isvalid(addr_state) (addr_state & IP6_ADDR_VALID)
+#define ip6_addr_ispreferred(addr_state) (addr_state == IP6_ADDR_PREFERRED)
+#define ip6_addr_isdeprecated(addr_state) (addr_state == IP6_ADDR_DEPRECATED)
+ */
+
+/**
+ * @brief Security settings for wifi network
+ */
+typedef enum
+{
+ MX_WIFI_SEC_NONE, /**< Open system. */
+ MX_WIFI_SEC_WEP, /**< Wired Equivalent Privacy. WEP security. */
+ MX_WIFI_SEC_WPA_TKIP, /**< WPA /w TKIP */
+ MX_WIFI_SEC_WPA_AES, /**< WPA /w AES */
+ MX_WIFI_SEC_WPA2_TKIP, /**< WPA2 /w TKIP */
+ MX_WIFI_SEC_WPA2_AES, /**< WPA2 /w AES */
+ MX_WIFI_SEC_WPA2_MIXED, /**< WPA2 /w AES or TKIP */
+ MX_WIFI_SEC_AUTO /**< It is used when calling @ref mwifi_connect,
+ MXOS read security type from scan result. */
+} MX_WIFI_SecurityType_t;
+
+typedef int8_t (*IO_Init_Func)(uint16_t mode); /**< I/O interface init function. */
+typedef int8_t (*IO_DeInit_Func)(void); /**< I/O interface deinit function. */
+typedef void (*IO_Delay_Func)(uint32_t ms); /**< I/O interface delay function. */
+typedef uint16_t (*IO_Send_Func)(uint8_t *data, uint16_t len); /**< I/O interface send function. */
+typedef uint16_t (*IO_Receive_Func)(uint8_t *buffer, uint16_t buff_size); /**< I/O interface receive function. */
+
+/**
+ * @brief Wi-Fi low level I/O interface operation handles
+ */
+typedef struct
+{
+ IO_Init_Func IO_Init; /**< I/O interface init function. */
+ IO_DeInit_Func IO_DeInit; /**< I/O interface deinit function. */
+ IO_Delay_Func IO_Delay; /**< I/O interface delay function. */
+ IO_Send_Func IO_Send; /**< I/O interface send function. */
+ IO_Receive_Func IO_Receive; /**< I/O interface receive function. */
+} MX_WIFI_IO_t;
+
+/**
+ * @brief Wi-Fi system info
+ */
+typedef struct
+{
+ /* FW info */
+ uint8_t Product_Name[MX_WIFI_PRODUCT_NAME_SIZE];/**< product name. */
+ uint8_t Product_ID[MX_WIFI_PRODUCT_ID_SIZE]; /**< product ID. */
+ uint8_t FW_Rev[MX_WIFI_FW_REV_SIZE]; /**< firmware version. */
+ uint8_t MAC[MX_WIFI_MAC_SIZE]; /**< Wi-Fi MAC address. */
+} MX_WIFI_SystemInfo_t;
+
+/**
+ * @brief Wi-Fi station info
+ */
+typedef struct
+{
+ /* wifi station setting */
+ uint8_t SSID[MX_WIFI_MAX_SSID_NAME_SIZE + 1]; /**< Wi-Fi station SSID. */
+ uint8_t pswd[MX_WIFI_MAX_PSWD_NAME_SIZE + 1]; /**< Wi-Fi station passwd. */
+ MX_WIFI_SecurityType_t Security; /**< Wi-Fi station security. */
+ uint8_t DHCP_IsEnabled; /**< Wi-Fi station DHCP. */
+ /* status */
+ int8_t IsConnected; /**< Wi-Fi station connection status. */
+ /*ipv4 */
+ uint8_t IP_Addr[4]; /**< Wi-Fi station IP address. */
+ uint8_t IP_Mask[4]; /**< Wi-Fi station IP mask. */
+ uint8_t Gateway_Addr[4]; /**< Wi-Fi station gateway. */
+ uint8_t DNS1[4]; /**< Wi-Fi station DNS server. */
+ /* ipv6 */
+ int32_t IP6_state[3]; /**< Wi-Fi station IPv6 address state. */
+ uint8_t IP6_Addr[3][16]; /**< Wi-Fi station IPv6 address. */
+ uint8_t IP6_Mask[16]; /**< Wi-Fi station IPv6 mask. */
+ uint8_t Gateway6_Addr[16]; /**< Wi-Fi station IPv6 gateway. */
+ uint8_t IP6_DNS1[16]; /**< Wi-Fi station IPv6 DNS server. */
+} MX_WIFI_Network_t;
+
+/**
+ * @brief Wi-Fi softAP info
+ */
+typedef struct
+{
+ char SSID[MX_WIFI_MAX_SSID_NAME_SIZE + 1]; /**< Wi-Fi softAP SSID. */
+ char pswd[MX_WIFI_MAX_PSWD_NAME_SIZE + 1]; /**< Wi-Fi softAP password. */
+ /* MX_WIFI_SecurityType_t Security; OPEN: no passwd, WPA2: has passwd, NOT SUPPORTED NOW */
+ uint8_t channel; /**< Wi-Fi softAP Channel. */
+ mwifi_ip_attr_t ip; /**< Wi-Fi softAP IP settings. */
+} MX_WIFI_APSettings_t;
+
+/** Prototype of Wi-Fi status changed callback function. */
+/**
+ * @param cate wifi status: MC_STATION, MC_SOFTAP
+ * @param event wifi events: MWIFI_EVENT_STA_DOWN,
+ * MWIFI_EVENT_STA_UP,
+ * WIFI_EVENT_STA_GOT_IP,
+ * MWIFI_EVENT_AP_UP,
+ * MWIFI_EVENT_AP_DOWN
+ * @param arg user argument passed by @MX_WIFI_RegisterStatusCallback
+ */
+typedef void (*mx_wifi_status_callback_t)(uint8_t cate, uint8_t event, void *arg);
+
+/**
+ * @brief FOTA status
+ */
+typedef enum
+{
+ MX_WIFI_FOTA_SUCCESS,
+ MX_WIFI_FOTA_FAILED
+} mx_wifi_fota_status_e;
+
+/**
+ * @brief Prototype of FOTA status callback function
+ */
+typedef void (*mx_wifi_fota_status_cb_t)(mx_wifi_fota_status_e status, uint32_t user_args);
+
+/**
+ * @brief Prototype of netlink input callback function for network bypass mode
+ */
+typedef void (*mx_wifi_netlink_input_cb_t)(mx_buf_t *pbuf, void *user_args);
+
+/**
+ * @brief Wi-Fi runtime info
+ */
+typedef struct
+{
+ uint32_t Timeout; /**< Wi-Fi cmd timeout in ms. */
+
+ mx_wifi_status_callback_t status_cb[MC_WIFI_INTERFACE_NUM]; /**< Wi-Fi status callback. */
+ void *callback_arg[MC_WIFI_INTERFACE_NUM]; /**< Wi-Fi status callback argument. */
+
+ mx_wifi_fota_status_cb_t fota_status_cb; /**< FOTA status callback. */
+ uint32_t fota_user_args; /**< FOTA status callback argument. */
+
+ mx_wifi_netlink_input_cb_t netlink_input_cb; /**< netlink input callback. */
+ void *netlink_user_args; /**< netlink input callback argument. */
+
+ uint8_t scan_result[MX_WIFI_SCAN_BUF_SIZE]; /**< Wi-Fi scan result buffer. */
+ uint8_t scan_number; /**< Num of Wi-Fi scan result to get. */
+
+ uint8_t interfaces; /**< Num of Wi-Fi interfaces inited, 2 if STA+AP inited. */
+} MX_WIFI_Runtime_t;
+
+/**
+ * @brief Wi-Fi Wi-Fi object handle
+ */
+typedef struct
+{
+ /* HW IO */
+ MX_WIFI_IO_t fops; /**< Wi-Fi low level I/O operation handles. */
+
+ /* system info */
+ MX_WIFI_SystemInfo_t SysInfo; /**< Wi-Fi system info. */
+
+ /* network info */
+ MX_WIFI_Network_t NetSettings; /**< Wi-Fi station info. */
+ MX_WIFI_APSettings_t APSettings; /**< Wi-Fi softAP info. */
+
+ /* run time data */
+ MX_WIFI_Runtime_t Runtime; /**< Wi-Fi runtime info. */
+
+ /* wifi obj lock */
+ LOCK_DECLARE(lockcmd);
+} MX_WIFIObject_t;
+
+
+/* Exported functions --------------------------------------------------------*/
+
+/**
+ * @defgroup MX_WIFI_IO Driver_I/O
+ * @brief Driver I/O interface setting API
+ * @{ **
+ */
+
+
+/**
+ * @brief Register low level IO interface.
+ * @param Obj wifi object handle.
+ * @param IO_Init IO init function
+ * @param IO_DeInit IO de-init function
+ * @param IO_Delay IO delay function in ms
+ * @param IO_Send IO send data function
+ * @param IO_Receive IO receive data function
+ *
+ * @return result
+ * @retval MX_WIFI_STATUS_OK success
+ * @retval others failure
+ */
+MX_WIFI_STATUS_T MX_WIFI_RegisterBusIO(MX_WIFIObject_t *Obj,
+ IO_Init_Func IO_Init, IO_DeInit_Func IO_DeInit, IO_Delay_Func IO_Delay,
+ IO_Send_Func IO_Send, IO_Receive_Func IO_Receive);
+/**
+ * @brief Reset wifi module by hardware IO.
+ * @param Obj wifi object handle.
+ *
+ * @return result
+ * @retval MX_WIFI_STATUS_OK success
+ * @retval others failure
+ */
+MX_WIFI_STATUS_T MX_WIFI_HardResetModule(MX_WIFIObject_t *Obj);
+
+/**
+ * @} **
+ */
+
+/**
+ * @defgroup MX_WIFI_INIT Driver_init
+ * @brief Driver init API
+ * @{ **
+ */
+
+/**
+ * @brief Wi-Fi module init type
+ */
+typedef enum
+{
+ MX_WIFI_INIT = 0, /**< Wi-Fi module init(not reboot). */
+ MX_WIFI_RESET = 1 /**< Wi-Fi module reset(reboot). */
+} MX_WIFI_InitMode_t;
+
+/**
+ * @brief Initialize WIFI module and get module fw & mac info.
+ * @param Obj: pointer to module handle
+ * @retval Operation Status.
+ */
+MX_WIFI_STATUS_T MX_WIFI_Init(MX_WIFIObject_t *Obj);
+
+/**
+ * @brief DeInitialize WIFI module.
+ * @param Obj: pointer to module handle
+ * @retval Operation Status.
+ */
+MX_WIFI_STATUS_T MX_WIFI_DeInit(MX_WIFIObject_t *Obj);
+
+/**
+ * @brief Change default Timeout for wifi cmd.
+ * @param Obj: pointer to module handle
+ * @param Timeout: Timeout in mS
+ * @retval Operation Status.
+ */
+MX_WIFI_STATUS_T MX_WIFI_SetTimeout(MX_WIFIObject_t *Obj, uint32_t Timeout);
+
+/**
+ * @brief Yield data from Wi-Fi module.
+ * @param Obj: pointer to module handle
+ * @param timeout: yield timeout in ms
+ * @retval Operation Status.
+ * @note This will be called periodically
+ */
+MX_WIFI_STATUS_T MX_WIFI_IO_YIELD(MX_WIFIObject_t *Obj, uint32_t timeout);
+
+/**
+ * @} **
+ */
+
+/**
+ * @defgroup MX_WIFI_NETWORK_BYPASS_MODE Network bypass mode
+ * @brief Network bypass mode API
+ * @{ **
+ */
+
+/**
+ * @brief Network bypass interface index
+ */
+enum
+{
+ STATION_IDX = 0,
+ SOFTAP_IDX = 1 /* NOT SUPPORTED NOW */
+};
+
+
+MX_WIFIObject_t *wifi_obj_get(void);
+
+
+
+#if (MX_WIFI_NETWORK_BYPASS_MODE == 1)
+/**
+ * @brief Set network bypass mode
+ * @param Obj: pointer to module handle
+ * @param enable: 0=disable, 1=enable
+ * @param netlink_input_callbck: input data callback function
+ * @param user_args: user arguments for callback function
+ * @retval Operation Status.
+ */
+MX_WIFI_STATUS_T MX_WIFI_Network_bypass_mode_set(MX_WIFIObject_t *Obj, int32_t enable,
+ mx_wifi_netlink_input_cb_t netlink_input_callbck, void *user_args);
+
+/**
+ * @brief Network bypass mode data output
+ * @param Obj: pointer to module handle
+ * @param pbuf: pbuf data to send
+ * @param size: pbuf size
+ * @param data: pbuf payload
+ * @param len: payload len
+ * @param interface: STATION_IDX, SOFTAP_IDX(not supported now)
+ * @retval Operation Status.
+ */
+MX_WIFI_STATUS_T MX_WIFI_Network_bypass_netlink_output(MX_WIFIObject_t *Obj, void *data,
+ int32_t len,
+ int32_t interface);
+#endif /* MX_WIFI_NETWORK_BYPASS_MODE */
+
+
+/**
+ * @brief set powersave onoff for wifi station mode.
+ * @param Obj: pointer to module handle
+ * @param ps_onoff: 0 -- powersave off, 1 -- powersave on
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_station_powersave(MX_WIFIObject_t *Obj, int32_t ps_onoff);
+
+
+/**
+ * @} **
+ */
+
+enum
+{
+ MWIFI_EVENT_NONE = 0x00, /* invalid event */
+ MWIFI_EVENT_STA_DOWN = 0x01, /**< Wi-Fi station down event. */
+ MWIFI_EVENT_STA_UP = 0x02, /**< Wi-Fi station up event. */
+ MWIFI_EVENT_STA_GOT_IP = 0X03, /**< Wi-Fi station got ip event. */
+ MWIFI_EVENT_AP_DOWN = 0x04, /**< Wi-Fi softap down event. */
+ MWIFI_EVENT_AP_UP = 0x05, /**< Wi-Fi softap up event. */
+};
+typedef uint8_t mwifi_status_t;
+
+/**
+ * @defgroup MX_WIFI_BASIC Station
+ * @brief station mode API
+ * @{ **
+ */
+
+/**
+ * @brief Wi-Fi station link info
+ */
+#pragma pack(1)
+typedef struct
+{
+ uint8_t is_connected; /**< Wi-Fi station connection status. */
+ char ssid[MX_MAX_SSID_LEN]; /**< Wi-Fi connection AP ssid to connect. */
+ uint8_t bssid[MX_MAX_BSSID_LEN]; /**< Wi-Fi connection AP bssid. */
+ uint8_t security; /**< Wi-Fi connection security type. */
+ uint8_t channel; /**< Wi-Fi connection channel. */
+ int32_t rssi; /**< Wi-Fi connection rssi. */
+} mc_wifi_link_info_t;
+#pragma pack()
+
+/**
+ * @brief Reset the module by Software.
+ * @param Obj: pointer to module handle
+ * @retval Operation Status.
+ */
+MX_WIFI_STATUS_T MX_WIFI_ResetModule(MX_WIFIObject_t *Obj);
+
+/**
+ * @brief Reset To factory defaults.
+ * @param Obj: pointer to module handle
+ * @note NOT USED NOW
+ * @retval Operation Status.
+ */
+MX_WIFI_STATUS_T MX_WIFI_ResetToFactoryDefault(MX_WIFIObject_t *Obj);
+
+/**
+ * @brief Get the firmware version string of the wifi module.
+ * @param Obj: pointer to module handle
+ * @param version: buffer pointer to receive the version string.
+ * @param size: length of the buffer, max size 24Bytes.
+ * @retval Operation Status.
+ */
+MX_WIFI_STATUS_T MX_WIFI_GetVersion(MX_WIFIObject_t *Obj, uint8_t *version, uint32_t size);
+
+/**
+ * @brief Get the MAC address of the wifi module.
+ * @param Obj: pointer to module handle
+ * @param mac: pointer to the MAC address array, size 6Bytes.
+ * @retval Operation Status.
+ */
+MX_WIFI_STATUS_T MX_WIFI_GetMACAddress(MX_WIFIObject_t *Obj, uint8_t *mac);
+
+/**
+ * @brief wifi block scan
+ * @param Obj: pointer to module handle
+ * @param scan_mode: scan mode
+ * @param ssid: ssid for active scan(scan specified AP), not used(set NULL) if do passive scan(scan all APs)
+ * @param len: ssid len of the AP to scan, not used(set 0) if do passive scan
+ * @note This API just start scan, use @MX_WIFI_Get_scan_result to get the scan result.
+ * @code Example:
+ * Active scan:
+ * MX_WIFI_Scan(pWifiObj, MC_SCAN_ACTIVE, "ssid_ap", 7);
+ * Passive scan:
+ * MX_WIFI_Scan(pWifiObj, MC_SCAN_PASSIVE, NULL, 0);
+ *
+ * Get scan result:
+ * mwifi_ap_info_t mx_aps[MX_WIFI_MAX_DETECTED_AP]; ( array to store scan AP info )
+ * int32_t ap_num;
+ * ap_num = MX_WIFI_Get_scan_result(pWifiObj, (uint8_t*)&(mx_aps[0]), MX_WIFI_MAX_DETECTED_AP);
+ * if(ap_num > 0)
+ * {
+ * for(int32_t i = 0; i < ap_num; i++)
+ * {
+ * ( mx_aps[i].ssid )
+ * ( mx_aps[i].rssi )
+ * }
+ * }
+ * @endcode
+ * @retval Operation Status.
+ */
+MX_WIFI_STATUS_T MX_WIFI_Scan(MX_WIFIObject_t *Obj, mc_wifi_scan_mode_t scan_mode, char *ssid, int32_t len);
+
+/**
+ * @brief wifi get scan result
+ * @param Obj: pointer to module handle
+ * @param results: scan result buffer, contains mwifi_ap_info_t * number
+ * @param number: max ap number to get, max 10
+ * @retval return the real ap number got.
+ * @note must be called after @MX_WIFI_Scan
+ */
+int8_t MX_WIFI_Get_scan_result(MX_WIFIObject_t *Obj, uint8_t *results, uint8_t number);
+
+/**
+ * @brief Register wifi status changed callback
+ * @param Obj: pointer to module handle
+ * @param cb: wifi status callback function
+ * @param arg: argument pass to callback
+ * @retval Operation Status.
+ */
+MX_WIFI_STATUS_T MX_WIFI_RegisterStatusCallback(MX_WIFIObject_t *Obj,
+ mx_wifi_status_callback_t cb, void *arg);
+MX_WIFI_STATUS_T MX_WIFI_RegisterStatusCallback_if(MX_WIFIObject_t *Obj,
+ mx_wifi_status_callback_t cb,
+ void *arg,
+ mwifi_if_t interface);
+
+/**
+ * @brief UnRegister wifi status changed callback
+ * @param Obj: pointer to module handle
+ * @retval Operation Status.
+ */
+MX_WIFI_STATUS_T MX_WIFI_UnRegisterStatusCallback(MX_WIFIObject_t *Obj);
+MX_WIFI_STATUS_T MX_WIFI_UnRegisterStatusCallback_if(MX_WIFIObject_t *Obj, mwifi_if_t interface);
+
+/**
+ * @brief Join an Access point.
+ * @param Obj: pointer to module handle
+ * @param Ssid: the access point id.
+ * @param Password: the Access point password.
+ * @param SecType: Security type.
+ * @retval Operation Status.
+ */
+MX_WIFI_STATUS_T MX_WIFI_Connect(MX_WIFIObject_t *Obj, const char *SSID,
+ const char *Password, MX_WIFI_SecurityType_t SecType);
+
+/**
+ * @brief Join an Access point with WPA-E.
+ * @param Obj: pointer to module handle
+ * @param Ssid: the access point ID.
+ * @param Identity: client identity.
+ * @param Password: client password.
+ * @param attr: extral attributes of EAP method. NULL for default mode EAP-PEAP.
+ * @param ip: Station IP settings, NULL for DHCP mode.
+ * @retval Operation Status.
+ */
+MX_WIFI_STATUS_T MX_WIFI_EAP_Connect(MX_WIFIObject_t *Obj, const char *SSID,
+ const char *Identity, const char *Password,
+ mwifi_eap_attr_t *attr, mwifi_ip_attr_t *ip);
+
+/**
+ * @brief Disconnect from a network.
+ * @param Obj: pointer to module handle
+ * @retval Operation Status.
+ */
+MX_WIFI_STATUS_T MX_WIFI_Disconnect(MX_WIFIObject_t *Obj);
+
+/**
+ * @brief Join an Access point with WPS (PUSH-BUTTON) mode.
+ * @retval Operation Status.
+ */
+MX_WIFI_STATUS_T MX_WIFI_WPS_Connect(MX_WIFIObject_t *Obj);
+
+/**
+ * @brief Stop WPS connect.
+ * @param Obj: pointer to module handle
+ * @retval Operation Status.
+ */
+MX_WIFI_STATUS_T MX_WIFI_WPS_Stop(MX_WIFIObject_t *Obj);
+
+/**
+ * @brief Check whether the module is connected to an access point.
+ * @retval link status 1: connected, otherwise not connect.
+ */
+int8_t MX_WIFI_IsConnected(MX_WIFIObject_t *Obj);
+
+/**
+ * @brief Get the local IPv4 address of the wifi module.
+ * @param Obj: pointer to module handle
+ * @param ipaddr: pointer to the IP address array(4 bytes).
+ * @param wifi_if: wifi mode(station or softap).
+ * @retval Operation Status.
+ */
+MX_WIFI_STATUS_T MX_WIFI_GetIPAddress(MX_WIFIObject_t *Obj, uint8_t *ipaddr, mwifi_if_t wifi_if);
+
+/**
+ * @brief Get the local IPv6 address of the wifi module.
+ * @param Obj: pointer to module handle
+ * @param ipaddr6: buf to the IPv6 address array(16 bytes).
+ * @param addr_num: index of the IPv6 address (index: 0/1/2).
+ * @param wifi_if: wifi mode(station or softap).
+ * @retval Operation Status.
+ */
+MX_WIFI_STATUS_T MX_WIFI_GetIP6Address(MX_WIFIObject_t *Obj, uint8_t *ipaddr6, int32_t addr_num, mwifi_if_t wifi_if);
+
+/**
+ * @brief Get the local IPv6 address state of the wifi module.
+ * @param Obj: pointer to module handle
+ * @param addr_num: index of the IPv6 address (index: 0/1/2).
+ * @param wifi_if: wifi mode(station or softap).
+ * @retval IPV6 address State, error if < 0
+ */
+int32_t MX_WIFI_GetIP6AddressState(MX_WIFIObject_t *Obj, int32_t addr_num, mwifi_if_t wifi_if);
+
+
+/**
+ * @} **
+ */
+
+/**
+ * @defgroup MX_WIFI_SOFTAP SoftAP
+ * @brief softAP mode API
+ * @{ **
+ */
+
+/**
+ * @brief Wi-Fi softAP info
+ */
+typedef uint8_t mwifi_security_t;
+#pragma pack(1)
+typedef struct
+{
+ int32_t rssi; /**< Signal strength of the AP */
+ char ssid[33]; /**< SSID of the AP */
+ uint8_t bssid[6]; /**< BSSID of the AP */
+ int32_t channel; /**< Channel of the AP */
+ mwifi_security_t security; /**< security of the AP */
+} mwifi_ap_info_t;
+#pragma pack()
+
+/**
+ * @brief Start softAP(miniAP) mode
+ * @param Obj: pointer to module handle
+ * @param ap_settings: softAP settings.
+ * @retval Operation Status.
+ */
+MX_WIFI_STATUS_T MX_WIFI_StartAP(MX_WIFIObject_t *Obj, MX_WIFI_APSettings_t *ap_settings);
+
+/**
+ * @brief Stop softAP(miniAP) mode
+ * @param Obj: pointer to module handle
+ * @retval Operation Status.
+ */
+MX_WIFI_STATUS_T MX_WIFI_StopAP(MX_WIFIObject_t *Obj);
+
+/**
+ * @} **
+ */
+
+#if MX_WIFI_NETWORK_BYPASS_MODE == 0
+
+/**
+ * @defgroup WIFI_SOCKET Socket
+ * @brief socket related API
+ * @{ **
+ */
+
+#ifndef socklen_t
+#define socklen_t uint32_t
+#endif /* socklen_t */
+
+/**
+ * @brief socket address struct
+ */
+
+struct sockaddr
+{
+ uint8_t sa_len;
+ uint8_t sa_family;
+ uint8_t sa_data[14];
+};
+
+/**
+ * @brief socket address(net format)
+ */
+struct in_addr
+{
+ uint32_t s_addr;
+};
+
+/**
+ * @brief socket address_in struct
+ */
+struct sockaddr_in
+{
+ uint8_t sin_len;
+ uint8_t sin_family;
+ uint16_t sin_port;
+ struct in_addr sin_addr;
+ char sin_zero[8];
+};
+
+/**
+ * @brief socket address(IPV6 net format)
+ */
+struct in6_addr
+{
+ union
+ {
+ uint32_t u32_addr[4];
+ uint8_t u8_addr[16];
+ } un;
+ /* #define s6_addr un.u8_addr */
+};
+
+/**
+ * @brief socket address_in6 struct
+ */
+struct sockaddr_in6
+{
+ uint8_t sin6_len; /* length of this structure */
+ uint8_t sin6_family; /* AF_INET6 */
+ uint16_t sin6_port; /* Transport layer port # */
+ uint32_t sin6_flowinfo; /* IPv6 flow information */
+ struct in6_addr sin6_addr; /* IPv6 address */
+ uint32_t sin6_scope_id; /* Set of interfaces for scope */
+};
+
+struct sockaddr_storage
+{
+ uint8_t s2_len;
+ uint8_t ss_family;
+ char s2_data1[2];
+ uint32_t s2_data2[3];
+ uint32_t s2_data3[3];
+};
+
+/**
+ * @brief socket address_in6 info
+ */
+struct addrinfo
+{
+ int32_t ai_flags; /* Input flags. */
+ int32_t ai_family; /* Address family of socket. */
+ int32_t ai_socktype; /* Socket type. */
+ int32_t ai_protocol; /* Protocol of socket. */
+ uint32_t ai_addrlen; /* Length of socket address. */
+ struct sockaddr *ai_addr; /* Socket address of socket. */
+ char *ai_canonname; /* Canonical name of service location. */
+ struct addrinfo *ai_next; /* Pointer to next in list. */
+};
+
+/* Socket protocol types (TCP/UDP/RAW) */
+#define SOCK_STREAM 1
+#define SOCK_DGRAM 2
+#define SOCK_RAW 3
+
+#define SOL_SOCKET 0xfff /* options for socket level */
+
+#define AF_UNSPEC 0
+#define AF_INET 2
+#define AF_INET6 10
+
+#define PF_UNSPEC AF_UNSPEC
+#define PF_INET AF_INET
+#define PF_INET6 AF_INET6
+
+#define IPPROTO_IP 0
+#define IPPROTO_ICMP 1
+#define IPPROTO_TCP 6
+#define IPPROTO_UDP 17
+#define IPPROTO_IPV6 41
+#define IPPROTO_ICMPV6 58
+#define IPPROTO_UDPLITE 136
+
+#define F_GETFL 3
+#define F_SETFL 4
+
+#define O_NONBLOCK 1 /* nonblocking I/O */
+
+/**
+ * @brief socket option value
+ */
+typedef enum
+{
+ SO_DEBUG = 0x0001, /**< Unimplemented: turn on debugging info recording */
+ SO_ACCEPTCONN = 0x0002, /**< socket has had listen() */
+ SO_REUSEADDR = 0x0004, /**< Allow local address reuse */
+ SO_KEEPALIVE = 0x0008, /**< keep connections alive */
+ SO_DONTROUTE = 0x0010, /**< Just use interface addresses */
+ SO_BROADCAST = 0x0020, /**< Permit to send and to receive broadcast messages */
+ SO_USELOOPBACK = 0x0040, /**< Bypass hardware when possible */
+ SO_LINGER = 0x0080, /**< linger on close if data present */
+ SO_OOBINLINE = 0x0100, /**< Leave received OOB data in line */
+ SO_REUSEPORT = 0x0200, /**< Allow local address & port reuse */
+ SO_BLOCKMODE = 0x1000, /**< set socket as block(optval=0)/non-block(optval=1) mode.
+ Default is block mode. */
+ SO_SNDBUF = 0x1001,
+ SO_SNDTIMEO = 0x1005, /**< Send timeout in block mode. block for ever in default mode. */
+ SO_RCVTIMEO = 0x1006, /**< Recv timeout in block mode. block 1 second in default mode. */
+ SO_ERROR = 0x1007, /**< Get socket error number. */
+ SO_TYPE = 0x1008, /**< Get socket type. */
+ SO_NO_CHECK = 0x100a /**< Don't create UDP checksum. */
+
+} SOCK_OPT_VAL;
+
+#if !defined __GNUC__
+#define FD_SETSIZE 64 /**< MAX fd number is 64 in MXOS. */
+#define HOWMANY(x, y) (((x) + ((y) - 1)) / (y))
+
+#define NBBY 8 /**< number of bits in a byte. */
+#define NFDBITS (sizeof(unsigned long) * NBBY) /**< bits per mask */
+
+#define MC_FDSET_MASK(n) ((unsigned long)1 << ((n) % NFDBITS))
+
+typedef struct _fd_set
+{
+ unsigned long fds_bits[HOWMANY(FD_SETSIZE, NFDBITS)];
+} fd_set;
+
+#define FD_SET(n, p) ((p)->fds_bits[(n)/NFDBITS] |= MC_FDSET_MASK(n)) /**< Add a fd to FD set. */
+#define FD_CLR(n, p) ((p)->fds_bits[(n)/NFDBITS] &= ~MC_FDSET_MASK(n)) /**< Remove fd from FD set. */
+#define FD_ISSET(n, p) ((p)->fds_bits[(n)/NFDBITS] & MC_FDSET_MASK(n)) /**< Check if the fd is set in FD set. */
+#define FD_ZERO(p) memset((p), 0, sizeof(*(p))) /**< Clear FD set. */
+#endif /* !__GNUC__ */
+
+/**
+ * @brief IP option types, level: IPPROTO_IP
+ */
+typedef enum
+{
+ IP_ADD_MEMBERSHIP = 0x0003, /**< Join multicast group. */
+ IP_DROP_MEMBERSHIP = 0x0004, /**< Leave multicast group. */
+ IP_MULTICAST_TTL = 0x0005,
+ IP_MULTICAST_IF = 0x0006,
+ IP_MULTICAST_LOOP = 0x0007
+} IP_OPT_VAL;
+
+/**
+ * @brief Create a socket.
+ * @param Obj: pointer to module handle
+ * @param domain: socket domain
+ * @param type: socket type
+ * @param protocol: socket protocol
+ * @retval Socket file descriptor, return < 1 if failed.
+ */
+int32_t MX_WIFI_Socket_create(MX_WIFIObject_t *Obj, int32_t domain, int32_t type, int32_t protocol);
+
+/**
+ * @brief Set option for a socket
+ * @param Obj: pointer to module handle
+ * @param sockfd: socket fd
+ * @param level: option level
+ * @param optname: option to set
+ * @param optvalue: value buffer for the option
+ * @param optlen: length of the option value
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_Socket_setsockopt(MX_WIFIObject_t *Obj, int32_t sockfd, int32_t level,
+ int32_t optname, const void *optvalue, int32_t optlen);
+
+/**
+ * @brief Get option of a socket.
+ * @param Obj: pointer to module handle
+ * @param sockfd: socket fd
+ * @param level: option level
+ * @param optname: option to set
+ * @param optvalue: buffer pointer of value of the option
+ * @param optlen: buffer pointer of length of the option value
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_Socket_getsockopt(MX_WIFIObject_t *Obj, int32_t sockfd, int32_t level,
+ int32_t optname, void *optvalue, uint32_t *optlen);
+
+/**
+ * @brief Bind a socket.
+ * @param Obj: pointer to module handle
+ * @param sockfd: socket fd
+ * @param addr: socket address
+ * @param addrlen: address length
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_Socket_bind(MX_WIFIObject_t *Obj, int32_t sockfd, const struct sockaddr *addr, int32_t addrlen);
+
+/**
+ * @brief Listen a socket.
+ * @param Obj: pointer to module handle
+ * @param sockfd: socket fd
+ * @param backlog: max number to queued.
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_Socket_listen(MX_WIFIObject_t *Obj, int32_t sockfd, int32_t backlog);
+
+/**
+ * @brief Accept a socket.
+ * @param Obj: pointer to module handle
+ * @param sockfd: socket fd
+ * @param addr: client address
+ * @param addrlen: length of client address
+ * @retval Accepted client socket fd, return < 0 if failed.
+ */
+int32_t MX_WIFI_Socket_accept(MX_WIFIObject_t *Obj, int32_t sockfd, struct sockaddr *addr, uint32_t *addrlen);
+
+/**
+ * @brief Socket connect.
+ * @param Obj: pointer to module handle
+ * @param sockfd: socket fd
+ * @param addr: client address
+ * @param addrlen: length of client address
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_Socket_connect(MX_WIFIObject_t *Obj, int32_t sockfd, const struct sockaddr *addr, int32_t addrlen);
+
+/**
+ * @brief Socket shutdown.
+ * @param Obj: pointer to module handle
+ * @param sockfd: socket fd
+ * @param mode: shutdown mode:
+ * 0 Stop receiving data for this socket;
+ * 1 Stop trying to transmit data from this socket
+ * 2 Stop all transmit from this socket
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_Socket_shutdown(MX_WIFIObject_t *Obj, int32_t sockfd, int32_t mode);
+
+/**
+ * @brief Socket close.
+ * @param Obj: pointer to module handle
+ * @param sockfd: socket fd
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_Socket_close(MX_WIFIObject_t *Obj, int32_t sockfd);
+
+/**
+ * @brief Socket send.
+ * @param Obj: pointer to module handle
+ * @param sockfd: socket fd
+ * @param buf: send data buffer
+ * @param len: length of send data
+ * @param flags: zero for MXOS
+ * @retval Number of bytes sent, return < 0 if failed.
+ */
+int32_t MX_WIFI_Socket_send(MX_WIFIObject_t *Obj, int32_t sockfd, uint8_t *buf, int32_t len, int32_t flags);
+
+/**
+ * @brief Socket recv.
+ * @param Obj: pointer to module handle
+ * @param sockfd: socket fd
+ * @param buf: recv buffer
+ * @param len: length of recv buffer
+ * @param flags: zero for MXOS
+ * @retval Number of bytes received, return < 0 if failed.
+ */
+int32_t MX_WIFI_Socket_recv(MX_WIFIObject_t *Obj, int32_t sockfd, uint8_t *buf, int32_t len, int32_t flags);
+
+/**
+ * @brief Socket sendto.
+ * @param Obj: pointer to module handle
+ * @param sockfd: socket fd
+ * @param buf: send data buffer
+ * @param len: length of send data
+ * @param flags: zero for MXOS
+ * @param toaddr: address to send
+ * @param toaddrlen: length of address to send
+ * @retval Number of bytes sent, return < 0 if failed.
+ */
+int32_t MX_WIFI_Socket_sendto(MX_WIFIObject_t *Obj, int32_t sockfd, uint8_t *buf, int32_t len, int32_t flags,
+ struct sockaddr *toaddr, int32_t toaddrlen);
+
+/**
+ * @brief Socket recvfrom.
+ * @param Obj: pointer to module handle
+ * @param sockfd: socket fd
+ * @param buf: recv buffer
+ * @param len: length of recv buffer
+ * @param fromaddr: address of the data source
+ * @param fromaddrlen: length of address of the data source
+ * @param flags: zero for MXOS
+ * @retval Number of bytes received, return < 0 if failed.
+ */
+int32_t MX_WIFI_Socket_recvfrom(MX_WIFIObject_t *Obj, int32_t sockfd, uint8_t *buf, int32_t len, int32_t flags,
+ struct sockaddr *fromaddr, uint32_t *fromaddrlen);
+
+/**
+ * @brief Gethostbyname, only for IPv4 address.
+ * @param Obj: pointer to module handle
+ * @param addr: address of the host
+ * @param name: hostname
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_Socket_gethostbyname(MX_WIFIObject_t *Obj, struct sockaddr *addr, char *name);
+
+/**
+ * @brief Ping a host, only for IPv4 address.
+ * @param Obj: pointer to module handle
+ * @param addr: hostname
+ * @param count: ping max count
+ * @param delay: ping delay in millisecond
+ * @param response: response time array of ping result
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_Socket_ping(MX_WIFIObject_t *Obj, const char *hostname, int32_t count, int32_t delay,
+ int32_t response[]);
+
+#if 0
+/**
+ * @brief Get IPv4/v6 address info by nodename.
+ * @param Obj: pointer to module handle
+ * @param nodename: descriptive name or address string of the host
+ * @param servname: not used, set NULL
+ * @param hints: structure containing input values that set socktype and protocol
+ * @param res: buf to store the result (set to NULL on failure)
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_Socket_getaddrinfo(MX_WIFIObject_t *Obj, const char *nodename, const char *servname,
+ const struct addrinfo *hints, struct mc_addrinfo *res);
+
+/**
+ * @brief Monitor multiple file descriptors for sockets
+ * @attention Never doing operations in different threads
+ * @param Obj: pointer to module handle
+ * @param nfds: is the highest-numbered file descriptor in any of the three
+ * sets, plus 1
+ * @param readfds: A file descriptor sets will be watched to see if characters
+ * become available for reading
+ * @param writefds: A file descriptor sets will be watched to see if a write
+ * will not block.
+ * @param exceptfds: A file descriptor sets will be watched for exceptions.
+ * @param timeout: The timeout argument specifies the interval that select()
+ * should block waiting for a file descriptor to become ready.
+ * If timeout is NULL (no timeout), select() can block until API timeout.
+ * @retval On success, return the number of file descriptors contained in the
+ * three returned descriptor sets (that is, the total number of bits
+ * that are set in readfds, writefds, exceptfds) which may be zero if
+ * the timeout expires before anything interesting happens. On error,
+ * -1 is returned, the file descriptor sets are unmodified, and timeout
+ * becomes undefined.
+ */
+int32_t MX_WIFI_Socket_select(MX_WIFIObject_t *Obj, int32_t nfds, fd_set *readfds, fd_set *writefds,
+ fd_set *exceptfds, struct mc_timeval *timeout);
+#endif /* 0 */
+
+
+/**
+ * @brief socket getpeername.
+ * @param Obj: pointer to module handle
+ * @param sockfd: socket fd
+ * @param addr: address buffer
+ * @param addrlen: size of address buffer
+ * @retval get address of peer socket, return < 0 if failed.
+ */
+int32_t MX_WIFI_Socket_getpeername(MX_WIFIObject_t *Obj, int32_t sockfd, struct sockaddr *addr, uint32_t *addrlen);
+
+/**
+ * @brief socket getsockname.
+ * @param Obj: pointer to module handle
+ * @param sockfd: socket fd
+ * @param addr: address buffer
+ * @param addrlen: size of address buffer
+ * @retval get address of local socket, return < 0 if failed.
+ */
+int32_t MX_WIFI_Socket_getsockname(MX_WIFIObject_t *Obj, int32_t sockfd, struct sockaddr *addr, uint32_t *addrlen);
+
+/**
+ * @} **
+ */
+
+/**
+ * @defgroup MX_WIFI_MDNS mDNS
+ * @brief mDNS related API
+ * @{ **
+ */
+
+/** Maximum length of labels
+ *
+ * A label is one segment of a DNS name. For example, "foo" is a label in the
+ * name "foo.local.". RFC 1035 requires that labels do not exceed 63 bytes.
+ */
+#define MDNS_MAX_LABEL_LEN 63 /* defined by the standard */
+
+/** Maximum length of names
+ *
+ * A name is a list of labels such as "My Webserver.foo.local" or
+ * mydevice.local. RFC 1035 requires that names do not exceed 255 bytes.
+ */
+#define MDNS_MAX_NAME_LEN 255 /* defined by the standard : 255*/
+
+/** Maximum length of key/value pair
+ *
+ * TXT records associated with a service are populated with key/value pairs.
+ * These key/value pairs must not exceed this length.
+ */
+#define MDNS_MAX_KEYVAL_LEN 255 /* defined by the standard : 255*/
+
+/** protocol values for the proto member of the mdns_service descriptor */
+/** TCP Protocol */
+#define MDNS_PROTO_TCP 0
+/** UDP Protocol */
+#define MDNS_PROTO_UDP 1
+
+/** Maximum no. of services allowed to be announced on a single interface. */
+#define MAX_MDNS_LST 5 /* Maximum no. of services */
+
+/* MDNS Error Codes */
+#define ERR_MDNS_BASE -36650 /**< Starting error code for all mdns errors. */
+#define ERR_MDNS_INVAL -36651 /**< invalid argument */
+#define ERR_MDNS_BADSRC -36652 /**< bad service descriptor */
+#define ERR_MDNS_TOOBIG -36653 /**< not enough room for everything */
+#define ERR_MDNS_NOIMPL -36654 /**< unimplemented feature */
+#define ERR_MDNS_NOMEM -36655 /**< insufficient memory */
+#define ERR_MDNS_INUSE -36656 /**< requested resource is in use */
+#define ERR_MDNS_NORESP -36657 /**< requested resource is in use */
+#define ERR_MDNS_FSOC -36658 /**< failed to create socket for mdns */
+#define ERR_MDNS_FREUSE -36659 /**< failed to reuse multicast socket */
+#define ERR_MDNS_FBINDTODEVICE -36660 /**< failed to bind mdns socket to device */
+#define ERR_MDNS_FBIND -36661 /**< failed to bind mdns socket */
+#define ERR_MDNS_FMCAST_JOIN -36662 /**< failed to join multicast socket */
+#define ERR_MDNS_FMCAST_SET -36663 /**< failed to set multicast socket */
+#define ERR_MDNS_FQUERY_SOC -36664 /**< failed to create query socket */
+#define ERR_MDNS_FQUERY_THREAD -36665 /**< failed to create mdns thread */
+#define ERR_MDNS_END -36670 /**< Last generic error code (inclusive) */
+
+/** mDNS Interface State
+ * mDNS interface state can be changed by using mdns_iface_state_change()
+ * function. For details about when to use the enum please refer to
+ * documentation for mdns_iface_state_change(). */
+enum iface_state
+{
+ /** UP the interface and announce services
+ * mDNS will probe and announce all services announced via
+ * mdns_announce_service() and/or mdns_announce_service_arr().
+ * mDNS will go through entire probing sequence explained in above
+ * functions. Interface state can be changed to UP, if its DOWN.
+ */
+ UP = 0,
+ /** DOWN the interface and de-announce services
+ * mDNS sends good bye packet with ttl=0 so that mDNS clients can remove
+ * the services from their mDNS cache table.
+ */
+ DOWN,
+ /** Forcefully re-announce services
+ * This state should be used after services are already
+ * announced and force announcement is needed due to some reason.
+ * mDNS will not perform probing sequence, as it does in case of UP, and
+ * will directly re-announce services.
+ */
+ REANNOUNCE
+};
+
+/**
+ * @brief mDNS service info
+ */
+#pragma pack(1)
+struct mc_mdns_service
+{
+ /** Name of MDNS service */
+ char servname[MDNS_MAX_LABEL_LEN + 1];
+ /** Type of MDNS service */
+ char servtype[MDNS_MAX_LABEL_LEN + 1];
+ /** Domain for MDNS service */
+ char domain[MDNS_MAX_LABEL_LEN + 1];
+ /** Port number */
+ uint16_t port;
+ /** Protocol used */
+ int32_t proto;
+ /** Key value pairs for TXT records*/
+ char keyvals[MDNS_MAX_KEYVAL_LEN + 1];
+ /** IP Address of device */
+ uint32_t ipaddr;
+ /** IPv6 Address of device */
+ uint32_t ip6addr[4];
+
+ /** separator for txt record */
+ char separator; /* user set this for keyvals */
+};
+#pragma pack()
+
+/**
+ * @brief start mDNS service.
+ * @param Obj: pointer to module handle
+ * @param domain: domain of service
+ * @param name: hostname
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_MDNS_start(MX_WIFIObject_t *Obj, const char *domain, char *hostname);
+
+/**
+ * @brief stop mDNS service.
+ * @param Obj: pointer to module handle
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_MDNS_stop(MX_WIFIObject_t *Obj);
+
+/**
+ * @brief announce a service.
+ * @param Obj: pointer to module handle
+ * @param service: service to announce
+ * @param interface: wifi interface
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_MDNS_announce_service(MX_WIFIObject_t *Obj, struct mc_mdns_service *service, mwifi_if_t interface);
+
+/**
+ * @brief deannounce a service.
+ * @param Obj: pointer to module handle
+ * @param service: service to deannounce
+ * @param interface: wifi interface
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_MDNS_deannounce_service(MX_WIFIObject_t *Obj, struct mc_mdns_service *service, mwifi_if_t interface);
+
+/**
+ * @brief deannounce all services.
+ * @param Obj: pointer to module handle
+ * @param interface: wifi interface
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_MDNS_deannounce_service_all(MX_WIFIObject_t *Obj, mwifi_if_t interface);
+
+/**
+ * @brief Send interface state change event to mdns
+ * @param Obj: pointer to module handle
+ * @param interface: wifi interface
+ * @param state: state event, valid interface state from \ref iface_state
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_MDNS_iface_state_change(MX_WIFIObject_t *Obj, mwifi_if_t interface, enum iface_state state);
+
+/**
+ * @brief Set new host name, use mdns_iface_state_change(interface, REANNOUNCE) to anounce
+ * the new host name.
+ * @param Obj: pointer to module handle
+ * @param hostname: new hostname
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_MDNS_set_hostname(MX_WIFIObject_t *Obj, char *hostname);
+
+/**
+ * @brief sets the TXT record field for a given mDNS service.
+ * @param Obj: pointer to module handle
+ * @param service: mDNS service
+ * @param keyvals: new txt record string
+ * @param separator: the separator used to separate individual key value pairs
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_MDNS_set_txt_rec(MX_WIFIObject_t *Obj, struct mc_mdns_service *service, char *keyvals,
+ char separator);
+
+/**
+ * @} **
+ */
+
+/**
+ * @defgroup MX_WIFI_TLS TLS
+ * @brief TLS related API
+ * @{ **
+ */
+
+/**
+ * @brief mxchip TLS handler type
+ */
+typedef void *mtls_t;
+
+/**
+ * @brief mxchip TLS version
+ */
+enum
+{
+ SSL_V3_MODE = 1, /**< SSL V3 */
+ TLS_V1_0_MODE = 2, /**< TLS V1.0 */
+ TLS_V1_1_MODE = 3, /**< TLS V1.1 */
+ TLS_V1_2_MODE = 4 /**< TLS V1.2 */
+};
+
+typedef uint8_t mtls_ver_t;
+
+/**
+ * @brief set the TLS protocol version.
+ * @param Obj: pointer to module handle
+ * @param version: TLS protocol version
+ * @retval Operation Status.
+ * @note This function should be called before TLS is ready to function (before
+ * mtls_connect and mtls_accept is called by application ).
+ */
+int32_t MX_WIFI_TLS_set_ver(MX_WIFIObject_t *Obj, mtls_ver_t version);
+
+/**
+ * @brief TLS set client certificate
+ * @param Obj: pointer to module handle
+ * @param client_cert: Point to buffer of client cert.
+ * @param cert_len: length of the client cert.
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_TLS_set_clientCertificate(MX_WIFIObject_t *Obj, uint8_t *client_cert, uint16_t cert_len);
+
+/**
+ * @brief TLS set client private key
+ * @param Obj: pointer to module handle
+ * @param client_private_key: Point to buffer of client private key.
+ * @param key_len: length of the client cert.
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_TLS_set_clientPrivateKey(MX_WIFIObject_t *Obj, uint8_t *client_private_key, uint16_t key_len);
+
+/**
+ * @brief TLS client create a TLS connection.
+ * @param Obj: pointer to module handle
+ * @details This function is called on the client side and initiates an TLS/TLS handshake with a
+ * server. When this function is called, the underlying communication channel has already
+ * been set up. This function is called after TCP 3-way handshak finished.
+ * @param domain: Specifies a communication domain
+ * @param type: Specifies the communication semantics.
+ * @param protocol: specifies a particular protocol to be used with the socket.
+ * @param addr: Point to the target address to be connected
+ * @param addrlen: containing the size of the buffer pointed to by addr
+ * @param ca: pointer to the CA certificate string, used to verify server's certificate.
+ * @param calen: the string length of ca. 0=do not verify server's certificate.
+ * @retval return the TLS context pointer on success or NULL for fail.
+ */
+int32_t MX_WIFI_TLS_connect(MX_WIFIObject_t *Obj, int32_t domain, int32_t type, int32_t protocol,
+ const struct sockaddr *addr, int32_t addrlen, char *ca, int32_t calen);
+
+/**
+ * @brief TLS client create a TLS connection with SNI.
+ * @param Obj: pointer to module handle
+ * @details This function is called on the client side and initiates an TLS/TLS handshake with a
+ * server. When this function is called, the underlying communication channel has already
+ * been set up. This function is called after TCP 3-way handshak finished.
+ * @param sni_servername: Specifies the SNI servername
+ * @param sni_servername_len: Specifies the SNI servername length, max size MX_TLS_SNI_SERVERNAME_SIZE
+ * @param addr: Point to the target address to be connected
+ * @param addrlen: containing the size of the buffer pointed to by addr
+ * @param ca: pointer to the CA certificate string, used to verify server's certificate.
+ * @param calen: the string length of ca. 0=do not verify server's certificate.
+ * @retval return the TLS context pointer on success or NULL for fail.
+ */
+int32_t MX_WIFI_TLS_connect_sni(MX_WIFIObject_t *Obj, const char *sni_servername, int32_t sni_servername_len,
+ const struct sockaddr *addr, int32_t addrlen, char *ca, int32_t calen);
+
+/**
+ * @brief TLS send data
+ * @param Obj: pointer to module handle
+ * @param tls: Point to the TLS context.
+ * @param data: Point to data to send.
+ * @param len: data length.
+ * @retval On success, return the number of bytes sent. On error,
+ * error code (< 0) is returned.
+ */
+int32_t MX_WIFI_TLS_send(MX_WIFIObject_t *Obj, mtls_t tls, void *data, int32_t len);
+
+/**
+ * @brief TLS redeive data
+ * @param Obj: pointer to module handle
+ * @param tls: Point to the TLS context.
+ * @param data: Point to buffer to receive TLS data.
+ * @param len: max receive buffer length.
+ * @retval On success, return the number of bytes received. On error,
+ * error code (< 0) is returned.
+ */
+int32_t MX_WIFI_TLS_recv(MX_WIFIObject_t *Obj, mtls_t tls, void *buf, int32_t len);
+
+/**
+ * @brief Close the TLS session, release resource.
+ * @param Obj: pointer to module handle
+ * @param tls: Point to the TLS context.
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_TLS_close(MX_WIFIObject_t *Obj, mtls_t tls);
+
+/**
+ * @brief Set TLS nonblock mode.
+ * @param Obj: pointer to module handle
+ * @param tls: Point to the TLS context.
+ * @param nonblock: true - nonblock, flase - block
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_TLS_set_nonblock(MX_WIFIObject_t *Obj, mtls_t tls, int32_t nonblock);
+
+/**
+ * @} **
+ */
+
+
+/**
+ * @defgroup MX_WIFI_WEBSERVER Webserver
+ * @brief Webserver related API
+ * @{ **
+ */
+
+
+/**
+ * @brief Start webserver.
+ * @param Obj: pointer to module handle
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_Webserver_start(MX_WIFIObject_t *Obj);
+
+/**
+ * @brief Stop webserver.
+ * @param Obj: pointer to module handle
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_Webserver_stop(MX_WIFIObject_t *Obj);
+
+
+/**
+ * @} **
+ */
+
+
+/**
+ * @defgroup MX_WIFI_FOTA FOTA
+ * @brief FOTA related API
+ * @{ **
+ */
+
+
+/**
+ * @brief Start FOTA.
+ * @param Obj: pointer to module handle
+ * @param url: HTTP/HTTPS url of bin file to update
+ * @param md5: MD5 string(32Bytes) of bin file to update
+ * @param ota_status_callback: callback function for ota status
+ * @retval Operation Status.
+ */
+int32_t MX_WIFI_FOTA_start(MX_WIFIObject_t *Obj, const char *url, const char *md5,
+ mx_wifi_fota_status_cb_t fota_status_callback, uint32_t user_args);
+
+/**
+ * @} **
+ */
+
+/**
+ * @defgroup MX_WIFI_STATION_POWERSAVE
+ * @brief Wi-Fi station powersave API
+ * @{ **
+ */
+
+#endif /* MX_WIFI_NETWORK_BYPASS_MODE */
+
+/**
+ * @} **
+ */
+
+
+/**
+ * @} **
+ */
+
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* MX_WIFI_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/mx_wifi/mx_wifi.md b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/mx_wifi/mx_wifi.md
new file mode 100644
index 00000000..c54237a3
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/mx_wifi/mx_wifi.md
@@ -0,0 +1,324 @@
+---
+pagetitle: Release Notes for MX_WIFI Component Driver
+lang: en
+header-includes:
+# Release Notes for MX_WIFI Component Driver
+Copyright © 2020 STMicroelectronics\
+Microcontrollers Division - Application Team
+
+[](https://www.st.com){.logo}
+
+
+
+# Purpose
+
+This directory contains the Wi-Fi component driver running on STM32 host for the EMW3080B Wi-Fi module from MXCHIP.
+
+:::
+
+::: {.col-sm-12 .col-lg-8}
+# Update History
+
+::: {.collapse}
+V2.1.11 / 17-June-2021
+
+## Main changes
+
+ - Update the way to declare licenses
+ - Fix MISRA and Codesonar errors
+ - Create IO pattern files for UART and SPI interface
+ - Adress some code alignment and cosmetics
+
+## Limitation
+ - Access point mode with the TCP/IP mode on STM32 host is not functional. It works when TCP/IP runs on the EMW3080B module.
+
+
+
+
+:::
+
+
+::: {.collapse}
+V2.1.10 / 8-April-2021
+
+## Main changes
+
+ - Clean configuration for FreeRTOS and Bare metal support
+ - Add Support for MXCHIP Firmware 2.1.10 (adding updater)
+ - Driver is backward compatible to 2.1.9 firmware
+ - Tested on U5 Discovery board Rev C
+
+
+:::
+
+::: {.collapse}
+V2.1.9 / 30-March-2021
+
+## Main changes
+
+ - Strongly improve performances and stability
+ - Add SPI DMA support
+ - Fix Access Point mode support
+ - Tested on U5 Discovery board Rev C
+
+
+:::
+
+::: {.collapse}
+V2.1.6 / 09-February-2021
+
+## Main changes
+
+ - Add Error mngt
+ - Remove Circular buffer, use directly Pbuf
+ - Improve debug msg and echo server
+ - Fix memory overrun
+ - Adding debug support
+ - SPI protocol fix
+ - SPI checksum fix
+ - Improve OS porting, change LOCK
+ - Improve Malloc and Messages Macros
+
+
+:::
+
+
+::: {.collapse}
+V2.1.4 / 08-February-2021
+
+## Main changes
+
+ - Overall driver rework
+ - SPI fix
+ - Race condition fixes
+ - Optimized memory usage
+
+
+:::
+
+
+::: {.collapse}
+V1.4.0 / 18-November-2020
+
+## Main changes
+
+ - Add new API getsockname, getpeername
+
+
+:::
+
+::: {.collapse}
+V1.3.0 / 05-November-2020
+
+## Main changes
+
+ - Hardware flow control: removed the flow pin usage
+ - MISRA-C_2012 compliant
+ - AStyle run
+ - Fixed CodeSonar warnings
+ - Licensed under ST license SLA0044 (the "License")
+
+
+:::
+
+::: {.collapse}
+V1.0.4 / 15-May-2020
+
+
+## Main changes
+
+ - First official release of MX_WIFI WiFi component.
+
+
+:::
+
+# Firmware update
+
+ - The EMW3080B MXCHIP Wi-Fi module firmware and the way to update your board with it are available at [X-WIFI-EMW3080B](https://www.st.com/en/development-tools/x-wifi-emw3080b.html).
+ - Below are noted 2 methods for updating the EMW3080B Wi-Fi module firmware
+ - On top for the B-U585I-IOT02A, the above web page on st.com will provide a flasher simplifying the firmware update procedure (click to open)
+
+
+
+
+::: {.collapse}
+
+Update via UART
+
+
+This section provides you with a step by step procedure to upload the MXCHIP firmware of an MXCHIP Arduino shield using the MXCHIP UART interface.
+
+Prerequisites:
+
+ - The steps described in this document use Tera Term as a terminal emulator. For the firmware update, you should not use a version more recent than 4.85 as you may encounter some issues when using YModem.
+ - The material you need to have is:
+ - a USB to TTL connector
+ - 4 male to female cables with PCX connectors
+ - 1 female to female cable with PCX connectors
+
+
+
+:::
+
+::: {.collapse}
+Update via SWD
+
+
+This section provides you with a step by step procedure to upload the MXCHIP firmware of an MXCHIP Arduino shield using the SWD interface.
+
+The MXCHIP-FlashTool is a software tool running on PC in order to download a MXCHIP firmware using the SWD interface.
+
+The MXCHIP-FlashTool is supported on these PC OS:
+
+ - Windows 7/10
+ - MacOS
+ - Linux
+
+And with these debug probes:
+
+ - J-LINK
+ - ST-LINK_V2
+ - ST-LINK_V2-1
+
+Prerequisites:
+
+ - The MXCHIP-Flash tool is to be installed as described into the below "Tool installation" section.
+ - The material you need to have is:
+ - A debug probe
+ - 4 female to female cables with PCX connectors
+ - A 3.3 V generator. Another board can be used as shown in the below picture supplying the power via 2 male to male cables with PCX connectors
+Tool installation:
+
+ - Python3 installation:
+ - Goto the official website to download python:
+ - Run zadig with administrator rights
+ - Select: Options / List All Devices / Bulk interface / Replace Driver
+
+Connect the debug probe to the MXCHIP board
+
+ - Debug probe VCC to MXCHIP VDD
+ - Debug probe DIO to MXCHIP DIO
+ - Debug probe SCK to MXCHIP CLK
+ - Debug probe GND to MXCHIP GND
+
+Connect the +3.3 V and GND MXCHIP board to a power supply.
+
+{width=60%}
+
+
+:::
+
+
+
+
+:::
+:::
+
+
+For complete documentation on STM32 microcontrollers please visit
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/mx_wifi/mx_wifi_conf_template.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/mx_wifi/mx_wifi_conf_template.h
new file mode 100644
index 00000000..020f976e
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/mx_wifi/mx_wifi_conf_template.h
@@ -0,0 +1,234 @@
+/**
+ ******************************************************************************
+ * @file mx_wifi_conf_template.h
+ * @author MCD Application Team
+ * @brief Header for mx_wifi_conf_template module
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef MX_WIFI_CONF_TEMPLATE_H
+#define MX_WIFI_CONF_TEMPLATE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include
+
+int32_t mxwifi_probe(void **ll_drv_context);
+
+/* use SPI interface by default */
+
+#ifndef MX_WIFI_USE_SPI
+#define MX_WIFI_USE_SPI (1)
+#endif /* MX_WIFI_USE_SPI */
+
+/* do not use RTOS but bare metal approach by default */
+#ifndef MX_WIFI_USE_CMSIS_OS
+#define MX_WIFI_USE_CMSIS_OS (0)
+#endif /* MX_WIFI_USE_CMSIS_OS */
+
+/* Use At command mode by default, TCP/IP stack is running on module */
+#ifndef MX_WIFI_NETWORK_BYPASS_MODE
+#define MX_WIFI_NETWORK_BYPASS_MODE (0)
+#endif /* MX_WIFI_NETWORK_BYPASS_MODE */
+
+
+/* Do not copy TX buffer */
+#ifndef MX_WIFI_TX_BUFFER_NO_COPY
+#define MX_WIFI_TX_BUFFER_NO_COPY (1)
+#endif /* MX_WIFI_TX_BUFFER_NO_COPY */
+
+
+/* DEBUG LOG */
+/* #define MX_WIFI_API_DEBUG */
+/* #define MX_WIFI_IPC_DEBUG */
+/* #define MX_WIFI_HCI_DEBUG */
+/* #define MX_WIFI_SLIP_DEBUG */
+/* #define MX_WIFI_IO_DEBUG */
+
+/* check if OS primitive are already declared */
+/* if not, include default declaration */
+#ifndef LOCK_DECLARE
+
+#if (MX_WIFI_USE_CMSIS_OS == 1)
+#include "mx_wifi_cmsis_os.h"
+#else
+#include "mx_wifi_bare_os.h"
+#endif /* MX_WIFI_USE_CMSIS_OS */
+
+#endif /* LOCK_DECLARE */
+
+
+#define MX_WIFI_PRODUCT_NAME ("MXCHIP-WIFI")
+#define MX_WIFI_PRODUCT_ID ("EMW3080B")
+
+#ifndef MX_WIFI_USE_SPI
+#define MX_WIFI_USE_SPI (0)
+#endif /* MX_WIFI_USE_SPI */
+
+
+#ifndef MX_WIFI_UART_BAUDRATE
+#define MX_WIFI_UART_BAUDRATE (115200*2)
+#endif /* MX_WIFI_UART_BAUDRATE */
+
+#ifndef MX_WIFI_MTU_SIZE
+#define MX_WIFI_MTU_SIZE (1500)
+#endif /* MX_WIFI_MTU_SIZE */
+
+#define MX_WIFI_BYPASS_HEADER_SIZE (28) /* MX_IPC_header(6) + sizeof(bypass_in_t)(22),
+ * set with PBUF_LINK_ENCAPSULATION_HLEN */
+#define MX_WIFI_PBUF_LINK_HLEN (14) /* link header (PBUF_LINK_HLEN) set in lwip */
+
+#if (MX_WIFI_NETWORK_BYPASS_MODE==1)
+/* Use lwip PBUF_POOL_BUFSIZE = TCP_MSS + 40 + PBUF_LINK_ENCAPSULATION_HLEN + PBUF_LINK_HLEN. */
+#define MX_WIFI_BUFFER_SIZE \
+ (MX_WIFI_MTU_SIZE + MX_WIFI_BYPASS_HEADER_SIZE + MX_WIFI_PBUF_LINK_HLEN)
+#else
+#define MX_WIFI_BUFFER_SIZE (2500) /* bigger buffer size */
+#endif /* (MX_WIFI_NETWORK_BYPASS_MODE==1) */
+
+/* MX_WIFI_BUFFER_SIZE - MX_IPC_header */
+#define MX_WIFI_IPC_PAYLOAD_SIZE ((MX_WIFI_BUFFER_SIZE) - 6)
+
+/* MX_WIFI_IPC_PAYLOAD_SIZE - socket_api_params_header */
+#define MX_WIFI_SOCKET_DATA_SIZE ((MX_WIFI_IPC_PAYLOAD_SIZE)-12)
+
+#ifndef MX_WIFI_CMD_TIMEOUT
+#define MX_WIFI_CMD_TIMEOUT (10000)
+#endif
+#define MX_WIFI_MAX_SOCKET_NBR (8)
+#define MX_WIFI_MAX_DETECTED_AP (10)
+
+#define MX_WIFI_MAX_SSID_NAME_SIZE 32
+#define MX_WIFI_MAX_PSWD_NAME_SIZE 64
+
+#define MX_WIFI_PRODUCT_NAME_SIZE 32
+#define MX_WIFI_PRODUCT_ID_SIZE 32
+
+#define MX_WIFI_FW_REV_SIZE 24
+#ifndef MX_WIFI_SPI_THREAD_PRIORITY
+#define MX_WIFI_SPI_THREAD_PRIORITY (OSPRIORITYREALTIME)
+#endif /* MX_WIFI_SPI_THREAD_PRIORITY */
+#ifndef MX_WIFI_SPI_THREAD_STACK_SIZE
+#define MX_WIFI_SPI_THREAD_STACK_SIZE (1024)
+#endif /* MX_WIFI_SPI_THREAD_STACK_SIZE */
+
+
+
+#ifndef MX_WIFI_RECEIVED_THREAD_PRIORITY
+#define MX_WIFI_RECEIVED_THREAD_PRIORITY (OSPRIORITYABOVENORMAL)
+#endif /* MX_WIFI_RECEIVED_THREAD_PRIORITY */
+
+#ifndef MX_WIFI_RECEIVED_THREAD_STACK_SIZE
+#define MX_WIFI_RECEIVED_THREAD_STACK_SIZE (1024)
+#endif /* MX_WIFI_RECEIVED_THREAD_STACK_SIZE*/
+
+#ifndef MX_WIFI_TRANSMIT_THREAD_PRIORITY
+#define MX_WIFI_TRANSMIT_THREAD_PRIORITY (OSPRIORITYABOVENORMAL)
+#endif /* MX_WIFI_TRANSMIT_THREAD_PRIORITY */
+
+#ifndef MX_WIFI_TRANSMIT_THREAD_STACK_SIZE
+#define MX_WIFI_TRANSMIT_THREAD_STACK_SIZE (1024)
+#endif /* MX_WIFI_TRANSMIT_THREAD_STACK_SIZE */
+
+
+/* Maximum number of RX buffer that can be queued by Hardware interface (SPI/UART) */
+/* This is used to size internal queue, and avoid to block the IP thread if it can still push some buffers */
+/* Impact on Memory foot print is weak , one single void* per place in the queue */
+#ifndef MX_WIFI_MAX_RX_BUFFER_COUNT
+#define MX_WIFI_MAX_RX_BUFFER_COUNT (2)
+#endif /* MX_WIFI_MAX_RX_BUFFER_COUNT */
+
+
+/* Maximum number of TX buffer that can be queued by IP stack (LwIP or Netx) without blocking the calling thread */
+/* This is used to size internal queue, and avoid to block the IP thread if it can still push some buffers */
+/* Impact on Memory foot print is one single void* per place in the queue, but it may lead to over allocation */
+/* TCP/IP stack (LwIP for instance ) */
+#ifndef MX_WIFI_MAX_TX_BUFFER_COUNT
+#define MX_WIFI_MAX_TX_BUFFER_COUNT (4)
+#endif /* MX_WIFI_MAX_TX_BUFFER_COUNT */
+
+
+
+/**
+ * For the TX buffer, by default no-copy feature is enabled, meaning that
+ * the IP buffer are used in the whole process and should come with
+ * available room in front of payload to accommodate transport header buffer.
+ * This is managed in interface between driver and IP stack
+ */
+
+/**
+ * For LwIP "PBUF_LINK_ENCAPSULATION_HLEN" must be defined as > MX_WIFI_MIN_TX_HEADER_SIZE,
+ * see net_mx_wifi/c file for implementation.
+ */
+#define MX_WIFI_MIN_TX_HEADER_SIZE (28)
+
+#ifndef MX_WIFI_TX_BUFFER_NO_COPY
+#define MX_WIFI_TX_BUFFER_NO_COPY (1)
+#endif /* MX_WIFI_TX_BUFFER_NO_COPY */
+
+
+/* Sizeof the circular buffer for Uart mode, when buffer is hlaf full data are transmitted to next stage */
+#ifndef MX_CIRCULAR_UART_RX_BUFFER_SIZE
+#define MX_CIRCULAR_UART_RX_BUFFER_SIZE (400)
+#endif /* MX_CIRCULAR_UART_RX_BUFFER_SIZE */
+
+
+
+#ifndef MX_STAT_ON
+#define MX_STAT_ON 0
+#endif /* MX_STAT_ON */
+
+#if MX_STAT_ON == 1
+typedef struct
+{
+ uint32_t alloc;
+ uint32_t free;
+ uint32_t cmd_get_answer;
+ uint32_t callback;
+ uint32_t in_fifo;
+ uint32_t out_fifo;
+} mx_stat_t;
+
+extern mx_stat_t mx_stat;
+
+#define MX_STAT_LOG() \
+ (void) printf("Number of allocated buffer for Rx and command answer %ld\n", mx_stat.alloc);\
+ (void) printf("Number of free buffer %ld\n",mx_stat.free);\
+ (void) printf("Number of command answer %ld , callback %ld, sum of both %ld (should match alloc && free)\n",\
+ mx_stat.cmd_get_answer,mx_stat.callback,mx_stat.cmd_get_answer+mx_stat.callback);\
+ (void) printf("Number of posted answer (callback + cmd answer) %ld, processed answer %ld\n",\
+ mx_stat.in_fifo,mx_stat.out_fifo);\
+
+#define MX_STAT_INIT() (void) memset((void*)&mx_stat, 0, sizeof(mx_stat))
+#define MX_STAT(A) mx_stat.A++
+#define MX_STAT_DECLARE() mx_stat_t mx_stat
+
+#else
+
+#define MX_STAT_INIT()
+#define MX_STAT(A)
+#define MX_STAT_LOG()
+#define MX_STAT_DECLARE()
+
+#endif /* MX_STAT_ON */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* MX_WIFI_CONF_TEMPLATE_H */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/ov5640/ov5640.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/ov5640/ov5640.c
new file mode 100644
index 00000000..fdea0eed
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/ov5640/ov5640.c
@@ -0,0 +1,2076 @@
+/**
+ ******************************************************************************
+ * @file ov5640.c
+ * @author MCD Application Team
+ * @brief This file provides the OV5640 camera driver
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved. © Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
+
+/** @addtogroup BSP
+ * @{
+ */
+
+/** @addtogroup Components
+ * @{
+ */
+
+/** @addtogroup ov5640
+ * @{
+ */
+
+/** @defgroup OV5640_Exported_Types
+ * @{
+ */
+
+typedef int32_t (*OV5640_Init_Func)(void);
+typedef int32_t (*OV5640_DeInit_Func)(void);
+typedef int32_t (*OV5640_GetTick_Func)(void);
+typedef int32_t (*OV5640_Delay_Func)(uint32_t);
+typedef int32_t (*OV5640_WriteReg_Func)(uint16_t, uint16_t, uint8_t *, uint16_t);
+typedef int32_t (*OV5640_ReadReg_Func)(uint16_t, uint16_t, uint8_t *, uint16_t);
+
+typedef struct
+{
+ OV5640_Init_Func Init;
+ OV5640_DeInit_Func DeInit;
+ uint16_t Address;
+ OV5640_WriteReg_Func WriteReg;
+ OV5640_ReadReg_Func ReadReg;
+ OV5640_GetTick_Func GetTick;
+} OV5640_IO_t;
+
+
+typedef struct
+{
+ OV5640_IO_t IO;
+ ov5640_ctx_t Ctx;
+ uint8_t IsInitialized;
+} OV5640_Object_t;
+
+typedef struct
+{
+ uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */
+ uint8_t LineStartCode; /*!< Specifies the code of the line start delimiter. */
+ uint8_t LineEndCode; /*!< Specifies the code of the line end delimiter. */
+ uint8_t FrameEndCode; /*!< Specifies the code of the frame end delimiter. */
+
+} OV5640_SyncCodes_t;
+
+typedef struct
+{
+ uint32_t Config_Resolution;
+ uint32_t Config_LightMode;
+ uint32_t Config_SpecialEffect;
+ uint32_t Config_Brightness;
+ uint32_t Config_Saturation;
+ uint32_t Config_Contrast;
+ uint32_t Config_HueDegree;
+ uint32_t Config_MirrorFlip;
+ uint32_t Config_Zoom;
+ uint32_t Config_NightMode;
+} OV5640_Capabilities_t;
+
+typedef struct
+{
+ int32_t (*Init)(OV5640_Object_t *, uint32_t, uint32_t);
+ int32_t (*DeInit)(OV5640_Object_t *);
+ int32_t (*ReadID)(OV5640_Object_t *, uint32_t *);
+ int32_t (*GetCapabilities)(OV5640_Object_t *, OV5640_Capabilities_t *);
+ int32_t (*SetLightMode)(OV5640_Object_t *, uint32_t);
+ int32_t (*SetColorEffect)(OV5640_Object_t *, uint32_t);
+ int32_t (*SetBrightness)(OV5640_Object_t *, int32_t);
+ int32_t (*SetSaturation)(OV5640_Object_t *, int32_t);
+ int32_t (*SetContrast)(OV5640_Object_t *, int32_t);
+ int32_t (*SetHueDegree)(OV5640_Object_t *, int32_t);
+ int32_t (*MirrorFlipConfig)(OV5640_Object_t *, uint32_t);
+ int32_t (*ZoomConfig)(OV5640_Object_t *, uint32_t);
+ int32_t (*SetResolution)(OV5640_Object_t *, uint32_t);
+ int32_t (*GetResolution)(OV5640_Object_t *, uint32_t *);
+ int32_t (*SetPixelFormat)(OV5640_Object_t *, uint32_t);
+ int32_t (*GetPixelFormat)(OV5640_Object_t *, uint32_t *);
+ int32_t (*NightModeConfig)(OV5640_Object_t *, uint32_t);
+} OV5640_CAMERA_Drv_t;
+/**
+ * @}
+ */
+
+/** @defgroup OV5640_Exported_Constants
+ * @{
+ */
+#define OV5640_OK (0)
+#define OV5640_ERROR (-1)
+/**
+ * @brief OV5640 Features Parameters
+ */
+/* Camera resolutions */
+#define OV5640_R160x120 0x00U /* QQVGA Resolution */
+#define OV5640_R320x240 0x01U /* QVGA Resolution */
+#define OV5640_R480x272 0x02U /* 480x272 Resolution */
+#define OV5640_R640x480 0x03U /* VGA Resolution */
+#define OV5640_R800x480 0x04U /* WVGA Resolution */
+
+/* Camera Pixel Format */
+#define OV5640_RGB565 0x00U /* Pixel Format RGB565 */
+#define OV5640_RGB888 0x01U /* Pixel Format RGB888 */
+#define OV5640_YUV422 0x02U /* Pixel Format YUV422 */
+#define OV5640_Y8 0x07U /* Pixel Format Y8 */
+#define OV5640_JPEG 0x08U /* Compressed format JPEG */
+
+/* Polarity */
+#define OV5640_POLARITY_PCLK_LOW 0x00U /* Signal Active Low */
+#define OV5640_POLARITY_PCLK_HIGH 0x01U /* Signal Active High */
+#define OV5640_POLARITY_HREF_LOW 0x00U /* Signal Active Low */
+#define OV5640_POLARITY_HREF_HIGH 0x01U /* Signal Active High */
+#define OV5640_POLARITY_VSYNC_LOW 0x01U /* Signal Active Low */
+#define OV5640_POLARITY_VSYNC_HIGH 0x00U /* Signal Active High */
+
+/* Mirror/Flip */
+#define OV5640_MIRROR_FLIP_NONE 0x00U /* Set camera normal mode */
+#define OV5640_FLIP 0x01U /* Set camera flip config */
+#define OV5640_MIRROR 0x02U /* Set camera mirror config */
+#define OV5640_MIRROR_FLIP 0x03U /* Set camera mirror and flip */
+
+/* Zoom */
+#define OV5640_ZOOM_x8 0x00U /* Set zoom to x8 */
+#define OV5640_ZOOM_x4 0x11U /* Set zoom to x4 */
+#define OV5640_ZOOM_x2 0x22U /* Set zoom to x2 */
+#define OV5640_ZOOM_x1 0x44U /* Set zoom to x1 */
+
+/* Special Effect */
+#define OV5640_COLOR_EFFECT_NONE 0x00U /* No effect */
+#define OV5640_COLOR_EFFECT_BLUE 0x01U /* Blue effect */
+#define OV5640_COLOR_EFFECT_RED 0x02U /* Red effect */
+#define OV5640_COLOR_EFFECT_GREEN 0x04U /* Green effect */
+#define OV5640_COLOR_EFFECT_BW 0x08U /* Black and White effect */
+#define OV5640_COLOR_EFFECT_SEPIA 0x10U /* Sepia effect */
+#define OV5640_COLOR_EFFECT_NEGATIVE 0x20U /* Negative effect */
+
+
+/* Light Mode */
+#define OV5640_LIGHT_AUTO 0x00U /* Light Mode Auto */
+#define OV5640_LIGHT_SUNNY 0x01U /* Light Mode Sunny */
+#define OV5640_LIGHT_OFFICE 0x02U /* Light Mode Office */
+#define OV5640_LIGHT_HOME 0x04U /* Light Mode Home */
+#define OV5640_LIGHT_CLOUDY 0x08U /* Light Mode Claudy */
+
+/* Night Mode */
+#define NIGHT_MODE_DISABLE 0x00U /* Disable night mode */
+#define NIGHT_MODE_ENABLE 0x01U /* Enable night mode */
+
+/* Colorbar Mode */
+#define COLORBAR_MODE_DISABLE 0x00U /* Disable colorbar mode */
+#define COLORBAR_MODE_ENABLE 0x01U /* 8 bars W/Y/C/G/M/R/B/Bl */
+#define COLORBAR_MODE_GRADUALV 0x02U /* Gradual vertical colorbar */
+
+/* Pixel Clock */
+#define OV5640_PCLK_7M 0x00U /* Pixel Clock set to 7Mhz */
+#define OV5640_PCLK_8M 0x01U /* Pixel Clock set to 8Mhz */
+#define OV5640_PCLK_9M 0x02U /* Pixel Clock set to 9Mhz */
+#define OV5640_PCLK_12M 0x04U /* Pixel Clock set to 12Mhz */
+#define OV5640_PCLK_24M 0x08U /* Pixel Clock set to 24Mhz */
+
+/**
+ * @}
+ */
+
+/** @defgroup OV5640_Exported_Functions OV5640 Exported Functions
+ * @{
+ */
+int32_t OV5640_RegisterBusIO(OV5640_Object_t *pObj, OV5640_IO_t *pIO);
+int32_t OV5640_Init(OV5640_Object_t *pObj, uint32_t Resolution, uint32_t PixelFormat);
+int32_t OV5640_DeInit(OV5640_Object_t *pObj);
+int32_t OV5640_ReadID(OV5640_Object_t *pObj, uint32_t *Id);
+int32_t OV5640_GetCapabilities(OV5640_Object_t *pObj, OV5640_Capabilities_t *Capabilities);
+int32_t OV5640_SetLightMode(OV5640_Object_t *pObj, uint32_t LightMode);
+int32_t OV5640_SetColorEffect(OV5640_Object_t *pObj, uint32_t Effect);
+int32_t OV5640_SetBrightness(OV5640_Object_t *pObj, int32_t Level);
+int32_t OV5640_SetSaturation(OV5640_Object_t *pObj, int32_t Level);
+int32_t OV5640_SetContrast(OV5640_Object_t *pObj, int32_t Level);
+int32_t OV5640_SetHueDegree(OV5640_Object_t *pObj, int32_t Degree);
+int32_t OV5640_MirrorFlipConfig(OV5640_Object_t *pObj, uint32_t Config);
+int32_t OV5640_ZoomConfig(OV5640_Object_t *pObj, uint32_t Zoom);
+int32_t OV5640_SetResolution(OV5640_Object_t *pObj, uint32_t Resolution);
+int32_t OV5640_GetResolution(OV5640_Object_t *pObj, uint32_t *Resolution);
+int32_t OV5640_SetPixelFormat(OV5640_Object_t *pObj, uint32_t PixelFormat);
+int32_t OV5640_GetPixelFormat(OV5640_Object_t *pObj, uint32_t *PixelFormat);
+int32_t OV5640_SetPolarities(OV5640_Object_t *pObj, uint32_t PclkPolarity, uint32_t HrefPolarity,
+ uint32_t VsyncPolarity);
+int32_t OV5640_GetPolarities(OV5640_Object_t *pObj, uint32_t *PclkPolarity, uint32_t *HrefPolarity,
+ uint32_t *VsyncPolarity);
+int32_t OV5640_NightModeConfig(OV5640_Object_t *pObj, uint32_t Cmd);
+int32_t OV5640_ColorbarModeConfig(OV5640_Object_t *pObj, uint32_t Cmd);
+int32_t OV5640_EmbeddedSynchroConfig(OV5640_Object_t *pObj, OV5640_SyncCodes_t *pSyncCodes);
+int32_t OV5640_SetPCLK(OV5640_Object_t *pObj, uint32_t ClockValue);
+
+/* CAMERA driver structure */
+extern OV5640_CAMERA_Drv_t OV5640_CAMERA_Driver;
+/**
+ * @}
+ */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* OV5640_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/ov5640/ov5640_reg.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/ov5640/ov5640_reg.c
new file mode 100644
index 00000000..3fee034d
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/ov5640/ov5640_reg.c
@@ -0,0 +1,76 @@
+/**
+ ******************************************************************************
+ * @file ov5640_reg.c
+ * @author MCD Application Team
+ * @brief This file provides unitary register function to control the OV5640
+ * Camera driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved. © Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+/** @addtogroup BSP
+ * @{
+ */
+
+/** @addtogroup Components
+ * @{
+ */
+
+/** @addtogroup OV5640
+ * @{
+ */
+
+/** @defgroup OV5640_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup OV5640_Exported_Constants OV5640 Exported Constants
+ * @{
+ */
+
+/**
+ * @brief OV5640 ID
+ */
+#define OV5640_ID 0x5640U
+/**
+ * @brief OV5640 Registers
+ */
+/* system and IO pad control [0x3000 ~ 0x3052] */
+#define OV5640_SYSREM_RESET00 0x3000U
+#define OV5640_SYSREM_RESET01 0x3001U
+#define OV5640_SYSREM_RESET02 0x3002U
+#define OV5640_SYSREM_RESET03 0x3003U
+#define OV5640_CLOCK_ENABLE00 0x3004U
+#define OV5640_CLOCK_ENABLE01 0x3005U
+#define OV5640_CLOCK_ENABLE02 0x3006U
+#define OV5640_CLOCK_ENABLE03 0x3007U
+#define OV5640_SYSTEM_CTROL0 0x3008U
+#define OV5640_CHIP_ID_HIGH_BYTE 0x300AU
+#define OV5640_CHIP_ID_LOW_BYTE 0x300BU
+#define OV5640_MIPI_CONTROL00 0x300EU
+#define OV5640_PAD_OUTPUT_ENABLE00 0x3016U
+#define OV5640_PAD_OUTPUT_ENABLE01 0x3017U
+#define OV5640_PAD_OUTPUT_ENABLE02 0x3018U
+#define OV5640_PAD_OUTPUT_VALUE00 0x3019U
+#define OV5640_PAD_OUTPUT_VALUE01 0x301AU
+#define OV5640_PAD_OUTPUT_VALUE02 0x301BU
+#define OV5640_PAD_SELECT00 0x301CU
+#define OV5640_PAD_SELECT01 0x301DU
+#define OV5640_PAD_SELECT02 0x301EU
+#define OV5640_CHIP_REVISION 0x302AU
+#define OV5640_PAD_CONTROL00 0x301CU
+#define OV5640_SC_PWC 0x3031U
+#define OV5640_SC_PLL_CONTRL0 0x3034U
+#define OV5640_SC_PLL_CONTRL1 0x3035U
+#define OV5640_SC_PLL_CONTRL2 0x3036U
+#define OV5640_SC_PLL_CONTRL3 0x3037U
+#define OV5640_SC_PLL_CONTRL4 0x3038U
+#define OV5640_SC_PLL_CONTRL5 0x3039U
+#define OV5640_SC_PLLS_CTRL0 0x303AU
+#define OV5640_SC_PLLS_CTRL1 0x303BU
+#define OV5640_SC_PLLS_CTRL2 0x303CU
+#define OV5640_SC_PLLS_CTRL3 0x303DU
+#define OV5640_IO_PAD_VALUE00 0x3050U
+#define OV5640_IO_PAD_VALUE01 0x3051U
+#define OV5640_IO_PAD_VALUE02 0x3052U
+
+/* SCCB control [0x3100 ~ 0x3108] */
+#define OV5640_SCCB_ID 0x3100U
+#define OV5640_SCCB_SYSTEM_CTRL0 0x3102U
+#define OV5640_SCCB_SYSTEM_CTRL1 0x3103U
+#define OV5640_SYSTEM_ROOT_DIVIDER 0x3108U
+
+/* SRB control [0x3200 ~ 0x3213] */
+#define OV5640_GROUP_ADDR0 0x3200U
+#define OV5640_GROUP_ADDR1 0x3201U
+#define OV5640_GROUP_ADDR2 0x3202U
+#define OV5640_GROUP_ADDR3 0x3203U
+#define OV5640_SRM_GROUP_ACCESS 0x3212U
+#define OV5640_SRM_GROUP_STATUS 0x3213U
+
+/* AWB gain control [0x3400 ~ 0x3406] */
+#define OV5640_AWB_R_GAIN_MSB 0x3400U
+#define OV5640_AWB_R_GAIN_LSB 0x3401U
+#define OV5640_AWB_G_GAIN_MSB 0x3402U
+#define OV5640_AWB_G_GAIN_LSB 0x3403U
+#define OV5640_AWB_B_GAIN_MSB 0x3404U
+#define OV5640_AWB_B_GAIN_LSB 0x3405U
+#define OV5640_AWB_MANUAL_CONTROL 0x3406U
+
+/* AEC/AGC control [0x3500 ~ 0x350D] */
+#define OV5640_AEC_PK_EXPOSURE_19_16 0x3500U
+#define OV5640_AEC_PK_EXPOSURE_HIGH 0x3501U
+#define OV5640_AEC_PK_EXPOSURE_LOW 0x3502U
+#define OV5640_AEC_PK_MANUAL 0x3503U
+#define OV5640_AEC_PK_REAL_GAIN_9_8 0x350AU
+#define OV5640_AEC_PK_REAL_GAIN_LOW 0x350BU
+#define OV5640_AEC_PK_VTS_HIGH 0x350CU
+#define OV5640_AEC_PK_VTS_LOW 0x350DU
+
+/* VCM control [0x3600 ~ 0x3606] */
+#define OV5640_VCM_CONTROL_0 0x3602U
+#define OV5640_VCM_CONTROL_1 0x3603U
+#define OV5640_VCM_CONTROL_2 0x3604U
+#define OV5640_VCM_CONTROL_3 0x3605U
+#define OV5640_VCM_CONTROL_4 0x3606U
+
+/* timing control [0x3800 ~ 0x3821] */
+#define OV5640_TIMING_HS_HIGH 0x3800U
+#define OV5640_TIMING_HS_LOW 0x3801U
+#define OV5640_TIMING_VS_HIGH 0x3802U
+#define OV5640_TIMING_VS_LOW 0x3803U
+#define OV5640_TIMING_HW_HIGH 0x3804U
+#define OV5640_TIMING_HW_LOW 0x3805U
+#define OV5640_TIMING_VH_HIGH 0x3806U
+#define OV5640_TIMING_VH_LOW 0x3807U
+#define OV5640_TIMING_DVPHO_HIGH 0x3808U
+#define OV5640_TIMING_DVPHO_LOW 0x3809U
+#define OV5640_TIMING_DVPVO_HIGH 0x380AU
+#define OV5640_TIMING_DVPVO_LOW 0x380BU
+#define OV5640_TIMING_HTS_HIGH 0x380CU
+#define OV5640_TIMING_HTS_LOW 0x380DU
+#define OV5640_TIMING_VTS_HIGH 0x380EU
+#define OV5640_TIMING_VTS_LOW 0x380FU
+#define OV5640_TIMING_HOFFSET_HIGH 0x3810U
+#define OV5640_TIMING_HOFFSET_LOW 0x3811U
+#define OV5640_TIMING_VOFFSET_HIGH 0x3812U
+#define OV5640_TIMING_VOFFSET_LOW 0x3813U
+#define OV5640_TIMING_X_INC 0x3814U
+#define OV5640_TIMING_Y_INC 0x3815U
+#define OV5640_HSYNC_START_HIGH 0x3816U
+#define OV5640_HSYNC_START_LOW 0x3817U
+#define OV5640_HSYNC_WIDTH_HIGH 0x3818U
+#define OV5640_HSYNC_WIDTH_LOW 0x3819U
+#define OV5640_TIMING_TC_REG20 0x3820U
+#define OV5640_TIMING_TC_REG21 0x3821U
+
+/* AEC/AGC power down domain control [0x3A00 ~ 0x3A25] */
+#define OV5640_AEC_CTRL00 0x3A00U
+#define OV5640_AEC_CTRL01 0x3A01U
+#define OV5640_AEC_CTRL02 0x3A02U
+#define OV5640_AEC_CTRL03 0x3A03U
+#define OV5640_AEC_CTRL04 0x3A04U
+#define OV5640_AEC_CTRL05 0x3A05U
+#define OV5640_AEC_CTRL06 0x3A06U
+#define OV5640_AEC_CTRL07 0x3A07U
+#define OV5640_AEC_B50_STEP_HIGH 0x3A08U
+#define OV5640_AEC_B50_STEP_LOW 0x3A09U
+#define OV5640_AEC_B60_STEP_HIGH 0x3A0AU
+#define OV5640_AEC_B60_STEP_LOW 0x3A0BU
+#define OV5640_AEC_AEC_CTRL0C 0x3A0CU
+#define OV5640_AEC_CTRL0D 0x3A0DU
+#define OV5640_AEC_CTRL0E 0x3A0EU
+#define OV5640_AEC_CTRL0F 0x3A0FU
+#define OV5640_AEC_CTRL10 0x3A10U
+#define OV5640_AEC_CTRL11 0x3A11U
+#define OV5640_AEC_CTRL13 0x3A13U
+#define OV5640_AEC_MAX_EXPO_HIGH 0x3A14U
+#define OV5640_AEC_MAX_EXPO_LOW 0x3A15U
+#define OV5640_AEC_CTRL17 0x3A17U
+#define OV5640_AEC_GAIN_CEILING_HIGH 0x3A18U
+#define OV5640_AEC_GAIN_CEILING_LOW 0x3A19U
+#define OV5640_AEC_DIFF_MIN 0x3A1AU
+#define OV5640_AEC_CTRL1B 0x3A1BU
+#define OV5640_LED_ADD_ROW_HIGH 0x3A1CU
+#define OV5640_LED_ADD_ROW_LOW 0x3A1DU
+#define OV5640_AEC_CTRL1E 0x3A1EU
+#define OV5640_AEC_CTRL1F 0x3A1FU
+#define OV5640_AEC_CTRL20 0x3A20U
+#define OV5640_AEC_CTRL21 0x3A21U
+#define OV5640_AEC_CTRL25 0x3A25U
+
+/* strobe control [0x3B00 ~ 0x3B0C] */
+#define OV5640_STROBE_CTRL 0x3B00U
+#define OV5640_FREX_EXPOSURE02 0x3B01U
+#define OV5640_FREX_SHUTTER_DLY01 0x3B02U
+#define OV5640_FREX_SHUTTER_DLY00 0x3B03U
+#define OV5640_FREX_EXPOSURE01 0x3B04U
+#define OV5640_FREX_EXPOSURE00 0x3B05U
+#define OV5640_FREX_CTRL07 0x3B06U
+#define OV5640_FREX_MODE 0x3B07U
+#define OV5640_FREX_RQST 0x3B08U
+#define OV5640_FREX_HREF_DLY 0x3B09U
+#define OV5640_FREX_RST_LENGTH 0x3B0AU
+#define OV5640_STROBE_WIDTH_HIGH 0x3B0BU
+#define OV5640_STROBE_WIDTH_LOW 0x3B0CU
+
+/* 50/60Hz detector control [0x3C00 ~ 0x3C1E] */
+#define OV5640_5060HZ_CTRL00 0x3C00U
+#define OV5640_5060HZ_CTRL01 0x3C01U
+#define OV5640_5060HZ_CTRL02 0x3C02U
+#define OV5640_5060HZ_CTRL03 0x3C03U
+#define OV5640_5060HZ_CTRL04 0x3C04U
+#define OV5640_5060HZ_CTRL05 0x3C05U
+#define OV5640_LIGHTMETER1_TH_HIGH 0x3C06U
+#define OV5640_LIGHTMETER1_TH_LOW 0x3C07U
+#define OV5640_LIGHTMETER2_TH_HIGH 0x3C08U
+#define OV5640_LIGHTMETER2_TH_LOW 0x3C09U
+#define OV5640_SAMPLE_NUMBER_HIGH 0x3C0AU
+#define OV5640_SAMPLE_NUMBER_LOW 0x3C0BU
+#define OV5640_SIGMA_DELTA_CTRL0C 0x3C0CU
+#define OV5640_SUM50_BYTE4 0x3C0DU
+#define OV5640_SUM50_BYTE3 0x3C0EU
+#define OV5640_SUM50_BYTE2 0x3C0FU
+#define OV5640_SUM50_BYTE1 0x3C10U
+#define OV5640_SUM60_BYTE4 0x3C11U
+#define OV5640_SUM60_BYTE3 0x3C12U
+#define OV5640_SUM60_BYTE2 0x3C13U
+#define OV5640_SUM60_BYTE1 0x3C14U
+#define OV5640_SUM5060_HIGH 0x3C15U
+#define OV5640_SUM5060_LOW 0x3C16U
+#define OV5640_BLOCK_CNTR_HIGH 0x3C17U
+#define OV5640_BLOCK_CNTR_LOW 0x3C18U
+#define OV5640_B6_HIGH 0x3C19U
+#define OV5640_B6_LOW 0x3C1AU
+#define OV5640_LIGHTMETER_OUTPUT_BYTE3 0x3C1BU
+#define OV5640_LIGHTMETER_OUTPUT_BYTE2 0x3C1CU
+#define OV5640_LIGHTMETER_OUTPUT_BYTE1 0x3C1DU
+#define OV5640_SUM_THRESHOLD 0x3C1EU
+
+/* OTP control [0x3D00 ~ 0x3D21] */
+/* MC control [0x3F00 ~ 0x3F0D] */
+/* BLC control [0x4000 ~ 0x4033] */
+#define OV5640_BLC_CTRL00 0x4000U
+#define OV5640_BLC_CTRL01 0x4001U
+#define OV5640_BLC_CTRL02 0x4002U
+#define OV5640_BLC_CTRL03 0x4003U
+#define OV5640_BLC_CTRL04 0x4004U
+#define OV5640_BLC_CTRL05 0x4005U
+
+/* frame control [0x4201 ~ 0x4202] */
+#define OV5640_FRAME_CTRL01 0x4201U
+#define OV5640_FRAME_CTRL02 0x4202U
+
+/* format control [0x4300 ~ 0x430D] */
+#define OV5640_FORMAT_CTRL00 0x4300U
+#define OV5640_FORMAT_CTRL01 0x4301U
+#define OV5640_YMAX_VAL_HIGH 0x4302U
+#define OV5640_YMAX_VAL_LOW 0x4303U
+#define OV5640_YMIN_VAL_HIGH 0x4304U
+#define OV5640_YMIN_VAL_LOW 0x4305U
+#define OV5640_UMAX_VAL_HIGH 0x4306U
+#define OV5640_UMAX_VAL_LOW 0x4307U
+#define OV5640_UMIN_VAL_HIGH 0x4308U
+#define OV5640_UMIN_VAL_LOW 0x4309U
+#define OV5640_VMAX_VAL_HIGH 0x430AU
+#define OV5640_VMAX_VAL_LOW 0x430BU
+#define OV5640_VMIN_VAL_HIGH 0x430CU
+#define OV5640_VMIN_VAL_LOW 0x430DU
+
+/* JPEG control [0x4400 ~ 0x4431] */
+#define OV5640_JPEG_CTRL00 0x4400U
+#define OV5640_JPEG_CTRL01 0x4401U
+#define OV5640_JPEG_CTRL02 0x4402U
+#define OV5640_JPEG_CTRL03 0x4403U
+#define OV5640_JPEG_CTRL04 0x4404U
+#define OV5640_JPEG_CTRL05 0x4405U
+#define OV5640_JPEG_CTRL06 0x4406U
+#define OV5640_JPEG_CTRL07 0x4407U
+#define OV5640_JPEG_ISI_CTRL1 0x4408U
+#define OV5640_JPEG_CTRL09 0x4409U
+#define OV5640_JPEG_CTRL0A 0x440AU
+#define OV5640_JPEG_CTRL0B 0x440BU
+#define OV5640_JPEG_CTRL0C 0x440CU
+#define OV5640_JPEG_QT_DATA 0x4410U
+#define OV5640_JPEG_QT_ADDR 0x4411U
+#define OV5640_JPEG_ISI_DATA 0x4412U
+#define OV5640_JPEG_ISI_CTRL2 0x4413U
+#define OV5640_JPEG_LENGTH_BYTE3 0x4414U
+#define OV5640_JPEG_LENGTH_BYTE2 0x4415U
+#define OV5640_JPEG_LENGTH_BYTE1 0x4416U
+#define OV5640_JFIFO_OVERFLOW 0x4417U
+
+/* VFIFO control [0x4600 ~ 0x460D] */
+#define OV5640_VFIFO_CTRL00 0x4600U
+#define OV5640_VFIFO_HSIZE_HIGH 0x4602U
+#define OV5640_VFIFO_HSIZE_LOW 0x4603U
+#define OV5640_VFIFO_VSIZE_HIGH 0x4604U
+#define OV5640_VFIFO_VSIZE_LOW 0x4605U
+#define OV5640_VFIFO_CTRL0C 0x460CU
+#define OV5640_VFIFO_CTRL0D 0x460DU
+
+/* DVP control [0x4709 ~ 0x4745] */
+#define OV5640_DVP_VSYNC_WIDTH0 0x4709U
+#define OV5640_DVP_VSYNC_WIDTH1 0x470AU
+#define OV5640_DVP_VSYNC_WIDTH2 0x470BU
+#define OV5640_PAD_LEFT_CTRL 0x4711U
+#define OV5640_PAD_RIGHT_CTRL 0x4712U
+#define OV5640_JPG_MODE_SELECT 0x4713U
+#define OV5640_656_DUMMY_LINE 0x4715U
+#define OV5640_CCIR656_CTRL 0x4719U
+#define OV5640_HSYNC_CTRL00 0x471BU
+#define OV5640_DVP_VSYN_CTRL 0x471DU
+#define OV5640_DVP_HREF_CTRL 0x471FU
+#define OV5640_VSTART_OFFSET 0x4721U
+#define OV5640_VEND_OFFSET 0x4722U
+#define OV5640_DVP_CTRL23 0x4723U
+#define OV5640_CCIR656_CTRL00 0x4730U
+#define OV5640_CCIR656_CTRL01 0x4731U
+#define OV5640_CCIR656_FS 0x4732U
+#define OV5640_CCIR656_FE 0x4733U
+#define OV5640_CCIR656_LS 0x4734U
+#define OV5640_CCIR656_LE 0x4735U
+#define OV5640_CCIR656_CTRL06 0x4736U
+#define OV5640_CCIR656_CTRL07 0x4737U
+#define OV5640_CCIR656_CTRL08 0x4738U
+#define OV5640_POLARITY_CTRL 0x4740U
+#define OV5640_TEST_PATTERN 0x4741U
+#define OV5640_DATA_ORDER 0x4745U
+
+/* MIPI control [0x4800 ~ 0x4837] */
+#define OV5640_MIPI_CTRL00 0x4800U
+#define OV5640_MIPI_CTRL01 0x4801U
+#define OV5640_MIPI_CTRL05 0x4805U
+#define OV5640_MIPI_DATA_ORDER 0x480AU
+#define OV5640_MIN_HS_ZERO_HIGH 0x4818U
+#define OV5640_MIN_HS_ZERO_LOW 0x4819U
+#define OV5640_MIN_MIPI_HS_TRAIL_HIGH 0x481AU
+#define OV5640_MIN_MIPI_HS_TRAIL_LOW 0x481BU
+#define OV5640_MIN_MIPI_CLK_ZERO_HIGH 0x481CU
+#define OV5640_MIN_MIPI_CLK_ZERO_LOW 0x481DU
+#define OV5640_MIN_MIPI_CLK_PREPARE_HIGH 0x481EU
+#define OV5640_MIN_MIPI_CLK_PREPARE_LOW 0x481FU
+#define OV5640_MIN_CLK_POST_HIGH 0x4820U
+#define OV5640_MIN_CLK_POST_LOW 0x4821U
+#define OV5640_MIN_CLK_TRAIL_HIGH 0x4822U
+#define OV5640_MIN_CLK_TRAIL_LOW 0x4823U
+#define OV5640_MIN_LPX_PCLK_HIGH 0x4824U
+#define OV5640_MIN_LPX_PCLK_LOW 0x4825U
+#define OV5640_MIN_HS_PREPARE_HIGH 0x4826U
+#define OV5640_MIN_HS_PREPARE_LOW 0x4827U
+#define OV5640_MIN_HS_EXIT_HIGH 0x4828U
+#define OV5640_MIN_HS_EXIT_LOW 0x4829U
+#define OV5640_MIN_HS_ZERO_UI 0x482AU
+#define OV5640_MIN_HS_TRAIL_UI 0x482BU
+#define OV5640_MIN_CLK_ZERO_UI 0x482CU
+#define OV5640_MIN_CLK_PREPARE_UI 0x482DU
+#define OV5640_MIN_CLK_POST_UI 0x482EU
+#define OV5640_MIN_CLK_TRAIL_UI 0x482FU
+#define OV5640_MIN_LPX_PCLK_UI 0x4830U
+#define OV5640_MIN_HS_PREPARE_UI 0x4831U
+#define OV5640_MIN_HS_EXIT_UI 0x4832U
+#define OV5640_PCLK_PERIOD 0x4837U
+
+/* ISP frame control [0x4901 ~ 0x4902] */
+#define OV5640_ISP_FRAME_CTRL01 0x4901U
+#define OV5640_ISP_FRAME_CTRL02 0x4902U
+
+/* ISP top control [0x5000 ~ 0x5063] */
+#define OV5640_ISP_CONTROL00 0x5000U
+#define OV5640_ISP_CONTROL01 0x5001U
+#define OV5640_ISP_CONTROL03 0x5003U
+#define OV5640_ISP_CONTROL05 0x5005U
+#define OV5640_ISP_MISC0 0x501DU
+#define OV5640_ISP_MISC1 0x501EU
+#define OV5640_FORMAT_MUX_CTRL 0x501FU
+#define OV5640_DITHER_CTRL0 0x5020U
+#define OV5640_DRAW_WINDOW_CTRL00 0x5027U
+#define OV5640_DRAW_WINDOW_LEFT_CTRL_HIGH 0x5028U
+#define OV5640_DRAW_WINDOW_LEFT_CTRL_LOW 0x5029U
+#define OV5640_DRAW_WINDOW_RIGHT_CTRL_HIGH 0x502AU
+#define OV5640_DRAW_WINDOW_RIGHT_CTRL_LOW 0x502BU
+#define OV5640_DRAW_WINDOW_TOP_CTRL_HIGH 0x502CU
+#define OV5640_DRAW_WINDOW_TOP_CTRL_LOW 0x502DU
+#define OV5640_DRAW_WINDOW_BOTTOM_CTRL_HIGH 0x502EU
+#define OV5640_DRAW_WINDOW_BOTTOM_CTRL_LOW 0x502FU
+#define OV5640_DRAW_WINDOW_HBW_CTRL_HIGH 0x5030U /* HBW: Horizontal Boundary Width */
+#define OV5640_DRAW_WINDOW_HBW_CTRL_LOW 0x5031U
+#define OV5640_DRAW_WINDOW_VBW_CTRL_HIGH 0x5032U /* VBW: Vertical Boundary Width */
+#define OV5640_DRAW_WINDOW_VBW_CTRL_LOW 0x5033U
+#define OV5640_DRAW_WINDOW_Y_CTRL 0x5034U
+#define OV5640_DRAW_WINDOW_U_CTRL 0x5035U
+#define OV5640_DRAW_WINDOW_V_CTRL 0x5036U
+#define OV5640_PRE_ISP_TEST_SETTING1 0x503DU
+#define OV5640_ISP_SENSOR_BIAS_I 0x5061U
+#define OV5640_ISP_SENSOR_GAIN1_I 0x5062U
+#define OV5640_ISP_SENSOR_GAIN2_I 0x5063U
+
+/* AWB control [0x5180 ~ 0x51D0] */
+#define OV5640_AWB_CTRL00 0x5180U
+#define OV5640_AWB_CTRL01 0x5181U
+#define OV5640_AWB_CTRL02 0x5182U
+#define OV5640_AWB_CTRL03 0x5183U
+#define OV5640_AWB_CTRL04 0x5184U
+#define OV5640_AWB_CTRL05 0x5185U
+#define OV5640_AWB_CTRL06 0x5186U /* Advanced AWB control registers: 0x5186 ~ 0x5190 */
+#define OV5640_AWB_CTRL07 0x5187U
+#define OV5640_AWB_CTRL08 0x5188U
+#define OV5640_AWB_CTRL09 0x5189U
+#define OV5640_AWB_CTRL10 0x518AU
+#define OV5640_AWB_CTRL11 0x518BU
+#define OV5640_AWB_CTRL12 0x518CU
+#define OV5640_AWB_CTRL13 0x518DU
+#define OV5640_AWB_CTRL14 0x518EU
+#define OV5640_AWB_CTRL15 0x518FU
+#define OV5640_AWB_CTRL16 0x5190U
+#define OV5640_AWB_CTRL17 0x5191U
+#define OV5640_AWB_CTRL18 0x5192U
+#define OV5640_AWB_CTRL19 0x5193U
+#define OV5640_AWB_CTRL20 0x5194U
+#define OV5640_AWB_CTRL21 0x5195U
+#define OV5640_AWB_CTRL22 0x5196U
+#define OV5640_AWB_CTRL23 0x5197U
+#define OV5640_AWB_CTRL24 0x5198U
+#define OV5640_AWB_CTRL25 0x5199U
+#define OV5640_AWB_CTRL26 0x519AU
+#define OV5640_AWB_CTRL27 0x519BU
+#define OV5640_AWB_CTRL28 0x519CU
+#define OV5640_AWB_CTRL29 0x519DU
+#define OV5640_AWB_CTRL30 0x519EU
+#define OV5640_AWB_CURRENT_R_GAIN_HIGH 0x519FU
+#define OV5640_AWB_CURRENT_R_GAIN_LOW 0x51A0U
+#define OV5640_AWB_CURRENT_G_GAIN_HIGH 0x51A1U
+#define OV5640_AWB_CURRENT_G_GAIN_LOW 0x51A2U
+#define OV5640_AWB_CURRENT_B_GAIN_HIGH 0x51A3U
+#define OV5640_AWB_CURRENT_B_GAIN_LOW 0x51A4U
+#define OV5640_AWB_AVERAGE_R 0x51A5U
+#define OV5640_AWB_AVERAGE_G 0x51A6U
+#define OV5640_AWB_AVERAGE_B 0x51A7U
+#define OV5640_AWB_CTRL74 0x5180U
+
+/* CIP control [0x5300 ~ 0x530F] */
+#define OV5640_CIP_SHARPENMT_TH1 0x5300U
+#define OV5640_CIP_SHARPENMT_TH2 0x5301U
+#define OV5640_CIP_SHARPENMT_OFFSET1 0x5302U
+#define OV5640_CIP_SHARPENMT_OFFSET2 0x5303U
+#define OV5640_CIP_DNS_TH1 0x5304U
+#define OV5640_CIP_DNS_TH2 0x5305U
+#define OV5640_CIP_DNS_OFFSET1 0x5306U
+#define OV5640_CIP_DNS_OFFSET2 0x5307U
+#define OV5640_CIP_CTRL 0x5308U
+#define OV5640_CIP_SHARPENTH_TH1 0x5309U
+#define OV5640_CIP_SHARPENTH_TH2 0x530AU
+#define OV5640_CIP_SHARPENTH_OFFSET1 0x530BU
+#define OV5640_CIP_SHARPENTH_OFFSET2 0x530CU
+#define OV5640_CIP_EDGE_MT_AUTO 0x530DU
+#define OV5640_CIP_DNS_TH_AUTO 0x530EU
+#define OV5640_CIP_SHARPEN_TH_AUTO 0x530FU
+
+/* CMX control [0x5380 ~ 0x538B] */
+#define OV5640_CMX_CTRL 0x5380U
+#define OV5640_CMX1 0x5381U
+#define OV5640_CMX2 0x5382U
+#define OV5640_CMX3 0x5383U
+#define OV5640_CMX4 0x5384U
+#define OV5640_CMX5 0x5385U
+#define OV5640_CMX6 0x5386U
+#define OV5640_CMX7 0x5387U
+#define OV5640_CMX8 0x5388U
+#define OV5640_CMX9 0x5389U
+#define OV5640_CMXSIGN_HIGH 0x538AU
+#define OV5640_CMXSIGN_LOW 0x538BU
+
+/* gamma control [0x5480 ~ 0x5490] */
+#define OV5640_GAMMA_CTRL00 0x5480U
+#define OV5640_GAMMA_YST00 0x5481U
+#define OV5640_GAMMA_YST01 0x5482U
+#define OV5640_GAMMA_YST02 0x5483U
+#define OV5640_GAMMA_YST03 0x5484U
+#define OV5640_GAMMA_YST04 0x5485U
+#define OV5640_GAMMA_YST05 0x5486U
+#define OV5640_GAMMA_YST06 0x5487U
+#define OV5640_GAMMA_YST07 0x5488U
+#define OV5640_GAMMA_YST08 0x5489U
+#define OV5640_GAMMA_YST09 0x548AU
+#define OV5640_GAMMA_YST0A 0x548BU
+#define OV5640_GAMMA_YST0B 0x548CU
+#define OV5640_GAMMA_YST0C 0x548DU
+#define OV5640_GAMMA_YST0D 0x548EU
+#define OV5640_GAMMA_YST0E 0x548FU
+#define OV5640_GAMMA_YST0F 0x5490U
+
+/* SDE control [0x5580 ~ 0x558C] */
+#define OV5640_SDE_CTRL0 0x5580U
+#define OV5640_SDE_CTRL1 0x5581U
+#define OV5640_SDE_CTRL2 0x5582U
+#define OV5640_SDE_CTRL3 0x5583U
+#define OV5640_SDE_CTRL4 0x5584U
+#define OV5640_SDE_CTRL5 0x5585U
+#define OV5640_SDE_CTRL6 0x5586U
+#define OV5640_SDE_CTRL7 0x5587U
+#define OV5640_SDE_CTRL8 0x5588U
+#define OV5640_SDE_CTRL9 0x5589U
+#define OV5640_SDE_CTRL10 0x558AU
+#define OV5640_SDE_CTRL11 0x558BU
+#define OV5640_SDE_CTRL12 0x558CU
+
+/* scale control [0x5600 ~ 0x5606] */
+#define OV5640_SCALE_CTRL0 0x5600U
+#define OV5640_SCALE_CTRL1 0x5601U
+#define OV5640_SCALE_CTRL2 0x5602U
+#define OV5640_SCALE_CTRL3 0x5603U
+#define OV5640_SCALE_CTRL4 0x5604U
+#define OV5640_SCALE_CTRL5 0x5605U
+#define OV5640_SCALE_CTRL6 0x5606U
+
+
+/* AVG control [0x5680 ~ 0x56A2] */
+#define OV5640_X_START_HIGH 0x5680U
+#define OV5640_X_START_LOW 0x5681U
+#define OV5640_Y_START_HIGH 0x5682U
+#define OV5640_Y_START_LOW 0x5683U
+#define OV5640_X_WINDOW_HIGH 0x5684U
+#define OV5640_X_WINDOW_LOW 0x5685U
+#define OV5640_Y_WINDOW_HIGH 0x5686U
+#define OV5640_Y_WINDOW_LOW 0x5687U
+#define OV5640_WEIGHT00 0x5688U
+#define OV5640_WEIGHT01 0x5689U
+#define OV5640_WEIGHT02 0x568AU
+#define OV5640_WEIGHT03 0x568BU
+#define OV5640_WEIGHT04 0x568CU
+#define OV5640_WEIGHT05 0x568DU
+#define OV5640_WEIGHT06 0x568EU
+#define OV5640_WEIGHT07 0x568FU
+#define OV5640_AVG_CTRL10 0x5690U
+#define OV5640_AVG_WIN_00 0x5691U
+#define OV5640_AVG_WIN_01 0x5692U
+#define OV5640_AVG_WIN_02 0x5693U
+#define OV5640_AVG_WIN_03 0x5694U
+#define OV5640_AVG_WIN_10 0x5695U
+#define OV5640_AVG_WIN_11 0x5696U
+#define OV5640_AVG_WIN_12 0x5697U
+#define OV5640_AVG_WIN_13 0x5698U
+#define OV5640_AVG_WIN_20 0x5699U
+#define OV5640_AVG_WIN_21 0x569AU
+#define OV5640_AVG_WIN_22 0x569BU
+#define OV5640_AVG_WIN_23 0x569CU
+#define OV5640_AVG_WIN_30 0x569DU
+#define OV5640_AVG_WIN_31 0x569EU
+#define OV5640_AVG_WIN_32 0x569FU
+#define OV5640_AVG_WIN_33 0x56A0U
+#define OV5640_AVG_READOUT 0x56A1U
+#define OV5640_AVG_WEIGHT_SUM 0x56A2U
+
+/* LENC control [0x5800 ~ 0x5849] */
+#define OV5640_GMTRX00 0x5800U
+#define OV5640_GMTRX01 0x5801U
+#define OV5640_GMTRX02 0x5802U
+#define OV5640_GMTRX03 0x5803U
+#define OV5640_GMTRX04 0x5804U
+#define OV5640_GMTRX05 0x5805U
+#define OV5640_GMTRX10 0x5806U
+#define OV5640_GMTRX11 0x5807U
+#define OV5640_GMTRX12 0x5808U
+#define OV5640_GMTRX13 0x5809U
+#define OV5640_GMTRX14 0x580AU
+#define OV5640_GMTRX15 0x580BU
+#define OV5640_GMTRX20 0x580CU
+#define OV5640_GMTRX21 0x580DU
+#define OV5640_GMTRX22 0x580EU
+#define OV5640_GMTRX23 0x580FU
+#define OV5640_GMTRX24 0x5810U
+#define OV5640_GMTRX25 0x5811U
+#define OV5640_GMTRX30 0x5812U
+#define OV5640_GMTRX31 0x5813U
+#define OV5640_GMTRX32 0x5814U
+#define OV5640_GMTRX33 0x5815U
+#define OV5640_GMTRX34 0x5816U
+#define OV5640_GMTRX35 0x5817U
+#define OV5640_GMTRX40 0x5818U
+#define OV5640_GMTRX41 0x5819U
+#define OV5640_GMTRX42 0x581AU
+#define OV5640_GMTRX43 0x581BU
+#define OV5640_GMTRX44 0x581CU
+#define OV5640_GMTRX45 0x581DU
+#define OV5640_GMTRX50 0x581EU
+#define OV5640_GMTRX51 0x581FU
+#define OV5640_GMTRX52 0x5820U
+#define OV5640_GMTRX53 0x5821U
+#define OV5640_GMTRX54 0x5822U
+#define OV5640_GMTRX55 0x5823U
+#define OV5640_BRMATRX00 0x5824U
+#define OV5640_BRMATRX01 0x5825U
+#define OV5640_BRMATRX02 0x5826U
+#define OV5640_BRMATRX03 0x5827U
+#define OV5640_BRMATRX04 0x5828U
+#define OV5640_BRMATRX05 0x5829U
+#define OV5640_BRMATRX06 0x582AU
+#define OV5640_BRMATRX07 0x582BU
+#define OV5640_BRMATRX08 0x582CU
+#define OV5640_BRMATRX09 0x582DU
+#define OV5640_BRMATRX20 0x582EU
+#define OV5640_BRMATRX21 0x582FU
+#define OV5640_BRMATRX22 0x5830U
+#define OV5640_BRMATRX23 0x5831U
+#define OV5640_BRMATRX24 0x5832U
+#define OV5640_BRMATRX30 0x5833U
+#define OV5640_BRMATRX31 0x5834U
+#define OV5640_BRMATRX32 0x5835U
+#define OV5640_BRMATRX33 0x5836U
+#define OV5640_BRMATRX34 0x5837U
+#define OV5640_BRMATRX40 0x5838U
+#define OV5640_BRMATRX41 0x5839U
+#define OV5640_BRMATRX42 0x583AU
+#define OV5640_BRMATRX43 0x583BU
+#define OV5640_BRMATRX44 0x583CU
+#define OV5640_LENC_BR_OFFSET 0x583DU
+#define OV5640_MAX_GAIN 0x583EU
+#define OV5640_MIN_GAIN 0x583FU
+#define OV5640_MIN_Q 0x5840U
+#define OV5640_LENC_CTRL59 0x5841U
+#define OV5640_BR_HSCALE_HIGH 0x5842U
+#define OV5640_BR_HSCALE_LOW 0x5843U
+#define OV5640_BR_VSCALE_HIGH 0x5844U
+#define OV5640_BR_VSCALE_LOW 0x5845U
+#define OV5640_G_HSCALE_HIGH 0x5846U
+#define OV5640_G_HSCALE_LOW 0x5847U
+#define OV5640_G_VSCALE_HIGH 0x5848U
+#define OV5640_G_VSCALE_LOW 0x5849U
+
+/* AFC control [0x6000 ~ 0x603F] */
+#define OV5640_AFC_CTRL00 0x6000U
+#define OV5640_AFC_CTRL01 0x6001U
+#define OV5640_AFC_CTRL02 0x6002U
+#define OV5640_AFC_CTRL03 0x6003U
+#define OV5640_AFC_CTRL04 0x6004U
+#define OV5640_AFC_CTRL05 0x6005U
+#define OV5640_AFC_CTRL06 0x6006U
+#define OV5640_AFC_CTRL07 0x6007U
+#define OV5640_AFC_CTRL08 0x6008U
+#define OV5640_AFC_CTRL09 0x6009U
+#define OV5640_AFC_CTRL10 0x600AU
+#define OV5640_AFC_CTRL11 0x600BU
+#define OV5640_AFC_CTRL12 0x600CU
+#define OV5640_AFC_CTRL13 0x600DU
+#define OV5640_AFC_CTRL14 0x600EU
+#define OV5640_AFC_CTRL15 0x600FU
+#define OV5640_AFC_CTRL16 0x6010U
+#define OV5640_AFC_CTRL17 0x6011U
+#define OV5640_AFC_CTRL18 0x6012U
+#define OV5640_AFC_CTRL19 0x6013U
+#define OV5640_AFC_CTRL20 0x6014U
+#define OV5640_AFC_CTRL21 0x6015U
+#define OV5640_AFC_CTRL22 0x6016U
+#define OV5640_AFC_CTRL23 0x6017U
+#define OV5640_AFC_CTRL24 0x6018U
+#define OV5640_AFC_CTRL25 0x6019U
+#define OV5640_AFC_CTRL26 0x601AU
+#define OV5640_AFC_CTRL27 0x601BU
+#define OV5640_AFC_CTRL28 0x601CU
+#define OV5640_AFC_CTRL29 0x601DU
+#define OV5640_AFC_CTRL30 0x601EU
+#define OV5640_AFC_CTRL31 0x601FU
+#define OV5640_AFC_CTRL32 0x6020U
+#define OV5640_AFC_CTRL33 0x6021U
+#define OV5640_AFC_CTRL34 0x6022U
+#define OV5640_AFC_CTRL35 0x6023U
+#define OV5640_AFC_CTRL36 0x6024U
+#define OV5640_AFC_CTRL37 0x6025U
+#define OV5640_AFC_CTRL38 0x6026U
+#define OV5640_AFC_CTRL39 0x6027U
+#define OV5640_AFC_CTRL40 0x6028U
+#define OV5640_AFC_CTRL41 0x6029U
+#define OV5640_AFC_CTRL42 0x602AU
+#define OV5640_AFC_CTRL43 0x602BU
+#define OV5640_AFC_CTRL44 0x602CU
+#define OV5640_AFC_CTRL45 0x602DU
+#define OV5640_AFC_CTRL46 0x602EU
+#define OV5640_AFC_CTRL47 0x602FU
+#define OV5640_AFC_CTRL48 0x6030U
+#define OV5640_AFC_CTRL49 0x6031U
+#define OV5640_AFC_CTRL50 0x6032U
+#define OV5640_AFC_CTRL51 0x6033U
+#define OV5640_AFC_CTRL52 0x6034U
+#define OV5640_AFC_CTRL53 0x6035U
+#define OV5640_AFC_CTRL54 0x6036U
+#define OV5640_AFC_CTRL55 0x6037U
+#define OV5640_AFC_CTRL56 0x6038U
+#define OV5640_AFC_CTRL57 0x6039U
+#define OV5640_AFC_CTRL58 0x603AU
+#define OV5640_AFC_CTRL59 0x603BU
+#define OV5640_AFC_CTRL60 0x603CU
+#define OV5640_AFC_READ58 0x603DU
+#define OV5640_AFC_READ59 0x603EU
+#define OV5640_AFC_READ60 0x603FU
+
+/**
+ * @}
+ */
+
+/************** Generic Function *******************/
+
+typedef int32_t (*OV5640_Write_Func)(void *, uint16_t, uint8_t *, uint16_t);
+typedef int32_t (*OV5640_Read_Func)(void *, uint16_t, uint8_t *, uint16_t);
+
+typedef struct
+{
+ OV5640_Write_Func WriteReg;
+ OV5640_Read_Func ReadReg;
+ void *handle;
+} ov5640_ctx_t;
+
+/*******************************************************************************
+ * Register : Generic - All
+ * Address : Generic - All
+ * Bit Group Name: None
+ * Permission : W
+ *******************************************************************************/
+int32_t ov5640_write_reg(ov5640_ctx_t *ctx, uint16_t reg, uint8_t *pdata, uint16_t length);
+int32_t ov5640_read_reg(ov5640_ctx_t *ctx, uint16_t reg, uint8_t *pdata, uint16_t length);
+
+int32_t ov5640_register_set(ov5640_ctx_t *ctx, uint16_t reg, uint8_t value);
+int32_t ov5640_register_get(ov5640_ctx_t *ctx, uint16_t reg, uint8_t *value);
+
+
+/**
+ * @}
+ */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* OV5640_REG_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/stm32wb_at/License.md b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/stm32wb_at/License.md
new file mode 100644
index 00000000..9226612a
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/stm32wb_at/License.md
@@ -0,0 +1,27 @@
+Copyright 2021 STMicroelectronics.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice,
+this list of conditions and the following disclaimer in the documentation and/or
+other materials provided with the distribution.
+
+3. Neither the name of the copyright holder nor the names of its contributors
+may be used to endorse or promote products derived from this software without
+specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/stm32wb_at/stm32wb_at.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/stm32wb_at/stm32wb_at.c
new file mode 100644
index 00000000..c8ec76ac
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/stm32wb_at/stm32wb_at.c
@@ -0,0 +1,148 @@
+/**
+ ******************************************************************************
+ * @file stm32wb_at.c
+ * @author MCD Application Team
+ * @brief Transport layer.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wb_at.h"
+#include "stm32wb_at_ll.h"
+#include "stm32wb_at_client.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+uint8_t *buffer_rx;
+uint8_t buffer_rx_size;
+uint8_t buffer_rx_cursor;
+char str_received[64];
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+
+/**
+ * @brief Init the at module
+ * @param None
+ * @retval 0 in case of success, an error code otherwise
+ */
+uint8_t stm32wb_at_Init(uint8_t *buff_rx, uint8_t buff_rx_size)
+{
+ uint8_t status;
+
+ if(buff_rx_size >= sizeof(str_received))
+ {
+ buffer_rx_size = buff_rx_size;
+ buffer_rx = buff_rx;
+ (void)memset(&buffer_rx[0], 0, buffer_rx_size);
+ buffer_rx_cursor = 0;
+ (void)memset(&str_received[0], 0, sizeof(str_received));
+
+ stm32wb_at_ll_Async_receive(0);
+ status = 0;
+ }
+ else
+ {
+ status = 1;
+ }
+ return status;
+}
+
+/**
+ * @brief Accumulate bytes received and detects a new frame received
+ * @param byte the last byte received
+ * @retval 0 in case of success, an error code otherwise
+ */
+uint8_t stm32wb_at_Received(uint8_t byte)
+{
+ uint8_t status, i;
+
+ if(buffer_rx_cursor < buffer_rx_size)
+ {
+ buffer_rx[buffer_rx_cursor] = byte;
+ buffer_rx_cursor++;
+
+ /* check if we have received the command delimiter LF */
+ if(byte == (uint8_t)'\n')
+ {
+ if(buffer_rx_cursor > 2U){
+ /* remove CR if any */
+ if( buffer_rx[buffer_rx_cursor - 2U] == (uint8_t)'\r')
+ {
+ buffer_rx[buffer_rx_cursor - 1U] = 0U;
+ buffer_rx[buffer_rx_cursor - 2U] = (uint8_t)'\n';
+ buffer_rx_cursor--;
+ }
+ /* remove the last \n */
+ buffer_rx[buffer_rx_cursor - 1U] = 0U;
+ buffer_rx_cursor--;
+
+ if( buffer_rx[0] == 0U)
+ {
+ i = 1U;
+ while(buffer_rx[i] != 0U)
+ {
+ buffer_rx[i - 1U] = buffer_rx[i];
+ i++;
+ }
+ buffer_rx[i - 1U] = 0U;
+ }
+ }
+
+ /* check if command is long enough */
+ if(buffer_rx_cursor > 1U)
+ {
+ (void)strcpy(&str_received[0], (char*)&buffer_rx[0]);
+
+ stm32wb_at_ll_Async_receive((uint8_t)sizeof(str_received));
+
+ (void)memset(&buffer_rx[0], 0, buffer_rx_size);
+ buffer_rx_cursor = 0U;
+
+ status = stm32wb_at_Process_rx_frame(str_received);
+ (void)memset(&str_received[0], 0, sizeof(str_received));
+ }
+ else
+ {
+ (void)memset(&buffer_rx[0], 0, buffer_rx_size);
+ buffer_rx_cursor = 0U;
+ }
+ }
+ else
+ {
+ stm32wb_at_ll_Async_receive(0);
+ }
+ status = 0U;
+ }
+ else
+ {
+ status = 1U;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Process a frame received
+ * @param str pointer string to process
+ * @retval 0 in case of success, an error code otherwise
+ */
+__weak uint8_t stm32wb_at_Process_rx_frame(char * str)
+{
+ (void)stm32wb_at_client_Process_rx_frame(str);
+
+ return 0;
+}
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/stm32wb_at/stm32wb_at.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/stm32wb_at/stm32wb_at.h
new file mode 100644
index 00000000..3966e121
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/stm32wb_at/stm32wb_at.h
@@ -0,0 +1,66 @@
+/**
+ ******************************************************************************
+ * @file stm32wb_at.h
+ * @author MCD Application Team
+ * @brief Header file of AT transport layer.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32WB_AT_H
+#define STM32WB_AT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include
+#include
+#include
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+#define AT_PRE_CMD "AT+"
+#define AT_CMD_TEST "AT"
+
+#define AT_GET "?"
+#define AT_SET "="
+#define AT_READ ":"
+#define AT_REPLY "+"
+#define AT_EVENT "<"
+#define AT_SEPARATOR ","
+#define AT_EOL "\r\n"
+
+#define AT_CMD_STATUS_OK "OK"
+#define AT_CMD_STATUS_ERROR "ERROR"
+
+/* Exported macros -----------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+uint8_t stm32wb_at_Init(uint8_t *buff_rx, uint8_t buff_rx_size);
+uint8_t stm32wb_at_Received(uint8_t byte);
+uint8_t stm32wb_at_Process_rx_frame(char * str);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32WB_AT_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/stm32wb_at/stm32wb_at_ble.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/stm32wb_at/stm32wb_at_ble.c
new file mode 100644
index 00000000..7ae505d5
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/stm32wb_at/stm32wb_at_ble.c
@@ -0,0 +1,39 @@
+/**
+ ******************************************************************************
+ * @file stm32wb_at_ble.c
+ * @author MCD Application Team
+ * @brief AT BLE commands
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wb_at_ble.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported variable ---------------------------------------------------------*/
+const char *AT_BLE_CMD_STRING[] = {
+ FOREACH_AT_BLE_CMD(GENERATE_STRING)
+};
+
+const char *AT_BLE_EVT_STRING[] = {
+ FOREACH_AT_BLE_EVT(GENERATE_STRING)
+};
+
+/* Exported functions --------------------------------------------------------*/
+FOREACH_AT_BLE_CMD(GENERATE_AT_BLE_CB_FUNC)
+FOREACH_AT_BLE_EVT(GENERATE_AT_BLE_EVT_CB_FUNC)
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/stm32wb_at/stm32wb_at_ble.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/stm32wb_at/stm32wb_at_ble.h
new file mode 100644
index 00000000..8ff60df8
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/stm32wb_at/stm32wb_at_ble.h
@@ -0,0 +1,129 @@
+/**
+ ******************************************************************************
+ * @file stm32wb_at_ble.h
+ * @author MCD Application Team
+ * @brief Header file of AT BLE commands.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32WB_AT_BLE_H
+#define STM32WB_AT_BLE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wb_at.h"
+
+/* Private includes ----------------------------------------------------------*/
+#define FOREACH_AT_BLE_CMD(AT_BLE_CMD)\
+ AT_BLE_CMD(BLE_TEST)\
+ AT_BLE_CMD(BLE_SVC)\
+ AT_BLE_CMD(BLE_NOTIF_VAL)\
+ AT_BLE_CMD(BLE_CONN_INT)\
+ AT_BLE_CMD(BLE_NONE)\
+
+#define GENERATE_ENUM(ENUM) ENUM,
+#define GENERATE_STRING(STRING) #STRING,
+#define GENERATE_AT_BLE_CB_PROTO(CMD) uint8_t stm32wb_at_##CMD##_cb(stm32wb_at_##CMD##_t *param);
+#define GENERATE_AT_BLE_CB_FUNC(CMD) __weak uint8_t stm32wb_at_##CMD##_cb(stm32wb_at_##CMD##_t *param){UNUSED(param);return 1;}
+#define GENERATE_AT_BLE_SERVER_CB_PROTO(CMD) uint8_t stm32wb_at_##CMD##_server_cb(char *buff);
+#define GENERATE_AT_BLE_SERVER_CB_FUNC(CMD) __weak uint8_t stm32wb_at_##CMD##_server_cb(char *buff){return 1;}
+
+#define FOREACH_AT_BLE_EVT(AT_BLE_EVT)\
+ AT_BLE_EVT(BLE_EVT_WRITE)\
+ AT_BLE_EVT(BLE_EVT_CONN)\
+ AT_BLE_EVT(BLE_EVT_NONE)\
+
+#define GENERATE_AT_BLE_EVT_CB_PROTO(CMD) uint8_t stm32wb_at_##CMD##_cb(stm32wb_at_##CMD##_t *param);
+#define GENERATE_AT_BLE_EVT_CB_FUNC(CMD) __weak uint8_t stm32wb_at_##CMD##_cb(stm32wb_at_##CMD##_t *param){UNUSED(param);return 1;}
+
+/* Exported types ------------------------------------------------------------*/
+/* BLE_TEST */
+typedef struct
+{
+ uint8_t dummy;
+} stm32wb_at_BLE_TEST_t;
+
+/* BLE_SVC */
+typedef struct
+{
+ uint8_t index;
+} stm32wb_at_BLE_SVC_t;
+
+/* BLE_NOTIF_VAL */
+typedef struct
+{
+ uint8_t svc_index;
+ uint8_t char_index;
+ uint16_t value;
+} stm32wb_at_BLE_NOTIF_VAL_t;
+
+/* BLE_CONN_INT */
+typedef struct
+{
+ uint16_t min;
+ uint16_t max;
+} stm32wb_at_BLE_CONN_INT_t;
+
+/* BLE_NONE */
+typedef struct
+{
+ uint8_t dummy;
+} stm32wb_at_BLE_NONE_t;
+
+/* BLE_EVT_WRITE */
+typedef struct
+{
+ uint8_t svc_index;
+ uint8_t char_index;
+ uint32_t value;
+} stm32wb_at_BLE_EVT_WRITE_t;
+
+/* BLE_EVT_CONN */
+typedef struct
+{
+ uint8_t status;
+} stm32wb_at_BLE_EVT_CONN_t;
+
+/* BLE_EVT_NONE */
+typedef struct
+{
+ uint8_t dummy;
+} stm32wb_at_BLE_EVT_NONE_t;
+
+/* Exported constants --------------------------------------------------------*/
+typedef enum AT_BLE_CMD_ENUM {
+ FOREACH_AT_BLE_CMD(GENERATE_ENUM)
+}stm32wb_at_BLE_CMD_t;
+
+typedef enum AT_BLE_EVT_ENUM {
+ FOREACH_AT_BLE_EVT(GENERATE_ENUM)
+}stm32wb_at_BLE_EVT_t;
+
+extern const char* AT_BLE_CMD_STRING[];
+extern const char* AT_BLE_EVT_STRING[];
+
+/* Exported macros -----------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+FOREACH_AT_BLE_CMD(GENERATE_AT_BLE_CB_PROTO)
+FOREACH_AT_BLE_EVT(GENERATE_AT_BLE_EVT_CB_PROTO)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32WB_AT_BLE_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/stm32wb_at/stm32wb_at_client.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/stm32wb_at/stm32wb_at_client.c
new file mode 100644
index 00000000..6558bd59
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/stm32wb_at/stm32wb_at_client.c
@@ -0,0 +1,307 @@
+/**
+ ******************************************************************************
+ * @file stm32wb_at_client.c
+ * @author MCD Application Team
+ * @brief AT client.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wb_at_client.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+static char client_buff_tx[64];
+static stm32wb_at_BLE_CMD_t client_current_cmd;
+
+/* Private function prototypes -----------------------------------------------*/
+static uint8_t stm32wb_at_client_Wait_ready(void);
+
+/* Exported functions --------------------------------------------------------*/
+
+/**
+ * @brief Init the at client
+ * @param None
+ * @retval 0 in case of success, an error code otherwise
+ */
+uint8_t stm32wb_at_client_Init(void)
+{
+ (void)memset(&client_buff_tx[0], 0, sizeof(client_buff_tx));
+ client_current_cmd = BLE_NONE;
+
+ return 0;
+}
+
+/**
+ * @brief Query the server on a specified command
+ * @param cmd code to query
+ * @retval 0 in case of success, an error code otherwise
+ */
+uint8_t stm32wb_at_client_Query(stm32wb_at_BLE_CMD_t cmd)
+{
+ uint8_t status;
+
+ (void)stm32wb_at_client_Wait_ready();
+
+ if(cmd == BLE_TEST)
+ {
+ (void)strcpy(client_buff_tx, AT_CMD_TEST);
+ (void)strcat(client_buff_tx, AT_EOL);
+
+ client_current_cmd = cmd;
+ status = stm32wb_at_ll_Transmit((uint8_t *)&client_buff_tx[0], (uint16_t)strlen(client_buff_tx));
+ (void)memset(&client_buff_tx[0], 0, sizeof(client_buff_tx));
+ }
+ else if(cmd < BLE_NONE)
+ {
+ (void)strcpy(client_buff_tx, AT_PRE_CMD);
+ (void)strcat(client_buff_tx, AT_BLE_CMD_STRING[cmd]);
+ (void)strcat(client_buff_tx, AT_GET);
+ (void)strcat(client_buff_tx, AT_EOL);
+
+ client_current_cmd = cmd;
+ status = stm32wb_at_ll_Transmit((uint8_t *)&client_buff_tx[0], (uint16_t)strlen(client_buff_tx));
+ (void)memset(&client_buff_tx[0], 0, sizeof(client_buff_tx));
+ }
+ else
+ {
+ status = 1;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Process an At string and perform required actions
+ * @param str pointer to the string to process
+ * @retval 0 in case of success, an error code otherwise
+ */
+uint8_t stm32wb_at_client_Process_rx_frame(char * str)
+{
+ uint8_t status;
+ stm32wb_at_BLE_EVT_t current_evt;
+
+ status = 1;
+
+ if( strcmp(str, AT_CMD_STATUS_OK) == 0)
+ {
+ client_current_cmd = BLE_NONE;
+ status = 0;
+ }
+ else if( strcmp(str, AT_CMD_STATUS_ERROR) == 0)
+ {
+ client_current_cmd = BLE_NONE;
+ status = 0;
+ }
+ else if( strncmp(str, AT_REPLY, strlen(AT_REPLY)) == 0)
+ {
+ str++;
+ /* check if it's a response of current command */
+ if( strncmp(str, AT_BLE_CMD_STRING[client_current_cmd], strlen(AT_BLE_CMD_STRING[client_current_cmd])) == 0 )
+ {
+ str += strlen(AT_BLE_CMD_STRING[client_current_cmd]);
+
+ if( strncmp(str, AT_READ, strlen(AT_READ)) == 0)
+ {
+ str++;
+ /* extract params regarding current command */
+ switch (client_current_cmd) {
+ case BLE_SVC:
+ {
+ stm32wb_at_BLE_SVC_t param;
+ param.index = (uint8_t)strtol(str, NULL, 10);
+ status = stm32wb_at_BLE_SVC_cb(¶m);
+ break;
+ }
+ case BLE_CONN_INT:
+ {
+ stm32wb_at_BLE_CONN_INT_t param;
+ char * token;
+
+ token = strtok(str, AT_SEPARATOR);
+ param.min = (uint8_t)strtol(token, NULL, 10);
+
+ token = strtok(NULL, AT_SEPARATOR);
+ param.max = (uint8_t)strtol(token, NULL, 10);
+
+ status = stm32wb_at_BLE_CONN_INT_cb(¶m);
+ break;
+ }
+ default:
+ break;
+ }
+ }
+ }
+ }
+ else if( strncmp(str, AT_EVENT, strlen(AT_EVENT)) == 0)
+ {
+ str++;
+
+ for( current_evt = (stm32wb_at_BLE_EVT_t)0 ; current_evt < BLE_EVT_NONE ; current_evt++ )
+ {
+ if( strncmp(str, AT_BLE_EVT_STRING[current_evt], strlen(AT_BLE_EVT_STRING[current_evt])) == 0 )
+ {
+ str += strlen(AT_BLE_EVT_STRING[current_evt]);
+ break;
+ }
+ }
+ if( current_evt == BLE_EVT_NONE)
+ {
+ status = 1;
+ }
+ else
+ {
+ if (strncmp(str, AT_SET, strlen(AT_SET)) == 0)
+ {
+ str++;
+ /* extract params regarding current command */
+ switch (current_evt) {
+ case BLE_EVT_WRITE:
+ {
+ stm32wb_at_BLE_EVT_WRITE_t param;
+ char * token;
+
+ token = strtok(str, AT_SEPARATOR);
+ param.svc_index = (uint8_t)strtol(token, NULL, 10);
+
+ token = strtok(NULL, AT_SEPARATOR);
+ param.char_index = (uint8_t)strtol(token, NULL, 10);
+
+ token = strtok(NULL, AT_SEPARATOR);
+ param.value = (uint8_t)strtol(token, NULL, 10);
+
+ status = stm32wb_at_BLE_EVT_WRITE_cb(¶m);
+ break;
+ }
+ case BLE_EVT_CONN:
+ {
+ stm32wb_at_BLE_EVT_CONN_t param;
+ char * token;
+
+ token = strtok(str, AT_SEPARATOR);
+ param.status = (uint8_t)strtol(token, NULL, 10);
+
+ status = stm32wb_at_BLE_EVT_CONN_cb(¶m);
+ break;
+ }
+ default:
+ break;
+ }
+ }
+ else
+ {
+ status = 1;
+ }
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Send an AT set with specified command and parameters
+ * @param cmd command code
+ * @param param pointer to parameters of command
+ * @retval 0 in case of success, an error code otherwise
+ */
+uint8_t stm32wb_at_client_Set(stm32wb_at_BLE_CMD_t cmd, void *param)
+{
+ uint8_t status;
+
+ (void)stm32wb_at_client_Wait_ready();
+
+ if(cmd < BLE_NONE)
+ {
+ client_current_cmd = cmd;
+
+ (void)strcpy(client_buff_tx, AT_PRE_CMD);
+ (void)strcat(client_buff_tx, AT_BLE_CMD_STRING[cmd]);
+ (void)strcat(client_buff_tx, AT_SET);
+
+ switch (cmd) {
+ case BLE_SVC:
+ {
+ stm32wb_at_BLE_SVC_t *p = param;
+ char str_tmp[8];
+
+ (void)sprintf(str_tmp, "%d", p->index);
+ (void)strcat(client_buff_tx, str_tmp);
+
+ break;
+ }
+ case BLE_NOTIF_VAL:
+ {
+ stm32wb_at_BLE_NOTIF_VAL_t *p = param;
+ char str_tmp[8];
+
+ (void)sprintf(str_tmp, "%d", p->svc_index);
+ (void)strcat(client_buff_tx, str_tmp);
+ (void)strcat(client_buff_tx, AT_SEPARATOR);
+
+ (void)sprintf(str_tmp, "%d", p->char_index);
+ (void)strcat(client_buff_tx, str_tmp);
+ (void)strcat(client_buff_tx, AT_SEPARATOR);
+
+ (void)sprintf(str_tmp, "%d", p->value);
+ (void)strcat(client_buff_tx, str_tmp);
+
+ break;
+ }
+ case BLE_CONN_INT:
+ {
+ stm32wb_at_BLE_CONN_INT_t *p = param;
+ char str_tmp[8];
+
+ (void)sprintf(str_tmp, "%d", p->min);
+ (void)strcat(client_buff_tx, str_tmp);
+ (void)strcat(client_buff_tx, AT_SEPARATOR);
+
+ (void)sprintf(str_tmp, "%d", p->max);
+ (void)strcat(client_buff_tx, str_tmp);
+
+ break;
+ }
+ default:
+ break;
+ }
+
+ (void)strcat(client_buff_tx, AT_EOL);
+
+ client_current_cmd = cmd;
+ status = stm32wb_at_ll_Transmit((uint8_t *)&client_buff_tx[0], (uint16_t)strlen(client_buff_tx));
+ (void)memset(&client_buff_tx[0], 0, sizeof(client_buff_tx));
+ }
+ else
+ {
+ status = 1;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Wait for the last AT command completed
+ * @param None
+ * @retval 0 in case of success, an error code otherwise
+ */
+static uint8_t stm32wb_at_client_Wait_ready(void)
+{
+ while (client_current_cmd != BLE_NONE)
+ {
+ }
+
+ return 0;
+}
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/stm32wb_at/stm32wb_at_client.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/stm32wb_at/stm32wb_at_client.h
new file mode 100644
index 00000000..06af95db
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/stm32wb_at/stm32wb_at_client.h
@@ -0,0 +1,50 @@
+/**
+ ******************************************************************************
+ * @file stm32wb_at_client.h
+ * @author MCD Application Team
+ * @brief Header file of AT client.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32WB_AT_CLIENT_H
+#define STM32WB_AT_CLIENT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wb_at.h"
+#include "stm32wb_at_ll.h"
+#include "stm32wb_at_ble.h"
+
+/* Private includes ----------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+
+/* Exported macros -----------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+uint8_t stm32wb_at_client_Init(void);
+uint8_t stm32wb_at_client_Query(stm32wb_at_BLE_CMD_t cmd);
+uint8_t stm32wb_at_client_Process_rx_frame(char * str);
+uint8_t stm32wb_at_client_Set(stm32wb_at_BLE_CMD_t cmd, void *param);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32WB_AT_CLIENT_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/stm32wb_at/stm32wb_at_ll.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/stm32wb_at/stm32wb_at_ll.c
new file mode 100644
index 00000000..5f74dd4a
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/stm32wb_at/stm32wb_at_ll.c
@@ -0,0 +1,73 @@
+/**
+ ******************************************************************************
+ * @file stm32wb_at_ll.c
+ * @author MCD Application Team
+ * @brief Transport layer interface file, user have to implement these
+ * functions in his application.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wb_at.h"
+#include "stm32wb_at_ll.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/**
+ * @brief Init the transport module
+ * @param None
+ * @retval 0 in case of success, an error code otherwise
+ */
+__weak uint8_t stm32wb_at_ll_Init(void)
+{
+ return 1;
+}
+
+/**
+ * @brief De init the transport module
+ * @param None
+ * @retval 0 in case of success, an error code otherwise
+ */
+__weak uint8_t stm32wb_at_ll_DeInit(void)
+{
+ return 1;
+}
+
+/**
+ * @brief Triggers the reception of a byte
+ * @param pBuff pointer to the first byte to transmit
+ * @param Size byte count to transfer
+ * @retval 0 in case of success, an error code otherwise
+ */
+__weak uint8_t stm32wb_at_ll_Transmit(uint8_t *pBuff, uint16_t Size)
+{
+ UNUSED(pBuff);
+ UNUSED(Size);
+
+ return 1;
+}
+
+/**
+ * @brief Triggers the reception of a byte
+ * @param new_frame containts the length of a new frame received in rx buffer, else 0
+ * @retval None
+ */
+__weak void stm32wb_at_ll_Async_receive(uint8_t new_frame)
+{
+ UNUSED(new_frame);
+ return;
+}
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/stm32wb_at/stm32wb_at_ll.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/stm32wb_at/stm32wb_at_ll.h
new file mode 100644
index 00000000..52265731
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/stm32wb_at/stm32wb_at_ll.h
@@ -0,0 +1,49 @@
+/**
+ ******************************************************************************
+ * @file stm32wb_at_ll.h
+ * @author MCD Application Team
+ * @brief Header file of AT client.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32WB_AT_LL_H
+#define STM32WB_AT_LL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wb_at.h"
+#include "stm32wb_at_ll.h"
+
+/* Private includes ----------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+
+/* Exported macros -----------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+uint8_t stm32wb_at_ll_Init(void);
+uint8_t stm32wb_at_ll_DeInit(void);
+uint8_t stm32wb_at_ll_Transmit(uint8_t *pBuff, uint16_t Size);
+void stm32wb_at_ll_Async_receive(uint8_t new_frame);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32WB_AT_LL_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/sx8651/LICENSE.md b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/sx8651/LICENSE.md
new file mode 100644
index 00000000..9226612a
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/sx8651/LICENSE.md
@@ -0,0 +1,27 @@
+Copyright 2021 STMicroelectronics.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice,
+this list of conditions and the following disclaimer in the documentation and/or
+other materials provided with the distribution.
+
+3. Neither the name of the copyright holder nor the names of its contributors
+may be used to endorse or promote products derived from this software without
+specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/sx8651/sx8651.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/sx8651/sx8651.c
new file mode 100644
index 00000000..8ae0ac3d
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/sx8651/sx8651.c
@@ -0,0 +1,555 @@
+/**
+ ******************************************************************************
+ * @file sx8651.c
+ * @author MCD Application Team
+ * @brief This file provides a set of functions needed to manage the SX8651
+ * Touch screen device.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved. © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
+#include "sx8651_conf.h"
+
+/* Macros --------------------------------------------------------------------*/
+
+/** @addtogroup BSP
+ * @{
+ */
+
+/** @addtogroup Component
+ * @{
+ */
+
+/** @addtogroup SX8651
+ * @{
+ */
+
+/** @defgroup SX8651_Exported_Constants SX8651 Exported Constants
+ * @{
+ */
+#define SX8651_OK (0)
+#define SX8651_ERROR (-1)
+
+/* Max detectable simultaneous touches */
+#define SX8651_MAX_NB_TOUCH 2U
+
+/* Software reset value of SX8651_SOFTRESET_REG */
+#define SX8651_SOFTRESET_VALUE 0xDEU
+
+/* Psedo Chip IDs, @I2CRegChanMsk */
+#define SX8651_ID 0xC0
+
+/* Psedo Identification register */
+#define SX8651_REG_CHP_ID 0x08
+
+/* Global interrupt Enable bit */
+#define SX8651_GIT_EN 0x01
+
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup SX8651_Exported_Types SX8651 Exported Types
+ * @{
+ */
+typedef struct
+{
+ uint32_t Radian;
+ uint32_t OffsetLeftRight;
+ uint32_t OffsetUpDown;
+ uint32_t DistanceLeftRight;
+ uint32_t DistanceUpDown;
+ uint32_t DistanceZoom;
+} SX8651_Gesture_Init_t;
+
+typedef int32_t (*SX8651_Init_Func)(void);
+typedef int32_t (*SX8651_DeInit_Func)(void);
+typedef int32_t (*SX8651_GetTick_Func)(void);
+typedef int32_t (*SX8651_Delay_Func)(uint32_t);
+typedef int32_t (*SX8651_WriteReg_Func)(uint16_t, uint16_t, uint8_t *, uint16_t);
+typedef int32_t (*SX8651_ReadReg_Func)(uint16_t, uint16_t, uint8_t *, uint16_t);
+typedef int32_t (*SX8651_ReadData_Func)(uint16_t, uint8_t *, uint16_t);
+typedef int32_t (*SX8651_WriteData_Func)(uint16_t, uint8_t *, uint16_t);
+
+typedef struct
+{
+ SX8651_Init_Func Init;
+ SX8651_DeInit_Func DeInit;
+ uint16_t Address;
+ SX8651_WriteReg_Func WriteReg;
+ SX8651_ReadReg_Func ReadReg;
+ SX8651_ReadData_Func ReadData;
+ SX8651_WriteData_Func WriteCmd;
+ SX8651_GetTick_Func GetTick;
+} SX8651_IO_t;
+
+typedef struct
+{
+ uint32_t TouchDetected;
+ uint32_t TouchX;
+ uint32_t TouchY;
+} SX8651_State_t;
+
+typedef struct
+{
+ uint32_t TouchDetected;
+ uint32_t TouchX[SX8651_MAX_NB_TOUCH];
+ uint32_t TouchY[SX8651_MAX_NB_TOUCH];
+ uint32_t TouchWeight[SX8651_MAX_NB_TOUCH];
+ uint32_t TouchEvent[SX8651_MAX_NB_TOUCH];
+ uint32_t TouchArea[SX8651_MAX_NB_TOUCH];
+} SX8651_MultiTouch_State_t;
+
+typedef struct
+{
+ SX8651_IO_t IO;
+ sx8651_ctx_t Ctx;
+ uint8_t IsInitialized;
+} SX8651_Object_t;
+
+typedef struct
+{
+ uint8_t MultiTouch;
+ uint8_t Gesture;
+ uint8_t MaxTouch;
+ uint32_t MaxXl;
+ uint32_t MaxYl;
+} SX8651_Capabilities_t;
+
+typedef struct
+{
+ int32_t (*Init)(SX8651_Object_t *);
+ int32_t (*DeInit)(SX8651_Object_t *);
+ int32_t (*GestureConfig)(SX8651_Object_t *, SX8651_Gesture_Init_t *);
+ int32_t (*ReadID)(SX8651_Object_t *, uint32_t *);
+ int32_t (*GetState)(SX8651_Object_t *, SX8651_State_t *);
+ int32_t (*GetMultiTouchState)(SX8651_Object_t *, SX8651_MultiTouch_State_t *);
+ int32_t (*GetGesture)(SX8651_Object_t *, uint8_t *);
+ int32_t (*GetCapabilities)(SX8651_Object_t *, SX8651_Capabilities_t *);
+ int32_t (*EnableIT)(SX8651_Object_t *);
+ int32_t (*DisableIT)(SX8651_Object_t *);
+ int32_t (*ClearIT)(SX8651_Object_t *);
+ int32_t (*ITStatus)(SX8651_Object_t *);
+} SX8651_TS_Drv_t;
+/**
+ * @}
+ */
+
+/** @addtogroup SX8651_Exported_Variables
+ * @{
+ */
+extern SX8651_TS_Drv_t SX8651_TS_Driver;
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup SX8651_Exported_Functions
+ * @{
+ */
+
+int32_t SX8651_RegisterBusIO(SX8651_Object_t *pObj, SX8651_IO_t *pIO);
+int32_t SX8651_Init(SX8651_Object_t *pObj);
+int32_t SX8651_DeInit(SX8651_Object_t *pObj);
+int32_t SX8651_GestureConfig(SX8651_Object_t *pObj, SX8651_Gesture_Init_t *GestureInit);
+int32_t SX8651_ReadID(SX8651_Object_t *pObj, uint32_t *Id);
+int32_t SX8651_GetState(SX8651_Object_t *pObj, SX8651_State_t *State);
+int32_t SX8651_GetMultiTouchState(SX8651_Object_t *pObj, SX8651_MultiTouch_State_t *State);
+int32_t SX8651_GetGesture(SX8651_Object_t *pObj, uint8_t *GestureId);
+int32_t SX8651_EnableIT(SX8651_Object_t *pObj);
+int32_t SX8651_DisableIT(SX8651_Object_t *pObj);
+int32_t SX8651_ITStatus(SX8651_Object_t *pObj);
+int32_t SX8651_ClearIT(SX8651_Object_t *pObj);
+int32_t SX8651_GetCapabilities(SX8651_Object_t *pObj, SX8651_Capabilities_t *Capabilities);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* SX8651_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/sx8651/sx8651_conf_template.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/sx8651/sx8651_conf_template.h
new file mode 100644
index 00000000..b1266974
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/sx8651/sx8651_conf_template.h
@@ -0,0 +1,42 @@
+/**
+ ******************************************************************************
+ * @file sx8651_conf_template.h
+ * @author MCD Application Team
+ * @brief This file contains specific configuration for the
+ * sx8651.c that can be modified by user.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved. © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved. © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+/* Macros --------------------------------------------------------------------*/
+
+/** @addtogroup BSP
+ * @{
+ */
+
+/** @addtogroup Component
+ * @{
+ */
+
+/** @addtogroup SX8651
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup SX8651_Exported_Types SX8651 Exported Types
+ * @{
+ */
+/************** Generic Function *******************/
+
+typedef int32_t (*SX8651_Write_Func)(void *, uint8_t, uint8_t *, uint16_t);
+typedef int32_t (*SX8651_Read_Func)(void *, uint8_t, uint8_t *, uint16_t);
+typedef int32_t (*SX8651_ReadBuff_Func)(void *, uint8_t *, uint16_t);
+typedef int32_t (*SX8651_WriteCmd_Func)(void *, uint8_t *, uint16_t);
+
+/**
+ * @}
+ */
+
+/** @defgroup SX8651_Imported_Globals SX8651 Imported Globals
+ * @{
+ */
+typedef struct
+{
+ SX8651_Write_Func WriteReg;
+ SX8651_Read_Func ReadReg;
+ SX8651_ReadBuff_Func ReadData;
+ SX8651_WriteCmd_Func WriteCmd;
+ void *handle;
+} sx8651_ctx_t;
+/**
+ * @}
+ */
+
+/** @defgroup SX8651_Exported_Constants SX8651 Exported Constants
+ * @{
+ */
+
+/* Touch controller registers (W/R) */
+#define SX8651_CTRL_0_REG 0x00
+#define SX8651_CTRL_1_REG 0x01
+#define SX8651_CTRL_2_REG 0x02
+#define SX8651_CTRL_3_REG 0x03
+
+/* (W/R) */
+#define SX8651_CHANMSK_REG 0x04
+
+/* SX8651 status register (R)*/
+#define SX8651_STAT_REG 0x45
+
+/* Software Reset register (W) */
+#define SX8651_SOFTRESET_REG 0x1F
+
+/* MANAUTO mode */
+#define SX8651_MODE_MANAUTO 0xB0
+
+/* PENTRG mode */
+#define SX8651_MODE_PENTRG 0xE0
+
+#define SX8651_MODE_PENDET 0xC0
+
+
+#define SX8651_P1_XH_TP_BIT_MASK 0xFF
+#define SX8651_P1_XL_TP_BIT_MASK 0x0F
+#define SX8651_P1_YH_TP_BIT_MASK 0xFF
+#define SX8651_P1_YL_TP_BIT_MASK 0x0F
+
+
+/* Read Address OR value */
+#define SX8651_READ_ADDR 0x40
+
+/* command SELECT(CHAN) Address OR value */
+#define SX8651_CMD_SELECT 0x80
+
+/* command CONVERT(CHAN) Address OR value */
+#define SX8651_CMD_CONVERT 0x90
+
+/* command MANAUTO Address OR value */
+#define SX8651_CMD_MANAUTO 0xB0
+
+/* command PENDET Address OR value */
+#define SX8651_CMD_PENDET 0xC0
+
+/* command PENTRG Address OR value */
+#define SX8651_CMD_PENTRG 0xE0
+
+/* IO expander functionalities */
+
+/* Global Interrupts definitions */
+#define SX8651_CONVIRQ 0x80 /* End of conversion sequence interrupt */
+#define SX8651_PENIRQ 0x20 /* Pen detected interrupt */
+#define SX8651_ALL_GIT 0xA0 /* All global interrupts */
+#define SX8651_TS_IT (SX8651_CONVIRQ) /* Touch screen interrupts */
+
+/* General Control Registers */
+#define SX8651_REG_CTRL0 0x00
+#define SX8651_REG_CTRL1 0x01
+#define SX8651_REG_CTRL2 0x02
+#define SX8651_REG_CTRL3 0x03
+#define SX8651_REG_CHAN_MSK 0x04
+#define SX8651_REG_SOFT_RESET 0x1F
+
+/* Interrupt system Registers */
+#define SX8651_REG_STAT 0x05
+
+/* IO Pins definition */
+#define SX8651_PIN_0 0x01
+#define SX8651_PIN_1 0x02
+#define SX8651_PIN_2 0x04
+#define SX8651_PIN_3 0x08
+#define SX8651_PIN_4 0x10
+#define SX8651_PIN_5 0x20
+#define SX8651_PIN_6 0x40
+#define SX8651_PIN_7 0x80
+#define SX8651_PIN_ALL 0xFF
+
+/* TS registers masks */
+#define SX8651_TS_CTRL_ENABLE 0x01
+#define SX8651_TS_CTRL_STATUS 0x80
+
+/* REG_CTRL0 bits */
+#define REG_CTRL0_RATE_100CPS 0x60
+#define REG_CTRL0_RATE_300CPS 0x80
+#define REG_CTRL0_RATE_1KCPS 0xB0
+#define REG_CTRL0_POWDLY_36US 0x06
+#define REG_CTRL0_POWDLY_140US 0x08
+#define REG_CTRL0_POWDLY_1MS 0x0B
+
+/* REG_CTRL1 bits */
+#define REG_CTRL1_AUXAQC_ANA 0x00
+#define REG_CTRL1_AUXAQC_RISING 0x40
+#define REG_CTRL1_AUXAQC_FALLING 0x80
+#define REG_CTRL1_AUXAQC_BOTH 0xC0
+#define REG_CTRL1_CONDIRQ_ALWAYS 0x00
+#define REG_CTRL1_CONDIRQ_DETECTED 0x20
+#define REG_CTRL1_RPDNT_100KOHM 0x00
+#define REG_CTRL1_RPDNT_200KOHM 0x04
+#define REG_CTRL1_RPDNT_50KOHM 0x08
+#define REG_CTRL1_RPDNT_25KOHM 0x0C
+#define REG_CTRL1_FILT_DISABLE 0x00
+#define REG_CTRL1_FILT_3AVERAGE 0x01
+#define REG_CTRL1_FILT_5AVERAGE 0x02
+#define REG_CTRL1_FILT_7AVERAGE 0x03
+
+/* REG_CTRL2 bits */
+#define REG_CTRL2_SETDLY_36US 0x06
+#define REG_CTRL2_SETDLY_140US 0x08
+#define REG_CTRL2_SETDLY_1MS 0x0B
+
+/* REG_CTRL3 bits */
+#define REG_CTRL3_RM_SEL_Y_137OHM 0x00
+#define REG_CTRL3_RM_SEL_Y_242OHM 0x08
+#define REG_CTRL3_RM_SEL_Y_542OHM 0x10
+#define REG_CTRL3_RM_SEL_Y_1327OHM 0x18
+#define REG_CTRL3_RM_SEL_Y_2865OHM 0x20
+#define REG_CTRL3_RM_SEL_Y_6405OHM 0x28
+#define REG_CTRL3_RM_SEL_Y_13KOHM 0x30
+#define REG_CTRL3_RM_SEL_Y_40KOHM 0x38
+#define REG_CTRL3_RM_SEL_X_137OHM 0x00
+#define REG_CTRL3_RM_SEL_X_242OHM 0x01
+#define REG_CTRL3_RM_SEL_X_542OHM 0x02
+#define REG_CTRL3_RM_SEL_X_1327OHM 0x03
+#define REG_CTRL3_RM_SEL_X_2865OHM 0x04
+#define REG_CTRL3_RM_SEL_X_6405OHM 0x05
+#define REG_CTRL3_RM_SEL_X_13KOHM 0x06
+#define REG_CTRL3_RM_SEL_X_40KOHM 0x07
+
+/* REG_CHAN_MSK bits */
+#define REG_CHAN_MSK_XCONV 0x80
+#define REG_CHAN_MSK_YCONV 0x40
+#define REG_CHAN_MSK_Z1CONV 0x20
+#define REG_CHAN_MSK_Z2CONV 0x10
+#define REG_CHAN_MSK_AUXCONV 0x08
+#define REG_CHAN_MSK_RXCONV 0x04
+#define REG_CHAN_MSK_RYCONV 0x02
+
+/* REG_STAT bits */
+#define REG_STAT_CONVIRQ 0x80
+#define REG_STAT_PENIRQ 0x40
+
+/* Data Channel bits */
+#define DATA_CHANNEL_INVALID 0x8000
+#define DATA_CHANNEL_MASK 0x7000
+#define DATA_CHANNEL_MASK_X 0x0000
+#define DATA_CHANNEL_MASK_Y 0x1000
+#define DATA_CHANNEL_MASK_SEQ 0x7000
+#define DATA_CHANNEL_DATA 0x0FFF
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Register : Generic - All
+ * Address : Generic - All
+ * Bit Group Name: None
+ * Permission : W
+ *******************************************************************************/
+int32_t sx8651_write_reg(sx8651_ctx_t *ctx, uint8_t reg, uint8_t *pbuf, uint16_t length);
+int32_t sx8651_read_reg(sx8651_ctx_t *ctx, uint8_t reg, uint8_t *pbuf, uint16_t length);
+int32_t sx8651_read_data(sx8651_ctx_t *ctx, uint8_t *pdata, uint16_t length);
+int32_t sx8651_write_cmd(sx8651_ctx_t *ctx, uint8_t *pdata, uint16_t length);
+int32_t sx8651_read_chan(sx8651_ctx_t *ctx, uint8_t chan, uint8_t *pdata, uint16_t length);
+
+/**************** Base Function *******************/
+
+/*******************************************************************************
+ * Register : CTRL_0
+ * Address : 0X00
+ * Bit Group Name: Touch RATE
+ * Permission : RW
+ * Default value : 0x00U
+ *******************************************************************************/
+#define SX8651_CTRL_RATE_BIT_MASK 0xF0U
+#define SX8651_CTRL_RATE_BIT_POSITION 4
+int32_t sx8651_ctrl_rate_w(sx8651_ctx_t *ctx, uint8_t value);
+int32_t sx8651_ctrl_rate_r(sx8651_ctx_t *ctx, uint8_t *value);
+
+/*******************************************************************************
+ * Register : CTRL_0
+ * Address : 0X00
+ * Bit Group Name: Touch POWDLY
+ * Permission : RW
+ * Default value : 0x00U
+ *******************************************************************************/
+#define SX8651_CTRL_POWDLY_BIT_MASK 0x0FU
+#define SX8651_CTRL_POWDLY_BIT_POSITION 0
+int32_t sx8651_ctrl_powdly_w(sx8651_ctx_t *ctx, uint8_t value);
+int32_t sx8651_ctrl_powdly_r(sx8651_ctx_t *ctx, uint8_t *value);
+
+/*******************************************************************************
+ * Register : CTRL_1
+ * Address : 0X01
+ * Bit Group Name: Touch AUXAQC
+ * Permission : RW
+ * Default value : 0x0U
+ *******************************************************************************/
+#define SX8651_CTRL_AUXAQC_BIT_MASK 0xC0U
+#define SX8651_CTRL_AUXAQC_BIT_POSITION 6
+int32_t sx8651_ctrl_auxaqc_w(sx8651_ctx_t *ctx, uint8_t value);
+int32_t sx8651_ctrl_auxaqc_r(sx8651_ctx_t *ctx, uint8_t *value);
+
+/*******************************************************************************
+ * Register : CTRL_1
+ * Address : 0X01
+ * Bit Group Name: Touch CONDIRQ
+ * Permission : RW
+ * Default value : 0x1U
+ *******************************************************************************/
+#define SX8651_CTRL_CONDIRQ_BIT_MASK 0x20U
+#define SX8651_CTRL_CONDIRQ_BIT_POSITION 5
+int32_t sx8651_ctrl_condirq_w(sx8651_ctx_t *ctx, uint8_t value);
+int32_t sx8651_ctrl_condirq_r(sx8651_ctx_t *ctx, uint8_t *value);
+
+/*******************************************************************************
+ * Register : CTRL_1
+ * Address : 0X01
+ * Bit Group Name: Touch RPDNT
+ * Permission : RW
+ * Default value : 0x0U
+ *******************************************************************************/
+#define SX8651_CTRL_RPDNT_BIT_MASK 0x0CU
+#define SX8651_CTRL_RPDNT_BIT_POSITION 2
+int32_t sx8651_ctrl_rpdnt_w(sx8651_ctx_t *ctx, uint8_t value);
+int32_t sx8651_ctrl_rpdnt_r(sx8651_ctx_t *ctx, uint8_t *value);
+
+/*******************************************************************************
+ * Register : CTRL_1
+ * Address : 0X01
+ * Bit Group Name: Touch FILT
+ * Permission : RW
+ * Default value : 0x0U
+ *******************************************************************************/
+#define SX8651_CTRL_FILT_BIT_MASK 0x03U
+#define SX8651_CTRL_FILT_BIT_POSITION 0
+int32_t sx8651_ctrl_filt_w(sx8651_ctx_t *ctx, uint8_t value);
+int32_t sx8651_ctrl_filt_r(sx8651_ctx_t *ctx, uint8_t *value);
+
+/*******************************************************************************
+ * Register : CTRL_2
+ * Address : 0X02
+ * Bit Group Name: Touch SETDLY
+ * Permission : RW
+ * Default value : 0x0U
+ *******************************************************************************/
+#define SX8651_CTRL_SETDLY_BIT_MASK 0x0FU
+#define SX8651_CTRL_SETDLY_BIT_POSITION 0
+int32_t sx8651_ctrl_setdly_w(sx8651_ctx_t *ctx, uint8_t value);
+int32_t sx8651_ctrl_setdly_r(sx8651_ctx_t *ctx, uint8_t *value);
+
+/*******************************************************************************
+ * Register : CTRL_3
+ * Address : 0X03
+ * Bit Group Name: Touch RM_SEL_Y
+ * Permission : RW
+ *******************************************************************************/
+#define SX8651_CTRL_RMSEL_Y_BIT_MASK 0x38U
+#define SX8651_CTRL_RMSEL_Y_BIT_POSITION 3
+int32_t sx8651_ctrl_rmsel_y_w(sx8651_ctx_t *ctx, uint8_t value);
+int32_t sx8651_ctrl_rmsel_y_r(sx8651_ctx_t *ctx, uint8_t *value);
+
+/*******************************************************************************
+ * Register : CTRL_3
+ * Address : 0X03
+ * Bit Group Name: Touch RM_SEL_X
+ * Permission : RW
+ *******************************************************************************/
+#define SX8651_CTRL_RMSEL_X_BIT_MASK 0x07U
+#define SX8651_CTRL_RMSEL_X_BIT_POSITION 0
+int32_t sx8651_ctrl_rmsel_x_w(sx8651_ctx_t *ctx, uint8_t value);
+int32_t sx8651_ctrl_rmsel_x_r(sx8651_ctx_t *ctx, uint8_t *value);
+
+/*******************************************************************************
+ * Register : CHANMSK
+ * Address : 0X04
+ * Bit Group Name: Touch XCONV
+ * Permission : RW
+ * Default value : 0x1U
+ *******************************************************************************/
+#define SX8651_CTRL_XCONV_BIT_MASK 0x80U
+#define SX8651_CTRL_XCONV_BIT_POSITION 7
+int32_t sx8651_ctrl_xconv_w(sx8651_ctx_t *ctx, uint8_t value);
+int32_t sx8651_ctrl_xconv_r(sx8651_ctx_t *ctx, uint8_t *value);
+
+/*******************************************************************************
+ * Register : CHANMSK
+ * Address : 0X04
+ * Bit Group Name: Touch YCONV
+ * Permission : RW
+ * Default value : 0x1U
+ *******************************************************************************/
+#define SX8651_CTRL_YCONV_BIT_MASK 0x40U
+#define SX8651_CTRL_YCONV_BIT_POSITION 6
+int32_t sx8651_ctrl_yconv_w(sx8651_ctx_t *ctx, uint8_t value);
+int32_t sx8651_ctrl_yconv_r(sx8651_ctx_t *ctx, uint8_t *value);
+
+/*******************************************************************************
+ * Register : CHANMSK
+ * Address : 0X04
+ * Bit Group Name: Touch Z1CONV
+ * Permission : RW
+ * Default value : 0x0U
+ *******************************************************************************/
+#define SX8651_CTRL_Z1CONV_BIT_MASK 0x20U
+#define SX8651_CTRL_Z1CONV_BIT_POSITION 5
+int32_t sx8651_ctrl_z1conv_w(sx8651_ctx_t *ctx, uint8_t value);
+int32_t sx8651_ctrl_z1conv_r(sx8651_ctx_t *ctx, uint8_t *value);
+
+/*******************************************************************************
+ * Register : CHANMSK
+ * Address : 0X04
+ * Bit Group Name: Touch Z2CONV
+ * Permission : RW
+ * Default value : 0x0U
+ *******************************************************************************/
+#define SX8651_CTRL_Z2CONV_BIT_MASK 0x10U
+#define SX8651_CTRL_Z2CONV_BIT_POSITION 4
+int32_t sx8651_ctrl_z2conv_w(sx8651_ctx_t *ctx, uint8_t value);
+int32_t sx8651_ctrl_z2conv_r(sx8651_ctx_t *ctx, uint8_t *value);
+
+/*******************************************************************************
+ * Register : CHANMSK
+ * Address : 0X04
+ * Bit Group Name: Touch AUXCONV
+ * Permission : RW
+ * Default value : 0x0U
+ *******************************************************************************/
+#define SX8651_CTRL_AUXCONV_BIT_MASK 0x08U
+#define SX8651_CTRL_AUXCONV_BIT_POSITION 3
+int32_t sx8651_ctrl_auxconv_w(sx8651_ctx_t *ctx, uint8_t value);
+int32_t sx8651_ctrl_auxconv_r(sx8651_ctx_t *ctx, uint8_t *value);
+
+/*******************************************************************************
+ * Register : CHANMSK
+ * Address : 0X04
+ * Bit Group Name: Touch RXCONV
+ * Permission : RW
+ * Default value : 0x0U
+ *******************************************************************************/
+#define SX8651_CTRL_RXCONV_BIT_MASK 0x04U
+#define SX8651_CTRL_RXCONV_BIT_POSITION 2
+int32_t sx8651_ctrl_rxconv_w(sx8651_ctx_t *ctx, uint8_t value);
+int32_t sx8651_ctrl_rxconv_r(sx8651_ctx_t *ctx, uint8_t *value);
+
+/*******************************************************************************
+ * Register : CHANMSK
+ * Address : 0X04
+ * Bit Group Name: Touch RYCONV
+ * Permission : RW
+ * Default value : 0x0U
+ *******************************************************************************/
+#define SX8651_CTRL_RYCONV_BIT_MASK 0x02U
+#define SX8651_CTRL_RYCONV_BIT_POSITION 1
+int32_t sx8651_ctrl_ryconv_w(sx8651_ctx_t *ctx, uint8_t value);
+int32_t sx8651_ctrl_ryconv_r(sx8651_ctx_t *ctx, uint8_t *value);
+
+/*******************************************************************************
+ * Register : STAT
+ * Address : 0X05
+ * Bit Group Name: Touch CONVIRQ
+ * Permission : R
+ * Default value : 0x0U
+ *******************************************************************************/
+#define SX8651_CTRL_CONVIRQ_BIT_MASK 0x80U
+#define SX8651_CTRL_CONVIRQ_BIT_POSITION 7
+int32_t sx8651_ctrl_convirq(sx8651_ctx_t *ctx, uint8_t *value);
+
+/*******************************************************************************
+ * Register : STAT
+ * Address : 0X05
+ * Bit Group Name: Touch PENIRQ
+ * Permission : R
+ * Default value : 0x0U
+ *******************************************************************************/
+#define SX8651_CTRL_PENIRQ_BIT_MASK 0x40U
+#define SX8651_CTRL_PENIRQ_BIT_POSITION 6
+int32_t sx8651_ctrl_penirq(sx8651_ctx_t *ctx, uint8_t *value);
+
+/*******************************************************************************
+ * Register : SOFTRESET
+ * Address : 0X1F
+ * Bit Group Name: Touch SOFTRESET
+ * Permission : W
+ * Default value : 0x00U
+ *******************************************************************************/
+#define SX8651_CTRL_SOFTRESET_BIT_MASK 0xFFU
+#define SX8651_CTRL_SOFTRESET_BIT_POSITION 0
+int32_t sx8651_ctrl_softreset(sx8651_ctx_t *ctx, uint8_t value);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* SX8651_REG_H */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/tcpp0203/LICENSE.md b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/tcpp0203/LICENSE.md
new file mode 100644
index 00000000..9226612a
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/tcpp0203/LICENSE.md
@@ -0,0 +1,27 @@
+Copyright 2021 STMicroelectronics.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice,
+this list of conditions and the following disclaimer in the documentation and/or
+other materials provided with the distribution.
+
+3. Neither the name of the copyright holder nor the names of its contributors
+may be used to endorse or promote products derived from this software without
+specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/tcpp0203/tcpp0203.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/tcpp0203/tcpp0203.c
new file mode 100644
index 00000000..c13f91d5
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/tcpp0203/tcpp0203.c
@@ -0,0 +1,888 @@
+/**
+ ******************************************************************************
+ * @file tcpp0203.c
+ * @author MCD Application Team
+ * @brief This file provides the TCPP02/03 Type-C port protection driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tcpp0203.h"
+
+#if defined(_TRACE)
+#include "usbpd_core.h"
+#include "usbpd_trace.h"
+#include "string.h"
+#include "stdio.h"
+#endif /* _TRACE */
+
+/** @addtogroup BSP
+ * @{
+ */
+
+/** @addtogroup Components
+ * @{
+ */
+
+/** @addtogroup TCPP0203
+ * @brief This file provides a set of functions needed to drive the
+ * TCPP02/03 Type-C port protection.
+ * @{
+ */
+
+/** @defgroup TCPP0203_Private_Constants Private Constants
+ * @{
+ */
+
+/* Compilation option in order to enable/disable a concistency check performed
+ after each I2C access into TCPP0203 registers : goal is to check that written value in Reg0
+ is properly reflected into reg1 register content.
+ To enable register consistency check, please uncomment below definition.
+ To disable it, comment below line */
+/* #define TCPP0203_REGISTER_CONSISTENCY_CHECK */
+
+/** @defgroup TCPP0203_Private_Types Private Types
+ * @{
+ */
+/* TCPP02/03 Type-C port protection driver structure initialization */
+TCPP0203_Drv_t TCPP0203_Driver =
+{
+ TCPP0203_Init,
+ TCPP0203_DeInit,
+ TCPP0203_Reset,
+ TCPP0203_SetVConnSwitch,
+ TCPP0203_SetGateDriverProvider,
+ TCPP0203_SetGateDriverConsumer,
+ TCPP0203_SetPowerMode,
+ TCPP0203_SetVBusDischarge,
+ TCPP0203_SetVConnDischarge,
+ TCPP0203_GetVConnSwitchAck,
+ TCPP0203_GetGateDriverProviderAck,
+ TCPP0203_GetGateDriverConsumerAck,
+ TCPP0203_GetPowerModeAck,
+ TCPP0203_GetVBusDischargeAck,
+ TCPP0203_GetVConnDischargeAck,
+ TCPP0203_GetOCPVConnFlag,
+ TCPP0203_GetOCPVBusFlag,
+ TCPP0203_GetOVPVBusFlag,
+ TCPP0203_GetOVPCCFlag,
+ TCPP0203_GetOTPFlag,
+ TCPP0203_GetVBusOkFlag,
+ TCPP0203_ReadTCPPType,
+ TCPP0203_ReadVCONNPower,
+ TCPP0203_WriteCtrlRegister,
+ TCPP0203_ReadAckRegister,
+ TCPP0203_ReadFlagRegister,
+};
+
+/**
+ * @}
+ */
+
+/** @defgroup TCPP0203_Private_Variables Private Variables
+ * @{
+ */
+static uint8_t TCPP0203_DeviceType = TCPP0203_DEVICE_TYPE_03;
+
+#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK)
+static uint8_t Reg0_Expected_Value = 0x00;
+static uint8_t Reg1_LastRead_Value = 0x00;
+#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/** @defgroup TCPP0203_Private_Function_Prototypes TCPP0203 Private Function Prototypes
+ * @{
+ */
+static int32_t TCPP0203_ReadRegWrap(void *handle, uint8_t Reg, uint8_t *Data, uint8_t Length);
+static int32_t TCPP0203_WriteRegWrap(void *handle, uint8_t Reg, uint8_t *Data, uint8_t Length);
+
+static int32_t TCPP0203_ModifyReg0(TCPP0203_Object_t *pObj, uint8_t Value, uint8_t Mask);
+
+#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK)
+static int32_t TCPP0203_CheckReg0Reg1(TCPP0203_Object_t *pObj, uint8_t Reg0ExpectedValue);
+#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */
+
+/**
+ * @}
+ */
+
+/** @defgroup TCPP0203_Exported_Functions TCPP0203 Exported Functions
+ * @{
+ */
+
+/**
+ * @brief Register Bus Io to component
+ * @param Component object pointer
+ * @retval Status of execution
+ */
+int32_t TCPP0203_RegisterBusIO(TCPP0203_Object_t *pObj, TCPP0203_IO_t *pIO)
+{
+ int32_t ret;
+
+ if (pObj == NULL)
+ {
+ ret = TCPP0203_ERROR;
+ }
+ else
+ {
+ pObj->IO.Init = pIO->Init;
+ pObj->IO.DeInit = pIO->DeInit;
+ pObj->IO.Address = pIO->Address;
+ pObj->IO.WriteReg = pIO->WriteReg;
+ pObj->IO.ReadReg = pIO->ReadReg;
+ pObj->IO.GetTick = pIO->GetTick;
+
+ pObj->Ctx.ReadReg = TCPP0203_ReadRegWrap;
+ pObj->Ctx.WriteReg = TCPP0203_WriteRegWrap;
+ pObj->Ctx.handle = pObj;
+
+ if (pObj->IO.Init != NULL)
+ {
+ ret = pObj->IO.Init();
+ }
+ else
+ {
+ ret = TCPP0203_ERROR;
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Initializes the TCPP0203 interface
+ * @param pObj Pointer to component object
+ * @retval Component status (TCPP0203_OK / TCPP0203_ERROR)
+ */
+int32_t TCPP0203_Init(TCPP0203_Object_t *pObj)
+{
+ int32_t ret = 0;
+ uint8_t tmp;
+
+ if (pObj->IsInitialized == 0U)
+ {
+ /* Read TCPP Device type */
+ ret += tcpp0203_read_reg(&pObj->Ctx, TCPP0203_READ_REG2, &tmp, 1);
+
+ if (ret == TCPP0203_OK)
+ {
+ TCPP0203_DeviceType = (tmp & TCPP0203_DEVICE_TYPE_MSK);
+ }
+ else
+ {
+ TCPP0203_DeviceType = TCPP0203_DEVICE_TYPE_02;
+ }
+ pObj->IsInitialized = 1U;
+ }
+
+ if (ret != TCPP0203_OK)
+ {
+ ret = TCPP0203_ERROR;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Deinitializes the TCPP0203 interface
+ * @param pObj Pointer to component object
+ * @retval Component status (TCPP0203_OK / TCPP0203_ERROR)
+ */
+int32_t TCPP0203_DeInit(TCPP0203_Object_t *pObj)
+{
+ if (pObj->IsInitialized == 1U)
+ {
+ /* De-Initialize IO BUS layer */
+ pObj->IO.DeInit();
+
+ pObj->IsInitialized = 0U;
+ }
+
+ return TCPP0203_OK;
+}
+
+/**
+ * @brief Resets TCPP0203 register (Reg0)
+ * @param pObj Pointer to component object
+ * @retval Component status (TCPP0203_OK / TCPP0203_ERROR)
+ */
+int32_t TCPP0203_Reset(TCPP0203_Object_t *pObj)
+{
+ int32_t ret = TCPP0203_OK;
+ uint8_t tmp = TCPP0203_REG0_RST_VALUE;
+
+ /* Write reset values in Reg0 register */
+ if (tcpp0203_write_reg(&pObj->Ctx, TCPP0203_PROG_CTRL, &tmp, 1) != TCPP0203_OK)
+ {
+ ret = TCPP0203_ERROR;
+ }
+
+#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK)
+ Reg0_Expected_Value = TCPP0203_REG0_RST_VALUE;
+ Reg1_LastRead_Value = TCPP0203_REG0_RST_VALUE;
+#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */
+
+ return ret;
+}
+
+/**
+ * @brief Configure TCPP0203 VConn Switch
+ * @param pObj Pointer to component object
+ * @param VConnSwitch VConn Switch requested setting
+ * This parameter can be one of the following values:
+ * @arg TCPP0203_VCONN_SWITCH_OPEN VConn switch open
+ * @arg TCPP0203_VCONN_SWITCH_CC1 VConn closed on CC1
+ * @arg TCPP0203_VCONN_SWITCH_CC2 VConn closed on CC2
+ * @retval Component status
+ */
+int32_t TCPP0203_SetVConnSwitch(TCPP0203_Object_t *pObj, uint8_t VConnSwitch)
+{
+ int32_t ret = TCPP0203_OK;
+
+ if ((VConnSwitch != TCPP0203_VCONN_SWITCH_OPEN)
+ && (VConnSwitch != TCPP0203_VCONN_SWITCH_CC1)
+ && (VConnSwitch != TCPP0203_VCONN_SWITCH_CC2))
+ {
+ ret = TCPP0203_ERROR;
+ }
+ else
+ {
+ /* Update VConn switch setting in Writing register Reg0 */
+ ret += TCPP0203_ModifyReg0(pObj, VConnSwitch, TCPP0203_VCONN_SWITCH_MSK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Configure TCPP0203 Gate Driver for Provider path
+ * @param pObj Pointer to component object
+ * @param GateDriverProvider GDP switch load requested setting
+ * This parameter can be one of the following values:
+ * @arg TCPP0203_GD_PROVIDER_SWITCH_OPEN GDP Switch Load Open
+ * @arg TCPP0203_GD_PROVIDER_SWITCH_CLOSED GDP Switch Load closed
+ * @retval Component status
+ */
+int32_t TCPP0203_SetGateDriverProvider(TCPP0203_Object_t *pObj, uint8_t GateDriverProvider)
+{
+ int32_t ret = TCPP0203_OK;
+
+ if ((GateDriverProvider != TCPP0203_GD_PROVIDER_SWITCH_OPEN)
+ && (GateDriverProvider != TCPP0203_GD_PROVIDER_SWITCH_CLOSED))
+ {
+ ret = TCPP0203_ERROR;
+ }
+ else
+ {
+ /* Update GDP Switch Load setting in Writing register Reg0 */
+ if (GateDriverProvider == TCPP0203_GD_PROVIDER_SWITCH_CLOSED)
+ {
+ /* If Gate Driver Provider is to be closed, Gate Driver Consumer should be open */
+ ret += TCPP0203_ModifyReg0(pObj, (GateDriverProvider | TCPP0203_GD_CONSUMER_SWITCH_OPEN),
+ (TCPP0203_GD_PROVIDER_SWITCH_MSK | TCPP0203_GD_CONSUMER_SWITCH_MSK));
+ }
+ else
+ {
+ ret += TCPP0203_ModifyReg0(pObj, GateDriverProvider, TCPP0203_GD_PROVIDER_SWITCH_MSK);
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Configure TCPP0203 Gate Driver for Consumer path
+ * @param pObj Pointer to component object
+ * @param GateDriverConsumer GDC switch load requested setting
+ * This parameter can be one of the following values:
+ * @arg TCPP0203_GD_CONSUMER_SWITCH_OPEN GDC Switch Load Open
+ * @arg TCPP0203_GD_CONSUMER_SWITCH_CLOSED GDC Switch Load closed
+ * @retval Component status
+ */
+int32_t TCPP0203_SetGateDriverConsumer(TCPP0203_Object_t *pObj, uint8_t GateDriverConsumer)
+{
+ int32_t ret = TCPP0203_OK;
+
+ /* Check if TCPP type is TCPP03. Otherwise, return error */
+ if (TCPP0203_DeviceType != TCPP0203_DEVICE_TYPE_03)
+ {
+ return (TCPP0203_ERROR);
+ }
+
+ if ((GateDriverConsumer != TCPP0203_GD_CONSUMER_SWITCH_OPEN)
+ && (GateDriverConsumer != TCPP0203_GD_CONSUMER_SWITCH_CLOSED))
+ {
+ ret = TCPP0203_ERROR;
+ }
+ else
+ {
+ /* Update GDC Switch Load setting in Writing register Reg0 */
+ if (GateDriverConsumer == TCPP0203_GD_CONSUMER_SWITCH_CLOSED)
+ {
+ /* If Gate Driver Consumer is to be closed, Gate Driver Provider should be open */
+ ret += TCPP0203_ModifyReg0(pObj, (GateDriverConsumer | TCPP0203_GD_PROVIDER_SWITCH_OPEN),
+ (TCPP0203_GD_PROVIDER_SWITCH_MSK | TCPP0203_GD_CONSUMER_SWITCH_MSK));
+ }
+ else
+ {
+ ret += TCPP0203_ModifyReg0(pObj, GateDriverConsumer, TCPP0203_GD_CONSUMER_SWITCH_MSK);
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Configure TCPP0203 Power Mode
+ * @param pObj Pointer to component object
+ * @param PowerMode Power mode requested setting
+ * This parameter can be one of the following values:
+ * @arg TCPP0203_POWER_MODE_HIBERNATE Hibernate
+ * @arg TCPP0203_POWER_MODE_LOWPOWER Low Power
+ * @arg TCPP0203_POWER_MODE_NORMAL Normal
+ * @retval Component status
+ */
+int32_t TCPP0203_SetPowerMode(TCPP0203_Object_t *pObj, uint8_t PowerMode)
+{
+ int32_t ret = TCPP0203_OK;
+
+ if ((PowerMode != TCPP0203_POWER_MODE_HIBERNATE)
+ && (PowerMode != TCPP0203_POWER_MODE_LOWPOWER)
+ && (PowerMode != TCPP0203_POWER_MODE_NORMAL))
+ {
+ ret = TCPP0203_ERROR;
+ }
+ else
+ {
+ /* Update Power Mode setting in Writing register Reg0 */
+ ret += TCPP0203_ModifyReg0(pObj, PowerMode, TCPP0203_POWER_MODE_MSK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Configure TCPP0203 Gate Driver for Provider path
+ * @param pObj Pointer to component object
+ * @param VBusDischarge VBUS Discharge requested setting
+ * This parameter can be one of the following values:
+ * @arg TCPP0203_VBUS_DISCHARGE_OFF VBUS Discharge Off
+ * @arg TCPP0203_VBUS_DISCHARGE_ON VBUS Discharge On
+ * @retval Component status
+ */
+int32_t TCPP0203_SetVBusDischarge(TCPP0203_Object_t *pObj, uint8_t VBusDischarge)
+{
+ int32_t ret = TCPP0203_OK;
+
+ if ((VBusDischarge != TCPP0203_VBUS_DISCHARGE_OFF)
+ && (VBusDischarge != TCPP0203_VBUS_DISCHARGE_ON))
+ {
+ ret = TCPP0203_ERROR;
+ }
+ else
+ {
+ /* Update VBUS Discharge setting in Writing register Reg0 */
+ ret += TCPP0203_ModifyReg0(pObj, VBusDischarge, TCPP0203_VBUS_DISCHARGE_MSK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Configure TCPP0203 Gate Driver for Provider path
+ * @param pObj Pointer to component object
+ * @param VConnDischarge GDP switch load requested setting
+ * This parameter can be one of the following values:
+ * @arg TCPP0203_VCONN_DISCHARGE_OFF VConn Discharge Off
+ * @arg TCPP0203_VCONN_DISCHARGE_ON VConn Discharge On
+ * @retval Component status
+ */
+int32_t TCPP0203_SetVConnDischarge(TCPP0203_Object_t *pObj, uint8_t VConnDischarge)
+{
+ int32_t ret = TCPP0203_OK;
+
+ if ((VConnDischarge != TCPP0203_VCONN_DISCHARGE_OFF)
+ && (VConnDischarge != TCPP0203_VCONN_DISCHARGE_ON))
+ {
+ ret = TCPP0203_ERROR;
+ }
+ else
+ {
+ /* Update VConn Discharge setting in Writing register Reg0 */
+ ret += TCPP0203_ModifyReg0(pObj, VConnDischarge, TCPP0203_VCONN_DISCHARGE_MSK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Get VConn switch Ack value
+ * @param pObj Pointer to component object
+ * @param pVConnSwitchAck Pointer on VConn switch Ack value
+ * This output parameter can be one of the following values:
+ * @arg TCPP0203_VCONN_SWITCH_OPEN VConn switch open Ack
+ * @arg TCPP0203_VCONN_SWITCH_CC1 VConn closed on CC1 Ack
+ * @arg TCPP0203_VCONN_SWITCH_CC2 VConn closed on CC2 Ack
+ * @retval Component status
+ */
+int32_t TCPP0203_GetVConnSwitchAck(TCPP0203_Object_t *pObj, uint8_t *pVConnSwitchAck)
+{
+ int32_t ret;
+ uint8_t tmp;
+
+ ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1);
+ *pVConnSwitchAck = (tmp & TCPP0203_VCONN_SWITCH_ACK_MSK);
+
+ return ret;
+}
+
+/**
+ * @brief Get Gate Driver Provider Ack value
+ * @param pObj Pointer to component object
+ * @param pGateDriverProviderAck Pointer on Gate Driver Provider Ack value
+ * This output parameter can be one of the following values:
+ * @arg TCPP0203_GD_PROVIDER_SWITCH_ACK_OPEN Gate Driver Provider Open Ack
+ * @arg TCPP0203_GD_PROVIDER_SWITCH_ACK_CLOSED Gate Driver Provider Closed Ack
+ * @retval Component status
+ */
+int32_t TCPP0203_GetGateDriverProviderAck(TCPP0203_Object_t *pObj, uint8_t *pGateDriverProviderAck)
+{
+ int32_t ret;
+ uint8_t tmp;
+
+ ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1);
+ *pGateDriverProviderAck = (tmp & TCPP0203_GD_PROVIDER_SWITCH_ACK_MSK);
+
+ return ret;
+}
+
+/**
+ * @brief Get Gate Driver Consumer Ack value
+ * @param pObj Pointer to component object
+ * @param pGateDriverConsumerAck Pointer on Gate Driver Consumer Ack value
+ * This output parameter can be one of the following values:
+ * @arg TCPP0203_GD_CONSUMER_SWITCH_ACK_OPEN Gate Driver Consumer Open Ack
+ * @arg TCPP0203_GD_CONSUMER_SWITCH_ACK_CLOSED Gate Driver Consumer Closed Ack
+ * @retval Component status
+ */
+int32_t TCPP0203_GetGateDriverConsumerAck(TCPP0203_Object_t *pObj, uint8_t *pGateDriverConsumerAck)
+{
+ int32_t ret;
+ uint8_t tmp;
+
+ /* Check if TCPP type is TCPP03. Otherwise, return error */
+ if (TCPP0203_DeviceType != TCPP0203_DEVICE_TYPE_03)
+ {
+ return (TCPP0203_ERROR);
+ }
+
+ ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1);
+ *pGateDriverConsumerAck = (tmp & TCPP0203_GD_CONSUMER_SWITCH_ACK_MSK);
+
+ return ret;
+}
+
+/**
+ * @brief Get Power Mode Ack value
+ * @param pObj Pointer to component object
+ * @param pPowerModeAck Pointer on Power Mode Ack value
+ * This output parameter can be one of the following values:
+ * @arg TCPP0203_POWER_MODE_ACK_HIBERNATE Power Mode Hibernate Ack
+ * @arg TCPP0203_POWER_MODE_ACK_LOWPOWER Power Mode Low Power Ack
+ * @arg TCPP0203_POWER_MODE_ACK_NORMAL Power Mode Normal Ack
+ * @retval Component status
+ */
+int32_t TCPP0203_GetPowerModeAck(TCPP0203_Object_t *pObj, uint8_t *pPowerModeAck)
+{
+ int32_t ret;
+ uint8_t tmp;
+
+ ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1);
+ *pPowerModeAck = (tmp & TCPP0203_POWER_MODE_ACK_MSK);
+
+ return ret;
+}
+
+/**
+ * @brief Get VBUS Discharge Ack value
+ * @param pObj Pointer to component object
+ * @param pVBusDischargeAck Pointer on VBUS Discharge Ack value
+ * This output parameter can be one of the following values:
+ * @arg TCPP0203_VBUS_DISCHARGE_ACK_OFF VBUS Discharge Off Ack
+ * @arg TCPP0203_VBUS_DISCHARGE_ACK_ON VBUS Discharge On Ack
+ * @retval Component status
+ */
+int32_t TCPP0203_GetVBusDischargeAck(TCPP0203_Object_t *pObj, uint8_t *pVBusDischargeAck)
+{
+ int32_t ret;
+ uint8_t tmp;
+
+ ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1);
+ *pVBusDischargeAck = (tmp & TCPP0203_VBUS_DISCHARGE_ACK_MSK);
+
+ return ret;
+}
+
+/**
+ * @brief Get VConn Discharge Ack value
+ * @param pObj Pointer to component object
+ * @param pVConnDischargeAck Pointer on VConn Discharge Ack value
+ * This output parameter can be one of the following values:
+ * @arg TCPP0203_VCONN_DISCHARGE_ACK_OFF VConn Discharge Off Ack
+ * @arg TCPP0203_VCONN_DISCHARGE_ACK_ON VConn Discharge On Ack
+ * @retval Component status
+ */
+int32_t TCPP0203_GetVConnDischargeAck(TCPP0203_Object_t *pObj, uint8_t *pVConnDischargeAck)
+{
+ int32_t ret;
+ uint8_t tmp;
+
+ ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1);
+ *pVConnDischargeAck = (tmp & TCPP0203_VCONN_DISCHARGE_ACK_MSK);
+
+ return ret;
+}
+
+/**
+ * @brief Get OCP VConn Flag value
+ * @param pObj Pointer to component object
+ * @param pOCPVConnFlag Pointer on OCP VConn Flag value
+ * This output parameter can be one of the following values:
+ * @arg TCPP0203_FLAG_OCP_VCONN_RESET OCP VConn flag not set
+ * @arg TCPP0203_FLAG_OCP_VCONN_SET OCP VConn flag set
+ * @retval Component status
+ */
+int32_t TCPP0203_GetOCPVConnFlag(TCPP0203_Object_t *pObj, uint8_t *pOCPVConnFlag)
+{
+ int32_t ret;
+ uint8_t tmp;
+
+ ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1);
+ *pOCPVConnFlag = (tmp & TCPP0203_FLAG_OCP_VCONN_MSK);
+
+ return ret;
+}
+
+/**
+ * @brief Get OCP VBUS Flag value
+ * @param pObj Pointer to component object
+ * @param GetOCPVBusFlag Pointer on OCP VBUS Flag value
+ * This output parameter can be one of the following values:
+ * @arg TCPP0203_FLAG_OCP_VBUS_RESET OCP VBUS flag not set
+ * @arg TCPP0203_FLAG_OCP_VBUS_SET OCP VBUS flag set
+ * @retval Component status
+ */
+int32_t TCPP0203_GetOCPVBusFlag(TCPP0203_Object_t *pObj, uint8_t *GetOCPVBusFlag)
+{
+ int32_t ret;
+ uint8_t tmp;
+
+ ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1);
+ *GetOCPVBusFlag = (tmp & TCPP0203_FLAG_OCP_VBUS_MSK);
+
+ return ret;
+}
+
+/**
+ * @brief Get OVP VBUS Flag value
+ * @param pObj Pointer to component object
+ * @param OVPVBusFlag Pointer on OVP VBUS Flag value
+ * This output parameter can be one of the following values:
+ * @arg TCPP0203_FLAG_OVP_VBUS_RESET OVP VBUS flag not set
+ * @arg TCPP0203_FLAG_OVP_VBUS_SET OVP VBUS flag set
+ * @retval Component status
+ */
+int32_t TCPP0203_GetOVPVBusFlag(TCPP0203_Object_t *pObj, uint8_t *OVPVBusFlag)
+{
+ int32_t ret;
+ uint8_t tmp;
+
+ ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1);
+ *OVPVBusFlag = (tmp & TCPP0203_FLAG_OVP_VBUS_MSK);
+
+ return ret;
+}
+
+/**
+ * @brief Get OVP CC Flag value
+ * @param pObj Pointer to component object
+ * @param pOCPVConnFlag Pointer on OVP CC Flag value
+ * This output parameter can be one of the following values:
+ * @arg TCPP0203_FLAG_OVP_CC_RESET OVP CC flag not set
+ * @arg TCPP0203_FLAG_OVP_CC_SET OVP CC flag set
+ * @retval Component status
+ */
+int32_t TCPP0203_GetOVPCCFlag(TCPP0203_Object_t *pObj, uint8_t *OVPCCFlag)
+{
+ int32_t ret;
+ uint8_t tmp;
+
+ ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1);
+ *OVPCCFlag = (tmp & TCPP0203_FLAG_OVP_CC_MSK);
+
+ return ret;
+}
+
+/**
+ * @brief Get Over Temperature Flag value
+ * @param pObj Pointer to component object
+ * @param OTPFlag Pointer on Over Temperature Flag value
+ * This output parameter can be one of the following values:
+ * @arg TCPP0203_FLAG_OTP_RESET Over Temperature flag not set
+ * @arg TCPP0203_FLAG_OTP_SET Over Temperature flag set
+ * @retval Component status
+ */
+int32_t TCPP0203_GetOTPFlag(TCPP0203_Object_t *pObj, uint8_t *OTPFlag)
+{
+ int32_t ret;
+ uint8_t tmp;
+
+ ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1);
+ *OTPFlag = (tmp & TCPP0203_FLAG_OTP_MSK);
+
+ return ret;
+}
+
+/**
+ * @brief Get VBUS OK Flag value
+ * @param pObj Pointer to component object
+ * @param VBusOkFlag Pointer on VBUS OK Flag value
+ * This output parameter can be one of the following values:
+ * @arg TCPP0203_FLAG_VBUS_OK_RESET VBUS OK flag not set
+ * @arg TCPP0203_FLAG_VBUS_OK_SET VBUS OK flag set
+ * @retval Component status
+ */
+int32_t TCPP0203_GetVBusOkFlag(TCPP0203_Object_t *pObj, uint8_t *VBusOkFlag)
+{
+ int32_t ret;
+ uint8_t tmp;
+
+ ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1);
+ *VBusOkFlag = (tmp & TCPP0203_FLAG_VBUS_OK_MSK);
+
+ return ret;
+}
+
+/**
+ * @brief Get TCPP0203 Device Type value
+ * @param pObj Pointer to component object
+ * @param pTCPPType Pointer on TCPP0203 Device Type value
+ * This output parameter can be one of the following values:
+ * @arg TCPP0203_DEVICE_TYPE_02 TCPP02 Type
+ * @arg TCPP0203_DEVICE_TYPE_03 TCPP03 Type
+ * @retval Component status
+ */
+int32_t TCPP0203_ReadTCPPType(TCPP0203_Object_t *pObj, uint8_t *pTCPPType)
+{
+ int32_t ret;
+ uint8_t tmp;
+
+ ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1);
+ *pTCPPType = (tmp & TCPP0203_DEVICE_TYPE_MSK);
+
+ return ret;
+}
+
+/**
+ * @brief Get VConn Power value
+ * @param pObj Pointer to component object
+ * @param pVCONNPower Pointer on VConn Power value
+ * This output parameter can be one of the following values:
+ * @arg TCPP0203_FLAG_VCONN_PWR_1W OCP VConn flag not set
+ * @arg TCPP0203_FLAG_VCONN_PWR_0_1W OCP VConn flag set
+ * @retval Component status
+ */
+int32_t TCPP0203_ReadVCONNPower(TCPP0203_Object_t *pObj, uint8_t *pVCONNPower)
+{
+ int32_t ret;
+ uint8_t tmp;
+
+ ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1);
+ *pVCONNPower = (tmp & TCPP0203_FLAG_VCONN_PWR_MSK);
+
+ return ret;
+}
+
+/**
+ * @brief Set complete Ctrl register value (Reg 0)
+ * @param pObj Pointer to component object
+ * @param pCtrlRegister Pointer on Ctrl register value
+ * @retval Component status
+ */
+int32_t TCPP0203_WriteCtrlRegister(TCPP0203_Object_t *pObj, uint8_t *pCtrlRegister)
+{
+ int32_t ret;
+
+ /* Update value in writing register (reg0) */
+ ret = tcpp0203_write_reg(&pObj->Ctx, TCPP0203_PROG_CTRL, pCtrlRegister, 1);
+
+#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK)
+ Reg0_Expected_Value = *pCtrlRegister;
+#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */
+
+ return ret;
+}
+
+/**
+ * @brief Get complete Ack register value
+ * @param pObj Pointer to component object
+ * @param pAckRegister Pointer on Ack register value
+ * @retval Component status
+ */
+int32_t TCPP0203_ReadAckRegister(TCPP0203_Object_t *pObj, uint8_t *pAckRegister)
+{
+ int32_t ret;
+
+ ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, pAckRegister, 1);
+
+ return ret;
+}
+
+/**
+ * @brief Get complete Flag register value
+ * @param pObj Pointer to component object
+ * @param pFlagRegister Pointer on Flag register value
+ * @retval Component status
+ */
+int32_t TCPP0203_ReadFlagRegister(TCPP0203_Object_t *pObj, uint8_t *pFlagRegister)
+{
+ int32_t ret;
+
+ ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, pFlagRegister, 1);
+
+ return ret;
+}
+
+/******************** Static functions ****************************************/
+/**
+ * @brief Wrap TCPP0203 read function to Bus IO function
+ * @param handle Component object handle
+ * @param Reg Target register address to read
+ * @param pData Buffer where Target register value should be stored
+ * @param Length buffer size to be read
+ * @retval error status
+ */
+static int32_t TCPP0203_ReadRegWrap(void *handle, uint8_t Reg, uint8_t *pData, uint8_t Length)
+{
+ TCPP0203_Object_t *pObj = (TCPP0203_Object_t *)handle;
+
+ return pObj->IO.ReadReg(pObj->IO.Address, Reg, pData, Length);
+}
+
+/**
+ * @brief Wrap TCPP0203 write function to Bus IO function
+ * @param handle Component object handle
+ * @param Reg Target register address to write
+ * @param pData Target register value to be written
+ * @param Length Buffer size to be written
+ * @retval error status
+ */
+static int32_t TCPP0203_WriteRegWrap(void *handle, uint8_t Reg, uint8_t *pData, uint8_t Length)
+{
+ TCPP0203_Object_t *pObj = (TCPP0203_Object_t *)handle;
+
+#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK)
+ Reg0_Expected_Value = *pData;
+#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */
+
+ return pObj->IO.WriteReg(pObj->IO.Address, Reg, pData, Length);
+}
+
+/**
+ * @brief TCPP0203 register update function to Bus IO function
+ * @param handle Component object handle
+ * @param Reg Target register address to write
+ * @param pData Target register value to be written
+ * @param Length Buffer size to be written
+ * @retval error status
+ */
+static int32_t TCPP0203_ModifyReg0(TCPP0203_Object_t *pObj, uint8_t Value, uint8_t Mask)
+{
+ int32_t ret;
+ uint8_t tmp;
+
+ /* Read current content of ACK register (reflects content of bits set to 1 in Writing register Reg0) */
+ ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1);
+
+ /* Update only the area dedicated to Mask */
+ tmp &= ~(Mask);
+ tmp |= (Value & Mask);
+
+#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK)
+ Reg0_Expected_Value = tmp;
+#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */
+
+ /* Update value in writing register (reg0) */
+ ret += tcpp0203_write_reg(&pObj->Ctx, TCPP0203_PROG_CTRL, &tmp, 1);
+
+#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK)
+ ret += TCPP0203_CheckReg0Reg1(pObj, Reg0_Expected_Value);
+#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */
+
+ return ret;
+}
+
+#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK)
+/**
+ * @brief TCPP0203 register control function between Reg0 and Reg1 value
+ * @param handle Component object handle
+ * @param Reg0ExpectedValue Value expected in Reg0 (built after all calls to write functions)
+ * @retval error status
+ */
+static int32_t TCPP0203_CheckReg0Reg1(TCPP0203_Object_t *pObj, uint8_t Reg0ExpectedValue)
+{
+ int32_t ret;
+
+ /* Read current content of ACK register (expected to reflect content of bits set to 1 in Writing register Reg0) */
+ ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &Reg1_LastRead_Value, 1);
+
+#ifdef _TRACE
+ char str[12];
+ sprintf(str, "Exp0_0x%02x", Reg0ExpectedValue);
+ USBPD_TRACE_Add(USBPD_TRACE_DEBUG, 0U, 0U, (uint8_t *)str, sizeof(str) - 1U);
+ sprintf(str, "Reg1_0x%02x", Reg1_LastRead_Value);
+ USBPD_TRACE_Add(USBPD_TRACE_DEBUG, 0U, 0U, (uint8_t *)str, sizeof(str) - 1U);
+#endif /* _TRACE */
+
+ /* Control if Reg1 value is same as Reg0 expected one */
+ if (Reg1_LastRead_Value != Reg0ExpectedValue)
+ {
+ while (1);
+ }
+
+ return ret;
+}
+#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/tcpp0203/tcpp0203.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/tcpp0203/tcpp0203.h
new file mode 100644
index 00000000..f6341605
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/tcpp0203/tcpp0203.h
@@ -0,0 +1,356 @@
+/**
+ ******************************************************************************
+ * @file tcpp0203.h
+ * @author MCD Application Team
+ * @brief This file contains all the functions prototypes for the
+ * tcpp0203.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef TCPP0203_H
+#define TCPP0203_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "tcpp0203_reg.h"
+#include
+
+/** @addtogroup BSP
+ * @{
+ */
+
+/** @addtogroup Component
+ * @{
+ */
+
+/** @addtogroup TCPP0203
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup TCPP0203_Exported_Types TCPP0203 Exported Types
+ * @{
+ */
+typedef int32_t (*TCPP0203_Init_Func)(void);
+typedef int32_t (*TCPP0203_DeInit_Func)(void);
+typedef int32_t (*TCPP0203_GetTick_Func)(void);
+typedef int32_t (*TCPP0203_Delay_Func)(uint32_t);
+typedef int32_t (*TCPP0203_WriteReg_Func)(uint16_t, uint16_t, uint8_t *, uint16_t);
+typedef int32_t (*TCPP0203_ReadReg_Func)(uint16_t, uint16_t, uint8_t *, uint16_t);
+
+typedef struct
+{
+ TCPP0203_Init_Func Init;
+ TCPP0203_DeInit_Func DeInit;
+ uint16_t Address;
+ TCPP0203_WriteReg_Func WriteReg;
+ TCPP0203_ReadReg_Func ReadReg;
+ TCPP0203_GetTick_Func GetTick;
+} TCPP0203_IO_t;
+
+
+typedef struct
+{
+ TCPP0203_IO_t IO;
+ TCPP0203_ctx_t Ctx;
+ uint8_t IsInitialized;
+} TCPP0203_Object_t;
+
+typedef struct
+{
+ int32_t (*Init)(TCPP0203_Object_t *);
+ int32_t (*DeInit)(TCPP0203_Object_t *);
+ int32_t (*Reset)(TCPP0203_Object_t *);
+ int32_t (*SetVConnSwitch)(TCPP0203_Object_t *, uint8_t);
+ int32_t (*SetGateDriverProvider)(TCPP0203_Object_t *, uint8_t);
+ int32_t (*SetGateDriverConsumer)(TCPP0203_Object_t *, uint8_t);
+ int32_t (*SetPowerMode)(TCPP0203_Object_t *, uint8_t);
+ int32_t (*SetVBusDischarge)(TCPP0203_Object_t *, uint8_t);
+ int32_t (*SetVConnDischarge)(TCPP0203_Object_t *, uint8_t);
+ int32_t (*GetVConnSwitchAck)(TCPP0203_Object_t *, uint8_t *);
+ int32_t (*GetGateDriverProviderAck)(TCPP0203_Object_t *, uint8_t *);
+ int32_t (*GetGateDriverConsumerAck)(TCPP0203_Object_t *, uint8_t *);
+ int32_t (*GetPowerModeAck)(TCPP0203_Object_t *, uint8_t *);
+ int32_t (*GetVBusDischargeAck)(TCPP0203_Object_t *, uint8_t *);
+ int32_t (*GetVConnDischargeAck)(TCPP0203_Object_t *, uint8_t *);
+ int32_t (*GetOCPVConnFlag)(TCPP0203_Object_t *, uint8_t *);
+ int32_t (*GetOCPVBusFlag)(TCPP0203_Object_t *, uint8_t *);
+ int32_t (*GetOVPVBusFlag)(TCPP0203_Object_t *, uint8_t *);
+ int32_t (*GetOVPCCFlag)(TCPP0203_Object_t *, uint8_t *);
+ int32_t (*GetOTPFlag)(TCPP0203_Object_t *, uint8_t *);
+ int32_t (*GetVBusOkFlag)(TCPP0203_Object_t *, uint8_t *);
+ int32_t (*ReadTCPPType)(TCPP0203_Object_t *, uint8_t *);
+ int32_t (*ReadVCONNPower)(TCPP0203_Object_t *, uint8_t *);
+ int32_t (*WriteCtrlRegister)(TCPP0203_Object_t *, uint8_t *);
+ int32_t (*ReadAckRegister)(TCPP0203_Object_t *, uint8_t *);
+ int32_t (*ReadFlagRegister)(TCPP0203_Object_t *, uint8_t *);
+} TCPP0203_Drv_t;
+
+/**
+ * @}
+ */
+
+/** @defgroup TCPP0203_Exported_Constants TCPP0203 Exported Constants
+ * @{
+ */
+/**
+ * @brief TCPP0203 Driver Response codes
+ */
+#define TCPP0203_OK (0)
+#define TCPP0203_ERROR (-1)
+
+/**
+ * @brief TCPP0203 possible I2C Addresses
+ */
+#define TCPP0203_I2C_ADDRESS_X68 (0x68U)
+#define TCPP0203_I2C_ADDRESS_X6A (0x6AU)
+
+/**
+ * @brief TCPP0203 Reg0 Reset Value
+ */
+#define TCPP0203_REG0_RST_VALUE TCPP0203_GD_CONSUMER_SWITCH_CLOSED
+
+/**
+ * @brief TCPP0203 VCONN Switch
+ */
+#define TCPP0203_VCONN_SWITCH_POS (0U)
+#define TCPP0203_VCONN_SWITCH_MSK (0x03U << TCPP0203_VCONN_SWITCH_POS)
+#define TCPP0203_VCONN_SWITCH_OPEN (0x00U)
+#define TCPP0203_VCONN_SWITCH_CC1 (0x01U << TCPP0203_VCONN_SWITCH_POS)
+#define TCPP0203_VCONN_SWITCH_CC2 (0x02U << TCPP0203_VCONN_SWITCH_POS)
+
+/**
+ * @brief TCPP0203 Gate Driver Provider values
+ */
+#define TCPP0203_GD_PROVIDER_SWITCH_POS (2U)
+#define TCPP0203_GD_PROVIDER_SWITCH_MSK (0x01U << TCPP0203_GD_PROVIDER_SWITCH_POS)
+#define TCPP0203_GD_PROVIDER_SWITCH_OPEN (0x00U)
+#define TCPP0203_GD_PROVIDER_SWITCH_CLOSED (TCPP0203_GD_PROVIDER_SWITCH_MSK)
+
+/**
+ * @brief TCPP0203 Gate Driver Consumer values
+ */
+#define TCPP0203_GD_CONSUMER_SWITCH_POS (3U)
+#define TCPP0203_GD_CONSUMER_SWITCH_MSK (0x01U << TCPP0203_GD_CONSUMER_SWITCH_POS)
+#define TCPP0203_GD_CONSUMER_SWITCH_CLOSED (0x00U)
+#define TCPP0203_GD_CONSUMER_SWITCH_OPEN (TCPP0203_GD_CONSUMER_SWITCH_MSK)
+
+/**
+ * @brief TCPP0203 Power Mode values
+ */
+#define TCPP0203_POWER_MODE_POS (4U)
+#define TCPP0203_POWER_MODE_MSK (0x03U << TCPP0203_POWER_MODE_POS)
+#define TCPP0203_POWER_MODE_HIBERNATE (0x00U)
+#define TCPP0203_POWER_MODE_LOWPOWER (0x02U << TCPP0203_POWER_MODE_POS)
+#define TCPP0203_POWER_MODE_NORMAL (0x01U << TCPP0203_POWER_MODE_POS)
+
+/**
+ * @brief TCPP0203 VBUS Discharge management
+ */
+#define TCPP0203_VBUS_DISCHARGE_POS (6U)
+#define TCPP0203_VBUS_DISCHARGE_MSK (0x01U << TCPP0203_VBUS_DISCHARGE_POS)
+#define TCPP0203_VBUS_DISCHARGE_OFF (0x00U)
+#define TCPP0203_VBUS_DISCHARGE_ON (TCPP0203_VBUS_DISCHARGE_MSK)
+
+/**
+ * @brief TCPP0203 VConn Discharge management
+ */
+#define TCPP0203_VCONN_DISCHARGE_POS (7U)
+#define TCPP0203_VCONN_DISCHARGE_MSK (0x01U << TCPP0203_VCONN_DISCHARGE_POS)
+#define TCPP0203_VCONN_DISCHARGE_OFF (0x00U)
+#define TCPP0203_VCONN_DISCHARGE_ON (TCPP0203_VCONN_DISCHARGE_MSK)
+
+/**
+ * @brief TCPP0203 VCONN Switch Acknowledge
+ */
+#define TCPP0203_VCONN_SWITCH_ACK_POS (0U)
+#define TCPP0203_VCONN_SWITCH_ACK_MSK (0x03U << TCPP0203_VCONN_SWITCH_ACK_POS)
+#define TCPP0203_VCONN_SWITCH_ACK_OPEN (0x00U)
+#define TCPP0203_VCONN_SWITCH_ACK_CC1 (0x02U << TCPP0203_VCONN_SWITCH_ACK_POS)
+#define TCPP0203_VCONN_SWITCH_ACK_CC2 (0x01U << TCPP0203_VCONN_SWITCH_ACK_POS)
+
+/**
+ * @brief TCPP0203 Gate Driver Provider Acknowledge
+ */
+#define TCPP0203_GD_PROVIDER_SWITCH_ACK_POS (2U)
+#define TCPP0203_GD_PROVIDER_SWITCH_ACK_MSK (0x01U << TCPP0203_GD_PROVIDER_SWITCH_ACK_POS)
+#define TCPP0203_GD_PROVIDER_SWITCH_ACK_OPEN (0x00U)
+#define TCPP0203_GD_PROVIDER_SWITCH_ACK_CLOSED (TCPP0203_GD_PROVIDER_SWITCH_ACK_MSK)
+
+/**
+ * @brief TCPP0203 Gate Driver Consumer Acknowledge
+ */
+#define TCPP0203_GD_CONSUMER_SWITCH_ACK_POS (3U)
+#define TCPP0203_GD_CONSUMER_SWITCH_ACK_MSK (0x01U << TCPP0203_GD_CONSUMER_SWITCH_ACK_POS)
+#define TCPP0203_GD_CONSUMER_SWITCH_ACK_CLOSED (0x00U)
+#define TCPP0203_GD_CONSUMER_SWITCH_ACK_OPEN (TCPP0203_GD_CONSUMER_SWITCH_ACK_MSK)
+
+/**
+ * @brief TCPP0203 Power Mode Acknowledge
+ */
+#define TCPP0203_POWER_MODE_ACK_POS (4U)
+#define TCPP0203_POWER_MODE_ACK_MSK (0x03U << TCPP0203_POWER_MODE_ACK_POS)
+#define TCPP0203_POWER_MODE_ACK_HIBERNATE (0x00U)
+#define TCPP0203_POWER_MODE_ACK_LOWPOWER (0x01U << TCPP0203_POWER_MODE_ACK_POS)
+#define TCPP0203_POWER_MODE_ACK_NORMAL (0x02U << TCPP0203_POWER_MODE_ACK_POS)
+
+/**
+ * @brief TCPP0203 VBUS Discharge Acknowledge
+ */
+#define TCPP0203_VBUS_DISCHARGE_ACK_POS (6U)
+#define TCPP0203_VBUS_DISCHARGE_ACK_MSK (0x01U << TCPP0203_VBUS_DISCHARGE_ACK_POS)
+#define TCPP0203_VBUS_DISCHARGE_ACK_OFF (0x00U)
+#define TCPP0203_VBUS_DISCHARGE_ACK_ON (TCPP0203_VBUS_DISCHARGE_ACK_MSK)
+
+/**
+ * @brief TCPP0203 VConn Discharge Acknowledge
+ */
+#define TCPP0203_VCONN_DISCHARGE_ACK_POS (7U)
+#define TCPP0203_VCONN_DISCHARGE_ACK_MSK (0x01U << TCPP0203_VCONN_DISCHARGE_ACK_POS)
+#define TCPP0203_VCONN_DISCHARGE_ACK_OFF (0x00U)
+#define TCPP0203_VCONN_DISCHARGE_ACK_ON (TCPP0203_VCONN_DISCHARGE_ACK_MSK)
+
+/**
+ * @brief TCPP0203 OCP Vconn Flag management
+ */
+#define TCPP0203_FLAG_OCP_VCONN_POS (0U)
+#define TCPP0203_FLAG_OCP_VCONN_MSK (0x01U << TCPP0203_FLAG_OCP_VCONN_POS)
+#define TCPP0203_FLAG_OCP_VCONN_SET (TCPP0203_FLAG_OCP_VCONN_MSK)
+#define TCPP0203_FLAG_OCP_VCONN_RESET (0x00U)
+
+/**
+ * @brief TCPP0203 OCP VBUS Flag management
+ */
+#define TCPP0203_FLAG_OCP_VBUS_POS (1U)
+#define TCPP0203_FLAG_OCP_VBUS_MSK (0x01U << TCPP0203_FLAG_OCP_VBUS_POS)
+#define TCPP0203_FLAG_OCP_VBUS_SET (TCPP0203_FLAG_OCP_VBUS_MSK)
+#define TCPP0203_FLAG_OCP_VBUS_RESET (0x00U)
+
+/**
+ * @brief TCPP0203 OVP VBUS Flag management
+ */
+#define TCPP0203_FLAG_OVP_VBUS_POS (2U)
+#define TCPP0203_FLAG_OVP_VBUS_MSK (0x01U << TCPP0203_FLAG_OVP_VBUS_POS)
+#define TCPP0203_FLAG_OVP_VBUS_SET (TCPP0203_FLAG_OVP_VBUS_MSK)
+#define TCPP0203_FLAG_OVP_VBUS_RESET (0x00U)
+
+/**
+ * @brief TCPP0203 OVP CC Flag management
+ */
+#define TCPP0203_FLAG_OVP_CC_POS (3U)
+#define TCPP0203_FLAG_OVP_CC_MSK (0x01U << TCPP0203_FLAG_OVP_CC_POS)
+#define TCPP0203_FLAG_OVP_CC_SET (TCPP0203_FLAG_OVP_CC_MSK)
+#define TCPP0203_FLAG_OVP_CC_RESET (0x00U)
+
+/**
+ * @brief TCPP0203 OTP Flag management
+ */
+#define TCPP0203_FLAG_OTP_POS (4U)
+#define TCPP0203_FLAG_OTP_MSK (0x01U << TCPP0203_FLAG_OTP_POS)
+#define TCPP0203_FLAG_OTP_SET (TCPP0203_FLAG_OTP_MSK)
+#define TCPP0203_FLAG_OTP_RESET (0x00U)
+
+/**
+ * @brief TCPP0203 VBUS OK Flag management
+ */
+#define TCPP0203_FLAG_VBUS_OK_POS (5U)
+#define TCPP0203_FLAG_VBUS_OK_MSK (0x01U << TCPP0203_FLAG_VBUS_OK_POS)
+#define TCPP0203_FLAG_VBUS_OK_SET (TCPP0203_FLAG_VBUS_OK_MSK)
+#define TCPP0203_FLAG_VBUS_OK_RESET (0x00U)
+
+/**
+ * @brief TCPP0203 VConn Power
+ */
+#define TCPP0203_FLAG_VCONN_PWR_POS (6U)
+#define TCPP0203_FLAG_VCONN_PWR_MSK (0x01U << TCPP0203_FLAG_VCONN_PWR_POS)
+#define TCPP0203_FLAG_VCONN_PWR_1W (TCPP0203_FLAG_VCONN_PWR_MSK)
+#define TCPP0203_FLAG_VCONN_PWR_0_1W (0x00U)
+
+/**
+ * @brief TCPP0203 Device Type
+ */
+#define TCPP0203_DEVICE_TYPE_POS (7U)
+#define TCPP0203_DEVICE_TYPE_MSK (0x01U << TCPP0203_DEVICE_TYPE_POS)
+#define TCPP0203_DEVICE_TYPE_02 (TCPP0203_DEVICE_TYPE_MSK)
+#define TCPP0203_DEVICE_TYPE_03 (0x00U)
+
+/**
+ * @}
+ */
+
+/** @defgroup TCPP0203_Exported_Macros TCPP0203 Exported Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @defgroup TCPP0203_Exported_Functions TCPP0203 Exported Functions
+ * @{
+ */
+
+/*------------------------------------------------------------------------------
+ TCPP02/03 Type-C port protection functions
+------------------------------------------------------------------------------*/
+/* High Layer codec functions */
+int32_t TCPP0203_RegisterBusIO(TCPP0203_Object_t *pObj, TCPP0203_IO_t *pIO);
+int32_t TCPP0203_Init(TCPP0203_Object_t *pObj);
+int32_t TCPP0203_DeInit(TCPP0203_Object_t *pObj);
+int32_t TCPP0203_Reset(TCPP0203_Object_t *pObj);
+int32_t TCPP0203_SetVConnSwitch(TCPP0203_Object_t *pObj, uint8_t VConnSwitch);
+int32_t TCPP0203_SetGateDriverProvider(TCPP0203_Object_t *pObj, uint8_t GateDriverProvider);
+int32_t TCPP0203_SetGateDriverConsumer(TCPP0203_Object_t *pObj, uint8_t GateDriverConsumer);
+int32_t TCPP0203_SetPowerMode(TCPP0203_Object_t *pObj, uint8_t PowerMode);
+int32_t TCPP0203_SetVBusDischarge(TCPP0203_Object_t *pObj, uint8_t VBusDischarge);
+int32_t TCPP0203_SetVConnDischarge(TCPP0203_Object_t *pObj, uint8_t VConnDischarge);
+int32_t TCPP0203_GetVConnSwitchAck(TCPP0203_Object_t *pObj, uint8_t *pVConnSwitchAck);
+int32_t TCPP0203_GetGateDriverProviderAck(TCPP0203_Object_t *pObj, uint8_t *pGateDriverProviderAck);
+int32_t TCPP0203_GetGateDriverConsumerAck(TCPP0203_Object_t *pObj, uint8_t *pGateDriverConsumerAck);
+int32_t TCPP0203_GetPowerModeAck(TCPP0203_Object_t *pObj, uint8_t *pPowerModeAck);
+int32_t TCPP0203_GetVBusDischargeAck(TCPP0203_Object_t *pObj, uint8_t *pVBusDischargeAck);
+int32_t TCPP0203_GetVConnDischargeAck(TCPP0203_Object_t *pObj, uint8_t *pVConnDischargeAck);
+int32_t TCPP0203_GetOCPVConnFlag(TCPP0203_Object_t *pObj, uint8_t *pOCPVConnFlag);
+int32_t TCPP0203_GetOCPVBusFlag(TCPP0203_Object_t *pObj, uint8_t *pGetOCPVBusFlag);
+int32_t TCPP0203_GetOVPVBusFlag(TCPP0203_Object_t *pObj, uint8_t *pOVPVBusFlag);
+int32_t TCPP0203_GetOVPCCFlag(TCPP0203_Object_t *pObj, uint8_t *pOVPCCFlag);
+int32_t TCPP0203_GetOTPFlag(TCPP0203_Object_t *pObj, uint8_t *pOTPFlag);
+int32_t TCPP0203_GetVBusOkFlag(TCPP0203_Object_t *pObj, uint8_t *pVBusOkFlag);
+int32_t TCPP0203_ReadTCPPType(TCPP0203_Object_t *pObj, uint8_t *pTCPPType);
+int32_t TCPP0203_ReadVCONNPower(TCPP0203_Object_t *pObj, uint8_t *pVCONNPower);
+int32_t TCPP0203_WriteCtrlRegister(TCPP0203_Object_t *pObj, uint8_t *pAckRegister);
+int32_t TCPP0203_ReadAckRegister(TCPP0203_Object_t *pObj, uint8_t *pAckRegister);
+int32_t TCPP0203_ReadFlagRegister(TCPP0203_Object_t *pObj, uint8_t *pFlagRegister);
+
+/**
+ * @}
+ */
+
+/* TCPP02/03 Type-C port protection driver structure */
+extern TCPP0203_Drv_t TCPP0203_Driver;
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* TCPP0203_H */
+
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/tcpp0203/tcpp0203_reg.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/tcpp0203/tcpp0203_reg.c
new file mode 100644
index 00000000..56425c44
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/tcpp0203/tcpp0203_reg.c
@@ -0,0 +1,75 @@
+/**
+ ******************************************************************************
+ * @file tcpp0203_reg.c
+ * @author MCD Application Team
+ * @brief This file provides unitary register function to control the TCPP02-03
+ * Type-C port protection driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tcpp0203_reg.h"
+
+/** @addtogroup BSP
+ * @{
+ */
+
+/** @addtogroup Components
+ * @{
+ */
+
+/** @addtogroup TCPP0203
+ * @brief This file provides a set of functions needed to drive the
+ * TCPP02/03 Type-C port protection codec.
+ * @{
+ */
+
+/************** Generic Function *******************/
+/*******************************************************************************
+ * Function Name : tcpp0203_read_reg
+ * Description : Generic Reading function. It must be fulfilled with either
+ * I2C or SPI reading functions
+ * Input : Register Address, length of buffer
+ * Output : data Read
+ *******************************************************************************/
+int32_t tcpp0203_read_reg(TCPP0203_ctx_t *ctx, uint8_t reg, uint8_t *data, uint8_t length)
+{
+ return ctx->ReadReg(ctx->handle, reg, data, length);
+}
+
+/*******************************************************************************
+ * Function Name : tcpp0203_write_reg
+ * Description : Generic Writing function. It must be fulfilled with either
+ * I2C or SPI writing function
+ * Input : Register Address, data to be written, length of buffer
+ * Output : None
+ *******************************************************************************/
+int32_t tcpp0203_write_reg(TCPP0203_ctx_t *ctx, uint8_t reg, uint8_t *data, uint8_t length)
+{
+ return ctx->WriteReg(ctx->handle, reg, data, length);
+}
+
+/******************************************************************************/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/tcpp0203/tcpp0203_reg.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/tcpp0203/tcpp0203_reg.h
new file mode 100644
index 00000000..ef27482b
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/tcpp0203/tcpp0203_reg.h
@@ -0,0 +1,100 @@
+/**
+ ******************************************************************************
+ * @file tcpp0203_reg.h
+ * @author MCD Application Team
+ * @brief Header of tcpp0203_reg.c
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef TCPP0203_REG_H
+#define TCPP0203_REG_H
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+/** @addtogroup BSP
+ * @{
+ */
+
+/** @addtogroup Component
+ * @{
+ */
+
+/** @addtogroup TCPP0203
+ * @{
+ */
+
+
+/** @defgroup TCPP0203_Exported_Constants TCPP0203 Exported Constants
+ * @{
+ */
+/******************************************************************************/
+/****************************** REGISTER MAPPING ******************************/
+/******************************************************************************/
+#define TCPP0203_WRITE_REG 0x00U
+#define TCPP0203_PROG_CTRL TCPP0203_WRITE_REG
+#define TCPP0203_READ_REG1 0x01U
+#define TCPP0203_ACK_REG TCPP0203_READ_REG1
+#define TCPP0203_READ_REG2 0x02U
+#define TCPP0203_FLAG_REG TCPP0203_READ_REG2
+
+/**
+ * @}
+ */
+
+/************** Generic Function *******************/
+
+typedef int32_t (*TCPP0203_Write_Func)(void *, uint8_t, uint8_t *, uint8_t);
+typedef int32_t (*TCPP0203_Read_Func)(void *, uint8_t, uint8_t *, uint8_t);
+
+typedef struct
+{
+ TCPP0203_Write_Func WriteReg;
+ TCPP0203_Read_Func ReadReg;
+ void *handle;
+} TCPP0203_ctx_t;
+
+/*******************************************************************************
+ * Register : Generic - All
+ * Address : Generic - All
+ * Bit Group Name: None
+ * Permission : W
+ *******************************************************************************/
+int32_t tcpp0203_write_reg(TCPP0203_ctx_t *ctx, uint8_t reg, uint8_t *data, uint8_t length);
+int32_t tcpp0203_read_reg(TCPP0203_ctx_t *ctx, uint8_t reg, uint8_t *data, uint8_t length);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* TCPP0203_REG_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/veml6030/veml6030.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/veml6030/veml6030.c
new file mode 100644
index 00000000..fd672dba
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/veml6030/veml6030.c
@@ -0,0 +1,1019 @@
+/**
+ ******************************************************************************
+ * @file veml6030.c
+ * @author MCD Application Team
+ * @brief VEML6030 driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved. © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+
+/** @addtogroup BSP
+ * @{
+ */
+
+/** @addtogroup Components
+ * @{
+ */
+
+/** @addtogroup VEML6030
+ * @{
+ */
+
+/** @defgroup VEML6030_Exported_Types
+ * @{
+ */
+
+typedef int32_t (*VEML6030_Init_Func)(void);
+typedef int32_t (*VEML6030_DeInit_Func)(void);
+typedef int32_t (*VEML6030_GetTick_Func)(void);
+typedef int32_t (*VEML6030_Delay_Func)(uint32_t);
+typedef int32_t (*VEML6030_WriteReg_Func)(uint16_t, uint16_t, uint8_t*, uint16_t);
+typedef int32_t (*VEML6030_ReadReg_Func)(uint16_t, uint16_t, uint8_t*, uint16_t);
+typedef int32_t (*VEML6030_IsReady_Func)(uint16_t, uint32_t);
+
+typedef struct
+{
+ VEML6030_Init_Func Init;
+ VEML6030_DeInit_Func DeInit;
+ uint16_t ReadAddress;
+ uint16_t WriteAddress;
+ VEML6030_IsReady_Func IsReady;
+ VEML6030_WriteReg_Func WriteReg;
+ VEML6030_ReadReg_Func ReadReg;
+ VEML6030_GetTick_Func GetTick;
+} VEML6030_IO_t;
+
+
+typedef struct
+{
+ VEML6030_IO_t IO;
+ veml6030_ctx_t Ctx;
+ uint8_t IsInitialized;
+ uint8_t IsContinuous;
+ uint8_t IsStarted;
+} VEML6030_Object_t;
+
+
+typedef struct
+{
+ uint8_t NumberOfChannels; /*!< Max: LIGHT_SENSOR_MAX_CHANNELS */
+ uint8_t FlickerDetection; /*!< Not available: 0, Available: 1 */
+ uint8_t Autogain; /*!< Not available: 0, Available: 1 */
+} VEML6030_Capabilities_t;
+
+typedef struct
+{
+ int32_t (*Init)(VEML6030_Object_t *);
+ int32_t (*DeInit)(VEML6030_Object_t *);
+ int32_t (*ReadID)(VEML6030_Object_t *, uint32_t *);
+ int32_t (*GetCapabilities)(VEML6030_Object_t *, VEML6030_Capabilities_t *);
+ int32_t (*SetExposureTime)(VEML6030_Object_t *, uint32_t);
+ int32_t (*GetExposureTime)(VEML6030_Object_t *, uint32_t *);
+ int32_t (*SetGain)(VEML6030_Object_t *, uint8_t, uint32_t);
+ int32_t (*GetGain)(VEML6030_Object_t *, uint8_t, uint32_t *);
+ int32_t (*SetInterMeasurementTime)(VEML6030_Object_t *, uint32_t);
+ int32_t (*GetInterMeasurementTime)(VEML6030_Object_t *, uint32_t *);
+ int32_t (*Start)(VEML6030_Object_t *, uint32_t);
+ int32_t (*Stop)(VEML6030_Object_t *);
+ int32_t (*StartFlicker)(VEML6030_Object_t *, uint8_t, uint8_t);
+ int32_t (*StopFlicker)(VEML6030_Object_t *);
+ int32_t (*GetValues)(VEML6030_Object_t *, uint32_t *);
+ int32_t (*SetControlMode)(VEML6030_Object_t *, uint32_t, uint32_t);
+}VEML6030_Drv_t;
+
+/**
+ * @}
+ */
+
+/** @defgroup VEML6030_Exported_Constants
+ * @{
+ */
+
+/* VEML6030 error codes */
+#define VEML6030_OK (0)
+#define VEML6030_ERROR (-1)
+#define VEML6030_INVALID_PARAM (-2)
+
+/* softowre ID */
+#define VEML6030_ID (0x6030U)
+
+/**
+ * @brief VEML6030 Features Parameters
+ */
+
+/* VEML6030 Channel */
+#define VEML6030_ALS_CHANNEL (0U)
+#define VEML6030_WHITE_CHANNEL (1U)
+#define VEML6030_MAX_CHANNELS (2U) /*!< Number of channels of the device */
+
+/* VEML6030 capture modes */
+#define VEML6030_MODE_CONTINUOUS (1U)
+
+/* VEML6030 interrupt */
+#define VEML6030_INT_TH_NONE 0U
+#define VEML6030_INT_TH_LOW 1U
+#define VEML6030_INT_TH_HIGH 2U
+
+ /* VEML6030 I2C ADDRESS */
+#define VEML6030_I2C_READ_ADD 0x21
+#define VEML6030_I2C_WRITE_ADD 0x20
+
+/* VEML6030 Refresh Time (Intermesurment Time) definitions */
+/* VEML6030’s refresh time can be determined by Power Saving Mode (PSM) and the Integration Time (ALS_IT) */
+/* The tow first LSB bits of each refresh time first byte definition represent the integration time */
+/* The tow first MSB bits of each refresh time first byte definition represent the Power saving Mode */
+#define VEML6030_REFRESH_TIME_600 (0x00U)
+#define VEML6030_REFRESH_TIME_700 (0x01U)
+#define VEML6030_REFRESH_TIME_900 (0x02U)
+#define VEML6030_REFRESH_TIME_1100 (0x04U)
+#define VEML6030_REFRESH_TIME_1200 (0x05U)
+#define VEML6030_REFRESH_TIME_1300 (0x03U)
+#define VEML6030_REFRESH_TIME_1400 (0x06U)
+#define VEML6030_REFRESH_TIME_1800 (0x07U)
+#define VEML6030_REFRESH_TIME_2100 (0x08U)
+#define VEML6030_REFRESH_TIME_2200 (0x09U)
+#define VEML6030_REFRESH_TIME_2400 (0x0AU)
+#define VEML6030_REFRESH_TIME_2800 (0x0BU)
+#define VEML6030_REFRESH_TIME_4100 (0x0CU)
+#define VEML6030_REFRESH_TIME_4200 (0x0DU)
+#define VEML6030_REFRESH_TIME_4400 (0x0EU)
+#define VEML6030_REFRESH_TIME_4800 (0x0FU)
+
+/* driver structure */
+extern VEML6030_Drv_t VEML6030_Driver;
+
+/**
+ * @}
+ */
+
+/** @addtogroup VEML6030_Exported_Functions VEML6030 Exported Functions
+ * @{
+ */
+
+ int32_t VEML6030_RegisterBusIO(VEML6030_Object_t *pObj, VEML6030_IO_t *pIO);
+ int32_t VEML6030_Init(VEML6030_Object_t *pObj);
+ int32_t VEML6030_DeInit(VEML6030_Object_t *pObj);
+ int32_t VEML6030_ReadID(VEML6030_Object_t *pObj, uint32_t *pId);
+ int32_t VEML6030_SetExposureTime(VEML6030_Object_t *pObj, uint32_t ExposureTime);
+ int32_t VEML6030_GetExposureTime(VEML6030_Object_t *pObj, uint32_t *pExposureTime);
+ int32_t VEML6030_GetCapabilities(VEML6030_Object_t *pObj, VEML6030_Capabilities_t *pCapabilities);
+ int32_t VEML6030_SetGain(VEML6030_Object_t *pObj, uint8_t Channel, uint32_t Gain);
+ int32_t VEML6030_GetGain(VEML6030_Object_t *pObj, uint8_t Channel, uint32_t *Gain);
+ int32_t VEML6030_SetInterMeasurementTime(VEML6030_Object_t *pObj, uint32_t InterMeasurementTime);
+ int32_t VEML6030_GetInterMeasurementTime(VEML6030_Object_t *pObj, uint32_t *InterMeasurementTime);
+ int32_t VEML6030_Start(VEML6030_Object_t *pObj, uint32_t);
+ int32_t VEML6030_Stop(VEML6030_Object_t *pObj);
+ int32_t VEML6030_GetValues(VEML6030_Object_t *, uint32_t *Values);
+ int32_t VEML6030_StartFlicker(VEML6030_Object_t *pObj, uint8_t Channel, uint8_t OutputMode);
+ int32_t VEML6030_StopFlicker(VEML6030_Object_t *pObj);
+ int32_t VEML6030_SetControlMode(VEML6030_Object_t *pObj, uint32_t ControlMode, uint32_t Value);
+
+ int32_t VEML6030_SetPowerSavingMode(VEML6030_Object_t *pObj, uint32_t PowerMode);
+ int32_t VEML6030_GetPowerSavingMode(VEML6030_Object_t *pObj, uint32_t *pPowerMode);
+ int32_t VEML6030_SetPersistence(VEML6030_Object_t *pObj, uint32_t Persistence);
+ int32_t VEML6030_GetPersistence(VEML6030_Object_t *pObj, uint32_t *Persistence);
+ int32_t VEML6030_GetWhiteValues(VEML6030_Object_t *pObj, uint32_t *Values);
+ /* interrupt Mangement Functions */
+ int32_t VEML6030_SetHighThreshold(VEML6030_Object_t *pObj , uint16_t Threshold);
+ int32_t VEML6030_GetHighThreshold(VEML6030_Object_t *pObj , uint32_t *Threshold);
+ int32_t VEML6030_SetLowThreshold(VEML6030_Object_t *pObj , uint16_t Threshold);
+ int32_t VEML6030_GetLowThreshold(VEML6030_Object_t *pObj , uint32_t *Threshold);
+ int32_t VEML6030_GetIntStatus(VEML6030_Object_t *pObj,uint32_t *status);
+ int32_t VEML6030_Disable_IT(VEML6030_Object_t *pObj);
+ int32_t VEML6030_Enable_IT(VEML6030_Object_t *pObj);
+
+/**
+ * @}
+ */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* VEML6030_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\ No newline at end of file
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/veml6030/veml6030_reg.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/veml6030/veml6030_reg.c
new file mode 100644
index 00000000..2d90cc52
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/BSP/Components/veml6030/veml6030_reg.c
@@ -0,0 +1,90 @@
+/*
+ ******************************************************************************
+ * @file veml6030_reg.c
+ * @author MCD Application Team
+ * @brief VEML6030 driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved. © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+#include
+
+/* VEML6030 registers */
+#define VEML6030_REG_ALS_CONF 0x00
+#define VEML6030_REG_ALS_WH 0x01
+#define VEML6030_REG_ALS_WL 0x02
+#define VEML6030_REG_POWER_SAVING 0x03
+#define VEML6030_REG_ALS 0x04
+#define VEML6030_REG_WHITE 0x05
+#define VEML6030_REG_ALS_INT 0x06
+
+/* ALS gain constants */
+#define VEML6030_CONF_GAIN_1 (0x00 << 11)
+#define VEML6030_CONF_GAIN_2 (0x01 << 11)
+#define VEML6030_CONF_GAIN_1_8 (0x02 << 11)
+#define VEML6030_CONF_GAIN_1_4 (0x03 << 11)
+#define VEML6030_GAIN_MASK (uint16_t)(0x1800)
+
+/* ALS integration times (ms) */
+#define VEML6030_CONF_IT25 (0x0C << 6)
+#define VEML6030_CONF_IT50 (0x08 << 6)
+#define VEML6030_CONF_IT100 (0x00 << 6)
+#define VEML6030_CONF_IT200 (0x01 << 6)
+#define VEML6030_CONF_IT400 (0x02 << 6)
+#define VEML6030_CONF_IT800 (0x03 << 6)
+/* ALS integration times - all bits */
+#define VEML6030_CONF_IT_MASK (0x0f << 6)
+
+/* Register 0x0: ALS_CONF */
+/* ALS persistent protect number */
+#define VEML6030_CONF_PERS_1 (0x00 << 4)
+#define VEML6030_CONF_PERS_2 (0x01 << 4)
+#define VEML6030_CONF_PERS_4 (0x02 << 4)
+#define VEML6030_CONF_PERS_8 (0x03 << 4)
+#define VEML6030_PERS_MASK (uint16_t)(0x0030)
+/* ALS interrupt enable*/
+#define VEML6030_CONF_IT_ENABLE (0x01 << 1)
+/* ALS shutdown setting */
+#define VEML6030_CONF_SHUTDOWN 0x01
+
+/* Register 0x3: POWER SAVING */
+/* Power saving modes */
+#define VEML6030_POWER_SAVING_PSM_1 (0x00 << 1)
+#define VEML6030_POWER_SAVING_PSM_2 (0x01 << 1)
+#define VEML6030_POWER_SAVING_PSM_3 (0x02 << 1)
+#define VEML6030_POWER_SAVING_PSM_4 (0x03 << 1)
+#define VEML6030_POWER_SAVING_ENABLE (0x01U)
+#define VEML6030_POWER_SAVING_DISABLE (0x00U)
+
+/************** Generic Function *******************/
+
+typedef int32_t (*VEML6030_Write_Func)(void *, uint16_t, uint8_t *, uint16_t);
+typedef int32_t (*VEML6030_Read_Func)(void *, uint16_t, uint8_t *, uint16_t);
+
+typedef struct
+{
+ VEML6030_Write_Func WriteReg;
+ VEML6030_Read_Func ReadReg;
+ void *handle;
+} veml6030_ctx_t;
+
+/*******************************************************************************
+ * Register : Generic - All
+ * Address : Generic - All
+ * Bit Group Name: None
+ * Permission : W
+ *******************************************************************************/
+int32_t veml6030_write_reg(veml6030_ctx_t *ctx, uint16_t reg, uint16_t *pdata, uint16_t length);
+int32_t veml6030_read_reg(veml6030_ctx_t *ctx, uint16_t reg, uint16_t *pdata, uint16_t length);
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*VEML6030_REGS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/ARM.CMSIS.pdsc b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/ARM.CMSIS.pdsc
new file mode 100644
index 00000000..90f58457
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/ARM.CMSIS.pdsc
@@ -0,0 +1,4073 @@
+
+
+
+ CMSIS
+ CMSIS (Cortex Microcontroller Software Interface Standard)
+ ARM
+
+ http://www.keil.com/pack/
+
+
+
+ CMSIS-Core(M): 5.3.0 (see revision history for details)
+ - Added provisions for compiler-independent C startup code.
+ CMSIS-Core(A): 1.1.4 (see revision history for details)
+ - Fixed __FPU_Enable.
+ CMSIS-DSP: 1.7.0 (see revision history for details)
+ - New Neon versions of f32 functions
+ - Python wrapper
+ - Preliminary cmake build
+ - Compilation flags for FFTs
+ - Changes to arm_math.h
+ CMSIS-NN: 1.2.0 (see revision history for details)
+ - New function for depthwise convolution with asymmetric quantization.
+ - New support functions for requantization.
+ CMSIS-RTOS:
+ - RTX 4.82.0 (updated provisions for Arm Compiler 6 when using Cortex-M0/M0+)
+ CMSIS-RTOS2:
+ - RTX 5.5.1 (see revision history for details)
+ CMSIS-Driver: 2.7.1
+ - WiFi Interface API 1.0.0
+ Devices:
+ - Generalized C startup code for all Cortex-M familiy devices.
+ - Updated Cortex-A default memory regions and MMU configurations
+ - Moved Cortex-A memory and system config files to avoid include path issues
+
+
+ The following folders are deprecated
+ - CMSIS/Include/ (superseded by CMSIS/DSP/Include/ and CMSIS/Core/Include/)
+
+ CMSIS-Core(M): 5.2.1 (see revision history for details)
+ - Fixed compilation issue in cmsis_armclang_ltm.h
+
+
+ The following folders have been removed:
+ - CMSIS/Lib/ (superseded by CMSIS/DSP/Lib/)
+ - CMSIS/DSP_Lib/ (superseded by CMSIS/DSP/)
+ The following folders are deprecated
+ - CMSIS/Include/ (superseded by CMSIS/DSP/Include/ and CMSIS/Core/Include/)
+
+ CMSIS-Core(M): 5.2.0 (see revision history for details)
+ - Reworked Stack/Heap configuration for ARM startup files.
+ - Added Cortex-M35P device support.
+ - Added generic Armv8.1-M Mainline device support.
+ CMSIS-Core(A): 1.1.3 (see revision history for details)
+ CMSIS-DSP: 1.6.0 (see revision history for details)
+ - reworked DSP library source files
+ - reworked DSP library documentation
+ - Changed DSP folder structure
+ - moved DSP libraries to folder ./DSP/Lib
+ - ARM DSP Libraries are built with ARMCLANG
+ - Added DSP Libraries Source variant
+ CMSIS-RTOS2:
+ - RTX 5.5.0 (see revision history for details)
+ CMSIS-Driver: 2.7.0
+ - Added WiFi Interface API 1.0.0-beta
+ - Added components for project specific driver implementations
+ CMSIS-Pack: 1.6.0 (see revision history for details)
+ Devices:
+ - Added Cortex-M35P and ARMv81MML device templates.
+ - Fixed C-Startup Code for GCC (aligned with other compilers)
+ Utilities:
+ - SVDConv 3.3.25
+ - PackChk 1.3.82
+
+
+ Aligned pack structure with repository.
+ The following folders are deprecated:
+ - CMSIS/Include/
+ - CMSIS/DSP_Lib/
+
+ CMSIS-Core(M): 5.1.2 (see revision history for details)
+ - Added Cortex-M1 support (beta).
+ CMSIS-Core(A): 1.1.2 (see revision history for details)
+ CMSIS-NN: 1.1.0
+ - Added new math functions.
+ CMSIS-RTOS2:
+ - API 2.1.3 (see revision history for details)
+ - RTX 5.4.0 (see revision history for details)
+ * Updated exception handling on Cortex-A
+ CMSIS-Driver:
+ - Flash Driver API V2.2.0
+ Utilities:
+ - SVDConv 3.3.21
+ - PackChk 1.3.71
+
+
+ Updated Arm company brand.
+ CMSIS-Core(M): 5.1.1 (see revision history for details)
+ CMSIS-Core(A): 1.1.1 (see revision history for details)
+ CMSIS-DAP: 2.0.0 (see revision history for details)
+ CMSIS-NN: 1.0.0
+ - Initial contribution of the bare metal Neural Network Library.
+ CMSIS-RTOS2:
+ - RTX 5.3.0 (see revision history for details)
+ - OS Tick API 1.0.1
+
+
+ CMSIS-Core(M): 5.1.0 (see revision history for details)
+ - Added MPU Functions for ARMv8-M for Cortex-M23/M33.
+ - Added compiler_iccarm.h to replace compiler_iar.h shipped with the compiler.
+ CMSIS-Core(A): 1.1.0 (see revision history for details)
+ - Added compiler_iccarm.h.
+ - Added additional access functions for physical timer.
+ CMSIS-DAP: 1.2.0 (see revision history for details)
+ CMSIS-DSP: 1.5.2 (see revision history for details)
+ CMSIS-Driver: 2.6.0 (see revision history for details)
+ - CAN Driver API V1.2.0
+ - NAND Driver API V2.3.0
+ CMSIS-RTOS:
+ - RTX: added variant for Infineon XMC4 series affected by PMU_CM.001 errata.
+ CMSIS-RTOS2:
+ - API 2.1.2 (see revision history for details)
+ - RTX 5.2.3 (see revision history for details)
+ Devices:
+ - Added GCC startup and linker script for Cortex-A9.
+ - Added device ARMCM0plus_MPU for Cortex-M0+ with MPU.
+ - Added IAR startup code for Cortex-A9
+
+
+ CMSIS-RTOS2:
+ - RTX 5.2.1 (see revision history for details)
+
+
+ CMSIS-Core(M): 5.0.2 (see revision history for details)
+ - Changed Version Control macros to be core agnostic.
+ - Added MPU Functions for ARMv7-M for Cortex-M0+/M3/M4/M7.
+ CMSIS-Core(A): 1.0.0 (see revision history for details)
+ - Initial release
+ - IRQ Controller API 1.0.0
+ CMSIS-Driver: 2.05 (see revision history for details)
+ - All typedefs related to status have been made volatile.
+ CMSIS-RTOS2:
+ - API 2.1.1 (see revision history for details)
+ - RTX 5.2.0 (see revision history for details)
+ - OS Tick API 1.0.0
+ CMSIS-DSP: 1.5.2 (see revision history for details)
+ - Fixed GNU Compiler specific diagnostics.
+ CMSIS-Pack: 1.5.0 (see revision history for details)
+ - added System Description File (*.SDF) Format
+ CMSIS-Zone: 0.0.1 (Preview)
+ - Initial specification draft
+
+
+ Package Description:
+ - added taxonomy for Cclass RTOS
+ CMSIS-RTOS2:
+ - API 2.1 (see revision history for details)
+ - RTX 5.1.0 (see revision history for details)
+ CMSIS-Core: 5.0.1 (see revision history for details)
+ - Added __PACKED_STRUCT macro
+ - Added uVisior support
+ - Updated cmsis_armcc.h: corrected macro __ARM_ARCH_6M__
+ - Updated template for secure main function (main_s.c)
+ - Updated template for Context Management for ARMv8-M TrustZone (tz_context.c)
+ CMSIS-DSP: 1.5.1 (see revision history for details)
+ - added ARMv8M DSP libraries.
+ CMSIS-Pack:1.4.9 (see revision history for details)
+ - added Pack Index File specification and schema file
+
+
+ Changed open source license to Apache 2.0
+ CMSIS_Core:
+ - Added support for Cortex-M23 and Cortex-M33.
+ - Added ARMv8-M device configurations for mainline and baseline.
+ - Added CMSE support and thread context management for TrustZone for ARMv8-M
+ - Added cmsis_compiler.h to unify compiler behaviour.
+ - Updated function SCB_EnableICache (for Cortex-M7).
+ - Added functions: NVIC_GetEnableIRQ, SCB_GetFPUType
+ CMSIS-RTOS:
+ - bug fix in RTX 4.82 (see revision history for details)
+ CMSIS-RTOS2:
+ - new API including compatibility layer to CMSIS-RTOS
+ - reference implementation based on RTX5
+ - supports all Cortex-M variants including TrustZone for ARMv8-M
+ CMSIS-SVD:
+ - reworked SVD format documentation
+ - removed SVD file database documentation as SVD files are distributed in packs
+ - updated SVDConv for Win32 and Linux
+ CMSIS-DSP:
+ - Moved DSP libraries from CMSIS/DSP/Lib to CMSIS/Lib.
+ - Added DSP libraries build projects to CMSIS pack.
+
+
+ - CMSIS-Core 4.30.0 (see revision history for details)
+ - CMSIS-DAP 1.1.0 (unchanged)
+ - CMSIS-Driver 2.04.0 (see revision history for details)
+ - CMSIS-DSP 1.4.7 (no source code change [still labeled 1.4.5], see revision history for details)
+ - CMSIS-Pack 1.4.1 (see revision history for details)
+ - CMSIS-RTOS 4.80.0 Restored time delay parameter 'millisec' old behavior (prior V4.79) for software compatibility. (see revision history for details)
+ - CMSIS-SVD 1.3.1 (see revision history for details)
+
+
+ - CMSIS-Core 4.20 (see revision history for details)
+ - CMSIS-DSP 1.4.6 (no source code change [still labeled 1.4.5], see revision history for details)
+ - CMSIS-Pack 1.4.0 (adding memory attributes, algorithm style)
+ - CMSIS-Driver 2.03.0 (adding CAN [Controller Area Network] API)
+ - CMSIS-RTOS
+ -- API 1.02 (unchanged)
+ -- RTX 4.79 (see revision history for details)
+ - CMSIS-SVD 1.3.0 (see revision history for details)
+ - CMSIS-DAP 1.1.0 (extended with SWO support)
+
+
+ - CMSIS-Core 4.10 (Cortex-M7 extended Cache Maintenance functions)
+ - CMSIS-DSP 1.4.5 (see revision history for details)
+ - CMSIS-Driver 2.02 (adding SAI (Serial Audio Interface) API)
+ - CMSIS-Pack 1.3.3 (Semantic Versioning, Generator extensions)
+ - CMSIS-RTOS
+ -- API 1.02 (unchanged)
+ -- RTX 4.78 (see revision history for details)
+ - CMSIS-SVD 1.2 (unchanged)
+
+
+ Adding Cortex-M7 support
+ - CMSIS-Core 4.00 (Cortex-M7 support, corrected C++ include guards in core header files)
+ - CMSIS-DSP 1.4.4 (Cortex-M7 support and corrected out of bound issues)
+ - CMSIS-Pack 1.3.1 (Cortex-M7 updates, clarification, corrected batch files in Tutorial)
+ - CMSIS-SVD 1.2 (Cortex-M7 extensions)
+ - CMSIS-RTOS RTX 4.75 (see revision history for details)
+
+
+ - fixed conditions preventing the inclusion of the DSP library in projects for Infineon XMC4000 series devices
+
+
+ - CMSIS-Driver 2.02 (incompatible update)
+ - CMSIS-Pack 1.3 (see revision history for details)
+ - CMSIS-DSP 1.4.2 (unchanged)
+ - CMSIS-Core 3.30 (unchanged)
+ - CMSIS-RTOS RTX 4.74 (unchanged)
+ - CMSIS-RTOS API 1.02 (unchanged)
+ - CMSIS-SVD 1.10 (unchanged)
+ PACK:
+ - removed G++ specific files from PACK
+ - added Component Startup variant "C Startup"
+ - added Pack Checking Utility
+ - updated conditions to reflect tool-chain dependency
+ - added Taxonomy for Graphics
+ - updated Taxonomy for unified drivers from "Drivers" to "CMSIS Drivers"
+
+
+
+ - CMSIS-RTOS 4.74 (see revision history for details)
+ - PACK Extensions (Boards, Device Features, Flash Programming, Generators, Configuration Wizard). Schema version 1.1.
+
+
+
+
+
+
+
+
+ Software components for audio processing
+ Generic Interfaces for Evaluation and Development Boards
+ Drivers that support an external component available on an evaluation board
+ Compiler Software Extensions
+ Cortex Microcontroller Software Interface Components
+ Unified Device Drivers compliant to CMSIS-Driver Specifications
+ Startup, System Setup
+ Data exchange or data formatter
+ Drivers that support an extension board or shield
+ File Drive Support and File System
+ IoT cloud client connector
+ IoT specific software utility
+ Graphical User Interface
+ Network Stack using Internet Protocols
+ Real-time Operating System
+ Encryption for secure communication or storage
+ Universal Serial Bus Stack
+ Generic software utility components
+
+
+
+
+
+
+The Cortex-M0 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
+- simple, easy-to-use programmers model
+- highly efficient ultra-low power operation
+- excellent code density
+- deterministic, high-performance interrupt handling
+- upward compatibility with the rest of the Cortex-M processor family.
+
+
+
+
+
+
+
+
+
+The Cortex-M0+ processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
+- simple, easy-to-use programmers model
+- highly efficient ultra-low power operation
+- excellent code density
+- deterministic, high-performance interrupt handling
+- upward compatibility with the rest of the Cortex-M processor family.
+
+
+
+
+
+
+
+
+
+
+
+
+
+The ARM Cortex-M1 FPGA processor is intended for deeply embedded applications that require a small processor integrated into an FPGA.
+The ARM Cortex-M1 processor implements the ARMv6-M architecture profile.
+
+
+
+
+
+
+
+
+
+The Cortex-M3 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
+- simple, easy-to-use programmers model
+- highly efficient ultra-low power operation
+- excellent code density
+- deterministic, high-performance interrupt handling
+- upward compatibility with the rest of the Cortex-M processor family.
+
+
+
+
+
+
+
+
+
+The Cortex-M4 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
+- simple, easy-to-use programmers model
+- highly efficient ultra-low power operation
+- excellent code density
+- deterministic, high-performance interrupt handling
+- upward compatibility with the rest of the Cortex-M processor family.
+
+
+
+
+
+
+
+
+
+
+
+
+The Cortex-M7 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
+- simple, easy-to-use programmers model
+- highly efficient ultra-low power operation
+- excellent code density
+- deterministic, high-performance interrupt handling
+- upward compatibility with the rest of the Cortex-M processor family.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+The Arm Cortex-M23 is based on the Armv8-M baseline architecture.
+It is the smallest and most energy efficient Arm processor with Arm TrustZone technology.
+Cortex-M23 is the ideal processor for constrained embedded applications requiring efficient security.
+
+
+
+
+
+
+
+
+
+
+
+
+
+The Arm Cortex-M33 is the most configurable of all Cortex-M processors. It is a full featured microcontroller
+class processor based on the Armv8-M mainline architecture with Arm TrustZone security.
+
+
+
+
+ no DSP Instructions, no Floating Point Unit, no TrustZone
+
+
+
+
+
+ no DSP Instructions, no Floating Point Unit, TrustZone
+
+
+
+
+
+ DSP Instructions, Single Precision Floating Point Unit, no TrustZone
+
+
+
+
+
+ DSP Instructions, Single Precision Floating Point Unit, TrustZone
+
+
+
+
+
+
+
+
+The Arm Cortex-M35P is the most configurable of all Cortex-M processors. It is a full featured microcontroller
+class processor based on the Armv8-M mainline architecture with Arm TrustZone security designed for a broad range of secure embedded applications.
+
+
+
+
+
+ no DSP Instructions, no Floating Point Unit, no TrustZone
+
+
+
+
+
+ no DSP Instructions, no Floating Point Unit, TrustZone
+
+
+
+
+
+ DSP Instructions, Single Precision Floating Point Unit, no TrustZone
+
+
+
+
+
+ DSP Instructions, Single Precision Floating Point Unit, TrustZone
+
+
+
+
+
+
+
+The Arm SC000 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of secure embedded applications. It offers significant benefits to developers, including:
+- simple, easy-to-use programmers model
+- highly efficient ultra-low power operation
+- excellent code density
+- deterministic, high-performance interrupt handling
+
+
+
+
+
+
+
+
+
+The ARM SC300 processor is an entry-level 32-bit ARM Cortex processor designed for a broad range of secure embedded applications. It offers significant benefits to developers, including:
+- simple, easy-to-use programmers model
+- highly efficient ultra-low power operation
+- excellent code density
+- deterministic, high-performance interrupt handling
+
+
+
+
+
+
+
+
+
+
+Armv8-M Baseline based device with TrustZone
+
+
+
+
+
+
+
+
+
+
+Armv8-M Mainline based device with TrustZone
+
+
+
+
+ no DSP Instructions, no Floating Point Unit, TrustZone
+
+
+
+
+
+ DSP Instructions, no Floating Point Unit, TrustZone
+
+
+
+
+
+ no DSP Instructions, Single Precision Floating Point Unit, TrustZone
+
+
+
+
+
+ DSP Instructions, Single Precision Floating Point Unit, TrustZone
+
+
+
+
+
+ no DSP Instructions, Double Precision Floating Point Unit, TrustZone
+
+
+
+
+
+ DSP Instructions, Double Precision Floating Point Unit, TrustZone
+
+
+
+
+
+
+
+
+Armv8.1-M Mainline based device with TrustZone and MVE
+
+
+
+
+ Double Precision Vector Extensions, DSP Instructions, Double Precision Floating Point Unit, TrustZone
+
+
+
+
+
+
+
+The Arm Cortex-A5 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full
+virtual memory capabilities. The Cortex-A5 processor implements the Armv7-A architecture profile and can execute 32-bit
+Arm instructions and 16-bit and 32-bit Thumb instructions. The Cortex-A5 is the smallest member of the Cortex-A processor family.
+
+
+
+
+
+
+
+
+
+The Cortex-A7 MPCore processor is a high-performance, low-power processor that implements the Armv7-A architecture.
+The Cortex-A7 MPCore processor has one to four processors in a single multiprocessor device with a L1 cache subsystem,
+an optional integrated GIC, and an optional L2 cache controller.
+
+
+
+
+
+
+
+
+
+The Cortex-A9 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full virtual memory capabilities.
+The Cortex-A9 processor implements the Armv7-A architecture and runs 32-bit Arm instructions, 16-bit and 32-bit Thumb instructions,
+and 8-bit Java bytecodes in Jazelle state.
+
+
+
+
+
+
+
+
+
+
+
+ Device interrupt controller interface
+
+
+
+
+ RTOS Kernel system tick timer interface
+
+
+
+
+
+ CMSIS-RTOS API for Cortex-M, SC000, and SC300
+
+
+
+
+ CMSIS-RTOS API for Cortex-M, SC000, and SC300
+
+
+
+
+
+ USART Driver API for Cortex-M
+
+
+
+
+ SPI Driver API for Cortex-M
+
+
+
+
+ SAI Driver API for Cortex-M
+
+
+
+
+ I2C Driver API for Cortex-M
+
+
+
+
+ CAN Driver API for Cortex-M
+
+
+
+
+ Flash Driver API for Cortex-M
+
+
+
+
+ MCI Driver API for Cortex-M
+
+
+
+
+ NAND Flash Driver API for Cortex-M
+
+
+
+
+ Ethernet MAC and PHY Driver API for Cortex-M
+
+
+
+
+ Ethernet MAC Driver API for Cortex-M
+
+
+
+
+ Ethernet PHY Driver API for Cortex-M
+
+
+
+
+ USB Device Driver API for Cortex-M
+
+
+
+
+ USB Host Driver API for Cortex-M
+
+
+
+
+ WiFi driver
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Armv6-M architecture based device
+
+
+ Armv7-M architecture based device
+
+
+ Armv8-M architecture based device
+
+
+ Armv8-M architecture based device with TrustZone
+
+
+ Armv6_7-M architecture based device
+
+
+ Armv6_7_8-M architecture based device
+
+
+ Armv7-A architecture based device
+
+
+
+
+ Cortex-M0 or Cortex-M0+ or SC000 processor based device
+
+
+ Cortex-M1
+
+
+ Cortex-M3 or SC300 processor based device
+
+
+ Cortex-M4 processor based device
+
+
+ Cortex-M4 processor based device using Floating Point Unit
+
+
+ Cortex-M7 processor based device
+
+
+ Cortex-M7 processor based device using Floating Point Unit
+
+
+ Cortex-M7 processor based device using Floating Point Unit (SP)
+
+
+ Cortex-M7 processor based device using Floating Point Unit (DP)
+
+
+ Cortex-M23 processor based device
+
+
+ Cortex-M33 processor based device
+
+
+ Cortex-M33 processor based device using Floating Point Unit
+
+
+ Cortex-M35P processor based device
+
+
+ Cortex-M35P processor based device using Floating Point Unit
+
+
+ Armv8-M Baseline processor based device
+
+
+ Armv8-M Mainline processor based device
+
+
+ Armv8-M Mainline processor based device using Floating Point Unit
+
+
+
+ CM33, no DSP, no FPU
+
+
+ CM33, DSP, no FPU
+
+
+ CM33, no DSP, SP FPU
+
+
+ CM33, DSP, SP FPU
+
+
+
+ CM35P, no DSP, no FPU
+
+
+ CM35P, DSP, no FPU
+
+
+ CM35P, no DSP, SP FPU
+
+
+ CM35P, DSP, SP FPU
+
+
+
+ Armv8-M Mainline, no DSP, no FPU
+
+
+ Armv8-M Mainline, DSP, no FPU
+
+
+ Armv8-M Mainline, no DSP, SP FPU
+
+
+ Armv8-M Mainline, DSP, SP FPU
+
+
+
+ Cortex-A5 or Cortex-A9 processor based device
+
+
+
+ Cortex-A7 processor based device
+
+
+
+
+ Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the Arm Compiler 5
+
+
+ Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the Arm Compiler 6
+
+
+
+ Cortex-M0 or Cortex-M0+ or SC000 processor based device for the Arm Compiler
+
+
+ Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the Arm Compiler
+
+
+ Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the Arm Compiler
+
+
+
+ Cortex-M1 based device for the Arm Compiler
+
+
+ Cortex-M1 based device in little endian mode for the Arm Compiler
+
+
+ Cortex-M1 based device in big endian mode for the Arm Compiler
+
+
+
+ Cortex-M3 or SC300 processor based device for the Arm Compiler
+
+
+ Cortex-M3 or SC300 processor based device in little endian mode for the Arm Compiler
+
+
+ Cortex-M3 or SC300 processor based device in big endian mode for the Arm Compiler
+
+
+
+ Cortex-M4 processor based device for the Arm Compiler
+
+
+ Cortex-M4 processor based device in little endian mode for the Arm Compiler
+
+
+ Cortex-M4 processor based device in big endian mode for the Arm Compiler
+
+
+
+ Cortex-M4 processor based device using Floating Point Unit for the Arm Compiler
+
+
+ Cortex-M4 processor based device using Floating Point Unit in little endian mode for the Arm Compiler
+
+
+ Cortex-M4 processor based device using Floating Point Unit in big endian mode for the Arm Compiler
+
+
+
+ Cortex-M7 processor based device for the Arm Compiler
+
+
+ Cortex-M7 processor based device in little endian mode for the Arm Compiler
+
+
+ Cortex-M7 processor based device in big endian mode for the Arm Compiler
+
+
+
+ Cortex-M7 processor based device using Floating Point Unit for the Arm Compiler
+
+
+ Cortex-M7 processor based device using Floating Point Unit in little endian mode for the Arm Compiler
+
+
+ Cortex-M7 processor based device using Floating Point Unit in big endian mode for the Arm Compiler
+
+
+
+ Cortex-M7 processor based device using Floating Point Unit (SP) for the Arm Compiler
+
+
+ Cortex-M7 processor based device using Floating Point Unit (SP) in little endian mode for the Arm Compiler
+
+
+ Cortex-M7 processor based device using Floating Point Unit (SP) in big endian mode for the Arm Compiler
+
+
+
+ Cortex-M7 processor based device using Floating Point Unit (DP) for the Arm Compiler
+
+
+ Cortex-M7 processor based device using Floating Point Unit (DP) in little endian mode for the Arm Compiler
+
+
+ Cortex-M7 processor based device using Floating Point Unit (DP) in big endian mode for the Arm Compiler
+
+
+
+ Cortex-M23 processor based device for the Arm Compiler
+
+
+ Cortex-M23 processor based device in little endian mode for the Arm Compiler
+
+
+
+ Cortex-M33 processor based device for the Arm Compiler
+
+
+ Cortex-M33 processor based device in little endian mode for the Arm Compiler
+
+
+
+ Cortex-M33 processor based device using Floating Point Unit for the Arm Compiler
+
+
+ Cortex-M33 processor based device using Floating Point Unit in little endian mode for the Arm Compiler
+
+
+
+ Cortex-M33 processor, no DSP, no FPU, Arm Compiler
+
+
+ Cortex-M33 processor, DSP, no FPU, Arm Compiler
+
+
+ Cortex-M33 processor, no DSP, SP FPU, Arm Compiler
+
+
+ Cortex-M33 processor, DSP, SP FPU, Arm Compiler
+
+
+ Cortex-M33 processor, little endian, no DSP, no FPU, Arm Compiler
+
+
+ Cortex-M33 processor, little endian, DSP, no FPU, Arm Compiler
+
+
+ Cortex-M33 processor, little endian, no DSP, SP FPU, Arm Compiler
+
+
+ Cortex-M33 processor, little endian, DSP, SP FPU, Arm Compiler
+
+
+
+ Cortex-M35P processor based device for the Arm Compiler
+
+
+ Cortex-M35P processor based device in little endian mode for the Arm Compiler
+
+
+
+ Cortex-M35P processor based device using Floating Point Unit for the Arm Compiler
+
+
+ Cortex-M35P processor based device using Floating Point Unit in little endian mode for the Arm Compiler
+
+
+
+ Cortex-M35P processor, no DSP, no FPU, Arm Compiler
+
+
+ Cortex-M35P processor, DSP, no FPU, Arm Compiler
+
+
+ Cortex-M35P processor, no DSP, SP FPU, Arm Compiler
+
+
+ Cortex-M35P processor, DSP, SP FPU, Arm Compiler
+
+
+ Cortex-M35P processor, little endian, no DSP, no FPU, Arm Compiler
+
+
+ Cortex-M35P processor, little endian, DSP, no FPU, Arm Compiler
+
+
+ Cortex-M35P processor, little endian, no DSP, SP FPU, Arm Compiler
+
+
+ Cortex-M35P processor, little endian, DSP, SP FPU, Arm Compiler
+
+
+
+ Armv8-M Baseline processor based device for the Arm Compiler
+
+
+ Armv8-M Baseline processor based device in little endian mode for the Arm Compiler
+
+
+
+ Armv8-M Mainline processor based device for the Arm Compiler
+
+
+ Armv8-M Mainline processor based device in little endian mode for the Arm Compiler
+
+
+
+ Armv8-M Mainline processor based device using Floating Point Unit for the Arm Compiler
+
+
+ Armv8-M Mainline processor based device using Floating Point Unit in little endian mode for the Arm Compiler
+
+
+
+ Armv8-M Mainline, no DSP, no FPU, Arm Compiler
+
+
+ Armv8-M Mainline, DSP, no FPU, Arm Compiler
+
+
+ Armv8-M Mainline, no DSP, SP FPU, Arm Compiler
+
+
+ Armv8-M Mainline, DSP, SP FPU, Arm Compiler
+
+
+ Armv8-M Mainline, little endian, no DSP, no FPU, Arm Compiler
+
+
+ Armv8-M Mainline, little endian, DSP, no FPU, Arm Compiler
+
+
+ Armv8-M Mainline, little endian, no DSP, SP FPU, Arm Compiler
+
+
+ Armv8-M Mainline, little endian, DSP, SP FPU, Arm Compiler
+
+
+
+
+ Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the GCC Compiler
+
+
+
+ Cortex-M0 or Cortex-M0+ or SC000 processor based device for the GCC Compiler
+
+
+ Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the GCC Compiler
+
+
+ Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the GCC Compiler
+
+
+
+ Cortex-M1 based device for the GCC Compiler
+
+
+ Cortex-M1 based device in little endian mode for the GCC Compiler
+
+
+ Cortex-M1 based device in big endian mode for the GCC Compiler
+
+
+
+ Cortex-M3 or SC300 processor based device for the GCC Compiler
+
+
+ Cortex-M3 or SC300 processor based device in little endian mode for the GCC Compiler
+
+
+ Cortex-M3 or SC300 processor based device in big endian mode for the GCC Compiler
+
+
+
+ Cortex-M4 processor based device for the GCC Compiler
+
+
+ Cortex-M4 processor based device in little endian mode for the GCC Compiler
+
+
+ Cortex-M4 processor based device in big endian mode for the GCC Compiler
+
+
+
+ Cortex-M4 processor based device using Floating Point Unit for the GCC Compiler
+
+
+ Cortex-M4 processor based device using Floating Point Unit in little endian mode for the GCC Compiler
+
+
+ Cortex-M4 processor based device using Floating Point Unit in big endian mode for the GCC Compiler
+
+
+
+ Cortex-M7 processor based device for the GCC Compiler
+
+
+ Cortex-M7 processor based device in little endian mode for the GCC Compiler
+
+
+ Cortex-M7 processor based device in big endian mode for the GCC Compiler
+
+
+
+ Cortex-M7 processor based device using Floating Point Unit for the GCC Compiler
+
+
+ Cortex-M7 processor based device using Floating Point Unit in little endian mode for the GCC Compiler
+
+
+ Cortex-M7 processor based device using Floating Point Unit in big endian mode for the GCC Compiler
+
+
+
+ Cortex-M7 processor based device using Floating Point Unit (SP) for the GCC Compiler
+
+
+ Cortex-M7 processor based device using Floating Point Unit (SP) in little endian mode for the GCC Compiler
+
+
+
+ Cortex-M7 processor based device using Floating Point Unit (DP) for the GCC Compiler
+
+
+ Cortex-M7 processor based device using Floating Point Unit (DP) in little endian mode for the GCC Compiler
+
+
+
+ Cortex-M23 processor based device for the GCC Compiler
+
+
+ Cortex-M23 processor based device in little endian mode for the GCC Compiler
+
+
+
+ Cortex-M33 processor based device for the GCC Compiler
+
+
+ Cortex-M33 processor based device in little endian mode for the GCC Compiler
+
+
+
+ Cortex-M33 processor based device using Floating Point Unit for the GCC Compiler
+
+
+ Cortex-M33 processor based device using Floating Point Unit in little endian mode for the GCC Compiler
+
+
+
+ CM33, no DSP, no FPU, GCC Compiler
+
+
+ CM33, DSP, no FPU, GCC Compiler
+
+
+ CM33, no DSP, SP FPU, GCC Compiler
+
+
+ CM33, DSP, SP FPU, GCC Compiler
+
+
+ CM33, little endian, no DSP, no FPU, GCC Compiler
+
+
+ CM33, little endian, DSP, no FPU, GCC Compiler
+
+
+ CM33, little endian, no DSP, SP FPU, GCC Compiler
+
+
+ CM33, little endian, DSP, SP FPU, GCC Compiler
+
+
+
+ Cortex-M35P processor based device for the GCC Compiler
+
+
+ Cortex-M35P processor based device in little endian mode for the GCC Compiler
+
+
+
+ Cortex-M35P processor based device using Floating Point Unit for the GCC Compiler
+
+
+ Cortex-M35P processor based device using Floating Point Unit in little endian mode for the GCC Compiler
+
+
+
+ CM35P, no DSP, no FPU, GCC Compiler
+
+
+ CM35P, DSP, no FPU, GCC Compiler
+
+
+ CM35P, no DSP, SP FPU, GCC Compiler
+
+
+ CM35P, DSP, SP FPU, GCC Compiler
+
+
+ CM35P, little endian, no DSP, no FPU, GCC Compiler
+
+
+ CM35P, little endian, DSP, no FPU, GCC Compiler
+
+
+ CM35P, little endian, no DSP, SP FPU, GCC Compiler
+
+
+ CM35P, little endian, DSP, SP FPU, GCC Compiler
+
+
+
+ Armv8-M Baseline processor based device for the GCC Compiler
+
+
+ Armv8-M Baseline processor based device in little endian mode for the GCC Compiler
+
+
+
+ Armv8-M Mainline processor based device for the GCC Compiler
+
+
+ Armv8-M Mainline processor based device in little endian mode for the GCC Compiler
+
+
+
+ Armv8-M Mainline processor based device using Floating Point Unit for the GCC Compiler
+
+
+ Armv8-M Mainline processor based device using Floating Point Unit in little endian mode for the GCC Compiler
+
+
+
+ Armv8-M Mainline, no DSP, no FPU, GCC Compiler
+
+
+ Armv8-M Mainline, DSP, no FPU, GCC Compiler
+
+
+ Armv8-M Mainline, no DSP, SP FPU, GCC Compiler
+
+
+ Armv8-M Mainline, DSP, SP FPU, GCC Compiler
+
+
+ Armv8-M Mainline, little endian, no DSP, no FPU, GCC Compiler
+
+
+ Armv8-M Mainline, little endian, DSP, no FPU, GCC Compiler
+
+
+ Armv8-M Mainline, little endian, no DSP, SP FPU, GCC Compiler
+
+
+ Armv8-M Mainline, little endian, DSP, SP FPU, GCC Compiler
+
+
+
+
+ Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the IAR Compiler
+
+
+
+ Cortex-M0 or Cortex-M0+ or SC000 processor based device for the IAR Compiler
+
+
+ Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the IAR Compiler
+
+
+ Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the IAR Compiler
+
+
+
+ Cortex-M1 based device for the IAR Compiler
+
+
+ Cortex-M1 based device in little endian mode for the IAR Compiler
+
+
+ Cortex-M1 based device in big endian mode for the IAR Compiler
+
+
+
+ Cortex-M3 or SC300 processor based device for the IAR Compiler
+
+
+ Cortex-M3 or SC300 processor based device in little endian mode for the IAR Compiler
+
+
+ Cortex-M3 or SC300 processor based device in big endian mode for the IAR Compiler
+
+
+
+ Cortex-M4 processor based device for the IAR Compiler
+
+
+ Cortex-M4 processor based device in little endian mode for the IAR Compiler
+
+
+ Cortex-M4 processor based device in big endian mode for the IAR Compiler
+
+
+
+ Cortex-M4 processor based device using Floating Point Unit for the IAR Compiler
+
+
+ Cortex-M4 processor based device using Floating Point Unit in little endian mode for the IAR Compiler
+
+
+ Cortex-M4 processor based device using Floating Point Unit in big endian mode for the IAR Compiler
+
+
+
+ Cortex-M7 processor based device for the IAR Compiler
+
+
+ Cortex-M7 processor based device in little endian mode for the IAR Compiler
+
+
+ Cortex-M7 processor based device in big endian mode for the IAR Compiler
+
+
+
+ Cortex-M7 processor based device using Floating Point Unit for the IAR Compiler
+
+
+ Cortex-M7 processor based device using Floating Point Unit in little endian mode for the IAR Compiler
+
+
+ Cortex-M7 processor based device using Floating Point Unit in big endian mode for the IAR Compiler
+
+
+
+ Cortex-M7 processor based device using Floating Point Unit (SP) for the IAR Compiler
+
+
+ Cortex-M7 processor based device using Floating Point Unit (SP) in little endian mode for the IAR Compiler
+
+
+ Cortex-M7 processor based device using Floating Point Unit (SP) in big endian mode for the IAR Compiler
+
+
+
+ Cortex-M7 processor based device using Floating Point Unit (DP) for the IAR Compiler
+
+
+ Cortex-M7 processor based device using Floating Point Unit (DP) in little endian mode for the IAR Compiler
+
+
+ Cortex-M7 processor based device using Floating Point Unit (DP) in big endian mode for the IAR Compiler
+
+
+
+ Cortex-M23 processor based device for the IAR Compiler
+
+
+ Cortex-M23 processor based device in little endian mode for the IAR Compiler
+
+
+
+ Cortex-M33 processor based device for the IAR Compiler
+
+
+ Cortex-M33 processor based device in little endian mode for the IAR Compiler
+
+
+
+ Cortex-M33 processor based device using Floating Point Unit for the IAR Compiler
+
+
+ Cortex-M33 processor based device using Floating Point Unit in little endian mode for the IAR Compiler
+
+
+
+ CM33, no DSP, no FPU, IAR Compiler
+
+
+ CM33, DSP, no FPU, IAR Compiler
+
+
+ CM33, no DSP, SP FPU, IAR Compiler
+
+
+ CM33, DSP, SP FPU, IAR Compiler
+
+
+ CM33, little endian, no DSP, no FPU, IAR Compiler
+
+
+ CM33, little endian, DSP, no FPU, IAR Compiler
+
+
+ CM33, little endian, no DSP, SP FPU, IAR Compiler
+
+
+ CM33, little endian, DSP, SP FPU, IAR Compiler
+
+
+
+ Cortex-M35P processor based device for the IAR Compiler
+
+
+ Cortex-M35P processor based device in little endian mode for the IAR Compiler
+
+
+
+ Cortex-M35P processor based device using Floating Point Unit for the IAR Compiler
+
+
+ Cortex-M35P processor based device using Floating Point Unit in little endian mode for the IAR Compiler
+
+
+
+ CM35P, no DSP, no FPU, IAR Compiler
+
+
+ CM35P, DSP, no FPU, IAR Compiler
+
+
+ CM35P, no DSP, SP FPU, IAR Compiler
+
+
+ CM35P, DSP, SP FPU, IAR Compiler
+
+
+ CM35P, little endian, no DSP, no FPU, IAR Compiler
+
+
+ CM35P, little endian, DSP, no FPU, IAR Compiler
+
+
+ CM35P, little endian, no DSP, SP FPU, IAR Compiler
+
+
+ CM35P, little endian, DSP, SP FPU, IAR Compiler
+
+
+
+ Armv8-M Baseline processor based device for the IAR Compiler
+
+
+ Armv8-M Baseline processor based device in little endian mode for the IAR Compiler
+
+
+
+ Armv8-M Mainline processor based device for the IAR Compiler
+
+
+ Armv8-M Mainline processor based device in little endian mode for the IAR Compiler
+
+
+
+ Armv8-M Mainline processor based device using Floating Point Unit for the IAR Compiler
+
+
+ Armv8-M Mainline processor based device using Floating Point Unit in little endian mode for the IAR Compiler
+
+
+
+ Armv8-M Mainline, no DSP, no FPU, IAR Compiler
+
+
+ Armv8-M Mainline, DSP, no FPU, IAR Compiler
+
+
+ Armv8-M Mainline, no DSP, SP FPU, IAR Compiler
+
+
+ Armv8-M Mainline, DSP, SP FPU, IAR Compiler
+
+
+ Armv8-M Mainline, little endian, no DSP, no FPU, IAR Compiler
+
+
+ Armv8-M Mainline, little endian, DSP, no FPU, IAR Compiler
+
+
+ Armv8-M Mainline, little endian, no DSP, SP FPU, IAR Compiler
+
+
+ Armv8-M Mainline, little endian, DSP, SP FPU, IAR Compiler
+
+
+
+
+ Generic Arm Cortex-M0 device startup and depends on CMSIS Core
+
+
+
+ Generic Arm Cortex-M0+ device startup and depends on CMSIS Core
+
+
+
+ Generic Arm Cortex-M1 device startup and depends on CMSIS Core
+
+
+
+ Generic Arm Cortex-M3 device startup and depends on CMSIS Core
+
+
+
+ Generic Arm Cortex-M4 device startup and depends on CMSIS Core
+
+
+
+ Generic Arm Cortex-M7 device startup and depends on CMSIS Core
+
+
+
+ Generic Arm Cortex-M23 device startup and depends on CMSIS Core
+
+
+
+ Generic Arm Cortex-M33 device startup and depends on CMSIS Core
+
+
+
+ Generic Arm Cortex-M35P device startup and depends on CMSIS Core
+
+
+
+ Generic Arm SC000 device startup and depends on CMSIS Core
+
+
+
+ Generic Arm SC300 device startup and depends on CMSIS Core
+
+
+
+ Generic Armv8-M Baseline device startup and depends on CMSIS Core
+
+
+
+ Generic Armv8-M Mainline device startup and depends on CMSIS Core
+
+
+
+ Generic Armv8.1-M Mainline device startup and depends on CMSIS Core
+
+
+
+ Generic Arm Cortex-A5 device startup and depends on CMSIS Core
+
+
+
+ Generic Arm Cortex-A7 device startup and depends on CMSIS Core
+
+
+
+ Generic Arm Cortex-A9 device startup and depends on CMSIS Core
+
+
+
+
+ Components required for DSP
+
+
+
+
+ Components required for NN
+
+
+
+
+ Components required for RTOS RTX
+
+
+ Components required for RTOS RTX IFX
+
+
+ Components required for RTOS RTX5
+
+
+ Components required for RTOS2 RTX5
+
+
+ Components required for RTOS2 RTX5 on Armv7-A
+
+
+ Components required for RTOS2 RTX5 Library
+
+
+ Components required for RTOS2 RTX5 in Non-Secure Domain
+
+
+
+
+ Components required for OS Tick Private Timer
+
+
+
+ Components required for OS Tick Generic Physical Timer
+
+
+
+
+
+
+
+ CMSIS-CORE for Cortex-M, SC000, SC300, ARMv8-M, ARMv8.1-M
+
+
+
+
+
+
+ CMSIS-CORE for Cortex-A
+
+
+
+
+
+
+
+
+ System and Startup for Generic Arm Cortex-M0 device
+
+
+
+
+
+ DEPRECATED: System and Startup for Generic Arm Cortex-M0 device
+
+
+
+
+
+
+
+ System and Startup for Generic Arm Cortex-M0+ device
+
+
+
+
+
+ DEPRECATED: System and Startup for Generic Arm Cortex-M0+ device
+
+
+
+
+
+
+
+ System and Startup for Generic Arm Cortex-M1 device
+
+
+
+
+
+ DEPRECATED: System and Startup for Generic Arm Cortex-M1 device
+
+
+
+
+
+
+
+ System and Startup for Generic Arm Cortex-M3 device
+
+
+
+
+
+ DEPRECATED: System and Startup for Generic Arm Cortex-M3 device
+
+
+
+
+
+
+
+ System and Startup for Generic Arm Cortex-M4 device
+
+
+
+
+
+ DEPRECATED: System and Startup for Generic Arm Cortex-M4 device
+
+
+
+
+
+
+
+ System and Startup for Generic Arm Cortex-M7 device
+
+
+
+
+
+ DEPRECATED: System and Startup for Generic Arm Cortex-M7 device
+
+
+
+
+
+
+
+ System and Startup for Generic Arm Cortex-M23 device
+
+
+
+
+
+ DEPRECATED: System and Startup for Generic Arm Cortex-M23 device
+
+
+
+
+
+
+
+ System and Startup for Generic Arm Cortex-M33 device
+
+
+
+
+
+ DEPRECATED: System and Startup for Generic Arm Cortex-M33 device
+
+
+
+
+
+
+
+ System and Startup for Generic Arm Cortex-M35P device
+
+
+
+
+
+ DEPRECATED: System and Startup for Generic Arm Cortex-M35P device
+
+
+
+
+
+
+
+ System and Startup for Generic Arm SC000 device
+
+
+
+
+
+ DEPRECATED: System and Startup for Generic Arm SC000 device
+
+
+
+
+
+
+
+ System and Startup for Generic Arm SC300 device
+
+
+
+
+
+ DEPRECATED: System and Startup for Generic Arm SC300 device
+
+
+
+
+
+
+
+ System and Startup for Generic Armv8-M Baseline device
+
+
+
+
+
+ DEPRECATED: System and Startup for Generic Armv8-M Baseline device
+
+
+
+
+
+
+
+ System and Startup for Generic Armv8-M Mainline device
+
+
+
+
+
+ DEPRECATED: System and Startup for Generic Armv8-M Mainline device
+
+
+
+
+
+
+
+ System and Startup for Generic Armv8.1-M Mainline device
+
+
+
+
+
+
+
+ System and Startup for Generic Arm Cortex-A5 device
+
+
+
+
+
+
+
+ System and Startup for Generic Arm Cortex-A7 device
+
+
+
+
+
+
+
+ System and Startup for Generic Arm Cortex-A9 device
+
+
+
+
+
+
+
+ IRQ Controller implementation using GIC
+
+
+
+
+
+
+ OS Tick implementation using Private Timer
+
+
+
+
+
+ OS Tick implementation using Generic Physical Timer
+
+
+
+
+
+
+ CMSIS-DSP Library for Cortex-M, SC000, and SC300
+
+
+
+
+
+ CMSIS-DSP Library for Cortex-M, SC000, and SC300
+
+
+
+
+
+
+
+ CMSIS-NN Neural Network Library
+
+
+
+
+
+
+ CMSIS-RTOS RTX implementation for Cortex-M, SC000, and SC300
+
+
+ #define RTE_CMSIS_RTOS /* CMSIS-RTOS */
+ #define RTE_CMSIS_RTOS_RTX /* CMSIS-RTOS Keil RTX */
+
+
+
+
+
+
+
+ CMSIS-RTOS RTX implementation for Infineon XMC4 series affected by PMU_CM.001 errata
+
+
+ #define RTE_CMSIS_RTOS /* CMSIS-RTOS */
+ #define RTE_CMSIS_RTOS_RTX /* CMSIS-RTOS Keil RTX */
+
+
+
+
+
+
+
+
+ CMSIS-RTOS RTX5 implementation for Cortex-M, SC000, and SC300
+
+
+ #define RTE_CMSIS_RTOS /* CMSIS-RTOS */
+ #define RTE_CMSIS_RTOS_RTX5 /* CMSIS-RTOS Keil RTX5 */
+
+
+
+
+
+
+
+
+ CMSIS-RTOS2 RTX5 for Cortex-M, SC000, C300 and Armv8-M (Library)
+
+
+ #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */
+ #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */
+
+
+
+
+
+
+ CMSIS-RTOS2 RTX5 for Armv8-M Non-Secure Domain (Library)
+
+
+ #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */
+ #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */
+ #define RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS /* CMSIS-RTOS2 Keil RTX5 Armv8-M Non-secure domain */
+
+
+
+
+
+
+ CMSIS-RTOS2 RTX5 for Cortex-M, SC000, C300 and Armv8-M (Source)
+
+
+ #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */
+ #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */
+ #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */
+
+
+
+
+
+
+ CMSIS-RTOS2 RTX5 for Armv7-A (Source)
+
+
+ #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */
+ #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */
+ #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */
+
+
+
+
+
+
+ CMSIS-RTOS2 RTX5 for Armv8-M Non-Secure Domain (Source)
+
+
+ #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */
+ #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */
+ #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */
+ #define RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS /* CMSIS-RTOS2 Keil RTX5 Armv8-M Non-secure domain */
+
+
+
+
+
+
+
+
+ Access to #include Driver_USART.h file and code template for custom implementation
+
+
+
+
+ Access to #include Driver_SPI.h file and code template for custom implementation
+
+
+
+
+ Access to #include Driver_SAI.h file and code template for custom implementation
+
+
+
+
+ Access to #include Driver_I2C.h file and code template for custom implementation
+
+
+
+
+ Access to #include Driver_CAN.h file and code template for custom implementation
+
+
+
+
+ Access to #include Driver_Flash.h file and code template for custom implementation
+
+
+
+
+ Access to #include Driver_MCI.h file and code template for custom implementation
+
+
+
+
+ Access to #include Driver_NAND.h file and code template for custom implementation
+
+
+
+
+ Access to #include Driver_ETH_PHY/MAC.h files and code templates for custom implementation
+
+
+
+
+ Access to #include Driver_ETH_MAC.h file and code template for custom implementation
+
+
+
+
+ Access to #include Driver_ETH_PHY.h file and code template for custom implementation
+
+
+
+
+ Access to #include Driver_USBD.h file and code template for custom implementation
+
+
+
+
+ Access to #include Driver_USBH.h file and code template for custom implementation
+
+
+
+
+ Access to #include Driver_WiFi.h file
+
+
+
+
+
+
+
+ uVision Simulator
+
+
+
+ EWARM Simulator
+
+
+
+
+
+ DSP_Lib Class Marks example
+
+
+
+ Getting Started
+
+
+
+
+ DSP_Lib Convolution example
+
+
+
+ Getting Started
+
+
+
+
+ DSP_Lib Dotproduct example
+
+
+
+ Getting Started
+
+
+
+
+ DSP_Lib FFT Bin example
+
+
+
+ Getting Started
+
+
+
+
+ DSP_Lib FIR example
+
+
+
+ Getting Started
+
+
+
+
+ DSP_Lib Graphic Equalizer example
+
+
+
+ Getting Started
+
+
+
+
+ DSP_Lib Linear Interpolation example
+
+
+
+ Getting Started
+
+
+
+
+ DSP_Lib Matrix example
+
+
+
+ Getting Started
+
+
+
+
+ DSP_Lib Signal Convergence example
+
+
+
+ Getting Started
+
+
+
+
+ DSP_Lib Sinus/Cosinus example
+
+
+
+ Getting Started
+
+
+
+
+ DSP_Lib Variance example
+
+
+
+ Getting Started
+
+
+
+
+ Neural Network CIFAR10 example
+
+
+
+ Getting Started
+
+
+
+
+ Neural Network CIFAR10 example
+
+
+
+ Getting Started
+
+
+
+
+ Neural Network GRU example
+
+
+
+ Getting Started
+
+
+
+
+ Neural Network GRU example
+
+
+
+ Getting Started
+
+
+
+
+ CMSIS-RTOS2 Blinky example
+
+
+
+ Getting Started
+
+
+
+
+ CMSIS-RTOS2 mixed API v1 and v2
+
+
+
+ Getting Started
+
+
+
+
+ CMSIS-RTOS2 Message Queue Example
+
+
+
+ Getting Started
+
+
+
+
+ CMSIS-RTOS2 Memory Pool Example
+
+
+
+ Getting Started
+
+
+
+
+ Bare-metal secure/non-secure example without RTOS
+
+
+
+ Getting Started
+
+
+
+
+ Secure/non-secure RTOS example with thread context management
+
+
+
+ Getting Started
+
+
+
+
+ Secure/non-secure RTOS example with security test cases and system recovery
+
+
+
+ Getting Started
+
+
+
+
+
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Core/Include/cmsis_armcc.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Core/Include/cmsis_armcc.h
new file mode 100644
index 00000000..59f173ac
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Core/Include/cmsis_armcc.h
@@ -0,0 +1,894 @@
+/**************************************************************************//**
+ * @file cmsis_armcc.h
+ * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version V5.1.0
+ * @date 08. May 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+ #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
+ (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
+ #define __ARM_ARCH_6M__ 1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
+ #define __ARM_ARCH_7M__ 1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+ #define __ARM_ARCH_7EM__ 1
+#endif
+
+ /* __ARM_ARCH_8M_BASE__ not applicable */
+ /* __ARM_ARCH_8M_MAIN__ not applicable */
+
+/* CMSIS compiler control DSP macros */
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+ #define __ARM_FEATURE_DSP 1
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE static __forceinline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __declspec(noreturn)
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT __packed struct
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION __packed union
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __memory_changed()
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET")))
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); */
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ register uint32_t __regBasePriMax __ASM("basepri_max");
+ __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#else
+ (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() do {\
+ __schedule_barrier();\
+ __isb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+ __schedule_barrier();\
+ __dsb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+ __schedule_barrier();\
+ __dmb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+ #define __RBIT __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value != 0U; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+ return result;
+}
+#endif
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+#else
+ #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+#else
+ #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+#else
+ #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXB(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXH(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXW(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __clrex
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+ rrx r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRBT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRHT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRT(value, ptr) __strt(value, ptr)
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+ ((int64_t)(ARG3) << 32U) ) >> 32U))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Core/Include/cmsis_armclang.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Core/Include/cmsis_armclang.h
new file mode 100644
index 00000000..e917f357
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Core/Include/cmsis_armclang.h
@@ -0,0 +1,1444 @@
+/**************************************************************************//**
+ * @file cmsis_armclang.h
+ * @brief CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version V5.2.0
+ * @date 08. May 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET")))
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR() ((uint32_t)0U)
+#endif
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __set_FPSCR __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x) ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __builtin_arm_nop
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __builtin_arm_wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __builtin_arm_wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __builtin_arm_sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __builtin_arm_isb(0xF)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __builtin_arm_dsb(0xF)
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __builtin_arm_dmb(0xF)
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV(value) __builtin_bswap32(value)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __builtin_arm_rbit
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+ __builtin_clz(0) is undefined behaviour, so handle this case specially.
+ This guarantees ARM-compatible results if happening to compile on a non-ARM
+ target, and ensures the compiler doesn't decide to activate any
+ optimisations using the logic "value was passed to __builtin_clz, so it
+ is non-zero".
+ ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
+ single CLZ instruction.
+ */
+ if (value == 0U)
+ {
+ return 32U;
+ }
+ return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __builtin_arm_ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __builtin_arm_usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDAEX (uint32_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXB (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXH (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEX (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+#define __SADD8 __builtin_arm_sadd8
+#define __QADD8 __builtin_arm_qadd8
+#define __SHADD8 __builtin_arm_shadd8
+#define __UADD8 __builtin_arm_uadd8
+#define __UQADD8 __builtin_arm_uqadd8
+#define __UHADD8 __builtin_arm_uhadd8
+#define __SSUB8 __builtin_arm_ssub8
+#define __QSUB8 __builtin_arm_qsub8
+#define __SHSUB8 __builtin_arm_shsub8
+#define __USUB8 __builtin_arm_usub8
+#define __UQSUB8 __builtin_arm_uqsub8
+#define __UHSUB8 __builtin_arm_uhsub8
+#define __SADD16 __builtin_arm_sadd16
+#define __QADD16 __builtin_arm_qadd16
+#define __SHADD16 __builtin_arm_shadd16
+#define __UADD16 __builtin_arm_uadd16
+#define __UQADD16 __builtin_arm_uqadd16
+#define __UHADD16 __builtin_arm_uhadd16
+#define __SSUB16 __builtin_arm_ssub16
+#define __QSUB16 __builtin_arm_qsub16
+#define __SHSUB16 __builtin_arm_shsub16
+#define __USUB16 __builtin_arm_usub16
+#define __UQSUB16 __builtin_arm_uqsub16
+#define __UHSUB16 __builtin_arm_uhsub16
+#define __SASX __builtin_arm_sasx
+#define __QASX __builtin_arm_qasx
+#define __SHASX __builtin_arm_shasx
+#define __UASX __builtin_arm_uasx
+#define __UQASX __builtin_arm_uqasx
+#define __UHASX __builtin_arm_uhasx
+#define __SSAX __builtin_arm_ssax
+#define __QSAX __builtin_arm_qsax
+#define __SHSAX __builtin_arm_shsax
+#define __USAX __builtin_arm_usax
+#define __UQSAX __builtin_arm_uqsax
+#define __UHSAX __builtin_arm_uhsax
+#define __USAD8 __builtin_arm_usad8
+#define __USADA8 __builtin_arm_usada8
+#define __SSAT16 __builtin_arm_ssat16
+#define __USAT16 __builtin_arm_usat16
+#define __UXTB16 __builtin_arm_uxtb16
+#define __UXTAB16 __builtin_arm_uxtab16
+#define __SXTB16 __builtin_arm_sxtb16
+#define __SXTAB16 __builtin_arm_sxtab16
+#define __SMUAD __builtin_arm_smuad
+#define __SMUADX __builtin_arm_smuadx
+#define __SMLAD __builtin_arm_smlad
+#define __SMLADX __builtin_arm_smladx
+#define __SMLALD __builtin_arm_smlald
+#define __SMLALDX __builtin_arm_smlaldx
+#define __SMUSD __builtin_arm_smusd
+#define __SMUSDX __builtin_arm_smusdx
+#define __SMLSD __builtin_arm_smlsd
+#define __SMLSDX __builtin_arm_smlsdx
+#define __SMLSLD __builtin_arm_smlsld
+#define __SMLSLDX __builtin_arm_smlsldx
+#define __SEL __builtin_arm_sel
+#define __QADD __builtin_arm_qadd
+#define __QSUB __builtin_arm_qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Core/Include/cmsis_armclang_ltm.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Core/Include/cmsis_armclang_ltm.h
new file mode 100644
index 00000000..feec3240
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Core/Include/cmsis_armclang_ltm.h
@@ -0,0 +1,1891 @@
+/**************************************************************************//**
+ * @file cmsis_armclang_ltm.h
+ * @brief CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version V1.2.0
+ * @date 08. May 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2018-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET")))
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR() ((uint32_t)0U)
+#endif
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __set_FPSCR __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x) ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __builtin_arm_nop
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __builtin_arm_wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __builtin_arm_wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __builtin_arm_sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __builtin_arm_isb(0xF)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __builtin_arm_dsb(0xF)
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __builtin_arm_dmb(0xF)
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV(value) __builtin_bswap32(value)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __builtin_arm_rbit
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+ __builtin_clz(0) is undefined behaviour, so handle this case specially.
+ This guarantees ARM-compatible results if happening to compile on a non-ARM
+ target, and ensures the compiler doesn't decide to activate any
+ optimisations using the logic "value was passed to __builtin_clz, so it
+ is non-zero".
+ ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
+ single CLZ instruction.
+ */
+ if (value == 0U)
+ {
+ return 32U;
+ }
+ return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __builtin_arm_ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __builtin_arm_usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDAEX (uint32_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXB (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXH (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEX (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Core/Include/cmsis_compiler.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Core/Include/cmsis_compiler.h
new file mode 100644
index 00000000..adbf296f
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Core/Include/cmsis_compiler.h
@@ -0,0 +1,283 @@
+/**************************************************************************//**
+ * @file cmsis_compiler.h
+ * @brief CMSIS compiler generic header file
+ * @version V5.1.0
+ * @date 09. October 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include
+
+/*
+ * Arm Compiler 4/5
+ */
+#if defined ( __CC_ARM )
+ #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6.6 LTM (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+ #include "cmsis_armclang_ltm.h"
+
+ /*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+ #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+ #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+ #include
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+ #include
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed))
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed))
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #endif
+ #ifndef __RESTRICT
+ #define __RESTRICT __restrict
+ #endif
+ #ifndef __COMPILER_BARRIER
+ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+ #define __COMPILER_BARRIER() (void)0
+ #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __packed__
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __packed__
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __packed__
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __packed__ T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __align(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+ #ifndef __COMPILER_BARRIER
+ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+ #define __COMPILER_BARRIER() (void)0
+ #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+ #include
+
+ #ifndef __ASM
+ #define __ASM _asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ // NO RETURN is automatically detected hence no warning here
+ #define __NO_RETURN
+ #endif
+ #ifndef __USED
+ #warning No compiler specific solution for __USED. __USED is ignored.
+ #define __USED
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __weak
+ #endif
+ #ifndef __PACKED
+ #define __PACKED @packed
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT @packed struct
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION @packed union
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ @packed struct T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+ #ifndef __COMPILER_BARRIER
+ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+ #define __COMPILER_BARRIER() (void)0
+ #endif
+
+
+#else
+ #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Core/Include/cmsis_gcc.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Core/Include/cmsis_gcc.h
new file mode 100644
index 00000000..3ddcc58b
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Core/Include/cmsis_gcc.h
@@ -0,0 +1,2168 @@
+/**************************************************************************//**
+ * @file cmsis_gcc.h
+ * @brief CMSIS compiler GCC header file
+ * @version V5.2.0
+ * @date 08. May 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+ #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+
+/**
+ \brief Initializes data and bss sections
+ \details This default implementations initialized all data and additional bss
+ sections relying on .copy.table and .zero.table specified properly
+ in the used linker script.
+
+ */
+__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
+{
+ extern void _start(void) __NO_RETURN;
+
+ typedef struct {
+ uint32_t const* src;
+ uint32_t* dest;
+ uint32_t wlen;
+ } __copy_table_t;
+
+ typedef struct {
+ uint32_t* dest;
+ uint32_t wlen;
+ } __zero_table_t;
+
+ extern const __copy_table_t __copy_table_start__;
+ extern const __copy_table_t __copy_table_end__;
+ extern const __zero_table_t __zero_table_start__;
+ extern const __zero_table_t __zero_table_end__;
+
+ for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) {
+ for(uint32_t i=0u; iwlen; ++i) {
+ pTable->dest[i] = pTable->src[i];
+ }
+ }
+
+ for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) {
+ for(uint32_t i=0u; iwlen; ++i) {
+ pTable->dest[i] = 0u;
+ }
+ }
+
+ _start();
+}
+
+#define __PROGRAM_START __cmsis_start
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP __StackTop
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT __StackLimit
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors")))
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_get_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ return __builtin_arm_get_fpscr();
+#else
+ uint32_t result;
+
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ return(result);
+#endif
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_set_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ __builtin_arm_set_fpscr(fpscr);
+#else
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+ (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP() __ASM volatile ("nop")
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI() __ASM volatile ("wfi")
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE() __ASM volatile ("wfe")
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV() __ASM volatile ("sev")
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+ __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+ __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+ __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (int16_t)__builtin_bswap16(value);
+#else
+ int16_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value != 0U; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return result;
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+ __builtin_clz(0) is undefined behaviour, so handle this case specially.
+ This guarantees ARM-compatible results if happening to compile on a non-ARM
+ target, and ensures the compiler doesn't decide to activate any
+ optimisations using the logic "value was passed to __builtin_clz, so it
+ is non-zero".
+ ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
+ single CLZ instruction.
+ */
+ if (value == 0U)
+ {
+ return 32U;
+ }
+ return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+__extension__ \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+ __extension__ \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Core/Include/cmsis_iccarm.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Core/Include/cmsis_iccarm.h
new file mode 100644
index 00000000..12d68fd9
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Core/Include/cmsis_iccarm.h
@@ -0,0 +1,964 @@
+/**************************************************************************//**
+ * @file cmsis_iccarm.h
+ * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version V5.1.0
+ * @date 08. May 2019
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2019 IAR Systems
+// Copyright (c) 2017-2019 Arm Limited. All rights reserved.
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+ #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+ #define __ICCARM_V8 1
+#else
+ #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+ #if __ICCARM_V8
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #elif (__VER__ >= 7080000)
+ /* Needs IAR language extensions */
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #else
+ #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+ #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #elif defined(__ARM8M_BASELINE__)
+ #define __ARM_ARCH_8M_BASE__ 1
+ #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+ #if __ARM_ARCH == 6
+ #define __ARM_ARCH_6M__ 1
+ #elif __ARM_ARCH == 7
+ #if __ARM_FEATURE_DSP
+ #define __ARM_ARCH_7EM__ 1
+ #else
+ #define __ARM_ARCH_7M__ 1
+ #endif
+ #endif /* __ARM_ARCH */
+ #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+ !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+ #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+ #define __ARM_ARCH_6M__ 1
+ #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+ #define __ARM_ARCH_7M__ 1
+ #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+ #define __ARM_ARCH_7EM__ 1
+ #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+ #define __ARM_ARCH_8M_BASE__ 1
+ #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #else
+ #error "Unknown target."
+ #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+ #define __IAR_M0_FAMILY 1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+ #define __IAR_M0_FAMILY 1
+#else
+ #define __IAR_M0_FAMILY 0
+#endif
+
+
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+
+#ifndef __NO_RETURN
+ #if __ICCARM_V8
+ #define __NO_RETURN __attribute__((__noreturn__))
+ #else
+ #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+ #endif
+#endif
+
+#ifndef __PACKED
+ #if __ICCARM_V8
+ #define __PACKED __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED __packed
+ #endif
+#endif
+
+#ifndef __PACKED_STRUCT
+ #if __ICCARM_V8
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED_STRUCT __packed struct
+ #endif
+#endif
+
+#ifndef __PACKED_UNION
+ #if __ICCARM_V8
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED_UNION __packed union
+ #endif
+#endif
+
+#ifndef __RESTRICT
+ #if __ICCARM_V8
+ #define __RESTRICT __restrict
+ #else
+ /* Needs IAR language extensions */
+ #define __RESTRICT restrict
+ #endif
+#endif
+
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+
+#ifndef __FORCEINLINE
+ #define __FORCEINLINE _Pragma("inline=forced")
+#endif
+
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+ return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+ *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+ return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+ *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef __USED
+ #if __ICCARM_V8
+ #define __USED __attribute__((used))
+ #else
+ #define __USED _Pragma("__root")
+ #endif
+#endif
+
+#ifndef __WEAK
+ #if __ICCARM_V8
+ #define __WEAK __attribute__((weak))
+ #else
+ #define __WEAK _Pragma("__weak")
+ #endif
+#endif
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __iar_program_start
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP CSTACK$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT CSTACK$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __vector_table
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE @".intvec"
+#endif
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+ #define __ICCARM_INTRINSICS_VERSION__ 0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+ #if defined(__CLZ)
+ #undef __CLZ
+ #endif
+ #if defined(__REVSH)
+ #undef __REVSH
+ #endif
+ #if defined(__RBIT)
+ #undef __RBIT
+ #endif
+ #if defined(__SSAT)
+ #undef __SSAT
+ #endif
+ #if defined(__USAT)
+ #undef __USAT
+ #endif
+
+ #include "iccarm_builtin.h"
+
+ #define __disable_fault_irq __iar_builtin_disable_fiq
+ #define __disable_irq __iar_builtin_disable_interrupt
+ #define __enable_fault_irq __iar_builtin_enable_fiq
+ #define __enable_irq __iar_builtin_enable_interrupt
+ #define __arm_rsr __iar_builtin_rsr
+ #define __arm_wsr __iar_builtin_wsr
+
+
+ #define __get_APSR() (__arm_rsr("APSR"))
+ #define __get_BASEPRI() (__arm_rsr("BASEPRI"))
+ #define __get_CONTROL() (__arm_rsr("CONTROL"))
+ #define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
+
+ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ #define __get_FPSCR() (__arm_rsr("FPSCR"))
+ #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
+ #else
+ #define __get_FPSCR() ( 0 )
+ #define __set_FPSCR(VALUE) ((void)VALUE)
+ #endif
+
+ #define __get_IPSR() (__arm_rsr("IPSR"))
+ #define __get_MSP() (__arm_rsr("MSP"))
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ #define __get_MSPLIM() (0U)
+ #else
+ #define __get_MSPLIM() (__arm_rsr("MSPLIM"))
+ #endif
+ #define __get_PRIMASK() (__arm_rsr("PRIMASK"))
+ #define __get_PSP() (__arm_rsr("PSP"))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __get_PSPLIM() (0U)
+ #else
+ #define __get_PSPLIM() (__arm_rsr("PSPLIM"))
+ #endif
+
+ #define __get_xPSR() (__arm_rsr("xPSR"))
+
+ #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
+ #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
+ #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
+ #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
+ #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ #define __set_MSPLIM(VALUE) ((void)(VALUE))
+ #else
+ #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
+ #endif
+ #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
+ #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __set_PSPLIM(VALUE) ((void)(VALUE))
+ #else
+ #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
+ #endif
+
+ #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
+ #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
+ #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
+ #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
+ #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
+ #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
+ #define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
+ #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
+ #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
+ #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
+ #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
+ #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
+ #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
+ #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __TZ_get_PSPLIM_NS() (0U)
+ #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+ #else
+ #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
+ #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+ #endif
+
+ #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
+ #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+ #define __NOP __iar_builtin_no_operation
+
+ #define __CLZ __iar_builtin_CLZ
+ #define __CLREX __iar_builtin_CLREX
+
+ #define __DMB __iar_builtin_DMB
+ #define __DSB __iar_builtin_DSB
+ #define __ISB __iar_builtin_ISB
+
+ #define __LDREXB __iar_builtin_LDREXB
+ #define __LDREXH __iar_builtin_LDREXH
+ #define __LDREXW __iar_builtin_LDREX
+
+ #define __RBIT __iar_builtin_RBIT
+ #define __REV __iar_builtin_REV
+ #define __REV16 __iar_builtin_REV16
+
+ __IAR_FT int16_t __REVSH(int16_t val)
+ {
+ return (int16_t) __iar_builtin_REVSH(val);
+ }
+
+ #define __ROR __iar_builtin_ROR
+ #define __RRX __iar_builtin_RRX
+
+ #define __SEV __iar_builtin_SEV
+
+ #if !__IAR_M0_FAMILY
+ #define __SSAT __iar_builtin_SSAT
+ #endif
+
+ #define __STREXB __iar_builtin_STREXB
+ #define __STREXH __iar_builtin_STREXH
+ #define __STREXW __iar_builtin_STREX
+
+ #if !__IAR_M0_FAMILY
+ #define __USAT __iar_builtin_USAT
+ #endif
+
+ #define __WFE __iar_builtin_WFE
+ #define __WFI __iar_builtin_WFI
+
+ #if __ARM_MEDIA__
+ #define __SADD8 __iar_builtin_SADD8
+ #define __QADD8 __iar_builtin_QADD8
+ #define __SHADD8 __iar_builtin_SHADD8
+ #define __UADD8 __iar_builtin_UADD8
+ #define __UQADD8 __iar_builtin_UQADD8
+ #define __UHADD8 __iar_builtin_UHADD8
+ #define __SSUB8 __iar_builtin_SSUB8
+ #define __QSUB8 __iar_builtin_QSUB8
+ #define __SHSUB8 __iar_builtin_SHSUB8
+ #define __USUB8 __iar_builtin_USUB8
+ #define __UQSUB8 __iar_builtin_UQSUB8
+ #define __UHSUB8 __iar_builtin_UHSUB8
+ #define __SADD16 __iar_builtin_SADD16
+ #define __QADD16 __iar_builtin_QADD16
+ #define __SHADD16 __iar_builtin_SHADD16
+ #define __UADD16 __iar_builtin_UADD16
+ #define __UQADD16 __iar_builtin_UQADD16
+ #define __UHADD16 __iar_builtin_UHADD16
+ #define __SSUB16 __iar_builtin_SSUB16
+ #define __QSUB16 __iar_builtin_QSUB16
+ #define __SHSUB16 __iar_builtin_SHSUB16
+ #define __USUB16 __iar_builtin_USUB16
+ #define __UQSUB16 __iar_builtin_UQSUB16
+ #define __UHSUB16 __iar_builtin_UHSUB16
+ #define __SASX __iar_builtin_SASX
+ #define __QASX __iar_builtin_QASX
+ #define __SHASX __iar_builtin_SHASX
+ #define __UASX __iar_builtin_UASX
+ #define __UQASX __iar_builtin_UQASX
+ #define __UHASX __iar_builtin_UHASX
+ #define __SSAX __iar_builtin_SSAX
+ #define __QSAX __iar_builtin_QSAX
+ #define __SHSAX __iar_builtin_SHSAX
+ #define __USAX __iar_builtin_USAX
+ #define __UQSAX __iar_builtin_UQSAX
+ #define __UHSAX __iar_builtin_UHSAX
+ #define __USAD8 __iar_builtin_USAD8
+ #define __USADA8 __iar_builtin_USADA8
+ #define __SSAT16 __iar_builtin_SSAT16
+ #define __USAT16 __iar_builtin_USAT16
+ #define __UXTB16 __iar_builtin_UXTB16
+ #define __UXTAB16 __iar_builtin_UXTAB16
+ #define __SXTB16 __iar_builtin_SXTB16
+ #define __SXTAB16 __iar_builtin_SXTAB16
+ #define __SMUAD __iar_builtin_SMUAD
+ #define __SMUADX __iar_builtin_SMUADX
+ #define __SMMLA __iar_builtin_SMMLA
+ #define __SMLAD __iar_builtin_SMLAD
+ #define __SMLADX __iar_builtin_SMLADX
+ #define __SMLALD __iar_builtin_SMLALD
+ #define __SMLALDX __iar_builtin_SMLALDX
+ #define __SMUSD __iar_builtin_SMUSD
+ #define __SMUSDX __iar_builtin_SMUSDX
+ #define __SMLSD __iar_builtin_SMLSD
+ #define __SMLSDX __iar_builtin_SMLSDX
+ #define __SMLSLD __iar_builtin_SMLSLD
+ #define __SMLSLDX __iar_builtin_SMLSLDX
+ #define __SEL __iar_builtin_SEL
+ #define __QADD __iar_builtin_QADD
+ #define __QSUB __iar_builtin_QSUB
+ #define __PKHBT __iar_builtin_PKHBT
+ #define __PKHTB __iar_builtin_PKHTB
+ #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+ #if __IAR_M0_FAMILY
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+ #define __CLZ __cmsis_iar_clz_not_active
+ #define __SSAT __cmsis_iar_ssat_not_active
+ #define __USAT __cmsis_iar_usat_not_active
+ #define __RBIT __cmsis_iar_rbit_not_active
+ #define __get_APSR __cmsis_iar_get_APSR_not_active
+ #endif
+
+
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
+ #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+ #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+ #endif
+
+ #ifdef __INTRINSICS_INCLUDED
+ #error intrinsics.h is already included previously!
+ #endif
+
+ #include
+
+ #if __IAR_M0_FAMILY
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+ #undef __CLZ
+ #undef __SSAT
+ #undef __USAT
+ #undef __RBIT
+ #undef __get_APSR
+
+ __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+ {
+ if (data == 0U) { return 32U; }
+
+ uint32_t count = 0U;
+ uint32_t mask = 0x80000000U;
+
+ while ((data & mask) == 0U)
+ {
+ count += 1U;
+ mask = mask >> 1U;
+ }
+ return count;
+ }
+
+ __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+ {
+ uint8_t sc = 31U;
+ uint32_t r = v;
+ for (v >>= 1U; v; v >>= 1U)
+ {
+ r <<= 1U;
+ r |= v & 1U;
+ sc--;
+ }
+ return (r << sc);
+ }
+
+ __STATIC_INLINE uint32_t __get_APSR(void)
+ {
+ uint32_t res;
+ __asm("MRS %0,APSR" : "=r" (res));
+ return res;
+ }
+
+ #endif
+
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
+ #undef __get_FPSCR
+ #undef __set_FPSCR
+ #define __get_FPSCR() (0)
+ #define __set_FPSCR(VALUE) ((void)VALUE)
+ #endif
+
+ #pragma diag_suppress=Pe940
+ #pragma diag_suppress=Pe177
+
+ #define __enable_irq __enable_interrupt
+ #define __disable_irq __disable_interrupt
+ #define __NOP __no_operation
+
+ #define __get_xPSR __get_PSR
+
+ #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+ __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+ {
+ return __LDREX((unsigned long *)ptr);
+ }
+
+ __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+ {
+ return __STREX(value, (unsigned long *)ptr);
+ }
+ #endif
+
+
+ /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+ #if (__CORTEX_M >= 0x03)
+
+ __IAR_FT uint32_t __RRX(uint32_t value)
+ {
+ uint32_t result;
+ __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
+ return(result);
+ }
+
+ __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+ {
+ __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
+ }
+
+
+ #define __enable_fault_irq __enable_fiq
+ #define __disable_fault_irq __disable_fiq
+
+
+ #endif /* (__CORTEX_M >= 0x03) */
+
+ __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+ {
+ return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+ }
+
+ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+ __IAR_FT uint32_t __get_MSPLIM(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,MSPLIM" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __set_MSPLIM(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR MSPLIM,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __get_PSPLIM(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,PSPLIM" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __set_PSPLIM(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR PSPLIM,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
+ {
+ __asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PSP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,PSP_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PSP_NS(uint32_t value)
+ {
+ __asm volatile("MSR PSP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_MSP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,MSP_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_MSP_NS(uint32_t value)
+ {
+ __asm volatile("MSR MSP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_SP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,SP_NS" : "=r" (res));
+ return res;
+ }
+ __IAR_FT void __TZ_set_SP_NS(uint32_t value)
+ {
+ __asm volatile("MSR SP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
+ {
+ __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
+ {
+ __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
+ {
+ __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
+ {
+ __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
+ }
+
+ #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+ __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+ {
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+ }
+
+ __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+ {
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+ }
+#endif
+
+#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+ __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+ {
+ uint32_t res;
+ __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+ {
+ uint32_t res;
+ __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+ {
+ uint32_t res;
+ __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return res;
+ }
+
+ __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+ {
+ __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+ }
+
+ __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+ {
+ __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+ }
+
+ __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+ {
+ __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+ }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+
+ __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return res;
+ }
+
+ __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+ {
+ __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+ {
+ __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+ {
+ __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#endif /* __CMSIS_ICCARM_H__ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Core/Include/cmsis_version.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Core/Include/cmsis_version.h
new file mode 100644
index 00000000..f2e27466
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Core/Include/cmsis_version.h
@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file cmsis_version.h
+ * @brief CMSIS Core(M) Version definitions
+ * @version V5.0.3
+ * @date 24. June 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/* CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+ __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
+#endif
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Core/Include/core_armv81mml.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Core/Include/core_armv81mml.h
new file mode 100644
index 00000000..8441e57f
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Core/Include/core_armv81mml.h
@@ -0,0 +1,2968 @@
+/**************************************************************************//**
+ * @file core_armv81mml.h
+ * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File
+ * @version V1.0.0
+ * @date 15. March 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2018-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV81MML_H_GENERIC
+#define __CORE_ARMV81MML_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv81MML */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ uint32_t RESERVED7[6U];
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[4U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */
+#define MPU_RLAR_PXN_Msk (0x1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h__Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MBL */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ uint32_t RESERVED0[6U];
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[809U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
+ uint32_t RESERVED4[4U];
+ __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ uint32_t RESERVED0[7U];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ If VTOR is not present address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h__Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MML */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[4U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[809U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
+ uint32_t RESERVED4[4U];
+ __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h__Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ uint32_t RESERVED0;
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ Address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t vectors = 0x0U;
+ (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
+ /* ARM Application Note 321 states that the M0 does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t vectors = 0x0U;
+ return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M0+ header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ If VTOR is not present address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t vectors = SCB->VTOR;
+#else
+ uint32_t vectors = 0x0U;
+#endif
+ (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
+ /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t vectors = SCB->VTOR;
+#else
+ uint32_t vectors = 0x0U;
+#endif
+ return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M1 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ uint32_t RESERVED0;
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
+
+#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M1 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ Address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)0x0U;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ /* ARM Application Note 321 states that the M1 does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)0x0U;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M23 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ uint32_t RESERVED0[6U];
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
+ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
+ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ uint32_t RESERVED0[7U];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ If VTOR is not present address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h__Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1[1U];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
+#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+#endif
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t vectors = (uint32_t )SCB->VTOR;
+ (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
+ /* ARM Application Note 321 states that the M3 does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t vectors = (uint32_t )SCB->VTOR;
+ return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M33 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[4U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
+ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
+ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h__Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M35P */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[4U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
+ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
+ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h__Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */
+#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t vectors = (uint32_t )SCB->VTOR;
+ (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
+ /* ARM Application Note 321 states that the M4 does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t vectors = (uint32_t )SCB->VTOR;
+ return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[1U];
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ uint32_t RESERVED3[93U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ uint32_t RESERVED7[6U];
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */
+#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */
+
+#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */
+#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */
+
+#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */
+#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */
+
+#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */
+#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */
+
+#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */
+#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */
+
+#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */
+#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */
+
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED3[981U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */
+#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t vectors = (uint32_t )SCB->VTOR;
+ (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t vectors = (uint32_t )SCB->VTOR;
+ return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = SCB->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## Cache functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_CacheFunctions Cache Functions
+ \brief Functions that configure Instruction and Data cache.
+ @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
+
+#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
+#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
+
+/**
+ \brief Enable I-Cache
+ \details Turns on I-Cache
+ */
+__STATIC_FORCEINLINE void SCB_EnableICache (void)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */
+
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */
+ __DSB();
+ __ISB();
+ SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Disable I-Cache
+ \details Turns off I-Cache
+ */
+__STATIC_FORCEINLINE void SCB_DisableICache (void)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Invalidate I-Cache
+ \details Invalidates I-Cache
+ */
+__STATIC_FORCEINLINE void SCB_InvalidateICache (void)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0UL;
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief I-Cache Invalidate by address
+ \details Invalidates I-Cache for the given address.
+ I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
+ I-Cache memory blocks which are part of given address + given size are invalidated.
+ \param[in] addr address
+ \param[in] isize size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ if ( isize > 0 ) {
+ int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
+ uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
+
+ __DSB();
+
+ do {
+ SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+ op_addr += __SCB_ICACHE_LINE_SIZE;
+ op_size -= __SCB_ICACHE_LINE_SIZE;
+ } while ( op_size > 0 );
+
+ __DSB();
+ __ISB();
+ }
+ #endif
+}
+
+
+/**
+ \brief Enable D-Cache
+ \details Turns on D-Cache
+ */
+__STATIC_FORCEINLINE void SCB_EnableDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */
+
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+ __DSB();
+
+ SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Disable D-Cache
+ \details Turns off D-Cache
+ */
+__STATIC_FORCEINLINE void SCB_DisableDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
+ __DSB();
+
+ SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean & invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Invalidate D-Cache
+ \details Invalidates D-Cache
+ */
+__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Clean D-Cache
+ \details Cleans D-Cache
+ */
+__STATIC_FORCEINLINE void SCB_CleanDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+ ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Clean & Invalidate D-Cache
+ \details Cleans and Invalidates D-Cache
+ */
+__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean & invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief D-Cache Invalidate by address
+ \details Invalidates D-Cache for the given address.
+ D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
+ D-Cache memory blocks which are part of given address + given size are invalidated.
+ \param[in] addr address
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ if ( dsize > 0 ) {
+ int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+ uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+
+ __DSB();
+
+ do {
+ SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+ op_addr += __SCB_DCACHE_LINE_SIZE;
+ op_size -= __SCB_DCACHE_LINE_SIZE;
+ } while ( op_size > 0 );
+
+ __DSB();
+ __ISB();
+ }
+ #endif
+}
+
+
+/**
+ \brief D-Cache Clean by address
+ \details Cleans D-Cache for the given address
+ D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.
+ D-Cache memory blocks which are part of given address + given size are cleaned.
+ \param[in] addr address
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ if ( dsize > 0 ) {
+ int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+ uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+
+ __DSB();
+
+ do {
+ SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+ op_addr += __SCB_DCACHE_LINE_SIZE;
+ op_size -= __SCB_DCACHE_LINE_SIZE;
+ } while ( op_size > 0 );
+
+ __DSB();
+ __ISB();
+ }
+ #endif
+}
+
+
+/**
+ \brief D-Cache Clean and Invalidate by address
+ \details Cleans and invalidates D_Cache for the given address
+ D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.
+ D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ if ( dsize > 0 ) {
+ int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+ uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+
+ __DSB();
+
+ do {
+ SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+ op_addr += __SCB_DCACHE_LINE_SIZE;
+ op_size -= __SCB_DCACHE_LINE_SIZE;
+ } while ( op_size > 0 );
+
+ __DSB();
+ __ISB();
+ }
+ #endif
+}
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ uint32_t RESERVED1[154U];
+ __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the SC000 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ uint32_t RESERVED1[129U];
+ __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t vectors = (uint32_t )SCB->VTOR;
+ (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
+ /* ARM Application Note 321 states that the M3 does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t vectors = (uint32_t )SCB->VTOR;
+ return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h
+
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in] module identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0 no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+
+#endif // TZ_CONTEXT_H
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Core/Template/ARMv8-M/main_s.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Core/Template/ARMv8-M/main_s.c
new file mode 100644
index 00000000..273607b2
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Core/Template/ARMv8-M/main_s.c
@@ -0,0 +1,58 @@
+/******************************************************************************
+ * @file main_s.c
+ * @brief Code template for secure main function
+ * @version V1.1.1
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* Use CMSE intrinsics */
+#include
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+/* TZ_START_NS: Start address of non-secure application */
+#ifndef TZ_START_NS
+#define TZ_START_NS (0x200000U)
+#endif
+
+/* typedef for non-secure callback functions */
+typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call));
+
+/* Secure main() */
+int main(void) {
+ funcptr_void NonSecure_ResetHandler;
+
+ /* Add user setup code for secure part here*/
+
+ /* Set non-secure main stack (MSP_NS) */
+ __TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS)));
+
+ /* Get non-secure reset handler */
+ NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U)));
+
+ /* Start non-secure state software application */
+ NonSecure_ResetHandler();
+
+ /* Non-secure software does not return, this code is not executed */
+ while (1) {
+ __NOP();
+ }
+}
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Core/Template/ARMv8-M/tz_context.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Core/Template/ARMv8-M/tz_context.c
new file mode 100644
index 00000000..e2e82942
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Core/Template/ARMv8-M/tz_context.c
@@ -0,0 +1,200 @@
+/******************************************************************************
+ * @file tz_context.c
+ * @brief Context Management for Armv8-M TrustZone - Sample implementation
+ * @version V1.1.1
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2016-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+#include "tz_context.h"
+
+/// Number of process slots (threads may call secure library code)
+#ifndef TZ_PROCESS_STACK_SLOTS
+#define TZ_PROCESS_STACK_SLOTS 8U
+#endif
+
+/// Stack size of the secure library code
+#ifndef TZ_PROCESS_STACK_SIZE
+#define TZ_PROCESS_STACK_SIZE 256U
+#endif
+
+typedef struct {
+ uint32_t sp_top; // stack space top
+ uint32_t sp_limit; // stack space limit
+ uint32_t sp; // current stack pointer
+} stack_info_t;
+
+static stack_info_t ProcessStackInfo [TZ_PROCESS_STACK_SLOTS];
+static uint64_t ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/8U];
+static uint32_t ProcessStackFreeSlot = 0xFFFFFFFFU;
+
+
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+__attribute__((cmse_nonsecure_entry))
+uint32_t TZ_InitContextSystem_S (void) {
+ uint32_t n;
+
+ if (__get_IPSR() == 0U) {
+ return 0U; // Thread Mode
+ }
+
+ for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) {
+ ProcessStackInfo[n].sp = 0U;
+ ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n];
+ ProcessStackInfo[n].sp_top = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE;
+ *((uint32_t *)ProcessStackMemory[n]) = n + 1U;
+ }
+ *((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU;
+
+ ProcessStackFreeSlot = 0U;
+
+ // Default process stack pointer and stack limit
+ __set_PSPLIM((uint32_t)ProcessStackMemory);
+ __set_PSP ((uint32_t)ProcessStackMemory);
+
+ // Privileged Thread Mode using PSP
+ __set_CONTROL(0x02U);
+
+ return 1U; // Success
+}
+
+
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in] module identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0 no memory available or internal error
+__attribute__((cmse_nonsecure_entry))
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module) {
+ uint32_t slot;
+
+ (void)module; // Ignore (fixed Stack size)
+
+ if (__get_IPSR() == 0U) {
+ return 0U; // Thread Mode
+ }
+
+ if (ProcessStackFreeSlot == 0xFFFFFFFFU) {
+ return 0U; // No slot available
+ }
+
+ slot = ProcessStackFreeSlot;
+ ProcessStackFreeSlot = *((uint32_t *)ProcessStackMemory[slot]);
+
+ ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top;
+
+ return (slot + 1U);
+}
+
+
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+__attribute__((cmse_nonsecure_entry))
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id) {
+ uint32_t slot;
+
+ if (__get_IPSR() == 0U) {
+ return 0U; // Thread Mode
+ }
+
+ if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
+ return 0U; // Invalid ID
+ }
+
+ slot = id - 1U;
+
+ if (ProcessStackInfo[slot].sp == 0U) {
+ return 0U; // Inactive slot
+ }
+ ProcessStackInfo[slot].sp = 0U;
+
+ *((uint32_t *)ProcessStackMemory[slot]) = ProcessStackFreeSlot;
+ ProcessStackFreeSlot = slot;
+
+ return 1U; // Success
+}
+
+
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+__attribute__((cmse_nonsecure_entry))
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id) {
+ uint32_t slot;
+
+ if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {
+ return 0U; // Thread Mode or using Main Stack for threads
+ }
+
+ if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
+ return 0U; // Invalid ID
+ }
+
+ slot = id - 1U;
+
+ if (ProcessStackInfo[slot].sp == 0U) {
+ return 0U; // Inactive slot
+ }
+
+ // Setup process stack pointer and stack limit
+ __set_PSPLIM(ProcessStackInfo[slot].sp_limit);
+ __set_PSP (ProcessStackInfo[slot].sp);
+
+ return 1U; // Success
+}
+
+
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+__attribute__((cmse_nonsecure_entry))
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id) {
+ uint32_t slot;
+ uint32_t sp;
+
+ if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {
+ return 0U; // Thread Mode or using Main Stack for threads
+ }
+
+ if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
+ return 0U; // Invalid ID
+ }
+
+ slot = id - 1U;
+
+ if (ProcessStackInfo[slot].sp == 0U) {
+ return 0U; // Inactive slot
+ }
+
+ sp = __get_PSP();
+ if ((sp < ProcessStackInfo[slot].sp_limit) ||
+ (sp > ProcessStackInfo[slot].sp_top)) {
+ return 0U; // SP out of range
+ }
+ ProcessStackInfo[slot].sp = sp;
+
+ // Default process stack pointer and stack limit
+ __set_PSPLIM((uint32_t)ProcessStackMemory);
+ __set_PSP ((uint32_t)ProcessStackMemory);
+
+ return 1U; // Success
+}
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u575xx.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u575xx.h
new file mode 100644
index 00000000..80dfccad
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u575xx.h
@@ -0,0 +1,662 @@
+/**
+ ******************************************************************************
+ * @file partition_stm32u575xx.h
+ * @author MCD Application Team
+ * @brief CMSIS STM32U575xx Device Initial Setup for Secure / Non-Secure Zones
+ * for ARMCM33 based on CMSIS CORE partition_ARMCM33.h Template.
+ *
+ * This file contains:
+ * - Initialize Security Attribution Unit (SAU) CTRL register
+ * - Setup behavior of Sleep and Exception Handling
+ * - Setup behavior of Floating Point Unit
+ * - Setup Interrupt Target
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Portions Copyright (c) 2021 STMicroelectronics, all rights reserved
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef PARTITION_STM32U575XX_H
+#define PARTITION_STM32U575XX_H
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+*/
+
+/*
+// Initialize Security Attribution Unit (SAU) CTRL register
+*/
+#define SAU_INIT_CTRL 1
+
+/*
+// Enable SAU
+// Value for SAU->CTRL register bit ENABLE
+*/
+#define SAU_INIT_CTRL_ENABLE 0
+
+/*
+// When SAU is disabled
+// <0=> All Memory is Secure
+// <1=> All Memory is Non-Secure
+// Value for SAU->CTRL register bit ALLNS
+// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
+*/
+#define SAU_INIT_CTRL_ALLNS 1
+
+/*
+//
+*/
+
+/*
+// Initialize Security Attribution Unit (SAU) Address Regions
+// SAU configuration specifies regions to be one of:
+// - Secure and Non-Secure Callable
+// - Non-Secure
+// Note: All memory regions not configured by SAU are Secure
+*/
+#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
+
+/*
+// Initialize SAU Region 0
+// Setup SAU Region 0 memory attributes
+*/
+#define SAU_INIT_REGION0 0
+
+/*
+// Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START0 0x0C0FE000 /* start address of SAU region 0 */
+
+/*
+// End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END0 0x0C0FFFFF /* end address of SAU region 0 */
+
+/*
+// Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC0 1
+/*
+//
+*/
+
+/*
+// Initialize SAU Region 1
+// Setup SAU Region 1 memory attributes
+*/
+#define SAU_INIT_REGION1 0
+
+/*
+// Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START1 0x08100000 /* start address of SAU region 1 */
+
+/*
+// End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END1 0x081FFFFF /* end address of SAU region 1 */
+
+/*
+// Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC1 0
+/*
+//
+*/
+
+/*
+// Initialize SAU Region 2
+// Setup SAU Region 2 memory attributes
+*/
+#define SAU_INIT_REGION2 0
+
+/*
+// Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START2 0x20040000 /* start address of SAU region 2 */
+
+/*
+// End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END2 0x200BFFFF /* end address of SAU region 2 */
+
+/*
+// Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC2 0
+/*
+//
+*/
+
+/*
+// Initialize SAU Region 3
+// Setup SAU Region 3 memory attributes
+*/
+#define SAU_INIT_REGION3 0
+
+/*
+// Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */
+
+/*
+// End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END3 0x4FFFFFFF /* end address of SAU region 3 */
+
+/*
+// Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC3 0
+/*
+//
+*/
+
+/*
+// Initialize SAU Region 4
+// Setup SAU Region 4 memory attributes
+*/
+#define SAU_INIT_REGION4 0
+
+/*
+// Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START4 0x60000000 /* start address of SAU region 4 */
+
+/*
+// End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END4 0x9FFFFFFF /* end address of SAU region 4 */
+
+/*
+// Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC4 0
+/*
+//
+*/
+
+/*
+// Initialize SAU Region 5
+// Setup SAU Region 5 memory attributes
+*/
+#define SAU_INIT_REGION5 0
+
+/*
+// Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START5 0x0BF90000 /* start address of SAU region 5 */
+
+/*
+// End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END5 0x0BFA8FFF /* end address of SAU region 5 */
+
+/*
+// Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC5 0
+/*
+//
+*/
+
+/*
+// Initialize SAU Region 6
+// Setup SAU Region 6 memory attributes
+*/
+#define SAU_INIT_REGION6 0
+
+/*
+// Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */
+
+/*
+// End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */
+
+/*
+// Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC6 0
+/*
+//
+*/
+
+/*
+// Initialize SAU Region 7
+// Setup SAU Region 7 memory attributes
+*/
+#define SAU_INIT_REGION7 0
+
+/*
+// Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */
+
+/*
+// End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */
+
+/*
+// Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC7 0
+/*
+//
+*/
+
+/*
+//
+*/
+
+/*
+// Setup behaviour of Sleep and Exception Handling
+*/
+#define SCB_CSR_AIRCR_INIT 0
+
+/*
+// Deep Sleep can be enabled by
+// <0=>Secure and Non-Secure state
+// <1=>Secure state only
+// Value for SCB->CSR register bit DEEPSLEEPS
+*/
+#define SCB_CSR_DEEPSLEEPS_VAL 0
+
+/*
+// System reset request accessible from
+// <0=> Secure and Non-Secure state
+// <1=> Secure state only
+// Value for SCB->AIRCR register bit SYSRESETREQS
+*/
+#define SCB_AIRCR_SYSRESETREQS_VAL 0
+
+/*
+// Priority of Non-Secure exceptions is
+// <0=> Not altered
+// <1=> Lowered to 0x04-0x07
+// Value for SCB->AIRCR register bit PRIS
+*/
+#define SCB_AIRCR_PRIS_VAL 0
+
+/*
+// BusFault, HardFault, and NMI target
+// <0=> Secure state
+// <1=> Non-Secure state
+// Value for SCB->AIRCR register bit BFHFNMINS
+*/
+#define SCB_AIRCR_BFHFNMINS_VAL 0
+
+/*
+//
+*/
+
+/*
+// Setup behaviour of Floating Point Unit
+*/
+#define TZ_FPU_NS_USAGE 1
+
+/*
+// Floating Point Unit usage
+// <0=> Secure state only
+// <3=> Secure and Non-Secure state
+// Value for SCB->NSACR register bits CP10, CP11
+*/
+#define SCB_NSACR_CP10_11_VAL 3
+
+/*
+// Treat floating-point registers as Secure
+// <0=> Disabled
+// <1=> Enabled
+// Value for FPU->FPCCR register bit TS
+*/
+#define FPU_FPCCR_TS_VAL 0
+
+/*
+// Clear on return (CLRONRET) accessibility
+// <0=> Secure and Non-Secure state
+// <1=> Secure state only
+// Value for FPU->FPCCR register bit CLRONRETS
+*/
+#define FPU_FPCCR_CLRONRETS_VAL 0
+
+/*
+// Clear floating-point caller saved registers on exception return
+// <0=> Disabled
+// <1=> Enabled
+// Value for FPU->FPCCR register bit CLRONRET
+*/
+#define FPU_FPCCR_CLRONRET_VAL 1
+
+/*
+//
+*/
+
+/*
+// Setup Interrupt Target
+*/
+
+/*
+// Initialize ITNS 0 (Interrupts 0..31)
+*/
+#define NVIC_INIT_ITNS0 1
+
+/*
+// Interrupts 0..31
+// WWDG_IRQn <0=> Secure state <1=> Non-Secure state
+// PVD_AVD_IRQn <0=> Secure state <1=> Non-Secure state
+// RTC_IRQn <0=> Secure state <1=> Non-Secure state
+// RTC_S_IRQn <0=> Secure state <1=> Non-Secure state
+// TAMP_IRQn <0=> Secure state <1=> Non-Secure state
+// RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state
+// FLASH_IRQn <0=> Secure state <1=> Non-Secure state
+// FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state
+// GTZC_IRQn <0=> Secure state <1=> Non-Secure state
+// RCC_IRQn <0=> Secure state <1=> Non-Secure state
+// RCC_S_IRQn <0=> Secure state <1=> Non-Secure state
+// EXTI0_IRQn <0=> Secure state <1=> Non-Secure state
+// EXTI1_IRQn <0=> Secure state <1=> Non-Secure state
+// EXTI2_IRQn <0=> Secure state <1=> Non-Secure state
+// EXTI3_IRQn <0=> Secure state <1=> Non-Secure state
+// EXTI4_IRQn <0=> Secure state <1=> Non-Secure state
+// EXTI5_IRQn <0=> Secure state <1=> Non-Secure state
+// EXTI6_IRQn <0=> Secure state <1=> Non-Secure state
+// EXTI7_IRQn <0=> Secure state <1=> Non-Secure state
+// EXTI8_IRQn <0=> Secure state <1=> Non-Secure state
+// EXTI9_IRQn <0=> Secure state <1=> Non-Secure state
+// EXTI10_IRQn <0=> Secure state <1=> Non-Secure state
+// EXTI11_IRQn <0=> Secure state <1=> Non-Secure state
+// EXTI12_IRQn <0=> Secure state <1=> Non-Secure state
+// EXTI13_IRQn <0=> Secure state <1=> Non-Secure state
+// EXTI14_IRQn <0=> Secure state <1=> Non-Secure state
+// EXTI15_IRQn <0=> Secure state <1=> Non-Secure state
+// IWDG_IRQn <0=> Secure state <1=> Non-Secure state
+// SAES_IRQn <0=> Secure state <1=> Non-Secure state
+// GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state
+// GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state
+// GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS0_VAL 0x00000000
+
+/*
+//
+*/
+
+/*
+// Initialize ITNS 1 (Interrupts 32..63)
+*/
+#define NVIC_INIT_ITNS1 1
+
+/*
+// Interrupts 32..63
+// GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state
+// GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state
+// GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state
+// GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state
+// GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state
+// ADC1_IRQn <0=> Secure state <1=> Non-Secure state
+// DAC1_IRQn <0=> Secure state <1=> Non-Secure state
+// FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state
+// FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state
+// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state
+// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state
+// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state
+// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state
+// TIM2_IRQn <0=> Secure state <1=> Non-Secure state
+// TIM3_IRQn <0=> Secure state <1=> Non-Secure state
+// TIM4_IRQn <0=> Secure state <1=> Non-Secure state
+// TIM5_IRQn <0=> Secure state <1=> Non-Secure state
+// TIM6_IRQn <0=> Secure state <1=> Non-Secure state
+// TIM7_IRQn <0=> Secure state <1=> Non-Secure state
+// TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state
+// TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state
+// TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state
+// TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state
+// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state
+// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state
+// I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state
+// I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state
+// SPI1_IRQn <0=> Secure state <1=> Non-Secure state
+// SPI2_IRQn <0=> Secure state <1=> Non-Secure state
+// USART1_IRQn <0=> Secure state <1=> Non-Secure state
+// USART2_IRQn <0=> Secure state <1=> Non-Secure state
+// USART3_IRQn <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS1_VAL 0x00000000
+
+/*
+//
+*/
+
+/*
+// Initialize ITNS 2 (Interrupts 64..95)
+*/
+#define NVIC_INIT_ITNS2 1
+
+/*
+// Interrupts 64..95
+// UART4_IRQn <0=> Secure state <1=> Non-Secure state
+// UART5_IRQn <0=> Secure state <1=> Non-Secure state
+// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state
+// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state
+// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state
+// TIM15_IRQn <0=> Secure state <1=> Non-Secure state
+// TIM16_IRQn <0=> Secure state <1=> Non-Secure state
+// TIM17_IRQn <0=> Secure state <1=> Non-Secure state
+// COMP_IRQn <0=> Secure state <1=> Non-Secure state
+// OTG_FS_IRQn <0=> Secure state <1=> Non-Secure state
+// CRS_IRQn <0=> Secure state <1=> Non-Secure state
+// FMC_IRQn <0=> Secure state <1=> Non-Secure state
+// OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state
+// PWR_S3WU_IRQn <0=> Secure state <1=> Non-Secure state
+// SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state
+// SDMMC2_IRQn <0=> Secure state <1=> Non-Secure state
+// GPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state
+// GPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state
+// GPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state
+// GPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state
+// GPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state
+// GPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state
+// GPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state
+// GPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state
+// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state
+// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state
+// SAI1_IRQn <0=> Secure state <1=> Non-Secure state
+// SAI2_IRQn <0=> Secure state <1=> Non-Secure state
+// TSC_IRQn <0=> Secure state <1=> Non-Secure state
+// AES_IRQn <0=> Secure state <1=> Non-Secure state
+// RNG_IRQn <0=> Secure state <1=> Non-Secure state
+// FPU_IRQn <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS2_VAL 0x00000000
+
+/*
+//
+*/
+
+/*
+// Initialize ITNS 3 (Interrupts 96..108)
+*/
+#define NVIC_INIT_ITNS3 1
+
+/*
+// Interrupts 96..125
+// HASH_IRQn <0=> Secure state <1=> Non-Secure state
+// PKA_IRQn <0=> Secure state <1=> Non-Secure state
+// LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state
+// SPI3_IRQn <0=> Secure state <1=> Non-Secure state
+// I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state
+// I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state
+// MDF1_FLT0_IRQn <0=> Secure state <1=> Non-Secure state
+// MDF1_FLT1_IRQn <0=> Secure state <1=> Non-Secure state
+// MDF1_FLT2_IRQn <0=> Secure state <1=> Non-Secure state
+// MDF1_FLT3_IRQn <0=> Secure state <1=> Non-Secure state
+// UCPD1_IRQn <0=> Secure state <1=> Non-Secure state
+// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state
+// OTFDEC1_IRQn <0=> Secure state <1=> Non-Secure state
+// OTFDEC2_IRQn <0=> Secure state <1=> Non-Secure state
+// LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state
+// DCACHE1_IRQn <0=> Secure state <1=> Non-Secure state
+// ADF1_IRQn <0=> Secure state <1=> Non-Secure state
+// ADC4_IRQn <0=> Secure state <1=> Non-Secure state
+// LPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state
+// LPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state
+// LPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state
+// LPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state
+// DMA2D_IRQn <0=> Secure state <1=> Non-Secure state
+// DCMI_PSSI_IRQN <0=> Secure state <1=> Non-Secure state
+// OCTOSPI2_IRQn <0=> Secure state <1=> Non-Secure state
+// MDF1_FLT4_IRQn <0=> Secure state <1=> Non-Secure state
+// MDF1_FLT5_IRQn <0=> Secure state <1=> Non-Secure state
+// CORDIC_IRQn <0=> Secure state <1=> Non-Secure state
+// FMAC_IRQn <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS3_VAL 0x00000000
+
+/*
+//
+*/
+
+/*
+//
+*/
+
+/*
+ max 8 SAU regions.
+ SAU regions are defined in partition.h
+ */
+
+#define SAU_INIT_REGION(n) \
+ SAU->RNR = (n & SAU_RNR_REGION_Msk); \
+ SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
+ SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
+ ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
+
+/**
+ \brief Setup a SAU Region
+ \details Writes the region information contained in SAU_Region to the
+ registers SAU_RNR, SAU_RBAR, and SAU_RLAR
+ */
+__STATIC_INLINE void TZ_SAU_Setup (void)
+{
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+
+ #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
+ SAU_INIT_REGION(0);
+ #endif
+
+ #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
+ SAU_INIT_REGION(1);
+ #endif
+
+ #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
+ SAU_INIT_REGION(2);
+ #endif
+
+ #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
+ SAU_INIT_REGION(3);
+ #endif
+
+ #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
+ SAU_INIT_REGION(4);
+ #endif
+
+ #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
+ SAU_INIT_REGION(5);
+ #endif
+
+ #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
+ SAU_INIT_REGION(6);
+ #endif
+
+ #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
+ SAU_INIT_REGION(7);
+ #endif
+
+ /* repeat this for all possible SAU regions */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+
+ #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
+ SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
+ ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
+ #endif
+
+ #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
+ SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
+ ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
+
+ SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
+ SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) |
+ ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
+ ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
+ ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
+ ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
+ #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
+
+ #if defined (__FPU_USED) && (__FPU_USED == 1U) && \
+ defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
+
+ SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
+ ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
+
+ FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
+ ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) |
+ ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
+ ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
+ #endif
+
+ #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
+ NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
+ NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
+ NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
+ NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
+ #endif
+
+}
+
+#endif /* PARTITION_STM32U575XX_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u585xx.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u585xx.h
new file mode 100644
index 00000000..45e8a47d
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u585xx.h
@@ -0,0 +1,662 @@
+/**
+ ******************************************************************************
+ * @file partition_stm32u585xx.h
+ * @author MCD Application Team
+ * @brief CMSIS STM32U585xx Device Initial Setup for Secure / Non-Secure Zones
+ * for ARMCM33 based on CMSIS CORE partition_ARMCM33.h Template.
+ *
+ * This file contains:
+ * - Initialize Security Attribution Unit (SAU) CTRL register
+ * - Setup behavior of Sleep and Exception Handling
+ * - Setup behavior of Floating Point Unit
+ * - Setup Interrupt Target
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Portions Copyright (c) 2021 STMicroelectronics, all rights reserved
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef PARTITION_STM32U585XX_H
+#define PARTITION_STM32U585XX_H
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+*/
+
+/*
+// Initialize Security Attribution Unit (SAU) CTRL register
+*/
+#define SAU_INIT_CTRL 1
+
+/*
+// Enable SAU
+// Value for SAU->CTRL register bit ENABLE
+*/
+#define SAU_INIT_CTRL_ENABLE 0
+
+/*
+// When SAU is disabled
+// <0=> All Memory is Secure
+// <1=> All Memory is Non-Secure
+// Value for SAU->CTRL register bit ALLNS
+// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
+*/
+#define SAU_INIT_CTRL_ALLNS 1
+
+/*
+//
+*/
+
+/*
+// Initialize Security Attribution Unit (SAU) Address Regions
+// SAU configuration specifies regions to be one of:
+// - Secure and Non-Secure Callable
+// - Non-Secure
+// Note: All memory regions not configured by SAU are Secure
+*/
+#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
+
+/*
+// Initialize SAU Region 0
+// Setup SAU Region 0 memory attributes
+*/
+#define SAU_INIT_REGION0 0
+
+/*
+// Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START0 0x0C0FE000 /* start address of SAU region 0 */
+
+/*
+// End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END0 0x0C0FFFFF /* end address of SAU region 0 */
+
+/*
+// Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC0 1
+/*
+//
+*/
+
+/*
+// Initialize SAU Region 1
+// Setup SAU Region 1 memory attributes
+*/
+#define SAU_INIT_REGION1 0
+
+/*
+// Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START1 0x08100000 /* start address of SAU region 1 */
+
+/*
+// End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END1 0x081FFFFF /* end address of SAU region 1 */
+
+/*
+// Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC1 0
+/*
+//
+*/
+
+/*
+// Initialize SAU Region 2
+// Setup SAU Region 2 memory attributes
+*/
+#define SAU_INIT_REGION2 0
+
+/*
+// Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START2 0x20040000 /* start address of SAU region 2 */
+
+/*
+// End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END2 0x200BFFFF /* end address of SAU region 2 */
+
+/*
+// Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC2 0
+/*
+//
+*/
+
+/*
+// Initialize SAU Region 3
+// Setup SAU Region 3 memory attributes
+*/
+#define SAU_INIT_REGION3 0
+
+/*
+// Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */
+
+/*
+// End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END3 0x4FFFFFFF /* end address of SAU region 3 */
+
+/*
+// Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC3 0
+/*
+//
+*/
+
+/*
+// Initialize SAU Region 4
+// Setup SAU Region 4 memory attributes
+*/
+#define SAU_INIT_REGION4 0
+
+/*
+// Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START4 0x60000000 /* start address of SAU region 4 */
+
+/*
+// End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END4 0x9FFFFFFF /* end address of SAU region 4 */
+
+/*
+// Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC4 0
+/*
+//
+*/
+
+/*
+// Initialize SAU Region 5
+// Setup SAU Region 5 memory attributes
+*/
+#define SAU_INIT_REGION5 0
+
+/*
+// Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START5 0x0BF90000 /* start address of SAU region 5 */
+
+/*
+// End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END5 0x0BFA8FFF /* end address of SAU region 5 */
+
+/*
+// Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC5 0
+/*
+//
+*/
+
+/*
+// Initialize SAU Region 6
+// Setup SAU Region 6 memory attributes
+*/
+#define SAU_INIT_REGION6 0
+
+/*
+// Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */
+
+/*
+// End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */
+
+/*
+// Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC6 0
+/*
+//
+*/
+
+/*
+// Initialize SAU Region 7
+// Setup SAU Region 7 memory attributes
+*/
+#define SAU_INIT_REGION7 0
+
+/*
+// Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */
+
+/*
+// End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */
+
+/*
+// Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC7 0
+/*
+//
+*/
+
+/*
+//
+*/
+
+/*
+// Setup behaviour of Sleep and Exception Handling
+*/
+#define SCB_CSR_AIRCR_INIT 0
+
+/*
+// Deep Sleep can be enabled by
+// <0=>Secure and Non-Secure state
+// <1=>Secure state only
+// Value for SCB->CSR register bit DEEPSLEEPS
+*/
+#define SCB_CSR_DEEPSLEEPS_VAL 0
+
+/*
+// System reset request accessible from
+// <0=> Secure and Non-Secure state
+// <1=> Secure state only
+// Value for SCB->AIRCR register bit SYSRESETREQS
+*/
+#define SCB_AIRCR_SYSRESETREQS_VAL 0
+
+/*
+// Priority of Non-Secure exceptions is
+// <0=> Not altered
+// <1=> Lowered to 0x04-0x07
+// Value for SCB->AIRCR register bit PRIS
+*/
+#define SCB_AIRCR_PRIS_VAL 0
+
+/*
+// BusFault, HardFault, and NMI target
+// <0=> Secure state
+// <1=> Non-Secure state
+// Value for SCB->AIRCR register bit BFHFNMINS
+*/
+#define SCB_AIRCR_BFHFNMINS_VAL 0
+
+/*
+//
+*/
+
+/*
+// Setup behaviour of Floating Point Unit
+*/
+#define TZ_FPU_NS_USAGE 1
+
+/*
+// Floating Point Unit usage
+// <0=> Secure state only
+// <3=> Secure and Non-Secure state
+// Value for SCB->NSACR register bits CP10, CP11
+*/
+#define SCB_NSACR_CP10_11_VAL 3
+
+/*
+// Treat floating-point registers as Secure
+// <0=> Disabled
+// <1=> Enabled
+// Value for FPU->FPCCR register bit TS
+*/
+#define FPU_FPCCR_TS_VAL 0
+
+/*
+// Clear on return (CLRONRET) accessibility
+// <0=> Secure and Non-Secure state
+// <1=> Secure state only
+// Value for FPU->FPCCR register bit CLRONRETS
+*/
+#define FPU_FPCCR_CLRONRETS_VAL 0
+
+/*
+// Clear floating-point caller saved registers on exception return
+// <0=> Disabled
+// <1=> Enabled
+// Value for FPU->FPCCR register bit CLRONRET
+*/
+#define FPU_FPCCR_CLRONRET_VAL 1
+
+/*
+//
+*/
+
+/*
+// Setup Interrupt Target
+*/
+
+/*
+// Initialize ITNS 0 (Interrupts 0..31)
+*/
+#define NVIC_INIT_ITNS0 1
+
+/*
+// Interrupts 0..31
+// WWDG_IRQn <0=> Secure state <1=> Non-Secure state
+// PVD_AVD_IRQn <0=> Secure state <1=> Non-Secure state
+// RTC_IRQn <0=> Secure state <1=> Non-Secure state
+// RTC_S_IRQn <0=> Secure state <1=> Non-Secure state
+// TAMP_IRQn <0=> Secure state <1=> Non-Secure state
+// RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state
+// FLASH_IRQn <0=> Secure state <1=> Non-Secure state
+// FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state
+// GTZC_IRQn <0=> Secure state <1=> Non-Secure state
+// RCC_IRQn <0=> Secure state <1=> Non-Secure state
+// RCC_S_IRQn <0=> Secure state <1=> Non-Secure state
+// EXTI0_IRQn <0=> Secure state <1=> Non-Secure state
+// EXTI1_IRQn <0=> Secure state <1=> Non-Secure state
+// EXTI2_IRQn <0=> Secure state <1=> Non-Secure state
+// EXTI3_IRQn <0=> Secure state <1=> Non-Secure state
+// EXTI4_IRQn <0=> Secure state <1=> Non-Secure state
+// EXTI5_IRQn <0=> Secure state <1=> Non-Secure state
+// EXTI6_IRQn <0=> Secure state <1=> Non-Secure state
+// EXTI7_IRQn <0=> Secure state <1=> Non-Secure state
+// EXTI8_IRQn <0=> Secure state <1=> Non-Secure state
+// EXTI9_IRQn <0=> Secure state <1=> Non-Secure state
+// EXTI10_IRQn <0=> Secure state <1=> Non-Secure state
+// EXTI11_IRQn <0=> Secure state <1=> Non-Secure state
+// EXTI12_IRQn <0=> Secure state <1=> Non-Secure state
+// EXTI13_IRQn <0=> Secure state <1=> Non-Secure state
+// EXTI14_IRQn <0=> Secure state <1=> Non-Secure state
+// EXTI15_IRQn <0=> Secure state <1=> Non-Secure state
+// IWDG_IRQn <0=> Secure state <1=> Non-Secure state
+// SAES_IRQn <0=> Secure state <1=> Non-Secure state
+// GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state
+// GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state
+// GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS0_VAL 0x00000000
+
+/*
+//
+*/
+
+/*
+// Initialize ITNS 1 (Interrupts 32..63)
+*/
+#define NVIC_INIT_ITNS1 1
+
+/*
+// Interrupts 32..63
+// GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state
+// GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state
+// GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state
+// GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state
+// GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state
+// ADC1_IRQn <0=> Secure state <1=> Non-Secure state
+// DAC1_IRQn <0=> Secure state <1=> Non-Secure state
+// FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state
+// FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state
+// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state
+// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state
+// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state
+// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state
+// TIM2_IRQn <0=> Secure state <1=> Non-Secure state
+// TIM3_IRQn <0=> Secure state <1=> Non-Secure state
+// TIM4_IRQn <0=> Secure state <1=> Non-Secure state
+// TIM5_IRQn <0=> Secure state <1=> Non-Secure state
+// TIM6_IRQn <0=> Secure state <1=> Non-Secure state
+// TIM7_IRQn <0=> Secure state <1=> Non-Secure state
+// TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state
+// TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state
+// TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state
+// TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state
+// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state
+// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state
+// I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state
+// I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state
+// SPI1_IRQn <0=> Secure state <1=> Non-Secure state
+// SPI2_IRQn <0=> Secure state <1=> Non-Secure state
+// USART1_IRQn <0=> Secure state <1=> Non-Secure state
+// USART2_IRQn <0=> Secure state <1=> Non-Secure state
+// USART3_IRQn <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS1_VAL 0x00000000
+
+/*
+//
+*/
+
+/*
+// Initialize ITNS 2 (Interrupts 64..95)
+*/
+#define NVIC_INIT_ITNS2 1
+
+/*
+// Interrupts 64..95
+// UART4_IRQn <0=> Secure state <1=> Non-Secure state
+// UART5_IRQn <0=> Secure state <1=> Non-Secure state
+// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state
+// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state
+// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state
+// TIM15_IRQn <0=> Secure state <1=> Non-Secure state
+// TIM16_IRQn <0=> Secure state <1=> Non-Secure state
+// TIM17_IRQn <0=> Secure state <1=> Non-Secure state
+// COMP_IRQn <0=> Secure state <1=> Non-Secure state
+// OTG_FS_IRQn <0=> Secure state <1=> Non-Secure state
+// CRS_IRQn <0=> Secure state <1=> Non-Secure state
+// FMC_IRQn <0=> Secure state <1=> Non-Secure state
+// OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state
+// PWR_S3WU_IRQn <0=> Secure state <1=> Non-Secure state
+// SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state
+// SDMMC2_IRQn <0=> Secure state <1=> Non-Secure state
+// GPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state
+// GPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state
+// GPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state
+// GPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state
+// GPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state
+// GPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state
+// GPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state
+// GPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state
+// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state
+// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state
+// SAI1_IRQn <0=> Secure state <1=> Non-Secure state
+// SAI2_IRQn <0=> Secure state <1=> Non-Secure state
+// TSC_IRQn <0=> Secure state <1=> Non-Secure state
+// AES_IRQn <0=> Secure state <1=> Non-Secure state
+// RNG_IRQn <0=> Secure state <1=> Non-Secure state
+// FPU_IRQn <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS2_VAL 0x00000000
+
+/*
+//
+*/
+
+/*
+// Initialize ITNS 3 (Interrupts 96..108)
+*/
+#define NVIC_INIT_ITNS3 1
+
+/*
+// Interrupts 96..125
+// HASH_IRQn <0=> Secure state <1=> Non-Secure state
+// PKA_IRQn <0=> Secure state <1=> Non-Secure state
+// LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state
+// SPI3_IRQn <0=> Secure state <1=> Non-Secure state
+// I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state
+// I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state
+// MDF1_FLT0_IRQn <0=> Secure state <1=> Non-Secure state
+// MDF1_FLT1_IRQn <0=> Secure state <1=> Non-Secure state
+// MDF1_FLT2_IRQn <0=> Secure state <1=> Non-Secure state
+// MDF1_FLT3_IRQn <0=> Secure state <1=> Non-Secure state
+// UCPD1_IRQn <0=> Secure state <1=> Non-Secure state
+// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state
+// OTFDEC1_IRQn <0=> Secure state <1=> Non-Secure state
+// OTFDEC2_IRQn <0=> Secure state <1=> Non-Secure state
+// LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state
+// DCACHE1_IRQn <0=> Secure state <1=> Non-Secure state
+// ADF1_IRQn <0=> Secure state <1=> Non-Secure state
+// ADC4_IRQn <0=> Secure state <1=> Non-Secure state
+// LPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state
+// LPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state
+// LPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state
+// LPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state
+// DMA2D_IRQn <0=> Secure state <1=> Non-Secure state
+// DCMI_PSSI_IRQN <0=> Secure state <1=> Non-Secure state
+// OCTOSPI2_IRQn <0=> Secure state <1=> Non-Secure state
+// MDF1_FLT4_IRQn <0=> Secure state <1=> Non-Secure state
+// MDF1_FLT5_IRQn <0=> Secure state <1=> Non-Secure state
+// CORDIC_IRQn <0=> Secure state <1=> Non-Secure state
+// FMAC_IRQn <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS3_VAL 0x00000000
+
+/*
+//
+*/
+
+/*
+//
+*/
+
+/*
+ max 8 SAU regions.
+ SAU regions are defined in partition.h
+ */
+
+#define SAU_INIT_REGION(n) \
+ SAU->RNR = (n & SAU_RNR_REGION_Msk); \
+ SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
+ SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
+ ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
+
+/**
+ \brief Setup a SAU Region
+ \details Writes the region information contained in SAU_Region to the
+ registers SAU_RNR, SAU_RBAR, and SAU_RLAR
+ */
+__STATIC_INLINE void TZ_SAU_Setup (void)
+{
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+
+ #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
+ SAU_INIT_REGION(0);
+ #endif
+
+ #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
+ SAU_INIT_REGION(1);
+ #endif
+
+ #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
+ SAU_INIT_REGION(2);
+ #endif
+
+ #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
+ SAU_INIT_REGION(3);
+ #endif
+
+ #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
+ SAU_INIT_REGION(4);
+ #endif
+
+ #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
+ SAU_INIT_REGION(5);
+ #endif
+
+ #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
+ SAU_INIT_REGION(6);
+ #endif
+
+ #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
+ SAU_INIT_REGION(7);
+ #endif
+
+ /* repeat this for all possible SAU regions */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+
+ #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
+ SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
+ ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
+ #endif
+
+ #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
+ SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
+ ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
+
+ SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
+ SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) |
+ ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
+ ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
+ ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
+ ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
+ #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
+
+ #if defined (__FPU_USED) && (__FPU_USED == 1U) && \
+ defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
+
+ SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
+ ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
+
+ FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
+ ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) |
+ ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
+ ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
+ #endif
+
+ #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
+ NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
+ NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
+ NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
+ NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
+ #endif
+
+}
+
+#endif /* PARTITION_STM32U585XX_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Device/ST/STM32U5xx/Include/partition_stm32u5xx.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Device/ST/STM32U5xx/Include/partition_stm32u5xx.h
new file mode 100644
index 00000000..7e1296bd
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Device/ST/STM32U5xx/Include/partition_stm32u5xx.h
@@ -0,0 +1,69 @@
+/**
+ ******************************************************************************
+ * @file partition_stm32u5xx.h
+ * @author MCD Application Team
+ * @brief CMSIS STM32U5xx Device Header File for Initial Setup for
+ * Secure / Non-Secure Zones based on CMSIS CORE V5.4.0
+ *
+ * The file is included in system_stm32u5xx_s.c in secure application.
+ * It includes the configuration section that allows to select the
+ * STM32U5xx device partitioning file for system core secure attributes
+ * and interrupt secure and non-secure assignment.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32u5xx
+ * @{
+ */
+
+#ifndef PARTITION_STM32U5XX_H
+#define PARTITION_STM32U5XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Secure_configuration_section
+ * @{
+ */
+
+#if defined(STM32U575xx)
+ #include "partition_stm32u575xx.h"
+#elif defined(STM32U585xx)
+ #include "partition_stm32u585xx.h"
+#else
+ #error "Please select first the target STM32U5xx device used in your application (in stm32u5xx.h file)"
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* PARTITION_STM32U5XX_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u575xx.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u575xx.h
new file mode 100644
index 00000000..9b64eb9d
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u575xx.h
@@ -0,0 +1,23808 @@
+/**
+ ******************************************************************************
+ * @file stm32u575xx.h
+ * @author MCD Application Team
+ * @brief CMSIS STM32U575xx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+#ifndef STM32U575xx_H
+#define STM32U575xx_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup ST
+ * @{
+ */
+
+
+/** @addtogroup STM32U575xx
+ * @{
+ */
+
+
+/** @addtogroup Configuration_of_CMSIS
+ * @{
+ */
+
+
+/* =========================================================================================================================== */
+/* ================ Interrupt Number Definition ================ */
+/* =========================================================================================================================== */
+
+typedef enum
+{
+/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */
+ Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
+ MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation
+ and No Match */
+ BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
+ related Fault */
+ UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+ SecureFault_IRQn = -9, /*!< -9 Secure Fault */
+ SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
+ PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< -1 System Tick Timer */
+
+/* =========================================== STM32U575xx Specific Interrupt Numbers ================================= */
+ WWDG_IRQn = 0, /*!< Window WatchDog interrupt */
+ PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */
+ RTC_IRQn = 2, /*!< RTC non-secure interrupt */
+ RTC_S_IRQn = 3, /*!< RTC secure interrupt */
+ TAMP_IRQn = 4, /*!< Tamper non-secure interrupt */
+ RAMCFG_IRQn = 5, /*!< RAMCFG global interrupt */
+ FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt */
+ FLASH_S_IRQn = 7, /*!< FLASH secure global interrupt */
+ GTZC_IRQn = 8, /*!< Global TrustZone Controller interrupt */
+ RCC_IRQn = 9, /*!< RCC non secure global interrupt */
+ RCC_S_IRQn = 10, /*!< RCC secure global interrupt */
+ EXTI0_IRQn = 11, /*!< EXTI Line0 interrupt */
+ EXTI1_IRQn = 12, /*!< EXTI Line1 interrupt */
+ EXTI2_IRQn = 13, /*!< EXTI Line2 interrupt */
+ EXTI3_IRQn = 14, /*!< EXTI Line3 interrupt */
+ EXTI4_IRQn = 15, /*!< EXTI Line4 interrupt */
+ EXTI5_IRQn = 16, /*!< EXTI Line5 interrupt */
+ EXTI6_IRQn = 17, /*!< EXTI Line6 interrupt */
+ EXTI7_IRQn = 18, /*!< EXTI Line7 interrupt */
+ EXTI8_IRQn = 19, /*!< EXTI Line8 interrupt */
+ EXTI9_IRQn = 20, /*!< EXTI Line9 interrupt */
+ EXTI10_IRQn = 21, /*!< EXTI Line10 interrupt */
+ EXTI11_IRQn = 22, /*!< EXTI Line11 interrupt */
+ EXTI12_IRQn = 23, /*!< EXTI Line12 interrupt */
+ EXTI13_IRQn = 24, /*!< EXTI Line13 interrupt */
+ EXTI14_IRQn = 25, /*!< EXTI Line14 interrupt */
+ EXTI15_IRQn = 26, /*!< EXTI Line15 interrupt */
+ IWDG_IRQn = 27, /*!< IWDG global interrupt */
+ GPDMA1_Channel0_IRQn = 29, /*!< GPDMA1 Channel 0 global interrupt */
+ GPDMA1_Channel1_IRQn = 30, /*!< GPDMA1 Channel 1 global interrupt */
+ GPDMA1_Channel2_IRQn = 31, /*!< GPDMA1 Channel 2 global interrupt */
+ GPDMA1_Channel3_IRQn = 32, /*!< GPDMA1 Channel 3 global interrupt */
+ GPDMA1_Channel4_IRQn = 33, /*!< GPDMA1 Channel 4 global interrupt */
+ GPDMA1_Channel5_IRQn = 34, /*!< GPDMA1 Channel 5 global interrupt */
+ GPDMA1_Channel6_IRQn = 35, /*!< GPDMA1 Channel 6 global interrupt */
+ GPDMA1_Channel7_IRQn = 36, /*!< GPDMA1 Channel 7 global interrupt */
+ ADC1_IRQn = 37, /*!< ADC1 global interrupt */
+ DAC1_IRQn = 38, /*!< DAC1 global interrupt */
+ FDCAN1_IT0_IRQn = 39, /*!< FDCAN1 interrupt 0 */
+ FDCAN1_IT1_IRQn = 40, /*!< FDCAN1 interrupt 1 */
+ TIM1_BRK_IRQn = 41, /*!< TIM1 Break interrupt */
+ TIM1_UP_IRQn = 42, /*!< TIM1 Update interrupt */
+ TIM1_TRG_COM_IRQn = 43, /*!< TIM1 Trigger and Commutation interrupt */
+ TIM1_CC_IRQn = 44, /*!< TIM1 Capture Compare interrupt */
+ TIM2_IRQn = 45, /*!< TIM2 global interrupt */
+ TIM3_IRQn = 46, /*!< TIM3 global interrupt */
+ TIM4_IRQn = 47, /*!< TIM4 global interrupt */
+ TIM5_IRQn = 48, /*!< TIM5 global interrupt */
+ TIM6_IRQn = 49, /*!< TIM6 global interrupt */
+ TIM7_IRQn = 50, /*!< TIM7 global interrupt */
+ TIM8_BRK_IRQn = 51, /*!< TIM8 Break interrupt */
+ TIM8_UP_IRQn = 52, /*!< TIM8 Update interrupt */
+ TIM8_TRG_COM_IRQn = 53, /*!< TIM8 Trigger and Commutation interrupt */
+ TIM8_CC_IRQn = 54, /*!< TIM8 Capture Compare interrupt */
+ I2C1_EV_IRQn = 55, /*!< I2C1 Event interrupt */
+ I2C1_ER_IRQn = 56, /*!< I2C1 Error interrupt */
+ I2C2_EV_IRQn = 57, /*!< I2C2 Event interrupt */
+ I2C2_ER_IRQn = 58, /*!< I2C2 Error interrupt */
+ SPI1_IRQn = 59, /*!< SPI1 global interrupt */
+ SPI2_IRQn = 60, /*!< SPI2 global interrupt */
+ USART1_IRQn = 61, /*!< USART1 global interrupt */
+ USART2_IRQn = 62, /*!< USART2 global interrupt */
+ USART3_IRQn = 63, /*!< USART3 global interrupt */
+ UART4_IRQn = 64, /*!< UART4 global interrupt */
+ UART5_IRQn = 65, /*!< UART5 global interrupt */
+ LPUART1_IRQn = 66, /*!< LPUART1 global interrupt */
+ LPTIM1_IRQn = 67, /*!< LPTIM1 global interrupt */
+ LPTIM2_IRQn = 68, /*!< LPTIM2 global interrupt */
+ TIM15_IRQn = 69, /*!< TIM15 global interrupt */
+ TIM16_IRQn = 70, /*!< TIM16 global interrupt */
+ TIM17_IRQn = 71, /*!< TIM17 global interrupt */
+ COMP_IRQn = 72, /*!< COMP1 and COMP2 through EXTI Lines interrupts */
+ OTG_FS_IRQn = 73, /*!< USB OTG FS global interrupt */
+ CRS_IRQn = 74, /*!< CRS global interrupt */
+ FMC_IRQn = 75, /*!< FSMC global interrupt */
+ OCTOSPI1_IRQn = 76, /*!< OctoSPI1 global interrupt */
+ PWR_S3WU_IRQn = 77, /*!< PWR wake up from Stop3 interrupt */
+ SDMMC1_IRQn = 78, /*!< SDMMC1 global interrupt */
+ SDMMC2_IRQn = 79, /*!< SDMMC2 global interrupt */
+ GPDMA1_Channel8_IRQn = 80, /*!< GPDMA1 Channel 8 global interrupt */
+ GPDMA1_Channel9_IRQn = 81, /*!< GPDMA1 Channel 9 global interrupt */
+ GPDMA1_Channel10_IRQn = 82, /*!< GPDMA1 Channel 10 global interrupt */
+ GPDMA1_Channel11_IRQn = 83, /*!< GPDMA1 Channel 11 global interrupt */
+ GPDMA1_Channel12_IRQn = 84, /*!< GPDMA1 Channel 12 global interrupt */
+ GPDMA1_Channel13_IRQn = 85, /*!< GPDMA1 Channel 13 global interrupt */
+ GPDMA1_Channel14_IRQn = 86, /*!< GPDMA1 Channel 14 global interrupt */
+ GPDMA1_Channel15_IRQn = 87, /*!< GPDMA1 Channel 15 global interrupt */
+ I2C3_EV_IRQn = 88, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 89, /*!< I2C3 error interrupt */
+ SAI1_IRQn = 90, /*!< Serial Audio Interface 1 global interrupt */
+ SAI2_IRQn = 91, /*!< Serial Audio Interface 2 global interrupt */
+ TSC_IRQn = 92, /*!< Touch Sense Controller global interrupt */
+ RNG_IRQn = 94, /*!< RNG global interrupt */
+ FPU_IRQn = 95, /*!< FPU global interrupt */
+ HASH_IRQn = 96, /*!< HASH global interrupt */
+ LPTIM3_IRQn = 98, /*!< LPTIM3 global interrupt */
+ SPI3_IRQn = 99, /*!< SPI3 global interrupt */
+ I2C4_ER_IRQn = 100, /*!< I2C4 Error interrupt */
+ I2C4_EV_IRQn = 101, /*!< I2C4 Event interrupt */
+ MDF1_FLT0_IRQn = 102, /*!< MDF1 Filter 0 global interrupt */
+ MDF1_FLT1_IRQn = 103, /*!< MDF1 Filter 1 global interrupt */
+ MDF1_FLT2_IRQn = 104, /*!< MDF1 Filter 2 global interrupt */
+ MDF1_FLT3_IRQn = 105, /*!< MDF1 Filter 3 global interrupt */
+ UCPD1_IRQn = 106, /*!< UCPD1 global interrupt */
+ ICACHE_IRQn = 107, /*!< Instruction cache global interrupt */
+ LPTIM4_IRQn = 110, /*!< LPTIM4 global interrupt */
+ DCACHE1_IRQn = 111, /*!< Data cache global interrupt */
+ ADF1_IRQn = 112, /*!< ADF interrupt */
+ ADC4_IRQn = 113, /*!< ADC4 (12bits) global interrupt */
+ LPDMA1_Channel0_IRQn = 114, /*!< LPDMA1 SmartRun Channel 0 global interrupt */
+ LPDMA1_Channel1_IRQn = 115, /*!< LPDMA1 SmartRun Channel 1 global interrupt */
+ LPDMA1_Channel2_IRQn = 116, /*!< LPDMA1 SmartRun Channel 2 global interrupt */
+ LPDMA1_Channel3_IRQn = 117, /*!< LPDMA1 SmartRun Channel 3 global interrupt */
+ DMA2D_IRQn = 118, /*!< DMA2D global interrupt */
+ DCMI_PSSI_IRQn = 119, /*!< DCMI/PSSI global interrupt */
+ OCTOSPI2_IRQn = 120, /*!< OCTOSPI2 global interrupt */
+ MDF1_FLT4_IRQn = 121, /*!< MDF1 Filter 4 global interrupt */
+ MDF1_FLT5_IRQn = 122, /*!< MDF1 Filter 5 global interrupt */
+ CORDIC_IRQn = 123, /*!< CORDIC global interrupt */
+ FMAC_IRQn = 124, /*!< FMAC global interrupt */
+} IRQn_Type;
+
+
+/* =========================================================================================================================== */
+/* ================ Processor and Core Peripheral Section ================ */
+/* =========================================================================================================================== */
+
+/* ------- Start of section using anonymous unions and disabling warnings ------- */
+#if defined (__CC_ARM)
+ #pragma push
+ #pragma anon_unions
+#elif defined (__ICCARM__)
+ #pragma language=extended
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wc11-extensions"
+ #pragma clang diagnostic ignored "-Wreserved-id-macro"
+#elif defined (__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+ #pragma warning 586
+#elif defined (__CSMC__)
+ /* anonymous unions are enabled by default */
+#else
+ #warning Not supported compiler type
+#endif
+
+/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */
+#define __CM33_REV 0x0000U /* Core revision r0p1 */
+#define __SAUREGION_PRESENT 1U /* SAU regions present */
+#define __MPU_PRESENT 1U /* MPU present */
+#define __VTOR_PRESENT 1U /* VTOR present */
+#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /* FPU present */
+#define __DSP_PRESENT 1U /* DSP extension present */
+
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include /*!< ARM Cortex-M33 processor and core peripherals */
+#include "system_stm32u5xx.h" /*!< STM32U5xx System */
+
+
+/* =========================================================================================================================== */
+/* ================ Device Specific Peripheral Section ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup STM32U5xx_peripherals
+ * @{
+ */
+
+/**
+ * @brief CRC calculation unit
+ */
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+ uint32_t RESERVED2; /*!< Reserved, 0x0C */
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+ uint32_t RESERVED3[246]; /*!< Reserved, */
+ __IO uint32_t HWCFGR; /*!< CRC IP HWCFGR register, Address offset: 0x3F0 */
+ __IO uint32_t VERR; /*!< CRC IP version register, Address offset: 0x3F4 */
+ __IO uint32_t PIDR; /*!< CRC IP type identification register, Address offset: 0x3F8 */
+ __IO uint32_t SIDR; /*!< CRC IP map Size ID register, Address offset: 0x3FC */
+} CRC_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
+ __IO uint32_t AUTOCR;
+} I2C_TypeDef;
+
+/**
+ * @brief DAC
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+ __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
+ __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
+ __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
+ __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
+ __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
+ __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
+ __IO uint32_t RESERVED[1];
+ __IO uint32_t AUTOCR; /*!< DAC Autonomous mode register, Address offset: 0x54 */
+} DAC_TypeDef;
+
+/**
+ * @brief Clock Recovery System
+ */
+typedef struct
+{
+__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
+__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
+__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
+__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
+} CRS_TypeDef;
+
+/**
+ * @brief HASH
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
+ __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
+ __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
+ __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
+ __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
+ __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
+ uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
+ __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
+} HASH_TypeDef;
+
+/**
+ * @brief HASH_DIGEST
+ */
+typedef struct
+{
+ __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
+} HASH_DIGEST_TypeDef;
+
+/**
+ * @brief RNG
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+ uint32_t RESERVED;
+ __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */
+} RNG_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
+ __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
+ __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
+ __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */
+ uint32_t RESERVED1[2];/*!< Reserved, 0x18 - 0x1C */
+ __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */
+ uint32_t RESERVED2; /*!< Reserved, 0x24 */
+ __IO uint32_t AHB3FZR; /*!< Debug MCU AHB3 freeze register, Address offset: 0x28 */
+} DBGMCU_TypeDef;
+
+/**
+ * @brief DCMI
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
+ __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
+ __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
+ __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
+ __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
+ __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+ __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
+ __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
+ __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+typedef struct
+{
+ __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */
+ __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */
+ __IO uint32_t RCFGLOCKR; /*!< DMA lock configuration register, Address offset: 0x08 */
+ __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */
+ __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */
+} DMA_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */
+ uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */
+ __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */
+ __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */
+ __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */
+ uint32_t RESERVED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */
+ __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */
+ __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */
+ __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */
+ __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */
+ __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */
+ __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */
+ __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */
+ uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */
+ __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */
+} DMA_Channel_TypeDef;
+
+/**
+ * @brief DMA2D Controller
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
+ __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
+ __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
+ __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
+ __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
+ __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
+ __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
+ __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
+ __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
+ __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
+ __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
+ __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
+ __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
+ __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
+ __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
+ __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
+ __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
+ __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
+ __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
+ __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
+ uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FC */
+ __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FC */
+ __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFC */
+} DMA2D_TypeDef;
+
+/**
+ * @brief Asynch Interrupt/Event Controller (EXTI)
+ */
+typedef struct
+{
+ __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */
+ __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */
+ __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */
+ __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */
+ __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */
+ __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */
+ __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */
+ uint32_t RESERVED1[17]; /*!< Reserved 1, 0x1C -- 0x5C */
+ __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */
+ __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */
+ uint32_t RESERVED2[3]; /*!< Reserved 2, 0x74 -- 0x7C */
+ __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */
+ __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */
+ __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x08 */
+ __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x0C */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x10 */
+ __IO uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x14 */
+ __IO uint32_t PDKEY1R; /*!< FLASH Bank 1 power-down key register, Address offset: 0x18 */
+ __IO uint32_t PDKEY2R; /*!< FLASH Bank 2 power-down key register, Address offset: 0x1C */
+ __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */
+ __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */
+ __IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offset: 0x28 */
+ __IO uint32_t SECCR; /*!< FLASH secure control register, Address offset: 0x2C */
+ __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x30 */
+ __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x34 */
+ uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x38-0x3C */
+ __IO uint32_t OPTR; /*!< FLASH option control register, Address offset: 0x40 */
+ __IO uint32_t NSBOOTADD0R; /*!< FLASH non-secure boot address 0 register, Address offset: 0x44 */
+ __IO uint32_t NSBOOTADD1R; /*!< FLASH non-secure boot address 1 register, Address offset: 0x48 */
+ __IO uint32_t SECBOOTADD0R; /*!< FLASH secure boot address 0 register, Address offset: 0x4C */
+ __IO uint32_t SECWM1R1; /*!< FLASH secure watermark1 register 1, Address offset: 0x50 */
+ __IO uint32_t SECWM1R2; /*!< FLASH secure watermark1 register 2, Address offset: 0x54 */
+ __IO uint32_t WRP1AR; /*!< FLASH WRP1 area A address register, Address offset: 0x58 */
+ __IO uint32_t WRP1BR; /*!< FLASH WRP1 area B address register, Address offset: 0x5C */
+ __IO uint32_t SECWM2R1; /*!< FLASH secure watermark2 register 1, Address offset: 0x60 */
+ __IO uint32_t SECWM2R2; /*!< FLASH secure watermark2 register 2, Address offset: 0x64 */
+ __IO uint32_t WRP2AR; /*!< FLASH WRP2 area A address register, Address offset: 0x68 */
+ __IO uint32_t WRP2BR; /*!< FLASH WRP2 area B address register, Address offset: 0x6C */
+ __IO uint32_t OEM1KEYR1; /*!< FLASH OEM1 key register 1, Address offset: 0x70 */
+ __IO uint32_t OEM1KEYR2; /*!< FLASH OEM1 key register 2, Address offset: 0x74 */
+ __IO uint32_t OEM2KEYR1; /*!< FLASH OEM2 key register 1, Address offset: 0x78 */
+ __IO uint32_t OEM2KEYR2; /*!< FLASH OEM2 key register 2, Address offset: 0x7C */
+ __IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offset: 0x80 */
+ __IO uint32_t SECBB1R2; /*!< FLASH secure block-based bank 1 register 2, Address offset: 0x84 */
+ __IO uint32_t SECBB1R3; /*!< FLASH secure block-based bank 1 register 3, Address offset: 0x88 */
+ __IO uint32_t SECBB1R4; /*!< FLASH secure block-based bank 1 register 4, Address offset: 0x8C */
+ uint32_t RESERVED4[4]; /*!< Reserved4, Address offset: 0x90-0x9C */
+ __IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offset: 0xA0 */
+ __IO uint32_t SECBB2R2; /*!< FLASH secure block-based bank 2 register 2, Address offset: 0xA4 */
+ __IO uint32_t SECBB2R3; /*!< FLASH secure block-based bank 2 register 3, Address offset: 0xA8 */
+ __IO uint32_t SECBB2R4; /*!< FLASH secure block-based bank 2 register 4, Address offset: 0xAC */
+ uint32_t RESERVED5[4]; /*!< Reserved5, Address offset: 0xB0-0xBC */
+ __IO uint32_t SECHDPCR; /*!< FLASH secure HDP control register, Address offset: 0xC0 */
+ __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0xC4 */
+ uint32_t RESERVED6[2]; /*!< Reserved6, Address offset: 0xC8-0xCC */
+ __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xD0 */
+ __IO uint32_t PRIVBB1R2; /*!< FLASH privilege block-based bank 1 register 2, Address offset: 0xD4 */
+ __IO uint32_t PRIVBB1R3; /*!< FLASH privilege block-based bank 1 register 3, Address offset: 0xD8 */
+ __IO uint32_t PRIVBB1R4; /*!< FLASH privilege block-based bank 1 register 4, Address offset: 0xDC */
+ uint32_t RESERVED7[4]; /*!< Reserved7, Address offset: 0xE0-0xEC */
+ __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0xF0 */
+ __IO uint32_t PRIVBB2R2; /*!< FLASH privilege block-based bank 2 register 2, Address offset: 0xF4 */
+ __IO uint32_t PRIVBB2R3; /*!< FLASH privilege block-based bank 2 register 3, Address offset: 0xF8 */
+ __IO uint32_t PRIVBB2R4; /*!< FLASH privilege block-based bank 2 register 4, Address offset: 0xFC */
+} FLASH_TypeDef;
+
+/**
+ * @brief FMAC
+ */
+typedef struct
+{
+ __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */
+ __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */
+ __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */
+ __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */
+ __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */
+ __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */
+ __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */
+} FMAC_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+ __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
+ __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */
+ __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */
+} GPIO_TypeDef;
+
+/**
+ * @brief Global TrustZone Controller
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */
+ uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */
+ __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */
+ __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */
+ __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */
+ uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */
+ __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */
+ __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */
+ __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */
+ uint32_t RESERVED3[5]; /*!< Reserved3, Address offset: 0x2C-0x3C */
+ __IO uint32_t MPCWM1ACFGR; /*!< TZSC memory 1 sub-region A watermark configuration register, Address offset: 0x40 */
+ __IO uint32_t MPCWM1AR; /*!< TZSC memory 1 sub-region A watermark register, Address offset: 0x44 */
+ __IO uint32_t MPCWM1BCFGR; /*!< TZSC memory 1 sub-region B watermark configuration register, Address offset: 0x48 */
+ __IO uint32_t MPCWM1BR; /*!< TZSC memory 1 sub-region B watermark register, Address offset: 0x4C */
+ __IO uint32_t MPCWM2ACFGR; /*!< TZSC memory 2 sub-region A watermark configuration register, Address offset: 0x50 */
+ __IO uint32_t MPCWM2AR; /*!< TZSC memory 2 sub-region A watermark register, Address offset: 0x54 */
+ __IO uint32_t MPCWM2BCFGR; /*!< TZSC memory 2 sub-region B watermark configuration register, Address offset: 0x58 */
+ __IO uint32_t MPCWM2BR; /*!< TZSC memory 2 sub-region B watermark register, Address offset: 0x5C */
+ __IO uint32_t MPCWM3ACFGR; /*!< TZSC memory 3 sub-region A watermark configuration register, Address offset: 0x60 */
+ __IO uint32_t MPCWM3AR; /*!< TZSC memory 3 sub-region A watermark register, Address offset: 0x64 */
+ uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x68-0x6C */
+ __IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, Address offset: 0x70 */
+ __IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, Address offset: 0x74 */
+ uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0x78-0x7C */
+ __IO uint32_t MPCWM5ACFGR; /*!< TZSC memory 5 sub-region A watermark configuration register, Address offset: 0x80 */
+ __IO uint32_t MPCWM5AR; /*!< TZSC memory 5 sub-region A watermark register, Address offset: 0x84 */
+ __IO uint32_t MPCWM5BCFGR; /*!< TZSC memory 5 sub-region B watermark configuration register, Address offset: 0x88 */
+ __IO uint32_t MPCWM5BR; /*!< TZSC memory 5 sub-region B watermark register, Address offset: 0x8C */
+} GTZC_TZSC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */
+ uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */
+ __IO uint32_t CFGLOCKR1; /*!< MPCBBx Configuration lock register, Address offset: 0x10 */
+ uint32_t RESERVED2[59]; /*!< Reserved2, Address offset: 0x14-0xFC */
+ __IO uint32_t SECCFGR[32]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x180 */
+ uint32_t RESERVED3[32]; /*!< Reserved3, Address offset: 0x180-0x200 */
+ __IO uint32_t PRIVCFGR[32]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x280 */
+} GTZC_MPCBB_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */
+ __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */
+ __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */
+ __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */
+ __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */
+ __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */
+ __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */
+ __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */
+ __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */
+ __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */
+ __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */
+ __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */
+} GTZC_TZIC_TypeDef;
+
+/**
+ * @brief Instruction Cache
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */
+ __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */
+ __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */
+ __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */
+ __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */
+ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */
+ __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */
+ __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */
+ __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */
+ __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */
+ uint32_t RESERVED2[240]; /*!< Reserved, Address offset: 0x30-0x3EC */
+ __IO uint32_t HWCFGR; /*!< ICACHE HW configuration register, Address offset: 0x3F0 */
+ __IO uint32_t VERR; /*!< ICACHE version register, Address offset: 0x3F4 */
+ __IO uint32_t IPIDR; /*!< ICACHE IP identification register, Address offset: 0x3F8 */
+ __IO uint32_t SIDR; /*!< ICACHE size identification register, Address offset: 0x3FC */
+} ICACHE_TypeDef;
+
+/**
+ * @brief Data Cache
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< DCACHE control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< DCACHE status register, Address offset: 0x04 */
+ __IO uint32_t IER; /*!< DCACHE interrupt enable register, Address offset: 0x08 */
+ __IO uint32_t FCR; /*!< DCACHE Flag clear register, Address offset: 0x0C */
+ __IO uint32_t RHMONR; /*!< DCACHE Read hit monitor register, Address offset: 0x10 */
+ __IO uint32_t RMMONR; /*!< DCACHE Read miss monitor register, Address offset: 0x14 */
+ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */
+ __IO uint32_t WHMONR; /*!< DCACHE Write hit monitor register, Address offset: 0x20 */
+ __IO uint32_t WMMONR; /*!< DCACHE Write miss monitor register, Address offset: 0x24 */
+ __IO uint32_t CMDRSADDRR; /*!< DCACHE Command Start Address register, Address offset: 0x28 */
+ __IO uint32_t CMDREADDRR; /*!< DCACHE Command End Address register, Address offset: 0x2C */
+} DCACHE_TypeDef;
+
+/**
+ * @brief PSSI
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */
+ __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */
+ __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */
+ __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */
+ __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */
+ __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */
+ __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */
+ __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */
+} PSSI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */
+ __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */
+ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */
+ __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */
+ __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */
+ __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */
+ __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */
+ __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */
+ __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */
+ uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */
+} TIM_TypeDef;
+
+/**
+ * @brief LPTIMER
+ */
+typedef struct
+{
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
+ __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
+ __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
+ __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */
+ __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */
+ __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */
+ __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */
+ __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */
+ __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */
+} LPTIM_TypeDef;
+
+/**
+ * @brief Comparator
+ */
+typedef struct
+{
+ __IO uint32_t CSR; /*!< Comparator control/status register , Address offset: 0x00 */
+} COMP_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */
+ __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */
+} COMP_Common_TypeDef;
+
+/**
+ * @brief Operational Amplifier (OPAMP)
+ */
+typedef struct
+{
+ __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
+ __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
+ __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
+} OPAMP_TypeDef;
+
+/*Aliases */
+#define OPAMP_Common_TypeDef OPAMP_TypeDef
+
+/**
+ * @brief MDF/ADF
+ */
+typedef struct
+{
+ __IO uint32_t GCR; /*!< MDF Global Control register, Address offset: 0x00 */
+ __IO uint32_t CKGCR; /*!< MDF Clock Generator Control Register, Address offset: 0x04 */
+ uint32_t RESERVED1[6]; /*!< Reserved, 0x08-0x1C */
+ __IO uint32_t OR; /*!< MDF Option Register, Address offset: 0x20 */
+}MDF_TypeDef;
+
+/**
+ * @brief MDF/ADF filter
+ */
+typedef struct
+{
+ __IO uint32_t SITFCR; /*!< MDF Serial Interface Control Register, Address offset: 0x80 */
+ __IO uint32_t BSMXCR; /*!< MDF Bitstream Matrix Control Register, Address offset: 0x84 */
+ __IO uint32_t DFLTCR; /*!< MDF Digital Filter Control Register, Address offset: 0x88 */
+ __IO uint32_t DFLTCICR; /*!< MDF MCIC Configuration Register, Address offset: 0x8C */
+ __IO uint32_t DFLTRSFR; /*!< MDF Reshape Filter Configuration Register, Address offset: 0x90 */
+ __IO uint32_t DFLTINTR; /*!< MDF Integrator Configuration Register, Address offset: 0x94 */
+ __IO uint32_t OLDCR; /*!< MDF Out-Of Limit Detector Control Register, Address offset: 0x98 */
+ __IO uint32_t OLDTHLR; /*!< MDF OLD Threshold Low Register, Address offset: 0x9C */
+ __IO uint32_t OLDTHHR; /*!< MDF OLD Threshold High Register, Address offset: 0xA0 */
+ __IO uint32_t DLYCR; /*!< MDF Delay control Register, Address offset: 0xA4 */
+ __IO uint32_t SCDCR; /*!< MDF short circuit detector control Register, Address offset: 0xA8 */
+ __IO uint32_t DFLTIER; /*!< MDF DFLT Interrupt enable Register, Address offset: 0xAC */
+ __IO uint32_t DFLTISR; /*!< MDF DFLT Interrupt status Register, Address offset: 0xB0 */
+ __IO uint32_t OECCR; /*!< MDF Offset Error Compensation Control Register, Address offset: 0xB4 */
+ __IO uint32_t SADCR; /*!< MDF SAD Control Register, Address offset: 0xB8 */
+ __IO uint32_t SADCFGR; /*!< MDF SAD configuration register, Address offset: 0xBC */
+ __IO uint32_t SADSDLVR; /*!< MDF SAD Sound level Register, Address offset: 0xC0 */
+ __IO uint32_t SADANLVR; /*!< MDF SAD Ambient Noise level Register, Address offset: 0xC4 */
+ uint32_t RESERVED1[9]; /*!< Reserved, 0xC8-0xE8 */
+ __IO uint32_t SNPSDR; /*!< MDF Snapshot Data Register, Address offset: 0xEC */
+ __IO uint32_t DFLTDR; /*!< MDF Digital Filter Data Register, Address offset: 0xF0 */
+} MDF_Filter_TypeDef;
+
+/**
+ * @brief OCTO Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< OCTOSPI Control register, Address offset: 0x000 */
+ uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */
+ __IO uint32_t DCR1; /*!< OCTOSPI Device Configuration register 1, Address offset: 0x008 */
+ __IO uint32_t DCR2; /*!< OCTOSPI Device Configuration register 2, Address offset: 0x00C */
+ __IO uint32_t DCR3; /*!< OCTOSPI Device Configuration register 3, Address offset: 0x010 */
+ __IO uint32_t DCR4; /*!< OCTOSPI Device Configuration register 4, Address offset: 0x014 */
+ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */
+ __IO uint32_t SR; /*!< OCTOSPI Status register, Address offset: 0x020 */
+ __IO uint32_t FCR; /*!< OCTOSPI Flag Clear register, Address offset: 0x024 */
+ uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */
+ __IO uint32_t DLR; /*!< OCTOSPI Data Length register, Address offset: 0x040 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */
+ __IO uint32_t AR; /*!< OCTOSPI Address register, Address offset: 0x048 */
+ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */
+ __IO uint32_t DR; /*!< OCTOPSI Data register, Address offset: 0x050 */
+ uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */
+ __IO uint32_t PSMKR; /*!< OCTOSPI Polling Status Mask register, Address offset: 0x080 */
+ uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */
+ __IO uint32_t PSMAR; /*!< OCTOSPI Polling Status Match register, Address offset: 0x088 */
+ uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */
+ __IO uint32_t PIR; /*!< OCTOSPI Polling Interval register, Address offset: 0x090 */
+ uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */
+ __IO uint32_t CCR; /*!< OCTOSPI Communication Configuration register, Address offset: 0x100 */
+ uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */
+ __IO uint32_t TCR; /*!< OCTOSPI Timing Configuration register, Address offset: 0x108 */
+ uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */
+ __IO uint32_t IR; /*!< OCTOSPI Instruction register, Address offset: 0x110 */
+ uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */
+ __IO uint32_t ABR; /*!< OCTOSPI Alternate Bytes register, Address offset: 0x120 */
+ uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */
+ __IO uint32_t LPTR; /*!< OCTOSPI Low Power Timeout register, Address offset: 0x130 */
+ uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */
+ __IO uint32_t WPCCR; /*!< OCTOSPI Wrap Communication Configuration register, Address offset: 0x140 */
+ uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */
+ __IO uint32_t WPTCR; /*!< OCTOSPI Wrap Timing Configuration register, Address offset: 0x148 */
+ uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */
+ __IO uint32_t WPIR; /*!< OCTOSPI Wrap Instruction register, Address offset: 0x150 */
+ uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */
+ __IO uint32_t WPABR; /*!< OCTOSPI Wrap Alternate Bytes register, Address offset: 0x160 */
+ uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */
+ __IO uint32_t WCCR; /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */
+ uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */
+ __IO uint32_t WTCR; /*!< OCTOSPI Write Timing Configuration register, Address offset: 0x188 */
+ uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */
+ __IO uint32_t WIR; /*!< OCTOSPI Write Instruction register, Address offset: 0x190 */
+ uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */
+ __IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */
+ uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */
+ __IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */
+} OCTOSPI_TypeDef;
+
+/**
+ * @brief OCTO Serial Peripheral Interface IO Manager
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< OCTOSPI IO Manager Control register, Address offset: 0x00 */
+ __IO uint32_t PCR[8]; /*!< OCTOSPI IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */
+} OCTOSPIM_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */
+ __IO uint32_t VOSR; /*!< PWR voltage scaling register, Address offset: 0x0C */
+ __IO uint32_t SVMCR; /*!< PWR supply voltage monitoring control register, Address offset: 0x10 */
+ __IO uint32_t WUCR1; /*!< PWR wakeup control register 1, Address offset: 0x14 */
+ __IO uint32_t WUCR2; /*!< PWR wakeup control register 2, Address offset: 0x18 */
+ __IO uint32_t WUCR3; /*!< PWR wakeup control register 3, Address offset: 0x1C */
+ __IO uint32_t BDCR1; /*!< PWR backup domain control register 1, Address offset: 0x20 */
+ __IO uint32_t BDCR2; /*!< PWR backup domain control register 2, Address offset: 0x24 */
+ __IO uint32_t DBPR; /*!< PWR disable backup domain register, Address offset: 0x28 */
+ __IO uint32_t UCPDR; /*!< PWR USB Type-C and Power Delivery register, Address offset: 0x2C */
+ __IO uint32_t SECCFGR; /*!< PWR Security configuration register, Address offset: 0x30 */
+ __IO uint32_t PRIVCFGR; /*!< PWR privilege control register, Address offset: 0x34 */
+ __IO uint32_t SR; /*!< PWR status register, Address offset: 0x38 */
+ __IO uint32_t SVMSR; /*!< PWR supply voltage monitoring status register, Address offset: 0x3C */
+ __IO uint32_t BDSR; /*!< PWR backup domain status register, Address offset: 0x40 */
+ __IO uint32_t WUSR; /*!< PWR wakeup status register, Address offset: 0x44 */
+ __IO uint32_t WUSCR; /*!< PWR wakeup status clear register, Address offset: 0x48 */
+ __IO uint32_t APCR; /*!< PWR apply pull configuration register, Address offset: 0x4C */
+ __IO uint32_t PUCRA; /*!< Power Port A pull-up control register, Address offset: 0x50 */
+ __IO uint32_t PDCRA; /*!< Power Port A pull-down control register, Address offset: 0x54 */
+ __IO uint32_t PUCRB; /*!< Power Port B pull-up control register, Address offset: 0x58 */
+ __IO uint32_t PDCRB; /*!< Power Port B pull-down control register, Address offset: 0x5C */
+ __IO uint32_t PUCRC; /*!< Power Port C pull-up control register, Address offset: 0x60 */
+ __IO uint32_t PDCRC; /*!< Power Port C pull-down control register, Address offset: 0x64 */
+ __IO uint32_t PUCRD; /*!< Power Port D pull-up control register, Address offset: 0x68 */
+ __IO uint32_t PDCRD; /*!< Power Port D pull-down control register, Address offset: 0x6C */
+ __IO uint32_t PUCRE; /*!< Power Port E pull-up control register, Address offset: 0x70 */
+ __IO uint32_t PDCRE; /*!< Power Port E pull-down control register, Address offset: 0x74 */
+ __IO uint32_t PUCRF; /*!< Power Port F pull-up control register, Address offset: 0x78 */
+ __IO uint32_t PDCRF; /*!< Power Port F pull-down control register, Address offset: 0x7C */
+ __IO uint32_t PUCRG; /*!< Power Port G pull-up control register, Address offset: 0x80 */
+ __IO uint32_t PDCRG; /*!< Power Port G pull-down control register, Address offset: 0x84 */
+ __IO uint32_t PUCRH; /*!< Power Port H pull-up control register, Address offset: 0x88 */
+ __IO uint32_t PDCRH; /*!< Power Port H pull-down control register, Address offset: 0x8C */
+ __IO uint32_t PUCRI; /*!< Power Port I pull-up control register, Address offset: 0x90 */
+ __IO uint32_t PDCRI; /*!< Power Port I pull-down control register, Address offset: 0x94 */
+} PWR_TypeDef;
+
+/**
+ * @brief SRAMs configuration controller
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */
+ __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */
+ __IO uint32_t SEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */
+ __IO uint32_t DEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */
+ __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */
+ __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */
+ __IO uint32_t WPR2; /*!< SRAM Write Protection Register 2, Address offset: 0x1C */
+ uint32_t RESERVED; /*!< Reserved, Address offset: 0x20 */
+ __IO uint32_t ECCKEY; /*!< SRAM ECC Key Register, Address offset: 0x24 */
+ __IO uint32_t ERKEYR; /*!< SRAM Erase Key Register, Address offset: 0x28 */
+}RAMCFG_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x00 */
+ uint32_t RESERVED0; /*!< Reserved Address offset: 0x04 */
+ __IO uint32_t ICSCR1; /*!< RCC internal clock sources calibration register 1 Address offset: 0x08 */
+ __IO uint32_t ICSCR2; /*!< RCC internal clock sources calibration register 2 Address offset: 0x0C */
+ __IO uint32_t ICSCR3; /*!< RCC internal clock sources calibration register 3 Address offset: 0x10 */
+ __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register Address offset: 0x14 */
+ uint32_t RESERVED1; /*!< Reserved Address offset: 0x18 */
+ __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x1C */
+ __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x20 */
+ __IO uint32_t CFGR3; /*!< RCC clock configuration register 3 Address offset: 0x24 */
+ __IO uint32_t PLL1CFGR; /*!< PLL1 Configuration Register Address offset: 0x28 */
+ __IO uint32_t PLL2CFGR; /*!< PLL2 Configuration Register Address offset: 0x2C */
+ __IO uint32_t PLL3CFGR; /*!< PLL3 Configuration Register Address offset: 0x30 */
+ __IO uint32_t PLL1DIVR; /*!< PLL1 Dividers Configuration Register Address offset: 0x34 */
+ __IO uint32_t PLL1FRACR; /*!< PLL1 Fractional Divider Configuration Register Address offset: 0x38 */
+ __IO uint32_t PLL2DIVR; /*!< PLL2 Dividers Configuration Register Address offset: 0x3C */
+ __IO uint32_t PLL2FRACR; /*!< PLL2 Fractional Divider Configuration Register Address offset: 0x40 */
+ __IO uint32_t PLL3DIVR; /*!< PLL3 Dividers Configuration Register Address offset: 0x44 */
+ __IO uint32_t PLL3FRACR; /*!< PLL3 Fractional Divider Configuration Register Address offset: 0x48 */
+ uint32_t RESERVED2; /*!< Reserved Address offset: 0x4C */
+ __IO uint32_t CIER; /*!< Clock Interrupt Enable Register Address offset: 0x50 */
+ __IO uint32_t CIFR; /*!< Clock Interrupt Flag Register Address offset: 0x54 */
+ __IO uint32_t CICR; /*!< Clock Interrupt Clear Register Address offset: 0x58 */
+ uint32_t RESERVED3; /*!< Reserved Address offset: 0x5C */
+ __IO uint32_t AHB1RSTR; /*!< AHB1 Peripherals Reset Register Address offset: 0x60 */
+ __IO uint32_t AHB2RSTR1; /*!< AHB2 Peripherals Reset Register 1 Address offset: 0x64 */
+ __IO uint32_t AHB2RSTR2; /*!< AHB2 Peripherals Reset Register 2 Address offset: 0x68 */
+ __IO uint32_t AHB3RSTR; /*!< AHB3 Peripherals Reset Register Address offset: 0x6C */
+ uint32_t RESERVED4; /*!< Reserved Address offset: 0x70 */
+ __IO uint32_t APB1RSTR1; /*!< APB1 Peripherals Reset Register 1 Address offset: 0x74 */
+ __IO uint32_t APB1RSTR2; /*!< APB1 Peripherals Reset Register 2 Address offset: 0x78 */
+ __IO uint32_t APB2RSTR; /*!< APB2 Peripherals Reset Register Address offset: 0x7C */
+ __IO uint32_t APB3RSTR; /*!< APB3 Peripherals Reset Register Address offset: 0x80 */
+ uint32_t RESERVED5; /*!< Reserved Address offset: 0x84 */
+ __IO uint32_t AHB1ENR; /*!< AHB1 Peripherals Clock Enable Register Address offset: 0x88 */
+ __IO uint32_t AHB2ENR1; /*!< AHB2 Peripherals Clock Enable Register 1 Address offset: 0x8C */
+ __IO uint32_t AHB2ENR2; /*!< AHB2 Peripherals Clock Enable Register 2 Address offset: 0x90 */
+ __IO uint32_t AHB3ENR; /*!< AHB3 Peripherals Clock Enable Register Address offset: 0x94 */
+ uint32_t RESERVED6; /*!< Reserved Address offset: 0x98 */
+ __IO uint32_t APB1ENR1; /*!< APB1 Peripherals Clock Enable Register 1 Address offset: 0x9C */
+ __IO uint32_t APB1ENR2; /*!< APB1 Peripherals Clock Enable Register 2 Address offset: 0xA0 */
+ __IO uint32_t APB2ENR; /*!< APB2 Peripherals Clock Enable Register Address offset: 0xA4 */
+ __IO uint32_t APB3ENR; /*!< APB3 Peripherals Clock Enable Register Address offset: 0xA8 */
+ uint32_t RESERVED7; /*!< Reserved Address offset: 0xAC */
+ __IO uint32_t AHB1SMENR; /*!< AHB1 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xB0 */
+ __IO uint32_t AHB2SMENR1; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xB4 */
+ __IO uint32_t AHB2SMENR2; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xB8 */
+ __IO uint32_t AHB3SMENR; /*!< AHB3 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xBC */
+ uint32_t RESERVED8; /*!< Reserved Address offset: 0xC0 */
+ __IO uint32_t APB1SMENR1; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xC4 */
+ __IO uint32_t APB1SMENR2; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xC8 */
+ __IO uint32_t APB2SMENR; /*!< APB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xCC */
+ __IO uint32_t APB3SMENR; /*!< APB3 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xD0 */
+ uint32_t RESERVED9; /*!< Reserved Address offset: 0xD4 */
+ __IO uint32_t SRDAMR; /*!< SRD Autonomous Mode Register Address offset: 0xD8 */
+ uint32_t RESERVED10; /*!< Reserved, Address offset: 0xDC */
+ __IO uint32_t CCIPR1; /*!< IPs Clocks Configuration Register 1 Address offset: 0xE0 */
+ __IO uint32_t CCIPR2; /*!< IPs Clocks Configuration Register 2 Address offset: 0xE4 */
+ __IO uint32_t CCIPR3; /*!< IPs Clocks Configuration Register 3 Address offset: 0xE8 */
+ uint32_t RESERVED11; /*!< Reserved, Address offset: 0xEC */
+ __IO uint32_t BDCR; /*!< Backup Domain Control Register Address offset: 0xF0 */
+ __IO uint32_t CSR; /*!< V33 Clock Control & Status Register Address offset: 0xF4 */
+ uint32_t RESERVED[6]; /*!< Reserved Address offset: 0xF8 */
+ __IO uint32_t SECCFGR; /*!< RCC secure configuration register Address offset: 0x110 */
+ __IO uint32_t PRIVCFGR; /*!< RCC privilege configuration register Address offset: 0x114 */
+} RCC_TypeDef;
+
+/*
+* @brief RTC Specific device feature definitions
+*/
+#define RTC_BKP_NB 32U
+#define RTC_TAMP_NB 8U
+
+/**
+ * @brief Real-Time Clock
+ */
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */
+ __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */
+ __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */
+ __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */
+ __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */
+ __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */
+ __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */
+ __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */
+ uint32_t RESERVED4[4];/*!< Reserved, Address offset: 0x58 */
+ __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */
+ __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */
+} RTC_TypeDef;
+
+/**
+ * @brief Tamper and backup registers
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */
+ __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */
+ __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */
+ __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */
+ __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */
+ __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */
+ __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */
+ __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */
+ uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */
+ __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */
+ __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */
+ __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */
+ __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register,Address offset: 0x38 */
+ __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */
+ __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */
+ uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x43 -- 0x50 */
+ __IO uint32_t ERCFGR; /*!< TAMP erase configuration register, Address offset: 0x54 */
+ uint32_t RESERVED2[42]; /*!< Reserved, Address offset: 0x58 -- 0xFC */
+ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */
+ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */
+ __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */
+ __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */
+ __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */
+ __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */
+ __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */
+ __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */
+ __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */
+ __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */
+ __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */
+ __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */
+ __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */
+ __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */
+ __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */
+ __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */
+ __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */
+ __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */
+ __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */
+ __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */
+ __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */
+ __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */
+ __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */
+ __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */
+ __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */
+ __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */
+ __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */
+ __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */
+ __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */
+ __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */
+ __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */
+ __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */
+} TAMP_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
+ __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
+ __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
+ __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */
+ __IO uint32_t AUTOCR; /*!< USART Autonomous mode control register Address offset: 0x30 */
+} USART_TypeDef;
+
+/**
+ * @brief Serial Audio Interface
+ */
+typedef struct
+{
+ __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
+ uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */
+ __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
+ __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
+} SAI_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
+ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
+ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
+ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
+ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+typedef struct
+{
+ __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
+ __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */
+ __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */
+ __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */
+ __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */
+ __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */
+ __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */
+ __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */
+ uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */
+ __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */
+ uint32_t RESERVED2[16];/*!< RESERVED2, Address offset: 0x30 - 0x6C */
+ __IO uint32_t UCPD; /*!< SYSCFG USB Type C and Power delivery register Address offset: 0x70 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Secure digital input/output Interface
+ */
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
+ __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
+ __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
+ __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
+ __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
+ __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
+ __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
+ __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
+ __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */
+ uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */
+ __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */
+ __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */
+ __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x60 */
+ __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */
+ __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */
+ uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */
+ __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
+} SDMMC_TypeDef;
+
+
+
+/**
+ * @brief Delay Block DLYB
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */
+ __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */
+} DLYB_TypeDef;
+
+/**
+ * @brief UCPD
+ */
+typedef struct
+{
+ __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */
+ __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */
+ uint32_t RESERVED0; /*!< Reserved Address offset: 0x08 */
+ __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */
+ __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */
+ __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */
+ __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */
+ __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */
+ __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */
+ __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */
+ __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */
+ __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */
+ __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */
+ __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */
+ __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */
+} UCPD_TypeDef;
+
+/**
+ * @brief USB_OTG_Core_register
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register, Address offset: 000h */
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register, Address offset: 004h */
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register, Address offset: 008h */
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register, Address offset: 00Ch */
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register, Address offset: 010h */
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register, Address offset: 014h */
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register, Address offset: 018h */
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register, Address offset: 01Ch */
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register, Address offset: 020h */
+ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register, Address offset: 024h */
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register, Address offset: 028h */
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg, Address offset: 02Ch */
+ __IO uint32_t Reserved30[2]; /*!< Reserved, Address offset: 030h */
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register, Address offset: 038h */
+ __IO uint32_t CID; /*!< User ID Register, Address offset: 03Ch */
+ __IO uint32_t GSNPSID; /*!< USB_OTG core ID, Address offset: 040h */
+ __IO uint32_t GHWCFG1; /*!< User HW config1, Address offset: 044h */
+ __IO uint32_t GHWCFG2; /*!< User HW config2, Address offset: 048h */
+ __IO uint32_t GHWCFG3; /*!< User HW config3, Address offset: 04Ch */
+ __IO uint32_t Reserved6; /*!< Reserved, Address offset: 050h */
+ __IO uint32_t GLPMCFG; /*!< LPM Register, Address offset: 054h */
+ __IO uint32_t GPWRDN; /*!< Power Down Register, Address offset: 058h */
+ __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register, Address offset: 05Ch */
+ __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register, Address offset: 60Ch */
+ __IO uint32_t Reserved43[39]; /*!< Reserved, Address offset: 058h */
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg, Address offset: 100h */
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 104h */
+} USB_OTG_GlobalTypeDef;
+
+/**
+ * @brief USB_OTG_device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /*!< dev Configuration Register, Address offset: 800h */
+ __IO uint32_t DCTL; /*!< dev Control Register, Address offset: 804h */
+ __IO uint32_t DSTS; /*!< dev Status Register (RO), Address offset: 808h */
+ uint32_t Reserved0C; /*!< Reserved, Address offset: 80Ch */
+ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask, Address offset: 810h */
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask, Address offset: 814h */
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg, Address offset: 818h */
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask, Address offset: 81Ch */
+ uint32_t Reserved20; /*!< Reserved, Address offset: 820h */
+ uint32_t Reserved9; /*!< Reserved, Address offset: 824h */
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register, Address offset: 828h */
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register, Address offset: 82Ch */
+ __IO uint32_t DTHRCTL; /*!< dev threshold, Address offset: 830h */
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk, Address offset: 834h */
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt, Address offset: 838h */
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk, Address offset: 83Ch */
+ uint32_t Reserved40; /*!< dedicated EP mask, Address offset: 840h */
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask, Address offset: 844h */
+ uint32_t Reserved44[15]; /*!< Reserved, Address offset: 844-87Ch */
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk, Address offset: 884h */
+} USB_OTG_DeviceTypeDef;
+
+
+/**
+ * @brief USB_OTG_IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Register, Address offset: 900h + (ep_num * 20h) + 00h */
+ __IO uint32_t Reserved04; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 04h */
+ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Register, Address offset: 900h + (ep_num * 20h) + 08h */
+ __IO uint32_t Reserved0C; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size Register, Address offset: 900h + (ep_num * 20h) + 10h */
+ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Register, Address offset: 900h + (ep_num * 20h) + 14h */
+ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Register, Address offset: 900h + (ep_num * 20h) + 18h */
+ __IO uint32_t Reserved18; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Register, Address offset: B00h + (ep_num * 20h) + 00h */
+ __IO uint32_t Reserved04; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 04h */
+ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Register, Address offset: B00h + (ep_num * 20h) + 08h */
+ __IO uint32_t Reserved0C; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size Register, Address offset: B00h + (ep_num * 20h) + 10h */
+ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address Register, Address offset: B00h + (ep_num * 20h) + 14h */
+ __IO uint32_t Reserved18[2]; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 18h */
+} USB_OTG_OUTEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /*!< Host Configuration Register, Address offset: 400h */
+ __IO uint32_t HFIR; /*!< Host Frame Interval Register, Address offset: 404h */
+ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining, Address offset: 408h */
+ uint32_t Reserved40C; /*!< Reserved, Address offset: 40Ch */
+ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status, Address offset: 410h */
+ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register, Address offset: 414h */
+ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask, Address offset: 418h */
+} USB_OTG_HostTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register, Address offset: 500h */
+ __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register, Address offset: 504h */
+ __IO uint32_t HCINT; /*!< Host Channel Interrupt Register, Address offset: 508h */
+ __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register, Address offset: 50Ch */
+ __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register, Address offset: 510h */
+ __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register, Address offset: 514h */
+ uint32_t Reserved[2]; /*!< Reserved, Address offset: 518h */
+} USB_OTG_HostChannelTypeDef;
+
+/**
+ * @brief FD Controller Area Network
+ */
+typedef struct
+{
+ __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */
+ __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */
+ uint32_t RESERVED1; /*!< Reserved, 0x008 */
+ __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */
+ __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */
+ __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */
+ __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */
+ __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */
+ __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */
+ __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */
+ __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */
+ __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */
+ uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */
+ __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */
+ __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */
+ __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */
+ uint32_t RESERVED3; /*!< Reserved, 0x04C */
+ __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */
+ __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */
+ __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */
+ __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */
+ uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */
+ __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */
+ __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */
+ __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */
+ uint32_t RESERVED5; /*!< Reserved, 0x08C */
+ __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */
+ __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */
+ __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */
+ __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */
+ uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */
+ __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */
+ __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */
+ __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */
+ __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */
+ __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */
+ __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */
+ __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */
+ __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */
+ __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */
+ __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */
+ __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */
+} FDCAN_GlobalTypeDef;
+
+/**
+ * @brief FD Controller Area Network Configuration
+ */
+typedef struct
+{
+ __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */
+ uint32_t RESERVED1[128];/*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */
+ __IO uint32_t OPTR; /*!< FDCAN option register, Address offset: 0x100 + 0x204 */
+ uint32_t RESERVED2[58];/*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */
+ __IO uint32_t HWCFG; /*!< FDCAN hardware configuration register, Address offset: 0x100 + 0x2F0 */
+ __IO uint32_t VERR; /*!< FDCAN IP version register, Address offset: 0x100 + 0x2F4 */
+ __IO uint32_t IPIDR; /*!< FDCAN IP ID register, Address offset: 0x100 + 0x2F8 */
+ __IO uint32_t SIDR; /*!< FDCAN size ID register, Address offset: 0x100 + 0x2FC */
+} FDCAN_Config_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller
+ */
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+ __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register, Address offset: 0x20 */
+} FMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank1E
+ */
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank3
+ */
+typedef struct
+{
+ __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
+ __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
+ __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
+ __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
+ uint32_t RESERVED0; /*!< Reserved, 0x90 */
+ __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
+} FMC_Bank3_TypeDef;
+
+/**
+ * @brief VREFBUF
+ */
+typedef struct
+{
+ __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
+ __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
+} VREFBUF_TypeDef;
+
+/**
+ * @brief ADC
+ */
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
+ __IO uint32_t CFGR1; /*!< ADC Configuration register, Address offset: 0x0C */
+ __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ /* Specific to ADC 14Bits*/
+ __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */
+ __IO uint32_t AWD1TR; /*!< ADC watchdog threshold register, Address offset: 0x20 */ /* Specific to ADC 12Bits*/
+ __IO uint32_t AWD2TR; /*!< ADC watchdog threshold register, Address offset: 0x24 */ /* Specific to ADC 12Bits*/
+ __IO uint32_t CHSELR; /*!< ADC channel select register, Address offset: 0x28 */ /* Specific to ADC 12Bits*/
+ __IO uint32_t AWD3TR; /*!< ADC watchdog threshold register, Address offset: 0x2C */ /* Specific to ADC 12Bits*/
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ /* Specific to ADC 14Bits*/
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ /* Specific to ADC 14Bits*/
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ /* Specific to ADC 14Bits*/
+ __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ /* Specific to ADC 14Bits*/
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
+ __IO uint32_t PW; /*!< ADC power register, Address offset: 0x44 */
+ uint32_t RESERVED1; /*!< Reserved, 0x048 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ /* Specific to ADC 14Bits*/
+ uint32_t RESERVED2[4]; /*!< Reserved, 0x050 - 0x05C */
+ __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ /* Specific to ADC 14Bits*/
+ __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ /* Specific to ADC 14Bits*/
+ __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ /* Specific to ADC 14Bits*/
+ __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ /* Specific to ADC 14Bits*/
+ __IO uint32_t GCOMP; /*!< ADC gain compensation register, Address offset: 0x70 */ /* Specific to ADC 14Bits*/
+ uint32_t RESERVED3[3]; /*!< Reserved, 0x074 - 0x07C */
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ /* Specific to ADC 14Bits*/
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ /* Specific to ADC 14Bits*/
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ /* Specific to ADC 14Bits*/
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ /* Specific to ADC 14Bits*/
+ uint32_t RESERVED4[4]; /*!< Reserved, 0x090 - 0x09C */
+ __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
+ __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
+ __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0xA8 */ /* Specific to ADC 14Bits*/
+ __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0xAC */ /* Specific to ADC 14Bits*/
+ __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ /* Specific to ADC 14Bits*/
+ __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ /* Specific to ADC 14Bits*/
+ __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ /* Specific to ADC 14Bits*/
+ __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ /* Specific to ADC 14Bits*/
+ __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ /* Specific to ADC 14Bits*/
+ __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */
+ __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ /* Specific to ADC 14Bits*/
+ uint32_t RESERVED5; /*!< Reserved, 0x0CC */
+ __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0xD0 */ /* Specific to ADC 12Bits*/
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: 0x308 */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief CORDIC
+ */
+typedef struct
+{
+ __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */
+ __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */
+ __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */
+} CORDIC_TypeDef;
+
+/**
+ * @brief IWDG
+ */
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
+ __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */
+} IWDG_TypeDef;
+
+/**
+ * @brief SPI
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
+ __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */
+ __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */
+ __IO uint32_t IER; /*!< SPI Interrupt Enable register, Address offset: 0x10 */
+ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x14 */
+ __IO uint32_t IFCR; /*!< SPI Interrupt/Status Flags Clear register, Address offset: 0x18 */
+ __IO uint32_t AUTOCR; /*!< SPI Autonomous Mode Control register, Address offset: 0x1C */
+ __IO uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */
+ uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */
+ __IO uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */
+ uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */
+ __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */
+ __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */
+ __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */
+ __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */
+} SPI_TypeDef;
+
+/**
+ * @brief Touch Sensing Controller (TSC)
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
+ __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
+ __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
+ __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
+ __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
+ __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
+ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
+ __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
+ __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
+} TSC_TypeDef;
+
+/**
+ * @brief WWDG
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/*@}*/ /* end of group STM32U5xx_peripherals */
+
+
+/* -------- End of section using anonymous unions and disabling warnings -------- */
+#if defined (__CC_ARM)
+ #pragma pop
+#elif defined (__ICCARM__)
+ /* leave anonymous unions enabled */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+#elif defined (__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+ #pragma warning restore
+#elif defined (__CSMC__)
+ /* anonymous unions are enabled by default */
+#else
+ #warning Not supported compiler type
+#endif
+
+
+/* =========================================================================================================================== */
+/* ================ Device Specific Peripheral Address Map ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup STM32U5xx_Peripheral_peripheralAddr
+ * @{
+ */
+
+/* Internal SRAMs size */
+#define SRAM1_SIZE (0x30000UL) /*!< SRAM1=192k */
+#define SRAM2_SIZE (0x10000UL) /*!< SRAM2=64k */
+#define SRAM3_SIZE (0x80000UL) /*!< SRAM3=512k */
+#define SRAM4_SIZE (0x04000UL) /*!< SRAM4=16k */
+
+/* External memories base addresses - Not aliased */
+#define FMC_BASE (0x60000000UL) /*!< FMC base address */
+#define OCTOSPI2_BASE (0x70000000UL) /*!< OCTOSPI2 memories accessible over AHB base address */
+#define OCTOSPI1_BASE (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */
+
+#define FMC_BANK1 FMC_BASE
+#define FMC_BANK1_1 FMC_BANK1
+#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL)
+#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL)
+#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL)
+#define FMC_BANK3 (FMC_BASE + 0x20000000UL)
+
+/* Flash, Peripheral and internal SRAMs base addresses - Non secure */
+#define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (up to 2 MB) non-secure base address */
+#define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (192 KB) non-secure base address */
+#define SRAM2_BASE_NS (0x20030000UL) /*!< SRAM2 (64 KB) non-secure base address */
+#define SRAM3_BASE_NS (0x20040000UL) /*!< SRAM3 (512 KB) non-secure base address */
+#define SRAM4_BASE_NS (0x28000000UL) /*!< SRAM4 (16 KB) non-secure base address */
+#define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address */
+
+/* Peripheral memory map - Non secure */
+#define APB1PERIPH_BASE_NS PERIPH_BASE_NS
+#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL)
+#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL)
+#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL)
+#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL)
+#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06020000UL)
+
+/*!< APB1 Non secure peripherals */
+#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL)
+#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL)
+#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL)
+#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL)
+#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL)
+#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL)
+#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL)
+#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL)
+#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL)
+#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL)
+#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL)
+#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL)
+#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL)
+#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL)
+#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL)
+#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL)
+#define I2C4_BASE_NS (APB1PERIPH_BASE_NS + 0x8400UL)
+#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL)
+#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL)
+#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA500UL)
+#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xAC00UL)
+#define UCPD1_BASE_NS (APB1PERIPH_BASE_NS + 0xDC00UL)
+
+/*!< APB2 Non secure peripherals */
+#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL)
+#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL)
+#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL)
+#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL)
+#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL)
+#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL)
+#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL)
+#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5400UL)
+#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x004UL)
+#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x024UL)
+#define SAI2_BASE_NS (APB2PERIPH_BASE_NS + 0x5800UL)
+#define SAI2_Block_A_BASE_NS (SAI2_BASE_NS + 0x004UL)
+#define SAI2_Block_B_BASE_NS (SAI2_BASE_NS + 0x024UL)
+
+/*!< APB3 Non secure peripherals */
+#define SYSCFG_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL)
+#define SPI3_BASE_NS (APB3PERIPH_BASE_NS + 0x2000UL)
+#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x2400UL)
+#define I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x2800UL)
+#define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x4400UL)
+#define LPTIM3_BASE_NS (APB3PERIPH_BASE_NS + 0x4800UL)
+#define LPTIM4_BASE_NS (APB3PERIPH_BASE_NS + 0x4C00UL)
+#define OPAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL)
+#define OPAMP1_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL)
+#define OPAMP2_BASE_NS (APB3PERIPH_BASE_NS + 0x5010UL)
+#define COMP12_BASE_NS (APB3PERIPH_BASE_NS + 0x5400UL)
+#define COMP1_BASE_NS (COMP12_BASE_NS)
+#define COMP2_BASE_NS (COMP12_BASE_NS + 0x04UL)
+#define VREFBUF_BASE_NS (APB3PERIPH_BASE_NS + 0x7400UL)
+#define RTC_BASE_NS (APB3PERIPH_BASE_NS + 0x7800UL)
+#define TAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x7C00UL)
+
+/*!< AHB1 Non secure peripherals */
+#define GPDMA1_BASE_NS (AHB1PERIPH_BASE_NS)
+#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL)
+#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL)
+#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL)
+#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL)
+#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL)
+#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL)
+#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL)
+#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL)
+#define GPDMA1_Channel8_BASE_NS (GPDMA1_BASE_NS + 0x0450UL)
+#define GPDMA1_Channel9_BASE_NS (GPDMA1_BASE_NS + 0x04D0UL)
+#define GPDMA1_Channel10_BASE_NS (GPDMA1_BASE_NS + 0x0550UL)
+#define GPDMA1_Channel11_BASE_NS (GPDMA1_BASE_NS + 0x05D0UL)
+#define GPDMA1_Channel12_BASE_NS (GPDMA1_BASE_NS + 0x0650UL)
+#define GPDMA1_Channel13_BASE_NS (GPDMA1_BASE_NS + 0x06D0UL)
+#define GPDMA1_Channel14_BASE_NS (GPDMA1_BASE_NS + 0x0750UL)
+#define GPDMA1_Channel15_BASE_NS (GPDMA1_BASE_NS + 0x07D0UL)
+#define CORDIC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01000UL)
+#define FMAC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01400UL)
+#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL)
+#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL)
+#define TSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x04000UL)
+#define MDF1_BASE_NS (AHB1PERIPH_BASE_NS + 0x05000UL)
+#define MDF1_Filter0_BASE_NS (MDF1_BASE_NS + 0x80UL)
+#define MDF1_Filter1_BASE_NS (MDF1_BASE_NS + 0x100UL)
+#define MDF1_Filter2_BASE_NS (MDF1_BASE_NS + 0x180UL)
+#define MDF1_Filter3_BASE_NS (MDF1_BASE_NS + 0x200UL)
+#define MDF1_Filter4_BASE_NS (MDF1_BASE_NS + 0x280UL)
+#define MDF1_Filter5_BASE_NS (MDF1_BASE_NS + 0x300UL)
+#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL)
+#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS)
+#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL)
+#define RAMCFG_SRAM3_BASE_NS (RAMCFG_BASE_NS + 0x0080UL)
+#define RAMCFG_SRAM4_BASE_NS (RAMCFG_BASE_NS + 0x00C0UL)
+#define RAMCFG_BKPRAM_BASE_NS (RAMCFG_BASE_NS + 0x0100UL)
+#define DMA2D_BASE_NS (AHB1PERIPH_BASE_NS + 0x0B000UL)
+#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL)
+#define DCACHE1_BASE_NS (AHB1PERIPH_BASE_NS + 0x11400UL)
+#define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL)
+#define GTZC_TZIC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12800UL)
+#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL)
+#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL)
+#define GTZC_MPCBB3_BASE_NS (AHB1PERIPH_BASE_NS + 0x13400UL)
+#define BKPSRAM_BASE_NS (AHB1PERIPH_BASE_NS + 0x16400UL)
+
+/*!< AHB2 Non secure peripherals */
+#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000UL)
+#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL)
+#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL)
+#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00C00UL)
+#define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x01000UL)
+#define GPIOF_BASE_NS (AHB2PERIPH_BASE_NS + 0x01400UL)
+#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x01800UL)
+#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL)
+#define GPIOI_BASE_NS (AHB2PERIPH_BASE_NS + 0x02000UL)
+#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08000UL)
+#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08308UL)
+#define DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL)
+#define PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL)
+#define USB_OTG_FS_BASE_NS (AHB2PERIPH_BASE_NS + 0x20000UL)
+#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL)
+#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL)
+#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL)
+#define OCTOSPIM_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xA4000UL) /*!< OCTOSPIO Manager control registers base address */
+#define SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8000UL)
+#define SDMMC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8C00UL)
+#define DLYB_SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8400UL)
+#define DLYB_SDMMC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8800UL)
+#define DLYB_OCTOSPI1_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF000UL)
+#define DLYB_OCTOSPI2_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF400UL)
+#define FMC_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB0400UL) /*!< FMC control registers base address */
+#define FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL)
+#define FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL)
+#define FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL)
+#define OCTOSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB1400UL) /*!< OCTOSPI1 control registers base address */
+#define OCTOSPI2_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB2400UL) /*!< OCTOSPI2 control registers base address */
+
+/*!< AHB3 Non secure peripherals */
+#define LPGPIO1_BASE_NS (AHB3PERIPH_BASE_NS)
+#define PWR_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL)
+#define RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL)
+#define ADC4_BASE_NS (AHB3PERIPH_BASE_NS + 0x1000UL)
+#define ADC4_COMMON_BASE_NS (AHB3PERIPH_BASE_NS + 0x1308UL)
+#define DAC1_BASE_NS (AHB3PERIPH_BASE_NS + 0x1800UL)
+#define EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL)
+#define GTZC_TZSC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3000UL)
+#define GTZC_TZIC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3400UL)
+#define GTZC_MPCBB4_BASE_NS (AHB3PERIPH_BASE_NS + 0x3800UL)
+#define ADF1_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL)
+#define ADF1_Filter0_BASE_NS (ADF1_BASE_NS + 0x80UL)
+#define LPDMA1_BASE_NS (AHB3PERIPH_BASE_NS + 0x5000UL)
+#define LPDMA1_Channel0_BASE_NS (LPDMA1_BASE_NS + 0x0050UL)
+#define LPDMA1_Channel1_BASE_NS (LPDMA1_BASE_NS + 0x00D0UL)
+#define LPDMA1_Channel2_BASE_NS (LPDMA1_BASE_NS + 0x0150UL)
+#define LPDMA1_Channel3_BASE_NS (LPDMA1_BASE_NS + 0x01D0UL)
+
+/* Flash, Peripheral and internal SRAMs base addresses - Secure */
+#define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (up to 2 MB) secure base address */
+#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (192 KB) secure base address */
+#define SRAM2_BASE_S (0x30030000UL) /*!< SRAM2 (64 KB) secure base address */
+#define SRAM3_BASE_S (0x30040000UL) /*!< SRAM3 (512 KB) secure base address */
+#define SRAM4_BASE_S (0x38000000UL) /*!< SRAM4 (16 KB) secure base address */
+#define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */
+
+/* Peripheral memory map - Secure */
+#define APB1PERIPH_BASE_S PERIPH_BASE_S
+#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL)
+#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL)
+#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL)
+#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL)
+#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06020000UL)
+
+/*!< APB1 Secure peripherals */
+#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL)
+#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL)
+#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL)
+#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL)
+#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL)
+#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL)
+#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL)
+#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL)
+#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL)
+#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL)
+#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL)
+#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL)
+#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL)
+#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL)
+#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL)
+#define I2C4_BASE_S (APB1PERIPH_BASE_S + 0x8400UL)
+#define CRS_BASE_S (APB1PERIPH_BASE_S + 0x6000UL)
+#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL)
+#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA400UL)
+#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA500UL)
+#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xAC00UL)
+#define UCPD1_BASE_S (APB1PERIPH_BASE_S + 0xDC00UL)
+
+/*!< APB2 Secure peripherals */
+#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL)
+#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL)
+#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x3400UL)
+#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL)
+#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL)
+#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL)
+#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL)
+#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5400UL)
+#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x004UL)
+#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x024UL)
+#define SAI2_BASE_S (APB2PERIPH_BASE_S + 0x5800UL)
+#define SAI2_Block_A_BASE_S (SAI2_BASE_S + 0x004UL)
+#define SAI2_Block_B_BASE_S (SAI2_BASE_S + 0x024UL)
+
+/*!< APB3 Secure peripherals */
+#define SYSCFG_BASE_S (APB3PERIPH_BASE_S + 0x0400UL)
+#define ADC4_BASE_S (AHB3PERIPH_BASE_S + 0x1000UL)
+#define ADC4_COMMON_BASE_S (AHB3PERIPH_BASE_S + 0x1308UL)
+#define SPI3_BASE_S (APB3PERIPH_BASE_S + 0x2000UL)
+#define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x2400UL)
+#define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x2800UL)
+#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4300UL)
+#define LPTIM3_BASE_S (APB3PERIPH_BASE_S + 0x4800UL)
+#define LPTIM4_BASE_S (APB3PERIPH_BASE_S + 0x4C00UL)
+#define OPAMP_BASE_S (APB3PERIPH_BASE_S + 0x5000UL)
+#define OPAMP1_BASE_S (APB3PERIPH_BASE_S + 0x5000UL)
+#define OPAMP2_BASE_S (APB3PERIPH_BASE_S + 0x5010UL)
+#define COMP12_BASE_S (APB3PERIPH_BASE_S + 0x5400UL)
+#define COMP1_BASE_S (COMP12_BASE_S)
+#define COMP2_BASE_S (COMP12_BASE_S + 0x04UL)
+#define VREFBUF_BASE_S (APB3PERIPH_BASE_S + 0x7400UL)
+#define RTC_BASE_S (APB3PERIPH_BASE_S + 0x7800UL)
+#define TAMP_BASE_S (APB3PERIPH_BASE_S + 0x7C00UL)
+
+/*!< AHB1 Secure peripherals */
+#define GPDMA1_BASE_S (AHB1PERIPH_BASE_S)
+#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL)
+#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL)
+#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL)
+#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL)
+#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL)
+#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL)
+#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL)
+#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL)
+#define GPDMA1_Channel8_BASE_S (GPDMA1_BASE_S + 0x0450UL)
+#define GPDMA1_Channel9_BASE_S (GPDMA1_BASE_S + 0x04D0UL)
+#define GPDMA1_Channel10_BASE_S (GPDMA1_BASE_S + 0x0550UL)
+#define GPDMA1_Channel11_BASE_S (GPDMA1_BASE_S + 0x05D0UL)
+#define GPDMA1_Channel12_BASE_S (GPDMA1_BASE_S + 0x0650UL)
+#define GPDMA1_Channel13_BASE_S (GPDMA1_BASE_S + 0x06D0UL)
+#define GPDMA1_Channel14_BASE_S (GPDMA1_BASE_S + 0x0750UL)
+#define GPDMA1_Channel15_BASE_S (GPDMA1_BASE_S + 0x07D0UL)
+#define CORDIC_BASE_S (AHB1PERIPH_BASE_S + 0x01000UL)
+#define FMAC_BASE_S (AHB1PERIPH_BASE_S + 0x01400UL)
+#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL)
+#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL)
+#define TSC_BASE_S (AHB1PERIPH_BASE_S + 0x04000UL)
+#define MDF1_BASE_S (AHB1PERIPH_BASE_S + 0x05000UL)
+#define MDF1_Filter0_BASE_S (MDF1_BASE_S + 0x80UL)
+#define MDF1_Filter1_BASE_S (MDF1_BASE_S + 0x100UL)
+#define MDF1_Filter2_BASE_S (MDF1_BASE_S + 0x180UL)
+#define MDF1_Filter3_BASE_S (MDF1_BASE_S + 0x200UL)
+#define MDF1_Filter4_BASE_S (MDF1_BASE_S + 0x280UL)
+#define MDF1_Filter5_BASE_S (MDF1_BASE_S + 0x300UL)
+#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL)
+#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S)
+#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL)
+#define RAMCFG_SRAM3_BASE_S (RAMCFG_BASE_S + 0x0080UL)
+#define RAMCFG_SRAM4_BASE_S (RAMCFG_BASE_S + 0x00C0UL)
+#define RAMCFG_BKPRAM_BASE_S (RAMCFG_BASE_S + 0x0100UL)
+#define DMA2D_BASE_S (AHB1PERIPH_BASE_S + 0x0B000UL)
+#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL)
+#define DCACHE1_BASE_S (AHB1PERIPH_BASE_S + 0x11400UL)
+#define GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL)
+#define GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL)
+#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL)
+#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL)
+#define GTZC_MPCBB3_BASE_S (AHB1PERIPH_BASE_S + 0x13400UL)
+#define BKPSRAM_BASE_S (AHB1PERIPH_BASE_S + 0x16400UL)
+
+/*!< AHB2 Secure peripherals */
+#define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000UL)
+#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL)
+#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL)
+#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00C00UL)
+#define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x01000UL)
+#define GPIOF_BASE_S (AHB2PERIPH_BASE_S + 0x01400UL)
+#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x01800UL)
+#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL)
+#define GPIOI_BASE_S (AHB2PERIPH_BASE_S + 0x02000UL)
+#define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x08000UL)
+#define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x08308UL)
+#define DCMI_BASE_S (AHB2PERIPH_BASE_S + 0x0C000UL)
+#define PSSI_BASE_S (AHB2PERIPH_BASE_S + 0x0C400UL)
+#define USB_OTG_FS_BASE_S (AHB2PERIPH_BASE_S + 0x20000UL)
+#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL)
+#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL)
+#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL)
+#define OCTOSPIM_R_BASE_S (AHB2PERIPH_BASE_S + 0xA4000UL) /*!< OCTOSPIM control registers base address */
+#define SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8000UL)
+#define SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8C00UL)
+#define DLYB_SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8400UL)
+#define DLYB_SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8800UL)
+#define DLYB_OCTOSPI1_BASE_S (AHB2PERIPH_BASE_S + 0xAF000UL)
+#define DLYB_OCTOSPI2_BASE_S (AHB2PERIPH_BASE_S + 0xAF400UL)
+#define FMC_R_BASE_S (AHB2PERIPH_BASE_S + 0xB0400UL) /*!< FMC control registers base address */
+#define FMC_Bank1_R_BASE_S (FMC_R_BASE_S + 0x0000UL)
+#define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL)
+#define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL)
+#define OCTOSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0xB1400UL) /*!< OCTOSPI1 control registers base address */
+#define OCTOSPI2_R_BASE_S (AHB2PERIPH_BASE_S + 0xB2400UL) /*!< OCTOSPI2 control registers base address */
+
+/*!< AHB3 Secure peripherals */
+#define LPGPIO1_BASE_S (AHB3PERIPH_BASE_S)
+#define PWR_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL)
+#define RCC_BASE_S (AHB3PERIPH_BASE_S + 0x0C00UL)
+#define DAC1_BASE_S (AHB3PERIPH_BASE_S + 0x1800UL)
+#define EXTI_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL)
+#define GTZC_TZSC2_BASE_S (AHB3PERIPH_BASE_S + 0x3000UL)
+#define GTZC_TZIC2_BASE_S (AHB3PERIPH_BASE_S + 0x3400UL)
+#define GTZC_MPCBB4_BASE_S (AHB3PERIPH_BASE_S + 0x3800UL)
+#define ADF1_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL)
+#define ADF1_Filter0_BASE_S (ADF1_BASE_S + 0x80UL)
+#define LPDMA1_BASE_S (AHB3PERIPH_BASE_S + 0x5000UL)
+#define LPDMA1_Channel0_BASE_S (LPDMA1_BASE_S + 0x0050UL)
+#define LPDMA1_Channel1_BASE_S (LPDMA1_BASE_S + 0x00D0UL)
+#define LPDMA1_Channel2_BASE_S (LPDMA1_BASE_S + 0x0150UL)
+#define LPDMA1_Channel3_BASE_S (LPDMA1_BASE_S + 0x01D0UL)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE (0xE0044000UL)
+
+#define PACKAGE_BASE (0x0BFA0500UL) /*!< Package data register base address */
+#define UID_BASE (0x0BFA0700UL) /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE (0x0BFA07A0UL) /*!< Flash size data register base address */
+
+/* Internal Flash OTP Area */
+#define FLASH_OTP_BASE (0x0BFA0000UL) /*!< FLASH OTP (one-time programmable) base address */
+#define FLASH_OTP_SIZE (0x200U) /*!< 512 bytes OTP (one-time programmable) */
+
+/* USB OTG FS registers Base address */
+#define USB_OTG_GLOBAL_BASE (0x0000UL)
+#define USB_OTG_DEVICE_BASE (0x0800UL)
+#define USB_OTG_IN_ENDPOINT_BASE (0x0900UL)
+#define USB_OTG_OUT_ENDPOINT_BASE (0x0B00UL)
+#define USB_OTG_EP_REG_SIZE (0x0020UL)
+#define USB_OTG_HOST_BASE (0x0400UL)
+#define USB_OTG_HOST_PORT_BASE (0x0440UL)
+#define USB_OTG_HOST_CHANNEL_BASE (0x0500UL)
+#define USB_OTG_HOST_CHANNEL_SIZE (0x0020UL)
+#define USB_OTG_PCGCCTL_BASE (0x0E00UL)
+#define USB_OTG_FIFO_BASE (0x1000UL)
+#define USB_OTG_FIFO_SIZE (0x1000UL)
+
+/*!< Root Secure Service Library */
+/************ RSSLIB SAU system Flash region definition constants *************/
+#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0x0BF99E40UL)
+#define RSSLIB_SYS_FLASH_NS_PFUNC_END (0x0BF99EFFUL)
+
+/************ RSSLIB function return constants ********************************/
+#define RSSLIB_ERROR (0xF5F5F5F5UL)
+#define RSSLIB_SUCCESS (0xEAEAEAEAUL)
+
+/*!< RSSLIB pointer function structure address definition */
+#define RSSLIB_PFUNC_BASE RSSLIB_SYS_FLASH_NS_PFUNC_START
+#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE)
+
+/*!< HDP Area constant definition */
+#define RSSLIB_HDP_AREA_Pos (0U)
+#define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos )
+#define RSSLIB_HDP_AREA1_Pos (0U)
+#define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos )
+#define RSSLIB_HDP_AREA2_Pos (1U)
+#define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos )
+
+/**
+ * @brief Prototype of RSSLIB Close and exit HDP Function
+ * @detail This function close the requested hdp area passed in input
+ * parameter and jump to the reset handler present within the
+ * Vector table. The function does not return on successful execution.
+ * @param HdpArea notifies which hdp area to close, can be a combination of
+ * hdpa area 1 and hdp area 2
+ * @param pointer on the vector table containing the reset handler the function
+ * jumps to.
+ * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return.
+ */
+typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr );
+
+
+/**
+ * @brief RSSLib non-secure callable function pointer structure
+ */
+typedef struct
+{
+ __IM uint32_t Reserved[8];
+}NSC_pFuncTypeDef;
+
+/**
+ * @brief RSSLib secure callable function pointer structure
+ */
+typedef struct
+{
+ __IM uint32_t Reserved2[2];
+ __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP; /*!< RSSLIB Bootloader Close and exit HDP Address offset: 0x28 */
+}S_pFuncTypeDef;
+
+/**
+ * @brief RSSLib function pointer structure
+ */
+typedef struct
+{
+ NSC_pFuncTypeDef NSC;
+ S_pFuncTypeDef S;
+}RSSLIB_pFunc_TypeDef;
+
+/** @} */ /* End of group STM32U5xx_Peripheral_peripheralAddr */
+
+
+/* =========================================================================================================================== */
+/* ================ Peripheral declaration ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup STM32U5xx_Peripheral_declaration
+ * @{
+ */
+
+/*!< APB1 Non secure peripherals */
+#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS)
+#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS)
+#define TIM4_NS ((TIM_TypeDef *) TIM4_BASE_NS)
+#define TIM5_NS ((TIM_TypeDef *) TIM5_BASE_NS)
+#define TIM6_NS ((TIM_TypeDef *) TIM6_BASE_NS)
+#define TIM7_NS ((TIM_TypeDef *) TIM7_BASE_NS)
+#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS)
+#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS)
+#define SPI2_NS ((SPI_TypeDef *) SPI2_BASE_NS)
+#define USART2_NS ((USART_TypeDef *) USART2_BASE_NS)
+#define USART3_NS ((USART_TypeDef *) USART3_BASE_NS)
+#define UART4_NS ((USART_TypeDef *) UART4_BASE_NS)
+#define UART5_NS ((USART_TypeDef *) UART5_BASE_NS)
+#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS)
+#define I2C2_NS ((I2C_TypeDef *) I2C2_BASE_NS)
+#define CRS_NS ((CRS_TypeDef *) CRS_BASE_NS)
+#define I2C4_NS ((I2C_TypeDef *) I2C4_BASE_NS)
+#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS)
+#define FDCAN1_NS ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS)
+#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS)
+#define UCPD1_NS ((UCPD_TypeDef *) UCPD1_BASE_NS)
+
+/*!< APB2 Non secure peripherals */
+#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS)
+#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS)
+#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS)
+#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS)
+#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS)
+#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS)
+#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS)
+#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS)
+#define SAI1_Block_A_NS ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS)
+#define SAI1_Block_B_NS ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS)
+#define SAI2_NS ((SAI_TypeDef *) SAI2_BASE_NS)
+#define SAI2_Block_A_NS ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_NS)
+#define SAI2_Block_B_NS ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_NS)
+
+/*!< APB3 Non secure peripherals */
+#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS)
+#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS)
+#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS)
+#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS)
+#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS)
+#define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS)
+#define LPTIM4_NS ((LPTIM_TypeDef *) LPTIM4_BASE_NS)
+#define OPAMP_NS ((OPAMP_TypeDef *) OPAMP_BASE_NS)
+#define OPAMP1_NS ((OPAMP_TypeDef *) OPAMP1_BASE_NS)
+#define OPAMP2_NS ((OPAMP_TypeDef *) OPAMP2_BASE_NS)
+#define COMP12_NS ((COMP_TypeDef *) COMP12_BASE_NS)
+#define COMP1_NS ((COMP_TypeDef *) COMP1_BASE_NS)
+#define COMP2_NS ((COMP_TypeDef *) COMP2_BASE_NS)
+#define COMP12_COMMON_NS ((COMP_Common_TypeDef *) COMP1_BASE_NS)
+#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS)
+#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS)
+#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS)
+
+/*!< AHB1 Non secure peripherals */
+#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS)
+#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS)
+#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS)
+#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS)
+#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS)
+#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS)
+#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS)
+#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS)
+#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS)
+#define GPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS)
+#define GPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS)
+#define GPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS)
+#define GPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS)
+#define GPDMA1_Channel12_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_NS)
+#define GPDMA1_Channel13_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_NS)
+#define GPDMA1_Channel14_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_NS)
+#define GPDMA1_Channel15_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_NS)
+#define CORDIC_NS ((CORDIC_TypeDef *) CORDIC_BASE_NS)
+#define FMAC_NS ((FMAC_TypeDef *) FMAC_BASE_NS)
+#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS)
+#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS)
+#define TSC_NS ((TSC_TypeDef *) TSC_BASE_NS)
+#define MDF1_NS ((MDF_TypeDef *) MDF1_BASE_NS)
+#define MDF1_Filter0_NS ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_NS)
+#define MDF1_Filter1_NS ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_NS)
+#define MDF1_Filter2_NS ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_NS)
+#define MDF1_Filter3_NS ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_NS)
+#define MDF1_Filter4_NS ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_NS)
+#define MDF1_Filter5_NS ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_NS)
+#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS)
+#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS)
+#define RAMCFG_SRAM3_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_NS)
+#define RAMCFG_SRAM4_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_NS)
+#define RAMCFG_BKPRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS)
+#define DMA2D_NS ((DMA2D_TypeDef *) DMA2D_BASE_NS)
+#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS)
+#define DCACHE1_NS ((DCACHE_TypeDef *) DCACHE1_BASE_NS)
+#define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS)
+#define GTZC_TZIC1_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_NS)
+#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS)
+#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS)
+#define GTZC_MPCBB3_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_NS)
+
+/*!< AHB2 Non secure peripherals */
+#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS)
+#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS)
+#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS)
+#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS)
+#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS)
+#define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS)
+#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS)
+#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS)
+#define GPIOI_NS ((GPIO_TypeDef *) GPIOI_BASE_NS)
+#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS)
+#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS)
+#define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS)
+#define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS)
+#define USB_OTG_FS_NS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_BASE_NS)
+#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS)
+#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS)
+#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS)
+#define OCTOSPIM_NS ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_NS)
+#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS)
+#define SDMMC2_NS ((SDMMC_TypeDef *) SDMMC2_BASE_NS)
+#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS)
+#define DLYB_SDMMC2_NS ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_NS)
+#define DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS)
+#define DLYB_OCTOSPI2_NS ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_NS)
+#define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS)
+#define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS)
+#define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS)
+#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS)
+#define OCTOSPI2_NS ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_NS)
+
+/*!< AHB3 Non secure peripherals */
+#define LPGPIO1_NS ((GPIO_TypeDef *) LPGPIO1_BASE_NS)
+#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS)
+#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS)
+#define ADC4_NS ((ADC_TypeDef *) ADC4_BASE_NS)
+#define ADC4_COMMON_NS ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_NS)
+#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS)
+#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS)
+#define GTZC_TZSC2_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_NS)
+#define GTZC_TZIC2_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_NS)
+#define GTZC_MPCBB4_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_NS)
+#define ADF1_NS ((MDF_TypeDef *) ADF1_BASE_NS)
+#define ADF1_Filter0_NS ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_NS)
+#define LPDMA1_NS ((DMA_TypeDef *) LPDMA1_BASE_NS)
+#define LPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_NS)
+#define LPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_NS)
+#define LPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_NS)
+#define LPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_NS)
+
+/*!< APB1 Secure peripherals */
+#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S)
+#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S)
+#define TIM4_S ((TIM_TypeDef *) TIM4_BASE_S)
+#define TIM5_S ((TIM_TypeDef *) TIM5_BASE_S)
+#define TIM6_S ((TIM_TypeDef *) TIM6_BASE_S)
+#define TIM7_S ((TIM_TypeDef *) TIM7_BASE_S)
+#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S)
+#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S)
+#define SPI2_S ((SPI_TypeDef *) SPI2_BASE_S)
+#define USART2_S ((USART_TypeDef *) USART2_BASE_S)
+#define USART3_S ((USART_TypeDef *) USART3_BASE_S)
+#define UART4_S ((USART_TypeDef *) UART4_BASE_S)
+#define UART5_S ((USART_TypeDef *) UART5_BASE_S)
+#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S)
+#define I2C2_S ((I2C_TypeDef *) I2C2_BASE_S)
+#define CRS_S ((CRS_TypeDef *) CRS_BASE_S)
+#define I2C4_S ((I2C_TypeDef *) I2C4_BASE_S)
+#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S)
+#define FDCAN1_S ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S)
+#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S)
+#define UCPD1_S ((UCPD_TypeDef *) UCPD1_BASE_S)
+
+/*!< APB2 Secure peripherals */
+#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S)
+#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S)
+#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S)
+#define USART1_S ((USART_TypeDef *) USART1_BASE_S)
+#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S)
+#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S)
+#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S)
+#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S)
+#define SAI1_Block_A_S ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S)
+#define SAI1_Block_B_S ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S)
+#define SAI2_S ((SAI_TypeDef *) SAI2_BASE_S)
+#define SAI2_Block_A_S ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_S)
+#define SAI2_Block_B_S ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_S)
+
+/*!< APB3 secure peripherals */
+#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S)
+#define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S)
+#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S)
+#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S)
+#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S)
+#define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S)
+#define LPTIM4_S ((LPTIM_TypeDef *) LPTIM4_BASE_S)
+#define OPAMP_S ((OPAMP_TypeDef *) OPAMP_BASE_S)
+#define OPAMP1_S ((OPAMP_TypeDef *) OPAMP1_BASE_S)
+#define OPAMP2_S ((OPAMP_TypeDef *) OPAMP2_BASE_S)
+#define COMP12_S ((COMP_TypeDef *) COMP12_BASE_S)
+#define COMP1_S ((COMP_TypeDef *) COMP1_BASE_S)
+#define COMP2_S ((COMP_TypeDef *) COMP2_BASE_S)
+#define COMP12_COMMON_S ((COMP_Common_TypeDef *) COMP1_BASE_S)
+#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S)
+#define RTC_S ((RTC_TypeDef *) RTC_BASE_S)
+#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S)
+
+/*!< AHB1 Secure peripherals */
+#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S)
+#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S)
+#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S)
+#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S)
+#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S)
+#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S)
+#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S)
+#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S)
+#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S)
+#define GPDMA1_Channel8_S ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S)
+#define GPDMA1_Channel9_S ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S)
+#define GPDMA1_Channel10_S ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S)
+#define GPDMA1_Channel11_S ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S)
+#define GPDMA1_Channel12_S ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_S)
+#define GPDMA1_Channel13_S ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_S)
+#define GPDMA1_Channel14_S ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_S)
+#define GPDMA1_Channel15_S ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_S)
+#define CORDIC_S ((CORDIC_TypeDef *) CORDIC_BASE_S)
+#define FMAC_S ((FMAC_TypeDef *) FMAC_BASE_S)
+#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S)
+#define CRC_S ((CRC_TypeDef *) CRC_BASE_S)
+#define TSC_S ((TSC_TypeDef *) TSC_BASE_S)
+#define MDF1_S ((MDF_TypeDef *) MDF1_BASE_S)
+#define MDF1_Filter0_S ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_S)
+#define MDF1_Filter1_S ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_S)
+#define MDF1_Filter2_S ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_S)
+#define MDF1_Filter3_S ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_S)
+#define MDF1_Filter4_S ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_S)
+#define MDF1_Filter5_S ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_S)
+#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S)
+#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S)
+#define RAMCFG_SRAM3_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_S)
+#define RAMCFG_SRAM4_S ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_S)
+#define RAMCFG_BKPRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_S)
+#define DMA2D_S ((DMA2D_TypeDef *) DMA2D_BASE_S)
+#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S)
+#define DCACHE1_S ((DCACHE_TypeDef *) DCACHE1_BASE_S)
+#define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S)
+#define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S)
+#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S)
+#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S)
+#define GTZC_MPCBB3_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_S)
+
+/*!< AHB2 Secure peripherals */
+#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S)
+#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S)
+#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S)
+#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S)
+#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S)
+#define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S)
+#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S)
+#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S)
+#define GPIOI_S ((GPIO_TypeDef *) GPIOI_BASE_S)
+#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S)
+#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S)
+#define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S)
+#define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S)
+#define USB_OTG_FS_S ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_BASE_S)
+#define HASH_S ((HASH_TypeDef *) HASH_BASE_S)
+#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S)
+#define RNG_S ((RNG_TypeDef *) RNG_BASE_S)
+#define OCTOSPIM_S ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_S)
+#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S)
+#define SDMMC2_S ((SDMMC_TypeDef *) SDMMC2_BASE_S)
+#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S)
+#define DLYB_SDMMC2_S ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_S)
+#define DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S)
+#define DLYB_OCTOSPI2_S ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_S)
+#define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S)
+#define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S)
+#define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S)
+#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S)
+#define OCTOSPI2_S ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_S)
+
+/*!< AHB3 Secure peripherals */
+#define LPGPIO1_S ((GPIO_TypeDef *) LPGPIO1_BASE_S)
+#define PWR_S ((PWR_TypeDef *) PWR_BASE_S)
+#define RCC_S ((RCC_TypeDef *) RCC_BASE_S)
+#define ADC4_S ((ADC_TypeDef *) ADC4_BASE_S)
+#define ADC4_COMMON_S ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_S)
+#define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S)
+#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S)
+#define GTZC_TZSC2_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_S)
+#define GTZC_TZIC2_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_S)
+#define GTZC_MPCBB4_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_S)
+#define ADF1_S ((MDF_TypeDef *) ADF1_BASE_S)
+#define ADF1_Filter0_S ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_S)
+#define LPDMA1_S ((DMA_TypeDef *) LPDMA1_BASE_S)
+#define LPDMA1_Channel0_S ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_S)
+#define LPDMA1_Channel1_S ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_S)
+#define LPDMA1_Channel2_S ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_S)
+#define LPDMA1_Channel3_S ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_S)
+
+/*!< DBGMCU peripheral */
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/*!< Memory base addresses for Secure peripherals */
+#define FLASH_BASE FLASH_BASE_S
+#define SRAM1_BASE SRAM1_BASE_S
+#define SRAM2_BASE SRAM2_BASE_S
+#define SRAM3_BASE SRAM3_BASE_S
+#define SRAM4_BASE SRAM4_BASE_S
+#define BKPSRAM_BASE BKPSRAM_BASE_S
+#define PERIPH_BASE PERIPH_BASE_S
+#define APB1PERIPH_BASE APB1PERIPH_BASE_S
+#define APB2PERIPH_BASE APB2PERIPH_BASE_S
+#define AHB1PERIPH_BASE AHB1PERIPH_BASE_S
+#define AHB2PERIPH_BASE AHB2PERIPH_BASE_S
+
+/*!< Instance aliases and base addresses for Secure peripherals */
+#define CORDIC CORDIC_S
+#define CORDIC_BASE CORDIC_BASE_S
+
+#define RCC RCC_S
+#define RCC_BASE RCC_BASE_S
+
+#define DCMI DCMI_S
+#define DCMI_BASE DCMI_BASE_S
+
+#define PSSI PSSI_S
+#define PSSI_BASE PSSI_BASE_S
+
+#define FLASH FLASH_S
+#define FLASH_R_BASE FLASH_R_BASE_S
+
+#define FMAC FMAC_S
+#define FMAC_BASE FMAC_BASE_S
+
+#define GPDMA1 GPDMA1_S
+#define GPDMA1_BASE GPDMA1_BASE_S
+
+#define GPDMA1_Channel0 GPDMA1_Channel0_S
+#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S
+
+#define GPDMA1_Channel1 GPDMA1_Channel1_S
+#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S
+
+#define GPDMA1_Channel2 GPDMA1_Channel2_S
+#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S
+
+#define GPDMA1_Channel3 GPDMA1_Channel3_S
+#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S
+
+#define GPDMA1_Channel4 GPDMA1_Channel4_S
+#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S
+
+#define GPDMA1_Channel5 GPDMA1_Channel5_S
+#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S
+
+#define GPDMA1_Channel6 GPDMA1_Channel6_S
+#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S
+
+#define GPDMA1_Channel7 GPDMA1_Channel7_S
+#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S
+
+#define GPDMA1_Channel8 GPDMA1_Channel8_S
+#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_S
+
+#define GPDMA1_Channel9 GPDMA1_Channel9_S
+#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_S
+
+#define GPDMA1_Channel10 GPDMA1_Channel10_S
+#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_S
+
+#define GPDMA1_Channel11 GPDMA1_Channel11_S
+#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_S
+
+#define GPDMA1_Channel12 GPDMA1_Channel12_S
+#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_S
+
+#define GPDMA1_Channel13 GPDMA1_Channel13_S
+#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_S
+
+#define GPDMA1_Channel14 GPDMA1_Channel14_S
+#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_S
+
+#define GPDMA1_Channel15 GPDMA1_Channel15_S
+#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_S
+
+#define LPDMA1 LPDMA1_S
+#define LPDMA1_BASE LPDMA1_BASE_S
+
+#define LPDMA1_Channel0 LPDMA1_Channel0_S
+#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_S
+
+#define LPDMA1_Channel1 LPDMA1_Channel1_S
+#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_S
+
+#define LPDMA1_Channel2 LPDMA1_Channel2_S
+#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_S
+
+#define LPDMA1_Channel3 LPDMA1_Channel3_S
+#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_S
+
+#define GPIOA GPIOA_S
+#define GPIOA_BASE GPIOA_BASE_S
+
+#define GPIOB GPIOB_S
+#define GPIOB_BASE GPIOB_BASE_S
+
+#define GPIOC GPIOC_S
+#define GPIOC_BASE GPIOC_BASE_S
+
+#define GPIOD GPIOD_S
+#define GPIOD_BASE GPIOD_BASE_S
+
+#define GPIOE GPIOE_S
+#define GPIOE_BASE GPIOE_BASE_S
+
+#define GPIOF GPIOF_S
+#define GPIOF_BASE GPIOF_BASE_S
+
+#define GPIOG GPIOG_S
+#define GPIOG_BASE GPIOG_BASE_S
+
+#define GPIOH GPIOH_S
+#define GPIOH_BASE GPIOH_BASE_S
+
+#define GPIOI GPIOI_S
+#define GPIOI_BASE GPIOI_BASE_S
+
+#define LPGPIO1 LPGPIO1_S
+#define LPGPIO1_BASE LPGPIO1_BASE_S
+
+#define PWR PWR_S
+#define PWR_BASE PWR_BASE_S
+
+#define RAMCFG_SRAM1 RAMCFG_SRAM1_S
+#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S
+
+#define RAMCFG_SRAM2 RAMCFG_SRAM2_S
+#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S
+
+#define RAMCFG_SRAM3 RAMCFG_SRAM3_S
+#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_S
+
+#define RAMCFG_SRAM4 RAMCFG_SRAM4_S
+#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_S
+
+#define RAMCFG_BKPRAM RAMCFG_BKPRAM_S
+#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_S
+
+#define EXTI EXTI_S
+#define EXTI_BASE EXTI_BASE_S
+
+#define ICACHE ICACHE_S
+#define ICACHE_BASE ICACHE_BASE_S
+
+#define DCACHE1 DCACHE1_S
+#define DCACHE1_BASE DCACHE1_BASE_S
+
+#define GTZC_TZSC1 GTZC_TZSC1_S
+#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_S
+
+#define GTZC_TZSC2 GTZC_TZSC2_S
+#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_S
+
+#define GTZC_TZIC1 GTZC_TZIC1_S
+#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_S
+
+#define GTZC_TZIC2 GTZC_TZIC2_S
+#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_S
+
+#define GTZC_MPCBB1 GTZC_MPCBB1_S
+#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S
+
+#define GTZC_MPCBB2 GTZC_MPCBB2_S
+#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S
+
+#define GTZC_MPCBB3 GTZC_MPCBB3_S
+#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_S
+
+#define GTZC_MPCBB4 GTZC_MPCBB4_S
+#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_S
+
+#define RTC RTC_S
+#define RTC_BASE RTC_BASE_S
+
+#define TAMP TAMP_S
+#define TAMP_BASE TAMP_BASE_S
+
+#define TIM1 TIM1_S
+#define TIM1_BASE TIM1_BASE_S
+
+#define TIM2 TIM2_S
+#define TIM2_BASE TIM2_BASE_S
+
+#define TIM3 TIM3_S
+#define TIM3_BASE TIM3_BASE_S
+
+#define TIM4 TIM4_S
+#define TIM4_BASE TIM4_BASE_S
+
+#define TIM5 TIM5_S
+#define TIM5_BASE TIM5_BASE_S
+
+#define TIM6 TIM6_S
+#define TIM6_BASE TIM6_BASE_S
+
+#define TIM7 TIM7_S
+#define TIM7_BASE TIM7_BASE_S
+
+#define TIM8 TIM8_S
+#define TIM8_BASE TIM8_BASE_S
+
+#define TIM15 TIM15_S
+#define TIM15_BASE TIM15_BASE_S
+
+#define TIM16 TIM16_S
+#define TIM16_BASE TIM16_BASE_S
+
+#define TIM17 TIM17_S
+#define TIM17_BASE TIM17_BASE_S
+
+#define WWDG WWDG_S
+#define WWDG_BASE WWDG_BASE_S
+
+#define IWDG IWDG_S
+#define IWDG_BASE IWDG_BASE_S
+
+#define SPI1 SPI1_S
+#define SPI1_BASE SPI1_BASE_S
+
+#define SPI2 SPI2_S
+#define SPI2_BASE SPI2_BASE_S
+
+#define SPI3 SPI3_S
+#define SPI3_BASE SPI3_BASE_S
+
+#define USART1 USART1_S
+#define USART1_BASE USART1_BASE_S
+
+#define USART2 USART2_S
+#define USART2_BASE USART2_BASE_S
+
+#define USART3 USART3_S
+#define USART3_BASE USART3_BASE_S
+
+#define UART4 UART4_S
+#define UART4_BASE UART4_BASE_S
+
+#define UART5 UART5_S
+#define UART5_BASE UART5_BASE_S
+
+#define I2C1 I2C1_S
+#define I2C1_BASE I2C1_BASE_S
+
+#define I2C2 I2C2_S
+#define I2C2_BASE I2C2_BASE_S
+
+#define I2C3 I2C3_S
+#define I2C3_BASE I2C3_BASE_S
+
+#define I2C4 I2C4_S
+#define I2C4_BASE I2C4_BASE_S
+
+#define CRS CRS_S
+#define CRS_BASE CRS_BASE_S
+
+#define FDCAN1 FDCAN1_S
+#define FDCAN1_BASE FDCAN1_BASE_S
+
+#define FDCAN_CONFIG FDCAN_CONFIG_S
+#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S
+#define SRAMCAN_BASE SRAMCAN_BASE_S
+
+#define DAC DAC_S
+#define DAC_BASE DAC_BASE_S
+
+#define DAC1 DAC1_S
+#define DAC1_BASE DAC1_BASE_S
+
+#define OPAMP OPAMP_S
+#define OPAMP_BASE OPAMP_BASE_S
+
+#define OPAMP1 OPAMP1_S
+#define OPAMP1_BASE OPAMP1_BASE_S
+
+#define OPAMP2 OPAMP2_S
+#define OPAMP2_BASE OPAMP2_BASE_S
+
+#define LPTIM1 LPTIM1_S
+#define LPTIM1_BASE LPTIM1_BASE_S
+
+#define LPTIM2 LPTIM2_S
+#define LPTIM2_BASE LPTIM2_BASE_S
+
+#define LPTIM3 LPTIM3_S
+#define LPTIM3_BASE LPTIM3_BASE_S
+
+#define LPTIM4 LPTIM4_S
+#define LPTIM4_BASE LPTIM4_BASE_S
+
+#define LPUART1 LPUART1_S
+#define LPUART1_BASE LPUART1_BASE_S
+
+#define UCPD1 UCPD1_S
+#define UCPD1_BASE UCPD1_BASE_S
+
+#define SYSCFG SYSCFG_S
+#define SYSCFG_BASE SYSCFG_BASE_S
+
+#define VREFBUF VREFBUF_S
+#define VREFBUF_BASE VREFBUF_BASE_S
+
+#define COMP12 COMP12_S
+#define COMP12_BASE COMP12_BASE_S
+
+#define COMP1 COMP1_S
+#define COMP1_BASE COMP1_BASE_S
+
+#define COMP2 COMP2_S
+#define COMP2_BASE COMP2_BASE_S
+
+#define COMP12_COMMON COMP12_COMMON_S
+#define COMP12_COMMON_BASE COMP1_BASE_S
+
+#define SAI1 SAI1_S
+#define SAI1_BASE SAI1_BASE_S
+
+#define SAI1_Block_A SAI1_Block_A_S
+#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S
+
+#define SAI1_Block_B SAI1_Block_B_S
+#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S
+
+#define SAI2 SAI2_S
+#define SAI2_BASE SAI2_BASE_S
+
+#define SAI2_Block_A SAI2_Block_A_S
+#define SAI2_Block_A_BASE SAI2_Block_A_BASE_S
+
+#define SAI2_Block_B SAI2_Block_B_S
+#define SAI2_Block_B_BASE SAI2_Block_B_BASE_S
+
+#define CRC CRC_S
+#define CRC_BASE CRC_BASE_S
+
+#define TSC TSC_S
+#define TSC_BASE TSC_BASE_S
+
+#define ADC1 ADC1_S
+#define ADC1_BASE ADC1_BASE_S
+
+#define ADC12_COMMON ADC12_COMMON_S
+#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S
+
+#define ADC4 ADC4_S
+#define ADC4_BASE ADC4_BASE_S
+
+#define ADC4_COMMON ADC4_COMMON_S
+#define ADC4_COMMON_BASE ADC4_COMMON_BASE_S
+
+#define HASH HASH_S
+#define HASH_BASE HASH_BASE_S
+
+#define HASH_DIGEST HASH_DIGEST_S
+#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S
+
+#define RNG RNG_S
+#define RNG_BASE RNG_BASE_S
+
+#define SDMMC1 SDMMC1_S
+#define SDMMC1_BASE SDMMC1_BASE_S
+
+#define SDMMC2 SDMMC2_S
+#define SDMMC2_BASE SDMMC2_BASE_S
+
+#define FMC_Bank1_R FMC_Bank1_R_S
+#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_S
+
+#define FMC_Bank1E_R FMC_Bank1E_R_S
+#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_S
+
+#define FMC_Bank3_R FMC_Bank3_R_S
+#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_S
+
+#define OCTOSPI1 OCTOSPI1_S
+#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S
+
+#define OCTOSPI2 OCTOSPI2_S
+#define OCTOSPI2_R_BASE OCTOSPI2_R_BASE_S
+
+#define OCTOSPIM OCTOSPIM_S
+#define OCTOSPIM_R_BASE OCTOSPIM_R_BASE_S
+
+#define DLYB_SDMMC1 DLYB_SDMMC1_S
+#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S
+
+#define DLYB_SDMMC2 DLYB_SDMMC2_S
+#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_S
+
+#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_S
+#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_S
+
+#define DLYB_OCTOSPI2 DLYB_OCTOSPI2_S
+#define DLYB_OCTOSPI2_BASE DLYB_OCTOSPI2_BASE_S
+
+#define DMA2D DMA2D_S
+#define DMA2D_BASE DMA2D_BASE_S
+
+#define USB_OTG_FS USB_OTG_FS_S
+#define USB_OTG_FS_BASE USB_OTG_FS_BASE_S
+
+#define MDF1 MDF1_S
+#define MDF1_BASE MDF1_BASE_S
+
+#define MDF1_Filter0 MDF1_Filter0_S
+#define MDF1_Filter0_BASE MDF1_Filter0_BASE_S
+
+#define MDF1_Filter1 MDF1_Filter1_S
+#define MDF1_Filter1_BASE MDF1_Filter1_BASE_S
+
+#define MDF1_Filter2 MDF1_Filter2_S
+#define MDF1_Filter2_BASE MDF1_Filter2_BASE_S
+
+#define MDF1_Filter3 MDF1_Filter3_S
+#define MDF1_Filter3_BASE MDF1_Filter3_BASE_S
+
+#define MDF1_Filter4 MDF1_Filter4_S
+#define MDF1_Filter4_BASE MDF1_Filter4_BASE_S
+
+#define MDF1_Filter5 MDF1_Filter5_S
+#define MDF1_Filter5_BASE MDF1_Filter5_BASE_S
+
+#define ADF1 ADF1_S
+#define ADF1_BASE ADF1_BASE_S
+
+#define ADF1_Filter0 ADF1_Filter0_S
+#define ADF1_Filter0_BASE ADF1_Filter0_BASE_S
+
+#else
+
+/*!< Memory base addresses for Non secure peripherals */
+#define FLASH_BASE FLASH_BASE_NS
+#define SRAM1_BASE SRAM1_BASE_NS
+#define SRAM2_BASE SRAM2_BASE_NS
+#define SRAM3_BASE SRAM3_BASE_NS
+#define SRAM4_BASE SRAM4_BASE_NS
+#define BKPSRAM_BASE BKPSRAM_BASE_NS
+#define PERIPH_BASE PERIPH_BASE_NS
+#define APB1PERIPH_BASE APB1PERIPH_BASE_NS
+#define APB2PERIPH_BASE APB2PERIPH_BASE_NS
+#define AHB1PERIPH_BASE AHB1PERIPH_BASE_NS
+#define AHB2PERIPH_BASE AHB2PERIPH_BASE_NS
+
+/*!< Instance aliases and base addresses for Non secure peripherals */
+#define CORDIC CORDIC_NS
+#define CORDIC_BASE CORDIC_BASE_NS
+
+#define RCC RCC_NS
+#define RCC_BASE RCC_BASE_NS
+
+#define DMA2D DMA2D_NS
+#define DMA2D_BASE DMA2D_BASE_NS
+
+#define DCMI DCMI_NS
+#define DCMI_BASE DCMI_BASE_NS
+
+#define PSSI PSSI_NS
+#define PSSI_BASE PSSI_BASE_NS
+
+#define FLASH FLASH_NS
+#define FLASH_R_BASE FLASH_R_BASE_NS
+
+#define FMAC FMAC_NS
+#define FMAC_BASE FMAC_BASE_NS
+
+#define GPDMA1 GPDMA1_NS
+#define GPDMA1_BASE GPDMA1_BASE_NS
+
+#define GPDMA1_Channel0 GPDMA1_Channel0_NS
+#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS
+
+#define GPDMA1_Channel1 GPDMA1_Channel1_NS
+#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS
+
+#define GPDMA1_Channel2 GPDMA1_Channel2_NS
+#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS
+
+#define GPDMA1_Channel3 GPDMA1_Channel3_NS
+#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS
+
+#define GPDMA1_Channel4 GPDMA1_Channel4_NS
+#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS
+
+#define GPDMA1_Channel5 GPDMA1_Channel5_NS
+#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS
+
+#define GPDMA1_Channel6 GPDMA1_Channel6_NS
+#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS
+
+#define GPDMA1_Channel7 GPDMA1_Channel7_NS
+#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS
+
+#define GPDMA1_Channel8 GPDMA1_Channel8_NS
+#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_NS
+
+#define GPDMA1_Channel9 GPDMA1_Channel9_NS
+#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_NS
+
+#define GPDMA1_Channel10 GPDMA1_Channel10_NS
+#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_NS
+
+#define GPDMA1_Channel11 GPDMA1_Channel11_NS
+#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_NS
+
+#define GPDMA1_Channel12 GPDMA1_Channel12_NS
+#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_NS
+
+#define GPDMA1_Channel13 GPDMA1_Channel13_NS
+#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_NS
+
+#define GPDMA1_Channel14 GPDMA1_Channel14_NS
+#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_NS
+
+#define GPDMA1_Channel15 GPDMA1_Channel15_NS
+#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_NS
+
+#define LPDMA1 LPDMA1_NS
+#define LPDMA1_BASE LPDMA1_BASE_NS
+
+#define LPDMA1_Channel0 LPDMA1_Channel0_NS
+#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_NS
+
+#define LPDMA1_Channel1 LPDMA1_Channel1_NS
+#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_NS
+
+#define LPDMA1_Channel2 LPDMA1_Channel2_NS
+#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_NS
+
+#define LPDMA1_Channel3 LPDMA1_Channel3_NS
+#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_NS
+
+#define GPIOA GPIOA_NS
+#define GPIOA_BASE GPIOA_BASE_NS
+
+#define GPIOB GPIOB_NS
+#define GPIOB_BASE GPIOB_BASE_NS
+
+#define GPIOC GPIOC_NS
+#define GPIOC_BASE GPIOC_BASE_NS
+
+#define GPIOD GPIOD_NS
+#define GPIOD_BASE GPIOD_BASE_NS
+
+#define GPIOE GPIOE_NS
+#define GPIOE_BASE GPIOE_BASE_NS
+
+#define GPIOF GPIOF_NS
+#define GPIOF_BASE GPIOF_BASE_NS
+
+#define GPIOG GPIOG_NS
+#define GPIOG_BASE GPIOG_BASE_NS
+
+#define GPIOH GPIOH_NS
+#define GPIOH_BASE GPIOH_BASE_NS
+
+#define GPIOI GPIOI_NS
+#define GPIOI_BASE GPIOI_BASE_NS
+
+#define LPGPIO1 LPGPIO1_NS
+#define LPGPIO1_BASE LPGPIO1_BASE_NS
+
+#define PWR PWR_NS
+#define PWR_BASE PWR_BASE_NS
+
+#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS
+#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS
+
+#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS
+#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS
+
+#define RAMCFG_SRAM3 RAMCFG_SRAM3_NS
+#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_NS
+
+#define RAMCFG_SRAM4 RAMCFG_SRAM4_NS
+#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_NS
+
+#define RAMCFG_BKPRAM RAMCFG_BKPRAM_NS
+#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_NS
+
+#define EXTI EXTI_NS
+#define EXTI_BASE EXTI_BASE_NS
+
+#define ICACHE ICACHE_NS
+#define ICACHE_BASE ICACHE_BASE_NS
+
+#define DCACHE1 DCACHE1_NS
+#define DCACHE1_BASE DCACHE1_BASE_NS
+
+#define GTZC_TZSC1 GTZC_TZSC1_NS
+#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS
+
+#define GTZC_TZSC2 GTZC_TZSC2_NS
+#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_NS
+
+#define GTZC_TZIC1 GTZC_TZIC1_NS
+#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_NS
+
+#define GTZC_TZIC2 GTZC_TZIC2_NS
+#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_NS
+
+#define GTZC_MPCBB1 GTZC_MPCBB1_NS
+#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS
+
+#define GTZC_MPCBB2 GTZC_MPCBB2_NS
+#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS
+
+#define GTZC_MPCBB3 GTZC_MPCBB3_NS
+#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_NS
+
+#define GTZC_MPCBB4 GTZC_MPCBB4_NS
+#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_NS
+
+#define RTC RTC_NS
+#define RTC_BASE RTC_BASE_NS
+
+#define TAMP TAMP_NS
+#define TAMP_BASE TAMP_BASE_NS
+
+#define TIM1 TIM1_NS
+#define TIM1_BASE TIM1_BASE_NS
+
+#define TIM2 TIM2_NS
+#define TIM2_BASE TIM2_BASE_NS
+
+#define TIM3 TIM3_NS
+#define TIM3_BASE TIM3_BASE_NS
+
+#define TIM4 TIM4_NS
+#define TIM4_BASE TIM4_BASE_NS
+
+#define TIM5 TIM5_NS
+#define TIM5_BASE TIM5_BASE_NS
+
+#define TIM6 TIM6_NS
+#define TIM6_BASE TIM6_BASE_NS
+
+#define TIM7 TIM7_NS
+#define TIM7_BASE TIM7_BASE_NS
+
+#define TIM8 TIM8_NS
+#define TIM8_BASE TIM8_BASE_NS
+
+#define TIM15 TIM15_NS
+#define TIM15_BASE TIM15_BASE_NS
+
+#define TIM16 TIM16_NS
+#define TIM16_BASE TIM16_BASE_NS
+
+#define TIM17 TIM17_NS
+#define TIM17_BASE TIM17_BASE_NS
+
+#define WWDG WWDG_NS
+#define WWDG_BASE WWDG_BASE_NS
+
+#define IWDG IWDG_NS
+#define IWDG_BASE IWDG_BASE_NS
+
+#define SPI1 SPI1_NS
+#define SPI1_BASE SPI1_BASE_NS
+
+#define SPI2 SPI2_NS
+#define SPI2_BASE SPI2_BASE_NS
+
+#define SPI3 SPI3_NS
+#define SPI3_BASE SPI3_BASE_NS
+
+#define USART1 USART1_NS
+#define USART1_BASE USART1_BASE_NS
+
+#define USART2 USART2_NS
+#define USART2_BASE USART2_BASE_NS
+
+#define USART3 USART3_NS
+#define USART3_BASE USART3_BASE_NS
+
+#define UART4 UART4_NS
+#define UART4_BASE UART4_BASE_NS
+
+#define UART5 UART5_NS
+#define UART5_BASE UART5_BASE_NS
+
+#define I2C1 I2C1_NS
+#define I2C1_BASE I2C1_BASE_NS
+
+#define I2C2 I2C2_NS
+#define I2C2_BASE I2C2_BASE_NS
+
+#define I2C3 I2C3_NS
+#define I2C3_BASE I2C3_BASE_NS
+
+#define I2C4 I2C4_NS
+#define I2C4_BASE I2C4_BASE_NS
+
+#define CRS CRS_NS
+#define CRS_BASE CRS_BASE_NS
+
+#define FDCAN1 FDCAN1_NS
+#define FDCAN1_BASE FDCAN1_BASE_NS
+
+#define FDCAN_CONFIG FDCAN_CONFIG_NS
+#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS
+#define SRAMCAN_BASE SRAMCAN_BASE_NS
+
+#define DAC1 DAC1_NS
+#define DAC1_BASE DAC1_BASE_NS
+
+#define OPAMP OPAMP_NS
+#define OPAMP_BASE OPAMP_BASE_NS
+
+#define OPAMP1 OPAMP1_NS
+#define OPAMP1_BASE OPAMP1_BASE_NS
+
+#define OPAMP2 OPAMP2_NS
+#define OPAMP2_BASE OPAMP2_BASE_NS
+
+#define LPTIM1 LPTIM1_NS
+#define LPTIM1_BASE LPTIM1_BASE_NS
+
+#define LPTIM2 LPTIM2_NS
+#define LPTIM2_BASE LPTIM2_BASE_NS
+
+#define LPTIM3 LPTIM3_NS
+#define LPTIM3_BASE LPTIM3_BASE_NS
+
+#define LPTIM4 LPTIM4_NS
+#define LPTIM4_BASE LPTIM4_BASE_NS
+
+#define LPUART1 LPUART1_NS
+#define LPUART1_BASE LPUART1_BASE_NS
+
+#define UCPD1 UCPD1_NS
+#define UCPD1_BASE UCPD1_BASE_NS
+
+#define SYSCFG SYSCFG_NS
+#define SYSCFG_BASE SYSCFG_BASE_NS
+
+#define VREFBUF VREFBUF_NS
+#define VREFBUF_BASE VREFBUF_BASE_NS
+
+#define COMP12 COMP12_NS
+#define COMP12_BASE COMP12_BASE_NS
+
+#define COMP1 COMP1_NS
+#define COMP1_BASE COMP1_BASE_NS
+
+#define COMP2 COMP2_NS
+#define COMP2_BASE COMP2_BASE_NS
+
+#define COMP12_COMMON COMP12_COMMON_NS
+#define COMP12_COMMON_BASE COMP1_BASE_NS
+
+#define SAI1 SAI1_NS
+#define SAI1_BASE SAI1_BASE_NS
+
+#define SAI1_Block_A SAI1_Block_A_NS
+#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS
+
+#define SAI1_Block_B SAI1_Block_B_NS
+#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS
+
+#define SAI2 SAI2_NS
+#define SAI2_BASE SAI2_BASE_NS
+
+#define SAI2_Block_A SAI2_Block_A_NS
+#define SAI2_Block_A_BASE SAI2_Block_A_BASE_NS
+
+#define SAI2_Block_B SAI2_Block_B_NS
+#define SAI2_Block_B_BASE SAI2_Block_B_BASE_NS
+
+#define CRC CRC_NS
+#define CRC_BASE CRC_BASE_NS
+
+#define TSC TSC_NS
+#define TSC_BASE TSC_BASE_NS
+
+#define ADC1 ADC1_NS
+#define ADC1_BASE ADC1_BASE_NS
+
+#define ADC12_COMMON ADC12_COMMON_NS
+#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS
+
+#define ADC4 ADC4_NS
+#define ADC4_BASE ADC4_BASE_NS
+
+#define ADC4_COMMON ADC4_COMMON_NS
+#define ADC4_COMMON_BASE ADC4_COMMON_BASE_NS
+
+#define HASH HASH_NS
+#define HASH_BASE HASH_BASE_NS
+
+#define HASH_DIGEST HASH_DIGEST_NS
+#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS
+
+#define RNG RNG_NS
+#define RNG_BASE RNG_BASE_NS
+
+#define SDMMC1 SDMMC1_NS
+#define SDMMC1_BASE SDMMC1_BASE_NS
+
+#define SDMMC2 SDMMC2_NS
+#define SDMMC2_BASE SDMMC2_BASE_NS
+
+#define FMC_Bank1_R FMC_Bank1_R_NS
+#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_NS
+
+#define FMC_Bank1E_R FMC_Bank1E_R_NS
+#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_NS
+
+#define FMC_Bank3_R FMC_Bank3_R_NS
+#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_NS
+
+#define OCTOSPI1 OCTOSPI1_NS
+#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS
+
+#define OCTOSPI2 OCTOSPI2_NS
+#define OCTOSPI2_R_BASE OCTOSPI2_R_BASE_NS
+
+#define OCTOSPIM OCTOSPIM_NS
+#define OCTOSPIM_R_BASE OCTOSPIM_R_BASE_NS
+
+#define DLYB_SDMMC1 DLYB_SDMMC1_NS
+#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS
+
+#define DLYB_SDMMC2 DLYB_SDMMC2_NS
+#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_NS
+
+#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS
+#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS
+
+#define DLYB_OCTOSPI2 DLYB_OCTOSPI2_NS
+#define DLYB_OCTOSPI2_BASE DLYB_OCTOSPI2_BASE_NS
+
+#define USB_OTG_FS USB_OTG_FS_NS
+#define USB_OTG_FS_BASE USB_OTG_FS_BASE_NS
+
+#define MDF1 MDF1_NS
+#define MDF1_BASE MDF1_BASE_NS
+
+#define MDF1_Filter0 MDF1_Filter0_NS
+#define MDF1_Filter0_BASE MDF1_Filter0_BASE_NS
+
+#define MDF1_Filter1 MDF1_Filter1_NS
+#define MDF1_Filter1_BASE MDF1_Filter1_BASE_NS
+
+#define MDF1_Filter2 MDF1_Filter2_NS
+#define MDF1_Filter2_BASE MDF1_Filter2_BASE_NS
+
+#define MDF1_Filter3 MDF1_Filter3_NS
+#define MDF1_Filter3_BASE MDF1_Filter3_BASE_NS
+
+#define MDF1_Filter4 MDF1_Filter4_NS
+#define MDF1_Filter4_BASE MDF1_Filter4_BASE_NS
+
+#define MDF1_Filter5 MDF1_Filter5_NS
+#define MDF1_Filter5_BASE MDF1_Filter5_BASE_NS
+
+#define ADF1 ADF1_NS
+#define ADF1_BASE ADF1_BASE_NS
+
+#define ADF1_Filter0 ADF1_Filter0_NS
+#define ADF1_Filter0_BASE ADF1_Filter0_BASE_NS
+
+#endif
+
+/** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 260U /*!< LSI Maximum startup time in us */
+
+/**
+ * @}
+ */
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/******************************* ADC VERSION ********************************/
+#define ADC_VER_V5_X
+/******************** Bit definition for ADC_ISR register ********************/
+#define ADC_ISR_ADRDY_Pos (0U)
+#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
+#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */
+#define ADC_ISR_EOSMP_Pos (1U)
+#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
+#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */
+#define ADC_ISR_EOC_Pos (2U)
+#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
+#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */
+#define ADC_ISR_EOS_Pos (3U)
+#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
+#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */
+#define ADC_ISR_OVR_Pos (4U)
+#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
+#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */
+#define ADC_ISR_JEOC_Pos (5U)
+#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
+#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */
+#define ADC_ISR_JEOS_Pos (6U)
+#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
+#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */
+#define ADC_ISR_AWD1_Pos (7U)
+#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
+#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */
+#define ADC_ISR_AWD2_Pos (8U)
+#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
+#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */
+#define ADC_ISR_AWD3_Pos (9U)
+#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
+#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */
+#define ADC_ISR_JQOVF_Pos (10U)
+#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
+#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_EOCAL_Pos (11U)
+#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */
+#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC End of Calibration flag */
+#define ADC_ISR_LDORDY_Pos (12U)
+#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
+#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC Voltage Regulator Ready flag */
+
+/******************** Bit definition for ADC_IER register ********************/
+#define ADC_IER_ADRDYIE_Pos (0U)
+#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */
+#define ADC_IER_EOSMPIE_Pos (1U)
+#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */
+#define ADC_IER_EOCIE_Pos (2U)
+#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
+#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */
+#define ADC_IER_EOSIE_Pos (3U)
+#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
+#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */
+#define ADC_IER_OVRIE_Pos (4U)
+#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
+#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */
+#define ADC_IER_JEOCIE_Pos (5U)
+#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
+#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */
+#define ADC_IER_JEOSIE_Pos (6U)
+#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
+#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */
+#define ADC_IER_AWD1IE_Pos (7U)
+#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
+#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */
+#define ADC_IER_AWD2IE_Pos (8U)
+#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
+#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */
+#define ADC_IER_AWD3IE_Pos (9U)
+#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
+#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */
+#define ADC_IER_JQOVFIE_Pos (10U)
+#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
+#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */
+#define ADC_IER_EOCALIE_Pos (11U)
+#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */
+#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC End of Calibration Enable */
+#define ADC_IER_LDORDYIE_Pos (12U)
+#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */
+#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC Voltage Regulator Ready flag */
+
+/******************** Bit definition for ADC_CR register ********************/
+#define ADC_CR_ADEN_Pos (0U)
+#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
+#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */
+#define ADC_CR_ADDIS_Pos (1U)
+#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
+#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */
+#define ADC_CR_ADSTART_Pos (2U)
+#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
+#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */
+#define ADC_CR_JADSTART_Pos (3U)
+#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
+#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */
+#define ADC_CR_ADSTP_Pos (4U)
+#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
+#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */
+#define ADC_CR_JADSTP_Pos (5U)
+#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
+#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */
+#define ADC_CR_ADCALLIN_Pos (16U)
+#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */
+#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */
+
+#define ADC_CR_CALINDEX0_Pos (24U)
+#define ADC_CR_CALINDEX0_Msk (0x1UL << ADC_CR_CALINDEX0_Pos) /*!< 0x01000000 */
+#define ADC_CR_CALINDEX0 ADC_CR_CALINDEX0_Msk /*!< ADC Linearity calibration ready Word 3 */
+#define ADC_CR_CALINDEX1_Pos (25U)
+#define ADC_CR_CALINDEX1_Msk (0x1UL << ADC_CR_CALINDEX1_Pos) /*!< 0x02000000 */
+#define ADC_CR_CALINDEX1 ADC_CR_CALINDEX1_Msk /*!< ADC Linearity calibration ready Word 4 */
+#define ADC_CR_CALINDEX2_Pos (26U)
+#define ADC_CR_CALINDEX2_Msk (0x1UL << ADC_CR_CALINDEX2_Pos) /*!< 0x04000000 */
+#define ADC_CR_CALINDEX2 ADC_CR_CALINDEX2_Msk /*!< ADC Linearity calibration ready Word 5 */
+#define ADC_CR_CALINDEX3_Pos (27U)
+#define ADC_CR_CALINDEX3_Msk (0x1UL << ADC_CR_CALINDEX3_Pos) /*!< 0x08000000 */
+#define ADC_CR_CALINDEX3 ADC_CR_CALINDEX3_Msk /*!< ADC Linearity calibration ready Word 6 */
+#define ADC_CR_ADVREGEN_Pos (28U)
+#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */
+#define ADC_CR_DEEPPWD_Pos (29U)
+#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
+#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */
+#define ADC_CR_ADCAL_Pos (31U)
+#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
+#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */
+
+/******************** Bit definition for ADC_CFGR register ********************/
+#define ADC_CFGR1_DMNGT_Pos (0U)
+#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */
+#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC Data Management configuration */
+#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */
+#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */
+
+#define ADC_CFGR1_RES_Pos (2U)
+#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */
+#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC Data resolution */
+#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */
+#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
+
+#define ADC4_CFGR1_DMAEN_Pos (0U)
+#define ADC4_CFGR1_DMAEN_Msk (0x1UL << ADC4_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
+#define ADC4_CFGR1_DMAEN ADC4_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */
+#define ADC4_CFGR1_DMACFG_Pos (1U)
+#define ADC4_CFGR1_DMACFG_Msk (0x1UL << ADC4_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
+#define ADC4_CFGR1_DMACFG ADC4_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */
+
+#define ADC4_CFGR1_SCANDIR_Pos (4U)
+#define ADC4_CFGR1_SCANDIR_Msk (0x1UL << ADC4_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
+#define ADC4_CFGR1_SCANDIR ADC4_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */
+
+#define ADC4_CFGR1_ALIGN_Pos (5U)
+#define ADC4_CFGR1_ALIGN_Msk (0x1UL << ADC4_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
+#define ADC4_CFGR1_ALIGN ADC4_CFGR1_ALIGN_Msk /*!< ADC data alignment */
+
+#define ADC_CFGR1_EXTSEL_Pos (5U)
+#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */
+#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */
+#define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */
+#define ADC_CFGR1_EXTSEL_1 (0x02UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
+#define ADC_CFGR1_EXTSEL_2 (0x04UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
+#define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
+#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */
+
+#define ADC_CFGR1_EXTEN_Pos (10U)
+#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
+#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */
+#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
+#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
+
+#define ADC_CFGR1_OVRMOD_Pos (12U)
+#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
+#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC overrun mode */
+#define ADC_CFGR1_CONT_Pos (13U)
+#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
+#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */
+
+#define ADC_CFGR1_AUTDLY_Pos (14U)
+#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */
+#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC Delayed conversion mode */
+
+#define ADC4_CFGR1_WAIT_Pos (14U)
+#define ADC4_CFGR1_WAIT_Msk (0x1UL << ADC4_CFGR1_WAIT_Pos) /*!< 0x00004000 */
+#define ADC4_CFGR1_WAIT ADC4_CFGR1_WAIT_Msk /*!< ADC Delayed conversion mode */
+
+
+#define ADC_CFGR1_DISCEN_Pos (16U)
+#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
+#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */
+
+#define ADC_CFGR1_DISCNUM_Pos (17U)
+#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */
+#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */
+#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */
+#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */
+#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */
+
+#define ADC_CFGR1_JDISCEN_Pos (20U)
+#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */
+#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */
+
+#define ADC_CFGR1_AWD1SGL_Pos (22U)
+#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */
+#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */
+#define ADC_CFGR1_AWD1EN_Pos (23U)
+#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */
+#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */
+#define ADC_CFGR1_JAWD1EN_Pos (24U)
+#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */
+#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */
+#define ADC_CFGR1_JAUTO_Pos (25U)
+#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */
+#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC Automatic injected group conversion */
+
+/* Specific ADC4 */
+#define ADC4_CFGR1_EXTSEL_Pos (6U)
+#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */
+#define ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */
+#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */
+#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
+#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
+
+#define ADC4_CFGR1_CHSELRMOD_Pos (21U)
+#define ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */
+#define ADC4_CFGR1_CHSELRMOD ADC4_CFGR1_CHSELRMOD_Msk /*!< ADC JSQR Queue mode */
+
+#define ADC_CFGR1_AWD1CH_Pos (26U)
+#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */
+#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */
+#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */
+#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */
+#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */
+#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */
+#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for ADC_CFGR2 register ********************/
+#define ADC_CFGR2_ROVSE_Pos (0U)
+#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
+#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */
+#define ADC_CFGR2_JOVSE_Pos (1U)
+#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
+#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */
+
+#define ADC_CFGR2_OVSS_Pos (5U)
+#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */
+#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
+
+#define ADC_CFGR2_TROVS_Pos (9U)
+#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
+#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */
+#define ADC_CFGR2_ROVSM_Pos (10U)
+#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
+#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */
+
+
+#define ADC_CFGR2_OVSR_Pos (16U)
+#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */
+#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */
+#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */
+#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */
+#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */
+#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */
+#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */
+#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */
+#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */
+#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */
+#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */
+#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */
+
+#define ADC_CFGR2_BULB_Pos (13U)
+#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */
+#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */
+
+#define ADC_CFGR2_SWTRIG_Pos (14U)
+#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */
+#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software trigger bit for sampling time control trigger mode */
+
+#define ADC_CFGR2_SMPTRIG_Pos (15U)
+#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */
+#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sampling time control trigger mode */
+
+#define ADC_CFGR2_LFTRIG_Pos (27U)
+#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x08000000 */
+#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */
+
+#define ADC_CFGR2_LSHIFT_Pos (28U)
+#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */
+#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */
+#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */
+#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */
+#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */
+#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */
+
+/* Specific ADC4 */
+#define ADC4_CFGR2_OVSR_Pos (2U)
+#define ADC4_CFGR2_OVSR_Msk (0x7UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x0000001C */
+#define ADC4_CFGR2_OVSR ADC4_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */
+#define ADC4_CFGR2_OVSR_0 (0x1UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000004 */
+#define ADC4_CFGR2_OVSR_1 (0x2UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000008 */
+#define ADC4_CFGR2_OVSR_2 (0x4UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000010 */
+
+#define ADC4_CFGR2_LFTRIG_Pos (29U)
+#define ADC4_CFGR2_LFTRIG_Msk (0x1UL << ADC4_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */
+#define ADC4_CFGR2_LFTRIG ADC4_CFGR2_LFTRIG_Msk /*!< ADC4 low frequency trigger mode */
+
+/******************** Bit definition for ADC_SMPR1 register ********************/
+#define ADC_SMPR1_SMP0_Pos (0U)
+#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
+#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */
+#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
+#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
+#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP1_Pos (3U)
+#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
+#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */
+#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
+#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
+#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP2_Pos (6U)
+#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */
+#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
+#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
+#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP3_Pos (9U)
+#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */
+#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
+#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
+#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP4_Pos (12U)
+#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
+#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */
+#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
+#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
+#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP5_Pos (15U)
+#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
+#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */
+#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
+#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
+#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP6_Pos (18U)
+#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */
+#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
+#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
+#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR1_SMP7_Pos (21U)
+#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */
+#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
+#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
+#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
+
+#define ADC_SMPR1_SMP8_Pos (24U)
+#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
+#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */
+#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
+#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
+#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
+
+#define ADC_SMPR1_SMP9_Pos (27U)
+#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
+#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */
+#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
+#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
+#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
+
+#define ADC4_SMPR_SMP1_Pos (0U)
+#define ADC4_SMPR_SMP1_Msk (0x7UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000007 */
+#define ADC4_SMPR_SMP1 ADC4_SMPR_SMP1_Msk /*!< ADC Channel 0 Sampling time selection */
+#define ADC4_SMPR_SMP1_0 (0x1UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000001 */
+#define ADC4_SMPR_SMP1_1 (0x2UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000002 */
+#define ADC4_SMPR_SMP1_2 (0x4UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000004 */
+
+#define ADC4_SMPR_SMP2_Pos (4U)
+#define ADC4_SMPR_SMP2_Msk (0x7UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000070 */
+#define ADC4_SMPR_SMP2 ADC4_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */
+#define ADC4_SMPR_SMP2_0 (0x1UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000010 */
+#define ADC4_SMPR_SMP2_1 (0x2UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000020 */
+#define ADC4_SMPR_SMP2_2 (0x4UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000040 */
+
+#define ADC4_SMPR_SMPSEL_Pos (8U)
+#define ADC4_SMPR_SMPSEL_Msk (0xFFFFFFUL << ADC4_SMPR_SMPSEL_Pos) /*!< 0xFFFFFF00 */
+#define ADC4_SMPR_SMPSEL ADC4_SMPR_SMPSEL_Msk /*!< ADC4 all channels sampling time selection */
+#define ADC4_SMPR_SMPSEL0_Pos (8U)
+#define ADC4_SMPR_SMPSEL0_Msk (0x1UL << ADC4_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */
+#define ADC4_SMPR_SMPSEL0 ADC4_SMPR_SMPSEL0_Msk /*!< ADC4 channel 0 sampling time selection */
+#define ADC4_SMPR_SMPSEL1_Pos (9U)
+#define ADC4_SMPR_SMPSEL1_Msk (0x1UL << ADC4_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */
+#define ADC4_SMPR_SMPSEL1 ADC4_SMPR_SMPSEL1_Msk /*!< ADC4 channel 1 sampling time selection */
+#define ADC4_SMPR_SMPSEL2_Pos (10U)
+#define ADC4_SMPR_SMPSEL2_Msk (0x1UL << ADC4_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */
+#define ADC4_SMPR_SMPSEL2 ADC4_SMPR_SMPSEL2_Msk /*!< ADC4 channel 2 sampling time selection */
+#define ADC4_SMPR_SMPSEL3_Pos (11U)
+#define ADC4_SMPR_SMPSEL3_Msk (0x1UL << ADC4_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */
+#define ADC4_SMPR_SMPSEL3 ADC4_SMPR_SMPSEL3_Msk /*!< ADC4 channel 3 sampling time selection */
+#define ADC4_SMPR_SMPSEL4_Pos (12U)
+#define ADC4_SMPR_SMPSEL4_Msk (0x1UL << ADC4_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */
+#define ADC4_SMPR_SMPSEL4 ADC4_SMPR_SMPSEL4_Msk /*!< ADC4 channel 4 sampling time selection */
+#define ADC4_SMPR_SMPSEL5_Pos (13U)
+#define ADC4_SMPR_SMPSEL5_Msk (0x1UL << ADC4_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */
+#define ADC4_SMPR_SMPSEL5 ADC4_SMPR_SMPSEL5_Msk /*!< ADC4 channel 5 sampling time selection */
+#define ADC4_SMPR_SMPSEL6_Pos (14U)
+#define ADC4_SMPR_SMPSEL6_Msk (0x1UL << ADC4_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */
+#define ADC4_SMPR_SMPSEL6 ADC4_SMPR_SMPSEL6_Msk /*!< ADC4 channel 6 sampling time selection */
+#define ADC4_SMPR_SMPSEL7_Pos (15U)
+#define ADC4_SMPR_SMPSEL7_Msk (0x1UL << ADC4_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */
+#define ADC4_SMPR_SMPSEL7 ADC4_SMPR_SMPSEL7_Msk /*!< ADC4 channel 7 sampling time selection */
+#define ADC4_SMPR_SMPSEL8_Pos (16U)
+#define ADC4_SMPR_SMPSEL8_Msk (0x1UL << ADC4_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */
+#define ADC4_SMPR_SMPSEL8 ADC4_SMPR_SMPSEL8_Msk /*!< ADC4 channel 8 sampling time selection */
+#define ADC4_SMPR_SMPSEL9_Pos (17U)
+#define ADC4_SMPR_SMPSEL9_Msk (0x1UL << ADC4_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */
+#define ADC4_SMPR_SMPSEL9 ADC4_SMPR_SMPSEL9_Msk /*!< ADC4 channel 9 sampling time selection */
+#define ADC4_SMPR_SMPSEL10_Pos (18U)
+#define ADC4_SMPR_SMPSEL10_Msk (0x1UL << ADC4_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */
+#define ADC4_SMPR_SMPSEL10 ADC4_SMPR_SMPSEL10_Msk /*!< ADC4 channel 10 sampling time selection */
+#define ADC4_SMPR_SMPSEL11_Pos (19U)
+#define ADC4_SMPR_SMPSEL11_Msk (0x1UL << ADC4_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */
+#define ADC4_SMPR_SMPSEL11 ADC4_SMPR_SMPSEL11_Msk /*!< ADC4 channel 11 sampling time selection */
+#define ADC4_SMPR_SMPSEL12_Pos (20U)
+#define ADC4_SMPR_SMPSEL12_Msk (0x1UL << ADC4_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */
+#define ADC4_SMPR_SMPSEL12 ADC4_SMPR_SMPSEL12_Msk /*!< ADC4 channel 12 sampling time selection */
+#define ADC4_SMPR_SMPSEL13_Pos (21U)
+#define ADC4_SMPR_SMPSEL13_Msk (0x1UL << ADC4_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */
+#define ADC4_SMPR_SMPSEL13 ADC4_SMPR_SMPSEL13_Msk /*!< ADC4 channel 13 sampling time selection */
+#define ADC4_SMPR_SMPSEL14_Pos (22U)
+#define ADC4_SMPR_SMPSEL14_Msk (0x1UL << ADC4_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */
+#define ADC4_SMPR_SMPSEL14 ADC4_SMPR_SMPSEL14_Msk /*!< ADC4 channel 14 sampling time selection */
+#define ADC4_SMPR_SMPSEL15_Pos (23U)
+#define ADC4_SMPR_SMPSEL15_Msk (0x1UL << ADC4_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */
+#define ADC4_SMPR_SMPSEL15 ADC4_SMPR_SMPSEL15_Msk /*!< ADC4 channel 15 sampling time selection */
+#define ADC4_SMPR_SMPSEL16_Pos (24U)
+#define ADC4_SMPR_SMPSEL16_Msk (0x1UL << ADC4_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */
+#define ADC4_SMPR_SMPSEL16 ADC4_SMPR_SMPSEL16_Msk /*!< ADC4 channel 16 sampling time selection */
+#define ADC4_SMPR_SMPSEL17_Pos (25U)
+#define ADC4_SMPR_SMPSEL17_Msk (0x1UL << ADC4_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */
+#define ADC4_SMPR_SMPSEL17 ADC4_SMPR_SMPSEL17_Msk /*!< ADC4 channel 17 sampling time selection */
+#define ADC4_SMPR_SMPSEL18_Pos (26U)
+#define ADC4_SMPR_SMPSEL18_Msk (0x1UL << ADC4_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */
+#define ADC4_SMPR_SMPSEL18 ADC4_SMPR_SMPSEL18_Msk /*!< ADC4 channel 18 sampling time selection */
+#define ADC4_SMPR_SMPSEL19_Pos (27U)
+#define ADC4_SMPR_SMPSEL19_Msk (0x1UL << ADC4_SMPR_SMPSEL19_Pos) /*!< 0x08000000 */
+#define ADC4_SMPR_SMPSEL19 ADC4_SMPR_SMPSEL19_Msk /*!< ADC4 channel 19 sampling time selection */
+#define ADC4_SMPR_SMPSEL20_Pos (26U)
+#define ADC4_SMPR_SMPSEL20_Msk (0x1UL << ADC4_SMPR_SMPSEL20_Pos) /*!< 0x10000000 */
+#define ADC4_SMPR_SMPSEL20 ADC4_SMPR_SMPSEL20_Msk /*!< ADC4 channel 20 sampling time selection */
+#define ADC4_SMPR_SMPSEL21_Pos (26U)
+#define ADC4_SMPR_SMPSEL21_Msk (0x1UL << ADC4_SMPR_SMPSEL21_Pos) /*!< 0x20000000 */
+#define ADC4_SMPR_SMPSEL21 ADC4_SMPR_SMPSEL21_Msk /*!< ADC4 channel 20 sampling time selection */
+#define ADC4_SMPR_SMPSEL22_Pos (30U)
+#define ADC4_SMPR_SMPSEL22_Msk (0x1UL << ADC4_SMPR_SMPSEL22_Pos) /*!< 0x40000000 */
+#define ADC4_SMPR_SMPSEL22 ADC4_SMPR_SMPSEL22_Msk /*!< ADC4 channel 21 sampling time selection */
+#define ADC4_SMPR_SMPSEL23_Pos (31U)
+#define ADC4_SMPR_SMPSEL23_Msk (0x1UL << ADC4_SMPR_SMPSEL23_Pos) /*!< 0x80000000 */
+#define ADC4_SMPR_SMPSEL23 ADC4_SMPR_SMPSEL23_Msk /*!< ADC4 channel 23 sampling time selection */
+
+
+/******************** Bit definition for ADC_SMPR2 register ********************/
+#define ADC_SMPR2_SMP10_Pos (0U)
+#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
+#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */
+#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
+#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
+#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP11_Pos (3U)
+#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
+#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */
+#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
+#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
+#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP12_Pos (6U)
+#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */
+#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
+#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
+#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP13_Pos (9U)
+#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */
+#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
+#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
+#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP14_Pos (12U)
+#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
+#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */
+#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
+#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
+#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP15_Pos (15U)
+#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
+#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */
+#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
+#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
+#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP16_Pos (18U)
+#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */
+#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
+#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
+#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP17_Pos (21U)
+#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */
+#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
+#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
+#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP18_Pos (24U)
+#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
+#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */
+#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
+#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
+#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
+
+#define ADC_SMPR2_SMP19_Pos (27U)
+#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */
+#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */
+#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */
+#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */
+#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */
+
+/******************** Bit definition for ADC_PCSEL register ********************/
+#define ADC_PCSEL_PCSEL_Pos (0U)
+#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */
+#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */
+#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */
+#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */
+#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */
+#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */
+#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */
+#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */
+#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */
+#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */
+#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */
+#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */
+#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */
+#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */
+#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */
+#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */
+#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */
+#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */
+#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */
+#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */
+#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */
+#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */
+
+/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/
+#define ADC_LTR_LT_Pos (0U)
+#define ADC_LTR_LT_Msk (0x01FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x01FFFFFF */
+#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */
+
+/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/
+#define ADC_HTR_HT_Pos (0U)
+#define ADC_HTR_HT_Msk (0x01FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x01FFFFFF */
+#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */
+
+#define ADC_HTR_AWDFILT_Pos (29U)
+#define ADC_HTR_AWDFILT_Msk (0x7UL << ADC_HTR_AWDFILT_Pos) /*!< 0xE0000000 */
+#define ADC_HTR_AWDFILT ADC_HTR_HT_Msk /*!< Analog watchdog filtering parameter, HTR1 only */
+#define ADC_HTR_AWDFILT_0 (0x1UL << ADC_HTR_AWDFILT_Pos) /*!< 0x20000000 */
+#define ADC_HTR_AWDFILT_1 (0x2UL << ADC_HTR_AWDFILT_Pos) /*!< 0x40000000 */
+#define ADC_HTR_AWDFILT_2 (0x4UL << ADC_HTR_AWDFILT_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for ADC_SQR1 register ********************/
+#define ADC_SQR1_L_Pos (0U)
+#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */
+#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
+#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
+#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
+#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */
+
+#define ADC_SQR1_SQ1_Pos (6U)
+#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
+#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */
+#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
+#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
+#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
+#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
+#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
+
+#define ADC_SQR1_SQ2_Pos (12U)
+#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
+#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */
+#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
+#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
+#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
+#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
+#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
+
+#define ADC_SQR1_SQ3_Pos (18U)
+#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
+#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */
+#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
+#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
+#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
+#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
+#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
+
+#define ADC_SQR1_SQ4_Pos (24U)
+#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
+#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */
+#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
+#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
+#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
+#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
+#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
+
+/******************** Bit definition for ADC_SQR2 register ********************/
+#define ADC_SQR2_SQ5_Pos (0U)
+#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
+#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */
+#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
+#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
+#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
+#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
+#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ6_Pos (6U)
+#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
+#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */
+#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
+#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
+#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
+#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
+#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
+
+#define ADC_SQR2_SQ7_Pos (12U)
+#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */
+#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
+#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
+#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
+#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
+#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
+
+#define ADC_SQR2_SQ8_Pos (18U)
+#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */
+#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
+#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
+#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
+#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
+#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
+
+#define ADC_SQR2_SQ9_Pos (24U)
+#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */
+#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
+#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
+#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
+#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
+#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
+
+/******************** Bit definition for ADC_SQR3 register ********************/
+#define ADC_SQR3_SQ10_Pos (0U)
+#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
+#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */
+#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
+#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
+#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
+#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
+#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ11_Pos (6U)
+#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
+#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */
+#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
+#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
+#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
+#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
+#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
+
+#define ADC_SQR3_SQ12_Pos (12U)
+#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
+#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */
+#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
+#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
+#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
+#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
+#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
+
+#define ADC_SQR3_SQ13_Pos (18U)
+#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
+#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */
+#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
+#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
+#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
+#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
+#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
+
+#define ADC_SQR3_SQ14_Pos (24U)
+#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
+#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */
+#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
+#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
+#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
+#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
+#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
+
+/******************** Bit definition for ADC_SQR4 register ********************/
+#define ADC_SQR4_SQ15_Pos (0U)
+#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
+#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */
+#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
+#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
+#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
+#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
+#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR4_SQ16_Pos (6U)
+#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
+#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */
+#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
+#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
+#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
+#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
+#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_RDATA_Pos (0U)
+#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */
+#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */
+
+/******************** Bit definition for ADC_PW register ********************/
+#define ADC4_PW_AUTOFF_Pos (0U)
+#define ADC4_PW_AUTOFF_Msk (0x1UL << ADC4_PW_AUTOFF_Pos) /*!< 0x00000001 */
+#define ADC4_PW_AUTOFF ADC4_PW_AUTOFF_Msk /*!< ADC Auto-Off mode */
+#define ADC4_PW_DPD_Pos (1U)
+#define ADC4_PW_DPD_Msk (0x1UL << ADC4_PW_DPD_Pos) /*!< 0x00000002 */
+#define ADC4_PW_DPD ADC4_PW_DPD_Msk /*!< ADC Deep Power mode */
+#define ADC4_PW_VREFPROT_Pos (2U)
+#define ADC4_PW_VREFPROT_Msk (0x1UL << ADC4_PW_VREFPROT_Pos) /*!< 0x00000004 */
+#define ADC4_PW_VREFPROT ADC4_PW_VREFPROT_Msk /*!< ADC Vref protection */
+#define ADC4_PW_VREFSECSMP_Pos (3U)
+#define ADC4_PW_VREFSECSMP_Msk (0x1UL << ADC4_PW_VREFSECSMP_Pos) /*!< 0x00000008 */
+#define ADC4_PW_VREFSECSMP ADC4_PW_VREFSECSMP_Msk /*!< ADC Vref Second Sample */
+
+
+/******************** Bit definition for ADC_JSQR register ********************/
+#define ADC_JSQR_JL_Pos (0U)
+#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */
+#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
+#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
+
+#define ADC_JSQR_JEXTSEL_Pos (2U)
+#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */
+#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */
+#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
+#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
+#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
+#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
+#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */
+
+#define ADC_JSQR_JEXTEN_Pos (7U)
+#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */
+#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */
+#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
+#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */
+
+#define ADC_JSQR_JSQ1_Pos (9U)
+#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */
+#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
+#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
+#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
+#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
+#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */
+
+#define ADC_JSQR_JSQ2_Pos (15U)
+#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */
+#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
+#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
+#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
+#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
+#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */
+
+#define ADC_JSQR_JSQ3_Pos (21U)
+#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */
+#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
+#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
+#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
+#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
+#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */
+
+#define ADC_JSQR_JSQ4_Pos (27U)
+#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */
+#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
+#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
+#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
+#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
+#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for ADC_OFR1 register ********************/
+#define ADC_OFR1_OFFSET1_Pos (0U)
+#define ADC_OFR1_OFFSET1_Msk (0x00FFFFFFUL << ADC_OFR1_OFFSET1_Pos)/*!< 0x00FFFFFF */
+#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
+#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
+#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
+#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
+#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
+#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
+#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
+#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
+#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
+#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
+#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
+#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
+#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
+#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */
+#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */
+#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */
+#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */
+#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */
+#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */
+#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */
+#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */
+#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */
+#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */
+#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */
+#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */
+
+#define ADC_OFR1_OFFSETPOS_Pos (24U)
+#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */
+#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */
+#define ADC_OFR1_USAT_Pos (25U)
+#define ADC_OFR1_USAT_Msk (0x1UL << ADC_OFR1_USAT_Pos) /*!< 0x02000000 */
+#define ADC_OFR1_USAT ADC_OFR1_USAT_Msk /*!< ADC offset number 1 saturation enable */
+
+#define ADC_OFR1_SSAT_Pos (26U)
+#define ADC_OFR1_SSAT_Msk (0x1UL << ADC_OFR1_SSAT_Pos) /*!< 0x80000000 */
+#define ADC_OFR1_SSAT ADC_OFR1_SSAT_Msk /*!< ADC Signed saturation Enable */
+
+
+#define ADC_OFR1_OFFSET1_CH_Pos (27U)
+#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
+#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */
+#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
+#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
+#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
+#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
+#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
+
+
+/******************** Bit definition for ADC_OFR2 register ********************/
+#define ADC_OFR2_OFFSET2_Pos (0U)
+#define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */
+#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
+#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
+#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
+#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
+#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
+#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
+#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
+#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
+#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
+#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
+#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
+#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
+#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
+#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */
+#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */
+#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */
+#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */
+#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */
+#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */
+#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */
+#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */
+#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */
+#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */
+#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */
+#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */
+
+#define ADC_OFR2_OFFSETPOS_Pos (24U)
+#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */
+#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 1 positive */
+#define ADC_OFR2_USAT_Pos (25U)
+#define ADC_OFR2_USAT_Msk (0x1UL << ADC_OFR2_USAT_Pos) /*!< 0x02000000 */
+#define ADC_OFR2_USAT ADC_OFR2_USAT_Msk /*!< ADC offset number 1 saturation enable */
+
+#define ADC_OFR2_SSAT_Pos (26U)
+#define ADC_OFR2_SSAT_Msk (0x1UL << ADC_OFR2_SSAT_Pos) /*!< 0x80000000 */
+#define ADC_OFR2_SSAT ADC_OFR2_SSAT_Msk /*!< ADC Signed saturation Enable */
+
+
+
+#define ADC_OFR2_OFFSET2_CH_Pos (27U)
+#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
+#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */
+#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
+#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
+#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
+#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
+#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for ADC_OFR3 register ********************/
+#define ADC_OFR3_OFFSET3_Pos (0U)
+#define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */
+#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
+#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
+#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
+#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
+#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
+#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
+#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
+#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
+#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
+#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
+#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
+#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
+#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
+#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */
+#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */
+#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */
+#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */
+#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */
+#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */
+#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */
+#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */
+#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */
+#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */
+#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */
+#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */
+
+#define ADC_OFR3_OFFSETPOS_Pos (24U)
+#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */
+#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 1 positive */
+#define ADC_OFR3_USAT_Pos (25U)
+#define ADC_OFR3_USAT_Msk (0x1UL << ADC_OFR3_USAT_Pos) /*!< 0x02000000 */
+#define ADC_OFR3_USAT ADC_OFR3_USAT_Msk /*!< ADC offset number 1 saturation enable */
+
+#define ADC_OFR3_SSAT_Pos (26U)
+#define ADC_OFR3_SSAT_Msk (0x1UL << ADC_OFR3_SSAT_Pos) /*!< 0x80000000 */
+#define ADC_OFR3_SSAT ADC_OFR3_SSAT_Msk /*!< ADC Signed saturation Enable */
+
+
+#define ADC_OFR3_OFFSET3_CH_Pos (27U)
+#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
+#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */
+#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
+#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
+#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
+#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
+#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
+
+
+/******************** Bit definition for ADC_OFR4 register ********************/
+#define ADC_OFR4_OFFSET4_Pos (0U)
+#define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */
+#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
+#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
+#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
+#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
+#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
+#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
+#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
+#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
+#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
+#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
+#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
+#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
+#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
+#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */
+#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */
+#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */
+#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */
+#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */
+#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */
+#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */
+#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */
+#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */
+#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */
+#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */
+#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */
+
+#define ADC_OFR4_OFFSETPOS_Pos (24U)
+#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */
+#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 1 positive */
+#define ADC_OFR4_USAT_Pos (25U)
+#define ADC_OFR4_USAT_Msk (0x1UL << ADC_OFR4_USAT_Pos) /*!< 0x02000000 */
+#define ADC_OFR4_USAT ADC_OFR4_USAT_Msk /*!< ADC offset number 1 saturation enable */
+
+#define ADC_OFR4_SSAT_Pos (26U)
+#define ADC_OFR4_SSAT_Msk (0x1UL << ADC_OFR4_SSAT_Pos) /*!< 0x80000000 */
+#define ADC_OFR4_SSAT ADC_OFR4_SSAT_Msk /*!< ADC Signed saturation Enable */
+
+#define ADC_OFR4_OFFSET4_CH_Pos (27U)
+#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
+#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */
+#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
+#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
+#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
+#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
+#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for ADC_GCOMP register ********************/
+#define ADC_GCOMP_GCOMPCOEFF_Pos (0U)
+#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)/*!< 0x00003FFF */
+#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Injected DATA */
+#define ADC_GCOMP_GCOMP_Pos (31U)
+#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x00003FFF */
+#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< ADC Injected DATA */
+
+
+/******************** Bit definition for ADC_JDR1 register ********************/
+#define ADC_JDR1_JDATA_Pos (0U)
+#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */
+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */
+#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
+#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
+#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
+#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
+#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
+#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
+#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
+#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
+#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
+#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
+#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
+#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
+#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
+#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
+#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
+#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
+#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */
+#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */
+#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */
+#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */
+#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */
+#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */
+#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */
+#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */
+#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */
+#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */
+#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */
+#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */
+#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */
+#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */
+#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */
+#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for ADC_JDR2 register ********************/
+#define ADC_JDR2_JDATA_Pos (0U)
+#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */
+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */
+#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
+#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
+#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
+#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
+#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
+#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
+#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
+#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
+#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
+#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
+#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
+#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
+#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
+#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
+#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
+#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
+#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */
+#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */
+#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */
+#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */
+#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */
+#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */
+#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */
+#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */
+#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */
+#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */
+#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */
+#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */
+#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */
+#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */
+#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */
+#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for ADC_JDR3 register ********************/
+#define ADC_JDR3_JDATA_Pos (0U)
+#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */
+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */
+#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
+#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
+#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
+#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
+#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
+#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
+#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
+#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
+#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
+#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
+#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
+#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
+#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
+#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
+#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
+#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
+#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */
+#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */
+#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */
+#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */
+#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */
+#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */
+#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */
+#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */
+#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */
+#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */
+#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */
+#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */
+#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */
+#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */
+#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */
+#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for ADC_JDR4 register ********************/
+#define ADC_JDR4_JDATA_Pos (0U)
+#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */
+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */
+#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
+#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
+#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
+#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
+#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
+#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
+#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
+#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
+#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
+#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
+#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
+#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
+#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
+#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
+#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
+#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
+#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */
+#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */
+#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */
+#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */
+#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */
+#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */
+#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */
+#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */
+#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */
+#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */
+#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */
+#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */
+#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */
+#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */
+#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */
+#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for ADC_AWD2CR register ********************/
+#define ADC_AWD2CR_AWD2CH_Pos (0U)
+#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00FFFFFF */
+#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */
+#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
+#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
+#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
+#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
+#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
+#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
+#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
+#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
+#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
+#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
+#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
+#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
+#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
+#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
+#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
+#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
+#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
+#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
+#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
+#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */
+#define ADC_AWD2CR_AWD2CH_20 (0x100000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00100000 */
+#define ADC_AWD2CR_AWD2CH_21 (0x200000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00200000 */
+#define ADC_AWD2CR_AWD2CH_22 (0x400000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00400000 */
+#define ADC_AWD2CR_AWD2CH_23 (0x800000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00800000 */
+
+
+/******************** Bit definition for ADC_AWD1TR register *******************/
+#define ADC_AWD1TR_LT1_Pos (0U)
+#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */
+#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
+#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */
+#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */
+#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */
+#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */
+#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */
+#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */
+#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */
+#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */
+#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */
+#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */
+#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */
+#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */
+
+#define ADC_AWD1TR_HT1_Pos (16U)
+#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */
+#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
+#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */
+#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */
+#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */
+#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */
+#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */
+#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */
+#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */
+#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */
+#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */
+#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */
+#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */
+#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */
+
+/******************** Bit definition for ADC_AWDTR2 register *******************/
+#define ADC_AWD2TR_LT2_Pos (0U)
+#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */
+#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
+#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */
+#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */
+#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */
+#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */
+#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */
+#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */
+#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */
+#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */
+#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */
+#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */
+#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */
+#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */
+
+#define ADC_AWD2TR_HT2_Pos (16U)
+#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */
+#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
+#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */
+#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */
+#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */
+#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */
+#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */
+#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */
+#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */
+#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */
+#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */
+#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */
+#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */
+#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */
+
+/******************** Bit definition for ADC_CHSELR register ****************/
+#define ADC_CHSELR_CHSEL_Pos (0U)
+#define ADC_CHSELR_CHSEL_Msk (0xFFFFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
+#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */
+
+#define ADC_CHSELR_CHSEL0_Pos (0U)
+#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
+#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL1_Pos (1U)
+#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
+#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL2_Pos (2U)
+#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
+#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL3_Pos (3U)
+#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
+#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL4_Pos (4U)
+#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
+#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL5_Pos (5U)
+#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
+#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL6_Pos (6U)
+#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
+#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL7_Pos (7U)
+#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
+#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL8_Pos (8U)
+#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
+#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL9_Pos (9U)
+#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
+#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL10_Pos (10U)
+#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
+#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL11_Pos (11U)
+#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
+#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL12_Pos (12U)
+#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
+#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL13_Pos (13U)
+#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
+#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL14_Pos (14U)
+#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
+#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL15_Pos (15U)
+#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
+#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL16_Pos (16U)
+#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */
+#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL17_Pos (17U)
+#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
+#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL18_Pos (18U)
+#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
+#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL19_Pos (19U)
+#define ADC_CHSELR_CHSEL19_Msk (0x1UL << ADC_CHSELR_CHSEL19_Pos) /*!< 0x00040000 */
+#define ADC_CHSELR_CHSEL19 ADC_CHSELR_CHSEL19_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL20_Pos (20U)
+#define ADC_CHSELR_CHSEL20_Msk (0x1UL << ADC_CHSELR_CHSEL20_Pos) /*!< 0x00040000 */
+#define ADC_CHSELR_CHSEL20 ADC_CHSELR_CHSEL20_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL21_Pos (21U)
+#define ADC_CHSELR_CHSEL21_Msk (0x1UL << ADC_CHSELR_CHSEL21_Pos) /*!< 0x00040000 */
+#define ADC_CHSELR_CHSEL21 ADC_CHSELR_CHSEL21_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL22_Pos (22U)
+#define ADC_CHSELR_CHSEL22_Msk (0x1UL << ADC_CHSELR_CHSEL22_Pos) /*!< 0x00040000 */
+#define ADC_CHSELR_CHSEL22 ADC_CHSELR_CHSEL22_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL23_Pos (23U)
+#define ADC_CHSELR_CHSEL23_Msk (0x1UL << ADC_CHSELR_CHSEL23_Pos) /*!< 0x00040000 */
+#define ADC_CHSELR_CHSEL23 ADC_CHSELR_CHSEL23_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */
+
+#define ADC_CHSELR_SQ_ALL_Pos (0U)
+#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */
+#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */
+
+#define ADC_CHSELR_SQ1_Pos (0U)
+#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */
+#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */
+#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */
+#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */
+#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */
+#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */
+
+#define ADC_CHSELR_SQ2_Pos (4U)
+#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */
+#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */
+#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */
+#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */
+#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */
+#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */
+
+#define ADC_CHSELR_SQ3_Pos (8U)
+#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */
+#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */
+#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */
+#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */
+#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */
+#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */
+
+#define ADC_CHSELR_SQ4_Pos (12U)
+#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */
+#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */
+#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */
+#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */
+#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */
+#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */
+
+#define ADC_CHSELR_SQ5_Pos (16U)
+#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */
+#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */
+#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */
+#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */
+#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */
+#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */
+
+#define ADC_CHSELR_SQ6_Pos (20U)
+#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */
+#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */
+#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */
+#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */
+#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */
+#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */
+
+#define ADC_CHSELR_SQ7_Pos (24U)
+#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */
+#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */
+#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */
+#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */
+#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */
+#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */
+
+#define ADC_CHSELR_SQ8_Pos (28U)
+#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */
+#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */
+#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */
+#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */
+#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */
+#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */
+
+
+/******************** Bit definition for ADC_AWD3TR register *******************/
+#define ADC_AWD3TR_LT3_Pos (0U)
+#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */
+#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
+#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */
+#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */
+#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */
+#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */
+#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */
+#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */
+#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */
+#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */
+#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */
+#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */
+#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */
+#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */
+
+#define ADC_AWD3TR_HT3_Pos (16U)
+#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */
+#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
+#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */
+#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */
+#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */
+#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */
+#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */
+#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */
+#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */
+#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */
+#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */
+#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */
+#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */
+#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */
+
+
+/******************** Bit definition for ADC_AWD3CR register ********************/
+#define ADC_AWD3CR_AWD3CH_Pos (0U)
+#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00FFFFFF */
+#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */
+#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
+#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
+#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
+#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
+#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
+#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
+#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
+#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
+#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
+#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
+#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
+#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
+#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
+#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
+#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
+#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
+#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
+#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
+#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
+#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */
+#define ADC_AWD3CR_AWD2CH_20 (0x100000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00100000 */
+#define ADC_AWD3CR_AWD2CH_21 (0x200000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00200000 */
+#define ADC_AWD3CR_AWD2CH_22 (0x400000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00400000 */
+#define ADC_AWD3CR_AWD2CH_23 (0x800000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00800000 */
+
+/******************** Bit definition for ADC_DIFSEL register ********************/
+#define ADC_DIFSEL_DIFSEL_Pos (0U)
+#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */
+#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */
+#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
+#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
+#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
+#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
+#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
+#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
+#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
+#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
+#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
+#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
+#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
+#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
+#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
+#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
+#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
+#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
+#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
+#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
+#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
+#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */
+
+/******************** Bit definition for ADC_CALFACT register ********************/
+#define ADC_CALFACT_I_APB_ADDR_Pos (0U)
+#define ADC_CALFACT_I_APB_ADDR_Msk (0xFFUL << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x000000FF */
+#define ADC_CALFACT_I_APB_ADDR ADC_CALFACT_I_APB_ADDR_Msk /*!< ADC calibration factors in single-ended mode */
+#define ADC_CALFACT_I_APB_ADDR_0 (0x001U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000001 */
+#define ADC_CALFACT_I_APB_ADDR_1 (0x002U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000002 */
+#define ADC_CALFACT_I_APB_ADDR_2 (0x004U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000004 */
+#define ADC_CALFACT_I_APB_ADDR_3 (0x008U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000008 */
+#define ADC_CALFACT_I_APB_ADDR_4 (0x010U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000010 */
+#define ADC_CALFACT_I_APB_ADDR_5 (0x020U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000020 */
+#define ADC_CALFACT_I_APB_ADDR_6 (0x040U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000040 */
+#define ADC_CALFACT_I_APB_ADDR_7 (0x080U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000080 */
+
+#define ADC_CALFACT_I_APB_DATA_Pos (08U)
+#define ADC_CALFACT_I_APB_DATA_Msk (0xFFUL << ADC_CALFACT_I_APB_DATA_Pos) /*!< 0x0000FF00 */
+#define ADC_CALFACT_I_APB_DATA ADC_CALFACT_I_APB_DATA_Msk /*!< ADC calibration factors in differential mode */
+#define ADC_CALFACT_APB_DATA_0 (0x001U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000100 */
+#define ADC_CALFACT_APB_DATA_1 (0x002U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000200 */
+#define ADC_CALFACT_APB_DATA_2 (0x004U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000400 */
+#define ADC_CALFACT_APB_DATA_3 (0x008U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000800 */
+#define ADC_CALFACT_APB_DATA_4 (0x010U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00001000 */
+#define ADC_CALFACT_APB_DATA_5 (0x020U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00002000 */
+#define ADC_CALFACT_APB_DATA_6 (0x040U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00004000 */
+#define ADC_CALFACT_APB_DATA_7 (0x080U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00008000 */
+
+#define ADC_CALFACT_VALIDITY_Pos (16U)
+#define ADC_CALFACT_VALIDITY_Msk (0x1UL << ADC_CALFACT_VALIDITY_Pos) /*!< 0x00010000 */
+#define ADC_CALFACT_VALIDITY ADC_CALFACT_VALIDITY_Msk /*!< ADC calibration factors in differential mode */
+#define ADC_CALFACT_LATCH_COEF_Pos (24U)
+#define ADC_CALFACT_LATCH_COEF_Msk (0x1UL << ADC_CALFACT_LATCH_COEF_Pos) /*!< 0x01000000 */
+#define ADC_CALFACT_LATCH_COEF ADC_CALFACT_LATCH_COEF_Msk /*!< ADC calibration factors in differential mode */
+#define ADC_CALFACT_CAPTURE_COEF_Pos (25U)
+#define ADC_CALFACT_CAPTURE_COEF_Msk (0x1UL << ADC_CALFACT_CAPTURE_COEF_Pos) /*!< 0x01000000 */
+#define ADC_CALFACT_CAPTURE_COEF ADC_CALFACT_CAPTURE_COEF_Msk /*!< ADC calibration factors in differential mode */
+
+
+#define ADC4_CALFACT_CALFACT_Pos (0U)
+#define ADC4_CALFACT_CALFACT_Msk (0x7FUL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x0000007F */
+#define ADC4_CALFACT_CALFACT ADC4_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */
+#define ADC4_CALFACT_CALFACT_0 (0x01UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000001 */
+#define ADC4_CALFACT_CALFACT_1 (0x02UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000002 */
+#define ADC4_CALFACT_CALFACT_2 (0x04UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000004 */
+#define ADC4_CALFACT_CALFACT_3 (0x08UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000008 */
+#define ADC4_CALFACT_CALFACT_4 (0x10UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000010 */
+#define ADC4_CALFACT_CALFACT_5 (0x20UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000020 */
+#define ADC4_CALFACT_CALFACT_6 (0x40UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000040 */
+
+
+
+/******************** Bit definition for ADC_CALFACT2 register ********************/
+#define ADC_CALFACT2_CALFACT_Pos (0U)
+#define ADC_CALFACT2_CALFACT_Msk (0xFFFFFFFFUL << ADC_CALFACT2_CALFACT_Pos) /*!< 0xFFFFFFFF */
+#define ADC_CALFACT2_CALFACT ADC_CALFACT2_CALFACT_Msk /*!< ADC Linearity calibration factors */
+#define ADC_CALFACT2_CALFACT_0 (0x00000001UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000001 */
+#define ADC_CALFACT2_CALFACT_1 (0x00000002UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000002 */
+#define ADC_CALFACT2_CALFACT_2 (0x00000004UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000004 */
+#define ADC_CALFACT2_CALFACT_3 (0x00000008UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000008 */
+#define ADC_CALFACT2_CALFACT_4 (0x00000010UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000010 */
+#define ADC_CALFACT2_CALFACT_5 (0x00000020UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000020 */
+#define ADC_CALFACT2_CALFACT_6 (0x00000040UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000040 */
+#define ADC_CALFACT2_CALFACT_7 (0x00000080UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000080 */
+#define ADC_CALFACT2_CALFACT_8 (0x00000100UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000100 */
+#define ADC_CALFACT2_CALFACT_9 (0x00000200UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000200 */
+#define ADC_CALFACT2_CALFACT_10 (0x00000400UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000400 */
+#define ADC_CALFACT2_CALFACT_11 (0x00000800UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000800 */
+#define ADC_CALFACT2_CALFACT_12 (0x00001000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00001000 */
+#define ADC_CALFACT2_CALFACT_13 (0x00002000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00002000 */
+#define ADC_CALFACT2_CALFACT_14 (0x00004000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00004000 */
+#define ADC_CALFACT2_CALFACT_15 (0x00008000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00008000 */
+#define ADC_CALFACT2_CALFACT_16 (0x00010000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00010000 */
+#define ADC_CALFACT2_CALFACT_17 (0x00020000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00020000 */
+#define ADC_CALFACT2_CALFACT_18 (0x00040000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00040000 */
+#define ADC_CALFACT2_CALFACT_19 (0x00080000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00080000 */
+#define ADC_CALFACT2_CALFACT_20 (0x00100000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00100000 */
+#define ADC_CALFACT2_CALFACT_21 (0x00200000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00200000 */
+#define ADC_CALFACT2_CALFACT_22 (0x00400000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00400000 */
+#define ADC_CALFACT2_CALFACT_23 (0x00800000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00800000 */
+#define ADC_CALFACT2_CALFACT_24 (0x01000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x01000000 */
+#define ADC_CALFACT2_CALFACT_25 (0x02000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x02000000 */
+#define ADC_CALFACT2_CALFACT_26 (0x04000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x04000000 */
+#define ADC_CALFACT2_CALFACT_27 (0x08000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x08000000 */
+#define ADC_CALFACT2_CALFACT_28 (0x10000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x10000000 */
+#define ADC_CALFACT2_CALFACT_29 (0x20000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x20000000 */
+#define ADC_CALFACT2_CALFACT_30 (0x40000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x40000000 */
+#define ADC_CALFACT2_CALFACT_31 (0x80000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x80000000 */
+
+
+/******************** Bit definition for ADC_OR register ********************/
+#define ADC_OR_CHN0SEL_Pos (0U)
+#define ADC_OR_CHN0SEL_Msk (0x1UL << ADC_OR_CHN0SEL_Pos) /*!< 0x00000001 */
+#define ADC_OR_CHN0SEL ADC_OR_CHN0SEL_Msk /*!< ADC Channel 0 selection */
+
+
+/************************* ADC Common registers *****************************/
+/******************** Bit definition for ADC_CCR register ********************/
+
+
+#define ADC_CCR_PRESC_Pos (18U)
+#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
+#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */
+#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
+#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
+#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
+#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
+
+#define ADC_CCR_VREFEN_Pos (22U)
+#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */
+#define ADC_CCR_VSENSEEN_Pos (23U)
+#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */
+#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */
+#define ADC_CCR_VBATEN_Pos (24U)
+#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
+#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */
+#define ADC_CCR_LFMEN_Pos (25U)
+#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
+#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode Enable, specific ADC4*/
+#define ADC_CCR_VDDCOREN_Pos (26U)
+#define ADC_CCR_VDDCOREN_Msk (0x1UL << ADC_CCR_VDDCOREN_Pos) /*!< 0x04000000 */
+#define ADC_CCR_VDDCOREN ADC_CCR_VDDCOREN_Msk /*!< VDDCode enable */
+
+
+/******************************************************************************/
+/* */
+/* CORDIC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CORDIC_CSR register *****************/
+#define CORDIC_CSR_FUNC_Pos (0U)
+#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */
+#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */
+#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */
+#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */
+#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */
+#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */
+#define CORDIC_CSR_PRECISION_Pos (4U)
+#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */
+#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */
+#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */
+#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */
+#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */
+#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */
+#define CORDIC_CSR_SCALE_Pos (8U)
+#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */
+#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */
+#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */
+#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */
+#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */
+#define CORDIC_CSR_IEN_Pos (16U)
+#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */
+#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */
+#define CORDIC_CSR_DMAREN_Pos (17U)
+#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */
+#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */
+#define CORDIC_CSR_DMAWEN_Pos (18U)
+#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */
+#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */
+#define CORDIC_CSR_NRES_Pos (19U)
+#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */
+#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */
+#define CORDIC_CSR_NARGS_Pos (20U)
+#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */
+#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */
+#define CORDIC_CSR_RESSIZE_Pos (21U)
+#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */
+#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */
+#define CORDIC_CSR_ARGSIZE_Pos (22U)
+#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */
+#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */
+#define CORDIC_CSR_RRDY_Pos (31U)
+#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */
+#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */
+
+/******************* Bit definition for CORDIC_WDATA register ***************/
+#define CORDIC_WDATA_ARG_Pos (0U)
+#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */
+#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */
+
+/******************* Bit definition for CORDIC_RDATA register ***************/
+#define CORDIC_RDATA_RES_Pos (0U)
+#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */
+#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */
+
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR_Pos (0U)
+#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos (3U)
+#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos (5U)
+#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
+#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos (7U)
+#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
+#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
+
+/******************* Bit definition for CRC_INIT register *******************/
+#define CRC_INIT_INIT_Pos (0U)
+#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
+
+/******************* Bit definition for CRC_POL register ********************/
+#define CRC_POL_POL_Pos (0U)
+#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
+#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
+
+
+/******************************************************************************/
+/* */
+/* CRS Clock Recovery System */
+/******************************************************************************/
+/******************* Bit definition for CRS_CR register *********************/
+#define CRS_CR_SYNCOKIE_Pos (0U)
+#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
+#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */
+#define CRS_CR_SYNCWARNIE_Pos (1U)
+#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
+#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */
+#define CRS_CR_ERRIE_Pos (2U)
+#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
+#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */
+#define CRS_CR_ESYNCIE_Pos (3U)
+#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
+#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */
+#define CRS_CR_CEN_Pos (5U)
+#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */
+#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */
+#define CRS_CR_AUTOTRIMEN_Pos (6U)
+#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
+#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */
+#define CRS_CR_SWSYNC_Pos (7U)
+#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
+#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
+#define CRS_CR_TRIM_Pos (8U)
+#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
+#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
+
+/******************* Bit definition for CRS_CFGR register *********************/
+#define CRS_CFGR_RELOAD_Pos (0U)
+#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
+#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */
+#define CRS_CFGR_FELIM_Pos (16U)
+#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
+#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */
+#define CRS_CFGR_SYNCDIV_Pos (24U)
+#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
+#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */
+#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
+#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
+#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
+#define CRS_CFGR_SYNCSRC_Pos (28U)
+#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
+#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */
+#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
+#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
+#define CRS_CFGR_SYNCPOL_Pos (31U)
+#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
+#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */
+
+/******************* Bit definition for CRS_ISR register *********************/
+#define CRS_ISR_SYNCOKF_Pos (0U)
+#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
+#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */
+#define CRS_ISR_SYNCWARNF_Pos (1U)
+#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
+#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */
+#define CRS_ISR_ERRF_Pos (2U)
+#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
+#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */
+#define CRS_ISR_ESYNCF_Pos (3U)
+#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
+#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */
+#define CRS_ISR_SYNCERR_Pos (8U)
+#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
+#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */
+#define CRS_ISR_SYNCMISS_Pos (9U)
+#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
+#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */
+#define CRS_ISR_TRIMOVF_Pos (10U)
+#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
+#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */
+#define CRS_ISR_FEDIR_Pos (15U)
+#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
+#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */
+#define CRS_ISR_FECAP_Pos (16U)
+#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
+#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */
+
+/******************* Bit definition for CRS_ICR register *********************/
+#define CRS_ICR_SYNCOKC_Pos (0U)
+#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
+#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */
+#define CRS_ICR_SYNCWARNC_Pos (1U)
+#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
+#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */
+#define CRS_ICR_ERRC_Pos (2U)
+#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
+#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */
+#define CRS_ICR_ESYNCC_Pos (3U)
+#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
+#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */
+
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN_Pos (2U)
+#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
+#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
+#define RNG_CR_IE_Pos (3U)
+#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
+#define RNG_CR_IE RNG_CR_IE_Msk
+#define RNG_CR_CED_Pos (5U)
+#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */
+#define RNG_CR_CED RNG_CR_CED_Msk
+#define RNG_CR_ARDIS_Pos (7U)
+#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos)
+#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk
+#define RNG_CR_RNG_CONFIG3_Pos (8U)
+#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos)
+#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk
+#define RNG_CR_NISTC_Pos (12U)
+#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos)
+#define RNG_CR_NISTC RNG_CR_NISTC_Msk
+#define RNG_CR_RNG_CONFIG2_Pos (13U)
+#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos)
+#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk
+#define RNG_CR_CLKDIV_Pos (16U)
+#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos)
+#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk
+#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */
+#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */
+#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */
+#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */
+#define RNG_CR_RNG_CONFIG1_Pos (20U)
+#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos)
+#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk
+#define RNG_CR_CONDRST_Pos (30U)
+#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos)
+#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk
+#define RNG_CR_CONFIGLOCK_Pos (31U)
+#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos)
+#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY_Pos (0U)
+#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
+#define RNG_SR_DRDY RNG_SR_DRDY_Msk
+#define RNG_SR_CECS_Pos (1U)
+#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */
+#define RNG_SR_CECS RNG_SR_CECS_Msk
+#define RNG_SR_SECS_Pos (2U)
+#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */
+#define RNG_SR_SECS RNG_SR_SECS_Msk
+#define RNG_SR_CEIS_Pos (5U)
+#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
+#define RNG_SR_CEIS RNG_SR_CEIS_Msk
+#define RNG_SR_SEIS_Pos (6U)
+#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
+#define RNG_SR_SEIS RNG_SR_SEIS_Msk
+
+/******************** Bits definition for RNG_HTCR register *******************/
+#define RNG_HTCR_HTCFG_Pos (0U)
+#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */
+#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */
+
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1_Pos (0U)
+#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */
+#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/
+#define DAC_CR_CEN1_Pos (14U)
+#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
+#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/
+#define DAC_CR_EN2_Pos (16U)
+#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */
+#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/
+#define DAC_CR_CEN2_Pos (30U)
+#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
+#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
+#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1U)
+
+#define FLASH_PAGE_SIZE 0x2000U /* 8 KB */
+
+#define FLASH_PAGE_NB (FLASH_BANK_SIZE / FLASH_PAGE_SIZE)
+
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */
+#define FLASH_ACR_LATENCY_0WS (0x00000000U)
+#define FLASH_ACR_LATENCY_1WS (0x00000001U)
+#define FLASH_ACR_LATENCY_2WS (0x00000002U)
+#define FLASH_ACR_LATENCY_3WS (0x00000003U)
+#define FLASH_ACR_LATENCY_4WS (0x00000004U)
+#define FLASH_ACR_LATENCY_5WS (0x00000005U)
+#define FLASH_ACR_LATENCY_6WS (0x00000006U)
+#define FLASH_ACR_LATENCY_7WS (0x00000007U)
+#define FLASH_ACR_LATENCY_8WS (0x00000008U)
+#define FLASH_ACR_LATENCY_9WS (0x00000009U)
+#define FLASH_ACR_LATENCY_10WS (0x0000000AU)
+#define FLASH_ACR_LATENCY_11WS (0x0000000BU)
+#define FLASH_ACR_LATENCY_12WS (0x0000000CU)
+#define FLASH_ACR_LATENCY_13WS (0x0000000DU)
+#define FLASH_ACR_LATENCY_14WS (0x0000000EU)
+#define FLASH_ACR_LATENCY_15WS (0x0000000FU)
+#define FLASH_ACR_PRFTEN_Pos (8U)
+#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */
+#define FLASH_ACR_LPM_Pos (11U)
+#define FLASH_ACR_LPM_Msk (0x1UL << FLASH_ACR_LPM_Pos) /*!< 0x00000800 */
+#define FLASH_ACR_LPM FLASH_ACR_LPM_Msk /*!< Low-Power read mode */
+#define FLASH_ACR_PDREQ1_Pos (12U)
+#define FLASH_ACR_PDREQ1_Msk (0x1UL << FLASH_ACR_PDREQ1_Pos) /*!< 0x00001000 */
+#define FLASH_ACR_PDREQ1 FLASH_ACR_PDREQ1_Msk /*!< Bank 1 power-down mode request */
+#define FLASH_ACR_PDREQ2_Pos (13U)
+#define FLASH_ACR_PDREQ2_Msk (0x1UL << FLASH_ACR_PDREQ2_Pos) /*!< 0x00002000 */
+#define FLASH_ACR_PDREQ2 FLASH_ACR_PDREQ2_Msk /*!< Bank 2 power-down mode request */
+#define FLASH_ACR_SLEEP_PD_Pos (14U)
+#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */
+#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power-down mode during sleep */
+
+/****************** Bits definition for FLASH_NSSR register *****************/
+#define FLASH_NSSR_EOP_Pos (0U)
+#define FLASH_NSSR_EOP_Msk (0x1UL << FLASH_NSSR_EOP_Pos) /*!< 0x00000001 */
+#define FLASH_NSSR_EOP FLASH_NSSR_EOP_Msk /*!< Non-secure end of operation */
+#define FLASH_NSSR_OPERR_Pos (1U)
+#define FLASH_NSSR_OPERR_Msk (0x1UL << FLASH_NSSR_OPERR_Pos) /*!< 0x00000002 */
+#define FLASH_NSSR_OPERR FLASH_NSSR_OPERR_Msk /*!< Non-secure operation error */
+#define FLASH_NSSR_PROGERR_Pos (3U)
+#define FLASH_NSSR_PROGERR_Msk (0x1UL << FLASH_NSSR_PROGERR_Pos) /*!< 0x00000008 */
+#define FLASH_NSSR_PROGERR FLASH_NSSR_PROGERR_Msk /*!< Non-secure programming error */
+#define FLASH_NSSR_WRPERR_Pos (4U)
+#define FLASH_NSSR_WRPERR_Msk (0x1UL << FLASH_NSSR_WRPERR_Pos) /*!< 0x00000010 */
+#define FLASH_NSSR_WRPERR FLASH_NSSR_WRPERR_Msk /*!< Non-secure write protection error */
+#define FLASH_NSSR_PGAERR_Pos (5U)
+#define FLASH_NSSR_PGAERR_Msk (0x1UL << FLASH_NSSR_PGAERR_Pos) /*!< 0x00000020 */
+#define FLASH_NSSR_PGAERR FLASH_NSSR_PGAERR_Msk /*!< Non-secure programming alignment error */
+#define FLASH_NSSR_SIZERR_Pos (6U)
+#define FLASH_NSSR_SIZERR_Msk (0x1UL << FLASH_NSSR_SIZERR_Pos) /*!< 0x00000040 */
+#define FLASH_NSSR_SIZERR FLASH_NSSR_SIZERR_Msk /*!< Non-secure size error */
+#define FLASH_NSSR_PGSERR_Pos (7U)
+#define FLASH_NSSR_PGSERR_Msk (0x1UL << FLASH_NSSR_PGSERR_Pos) /*!< 0x00000080 */
+#define FLASH_NSSR_PGSERR FLASH_NSSR_PGSERR_Msk /*!< Non-secure programming sequence error */
+#define FLASH_NSSR_OPTWERR_Pos (13U)
+#define FLASH_NSSR_OPTWERR_Msk (0x1UL << FLASH_NSSR_OPTWERR_Pos) /*!< 0x00002000 */
+#define FLASH_NSSR_OPTWERR FLASH_NSSR_OPTWERR_Msk /*!< Option write error */
+#define FLASH_NSSR_BSY_Pos (16U)
+#define FLASH_NSSR_BSY_Msk (0x1UL << FLASH_NSSR_BSY_Pos) /*!< 0x00010000 */
+#define FLASH_NSSR_BSY FLASH_NSSR_BSY_Msk /*!< Non-secure busy */
+#define FLASH_NSSR_WDW_Pos (17U)
+#define FLASH_NSSR_WDW_Msk (0x1UL << FLASH_NSSR_WDW_Pos) /*!< 0x00020000 */
+#define FLASH_NSSR_WDW FLASH_NSSR_WDW_Msk /*!< Non-secure wait data to write */
+#define FLASH_NSSR_OEM1LOCK_Pos (18U)
+#define FLASH_NSSR_OEM1LOCK_Msk (0x1UL << FLASH_NSSR_OEM1LOCK_Pos) /*!< 0x00040000 */
+#define FLASH_NSSR_OEM1LOCK FLASH_NSSR_OEM1LOCK_Msk /*!< OEM1 lock */
+#define FLASH_NSSR_OEM2LOCK_Pos (19U)
+#define FLASH_NSSR_OEM2LOCK_Msk (0x1UL << FLASH_NSSR_OEM2LOCK_Pos) /*!< 0x00080000 */
+#define FLASH_NSSR_OEM2LOCK FLASH_NSSR_OEM2LOCK_Msk /*!< OEM2 lock */
+#define FLASH_NSSR_PD1_Pos (20U)
+#define FLASH_NSSR_PD1_Msk (0x1UL << FLASH_NSSR_PD1_Pos) /*!< 0x00100000 */
+#define FLASH_NSSR_PD1 FLASH_NSSR_PD1_Msk /*!< Bank 1 in power-down mode */
+#define FLASH_NSSR_PD2_Pos (21U)
+#define FLASH_NSSR_PD2_Msk (0x1UL << FLASH_NSSR_PD2_Pos) /*!< 0x00200000 */
+#define FLASH_NSSR_PD2 FLASH_NSSR_PD2_Msk /*!< Bank 2 in power-down mode */
+
+/****************** Bits definition for FLASH_SECSR register ****************/
+#define FLASH_SECSR_EOP_Pos (0U)
+#define FLASH_SECSR_EOP_Msk (0x1UL << FLASH_SECSR_EOP_Pos) /*!< 0x00000001 */
+#define FLASH_SECSR_EOP FLASH_SECSR_EOP_Msk /*!< Secure end of operation */
+#define FLASH_SECSR_OPERR_Pos (1U)
+#define FLASH_SECSR_OPERR_Msk (0x1UL << FLASH_SECSR_OPERR_Pos) /*!< 0x00000002 */
+#define FLASH_SECSR_OPERR FLASH_SECSR_OPERR_Msk /*!< Secure operation error */
+#define FLASH_SECSR_PROGERR_Pos (3U)
+#define FLASH_SECSR_PROGERR_Msk (0x1UL << FLASH_SECSR_PROGERR_Pos) /*!< 0x00000008 */
+#define FLASH_SECSR_PROGERR FLASH_SECSR_PROGERR_Msk /*!< Secure programming error */
+#define FLASH_SECSR_WRPERR_Pos (4U)
+#define FLASH_SECSR_WRPERR_Msk (0x1UL << FLASH_SECSR_WRPERR_Pos) /*!< 0x00000010 */
+#define FLASH_SECSR_WRPERR FLASH_SECSR_WRPERR_Msk /*!< Secure write protection error */
+#define FLASH_SECSR_PGAERR_Pos (5U)
+#define FLASH_SECSR_PGAERR_Msk (0x1UL << FLASH_SECSR_PGAERR_Pos) /*!< 0x00000020 */
+#define FLASH_SECSR_PGAERR FLASH_SECSR_PGAERR_Msk /*!< Secure programming alignment error */
+#define FLASH_SECSR_SIZERR_Pos (6U)
+#define FLASH_SECSR_SIZERR_Msk (0x1UL << FLASH_SECSR_SIZERR_Pos) /*!< 0x00000040 */
+#define FLASH_SECSR_SIZERR FLASH_SECSR_SIZERR_Msk /*!< Secure size error */
+#define FLASH_SECSR_PGSERR_Pos (7U)
+#define FLASH_SECSR_PGSERR_Msk (0x1UL << FLASH_SECSR_PGSERR_Pos) /*!< 0x00000080 */
+#define FLASH_SECSR_PGSERR FLASH_SECSR_PGSERR_Msk /*!< Secure programming sequence error */
+#define FLASH_SECSR_BSY_Pos (16U)
+#define FLASH_SECSR_BSY_Msk (0x1UL << FLASH_SECSR_BSY_Pos) /*!< 0x00010000 */
+#define FLASH_SECSR_BSY FLASH_SECSR_BSY_Msk /*!< Secure busy */
+#define FLASH_SECSR_WDW_Pos (17U)
+#define FLASH_SECSR_WDW_Msk (0x1UL << FLASH_SECSR_WDW_Pos) /*!< 0x00020000 */
+#define FLASH_SECSR_WDW FLASH_SECSR_WDW_Msk /*!< Secure wait data to write */
+
+/****************** Bits definition for FLASH_NSCR register *****************/
+#define FLASH_NSCR_PG_Pos (0U)
+#define FLASH_NSCR_PG_Msk (0x1UL << FLASH_NSCR_PG_Pos) /*!< 0x00000001 */
+#define FLASH_NSCR_PG FLASH_NSCR_PG_Msk /*!< Non-secure Programming */
+#define FLASH_NSCR_PER_Pos (1U)
+#define FLASH_NSCR_PER_Msk (0x1UL << FLASH_NSCR_PER_Pos) /*!< 0x00000002 */
+#define FLASH_NSCR_PER FLASH_NSCR_PER_Msk /*!< Non-secure Page Erase */
+#define FLASH_NSCR_MER1_Pos (2U)
+#define FLASH_NSCR_MER1_Msk (0x1UL << FLASH_NSCR_MER1_Pos) /*!< 0x00000004 */
+#define FLASH_NSCR_MER1 FLASH_NSCR_MER1_Msk /*!< Non-secure Bank 1 Mass Erase */
+#define FLASH_NSCR_PNB_Pos (3U)
+#define FLASH_NSCR_PNB_Msk (0x7FUL << FLASH_NSCR_PNB_Pos) /*!< 0x000003F8 */
+#define FLASH_NSCR_PNB FLASH_NSCR_PNB_Msk /*!< Non-secure Page Number selection */
+#define FLASH_NSCR_BKER_Pos (11U)
+#define FLASH_NSCR_BKER_Msk (0x1UL << FLASH_NSCR_BKER_Pos) /*!< 0x00000800 */
+#define FLASH_NSCR_BKER FLASH_NSCR_BKER_Msk /*!< Non-secure Bank Selection for Page Erase */
+#define FLASH_NSCR_BWR_Pos (14U)
+#define FLASH_NSCR_BWR_Msk (0x1UL << FLASH_NSCR_BWR_Pos) /*!< 0x00004000 */
+#define FLASH_NSCR_BWR FLASH_NSCR_BWR_Msk /*!< Non-secure Burst Write Programming mode */
+#define FLASH_NSCR_MER2_Pos (15U)
+#define FLASH_NSCR_MER2_Msk (0x1UL << FLASH_NSCR_MER2_Pos) /*!< 0x00008000 */
+#define FLASH_NSCR_MER2 FLASH_NSCR_MER2_Msk /*!< Non-secure Bank 2 Mass Erase */
+#define FLASH_NSCR_STRT_Pos (16U)
+#define FLASH_NSCR_STRT_Msk (0x1UL << FLASH_NSCR_STRT_Pos) /*!< 0x00010000 */
+#define FLASH_NSCR_STRT FLASH_NSCR_STRT_Msk /*!< Non-secure Start */
+#define FLASH_NSCR_OPTSTRT_Pos (17U)
+#define FLASH_NSCR_OPTSTRT_Msk (0x1UL << FLASH_NSCR_OPTSTRT_Pos) /*!< 0x00020000 */
+#define FLASH_NSCR_OPTSTRT FLASH_NSCR_OPTSTRT_Msk /*!< Option Modification Start */
+#define FLASH_NSCR_EOPIE_Pos (24U)
+#define FLASH_NSCR_EOPIE_Msk (0x1UL << FLASH_NSCR_EOPIE_Pos) /*!< 0x01000000 */
+#define FLASH_NSCR_EOPIE FLASH_NSCR_EOPIE_Msk /*!< Non-secure End of operation interrupt enable */
+#define FLASH_NSCR_ERRIE_Pos (25U)
+#define FLASH_NSCR_ERRIE_Msk (0x1UL << FLASH_NSCR_ERRIE_Pos) /*!< 0x02000000 */
+#define FLASH_NSCR_ERRIE FLASH_NSCR_ERRIE_Msk /*!< Non-secure error interrupt enable */
+#define FLASH_NSCR_OBL_LAUNCH_Pos (27U)
+#define FLASH_NSCR_OBL_LAUNCH_Msk (0x1UL << FLASH_NSCR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
+#define FLASH_NSCR_OBL_LAUNCH FLASH_NSCR_OBL_LAUNCH_Msk /*!< Force the option byte loading */
+#define FLASH_NSCR_OPTLOCK_Pos (30U)
+#define FLASH_NSCR_OPTLOCK_Msk (0x1UL << FLASH_NSCR_OPTLOCK_Pos) /*!< 0x40000000 */
+#define FLASH_NSCR_OPTLOCK FLASH_NSCR_OPTLOCK_Msk /*!< Option Lock */
+#define FLASH_NSCR_LOCK_Pos (31U)
+#define FLASH_NSCR_LOCK_Msk (0x1UL << FLASH_NSCR_LOCK_Pos) /*!< 0x80000000 */
+#define FLASH_NSCR_LOCK FLASH_NSCR_LOCK_Msk /*!< Non-secure Lock */
+
+/****************** Bits definition for FLASH_SECCR register ****************/
+#define FLASH_SECCR_PG_Pos (0U)
+#define FLASH_SECCR_PG_Msk (0x1UL << FLASH_SECCR_PG_Pos) /*!< 0x00000001 */
+#define FLASH_SECCR_PG FLASH_SECCR_PG_Msk /*!< Secure Programming */
+#define FLASH_SECCR_PER_Pos (1U)
+#define FLASH_SECCR_PER_Msk (0x1UL << FLASH_SECCR_PER_Pos) /*!< 0x00000002 */
+#define FLASH_SECCR_PER FLASH_SECCR_PER_Msk /*!< Secure Page Erase */
+#define FLASH_SECCR_MER1_Pos (2U)
+#define FLASH_SECCR_MER1_Msk (0x1UL << FLASH_SECCR_MER1_Pos) /*!< 0x00000004 */
+#define FLASH_SECCR_MER1 FLASH_SECCR_MER1_Msk /*!< Secure Bank 1 Mass Erase */
+#define FLASH_SECCR_PNB_Pos (3U)
+#define FLASH_SECCR_PNB_Msk (0x7FUL << FLASH_SECCR_PNB_Pos) /*!< 0x000003F8 */
+#define FLASH_SECCR_PNB FLASH_SECCR_PNB_Msk /*!< Secure Page Number selection */
+#define FLASH_SECCR_BKER_Pos (11U)
+#define FLASH_SECCR_BKER_Msk (0x1UL << FLASH_SECCR_BKER_Pos) /*!< 0x00000800 */
+#define FLASH_SECCR_BKER FLASH_SECCR_BKER_Msk /*!< Secure Bank Selection for Page Erase */
+#define FLASH_SECCR_BWR_Pos (14U)
+#define FLASH_SECCR_BWR_Msk (0x1UL << FLASH_SECCR_BWR_Pos) /*!< 0x00004000 */
+#define FLASH_SECCR_BWR FLASH_SECCR_BWR_Msk /*!< Secure Burst Write programming mode */
+#define FLASH_SECCR_MER2_Pos (15U)
+#define FLASH_SECCR_MER2_Msk (0x1UL << FLASH_SECCR_MER2_Pos) /*!< 0x00008000 */
+#define FLASH_SECCR_MER2 FLASH_SECCR_MER2_Msk /*!< Secure Bank 2 Mass Erase */
+#define FLASH_SECCR_STRT_Pos (16U)
+#define FLASH_SECCR_STRT_Msk (0x1UL << FLASH_SECCR_STRT_Pos) /*!< 0x00010000 */
+#define FLASH_SECCR_STRT FLASH_SECCR_STRT_Msk /*!< Secure Start */
+#define FLASH_SECCR_EOPIE_Pos (24U)
+#define FLASH_SECCR_EOPIE_Msk (0x1UL << FLASH_SECCR_EOPIE_Pos) /*!< 0x01000000 */
+#define FLASH_SECCR_EOPIE FLASH_SECCR_EOPIE_Msk /*!< Secure end of operation interrupt enable */
+#define FLASH_SECCR_ERRIE_Pos (25U)
+#define FLASH_SECCR_ERRIE_Msk (0x1UL << FLASH_SECCR_ERRIE_Pos) /*!< 0x02000000 */
+#define FLASH_SECCR_ERRIE FLASH_SECCR_ERRIE_Msk /*!< Secure error interrupt enable */
+#define FLASH_SECCR_INV_Pos (29U)
+#define FLASH_SECCR_INV_Msk (0x1UL << FLASH_SECCR_INV_Pos) /*!< 0x20000000 */
+#define FLASH_SECCR_INV FLASH_SECCR_INV_Msk /*!< Flash Security State Invert */
+#define FLASH_SECCR_LOCK_Pos (31U)
+#define FLASH_SECCR_LOCK_Msk (0x1UL << FLASH_SECCR_LOCK_Pos) /*!< 0x80000000 */
+#define FLASH_SECCR_LOCK FLASH_SECCR_LOCK_Msk /*!< Secure Lock */
+
+/******************* Bits definition for FLASH_ECCR register ***************/
+#define FLASH_ECCR_ADDR_ECC_Pos (0U)
+#define FLASH_ECCR_ADDR_ECC_Msk (0xFFFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x000FFFFF */
+#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */
+#define FLASH_ECCR_BK_ECC_Pos (21U)
+#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00200000 */
+#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail bank */
+#define FLASH_ECCR_SYSF_ECC_Pos (22U)
+#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */
+#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */
+#define FLASH_ECCR_ECCIE_Pos (24U)
+#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */
+#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */
+#define FLASH_ECCR_ECCC_Pos (30U)
+#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */
+#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */
+#define FLASH_ECCR_ECCD_Pos (31U)
+#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */
+#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */
+
+/******************* Bits definition for FLASH_OPSR register ***************/
+#define FLASH_OPSR_ADDR_OP_Pos (0U)
+#define FLASH_OPSR_ADDR_OP_Msk (0xFFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x000FFFFF */
+#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Flash operation address */
+#define FLASH_OPSR_BK_OP_Pos (21U)
+#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00200000 */
+#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation bank */
+#define FLASH_OPSR_SYSF_OP_Pos (22U)
+#define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00400000 */
+#define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in System Flash interrupted */
+#define FLASH_OPSR_CODE_OP_Pos (29U)
+#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */
+#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash operation code */
+#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */
+#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */
+#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */
+
+/******************* Bits definition for FLASH_OPTR register ***************/
+#define FLASH_OPTR_RDP_Pos (0U)
+#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */
+#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk /*!< Readout protection level */
+#define FLASH_OPTR_BOR_LEV_Pos (8U)
+#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */
+#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR reset Level */
+#define FLASH_OPTR_BOR_LEV_0 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */
+#define FLASH_OPTR_BOR_LEV_1 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */
+#define FLASH_OPTR_BOR_LEV_2 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */
+#define FLASH_OPTR_nRST_STOP_Pos (12U)
+#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */
+#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */
+#define FLASH_OPTR_nRST_STDBY_Pos (13U)
+#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */
+#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */
+#define FLASH_OPTR_nRST_SHDW_Pos (14U)
+#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */
+#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk /*!< nRST_SHDW */
+#define FLASH_OPTR_SRAM134_RST_Pos (15U)
+#define FLASH_OPTR_SRAM134_RST_Msk (0x1UL << FLASH_OPTR_SRAM134_RST_Pos) /*!< 0x00008000 */
+#define FLASH_OPTR_SRAM134_RST FLASH_OPTR_SRAM134_RST_Msk /*!< SRAM1, SRAM3 and SRAM4 erase upon system reset */
+#define FLASH_OPTR_IWDG_SW_Pos (16U)
+#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */
+#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */
+#define FLASH_OPTR_IWDG_STOP_Pos (17U)
+#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */
+#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */
+#define FLASH_OPTR_IWDG_STDBY_Pos (18U)
+#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
+#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */
+#define FLASH_OPTR_WWDG_SW_Pos (19U)
+#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */
+#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk /*!< Window watchdog selection */
+#define FLASH_OPTR_SWAP_BANK_Pos (20U)
+#define FLASH_OPTR_SWAP_BANK_Msk (0x1UL << FLASH_OPTR_SWAP_BANK_Pos) /*!< 0x00100000 */
+#define FLASH_OPTR_SWAP_BANK FLASH_OPTR_SWAP_BANK_Msk /*!< Swap banks */
+#define FLASH_OPTR_DUALBANK_Pos (21U)
+#define FLASH_OPTR_DUALBANK_Msk (0x1UL << FLASH_OPTR_DUALBANK_Pos) /*!< 0x00200000 */
+#define FLASH_OPTR_DUALBANK FLASH_OPTR_DUALBANK_Msk /*!< Dual-bank on 1M and 512 Kbytes Flash memory devices */
+#define FLASH_OPTR_BKPRAM_ECC_Pos (22U)
+#define FLASH_OPTR_BKPRAM_ECC_Msk (0x1UL << FLASH_OPTR_BKPRAM_ECC_Pos) /*!< 0x00400000 */
+#define FLASH_OPTR_BKPRAM_ECC FLASH_OPTR_BKPRAM_ECC_Msk /*!< Backup RAM ECC detection and correction enable */
+#define FLASH_OPTR_SRAM3_ECC_Pos (23U)
+#define FLASH_OPTR_SRAM3_ECC_Msk (0x1UL << FLASH_OPTR_SRAM3_ECC_Pos) /*!< 0x00800000 */
+#define FLASH_OPTR_SRAM3_ECC FLASH_OPTR_SRAM3_ECC_Msk /*!< SRAM3 ECC detection and correction enable */
+#define FLASH_OPTR_SRAM2_ECC_Pos (24U)
+#define FLASH_OPTR_SRAM2_ECC_Msk (0x1UL << FLASH_OPTR_SRAM2_ECC_Pos) /*!< 0x01000000 */
+#define FLASH_OPTR_SRAM2_ECC FLASH_OPTR_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction enable*/
+#define FLASH_OPTR_SRAM2_RST_Pos (25U)
+#define FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */
+#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk /*!< SRAM2 erase when system reset */
+#define FLASH_OPTR_nSWBOOT0_Pos (26U)
+#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */
+#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk /*!< Software BOOT0 */
+#define FLASH_OPTR_nBOOT0_Pos (27U)
+#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */
+#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk /*!< nBOOT0 option bit */
+#define FLASH_OPTR_PA15_PUPEN_Pos (28U)
+#define FLASH_OPTR_PA15_PUPEN_Msk (0x1UL << FLASH_OPTR_PA15_PUPEN_Pos) /*!< 0x10000000 */
+#define FLASH_OPTR_PA15_PUPEN FLASH_OPTR_PA15_PUPEN_Msk /*!< PA15 pull-up enable */
+#define FLASH_OPTR_IO_VDD_HSLV_Pos (29U)
+#define FLASH_OPTR_IO_VDD_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDD_HSLV_Pos) /*!< 0x20000000 */
+#define FLASH_OPTR_IO_VDD_HSLV FLASH_OPTR_IO_VDD_HSLV_Msk /*!< High speed IO at low voltage configuration bit */
+#define FLASH_OPTR_IO_VDDIO2_HSLV_Pos (30U)
+#define FLASH_OPTR_IO_VDDIO2_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDDIO2_HSLV_Pos) /*!< 0x40000000 */
+#define FLASH_OPTR_IO_VDDIO2_HSLV FLASH_OPTR_IO_VDDIO2_HSLV_Msk /*!< High speed IO at low VDDIO2 voltage configuration bit */
+#define FLASH_OPTR_TZEN_Pos (31U)
+#define FLASH_OPTR_TZEN_Msk (0x1UL << FLASH_OPTR_TZEN_Pos) /*!< 0x80000000 */
+#define FLASH_OPTR_TZEN FLASH_OPTR_TZEN_Msk /*!< Global TrustZone security enable */
+
+/**************** Bits definition for FLASH_NSBOOTADD0R register ************/
+#define FLASH_NSBOOTADD0R_NSBOOTADD0_Pos (7U)
+#define FLASH_NSBOOTADD0R_NSBOOTADD0_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD0R_NSBOOTADD0_Pos) /*!< 0xFFFFFF80 */
+#define FLASH_NSBOOTADD0R_NSBOOTADD0 FLASH_NSBOOTADD0R_NSBOOTADD0_Msk /*!< Non-secure boot address 0 */
+
+/**************** Bits definition for FLASH_NSBOOTADD1R register ************/
+#define FLASH_NSBOOTADD1R_NSBOOTADD1_Pos (7U)
+#define FLASH_NSBOOTADD1R_NSBOOTADD1_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD1R_NSBOOTADD1_Pos) /*!< 0xFFFFFF80 */
+#define FLASH_NSBOOTADD1R_NSBOOTADD1 FLASH_NSBOOTADD1R_NSBOOTADD1_Msk /*!< Non-secure boot address 1 */
+
+/**************** Bits definition for FLASH_SECBOOTADD0R register ***********/
+#define FLASH_SECBOOTADD0R_BOOT_LOCK_Pos (0U)
+#define FLASH_SECBOOTADD0R_BOOT_LOCK_Msk (0x1UL << FLASH_SECBOOTADD0R_BOOT_LOCK_Pos) /*!< 0x00000001 */
+#define FLASH_SECBOOTADD0R_BOOT_LOCK FLASH_SECBOOTADD0R_BOOT_LOCK_Msk /*!< Boot Lock */
+#define FLASH_SECBOOTADD0R_SECBOOTADD0_Pos (7U)
+#define FLASH_SECBOOTADD0R_SECBOOTADD0_Msk (0x1FFFFFFUL << FLASH_SECBOOTADD0R_SECBOOTADD0_Pos) /*!< 0xFFFFFF80 */
+#define FLASH_SECBOOTADD0R_SECBOOTADD0 FLASH_SECBOOTADD0R_SECBOOTADD0_Msk /*!< Secure boot address 0 */
+
+/***************** Bits definition for FLASH_SECWM1R1 register **************/
+#define FLASH_SECWM1R1_SECWM1_PSTRT_Pos (0U)
+#define FLASH_SECWM1R1_SECWM1_PSTRT_Msk (0x7FUL << FLASH_SECWM1R1_SECWM1_PSTRT_Pos) /*!< 0x0000007F */
+#define FLASH_SECWM1R1_SECWM1_PSTRT FLASH_SECWM1R1_SECWM1_PSTRT_Msk /*!< Start page of first secure area */
+#define FLASH_SECWM1R1_SECWM1_PEND_Pos (16U)
+#define FLASH_SECWM1R1_SECWM1_PEND_Msk (0x7FUL << FLASH_SECWM1R1_SECWM1_PEND_Pos) /*!< 0x007F0000 */
+#define FLASH_SECWM1R1_SECWM1_PEND FLASH_SECWM1R1_SECWM1_PEND_Msk /*!< End page of first secure area */
+
+/***************** Bits definition for FLASH_SECWM1R2 register **************/
+#define FLASH_SECWM1R2_HDP1_PEND_Pos (16U)
+#define FLASH_SECWM1R2_HDP1_PEND_Msk (0x7FUL << FLASH_SECWM1R2_HDP1_PEND_Pos) /*!< 0x007F0000 */
+#define FLASH_SECWM1R2_HDP1_PEND FLASH_SECWM1R2_HDP1_PEND_Msk /*!< End page of first hide protection area */
+#define FLASH_SECWM1R2_HDP1EN_Pos (31U)
+#define FLASH_SECWM1R2_HDP1EN_Msk (0x1UL << FLASH_SECWM1R2_HDP1EN_Pos) /*!< 0x80000000 */
+#define FLASH_SECWM1R2_HDP1EN FLASH_SECWM1R2_HDP1EN_Msk /*!< Hide protection first area enable */
+
+/****************** Bits definition for FLASH_WRP1AR register ***************/
+#define FLASH_WRP1AR_WRP1A_PSTRT_Pos (0U)
+#define FLASH_WRP1AR_WRP1A_PSTRT_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_PSTRT_Pos) /*!< 0x0000007F */
+#define FLASH_WRP1AR_WRP1A_PSTRT FLASH_WRP1AR_WRP1A_PSTRT_Msk /*!< Bank 1 WPR first area A start page */
+#define FLASH_WRP1AR_WRP1A_PEND_Pos (16U)
+#define FLASH_WRP1AR_WRP1A_PEND_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_PEND_Pos) /*!< 0x007F0000 */
+#define FLASH_WRP1AR_WRP1A_PEND FLASH_WRP1AR_WRP1A_PEND_Msk /*!< Bank 1 WPR first area A end page */
+#define FLASH_WRP1AR_UNLOCK_Pos (31U)
+#define FLASH_WRP1AR_UNLOCK_Msk (0x1UL << FLASH_WRP1AR_UNLOCK_Pos) /*!< 0x80000000 */
+#define FLASH_WRP1AR_UNLOCK FLASH_WRP1AR_UNLOCK_Msk /*!< Bank 1 WPR first area A unlock */
+
+/****************** Bits definition for FLASH_WRP1BR register ***************/
+#define FLASH_WRP1BR_WRP1B_PSTRT_Pos (0U)
+#define FLASH_WRP1BR_WRP1B_PSTRT_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_PSTRT_Pos) /*!< 0x0000007F */
+#define FLASH_WRP1BR_WRP1B_PSTRT FLASH_WRP1BR_WRP1B_PSTRT_Msk /*!< Bank 1 WPR second area B start page */
+#define FLASH_WRP1BR_WRP1B_PEND_Pos (16U)
+#define FLASH_WRP1BR_WRP1B_PEND_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_PEND_Pos) /*!< 0x007F0000 */
+#define FLASH_WRP1BR_WRP1B_PEND FLASH_WRP1BR_WRP1B_PEND_Msk /*!< Bank 1 WPR second area B end page */
+#define FLASH_WRP1BR_UNLOCK_Pos (31U)
+#define FLASH_WRP1BR_UNLOCK_Msk (0x1UL << FLASH_WRP1BR_UNLOCK_Pos) /*!< 0x80000000 */
+#define FLASH_WRP1BR_UNLOCK FLASH_WRP1BR_UNLOCK_Msk /*!< Bank 1 WPR first area B unlock */
+
+/***************** Bits definition for FLASH_SECWM2R1 register **************/
+#define FLASH_SECWM2R1_SECWM2_PSTRT_Pos (0U)
+#define FLASH_SECWM2R1_SECWM2_PSTRT_Msk (0x7FUL << FLASH_SECWM2R1_SECWM2_PSTRT_Pos) /*!< 0x0000007F */
+#define FLASH_SECWM2R1_SECWM2_PSTRT FLASH_SECWM2R1_SECWM2_PSTRT_Msk /*!< Start page of second secure area */
+#define FLASH_SECWM2R1_SECWM2_PEND_Pos (16U)
+#define FLASH_SECWM2R1_SECWM2_PEND_Msk (0x7FUL << FLASH_SECWM2R1_SECWM2_PEND_Pos) /*!< 0x007F0000 */
+#define FLASH_SECWM2R1_SECWM2_PEND FLASH_SECWM2R1_SECWM2_PEND_Msk /*!< End page of second secure area */
+
+/***************** Bits definition for FLASH_SECWM2R2 register **************/
+#define FLASH_SECWM2R2_HDP2_PEND_Pos (16U)
+#define FLASH_SECWM2R2_HDP2_PEND_Msk (0x7FUL << FLASH_SECWM2R2_HDP2_PEND_Pos) /*!< 0x007F0000 */
+#define FLASH_SECWM2R2_HDP2_PEND FLASH_SECWM2R2_HDP2_PEND_Msk /*!< End page of hide protection second area */
+#define FLASH_SECWM2R2_HDP2EN_Pos (31U)
+#define FLASH_SECWM2R2_HDP2EN_Msk (0x1UL << FLASH_SECWM2R2_HDP2EN_Pos) /*!< 0x80000000 */
+#define FLASH_SECWM2R2_HDP2EN FLASH_SECWM2R2_HDP2EN_Msk /*!< Hide protection second area enable */
+
+/****************** Bits definition for FLASH_WRP2AR register ***************/
+#define FLASH_WRP2AR_WRP2A_PSTRT_Pos (0U)
+#define FLASH_WRP2AR_WRP2A_PSTRT_Msk (0x7FUL << FLASH_WRP2AR_WRP2A_PSTRT_Pos) /*!< 0x0000007F */
+#define FLASH_WRP2AR_WRP2A_PSTRT FLASH_WRP2AR_WRP2A_PSTRT_Msk /*!< Bank 2 WPR first area A start page */
+#define FLASH_WRP2AR_WRP2A_PEND_Pos (16U)
+#define FLASH_WRP2AR_WRP2A_PEND_Msk (0x7FUL << FLASH_WRP2AR_WRP2A_PEND_Pos) /*!< 0x007F0000 */
+#define FLASH_WRP2AR_WRP2A_PEND FLASH_WRP2AR_WRP2A_PEND_Msk /*!< Bank 2 WPR first area A end page */
+#define FLASH_WRP2AR_UNLOCK_Pos (31U)
+#define FLASH_WRP2AR_UNLOCK_Msk (0x1UL << FLASH_WRP2AR_UNLOCK_Pos) /*!< 0x80000000 */
+#define FLASH_WRP2AR_UNLOCK FLASH_WRP2AR_UNLOCK_Msk /*!< Bank 2 WPR first area A unlock */
+
+/****************** Bits definition for FLASH_WRP2BR register ***************/
+#define FLASH_WRP2BR_WRP2B_PSTRT_Pos (0U)
+#define FLASH_WRP2BR_WRP2B_PSTRT_Msk (0x7FUL << FLASH_WRP2BR_WRP2B_PSTRT_Pos) /*!< 0x0000007F */
+#define FLASH_WRP2BR_WRP2B_PSTRT FLASH_WRP2BR_WRP2B_PSTRT_Msk /*!< Bank 2 WPR first area B start page */
+#define FLASH_WRP2BR_WRP2B_PEND_Pos (16U)
+#define FLASH_WRP2BR_WRP2B_PEND_Msk (0x7FUL << FLASH_WRP2BR_WRP2B_PEND_Pos) /*!< 0x007F0000 */
+#define FLASH_WRP2BR_WRP2B_PEND FLASH_WRP2BR_WRP2B_PEND_Msk /*!< Bank 2 WPR first area B end page */
+#define FLASH_WRP2BR_UNLOCK_Pos (31U)
+#define FLASH_WRP2BR_UNLOCK_Msk (0x1UL << FLASH_WRP2BR_UNLOCK_Pos) /*!< 0x80000000 */
+#define FLASH_WRP2BR_UNLOCK FLASH_WRP2BR_UNLOCK_Msk /*!< Bank 2 WPR first area B unlock */
+
+/****************** Bits definition for FLASH_SECHDPCR register ***********/
+#define FLASH_SECHDPCR_HDP1_ACCDIS_Pos (0U)
+#define FLASH_SECHDPCR_HDP1_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP1_ACCDIS_Pos) /*!< 0x00000001 */
+#define FLASH_SECHDPCR_HDP1_ACCDIS FLASH_SECHDPCR_HDP1_ACCDIS_Msk /*!< HDP1 area access disable */
+#define FLASH_SECHDPCR_HDP2_ACCDIS_Pos (1U)
+#define FLASH_SECHDPCR_HDP2_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP2_ACCDIS_Pos) /*!< 0x00000002 */
+#define FLASH_SECHDPCR_HDP2_ACCDIS FLASH_SECHDPCR_HDP2_ACCDIS_Msk /*!< HDP2 area access disable */
+
+/****************** Bits definition for FLASH_PRIVCFGR register ***********/
+#define FLASH_PRIVCFGR_SPRIV_Pos (0U)
+#define FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */
+#define FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk /*!< Privilege protection for secure registers */
+#define FLASH_PRIVCFGR_NSPRIV_Pos (1U)
+#define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */
+#define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */
+
+
+/******************************************************************************/
+/* */
+/* Filter Mathematical ACcelerator unit (FMAC) */
+/* */
+/******************************************************************************/
+/***************** Bit definition for FMAC_X1BUFCFG register ****************/
+#define FMAC_X1BUFCFG_X1_BASE_Pos (0U)
+#define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos) /*!< 0x000000FF */
+#define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk /*!< Base address of X1 buffer */
+#define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8U)
+#define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) /*!< 0x0000FF00 */
+#define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */
+#define FMAC_X1BUFCFG_FULL_WM_Pos (24U)
+#define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos) /*!< 0x03000000 */
+#define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk /*!< Watermark for buffer full flag */
+
+/***************** Bit definition for FMAC_X2BUFCFG register ****************/
+#define FMAC_X2BUFCFG_X2_BASE_Pos (0U)
+#define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos) /*!< 0x000000FF */
+#define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk /*!< Base address of X2 buffer */
+#define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8U)
+#define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) /*!< 0x0000FF00 */
+#define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */
+
+/***************** Bit definition for FMAC_YBUFCFG register *****************/
+#define FMAC_YBUFCFG_Y_BASE_Pos (0U)
+#define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos) /*!< 0x000000FF */
+#define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk /*!< Base address of Y buffer */
+#define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8U)
+#define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) /*!< 0x0000FF00 */
+#define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */
+#define FMAC_YBUFCFG_EMPTY_WM_Pos (24U)
+#define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos) /*!< 0x03000000 */
+#define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk /*!< Watermark for buffer empty flag */
+
+/****************** Bit definition for FMAC_PARAM register ******************/
+#define FMAC_PARAM_P_Pos (0U)
+#define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos) /*!< 0x000000FF */
+#define FMAC_PARAM_P FMAC_PARAM_P_Msk /*!< Input parameter P */
+#define FMAC_PARAM_Q_Pos (8U)
+#define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos) /*!< 0x0000FF00 */
+#define FMAC_PARAM_Q FMAC_PARAM_Q_Msk /*!< Input parameter Q */
+#define FMAC_PARAM_R_Pos (16U)
+#define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos) /*!< 0x00FF0000 */
+#define FMAC_PARAM_R FMAC_PARAM_R_Msk /*!< Input parameter R */
+#define FMAC_PARAM_FUNC_Pos (24U)
+#define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos) /*!< 0x7F000000 */
+#define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk /*!< Function */
+#define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos) /*!< 0x01000000 */
+#define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos) /*!< 0x02000000 */
+#define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos) /*!< 0x04000000 */
+#define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos) /*!< 0x08000000 */
+#define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos) /*!< 0x10000000 */
+#define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos) /*!< 0x20000000 */
+#define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos) /*!< 0x40000000 */
+#define FMAC_PARAM_START_Pos (31U)
+#define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos) /*!< 0x80000000 */
+#define FMAC_PARAM_START FMAC_PARAM_START_Msk /*!< Enable execution */
+
+/******************** Bit definition for FMAC_CR register *******************/
+#define FMAC_CR_RIEN_Pos (0U)
+#define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos) /*!< 0x00000001 */
+#define FMAC_CR_RIEN FMAC_CR_RIEN_Msk /*!< Enable read interrupt */
+#define FMAC_CR_WIEN_Pos (1U)
+#define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos) /*!< 0x00000002 */
+#define FMAC_CR_WIEN FMAC_CR_WIEN_Msk /*!< Enable write interrupt */
+#define FMAC_CR_OVFLIEN_Pos (2U)
+#define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos) /*!< 0x00000004 */
+#define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk /*!< Enable overflow error interrupts */
+#define FMAC_CR_UNFLIEN_Pos (3U)
+#define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos) /*!< 0x00000008 */
+#define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk /*!< Enable underflow error interrupts */
+#define FMAC_CR_SATIEN_Pos (4U)
+#define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos) /*!< 0x00000010 */
+#define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk /*!< Enable saturation error interrupts */
+#define FMAC_CR_DMAREN_Pos (8U)
+#define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos) /*!< 0x00000100 */
+#define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk /*!< Enable DMA read channel requests */
+#define FMAC_CR_DMAWEN_Pos (9U)
+#define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos) /*!< 0x00000200 */
+#define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk /*!< Enable DMA write channel requests */
+#define FMAC_CR_CLIPEN_Pos (15U)
+#define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos) /*!< 0x00008000 */
+#define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk /*!< Enable clipping */
+#define FMAC_CR_RESET_Pos (16U)
+#define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos) /*!< 0x00010000 */
+#define FMAC_CR_RESET FMAC_CR_RESET_Msk /*!< Reset filter mathematical accelerator unit */
+
+/******************* Bit definition for FMAC_SR register ********************/
+#define FMAC_SR_YEMPTY_Pos (0U)
+#define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos) /*!< 0x00000001 */
+#define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk /*!< Y buffer empty flag */
+#define FMAC_SR_X1FULL_Pos (1U)
+#define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos) /*!< 0x00000002 */
+#define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk /*!< X1 buffer full flag */
+#define FMAC_SR_OVFL_Pos (8U)
+#define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos) /*!< 0x00000100 */
+#define FMAC_SR_OVFL FMAC_SR_OVFL_Msk /*!< Overflow error flag */
+#define FMAC_SR_UNFL_Pos (9U)
+#define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos) /*!< 0x00000200 */
+#define FMAC_SR_UNFL FMAC_SR_UNFL_Msk /*!< Underflow error flag */
+#define FMAC_SR_SAT_Pos (10U)
+#define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos) /*!< 0x00000400 */
+#define FMAC_SR_SAT FMAC_SR_SAT_Msk /*!< Saturation error flag */
+
+/****************** Bit definition for FMAC_WDATA register ******************/
+#define FMAC_WDATA_WDATA_Pos (0U)
+#define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos) /*!< 0x0000FFFF */
+#define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk /*!< Write data */
+
+/****************** Bit definition for FMACX_RDATA register *****************/
+#define FMAC_RDATA_RDATA_Pos (0U)
+#define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */
+#define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */
+
+
+/******************************************************************************/
+/* */
+/* Flexible Memory Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for FMC_BCR1 register *******************/
+#define FMC_BCR1_CCLKEN_Pos (20U)
+#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wc11-extensions"
+ #pragma clang diagnostic ignored "-Wreserved-id-macro"
+#elif defined (__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+ #pragma warning 586
+#elif defined (__CSMC__)
+ /* anonymous unions are enabled by default */
+#else
+ #warning Not supported compiler type
+#endif
+
+/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */
+#define __CM33_REV 0x0000U /* Core revision r0p1 */
+#define __SAUREGION_PRESENT 1U /* SAU regions present */
+#define __MPU_PRESENT 1U /* MPU present */
+#define __VTOR_PRESENT 1U /* VTOR present */
+#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /* FPU present */
+#define __DSP_PRESENT 1U /* DSP extension present */
+
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include /*!< ARM Cortex-M33 processor and core peripherals */
+#include "system_stm32u5xx.h" /*!< STM32U5xx System */
+
+
+/* =========================================================================================================================== */
+/* ================ Device Specific Peripheral Section ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup STM32U5xx_peripherals
+ * @{
+ */
+
+/**
+ * @brief CRC calculation unit
+ */
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+ uint32_t RESERVED2; /*!< Reserved, 0x0C */
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+ uint32_t RESERVED3[246]; /*!< Reserved, */
+ __IO uint32_t HWCFGR; /*!< CRC IP HWCFGR register, Address offset: 0x3F0 */
+ __IO uint32_t VERR; /*!< CRC IP version register, Address offset: 0x3F4 */
+ __IO uint32_t PIDR; /*!< CRC IP type identification register, Address offset: 0x3F8 */
+ __IO uint32_t SIDR; /*!< CRC IP map Size ID register, Address offset: 0x3FC */
+} CRC_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
+ __IO uint32_t AUTOCR;
+} I2C_TypeDef;
+
+/**
+ * @brief DAC
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+ __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
+ __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
+ __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
+ __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
+ __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
+ __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
+ __IO uint32_t RESERVED[1];
+ __IO uint32_t AUTOCR; /*!< DAC Autonomous mode register, Address offset: 0x54 */
+} DAC_TypeDef;
+
+/**
+ * @brief Clock Recovery System
+ */
+typedef struct
+{
+__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
+__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
+__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
+__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
+} CRS_TypeDef;
+
+/**
+ * @brief AES hardware accelerator
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */
+ __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */
+ __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */
+ __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */
+ __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */
+ __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */
+ __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */
+ __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */
+ __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */
+ __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */
+ __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */
+ __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */
+ __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */
+ __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */
+ __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */
+ __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */
+ __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */
+ __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */
+ __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */
+ __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */
+ __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */
+ __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */
+ __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x5C */
+ uint32_t RESERVED1[168];/*!< Reserved, Address offset: 0x60 -- 0x2FC */
+ __IO uint32_t IER; /*!< AES Interrupt Enable Register, Address offset: 0x300 */
+ __IO uint32_t ISR; /*!< AES Interrupt Status Register, Address offset: 0x304 */
+ __IO uint32_t ICR; /*!< AES Interrupt Clear Register, Address offset: 0x308 */
+} AES_TypeDef;
+
+/**
+ * @brief HASH
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
+ __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
+ __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
+ __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
+ __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
+ __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
+ uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
+ __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
+} HASH_TypeDef;
+
+/**
+ * @brief HASH_DIGEST
+ */
+typedef struct
+{
+ __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
+} HASH_DIGEST_TypeDef;
+
+/**
+ * @brief RNG
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+ uint32_t RESERVED;
+ __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */
+} RNG_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
+ __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
+ __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
+ __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */
+ uint32_t RESERVED1[2];/*!< Reserved, 0x18 - 0x1C */
+ __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */
+ uint32_t RESERVED2; /*!< Reserved, 0x24 */
+ __IO uint32_t AHB3FZR; /*!< Debug MCU AHB3 freeze register, Address offset: 0x28 */
+} DBGMCU_TypeDef;
+
+/**
+ * @brief DCMI
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
+ __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
+ __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
+ __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
+ __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
+ __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+ __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
+ __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
+ __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+typedef struct
+{
+ __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */
+ __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */
+ __IO uint32_t RCFGLOCKR; /*!< DMA lock configuration register, Address offset: 0x08 */
+ __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */
+ __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */
+} DMA_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */
+ uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */
+ __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */
+ __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */
+ __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */
+ uint32_t RESERVED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */
+ __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */
+ __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */
+ __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */
+ __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */
+ __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */
+ __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */
+ __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */
+ uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */
+ __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */
+} DMA_Channel_TypeDef;
+
+/**
+ * @brief DMA2D Controller
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
+ __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
+ __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
+ __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
+ __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
+ __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
+ __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
+ __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
+ __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
+ __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
+ __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
+ __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
+ __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
+ __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
+ __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
+ __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
+ __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
+ __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
+ __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
+ __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
+ uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FC */
+ __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FC */
+ __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFC */
+} DMA2D_TypeDef;
+
+/**
+ * @brief Asynch Interrupt/Event Controller (EXTI)
+ */
+typedef struct
+{
+ __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */
+ __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */
+ __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */
+ __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */
+ __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */
+ __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */
+ __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */
+ uint32_t RESERVED1[17]; /*!< Reserved 1, 0x1C -- 0x5C */
+ __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */
+ __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */
+ uint32_t RESERVED2[3]; /*!< Reserved 2, 0x74 -- 0x7C */
+ __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */
+ __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */
+ __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x08 */
+ __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x0C */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x10 */
+ __IO uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x14 */
+ __IO uint32_t PDKEY1R; /*!< FLASH Bank 1 power-down key register, Address offset: 0x18 */
+ __IO uint32_t PDKEY2R; /*!< FLASH Bank 2 power-down key register, Address offset: 0x1C */
+ __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */
+ __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */
+ __IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offset: 0x28 */
+ __IO uint32_t SECCR; /*!< FLASH secure control register, Address offset: 0x2C */
+ __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x30 */
+ __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x34 */
+ uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x38-0x3C */
+ __IO uint32_t OPTR; /*!< FLASH option control register, Address offset: 0x40 */
+ __IO uint32_t NSBOOTADD0R; /*!< FLASH non-secure boot address 0 register, Address offset: 0x44 */
+ __IO uint32_t NSBOOTADD1R; /*!< FLASH non-secure boot address 1 register, Address offset: 0x48 */
+ __IO uint32_t SECBOOTADD0R; /*!< FLASH secure boot address 0 register, Address offset: 0x4C */
+ __IO uint32_t SECWM1R1; /*!< FLASH secure watermark1 register 1, Address offset: 0x50 */
+ __IO uint32_t SECWM1R2; /*!< FLASH secure watermark1 register 2, Address offset: 0x54 */
+ __IO uint32_t WRP1AR; /*!< FLASH WRP1 area A address register, Address offset: 0x58 */
+ __IO uint32_t WRP1BR; /*!< FLASH WRP1 area B address register, Address offset: 0x5C */
+ __IO uint32_t SECWM2R1; /*!< FLASH secure watermark2 register 1, Address offset: 0x60 */
+ __IO uint32_t SECWM2R2; /*!< FLASH secure watermark2 register 2, Address offset: 0x64 */
+ __IO uint32_t WRP2AR; /*!< FLASH WRP2 area A address register, Address offset: 0x68 */
+ __IO uint32_t WRP2BR; /*!< FLASH WRP2 area B address register, Address offset: 0x6C */
+ __IO uint32_t OEM1KEYR1; /*!< FLASH OEM1 key register 1, Address offset: 0x70 */
+ __IO uint32_t OEM1KEYR2; /*!< FLASH OEM1 key register 2, Address offset: 0x74 */
+ __IO uint32_t OEM2KEYR1; /*!< FLASH OEM2 key register 1, Address offset: 0x78 */
+ __IO uint32_t OEM2KEYR2; /*!< FLASH OEM2 key register 2, Address offset: 0x7C */
+ __IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offset: 0x80 */
+ __IO uint32_t SECBB1R2; /*!< FLASH secure block-based bank 1 register 2, Address offset: 0x84 */
+ __IO uint32_t SECBB1R3; /*!< FLASH secure block-based bank 1 register 3, Address offset: 0x88 */
+ __IO uint32_t SECBB1R4; /*!< FLASH secure block-based bank 1 register 4, Address offset: 0x8C */
+ uint32_t RESERVED4[4]; /*!< Reserved4, Address offset: 0x90-0x9C */
+ __IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offset: 0xA0 */
+ __IO uint32_t SECBB2R2; /*!< FLASH secure block-based bank 2 register 2, Address offset: 0xA4 */
+ __IO uint32_t SECBB2R3; /*!< FLASH secure block-based bank 2 register 3, Address offset: 0xA8 */
+ __IO uint32_t SECBB2R4; /*!< FLASH secure block-based bank 2 register 4, Address offset: 0xAC */
+ uint32_t RESERVED5[4]; /*!< Reserved5, Address offset: 0xB0-0xBC */
+ __IO uint32_t SECHDPCR; /*!< FLASH secure HDP control register, Address offset: 0xC0 */
+ __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0xC4 */
+ uint32_t RESERVED6[2]; /*!< Reserved6, Address offset: 0xC8-0xCC */
+ __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xD0 */
+ __IO uint32_t PRIVBB1R2; /*!< FLASH privilege block-based bank 1 register 2, Address offset: 0xD4 */
+ __IO uint32_t PRIVBB1R3; /*!< FLASH privilege block-based bank 1 register 3, Address offset: 0xD8 */
+ __IO uint32_t PRIVBB1R4; /*!< FLASH privilege block-based bank 1 register 4, Address offset: 0xDC */
+ uint32_t RESERVED7[4]; /*!< Reserved7, Address offset: 0xE0-0xEC */
+ __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0xF0 */
+ __IO uint32_t PRIVBB2R2; /*!< FLASH privilege block-based bank 2 register 2, Address offset: 0xF4 */
+ __IO uint32_t PRIVBB2R3; /*!< FLASH privilege block-based bank 2 register 3, Address offset: 0xF8 */
+ __IO uint32_t PRIVBB2R4; /*!< FLASH privilege block-based bank 2 register 4, Address offset: 0xFC */
+} FLASH_TypeDef;
+
+/**
+ * @brief FMAC
+ */
+typedef struct
+{
+ __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */
+ __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */
+ __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */
+ __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */
+ __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */
+ __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */
+ __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */
+} FMAC_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+ __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
+ __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */
+ __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */
+} GPIO_TypeDef;
+
+/**
+ * @brief Global TrustZone Controller
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */
+ uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */
+ __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */
+ __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */
+ __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */
+ uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */
+ __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */
+ __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */
+ __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */
+ uint32_t RESERVED3[5]; /*!< Reserved3, Address offset: 0x2C-0x3C */
+ __IO uint32_t MPCWM1ACFGR; /*!< TZSC memory 1 sub-region A watermark configuration register, Address offset: 0x40 */
+ __IO uint32_t MPCWM1AR; /*!< TZSC memory 1 sub-region A watermark register, Address offset: 0x44 */
+ __IO uint32_t MPCWM1BCFGR; /*!< TZSC memory 1 sub-region B watermark configuration register, Address offset: 0x48 */
+ __IO uint32_t MPCWM1BR; /*!< TZSC memory 1 sub-region B watermark register, Address offset: 0x4C */
+ __IO uint32_t MPCWM2ACFGR; /*!< TZSC memory 2 sub-region A watermark configuration register, Address offset: 0x50 */
+ __IO uint32_t MPCWM2AR; /*!< TZSC memory 2 sub-region A watermark register, Address offset: 0x54 */
+ __IO uint32_t MPCWM2BCFGR; /*!< TZSC memory 2 sub-region B watermark configuration register, Address offset: 0x58 */
+ __IO uint32_t MPCWM2BR; /*!< TZSC memory 2 sub-region B watermark register, Address offset: 0x5C */
+ __IO uint32_t MPCWM3ACFGR; /*!< TZSC memory 3 sub-region A watermark configuration register, Address offset: 0x60 */
+ __IO uint32_t MPCWM3AR; /*!< TZSC memory 3 sub-region A watermark register, Address offset: 0x64 */
+ uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x68-0x6C */
+ __IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, Address offset: 0x70 */
+ __IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, Address offset: 0x74 */
+ uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0x78-0x7C */
+ __IO uint32_t MPCWM5ACFGR; /*!< TZSC memory 5 sub-region A watermark configuration register, Address offset: 0x80 */
+ __IO uint32_t MPCWM5AR; /*!< TZSC memory 5 sub-region A watermark register, Address offset: 0x84 */
+ __IO uint32_t MPCWM5BCFGR; /*!< TZSC memory 5 sub-region B watermark configuration register, Address offset: 0x88 */
+ __IO uint32_t MPCWM5BR; /*!< TZSC memory 5 sub-region B watermark register, Address offset: 0x8C */
+} GTZC_TZSC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */
+ uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */
+ __IO uint32_t CFGLOCKR1; /*!< MPCBBx Configuration lock register, Address offset: 0x10 */
+ uint32_t RESERVED2[59]; /*!< Reserved2, Address offset: 0x14-0xFC */
+ __IO uint32_t SECCFGR[32]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x180 */
+ uint32_t RESERVED3[32]; /*!< Reserved3, Address offset: 0x180-0x200 */
+ __IO uint32_t PRIVCFGR[32]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x280 */
+} GTZC_MPCBB_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */
+ __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */
+ __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */
+ __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */
+ __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */
+ __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */
+ __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */
+ __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */
+ __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */
+ __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */
+ __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */
+ __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */
+} GTZC_TZIC_TypeDef;
+
+/**
+ * @brief Instruction Cache
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */
+ __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */
+ __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */
+ __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */
+ __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */
+ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */
+ __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */
+ __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */
+ __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */
+ __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */
+ uint32_t RESERVED2[240]; /*!< Reserved, Address offset: 0x30-0x3EC */
+ __IO uint32_t HWCFGR; /*!< ICACHE HW configuration register, Address offset: 0x3F0 */
+ __IO uint32_t VERR; /*!< ICACHE version register, Address offset: 0x3F4 */
+ __IO uint32_t IPIDR; /*!< ICACHE IP identification register, Address offset: 0x3F8 */
+ __IO uint32_t SIDR; /*!< ICACHE size identification register, Address offset: 0x3FC */
+} ICACHE_TypeDef;
+
+/**
+ * @brief Data Cache
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< DCACHE control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< DCACHE status register, Address offset: 0x04 */
+ __IO uint32_t IER; /*!< DCACHE interrupt enable register, Address offset: 0x08 */
+ __IO uint32_t FCR; /*!< DCACHE Flag clear register, Address offset: 0x0C */
+ __IO uint32_t RHMONR; /*!< DCACHE Read hit monitor register, Address offset: 0x10 */
+ __IO uint32_t RMMONR; /*!< DCACHE Read miss monitor register, Address offset: 0x14 */
+ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */
+ __IO uint32_t WHMONR; /*!< DCACHE Write hit monitor register, Address offset: 0x20 */
+ __IO uint32_t WMMONR; /*!< DCACHE Write miss monitor register, Address offset: 0x24 */
+ __IO uint32_t CMDRSADDRR; /*!< DCACHE Command Start Address register, Address offset: 0x28 */
+ __IO uint32_t CMDREADDRR; /*!< DCACHE Command End Address register, Address offset: 0x2C */
+} DCACHE_TypeDef;
+
+/**
+ * @brief PSSI
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */
+ __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */
+ __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */
+ __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */
+ __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */
+ __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */
+ __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */
+ __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */
+} PSSI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */
+ __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */
+ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */
+ __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */
+ __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */
+ __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */
+ __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */
+ __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */
+ __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */
+ uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */
+} TIM_TypeDef;
+
+/**
+ * @brief LPTIMER
+ */
+typedef struct
+{
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
+ __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
+ __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
+ __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */
+ __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */
+ __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */
+ __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */
+ __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */
+ __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */
+} LPTIM_TypeDef;
+
+/**
+ * @brief Comparator
+ */
+typedef struct
+{
+ __IO uint32_t CSR; /*!< Comparator control/status register , Address offset: 0x00 */
+} COMP_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */
+ __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */
+} COMP_Common_TypeDef;
+
+/**
+ * @brief Operational Amplifier (OPAMP)
+ */
+typedef struct
+{
+ __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
+ __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
+ __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
+} OPAMP_TypeDef;
+
+/*Aliases */
+#define OPAMP_Common_TypeDef OPAMP_TypeDef
+
+/**
+ * @brief MDF/ADF
+ */
+typedef struct
+{
+ __IO uint32_t GCR; /*!< MDF Global Control register, Address offset: 0x00 */
+ __IO uint32_t CKGCR; /*!< MDF Clock Generator Control Register, Address offset: 0x04 */
+ uint32_t RESERVED1[6]; /*!< Reserved, 0x08-0x1C */
+ __IO uint32_t OR; /*!< MDF Option Register, Address offset: 0x20 */
+}MDF_TypeDef;
+
+/**
+ * @brief MDF/ADF filter
+ */
+typedef struct
+{
+ __IO uint32_t SITFCR; /*!< MDF Serial Interface Control Register, Address offset: 0x80 */
+ __IO uint32_t BSMXCR; /*!< MDF Bitstream Matrix Control Register, Address offset: 0x84 */
+ __IO uint32_t DFLTCR; /*!< MDF Digital Filter Control Register, Address offset: 0x88 */
+ __IO uint32_t DFLTCICR; /*!< MDF MCIC Configuration Register, Address offset: 0x8C */
+ __IO uint32_t DFLTRSFR; /*!< MDF Reshape Filter Configuration Register, Address offset: 0x90 */
+ __IO uint32_t DFLTINTR; /*!< MDF Integrator Configuration Register, Address offset: 0x94 */
+ __IO uint32_t OLDCR; /*!< MDF Out-Of Limit Detector Control Register, Address offset: 0x98 */
+ __IO uint32_t OLDTHLR; /*!< MDF OLD Threshold Low Register, Address offset: 0x9C */
+ __IO uint32_t OLDTHHR; /*!< MDF OLD Threshold High Register, Address offset: 0xA0 */
+ __IO uint32_t DLYCR; /*!< MDF Delay control Register, Address offset: 0xA4 */
+ __IO uint32_t SCDCR; /*!< MDF short circuit detector control Register, Address offset: 0xA8 */
+ __IO uint32_t DFLTIER; /*!< MDF DFLT Interrupt enable Register, Address offset: 0xAC */
+ __IO uint32_t DFLTISR; /*!< MDF DFLT Interrupt status Register, Address offset: 0xB0 */
+ __IO uint32_t OECCR; /*!< MDF Offset Error Compensation Control Register, Address offset: 0xB4 */
+ __IO uint32_t SADCR; /*!< MDF SAD Control Register, Address offset: 0xB8 */
+ __IO uint32_t SADCFGR; /*!< MDF SAD configuration register, Address offset: 0xBC */
+ __IO uint32_t SADSDLVR; /*!< MDF SAD Sound level Register, Address offset: 0xC0 */
+ __IO uint32_t SADANLVR; /*!< MDF SAD Ambient Noise level Register, Address offset: 0xC4 */
+ uint32_t RESERVED1[9]; /*!< Reserved, 0xC8-0xE8 */
+ __IO uint32_t SNPSDR; /*!< MDF Snapshot Data Register, Address offset: 0xEC */
+ __IO uint32_t DFLTDR; /*!< MDF Digital Filter Data Register, Address offset: 0xF0 */
+} MDF_Filter_TypeDef;
+
+/**
+ * @brief OCTO Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< OCTOSPI Control register, Address offset: 0x000 */
+ uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */
+ __IO uint32_t DCR1; /*!< OCTOSPI Device Configuration register 1, Address offset: 0x008 */
+ __IO uint32_t DCR2; /*!< OCTOSPI Device Configuration register 2, Address offset: 0x00C */
+ __IO uint32_t DCR3; /*!< OCTOSPI Device Configuration register 3, Address offset: 0x010 */
+ __IO uint32_t DCR4; /*!< OCTOSPI Device Configuration register 4, Address offset: 0x014 */
+ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */
+ __IO uint32_t SR; /*!< OCTOSPI Status register, Address offset: 0x020 */
+ __IO uint32_t FCR; /*!< OCTOSPI Flag Clear register, Address offset: 0x024 */
+ uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */
+ __IO uint32_t DLR; /*!< OCTOSPI Data Length register, Address offset: 0x040 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */
+ __IO uint32_t AR; /*!< OCTOSPI Address register, Address offset: 0x048 */
+ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */
+ __IO uint32_t DR; /*!< OCTOPSI Data register, Address offset: 0x050 */
+ uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */
+ __IO uint32_t PSMKR; /*!< OCTOSPI Polling Status Mask register, Address offset: 0x080 */
+ uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */
+ __IO uint32_t PSMAR; /*!< OCTOSPI Polling Status Match register, Address offset: 0x088 */
+ uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */
+ __IO uint32_t PIR; /*!< OCTOSPI Polling Interval register, Address offset: 0x090 */
+ uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */
+ __IO uint32_t CCR; /*!< OCTOSPI Communication Configuration register, Address offset: 0x100 */
+ uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */
+ __IO uint32_t TCR; /*!< OCTOSPI Timing Configuration register, Address offset: 0x108 */
+ uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */
+ __IO uint32_t IR; /*!< OCTOSPI Instruction register, Address offset: 0x110 */
+ uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */
+ __IO uint32_t ABR; /*!< OCTOSPI Alternate Bytes register, Address offset: 0x120 */
+ uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */
+ __IO uint32_t LPTR; /*!< OCTOSPI Low Power Timeout register, Address offset: 0x130 */
+ uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */
+ __IO uint32_t WPCCR; /*!< OCTOSPI Wrap Communication Configuration register, Address offset: 0x140 */
+ uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */
+ __IO uint32_t WPTCR; /*!< OCTOSPI Wrap Timing Configuration register, Address offset: 0x148 */
+ uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */
+ __IO uint32_t WPIR; /*!< OCTOSPI Wrap Instruction register, Address offset: 0x150 */
+ uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */
+ __IO uint32_t WPABR; /*!< OCTOSPI Wrap Alternate Bytes register, Address offset: 0x160 */
+ uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */
+ __IO uint32_t WCCR; /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */
+ uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */
+ __IO uint32_t WTCR; /*!< OCTOSPI Write Timing Configuration register, Address offset: 0x188 */
+ uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */
+ __IO uint32_t WIR; /*!< OCTOSPI Write Instruction register, Address offset: 0x190 */
+ uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */
+ __IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */
+ uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */
+ __IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */
+} OCTOSPI_TypeDef;
+
+/**
+ * @brief OTFDEC register
+ */
+typedef struct
+{
+ __IO uint32_t REG_CONFIGR; /*!< OTFDEC Region Configuration register, Address offset: 0x20 + 0x30 * (x -1) (x = 1 to 4) */
+ __IO uint32_t REG_START_ADDR; /*!< OTFDEC Region Start Address register, Address offset: 0x24 + 0x30 * (x -1) (x = 1 to 4) */
+ __IO uint32_t REG_END_ADDR; /*!< OTFDEC Region End Address register, Address offset: 0x28 + 0x30 * (x -1) (x = 1 to 4) */
+ __IO uint32_t REG_NONCER0; /*!< OTFDEC Region Nonce register 0, Address offset: 0x2C + 0x30 * (x -1) (x = 1 to 4) */
+ __IO uint32_t REG_NONCER1; /*!< OTFDEC Region Nonce register 1, Address offset: 0x30 + 0x30 * (x -1) (x = 1 to 4) */
+ __IO uint32_t REG_KEYR0; /*!< OTFDEC Region Key register 0, Address offset: 0x34 + 0x30 * (x -1) (x = 1 to 4) */
+ __IO uint32_t REG_KEYR1; /*!< OTFDEC Region Key register 1, Address offset: 0x38 + 0x30 * (x -1) (x = 1 to 4) */
+ __IO uint32_t REG_KEYR2; /*!< OTFDEC Region Key register 2, Address offset: 0x3C + 0x30 * (x -1) (x = 1 to 4) */
+ __IO uint32_t REG_KEYR3; /*!< OTFDEC Region Key register 3, Address offset: 0x40 + 0x30 * (x -1) (x = 1 to 4) */
+} OTFDEC_Region_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< OTFDEC Control register, Address offset: 0x000 */
+ uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x004-0x00C */
+ __IO uint32_t PRIVCFGR; /*!< OTFDEC Privileged access control Configuration register, Address offset: 0x010 */
+ uint32_t RESERVED2[187]; /*!< Reserved, Address offset: 0x014-0x2FC */
+ __IO uint32_t ISR; /*!< OTFDEC Interrupt Status register, Address offset: 0x300 */
+ __IO uint32_t ICR; /*!< OTFDEC Interrupt Clear register, Address offset: 0x304 */
+ __IO uint32_t IER; /*!< OTFDEC Interrupt Enable register, Address offset: 0x308 */
+} OTFDEC_TypeDef;
+
+/**
+ * @brief OCTO Serial Peripheral Interface IO Manager
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< OCTOSPI IO Manager Control register, Address offset: 0x00 */
+ __IO uint32_t PCR[8]; /*!< OCTOSPI IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */
+} OCTOSPIM_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */
+ __IO uint32_t VOSR; /*!< PWR voltage scaling register, Address offset: 0x0C */
+ __IO uint32_t SVMCR; /*!< PWR supply voltage monitoring control register, Address offset: 0x10 */
+ __IO uint32_t WUCR1; /*!< PWR wakeup control register 1, Address offset: 0x14 */
+ __IO uint32_t WUCR2; /*!< PWR wakeup control register 2, Address offset: 0x18 */
+ __IO uint32_t WUCR3; /*!< PWR wakeup control register 3, Address offset: 0x1C */
+ __IO uint32_t BDCR1; /*!< PWR backup domain control register 1, Address offset: 0x20 */
+ __IO uint32_t BDCR2; /*!< PWR backup domain control register 2, Address offset: 0x24 */
+ __IO uint32_t DBPR; /*!< PWR disable backup domain register, Address offset: 0x28 */
+ __IO uint32_t UCPDR; /*!< PWR USB Type-C and Power Delivery register, Address offset: 0x2C */
+ __IO uint32_t SECCFGR; /*!< PWR Security configuration register, Address offset: 0x30 */
+ __IO uint32_t PRIVCFGR; /*!< PWR privilege control register, Address offset: 0x34 */
+ __IO uint32_t SR; /*!< PWR status register, Address offset: 0x38 */
+ __IO uint32_t SVMSR; /*!< PWR supply voltage monitoring status register, Address offset: 0x3C */
+ __IO uint32_t BDSR; /*!< PWR backup domain status register, Address offset: 0x40 */
+ __IO uint32_t WUSR; /*!< PWR wakeup status register, Address offset: 0x44 */
+ __IO uint32_t WUSCR; /*!< PWR wakeup status clear register, Address offset: 0x48 */
+ __IO uint32_t APCR; /*!< PWR apply pull configuration register, Address offset: 0x4C */
+ __IO uint32_t PUCRA; /*!< Power Port A pull-up control register, Address offset: 0x50 */
+ __IO uint32_t PDCRA; /*!< Power Port A pull-down control register, Address offset: 0x54 */
+ __IO uint32_t PUCRB; /*!< Power Port B pull-up control register, Address offset: 0x58 */
+ __IO uint32_t PDCRB; /*!< Power Port B pull-down control register, Address offset: 0x5C */
+ __IO uint32_t PUCRC; /*!< Power Port C pull-up control register, Address offset: 0x60 */
+ __IO uint32_t PDCRC; /*!< Power Port C pull-down control register, Address offset: 0x64 */
+ __IO uint32_t PUCRD; /*!< Power Port D pull-up control register, Address offset: 0x68 */
+ __IO uint32_t PDCRD; /*!< Power Port D pull-down control register, Address offset: 0x6C */
+ __IO uint32_t PUCRE; /*!< Power Port E pull-up control register, Address offset: 0x70 */
+ __IO uint32_t PDCRE; /*!< Power Port E pull-down control register, Address offset: 0x74 */
+ __IO uint32_t PUCRF; /*!< Power Port F pull-up control register, Address offset: 0x78 */
+ __IO uint32_t PDCRF; /*!< Power Port F pull-down control register, Address offset: 0x7C */
+ __IO uint32_t PUCRG; /*!< Power Port G pull-up control register, Address offset: 0x80 */
+ __IO uint32_t PDCRG; /*!< Power Port G pull-down control register, Address offset: 0x84 */
+ __IO uint32_t PUCRH; /*!< Power Port H pull-up control register, Address offset: 0x88 */
+ __IO uint32_t PDCRH; /*!< Power Port H pull-down control register, Address offset: 0x8C */
+ __IO uint32_t PUCRI; /*!< Power Port I pull-up control register, Address offset: 0x90 */
+ __IO uint32_t PDCRI; /*!< Power Port I pull-down control register, Address offset: 0x94 */
+} PWR_TypeDef;
+
+/**
+ * @brief SRAMs configuration controller
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */
+ __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */
+ __IO uint32_t SEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */
+ __IO uint32_t DEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */
+ __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */
+ __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */
+ __IO uint32_t WPR2; /*!< SRAM Write Protection Register 2, Address offset: 0x1C */
+ uint32_t RESERVED; /*!< Reserved, Address offset: 0x20 */
+ __IO uint32_t ECCKEY; /*!< SRAM ECC Key Register, Address offset: 0x24 */
+ __IO uint32_t ERKEYR; /*!< SRAM Erase Key Register, Address offset: 0x28 */
+}RAMCFG_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x00 */
+ uint32_t RESERVED0; /*!< Reserved Address offset: 0x04 */
+ __IO uint32_t ICSCR1; /*!< RCC internal clock sources calibration register 1 Address offset: 0x08 */
+ __IO uint32_t ICSCR2; /*!< RCC internal clock sources calibration register 2 Address offset: 0x0C */
+ __IO uint32_t ICSCR3; /*!< RCC internal clock sources calibration register 3 Address offset: 0x10 */
+ __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register Address offset: 0x14 */
+ uint32_t RESERVED1; /*!< Reserved Address offset: 0x18 */
+ __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x1C */
+ __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x20 */
+ __IO uint32_t CFGR3; /*!< RCC clock configuration register 3 Address offset: 0x24 */
+ __IO uint32_t PLL1CFGR; /*!< PLL1 Configuration Register Address offset: 0x28 */
+ __IO uint32_t PLL2CFGR; /*!< PLL2 Configuration Register Address offset: 0x2C */
+ __IO uint32_t PLL3CFGR; /*!< PLL3 Configuration Register Address offset: 0x30 */
+ __IO uint32_t PLL1DIVR; /*!< PLL1 Dividers Configuration Register Address offset: 0x34 */
+ __IO uint32_t PLL1FRACR; /*!< PLL1 Fractional Divider Configuration Register Address offset: 0x38 */
+ __IO uint32_t PLL2DIVR; /*!< PLL2 Dividers Configuration Register Address offset: 0x3C */
+ __IO uint32_t PLL2FRACR; /*!< PLL2 Fractional Divider Configuration Register Address offset: 0x40 */
+ __IO uint32_t PLL3DIVR; /*!< PLL3 Dividers Configuration Register Address offset: 0x44 */
+ __IO uint32_t PLL3FRACR; /*!< PLL3 Fractional Divider Configuration Register Address offset: 0x48 */
+ uint32_t RESERVED2; /*!< Reserved Address offset: 0x4C */
+ __IO uint32_t CIER; /*!< Clock Interrupt Enable Register Address offset: 0x50 */
+ __IO uint32_t CIFR; /*!< Clock Interrupt Flag Register Address offset: 0x54 */
+ __IO uint32_t CICR; /*!< Clock Interrupt Clear Register Address offset: 0x58 */
+ uint32_t RESERVED3; /*!< Reserved Address offset: 0x5C */
+ __IO uint32_t AHB1RSTR; /*!< AHB1 Peripherals Reset Register Address offset: 0x60 */
+ __IO uint32_t AHB2RSTR1; /*!< AHB2 Peripherals Reset Register 1 Address offset: 0x64 */
+ __IO uint32_t AHB2RSTR2; /*!< AHB2 Peripherals Reset Register 2 Address offset: 0x68 */
+ __IO uint32_t AHB3RSTR; /*!< AHB3 Peripherals Reset Register Address offset: 0x6C */
+ uint32_t RESERVED4; /*!< Reserved Address offset: 0x70 */
+ __IO uint32_t APB1RSTR1; /*!< APB1 Peripherals Reset Register 1 Address offset: 0x74 */
+ __IO uint32_t APB1RSTR2; /*!< APB1 Peripherals Reset Register 2 Address offset: 0x78 */
+ __IO uint32_t APB2RSTR; /*!< APB2 Peripherals Reset Register Address offset: 0x7C */
+ __IO uint32_t APB3RSTR; /*!< APB3 Peripherals Reset Register Address offset: 0x80 */
+ uint32_t RESERVED5; /*!< Reserved Address offset: 0x84 */
+ __IO uint32_t AHB1ENR; /*!< AHB1 Peripherals Clock Enable Register Address offset: 0x88 */
+ __IO uint32_t AHB2ENR1; /*!< AHB2 Peripherals Clock Enable Register 1 Address offset: 0x8C */
+ __IO uint32_t AHB2ENR2; /*!< AHB2 Peripherals Clock Enable Register 2 Address offset: 0x90 */
+ __IO uint32_t AHB3ENR; /*!< AHB3 Peripherals Clock Enable Register Address offset: 0x94 */
+ uint32_t RESERVED6; /*!< Reserved Address offset: 0x98 */
+ __IO uint32_t APB1ENR1; /*!< APB1 Peripherals Clock Enable Register 1 Address offset: 0x9C */
+ __IO uint32_t APB1ENR2; /*!< APB1 Peripherals Clock Enable Register 2 Address offset: 0xA0 */
+ __IO uint32_t APB2ENR; /*!< APB2 Peripherals Clock Enable Register Address offset: 0xA4 */
+ __IO uint32_t APB3ENR; /*!< APB3 Peripherals Clock Enable Register Address offset: 0xA8 */
+ uint32_t RESERVED7; /*!< Reserved Address offset: 0xAC */
+ __IO uint32_t AHB1SMENR; /*!< AHB1 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xB0 */
+ __IO uint32_t AHB2SMENR1; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xB4 */
+ __IO uint32_t AHB2SMENR2; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xB8 */
+ __IO uint32_t AHB3SMENR; /*!< AHB3 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xBC */
+ uint32_t RESERVED8; /*!< Reserved Address offset: 0xC0 */
+ __IO uint32_t APB1SMENR1; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xC4 */
+ __IO uint32_t APB1SMENR2; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xC8 */
+ __IO uint32_t APB2SMENR; /*!< APB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xCC */
+ __IO uint32_t APB3SMENR; /*!< APB3 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xD0 */
+ uint32_t RESERVED9; /*!< Reserved Address offset: 0xD4 */
+ __IO uint32_t SRDAMR; /*!< SRD Autonomous Mode Register Address offset: 0xD8 */
+ uint32_t RESERVED10; /*!< Reserved, Address offset: 0xDC */
+ __IO uint32_t CCIPR1; /*!< IPs Clocks Configuration Register 1 Address offset: 0xE0 */
+ __IO uint32_t CCIPR2; /*!< IPs Clocks Configuration Register 2 Address offset: 0xE4 */
+ __IO uint32_t CCIPR3; /*!< IPs Clocks Configuration Register 3 Address offset: 0xE8 */
+ uint32_t RESERVED11; /*!< Reserved, Address offset: 0xEC */
+ __IO uint32_t BDCR; /*!< Backup Domain Control Register Address offset: 0xF0 */
+ __IO uint32_t CSR; /*!< V33 Clock Control & Status Register Address offset: 0xF4 */
+ uint32_t RESERVED[6]; /*!< Reserved Address offset: 0xF8 */
+ __IO uint32_t SECCFGR; /*!< RCC secure configuration register Address offset: 0x110 */
+ __IO uint32_t PRIVCFGR; /*!< RCC privilege configuration register Address offset: 0x114 */
+} RCC_TypeDef;
+
+/**
+ * @brief PKA
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */
+ __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */
+ uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */
+ __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */
+} PKA_TypeDef;
+
+/*
+* @brief RTC Specific device feature definitions
+*/
+#define RTC_BKP_NB 32U
+#define RTC_TAMP_NB 8U
+
+/**
+ * @brief Real-Time Clock
+ */
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */
+ __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */
+ __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */
+ __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */
+ __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */
+ __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */
+ __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */
+ __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */
+ uint32_t RESERVED4[4];/*!< Reserved, Address offset: 0x58 */
+ __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */
+ __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */
+} RTC_TypeDef;
+
+/**
+ * @brief Tamper and backup registers
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */
+ __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */
+ __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */
+ __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */
+ __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */
+ __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */
+ __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */
+ __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */
+ uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */
+ __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */
+ __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */
+ __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */
+ __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register,Address offset: 0x38 */
+ __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */
+ __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */
+ uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x43 -- 0x50 */
+ __IO uint32_t ERCFGR; /*!< TAMP erase configuration register, Address offset: 0x54 */
+ uint32_t RESERVED2[42]; /*!< Reserved, Address offset: 0x58 -- 0xFC */
+ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */
+ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */
+ __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */
+ __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */
+ __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */
+ __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */
+ __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */
+ __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */
+ __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */
+ __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */
+ __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */
+ __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */
+ __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */
+ __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */
+ __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */
+ __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */
+ __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */
+ __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */
+ __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */
+ __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */
+ __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */
+ __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */
+ __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */
+ __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */
+ __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */
+ __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */
+ __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */
+ __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */
+ __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */
+ __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */
+ __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */
+ __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */
+} TAMP_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
+ __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
+ __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
+ __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */
+ __IO uint32_t AUTOCR; /*!< USART Autonomous mode control register Address offset: 0x30 */
+} USART_TypeDef;
+
+/**
+ * @brief Serial Audio Interface
+ */
+typedef struct
+{
+ __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
+ uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */
+ __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
+ __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
+} SAI_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
+ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
+ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
+ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
+ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+typedef struct
+{
+ __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
+ __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */
+ __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */
+ __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */
+ __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */
+ __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */
+ __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */
+ __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */
+ uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */
+ __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */
+ uint32_t RESERVED2[16];/*!< RESERVED2, Address offset: 0x30 - 0x6C */
+ __IO uint32_t UCPD; /*!< SYSCFG USB Type C and Power delivery register Address offset: 0x70 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Secure digital input/output Interface
+ */
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
+ __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
+ __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
+ __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
+ __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
+ __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
+ __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
+ __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
+ __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */
+ uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */
+ __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */
+ __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */
+ __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x60 */
+ __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */
+ __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */
+ uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */
+ __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
+} SDMMC_TypeDef;
+
+
+
+/**
+ * @brief Delay Block DLYB
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */
+ __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */
+} DLYB_TypeDef;
+
+/**
+ * @brief UCPD
+ */
+typedef struct
+{
+ __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */
+ __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */
+ uint32_t RESERVED0; /*!< Reserved Address offset: 0x08 */
+ __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */
+ __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */
+ __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */
+ __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */
+ __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */
+ __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */
+ __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */
+ __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */
+ __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */
+ __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */
+ __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */
+ __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */
+} UCPD_TypeDef;
+
+/**
+ * @brief USB_OTG_Core_register
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register, Address offset: 000h */
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register, Address offset: 004h */
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register, Address offset: 008h */
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register, Address offset: 00Ch */
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register, Address offset: 010h */
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register, Address offset: 014h */
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register, Address offset: 018h */
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register, Address offset: 01Ch */
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register, Address offset: 020h */
+ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register, Address offset: 024h */
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register, Address offset: 028h */
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg, Address offset: 02Ch */
+ __IO uint32_t Reserved30[2]; /*!< Reserved, Address offset: 030h */
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register, Address offset: 038h */
+ __IO uint32_t CID; /*!< User ID Register, Address offset: 03Ch */
+ __IO uint32_t GSNPSID; /*!< USB_OTG core ID, Address offset: 040h */
+ __IO uint32_t GHWCFG1; /*!< User HW config1, Address offset: 044h */
+ __IO uint32_t GHWCFG2; /*!< User HW config2, Address offset: 048h */
+ __IO uint32_t GHWCFG3; /*!< User HW config3, Address offset: 04Ch */
+ __IO uint32_t Reserved6; /*!< Reserved, Address offset: 050h */
+ __IO uint32_t GLPMCFG; /*!< LPM Register, Address offset: 054h */
+ __IO uint32_t GPWRDN; /*!< Power Down Register, Address offset: 058h */
+ __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register, Address offset: 05Ch */
+ __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register, Address offset: 60Ch */
+ __IO uint32_t Reserved43[39]; /*!< Reserved, Address offset: 058h */
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg, Address offset: 100h */
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 104h */
+} USB_OTG_GlobalTypeDef;
+
+/**
+ * @brief USB_OTG_device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /*!< dev Configuration Register, Address offset: 800h */
+ __IO uint32_t DCTL; /*!< dev Control Register, Address offset: 804h */
+ __IO uint32_t DSTS; /*!< dev Status Register (RO), Address offset: 808h */
+ uint32_t Reserved0C; /*!< Reserved, Address offset: 80Ch */
+ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask, Address offset: 810h */
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask, Address offset: 814h */
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg, Address offset: 818h */
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask, Address offset: 81Ch */
+ uint32_t Reserved20; /*!< Reserved, Address offset: 820h */
+ uint32_t Reserved9; /*!< Reserved, Address offset: 824h */
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register, Address offset: 828h */
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register, Address offset: 82Ch */
+ __IO uint32_t DTHRCTL; /*!< dev threshold, Address offset: 830h */
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk, Address offset: 834h */
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt, Address offset: 838h */
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk, Address offset: 83Ch */
+ uint32_t Reserved40; /*!< dedicated EP mask, Address offset: 840h */
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask, Address offset: 844h */
+ uint32_t Reserved44[15]; /*!< Reserved, Address offset: 844-87Ch */
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk, Address offset: 884h */
+} USB_OTG_DeviceTypeDef;
+
+
+/**
+ * @brief USB_OTG_IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Register, Address offset: 900h + (ep_num * 20h) + 00h */
+ __IO uint32_t Reserved04; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 04h */
+ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Register, Address offset: 900h + (ep_num * 20h) + 08h */
+ __IO uint32_t Reserved0C; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size Register, Address offset: 900h + (ep_num * 20h) + 10h */
+ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Register, Address offset: 900h + (ep_num * 20h) + 14h */
+ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Register, Address offset: 900h + (ep_num * 20h) + 18h */
+ __IO uint32_t Reserved18; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Register, Address offset: B00h + (ep_num * 20h) + 00h */
+ __IO uint32_t Reserved04; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 04h */
+ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Register, Address offset: B00h + (ep_num * 20h) + 08h */
+ __IO uint32_t Reserved0C; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size Register, Address offset: B00h + (ep_num * 20h) + 10h */
+ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address Register, Address offset: B00h + (ep_num * 20h) + 14h */
+ __IO uint32_t Reserved18[2]; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 18h */
+} USB_OTG_OUTEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /*!< Host Configuration Register, Address offset: 400h */
+ __IO uint32_t HFIR; /*!< Host Frame Interval Register, Address offset: 404h */
+ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining, Address offset: 408h */
+ uint32_t Reserved40C; /*!< Reserved, Address offset: 40Ch */
+ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status, Address offset: 410h */
+ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register, Address offset: 414h */
+ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask, Address offset: 418h */
+} USB_OTG_HostTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register, Address offset: 500h */
+ __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register, Address offset: 504h */
+ __IO uint32_t HCINT; /*!< Host Channel Interrupt Register, Address offset: 508h */
+ __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register, Address offset: 50Ch */
+ __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register, Address offset: 510h */
+ __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register, Address offset: 514h */
+ uint32_t Reserved[2]; /*!< Reserved, Address offset: 518h */
+} USB_OTG_HostChannelTypeDef;
+
+/**
+ * @brief FD Controller Area Network
+ */
+typedef struct
+{
+ __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */
+ __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */
+ uint32_t RESERVED1; /*!< Reserved, 0x008 */
+ __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */
+ __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */
+ __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */
+ __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */
+ __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */
+ __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */
+ __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */
+ __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */
+ __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */
+ uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */
+ __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */
+ __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */
+ __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */
+ uint32_t RESERVED3; /*!< Reserved, 0x04C */
+ __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */
+ __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */
+ __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */
+ __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */
+ uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */
+ __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */
+ __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */
+ __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */
+ uint32_t RESERVED5; /*!< Reserved, 0x08C */
+ __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */
+ __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */
+ __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */
+ __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */
+ uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */
+ __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */
+ __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */
+ __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */
+ __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */
+ __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */
+ __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */
+ __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */
+ __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */
+ __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */
+ __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */
+ __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */
+} FDCAN_GlobalTypeDef;
+
+/**
+ * @brief FD Controller Area Network Configuration
+ */
+typedef struct
+{
+ __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */
+ uint32_t RESERVED1[128];/*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */
+ __IO uint32_t OPTR; /*!< FDCAN option register, Address offset: 0x100 + 0x204 */
+ uint32_t RESERVED2[58];/*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */
+ __IO uint32_t HWCFG; /*!< FDCAN hardware configuration register, Address offset: 0x100 + 0x2F0 */
+ __IO uint32_t VERR; /*!< FDCAN IP version register, Address offset: 0x100 + 0x2F4 */
+ __IO uint32_t IPIDR; /*!< FDCAN IP ID register, Address offset: 0x100 + 0x2F8 */
+ __IO uint32_t SIDR; /*!< FDCAN size ID register, Address offset: 0x100 + 0x2FC */
+} FDCAN_Config_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller
+ */
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+ __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register, Address offset: 0x20 */
+} FMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank1E
+ */
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank3
+ */
+typedef struct
+{
+ __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
+ __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
+ __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
+ __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
+ uint32_t RESERVED0; /*!< Reserved, 0x90 */
+ __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
+} FMC_Bank3_TypeDef;
+
+/**
+ * @brief VREFBUF
+ */
+typedef struct
+{
+ __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
+ __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
+} VREFBUF_TypeDef;
+
+/**
+ * @brief ADC
+ */
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
+ __IO uint32_t CFGR1; /*!< ADC Configuration register, Address offset: 0x0C */
+ __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ /* Specific to ADC 14Bits*/
+ __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */
+ __IO uint32_t AWD1TR; /*!< ADC watchdog threshold register, Address offset: 0x20 */ /* Specific to ADC 12Bits*/
+ __IO uint32_t AWD2TR; /*!< ADC watchdog threshold register, Address offset: 0x24 */ /* Specific to ADC 12Bits*/
+ __IO uint32_t CHSELR; /*!< ADC channel select register, Address offset: 0x28 */ /* Specific to ADC 12Bits*/
+ __IO uint32_t AWD3TR; /*!< ADC watchdog threshold register, Address offset: 0x2C */ /* Specific to ADC 12Bits*/
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ /* Specific to ADC 14Bits*/
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ /* Specific to ADC 14Bits*/
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ /* Specific to ADC 14Bits*/
+ __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ /* Specific to ADC 14Bits*/
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
+ __IO uint32_t PW; /*!< ADC power register, Address offset: 0x44 */
+ uint32_t RESERVED1; /*!< Reserved, 0x048 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ /* Specific to ADC 14Bits*/
+ uint32_t RESERVED2[4]; /*!< Reserved, 0x050 - 0x05C */
+ __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ /* Specific to ADC 14Bits*/
+ __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ /* Specific to ADC 14Bits*/
+ __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ /* Specific to ADC 14Bits*/
+ __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ /* Specific to ADC 14Bits*/
+ __IO uint32_t GCOMP; /*!< ADC gain compensation register, Address offset: 0x70 */ /* Specific to ADC 14Bits*/
+ uint32_t RESERVED3[3]; /*!< Reserved, 0x074 - 0x07C */
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ /* Specific to ADC 14Bits*/
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ /* Specific to ADC 14Bits*/
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ /* Specific to ADC 14Bits*/
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ /* Specific to ADC 14Bits*/
+ uint32_t RESERVED4[4]; /*!< Reserved, 0x090 - 0x09C */
+ __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
+ __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
+ __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0xA8 */ /* Specific to ADC 14Bits*/
+ __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0xAC */ /* Specific to ADC 14Bits*/
+ __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ /* Specific to ADC 14Bits*/
+ __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ /* Specific to ADC 14Bits*/
+ __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ /* Specific to ADC 14Bits*/
+ __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ /* Specific to ADC 14Bits*/
+ __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ /* Specific to ADC 14Bits*/
+ __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */
+ __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ /* Specific to ADC 14Bits*/
+ uint32_t RESERVED5; /*!< Reserved, 0x0CC */
+ __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0xD0 */ /* Specific to ADC 12Bits*/
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: 0x308 */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief CORDIC
+ */
+typedef struct
+{
+ __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */
+ __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */
+ __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */
+} CORDIC_TypeDef;
+
+/**
+ * @brief IWDG
+ */
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
+ __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */
+} IWDG_TypeDef;
+
+/**
+ * @brief SPI
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
+ __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */
+ __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */
+ __IO uint32_t IER; /*!< SPI Interrupt Enable register, Address offset: 0x10 */
+ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x14 */
+ __IO uint32_t IFCR; /*!< SPI Interrupt/Status Flags Clear register, Address offset: 0x18 */
+ __IO uint32_t AUTOCR; /*!< SPI Autonomous Mode Control register, Address offset: 0x1C */
+ __IO uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */
+ uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */
+ __IO uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */
+ uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */
+ __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */
+ __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */
+ __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */
+ __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */
+} SPI_TypeDef;
+
+/**
+ * @brief Touch Sensing Controller (TSC)
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
+ __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
+ __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
+ __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
+ __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
+ __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
+ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
+ __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
+ __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
+} TSC_TypeDef;
+
+/**
+ * @brief WWDG
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/*@}*/ /* end of group STM32U5xx_peripherals */
+
+
+/* -------- End of section using anonymous unions and disabling warnings -------- */
+#if defined (__CC_ARM)
+ #pragma pop
+#elif defined (__ICCARM__)
+ /* leave anonymous unions enabled */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+#elif defined (__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+ #pragma warning restore
+#elif defined (__CSMC__)
+ /* anonymous unions are enabled by default */
+#else
+ #warning Not supported compiler type
+#endif
+
+
+/* =========================================================================================================================== */
+/* ================ Device Specific Peripheral Address Map ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup STM32U5xx_Peripheral_peripheralAddr
+ * @{
+ */
+
+/* Internal SRAMs size */
+#define SRAM1_SIZE (0x30000UL) /*!< SRAM1=192k */
+#define SRAM2_SIZE (0x10000UL) /*!< SRAM2=64k */
+#define SRAM3_SIZE (0x80000UL) /*!< SRAM3=512k */
+#define SRAM4_SIZE (0x04000UL) /*!< SRAM4=16k */
+
+/* External memories base addresses - Not aliased */
+#define FMC_BASE (0x60000000UL) /*!< FMC base address */
+#define OCTOSPI2_BASE (0x70000000UL) /*!< OCTOSPI2 memories accessible over AHB base address */
+#define OCTOSPI1_BASE (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */
+
+#define FMC_BANK1 FMC_BASE
+#define FMC_BANK1_1 FMC_BANK1
+#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL)
+#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL)
+#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL)
+#define FMC_BANK3 (FMC_BASE + 0x20000000UL)
+
+/* Flash, Peripheral and internal SRAMs base addresses - Non secure */
+#define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (up to 2 MB) non-secure base address */
+#define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (192 KB) non-secure base address */
+#define SRAM2_BASE_NS (0x20030000UL) /*!< SRAM2 (64 KB) non-secure base address */
+#define SRAM3_BASE_NS (0x20040000UL) /*!< SRAM3 (512 KB) non-secure base address */
+#define SRAM4_BASE_NS (0x28000000UL) /*!< SRAM4 (16 KB) non-secure base address */
+#define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address */
+
+/* Peripheral memory map - Non secure */
+#define APB1PERIPH_BASE_NS PERIPH_BASE_NS
+#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL)
+#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL)
+#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL)
+#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL)
+#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06020000UL)
+
+/*!< APB1 Non secure peripherals */
+#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL)
+#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL)
+#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL)
+#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL)
+#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL)
+#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL)
+#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL)
+#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL)
+#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL)
+#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL)
+#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL)
+#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL)
+#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL)
+#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL)
+#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL)
+#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL)
+#define I2C4_BASE_NS (APB1PERIPH_BASE_NS + 0x8400UL)
+#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL)
+#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL)
+#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA500UL)
+#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xAC00UL)
+#define UCPD1_BASE_NS (APB1PERIPH_BASE_NS + 0xDC00UL)
+
+/*!< APB2 Non secure peripherals */
+#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL)
+#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL)
+#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL)
+#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL)
+#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL)
+#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL)
+#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL)
+#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5400UL)
+#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x004UL)
+#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x024UL)
+#define SAI2_BASE_NS (APB2PERIPH_BASE_NS + 0x5800UL)
+#define SAI2_Block_A_BASE_NS (SAI2_BASE_NS + 0x004UL)
+#define SAI2_Block_B_BASE_NS (SAI2_BASE_NS + 0x024UL)
+
+/*!< APB3 Non secure peripherals */
+#define SYSCFG_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL)
+#define SPI3_BASE_NS (APB3PERIPH_BASE_NS + 0x2000UL)
+#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x2400UL)
+#define I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x2800UL)
+#define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x4400UL)
+#define LPTIM3_BASE_NS (APB3PERIPH_BASE_NS + 0x4800UL)
+#define LPTIM4_BASE_NS (APB3PERIPH_BASE_NS + 0x4C00UL)
+#define OPAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL)
+#define OPAMP1_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL)
+#define OPAMP2_BASE_NS (APB3PERIPH_BASE_NS + 0x5010UL)
+#define COMP12_BASE_NS (APB3PERIPH_BASE_NS + 0x5400UL)
+#define COMP1_BASE_NS (COMP12_BASE_NS)
+#define COMP2_BASE_NS (COMP12_BASE_NS + 0x04UL)
+#define VREFBUF_BASE_NS (APB3PERIPH_BASE_NS + 0x7400UL)
+#define RTC_BASE_NS (APB3PERIPH_BASE_NS + 0x7800UL)
+#define TAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x7C00UL)
+
+/*!< AHB1 Non secure peripherals */
+#define GPDMA1_BASE_NS (AHB1PERIPH_BASE_NS)
+#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL)
+#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL)
+#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL)
+#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL)
+#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL)
+#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL)
+#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL)
+#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL)
+#define GPDMA1_Channel8_BASE_NS (GPDMA1_BASE_NS + 0x0450UL)
+#define GPDMA1_Channel9_BASE_NS (GPDMA1_BASE_NS + 0x04D0UL)
+#define GPDMA1_Channel10_BASE_NS (GPDMA1_BASE_NS + 0x0550UL)
+#define GPDMA1_Channel11_BASE_NS (GPDMA1_BASE_NS + 0x05D0UL)
+#define GPDMA1_Channel12_BASE_NS (GPDMA1_BASE_NS + 0x0650UL)
+#define GPDMA1_Channel13_BASE_NS (GPDMA1_BASE_NS + 0x06D0UL)
+#define GPDMA1_Channel14_BASE_NS (GPDMA1_BASE_NS + 0x0750UL)
+#define GPDMA1_Channel15_BASE_NS (GPDMA1_BASE_NS + 0x07D0UL)
+#define CORDIC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01000UL)
+#define FMAC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01400UL)
+#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL)
+#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL)
+#define TSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x04000UL)
+#define MDF1_BASE_NS (AHB1PERIPH_BASE_NS + 0x05000UL)
+#define MDF1_Filter0_BASE_NS (MDF1_BASE_NS + 0x80UL)
+#define MDF1_Filter1_BASE_NS (MDF1_BASE_NS + 0x100UL)
+#define MDF1_Filter2_BASE_NS (MDF1_BASE_NS + 0x180UL)
+#define MDF1_Filter3_BASE_NS (MDF1_BASE_NS + 0x200UL)
+#define MDF1_Filter4_BASE_NS (MDF1_BASE_NS + 0x280UL)
+#define MDF1_Filter5_BASE_NS (MDF1_BASE_NS + 0x300UL)
+#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL)
+#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS)
+#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL)
+#define RAMCFG_SRAM3_BASE_NS (RAMCFG_BASE_NS + 0x0080UL)
+#define RAMCFG_SRAM4_BASE_NS (RAMCFG_BASE_NS + 0x00C0UL)
+#define RAMCFG_BKPRAM_BASE_NS (RAMCFG_BASE_NS + 0x0100UL)
+#define DMA2D_BASE_NS (AHB1PERIPH_BASE_NS + 0x0B000UL)
+#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL)
+#define DCACHE1_BASE_NS (AHB1PERIPH_BASE_NS + 0x11400UL)
+#define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL)
+#define GTZC_TZIC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12800UL)
+#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL)
+#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL)
+#define GTZC_MPCBB3_BASE_NS (AHB1PERIPH_BASE_NS + 0x13400UL)
+#define BKPSRAM_BASE_NS (AHB1PERIPH_BASE_NS + 0x16400UL)
+
+/*!< AHB2 Non secure peripherals */
+#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000UL)
+#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL)
+#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL)
+#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00C00UL)
+#define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x01000UL)
+#define GPIOF_BASE_NS (AHB2PERIPH_BASE_NS + 0x01400UL)
+#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x01800UL)
+#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL)
+#define GPIOI_BASE_NS (AHB2PERIPH_BASE_NS + 0x02000UL)
+#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08000UL)
+#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08308UL)
+#define DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL)
+#define PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL)
+#define USB_OTG_FS_BASE_NS (AHB2PERIPH_BASE_NS + 0x20000UL)
+#define AES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0000UL)
+#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL)
+#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL)
+#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL)
+#define SAES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0C00UL)
+#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2000UL)
+#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2400UL)
+#define OCTOSPIM_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xA4000UL) /*!< OCTOSPIO Manager control registers base address */
+#define OTFDEC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA5000UL)
+#define OTFDEC1_REGION1_BASE_NS (OTFDEC1_BASE_NS + 0x20UL)
+#define OTFDEC1_REGION2_BASE_NS (OTFDEC1_BASE_NS + 0x50UL)
+#define OTFDEC1_REGION3_BASE_NS (OTFDEC1_BASE_NS + 0x80UL)
+#define OTFDEC1_REGION4_BASE_NS (OTFDEC1_BASE_NS + 0xB0UL)
+#define OTFDEC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA5400UL)
+#define OTFDEC2_REGION1_BASE_NS (OTFDEC2_BASE_NS + 0x20UL)
+#define OTFDEC2_REGION2_BASE_NS (OTFDEC2_BASE_NS + 0x50UL)
+#define OTFDEC2_REGION3_BASE_NS (OTFDEC2_BASE_NS + 0x80UL)
+#define OTFDEC2_REGION4_BASE_NS (OTFDEC2_BASE_NS + 0xB0UL)
+#define SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8000UL)
+#define SDMMC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8C00UL)
+#define DLYB_SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8400UL)
+#define DLYB_SDMMC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8800UL)
+#define DLYB_OCTOSPI1_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF000UL)
+#define DLYB_OCTOSPI2_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF400UL)
+#define FMC_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB0400UL) /*!< FMC control registers base address */
+#define FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL)
+#define FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL)
+#define FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL)
+#define OCTOSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB1400UL) /*!< OCTOSPI1 control registers base address */
+#define OCTOSPI2_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB2400UL) /*!< OCTOSPI2 control registers base address */
+
+/*!< AHB3 Non secure peripherals */
+#define LPGPIO1_BASE_NS (AHB3PERIPH_BASE_NS)
+#define PWR_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL)
+#define RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL)
+#define ADC4_BASE_NS (AHB3PERIPH_BASE_NS + 0x1000UL)
+#define ADC4_COMMON_BASE_NS (AHB3PERIPH_BASE_NS + 0x1308UL)
+#define DAC1_BASE_NS (AHB3PERIPH_BASE_NS + 0x1800UL)
+#define EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL)
+#define GTZC_TZSC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3000UL)
+#define GTZC_TZIC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3400UL)
+#define GTZC_MPCBB4_BASE_NS (AHB3PERIPH_BASE_NS + 0x3800UL)
+#define ADF1_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL)
+#define ADF1_Filter0_BASE_NS (ADF1_BASE_NS + 0x80UL)
+#define LPDMA1_BASE_NS (AHB3PERIPH_BASE_NS + 0x5000UL)
+#define LPDMA1_Channel0_BASE_NS (LPDMA1_BASE_NS + 0x0050UL)
+#define LPDMA1_Channel1_BASE_NS (LPDMA1_BASE_NS + 0x00D0UL)
+#define LPDMA1_Channel2_BASE_NS (LPDMA1_BASE_NS + 0x0150UL)
+#define LPDMA1_Channel3_BASE_NS (LPDMA1_BASE_NS + 0x01D0UL)
+
+/* Flash, Peripheral and internal SRAMs base addresses - Secure */
+#define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (up to 2 MB) secure base address */
+#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (192 KB) secure base address */
+#define SRAM2_BASE_S (0x30030000UL) /*!< SRAM2 (64 KB) secure base address */
+#define SRAM3_BASE_S (0x30040000UL) /*!< SRAM3 (512 KB) secure base address */
+#define SRAM4_BASE_S (0x38000000UL) /*!< SRAM4 (16 KB) secure base address */
+#define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */
+
+/* Peripheral memory map - Secure */
+#define APB1PERIPH_BASE_S PERIPH_BASE_S
+#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL)
+#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL)
+#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL)
+#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL)
+#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06020000UL)
+
+/*!< APB1 Secure peripherals */
+#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL)
+#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL)
+#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL)
+#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL)
+#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL)
+#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL)
+#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL)
+#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL)
+#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL)
+#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL)
+#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL)
+#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL)
+#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL)
+#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL)
+#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL)
+#define I2C4_BASE_S (APB1PERIPH_BASE_S + 0x8400UL)
+#define CRS_BASE_S (APB1PERIPH_BASE_S + 0x6000UL)
+#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL)
+#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA400UL)
+#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA500UL)
+#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xAC00UL)
+#define UCPD1_BASE_S (APB1PERIPH_BASE_S + 0xDC00UL)
+
+/*!< APB2 Secure peripherals */
+#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL)
+#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL)
+#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x3400UL)
+#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL)
+#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL)
+#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL)
+#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL)
+#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5400UL)
+#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x004UL)
+#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x024UL)
+#define SAI2_BASE_S (APB2PERIPH_BASE_S + 0x5800UL)
+#define SAI2_Block_A_BASE_S (SAI2_BASE_S + 0x004UL)
+#define SAI2_Block_B_BASE_S (SAI2_BASE_S + 0x024UL)
+
+/*!< APB3 Secure peripherals */
+#define SYSCFG_BASE_S (APB3PERIPH_BASE_S + 0x0400UL)
+#define ADC4_BASE_S (AHB3PERIPH_BASE_S + 0x1000UL)
+#define ADC4_COMMON_BASE_S (AHB3PERIPH_BASE_S + 0x1308UL)
+#define SPI3_BASE_S (APB3PERIPH_BASE_S + 0x2000UL)
+#define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x2400UL)
+#define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x2800UL)
+#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4300UL)
+#define LPTIM3_BASE_S (APB3PERIPH_BASE_S + 0x4800UL)
+#define LPTIM4_BASE_S (APB3PERIPH_BASE_S + 0x4C00UL)
+#define OPAMP_BASE_S (APB3PERIPH_BASE_S + 0x5000UL)
+#define OPAMP1_BASE_S (APB3PERIPH_BASE_S + 0x5000UL)
+#define OPAMP2_BASE_S (APB3PERIPH_BASE_S + 0x5010UL)
+#define COMP12_BASE_S (APB3PERIPH_BASE_S + 0x5400UL)
+#define COMP1_BASE_S (COMP12_BASE_S)
+#define COMP2_BASE_S (COMP12_BASE_S + 0x04UL)
+#define VREFBUF_BASE_S (APB3PERIPH_BASE_S + 0x7400UL)
+#define RTC_BASE_S (APB3PERIPH_BASE_S + 0x7800UL)
+#define TAMP_BASE_S (APB3PERIPH_BASE_S + 0x7C00UL)
+
+/*!< AHB1 Secure peripherals */
+#define GPDMA1_BASE_S (AHB1PERIPH_BASE_S)
+#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL)
+#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL)
+#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL)
+#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL)
+#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL)
+#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL)
+#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL)
+#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL)
+#define GPDMA1_Channel8_BASE_S (GPDMA1_BASE_S + 0x0450UL)
+#define GPDMA1_Channel9_BASE_S (GPDMA1_BASE_S + 0x04D0UL)
+#define GPDMA1_Channel10_BASE_S (GPDMA1_BASE_S + 0x0550UL)
+#define GPDMA1_Channel11_BASE_S (GPDMA1_BASE_S + 0x05D0UL)
+#define GPDMA1_Channel12_BASE_S (GPDMA1_BASE_S + 0x0650UL)
+#define GPDMA1_Channel13_BASE_S (GPDMA1_BASE_S + 0x06D0UL)
+#define GPDMA1_Channel14_BASE_S (GPDMA1_BASE_S + 0x0750UL)
+#define GPDMA1_Channel15_BASE_S (GPDMA1_BASE_S + 0x07D0UL)
+#define CORDIC_BASE_S (AHB1PERIPH_BASE_S + 0x01000UL)
+#define FMAC_BASE_S (AHB1PERIPH_BASE_S + 0x01400UL)
+#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL)
+#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL)
+#define TSC_BASE_S (AHB1PERIPH_BASE_S + 0x04000UL)
+#define MDF1_BASE_S (AHB1PERIPH_BASE_S + 0x05000UL)
+#define MDF1_Filter0_BASE_S (MDF1_BASE_S + 0x80UL)
+#define MDF1_Filter1_BASE_S (MDF1_BASE_S + 0x100UL)
+#define MDF1_Filter2_BASE_S (MDF1_BASE_S + 0x180UL)
+#define MDF1_Filter3_BASE_S (MDF1_BASE_S + 0x200UL)
+#define MDF1_Filter4_BASE_S (MDF1_BASE_S + 0x280UL)
+#define MDF1_Filter5_BASE_S (MDF1_BASE_S + 0x300UL)
+#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL)
+#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S)
+#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL)
+#define RAMCFG_SRAM3_BASE_S (RAMCFG_BASE_S + 0x0080UL)
+#define RAMCFG_SRAM4_BASE_S (RAMCFG_BASE_S + 0x00C0UL)
+#define RAMCFG_BKPRAM_BASE_S (RAMCFG_BASE_S + 0x0100UL)
+#define DMA2D_BASE_S (AHB1PERIPH_BASE_S + 0x0B000UL)
+#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL)
+#define DCACHE1_BASE_S (AHB1PERIPH_BASE_S + 0x11400UL)
+#define GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL)
+#define GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL)
+#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL)
+#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL)
+#define GTZC_MPCBB3_BASE_S (AHB1PERIPH_BASE_S + 0x13400UL)
+#define BKPSRAM_BASE_S (AHB1PERIPH_BASE_S + 0x16400UL)
+
+/*!< AHB2 Secure peripherals */
+#define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000UL)
+#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL)
+#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL)
+#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00C00UL)
+#define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x01000UL)
+#define GPIOF_BASE_S (AHB2PERIPH_BASE_S + 0x01400UL)
+#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x01800UL)
+#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL)
+#define GPIOI_BASE_S (AHB2PERIPH_BASE_S + 0x02000UL)
+#define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x08000UL)
+#define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x08308UL)
+#define DCMI_BASE_S (AHB2PERIPH_BASE_S + 0x0C000UL)
+#define PSSI_BASE_S (AHB2PERIPH_BASE_S + 0x0C400UL)
+#define USB_OTG_FS_BASE_S (AHB2PERIPH_BASE_S + 0x20000UL)
+#define AES_BASE_S (AHB2PERIPH_BASE_S + 0xA0000UL)
+#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL)
+#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL)
+#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL)
+#define SAES_BASE_S (AHB2PERIPH_BASE_S + 0xA0C00UL)
+#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0xA2000UL)
+#define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0xA2400UL)
+#define OCTOSPIM_R_BASE_S (AHB2PERIPH_BASE_S + 0xA4000UL) /*!< OCTOSPIM control registers base address */
+#define OTFDEC1_BASE_S (AHB2PERIPH_BASE_S + 0xA5000UL)
+#define OTFDEC1_REGION1_BASE_S (OTFDEC1_BASE_S + 0x20UL)
+#define OTFDEC1_REGION2_BASE_S (OTFDEC1_BASE_S + 0x50UL)
+#define OTFDEC1_REGION3_BASE_S (OTFDEC1_BASE_S + 0x80UL)
+#define OTFDEC1_REGION4_BASE_S (OTFDEC1_BASE_S + 0xB0UL)
+#define OTFDEC2_BASE_S (AHB2PERIPH_BASE_S + 0xA5400UL)
+#define OTFDEC2_REGION1_BASE_S (OTFDEC2_BASE_S + 0x20UL)
+#define OTFDEC2_REGION2_BASE_S (OTFDEC2_BASE_S + 0x50UL)
+#define OTFDEC2_REGION3_BASE_S (OTFDEC2_BASE_S + 0x80UL)
+#define OTFDEC2_REGION4_BASE_S (OTFDEC2_BASE_S + 0xB0UL)
+#define SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8000UL)
+#define SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8C00UL)
+#define DLYB_SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8400UL)
+#define DLYB_SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8800UL)
+#define DLYB_OCTOSPI1_BASE_S (AHB2PERIPH_BASE_S + 0xAF000UL)
+#define DLYB_OCTOSPI2_BASE_S (AHB2PERIPH_BASE_S + 0xAF400UL)
+#define FMC_R_BASE_S (AHB2PERIPH_BASE_S + 0xB0400UL) /*!< FMC control registers base address */
+#define FMC_Bank1_R_BASE_S (FMC_R_BASE_S + 0x0000UL)
+#define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL)
+#define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL)
+#define OCTOSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0xB1400UL) /*!< OCTOSPI1 control registers base address */
+#define OCTOSPI2_R_BASE_S (AHB2PERIPH_BASE_S + 0xB2400UL) /*!< OCTOSPI2 control registers base address */
+
+/*!< AHB3 Secure peripherals */
+#define LPGPIO1_BASE_S (AHB3PERIPH_BASE_S)
+#define PWR_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL)
+#define RCC_BASE_S (AHB3PERIPH_BASE_S + 0x0C00UL)
+#define DAC1_BASE_S (AHB3PERIPH_BASE_S + 0x1800UL)
+#define EXTI_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL)
+#define GTZC_TZSC2_BASE_S (AHB3PERIPH_BASE_S + 0x3000UL)
+#define GTZC_TZIC2_BASE_S (AHB3PERIPH_BASE_S + 0x3400UL)
+#define GTZC_MPCBB4_BASE_S (AHB3PERIPH_BASE_S + 0x3800UL)
+#define ADF1_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL)
+#define ADF1_Filter0_BASE_S (ADF1_BASE_S + 0x80UL)
+#define LPDMA1_BASE_S (AHB3PERIPH_BASE_S + 0x5000UL)
+#define LPDMA1_Channel0_BASE_S (LPDMA1_BASE_S + 0x0050UL)
+#define LPDMA1_Channel1_BASE_S (LPDMA1_BASE_S + 0x00D0UL)
+#define LPDMA1_Channel2_BASE_S (LPDMA1_BASE_S + 0x0150UL)
+#define LPDMA1_Channel3_BASE_S (LPDMA1_BASE_S + 0x01D0UL)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE (0xE0044000UL)
+
+#define PACKAGE_BASE (0x0BFA0500UL) /*!< Package data register base address */
+#define UID_BASE (0x0BFA0700UL) /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE (0x0BFA07A0UL) /*!< Flash size data register base address */
+
+/* Internal Flash OTP Area */
+#define FLASH_OTP_BASE (0x0BFA0000UL) /*!< FLASH OTP (one-time programmable) base address */
+#define FLASH_OTP_SIZE (0x200U) /*!< 512 bytes OTP (one-time programmable) */
+
+/* USB OTG FS registers Base address */
+#define USB_OTG_GLOBAL_BASE (0x0000UL)
+#define USB_OTG_DEVICE_BASE (0x0800UL)
+#define USB_OTG_IN_ENDPOINT_BASE (0x0900UL)
+#define USB_OTG_OUT_ENDPOINT_BASE (0x0B00UL)
+#define USB_OTG_EP_REG_SIZE (0x0020UL)
+#define USB_OTG_HOST_BASE (0x0400UL)
+#define USB_OTG_HOST_PORT_BASE (0x0440UL)
+#define USB_OTG_HOST_CHANNEL_BASE (0x0500UL)
+#define USB_OTG_HOST_CHANNEL_SIZE (0x0020UL)
+#define USB_OTG_PCGCCTL_BASE (0x0E00UL)
+#define USB_OTG_FIFO_BASE (0x1000UL)
+#define USB_OTG_FIFO_SIZE (0x1000UL)
+
+/*!< Root Secure Service Library */
+/************ RSSLIB SAU system Flash region definition constants *************/
+#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0x0BF99E40UL)
+#define RSSLIB_SYS_FLASH_NS_PFUNC_END (0x0BF99EFFUL)
+
+/************ RSSLIB function return constants ********************************/
+#define RSSLIB_ERROR (0xF5F5F5F5UL)
+#define RSSLIB_SUCCESS (0xEAEAEAEAUL)
+
+/*!< RSSLIB pointer function structure address definition */
+#define RSSLIB_PFUNC_BASE RSSLIB_SYS_FLASH_NS_PFUNC_START
+#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE)
+
+/*!< HDP Area constant definition */
+#define RSSLIB_HDP_AREA_Pos (0U)
+#define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos )
+#define RSSLIB_HDP_AREA1_Pos (0U)
+#define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos )
+#define RSSLIB_HDP_AREA2_Pos (1U)
+#define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos )
+
+/**
+ * @brief Prototype of RSSLIB Close and exit HDP Function
+ * @detail This function close the requested hdp area passed in input
+ * parameter and jump to the reset handler present within the
+ * Vector table. The function does not return on successful execution.
+ * @param HdpArea notifies which hdp area to close, can be a combination of
+ * hdpa area 1 and hdp area 2
+ * @param pointer on the vector table containing the reset handler the function
+ * jumps to.
+ * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return.
+ */
+typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr );
+
+
+/**
+ * @brief RSSLib non-secure callable function pointer structure
+ */
+typedef struct
+{
+ __IM uint32_t Reserved[8];
+}NSC_pFuncTypeDef;
+
+/**
+ * @brief RSSLib secure callable function pointer structure
+ */
+typedef struct
+{
+ __IM uint32_t Reserved2[2];
+ __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP; /*!< RSSLIB Bootloader Close and exit HDP Address offset: 0x28 */
+}S_pFuncTypeDef;
+
+/**
+ * @brief RSSLib function pointer structure
+ */
+typedef struct
+{
+ NSC_pFuncTypeDef NSC;
+ S_pFuncTypeDef S;
+}RSSLIB_pFunc_TypeDef;
+
+/** @} */ /* End of group STM32U5xx_Peripheral_peripheralAddr */
+
+
+/* =========================================================================================================================== */
+/* ================ Peripheral declaration ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup STM32U5xx_Peripheral_declaration
+ * @{
+ */
+
+/*!< APB1 Non secure peripherals */
+#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS)
+#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS)
+#define TIM4_NS ((TIM_TypeDef *) TIM4_BASE_NS)
+#define TIM5_NS ((TIM_TypeDef *) TIM5_BASE_NS)
+#define TIM6_NS ((TIM_TypeDef *) TIM6_BASE_NS)
+#define TIM7_NS ((TIM_TypeDef *) TIM7_BASE_NS)
+#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS)
+#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS)
+#define SPI2_NS ((SPI_TypeDef *) SPI2_BASE_NS)
+#define USART2_NS ((USART_TypeDef *) USART2_BASE_NS)
+#define USART3_NS ((USART_TypeDef *) USART3_BASE_NS)
+#define UART4_NS ((USART_TypeDef *) UART4_BASE_NS)
+#define UART5_NS ((USART_TypeDef *) UART5_BASE_NS)
+#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS)
+#define I2C2_NS ((I2C_TypeDef *) I2C2_BASE_NS)
+#define CRS_NS ((CRS_TypeDef *) CRS_BASE_NS)
+#define I2C4_NS ((I2C_TypeDef *) I2C4_BASE_NS)
+#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS)
+#define FDCAN1_NS ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS)
+#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS)
+#define UCPD1_NS ((UCPD_TypeDef *) UCPD1_BASE_NS)
+
+/*!< APB2 Non secure peripherals */
+#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS)
+#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS)
+#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS)
+#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS)
+#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS)
+#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS)
+#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS)
+#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS)
+#define SAI1_Block_A_NS ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS)
+#define SAI1_Block_B_NS ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS)
+#define SAI2_NS ((SAI_TypeDef *) SAI2_BASE_NS)
+#define SAI2_Block_A_NS ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_NS)
+#define SAI2_Block_B_NS ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_NS)
+
+/*!< APB3 Non secure peripherals */
+#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS)
+#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS)
+#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS)
+#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS)
+#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS)
+#define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS)
+#define LPTIM4_NS ((LPTIM_TypeDef *) LPTIM4_BASE_NS)
+#define OPAMP_NS ((OPAMP_TypeDef *) OPAMP_BASE_NS)
+#define OPAMP1_NS ((OPAMP_TypeDef *) OPAMP1_BASE_NS)
+#define OPAMP2_NS ((OPAMP_TypeDef *) OPAMP2_BASE_NS)
+#define COMP12_NS ((COMP_TypeDef *) COMP12_BASE_NS)
+#define COMP1_NS ((COMP_TypeDef *) COMP1_BASE_NS)
+#define COMP2_NS ((COMP_TypeDef *) COMP2_BASE_NS)
+#define COMP12_COMMON_NS ((COMP_Common_TypeDef *) COMP1_BASE_NS)
+#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS)
+#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS)
+#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS)
+
+/*!< AHB1 Non secure peripherals */
+#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS)
+#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS)
+#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS)
+#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS)
+#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS)
+#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS)
+#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS)
+#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS)
+#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS)
+#define GPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS)
+#define GPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS)
+#define GPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS)
+#define GPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS)
+#define GPDMA1_Channel12_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_NS)
+#define GPDMA1_Channel13_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_NS)
+#define GPDMA1_Channel14_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_NS)
+#define GPDMA1_Channel15_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_NS)
+#define CORDIC_NS ((CORDIC_TypeDef *) CORDIC_BASE_NS)
+#define FMAC_NS ((FMAC_TypeDef *) FMAC_BASE_NS)
+#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS)
+#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS)
+#define TSC_NS ((TSC_TypeDef *) TSC_BASE_NS)
+#define MDF1_NS ((MDF_TypeDef *) MDF1_BASE_NS)
+#define MDF1_Filter0_NS ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_NS)
+#define MDF1_Filter1_NS ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_NS)
+#define MDF1_Filter2_NS ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_NS)
+#define MDF1_Filter3_NS ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_NS)
+#define MDF1_Filter4_NS ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_NS)
+#define MDF1_Filter5_NS ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_NS)
+#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS)
+#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS)
+#define RAMCFG_SRAM3_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_NS)
+#define RAMCFG_SRAM4_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_NS)
+#define RAMCFG_BKPRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS)
+#define DMA2D_NS ((DMA2D_TypeDef *) DMA2D_BASE_NS)
+#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS)
+#define DCACHE1_NS ((DCACHE_TypeDef *) DCACHE1_BASE_NS)
+#define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS)
+#define GTZC_TZIC1_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_NS)
+#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS)
+#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS)
+#define GTZC_MPCBB3_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_NS)
+
+/*!< AHB2 Non secure peripherals */
+#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS)
+#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS)
+#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS)
+#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS)
+#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS)
+#define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS)
+#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS)
+#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS)
+#define GPIOI_NS ((GPIO_TypeDef *) GPIOI_BASE_NS)
+#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS)
+#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS)
+#define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS)
+#define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS)
+#define USB_OTG_FS_NS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_BASE_NS)
+#define AES_NS ((AES_TypeDef *) AES_BASE_NS)
+#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS)
+#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS)
+#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS)
+#define SAES_NS ((AES_TypeDef *) SAES_BASE_NS)
+#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS)
+#define OTFDEC1_NS ((OTFDEC_TypeDef *) OTFDEC1_BASE_NS)
+#define OTFDEC1_REGION1_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_NS)
+#define OTFDEC1_REGION2_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_NS)
+#define OTFDEC1_REGION3_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_NS)
+#define OTFDEC1_REGION4_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_NS)
+#define OTFDEC2_NS ((OTFDEC_TypeDef *) OTFDEC2_BASE_NS)
+#define OTFDEC2_REGION1_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE_NS)
+#define OTFDEC2_REGION2_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE_NS)
+#define OTFDEC2_REGION3_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE_NS)
+#define OTFDEC2_REGION4_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE_NS)
+#define OCTOSPIM_NS ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_NS)
+#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS)
+#define SDMMC2_NS ((SDMMC_TypeDef *) SDMMC2_BASE_NS)
+#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS)
+#define DLYB_SDMMC2_NS ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_NS)
+#define DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS)
+#define DLYB_OCTOSPI2_NS ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_NS)
+#define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS)
+#define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS)
+#define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS)
+#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS)
+#define OCTOSPI2_NS ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_NS)
+
+/*!< AHB3 Non secure peripherals */
+#define LPGPIO1_NS ((GPIO_TypeDef *) LPGPIO1_BASE_NS)
+#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS)
+#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS)
+#define ADC4_NS ((ADC_TypeDef *) ADC4_BASE_NS)
+#define ADC4_COMMON_NS ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_NS)
+#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS)
+#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS)
+#define GTZC_TZSC2_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_NS)
+#define GTZC_TZIC2_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_NS)
+#define GTZC_MPCBB4_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_NS)
+#define ADF1_NS ((MDF_TypeDef *) ADF1_BASE_NS)
+#define ADF1_Filter0_NS ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_NS)
+#define LPDMA1_NS ((DMA_TypeDef *) LPDMA1_BASE_NS)
+#define LPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_NS)
+#define LPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_NS)
+#define LPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_NS)
+#define LPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_NS)
+
+/*!< APB1 Secure peripherals */
+#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S)
+#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S)
+#define TIM4_S ((TIM_TypeDef *) TIM4_BASE_S)
+#define TIM5_S ((TIM_TypeDef *) TIM5_BASE_S)
+#define TIM6_S ((TIM_TypeDef *) TIM6_BASE_S)
+#define TIM7_S ((TIM_TypeDef *) TIM7_BASE_S)
+#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S)
+#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S)
+#define SPI2_S ((SPI_TypeDef *) SPI2_BASE_S)
+#define USART2_S ((USART_TypeDef *) USART2_BASE_S)
+#define USART3_S ((USART_TypeDef *) USART3_BASE_S)
+#define UART4_S ((USART_TypeDef *) UART4_BASE_S)
+#define UART5_S ((USART_TypeDef *) UART5_BASE_S)
+#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S)
+#define I2C2_S ((I2C_TypeDef *) I2C2_BASE_S)
+#define CRS_S ((CRS_TypeDef *) CRS_BASE_S)
+#define I2C4_S ((I2C_TypeDef *) I2C4_BASE_S)
+#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S)
+#define FDCAN1_S ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S)
+#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S)
+#define UCPD1_S ((UCPD_TypeDef *) UCPD1_BASE_S)
+
+/*!< APB2 Secure peripherals */
+#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S)
+#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S)
+#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S)
+#define USART1_S ((USART_TypeDef *) USART1_BASE_S)
+#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S)
+#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S)
+#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S)
+#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S)
+#define SAI1_Block_A_S ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S)
+#define SAI1_Block_B_S ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S)
+#define SAI2_S ((SAI_TypeDef *) SAI2_BASE_S)
+#define SAI2_Block_A_S ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_S)
+#define SAI2_Block_B_S ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_S)
+
+/*!< APB3 secure peripherals */
+#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S)
+#define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S)
+#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S)
+#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S)
+#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S)
+#define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S)
+#define LPTIM4_S ((LPTIM_TypeDef *) LPTIM4_BASE_S)
+#define OPAMP_S ((OPAMP_TypeDef *) OPAMP_BASE_S)
+#define OPAMP1_S ((OPAMP_TypeDef *) OPAMP1_BASE_S)
+#define OPAMP2_S ((OPAMP_TypeDef *) OPAMP2_BASE_S)
+#define COMP12_S ((COMP_TypeDef *) COMP12_BASE_S)
+#define COMP1_S ((COMP_TypeDef *) COMP1_BASE_S)
+#define COMP2_S ((COMP_TypeDef *) COMP2_BASE_S)
+#define COMP12_COMMON_S ((COMP_Common_TypeDef *) COMP1_BASE_S)
+#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S)
+#define RTC_S ((RTC_TypeDef *) RTC_BASE_S)
+#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S)
+
+/*!< AHB1 Secure peripherals */
+#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S)
+#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S)
+#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S)
+#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S)
+#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S)
+#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S)
+#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S)
+#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S)
+#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S)
+#define GPDMA1_Channel8_S ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S)
+#define GPDMA1_Channel9_S ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S)
+#define GPDMA1_Channel10_S ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S)
+#define GPDMA1_Channel11_S ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S)
+#define GPDMA1_Channel12_S ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_S)
+#define GPDMA1_Channel13_S ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_S)
+#define GPDMA1_Channel14_S ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_S)
+#define GPDMA1_Channel15_S ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_S)
+#define CORDIC_S ((CORDIC_TypeDef *) CORDIC_BASE_S)
+#define FMAC_S ((FMAC_TypeDef *) FMAC_BASE_S)
+#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S)
+#define CRC_S ((CRC_TypeDef *) CRC_BASE_S)
+#define TSC_S ((TSC_TypeDef *) TSC_BASE_S)
+#define MDF1_S ((MDF_TypeDef *) MDF1_BASE_S)
+#define MDF1_Filter0_S ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_S)
+#define MDF1_Filter1_S ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_S)
+#define MDF1_Filter2_S ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_S)
+#define MDF1_Filter3_S ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_S)
+#define MDF1_Filter4_S ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_S)
+#define MDF1_Filter5_S ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_S)
+#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S)
+#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S)
+#define RAMCFG_SRAM3_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_S)
+#define RAMCFG_SRAM4_S ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_S)
+#define RAMCFG_BKPRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_S)
+#define DMA2D_S ((DMA2D_TypeDef *) DMA2D_BASE_S)
+#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S)
+#define DCACHE1_S ((DCACHE_TypeDef *) DCACHE1_BASE_S)
+#define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S)
+#define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S)
+#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S)
+#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S)
+#define GTZC_MPCBB3_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_S)
+
+/*!< AHB2 Secure peripherals */
+#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S)
+#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S)
+#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S)
+#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S)
+#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S)
+#define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S)
+#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S)
+#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S)
+#define GPIOI_S ((GPIO_TypeDef *) GPIOI_BASE_S)
+#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S)
+#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S)
+#define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S)
+#define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S)
+#define USB_OTG_FS_S ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_BASE_S)
+#define AES_S ((AES_TypeDef *) AES_BASE_S)
+#define HASH_S ((HASH_TypeDef *) HASH_BASE_S)
+#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S)
+#define RNG_S ((RNG_TypeDef *) RNG_BASE_S)
+#define SAES_S ((AES_TypeDef *) SAES_BASE_S)
+#define PKA_S ((PKA_TypeDef *) PKA_BASE_S)
+#define OTFDEC1_S ((OTFDEC_TypeDef *) OTFDEC1_BASE_S)
+#define OTFDEC1_REGION1_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_S)
+#define OTFDEC1_REGION2_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_S)
+#define OTFDEC1_REGION3_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_S)
+#define OTFDEC1_REGION4_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_S)
+#define OTFDEC2_S ((OTFDEC_TypeDef *) OTFDEC2_BASE_S)
+#define OTFDEC2_REGION1_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE_S)
+#define OTFDEC2_REGION2_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE_S)
+#define OTFDEC2_REGION3_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE_S)
+#define OTFDEC2_REGION4_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE_S)
+#define OCTOSPIM_S ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_S)
+#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S)
+#define SDMMC2_S ((SDMMC_TypeDef *) SDMMC2_BASE_S)
+#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S)
+#define DLYB_SDMMC2_S ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_S)
+#define DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S)
+#define DLYB_OCTOSPI2_S ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_S)
+#define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S)
+#define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S)
+#define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S)
+#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S)
+#define OCTOSPI2_S ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_S)
+
+/*!< AHB3 Secure peripherals */
+#define LPGPIO1_S ((GPIO_TypeDef *) LPGPIO1_BASE_S)
+#define PWR_S ((PWR_TypeDef *) PWR_BASE_S)
+#define RCC_S ((RCC_TypeDef *) RCC_BASE_S)
+#define ADC4_S ((ADC_TypeDef *) ADC4_BASE_S)
+#define ADC4_COMMON_S ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_S)
+#define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S)
+#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S)
+#define GTZC_TZSC2_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_S)
+#define GTZC_TZIC2_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_S)
+#define GTZC_MPCBB4_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_S)
+#define ADF1_S ((MDF_TypeDef *) ADF1_BASE_S)
+#define ADF1_Filter0_S ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_S)
+#define LPDMA1_S ((DMA_TypeDef *) LPDMA1_BASE_S)
+#define LPDMA1_Channel0_S ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_S)
+#define LPDMA1_Channel1_S ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_S)
+#define LPDMA1_Channel2_S ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_S)
+#define LPDMA1_Channel3_S ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_S)
+
+/*!< DBGMCU peripheral */
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/*!< Memory base addresses for Secure peripherals */
+#define FLASH_BASE FLASH_BASE_S
+#define SRAM1_BASE SRAM1_BASE_S
+#define SRAM2_BASE SRAM2_BASE_S
+#define SRAM3_BASE SRAM3_BASE_S
+#define SRAM4_BASE SRAM4_BASE_S
+#define BKPSRAM_BASE BKPSRAM_BASE_S
+#define PERIPH_BASE PERIPH_BASE_S
+#define APB1PERIPH_BASE APB1PERIPH_BASE_S
+#define APB2PERIPH_BASE APB2PERIPH_BASE_S
+#define AHB1PERIPH_BASE AHB1PERIPH_BASE_S
+#define AHB2PERIPH_BASE AHB2PERIPH_BASE_S
+
+/*!< Instance aliases and base addresses for Secure peripherals */
+#define CORDIC CORDIC_S
+#define CORDIC_BASE CORDIC_BASE_S
+
+#define RCC RCC_S
+#define RCC_BASE RCC_BASE_S
+
+#define DCMI DCMI_S
+#define DCMI_BASE DCMI_BASE_S
+
+#define PSSI PSSI_S
+#define PSSI_BASE PSSI_BASE_S
+
+#define FLASH FLASH_S
+#define FLASH_R_BASE FLASH_R_BASE_S
+
+#define FMAC FMAC_S
+#define FMAC_BASE FMAC_BASE_S
+
+#define GPDMA1 GPDMA1_S
+#define GPDMA1_BASE GPDMA1_BASE_S
+
+#define GPDMA1_Channel0 GPDMA1_Channel0_S
+#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S
+
+#define GPDMA1_Channel1 GPDMA1_Channel1_S
+#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S
+
+#define GPDMA1_Channel2 GPDMA1_Channel2_S
+#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S
+
+#define GPDMA1_Channel3 GPDMA1_Channel3_S
+#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S
+
+#define GPDMA1_Channel4 GPDMA1_Channel4_S
+#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S
+
+#define GPDMA1_Channel5 GPDMA1_Channel5_S
+#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S
+
+#define GPDMA1_Channel6 GPDMA1_Channel6_S
+#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S
+
+#define GPDMA1_Channel7 GPDMA1_Channel7_S
+#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S
+
+#define GPDMA1_Channel8 GPDMA1_Channel8_S
+#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_S
+
+#define GPDMA1_Channel9 GPDMA1_Channel9_S
+#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_S
+
+#define GPDMA1_Channel10 GPDMA1_Channel10_S
+#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_S
+
+#define GPDMA1_Channel11 GPDMA1_Channel11_S
+#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_S
+
+#define GPDMA1_Channel12 GPDMA1_Channel12_S
+#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_S
+
+#define GPDMA1_Channel13 GPDMA1_Channel13_S
+#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_S
+
+#define GPDMA1_Channel14 GPDMA1_Channel14_S
+#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_S
+
+#define GPDMA1_Channel15 GPDMA1_Channel15_S
+#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_S
+
+#define LPDMA1 LPDMA1_S
+#define LPDMA1_BASE LPDMA1_BASE_S
+
+#define LPDMA1_Channel0 LPDMA1_Channel0_S
+#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_S
+
+#define LPDMA1_Channel1 LPDMA1_Channel1_S
+#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_S
+
+#define LPDMA1_Channel2 LPDMA1_Channel2_S
+#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_S
+
+#define LPDMA1_Channel3 LPDMA1_Channel3_S
+#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_S
+
+#define GPIOA GPIOA_S
+#define GPIOA_BASE GPIOA_BASE_S
+
+#define GPIOB GPIOB_S
+#define GPIOB_BASE GPIOB_BASE_S
+
+#define GPIOC GPIOC_S
+#define GPIOC_BASE GPIOC_BASE_S
+
+#define GPIOD GPIOD_S
+#define GPIOD_BASE GPIOD_BASE_S
+
+#define GPIOE GPIOE_S
+#define GPIOE_BASE GPIOE_BASE_S
+
+#define GPIOF GPIOF_S
+#define GPIOF_BASE GPIOF_BASE_S
+
+#define GPIOG GPIOG_S
+#define GPIOG_BASE GPIOG_BASE_S
+
+#define GPIOH GPIOH_S
+#define GPIOH_BASE GPIOH_BASE_S
+
+#define GPIOI GPIOI_S
+#define GPIOI_BASE GPIOI_BASE_S
+
+#define LPGPIO1 LPGPIO1_S
+#define LPGPIO1_BASE LPGPIO1_BASE_S
+
+#define PWR PWR_S
+#define PWR_BASE PWR_BASE_S
+
+#define RAMCFG_SRAM1 RAMCFG_SRAM1_S
+#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S
+
+#define RAMCFG_SRAM2 RAMCFG_SRAM2_S
+#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S
+
+#define RAMCFG_SRAM3 RAMCFG_SRAM3_S
+#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_S
+
+#define RAMCFG_SRAM4 RAMCFG_SRAM4_S
+#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_S
+
+#define RAMCFG_BKPRAM RAMCFG_BKPRAM_S
+#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_S
+
+#define EXTI EXTI_S
+#define EXTI_BASE EXTI_BASE_S
+
+#define ICACHE ICACHE_S
+#define ICACHE_BASE ICACHE_BASE_S
+
+#define DCACHE1 DCACHE1_S
+#define DCACHE1_BASE DCACHE1_BASE_S
+
+#define GTZC_TZSC1 GTZC_TZSC1_S
+#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_S
+
+#define GTZC_TZSC2 GTZC_TZSC2_S
+#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_S
+
+#define GTZC_TZIC1 GTZC_TZIC1_S
+#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_S
+
+#define GTZC_TZIC2 GTZC_TZIC2_S
+#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_S
+
+#define GTZC_MPCBB1 GTZC_MPCBB1_S
+#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S
+
+#define GTZC_MPCBB2 GTZC_MPCBB2_S
+#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S
+
+#define GTZC_MPCBB3 GTZC_MPCBB3_S
+#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_S
+
+#define GTZC_MPCBB4 GTZC_MPCBB4_S
+#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_S
+
+#define RTC RTC_S
+#define RTC_BASE RTC_BASE_S
+
+#define TAMP TAMP_S
+#define TAMP_BASE TAMP_BASE_S
+
+#define TIM1 TIM1_S
+#define TIM1_BASE TIM1_BASE_S
+
+#define TIM2 TIM2_S
+#define TIM2_BASE TIM2_BASE_S
+
+#define TIM3 TIM3_S
+#define TIM3_BASE TIM3_BASE_S
+
+#define TIM4 TIM4_S
+#define TIM4_BASE TIM4_BASE_S
+
+#define TIM5 TIM5_S
+#define TIM5_BASE TIM5_BASE_S
+
+#define TIM6 TIM6_S
+#define TIM6_BASE TIM6_BASE_S
+
+#define TIM7 TIM7_S
+#define TIM7_BASE TIM7_BASE_S
+
+#define TIM8 TIM8_S
+#define TIM8_BASE TIM8_BASE_S
+
+#define TIM15 TIM15_S
+#define TIM15_BASE TIM15_BASE_S
+
+#define TIM16 TIM16_S
+#define TIM16_BASE TIM16_BASE_S
+
+#define TIM17 TIM17_S
+#define TIM17_BASE TIM17_BASE_S
+
+#define WWDG WWDG_S
+#define WWDG_BASE WWDG_BASE_S
+
+#define IWDG IWDG_S
+#define IWDG_BASE IWDG_BASE_S
+
+#define SPI1 SPI1_S
+#define SPI1_BASE SPI1_BASE_S
+
+#define SPI2 SPI2_S
+#define SPI2_BASE SPI2_BASE_S
+
+#define SPI3 SPI3_S
+#define SPI3_BASE SPI3_BASE_S
+
+#define USART1 USART1_S
+#define USART1_BASE USART1_BASE_S
+
+#define USART2 USART2_S
+#define USART2_BASE USART2_BASE_S
+
+#define USART3 USART3_S
+#define USART3_BASE USART3_BASE_S
+
+#define UART4 UART4_S
+#define UART4_BASE UART4_BASE_S
+
+#define UART5 UART5_S
+#define UART5_BASE UART5_BASE_S
+
+#define I2C1 I2C1_S
+#define I2C1_BASE I2C1_BASE_S
+
+#define I2C2 I2C2_S
+#define I2C2_BASE I2C2_BASE_S
+
+#define I2C3 I2C3_S
+#define I2C3_BASE I2C3_BASE_S
+
+#define I2C4 I2C4_S
+#define I2C4_BASE I2C4_BASE_S
+
+#define CRS CRS_S
+#define CRS_BASE CRS_BASE_S
+
+#define FDCAN1 FDCAN1_S
+#define FDCAN1_BASE FDCAN1_BASE_S
+
+#define FDCAN_CONFIG FDCAN_CONFIG_S
+#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S
+#define SRAMCAN_BASE SRAMCAN_BASE_S
+
+#define DAC DAC_S
+#define DAC_BASE DAC_BASE_S
+
+#define DAC1 DAC1_S
+#define DAC1_BASE DAC1_BASE_S
+
+#define OPAMP OPAMP_S
+#define OPAMP_BASE OPAMP_BASE_S
+
+#define OPAMP1 OPAMP1_S
+#define OPAMP1_BASE OPAMP1_BASE_S
+
+#define OPAMP2 OPAMP2_S
+#define OPAMP2_BASE OPAMP2_BASE_S
+
+#define LPTIM1 LPTIM1_S
+#define LPTIM1_BASE LPTIM1_BASE_S
+
+#define LPTIM2 LPTIM2_S
+#define LPTIM2_BASE LPTIM2_BASE_S
+
+#define LPTIM3 LPTIM3_S
+#define LPTIM3_BASE LPTIM3_BASE_S
+
+#define LPTIM4 LPTIM4_S
+#define LPTIM4_BASE LPTIM4_BASE_S
+
+#define LPUART1 LPUART1_S
+#define LPUART1_BASE LPUART1_BASE_S
+
+#define UCPD1 UCPD1_S
+#define UCPD1_BASE UCPD1_BASE_S
+
+#define SYSCFG SYSCFG_S
+#define SYSCFG_BASE SYSCFG_BASE_S
+
+#define VREFBUF VREFBUF_S
+#define VREFBUF_BASE VREFBUF_BASE_S
+
+#define COMP12 COMP12_S
+#define COMP12_BASE COMP12_BASE_S
+
+#define COMP1 COMP1_S
+#define COMP1_BASE COMP1_BASE_S
+
+#define COMP2 COMP2_S
+#define COMP2_BASE COMP2_BASE_S
+
+#define COMP12_COMMON COMP12_COMMON_S
+#define COMP12_COMMON_BASE COMP1_BASE_S
+
+#define SAI1 SAI1_S
+#define SAI1_BASE SAI1_BASE_S
+
+#define SAI1_Block_A SAI1_Block_A_S
+#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S
+
+#define SAI1_Block_B SAI1_Block_B_S
+#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S
+
+#define SAI2 SAI2_S
+#define SAI2_BASE SAI2_BASE_S
+
+#define SAI2_Block_A SAI2_Block_A_S
+#define SAI2_Block_A_BASE SAI2_Block_A_BASE_S
+
+#define SAI2_Block_B SAI2_Block_B_S
+#define SAI2_Block_B_BASE SAI2_Block_B_BASE_S
+
+#define CRC CRC_S
+#define CRC_BASE CRC_BASE_S
+
+#define TSC TSC_S
+#define TSC_BASE TSC_BASE_S
+
+#define ADC1 ADC1_S
+#define ADC1_BASE ADC1_BASE_S
+
+#define ADC12_COMMON ADC12_COMMON_S
+#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S
+
+#define ADC4 ADC4_S
+#define ADC4_BASE ADC4_BASE_S
+
+#define ADC4_COMMON ADC4_COMMON_S
+#define ADC4_COMMON_BASE ADC4_COMMON_BASE_S
+
+#define HASH HASH_S
+#define HASH_BASE HASH_BASE_S
+
+#define HASH_DIGEST HASH_DIGEST_S
+#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S
+
+#define AES AES_S
+#define AES_BASE AES_BASE_S
+
+#define RNG RNG_S
+#define RNG_BASE RNG_BASE_S
+
+#define SAES SAES_S
+#define SAES_BASE SAES_BASE_S
+
+#define PKA PKA_S
+#define PKA_BASE PKA_BASE_S
+#define PKA_RAM_BASE PKA_RAM_BASE_S
+
+#define OTFDEC1 OTFDEC1_S
+#define OTFDEC1_BASE OTFDEC1_BASE_S
+
+#define OTFDEC1_REGION1 OTFDEC1_REGION1_S
+#define OTFDEC1_REGION1_BASE OTFDEC1_REGION1_BASE_S
+
+#define OTFDEC1_REGION2 OTFDEC1_REGION2_S
+#define OTFDEC1_REGION2_BASE OTFDEC1_REGION2_BASE_S
+
+#define OTFDEC1_REGION3 OTFDEC1_REGION3_S
+#define OTFDEC1_REGION3_BASE OTFDEC1_REGION3_BASE_S
+
+#define OTFDEC1_REGION4 OTFDEC1_REGION4_S
+#define OTFDEC1_REGION4_BASE OTFDEC1_REGION4_BASE_S
+
+#define OTFDEC2 OTFDEC2_S
+#define OTFDEC2_BASE OTFDEC2_BASE_S
+
+#define OTFDEC2_REGION1 OTFDEC2_REGION1_S
+#define OTFDEC2_REGION1_BASE OTFDEC2_REGION1_BASE_S
+
+#define OTFDEC2_REGION2 OTFDEC2_REGION2_S
+#define OTFDEC2_REGION2_BASE OTFDEC2_REGION2_BASE_S
+
+#define OTFDEC2_REGION3 OTFDEC2_REGION3_S
+#define OTFDEC2_REGION3_BASE OTFDEC2_REGION3_BASE_S
+
+#define OTFDEC2_REGION4 OTFDEC2_REGION4_S
+#define OTFDEC2_REGION4_BASE OTFDEC2_REGION4_BASE_S
+
+#define SDMMC1 SDMMC1_S
+#define SDMMC1_BASE SDMMC1_BASE_S
+
+#define SDMMC2 SDMMC2_S
+#define SDMMC2_BASE SDMMC2_BASE_S
+
+#define FMC_Bank1_R FMC_Bank1_R_S
+#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_S
+
+#define FMC_Bank1E_R FMC_Bank1E_R_S
+#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_S
+
+#define FMC_Bank3_R FMC_Bank3_R_S
+#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_S
+
+#define OCTOSPI1 OCTOSPI1_S
+#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S
+
+#define OCTOSPI2 OCTOSPI2_S
+#define OCTOSPI2_R_BASE OCTOSPI2_R_BASE_S
+
+#define OCTOSPIM OCTOSPIM_S
+#define OCTOSPIM_R_BASE OCTOSPIM_R_BASE_S
+
+#define DLYB_SDMMC1 DLYB_SDMMC1_S
+#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S
+
+#define DLYB_SDMMC2 DLYB_SDMMC2_S
+#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_S
+
+#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_S
+#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_S
+
+#define DLYB_OCTOSPI2 DLYB_OCTOSPI2_S
+#define DLYB_OCTOSPI2_BASE DLYB_OCTOSPI2_BASE_S
+
+#define DMA2D DMA2D_S
+#define DMA2D_BASE DMA2D_BASE_S
+
+#define USB_OTG_FS USB_OTG_FS_S
+#define USB_OTG_FS_BASE USB_OTG_FS_BASE_S
+
+#define MDF1 MDF1_S
+#define MDF1_BASE MDF1_BASE_S
+
+#define MDF1_Filter0 MDF1_Filter0_S
+#define MDF1_Filter0_BASE MDF1_Filter0_BASE_S
+
+#define MDF1_Filter1 MDF1_Filter1_S
+#define MDF1_Filter1_BASE MDF1_Filter1_BASE_S
+
+#define MDF1_Filter2 MDF1_Filter2_S
+#define MDF1_Filter2_BASE MDF1_Filter2_BASE_S
+
+#define MDF1_Filter3 MDF1_Filter3_S
+#define MDF1_Filter3_BASE MDF1_Filter3_BASE_S
+
+#define MDF1_Filter4 MDF1_Filter4_S
+#define MDF1_Filter4_BASE MDF1_Filter4_BASE_S
+
+#define MDF1_Filter5 MDF1_Filter5_S
+#define MDF1_Filter5_BASE MDF1_Filter5_BASE_S
+
+#define ADF1 ADF1_S
+#define ADF1_BASE ADF1_BASE_S
+
+#define ADF1_Filter0 ADF1_Filter0_S
+#define ADF1_Filter0_BASE ADF1_Filter0_BASE_S
+
+#else
+
+/*!< Memory base addresses for Non secure peripherals */
+#define FLASH_BASE FLASH_BASE_NS
+#define SRAM1_BASE SRAM1_BASE_NS
+#define SRAM2_BASE SRAM2_BASE_NS
+#define SRAM3_BASE SRAM3_BASE_NS
+#define SRAM4_BASE SRAM4_BASE_NS
+#define BKPSRAM_BASE BKPSRAM_BASE_NS
+#define PERIPH_BASE PERIPH_BASE_NS
+#define APB1PERIPH_BASE APB1PERIPH_BASE_NS
+#define APB2PERIPH_BASE APB2PERIPH_BASE_NS
+#define AHB1PERIPH_BASE AHB1PERIPH_BASE_NS
+#define AHB2PERIPH_BASE AHB2PERIPH_BASE_NS
+
+/*!< Instance aliases and base addresses for Non secure peripherals */
+#define CORDIC CORDIC_NS
+#define CORDIC_BASE CORDIC_BASE_NS
+
+#define RCC RCC_NS
+#define RCC_BASE RCC_BASE_NS
+
+#define DMA2D DMA2D_NS
+#define DMA2D_BASE DMA2D_BASE_NS
+
+#define DCMI DCMI_NS
+#define DCMI_BASE DCMI_BASE_NS
+
+#define PSSI PSSI_NS
+#define PSSI_BASE PSSI_BASE_NS
+
+#define FLASH FLASH_NS
+#define FLASH_R_BASE FLASH_R_BASE_NS
+
+#define FMAC FMAC_NS
+#define FMAC_BASE FMAC_BASE_NS
+
+#define GPDMA1 GPDMA1_NS
+#define GPDMA1_BASE GPDMA1_BASE_NS
+
+#define GPDMA1_Channel0 GPDMA1_Channel0_NS
+#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS
+
+#define GPDMA1_Channel1 GPDMA1_Channel1_NS
+#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS
+
+#define GPDMA1_Channel2 GPDMA1_Channel2_NS
+#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS
+
+#define GPDMA1_Channel3 GPDMA1_Channel3_NS
+#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS
+
+#define GPDMA1_Channel4 GPDMA1_Channel4_NS
+#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS
+
+#define GPDMA1_Channel5 GPDMA1_Channel5_NS
+#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS
+
+#define GPDMA1_Channel6 GPDMA1_Channel6_NS
+#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS
+
+#define GPDMA1_Channel7 GPDMA1_Channel7_NS
+#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS
+
+#define GPDMA1_Channel8 GPDMA1_Channel8_NS
+#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_NS
+
+#define GPDMA1_Channel9 GPDMA1_Channel9_NS
+#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_NS
+
+#define GPDMA1_Channel10 GPDMA1_Channel10_NS
+#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_NS
+
+#define GPDMA1_Channel11 GPDMA1_Channel11_NS
+#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_NS
+
+#define GPDMA1_Channel12 GPDMA1_Channel12_NS
+#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_NS
+
+#define GPDMA1_Channel13 GPDMA1_Channel13_NS
+#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_NS
+
+#define GPDMA1_Channel14 GPDMA1_Channel14_NS
+#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_NS
+
+#define GPDMA1_Channel15 GPDMA1_Channel15_NS
+#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_NS
+
+#define LPDMA1 LPDMA1_NS
+#define LPDMA1_BASE LPDMA1_BASE_NS
+
+#define LPDMA1_Channel0 LPDMA1_Channel0_NS
+#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_NS
+
+#define LPDMA1_Channel1 LPDMA1_Channel1_NS
+#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_NS
+
+#define LPDMA1_Channel2 LPDMA1_Channel2_NS
+#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_NS
+
+#define LPDMA1_Channel3 LPDMA1_Channel3_NS
+#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_NS
+
+#define GPIOA GPIOA_NS
+#define GPIOA_BASE GPIOA_BASE_NS
+
+#define GPIOB GPIOB_NS
+#define GPIOB_BASE GPIOB_BASE_NS
+
+#define GPIOC GPIOC_NS
+#define GPIOC_BASE GPIOC_BASE_NS
+
+#define GPIOD GPIOD_NS
+#define GPIOD_BASE GPIOD_BASE_NS
+
+#define GPIOE GPIOE_NS
+#define GPIOE_BASE GPIOE_BASE_NS
+
+#define GPIOF GPIOF_NS
+#define GPIOF_BASE GPIOF_BASE_NS
+
+#define GPIOG GPIOG_NS
+#define GPIOG_BASE GPIOG_BASE_NS
+
+#define GPIOH GPIOH_NS
+#define GPIOH_BASE GPIOH_BASE_NS
+
+#define GPIOI GPIOI_NS
+#define GPIOI_BASE GPIOI_BASE_NS
+
+#define LPGPIO1 LPGPIO1_NS
+#define LPGPIO1_BASE LPGPIO1_BASE_NS
+
+#define PWR PWR_NS
+#define PWR_BASE PWR_BASE_NS
+
+#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS
+#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS
+
+#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS
+#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS
+
+#define RAMCFG_SRAM3 RAMCFG_SRAM3_NS
+#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_NS
+
+#define RAMCFG_SRAM4 RAMCFG_SRAM4_NS
+#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_NS
+
+#define RAMCFG_BKPRAM RAMCFG_BKPRAM_NS
+#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_NS
+
+#define EXTI EXTI_NS
+#define EXTI_BASE EXTI_BASE_NS
+
+#define ICACHE ICACHE_NS
+#define ICACHE_BASE ICACHE_BASE_NS
+
+#define DCACHE1 DCACHE1_NS
+#define DCACHE1_BASE DCACHE1_BASE_NS
+
+#define GTZC_TZSC1 GTZC_TZSC1_NS
+#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS
+
+#define GTZC_TZSC2 GTZC_TZSC2_NS
+#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_NS
+
+#define GTZC_TZIC1 GTZC_TZIC1_NS
+#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_NS
+
+#define GTZC_TZIC2 GTZC_TZIC2_NS
+#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_NS
+
+#define GTZC_MPCBB1 GTZC_MPCBB1_NS
+#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS
+
+#define GTZC_MPCBB2 GTZC_MPCBB2_NS
+#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS
+
+#define GTZC_MPCBB3 GTZC_MPCBB3_NS
+#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_NS
+
+#define GTZC_MPCBB4 GTZC_MPCBB4_NS
+#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_NS
+
+#define RTC RTC_NS
+#define RTC_BASE RTC_BASE_NS
+
+#define TAMP TAMP_NS
+#define TAMP_BASE TAMP_BASE_NS
+
+#define TIM1 TIM1_NS
+#define TIM1_BASE TIM1_BASE_NS
+
+#define TIM2 TIM2_NS
+#define TIM2_BASE TIM2_BASE_NS
+
+#define TIM3 TIM3_NS
+#define TIM3_BASE TIM3_BASE_NS
+
+#define TIM4 TIM4_NS
+#define TIM4_BASE TIM4_BASE_NS
+
+#define TIM5 TIM5_NS
+#define TIM5_BASE TIM5_BASE_NS
+
+#define TIM6 TIM6_NS
+#define TIM6_BASE TIM6_BASE_NS
+
+#define TIM7 TIM7_NS
+#define TIM7_BASE TIM7_BASE_NS
+
+#define TIM8 TIM8_NS
+#define TIM8_BASE TIM8_BASE_NS
+
+#define TIM15 TIM15_NS
+#define TIM15_BASE TIM15_BASE_NS
+
+#define TIM16 TIM16_NS
+#define TIM16_BASE TIM16_BASE_NS
+
+#define TIM17 TIM17_NS
+#define TIM17_BASE TIM17_BASE_NS
+
+#define WWDG WWDG_NS
+#define WWDG_BASE WWDG_BASE_NS
+
+#define IWDG IWDG_NS
+#define IWDG_BASE IWDG_BASE_NS
+
+#define SPI1 SPI1_NS
+#define SPI1_BASE SPI1_BASE_NS
+
+#define SPI2 SPI2_NS
+#define SPI2_BASE SPI2_BASE_NS
+
+#define SPI3 SPI3_NS
+#define SPI3_BASE SPI3_BASE_NS
+
+#define USART1 USART1_NS
+#define USART1_BASE USART1_BASE_NS
+
+#define USART2 USART2_NS
+#define USART2_BASE USART2_BASE_NS
+
+#define USART3 USART3_NS
+#define USART3_BASE USART3_BASE_NS
+
+#define UART4 UART4_NS
+#define UART4_BASE UART4_BASE_NS
+
+#define UART5 UART5_NS
+#define UART5_BASE UART5_BASE_NS
+
+#define I2C1 I2C1_NS
+#define I2C1_BASE I2C1_BASE_NS
+
+#define I2C2 I2C2_NS
+#define I2C2_BASE I2C2_BASE_NS
+
+#define I2C3 I2C3_NS
+#define I2C3_BASE I2C3_BASE_NS
+
+#define I2C4 I2C4_NS
+#define I2C4_BASE I2C4_BASE_NS
+
+#define CRS CRS_NS
+#define CRS_BASE CRS_BASE_NS
+
+#define FDCAN1 FDCAN1_NS
+#define FDCAN1_BASE FDCAN1_BASE_NS
+
+#define FDCAN_CONFIG FDCAN_CONFIG_NS
+#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS
+#define SRAMCAN_BASE SRAMCAN_BASE_NS
+
+#define DAC1 DAC1_NS
+#define DAC1_BASE DAC1_BASE_NS
+
+#define OPAMP OPAMP_NS
+#define OPAMP_BASE OPAMP_BASE_NS
+
+#define OPAMP1 OPAMP1_NS
+#define OPAMP1_BASE OPAMP1_BASE_NS
+
+#define OPAMP2 OPAMP2_NS
+#define OPAMP2_BASE OPAMP2_BASE_NS
+
+#define LPTIM1 LPTIM1_NS
+#define LPTIM1_BASE LPTIM1_BASE_NS
+
+#define LPTIM2 LPTIM2_NS
+#define LPTIM2_BASE LPTIM2_BASE_NS
+
+#define LPTIM3 LPTIM3_NS
+#define LPTIM3_BASE LPTIM3_BASE_NS
+
+#define LPTIM4 LPTIM4_NS
+#define LPTIM4_BASE LPTIM4_BASE_NS
+
+#define LPUART1 LPUART1_NS
+#define LPUART1_BASE LPUART1_BASE_NS
+
+#define UCPD1 UCPD1_NS
+#define UCPD1_BASE UCPD1_BASE_NS
+
+#define SYSCFG SYSCFG_NS
+#define SYSCFG_BASE SYSCFG_BASE_NS
+
+#define VREFBUF VREFBUF_NS
+#define VREFBUF_BASE VREFBUF_BASE_NS
+
+#define COMP12 COMP12_NS
+#define COMP12_BASE COMP12_BASE_NS
+
+#define COMP1 COMP1_NS
+#define COMP1_BASE COMP1_BASE_NS
+
+#define COMP2 COMP2_NS
+#define COMP2_BASE COMP2_BASE_NS
+
+#define COMP12_COMMON COMP12_COMMON_NS
+#define COMP12_COMMON_BASE COMP1_BASE_NS
+
+#define SAI1 SAI1_NS
+#define SAI1_BASE SAI1_BASE_NS
+
+#define SAI1_Block_A SAI1_Block_A_NS
+#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS
+
+#define SAI1_Block_B SAI1_Block_B_NS
+#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS
+
+#define SAI2 SAI2_NS
+#define SAI2_BASE SAI2_BASE_NS
+
+#define SAI2_Block_A SAI2_Block_A_NS
+#define SAI2_Block_A_BASE SAI2_Block_A_BASE_NS
+
+#define SAI2_Block_B SAI2_Block_B_NS
+#define SAI2_Block_B_BASE SAI2_Block_B_BASE_NS
+
+#define CRC CRC_NS
+#define CRC_BASE CRC_BASE_NS
+
+#define TSC TSC_NS
+#define TSC_BASE TSC_BASE_NS
+
+#define ADC1 ADC1_NS
+#define ADC1_BASE ADC1_BASE_NS
+
+#define ADC12_COMMON ADC12_COMMON_NS
+#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS
+
+#define ADC4 ADC4_NS
+#define ADC4_BASE ADC4_BASE_NS
+
+#define ADC4_COMMON ADC4_COMMON_NS
+#define ADC4_COMMON_BASE ADC4_COMMON_BASE_NS
+
+#define HASH HASH_NS
+#define HASH_BASE HASH_BASE_NS
+
+#define HASH_DIGEST HASH_DIGEST_NS
+#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS
+
+#define AES AES_NS
+#define AES_BASE AES_BASE_NS
+
+#define RNG RNG_NS
+#define RNG_BASE RNG_BASE_NS
+
+#define SAES SAES_NS
+#define SAES_BASE SAES_BASE_NS
+
+#define PKA PKA_NS
+#define PKA_BASE PKA_BASE_NS
+#define PKA_RAM_BASE PKA_RAM_BASE_NS
+
+#define OTFDEC1 OTFDEC1_NS
+#define OTFDEC1_BASE OTFDEC1_BASE_NS
+
+#define OTFDEC1_REGION1 OTFDEC1_REGION1_NS
+#define OTFDEC1_REGION1_BASE OTFDEC1_REGION1_BASE_NS
+
+#define OTFDEC1_REGION2 OTFDEC1_REGION2_NS
+#define OTFDEC1_REGION2_BASE OTFDEC1_REGION2_BASE_NS
+
+#define OTFDEC1_REGION3 OTFDEC1_REGION3_NS
+#define OTFDEC1_REGION3_BASE OTFDEC1_REGION3_BASE_NS
+
+#define OTFDEC1_REGION4 OTFDEC1_REGION4_NS
+#define OTFDEC1_REGION4_BASE OTFDEC1_REGION4_BASE_NS
+
+#define OTFDEC2 OTFDEC2_NS
+#define OTFDEC2_BASE OTFDEC2_BASE_NS
+
+#define OTFDEC2_REGION1 OTFDEC2_REGION1_NS
+#define OTFDEC2_REGION1_BASE OTFDEC2_REGION1_BASE_NS
+
+#define OTFDEC2_REGION2 OTFDEC2_REGION2_NS
+#define OTFDEC2_REGION2_BASE OTFDEC2_REGION2_BASE_NS
+
+#define OTFDEC2_REGION3 OTFDEC2_REGION3_NS
+#define OTFDEC2_REGION3_BASE OTFDEC2_REGION3_BASE_NS
+
+#define OTFDEC2_REGION4 OTFDEC2_REGION4_NS
+#define OTFDEC2_REGION4_BASE OTFDEC2_REGION4_BASE_NS
+
+#define SDMMC1 SDMMC1_NS
+#define SDMMC1_BASE SDMMC1_BASE_NS
+
+#define SDMMC2 SDMMC2_NS
+#define SDMMC2_BASE SDMMC2_BASE_NS
+
+#define FMC_Bank1_R FMC_Bank1_R_NS
+#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_NS
+
+#define FMC_Bank1E_R FMC_Bank1E_R_NS
+#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_NS
+
+#define FMC_Bank3_R FMC_Bank3_R_NS
+#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_NS
+
+#define OCTOSPI1 OCTOSPI1_NS
+#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS
+
+#define OCTOSPI2 OCTOSPI2_NS
+#define OCTOSPI2_R_BASE OCTOSPI2_R_BASE_NS
+
+#define OCTOSPIM OCTOSPIM_NS
+#define OCTOSPIM_R_BASE OCTOSPIM_R_BASE_NS
+
+#define DLYB_SDMMC1 DLYB_SDMMC1_NS
+#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS
+
+#define DLYB_SDMMC2 DLYB_SDMMC2_NS
+#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_NS
+
+#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS
+#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS
+
+#define DLYB_OCTOSPI2 DLYB_OCTOSPI2_NS
+#define DLYB_OCTOSPI2_BASE DLYB_OCTOSPI2_BASE_NS
+
+#define USB_OTG_FS USB_OTG_FS_NS
+#define USB_OTG_FS_BASE USB_OTG_FS_BASE_NS
+
+#define MDF1 MDF1_NS
+#define MDF1_BASE MDF1_BASE_NS
+
+#define MDF1_Filter0 MDF1_Filter0_NS
+#define MDF1_Filter0_BASE MDF1_Filter0_BASE_NS
+
+#define MDF1_Filter1 MDF1_Filter1_NS
+#define MDF1_Filter1_BASE MDF1_Filter1_BASE_NS
+
+#define MDF1_Filter2 MDF1_Filter2_NS
+#define MDF1_Filter2_BASE MDF1_Filter2_BASE_NS
+
+#define MDF1_Filter3 MDF1_Filter3_NS
+#define MDF1_Filter3_BASE MDF1_Filter3_BASE_NS
+
+#define MDF1_Filter4 MDF1_Filter4_NS
+#define MDF1_Filter4_BASE MDF1_Filter4_BASE_NS
+
+#define MDF1_Filter5 MDF1_Filter5_NS
+#define MDF1_Filter5_BASE MDF1_Filter5_BASE_NS
+
+#define ADF1 ADF1_NS
+#define ADF1_BASE ADF1_BASE_NS
+
+#define ADF1_Filter0 ADF1_Filter0_NS
+#define ADF1_Filter0_BASE ADF1_Filter0_BASE_NS
+
+#endif
+
+/** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 260U /*!< LSI Maximum startup time in us */
+
+/**
+ * @}
+ */
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/******************************* ADC VERSION ********************************/
+#define ADC_VER_V5_X
+/******************** Bit definition for ADC_ISR register ********************/
+#define ADC_ISR_ADRDY_Pos (0U)
+#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
+#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */
+#define ADC_ISR_EOSMP_Pos (1U)
+#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
+#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */
+#define ADC_ISR_EOC_Pos (2U)
+#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
+#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */
+#define ADC_ISR_EOS_Pos (3U)
+#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
+#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */
+#define ADC_ISR_OVR_Pos (4U)
+#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
+#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */
+#define ADC_ISR_JEOC_Pos (5U)
+#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
+#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */
+#define ADC_ISR_JEOS_Pos (6U)
+#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
+#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */
+#define ADC_ISR_AWD1_Pos (7U)
+#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
+#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */
+#define ADC_ISR_AWD2_Pos (8U)
+#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
+#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */
+#define ADC_ISR_AWD3_Pos (9U)
+#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
+#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */
+#define ADC_ISR_JQOVF_Pos (10U)
+#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
+#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_EOCAL_Pos (11U)
+#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */
+#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC End of Calibration flag */
+#define ADC_ISR_LDORDY_Pos (12U)
+#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
+#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC Voltage Regulator Ready flag */
+
+/******************** Bit definition for ADC_IER register ********************/
+#define ADC_IER_ADRDYIE_Pos (0U)
+#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */
+#define ADC_IER_EOSMPIE_Pos (1U)
+#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */
+#define ADC_IER_EOCIE_Pos (2U)
+#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
+#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */
+#define ADC_IER_EOSIE_Pos (3U)
+#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
+#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */
+#define ADC_IER_OVRIE_Pos (4U)
+#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
+#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */
+#define ADC_IER_JEOCIE_Pos (5U)
+#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
+#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */
+#define ADC_IER_JEOSIE_Pos (6U)
+#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
+#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */
+#define ADC_IER_AWD1IE_Pos (7U)
+#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
+#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */
+#define ADC_IER_AWD2IE_Pos (8U)
+#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
+#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */
+#define ADC_IER_AWD3IE_Pos (9U)
+#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
+#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */
+#define ADC_IER_JQOVFIE_Pos (10U)
+#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
+#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */
+#define ADC_IER_EOCALIE_Pos (11U)
+#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */
+#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC End of Calibration Enable */
+#define ADC_IER_LDORDYIE_Pos (12U)
+#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */
+#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC Voltage Regulator Ready flag */
+
+/******************** Bit definition for ADC_CR register ********************/
+#define ADC_CR_ADEN_Pos (0U)
+#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
+#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */
+#define ADC_CR_ADDIS_Pos (1U)
+#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
+#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */
+#define ADC_CR_ADSTART_Pos (2U)
+#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
+#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */
+#define ADC_CR_JADSTART_Pos (3U)
+#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
+#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */
+#define ADC_CR_ADSTP_Pos (4U)
+#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
+#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */
+#define ADC_CR_JADSTP_Pos (5U)
+#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
+#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */
+#define ADC_CR_ADCALLIN_Pos (16U)
+#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */
+#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */
+
+#define ADC_CR_CALINDEX0_Pos (24U)
+#define ADC_CR_CALINDEX0_Msk (0x1UL << ADC_CR_CALINDEX0_Pos) /*!< 0x01000000 */
+#define ADC_CR_CALINDEX0 ADC_CR_CALINDEX0_Msk /*!< ADC Linearity calibration ready Word 3 */
+#define ADC_CR_CALINDEX1_Pos (25U)
+#define ADC_CR_CALINDEX1_Msk (0x1UL << ADC_CR_CALINDEX1_Pos) /*!< 0x02000000 */
+#define ADC_CR_CALINDEX1 ADC_CR_CALINDEX1_Msk /*!< ADC Linearity calibration ready Word 4 */
+#define ADC_CR_CALINDEX2_Pos (26U)
+#define ADC_CR_CALINDEX2_Msk (0x1UL << ADC_CR_CALINDEX2_Pos) /*!< 0x04000000 */
+#define ADC_CR_CALINDEX2 ADC_CR_CALINDEX2_Msk /*!< ADC Linearity calibration ready Word 5 */
+#define ADC_CR_CALINDEX3_Pos (27U)
+#define ADC_CR_CALINDEX3_Msk (0x1UL << ADC_CR_CALINDEX3_Pos) /*!< 0x08000000 */
+#define ADC_CR_CALINDEX3 ADC_CR_CALINDEX3_Msk /*!< ADC Linearity calibration ready Word 6 */
+#define ADC_CR_ADVREGEN_Pos (28U)
+#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */
+#define ADC_CR_DEEPPWD_Pos (29U)
+#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
+#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */
+#define ADC_CR_ADCAL_Pos (31U)
+#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
+#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */
+
+/******************** Bit definition for ADC_CFGR register ********************/
+#define ADC_CFGR1_DMNGT_Pos (0U)
+#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */
+#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC Data Management configuration */
+#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */
+#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */
+
+#define ADC_CFGR1_RES_Pos (2U)
+#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */
+#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC Data resolution */
+#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */
+#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
+
+#define ADC4_CFGR1_DMAEN_Pos (0U)
+#define ADC4_CFGR1_DMAEN_Msk (0x1UL << ADC4_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
+#define ADC4_CFGR1_DMAEN ADC4_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */
+#define ADC4_CFGR1_DMACFG_Pos (1U)
+#define ADC4_CFGR1_DMACFG_Msk (0x1UL << ADC4_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
+#define ADC4_CFGR1_DMACFG ADC4_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */
+
+#define ADC4_CFGR1_SCANDIR_Pos (4U)
+#define ADC4_CFGR1_SCANDIR_Msk (0x1UL << ADC4_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
+#define ADC4_CFGR1_SCANDIR ADC4_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */
+
+#define ADC4_CFGR1_ALIGN_Pos (5U)
+#define ADC4_CFGR1_ALIGN_Msk (0x1UL << ADC4_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
+#define ADC4_CFGR1_ALIGN ADC4_CFGR1_ALIGN_Msk /*!< ADC data alignment */
+
+#define ADC_CFGR1_EXTSEL_Pos (5U)
+#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */
+#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */
+#define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */
+#define ADC_CFGR1_EXTSEL_1 (0x02UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
+#define ADC_CFGR1_EXTSEL_2 (0x04UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
+#define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
+#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */
+
+#define ADC_CFGR1_EXTEN_Pos (10U)
+#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
+#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */
+#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
+#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
+
+#define ADC_CFGR1_OVRMOD_Pos (12U)
+#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
+#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC overrun mode */
+#define ADC_CFGR1_CONT_Pos (13U)
+#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
+#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */
+
+#define ADC_CFGR1_AUTDLY_Pos (14U)
+#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */
+#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC Delayed conversion mode */
+
+#define ADC4_CFGR1_WAIT_Pos (14U)
+#define ADC4_CFGR1_WAIT_Msk (0x1UL << ADC4_CFGR1_WAIT_Pos) /*!< 0x00004000 */
+#define ADC4_CFGR1_WAIT ADC4_CFGR1_WAIT_Msk /*!< ADC Delayed conversion mode */
+
+
+#define ADC_CFGR1_DISCEN_Pos (16U)
+#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
+#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */
+
+#define ADC_CFGR1_DISCNUM_Pos (17U)
+#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */
+#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */
+#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */
+#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */
+#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */
+
+#define ADC_CFGR1_JDISCEN_Pos (20U)
+#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */
+#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */
+
+#define ADC_CFGR1_AWD1SGL_Pos (22U)
+#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */
+#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */
+#define ADC_CFGR1_AWD1EN_Pos (23U)
+#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */
+#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */
+#define ADC_CFGR1_JAWD1EN_Pos (24U)
+#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */
+#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */
+#define ADC_CFGR1_JAUTO_Pos (25U)
+#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */
+#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC Automatic injected group conversion */
+
+/* Specific ADC4 */
+#define ADC4_CFGR1_EXTSEL_Pos (6U)
+#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */
+#define ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */
+#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */
+#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
+#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
+
+#define ADC4_CFGR1_CHSELRMOD_Pos (21U)
+#define ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */
+#define ADC4_CFGR1_CHSELRMOD ADC4_CFGR1_CHSELRMOD_Msk /*!< ADC JSQR Queue mode */
+
+#define ADC_CFGR1_AWD1CH_Pos (26U)
+#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */
+#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */
+#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */
+#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */
+#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */
+#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */
+#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for ADC_CFGR2 register ********************/
+#define ADC_CFGR2_ROVSE_Pos (0U)
+#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
+#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */
+#define ADC_CFGR2_JOVSE_Pos (1U)
+#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
+#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */
+
+#define ADC_CFGR2_OVSS_Pos (5U)
+#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */
+#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
+
+#define ADC_CFGR2_TROVS_Pos (9U)
+#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
+#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */
+#define ADC_CFGR2_ROVSM_Pos (10U)
+#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
+#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */
+
+
+#define ADC_CFGR2_OVSR_Pos (16U)
+#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */
+#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */
+#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */
+#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */
+#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */
+#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */
+#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */
+#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */
+#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */
+#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */
+#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */
+#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */
+
+#define ADC_CFGR2_BULB_Pos (13U)
+#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */
+#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */
+
+#define ADC_CFGR2_SWTRIG_Pos (14U)
+#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */
+#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software trigger bit for sampling time control trigger mode */
+
+#define ADC_CFGR2_SMPTRIG_Pos (15U)
+#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */
+#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sampling time control trigger mode */
+
+#define ADC_CFGR2_LFTRIG_Pos (27U)
+#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x08000000 */
+#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */
+
+#define ADC_CFGR2_LSHIFT_Pos (28U)
+#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */
+#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */
+#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */
+#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */
+#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */
+#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */
+
+/* Specific ADC4 */
+#define ADC4_CFGR2_OVSR_Pos (2U)
+#define ADC4_CFGR2_OVSR_Msk (0x7UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x0000001C */
+#define ADC4_CFGR2_OVSR ADC4_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */
+#define ADC4_CFGR2_OVSR_0 (0x1UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000004 */
+#define ADC4_CFGR2_OVSR_1 (0x2UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000008 */
+#define ADC4_CFGR2_OVSR_2 (0x4UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000010 */
+
+#define ADC4_CFGR2_LFTRIG_Pos (29U)
+#define ADC4_CFGR2_LFTRIG_Msk (0x1UL << ADC4_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */
+#define ADC4_CFGR2_LFTRIG ADC4_CFGR2_LFTRIG_Msk /*!< ADC4 low frequency trigger mode */
+
+/******************** Bit definition for ADC_SMPR1 register ********************/
+#define ADC_SMPR1_SMP0_Pos (0U)
+#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
+#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */
+#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
+#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
+#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP1_Pos (3U)
+#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
+#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */
+#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
+#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
+#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP2_Pos (6U)
+#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */
+#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
+#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
+#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP3_Pos (9U)
+#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */
+#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
+#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
+#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP4_Pos (12U)
+#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
+#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */
+#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
+#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
+#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP5_Pos (15U)
+#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
+#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */
+#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
+#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
+#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP6_Pos (18U)
+#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */
+#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
+#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
+#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR1_SMP7_Pos (21U)
+#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */
+#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
+#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
+#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
+
+#define ADC_SMPR1_SMP8_Pos (24U)
+#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
+#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */
+#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
+#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
+#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
+
+#define ADC_SMPR1_SMP9_Pos (27U)
+#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
+#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */
+#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
+#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
+#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
+
+#define ADC4_SMPR_SMP1_Pos (0U)
+#define ADC4_SMPR_SMP1_Msk (0x7UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000007 */
+#define ADC4_SMPR_SMP1 ADC4_SMPR_SMP1_Msk /*!< ADC Channel 0 Sampling time selection */
+#define ADC4_SMPR_SMP1_0 (0x1UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000001 */
+#define ADC4_SMPR_SMP1_1 (0x2UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000002 */
+#define ADC4_SMPR_SMP1_2 (0x4UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000004 */
+
+#define ADC4_SMPR_SMP2_Pos (4U)
+#define ADC4_SMPR_SMP2_Msk (0x7UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000070 */
+#define ADC4_SMPR_SMP2 ADC4_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */
+#define ADC4_SMPR_SMP2_0 (0x1UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000010 */
+#define ADC4_SMPR_SMP2_1 (0x2UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000020 */
+#define ADC4_SMPR_SMP2_2 (0x4UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000040 */
+
+#define ADC4_SMPR_SMPSEL_Pos (8U)
+#define ADC4_SMPR_SMPSEL_Msk (0xFFFFFFUL << ADC4_SMPR_SMPSEL_Pos) /*!< 0xFFFFFF00 */
+#define ADC4_SMPR_SMPSEL ADC4_SMPR_SMPSEL_Msk /*!< ADC4 all channels sampling time selection */
+#define ADC4_SMPR_SMPSEL0_Pos (8U)
+#define ADC4_SMPR_SMPSEL0_Msk (0x1UL << ADC4_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */
+#define ADC4_SMPR_SMPSEL0 ADC4_SMPR_SMPSEL0_Msk /*!< ADC4 channel 0 sampling time selection */
+#define ADC4_SMPR_SMPSEL1_Pos (9U)
+#define ADC4_SMPR_SMPSEL1_Msk (0x1UL << ADC4_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */
+#define ADC4_SMPR_SMPSEL1 ADC4_SMPR_SMPSEL1_Msk /*!< ADC4 channel 1 sampling time selection */
+#define ADC4_SMPR_SMPSEL2_Pos (10U)
+#define ADC4_SMPR_SMPSEL2_Msk (0x1UL << ADC4_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */
+#define ADC4_SMPR_SMPSEL2 ADC4_SMPR_SMPSEL2_Msk /*!< ADC4 channel 2 sampling time selection */
+#define ADC4_SMPR_SMPSEL3_Pos (11U)
+#define ADC4_SMPR_SMPSEL3_Msk (0x1UL << ADC4_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */
+#define ADC4_SMPR_SMPSEL3 ADC4_SMPR_SMPSEL3_Msk /*!< ADC4 channel 3 sampling time selection */
+#define ADC4_SMPR_SMPSEL4_Pos (12U)
+#define ADC4_SMPR_SMPSEL4_Msk (0x1UL << ADC4_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */
+#define ADC4_SMPR_SMPSEL4 ADC4_SMPR_SMPSEL4_Msk /*!< ADC4 channel 4 sampling time selection */
+#define ADC4_SMPR_SMPSEL5_Pos (13U)
+#define ADC4_SMPR_SMPSEL5_Msk (0x1UL << ADC4_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */
+#define ADC4_SMPR_SMPSEL5 ADC4_SMPR_SMPSEL5_Msk /*!< ADC4 channel 5 sampling time selection */
+#define ADC4_SMPR_SMPSEL6_Pos (14U)
+#define ADC4_SMPR_SMPSEL6_Msk (0x1UL << ADC4_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */
+#define ADC4_SMPR_SMPSEL6 ADC4_SMPR_SMPSEL6_Msk /*!< ADC4 channel 6 sampling time selection */
+#define ADC4_SMPR_SMPSEL7_Pos (15U)
+#define ADC4_SMPR_SMPSEL7_Msk (0x1UL << ADC4_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */
+#define ADC4_SMPR_SMPSEL7 ADC4_SMPR_SMPSEL7_Msk /*!< ADC4 channel 7 sampling time selection */
+#define ADC4_SMPR_SMPSEL8_Pos (16U)
+#define ADC4_SMPR_SMPSEL8_Msk (0x1UL << ADC4_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */
+#define ADC4_SMPR_SMPSEL8 ADC4_SMPR_SMPSEL8_Msk /*!< ADC4 channel 8 sampling time selection */
+#define ADC4_SMPR_SMPSEL9_Pos (17U)
+#define ADC4_SMPR_SMPSEL9_Msk (0x1UL << ADC4_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */
+#define ADC4_SMPR_SMPSEL9 ADC4_SMPR_SMPSEL9_Msk /*!< ADC4 channel 9 sampling time selection */
+#define ADC4_SMPR_SMPSEL10_Pos (18U)
+#define ADC4_SMPR_SMPSEL10_Msk (0x1UL << ADC4_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */
+#define ADC4_SMPR_SMPSEL10 ADC4_SMPR_SMPSEL10_Msk /*!< ADC4 channel 10 sampling time selection */
+#define ADC4_SMPR_SMPSEL11_Pos (19U)
+#define ADC4_SMPR_SMPSEL11_Msk (0x1UL << ADC4_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */
+#define ADC4_SMPR_SMPSEL11 ADC4_SMPR_SMPSEL11_Msk /*!< ADC4 channel 11 sampling time selection */
+#define ADC4_SMPR_SMPSEL12_Pos (20U)
+#define ADC4_SMPR_SMPSEL12_Msk (0x1UL << ADC4_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */
+#define ADC4_SMPR_SMPSEL12 ADC4_SMPR_SMPSEL12_Msk /*!< ADC4 channel 12 sampling time selection */
+#define ADC4_SMPR_SMPSEL13_Pos (21U)
+#define ADC4_SMPR_SMPSEL13_Msk (0x1UL << ADC4_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */
+#define ADC4_SMPR_SMPSEL13 ADC4_SMPR_SMPSEL13_Msk /*!< ADC4 channel 13 sampling time selection */
+#define ADC4_SMPR_SMPSEL14_Pos (22U)
+#define ADC4_SMPR_SMPSEL14_Msk (0x1UL << ADC4_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */
+#define ADC4_SMPR_SMPSEL14 ADC4_SMPR_SMPSEL14_Msk /*!< ADC4 channel 14 sampling time selection */
+#define ADC4_SMPR_SMPSEL15_Pos (23U)
+#define ADC4_SMPR_SMPSEL15_Msk (0x1UL << ADC4_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */
+#define ADC4_SMPR_SMPSEL15 ADC4_SMPR_SMPSEL15_Msk /*!< ADC4 channel 15 sampling time selection */
+#define ADC4_SMPR_SMPSEL16_Pos (24U)
+#define ADC4_SMPR_SMPSEL16_Msk (0x1UL << ADC4_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */
+#define ADC4_SMPR_SMPSEL16 ADC4_SMPR_SMPSEL16_Msk /*!< ADC4 channel 16 sampling time selection */
+#define ADC4_SMPR_SMPSEL17_Pos (25U)
+#define ADC4_SMPR_SMPSEL17_Msk (0x1UL << ADC4_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */
+#define ADC4_SMPR_SMPSEL17 ADC4_SMPR_SMPSEL17_Msk /*!< ADC4 channel 17 sampling time selection */
+#define ADC4_SMPR_SMPSEL18_Pos (26U)
+#define ADC4_SMPR_SMPSEL18_Msk (0x1UL << ADC4_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */
+#define ADC4_SMPR_SMPSEL18 ADC4_SMPR_SMPSEL18_Msk /*!< ADC4 channel 18 sampling time selection */
+#define ADC4_SMPR_SMPSEL19_Pos (27U)
+#define ADC4_SMPR_SMPSEL19_Msk (0x1UL << ADC4_SMPR_SMPSEL19_Pos) /*!< 0x08000000 */
+#define ADC4_SMPR_SMPSEL19 ADC4_SMPR_SMPSEL19_Msk /*!< ADC4 channel 19 sampling time selection */
+#define ADC4_SMPR_SMPSEL20_Pos (26U)
+#define ADC4_SMPR_SMPSEL20_Msk (0x1UL << ADC4_SMPR_SMPSEL20_Pos) /*!< 0x10000000 */
+#define ADC4_SMPR_SMPSEL20 ADC4_SMPR_SMPSEL20_Msk /*!< ADC4 channel 20 sampling time selection */
+#define ADC4_SMPR_SMPSEL21_Pos (26U)
+#define ADC4_SMPR_SMPSEL21_Msk (0x1UL << ADC4_SMPR_SMPSEL21_Pos) /*!< 0x20000000 */
+#define ADC4_SMPR_SMPSEL21 ADC4_SMPR_SMPSEL21_Msk /*!< ADC4 channel 20 sampling time selection */
+#define ADC4_SMPR_SMPSEL22_Pos (30U)
+#define ADC4_SMPR_SMPSEL22_Msk (0x1UL << ADC4_SMPR_SMPSEL22_Pos) /*!< 0x40000000 */
+#define ADC4_SMPR_SMPSEL22 ADC4_SMPR_SMPSEL22_Msk /*!< ADC4 channel 21 sampling time selection */
+#define ADC4_SMPR_SMPSEL23_Pos (31U)
+#define ADC4_SMPR_SMPSEL23_Msk (0x1UL << ADC4_SMPR_SMPSEL23_Pos) /*!< 0x80000000 */
+#define ADC4_SMPR_SMPSEL23 ADC4_SMPR_SMPSEL23_Msk /*!< ADC4 channel 23 sampling time selection */
+
+
+/******************** Bit definition for ADC_SMPR2 register ********************/
+#define ADC_SMPR2_SMP10_Pos (0U)
+#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
+#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */
+#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
+#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
+#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP11_Pos (3U)
+#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
+#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */
+#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
+#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
+#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP12_Pos (6U)
+#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */
+#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
+#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
+#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP13_Pos (9U)
+#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */
+#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
+#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
+#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP14_Pos (12U)
+#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
+#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */
+#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
+#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
+#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP15_Pos (15U)
+#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
+#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */
+#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
+#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
+#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP16_Pos (18U)
+#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */
+#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
+#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
+#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP17_Pos (21U)
+#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */
+#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
+#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
+#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP18_Pos (24U)
+#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
+#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */
+#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
+#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
+#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
+
+#define ADC_SMPR2_SMP19_Pos (27U)
+#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */
+#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */
+#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */
+#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */
+#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */
+
+/******************** Bit definition for ADC_PCSEL register ********************/
+#define ADC_PCSEL_PCSEL_Pos (0U)
+#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */
+#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */
+#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */
+#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */
+#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */
+#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */
+#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */
+#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */
+#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */
+#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */
+#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */
+#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */
+#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */
+#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */
+#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */
+#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */
+#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */
+#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */
+#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */
+#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */
+#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */
+#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */
+
+/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/
+#define ADC_LTR_LT_Pos (0U)
+#define ADC_LTR_LT_Msk (0x01FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x01FFFFFF */
+#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */
+
+/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/
+#define ADC_HTR_HT_Pos (0U)
+#define ADC_HTR_HT_Msk (0x01FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x01FFFFFF */
+#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */
+
+#define ADC_HTR_AWDFILT_Pos (29U)
+#define ADC_HTR_AWDFILT_Msk (0x7UL << ADC_HTR_AWDFILT_Pos) /*!< 0xE0000000 */
+#define ADC_HTR_AWDFILT ADC_HTR_HT_Msk /*!< Analog watchdog filtering parameter, HTR1 only */
+#define ADC_HTR_AWDFILT_0 (0x1UL << ADC_HTR_AWDFILT_Pos) /*!< 0x20000000 */
+#define ADC_HTR_AWDFILT_1 (0x2UL << ADC_HTR_AWDFILT_Pos) /*!< 0x40000000 */
+#define ADC_HTR_AWDFILT_2 (0x4UL << ADC_HTR_AWDFILT_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for ADC_SQR1 register ********************/
+#define ADC_SQR1_L_Pos (0U)
+#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */
+#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
+#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
+#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
+#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */
+
+#define ADC_SQR1_SQ1_Pos (6U)
+#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
+#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */
+#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
+#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
+#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
+#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
+#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
+
+#define ADC_SQR1_SQ2_Pos (12U)
+#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
+#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */
+#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
+#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
+#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
+#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
+#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
+
+#define ADC_SQR1_SQ3_Pos (18U)
+#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
+#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */
+#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
+#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
+#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
+#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
+#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
+
+#define ADC_SQR1_SQ4_Pos (24U)
+#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
+#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */
+#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
+#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
+#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
+#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
+#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
+
+/******************** Bit definition for ADC_SQR2 register ********************/
+#define ADC_SQR2_SQ5_Pos (0U)
+#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
+#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */
+#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
+#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
+#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
+#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
+#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ6_Pos (6U)
+#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
+#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */
+#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
+#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
+#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
+#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
+#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
+
+#define ADC_SQR2_SQ7_Pos (12U)
+#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */
+#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
+#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
+#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
+#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
+#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
+
+#define ADC_SQR2_SQ8_Pos (18U)
+#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */
+#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
+#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
+#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
+#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
+#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
+
+#define ADC_SQR2_SQ9_Pos (24U)
+#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */
+#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
+#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
+#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
+#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
+#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
+
+/******************** Bit definition for ADC_SQR3 register ********************/
+#define ADC_SQR3_SQ10_Pos (0U)
+#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
+#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */
+#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
+#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
+#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
+#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
+#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ11_Pos (6U)
+#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
+#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */
+#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
+#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
+#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
+#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
+#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
+
+#define ADC_SQR3_SQ12_Pos (12U)
+#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
+#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */
+#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
+#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
+#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
+#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
+#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
+
+#define ADC_SQR3_SQ13_Pos (18U)
+#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
+#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */
+#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
+#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
+#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
+#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
+#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
+
+#define ADC_SQR3_SQ14_Pos (24U)
+#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
+#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */
+#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
+#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
+#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
+#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
+#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
+
+/******************** Bit definition for ADC_SQR4 register ********************/
+#define ADC_SQR4_SQ15_Pos (0U)
+#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
+#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */
+#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
+#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
+#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
+#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
+#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR4_SQ16_Pos (6U)
+#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
+#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */
+#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
+#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
+#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
+#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
+#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_RDATA_Pos (0U)
+#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */
+#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */
+
+/******************** Bit definition for ADC_PW register ********************/
+#define ADC4_PW_AUTOFF_Pos (0U)
+#define ADC4_PW_AUTOFF_Msk (0x1UL << ADC4_PW_AUTOFF_Pos) /*!< 0x00000001 */
+#define ADC4_PW_AUTOFF ADC4_PW_AUTOFF_Msk /*!< ADC Auto-Off mode */
+#define ADC4_PW_DPD_Pos (1U)
+#define ADC4_PW_DPD_Msk (0x1UL << ADC4_PW_DPD_Pos) /*!< 0x00000002 */
+#define ADC4_PW_DPD ADC4_PW_DPD_Msk /*!< ADC Deep Power mode */
+#define ADC4_PW_VREFPROT_Pos (2U)
+#define ADC4_PW_VREFPROT_Msk (0x1UL << ADC4_PW_VREFPROT_Pos) /*!< 0x00000004 */
+#define ADC4_PW_VREFPROT ADC4_PW_VREFPROT_Msk /*!< ADC Vref protection */
+#define ADC4_PW_VREFSECSMP_Pos (3U)
+#define ADC4_PW_VREFSECSMP_Msk (0x1UL << ADC4_PW_VREFSECSMP_Pos) /*!< 0x00000008 */
+#define ADC4_PW_VREFSECSMP ADC4_PW_VREFSECSMP_Msk /*!< ADC Vref Second Sample */
+
+
+/******************** Bit definition for ADC_JSQR register ********************/
+#define ADC_JSQR_JL_Pos (0U)
+#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */
+#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
+#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
+
+#define ADC_JSQR_JEXTSEL_Pos (2U)
+#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */
+#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */
+#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
+#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
+#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
+#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
+#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */
+
+#define ADC_JSQR_JEXTEN_Pos (7U)
+#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */
+#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */
+#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
+#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */
+
+#define ADC_JSQR_JSQ1_Pos (9U)
+#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */
+#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
+#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
+#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
+#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
+#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */
+
+#define ADC_JSQR_JSQ2_Pos (15U)
+#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */
+#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
+#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
+#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
+#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
+#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */
+
+#define ADC_JSQR_JSQ3_Pos (21U)
+#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */
+#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
+#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
+#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
+#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
+#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */
+
+#define ADC_JSQR_JSQ4_Pos (27U)
+#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */
+#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
+#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
+#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
+#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
+#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for ADC_OFR1 register ********************/
+#define ADC_OFR1_OFFSET1_Pos (0U)
+#define ADC_OFR1_OFFSET1_Msk (0x00FFFFFFUL << ADC_OFR1_OFFSET1_Pos)/*!< 0x00FFFFFF */
+#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
+#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
+#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
+#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
+#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
+#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
+#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
+#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
+#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
+#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
+#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
+#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
+#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
+#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */
+#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */
+#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */
+#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */
+#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */
+#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */
+#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */
+#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */
+#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */
+#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */
+#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */
+#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */
+
+#define ADC_OFR1_OFFSETPOS_Pos (24U)
+#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */
+#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */
+#define ADC_OFR1_USAT_Pos (25U)
+#define ADC_OFR1_USAT_Msk (0x1UL << ADC_OFR1_USAT_Pos) /*!< 0x02000000 */
+#define ADC_OFR1_USAT ADC_OFR1_USAT_Msk /*!< ADC offset number 1 saturation enable */
+
+#define ADC_OFR1_SSAT_Pos (26U)
+#define ADC_OFR1_SSAT_Msk (0x1UL << ADC_OFR1_SSAT_Pos) /*!< 0x80000000 */
+#define ADC_OFR1_SSAT ADC_OFR1_SSAT_Msk /*!< ADC Signed saturation Enable */
+
+
+#define ADC_OFR1_OFFSET1_CH_Pos (27U)
+#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
+#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */
+#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
+#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
+#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
+#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
+#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
+
+
+/******************** Bit definition for ADC_OFR2 register ********************/
+#define ADC_OFR2_OFFSET2_Pos (0U)
+#define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */
+#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
+#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
+#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
+#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
+#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
+#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
+#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
+#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
+#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
+#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
+#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
+#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
+#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
+#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */
+#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */
+#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */
+#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */
+#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */
+#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */
+#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */
+#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */
+#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */
+#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */
+#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */
+#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */
+
+#define ADC_OFR2_OFFSETPOS_Pos (24U)
+#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */
+#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 1 positive */
+#define ADC_OFR2_USAT_Pos (25U)
+#define ADC_OFR2_USAT_Msk (0x1UL << ADC_OFR2_USAT_Pos) /*!< 0x02000000 */
+#define ADC_OFR2_USAT ADC_OFR2_USAT_Msk /*!< ADC offset number 1 saturation enable */
+
+#define ADC_OFR2_SSAT_Pos (26U)
+#define ADC_OFR2_SSAT_Msk (0x1UL << ADC_OFR2_SSAT_Pos) /*!< 0x80000000 */
+#define ADC_OFR2_SSAT ADC_OFR2_SSAT_Msk /*!< ADC Signed saturation Enable */
+
+
+
+#define ADC_OFR2_OFFSET2_CH_Pos (27U)
+#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
+#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */
+#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
+#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
+#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
+#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
+#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for ADC_OFR3 register ********************/
+#define ADC_OFR3_OFFSET3_Pos (0U)
+#define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */
+#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
+#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
+#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
+#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
+#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
+#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
+#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
+#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
+#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
+#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
+#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
+#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
+#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
+#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */
+#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */
+#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */
+#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */
+#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */
+#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */
+#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */
+#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */
+#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */
+#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */
+#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */
+#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */
+
+#define ADC_OFR3_OFFSETPOS_Pos (24U)
+#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */
+#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 1 positive */
+#define ADC_OFR3_USAT_Pos (25U)
+#define ADC_OFR3_USAT_Msk (0x1UL << ADC_OFR3_USAT_Pos) /*!< 0x02000000 */
+#define ADC_OFR3_USAT ADC_OFR3_USAT_Msk /*!< ADC offset number 1 saturation enable */
+
+#define ADC_OFR3_SSAT_Pos (26U)
+#define ADC_OFR3_SSAT_Msk (0x1UL << ADC_OFR3_SSAT_Pos) /*!< 0x80000000 */
+#define ADC_OFR3_SSAT ADC_OFR3_SSAT_Msk /*!< ADC Signed saturation Enable */
+
+
+#define ADC_OFR3_OFFSET3_CH_Pos (27U)
+#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
+#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */
+#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
+#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
+#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
+#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
+#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
+
+
+/******************** Bit definition for ADC_OFR4 register ********************/
+#define ADC_OFR4_OFFSET4_Pos (0U)
+#define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */
+#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
+#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
+#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
+#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
+#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
+#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
+#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
+#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
+#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
+#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
+#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
+#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
+#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
+#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */
+#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */
+#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */
+#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */
+#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */
+#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */
+#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */
+#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */
+#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */
+#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */
+#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */
+#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */
+
+#define ADC_OFR4_OFFSETPOS_Pos (24U)
+#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */
+#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 1 positive */
+#define ADC_OFR4_USAT_Pos (25U)
+#define ADC_OFR4_USAT_Msk (0x1UL << ADC_OFR4_USAT_Pos) /*!< 0x02000000 */
+#define ADC_OFR4_USAT ADC_OFR4_USAT_Msk /*!< ADC offset number 1 saturation enable */
+
+#define ADC_OFR4_SSAT_Pos (26U)
+#define ADC_OFR4_SSAT_Msk (0x1UL << ADC_OFR4_SSAT_Pos) /*!< 0x80000000 */
+#define ADC_OFR4_SSAT ADC_OFR4_SSAT_Msk /*!< ADC Signed saturation Enable */
+
+#define ADC_OFR4_OFFSET4_CH_Pos (27U)
+#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
+#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */
+#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
+#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
+#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
+#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
+#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for ADC_GCOMP register ********************/
+#define ADC_GCOMP_GCOMPCOEFF_Pos (0U)
+#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)/*!< 0x00003FFF */
+#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Injected DATA */
+#define ADC_GCOMP_GCOMP_Pos (31U)
+#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x00003FFF */
+#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< ADC Injected DATA */
+
+
+/******************** Bit definition for ADC_JDR1 register ********************/
+#define ADC_JDR1_JDATA_Pos (0U)
+#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */
+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */
+#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
+#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
+#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
+#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
+#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
+#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
+#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
+#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
+#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
+#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
+#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
+#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
+#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
+#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
+#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
+#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
+#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */
+#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */
+#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */
+#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */
+#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */
+#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */
+#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */
+#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */
+#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */
+#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */
+#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */
+#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */
+#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */
+#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */
+#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */
+#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for ADC_JDR2 register ********************/
+#define ADC_JDR2_JDATA_Pos (0U)
+#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */
+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */
+#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
+#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
+#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
+#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
+#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
+#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
+#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
+#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
+#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
+#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
+#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
+#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
+#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
+#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
+#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
+#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
+#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */
+#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */
+#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */
+#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */
+#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */
+#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */
+#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */
+#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */
+#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */
+#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */
+#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */
+#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */
+#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */
+#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */
+#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */
+#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for ADC_JDR3 register ********************/
+#define ADC_JDR3_JDATA_Pos (0U)
+#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */
+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */
+#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
+#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
+#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
+#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
+#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
+#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
+#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
+#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
+#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
+#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
+#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
+#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
+#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
+#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
+#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
+#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
+#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */
+#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */
+#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */
+#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */
+#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */
+#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */
+#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */
+#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */
+#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */
+#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */
+#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */
+#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */
+#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */
+#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */
+#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */
+#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for ADC_JDR4 register ********************/
+#define ADC_JDR4_JDATA_Pos (0U)
+#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */
+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */
+#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
+#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
+#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
+#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
+#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
+#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
+#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
+#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
+#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
+#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
+#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
+#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
+#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
+#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
+#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
+#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
+#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */
+#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */
+#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */
+#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */
+#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */
+#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */
+#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */
+#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */
+#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */
+#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */
+#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */
+#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */
+#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */
+#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */
+#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */
+#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for ADC_AWD2CR register ********************/
+#define ADC_AWD2CR_AWD2CH_Pos (0U)
+#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00FFFFFF */
+#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */
+#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
+#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
+#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
+#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
+#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
+#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
+#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
+#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
+#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
+#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
+#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
+#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
+#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
+#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
+#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
+#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
+#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
+#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
+#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
+#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */
+#define ADC_AWD2CR_AWD2CH_20 (0x100000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00100000 */
+#define ADC_AWD2CR_AWD2CH_21 (0x200000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00200000 */
+#define ADC_AWD2CR_AWD2CH_22 (0x400000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00400000 */
+#define ADC_AWD2CR_AWD2CH_23 (0x800000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00800000 */
+
+
+/******************** Bit definition for ADC_AWD1TR register *******************/
+#define ADC_AWD1TR_LT1_Pos (0U)
+#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */
+#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
+#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */
+#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */
+#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */
+#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */
+#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */
+#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */
+#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */
+#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */
+#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */
+#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */
+#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */
+#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */
+
+#define ADC_AWD1TR_HT1_Pos (16U)
+#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */
+#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
+#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */
+#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */
+#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */
+#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */
+#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */
+#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */
+#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */
+#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */
+#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */
+#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */
+#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */
+#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */
+
+/******************** Bit definition for ADC_AWDTR2 register *******************/
+#define ADC_AWD2TR_LT2_Pos (0U)
+#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */
+#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
+#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */
+#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */
+#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */
+#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */
+#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */
+#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */
+#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */
+#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */
+#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */
+#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */
+#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */
+#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */
+
+#define ADC_AWD2TR_HT2_Pos (16U)
+#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */
+#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
+#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */
+#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */
+#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */
+#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */
+#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */
+#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */
+#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */
+#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */
+#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */
+#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */
+#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */
+#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */
+
+/******************** Bit definition for ADC_CHSELR register ****************/
+#define ADC_CHSELR_CHSEL_Pos (0U)
+#define ADC_CHSELR_CHSEL_Msk (0xFFFFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
+#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */
+
+#define ADC_CHSELR_CHSEL0_Pos (0U)
+#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
+#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL1_Pos (1U)
+#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
+#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL2_Pos (2U)
+#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
+#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL3_Pos (3U)
+#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
+#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL4_Pos (4U)
+#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
+#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL5_Pos (5U)
+#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
+#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL6_Pos (6U)
+#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
+#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL7_Pos (7U)
+#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
+#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL8_Pos (8U)
+#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
+#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL9_Pos (9U)
+#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
+#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL10_Pos (10U)
+#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
+#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL11_Pos (11U)
+#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
+#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL12_Pos (12U)
+#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
+#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL13_Pos (13U)
+#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
+#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL14_Pos (14U)
+#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
+#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL15_Pos (15U)
+#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
+#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL16_Pos (16U)
+#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */
+#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL17_Pos (17U)
+#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
+#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL18_Pos (18U)
+#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
+#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL19_Pos (19U)
+#define ADC_CHSELR_CHSEL19_Msk (0x1UL << ADC_CHSELR_CHSEL19_Pos) /*!< 0x00040000 */
+#define ADC_CHSELR_CHSEL19 ADC_CHSELR_CHSEL19_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL20_Pos (20U)
+#define ADC_CHSELR_CHSEL20_Msk (0x1UL << ADC_CHSELR_CHSEL20_Pos) /*!< 0x00040000 */
+#define ADC_CHSELR_CHSEL20 ADC_CHSELR_CHSEL20_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL21_Pos (21U)
+#define ADC_CHSELR_CHSEL21_Msk (0x1UL << ADC_CHSELR_CHSEL21_Pos) /*!< 0x00040000 */
+#define ADC_CHSELR_CHSEL21 ADC_CHSELR_CHSEL21_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL22_Pos (22U)
+#define ADC_CHSELR_CHSEL22_Msk (0x1UL << ADC_CHSELR_CHSEL22_Pos) /*!< 0x00040000 */
+#define ADC_CHSELR_CHSEL22 ADC_CHSELR_CHSEL22_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL23_Pos (23U)
+#define ADC_CHSELR_CHSEL23_Msk (0x1UL << ADC_CHSELR_CHSEL23_Pos) /*!< 0x00040000 */
+#define ADC_CHSELR_CHSEL23 ADC_CHSELR_CHSEL23_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */
+
+#define ADC_CHSELR_SQ_ALL_Pos (0U)
+#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */
+#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */
+
+#define ADC_CHSELR_SQ1_Pos (0U)
+#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */
+#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */
+#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */
+#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */
+#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */
+#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */
+
+#define ADC_CHSELR_SQ2_Pos (4U)
+#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */
+#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */
+#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */
+#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */
+#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */
+#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */
+
+#define ADC_CHSELR_SQ3_Pos (8U)
+#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */
+#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */
+#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */
+#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */
+#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */
+#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */
+
+#define ADC_CHSELR_SQ4_Pos (12U)
+#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */
+#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */
+#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */
+#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */
+#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */
+#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */
+
+#define ADC_CHSELR_SQ5_Pos (16U)
+#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */
+#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */
+#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */
+#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */
+#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */
+#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */
+
+#define ADC_CHSELR_SQ6_Pos (20U)
+#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */
+#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */
+#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */
+#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */
+#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */
+#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */
+
+#define ADC_CHSELR_SQ7_Pos (24U)
+#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */
+#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */
+#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */
+#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */
+#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */
+#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */
+
+#define ADC_CHSELR_SQ8_Pos (28U)
+#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */
+#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */
+#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */
+#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */
+#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */
+#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */
+
+
+/******************** Bit definition for ADC_AWD3TR register *******************/
+#define ADC_AWD3TR_LT3_Pos (0U)
+#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */
+#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
+#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */
+#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */
+#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */
+#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */
+#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */
+#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */
+#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */
+#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */
+#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */
+#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */
+#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */
+#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */
+
+#define ADC_AWD3TR_HT3_Pos (16U)
+#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */
+#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
+#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */
+#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */
+#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */
+#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */
+#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */
+#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */
+#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */
+#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */
+#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */
+#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */
+#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */
+#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */
+
+
+/******************** Bit definition for ADC_AWD3CR register ********************/
+#define ADC_AWD3CR_AWD3CH_Pos (0U)
+#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00FFFFFF */
+#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */
+#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
+#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
+#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
+#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
+#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
+#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
+#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
+#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
+#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
+#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
+#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
+#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
+#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
+#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
+#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
+#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
+#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
+#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
+#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
+#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */
+#define ADC_AWD3CR_AWD2CH_20 (0x100000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00100000 */
+#define ADC_AWD3CR_AWD2CH_21 (0x200000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00200000 */
+#define ADC_AWD3CR_AWD2CH_22 (0x400000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00400000 */
+#define ADC_AWD3CR_AWD2CH_23 (0x800000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00800000 */
+
+/******************** Bit definition for ADC_DIFSEL register ********************/
+#define ADC_DIFSEL_DIFSEL_Pos (0U)
+#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */
+#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */
+#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
+#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
+#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
+#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
+#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
+#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
+#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
+#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
+#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
+#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
+#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
+#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
+#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
+#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
+#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
+#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
+#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
+#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
+#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
+#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */
+
+/******************** Bit definition for ADC_CALFACT register ********************/
+#define ADC_CALFACT_I_APB_ADDR_Pos (0U)
+#define ADC_CALFACT_I_APB_ADDR_Msk (0xFFUL << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x000000FF */
+#define ADC_CALFACT_I_APB_ADDR ADC_CALFACT_I_APB_ADDR_Msk /*!< ADC calibration factors in single-ended mode */
+#define ADC_CALFACT_I_APB_ADDR_0 (0x001U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000001 */
+#define ADC_CALFACT_I_APB_ADDR_1 (0x002U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000002 */
+#define ADC_CALFACT_I_APB_ADDR_2 (0x004U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000004 */
+#define ADC_CALFACT_I_APB_ADDR_3 (0x008U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000008 */
+#define ADC_CALFACT_I_APB_ADDR_4 (0x010U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000010 */
+#define ADC_CALFACT_I_APB_ADDR_5 (0x020U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000020 */
+#define ADC_CALFACT_I_APB_ADDR_6 (0x040U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000040 */
+#define ADC_CALFACT_I_APB_ADDR_7 (0x080U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000080 */
+
+#define ADC_CALFACT_I_APB_DATA_Pos (08U)
+#define ADC_CALFACT_I_APB_DATA_Msk (0xFFUL << ADC_CALFACT_I_APB_DATA_Pos) /*!< 0x0000FF00 */
+#define ADC_CALFACT_I_APB_DATA ADC_CALFACT_I_APB_DATA_Msk /*!< ADC calibration factors in differential mode */
+#define ADC_CALFACT_APB_DATA_0 (0x001U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000100 */
+#define ADC_CALFACT_APB_DATA_1 (0x002U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000200 */
+#define ADC_CALFACT_APB_DATA_2 (0x004U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000400 */
+#define ADC_CALFACT_APB_DATA_3 (0x008U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000800 */
+#define ADC_CALFACT_APB_DATA_4 (0x010U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00001000 */
+#define ADC_CALFACT_APB_DATA_5 (0x020U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00002000 */
+#define ADC_CALFACT_APB_DATA_6 (0x040U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00004000 */
+#define ADC_CALFACT_APB_DATA_7 (0x080U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00008000 */
+
+#define ADC_CALFACT_VALIDITY_Pos (16U)
+#define ADC_CALFACT_VALIDITY_Msk (0x1UL << ADC_CALFACT_VALIDITY_Pos) /*!< 0x00010000 */
+#define ADC_CALFACT_VALIDITY ADC_CALFACT_VALIDITY_Msk /*!< ADC calibration factors in differential mode */
+#define ADC_CALFACT_LATCH_COEF_Pos (24U)
+#define ADC_CALFACT_LATCH_COEF_Msk (0x1UL << ADC_CALFACT_LATCH_COEF_Pos) /*!< 0x01000000 */
+#define ADC_CALFACT_LATCH_COEF ADC_CALFACT_LATCH_COEF_Msk /*!< ADC calibration factors in differential mode */
+#define ADC_CALFACT_CAPTURE_COEF_Pos (25U)
+#define ADC_CALFACT_CAPTURE_COEF_Msk (0x1UL << ADC_CALFACT_CAPTURE_COEF_Pos) /*!< 0x01000000 */
+#define ADC_CALFACT_CAPTURE_COEF ADC_CALFACT_CAPTURE_COEF_Msk /*!< ADC calibration factors in differential mode */
+
+
+#define ADC4_CALFACT_CALFACT_Pos (0U)
+#define ADC4_CALFACT_CALFACT_Msk (0x7FUL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x0000007F */
+#define ADC4_CALFACT_CALFACT ADC4_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */
+#define ADC4_CALFACT_CALFACT_0 (0x01UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000001 */
+#define ADC4_CALFACT_CALFACT_1 (0x02UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000002 */
+#define ADC4_CALFACT_CALFACT_2 (0x04UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000004 */
+#define ADC4_CALFACT_CALFACT_3 (0x08UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000008 */
+#define ADC4_CALFACT_CALFACT_4 (0x10UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000010 */
+#define ADC4_CALFACT_CALFACT_5 (0x20UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000020 */
+#define ADC4_CALFACT_CALFACT_6 (0x40UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000040 */
+
+
+
+/******************** Bit definition for ADC_CALFACT2 register ********************/
+#define ADC_CALFACT2_CALFACT_Pos (0U)
+#define ADC_CALFACT2_CALFACT_Msk (0xFFFFFFFFUL << ADC_CALFACT2_CALFACT_Pos) /*!< 0xFFFFFFFF */
+#define ADC_CALFACT2_CALFACT ADC_CALFACT2_CALFACT_Msk /*!< ADC Linearity calibration factors */
+#define ADC_CALFACT2_CALFACT_0 (0x00000001UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000001 */
+#define ADC_CALFACT2_CALFACT_1 (0x00000002UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000002 */
+#define ADC_CALFACT2_CALFACT_2 (0x00000004UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000004 */
+#define ADC_CALFACT2_CALFACT_3 (0x00000008UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000008 */
+#define ADC_CALFACT2_CALFACT_4 (0x00000010UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000010 */
+#define ADC_CALFACT2_CALFACT_5 (0x00000020UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000020 */
+#define ADC_CALFACT2_CALFACT_6 (0x00000040UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000040 */
+#define ADC_CALFACT2_CALFACT_7 (0x00000080UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000080 */
+#define ADC_CALFACT2_CALFACT_8 (0x00000100UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000100 */
+#define ADC_CALFACT2_CALFACT_9 (0x00000200UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000200 */
+#define ADC_CALFACT2_CALFACT_10 (0x00000400UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000400 */
+#define ADC_CALFACT2_CALFACT_11 (0x00000800UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000800 */
+#define ADC_CALFACT2_CALFACT_12 (0x00001000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00001000 */
+#define ADC_CALFACT2_CALFACT_13 (0x00002000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00002000 */
+#define ADC_CALFACT2_CALFACT_14 (0x00004000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00004000 */
+#define ADC_CALFACT2_CALFACT_15 (0x00008000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00008000 */
+#define ADC_CALFACT2_CALFACT_16 (0x00010000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00010000 */
+#define ADC_CALFACT2_CALFACT_17 (0x00020000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00020000 */
+#define ADC_CALFACT2_CALFACT_18 (0x00040000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00040000 */
+#define ADC_CALFACT2_CALFACT_19 (0x00080000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00080000 */
+#define ADC_CALFACT2_CALFACT_20 (0x00100000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00100000 */
+#define ADC_CALFACT2_CALFACT_21 (0x00200000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00200000 */
+#define ADC_CALFACT2_CALFACT_22 (0x00400000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00400000 */
+#define ADC_CALFACT2_CALFACT_23 (0x00800000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00800000 */
+#define ADC_CALFACT2_CALFACT_24 (0x01000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x01000000 */
+#define ADC_CALFACT2_CALFACT_25 (0x02000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x02000000 */
+#define ADC_CALFACT2_CALFACT_26 (0x04000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x04000000 */
+#define ADC_CALFACT2_CALFACT_27 (0x08000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x08000000 */
+#define ADC_CALFACT2_CALFACT_28 (0x10000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x10000000 */
+#define ADC_CALFACT2_CALFACT_29 (0x20000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x20000000 */
+#define ADC_CALFACT2_CALFACT_30 (0x40000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x40000000 */
+#define ADC_CALFACT2_CALFACT_31 (0x80000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x80000000 */
+
+
+/******************** Bit definition for ADC_OR register ********************/
+#define ADC_OR_CHN0SEL_Pos (0U)
+#define ADC_OR_CHN0SEL_Msk (0x1UL << ADC_OR_CHN0SEL_Pos) /*!< 0x00000001 */
+#define ADC_OR_CHN0SEL ADC_OR_CHN0SEL_Msk /*!< ADC Channel 0 selection */
+
+
+/************************* ADC Common registers *****************************/
+/******************** Bit definition for ADC_CCR register ********************/
+
+
+#define ADC_CCR_PRESC_Pos (18U)
+#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
+#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */
+#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
+#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
+#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
+#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
+
+#define ADC_CCR_VREFEN_Pos (22U)
+#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */
+#define ADC_CCR_VSENSEEN_Pos (23U)
+#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */
+#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */
+#define ADC_CCR_VBATEN_Pos (24U)
+#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
+#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */
+#define ADC_CCR_LFMEN_Pos (25U)
+#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
+#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode Enable, specific ADC4*/
+#define ADC_CCR_VDDCOREN_Pos (26U)
+#define ADC_CCR_VDDCOREN_Msk (0x1UL << ADC_CCR_VDDCOREN_Pos) /*!< 0x04000000 */
+#define ADC_CCR_VDDCOREN ADC_CCR_VDDCOREN_Msk /*!< VDDCode enable */
+
+
+/******************************************************************************/
+/* */
+/* CORDIC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CORDIC_CSR register *****************/
+#define CORDIC_CSR_FUNC_Pos (0U)
+#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */
+#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */
+#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */
+#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */
+#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */
+#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */
+#define CORDIC_CSR_PRECISION_Pos (4U)
+#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */
+#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */
+#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */
+#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */
+#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */
+#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */
+#define CORDIC_CSR_SCALE_Pos (8U)
+#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */
+#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */
+#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */
+#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */
+#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */
+#define CORDIC_CSR_IEN_Pos (16U)
+#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */
+#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */
+#define CORDIC_CSR_DMAREN_Pos (17U)
+#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */
+#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */
+#define CORDIC_CSR_DMAWEN_Pos (18U)
+#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */
+#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */
+#define CORDIC_CSR_NRES_Pos (19U)
+#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */
+#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */
+#define CORDIC_CSR_NARGS_Pos (20U)
+#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */
+#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */
+#define CORDIC_CSR_RESSIZE_Pos (21U)
+#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */
+#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */
+#define CORDIC_CSR_ARGSIZE_Pos (22U)
+#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */
+#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */
+#define CORDIC_CSR_RRDY_Pos (31U)
+#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */
+#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */
+
+/******************* Bit definition for CORDIC_WDATA register ***************/
+#define CORDIC_WDATA_ARG_Pos (0U)
+#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */
+#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */
+
+/******************* Bit definition for CORDIC_RDATA register ***************/
+#define CORDIC_RDATA_RES_Pos (0U)
+#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */
+#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */
+
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR_Pos (0U)
+#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos (3U)
+#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos (5U)
+#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
+#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos (7U)
+#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
+#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
+
+/******************* Bit definition for CRC_INIT register *******************/
+#define CRC_INIT_INIT_Pos (0U)
+#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
+
+/******************* Bit definition for CRC_POL register ********************/
+#define CRC_POL_POL_Pos (0U)
+#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
+#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
+
+
+/******************************************************************************/
+/* */
+/* CRS Clock Recovery System */
+/******************************************************************************/
+/******************* Bit definition for CRS_CR register *********************/
+#define CRS_CR_SYNCOKIE_Pos (0U)
+#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
+#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */
+#define CRS_CR_SYNCWARNIE_Pos (1U)
+#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
+#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */
+#define CRS_CR_ERRIE_Pos (2U)
+#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
+#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */
+#define CRS_CR_ESYNCIE_Pos (3U)
+#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
+#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */
+#define CRS_CR_CEN_Pos (5U)
+#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */
+#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */
+#define CRS_CR_AUTOTRIMEN_Pos (6U)
+#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
+#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */
+#define CRS_CR_SWSYNC_Pos (7U)
+#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
+#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
+#define CRS_CR_TRIM_Pos (8U)
+#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
+#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
+
+/******************* Bit definition for CRS_CFGR register *********************/
+#define CRS_CFGR_RELOAD_Pos (0U)
+#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
+#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */
+#define CRS_CFGR_FELIM_Pos (16U)
+#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
+#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */
+#define CRS_CFGR_SYNCDIV_Pos (24U)
+#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
+#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */
+#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
+#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
+#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
+#define CRS_CFGR_SYNCSRC_Pos (28U)
+#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
+#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */
+#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
+#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
+#define CRS_CFGR_SYNCPOL_Pos (31U)
+#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
+#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */
+
+/******************* Bit definition for CRS_ISR register *********************/
+#define CRS_ISR_SYNCOKF_Pos (0U)
+#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
+#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */
+#define CRS_ISR_SYNCWARNF_Pos (1U)
+#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
+#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */
+#define CRS_ISR_ERRF_Pos (2U)
+#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
+#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */
+#define CRS_ISR_ESYNCF_Pos (3U)
+#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
+#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */
+#define CRS_ISR_SYNCERR_Pos (8U)
+#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
+#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */
+#define CRS_ISR_SYNCMISS_Pos (9U)
+#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
+#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */
+#define CRS_ISR_TRIMOVF_Pos (10U)
+#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
+#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */
+#define CRS_ISR_FEDIR_Pos (15U)
+#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
+#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */
+#define CRS_ISR_FECAP_Pos (16U)
+#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
+#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */
+
+/******************* Bit definition for CRS_ICR register *********************/
+#define CRS_ICR_SYNCOKC_Pos (0U)
+#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
+#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */
+#define CRS_ICR_SYNCWARNC_Pos (1U)
+#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
+#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */
+#define CRS_ICR_ERRC_Pos (2U)
+#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
+#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */
+#define CRS_ICR_ESYNCC_Pos (3U)
+#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
+#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */
+
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN_Pos (2U)
+#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
+#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
+#define RNG_CR_IE_Pos (3U)
+#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
+#define RNG_CR_IE RNG_CR_IE_Msk
+#define RNG_CR_CED_Pos (5U)
+#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */
+#define RNG_CR_CED RNG_CR_CED_Msk
+#define RNG_CR_ARDIS_Pos (7U)
+#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos)
+#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk
+#define RNG_CR_RNG_CONFIG3_Pos (8U)
+#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos)
+#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk
+#define RNG_CR_NISTC_Pos (12U)
+#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos)
+#define RNG_CR_NISTC RNG_CR_NISTC_Msk
+#define RNG_CR_RNG_CONFIG2_Pos (13U)
+#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos)
+#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk
+#define RNG_CR_CLKDIV_Pos (16U)
+#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos)
+#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk
+#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */
+#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */
+#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */
+#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */
+#define RNG_CR_RNG_CONFIG1_Pos (20U)
+#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos)
+#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk
+#define RNG_CR_CONDRST_Pos (30U)
+#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos)
+#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk
+#define RNG_CR_CONFIGLOCK_Pos (31U)
+#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos)
+#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY_Pos (0U)
+#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
+#define RNG_SR_DRDY RNG_SR_DRDY_Msk
+#define RNG_SR_CECS_Pos (1U)
+#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */
+#define RNG_SR_CECS RNG_SR_CECS_Msk
+#define RNG_SR_SECS_Pos (2U)
+#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */
+#define RNG_SR_SECS RNG_SR_SECS_Msk
+#define RNG_SR_CEIS_Pos (5U)
+#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
+#define RNG_SR_CEIS RNG_SR_CEIS_Msk
+#define RNG_SR_SEIS_Pos (6U)
+#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
+#define RNG_SR_SEIS RNG_SR_SEIS_Msk
+
+/******************** Bits definition for RNG_HTCR register *******************/
+#define RNG_HTCR_HTCFG_Pos (0U)
+#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */
+#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */
+
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1_Pos (0U)
+#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */
+#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/
+#define DAC_CR_CEN1_Pos (14U)
+#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
+#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/
+#define DAC_CR_EN2_Pos (16U)
+#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */
+#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/
+#define DAC_CR_CEN2_Pos (30U)
+#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
+#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
+#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1U)
+
+#define FLASH_PAGE_SIZE 0x2000U /* 8 KB */
+
+#define FLASH_PAGE_NB (FLASH_BANK_SIZE / FLASH_PAGE_SIZE)
+
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */
+#define FLASH_ACR_LATENCY_0WS (0x00000000U)
+#define FLASH_ACR_LATENCY_1WS (0x00000001U)
+#define FLASH_ACR_LATENCY_2WS (0x00000002U)
+#define FLASH_ACR_LATENCY_3WS (0x00000003U)
+#define FLASH_ACR_LATENCY_4WS (0x00000004U)
+#define FLASH_ACR_LATENCY_5WS (0x00000005U)
+#define FLASH_ACR_LATENCY_6WS (0x00000006U)
+#define FLASH_ACR_LATENCY_7WS (0x00000007U)
+#define FLASH_ACR_LATENCY_8WS (0x00000008U)
+#define FLASH_ACR_LATENCY_9WS (0x00000009U)
+#define FLASH_ACR_LATENCY_10WS (0x0000000AU)
+#define FLASH_ACR_LATENCY_11WS (0x0000000BU)
+#define FLASH_ACR_LATENCY_12WS (0x0000000CU)
+#define FLASH_ACR_LATENCY_13WS (0x0000000DU)
+#define FLASH_ACR_LATENCY_14WS (0x0000000EU)
+#define FLASH_ACR_LATENCY_15WS (0x0000000FU)
+#define FLASH_ACR_PRFTEN_Pos (8U)
+#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */
+#define FLASH_ACR_LPM_Pos (11U)
+#define FLASH_ACR_LPM_Msk (0x1UL << FLASH_ACR_LPM_Pos) /*!< 0x00000800 */
+#define FLASH_ACR_LPM FLASH_ACR_LPM_Msk /*!< Low-Power read mode */
+#define FLASH_ACR_PDREQ1_Pos (12U)
+#define FLASH_ACR_PDREQ1_Msk (0x1UL << FLASH_ACR_PDREQ1_Pos) /*!< 0x00001000 */
+#define FLASH_ACR_PDREQ1 FLASH_ACR_PDREQ1_Msk /*!< Bank 1 power-down mode request */
+#define FLASH_ACR_PDREQ2_Pos (13U)
+#define FLASH_ACR_PDREQ2_Msk (0x1UL << FLASH_ACR_PDREQ2_Pos) /*!< 0x00002000 */
+#define FLASH_ACR_PDREQ2 FLASH_ACR_PDREQ2_Msk /*!< Bank 2 power-down mode request */
+#define FLASH_ACR_SLEEP_PD_Pos (14U)
+#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */
+#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power-down mode during sleep */
+
+/****************** Bits definition for FLASH_NSSR register *****************/
+#define FLASH_NSSR_EOP_Pos (0U)
+#define FLASH_NSSR_EOP_Msk (0x1UL << FLASH_NSSR_EOP_Pos) /*!< 0x00000001 */
+#define FLASH_NSSR_EOP FLASH_NSSR_EOP_Msk /*!< Non-secure end of operation */
+#define FLASH_NSSR_OPERR_Pos (1U)
+#define FLASH_NSSR_OPERR_Msk (0x1UL << FLASH_NSSR_OPERR_Pos) /*!< 0x00000002 */
+#define FLASH_NSSR_OPERR FLASH_NSSR_OPERR_Msk /*!< Non-secure operation error */
+#define FLASH_NSSR_PROGERR_Pos (3U)
+#define FLASH_NSSR_PROGERR_Msk (0x1UL << FLASH_NSSR_PROGERR_Pos) /*!< 0x00000008 */
+#define FLASH_NSSR_PROGERR FLASH_NSSR_PROGERR_Msk /*!< Non-secure programming error */
+#define FLASH_NSSR_WRPERR_Pos (4U)
+#define FLASH_NSSR_WRPERR_Msk (0x1UL << FLASH_NSSR_WRPERR_Pos) /*!< 0x00000010 */
+#define FLASH_NSSR_WRPERR FLASH_NSSR_WRPERR_Msk /*!< Non-secure write protection error */
+#define FLASH_NSSR_PGAERR_Pos (5U)
+#define FLASH_NSSR_PGAERR_Msk (0x1UL << FLASH_NSSR_PGAERR_Pos) /*!< 0x00000020 */
+#define FLASH_NSSR_PGAERR FLASH_NSSR_PGAERR_Msk /*!< Non-secure programming alignment error */
+#define FLASH_NSSR_SIZERR_Pos (6U)
+#define FLASH_NSSR_SIZERR_Msk (0x1UL << FLASH_NSSR_SIZERR_Pos) /*!< 0x00000040 */
+#define FLASH_NSSR_SIZERR FLASH_NSSR_SIZERR_Msk /*!< Non-secure size error */
+#define FLASH_NSSR_PGSERR_Pos (7U)
+#define FLASH_NSSR_PGSERR_Msk (0x1UL << FLASH_NSSR_PGSERR_Pos) /*!< 0x00000080 */
+#define FLASH_NSSR_PGSERR FLASH_NSSR_PGSERR_Msk /*!< Non-secure programming sequence error */
+#define FLASH_NSSR_OPTWERR_Pos (13U)
+#define FLASH_NSSR_OPTWERR_Msk (0x1UL << FLASH_NSSR_OPTWERR_Pos) /*!< 0x00002000 */
+#define FLASH_NSSR_OPTWERR FLASH_NSSR_OPTWERR_Msk /*!< Option write error */
+#define FLASH_NSSR_BSY_Pos (16U)
+#define FLASH_NSSR_BSY_Msk (0x1UL << FLASH_NSSR_BSY_Pos) /*!< 0x00010000 */
+#define FLASH_NSSR_BSY FLASH_NSSR_BSY_Msk /*!< Non-secure busy */
+#define FLASH_NSSR_WDW_Pos (17U)
+#define FLASH_NSSR_WDW_Msk (0x1UL << FLASH_NSSR_WDW_Pos) /*!< 0x00020000 */
+#define FLASH_NSSR_WDW FLASH_NSSR_WDW_Msk /*!< Non-secure wait data to write */
+#define FLASH_NSSR_OEM1LOCK_Pos (18U)
+#define FLASH_NSSR_OEM1LOCK_Msk (0x1UL << FLASH_NSSR_OEM1LOCK_Pos) /*!< 0x00040000 */
+#define FLASH_NSSR_OEM1LOCK FLASH_NSSR_OEM1LOCK_Msk /*!< OEM1 lock */
+#define FLASH_NSSR_OEM2LOCK_Pos (19U)
+#define FLASH_NSSR_OEM2LOCK_Msk (0x1UL << FLASH_NSSR_OEM2LOCK_Pos) /*!< 0x00080000 */
+#define FLASH_NSSR_OEM2LOCK FLASH_NSSR_OEM2LOCK_Msk /*!< OEM2 lock */
+#define FLASH_NSSR_PD1_Pos (20U)
+#define FLASH_NSSR_PD1_Msk (0x1UL << FLASH_NSSR_PD1_Pos) /*!< 0x00100000 */
+#define FLASH_NSSR_PD1 FLASH_NSSR_PD1_Msk /*!< Bank 1 in power-down mode */
+#define FLASH_NSSR_PD2_Pos (21U)
+#define FLASH_NSSR_PD2_Msk (0x1UL << FLASH_NSSR_PD2_Pos) /*!< 0x00200000 */
+#define FLASH_NSSR_PD2 FLASH_NSSR_PD2_Msk /*!< Bank 2 in power-down mode */
+
+/****************** Bits definition for FLASH_SECSR register ****************/
+#define FLASH_SECSR_EOP_Pos (0U)
+#define FLASH_SECSR_EOP_Msk (0x1UL << FLASH_SECSR_EOP_Pos) /*!< 0x00000001 */
+#define FLASH_SECSR_EOP FLASH_SECSR_EOP_Msk /*!< Secure end of operation */
+#define FLASH_SECSR_OPERR_Pos (1U)
+#define FLASH_SECSR_OPERR_Msk (0x1UL << FLASH_SECSR_OPERR_Pos) /*!< 0x00000002 */
+#define FLASH_SECSR_OPERR FLASH_SECSR_OPERR_Msk /*!< Secure operation error */
+#define FLASH_SECSR_PROGERR_Pos (3U)
+#define FLASH_SECSR_PROGERR_Msk (0x1UL << FLASH_SECSR_PROGERR_Pos) /*!< 0x00000008 */
+#define FLASH_SECSR_PROGERR FLASH_SECSR_PROGERR_Msk /*!< Secure programming error */
+#define FLASH_SECSR_WRPERR_Pos (4U)
+#define FLASH_SECSR_WRPERR_Msk (0x1UL << FLASH_SECSR_WRPERR_Pos) /*!< 0x00000010 */
+#define FLASH_SECSR_WRPERR FLASH_SECSR_WRPERR_Msk /*!< Secure write protection error */
+#define FLASH_SECSR_PGAERR_Pos (5U)
+#define FLASH_SECSR_PGAERR_Msk (0x1UL << FLASH_SECSR_PGAERR_Pos) /*!< 0x00000020 */
+#define FLASH_SECSR_PGAERR FLASH_SECSR_PGAERR_Msk /*!< Secure programming alignment error */
+#define FLASH_SECSR_SIZERR_Pos (6U)
+#define FLASH_SECSR_SIZERR_Msk (0x1UL << FLASH_SECSR_SIZERR_Pos) /*!< 0x00000040 */
+#define FLASH_SECSR_SIZERR FLASH_SECSR_SIZERR_Msk /*!< Secure size error */
+#define FLASH_SECSR_PGSERR_Pos (7U)
+#define FLASH_SECSR_PGSERR_Msk (0x1UL << FLASH_SECSR_PGSERR_Pos) /*!< 0x00000080 */
+#define FLASH_SECSR_PGSERR FLASH_SECSR_PGSERR_Msk /*!< Secure programming sequence error */
+#define FLASH_SECSR_BSY_Pos (16U)
+#define FLASH_SECSR_BSY_Msk (0x1UL << FLASH_SECSR_BSY_Pos) /*!< 0x00010000 */
+#define FLASH_SECSR_BSY FLASH_SECSR_BSY_Msk /*!< Secure busy */
+#define FLASH_SECSR_WDW_Pos (17U)
+#define FLASH_SECSR_WDW_Msk (0x1UL << FLASH_SECSR_WDW_Pos) /*!< 0x00020000 */
+#define FLASH_SECSR_WDW FLASH_SECSR_WDW_Msk /*!< Secure wait data to write */
+
+/****************** Bits definition for FLASH_NSCR register *****************/
+#define FLASH_NSCR_PG_Pos (0U)
+#define FLASH_NSCR_PG_Msk (0x1UL << FLASH_NSCR_PG_Pos) /*!< 0x00000001 */
+#define FLASH_NSCR_PG FLASH_NSCR_PG_Msk /*!< Non-secure Programming */
+#define FLASH_NSCR_PER_Pos (1U)
+#define FLASH_NSCR_PER_Msk (0x1UL << FLASH_NSCR_PER_Pos) /*!< 0x00000002 */
+#define FLASH_NSCR_PER FLASH_NSCR_PER_Msk /*!< Non-secure Page Erase */
+#define FLASH_NSCR_MER1_Pos (2U)
+#define FLASH_NSCR_MER1_Msk (0x1UL << FLASH_NSCR_MER1_Pos) /*!< 0x00000004 */
+#define FLASH_NSCR_MER1 FLASH_NSCR_MER1_Msk /*!< Non-secure Bank 1 Mass Erase */
+#define FLASH_NSCR_PNB_Pos (3U)
+#define FLASH_NSCR_PNB_Msk (0x7FUL << FLASH_NSCR_PNB_Pos) /*!< 0x000003F8 */
+#define FLASH_NSCR_PNB FLASH_NSCR_PNB_Msk /*!< Non-secure Page Number selection */
+#define FLASH_NSCR_BKER_Pos (11U)
+#define FLASH_NSCR_BKER_Msk (0x1UL << FLASH_NSCR_BKER_Pos) /*!< 0x00000800 */
+#define FLASH_NSCR_BKER FLASH_NSCR_BKER_Msk /*!< Non-secure Bank Selection for Page Erase */
+#define FLASH_NSCR_BWR_Pos (14U)
+#define FLASH_NSCR_BWR_Msk (0x1UL << FLASH_NSCR_BWR_Pos) /*!< 0x00004000 */
+#define FLASH_NSCR_BWR FLASH_NSCR_BWR_Msk /*!< Non-secure Burst Write Programming mode */
+#define FLASH_NSCR_MER2_Pos (15U)
+#define FLASH_NSCR_MER2_Msk (0x1UL << FLASH_NSCR_MER2_Pos) /*!< 0x00008000 */
+#define FLASH_NSCR_MER2 FLASH_NSCR_MER2_Msk /*!< Non-secure Bank 2 Mass Erase */
+#define FLASH_NSCR_STRT_Pos (16U)
+#define FLASH_NSCR_STRT_Msk (0x1UL << FLASH_NSCR_STRT_Pos) /*!< 0x00010000 */
+#define FLASH_NSCR_STRT FLASH_NSCR_STRT_Msk /*!< Non-secure Start */
+#define FLASH_NSCR_OPTSTRT_Pos (17U)
+#define FLASH_NSCR_OPTSTRT_Msk (0x1UL << FLASH_NSCR_OPTSTRT_Pos) /*!< 0x00020000 */
+#define FLASH_NSCR_OPTSTRT FLASH_NSCR_OPTSTRT_Msk /*!< Option Modification Start */
+#define FLASH_NSCR_EOPIE_Pos (24U)
+#define FLASH_NSCR_EOPIE_Msk (0x1UL << FLASH_NSCR_EOPIE_Pos) /*!< 0x01000000 */
+#define FLASH_NSCR_EOPIE FLASH_NSCR_EOPIE_Msk /*!< Non-secure End of operation interrupt enable */
+#define FLASH_NSCR_ERRIE_Pos (25U)
+#define FLASH_NSCR_ERRIE_Msk (0x1UL << FLASH_NSCR_ERRIE_Pos) /*!< 0x02000000 */
+#define FLASH_NSCR_ERRIE FLASH_NSCR_ERRIE_Msk /*!< Non-secure error interrupt enable */
+#define FLASH_NSCR_OBL_LAUNCH_Pos (27U)
+#define FLASH_NSCR_OBL_LAUNCH_Msk (0x1UL << FLASH_NSCR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
+#define FLASH_NSCR_OBL_LAUNCH FLASH_NSCR_OBL_LAUNCH_Msk /*!< Force the option byte loading */
+#define FLASH_NSCR_OPTLOCK_Pos (30U)
+#define FLASH_NSCR_OPTLOCK_Msk (0x1UL << FLASH_NSCR_OPTLOCK_Pos) /*!< 0x40000000 */
+#define FLASH_NSCR_OPTLOCK FLASH_NSCR_OPTLOCK_Msk /*!< Option Lock */
+#define FLASH_NSCR_LOCK_Pos (31U)
+#define FLASH_NSCR_LOCK_Msk (0x1UL << FLASH_NSCR_LOCK_Pos) /*!< 0x80000000 */
+#define FLASH_NSCR_LOCK FLASH_NSCR_LOCK_Msk /*!< Non-secure Lock */
+
+/****************** Bits definition for FLASH_SECCR register ****************/
+#define FLASH_SECCR_PG_Pos (0U)
+#define FLASH_SECCR_PG_Msk (0x1UL << FLASH_SECCR_PG_Pos) /*!< 0x00000001 */
+#define FLASH_SECCR_PG FLASH_SECCR_PG_Msk /*!< Secure Programming */
+#define FLASH_SECCR_PER_Pos (1U)
+#define FLASH_SECCR_PER_Msk (0x1UL << FLASH_SECCR_PER_Pos) /*!< 0x00000002 */
+#define FLASH_SECCR_PER FLASH_SECCR_PER_Msk /*!< Secure Page Erase */
+#define FLASH_SECCR_MER1_Pos (2U)
+#define FLASH_SECCR_MER1_Msk (0x1UL << FLASH_SECCR_MER1_Pos) /*!< 0x00000004 */
+#define FLASH_SECCR_MER1 FLASH_SECCR_MER1_Msk /*!< Secure Bank 1 Mass Erase */
+#define FLASH_SECCR_PNB_Pos (3U)
+#define FLASH_SECCR_PNB_Msk (0x7FUL << FLASH_SECCR_PNB_Pos) /*!< 0x000003F8 */
+#define FLASH_SECCR_PNB FLASH_SECCR_PNB_Msk /*!< Secure Page Number selection */
+#define FLASH_SECCR_BKER_Pos (11U)
+#define FLASH_SECCR_BKER_Msk (0x1UL << FLASH_SECCR_BKER_Pos) /*!< 0x00000800 */
+#define FLASH_SECCR_BKER FLASH_SECCR_BKER_Msk /*!< Secure Bank Selection for Page Erase */
+#define FLASH_SECCR_BWR_Pos (14U)
+#define FLASH_SECCR_BWR_Msk (0x1UL << FLASH_SECCR_BWR_Pos) /*!< 0x00004000 */
+#define FLASH_SECCR_BWR FLASH_SECCR_BWR_Msk /*!< Secure Burst Write programming mode */
+#define FLASH_SECCR_MER2_Pos (15U)
+#define FLASH_SECCR_MER2_Msk (0x1UL << FLASH_SECCR_MER2_Pos) /*!< 0x00008000 */
+#define FLASH_SECCR_MER2 FLASH_SECCR_MER2_Msk /*!< Secure Bank 2 Mass Erase */
+#define FLASH_SECCR_STRT_Pos (16U)
+#define FLASH_SECCR_STRT_Msk (0x1UL << FLASH_SECCR_STRT_Pos) /*!< 0x00010000 */
+#define FLASH_SECCR_STRT FLASH_SECCR_STRT_Msk /*!< Secure Start */
+#define FLASH_SECCR_EOPIE_Pos (24U)
+#define FLASH_SECCR_EOPIE_Msk (0x1UL << FLASH_SECCR_EOPIE_Pos) /*!< 0x01000000 */
+#define FLASH_SECCR_EOPIE FLASH_SECCR_EOPIE_Msk /*!< Secure end of operation interrupt enable */
+#define FLASH_SECCR_ERRIE_Pos (25U)
+#define FLASH_SECCR_ERRIE_Msk (0x1UL << FLASH_SECCR_ERRIE_Pos) /*!< 0x02000000 */
+#define FLASH_SECCR_ERRIE FLASH_SECCR_ERRIE_Msk /*!< Secure error interrupt enable */
+#define FLASH_SECCR_INV_Pos (29U)
+#define FLASH_SECCR_INV_Msk (0x1UL << FLASH_SECCR_INV_Pos) /*!< 0x20000000 */
+#define FLASH_SECCR_INV FLASH_SECCR_INV_Msk /*!< Flash Security State Invert */
+#define FLASH_SECCR_LOCK_Pos (31U)
+#define FLASH_SECCR_LOCK_Msk (0x1UL << FLASH_SECCR_LOCK_Pos) /*!< 0x80000000 */
+#define FLASH_SECCR_LOCK FLASH_SECCR_LOCK_Msk /*!< Secure Lock */
+
+/******************* Bits definition for FLASH_ECCR register ***************/
+#define FLASH_ECCR_ADDR_ECC_Pos (0U)
+#define FLASH_ECCR_ADDR_ECC_Msk (0xFFFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x000FFFFF */
+#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */
+#define FLASH_ECCR_BK_ECC_Pos (21U)
+#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00200000 */
+#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail bank */
+#define FLASH_ECCR_SYSF_ECC_Pos (22U)
+#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */
+#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */
+#define FLASH_ECCR_ECCIE_Pos (24U)
+#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */
+#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */
+#define FLASH_ECCR_ECCC_Pos (30U)
+#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */
+#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */
+#define FLASH_ECCR_ECCD_Pos (31U)
+#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */
+#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */
+
+/******************* Bits definition for FLASH_OPSR register ***************/
+#define FLASH_OPSR_ADDR_OP_Pos (0U)
+#define FLASH_OPSR_ADDR_OP_Msk (0xFFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x000FFFFF */
+#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Flash operation address */
+#define FLASH_OPSR_BK_OP_Pos (21U)
+#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00200000 */
+#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation bank */
+#define FLASH_OPSR_SYSF_OP_Pos (22U)
+#define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00400000 */
+#define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in System Flash interrupted */
+#define FLASH_OPSR_CODE_OP_Pos (29U)
+#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */
+#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash operation code */
+#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */
+#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */
+#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */
+
+/******************* Bits definition for FLASH_OPTR register ***************/
+#define FLASH_OPTR_RDP_Pos (0U)
+#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */
+#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk /*!< Readout protection level */
+#define FLASH_OPTR_BOR_LEV_Pos (8U)
+#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */
+#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR reset Level */
+#define FLASH_OPTR_BOR_LEV_0 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */
+#define FLASH_OPTR_BOR_LEV_1 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */
+#define FLASH_OPTR_BOR_LEV_2 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */
+#define FLASH_OPTR_nRST_STOP_Pos (12U)
+#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */
+#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */
+#define FLASH_OPTR_nRST_STDBY_Pos (13U)
+#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */
+#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */
+#define FLASH_OPTR_nRST_SHDW_Pos (14U)
+#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */
+#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk /*!< nRST_SHDW */
+#define FLASH_OPTR_SRAM134_RST_Pos (15U)
+#define FLASH_OPTR_SRAM134_RST_Msk (0x1UL << FLASH_OPTR_SRAM134_RST_Pos) /*!< 0x00008000 */
+#define FLASH_OPTR_SRAM134_RST FLASH_OPTR_SRAM134_RST_Msk /*!< SRAM1, SRAM3 and SRAM4 erase upon system reset */
+#define FLASH_OPTR_IWDG_SW_Pos (16U)
+#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */
+#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */
+#define FLASH_OPTR_IWDG_STOP_Pos (17U)
+#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */
+#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */
+#define FLASH_OPTR_IWDG_STDBY_Pos (18U)
+#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
+#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */
+#define FLASH_OPTR_WWDG_SW_Pos (19U)
+#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */
+#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk /*!< Window watchdog selection */
+#define FLASH_OPTR_SWAP_BANK_Pos (20U)
+#define FLASH_OPTR_SWAP_BANK_Msk (0x1UL << FLASH_OPTR_SWAP_BANK_Pos) /*!< 0x00100000 */
+#define FLASH_OPTR_SWAP_BANK FLASH_OPTR_SWAP_BANK_Msk /*!< Swap banks */
+#define FLASH_OPTR_DUALBANK_Pos (21U)
+#define FLASH_OPTR_DUALBANK_Msk (0x1UL << FLASH_OPTR_DUALBANK_Pos) /*!< 0x00200000 */
+#define FLASH_OPTR_DUALBANK FLASH_OPTR_DUALBANK_Msk /*!< Dual-bank on 1M and 512 Kbytes Flash memory devices */
+#define FLASH_OPTR_BKPRAM_ECC_Pos (22U)
+#define FLASH_OPTR_BKPRAM_ECC_Msk (0x1UL << FLASH_OPTR_BKPRAM_ECC_Pos) /*!< 0x00400000 */
+#define FLASH_OPTR_BKPRAM_ECC FLASH_OPTR_BKPRAM_ECC_Msk /*!< Backup RAM ECC detection and correction enable */
+#define FLASH_OPTR_SRAM3_ECC_Pos (23U)
+#define FLASH_OPTR_SRAM3_ECC_Msk (0x1UL << FLASH_OPTR_SRAM3_ECC_Pos) /*!< 0x00800000 */
+#define FLASH_OPTR_SRAM3_ECC FLASH_OPTR_SRAM3_ECC_Msk /*!< SRAM3 ECC detection and correction enable */
+#define FLASH_OPTR_SRAM2_ECC_Pos (24U)
+#define FLASH_OPTR_SRAM2_ECC_Msk (0x1UL << FLASH_OPTR_SRAM2_ECC_Pos) /*!< 0x01000000 */
+#define FLASH_OPTR_SRAM2_ECC FLASH_OPTR_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction enable*/
+#define FLASH_OPTR_SRAM2_RST_Pos (25U)
+#define FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */
+#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk /*!< SRAM2 erase when system reset */
+#define FLASH_OPTR_nSWBOOT0_Pos (26U)
+#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */
+#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk /*!< Software BOOT0 */
+#define FLASH_OPTR_nBOOT0_Pos (27U)
+#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */
+#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk /*!< nBOOT0 option bit */
+#define FLASH_OPTR_PA15_PUPEN_Pos (28U)
+#define FLASH_OPTR_PA15_PUPEN_Msk (0x1UL << FLASH_OPTR_PA15_PUPEN_Pos) /*!< 0x10000000 */
+#define FLASH_OPTR_PA15_PUPEN FLASH_OPTR_PA15_PUPEN_Msk /*!< PA15 pull-up enable */
+#define FLASH_OPTR_IO_VDD_HSLV_Pos (29U)
+#define FLASH_OPTR_IO_VDD_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDD_HSLV_Pos) /*!< 0x20000000 */
+#define FLASH_OPTR_IO_VDD_HSLV FLASH_OPTR_IO_VDD_HSLV_Msk /*!< High speed IO at low voltage configuration bit */
+#define FLASH_OPTR_IO_VDDIO2_HSLV_Pos (30U)
+#define FLASH_OPTR_IO_VDDIO2_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDDIO2_HSLV_Pos) /*!< 0x40000000 */
+#define FLASH_OPTR_IO_VDDIO2_HSLV FLASH_OPTR_IO_VDDIO2_HSLV_Msk /*!< High speed IO at low VDDIO2 voltage configuration bit */
+#define FLASH_OPTR_TZEN_Pos (31U)
+#define FLASH_OPTR_TZEN_Msk (0x1UL << FLASH_OPTR_TZEN_Pos) /*!< 0x80000000 */
+#define FLASH_OPTR_TZEN FLASH_OPTR_TZEN_Msk /*!< Global TrustZone security enable */
+
+/**************** Bits definition for FLASH_NSBOOTADD0R register ************/
+#define FLASH_NSBOOTADD0R_NSBOOTADD0_Pos (7U)
+#define FLASH_NSBOOTADD0R_NSBOOTADD0_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD0R_NSBOOTADD0_Pos) /*!< 0xFFFFFF80 */
+#define FLASH_NSBOOTADD0R_NSBOOTADD0 FLASH_NSBOOTADD0R_NSBOOTADD0_Msk /*!< Non-secure boot address 0 */
+
+/**************** Bits definition for FLASH_NSBOOTADD1R register ************/
+#define FLASH_NSBOOTADD1R_NSBOOTADD1_Pos (7U)
+#define FLASH_NSBOOTADD1R_NSBOOTADD1_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD1R_NSBOOTADD1_Pos) /*!< 0xFFFFFF80 */
+#define FLASH_NSBOOTADD1R_NSBOOTADD1 FLASH_NSBOOTADD1R_NSBOOTADD1_Msk /*!< Non-secure boot address 1 */
+
+/**************** Bits definition for FLASH_SECBOOTADD0R register ***********/
+#define FLASH_SECBOOTADD0R_BOOT_LOCK_Pos (0U)
+#define FLASH_SECBOOTADD0R_BOOT_LOCK_Msk (0x1UL << FLASH_SECBOOTADD0R_BOOT_LOCK_Pos) /*!< 0x00000001 */
+#define FLASH_SECBOOTADD0R_BOOT_LOCK FLASH_SECBOOTADD0R_BOOT_LOCK_Msk /*!< Boot Lock */
+#define FLASH_SECBOOTADD0R_SECBOOTADD0_Pos (7U)
+#define FLASH_SECBOOTADD0R_SECBOOTADD0_Msk (0x1FFFFFFUL << FLASH_SECBOOTADD0R_SECBOOTADD0_Pos) /*!< 0xFFFFFF80 */
+#define FLASH_SECBOOTADD0R_SECBOOTADD0 FLASH_SECBOOTADD0R_SECBOOTADD0_Msk /*!< Secure boot address 0 */
+
+/***************** Bits definition for FLASH_SECWM1R1 register **************/
+#define FLASH_SECWM1R1_SECWM1_PSTRT_Pos (0U)
+#define FLASH_SECWM1R1_SECWM1_PSTRT_Msk (0x7FUL << FLASH_SECWM1R1_SECWM1_PSTRT_Pos) /*!< 0x0000007F */
+#define FLASH_SECWM1R1_SECWM1_PSTRT FLASH_SECWM1R1_SECWM1_PSTRT_Msk /*!< Start page of first secure area */
+#define FLASH_SECWM1R1_SECWM1_PEND_Pos (16U)
+#define FLASH_SECWM1R1_SECWM1_PEND_Msk (0x7FUL << FLASH_SECWM1R1_SECWM1_PEND_Pos) /*!< 0x007F0000 */
+#define FLASH_SECWM1R1_SECWM1_PEND FLASH_SECWM1R1_SECWM1_PEND_Msk /*!< End page of first secure area */
+
+/***************** Bits definition for FLASH_SECWM1R2 register **************/
+#define FLASH_SECWM1R2_HDP1_PEND_Pos (16U)
+#define FLASH_SECWM1R2_HDP1_PEND_Msk (0x7FUL << FLASH_SECWM1R2_HDP1_PEND_Pos) /*!< 0x007F0000 */
+#define FLASH_SECWM1R2_HDP1_PEND FLASH_SECWM1R2_HDP1_PEND_Msk /*!< End page of first hide protection area */
+#define FLASH_SECWM1R2_HDP1EN_Pos (31U)
+#define FLASH_SECWM1R2_HDP1EN_Msk (0x1UL << FLASH_SECWM1R2_HDP1EN_Pos) /*!< 0x80000000 */
+#define FLASH_SECWM1R2_HDP1EN FLASH_SECWM1R2_HDP1EN_Msk /*!< Hide protection first area enable */
+
+/****************** Bits definition for FLASH_WRP1AR register ***************/
+#define FLASH_WRP1AR_WRP1A_PSTRT_Pos (0U)
+#define FLASH_WRP1AR_WRP1A_PSTRT_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_PSTRT_Pos) /*!< 0x0000007F */
+#define FLASH_WRP1AR_WRP1A_PSTRT FLASH_WRP1AR_WRP1A_PSTRT_Msk /*!< Bank 1 WPR first area A start page */
+#define FLASH_WRP1AR_WRP1A_PEND_Pos (16U)
+#define FLASH_WRP1AR_WRP1A_PEND_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_PEND_Pos) /*!< 0x007F0000 */
+#define FLASH_WRP1AR_WRP1A_PEND FLASH_WRP1AR_WRP1A_PEND_Msk /*!< Bank 1 WPR first area A end page */
+#define FLASH_WRP1AR_UNLOCK_Pos (31U)
+#define FLASH_WRP1AR_UNLOCK_Msk (0x1UL << FLASH_WRP1AR_UNLOCK_Pos) /*!< 0x80000000 */
+#define FLASH_WRP1AR_UNLOCK FLASH_WRP1AR_UNLOCK_Msk /*!< Bank 1 WPR first area A unlock */
+
+/****************** Bits definition for FLASH_WRP1BR register ***************/
+#define FLASH_WRP1BR_WRP1B_PSTRT_Pos (0U)
+#define FLASH_WRP1BR_WRP1B_PSTRT_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_PSTRT_Pos) /*!< 0x0000007F */
+#define FLASH_WRP1BR_WRP1B_PSTRT FLASH_WRP1BR_WRP1B_PSTRT_Msk /*!< Bank 1 WPR second area B start page */
+#define FLASH_WRP1BR_WRP1B_PEND_Pos (16U)
+#define FLASH_WRP1BR_WRP1B_PEND_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_PEND_Pos) /*!< 0x007F0000 */
+#define FLASH_WRP1BR_WRP1B_PEND FLASH_WRP1BR_WRP1B_PEND_Msk /*!< Bank 1 WPR second area B end page */
+#define FLASH_WRP1BR_UNLOCK_Pos (31U)
+#define FLASH_WRP1BR_UNLOCK_Msk (0x1UL << FLASH_WRP1BR_UNLOCK_Pos) /*!< 0x80000000 */
+#define FLASH_WRP1BR_UNLOCK FLASH_WRP1BR_UNLOCK_Msk /*!< Bank 1 WPR first area B unlock */
+
+/***************** Bits definition for FLASH_SECWM2R1 register **************/
+#define FLASH_SECWM2R1_SECWM2_PSTRT_Pos (0U)
+#define FLASH_SECWM2R1_SECWM2_PSTRT_Msk (0x7FUL << FLASH_SECWM2R1_SECWM2_PSTRT_Pos) /*!< 0x0000007F */
+#define FLASH_SECWM2R1_SECWM2_PSTRT FLASH_SECWM2R1_SECWM2_PSTRT_Msk /*!< Start page of second secure area */
+#define FLASH_SECWM2R1_SECWM2_PEND_Pos (16U)
+#define FLASH_SECWM2R1_SECWM2_PEND_Msk (0x7FUL << FLASH_SECWM2R1_SECWM2_PEND_Pos) /*!< 0x007F0000 */
+#define FLASH_SECWM2R1_SECWM2_PEND FLASH_SECWM2R1_SECWM2_PEND_Msk /*!< End page of second secure area */
+
+/***************** Bits definition for FLASH_SECWM2R2 register **************/
+#define FLASH_SECWM2R2_HDP2_PEND_Pos (16U)
+#define FLASH_SECWM2R2_HDP2_PEND_Msk (0x7FUL << FLASH_SECWM2R2_HDP2_PEND_Pos) /*!< 0x007F0000 */
+#define FLASH_SECWM2R2_HDP2_PEND FLASH_SECWM2R2_HDP2_PEND_Msk /*!< End page of hide protection second area */
+#define FLASH_SECWM2R2_HDP2EN_Pos (31U)
+#define FLASH_SECWM2R2_HDP2EN_Msk (0x1UL << FLASH_SECWM2R2_HDP2EN_Pos) /*!< 0x80000000 */
+#define FLASH_SECWM2R2_HDP2EN FLASH_SECWM2R2_HDP2EN_Msk /*!< Hide protection second area enable */
+
+/****************** Bits definition for FLASH_WRP2AR register ***************/
+#define FLASH_WRP2AR_WRP2A_PSTRT_Pos (0U)
+#define FLASH_WRP2AR_WRP2A_PSTRT_Msk (0x7FUL << FLASH_WRP2AR_WRP2A_PSTRT_Pos) /*!< 0x0000007F */
+#define FLASH_WRP2AR_WRP2A_PSTRT FLASH_WRP2AR_WRP2A_PSTRT_Msk /*!< Bank 2 WPR first area A start page */
+#define FLASH_WRP2AR_WRP2A_PEND_Pos (16U)
+#define FLASH_WRP2AR_WRP2A_PEND_Msk (0x7FUL << FLASH_WRP2AR_WRP2A_PEND_Pos) /*!< 0x007F0000 */
+#define FLASH_WRP2AR_WRP2A_PEND FLASH_WRP2AR_WRP2A_PEND_Msk /*!< Bank 2 WPR first area A end page */
+#define FLASH_WRP2AR_UNLOCK_Pos (31U)
+#define FLASH_WRP2AR_UNLOCK_Msk (0x1UL << FLASH_WRP2AR_UNLOCK_Pos) /*!< 0x80000000 */
+#define FLASH_WRP2AR_UNLOCK FLASH_WRP2AR_UNLOCK_Msk /*!< Bank 2 WPR first area A unlock */
+
+/****************** Bits definition for FLASH_WRP2BR register ***************/
+#define FLASH_WRP2BR_WRP2B_PSTRT_Pos (0U)
+#define FLASH_WRP2BR_WRP2B_PSTRT_Msk (0x7FUL << FLASH_WRP2BR_WRP2B_PSTRT_Pos) /*!< 0x0000007F */
+#define FLASH_WRP2BR_WRP2B_PSTRT FLASH_WRP2BR_WRP2B_PSTRT_Msk /*!< Bank 2 WPR first area B start page */
+#define FLASH_WRP2BR_WRP2B_PEND_Pos (16U)
+#define FLASH_WRP2BR_WRP2B_PEND_Msk (0x7FUL << FLASH_WRP2BR_WRP2B_PEND_Pos) /*!< 0x007F0000 */
+#define FLASH_WRP2BR_WRP2B_PEND FLASH_WRP2BR_WRP2B_PEND_Msk /*!< Bank 2 WPR first area B end page */
+#define FLASH_WRP2BR_UNLOCK_Pos (31U)
+#define FLASH_WRP2BR_UNLOCK_Msk (0x1UL << FLASH_WRP2BR_UNLOCK_Pos) /*!< 0x80000000 */
+#define FLASH_WRP2BR_UNLOCK FLASH_WRP2BR_UNLOCK_Msk /*!< Bank 2 WPR first area B unlock */
+
+/****************** Bits definition for FLASH_SECHDPCR register ***********/
+#define FLASH_SECHDPCR_HDP1_ACCDIS_Pos (0U)
+#define FLASH_SECHDPCR_HDP1_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP1_ACCDIS_Pos) /*!< 0x00000001 */
+#define FLASH_SECHDPCR_HDP1_ACCDIS FLASH_SECHDPCR_HDP1_ACCDIS_Msk /*!< HDP1 area access disable */
+#define FLASH_SECHDPCR_HDP2_ACCDIS_Pos (1U)
+#define FLASH_SECHDPCR_HDP2_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP2_ACCDIS_Pos) /*!< 0x00000002 */
+#define FLASH_SECHDPCR_HDP2_ACCDIS FLASH_SECHDPCR_HDP2_ACCDIS_Msk /*!< HDP2 area access disable */
+
+/****************** Bits definition for FLASH_PRIVCFGR register ***********/
+#define FLASH_PRIVCFGR_SPRIV_Pos (0U)
+#define FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */
+#define FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk /*!< Privilege protection for secure registers */
+#define FLASH_PRIVCFGR_NSPRIV_Pos (1U)
+#define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */
+#define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */
+
+
+/******************************************************************************/
+/* */
+/* Filter Mathematical ACcelerator unit (FMAC) */
+/* */
+/******************************************************************************/
+/***************** Bit definition for FMAC_X1BUFCFG register ****************/
+#define FMAC_X1BUFCFG_X1_BASE_Pos (0U)
+#define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos) /*!< 0x000000FF */
+#define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk /*!< Base address of X1 buffer */
+#define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8U)
+#define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) /*!< 0x0000FF00 */
+#define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */
+#define FMAC_X1BUFCFG_FULL_WM_Pos (24U)
+#define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos) /*!< 0x03000000 */
+#define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk /*!< Watermark for buffer full flag */
+
+/***************** Bit definition for FMAC_X2BUFCFG register ****************/
+#define FMAC_X2BUFCFG_X2_BASE_Pos (0U)
+#define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos) /*!< 0x000000FF */
+#define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk /*!< Base address of X2 buffer */
+#define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8U)
+#define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) /*!< 0x0000FF00 */
+#define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */
+
+/***************** Bit definition for FMAC_YBUFCFG register *****************/
+#define FMAC_YBUFCFG_Y_BASE_Pos (0U)
+#define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos) /*!< 0x000000FF */
+#define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk /*!< Base address of Y buffer */
+#define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8U)
+#define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) /*!< 0x0000FF00 */
+#define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */
+#define FMAC_YBUFCFG_EMPTY_WM_Pos (24U)
+#define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos) /*!< 0x03000000 */
+#define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk /*!< Watermark for buffer empty flag */
+
+/****************** Bit definition for FMAC_PARAM register ******************/
+#define FMAC_PARAM_P_Pos (0U)
+#define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos) /*!< 0x000000FF */
+#define FMAC_PARAM_P FMAC_PARAM_P_Msk /*!< Input parameter P */
+#define FMAC_PARAM_Q_Pos (8U)
+#define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos) /*!< 0x0000FF00 */
+#define FMAC_PARAM_Q FMAC_PARAM_Q_Msk /*!< Input parameter Q */
+#define FMAC_PARAM_R_Pos (16U)
+#define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos) /*!< 0x00FF0000 */
+#define FMAC_PARAM_R FMAC_PARAM_R_Msk /*!< Input parameter R */
+#define FMAC_PARAM_FUNC_Pos (24U)
+#define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos) /*!< 0x7F000000 */
+#define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk /*!< Function */
+#define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos) /*!< 0x01000000 */
+#define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos) /*!< 0x02000000 */
+#define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos) /*!< 0x04000000 */
+#define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos) /*!< 0x08000000 */
+#define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos) /*!< 0x10000000 */
+#define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos) /*!< 0x20000000 */
+#define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos) /*!< 0x40000000 */
+#define FMAC_PARAM_START_Pos (31U)
+#define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos) /*!< 0x80000000 */
+#define FMAC_PARAM_START FMAC_PARAM_START_Msk /*!< Enable execution */
+
+/******************** Bit definition for FMAC_CR register *******************/
+#define FMAC_CR_RIEN_Pos (0U)
+#define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos) /*!< 0x00000001 */
+#define FMAC_CR_RIEN FMAC_CR_RIEN_Msk /*!< Enable read interrupt */
+#define FMAC_CR_WIEN_Pos (1U)
+#define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos) /*!< 0x00000002 */
+#define FMAC_CR_WIEN FMAC_CR_WIEN_Msk /*!< Enable write interrupt */
+#define FMAC_CR_OVFLIEN_Pos (2U)
+#define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos) /*!< 0x00000004 */
+#define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk /*!< Enable overflow error interrupts */
+#define FMAC_CR_UNFLIEN_Pos (3U)
+#define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos) /*!< 0x00000008 */
+#define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk /*!< Enable underflow error interrupts */
+#define FMAC_CR_SATIEN_Pos (4U)
+#define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos) /*!< 0x00000010 */
+#define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk /*!< Enable saturation error interrupts */
+#define FMAC_CR_DMAREN_Pos (8U)
+#define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos) /*!< 0x00000100 */
+#define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk /*!< Enable DMA read channel requests */
+#define FMAC_CR_DMAWEN_Pos (9U)
+#define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos) /*!< 0x00000200 */
+#define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk /*!< Enable DMA write channel requests */
+#define FMAC_CR_CLIPEN_Pos (15U)
+#define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos) /*!< 0x00008000 */
+#define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk /*!< Enable clipping */
+#define FMAC_CR_RESET_Pos (16U)
+#define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos) /*!< 0x00010000 */
+#define FMAC_CR_RESET FMAC_CR_RESET_Msk /*!< Reset filter mathematical accelerator unit */
+
+/******************* Bit definition for FMAC_SR register ********************/
+#define FMAC_SR_YEMPTY_Pos (0U)
+#define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos) /*!< 0x00000001 */
+#define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk /*!< Y buffer empty flag */
+#define FMAC_SR_X1FULL_Pos (1U)
+#define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos) /*!< 0x00000002 */
+#define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk /*!< X1 buffer full flag */
+#define FMAC_SR_OVFL_Pos (8U)
+#define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos) /*!< 0x00000100 */
+#define FMAC_SR_OVFL FMAC_SR_OVFL_Msk /*!< Overflow error flag */
+#define FMAC_SR_UNFL_Pos (9U)
+#define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos) /*!< 0x00000200 */
+#define FMAC_SR_UNFL FMAC_SR_UNFL_Msk /*!< Underflow error flag */
+#define FMAC_SR_SAT_Pos (10U)
+#define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos) /*!< 0x00000400 */
+#define FMAC_SR_SAT FMAC_SR_SAT_Msk /*!< Saturation error flag */
+
+/****************** Bit definition for FMAC_WDATA register ******************/
+#define FMAC_WDATA_WDATA_Pos (0U)
+#define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos) /*!< 0x0000FFFF */
+#define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk /*!< Write data */
+
+/****************** Bit definition for FMACX_RDATA register *****************/
+#define FMAC_RDATA_RDATA_Pos (0U)
+#define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */
+#define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */
+
+
+/******************************************************************************/
+/* */
+/* Flexible Memory Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for FMC_BCR1 register *******************/
+#define FMC_BCR1_CCLKEN_Pos (20U)
+#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!>2) /*!< Input modulus number of bits */
+#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */
+
+/* Compute Montgomery parameter output data */
+#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */
+
+/* Compute modular exponentiation input data */
+#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */
+#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
+#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */
+#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */
+#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */
+#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */
+#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */
+#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/
+#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */
+#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */
+
+/* Compute modular exponentiation output data */
+#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */
+#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */
+#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */
+#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */
+
+/* Compute ECC scalar multiplication input data */
+#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */
+#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */
+#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */
+#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */
+#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */
+#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */
+#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */
+#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */
+#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */
+#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */
+
+/* Compute ECC scalar multiplication output data */
+#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */
+#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */
+#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */
+
+/* Point check input data */
+#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */
+#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */
+#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */
+#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */
+#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */
+#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */
+#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */
+#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */
+
+/* Point check output data */
+#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */
+
+/* ECDSA signature input data */
+#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */
+#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */
+#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */
+#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */
+#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */
+#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */
+#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */
+#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */
+#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */
+#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */
+#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */
+#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */
+
+/* ECDSA signature output data */
+#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */
+#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */
+#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */
+#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */
+#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */
+
+/* ECDSA verification input data */
+#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */
+#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */
+#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */
+#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */
+#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */
+#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */
+#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */
+#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */
+#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */
+#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */
+#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */
+#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */
+#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */
+
+/* ECDSA verification output data */
+#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
+
+/* RSA CRT exponentiation input data */
+#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */
+#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */
+#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */
+#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */
+#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */
+#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */
+#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */
+
+/* RSA CRT exponentiation output data */
+#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
+
+/* Modular reduction input data */
+#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */
+#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */
+#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */
+#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */
+
+/* Modular reduction output data */
+#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
+
+/* Arithmetic addition input data */
+#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
+#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
+#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
+
+/* Arithmetic addition output data */
+#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
+
+/* Arithmetic subtraction input data */
+#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
+#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
+#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
+
+/* Arithmetic subtraction output data */
+#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
+
+/* Arithmetic multiplication input data */
+#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
+#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
+#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
+
+/* Arithmetic multiplication output data */
+#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
+
+/* Comparison input data */
+#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
+#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
+#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
+
+/* Comparison output data */
+#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
+
+/* Modular addition input data */
+#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
+#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
+#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
+#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */
+
+/* Modular addition output data */
+#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
+
+/* Modular inversion input data */
+#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
+#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
+#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */
+
+/* Modular inversion output data */
+#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
+
+/* Modular subtraction input data */
+#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
+#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
+#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
+#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */
+
+/* Modular subtraction output data */
+#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
+
+/* Montgomery multiplication input data */
+#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
+#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
+#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
+#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */
+
+/* Montgomery multiplication output data */
+#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
+
+/* Generic Arithmetic input data */
+#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
+#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
+#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
+#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
+
+/* Generic Arithmetic output data */
+#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */
+
+/* Compute ECC complete addition input data */
+#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */
+#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */
+#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */
+#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */
+#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */
+#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */
+#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */
+#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */
+#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */
+#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */
+
+/* Compute ECC complete addition output data */
+#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */
+#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */
+#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */
+
+/* Compute ECC double base ladder input data */
+#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */
+#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */
+#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */
+#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */
+#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */
+#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */
+#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */
+#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */
+#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */
+#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */
+#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */
+#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */
+#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */
+
+/* Compute ECC double base ladder output data */
+#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */
+#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */
+#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */
+
+/* Compute ECC projective to affine conversion input data */
+#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */
+#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */
+#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */
+#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */
+#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */
+#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */
+
+/* Compute ECC projective to affine conversion output data */
+#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */
+#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */
+#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */
+
+/** @addtogroup STM32U5xx_Peripheral_Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \
+ ((INSTANCE) == ADC1_S) || \
+ ((INSTANCE) == ADC4_NS) || \
+ ((INSTANCE) == ADC4_S))
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \
+ ((INSTANCE) == ADC1_S))
+
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON_NS) || \
+ ((INSTANCE) == ADC12_COMMON_S) || \
+ ((INSTANCE) == ADC4_COMMON_NS) || \
+ ((INSTANCE) == ADC4_COMMON_S))
+
+/******************************* AES Instances ********************************/
+#define IS_AES_ALL_INSTANCE(INSTANCE) (((INSTANCE) == AES_NS) || ((INSTANCE) == AES_S))
+
+/******************************* PKA Instances ********************************/
+#define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_NS) || ((INSTANCE) == PKA_S))
+
+/******************************** FDCAN Instances *****************************/
+#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_NS) || ((INSTANCE) == FDCAN1_S))
+
+/******************************** COMP Instances ******************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP1_S) || \
+ ((INSTANCE) == COMP2_NS) || ((INSTANCE) == COMP2_S))
+
+/******************** COMP Instances with window mode capability **************/
+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (((INSTANCE) == COMP2_NS) || ((INSTANCE) == COMP2_S))
+
+/******************************* CORDIC Instances *****************************/
+#define IS_CORDIC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CORDIC_NS) || ((INSTANCE) == CORDIC_S))
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC_NS) || ((INSTANCE) == CRC_S))
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1_NS) || ((INSTANCE) == DAC1_S))
+
+/******************************* DELAYBLOCK Instances *******************************/
+#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1_NS) || \
+ ((INSTANCE) == DLYB_SDMMC2_NS) || \
+ ((INSTANCE) == DLYB_SDMMC1_S) || \
+ ((INSTANCE) == DLYB_SDMMC2_S) || \
+ ((INSTANCE) == DLYB_OCTOSPI1_NS) || \
+ ((INSTANCE) == DLYB_OCTOSPI2_NS) || \
+ ((INSTANCE) == DLYB_OCTOSPI1_S) || \
+ ((INSTANCE) == DLYB_OCTOSPI2_S ))
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \
+ ((INSTANCE) == GPDMA1_Channel1_NS) || ((INSTANCE) == GPDMA1_Channel1_S) || \
+ ((INSTANCE) == GPDMA1_Channel2_NS) || ((INSTANCE) == GPDMA1_Channel2_S) || \
+ ((INSTANCE) == GPDMA1_Channel3_NS) || ((INSTANCE) == GPDMA1_Channel3_S) || \
+ ((INSTANCE) == GPDMA1_Channel4_NS) || ((INSTANCE) == GPDMA1_Channel4_S) || \
+ ((INSTANCE) == GPDMA1_Channel5_NS) || ((INSTANCE) == GPDMA1_Channel5_S) || \
+ ((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \
+ ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \
+ ((INSTANCE) == GPDMA1_Channel8_NS) || ((INSTANCE) == GPDMA1_Channel8_S) || \
+ ((INSTANCE) == GPDMA1_Channel9_NS) || ((INSTANCE) == GPDMA1_Channel9_S) || \
+ ((INSTANCE) == GPDMA1_Channel10_NS) || ((INSTANCE) == GPDMA1_Channel10_S) || \
+ ((INSTANCE) == GPDMA1_Channel11_NS) || ((INSTANCE) == GPDMA1_Channel11_S) || \
+ ((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \
+ ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \
+ ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \
+ ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S) || \
+ ((INSTANCE) == LPDMA1_Channel0_NS) || ((INSTANCE) == LPDMA1_Channel0_S) || \
+ ((INSTANCE) == LPDMA1_Channel1_NS) || ((INSTANCE) == LPDMA1_Channel1_S) || \
+ ((INSTANCE) == LPDMA1_Channel2_NS) || ((INSTANCE) == LPDMA1_Channel2_S) || \
+ ((INSTANCE) == LPDMA1_Channel3_NS) || ((INSTANCE) == LPDMA1_Channel3_S))
+
+#define IS_GPDMA_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \
+ ((INSTANCE) == GPDMA1_Channel1_NS) || ((INSTANCE) == GPDMA1_Channel1_S) || \
+ ((INSTANCE) == GPDMA1_Channel2_NS) || ((INSTANCE) == GPDMA1_Channel2_S) || \
+ ((INSTANCE) == GPDMA1_Channel3_NS) || ((INSTANCE) == GPDMA1_Channel3_S) || \
+ ((INSTANCE) == GPDMA1_Channel4_NS) || ((INSTANCE) == GPDMA1_Channel4_S) || \
+ ((INSTANCE) == GPDMA1_Channel5_NS) || ((INSTANCE) == GPDMA1_Channel5_S) || \
+ ((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \
+ ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \
+ ((INSTANCE) == GPDMA1_Channel8_NS) || ((INSTANCE) == GPDMA1_Channel8_S) || \
+ ((INSTANCE) == GPDMA1_Channel9_NS) || ((INSTANCE) == GPDMA1_Channel9_S) || \
+ ((INSTANCE) == GPDMA1_Channel10_NS) || ((INSTANCE) == GPDMA1_Channel10_S) || \
+ ((INSTANCE) == GPDMA1_Channel11_NS) || ((INSTANCE) == GPDMA1_Channel11_S) || \
+ ((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \
+ ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \
+ ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \
+ ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S))
+
+#define IS_LPDMA_INSTANCE(INSTANCE) (((INSTANCE) == LPDMA1_Channel0_NS) || ((INSTANCE) == LPDMA1_Channel0_S) || \
+ ((INSTANCE) == LPDMA1_Channel1_NS) || ((INSTANCE) == LPDMA1_Channel1_S) || \
+ ((INSTANCE) == LPDMA1_Channel2_NS) || ((INSTANCE) == LPDMA1_Channel2_S) || \
+ ((INSTANCE) == LPDMA1_Channel3_NS) || ((INSTANCE) == LPDMA1_Channel3_S))
+
+#define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \
+ ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \
+ ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \
+ ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S))
+
+/****************************** OTFDEC Instances ********************************/
+#define IS_OTFDEC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OTFDEC1_NS) || ((INSTANCE) == OTFDEC1_S) || \
+ ((INSTANCE) == OTFDEC2_NS) || ((INSTANCE) == OTFDEC2_S))
+
+/****************************** RAMCFG Instances ********************************/
+#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || ((INSTANCE) == RAMCFG_SRAM1_S) || \
+ ((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \
+ ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \
+ ((INSTANCE) == RAMCFG_SRAM4_NS) || ((INSTANCE) == RAMCFG_SRAM4_S) || \
+ ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S))
+
+/***************************** RAMCFG ECC Instances *****************************/
+#define IS_RAMCFG_ECC_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \
+ ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \
+ ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S))
+
+/***************************** RAMCFG IT Instances ******************************/
+#define IS_RAMCFG_IT_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \
+ ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \
+ ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S))
+
+/************************ RAMCFG Write Protection Instances *********************/
+#define IS_RAMCFG_WP_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S))
+
+
+/******************************** FMAC Instances ******************************/
+#define IS_FMAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FMAC_NS) || ((INSTANCE) == FMAC_S))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_NS) || ((INSTANCE) == GPIOA_S) || \
+ ((INSTANCE) == GPIOB_NS) || ((INSTANCE) == GPIOB_S) || \
+ ((INSTANCE) == GPIOC_NS) || ((INSTANCE) == GPIOC_S) || \
+ ((INSTANCE) == GPIOD_NS) || ((INSTANCE) == GPIOD_S) || \
+ ((INSTANCE) == GPIOE_NS) || ((INSTANCE) == GPIOE_S) || \
+ ((INSTANCE) == GPIOF_NS) || ((INSTANCE) == GPIOF_S) || \
+ ((INSTANCE) == GPIOG_NS) || ((INSTANCE) == GPIOG_S) || \
+ ((INSTANCE) == GPIOH_NS) || ((INSTANCE) == GPIOH_S) || \
+ ((INSTANCE) == GPIOI_NS) || ((INSTANCE) == GPIOI_S) || \
+ ((INSTANCE) == LPGPIO1_NS) || ((INSTANCE) == LPGPIO1_S))
+
+/******************************* LPGPIO Instances *****************************/
+#define IS_LPGPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == LPGPIO1_NS) || ((INSTANCE) == LPGPIO1_S))
+
+/******************************* DMA2D Instances *******************************/
+#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA2D_NS) || ((__INSTANCE__) == DMA2D_S))
+
+/******************************* DCMI Instances *******************************/
+#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DCMI_NS) || ((__INSTANCE__) == DCMI_S))
+
+/******************************* DCACHE Instances *****************************/
+#define IS_DCACHE_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DCACHE1_NS) || ((INSTANCE) == DCACHE1_S))
+
+/******************************* PSSI Instances *******************************/
+#define IS_PSSI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == PSSI_NS) || ((__INSTANCE__) == PSSI_S))
+
+/******************************* GPIO AF Instances ****************************/
+/* On U5, all GPIO Bank support AF */
+#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances *****************************/
+/* On U5, all GPIO Bank support the Lock mechanism */
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \
+ ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \
+ ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S) || \
+ ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S))
+
+/****************** I2C Instances : wakeup capability from stop modes *********/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
+
+/******************* I2C Instances : Group belongingness *********************/
+#define IS_I2C_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \
+ ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \
+ ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S))
+
+#define IS_I2C_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S))
+
+/****************************** OPAMP Instances *******************************/
+#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1_NS) || ((INSTANCE) == OPAMP1_S) || \
+ ((INSTANCE) == OPAMP2_NS) || ((INSTANCE) == OPAMP2_S))
+
+/******************************* OSPI Instances *******************************/
+#define IS_OSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OCTOSPI1_NS) || ((INSTANCE) == OCTOSPI1_S) || \
+ ((INSTANCE) == OCTOSPI2_NS) || ((INSTANCE) == OCTOSPI2_S))
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RNG_NS) || ((INSTANCE) == RNG_S))
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_NS) || ((INSTANCE) == RTC_S))
+
+/******************************** SAI Instances *******************************/
+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_NS) || ((INSTANCE) == SAI1_Block_A_S) || \
+ ((INSTANCE) == SAI1_Block_B_NS) || ((INSTANCE) == SAI1_Block_B_S) || \
+ ((INSTANCE) == SAI2_Block_A_NS) || ((INSTANCE) == SAI2_Block_A_S) || \
+ ((INSTANCE) == SAI2_Block_B_NS) || ((INSTANCE) == SAI2_Block_B_S))
+
+/****************************** SDMMC Instances *******************************/
+#define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1_NS) || ((INSTANCE) == SDMMC1_S) || \
+ ((INSTANCE) == SDMMC2_NS) || ((INSTANCE) == SDMMC2_S))
+
+/****************************** SMBUS Instances *******************************/
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \
+ ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \
+ ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S) || \
+ ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S))
+
+/******************* SMBUS Instances : Group belongingness *********************/
+#define IS_SMBUS_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \
+ ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \
+ ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S))
+
+#define IS_SMBUS_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S))
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \
+ ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \
+ ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S))
+
+#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S))
+
+#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \
+ ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S))
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\
+ ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\
+ ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\
+ ((INSTANCE) == LPTIM4_NS) || ((INSTANCE) == LPTIM4_S))
+
+/****************** LPTIM Instances : DMA supported instances *****************/
+#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\
+ ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\
+ ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S))
+
+/************* LPTIM Instances : at least 1 capture/compare channel ***********/
+#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\
+ ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\
+ ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\
+ ((INSTANCE) == LPTIM4_NS) || ((INSTANCE) == LPTIM4_S))
+
+/************* LPTIM Instances : at least 2 capture/compare channel ***********/
+#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\
+ ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\
+ ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S))
+
+/****************** LPTIM Instances : supporting encoder interface **************/
+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\
+ ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S))
+
+/****************** LPTIM Instances : supporting Input Capture **************/
+#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\
+ ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\
+ ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
+ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
+ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \
+ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \
+ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \
+ ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \
+ ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \
+ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \
+ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
+ ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
+ ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
+
+/****************** TIM Instances : supporting 32 bits counter ****************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
+ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S))
+
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
+ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \
+ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
+ ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
+ ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
+
+/************** TIM Instances : supporting Break source selection *************/
+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
+ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \
+ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
+ ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
+ ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
+
+/****************** TIM Instances : supporting 2 break inputs *****************/
+#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
+ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
+ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
+ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \
+ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \
+ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \
+ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \
+ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
+ ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
+ ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
+ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
+ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \
+ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \
+ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \
+ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \
+ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
+ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
+ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \
+ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \
+ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \
+ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
+ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
+ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \
+ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \
+ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \
+ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S))
+
+/****************** TIM Instances : at least 5 capture/compare channels *******/
+#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
+ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S))
+
+/****************** TIM Instances : at least 6 capture/compare channels *******/
+#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
+ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S))
+
+/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
+ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \
+ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
+ ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
+ ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
+
+/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
+ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
+ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \
+ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \
+ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \
+ ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \
+ ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \
+ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \
+ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
+ ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
+ ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
+
+/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
+ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
+ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \
+ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \
+ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \
+ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \
+ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
+ ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
+ ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
+ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
+ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \
+ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \
+ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \
+ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \
+ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
+ ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
+ ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4) || \
+ ((CHANNEL) == TIM_CHANNEL_5) || \
+ ((CHANNEL) == TIM_CHANNEL_6))) \
+ || \
+ ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ ((((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ ((((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ ((((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4) || \
+ ((CHANNEL) == TIM_CHANNEL_5) || \
+ ((CHANNEL) == TIM_CHANNEL_6))) \
+ || \
+ ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/****************** TIM Instances : supporting complementary output(s) ********/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \
+ ((CHANNEL) == TIM_CHANNEL_1)))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
+ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
+ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \
+ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \
+ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \
+ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \
+ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
+ ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
+ ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
+ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
+ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \
+ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \
+ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \
+ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \
+ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
+ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
+ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \
+ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \
+ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \
+ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
+ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
+ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \
+ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \
+ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \
+ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \
+ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
+ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
+ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \
+ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \
+ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \
+ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \
+ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S))
+
+/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
+ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S))
+
+/****************** TIM Instances : supporting commutation event generation ***/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
+ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \
+ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
+ ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
+ ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
+ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
+ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \
+ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \
+ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \
+ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
+ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
+ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \
+ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \
+ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \
+ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S))
+
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
+ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
+ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \
+ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \
+ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \
+ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \
+ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S))
+
+/**************** TIM Instances : external trigger input available ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
+ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
+ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \
+ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \
+ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \
+ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S))
+
+/************* TIM Instances : supporting ETR source selection ***************/
+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
+ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
+ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \
+ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S))
+
+/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
+ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
+ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \
+ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \
+ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \
+ ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \
+ ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \
+ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \
+ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
+ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
+ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \
+ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \
+ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \
+ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \
+ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S))
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
+ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
+ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \
+ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \
+ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \
+ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
+ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
+ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \
+ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \
+ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \
+ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \
+ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
+ ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
+ ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
+ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \
+ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
+ ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
+ ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
+
+/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
+#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
+ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
+ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
+ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \
+ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \
+ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \
+ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \
+ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S))
+
+/******************* TIM Instances : Timer input selection ********************/
+#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) ||\
+ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) ||\
+ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) ||\
+ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) ||\
+ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) ||\
+ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) ||\
+ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)||\
+ ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)||\
+ ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
+
+/******************* TIM Instances : supporting HSE32 as input ********************/
+#define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) ||\
+ ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
+
+/****************** TIM Instances : Advanced timer instances *******************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
+ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S))
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1_NS) || ((__INSTANCE__) == TIM1_S) || \
+ ((__INSTANCE__) == TIM2_NS) || ((__INSTANCE__) == TIM2_S) || \
+ ((__INSTANCE__) == TIM3_NS) || ((__INSTANCE__) == TIM3_S) || \
+ ((__INSTANCE__) == TIM4_NS) || ((__INSTANCE__) == TIM4_S) || \
+ ((__INSTANCE__) == TIM5_NS) || ((__INSTANCE__) == TIM5_S) || \
+ ((__INSTANCE__) == TIM6_NS) || ((__INSTANCE__) == TIM6_S) || \
+ ((__INSTANCE__) == TIM7_NS) || ((__INSTANCE__) == TIM7_S) || \
+ ((__INSTANCE__) == TIM8_NS) || ((__INSTANCE__) == TIM8_S) || \
+ ((__INSTANCE__) == TIM15_NS) || ((__INSTANCE__) == TIM15_S))
+
+/****************************** TSC Instances *********************************/
+#define IS_TSC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == TSC_NS) || ((INSTANCE) == TSC_S))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \
+ ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \
+ ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \
+ ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \
+ ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \
+ ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \
+ ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S))
+
+/*********************** UART Instances : FIFO mode ***************************/
+#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \
+ ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \
+ ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \
+ ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \
+ ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \
+ ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S))
+
+/*********************** UART Instances : SPI Slave mode **********************/
+#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \
+ ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \
+ ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S))
+
+/****************** UART Instances : Auto Baud Rate detection ****************/
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \
+ ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \
+ ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \
+ ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \
+ ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S))
+
+/****************** UART Instances : Driver Enable *****************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \
+ ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \
+ ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \
+ ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \
+ ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \
+ ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \
+ ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \
+ ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \
+ ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \
+ ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \
+ ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \
+ ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \
+ ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \
+ ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \
+ ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \
+ ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \
+ ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \
+ ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \
+ ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \
+ ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S))
+
+/******************** UART Instances : Wake-up from Stop mode **********************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \
+ ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \
+ ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \
+ ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \
+ ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \
+ ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \
+ ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \
+ ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \
+ ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \
+ ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S))
+
+/********************* USART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \
+ ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \
+ ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S))
+
+/******************** LPUART Instance *****************************************/
+#define IS_LPUART_INSTANCE(INSTANCE) (((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S))
+
+/*********************** UART Instances : AUTONOMOUS mode ***************************/
+#define IS_UART_AUTONOMOUS_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \
+ ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \
+ ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \
+ ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \
+ ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \
+ ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG_NS) || ((INSTANCE) == IWDG_S))
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG_NS) || ((INSTANCE) == WWDG_S))
+
+/****************************** UCPD Instances ********************************/
+#define IS_UCPD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == UCPD1_NS) || ((INSTANCE) == UCPD1_S))
+
+/******************************* OTG FS HCD Instances *************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS_NS) || ((INSTANCE) == USB_OTG_FS_S))
+
+/******************************* OTG FS PCD Instances *************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS_NS) || ((INSTANCE) == USB_OTG_FS_S))
+
+/******************************* MDF/ADF Instances ****************************/
+#define IS_MDF_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDF1_Filter0_NS) || ((INSTANCE) == MDF1_Filter0_S) || \
+ ((INSTANCE) == MDF1_Filter1_NS) || ((INSTANCE) == MDF1_Filter1_S) || \
+ ((INSTANCE) == MDF1_Filter2_NS) || ((INSTANCE) == MDF1_Filter2_S) || \
+ ((INSTANCE) == MDF1_Filter3_NS) || ((INSTANCE) == MDF1_Filter3_S) || \
+ ((INSTANCE) == MDF1_Filter4_NS) || ((INSTANCE) == MDF1_Filter4_S) || \
+ ((INSTANCE) == MDF1_Filter5_NS) || ((INSTANCE) == MDF1_Filter5_S) || \
+ ((INSTANCE) == ADF1_Filter0_NS) || ((INSTANCE) == ADF1_Filter0_S))
+
+/** @} */ /* End of group STM32U5xx_Peripheral_Exported_macros */
+
+/** @} */ /* End of group STM32U585xx */
+
+/** @} */ /* End of group ST */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U585xx_H */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5xx.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5xx.h
new file mode 100644
index 00000000..e9c3cd87
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5xx.h
@@ -0,0 +1,233 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx.h
+ * @author MCD Application Team
+ * @brief CMSIS STM32U5xx Device Peripheral Access Layer Header File.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The STM32U5xx device used in the target application
+ * - To use or not the peripheral’s drivers in application code(i.e.
+ * code will be based on direct access to peripheral’s registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32u5xx
+ * @{
+ */
+
+#ifndef STM32U5xx_H
+#define STM32U5xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32U5)
+#define STM32U5
+#endif /* STM32U5 */
+
+/* Uncomment the line below according to the target STM32U5 device used in your
+ application
+ */
+
+#if !defined (STM32U575xx) && !defined (STM32U585xx)
+ /* #define STM32U575xx */ /*!< STM32U575CIU6 STM32U575CIT6 STM32U575RIT6 STM32U575VIT6 STM32U575ZIT6 STM32U575QII6 STM32U575AII6 STM32U575CIU6Q STM32U575CIT6Q STM32U575OIY6Q STM32U575VIT6Q STM32U575QII6Q STM32U575ZIT6Q STM32U575RIT6Q STM32U575CGU6 STM32U575CGT6 STM32U575RGT6 STM32U575VGT6 STM32U575ZGT6 STM32U575QGI6 STM32U575AGI6 STM32U575CGU6Q STM32U575CGT6Q STM32U575OGY6Q STM32U575VGT6Q STM32U575QGI6Q STM32U575ZGT6Q STM32U575RGT6Q STM32U575AGI6Q Devices */
+ /* #define STM32U585xx */ /*!< STM32U585CIU6 STM32U585CIT6 STM32U585RIT6 STM32U585VIT6 STM32U585AII6 STM32U585QII6 STM32U585ZIT6 STM32U585OIY6Q STM32U585VIT6Q STM32U585QEI6Q STM32U585RIT6Q STM32U585AII6Q STM32U585CIU6Q STM32U585CIT6Q STM32U585ZET6Q Devices */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+ /*#define USE_HAL_DRIVER */
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS Device version number 1.0.0
+ */
+#define __STM32U5_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
+#define __STM32U5_CMSIS_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
+#define __STM32U5_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32U5_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32U5_CMSIS_VERSION ((__STM32U5_CMSIS_VERSION_MAIN << 24U)\
+ |(__STM32U5_CMSIS_VERSION_SUB1 << 16U)\
+ |(__STM32U5_CMSIS_VERSION_SUB2 << 8U )\
+ |(__STM32U5_CMSIS_VERSION_RC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32U575xx)
+ #include "stm32u575xx.h"
+#elif defined(STM32U585xx)
+ #include "stm32u585xx.h"
+#else
+ #error "Please select first the target STM32U5xx device used in your application (in stm32u5xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ SUCCESS = 0,
+ ERROR = !SUCCESS
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+/* Use of CMSIS compiler intrinsics for register exclusive access */
+/* Atomic 32-bit register access macro to set one or several bits */
+#define ATOMIC_SET_BIT(REG, BIT) \
+ do { \
+ uint32_t val; \
+ do { \
+ val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \
+ } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
+ } while(0)
+
+/* Atomic 32-bit register access macro to clear one or several bits */
+#define ATOMIC_CLEAR_BIT(REG, BIT) \
+ do { \
+ uint32_t val; \
+ do { \
+ val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \
+ } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
+ } while(0)
+
+/* Atomic 32-bit register access macro to clear and set one or several bits */
+#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
+ do { \
+ uint32_t val; \
+ do { \
+ val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
+ } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
+ } while(0)
+
+/* Atomic 16-bit register access macro to set one or several bits */
+#define ATOMIC_SETH_BIT(REG, BIT) \
+ do { \
+ uint16_t val; \
+ do { \
+ val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \
+ } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
+ } while(0)
+
+/* Atomic 16-bit register access macro to clear one or several bits */
+#define ATOMIC_CLEARH_BIT(REG, BIT) \
+ do { \
+ uint16_t val; \
+ do { \
+ val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \
+ } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
+ } while(0)
+
+/* Atomic 16-bit register access macro to clear and set one or several bits */
+#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \
+ do { \
+ uint16_t val; \
+ do { \
+ val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
+ } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
+ } while(0)
+
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+
+
+/**
+ * @}
+ */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32u5xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* STM32U5xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Device/ST/STM32U5xx/Include/system_stm32u5xx.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Device/ST/STM32U5xx/Include/system_stm32u5xx.h
new file mode 100644
index 00000000..811a2702
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Device/ST/STM32U5xx/Include/system_stm32u5xx.h
@@ -0,0 +1,109 @@
+/**
+ ******************************************************************************
+ * @file system_stm32u5xx.h
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M33 Device System Source File for STM32U5xx devices.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32u5xx_system
+ * @{
+ */
+
+#ifndef SYSTEM_STM32U5XX_H
+#define SYSTEM_STM32U5XX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup STM32U5xx_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U5xx_System_Exported_Variables
+ * @{
+ */
+ /* The SystemCoreClock variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
+extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
+extern const uint32_t MSIRangeTable[16]; /*!< MSI ranges table values */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32U5xx_System_Exported_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+ * @brief Update SystemCoreClock variable.
+ *
+ * Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+
+/**
+ * @brief Update SystemCoreClock variable from secure application and return its value
+ * when security is implemented in the system (Non-secure callable function).
+ *
+ * Returns the SystemCoreClock value with current core Clock retrieved from cpu registers.
+ */
+extern uint32_t SECURE_SystemCoreClockUpdate(void);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_STM32U5XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Device/ST/STM32U5xx/LICENSE.md b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Device/ST/STM32U5xx/LICENSE.md
new file mode 100644
index 00000000..20b36299
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Device/ST/STM32U5xx/LICENSE.md
@@ -0,0 +1,201 @@
+ Apache License
+ Version 2.0, January 2004
+ http://www.apache.org/licenses/
+
+ TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+ 1. Definitions.
+
+ "License" shall mean the terms and conditions for use, reproduction,
+ and distribution as defined by Sections 1 through 9 of this document.
+
+ "Licensor" shall mean the copyright owner or entity authorized by
+ the copyright owner that is granting the License.
+
+ "Legal Entity" shall mean the union of the acting entity and all
+ other entities that control, are controlled by, or are under common
+ control with that entity. For the purposes of this definition,
+ "control" means (i) the power, direct or indirect, to cause the
+ direction or management of such entity, whether by contract or
+ otherwise, or (ii) ownership of fifty percent (50%) or more of the
+ outstanding shares, or (iii) beneficial ownership of such entity.
+
+ "You" (or "Your") shall mean an individual or Legal Entity
+ exercising permissions granted by this License.
+
+ "Source" form shall mean the preferred form for making modifications,
+ including but not limited to software source code, documentation
+ source, and configuration files.
+
+ "Object" form shall mean any form resulting from mechanical
+ transformation or translation of a Source form, including but
+ not limited to compiled object code, generated documentation,
+ and conversions to other media types.
+
+ "Work" shall mean the work of authorship, whether in Source or
+ Object form, made available under the License, as indicated by a
+ copyright notice that is included in or attached to the work
+ (an example is provided in the Appendix below).
+
+ "Derivative Works" shall mean any work, whether in Source or Object
+ form, that is based on (or derived from) the Work and for which the
+ editorial revisions, annotations, elaborations, or other modifications
+ represent, as a whole, an original work of authorship. For the purposes
+ of this License, Derivative Works shall not include works that remain
+ separable from, or merely link (or bind by name) to the interfaces of,
+ the Work and Derivative Works thereof.
+
+ "Contribution" shall mean any work of authorship, including
+ the original version of the Work and any modifications or additions
+ to that Work or Derivative Works thereof, that is intentionally
+ submitted to Licensor for inclusion in the Work by the copyright owner
+ or by an individual or Legal Entity authorized to submit on behalf of
+ the copyright owner. For the purposes of this definition, "submitted"
+ means any form of electronic, verbal, or written communication sent
+ to the Licensor or its representatives, including but not limited to
+ communication on electronic mailing lists, source code control systems,
+ and issue tracking systems that are managed by, or on behalf of, the
+ Licensor for the purpose of discussing and improving the Work, but
+ excluding communication that is conspicuously marked or otherwise
+ designated in writing by the copyright owner as "Not a Contribution."
+
+ "Contributor" shall mean Licensor and any individual or Legal Entity
+ on behalf of whom a Contribution has been received by Licensor and
+ subsequently incorporated within the Work.
+
+ 2. Grant of Copyright License. Subject to the terms and conditions of
+ this License, each Contributor hereby grants to You a perpetual,
+ worldwide, non-exclusive, no-charge, royalty-free, irrevocable
+ copyright license to reproduce, prepare Derivative Works of,
+ publicly display, publicly perform, sublicense, and distribute the
+ Work and such Derivative Works in Source or Object form.
+
+ 3. Grant of Patent License. Subject to the terms and conditions of
+ this License, each Contributor hereby grants to You a perpetual,
+ worldwide, non-exclusive, no-charge, royalty-free, irrevocable
+ (except as stated in this section) patent license to make, have made,
+ use, offer to sell, sell, import, and otherwise transfer the Work,
+ where such license applies only to those patent claims licensable
+ by such Contributor that are necessarily infringed by their
+ Contribution(s) alone or by combination of their Contribution(s)
+ with the Work to which such Contribution(s) was submitted. If You
+ institute patent litigation against any entity (including a
+ cross-claim or counterclaim in a lawsuit) alleging that the Work
+ or a Contribution incorporated within the Work constitutes direct
+ or contributory patent infringement, then any patent licenses
+ granted to You under this License for that Work shall terminate
+ as of the date such litigation is filed.
+
+ 4. Redistribution. You may reproduce and distribute copies of the
+ Work or Derivative Works thereof in any medium, with or without
+ modifications, and in Source or Object form, provided that You
+ meet the following conditions:
+
+ (a) You must give any other recipients of the Work or
+ Derivative Works a copy of this License; and
+
+ (b) You must cause any modified files to carry prominent notices
+ stating that You changed the files; and
+
+ (c) You must retain, in the Source form of any Derivative Works
+ that You distribute, all copyright, patent, trademark, and
+ attribution notices from the Source form of the Work,
+ excluding those notices that do not pertain to any part of
+ the Derivative Works; and
+
+ (d) If the Work includes a "NOTICE" text file as part of its
+ distribution, then any Derivative Works that You distribute must
+ include a readable copy of the attribution notices contained
+ within such NOTICE file, excluding those notices that do not
+ pertain to any part of the Derivative Works, in at least one
+ of the following places: within a NOTICE text file distributed
+ as part of the Derivative Works; within the Source form or
+ documentation, if provided along with the Derivative Works; or,
+ within a display generated by the Derivative Works, if and
+ wherever such third-party notices normally appear. The contents
+ of the NOTICE file are for informational purposes only and
+ do not modify the License. You may add Your own attribution
+ notices within Derivative Works that You distribute, alongside
+ or as an addendum to the NOTICE text from the Work, provided
+ that such additional attribution notices cannot be construed
+ as modifying the License.
+
+ You may add Your own copyright statement to Your modifications and
+ may provide additional or different license terms and conditions
+ for use, reproduction, or distribution of Your modifications, or
+ for any such Derivative Works as a whole, provided Your use,
+ reproduction, and distribution of the Work otherwise complies with
+ the conditions stated in this License.
+
+ 5. Submission of Contributions. Unless You explicitly state otherwise,
+ any Contribution intentionally submitted for inclusion in the Work
+ by You to the Licensor shall be under the terms and conditions of
+ this License, without any additional terms or conditions.
+ Notwithstanding the above, nothing herein shall supersede or modify
+ the terms of any separate license agreement you may have executed
+ with Licensor regarding such Contributions.
+
+ 6. Trademarks. This License does not grant permission to use the trade
+ names, trademarks, service marks, or product names of the Licensor,
+ except as required for reasonable and customary use in describing the
+ origin of the Work and reproducing the content of the NOTICE file.
+
+ 7. Disclaimer of Warranty. Unless required by applicable law or
+ agreed to in writing, Licensor provides the Work (and each
+ Contributor provides its Contributions) on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied, including, without limitation, any warranties or conditions
+ of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A
+ PARTICULAR PURPOSE. You are solely responsible for determining the
+ appropriateness of using or redistributing the Work and assume any
+ risks associated with Your exercise of permissions under this License.
+
+ 8. Limitation of Liability. In no event and under no legal theory,
+ whether in tort (including negligence), contract, or otherwise,
+ unless required by applicable law (such as deliberate and grossly
+ negligent acts) or agreed to in writing, shall any Contributor be
+ liable to You for damages, including any direct, indirect, special,
+ incidental, or consequential damages of any character arising as a
+ result of this License or out of the use or inability to use the
+ Work (including but not limited to damages for loss of goodwill,
+ work stoppage, computer failure or malfunction, or any and all
+ other commercial damages or losses), even if such Contributor
+ has been advised of the possibility of such damages.
+
+ 9. Accepting Warranty or Additional Liability. While redistributing
+ the Work or Derivative Works thereof, You may choose to offer,
+ and charge a fee for, acceptance of support, warranty, indemnity,
+ or other liability obligations and/or rights consistent with this
+ License. However, in accepting such obligations, You may act only
+ on Your own behalf and on Your sole responsibility, not on behalf
+ of any other Contributor, and only if You agree to indemnify,
+ defend, and hold each Contributor harmless for any liability
+ incurred by, or claims asserted against, such Contributor by reason
+ of your accepting any such warranty or additional liability.
+
+ END OF TERMS AND CONDITIONS
+
+ APPENDIX: How to apply the Apache License to your work.
+
+ To apply the Apache License to your work, attach the following
+ boilerplate notice, with the fields enclosed by brackets "[]"
+ replaced with your own identifying information. (Don't include
+ the brackets!) The text should be enclosed in the appropriate
+ comment syntax for the file format. We also recommend that a
+ file or class name and description of purpose be included on the
+ same "printed page" as the copyright notice for easier
+ identification within third-party archives.
+
+ Copyright 2021 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Device/ST/STM32U5xx/README.md b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Device/ST/STM32U5xx/README.md
new file mode 100644
index 00000000..6fc331c3
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Device/ST/STM32U5xx/README.md
@@ -0,0 +1,42 @@
+# STM32CubeU5 CMSIS Device MCU Component
+
+
+
+## Overview
+
+**STM32Cube** is an STMicroelectronics original initiative to ease the developers life by reducing efforts, time and cost.
+
+**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform delivered for each STM32 series.
+ * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product.
+ * The STM32 HAL-LL drivers, an abstraction layer offering a set of APIs ensuring maximized portability across the STM32 portfolio.
+ * The BSP drivers of each evaluation, demonstration or nucleo board provided for this STM32 series.
+ * A consistent set of middleware libraries such as RTOS, USB, FatFS, graphics, touch sensing library...
+ * A full set of software projects (basic examples, applications, and demonstrations) for each board provided for this STM32 series.
+
+Two models of publication are proposed for the STM32Cube embedded software:
+ * The monolithic **MCU Package**: all STM32Cube software modules of one STM32 series are present (Drivers, Middleware, Projects, Utilities) in the repository (usual name **STM32Cubexx**, xx corresponding to the STM32 series).
+ * The **MCU component**: each STM32Cube software module being part of the STM32Cube MCU Package, is delivered as an individual repository, allowing the user to select and get only the required software functions.
+
+## Description
+
+This **cmsis_device_u5** MCU component repo is one element of the STM32CubeU5 MCU embedded software package, providing the **cmsis device** part.
+
+## Release note
+
+Details about the content of this release are available in the release note [here](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/cmsis_device_u5/blob/main/Release_Notes.html).
+
+## Compatibility information
+
+In this table, you can find the successive versions of this CMSIS Device component, in-line with the corresponding versions of the full MCU package:
+
+CMSIS Device U5 | CMSIS Core | Was delivered in the full MCU package
+--------------- | --------------- | -------------------------------------
+Tag v1.0.0 | Tag v5.6.0_cm33 | Tag v1.0.0 (and following, if any, till next CMSIS tag)
+Tag v1.0.1 | Tag v5.6.0_cm33 | Tag v1.0.1 (and following, if any, till next CMSIS tag)
+
+
+The full **STM32CubeU5** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeU5).
+
+## Troubleshooting
+
+Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide.
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/arm/startup_stm32u575xx.s b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/arm/startup_stm32u575xx.s
new file mode 100644
index 00000000..819eeb19
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/arm/startup_stm32u575xx.s
@@ -0,0 +1,556 @@
+;*******************************************************************************
+;* File Name : startup_stm32u575xx.s
+;* Author : MCD Application Team
+;* Description : STM32U575xx Ultra Low Power devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M33 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2021 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD SecureFault_Handler ; Secure Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection Interrupt
+ DCD RTC_IRQHandler ; RTC non-secure interrupt
+ DCD RTC_S_IRQHandler ; RTC secure interrupt
+ DCD TAMP_IRQHandler ; Tamper non-secure interrupt
+ DCD RAMCFG_IRQHandler ; RAMCFG global
+ DCD FLASH_IRQHandler ; FLASH non-secure global interrupt
+ DCD FLASH_S_IRQHandler ; FLASH secure global interrupt
+ DCD GTZC_IRQHandler ; Global TrustZone Controller interrupt
+ DCD RCC_IRQHandler ; RCC non-secure global interrupt
+ DCD RCC_S_IRQHandler ; RCC secure global interrupt
+ DCD EXTI0_IRQHandler ; EXTI Line0 interrupt
+ DCD EXTI1_IRQHandler ; EXTI Line1 interrupt
+ DCD EXTI2_IRQHandler ; EXTI Line2 interrupt
+ DCD EXTI3_IRQHandler ; EXTI Line3 interrupt
+ DCD EXTI4_IRQHandler ; EXTI Line4 interrupt
+ DCD EXTI5_IRQHandler ; EXTI Line5 interrupt
+ DCD EXTI6_IRQHandler ; EXTI Line6 interrupt
+ DCD EXTI7_IRQHandler ; EXTI Line7 interrupt
+ DCD EXTI8_IRQHandler ; EXTI Line8 interrupt
+ DCD EXTI9_IRQHandler ; EXTI Line9 interrupt
+ DCD EXTI10_IRQHandler ; EXTI Line10 interrupt
+ DCD EXTI11_IRQHandler ; EXTI Line11 interrupt
+ DCD EXTI12_IRQHandler ; EXTI Line12 interrupt
+ DCD EXTI13_IRQHandler ; EXTI Line13 interrupt
+ DCD EXTI14_IRQHandler ; EXTI Line14 interrupt
+ DCD EXTI15_IRQHandler ; EXTI Line15 interrupt
+ DCD IWDG_IRQHandler ; IWDG global interrupt
+ DCD 0 ; Reserved
+ DCD GPDMA1_Channel0_IRQHandler ; GPDMA1 Channel 0 global interrupt
+ DCD GPDMA1_Channel1_IRQHandler ; GPDMA1 Channel 1 global interrupt
+ DCD GPDMA1_Channel2_IRQHandler ; GPDMA1 Channel 2 global interrupt
+ DCD GPDMA1_Channel3_IRQHandler ; GPDMA1 Channel 3 global interrupt
+ DCD GPDMA1_Channel4_IRQHandler ; GPDMA1 Channel 4 global interrupt
+ DCD GPDMA1_Channel5_IRQHandler ; GPDMA1 Channel 5 global interrupt
+ DCD GPDMA1_Channel6_IRQHandler ; GPDMA1 Channel 6 global interrupt
+ DCD GPDMA1_Channel7_IRQHandler ; GPDMA1 Channel 7 global interrupt
+ DCD ADC1_IRQHandler ; ADC1 global interrupt
+ DCD DAC1_IRQHandler ; DAC1 global interrupt
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt 1
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update interrupt
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare interrupt
+ DCD TIM2_IRQHandler ; TIM2 global interrupt
+ DCD TIM3_IRQHandler ; TIM3 global interrupt
+ DCD TIM4_IRQHandler ; TIM4 global interrupt
+ DCD TIM5_IRQHandler ; TIM5 global interrupt
+ DCD TIM6_IRQHandler ; TIM6 global interrupt
+ DCD TIM7_IRQHandler ; TIM7 global interrupt
+ DCD TIM8_BRK_IRQHandler ; TIM8 Break interrupt
+ DCD TIM8_UP_IRQHandler ; TIM8 Update interrupt
+ DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation interrupt
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare interrupt
+ DCD I2C1_EV_IRQHandler ; I2C1 Event interrupt
+ DCD I2C1_ER_IRQHandler ; I2C1 Error interrupt
+ DCD I2C2_EV_IRQHandler ; I2C2 Event interrupt
+ DCD I2C2_ER_IRQHandler ; I2C2 Error interrupt
+ DCD SPI1_IRQHandler ; SPI1 global interrupt
+ DCD SPI2_IRQHandler ; SPI2 global interrupt
+ DCD USART1_IRQHandler ; USART1 global interrupt
+ DCD USART2_IRQHandler ; USART2 global interrupt
+ DCD USART3_IRQHandler ; USART3 global interrupt
+ DCD UART4_IRQHandler ; UART4 global interrupt
+ DCD UART5_IRQHandler ; UART5 global interrupt
+ DCD LPUART1_IRQHandler ; LPUART1 global interrupt
+ DCD LPTIM1_IRQHandler ; LPTIM1 global interrupt
+ DCD LPTIM2_IRQHandler ; LPTIM2 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global interrupt
+ DCD TIM16_IRQHandler ; TIM16 global interrupt
+ DCD TIM17_IRQHandler ; TIM17 global interrupt
+ DCD COMP_IRQHandler ; COMP1 and COMP2 through EXTI Lines interrupt
+ DCD OTG_FS_IRQHandler ; USB OTG FS global interrupt
+ DCD CRS_IRQHandler ; CRS global interrupt
+ DCD FMC_IRQHandler ; FMC global interrupt
+ DCD OCTOSPI1_IRQHandler ; OctoSPI1 global interrupt
+ DCD PWR_S3WU_IRQHandler ; PWR wake up from Stop3 interrupt
+ DCD SDMMC1_IRQHandler ; SDMMC1 global interrupt
+ DCD SDMMC2_IRQHandler ; SDMMC2 global interrupt
+ DCD GPDMA1_Channel8_IRQHandler ; GPDMA1 Channel 8 global interrupt
+ DCD GPDMA1_Channel9_IRQHandler ; GPDMA1 Channel 9 global interrupt
+ DCD GPDMA1_Channel10_IRQHandler ; GPDMA1 Channel 10 global interrupt
+ DCD GPDMA1_Channel11_IRQHandler ; GPDMA1 Channel 11 global interrupt
+ DCD GPDMA1_Channel12_IRQHandler ; GPDMA1 Channel 12 global interrupt
+ DCD GPDMA1_Channel13_IRQHandler ; GPDMA1 Channel 13 global interrupt
+ DCD GPDMA1_Channel14_IRQHandler ; GPDMA1 Channel 14 global interrupt
+ DCD GPDMA1_Channel15_IRQHandler ; GPDMA1 Channel 15 global interrupt
+ DCD I2C3_EV_IRQHandler ; I2C3 event interrupt
+ DCD I2C3_ER_IRQHandler ; I2C3 error interrupt
+ DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
+ DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt
+ DCD TSC_IRQHandler ; Touch Sense Controller global interrupt
+ DCD 0 ; Reserved
+ DCD RNG_IRQHandler ; RNG global interrupt
+ DCD FPU_IRQHandler ; FPU global interrupt
+ DCD HASH_IRQHandler ; HASH global interrupt
+ DCD 0 ; Reserved
+ DCD LPTIM3_IRQHandler ; LPTIM3 global interrupt
+ DCD SPI3_IRQHandler ; SPI3 global interrupt
+ DCD I2C4_ER_IRQHandler ; I2C4 Error interrupt
+ DCD I2C4_EV_IRQHandler ; I2C4 Event interrupt
+ DCD MDF1_FLT0_IRQHandler ; MDF1 Filter 0 global interrupt
+ DCD MDF1_FLT1_IRQHandler ; MDF1 Filter 1 global interrupt
+ DCD MDF1_FLT2_IRQHandler ; MDF1 Filter 2 global interrupt
+ DCD MDF1_FLT3_IRQHandler ; MDF1 Filter 3 global interrupt
+ DCD UCPD1_IRQHandler ; UCPD1 global interrupt
+ DCD ICACHE_IRQHandler ; Instruction cache global interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD LPTIM4_IRQHandler ; LPTIM4 global interrupt
+ DCD DCACHE1_IRQHandler ; Data cache global interrupt
+ DCD ADF1_IRQHandler ; ADF interrupt
+ DCD ADC4_IRQHandler ; ADC4 (12bits) global interrupt
+ DCD LPDMA1_Channel0_IRQHandler ; LPDMA1 SmartRun Channel 0 global interrupt
+ DCD LPDMA1_Channel1_IRQHandler ; LPDMA1 SmartRun Channel 1 global interrupt
+ DCD LPDMA1_Channel2_IRQHandler ; LPDMA1 SmartRun Channel 2 global interrupt
+ DCD LPDMA1_Channel3_IRQHandler ; LPDMA1 SmartRun Channel 3 global interrupt
+ DCD DMA2D_IRQHandler ; DMA2D global interrupt
+ DCD DCMI_PSSI_IRQHandler ; DCMI/PSSI global interrupt
+ DCD OCTOSPI2_IRQHandler ; OCTOSPI2 global interrupt
+ DCD MDF1_FLT4_IRQHandler ; MDF1 Filter 4 global interrupt
+ DCD MDF1_FLT5_IRQHandler ; MDF1 Filter 5 global interrupt
+ DCD CORDIC_IRQHandler ; CORDIC global interrupt
+ DCD FMAC_IRQHandler ; FMAC global interrupt
+
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler\
+ PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SecureFault_Handler\
+ PROC
+ EXPORT SecureFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler\
+ PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler\
+ PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler\
+ PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_AVD_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT RTC_S_IRQHandler [WEAK]
+ EXPORT TAMP_IRQHandler [WEAK]
+ EXPORT RAMCFG_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT FLASH_S_IRQHandler [WEAK]
+ EXPORT GTZC_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT RCC_S_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT EXTI5_IRQHandler [WEAK]
+ EXPORT EXTI6_IRQHandler [WEAK]
+ EXPORT EXTI7_IRQHandler [WEAK]
+ EXPORT EXTI8_IRQHandler [WEAK]
+ EXPORT EXTI9_IRQHandler [WEAK]
+ EXPORT EXTI10_IRQHandler [WEAK]
+ EXPORT EXTI11_IRQHandler [WEAK]
+ EXPORT EXTI12_IRQHandler [WEAK]
+ EXPORT EXTI13_IRQHandler [WEAK]
+ EXPORT EXTI14_IRQHandler [WEAK]
+ EXPORT EXTI15_IRQHandler [WEAK]
+ EXPORT IWDG_IRQHandler [WEAK]
+ EXPORT GPDMA1_Channel0_IRQHandler [WEAK]
+ EXPORT GPDMA1_Channel1_IRQHandler [WEAK]
+ EXPORT GPDMA1_Channel2_IRQHandler [WEAK]
+ EXPORT GPDMA1_Channel3_IRQHandler [WEAK]
+ EXPORT GPDMA1_Channel4_IRQHandler [WEAK]
+ EXPORT GPDMA1_Channel5_IRQHandler [WEAK]
+ EXPORT GPDMA1_Channel6_IRQHandler [WEAK]
+ EXPORT GPDMA1_Channel7_IRQHandler [WEAK]
+ EXPORT ADC1_IRQHandler [WEAK]
+ EXPORT DAC1_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT1_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT TIM5_IRQHandler [WEAK]
+ EXPORT TIM6_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT TIM8_BRK_IRQHandler [WEAK]
+ EXPORT TIM8_UP_IRQHandler [WEAK]
+ EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM8_CC_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT LPUART1_IRQHandler [WEAK]
+ EXPORT LPTIM1_IRQHandler [WEAK]
+ EXPORT LPTIM2_IRQHandler [WEAK]
+ EXPORT TIM15_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT COMP_IRQHandler [WEAK]
+ EXPORT OTG_FS_IRQHandler [WEAK]
+ EXPORT CRS_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT OCTOSPI1_IRQHandler [WEAK]
+ EXPORT PWR_S3WU_IRQHandler [WEAK]
+ EXPORT SDMMC1_IRQHandler [WEAK]
+ EXPORT SDMMC2_IRQHandler [WEAK]
+ EXPORT GPDMA1_Channel8_IRQHandler [WEAK]
+ EXPORT GPDMA1_Channel9_IRQHandler [WEAK]
+ EXPORT GPDMA1_Channel10_IRQHandler [WEAK]
+ EXPORT GPDMA1_Channel11_IRQHandler [WEAK]
+ EXPORT GPDMA1_Channel12_IRQHandler [WEAK]
+ EXPORT GPDMA1_Channel13_IRQHandler [WEAK]
+ EXPORT GPDMA1_Channel14_IRQHandler [WEAK]
+ EXPORT GPDMA1_Channel15_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT SAI1_IRQHandler [WEAK]
+ EXPORT SAI2_IRQHandler [WEAK]
+ EXPORT TSC_IRQHandler [WEAK]
+ EXPORT RNG_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+ EXPORT HASH_IRQHandler [WEAK]
+ EXPORT LPTIM3_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT I2C4_ER_IRQHandler [WEAK]
+ EXPORT I2C4_EV_IRQHandler [WEAK]
+ EXPORT MDF1_FLT0_IRQHandler [WEAK]
+ EXPORT MDF1_FLT1_IRQHandler [WEAK]
+ EXPORT MDF1_FLT2_IRQHandler [WEAK]
+ EXPORT MDF1_FLT3_IRQHandler [WEAK]
+ EXPORT UCPD1_IRQHandler [WEAK]
+ EXPORT ICACHE_IRQHandler [WEAK]
+ EXPORT LPTIM4_IRQHandler [WEAK]
+ EXPORT DCACHE1_IRQHandler [WEAK]
+ EXPORT ADF1_IRQHandler [WEAK]
+ EXPORT ADC4_IRQHandler [WEAK]
+ EXPORT LPDMA1_Channel0_IRQHandler [WEAK]
+ EXPORT LPDMA1_Channel1_IRQHandler [WEAK]
+ EXPORT LPDMA1_Channel2_IRQHandler [WEAK]
+ EXPORT LPDMA1_Channel3_IRQHandler [WEAK]
+ EXPORT DMA2D_IRQHandler [WEAK]
+ EXPORT DCMI_PSSI_IRQHandler [WEAK]
+ EXPORT OCTOSPI2_IRQHandler [WEAK]
+ EXPORT MDF1_FLT4_IRQHandler [WEAK]
+ EXPORT MDF1_FLT5_IRQHandler [WEAK]
+ EXPORT CORDIC_IRQHandler [WEAK]
+ EXPORT FMAC_IRQHandler [WEAK]
+
+
+WWDG_IRQHandler
+PVD_AVD_IRQHandler
+RTC_IRQHandler
+RTC_S_IRQHandler
+TAMP_IRQHandler
+RAMCFG_IRQHandler
+FLASH_IRQHandler
+FLASH_S_IRQHandler
+GTZC_IRQHandler
+RCC_IRQHandler
+RCC_S_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+EXTI5_IRQHandler
+EXTI6_IRQHandler
+EXTI7_IRQHandler
+EXTI8_IRQHandler
+EXTI9_IRQHandler
+EXTI10_IRQHandler
+EXTI11_IRQHandler
+EXTI12_IRQHandler
+EXTI13_IRQHandler
+EXTI14_IRQHandler
+EXTI15_IRQHandler
+IWDG_IRQHandler
+GPDMA1_Channel0_IRQHandler
+GPDMA1_Channel1_IRQHandler
+GPDMA1_Channel2_IRQHandler
+GPDMA1_Channel3_IRQHandler
+GPDMA1_Channel4_IRQHandler
+GPDMA1_Channel5_IRQHandler
+GPDMA1_Channel6_IRQHandler
+GPDMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+DAC1_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+TIM5_IRQHandler
+TIM6_IRQHandler
+TIM7_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+LPUART1_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+COMP_IRQHandler
+OTG_FS_IRQHandler
+CRS_IRQHandler
+FMC_IRQHandler
+OCTOSPI1_IRQHandler
+PWR_S3WU_IRQHandler
+SDMMC1_IRQHandler
+SDMMC2_IRQHandler
+GPDMA1_Channel8_IRQHandler
+GPDMA1_Channel9_IRQHandler
+GPDMA1_Channel10_IRQHandler
+GPDMA1_Channel11_IRQHandler
+GPDMA1_Channel12_IRQHandler
+GPDMA1_Channel13_IRQHandler
+GPDMA1_Channel14_IRQHandler
+GPDMA1_Channel15_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SAI1_IRQHandler
+SAI2_IRQHandler
+TSC_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+HASH_IRQHandler
+LPTIM3_IRQHandler
+SPI3_IRQHandler
+I2C4_ER_IRQHandler
+I2C4_EV_IRQHandler
+MDF1_FLT0_IRQHandler
+MDF1_FLT1_IRQHandler
+MDF1_FLT2_IRQHandler
+MDF1_FLT3_IRQHandler
+UCPD1_IRQHandler
+ICACHE_IRQHandler
+LPTIM4_IRQHandler
+DCACHE1_IRQHandler
+ADF1_IRQHandler
+ADC4_IRQHandler
+LPDMA1_Channel0_IRQHandler
+LPDMA1_Channel1_IRQHandler
+LPDMA1_Channel2_IRQHandler
+LPDMA1_Channel3_IRQHandler
+DMA2D_IRQHandler
+DCMI_PSSI_IRQHandler
+OCTOSPI2_IRQHandler
+MDF1_FLT4_IRQHandler
+MDF1_FLT5_IRQHandler
+CORDIC_IRQHandler
+FMAC_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap PROC
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDP
+
+ ALIGN
+
+ ENDIF
+
+ END
+
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/arm/startup_stm32u585xx.s b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/arm/startup_stm32u585xx.s
new file mode 100644
index 00000000..c25ab8af
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/arm/startup_stm32u585xx.s
@@ -0,0 +1,565 @@
+;*******************************************************************************
+;* File Name : startup_stm32u585xx.s
+;* Author : MCD Application Team
+;* Description : STM32U585xx Ultra Low Power devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M33 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2021 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD SecureFault_Handler ; Secure Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection Interrupt
+ DCD RTC_IRQHandler ; RTC non-secure interrupt
+ DCD RTC_S_IRQHandler ; RTC secure interrupt
+ DCD TAMP_IRQHandler ; Tamper non-secure interrupt
+ DCD RAMCFG_IRQHandler ; RAMCFG global
+ DCD FLASH_IRQHandler ; FLASH non-secure global interrupt
+ DCD FLASH_S_IRQHandler ; FLASH secure global interrupt
+ DCD GTZC_IRQHandler ; Global TrustZone Controller interrupt
+ DCD RCC_IRQHandler ; RCC non-secure global interrupt
+ DCD RCC_S_IRQHandler ; RCC secure global interrupt
+ DCD EXTI0_IRQHandler ; EXTI Line0 interrupt
+ DCD EXTI1_IRQHandler ; EXTI Line1 interrupt
+ DCD EXTI2_IRQHandler ; EXTI Line2 interrupt
+ DCD EXTI3_IRQHandler ; EXTI Line3 interrupt
+ DCD EXTI4_IRQHandler ; EXTI Line4 interrupt
+ DCD EXTI5_IRQHandler ; EXTI Line5 interrupt
+ DCD EXTI6_IRQHandler ; EXTI Line6 interrupt
+ DCD EXTI7_IRQHandler ; EXTI Line7 interrupt
+ DCD EXTI8_IRQHandler ; EXTI Line8 interrupt
+ DCD EXTI9_IRQHandler ; EXTI Line9 interrupt
+ DCD EXTI10_IRQHandler ; EXTI Line10 interrupt
+ DCD EXTI11_IRQHandler ; EXTI Line11 interrupt
+ DCD EXTI12_IRQHandler ; EXTI Line12 interrupt
+ DCD EXTI13_IRQHandler ; EXTI Line13 interrupt
+ DCD EXTI14_IRQHandler ; EXTI Line14 interrupt
+ DCD EXTI15_IRQHandler ; EXTI Line15 interrupt
+ DCD IWDG_IRQHandler ; IWDG global interrupt
+ DCD SAES_IRQHandler ; Secure AES global interrupt
+ DCD GPDMA1_Channel0_IRQHandler ; GPDMA1 Channel 0 global interrupt
+ DCD GPDMA1_Channel1_IRQHandler ; GPDMA1 Channel 1 global interrupt
+ DCD GPDMA1_Channel2_IRQHandler ; GPDMA1 Channel 2 global interrupt
+ DCD GPDMA1_Channel3_IRQHandler ; GPDMA1 Channel 3 global interrupt
+ DCD GPDMA1_Channel4_IRQHandler ; GPDMA1 Channel 4 global interrupt
+ DCD GPDMA1_Channel5_IRQHandler ; GPDMA1 Channel 5 global interrupt
+ DCD GPDMA1_Channel6_IRQHandler ; GPDMA1 Channel 6 global interrupt
+ DCD GPDMA1_Channel7_IRQHandler ; GPDMA1 Channel 7 global interrupt
+ DCD ADC1_IRQHandler ; ADC1 global interrupt
+ DCD DAC1_IRQHandler ; DAC1 global interrupt
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt 1
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update interrupt
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare interrupt
+ DCD TIM2_IRQHandler ; TIM2 global interrupt
+ DCD TIM3_IRQHandler ; TIM3 global interrupt
+ DCD TIM4_IRQHandler ; TIM4 global interrupt
+ DCD TIM5_IRQHandler ; TIM5 global interrupt
+ DCD TIM6_IRQHandler ; TIM6 global interrupt
+ DCD TIM7_IRQHandler ; TIM7 global interrupt
+ DCD TIM8_BRK_IRQHandler ; TIM8 Break interrupt
+ DCD TIM8_UP_IRQHandler ; TIM8 Update interrupt
+ DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation interrupt
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare interrupt
+ DCD I2C1_EV_IRQHandler ; I2C1 Event interrupt
+ DCD I2C1_ER_IRQHandler ; I2C1 Error interrupt
+ DCD I2C2_EV_IRQHandler ; I2C2 Event interrupt
+ DCD I2C2_ER_IRQHandler ; I2C2 Error interrupt
+ DCD SPI1_IRQHandler ; SPI1 global interrupt
+ DCD SPI2_IRQHandler ; SPI2 global interrupt
+ DCD USART1_IRQHandler ; USART1 global interrupt
+ DCD USART2_IRQHandler ; USART2 global interrupt
+ DCD USART3_IRQHandler ; USART3 global interrupt
+ DCD UART4_IRQHandler ; UART4 global interrupt
+ DCD UART5_IRQHandler ; UART5 global interrupt
+ DCD LPUART1_IRQHandler ; LPUART1 global interrupt
+ DCD LPTIM1_IRQHandler ; LPTIM1 global interrupt
+ DCD LPTIM2_IRQHandler ; LPTIM2 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global interrupt
+ DCD TIM16_IRQHandler ; TIM16 global interrupt
+ DCD TIM17_IRQHandler ; TIM17 global interrupt
+ DCD COMP_IRQHandler ; COMP1 and COMP2 through EXTI Lines interrupt
+ DCD OTG_FS_IRQHandler ; USB OTG FS global interrupt
+ DCD CRS_IRQHandler ; CRS global interrupt
+ DCD FMC_IRQHandler ; FMC global interrupt
+ DCD OCTOSPI1_IRQHandler ; OctoSPI1 global interrupt
+ DCD PWR_S3WU_IRQHandler ; PWR wake up from Stop3 interrupt
+ DCD SDMMC1_IRQHandler ; SDMMC1 global interrupt
+ DCD SDMMC2_IRQHandler ; SDMMC2 global interrupt
+ DCD GPDMA1_Channel8_IRQHandler ; GPDMA Channel 8 global interrupt
+ DCD GPDMA1_Channel9_IRQHandler ; GPDMA1 Channel 9 global interrupt
+ DCD GPDMA1_Channel10_IRQHandler ; GPDMA1 Channel 10 global interrupt
+ DCD GPDMA1_Channel11_IRQHandler ; GPDMA1 Channel 11 global interrupt
+ DCD GPDMA1_Channel12_IRQHandler ; GPDMA1 Channel 12 global interrupt
+ DCD GPDMA1_Channel13_IRQHandler ; GPDMA1 Channel 13 global interrupt
+ DCD GPDMA1_Channel14_IRQHandler ; GPDMA1 Channel 14 global interrupt
+ DCD GPDMA1_Channel15_IRQHandler ; GPDMA1 Channel 15 global interrupt
+ DCD I2C3_EV_IRQHandler ; I2C3 event interrupt
+ DCD I2C3_ER_IRQHandler ; I2C3 error interrupt
+ DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
+ DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt
+ DCD TSC_IRQHandler ; Touch Sense Controller global interrupt
+ DCD AES_IRQHandler ; AES global interrupt
+ DCD RNG_IRQHandler ; RNG global interrupt
+ DCD FPU_IRQHandler ; FPU global interrupt
+ DCD HASH_IRQHandler ; HASH global interrupt
+ DCD PKA_IRQHandler ; PKA global interrupt
+ DCD LPTIM3_IRQHandler ; LPTIM3 global interrupt
+ DCD SPI3_IRQHandler ; SPI3 global interrupt
+ DCD I2C4_ER_IRQHandler ; I2C4 Error interrupt
+ DCD I2C4_EV_IRQHandler ; I2C4 Event interrupt
+ DCD MDF1_FLT0_IRQHandler ; MDF1 Filter 0 global interrupt
+ DCD MDF1_FLT1_IRQHandler ; MDF1 Filter 1 global interrupt
+ DCD MDF1_FLT2_IRQHandler ; MDF1 Filter 2 global interrupt
+ DCD MDF1_FLT3_IRQHandler ; MDF1 Filter 3 global interrupt
+ DCD UCPD1_IRQHandler ; UCPD1 global interrupt
+ DCD ICACHE_IRQHandler ; Instruction cache global interrupt
+ DCD OTFDEC1_IRQHandler ; OTFDEC1 global interrupt
+ DCD OTFDEC2_IRQHandler ; OTFDEC2 global interrupt
+ DCD LPTIM4_IRQHandler ; LPTIM4 global interrupt
+ DCD DCACHE1_IRQHandler ; Data cache global interrupt
+ DCD ADF1_IRQHandler ; ADF interrupt
+ DCD ADC4_IRQHandler ; ADC4 (12bits) global interrupt
+ DCD LPDMA1_Channel0_IRQHandler ; LPDMA1 SmartRun Channel 0 global interrupt
+ DCD LPDMA1_Channel1_IRQHandler ; LPDMA1 SmartRun Channel 1 global interrupt
+ DCD LPDMA1_Channel2_IRQHandler ; LPDMA1 SmartRun Channel 2 global interrupt
+ DCD LPDMA1_Channel3_IRQHandler ; LPDMA1 SmartRun Channel 3 global interrupt
+ DCD DMA2D_IRQHandler ; DMA2D global interrupt
+ DCD DCMI_PSSI_IRQHandler ; DCMI/PSSI global interrupt
+ DCD OCTOSPI2_IRQHandler ; OCTOSPI2 global interrupt
+ DCD MDF1_FLT4_IRQHandler ; MDF1 Filter 4 global interrupt
+ DCD MDF1_FLT5_IRQHandler ; MDF1 Filter 5 global interrupt
+ DCD CORDIC_IRQHandler ; CORDIC global interrupt
+ DCD FMAC_IRQHandler ; FMAC global interrupt
+
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler\
+ PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SecureFault_Handler\
+ PROC
+ EXPORT SecureFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler\
+ PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler\
+ PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler\
+ PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_AVD_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT RTC_S_IRQHandler [WEAK]
+ EXPORT TAMP_IRQHandler [WEAK]
+ EXPORT RAMCFG_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT FLASH_S_IRQHandler [WEAK]
+ EXPORT GTZC_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT RCC_S_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT EXTI5_IRQHandler [WEAK]
+ EXPORT EXTI6_IRQHandler [WEAK]
+ EXPORT EXTI7_IRQHandler [WEAK]
+ EXPORT EXTI8_IRQHandler [WEAK]
+ EXPORT EXTI9_IRQHandler [WEAK]
+ EXPORT EXTI10_IRQHandler [WEAK]
+ EXPORT EXTI11_IRQHandler [WEAK]
+ EXPORT EXTI12_IRQHandler [WEAK]
+ EXPORT EXTI13_IRQHandler [WEAK]
+ EXPORT EXTI14_IRQHandler [WEAK]
+ EXPORT EXTI15_IRQHandler [WEAK]
+ EXPORT IWDG_IRQHandler [WEAK]
+ EXPORT SAES_IRQHandler [WEAK]
+ EXPORT GPDMA1_Channel0_IRQHandler [WEAK]
+ EXPORT GPDMA1_Channel1_IRQHandler [WEAK]
+ EXPORT GPDMA1_Channel2_IRQHandler [WEAK]
+ EXPORT GPDMA1_Channel3_IRQHandler [WEAK]
+ EXPORT GPDMA1_Channel4_IRQHandler [WEAK]
+ EXPORT GPDMA1_Channel5_IRQHandler [WEAK]
+ EXPORT GPDMA1_Channel6_IRQHandler [WEAK]
+ EXPORT GPDMA1_Channel7_IRQHandler [WEAK]
+ EXPORT ADC1_IRQHandler [WEAK]
+ EXPORT DAC1_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT1_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT TIM5_IRQHandler [WEAK]
+ EXPORT TIM6_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT TIM8_BRK_IRQHandler [WEAK]
+ EXPORT TIM8_UP_IRQHandler [WEAK]
+ EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM8_CC_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT LPUART1_IRQHandler [WEAK]
+ EXPORT LPTIM1_IRQHandler [WEAK]
+ EXPORT LPTIM2_IRQHandler [WEAK]
+ EXPORT TIM15_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT COMP_IRQHandler [WEAK]
+ EXPORT OTG_FS_IRQHandler [WEAK]
+ EXPORT CRS_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT OCTOSPI1_IRQHandler [WEAK]
+ EXPORT PWR_S3WU_IRQHandler [WEAK]
+ EXPORT SDMMC1_IRQHandler [WEAK]
+ EXPORT SDMMC2_IRQHandler [WEAK]
+ EXPORT GPDMA1_Channel8_IRQHandler [WEAK]
+ EXPORT GPDMA1_Channel9_IRQHandler [WEAK]
+ EXPORT GPDMA1_Channel10_IRQHandler [WEAK]
+ EXPORT GPDMA1_Channel11_IRQHandler [WEAK]
+ EXPORT GPDMA1_Channel12_IRQHandler [WEAK]
+ EXPORT GPDMA1_Channel13_IRQHandler [WEAK]
+ EXPORT GPDMA1_Channel14_IRQHandler [WEAK]
+ EXPORT GPDMA1_Channel15_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT SAI1_IRQHandler [WEAK]
+ EXPORT SAI2_IRQHandler [WEAK]
+ EXPORT TSC_IRQHandler [WEAK]
+ EXPORT AES_IRQHandler [WEAK]
+ EXPORT RNG_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+ EXPORT HASH_IRQHandler [WEAK]
+ EXPORT PKA_IRQHandler [WEAK]
+ EXPORT LPTIM3_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT I2C4_ER_IRQHandler [WEAK]
+ EXPORT I2C4_EV_IRQHandler [WEAK]
+ EXPORT MDF1_FLT0_IRQHandler [WEAK]
+ EXPORT MDF1_FLT1_IRQHandler [WEAK]
+ EXPORT MDF1_FLT2_IRQHandler [WEAK]
+ EXPORT MDF1_FLT3_IRQHandler [WEAK]
+ EXPORT UCPD1_IRQHandler [WEAK]
+ EXPORT ICACHE_IRQHandler [WEAK]
+ EXPORT OTFDEC1_IRQHandler [WEAK]
+ EXPORT OTFDEC2_IRQHandler [WEAK]
+ EXPORT LPTIM4_IRQHandler [WEAK]
+ EXPORT DCACHE1_IRQHandler [WEAK]
+ EXPORT ADF1_IRQHandler [WEAK]
+ EXPORT ADC4_IRQHandler [WEAK]
+ EXPORT LPDMA1_Channel0_IRQHandler [WEAK]
+ EXPORT LPDMA1_Channel1_IRQHandler [WEAK]
+ EXPORT LPDMA1_Channel2_IRQHandler [WEAK]
+ EXPORT LPDMA1_Channel3_IRQHandler [WEAK]
+ EXPORT DMA2D_IRQHandler [WEAK]
+ EXPORT DCMI_PSSI_IRQHandler [WEAK]
+ EXPORT OCTOSPI2_IRQHandler [WEAK]
+ EXPORT MDF1_FLT4_IRQHandler [WEAK]
+ EXPORT MDF1_FLT5_IRQHandler [WEAK]
+ EXPORT CORDIC_IRQHandler [WEAK]
+ EXPORT FMAC_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_AVD_IRQHandler
+RTC_IRQHandler
+RTC_S_IRQHandler
+TAMP_IRQHandler
+RAMCFG_IRQHandler
+FLASH_IRQHandler
+FLASH_S_IRQHandler
+GTZC_IRQHandler
+RCC_IRQHandler
+RCC_S_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+EXTI5_IRQHandler
+EXTI6_IRQHandler
+EXTI7_IRQHandler
+EXTI8_IRQHandler
+EXTI9_IRQHandler
+EXTI10_IRQHandler
+EXTI11_IRQHandler
+EXTI12_IRQHandler
+EXTI13_IRQHandler
+EXTI14_IRQHandler
+EXTI15_IRQHandler
+IWDG_IRQHandler
+SAES_IRQHandler
+GPDMA1_Channel0_IRQHandler
+GPDMA1_Channel1_IRQHandler
+GPDMA1_Channel2_IRQHandler
+GPDMA1_Channel3_IRQHandler
+GPDMA1_Channel4_IRQHandler
+GPDMA1_Channel5_IRQHandler
+GPDMA1_Channel6_IRQHandler
+GPDMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+DAC1_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+TIM5_IRQHandler
+TIM6_IRQHandler
+TIM7_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+LPUART1_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+COMP_IRQHandler
+OTG_FS_IRQHandler
+CRS_IRQHandler
+FMC_IRQHandler
+OCTOSPI1_IRQHandler
+PWR_S3WU_IRQHandler
+SDMMC1_IRQHandler
+SDMMC2_IRQHandler
+GPDMA1_Channel8_IRQHandler
+GPDMA1_Channel9_IRQHandler
+GPDMA1_Channel10_IRQHandler
+GPDMA1_Channel11_IRQHandler
+GPDMA1_Channel12_IRQHandler
+GPDMA1_Channel13_IRQHandler
+GPDMA1_Channel14_IRQHandler
+GPDMA1_Channel15_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SAI1_IRQHandler
+SAI2_IRQHandler
+TSC_IRQHandler
+AES_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+HASH_IRQHandler
+PKA_IRQHandler
+LPTIM3_IRQHandler
+SPI3_IRQHandler
+I2C4_ER_IRQHandler
+I2C4_EV_IRQHandler
+MDF1_FLT0_IRQHandler
+MDF1_FLT1_IRQHandler
+MDF1_FLT2_IRQHandler
+MDF1_FLT3_IRQHandler
+UCPD1_IRQHandler
+ICACHE_IRQHandler
+OTFDEC1_IRQHandler
+OTFDEC2_IRQHandler
+LPTIM4_IRQHandler
+DCACHE1_IRQHandler
+ADF1_IRQHandler
+ADC4_IRQHandler
+LPDMA1_Channel0_IRQHandler
+LPDMA1_Channel1_IRQHandler
+LPDMA1_Channel2_IRQHandler
+LPDMA1_Channel3_IRQHandler
+DMA2D_IRQHandler
+DCMI_PSSI_IRQHandler
+OCTOSPI2_IRQHandler
+MDF1_FLT4_IRQHandler
+MDF1_FLT5_IRQHandler
+CORDIC_IRQHandler
+FMAC_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap PROC
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDP
+
+ ALIGN
+
+ ENDIF
+
+ END
+
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_FLASH.ld b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_FLASH.ld
new file mode 100644
index 00000000..86111514
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_FLASH.ld
@@ -0,0 +1,184 @@
+/*
+******************************************************************************
+**
+** File : LinkerScript.ld
+**
+** Author : Auto-generated by STM32CubeIDE
+**
+** Abstract : Linker script for STM32U575xx Device from STM32U5 series
+** 2048Kbytes ROM
+** 768Kbytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used.
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is without any warranty
+** of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** © Copyright (c) 2021 STMicroelectronics.
+** All rights reserved. © Copyright (c) 2021 STMicroelectronics.
+** All rights reserved. © Copyright (c) 2021 STMicroelectronics.
+** All rights reserved. © Copyright (c) 2021 STMicroelectronics.
+** All rights reserved. © Copyright (c) 2021 STMicroelectronics.
+** All rights reserved. © Copyright (c) 2021 STMicroelectronics.
+** All rights reserved. © Copyright (c) 2021 STMicroelectronics.
+** All rights reserved. © Copyright (c) 2021 STMicroelectronics.
+** All rights reserved. © Copyright (c) 2021 STMicroelectronics.
+** All rights reserved. © Copyright (c) 2021 STMicroelectronics.
+** All rights reserved. © Copyright (c) 2021 STMicroelectronics.
+** All rights reserved. © Copyright (c) 2021 STMicroelectronics.
+** All rights reserved.
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U5xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U5xx_System_Private_Defines
+ * @{
+ */
+
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE 16000000U /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (MSI_VALUE)
+ #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+/******************************************************************************/
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U5xx_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U5xx_System_Private_Variables
+ * @{
+ */
+ /* The SystemCoreClock variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+ uint32_t SystemCoreClock = 4000000U;
+
+ const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
+ const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
+ const uint32_t MSIRangeTable[16] = {48000000U,24000000U,16000000U,12000000U, 4000000U, 2000000U, 1500000U,\
+ 1000000U, 3072000U, 1536000U,1024000U, 768000U, 400000U, 200000U, 150000U, 100000U};
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U5xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U5xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system.
+ * @param None
+ * @retval None
+ */
+
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
+ #endif
+
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set MSION bit */
+ RCC->CR = RCC_CR_MSISON;
+
+ /* Reset CFGR register */
+ RCC->CFGR1 = 0U;
+ RCC->CFGR2 = 0U;
+ RCC->CFGR3 = 0U;
+
+ /* Reset HSEON, CSSON , HSION, PLLxON bits */
+ RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON);
+
+ /* Reset PLLCFGR register */
+ RCC->PLL1CFGR = 0U;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= ~(RCC_CR_HSEBYP);
+
+ /* Disable all interrupts */
+ RCC->CIER = 0U;
+
+ /* Configure the Vector Table location add offset address ------------------*/
+ #ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+ #else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+ #endif
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+ * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+ *
+ * (*) MSI_VALUE is a constant defined in stm32u5xx_hal.h file (default value
+ * 4 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSI_VALUE is a constant defined in stm32u5xx_hal.h file (default value
+ * 16 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (***) HSE_VALUE is a constant defined in stm32u5xx_hal.h file (default value
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate(void)
+{
+ uint32_t pllr, pllsource, pllm , tmp, pllfracen, msirange;
+ float_t fracn1, pllvco;
+
+ /* Get MSI Range frequency--------------------------------------------------*/
+ if(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL) == 0U)
+ {
+ /* MSISRANGE from RCC_CSR applies */
+ msirange = (RCC->CSR & RCC_CSR_MSISSRANGE) >> RCC_CSR_MSISSRANGE_Pos;
+ }
+ else
+ {
+ /* MSIRANGE from RCC_CR applies */
+ msirange = (RCC->ICSCR1 & RCC_ICSCR1_MSISRANGE) >> RCC_ICSCR1_MSISRANGE_Pos;
+ }
+
+ /*MSI frequency range in HZ*/
+ msirange = MSIRangeTable[msirange];
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ switch (RCC->CFGR1 & RCC_CFGR1_SWS)
+ {
+ case 0x00: /* MSI used as system clock source */
+ SystemCoreClock = msirange;
+ break;
+
+ case 0x04: /* HSI used as system clock source */
+ SystemCoreClock = HSI_VALUE;
+ break;
+
+ case 0x08: /* HSE used as system clock source */
+ SystemCoreClock = HSE_VALUE;
+ break;
+
+ case 0x0C: /* PLL used as system clock source */
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+ SYSCLK = PLL_VCO / PLLR
+ */
+ pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC);
+ pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M)>> RCC_PLL1CFGR_PLL1M_Pos) + 1U;
+ pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN)>>RCC_PLL1CFGR_PLL1FRACEN_Pos);
+ fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN)>> RCC_PLL1FRACR_PLL1FRACN_Pos));
+
+ switch (pllsource)
+ {
+ case 0x00: /* No clock sent to PLL*/
+ pllvco = (float_t)0U;
+ break;
+
+ case 0x02: /* HSI used as PLL clock source */
+ pllvco = ((float_t)HSI_VALUE / (float_t)pllm);
+ break;
+
+ case 0x03: /* HSE used as PLL clock source */
+ pllvco = ((float_t)HSE_VALUE / (float_t)pllm);
+ break;
+
+ default: /* MSI used as PLL clock source */
+ pllvco = ((float_t)msirange / (float_t)pllm);
+ break;
+ }
+
+ pllvco = pllvco * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + (fracn1/(float_t)0x2000) + (float_t)1U);
+ pllr = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U );
+ SystemCoreClock = (uint32_t)((uint32_t)pllvco/pllr);
+ break;
+
+ default:
+ SystemCoreClock = msirange;
+ break;
+ }
+ /* Compute HCLK clock frequency --------------------------------------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos)];
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/system_stm32u5xx_ns.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/system_stm32u5xx_ns.c
new file mode 100644
index 00000000..4e3c55c4
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/system_stm32u5xx_ns.c
@@ -0,0 +1,210 @@
+/**
+ ******************************************************************************
+ * @file system_stm32u5xx_ns.c
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File
+ * to be used in non-secure application when the system implements
+ * the TrustZone-M security.
+ *
+ * This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at non-secure startup before
+ * branch to non-secure main program.
+ * This call is made inside the "startup_stm32u5xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ * After each device reset the MSI (4 MHz) is used as system clock source.
+ * Then SystemInit() function is called, in "startup_stm32u5xx.s" file, to
+ * configure the system clock before to branch to main secure program.
+ * Later, when non-secure SystemInit() function is called, in "startup_stm32u5xx.s"
+ * file, the system clock may have been updated from reset value by the main
+ * secure program.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup STM32U5xx_system
+ * @{
+ */
+
+/** @addtogroup STM32U5xx_System_Private_Includes
+ * @{
+ */
+
+#include "stm32u5xx.h"
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U5xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U5xx_System_Private_Defines
+ * @{
+ */
+
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE 16000000U /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (MSI_VALUE)
+ #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U5xx_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U5xx_System_Private_Variables
+ * @{
+ */
+ /* The SystemCoreClock variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+ uint32_t SystemCoreClock = 4000000U;
+
+ const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
+ const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
+ const uint32_t MSIRangeTable[16] = {48000000U,24000000U,16000000U,12000000U, 4000000U, 2000000U, 1500000U,\
+ 1000000U, 3072000U, 1536000U,1024000U, 768000U, 400000U, 200000U, 150000U, 100000U};
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U5xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U5xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system.
+ * @retval None
+ */
+
+void SystemInit(void)
+{
+ /* Nothing done in non-secure */
+
+ /* Non-secure main application shall call SystemCoreClockUpdate() to update */
+ /* the SystemCoreClock variable to insure non-secure application relies on */
+ /* the initial clock reference set by secure application. */
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note From the non-secure application, the SystemCoreClock value is
+ * retrieved from the secure domain via a Non-Secure Callable function
+ * since the RCC peripheral may be protected with security attributes
+ * that prevent to compute the SystemCoreClock variable from the RCC
+ * peripheral registers.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+ * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+ *
+ * (*) MSI_VALUE is a constant defined in stm32u5xx_hal.h file (default value
+ * 4 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSI_VALUE is a constant defined in stm32u5xx_hal.h file (default value
+ * 16 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (***) HSE_VALUE is a constant defined in stm32u5xx_hal.h file (default value
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @retval None
+ */
+void SystemCoreClockUpdate(void)
+{
+ /* Get the SystemCoreClock value from the secure domain */
+ SystemCoreClock = SECURE_SystemCoreClockUpdate();
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/system_stm32u5xx_s.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/system_stm32u5xx_s.c
new file mode 100644
index 00000000..1dba4bca
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/system_stm32u5xx_s.c
@@ -0,0 +1,399 @@
+/**
+ ******************************************************************************
+ * @file system_stm32u5xx_s.c
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File
+ * to be used in secure application when the system implements
+ * the TrustZone-M security.
+ *
+ * This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at secure startup just after reset
+ * and before branch to secure main program.
+ * This call is made inside the "startup_stm32u5xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ * - SECURE_SystemCoreClockUpdate(): Non-secure callable function to update
+ * the variable SystemCoreClock and return
+ * its value to the non-secure calling
+ * application. It must be called whenever
+ * the core clock is changed during program
+ * execution.
+ *
+ * After each device reset the MSI (4 MHz) is used as system clock source.
+ * Then SystemInit() function is called, in "startup_stm32u5xx.s" file, to
+ * configure the system clock before to branch to main program.
+ *
+ * This file configures the system clock as follows:
+ *=============================================================================
+ *-----------------------------------------------------------------------------
+ * System Clock source | MSI
+ *-----------------------------------------------------------------------------
+ * SYSCLK(Hz) | 4000000
+ *-----------------------------------------------------------------------------
+ * HCLK(Hz) | 4000000
+ *-----------------------------------------------------------------------------
+ * AHB Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * APB1 Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * APB2 Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * APB3 Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * PLL1_SRC | No clock
+ *-----------------------------------------------------------------------------
+ * PLL1_M | 1
+ *-----------------------------------------------------------------------------
+ * PLL1_N | 8
+ *-----------------------------------------------------------------------------
+ * PLL1_P | 7
+ *-----------------------------------------------------------------------------
+ * PLL1_Q | 2
+ *-----------------------------------------------------------------------------
+ * PLL1_R | 2
+ *-----------------------------------------------------------------------------
+ * PLL2_SRC | NA
+ *-----------------------------------------------------------------------------
+ * PLL2_M | NA
+ *-----------------------------------------------------------------------------
+ * PLL2_N | NA
+ *-----------------------------------------------------------------------------
+ * PLL2_P | NA
+ *-----------------------------------------------------------------------------
+ * PLL2_Q | NA
+ *-----------------------------------------------------------------------------
+ * PLL2_R | NA
+ *-----------------------------------------------------------------------------
+ * PLL3_SRC | NA
+ *-----------------------------------------------------------------------------
+ * PLL3_M | NA
+ *-----------------------------------------------------------------------------
+ * PLL3_N | NA
+ *-----------------------------------------------------------------------------
+ * PLL3_P | NA
+ *-----------------------------------------------------------------------------
+ * Require 48MHz for USB FS, | Disabled
+ * SDIO and RNG clock |
+ *-----------------------------------------------------------------------------
+ *=============================================================================
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup STM32U5xx_system
+ * @{
+ */
+
+/** @addtogroup STM32U5xx_System_Private_Includes
+ * @{
+ */
+
+#include "stm32u5xx.h"
+#include "partition_stm32u5xx.h" /* Trustzone-M core secure attributes */
+#include
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U5xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+#if defined ( __ICCARM__ )
+# define CMSE_NS_ENTRY __cmse_nonsecure_entry
+#else
+# define CMSE_NS_ENTRY __attribute((cmse_nonsecure_entry))
+#endif
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U5xx_System_Private_Defines
+ * @{
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE 16000000U /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (MSI_VALUE)
+ #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+/******************************************************************************/
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U5xx_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U5xx_System_Private_Variables
+ * @{
+ */
+ /* The SystemCoreClock variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+ uint32_t SystemCoreClock = 4000000U;
+
+ const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
+ const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
+ const uint32_t MSIRangeTable[16] = {48000000U,24000000U,16000000U,12000000U, 4000000U, 2000000U, 1500000U,\
+ 1000000U, 3072000U, 1536000U,1024000U, 768000U, 400000U, 200000U, 150000U, 100000U};
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U5xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U5xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system.
+ * @param None
+ * @retval None
+ */
+
+void SystemInit(void)
+{
+ /* SAU/IDAU, FPU and Interrupts secure/non-secure allocation settings */
+ TZ_SAU_Setup();
+
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
+
+ SCB_NS->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
+#endif
+
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set MSION bit */
+ RCC->CR = RCC_CR_MSISON;
+
+ /* Reset CFGR register */
+ RCC->CFGR1 = 0U;
+ RCC->CFGR2 = 0U;
+ RCC->CFGR3 = 0U;
+
+ /* Reset HSEON, CSSON , HSION, PLLxON bits */
+ RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON);
+
+ /* Reset PLLCFGR register */
+ RCC->PLL1CFGR = 0U;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= ~(RCC_CR_HSEBYP);
+
+ /* Disable all interrupts */
+ RCC->CIER = 0U;
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Depending on secure or non-secure compilation, the adequate RCC peripheral
+ * memory are is accessed thanks to RCC alias defined in stm32u5xxxx.h device file
+ * so either from RCC_S peripheral register mapped memory in secure or from
+ * RCC_NS peripheral register mapped memory in non-secure.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+ * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+ *
+ * (*) MSI_VALUE is a constant defined in stm32u5xx_hal.h file (default value
+ * 4 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSI_VALUE is a constant defined in stm32u5xx_hal.h file (default value
+ * 16 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (***) HSE_VALUE is a constant defined in stm32u5xx_hal.h file (default value
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate(void)
+{
+ uint32_t pllr, pllsource, pllm , tmp, pllfracen, msirange;
+ float_t fracn1, pllvco;
+
+ /* Get MSI Range frequency--------------------------------------------------*/
+ if(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL) == 0U)
+ {
+ /* MSISRANGE from RCC_CSR applies */
+ msirange = (RCC->CSR & RCC_CSR_MSISSRANGE) >> RCC_CSR_MSISSRANGE_Pos;
+ }
+ else
+ {
+ /* MSIRANGE from RCC_CR applies */
+ msirange = (RCC->ICSCR1 & RCC_ICSCR1_MSISRANGE) >> RCC_ICSCR1_MSISRANGE_Pos;
+ }
+
+ /*MSI frequency range in HZ*/
+ msirange = MSIRangeTable[msirange];
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ switch (RCC->CFGR1 & RCC_CFGR1_SWS)
+ {
+ case 0x00: /* MSI used as system clock source */
+ SystemCoreClock = msirange;
+ break;
+
+ case 0x04: /* HSI used as system clock source */
+ SystemCoreClock = HSI_VALUE;
+ break;
+
+ case 0x08: /* HSE used as system clock source */
+ SystemCoreClock = HSE_VALUE;
+ break;
+
+ case 0x0C: /* PLL used as system clock source */
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+ SYSCLK = PLL_VCO / PLLR
+ */
+ pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC);
+ pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M)>> RCC_PLL1CFGR_PLL1M_Pos) + 1U;
+ pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN)>>RCC_PLL1CFGR_PLL1FRACEN_Pos);
+ fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN)>> RCC_PLL1FRACR_PLL1FRACN_Pos));
+
+ switch (pllsource)
+ {
+ case 0x00: /* No clock sent to PLL*/
+ pllvco = (float_t)0U;
+ break;
+
+ case 0x02: /* HSI used as PLL clock source */
+ pllvco = ((float_t)HSI_VALUE / (float_t)pllm);
+ break;
+
+ case 0x03: /* HSE used as PLL clock source */
+ pllvco = ((float_t)HSE_VALUE / (float_t)pllm);
+ break;
+
+ default: /* MSI used as PLL clock source */
+ pllvco = ((float_t)msirange / (float_t)pllm);
+ break;
+ }
+
+ pllvco = pllvco * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + (fracn1/(float_t)0x2000) + (float_t)1U);
+ pllr = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U );
+ SystemCoreClock = (uint32_t)((uint32_t)pllvco/pllr);
+ break;
+
+ default:
+ SystemCoreClock = msirange;
+ break;
+ }
+ /* Compute HCLK clock frequency --------------------------------------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos)];
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+/**
+ * @brief Secure Non-Secure-Callable function to return the current
+ * SystemCoreClock value after SystemCoreClock update.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ * @retval SystemCoreClock value (HCLK)
+ */
+CMSE_NS_ENTRY uint32_t SECURE_SystemCoreClockUpdate(void)
+{
+ SystemCoreClockUpdate();
+
+ return SystemCoreClock;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Include/cmsis_armcc.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Include/cmsis_armcc.h
new file mode 100644
index 00000000..59f173ac
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Include/cmsis_armcc.h
@@ -0,0 +1,894 @@
+/**************************************************************************//**
+ * @file cmsis_armcc.h
+ * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version V5.1.0
+ * @date 08. May 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+ #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
+ (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
+ #define __ARM_ARCH_6M__ 1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
+ #define __ARM_ARCH_7M__ 1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+ #define __ARM_ARCH_7EM__ 1
+#endif
+
+ /* __ARM_ARCH_8M_BASE__ not applicable */
+ /* __ARM_ARCH_8M_MAIN__ not applicable */
+
+/* CMSIS compiler control DSP macros */
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+ #define __ARM_FEATURE_DSP 1
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE static __forceinline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __declspec(noreturn)
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT __packed struct
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION __packed union
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __memory_changed()
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET")))
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); */
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ register uint32_t __regBasePriMax __ASM("basepri_max");
+ __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#else
+ (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() do {\
+ __schedule_barrier();\
+ __isb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+ __schedule_barrier();\
+ __dsb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+ __schedule_barrier();\
+ __dmb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+ #define __RBIT __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value != 0U; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+ return result;
+}
+#endif
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+#else
+ #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+#else
+ #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+#else
+ #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXB(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXH(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXW(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __clrex
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+ rrx r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRBT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRHT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRT(value, ptr) __strt(value, ptr)
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+ ((int64_t)(ARG3) << 32U) ) >> 32U))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Include/cmsis_armclang.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Include/cmsis_armclang.h
new file mode 100644
index 00000000..e917f357
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Include/cmsis_armclang.h
@@ -0,0 +1,1444 @@
+/**************************************************************************//**
+ * @file cmsis_armclang.h
+ * @brief CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version V5.2.0
+ * @date 08. May 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET")))
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR() ((uint32_t)0U)
+#endif
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __set_FPSCR __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x) ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __builtin_arm_nop
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __builtin_arm_wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __builtin_arm_wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __builtin_arm_sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __builtin_arm_isb(0xF)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __builtin_arm_dsb(0xF)
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __builtin_arm_dmb(0xF)
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV(value) __builtin_bswap32(value)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __builtin_arm_rbit
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+ __builtin_clz(0) is undefined behaviour, so handle this case specially.
+ This guarantees ARM-compatible results if happening to compile on a non-ARM
+ target, and ensures the compiler doesn't decide to activate any
+ optimisations using the logic "value was passed to __builtin_clz, so it
+ is non-zero".
+ ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
+ single CLZ instruction.
+ */
+ if (value == 0U)
+ {
+ return 32U;
+ }
+ return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __builtin_arm_ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __builtin_arm_usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDAEX (uint32_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXB (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXH (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEX (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+#define __SADD8 __builtin_arm_sadd8
+#define __QADD8 __builtin_arm_qadd8
+#define __SHADD8 __builtin_arm_shadd8
+#define __UADD8 __builtin_arm_uadd8
+#define __UQADD8 __builtin_arm_uqadd8
+#define __UHADD8 __builtin_arm_uhadd8
+#define __SSUB8 __builtin_arm_ssub8
+#define __QSUB8 __builtin_arm_qsub8
+#define __SHSUB8 __builtin_arm_shsub8
+#define __USUB8 __builtin_arm_usub8
+#define __UQSUB8 __builtin_arm_uqsub8
+#define __UHSUB8 __builtin_arm_uhsub8
+#define __SADD16 __builtin_arm_sadd16
+#define __QADD16 __builtin_arm_qadd16
+#define __SHADD16 __builtin_arm_shadd16
+#define __UADD16 __builtin_arm_uadd16
+#define __UQADD16 __builtin_arm_uqadd16
+#define __UHADD16 __builtin_arm_uhadd16
+#define __SSUB16 __builtin_arm_ssub16
+#define __QSUB16 __builtin_arm_qsub16
+#define __SHSUB16 __builtin_arm_shsub16
+#define __USUB16 __builtin_arm_usub16
+#define __UQSUB16 __builtin_arm_uqsub16
+#define __UHSUB16 __builtin_arm_uhsub16
+#define __SASX __builtin_arm_sasx
+#define __QASX __builtin_arm_qasx
+#define __SHASX __builtin_arm_shasx
+#define __UASX __builtin_arm_uasx
+#define __UQASX __builtin_arm_uqasx
+#define __UHASX __builtin_arm_uhasx
+#define __SSAX __builtin_arm_ssax
+#define __QSAX __builtin_arm_qsax
+#define __SHSAX __builtin_arm_shsax
+#define __USAX __builtin_arm_usax
+#define __UQSAX __builtin_arm_uqsax
+#define __UHSAX __builtin_arm_uhsax
+#define __USAD8 __builtin_arm_usad8
+#define __USADA8 __builtin_arm_usada8
+#define __SSAT16 __builtin_arm_ssat16
+#define __USAT16 __builtin_arm_usat16
+#define __UXTB16 __builtin_arm_uxtb16
+#define __UXTAB16 __builtin_arm_uxtab16
+#define __SXTB16 __builtin_arm_sxtb16
+#define __SXTAB16 __builtin_arm_sxtab16
+#define __SMUAD __builtin_arm_smuad
+#define __SMUADX __builtin_arm_smuadx
+#define __SMLAD __builtin_arm_smlad
+#define __SMLADX __builtin_arm_smladx
+#define __SMLALD __builtin_arm_smlald
+#define __SMLALDX __builtin_arm_smlaldx
+#define __SMUSD __builtin_arm_smusd
+#define __SMUSDX __builtin_arm_smusdx
+#define __SMLSD __builtin_arm_smlsd
+#define __SMLSDX __builtin_arm_smlsdx
+#define __SMLSLD __builtin_arm_smlsld
+#define __SMLSLDX __builtin_arm_smlsldx
+#define __SEL __builtin_arm_sel
+#define __QADD __builtin_arm_qadd
+#define __QSUB __builtin_arm_qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Include/cmsis_armclang_ltm.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Include/cmsis_armclang_ltm.h
new file mode 100644
index 00000000..feec3240
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Include/cmsis_armclang_ltm.h
@@ -0,0 +1,1891 @@
+/**************************************************************************//**
+ * @file cmsis_armclang_ltm.h
+ * @brief CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version V1.2.0
+ * @date 08. May 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2018-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET")))
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR() ((uint32_t)0U)
+#endif
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __set_FPSCR __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x) ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __builtin_arm_nop
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __builtin_arm_wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __builtin_arm_wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __builtin_arm_sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __builtin_arm_isb(0xF)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __builtin_arm_dsb(0xF)
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __builtin_arm_dmb(0xF)
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV(value) __builtin_bswap32(value)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __builtin_arm_rbit
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+ __builtin_clz(0) is undefined behaviour, so handle this case specially.
+ This guarantees ARM-compatible results if happening to compile on a non-ARM
+ target, and ensures the compiler doesn't decide to activate any
+ optimisations using the logic "value was passed to __builtin_clz, so it
+ is non-zero".
+ ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
+ single CLZ instruction.
+ */
+ if (value == 0U)
+ {
+ return 32U;
+ }
+ return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __builtin_arm_ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __builtin_arm_usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDAEX (uint32_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXB (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXH (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEX (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Include/cmsis_compiler.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Include/cmsis_compiler.h
new file mode 100644
index 00000000..adbf296f
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Include/cmsis_compiler.h
@@ -0,0 +1,283 @@
+/**************************************************************************//**
+ * @file cmsis_compiler.h
+ * @brief CMSIS compiler generic header file
+ * @version V5.1.0
+ * @date 09. October 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include
+
+/*
+ * Arm Compiler 4/5
+ */
+#if defined ( __CC_ARM )
+ #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6.6 LTM (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+ #include "cmsis_armclang_ltm.h"
+
+ /*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+ #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+ #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+ #include
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+ #include
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed))
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed))
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #endif
+ #ifndef __RESTRICT
+ #define __RESTRICT __restrict
+ #endif
+ #ifndef __COMPILER_BARRIER
+ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+ #define __COMPILER_BARRIER() (void)0
+ #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __packed__
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __packed__
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __packed__
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __packed__ T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __align(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+ #ifndef __COMPILER_BARRIER
+ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+ #define __COMPILER_BARRIER() (void)0
+ #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+ #include
+
+ #ifndef __ASM
+ #define __ASM _asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ // NO RETURN is automatically detected hence no warning here
+ #define __NO_RETURN
+ #endif
+ #ifndef __USED
+ #warning No compiler specific solution for __USED. __USED is ignored.
+ #define __USED
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __weak
+ #endif
+ #ifndef __PACKED
+ #define __PACKED @packed
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT @packed struct
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION @packed union
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ @packed struct T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+ #ifndef __COMPILER_BARRIER
+ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+ #define __COMPILER_BARRIER() (void)0
+ #endif
+
+
+#else
+ #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Include/cmsis_gcc.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Include/cmsis_gcc.h
new file mode 100644
index 00000000..3ddcc58b
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Include/cmsis_gcc.h
@@ -0,0 +1,2168 @@
+/**************************************************************************//**
+ * @file cmsis_gcc.h
+ * @brief CMSIS compiler GCC header file
+ * @version V5.2.0
+ * @date 08. May 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+ #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+
+/**
+ \brief Initializes data and bss sections
+ \details This default implementations initialized all data and additional bss
+ sections relying on .copy.table and .zero.table specified properly
+ in the used linker script.
+
+ */
+__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
+{
+ extern void _start(void) __NO_RETURN;
+
+ typedef struct {
+ uint32_t const* src;
+ uint32_t* dest;
+ uint32_t wlen;
+ } __copy_table_t;
+
+ typedef struct {
+ uint32_t* dest;
+ uint32_t wlen;
+ } __zero_table_t;
+
+ extern const __copy_table_t __copy_table_start__;
+ extern const __copy_table_t __copy_table_end__;
+ extern const __zero_table_t __zero_table_start__;
+ extern const __zero_table_t __zero_table_end__;
+
+ for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) {
+ for(uint32_t i=0u; iwlen; ++i) {
+ pTable->dest[i] = pTable->src[i];
+ }
+ }
+
+ for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) {
+ for(uint32_t i=0u; iwlen; ++i) {
+ pTable->dest[i] = 0u;
+ }
+ }
+
+ _start();
+}
+
+#define __PROGRAM_START __cmsis_start
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP __StackTop
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT __StackLimit
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors")))
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_get_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ return __builtin_arm_get_fpscr();
+#else
+ uint32_t result;
+
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ return(result);
+#endif
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_set_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ __builtin_arm_set_fpscr(fpscr);
+#else
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+ (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP() __ASM volatile ("nop")
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI() __ASM volatile ("wfi")
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE() __ASM volatile ("wfe")
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV() __ASM volatile ("sev")
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+ __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+ __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+ __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (int16_t)__builtin_bswap16(value);
+#else
+ int16_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value != 0U; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return result;
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+ __builtin_clz(0) is undefined behaviour, so handle this case specially.
+ This guarantees ARM-compatible results if happening to compile on a non-ARM
+ target, and ensures the compiler doesn't decide to activate any
+ optimisations using the logic "value was passed to __builtin_clz, so it
+ is non-zero".
+ ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
+ single CLZ instruction.
+ */
+ if (value == 0U)
+ {
+ return 32U;
+ }
+ return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+__extension__ \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+ __extension__ \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Include/cmsis_iccarm.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Include/cmsis_iccarm.h
new file mode 100644
index 00000000..12d68fd9
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Include/cmsis_iccarm.h
@@ -0,0 +1,964 @@
+/**************************************************************************//**
+ * @file cmsis_iccarm.h
+ * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version V5.1.0
+ * @date 08. May 2019
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2019 IAR Systems
+// Copyright (c) 2017-2019 Arm Limited. All rights reserved.
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+ #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+ #define __ICCARM_V8 1
+#else
+ #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+ #if __ICCARM_V8
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #elif (__VER__ >= 7080000)
+ /* Needs IAR language extensions */
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #else
+ #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+ #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #elif defined(__ARM8M_BASELINE__)
+ #define __ARM_ARCH_8M_BASE__ 1
+ #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+ #if __ARM_ARCH == 6
+ #define __ARM_ARCH_6M__ 1
+ #elif __ARM_ARCH == 7
+ #if __ARM_FEATURE_DSP
+ #define __ARM_ARCH_7EM__ 1
+ #else
+ #define __ARM_ARCH_7M__ 1
+ #endif
+ #endif /* __ARM_ARCH */
+ #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+ !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+ #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+ #define __ARM_ARCH_6M__ 1
+ #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+ #define __ARM_ARCH_7M__ 1
+ #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+ #define __ARM_ARCH_7EM__ 1
+ #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+ #define __ARM_ARCH_8M_BASE__ 1
+ #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #else
+ #error "Unknown target."
+ #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+ #define __IAR_M0_FAMILY 1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+ #define __IAR_M0_FAMILY 1
+#else
+ #define __IAR_M0_FAMILY 0
+#endif
+
+
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+
+#ifndef __NO_RETURN
+ #if __ICCARM_V8
+ #define __NO_RETURN __attribute__((__noreturn__))
+ #else
+ #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+ #endif
+#endif
+
+#ifndef __PACKED
+ #if __ICCARM_V8
+ #define __PACKED __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED __packed
+ #endif
+#endif
+
+#ifndef __PACKED_STRUCT
+ #if __ICCARM_V8
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED_STRUCT __packed struct
+ #endif
+#endif
+
+#ifndef __PACKED_UNION
+ #if __ICCARM_V8
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED_UNION __packed union
+ #endif
+#endif
+
+#ifndef __RESTRICT
+ #if __ICCARM_V8
+ #define __RESTRICT __restrict
+ #else
+ /* Needs IAR language extensions */
+ #define __RESTRICT restrict
+ #endif
+#endif
+
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+
+#ifndef __FORCEINLINE
+ #define __FORCEINLINE _Pragma("inline=forced")
+#endif
+
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+ return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+ *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+ return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+ *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef __USED
+ #if __ICCARM_V8
+ #define __USED __attribute__((used))
+ #else
+ #define __USED _Pragma("__root")
+ #endif
+#endif
+
+#ifndef __WEAK
+ #if __ICCARM_V8
+ #define __WEAK __attribute__((weak))
+ #else
+ #define __WEAK _Pragma("__weak")
+ #endif
+#endif
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __iar_program_start
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP CSTACK$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT CSTACK$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __vector_table
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE @".intvec"
+#endif
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+ #define __ICCARM_INTRINSICS_VERSION__ 0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+ #if defined(__CLZ)
+ #undef __CLZ
+ #endif
+ #if defined(__REVSH)
+ #undef __REVSH
+ #endif
+ #if defined(__RBIT)
+ #undef __RBIT
+ #endif
+ #if defined(__SSAT)
+ #undef __SSAT
+ #endif
+ #if defined(__USAT)
+ #undef __USAT
+ #endif
+
+ #include "iccarm_builtin.h"
+
+ #define __disable_fault_irq __iar_builtin_disable_fiq
+ #define __disable_irq __iar_builtin_disable_interrupt
+ #define __enable_fault_irq __iar_builtin_enable_fiq
+ #define __enable_irq __iar_builtin_enable_interrupt
+ #define __arm_rsr __iar_builtin_rsr
+ #define __arm_wsr __iar_builtin_wsr
+
+
+ #define __get_APSR() (__arm_rsr("APSR"))
+ #define __get_BASEPRI() (__arm_rsr("BASEPRI"))
+ #define __get_CONTROL() (__arm_rsr("CONTROL"))
+ #define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
+
+ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ #define __get_FPSCR() (__arm_rsr("FPSCR"))
+ #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
+ #else
+ #define __get_FPSCR() ( 0 )
+ #define __set_FPSCR(VALUE) ((void)VALUE)
+ #endif
+
+ #define __get_IPSR() (__arm_rsr("IPSR"))
+ #define __get_MSP() (__arm_rsr("MSP"))
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ #define __get_MSPLIM() (0U)
+ #else
+ #define __get_MSPLIM() (__arm_rsr("MSPLIM"))
+ #endif
+ #define __get_PRIMASK() (__arm_rsr("PRIMASK"))
+ #define __get_PSP() (__arm_rsr("PSP"))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __get_PSPLIM() (0U)
+ #else
+ #define __get_PSPLIM() (__arm_rsr("PSPLIM"))
+ #endif
+
+ #define __get_xPSR() (__arm_rsr("xPSR"))
+
+ #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
+ #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
+ #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
+ #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
+ #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ #define __set_MSPLIM(VALUE) ((void)(VALUE))
+ #else
+ #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
+ #endif
+ #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
+ #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __set_PSPLIM(VALUE) ((void)(VALUE))
+ #else
+ #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
+ #endif
+
+ #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
+ #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
+ #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
+ #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
+ #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
+ #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
+ #define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
+ #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
+ #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
+ #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
+ #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
+ #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
+ #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
+ #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __TZ_get_PSPLIM_NS() (0U)
+ #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+ #else
+ #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
+ #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+ #endif
+
+ #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
+ #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+ #define __NOP __iar_builtin_no_operation
+
+ #define __CLZ __iar_builtin_CLZ
+ #define __CLREX __iar_builtin_CLREX
+
+ #define __DMB __iar_builtin_DMB
+ #define __DSB __iar_builtin_DSB
+ #define __ISB __iar_builtin_ISB
+
+ #define __LDREXB __iar_builtin_LDREXB
+ #define __LDREXH __iar_builtin_LDREXH
+ #define __LDREXW __iar_builtin_LDREX
+
+ #define __RBIT __iar_builtin_RBIT
+ #define __REV __iar_builtin_REV
+ #define __REV16 __iar_builtin_REV16
+
+ __IAR_FT int16_t __REVSH(int16_t val)
+ {
+ return (int16_t) __iar_builtin_REVSH(val);
+ }
+
+ #define __ROR __iar_builtin_ROR
+ #define __RRX __iar_builtin_RRX
+
+ #define __SEV __iar_builtin_SEV
+
+ #if !__IAR_M0_FAMILY
+ #define __SSAT __iar_builtin_SSAT
+ #endif
+
+ #define __STREXB __iar_builtin_STREXB
+ #define __STREXH __iar_builtin_STREXH
+ #define __STREXW __iar_builtin_STREX
+
+ #if !__IAR_M0_FAMILY
+ #define __USAT __iar_builtin_USAT
+ #endif
+
+ #define __WFE __iar_builtin_WFE
+ #define __WFI __iar_builtin_WFI
+
+ #if __ARM_MEDIA__
+ #define __SADD8 __iar_builtin_SADD8
+ #define __QADD8 __iar_builtin_QADD8
+ #define __SHADD8 __iar_builtin_SHADD8
+ #define __UADD8 __iar_builtin_UADD8
+ #define __UQADD8 __iar_builtin_UQADD8
+ #define __UHADD8 __iar_builtin_UHADD8
+ #define __SSUB8 __iar_builtin_SSUB8
+ #define __QSUB8 __iar_builtin_QSUB8
+ #define __SHSUB8 __iar_builtin_SHSUB8
+ #define __USUB8 __iar_builtin_USUB8
+ #define __UQSUB8 __iar_builtin_UQSUB8
+ #define __UHSUB8 __iar_builtin_UHSUB8
+ #define __SADD16 __iar_builtin_SADD16
+ #define __QADD16 __iar_builtin_QADD16
+ #define __SHADD16 __iar_builtin_SHADD16
+ #define __UADD16 __iar_builtin_UADD16
+ #define __UQADD16 __iar_builtin_UQADD16
+ #define __UHADD16 __iar_builtin_UHADD16
+ #define __SSUB16 __iar_builtin_SSUB16
+ #define __QSUB16 __iar_builtin_QSUB16
+ #define __SHSUB16 __iar_builtin_SHSUB16
+ #define __USUB16 __iar_builtin_USUB16
+ #define __UQSUB16 __iar_builtin_UQSUB16
+ #define __UHSUB16 __iar_builtin_UHSUB16
+ #define __SASX __iar_builtin_SASX
+ #define __QASX __iar_builtin_QASX
+ #define __SHASX __iar_builtin_SHASX
+ #define __UASX __iar_builtin_UASX
+ #define __UQASX __iar_builtin_UQASX
+ #define __UHASX __iar_builtin_UHASX
+ #define __SSAX __iar_builtin_SSAX
+ #define __QSAX __iar_builtin_QSAX
+ #define __SHSAX __iar_builtin_SHSAX
+ #define __USAX __iar_builtin_USAX
+ #define __UQSAX __iar_builtin_UQSAX
+ #define __UHSAX __iar_builtin_UHSAX
+ #define __USAD8 __iar_builtin_USAD8
+ #define __USADA8 __iar_builtin_USADA8
+ #define __SSAT16 __iar_builtin_SSAT16
+ #define __USAT16 __iar_builtin_USAT16
+ #define __UXTB16 __iar_builtin_UXTB16
+ #define __UXTAB16 __iar_builtin_UXTAB16
+ #define __SXTB16 __iar_builtin_SXTB16
+ #define __SXTAB16 __iar_builtin_SXTAB16
+ #define __SMUAD __iar_builtin_SMUAD
+ #define __SMUADX __iar_builtin_SMUADX
+ #define __SMMLA __iar_builtin_SMMLA
+ #define __SMLAD __iar_builtin_SMLAD
+ #define __SMLADX __iar_builtin_SMLADX
+ #define __SMLALD __iar_builtin_SMLALD
+ #define __SMLALDX __iar_builtin_SMLALDX
+ #define __SMUSD __iar_builtin_SMUSD
+ #define __SMUSDX __iar_builtin_SMUSDX
+ #define __SMLSD __iar_builtin_SMLSD
+ #define __SMLSDX __iar_builtin_SMLSDX
+ #define __SMLSLD __iar_builtin_SMLSLD
+ #define __SMLSLDX __iar_builtin_SMLSLDX
+ #define __SEL __iar_builtin_SEL
+ #define __QADD __iar_builtin_QADD
+ #define __QSUB __iar_builtin_QSUB
+ #define __PKHBT __iar_builtin_PKHBT
+ #define __PKHTB __iar_builtin_PKHTB
+ #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+ #if __IAR_M0_FAMILY
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+ #define __CLZ __cmsis_iar_clz_not_active
+ #define __SSAT __cmsis_iar_ssat_not_active
+ #define __USAT __cmsis_iar_usat_not_active
+ #define __RBIT __cmsis_iar_rbit_not_active
+ #define __get_APSR __cmsis_iar_get_APSR_not_active
+ #endif
+
+
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
+ #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+ #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+ #endif
+
+ #ifdef __INTRINSICS_INCLUDED
+ #error intrinsics.h is already included previously!
+ #endif
+
+ #include
+
+ #if __IAR_M0_FAMILY
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+ #undef __CLZ
+ #undef __SSAT
+ #undef __USAT
+ #undef __RBIT
+ #undef __get_APSR
+
+ __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+ {
+ if (data == 0U) { return 32U; }
+
+ uint32_t count = 0U;
+ uint32_t mask = 0x80000000U;
+
+ while ((data & mask) == 0U)
+ {
+ count += 1U;
+ mask = mask >> 1U;
+ }
+ return count;
+ }
+
+ __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+ {
+ uint8_t sc = 31U;
+ uint32_t r = v;
+ for (v >>= 1U; v; v >>= 1U)
+ {
+ r <<= 1U;
+ r |= v & 1U;
+ sc--;
+ }
+ return (r << sc);
+ }
+
+ __STATIC_INLINE uint32_t __get_APSR(void)
+ {
+ uint32_t res;
+ __asm("MRS %0,APSR" : "=r" (res));
+ return res;
+ }
+
+ #endif
+
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
+ #undef __get_FPSCR
+ #undef __set_FPSCR
+ #define __get_FPSCR() (0)
+ #define __set_FPSCR(VALUE) ((void)VALUE)
+ #endif
+
+ #pragma diag_suppress=Pe940
+ #pragma diag_suppress=Pe177
+
+ #define __enable_irq __enable_interrupt
+ #define __disable_irq __disable_interrupt
+ #define __NOP __no_operation
+
+ #define __get_xPSR __get_PSR
+
+ #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+ __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+ {
+ return __LDREX((unsigned long *)ptr);
+ }
+
+ __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+ {
+ return __STREX(value, (unsigned long *)ptr);
+ }
+ #endif
+
+
+ /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+ #if (__CORTEX_M >= 0x03)
+
+ __IAR_FT uint32_t __RRX(uint32_t value)
+ {
+ uint32_t result;
+ __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
+ return(result);
+ }
+
+ __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+ {
+ __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
+ }
+
+
+ #define __enable_fault_irq __enable_fiq
+ #define __disable_fault_irq __disable_fiq
+
+
+ #endif /* (__CORTEX_M >= 0x03) */
+
+ __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+ {
+ return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+ }
+
+ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+ __IAR_FT uint32_t __get_MSPLIM(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,MSPLIM" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __set_MSPLIM(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR MSPLIM,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __get_PSPLIM(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,PSPLIM" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __set_PSPLIM(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR PSPLIM,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
+ {
+ __asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PSP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,PSP_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PSP_NS(uint32_t value)
+ {
+ __asm volatile("MSR PSP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_MSP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,MSP_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_MSP_NS(uint32_t value)
+ {
+ __asm volatile("MSR MSP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_SP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,SP_NS" : "=r" (res));
+ return res;
+ }
+ __IAR_FT void __TZ_set_SP_NS(uint32_t value)
+ {
+ __asm volatile("MSR SP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
+ {
+ __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
+ {
+ __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
+ {
+ __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
+ {
+ __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
+ }
+
+ #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+ __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+ {
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+ }
+
+ __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+ {
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+ }
+#endif
+
+#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+ __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+ {
+ uint32_t res;
+ __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+ {
+ uint32_t res;
+ __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+ {
+ uint32_t res;
+ __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return res;
+ }
+
+ __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+ {
+ __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+ }
+
+ __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+ {
+ __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+ }
+
+ __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+ {
+ __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+ }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+
+ __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return res;
+ }
+
+ __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+ {
+ __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+ {
+ __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+ {
+ __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#endif /* __CMSIS_ICCARM_H__ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Include/cmsis_version.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Include/cmsis_version.h
new file mode 100644
index 00000000..f2e27466
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Include/cmsis_version.h
@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file cmsis_version.h
+ * @brief CMSIS Core(M) Version definitions
+ * @version V5.0.3
+ * @date 24. June 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/* CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+ __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
+#endif
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Include/core_armv81mml.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Include/core_armv81mml.h
new file mode 100644
index 00000000..8441e57f
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/Include/core_armv81mml.h
@@ -0,0 +1,2968 @@
+/**************************************************************************//**
+ * @file core_armv81mml.h
+ * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File
+ * @version V1.0.0
+ * @date 15. March 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2018-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV81MML_H_GENERIC
+#define __CORE_ARMV81MML_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv81MML */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ uint32_t RESERVED7[6U];
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[4U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */
+#define MPU_RLAR_PXN_Msk (0x1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h__Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MBL */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ uint32_t RESERVED0[6U];
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[809U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
+ uint32_t RESERVED4[4U];
+ __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ uint32_t RESERVED0[7U];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ If VTOR is not present address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h__Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MML */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[4U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[809U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
+ uint32_t RESERVED4[4U];
+ __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h__Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ uint32_t RESERVED0;
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ Address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t vectors = 0x0U;
+ (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
+ /* ARM Application Note 321 states that the M0 does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t vectors = 0x0U;
+ return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M0+ header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ If VTOR is not present address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t vectors = SCB->VTOR;
+#else
+ uint32_t vectors = 0x0U;
+#endif
+ (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
+ /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t vectors = SCB->VTOR;
+#else
+ uint32_t vectors = 0x0U;
+#endif
+ return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M1 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ uint32_t RESERVED0;
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
+
+#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M1 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ Address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)0x0U;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ /* ARM Application Note 321 states that the M1 does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)0x0U;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M23 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ uint32_t RESERVED0[6U];
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
+ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
+ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ uint32_t RESERVED0[7U];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ If VTOR is not present address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h__Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1[1U];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
+#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+#endif
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t vectors = (uint32_t )SCB->VTOR;
+ (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
+ /* ARM Application Note 321 states that the M3 does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t vectors = (uint32_t )SCB->VTOR;
+ return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M33 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[4U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
+ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
+ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h__Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M35P */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[4U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
+ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
+ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h__Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */
+#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t vectors = (uint32_t )SCB->VTOR;
+ (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
+ /* ARM Application Note 321 states that the M4 does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t vectors = (uint32_t )SCB->VTOR;
+ return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[1U];
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ uint32_t RESERVED3[93U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ uint32_t RESERVED7[6U];
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */
+#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */
+
+#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */
+#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */
+
+#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */
+#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */
+
+#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */
+#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */
+
+#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */
+#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */
+
+#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */
+#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */
+
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED3[981U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */
+#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t vectors = (uint32_t )SCB->VTOR;
+ (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t vectors = (uint32_t )SCB->VTOR;
+ return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = SCB->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## Cache functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_CacheFunctions Cache Functions
+ \brief Functions that configure Instruction and Data cache.
+ @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
+
+#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
+#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
+
+/**
+ \brief Enable I-Cache
+ \details Turns on I-Cache
+ */
+__STATIC_FORCEINLINE void SCB_EnableICache (void)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */
+
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */
+ __DSB();
+ __ISB();
+ SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Disable I-Cache
+ \details Turns off I-Cache
+ */
+__STATIC_FORCEINLINE void SCB_DisableICache (void)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Invalidate I-Cache
+ \details Invalidates I-Cache
+ */
+__STATIC_FORCEINLINE void SCB_InvalidateICache (void)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0UL;
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief I-Cache Invalidate by address
+ \details Invalidates I-Cache for the given address.
+ I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
+ I-Cache memory blocks which are part of given address + given size are invalidated.
+ \param[in] addr address
+ \param[in] isize size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ if ( isize > 0 ) {
+ int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
+ uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
+
+ __DSB();
+
+ do {
+ SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+ op_addr += __SCB_ICACHE_LINE_SIZE;
+ op_size -= __SCB_ICACHE_LINE_SIZE;
+ } while ( op_size > 0 );
+
+ __DSB();
+ __ISB();
+ }
+ #endif
+}
+
+
+/**
+ \brief Enable D-Cache
+ \details Turns on D-Cache
+ */
+__STATIC_FORCEINLINE void SCB_EnableDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */
+
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+ __DSB();
+
+ SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Disable D-Cache
+ \details Turns off D-Cache
+ */
+__STATIC_FORCEINLINE void SCB_DisableDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
+ __DSB();
+
+ SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean & invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Invalidate D-Cache
+ \details Invalidates D-Cache
+ */
+__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Clean D-Cache
+ \details Cleans D-Cache
+ */
+__STATIC_FORCEINLINE void SCB_CleanDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+ ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Clean & Invalidate D-Cache
+ \details Cleans and Invalidates D-Cache
+ */
+__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean & invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief D-Cache Invalidate by address
+ \details Invalidates D-Cache for the given address.
+ D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
+ D-Cache memory blocks which are part of given address + given size are invalidated.
+ \param[in] addr address
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ if ( dsize > 0 ) {
+ int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+ uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+
+ __DSB();
+
+ do {
+ SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+ op_addr += __SCB_DCACHE_LINE_SIZE;
+ op_size -= __SCB_DCACHE_LINE_SIZE;
+ } while ( op_size > 0 );
+
+ __DSB();
+ __ISB();
+ }
+ #endif
+}
+
+
+/**
+ \brief D-Cache Clean by address
+ \details Cleans D-Cache for the given address
+ D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.
+ D-Cache memory blocks which are part of given address + given size are cleaned.
+ \param[in] addr address
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ if ( dsize > 0 ) {
+ int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+ uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+
+ __DSB();
+
+ do {
+ SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+ op_addr += __SCB_DCACHE_LINE_SIZE;
+ op_size -= __SCB_DCACHE_LINE_SIZE;
+ } while ( op_size > 0 );
+
+ __DSB();
+ __ISB();
+ }
+ #endif
+}
+
+
+/**
+ \brief D-Cache Clean and Invalidate by address
+ \details Cleans and invalidates D_Cache for the given address
+ D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.
+ D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ if ( dsize > 0 ) {
+ int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+ uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+
+ __DSB();
+
+ do {
+ SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+ op_addr += __SCB_DCACHE_LINE_SIZE;
+ op_size -= __SCB_DCACHE_LINE_SIZE;
+ } while ( op_size > 0 );
+
+ __DSB();
+ __ISB();
+ }
+ #endif
+}
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ uint32_t RESERVED1[154U];
+ __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the SC000 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ uint32_t RESERVED1[129U];
+ __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t vectors = (uint32_t )SCB->VTOR;
+ (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
+ /* ARM Application Note 321 states that the M3 does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t vectors = (uint32_t )SCB->VTOR;
+ return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h
+
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in] module identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0 no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+
+#endif // TZ_CONTEXT_H
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/LICENSE.txt b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/LICENSE.txt
new file mode 100644
index 00000000..8dada3ed
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/LICENSE.txt
@@ -0,0 +1,201 @@
+ Apache License
+ Version 2.0, January 2004
+ http://www.apache.org/licenses/
+
+ TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+ 1. Definitions.
+
+ "License" shall mean the terms and conditions for use, reproduction,
+ and distribution as defined by Sections 1 through 9 of this document.
+
+ "Licensor" shall mean the copyright owner or entity authorized by
+ the copyright owner that is granting the License.
+
+ "Legal Entity" shall mean the union of the acting entity and all
+ other entities that control, are controlled by, or are under common
+ control with that entity. For the purposes of this definition,
+ "control" means (i) the power, direct or indirect, to cause the
+ direction or management of such entity, whether by contract or
+ otherwise, or (ii) ownership of fifty percent (50%) or more of the
+ outstanding shares, or (iii) beneficial ownership of such entity.
+
+ "You" (or "Your") shall mean an individual or Legal Entity
+ exercising permissions granted by this License.
+
+ "Source" form shall mean the preferred form for making modifications,
+ including but not limited to software source code, documentation
+ source, and configuration files.
+
+ "Object" form shall mean any form resulting from mechanical
+ transformation or translation of a Source form, including but
+ not limited to compiled object code, generated documentation,
+ and conversions to other media types.
+
+ "Work" shall mean the work of authorship, whether in Source or
+ Object form, made available under the License, as indicated by a
+ copyright notice that is included in or attached to the work
+ (an example is provided in the Appendix below).
+
+ "Derivative Works" shall mean any work, whether in Source or Object
+ form, that is based on (or derived from) the Work and for which the
+ editorial revisions, annotations, elaborations, or other modifications
+ represent, as a whole, an original work of authorship. For the purposes
+ of this License, Derivative Works shall not include works that remain
+ separable from, or merely link (or bind by name) to the interfaces of,
+ the Work and Derivative Works thereof.
+
+ "Contribution" shall mean any work of authorship, including
+ the original version of the Work and any modifications or additions
+ to that Work or Derivative Works thereof, that is intentionally
+ submitted to Licensor for inclusion in the Work by the copyright owner
+ or by an individual or Legal Entity authorized to submit on behalf of
+ the copyright owner. For the purposes of this definition, "submitted"
+ means any form of electronic, verbal, or written communication sent
+ to the Licensor or its representatives, including but not limited to
+ communication on electronic mailing lists, source code control systems,
+ and issue tracking systems that are managed by, or on behalf of, the
+ Licensor for the purpose of discussing and improving the Work, but
+ excluding communication that is conspicuously marked or otherwise
+ designated in writing by the copyright owner as "Not a Contribution."
+
+ "Contributor" shall mean Licensor and any individual or Legal Entity
+ on behalf of whom a Contribution has been received by Licensor and
+ subsequently incorporated within the Work.
+
+ 2. Grant of Copyright License. Subject to the terms and conditions of
+ this License, each Contributor hereby grants to You a perpetual,
+ worldwide, non-exclusive, no-charge, royalty-free, irrevocable
+ copyright license to reproduce, prepare Derivative Works of,
+ publicly display, publicly perform, sublicense, and distribute the
+ Work and such Derivative Works in Source or Object form.
+
+ 3. Grant of Patent License. Subject to the terms and conditions of
+ this License, each Contributor hereby grants to You a perpetual,
+ worldwide, non-exclusive, no-charge, royalty-free, irrevocable
+ (except as stated in this section) patent license to make, have made,
+ use, offer to sell, sell, import, and otherwise transfer the Work,
+ where such license applies only to those patent claims licensable
+ by such Contributor that are necessarily infringed by their
+ Contribution(s) alone or by combination of their Contribution(s)
+ with the Work to which such Contribution(s) was submitted. If You
+ institute patent litigation against any entity (including a
+ cross-claim or counterclaim in a lawsuit) alleging that the Work
+ or a Contribution incorporated within the Work constitutes direct
+ or contributory patent infringement, then any patent licenses
+ granted to You under this License for that Work shall terminate
+ as of the date such litigation is filed.
+
+ 4. Redistribution. You may reproduce and distribute copies of the
+ Work or Derivative Works thereof in any medium, with or without
+ modifications, and in Source or Object form, provided that You
+ meet the following conditions:
+
+ (a) You must give any other recipients of the Work or
+ Derivative Works a copy of this License; and
+
+ (b) You must cause any modified files to carry prominent notices
+ stating that You changed the files; and
+
+ (c) You must retain, in the Source form of any Derivative Works
+ that You distribute, all copyright, patent, trademark, and
+ attribution notices from the Source form of the Work,
+ excluding those notices that do not pertain to any part of
+ the Derivative Works; and
+
+ (d) If the Work includes a "NOTICE" text file as part of its
+ distribution, then any Derivative Works that You distribute must
+ include a readable copy of the attribution notices contained
+ within such NOTICE file, excluding those notices that do not
+ pertain to any part of the Derivative Works, in at least one
+ of the following places: within a NOTICE text file distributed
+ as part of the Derivative Works; within the Source form or
+ documentation, if provided along with the Derivative Works; or,
+ within a display generated by the Derivative Works, if and
+ wherever such third-party notices normally appear. The contents
+ of the NOTICE file are for informational purposes only and
+ do not modify the License. You may add Your own attribution
+ notices within Derivative Works that You distribute, alongside
+ or as an addendum to the NOTICE text from the Work, provided
+ that such additional attribution notices cannot be construed
+ as modifying the License.
+
+ You may add Your own copyright statement to Your modifications and
+ may provide additional or different license terms and conditions
+ for use, reproduction, or distribution of Your modifications, or
+ for any such Derivative Works as a whole, provided Your use,
+ reproduction, and distribution of the Work otherwise complies with
+ the conditions stated in this License.
+
+ 5. Submission of Contributions. Unless You explicitly state otherwise,
+ any Contribution intentionally submitted for inclusion in the Work
+ by You to the Licensor shall be under the terms and conditions of
+ this License, without any additional terms or conditions.
+ Notwithstanding the above, nothing herein shall supersede or modify
+ the terms of any separate license agreement you may have executed
+ with Licensor regarding such Contributions.
+
+ 6. Trademarks. This License does not grant permission to use the trade
+ names, trademarks, service marks, or product names of the Licensor,
+ except as required for reasonable and customary use in describing the
+ origin of the Work and reproducing the content of the NOTICE file.
+
+ 7. Disclaimer of Warranty. Unless required by applicable law or
+ agreed to in writing, Licensor provides the Work (and each
+ Contributor provides its Contributions) on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied, including, without limitation, any warranties or conditions
+ of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A
+ PARTICULAR PURPOSE. You are solely responsible for determining the
+ appropriateness of using or redistributing the Work and assume any
+ risks associated with Your exercise of permissions under this License.
+
+ 8. Limitation of Liability. In no event and under no legal theory,
+ whether in tort (including negligence), contract, or otherwise,
+ unless required by applicable law (such as deliberate and grossly
+ negligent acts) or agreed to in writing, shall any Contributor be
+ liable to You for damages, including any direct, indirect, special,
+ incidental, or consequential damages of any character arising as a
+ result of this License or out of the use or inability to use the
+ Work (including but not limited to damages for loss of goodwill,
+ work stoppage, computer failure or malfunction, or any and all
+ other commercial damages or losses), even if such Contributor
+ has been advised of the possibility of such damages.
+
+ 9. Accepting Warranty or Additional Liability. While redistributing
+ the Work or Derivative Works thereof, You may choose to offer,
+ and charge a fee for, acceptance of support, warranty, indemnity,
+ or other liability obligations and/or rights consistent with this
+ License. However, in accepting such obligations, You may act only
+ on Your own behalf and on Your sole responsibility, not on behalf
+ of any other Contributor, and only if You agree to indemnify,
+ defend, and hold each Contributor harmless for any liability
+ incurred by, or claims asserted against, such Contributor by reason
+ of your accepting any such warranty or additional liability.
+
+ END OF TERMS AND CONDITIONS
+
+ APPENDIX: How to apply the Apache License to your work.
+
+ To apply the Apache License to your work, attach the following
+ boilerplate notice, with the fields enclosed by brackets "{}"
+ replaced with your own identifying information. (Don't include
+ the brackets!) The text should be enclosed in the appropriate
+ comment syntax for the file format. We also recommend that a
+ file or class name and description of purpose be included on the
+ same "printed page" as the copyright notice for easier
+ identification within third-party archives.
+
+ Copyright {yyyy} {name of copyright owner}
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/README.md b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/README.md
new file mode 100644
index 00000000..e80769ff
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/CMSIS/README.md
@@ -0,0 +1,138 @@
+# CMSIS Version 5
+
+The branch *master* of this GitHub repository contains the CMSIS Version 5.6.0. The [documentation](http://arm-software.github.io/CMSIS_5/General/html/index.html) is available under http://arm-software.github.io/CMSIS_5/General/html/index.html
+
+Use [Issues](https://github.com/ARM-software/CMSIS_5#issues-and-labels) to provide feedback and report problems for CMSIS Version 5.
+
+**Note:** The branch *develop* of this GitHub repository reflects our current state of development and is constantly updated. It gives our users and partners contiguous access to the CMSIS development. It allows you to review the work and provide feedback or create pull requests for contributions.
+
+A [pre-built documentation](http://www.keil.com/pack/doc/CMSIS_Dev/index.html) is updated from time to time, but may be also generated using the instructions under [Generate CMSIS Pack for Release](https://github.com/ARM-software/CMSIS_5#generate-cmsis-pack-for-release).
+
+## Overview of CMSIS Components
+
+The following is an list of all CMSIS components that are available.
+
+| CMSIS-... | Target Processors | Description |
+|:----------|:--------------------|:-------------|
+|[Core(M)](http://arm-software.github.io/CMSIS_5/Core/html/index.html) | All Cortex-M, SecurCore | Standardized API for the Cortex-M processor core and peripherals. Includes intrinsic functions for Cortex-M4/M7/M33/M35P SIMD instructions.|
+|[Core(A)](http://arm-software.github.io/CMSIS_5/Core_A/html/index.html)| Cortex-A5/A7/A9 | API and basic run-time system for the Cortex-A5/A7/A9 processor core and peripherals.|
+|[Driver](http://arm-software.github.io/CMSIS_5/Driver/html/index.html) | All Cortex-M, SecurCore | Generic peripheral driver interfaces for middleware. Connects microcontroller peripherals with middleware that implements for example communication stacks, file systems, or graphic user interfaces.|
+|[DSP](http://arm-software.github.io/CMSIS_5/DSP/html/index.html) | All Cortex-M | DSP library collection with over 60 Functions for various data types: fixed-point (fractional q7, q15, q31) and single precision floating-point (32-bit). Implementations optimized for the SIMD instruction set are available for Cortex-M4/M7/M33/M35P.|
+|[NN](http://arm-software.github.io/CMSIS_5/NN/html/index.html) | All Cortex-M | Collection of efficient neural network kernels developed to maximize the performance and minimize the memory footprint on Cortex-M processor cores.|
+|[RTOS v1](http://arm-software.github.io/CMSIS_5/RTOS/html/index.html) | Cortex-M0/M0+/M3/M4/M7 | Common API for real-time operating systems along with a reference implementation based on RTX. It enables software components that can work across multiple RTOS systems.|
+|[RTOS v2](http://arm-software.github.io/CMSIS_5/RTOS2/html/index.html)| All Cortex-M, Cortex-A5/A7/A9 | Extends CMSIS-RTOS v1 with Armv8-M support, dynamic object creation, provisions for multi-core systems, binary compatible interface. |
+|[Pack](http://arm-software.github.io/CMSIS_5/Pack/html/index.html) | All Cortex-M, SecurCore, Cortex-A5/A7/A9 | Describes a delivery mechanism for software components, device parameters, and evaluation board support. It simplifies software re-use and product life-cycle management (PLM). |
+|[SVD](http://arm-software.github.io/CMSIS_5/SVD/html/index.html) | All Cortex-M, SecurCore | Peripheral description of a device that can be used to create peripheral awareness in debuggers or CMSIS-Core header files.|
+|[DAP](http://arm-software.github.io/CMSIS_5/DAP/html/index.html) | All Cortex | Firmware for a debug unit that interfaces to the CoreSight Debug Access Port. |
+|[Zone](http://arm-software.github.io/CMSIS_5/Zone/html/index.html) | All Cortex | Defines methods to describe system resources and to partition these resources into multiple projects and execution areas. |
+
+## Implemented Enhancements
+ - CMSIS-Core-A, RTX5: implementation for Cortex-A5/A7/A9
+ - Support for Armv8-M Architecture (Mainline and Baseline) as well as devices Cortex-M23 and Cortex-M33
+ - CMSIS-RTOS2: RTX 5 is now available for IAR, GCC, Arm Compiler 5, Arm Compiler 6
+ - CMSIS-RTOS2: FreeRTOS adoption (release) is available https://github.com/ARM-software/CMSIS-FreeRTOS
+ - CMSIS-NN: Bare metal Neural Network function library.
+ - CMSIS-DAP v2: with WinUSB for faster communication and separate pipe for SWO support
+ - Config Wizard extension: access enum’s for configuration information
+
+## Further Planned Enhancements
+ - CMSIS-Zone: management of complex system
+ - CMSIS-Pack:
+ - System Description SDF Format: describe more complex debug topologies than with a Debug Description in a tool agnostic way
+ - Github based workflow: allows to develop software packs using github infra-structure
+ - Flash algorithm via debugger: Some TurstZone enable devices cannot execute RAM. Commands that allow flash programming will be added to Debug Description.
+ - CPDSC project file format: allows project templates that are agnostic of an IDE
+ - Minimize need for IDE specific settings: CMSIS-Pack supports IDE specific parameters. Analyze and minimize
+
+For further details see also the [Slides of the Embedded World CMSIS Partner Meeting](https://github.com/ARM-software/CMSIS_5/blob/develop/CMSIS_EW2019.pdf).
+
+## Other related GitHub repositories
+
+| Repository | Description |
+|:--------------------------- |:--------------------------------------------------------- |
+| [cmsis-pack-eclipse](https://github.com/ARM-software/cmsis-pack-eclipse) | CMSIS-Pack Management for Eclipse reference implementation Pack support |
+| [CMSIS-FreeRTOS](https://github.com/arm-software/CMSIS-FreeRTOS) | CMSIS-RTOS adoption of FreeRTOS |
+| [CMSIS-Driver](https://github.com/arm-software/CMSIS-Driver) | Generic MCU driver implementations and templates for Ethernet MAC/PHY and Flash. |
+| [CMSIS-Driver_Validation](https://github.com/ARM-software/CMSIS-Driver_Validation) | CMSIS-Driver Validation can be used to verify CMSIS-Driver in a user system |
+| [CMSIS-Zone](https://github.com/ARM-software/CMSIS-Zone) | CMSIS-Zone Utility along with example projects and FreeMarker templates |
+| [NXP_LPC](https://github.com/ARM-software/NXP_LPC) | CMSIS Driver Implementations for the NXP LPC Microcontroller Series |
+| [mdk-packs](https://github.com/mdk-packs) | IoT cloud connectors as trail implementations for MDK (help us to make it generic)|
+| [trustedfirmware.org](https://www.trustedfirmware.org/) | Arm Trusted Firmware provides a reference implementation of secure world software for Armv8-A and Armv8-M.|
+
+
+## Directory Structure
+
+| Directory | Content |
+|:-------------------- |:--------------------------------------------------------- |
+| CMSIS/Core | CMSIS-Core(M) related files (for release) |
+| CMSIS/Core_A | CMSIS-Core(A) related files (for release) |
+| CMSIS/CoreValidation | Validation for Core(M) and Core(A) (NOT part of release) |
+| CMSIS/DAP | CMSIS-DAP related files and examples |
+| CMSIS/Driver | CMSIS-Driver API headers and template files |
+| CMSIS/DSP | CMSIS-DSP related files |
+| CMSIS/NN | CMSIS-NN related files |
+| CMSIS/RTOS | RTOS v1 related files (for Cortex-M) |
+| CMSIS/RTOS2 | RTOS v2 related files (for Cortex-M & Armv8-M) |
+| CMSIS/Pack | CMSIS-Pack examples and tutorials |
+| CMSIS/DoxyGen | Source of the documentation |
+| CMSIS/Utilities | Utility programs |
+
+## Generate CMSIS Pack for Release
+
+This GitHub development repository contains already pre-built libraries (stored in Git-LFS) of various software components (DSP, RTOS, RTOS2).
+These libraries are validated for release. Git-LFS needs to be installed to retrieve the actual binary files, please see https://git-lfs.github.com/.
+
+To build a complete CMSIS pack for installation the following additional tools are required:
+ - **doxygen.exe** Version: 1.8.6 (Documentation Generator)
+ - **mscgen.exe** Version: 0.20 (Message Sequence Chart Converter)
+ - **7z.exe (7-Zip)** Version: 16.02 (File Archiver)
+
+Using these tools, you can generate on a Windows PC:
+ - **CMSIS Software Pack** using the batch file **gen_pack.bat** (located in ./CMSIS/Utilities). This batch file also generates the documentation.
+
+ - **CMSIS Documentation** using the batch file **genDoc.bat** (located in ./CMSIS/Doxygen).
+
+The file ./CMSIS/DoxyGen/How2Doc.txt describes the rules for creating API documentation.
+
+## License
+
+Arm CMSIS is licensed under Apache-2.0.
+
+## Contributions and Pull Requests
+
+Contributions are accepted under Apache-2.0. Only submit contributions where you have authored all of the code.
+
+### Issues and Labels
+
+Please feel free to raise an [issue on GitHub](https://github.com/ARM-software/CMSIS_5/issues)
+to report misbehavior (i.e. bugs) or start discussions about enhancements. This
+is your best way to interact directly with the maintenance team and the community.
+We encourage you to append implementation suggestions as this helps to decrease the
+workload of the very limited maintenance team.
+
+We will be monitoring and responding to issues as best we can.
+Please attempt to avoid filing duplicates of open or closed items when possible.
+In the spirit of openness we will be tagging issues with the following:
+
+- **bug** – We consider this issue to be a bug that will be investigated.
+
+- **wontfix** - We appreciate this issue but decided not to change the current behavior.
+
+- **enhancement** – Denotes something that will be implemented soon.
+
+- **future** - Denotes something not yet schedule for implementation.
+
+- **out-of-scope** - We consider this issue loosely related to CMSIS. It might by implemented outside of CMSIS. Let us know about your work.
+
+- **question** – We have further questions to this issue. Please review and provide feedback.
+
+- **documentation** - This issue is a documentation flaw that will be improved in future.
+
+- **review** - This issue is under review. Please be patient.
+
+- **DONE** - We consider this issue as resolved - please review and close it. In case of no further activity this issues will be closed after a week.
+
+- **duplicate** - This issue is already addressed elsewhere, see comment with provided references.
+
+- **Important Information** - We provide essential informations regarding planned or resolved major enhancements.
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
new file mode 100644
index 00000000..d6dd9e01
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
@@ -0,0 +1,3853 @@
+/**
+ ******************************************************************************
+ * @file stm32_hal_legacy.h
+ * @author MCD Application Team
+ * @brief This file contains aliases definition for the STM32Cube HAL constants
+ * macros and functions maintained for legacy purpose.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32_HAL_LEGACY
+#define STM32_HAL_LEGACY
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define AES_FLAG_RDERR CRYP_FLAG_RDERR
+#define AES_FLAG_WRERR CRYP_FLAG_WRERR
+#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
+#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
+#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
+#if defined(STM32U5)
+#define CRYP_DATATYPE_32B CRYP_NO_SWAP
+#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
+#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
+#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
+#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF
+#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
+#endif /* STM32U5 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define ADC_RESOLUTION12b ADC_RESOLUTION_12B
+#define ADC_RESOLUTION10b ADC_RESOLUTION_10B
+#define ADC_RESOLUTION8b ADC_RESOLUTION_8B
+#define ADC_RESOLUTION6b ADC_RESOLUTION_6B
+#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
+#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
+#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
+#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
+#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
+#define REGULAR_GROUP ADC_REGULAR_GROUP
+#define INJECTED_GROUP ADC_INJECTED_GROUP
+#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
+#define AWD_EVENT ADC_AWD_EVENT
+#define AWD1_EVENT ADC_AWD1_EVENT
+#define AWD2_EVENT ADC_AWD2_EVENT
+#define AWD3_EVENT ADC_AWD3_EVENT
+#define OVR_EVENT ADC_OVR_EVENT
+#define JQOVF_EVENT ADC_JQOVF_EVENT
+#define ALL_CHANNELS ADC_ALL_CHANNELS
+#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
+#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
+#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
+#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
+#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
+#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
+#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
+#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
+#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
+#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
+#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
+#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
+#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
+#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
+#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
+#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
+#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
+#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
+#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
+#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
+#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5
+
+#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
+#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
+#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
+#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
+#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
+#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
+#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
+
+#if defined(STM32H7)
+#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT
+#endif /* STM32H7 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
+#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
+#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
+#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
+#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
+#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
+#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
+#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
+#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
+#if defined(STM32L0)
+#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
+#endif
+#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
+#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32L0) || defined(STM32L4)
+#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
+
+#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
+#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
+#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
+#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
+#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
+#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
+
+#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
+#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
+#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
+#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
+#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
+#if defined(STM32L0)
+/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */
+/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */
+/* to the second dedicated IO (only for COMP2). */
+#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
+#else
+#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
+#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
+#endif
+#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
+#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
+
+#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
+#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
+
+/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
+/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
+#if defined(COMP_CSR_LOCK)
+#define COMP_FLAG_LOCK COMP_CSR_LOCK
+#elif defined(COMP_CSR_COMP1LOCK)
+#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
+#elif defined(COMP_CSR_COMPxLOCK)
+#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
+#endif
+
+#if defined(STM32L4)
+#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
+#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
+#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
+#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
+#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
+#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
+#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
+#endif
+
+#if defined(STM32L0)
+#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
+#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
+#else
+#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
+#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
+#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
+#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
+#endif
+
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Aliases CRC API aliases
+ * @{
+ */
+#if defined(STM32WL) || defined(STM32WB) || defined(STM32L5) || defined(STM32L4)
+#else
+#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
+#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
+#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define DAC1_CHANNEL_1 DAC_CHANNEL_1
+#define DAC1_CHANNEL_2 DAC_CHANNEL_2
+#define DAC2_CHANNEL_1 DAC_CHANNEL_1
+#define DAC_WAVE_NONE 0x00000000U
+#define DAC_WAVE_NOISE DAC_CR_WAVE1_0
+#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1
+#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
+#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
+#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
+
+#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
+#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
+#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
+#endif
+
+#if defined(STM32U5)
+#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1
+#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1
+#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
+#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1
+#endif
+
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
+#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
+#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
+#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
+#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
+#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
+#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
+#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
+#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
+#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
+#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
+#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
+#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
+#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
+#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
+#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
+
+#define IS_HAL_REMAPDMA IS_DMA_REMAP
+#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
+#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
+
+#if defined(STM32L4)
+
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT
+#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT
+#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT
+
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
+#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
+#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
+#endif
+
+#endif /* STM32L4 */
+
+#if defined(STM32G0)
+#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
+#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM
+#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM
+
+#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM
+#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM
+#endif
+
+#if defined(STM32H7)
+
+#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
+
+#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
+#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
+
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
+#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
+
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
+
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
+#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
+#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT
+#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
+#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
+
+#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT
+#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
+
+#endif /* STM32H7 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
+#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
+#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
+#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
+#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
+#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
+#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
+#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
+#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
+#define OBEX_PCROP OPTIONBYTE_PCROP
+#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
+#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
+#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
+#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
+#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
+#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
+#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
+#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
+#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
+#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
+#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
+#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
+#define PAGESIZE FLASH_PAGE_SIZE
+#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
+#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
+#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
+#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
+#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
+#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
+#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
+#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
+#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
+#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
+#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
+#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
+#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
+#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
+#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
+#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
+#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
+#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
+#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
+#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
+#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
+#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
+#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
+#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
+#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
+#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
+#define OB_WDG_SW OB_IWDG_SW
+#define OB_WDG_HW OB_IWDG_HW
+#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
+#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
+#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
+#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
+#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
+#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
+#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
+#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
+#if defined(STM32G0)
+#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE
+#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH
+#else
+#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE
+#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE
+#endif
+#if defined(STM32H7)
+#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
+#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
+#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1
+#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
+#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
+#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
+#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
+#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
+#endif /* STM32H7 */
+#if defined(STM32U5)
+#define OB_USER_nRST_STOP OB_USER_NRST_STOP
+#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
+#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
+#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0
+#define OB_USER_nBOOT0 OB_USER_NBOOT0
+#define OB_nBOOT0_RESET OB_NBOOT0_RESET
+#define OB_nBOOT0_SET OB_NBOOT0_SET
+#endif /* STM32U5 */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#if defined(STM32H7)
+#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE
+#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE
+#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET
+#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET
+#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
+#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
+#endif /* STM32H7 */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
+#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
+#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
+#if defined(STM32G4)
+
+#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster
+#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster
+#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD
+#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
+#endif /* STM32G4 */
+
+
+
+/**
+ * @}
+ */
+
+
+/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
+ * @{
+ */
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
+#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
+#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
+#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)
+#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
+#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
+#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
+#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
+#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
+/**
+ * @}
+ */
+
+/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define GET_GPIO_SOURCE GPIO_GET_INDEX
+#define GET_GPIO_INDEX GPIO_GET_INDEX
+
+#if defined(STM32F4)
+#define GPIO_AF12_SDMMC GPIO_AF12_SDIO
+#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
+#endif
+
+#if defined(STM32F7)
+#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
+#endif
+
+#if defined(STM32L4)
+#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
+#endif
+
+#if defined(STM32H7)
+#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1
+#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1
+#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1
+#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2
+#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2
+#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2
+
+#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \
+ defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx)
+#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
+#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
+#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
+#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
+#endif /* STM32H7 */
+
+#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
+#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
+#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
+
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
+#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
+#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
+#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/
+
+#if defined(STM32L1)
+#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
+#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
+#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
+#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L1 */
+
+#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
+#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
+#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
+#endif /* STM32F0 || STM32F3 || STM32F1 */
+
+#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
+/**
+ * @}
+ */
+
+/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
+
+#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
+#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
+#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
+#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD
+#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
+#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
+#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
+#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
+
+#if defined(STM32G4)
+#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig
+#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
+#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable
+#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset
+#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A
+#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B
+#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL
+#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL
+#endif /* STM32G4 */
+
+#if defined(STM32H7)
+#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+
+#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+#endif /* STM32H7 */
+
+#if defined(STM32F3)
+/** @brief Constants defining available sources associated to external events.
+ */
+#define HRTIM_EVENTSRC_1 (0x00000000U)
+#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0)
+#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
+#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
+
+/** @brief Constants defining the DLL calibration periods (in micro seconds)
+ */
+#define HRTIM_CALIBRATIONRATE_7300 0x00000000U
+#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0)
+#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1)
+#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
+
+#endif /* STM32F3 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
+#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
+#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
+#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
+#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
+#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
+#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
+#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
+#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
+#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
+#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX
+#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
+#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define KR_KEY_RELOAD IWDG_KEY_RELOAD
+#define KR_KEY_ENABLE IWDG_KEY_ENABLE
+#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
+#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
+
+#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
+#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
+#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
+
+#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+/* The following 3 definition have also been present in a temporary version of lptim.h */
+/* They need to be renamed also to the right name, just in case */
+#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+#if defined(STM32U5)
+#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF
+#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF
+#endif /* STM32U5 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b
+#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b
+#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b
+#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b
+
+#define NAND_AddressTypedef NAND_AddressTypeDef
+
+#define __ARRAY_ADDRESS ARRAY_ADDRESS
+#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
+#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
+#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
+#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define NOR_StatusTypedef HAL_NOR_StatusTypeDef
+#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
+#define NOR_ONGOING HAL_NOR_STATUS_ONGOING
+#define NOR_ERROR HAL_NOR_STATUS_ERROR
+#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
+
+#define __NOR_WRITE NOR_WRITE
+#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
+/**
+ * @}
+ */
+
+/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
+#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
+#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
+#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
+
+#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
+#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
+#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
+#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
+
+#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
+#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
+
+#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
+#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
+
+#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
+#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
+#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
+#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
+
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
+#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
+#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
+#endif
+
+#if defined(STM32L4) || defined(STM32L5)
+#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER
+#elif defined(STM32G4)
+#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
+
+#if defined(STM32H7)
+#define I2S_IT_TXE I2S_IT_TXP
+#define I2S_IT_RXNE I2S_IT_RXP
+
+#define I2S_FLAG_TXE I2S_FLAG_TXP
+#define I2S_FLAG_RXNE I2S_FLAG_RXP
+#endif
+
+#if defined(STM32F7)
+#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+/* Compact Flash-ATA registers description */
+#define CF_DATA ATA_DATA
+#define CF_SECTOR_COUNT ATA_SECTOR_COUNT
+#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
+#define CF_CYLINDER_LOW ATA_CYLINDER_LOW
+#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
+#define CF_CARD_HEAD ATA_CARD_HEAD
+#define CF_STATUS_CMD ATA_STATUS_CMD
+#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
+#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
+
+/* Compact Flash-ATA commands */
+#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
+#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
+#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
+#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
+
+#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
+#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
+#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
+#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
+#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define FORMAT_BIN RTC_FORMAT_BIN
+#define FORMAT_BCD RTC_FORMAT_BCD
+
+#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
+#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
+#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
+
+#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
+#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
+#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
+#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
+
+#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
+#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
+
+#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
+#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
+#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
+
+#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
+#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
+#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
+
+#if defined(STM32H7)
+#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
+#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
+
+#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
+#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
+#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
+#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL
+#endif /* STM32H7 */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
+#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
+
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+
+#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
+#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
+
+#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
+#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
+#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
+#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
+#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
+#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
+#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
+#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
+#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
+#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
+#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
+#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
+#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
+
+#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
+#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
+
+#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
+#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
+
+#if defined(STM32H7)
+
+#define SPI_FLAG_TXE SPI_FLAG_TXP
+#define SPI_FLAG_RXNE SPI_FLAG_RXP
+
+#define SPI_IT_TXE SPI_IT_TXP
+#define SPI_IT_RXNE SPI_IT_RXP
+
+#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
+#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
+#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
+#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
+
+#endif /* STM32H7 */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
+#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
+
+#define TIM_DMABase_CR1 TIM_DMABASE_CR1
+#define TIM_DMABase_CR2 TIM_DMABASE_CR2
+#define TIM_DMABase_SMCR TIM_DMABASE_SMCR
+#define TIM_DMABase_DIER TIM_DMABASE_DIER
+#define TIM_DMABase_SR TIM_DMABASE_SR
+#define TIM_DMABase_EGR TIM_DMABASE_EGR
+#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
+#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
+#define TIM_DMABase_CCER TIM_DMABASE_CCER
+#define TIM_DMABase_CNT TIM_DMABASE_CNT
+#define TIM_DMABase_PSC TIM_DMABASE_PSC
+#define TIM_DMABase_ARR TIM_DMABASE_ARR
+#define TIM_DMABase_RCR TIM_DMABASE_RCR
+#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
+#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
+#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
+#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
+#define TIM_DMABase_BDTR TIM_DMABASE_BDTR
+#define TIM_DMABase_DCR TIM_DMABASE_DCR
+#define TIM_DMABase_DMAR TIM_DMABASE_DMAR
+#define TIM_DMABase_OR1 TIM_DMABASE_OR1
+#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
+#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
+#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
+#define TIM_DMABase_OR2 TIM_DMABASE_OR2
+#define TIM_DMABase_OR3 TIM_DMABASE_OR3
+#define TIM_DMABase_OR TIM_DMABASE_OR
+
+#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
+#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
+#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
+#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
+#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
+#define TIM_EventSource_COM TIM_EVENTSOURCE_COM
+#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
+#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
+#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
+
+#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
+#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
+#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
+#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
+#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
+#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
+#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
+#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
+#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
+#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
+#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
+#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
+#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
+#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
+#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
+#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
+#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
+#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
+
+#if defined(STM32L0)
+#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO
+#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO
+#endif
+
+#if defined(STM32F3)
+#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
+#endif
+
+#if defined(STM32H7)
+#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1
+#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2
+#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1
+#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2
+#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1
+#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2
+#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1
+#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1
+#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2
+#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1
+#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2
+#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2
+#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1
+#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2
+#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
+#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
+/**
+ * @}
+ */
+
+/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
+#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
+
+#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
+#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
+
+#define __DIV_SAMPLING16 UART_DIV_SAMPLING16
+#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
+#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
+#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
+
+#define __DIV_SAMPLING8 UART_DIV_SAMPLING8
+#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
+#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
+#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
+
+#define __DIV_LPUART UART_DIV_LPUART
+
+#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
+#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
+#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
+
+#define USARTNACK_ENABLED USART_NACK_ENABLE
+#define USARTNACK_DISABLED USART_NACK_DISABLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define CFR_BASE WWDG_CFR_BASE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
+#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
+#define CAN_IT_RQCP0 CAN_IT_TME
+#define CAN_IT_RQCP1 CAN_IT_TME
+#define CAN_IT_RQCP2 CAN_IT_TME
+#define INAK_TIMEOUT CAN_TIMEOUT_VALUE
+#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
+#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
+#define CAN_TXSTATUS_OK ((uint8_t)0x01U)
+#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define VLAN_TAG ETH_VLAN_TAG
+#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
+#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
+#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
+#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
+#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
+#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
+#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
+
+#define ETH_MMCCR 0x00000100U
+#define ETH_MMCRIR 0x00000104U
+#define ETH_MMCTIR 0x00000108U
+#define ETH_MMCRIMR 0x0000010CU
+#define ETH_MMCTIMR 0x00000110U
+#define ETH_MMCTGFSCCR 0x0000014CU
+#define ETH_MMCTGFMSCCR 0x00000150U
+#define ETH_MMCTGFCR 0x00000168U
+#define ETH_MMCRFCECR 0x00000194U
+#define ETH_MMCRFAECR 0x00000198U
+#define ETH_MMCRGUFCR 0x000001C4U
+
+#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
+#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
+#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
+#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
+#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
+#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
+#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
+#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
+#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
+#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
+#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
+#if defined(STM32F1)
+#else
+#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
+#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
+#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
+#endif
+#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
+#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
+#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
+#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
+#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
+#define DCMI_IT_OVF DCMI_IT_OVR
+#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
+#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
+
+#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
+#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
+#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
+
+/**
+ * @}
+ */
+
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
+ || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
+ || defined(STM32H7)
+/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
+#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
+#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
+#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
+#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
+
+#define CM_ARGB8888 DMA2D_INPUT_ARGB8888
+#define CM_RGB888 DMA2D_INPUT_RGB888
+#define CM_RGB565 DMA2D_INPUT_RGB565
+#define CM_ARGB1555 DMA2D_INPUT_ARGB1555
+#define CM_ARGB4444 DMA2D_INPUT_ARGB4444
+#define CM_L8 DMA2D_INPUT_L8
+#define CM_AL44 DMA2D_INPUT_AL44
+#define CM_AL88 DMA2D_INPUT_AL88
+#define CM_L4 DMA2D_INPUT_L4
+#define CM_A8 DMA2D_INPUT_A8
+#define CM_A4 DMA2D_INPUT_A4
+/**
+ * @}
+ */
+#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */
+
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
+ || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
+ || defined(STM32H7) || defined(STM32U5)
+/** @defgroup DMA2D_Aliases DMA2D API Aliases
+ * @{
+ */
+#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort
+ for compatibility with legacy code */
+/**
+ * @}
+ */
+
+#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */
+
+/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose
+ * @{
+ */
+
+#if defined(STM32U5)
+#define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr
+#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT
+#endif /* STM32U5 */
+
+/**
+ * @}
+ */
+
+#if !defined(STM32F2)
+/** @defgroup HASH_alias HASH API alias
+ * @{
+ */
+#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */
+/**
+ *
+ * @}
+ */
+#endif /* STM32F2 */
+/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
+#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
+#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
+#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
+#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
+#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
+
+/*HASH Algorithm Selection*/
+
+#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
+#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
+#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
+#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
+
+#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
+#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
+
+#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
+#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
+
+#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
+
+#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
+#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
+#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT
+#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT
+
+#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt
+#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End
+#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT
+#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt
+#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End
+#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT
+#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt
+#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End
+#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
+#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
+
+#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
+#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
+#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
+#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
+#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
+#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
+#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
+ )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
+#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
+#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
+#if defined(STM32L0)
+#else
+#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
+#endif
+#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
+#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
+ )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
+#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
+#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
+#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
+#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
+#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode
+#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
+#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
+#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
+#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
+#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
+#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
+#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
+#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
+#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
+#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
+
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\
+ )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
+
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
+#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
+#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
+#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
+#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
+#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
+#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
+#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
+#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
+#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
+#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
+
+#if defined(STM32F4)
+#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT
+#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT
+#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT
+#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT
+#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA
+#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA
+#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA
+#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA
+#endif /* STM32F4 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
+ * @{
+ */
+
+#if defined(STM32G0)
+#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
+#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
+#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
+#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
+#endif
+#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
+#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
+#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
+#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
+#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
+#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
+#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
+#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
+#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
+#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
+#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
+#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
+#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
+#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
+#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
+#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
+
+#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
+#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
+#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
+#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
+#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
+#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
+#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
+
+#define CR_OFFSET_BB PWR_CR_OFFSET_BB
+#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
+#define PMODE_BIT_NUMBER VOS_BIT_NUMBER
+#define CR_PMODE_BB CR_VOS_BB
+
+#define DBP_BitNumber DBP_BIT_NUMBER
+#define PVDE_BitNumber PVDE_BIT_NUMBER
+#define PMODE_BitNumber PMODE_BIT_NUMBER
+#define EWUP_BitNumber EWUP_BIT_NUMBER
+#define FPDS_BitNumber FPDS_BIT_NUMBER
+#define ODEN_BitNumber ODEN_BIT_NUMBER
+#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
+#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
+#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
+#define BRE_BitNumber BRE_BIT_NUMBER
+
+#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
+#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
+#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
+#define HAL_TIM_DMAError TIM_DMAError
+#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
+#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
+#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
+#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
+#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
+#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
+#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent
+#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT
+#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA
+#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
+/**
+ * @}
+ */
+
+/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
+#define HAL_LTDC_Relaod HAL_LTDC_Reload
+#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig
+#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros ------------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define AES_IT_CC CRYP_IT_CC
+#define AES_IT_ERR CRYP_IT_ERR
+#define AES_FLAG_CCF CRYP_FLAG_CCF
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
+#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
+#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
+#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
+#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
+#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
+#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
+#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
+#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
+#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
+#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
+#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
+#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
+#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
+
+#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
+#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
+#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
+#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
+#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __ADC_ENABLE __HAL_ADC_ENABLE
+#define __ADC_DISABLE __HAL_ADC_DISABLE
+#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
+#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
+#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
+#define __ADC_IS_ENABLED ADC_IS_ENABLE
+#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
+#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
+#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
+#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
+
+#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
+#define __HAL_ADC_JSQR_RK ADC_JSQR_RK
+#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
+#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
+#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
+#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
+#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
+#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
+#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
+#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
+#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
+#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
+#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
+#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
+#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
+#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
+#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
+#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
+
+#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
+#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
+#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
+#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
+#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
+#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
+#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
+
+#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
+#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
+#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
+#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
+#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
+#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
+#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
+#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
+
+#define __HAL_ADC_SQR1 ADC_SQR1
+#define __HAL_ADC_SMPR1 ADC_SMPR1
+#define __HAL_ADC_SMPR2 ADC_SMPR2
+#define __HAL_ADC_SQR3_RK ADC_SQR3_RK
+#define __HAL_ADC_SQR2_RK ADC_SQR2_RK
+#define __HAL_ADC_SQR1_RK ADC_SQR1_RK
+#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
+#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
+#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
+#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
+#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
+#define __HAL_ADC_JSQR ADC_JSQR
+
+#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
+#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
+#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
+#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
+#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
+#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
+#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
+#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
+#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
+#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
+#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
+#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
+#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
+#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
+#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
+#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
+#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
+#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
+#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
+#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
+#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
+#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
+#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
+#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
+#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
+
+#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
+#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
+#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
+#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
+#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
+#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
+#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
+#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
+#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
+#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
+#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
+#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
+#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
+#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
+
+
+#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
+#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
+#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
+#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
+#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
+#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
+#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
+#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
+#if defined(STM32H7)
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
+#else
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
+#endif /* STM32H7 */
+#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
+#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
+#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
+#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
+#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
+#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
+#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
+#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
+#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
+#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
+#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
+#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#if defined(STM32F3)
+#define COMP_START __HAL_COMP_ENABLE
+#define COMP_STOP __HAL_COMP_DISABLE
+#define COMP_LOCK __HAL_COMP_LOCK
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F302xE) || defined(STM32F302xC)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP7_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP7_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP7_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F373xC) ||defined(STM32F378xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+# endif
+#else
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+#endif
+
+#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
+
+#if defined(STM32L0) || defined(STM32L4)
+/* Note: On these STM32 families, the only argument of this macro */
+/* is COMP_FLAG_LOCK. */
+/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
+/* argument. */
+#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
+#endif
+/**
+ * @}
+ */
+
+#if defined(STM32L0) || defined(STM32L4)
+/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
+#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
+/**
+ * @}
+ */
+#endif
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
+ ((WAVE) == DAC_WAVE_NOISE)|| \
+ ((WAVE) == DAC_WAVE_TRIANGLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define IS_WRPAREA IS_OB_WRPAREA
+#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
+#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
+#define IS_TYPEERASE IS_FLASH_TYPEERASE
+#define IS_NBSECTORS IS_FLASH_NBSECTORS
+#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
+#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
+#if defined(STM32F1)
+#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE
+#else
+#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
+#endif /* STM32F1 */
+#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
+#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
+#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
+#define __HAL_I2C_SPEED I2C_SPEED
+#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
+#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
+#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
+#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
+#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
+#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
+#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
+#define __HAL_I2C_FREQRANGE I2C_FREQRANGE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
+#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
+
+#if defined(STM32H7)
+#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __IRDA_DISABLE __HAL_IRDA_DISABLE
+#define __IRDA_ENABLE __HAL_IRDA_ENABLE
+
+#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
+#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
+#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
+#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
+
+#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
+
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
+#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
+#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
+#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
+#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
+#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
+#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
+#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
+#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
+#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
+#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
+#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
+#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
+#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
+#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
+#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
+#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
+#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
+#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
+#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
+#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
+#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
+#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
+#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
+#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
+#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
+
+#if defined (STM32F4)
+#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
+#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
+#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
+#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
+#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
+#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
+#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
+#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
+#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
+#endif /* STM32F4 */
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
+ * @{
+ */
+
+#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
+#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
+
+#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
+#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\
+ )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
+
+#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
+#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
+#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
+#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
+#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
+#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
+#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
+#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
+#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
+#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
+#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
+#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
+#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
+#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
+#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
+#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
+#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
+#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
+#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
+#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
+#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
+#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
+#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
+#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
+#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
+#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
+#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
+#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
+#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
+#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
+#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
+#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
+#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
+#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
+#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
+#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
+#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
+#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
+#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
+#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
+#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
+#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
+#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
+#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
+#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
+#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
+#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
+#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
+#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
+#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
+#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
+#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
+#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
+#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
+#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
+#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
+#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
+#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
+#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
+#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
+#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
+#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
+#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
+#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
+#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
+#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
+#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
+#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
+#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
+#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
+#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
+#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
+#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
+#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
+#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
+#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
+#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
+#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
+#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
+#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
+#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
+#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
+#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
+#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
+#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
+#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
+#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
+#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
+#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
+#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
+#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
+#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
+#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
+#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
+#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
+#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
+#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
+#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
+#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
+#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
+#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
+#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
+#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
+#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
+#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
+#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
+#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
+#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
+#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
+#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
+#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
+#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
+#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
+#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
+#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
+#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
+#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
+#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
+#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
+#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
+#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
+#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
+#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
+#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
+#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
+#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
+#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
+#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
+#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
+#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
+#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
+#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
+#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
+#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
+#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
+#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
+#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
+#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
+#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
+#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
+#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
+#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
+#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
+#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
+#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
+#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
+#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
+#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
+#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
+#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
+#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
+#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
+#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
+#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
+#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
+#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
+#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
+#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
+#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
+#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
+#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
+#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
+#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
+#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
+#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
+#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
+#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
+#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
+#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
+#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
+#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
+#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
+#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
+#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
+#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
+#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
+#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
+#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
+#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
+#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
+#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
+#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
+#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
+#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
+#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
+#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
+#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
+#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
+#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
+#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
+#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
+#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
+#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
+#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
+#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
+#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
+#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
+#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
+#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
+#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
+#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
+#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
+#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
+#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
+#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
+#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
+#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
+#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
+#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
+#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
+#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
+#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
+#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
+#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
+#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
+#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
+#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
+#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
+#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
+#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
+#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
+#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
+#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
+#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
+#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
+#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
+#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
+#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
+#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
+#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
+#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
+#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
+#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
+#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
+#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
+#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
+#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
+#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
+#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
+#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
+#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
+#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
+#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
+#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
+#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
+#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
+#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
+
+#if defined(STM32WB)
+#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE
+#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET
+#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
+#define QSPI_IRQHandler QUADSPI_IRQHandler
+#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
+
+#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
+#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
+#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
+#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
+#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
+#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
+#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
+#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
+#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
+#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
+#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
+#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
+#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
+#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
+#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
+#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
+#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
+#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
+#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
+#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
+#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
+#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
+#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
+#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
+#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
+#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
+#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
+#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
+#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
+#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
+#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
+#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
+#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
+#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
+#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
+#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
+#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
+#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
+#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
+#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
+#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
+#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
+#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
+#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
+#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
+#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
+#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
+#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
+#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
+#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
+#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
+#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
+#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
+#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
+#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
+#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
+#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
+#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
+#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
+#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
+#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
+#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
+#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
+#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
+#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
+#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
+#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
+#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
+#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
+#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
+#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
+#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
+#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
+#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
+#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
+#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
+#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
+#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
+#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
+#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
+#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
+#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
+#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
+#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
+#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
+#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
+#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
+#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
+#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
+#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
+#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
+#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
+#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
+#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
+#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
+#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
+#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
+#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
+#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
+#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
+#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
+#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
+#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
+#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
+#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
+#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
+#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
+#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
+#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
+#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
+#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
+#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
+#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
+#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
+#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
+#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
+#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
+#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
+#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
+#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
+#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
+#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
+#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
+#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
+#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
+#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
+#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
+#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
+#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
+#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
+#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
+#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
+#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
+#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
+#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
+#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
+#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
+#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
+#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
+#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
+#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
+#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
+#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
+#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
+#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
+#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
+#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
+#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
+#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
+#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
+#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
+#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
+#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
+#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
+#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
+#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
+#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
+#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
+#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
+#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
+#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
+#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
+#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
+#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
+#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
+#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
+#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
+#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
+#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
+#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
+#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
+#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
+#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
+#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
+#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
+#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
+#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
+#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
+#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
+#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
+#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
+#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
+#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
+#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
+#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
+#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
+#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
+#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
+#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
+#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
+#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
+#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
+#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
+#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
+#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
+#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
+#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
+#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
+#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
+#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
+#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
+#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
+#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
+#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
+#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
+#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
+#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
+#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
+
+#if defined(STM32H7)
+#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE
+#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE
+#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE
+
+#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/
+#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/
+
+
+#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED
+#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED
+#endif
+
+#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
+#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
+#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
+#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
+#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
+#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
+
+#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
+#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
+#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
+#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
+#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
+#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
+#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
+#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
+#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
+#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
+#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
+#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
+#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
+#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
+#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
+#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
+#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
+#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
+#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
+#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
+
+#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
+#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
+#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
+#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
+#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
+#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
+#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
+#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
+#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
+#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
+#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
+#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
+#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
+#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
+#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
+#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
+#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
+#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
+#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
+#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
+#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
+#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
+#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
+#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
+#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
+#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
+#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
+#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
+#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
+#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
+#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
+#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
+#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
+#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
+#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
+#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
+#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
+#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
+#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
+#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
+#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
+#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
+#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
+#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
+#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
+#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
+#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
+#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
+#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
+#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
+#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
+#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
+#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
+#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
+#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
+#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
+#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
+#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
+#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
+#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
+#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
+#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
+#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
+#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
+#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
+#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
+#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
+#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
+#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
+#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
+#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
+#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
+#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
+#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
+#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
+#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
+#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
+#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
+#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
+#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
+#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
+#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
+#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
+#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
+#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
+#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
+#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
+#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
+#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
+#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
+#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
+#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
+#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
+#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
+#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
+#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
+#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
+#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
+#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
+#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
+#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
+#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
+#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
+#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
+#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
+#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
+#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
+#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
+#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
+#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
+#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
+#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
+#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
+#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
+#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
+#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
+#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
+#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
+#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
+
+/* alias define maintained for legacy */
+#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+
+#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
+#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
+#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
+#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
+#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
+#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
+#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
+#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
+#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
+#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
+#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
+#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
+#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
+#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
+#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
+#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
+#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
+#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
+#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
+#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
+
+#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
+#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
+#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
+#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
+#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
+#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
+#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
+#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
+#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
+#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
+#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
+#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
+#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
+#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
+#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
+#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
+#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
+#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
+#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
+#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
+
+#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
+#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
+#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
+#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
+#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
+#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
+#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
+#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
+#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
+#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
+#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
+#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
+#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
+#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
+#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
+#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
+#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
+#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
+#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
+#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
+#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
+#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
+#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
+#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
+#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
+#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
+#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
+#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
+#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
+#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
+#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
+#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
+#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
+#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
+#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
+#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
+#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
+#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
+#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
+#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
+#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
+#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
+#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
+#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
+#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
+#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
+#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
+#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
+#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
+#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
+#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
+#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
+#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
+#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
+#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
+#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
+#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
+#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
+#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
+#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
+#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
+#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
+#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
+#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
+#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
+#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
+#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
+#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
+#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
+#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
+#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
+#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
+#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
+#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
+#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
+#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
+#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
+#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
+#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
+#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
+#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
+#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
+#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
+#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
+#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
+#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
+#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
+#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
+#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
+#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
+#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
+#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
+#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
+#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
+#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
+#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
+#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
+#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
+#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
+#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
+#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
+#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
+#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
+#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
+#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
+#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
+#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
+#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
+#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
+#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
+#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
+#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
+#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
+#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
+
+#if defined(STM32L1)
+#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
+#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
+#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
+#endif /* STM32L1 */
+
+#if defined(STM32F4)
+#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
+#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED
+#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED
+#define Sdmmc1ClockSelection SdioClockSelection
+#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
+#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
+#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
+#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
+#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
+#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
+#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED
+#define SdioClockSelection Sdmmc1ClockSelection
+#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
+#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
+#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
+#endif
+
+#if defined(STM32F7)
+#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
+#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
+#endif
+
+#if defined(STM32H7)
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
+
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
+#endif
+
+#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
+#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
+
+#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
+
+#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
+#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
+#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
+#define IS_RCC_HCLK_DIV IS_RCC_PCLK
+#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK
+
+#define RCC_IT_HSI14 RCC_IT_HSI14RDY
+
+#define RCC_IT_CSSLSE RCC_IT_LSECSS
+#define RCC_IT_CSSHSE RCC_IT_CSS
+
+#define RCC_PLLMUL_3 RCC_PLL_MUL3
+#define RCC_PLLMUL_4 RCC_PLL_MUL4
+#define RCC_PLLMUL_6 RCC_PLL_MUL6
+#define RCC_PLLMUL_8 RCC_PLL_MUL8
+#define RCC_PLLMUL_12 RCC_PLL_MUL12
+#define RCC_PLLMUL_16 RCC_PLL_MUL16
+#define RCC_PLLMUL_24 RCC_PLL_MUL24
+#define RCC_PLLMUL_32 RCC_PLL_MUL32
+#define RCC_PLLMUL_48 RCC_PLL_MUL48
+
+#define RCC_PLLDIV_2 RCC_PLL_DIV2
+#define RCC_PLLDIV_3 RCC_PLL_DIV3
+#define RCC_PLLDIV_4 RCC_PLL_DIV4
+
+#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
+#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
+#define RCC_MCO_NODIV RCC_MCODIV_1
+#define RCC_MCO_DIV1 RCC_MCODIV_1
+#define RCC_MCO_DIV2 RCC_MCODIV_2
+#define RCC_MCO_DIV4 RCC_MCODIV_4
+#define RCC_MCO_DIV8 RCC_MCODIV_8
+#define RCC_MCO_DIV16 RCC_MCODIV_16
+#define RCC_MCO_DIV32 RCC_MCODIV_32
+#define RCC_MCO_DIV64 RCC_MCODIV_64
+#define RCC_MCO_DIV128 RCC_MCODIV_128
+#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
+#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
+#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
+#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
+#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
+#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
+#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
+#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
+#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
+
+#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
+#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
+#else
+#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
+#endif
+
+#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
+#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
+#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
+#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
+#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
+#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
+
+#define HSION_BitNumber RCC_HSION_BIT_NUMBER
+#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
+#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
+#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
+#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
+#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
+#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
+#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
+#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
+#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
+#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
+#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
+#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
+#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
+#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
+#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
+#define LSION_BitNumber RCC_LSION_BIT_NUMBER
+#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
+#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
+#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
+#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
+#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
+#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
+#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
+#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
+#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
+#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
+#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
+#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
+#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
+#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
+#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
+
+#define CR_HSION_BB RCC_CR_HSION_BB
+#define CR_CSSON_BB RCC_CR_CSSON_BB
+#define CR_PLLON_BB RCC_CR_PLLON_BB
+#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
+#define CR_MSION_BB RCC_CR_MSION_BB
+#define CSR_LSION_BB RCC_CSR_LSION_BB
+#define CSR_LSEON_BB RCC_CSR_LSEON_BB
+#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
+#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
+#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
+#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
+#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
+#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
+#define CR_HSEON_BB RCC_CR_HSEON_BB
+#define CSR_RMVF_BB RCC_CSR_RMVF_BB
+#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
+#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
+
+#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
+#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
+#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
+#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
+#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
+
+#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
+
+#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
+#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
+
+#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
+#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
+#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
+#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
+#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
+#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
+
+#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
+#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
+#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
+#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
+#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
+#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
+#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
+#define DfsdmClockSelection Dfsdm1ClockSelection
+#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
+#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
+#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
+#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
+#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
+#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
+#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
+
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
+#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
+#if defined(STM32U5)
+#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
+#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
+#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE
+#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE
+#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE
+#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE
+#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE
+#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE
+#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE
+#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE
+#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE
+#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5)
+#else
+#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
+#endif
+#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
+#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
+
+#if defined (STM32F1)
+#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
+
+#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
+
+#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
+
+#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
+
+#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
+#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
+#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
+#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
+#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
+#endif /* STM32F1 */
+
+#define IS_ALARM IS_RTC_ALARM
+#define IS_ALARM_MASK IS_RTC_ALARM_MASK
+#define IS_TAMPER IS_RTC_TAMPER
+#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
+#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
+#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
+#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
+#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
+#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
+#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
+#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
+#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
+#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
+#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
+
+#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
+#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
+#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
+
+#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
+#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE
+#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE
+
+#define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV
+#define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV
+
+#if defined(STM32F4) || defined(STM32F2)
+#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
+#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
+#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
+#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
+#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
+#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
+#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
+#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
+#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
+#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
+#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
+#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
+#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
+#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
+#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
+#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
+#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
+#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
+#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
+#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
+/* alias CMSIS */
+#define SDMMC1_IRQn SDIO_IRQn
+#define SDMMC1_IRQHandler SDIO_IRQHandler
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define SD_SDIO_DISABLED SD_SDMMC_DISABLED
+#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
+#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
+#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
+#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
+#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
+#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
+#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
+#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
+#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
+#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
+#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
+#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
+#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
+#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
+#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
+#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
+#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
+#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
+#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
+/* alias CMSIS for compatibilities */
+#define SDIO_IRQn SDMMC1_IRQn
+#define SDIO_IRQHandler SDMMC1_IRQHandler
+#endif
+
+#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)
+#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
+#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
+#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
+#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
+#endif
+
+#if defined(STM32H7) || defined(STM32L5)
+#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
+#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
+#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
+#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback
+#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback
+#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback
+#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback
+#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback
+#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
+#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
+#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
+#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
+#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
+#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
+
+#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
+#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
+
+#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
+#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
+#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
+#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
+#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
+#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
+#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
+#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_SPI_1LINE_TX SPI_1LINE_TX
+#define __HAL_SPI_1LINE_RX SPI_1LINE_RX
+#define __HAL_SPI_RESET_CRC SPI_RESET_CRC
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
+#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
+#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
+#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
+
+#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
+
+#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
+#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
+#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
+#define __USART_ENABLE __HAL_USART_ENABLE
+#define __USART_DISABLE __HAL_USART_DISABLE
+
+#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
+#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
+
+#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7)
+#define USART_OVERSAMPLING_16 0x00000000U
+#define USART_OVERSAMPLING_8 USART_CR1_OVER8
+
+#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
+ ((__SAMPLING__) == USART_OVERSAMPLING_8))
+#endif /* STM32F0 || STM32F3 || STM32F7 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
+
+#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
+#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
+
+#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
+#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
+
+#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+
+#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
+#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
+
+#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
+#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
+#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
+
+#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
+#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
+
+#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
+
+#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
+#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
+#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
+#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
+#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
+#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
+#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
+#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
+#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
+#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
+#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
+#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
+
+#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
+#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
+
+#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
+#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
+#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_LTDC_LAYER LTDC_LAYER
+#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
+#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
+#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
+#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
+#define SAI_STREOMODE SAI_STEREOMODE
+#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
+#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
+#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
+#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
+#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
+#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
+#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
+#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1
+#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#if defined(STM32H7)
+#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow
+#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT
+#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
+#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
+#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
+#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
+#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
+#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
+#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
+#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
+#endif /* STM32L4 || STM32F4 || STM32F7 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32_HAL_LEGACY */
+
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32_assert_template.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32_assert_template.h
new file mode 100644
index 00000000..54042785
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32_assert_template.h
@@ -0,0 +1,54 @@
+/**
+ ******************************************************************************
+ * @file stm32_assert.h
+ * @author MCD Application Team
+ * @brief STM32 assert template file.
+ * This file should be copied to the application folder and renamed
+ * to stm32_assert.h.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_H
+#define __STM32_ASSERT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t *file, uint32_t line);
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_H */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal.h
new file mode 100644
index 00000000..0c0fb8fb
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal.h
@@ -0,0 +1,691 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal.h
+ * @author MCD Application Team
+ * @brief This file contains all the functions prototypes for the HAL
+ * module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32U5xx_HAL_H
+#define __STM32U5xx_HAL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_conf.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup HAL
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup HAL_Exported_Types HAL Exported Types
+ * @{
+ */
+
+/** @defgroup HAL_TICK_FREQ Tick Frequency
+ * @{
+ */
+typedef enum
+{
+ HAL_TICK_FREQ_10HZ = 100U,
+ HAL_TICK_FREQ_100HZ = 10U,
+ HAL_TICK_FREQ_1KHZ = 1U,
+ HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
+} HAL_TickFreqTypeDef;
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported variables --------------------------------------------------------*/
+/** @defgroup HAL_Exported_Variables HAL Exported Variables
+ * @{
+ */
+extern __IO uint32_t uwTick;
+extern uint32_t uwTickPrio;
+extern HAL_TickFreqTypeDef uwTickFreq;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup REV_ID device revision ID
+ * @{
+ */
+#define REV_ID_A 0x1000U /*!< STM32U5 rev.A */
+#define REV_ID_B 0x2000U /*!< STM32U5 rev.B */
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
+ * @{
+ */
+
+/** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts
+ * @{
+ */
+#define SYSCFG_IT_FPU_IOC SYSCFG_FPUIMR_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */
+#define SYSCFG_IT_FPU_DZC SYSCFG_FPUIMR_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */
+#define SYSCFG_IT_FPU_UFC SYSCFG_FPUIMR_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */
+#define SYSCFG_IT_FPU_OFC SYSCFG_FPUIMR_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */
+#define SYSCFG_IT_FPU_IDC SYSCFG_FPUIMR_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */
+#define SYSCFG_IT_FPU_IXC SYSCFG_FPUIMR_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
+ * @{
+ */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREF_OUT2) */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 2 (VREF_OUT3) */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 (VREFBUF_CSR_VRS_0 | VREFBUF_CSR_VRS_1) /*!< Voltage reference scale 3 (VREF_OUT4) */
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
+ * @{
+ */
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to
+ Voltage reference buffer output */
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_flags_definition Flags
+ * @{
+ */
+
+#define SYSCFG_FLAG_SRAM2_PE SYSCFG_CFGR2_SPF /*!< SRAM2 parity error */
+#define SYSCFG_FLAG_SRAM2_BUSY SYSCFG_SCSR_SRAM2BSY /*!< SRAM2 busy by erase operation */
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
+ * @{
+ */
+
+/** @brief Fast-mode Plus driving capability on a specific GPIO
+ */
+#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */
+#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */
+#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */
+#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_Lock_items SYSCFG Lock items
+ * @brief SYSCFG items to set lock on
+ * @{
+ */
+#define SYSCFG_MPU_NSEC SYSCFG_CNSLCKR_LOCKNSMPU /*!< Non-secure MPU lock (privileged secure or non-secure only) */
+#define SYSCFG_VTOR_NSEC SYSCFG_CNSLCKR_LOCKNSVTOR /*!< Non-secure VTOR lock (privileged secure or non-secure only) */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SYSCFG_SAU (SYSCFG_CSLCKR_LOCKSAU << 16U) /*!< SAU lock (privileged secure code only) */
+#define SYSCFG_MPU_SEC (SYSCFG_CSLCKR_LOCKSMPU << 16U) /*!< Secure MPU lock (privileged secure code only) */
+#define SYSCFG_VTOR_AIRCR_SEC (SYSCFG_CSLCKR_LOCKSVTAIRCR << 16U) /*!< VTOR_S and AIRCR lock (privileged secure code only) */
+#define SYSCFG_LOCK_ALL (SYSCFG_MPU_NSEC|SYSCFG_VTOR_NSEC|SYSCFG_SAU|SYSCFG_MPU_SEC|SYSCFG_VTOR_AIRCR_SEC) /*!< All */
+#else
+#define SYSCFG_LOCK_ALL (SYSCFG_MPU_NSEC|SYSCFG_VTOR_NSEC) /*!< All (privileged secure or non-secure only) */
+#endif /* __ARM_FEATURE_CMSE */
+/**
+ * @}
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/** @defgroup SYSCFG_Attributes_items SYSCFG Attributes items
+ * @brief SYSCFG items to configure secure or non-secure attributes on
+ * @{
+ */
+#define SYSCFG_CLK SYSCFG_SECCFGR_SYSCFGSEC /*!< SYSCFG clock control */
+#define SYSCFG_CLASSB SYSCFG_SECCFGR_CLASSBSEC /*!< Class B */
+#define SYSCFG_FPU SYSCFG_SECCFGR_FPUSEC /*!< FPU */
+#define SYSCFG_ALL (SYSCFG_CLK | SYSCFG_CLASSB | SYSCFG_FPU) /*!< All */
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_attributes SYSCFG attributes
+ * @brief SYSCFG secure or non-secure attributes
+ * @{
+ */
+#define SYSCFG_SEC 0x00000001U /*!< Secure attribute */
+#define SYSCFG_NSEC 0x00000000U /*!< Non-secure attribute */
+/**
+ * @}
+ */
+
+#endif /* __ARM_FEATURE_CMSE */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros
+ * @{
+ */
+
+/** @brief Freeze/Unfreeze Peripherals in Debug mode
+ */
+#if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_TIM2_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_TIM3_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_TIM4_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_TIM5_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_TIM6_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_TIM7_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP)
+#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
+#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_WWDG_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP)
+#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
+#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_IWDG_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_I2C1_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_I2C2_STOP */
+
+#if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C4() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C4() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
+#endif /* DBGMCU_APB1FZR2_DBG_I2C4_STOP */
+
+#if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
+#define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
+#endif /* DBGMCU_APB1FZR2_DBG_LPTIM2_STOP */
+
+#if defined(DBGMCU_APB1FZR2_DBG_FDCAN_STOP)
+#define __HAL_DBGMCU_FREEZE_FDCAN() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_FDCAN_STOP)
+#define __HAL_DBGMCU_UNFREEZE_FDCAN() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_FDCAN_STOP)
+#endif /* DBGMCU_APB1FZR2_DBG_FDCAN_STOP */
+
+#if defined(DBGMCU_APB2FZR_DBG_TIM1_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP)
+#endif /* DBGMCU_APB2FZR_DBG_TIM1_STOP */
+
+#if defined(DBGMCU_APB2FZR_DBG_TIM8_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM8_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM8_STOP)
+#endif /* DBGMCU_APB2FZR_DBG_TIM8_STOP */
+
+#if defined(DBGMCU_APB2FZR_DBG_TIM15_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM15_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM15_STOP)
+#endif /* DBGMCU_APB2FZR_DBG_TIM15_STOP */
+
+#if defined(DBGMCU_APB2FZR_DBG_TIM16_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM16_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM16_STOP)
+#endif /* DBGMCU_APB2FZR_DBG_TIM16_STOP */
+
+#if defined(DBGMCU_APB2FZR_DBG_TIM17_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM17_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM17_STOP)
+#endif /* DBGMCU_APB2FZR_DBG_TIM17_STOP */
+
+#if defined(DBGMCU_APB3FZR_DBG_I2C3_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C3() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C3_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C3() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C3_STOP)
+#endif /* DBGMCU_APB3FZR_DBG_I2C3_STOP */
+
+#if defined(DBGMCU_APB3FZR_DBG_LPTIM1_STOP)
+#define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM1_STOP)
+#endif /* DBGMCU_APB3FZR_DBG_LPTIM1_STOP */
+
+#if defined(DBGMCU_APB3FZR_DBG_LPTIM3_STOP)
+#define __HAL_DBGMCU_FREEZE_LPTIM3() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM3_STOP)
+#define __HAL_DBGMCU_UNFREEZE_LPTIM3() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM3_STOP)
+#endif /* DBGMCU_APB3FZR_DBG_LPTIM3_STOP */
+
+#if defined(DBGMCU_APB3FZR_DBG_LPTIM4_STOP)
+#define __HAL_DBGMCU_FREEZE_LPTIM4() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM4_STOP)
+#define __HAL_DBGMCU_UNFREEZE_LPTIM4() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM4_STOP)
+#endif /* DBGMCU_APB3FZR_DBG_LPTIM4_STOP */
+
+#if defined(DBGMCU_APB3FZR_DBG_RTC_STOP)
+#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_RTC_STOP)
+#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_RTC_STOP)
+#endif /* DBGMCU_APB3FZR_DBG_RTC_STOP */
+
+#if defined(DBGMCU_AHB1FZR_DBG_GPDMA0_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA0() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA0_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA0() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA0_STOP)
+#endif /* DBGMCU_AHB1FZR_DBG_GPDMA0_STOP */
+
+#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA1() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA1() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_STOP)
+#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_STOP */
+
+#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA2() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA2() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_STOP)
+#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_STOP */
+
+#if defined(DBGMCU_AHB1FZR_DBG_GPDMA3_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA3() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA3_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA3() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA3_STOP)
+#endif /* DBGMCU_AHB1FZR_DBG_GPDMA3_STOP */
+
+#if defined(DBGMCU_AHB1FZR_DBG_GPDMA4_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA4() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA4_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA4() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA4_STOP)
+#endif /* DBGMCU_AHB1FZR_DBG_GPDMA4_STOP */
+
+#if defined(DBGMCU_AHB1FZR_DBG_GPDMA5_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA5() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA5_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA5() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA5_STOP)
+#endif /* DBGMCU_AHB1FZR_DBG_GPDMA5_STOP */
+
+#if defined(DBGMCU_AHB1FZR_DBG_GPDMA6_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA6() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA6_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA6() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA6_STOP)
+#endif /* DBGMCU_AHB1FZR_DBG_GPDMA6_STOP */
+
+#if defined(DBGMCU_AHB1FZR_DBG_GPDMA7_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA7() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA7_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA7() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA7_STOP)
+#endif /* DBGMCU_AHB1FZR_DBG_GPDMA7_STOP */
+
+#if defined(DBGMCU_AHB1FZR_DBG_GPDMA8_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA8() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA8_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA8() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA8_STOP)
+#endif /* DBGMCU_AHB1FZR_DBG_GPDMA8_STOP */
+
+#if defined(DBGMCU_AHB1FZR_DBG_GPDMA9_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA9() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA9_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA9() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA9_STOP)
+#endif /* DBGMCU_AHB1FZR_DBG_GPDMA9_STOP */
+
+#if defined(DBGMCU_AHB1FZR_DBG_GPDMA10_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA10() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA10_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA10() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA10_STOP)
+#endif /* DBGMCU_AHB1FZR_DBG_GPDMA10_STOP */
+
+#if defined(DBGMCU_AHB1FZR_DBG_GPDMA11_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA11() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA11_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA11() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA11_STOP)
+#endif /* DBGMCU_AHB1FZR_DBG_GPDMA11_STOP */
+
+#if defined(DBGMCU_AHB1FZR_DBG_GPDMA12_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA12() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA12_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA12() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA12_STOP)
+#endif /* DBGMCU_AHB1FZR_DBG_GPDMA12_STOP */
+
+#if defined(DBGMCU_AHB1FZR_DBG_GPDMA13_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA13() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA13_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA13() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA13_STOP)
+#endif /* DBGMCU_AHB1FZR_DBG_GPDMA13_STOP */
+
+#if defined(DBGMCU_AHB1FZR_DBG_GPDMA14_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA14() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA14_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA14() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA14_STOP)
+#endif /* DBGMCU_AHB1FZR_DBG_GPDMA14_STOP */
+
+#if defined(DBGMCU_AHB1FZR_DBG_GPDMA15_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA15() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA15_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA15() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA15_STOP)
+#endif /* DBGMCU_AHB1FZR_DBG_GPDMA15_STOP */
+
+#if defined(DBGMCU_AHB3FZR_DBG_LPDMA0_STOP)
+#define __HAL_DBGMCU_FREEZE_LPDMA0() SET_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA0_STOP)
+#define __HAL_DBGMCU_UNFREEZE_LPDMA0() CLEAR_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA0_STOP)
+#endif /* DBGMCU_AHB3FZR_DBG_LPDMA0_STOP */
+
+#if defined(DBGMCU_AHB3FZR_DBG_LPDMA1_STOP)
+#define __HAL_DBGMCU_FREEZE_LPDMA1() SET_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_LPDMA1() CLEAR_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA1_STOP)
+#endif /* DBGMCU_AHB3FZR_DBG_LPDMA1_STOP */
+
+#if defined(DBGMCU_AHB3FZR_DBG_LPDMA2_STOP)
+#define __HAL_DBGMCU_FREEZE_LPDMA2() SET_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_LPDMA2() CLEAR_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA2_STOP)
+#endif /* DBGMCU_AHB3FZR_DBG_LPDMA2_STOP */
+
+#if defined(DBGMCU_AHB3FZR_DBG_LPDMA3_STOP)
+#define __HAL_DBGMCU_FREEZE_LPDMA3() SET_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA3_STOP)
+#define __HAL_DBGMCU_UNFREEZE_LPDMA3() CLEAR_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA3_STOP)
+#endif /* DBGMCU_AHB3FZR_DBG_LPDMA3_STOP */
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
+ * @{
+ */
+
+/** @brief Floating Point Unit interrupt enable/disable macros
+ * @param __INTERRUPT__: This parameter can be a value of @ref SYSCFG_FPU_Interrupts
+ */
+#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
+ SET_BIT(SYSCFG->FPUIMR, (__INTERRUPT__));\
+ }while(0)
+
+#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
+ CLEAR_BIT(SYSCFG->FPUIMR, (__INTERRUPT__));\
+ }while(0)
+
+/** @brief SYSCFG Break ECC lock.
+ * Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input.
+ * @note The selected configuration is locked and can be unlocked only by system reset.
+ */
+#define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
+
+/** @brief SYSCFG Break Cortex-M33 Lockup lock.
+ * Enable and lock the connection of Cortex-M33 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input.
+ * @note The selected configuration is locked and can be unlocked only by system reset.
+ */
+#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
+
+/** @brief SYSCFG Break PVD lock.
+ * Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in
+ * the PWR_CR2 register.
+ * @note The selected configuration is locked and can be unlocked only by system reset.
+ */
+#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
+
+/** @brief SYSCFG Break SRAM2 parity lock.
+ * Enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break input.
+ * @note The selected configuration is locked and can be unlocked by system reset.
+ */
+#define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL)
+
+/** @brief Check SYSCFG flag is set or not.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref SYSCFG_FLAG_SRAM2_PE SRAM2 Parity Error Flag
+ * @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2)\
+ & (__FLAG__))!= 0) ? 1 : 0)
+
+/** @brief Set the SPF bit to clear the SRAM Parity Error Flag.
+ */
+#define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
+
+/** @brief Fast-mode Plus driving capability enable/disable macros
+ * @param __FASTMODEPLUS__: This parameter can be a value of :
+ * @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6
+ * @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7
+ * @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8
+ * @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9
+ */
+#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) \
+ do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
+ SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
+ }while(0)
+
+#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) \
+ do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
+ CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
+ }while(0)
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros
+ * @{
+ */
+
+#define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \
+ (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \
+ (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \
+ (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \
+ (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \
+ (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC))
+
+#define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \
+ ((__CONFIG__) == SYSCFG_BREAK_PVD) || \
+ ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY) || \
+ ((__CONFIG__) == SYSCFG_BREAK_LOCKUP))
+
+#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
+ ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \
+ ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2) || \
+ ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE3))
+
+#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
+ ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
+
+#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
+
+#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
+ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
+ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
+ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+#define IS_SYSCFG_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == SYSCFG_SEC) ||\
+ ((__ATTRIBUTES__) == SYSCFG_NSEC))
+
+#define IS_SYSCFG_ITEMS_ATTRIBUTES(__ITEM__) ((((__ITEM__) & SYSCFG_CLK) == SYSCFG_CLK) || \
+ (((__ITEM__) & SYSCFG_CLASSB) == SYSCFG_CLASSB) || \
+ (((__ITEM__) & SYSCFG_FPU) == SYSCFG_FPU) || \
+ (((__ITEM__) & ~(SYSCFG_ALL)) == 0U))
+
+#define IS_SYSCFG_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SYSCFG_MPU_NSEC) == SYSCFG_MPU_NSEC) || \
+ (((__ITEM__) & SYSCFG_VTOR_NSEC) == SYSCFG_VTOR_NSEC) || \
+ (((__ITEM__) & SYSCFG_SAU) == SYSCFG_SAU) || \
+ (((__ITEM__) & SYSCFG_MPU_SEC) == SYSCFG_MPU_SEC) || \
+ (((__ITEM__) & SYSCFG_VTOR_AIRCR_SEC) == SYSCFG_VTOR_AIRCR_SEC) || \
+ (((__ITEM__) & ~(SYSCFG_LOCK_ALL)) == 0U))
+
+#else
+
+#define IS_SYSCFG_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SYSCFG_MPU_NSEC) == SYSCFG_MPU_NSEC) || \
+ (((__ITEM__) & SYSCFG_VTOR_NSEC) == SYSCFG_VTOR_NSEC) || \
+ (((__ITEM__) & ~(SYSCFG_LOCK_ALL)) == 0U))
+
+
+#endif /* __ARM_FEATURE_CMSE */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Private_Macros HAL Private Macros
+ * @{
+ */
+#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
+ ((FREQ) == HAL_TICK_FREQ_100HZ) || \
+ ((FREQ) == HAL_TICK_FREQ_1KHZ))
+/**
+ * @}
+ */
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup HAL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup HAL_Exported_Functions_Group1
+ * @{
+ */
+
+/* Initialization and de-initialization functions ******************************/
+HAL_StatusTypeDef HAL_Init(void);
+HAL_StatusTypeDef HAL_DeInit(void);
+void HAL_MspInit(void);
+void HAL_MspDeInit(void);
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HAL_Exported_Functions_Group2
+ * @{
+ */
+
+/* Peripheral Control functions ************************************************/
+void HAL_IncTick(void);
+void HAL_Delay(uint32_t Delay);
+uint32_t HAL_GetTick(void);
+uint32_t HAL_GetTickPrio(void);
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
+HAL_TickFreqTypeDef HAL_GetTickFreq(void);
+void HAL_SuspendTick(void);
+void HAL_ResumeTick(void);
+uint32_t HAL_GetHalVersion(void);
+uint32_t HAL_GetREVID(void);
+uint32_t HAL_GetDEVID(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HAL_Exported_Functions_Group3
+ * @{
+ */
+
+/* DBGMCU Peripheral Control functions *****************************************/
+void HAL_DBGMCU_EnableDBGStopMode(void);
+void HAL_DBGMCU_DisableDBGStopMode(void);
+void HAL_DBGMCU_EnableDBGStandbyMode(void);
+void HAL_DBGMCU_DisableDBGStandbyMode(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HAL_Exported_Functions_Group4
+ * @{
+ */
+
+/* SYSCFG Control functions ****************************************************/
+void HAL_SYSCFG_SRAM2Erase(void);
+
+void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
+void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
+void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
+HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
+void HAL_SYSCFG_DisableVREFBUF(void);
+
+void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void);
+void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HAL_Exported_Functions_Group5
+ * @{
+ */
+
+/* SYSCFG Lock functions ********************************************/
+void HAL_SYSCFG_Lock(uint32_t Item);
+HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem);
+
+/**
+ * @}
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/** @addtogroup HAL_Exported_Functions_Group6
+ * @{
+ */
+
+/* SYSCFG Attributes functions ********************************************/
+void HAL_SYSCFG_ConfigAttributes(uint32_t Item, uint32_t Attributes);
+HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes);
+
+/**
+ * @}
+ */
+
+#endif /* __ARM_FEATURE_CMSE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32U5xx_HAL_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_adc.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_adc.h
new file mode 100644
index 00000000..ca3e6f2e
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_adc.h
@@ -0,0 +1,2393 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_adc.h
+ * @author MCD Application Team
+ * @brief Header file of ADC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_ADC_H
+#define STM32U5xx_HAL_ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/* Include low level driver */
+#include "stm32u5xx_ll_adc.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup ADC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ADC_Exported_Types ADC Exported Types
+ * @{
+ */
+
+/**
+ * @brief ADC group regular oversampling structure definition
+ */
+typedef struct
+{
+ uint32_t Ratio; /*!< Configures the oversampling ratio.
+ This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
+
+ uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
+ This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
+
+ uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode.
+ This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */
+
+ uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode.
+ The oversampling is either temporary stopped or reset upon an injected
+ sequence interruption.
+ If oversampling is enabled on both regular and injected groups,
+ this parameter is discarded and forced to setting
+ "ADC_REGOVERSAMPLING_RESUMED_MODE"
+ (the oversampling buffer is zeroed during injection sequence).
+ This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG
+ Note: This parameter is not applicable for ADC4 */
+
+} ADC_OversamplingTypeDef;
+
+/**
+ * @brief Structure definition of ADC instance and ADC group regular.
+ * @note Parameters of this structure are shared within 2 scopes:
+ * - Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign,
+ * ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff.
+ * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode,
+ * NbrOfDiscConversion, ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun,
+ * OversamplingMode, Oversampling, ConversionDataManagement.
+ * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state.
+ * ADC state can be either:
+ * - For all parameters: ADC disabled
+ * - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling':
+ * ADC enabled without conversion on going on group regular.
+ * - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going
+ * on groups regular and injected.
+ * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+ * without error reporting (as it can be the expected behavior in case of intended action to update another
+ * parameter (which fulfills the ADC state condition) on the fly).
+ */
+typedef struct
+{
+ uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous
+ clock derived from system clock or PLL (Refer to reference manual for list of
+ clocks available)) and clock prescaler.
+ This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE.
+ Note: The ADC clock configuration is common to all ADC instances.
+ Note: In case of usage of channels on injected group, ADC frequency should be
+ lower than AHB clock frequency /4 for resolution 12 or 10 bits, AHB clock
+ frequency /3 for resolution 8 bits, AHB clock frequency /2 for
+ resolution 6 bits.
+ Note: In case of synchronous clock mode based on HCLK/1, the configuration must
+ be enabled only if the system clock has a 50% duty clock cycle
+ (APB prescaler configured inside RCC must be bypassed and PCLK clock must
+ have 50% duty cycle).
+ Refer to reference manual for details.
+ Note: In case of usage of asynchronous clock, the selected clock must be
+ preliminarily enabled at RCC top level.
+ Note: This parameter can be modified only if all ADC instances are disabled. */
+
+ uint32_t Resolution; /*!< Configure the ADC resolution.
+ This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */
+
+ uint32_t GainCompensation; /*!< Specify the ADC gain compensation coefficient to be applied to ADC raw
+ conversion data, based on following formula:
+ DATA = DATA(raw) * (gain compensation coef) / 4095
+ 14 bit format, unsigned: 2 bits exponents / 14 bits mantissa
+ Gain step is 1/4095 = 0.000244
+ Gain range is 0.0000 to 3.999756
+ This parameter value can be
+ 0 Gain compensation will be disabled and coefficient set to 0
+ 1 -> 0x3FFF Gain compensation will be enabled and coefficient set to
+ specified value */
+
+ uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected.
+ This parameter can be associated to parameter 'DiscontinuousConvMode'
+ to have main sequence subdivided in successive parts.
+ For ADC1 or ADC2 instances, this parameter could be enabled or disabled.
+ If disabled: Conversion is performed in single mode (one channel converted,
+ the one defined in rank 1).
+ Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion'
+ are discarded (equivalent to set to 1).
+ If enabled: Conversions are performed in sequence mode (multiple ranks defined
+ by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of
+ each channel in sequencer).
+ Scan direction is upward: from rank 1 to rank 'n'.
+ For ADC4 instance, this parameter could be "fully configurable" or
+ "not fully configurable":
+ - sequencer configured to fully configurable:
+ sequencer length and each rank affectation to a channel are configurable.
+ - Sequence length: Set number of ranks in the scan sequence.
+ - Sequence direction: Unless specified in parameters, sequencer
+ scan direction is forward (from rank 1 to rank n).
+ - sequencer configured to not fully configurable:
+ sequencer length and each rank affectation to a channel are fixed by
+ channel HW number.
+ - Sequence length: Number of ranks in the scan sequence is
+ defined by number of channels set in the sequence,
+ rank of each channel is fixed by channel HW number.
+ (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+ - Sequence direction: Unless specified in parameters, sequencer
+ scan direction is forward (from lowest channel number to
+ highest channel number).
+ This parameter can be a value of @ref ADC_Scan_mode */
+
+ uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left).
+ Refer to reference manual for alignments formats versus resolutions.
+ This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */
+
+ uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and
+ interruption: end of unitary conversion or end of sequence conversions.
+ This parameter can be a value of @ref ADC_EOCSelection. */
+
+ FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when
+ the previous conversion (for ADC group regular) or previous sequence
+ (for ADC group injected) has been retrieved by user software, using function
+ HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue().
+ This feature automatically adapts the frequency of ADC conversions triggers to
+ the speed of the system that reads the data. Moreover, this avoids risk
+ of overrun for low frequency applications.
+ This parameter can be set to ENABLE or DISABLE.
+ Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(),
+ HAL_ADC_Start_DMA()) since these modes have to clear immediately
+ the EOC flag (by CPU to free the IRQ pending event or by DMA).
+ Auto wait will work but fort a very short time, discarding its intended
+ benefit (except specific case of high load of CPU or DMA transfers
+ which can justify usage of auto wait).
+ Do use with polling: 1. Start conversion with HAL_ADC_Start(),
+ 2. Later on, when ADC conversion data is needed:
+ use HAL_ADC_GetValue() to retrieve conversion result and trig another
+ conversion start.
+ (in case of usage of ADC group injected, use the equivalent functions
+ HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */
+
+ uint32_t LowPowerAutoPowerOff; /*!< Select the auto-off low power mode: the ADC automatically powers-off after
+ a conversion and automatically wakes-up when a new conversion is triggered.
+ This feature can be combined with automatic wait mode ('LowPowerAutoWait').
+ This parameter can be value of @ref ADC_HAL_LowPower_DPD.
+ Note: If activated, this feature also turns off the ADC dedicated 16 MHz
+ RC oscillator (HSI16).
+ Note: This parameter can be used for ADC4 only. */
+
+ FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion)
+ or continuous mode for ADC group regular, after the first ADC conversion start
+ trigger occurred (software start or external trigger).
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group
+ sequencer.
+ This parameter is dependent on ADC instance.
+ If ADC1 or ADC2 instances:
+ To use the regular group sequencer and convert several ranks,
+ parameter 'ScanConvMode' must be enabled.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 16.
+ If ADC4 instance:
+ This parameter is dependent on ScanConvMode:
+ - sequencer configured to fully configurable:
+ Number of ranks in the scan sequence is configurable using this parameter.
+ Note: After the first call of 'HAL_ADC_Init()', each rank corresponding
+ to parameter "NbrOfConversion" must be set using 'HAL_ADC_ConfigChannel()'.
+ Afterwards, when all needed sequencer ranks are set, parameter
+ 'NbrOfConversion' can be updated without modifying configuration of
+ sequencer ranks (sequencer ranks above 'NbrOfConversion' are discarded).
+ - sequencer configured to not fully configurable:
+ Number of ranks in the scan sequence is defined by number of channels set in
+ the sequence. This parameter is discarded.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 8.
+ Note: This parameter must be modified when no conversion is on going on
+ regular group (ADC disabled, or ADC enabled without continuous mode
+ or external trigger that could launch a conversion). */
+
+ FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is
+ performed in Complete-sequence/Discontinuous-sequence
+ (main sequence subdivided in successive parts).
+ Discontinuous mode is used only if sequencer is enabled
+ (parameter 'ScanConvMode'). If sequencer is disabled, this parameter
+ is discarded.
+ Discontinuous mode can be enabled only if continuous mode is disabled.
+ If continuous mode is enabled, this parameter setting is discarded.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence
+ of ADC group regular (parameter NbrOfConversion) will be subdivided.
+ If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
+
+ uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular
+ conversion start.
+ If set to ADC_SOFTWARE_START, external triggers are disabled and software
+ trigger is used instead.
+ This parameter can be a value of @ref ADC_regular_external_trigger_source.
+ Caution: external trigger source is common to all ADC instances. */
+
+ uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular
+ conversion start.
+ If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.
+ This parameter can be a value of @ref ADC_regular_external_trigger_edge */
+
+ uint32_t ConversionDataManagement; /*!< Specifies whether the Data conversion data is managed: using the DMA
+ (oneshot or circular), or stored in the DR register or
+ transferred to MDF register.
+ Note: In continuous mode, DMA must be configured in circular mode.
+ Otherwise an overrun will be triggered when DMA buffer maximum pointer
+ is reached.
+ This parameter can be a value of @ref ADC_ConversionDataManagement.
+ Note: This parameter must be modified when no conversion is on going on both
+ regular and injected groups (ADC disabled, or ADC enabled without
+ continuous mode or external trigger that could launch a conversion). */
+
+ FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode
+ (DMA transfer stops when number of conversions is reached) or in
+ continuous mode (DMA transfer unlimited, whatever number of conversions).
+ This parameter can be set to ENABLE or DISABLE.
+ Note: In continuous mode, DMA must be configured in circular mode.
+ Otherwise an overrun will be triggered when DMA buffer maximum
+ pointer is reached. */
+
+ uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default).
+ This parameter applies to ADC group regular only.
+ This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR.
+ Note: In case of overrun set to data preserved and usage with programming model
+ with interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of
+ conversion flags, this induces the release of the preserved data.
+ If needed, this data can be saved in function HAL_ADC_ConvCpltCallback(),
+ placed in user program code (called before end of conversion flags clear).
+ Note: Error reporting with respect to the conversion mode:
+ - Usage with ADC conversion by polling for event or interruption:
+ Error is reported only if overrun is set to data preserved.
+ If overrun is set to data overwritten, user can willingly not read
+ all the converted data, this is not considered as an erroneous case.
+ - Usage with ADC conversion by DMA: Error is reported whatever overrun
+ setting (DMA is expected to process all data from data register). */
+
+ uint32_t SamplingTimeCommon1; /*!< Set sampling time common to a group of channels.
+ Unit: ADC clock cycles.
+ This parameter is applied for ADC4.
+ Conversion time is the addition of sampling time and processing time
+ (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits,
+ 8.5 cycles at 8 bits).
+ Note: On this STM32 family, two different sampling time settings are available,
+ each channel can use one of these two settings.
+ On some other STM32 devices, this parameter in channel wise and
+ is located into ADC channel initialization structure.
+ This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME
+ Note: In case of usage of internal measurement channels
+ (VrefInt/Vbat/TempSensor), sampling time constraints must be respected
+ (sampling time can be adjusted in function of ADC clock frequency and
+ sampling time setting).
+ Refer to device datasheet for timings values, parameters TS_vrefint,
+ TS_vbat, TS_temp (values rough order: few tens of microseconds). */
+
+ uint32_t SamplingTimeCommon2; /*!< Set sampling time common to a group of channels, second common setting possible.
+ Unit: ADC clock cycles
+ This parameter is applied for ADC4.
+ Conversion time is the addition of sampling time and processing time (12.5 ADC
+ clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits,
+ 8.5 cycles at 8 bits).
+ Note: On this STM32 family, two different sampling time settings are available,
+ each channel can use one of these two settings.
+ On some other STM32 devices, this parameter in channel wise and is located
+ into ADC channel initialization structure.
+ This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME
+ Note: In case of usage of internal measurement channels
+ (VrefInt/Vbat/TempSensor), sampling time constraints must be respected
+ (sampling time can be adjusted in function of ADC clock frequency and
+ sampling time setting)
+ Refer to device datasheet for timings values, parameters TS_vrefint,
+ TS_vbat, TS_temp (values rough order: few tens of microseconds). */
+
+ uint32_t LeftBitShift; /*!< Configures the left shifting applied to the final result with or without
+ oversampling.
+ This parameter can be a value of @ref ADCEx_Left_Bit_Shift */
+
+ FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled.
+ This parameter can be set to ENABLE or DISABLE.
+ Note: This parameter can be modified only if there is no conversion
+ is ongoing on ADC groups regular and injected */
+
+ ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters.
+ Caution: this setting overwrites the previous oversampling configuration
+ if oversampling is already enabled. */
+
+ uint32_t TriggerFrequencyMode; /*!< Set ADC trigger frequency mode.
+ This parameter can be a value of @ref ADC_HAL_EC_REG_TRIGGER_FREQ.
+ Note: ADC trigger frequency mode must be set to low frequency when
+ a duration is exceeded before ADC conversion start trigger event
+ (between ADC enable and ADC conversion start trigger event
+ or between two ADC conversion start trigger event).
+ Duration value: Refer to device datasheet, parameter "tIdle".
+ Note: When ADC trigger frequency mode is set to low frequency,
+ some rearm cycles are inserted before performing ADC conversion
+ start, inducing a delay of 2 ADC clock cycles. */
+
+ uint32_t VrefProtection; /*!< Select the Vref protection mode: specify VREF+ protection mode
+ when multiple ADCs are working simultaneously.
+ This parameter can be value of @ref ADC_HAL_VrefProt.
+ Note: This parameter can be used for ADC4 only. */
+
+} ADC_InitTypeDef;
+
+/**
+ * @brief Structure definition of ADC channel for regular group
+ * @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state.
+ * ADC state can be either:
+ * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff')
+ * - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on
+ * going on regular group.
+ * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going
+ * on regular and injected groups.
+ * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+ * without error reporting (as it can be the expected behavior in case of intended action to update another
+ * parameter (which fulfills the ADC state condition) on the fly.
+ */
+typedef struct
+{
+ uint32_t Channel; /*!< Specify the channel to configure into ADC regular group.
+ This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
+ Note: Depending on devices and ADC instances, some channels may not be
+ available on device package pins. Refer to device datasheet for
+ channels availability. */
+
+ uint32_t Rank; /*!< Specify the rank in the regular group sequencer.
+ This parameter is depending on ADC instances.
+ If ADC1 or ADC2 instances, this parameter specify the rank in the sequencer.
+ Note: to disable a channel or change order of conversion sequencer,
+ rank containing a previous channel setting can be overwritten by
+ the new channel setting (or parameter number of conversions adjusted)
+ If ADC4 instance, this parameter allows to add or remove the channel from
+ the ADC regular group sequencer and specify its conversion rank.
+ This parameter is depending on ScanConvMode:
+ - sequencer configured to fully configurable:
+ Channels ordering into each rank of scan sequence:
+ whatever channel can be placed into whatever rank.
+ - sequencer configured to not fully configurable:
+ rank of each channel is fixed by channel HW number.
+ (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+ Despite the channel rank is fixed, this parameter allow an additional
+ possibility: to remove the selected rank (selected channel) from sequencer.
+ This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS */
+
+ uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
+ Unit: ADC clock cycles
+ Conversion time is the addition of sampling time and processing time
+ (14.5 ADC clock cycles at ADC resolution 14 bits, 12.5 cycles at 12 bits,
+ 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
+ This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME
+ Caution: This parameter applies to a channel that can be used into regular
+ and/or injected group. It overwrites the last setting.
+ Note: On this STM32 family, two different sampling time settings are available
+ (refer to parameters "SamplingTimeCommon1" and "SamplingTimeCommon2"),
+ each channel can use one of these two settings.
+ Note: In case of usage of internal measurement channels
+ (VrefInt/Vbat/TempSensor), sampling time constraints must be respected
+ (sampling time can be adjusted in function of ADC clock frequency
+ and sampling time setting)
+ Refer to device datasheet for timings values. */
+
+ uint32_t SingleDiff; /*!< Select single-ended or differential input.
+ In differential mode: Differential measurement is carried out between
+ the selected channel 'i' (positive input) and channel
+ 'i+1' (negative input).
+ Only channel 'i' has to be configured, channel 'i+1' is
+ configured automatically.
+ This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING
+ Caution: This parameter applies to a channel that can be used in a regular
+ and/or injected group. It overwrites the last setting.
+ Note: Refer to Reference Manual to ensure the selected channel is available
+ in differential mode.
+ Note: When configuring a channel 'i' in differential mode, the channel 'i+1'
+ is not usable separately.
+ Note: This parameter must be modified when ADC is disabled (before ADC start
+ conversion or after ADC stop conversion).
+ If ADC is enabled, this parameter setting is bypassed without error
+ reporting (as it can be the expected behavior in case of another
+ parameter update on the fly) */
+
+ uint32_t OffsetNumber; /*!< Select the offset number
+ This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB
+ Caution: Only one offset is allowed per channel. This parameter overwrites the
+ last setting. */
+
+ uint32_t Offset; /*!< Define the offset to be subtracted from the raw converted data.
+ Offset value must be a positive number.
+ Depending of ADC resolution selected (14, 12, 10, 8 or 6 bits), this parameter
+ must be a number between Min_Data = 0x000 and Max_Data = 0x3FFF,
+ 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
+ Note: This parameter must be modified when no conversion is on going on without
+ both regular and injected groups (ADC disabled, or ADC enabled
+ continuous mode or external trigger that could launch a conversion). */
+
+ FunctionalState OffsetRightShift; /*!< Define the Right-shift data after Offset correction.
+ This parameter is applied only for 16-bit or 8-bit resolution.
+ This parameter can be set to ENABLE or DISABLE.*/
+
+ FunctionalState OffsetSignedSaturation; /*!< Specify whether the Signed saturation feature is used or not.
+ This parameter is applied only for 16-bit or 8-bit resolution.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ FunctionalState OffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow.
+ This parameter value can be ENABLE or DISABLE.
+ Note:
+ - This parameter must be modified when no conversion is on going on
+ both regular and injected groups (ADC disabled, or ADC enabled without
+ continuous mode or external trigger that could launch a conversion).
+ - Applicable for ADC1 */
+
+ uint32_t OffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added
+ (positive sign) from or to the raw converted data.
+ This parameter can be a value of @ref ADCEx_OffsetSign.
+ Note:
+ - This parameter must be modified when no conversion is on going on
+ both regular and injected groups (ADC disabled, or ADC enabled without
+ continuous mode or external trigger that could launch a conversion).
+ - Applicable for ADC1 */
+
+
+} ADC_ChannelConfTypeDef;
+
+/**
+ * @brief Structure definition of ADC analog watchdog
+ * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
+ * ADC state can be either:
+ * - For all parameters: ADC disabled or ADC enabled without conversion on going on ADC groups regular
+ * and injected.
+ */
+typedef struct
+{
+ uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel.
+ For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of
+ channels by setting parameter 'WatchdogMode').
+ For Analog Watchdog 2 and 3: Several channels can be monitored
+ (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel)
+ This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */
+
+ uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels.
+ For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or
+ all channels, ADC groups regular and-or injected.
+ For Analog Watchdog 2 and 3: Several channels can be monitored by applying
+ successively the AWD init structure.
+ For ADC1/ADC2, channels on ADC group regular and injected are not differentiated:
+ Set value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 channel, value
+ 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor all channels, value
+ 'ADC_ANALOGWATCHDOG_NONE' to monitor no channel.
+ This parameter can be a value of @ref ADC_analog_watchdog_mode. */
+
+ uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog.
+ For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode'
+ is configured on single channel (only 1 channel can be monitored).
+ For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature,
+ call successively the function HAL_ADC_AnalogWDGConfig() for each channel to
+ be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE').
+ Note: 'ORING' channels is not supported. For Analog watchdog 2 and 3 and for
+ multiple channels monitoring it's mandatory to recall successively the
+ function HAL_ADC_AnalogWDGConfig() to add monitored channel for each call.
+ This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */
+
+ FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode.
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value.
+ Depending of ADC resolution selected (14, 12, 10, 8 or 6 bits), this parameter must
+ be a number between Min_Data = 0x000 and Max_Data = 0x3FFF, 0xFFF, 0x3FF,
+ 0xFF or 0x3F respectively.
+ Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits:
+ - if ADC resolution is 12 bits the 4 LSB are ignored,
+ - if ADC resolution is 10 bits the 2 LSB are ignored.
+ Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are impacted:
+ the comparison of analog watchdog thresholds is done on oversampling
+ intermediate computation (after ratio, before shift application):
+ intermediate register bitfield [32:7] (26 most significant bits). */
+
+ uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value.
+ Depending of ADC resolution selected (14, 12, 10, 8 or 6 bits), this parameter
+ must be a number between Min_Data = 0x000 and Max_Data = 0x3FFF, 0xFFF, 0x3FF,
+ 0xFF or 0x3F respectively.
+ Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits:
+ - if ADC resolution is 12 bits the 4 LSB are ignored,
+ - if ADC resolution is 10 bits the 2 LSB are ignored.
+ Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
+ impacted: the comparison of analog watchdog thresholds is done on oversampling
+ intermediate computation (after ratio, before shift application):
+ intermediate register bitfield [32:7] (26 most significant bits). */
+
+ uint32_t FilteringConfig; /*!< Specify whether filtering should be use and the number of samples to consider.
+ Before setting flag or raising interrupt, analog watchdog can wait to have several
+ consecutive out-of-window samples. This parameter allows to configure this number.
+ This parameter only applies to Analog watchdog 1.
+ For others, use value ADC_AWD_FILTERING_NONE.
+ Note: This parameter is applicable for ADC1/ADC2 on this device.
+ This parameter can be a value of @ref ADC_analog_watchdog_filtering_config. */
+
+} ADC_AnalogWDGConfTypeDef;
+
+/**
+ * @brief ADC group injected contexts queue configuration
+ * @note Structure intended to be used only through structure "ADC_HandleTypeDef"
+ */
+typedef struct
+{
+ uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each
+ HAL_ADCEx_InjectedConfigChannel() call to finally initialize
+ JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */
+
+ uint32_t ChannelCount; /*!< Number of channels in the injected sequence */
+} ADC_InjectionConfigTypeDef;
+
+/** @defgroup ADC_States ADC States
+ * @{
+ */
+
+/**
+ * @brief HAL ADC state machine: ADC states definition (bitfields)
+ * @note ADC state machine is managed by bitfields, state must be compared
+ * with bit by bit.
+ * For example:
+ * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
+ * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
+ */
+/* States of ADC global scope */
+#define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */
+#define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */
+#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization,
+ calibration) */
+#define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */
+
+/* States of ADC errors */
+#define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL) /*!< Internal error occurrence */
+#define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL) /*!< Configuration error occurrence */
+#define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */
+
+/* States of ADC group regular */
+#define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur
+ (either by continuous mode, external trigger,
+ low power auto power-on (if feature available),
+ multimode ADC master control (if feature available)) */
+#define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */
+#define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */
+#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series:
+ End Of Sampling flag raised */
+
+/* States of ADC group injected */
+#define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur
+ (either by auto-injection mode, external trigger,
+ low power auto power-on (if feature available),
+ multimode ADC master control (if feature available)) */
+#define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Conversion data available on group injected */
+#define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Injected queue overflow occurrence */
+
+/* States of ADC analog watchdogs */
+#define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */
+#define HAL_ADC_STATE_AWD2 (0x00020000UL) /*!< Out-of-window occurrence of ADC analog watchdog 2 */
+#define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */
+
+/* States of ADC multi-mode */
+#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< ADC in multimode slave state, controlled by another
+ ADC master (when feature available) */
+
+/**
+ * @}
+ */
+
+/**
+ * @brief ADC handle Structure definition
+ */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+typedef struct __ADC_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+{
+ ADC_TypeDef *Instance; /*!< Register base address */
+ ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */
+ DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
+ HAL_LockTypeDef Lock; /*!< ADC locking object */
+ __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
+ __IO uint32_t ErrorCode; /*!< ADC Error code */
+ ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */
+ uint32_t ADCGroupRegularSequencerRanks; /*!< ADC group regular sequencer memorization
+ of ranks setting, used in mode "fully configurable"
+ (refer to parameter 'ScanConvMode') */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */
+ void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */
+ void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */
+ void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */
+ void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */
+ void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue overflow callback */
+ void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */
+ void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */
+ void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */
+ void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */
+ void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+} ADC_HandleTypeDef;
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL ADC Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */
+ HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */
+ HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */
+ HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */
+ HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */
+ HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID = 0x05U, /*!< ADC group injected context queue overflow callback ID */
+ HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */
+ HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */
+ HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */
+ HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */
+ HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */
+} HAL_ADC_CallbackIDTypeDef;
+
+/**
+ * @brief HAL ADC Callback pointer definition
+ */
+typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */
+
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Constants ADC Exported Constants
+ * @{
+ */
+
+/** @defgroup ADC_Error_Code ADC Error Code
+ * @{
+ */
+#define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */
+#define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking,
+ enable/disable, erroneous state, ...) */
+#define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */
+#define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */
+#define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
+ * @{
+ */
+#define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without prescaler */
+#define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler division by 2 */
+#define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler division by 4 */
+#define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler division by 6 */
+#define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler division by 8 */
+#define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler division by 10 */
+#define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler division by 12 */
+#define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler division by 16 */
+#define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler division by 32 */
+#define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler division by 64 */
+#define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler division by 128 */
+#define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler division by 256 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution
+ * @{
+ */
+
+#define ADC_RESOLUTION_14B (LL_ADC_RESOLUTION_14B) /*!< ADC resolution 14 bits */
+#define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */
+#define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */
+#define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */
+#define ADC_RESOLUTION_6B (0xFFFFFFFFUL)
+
+#define ADC4_RESOLUTION_12B (LL_ADC_RESOLUTION_12B_ADC4) /*!< ADC resolution 12 bits */
+#define ADC4_RESOLUTION_10B (LL_ADC_RESOLUTION_10B_ADC4) /*!< ADC resolution 10 bits */
+#define ADC4_RESOLUTION_8B (LL_ADC_RESOLUTION_8B_ADC4) /*!< ADC resolution 8 bits */
+#define ADC4_RESOLUTION_6B (LL_ADC_RESOLUTION_6B_ADC4) /*!< ADC resolution 6 bits */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment
+ * @{
+ */
+#define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
+#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Scan_mode ADC sequencer scan mode
+ * @{
+ */
+#define ADC_SCAN_DISABLE (0x00000000UL) /*!< Scan mode disabled */
+#define ADC_SCAN_ENABLE (0x00000001UL) /*!< Scan mode enabled */
+
+/** @defgroup ADC_Private_Constants ADC Private Constants
+ * @{
+ */
+
+/* Combination of all post-conversion flags bits: EOC/EOS, OVR, AWD */
+#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC)
+
+#define ADC4_SCAN_SEQ_FIXED_INT (0x80000000U) /* Internal definition to differentiate sequencer setting
+ fixed or configurable */
+
+#define ADC4_SCAN_DISABLE (0x00000000UL) /*!< Sequencer set to fully configurable: only the rank 1 is enabled (no scan sequence on several ranks) */
+#define ADC4_SCAN_ENABLE (ADC4_CFGR1_CHSELRMOD) /*!< Sequencer set to fully configurable: sequencer length and each rank affectation to a channel are configurable. */
+
+
+#define ADC_SCAN_SEQ_FIXED (ADC4_SCAN_SEQ_FIXED_INT) /*!< Sequencer set to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). Scan direction forward: from channel 0 to channel 18 */
+#define ADC_SCAN_SEQ_FIXED_BACKWARD (ADC4_SCAN_SEQ_FIXED_INT | ADC4_CFGR1_SCANDIR) /*!< Sequencer set to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). Scan direction backward: from channel 18 to channel 0 */
+
+#define ADC_SCAN_DIRECTION_FORWARD (ADC_SCAN_SEQ_FIXED) /* For compatibility with other STM32 devices */
+#define ADC_SCAN_DIRECTION_BACKWARD (ADC_SCAN_SEQ_FIXED_BACKWARD) /* For compatibility with other STM32 devices */
+
+/**
+ * @}
+ */
+
+/* Combination of all CHSELR bits: SQ2...SQ8 */
+#define ADC_CHSELR_SQ2_TO_SQ8 (ADC_CHSELR_SQ2 | ADC_CHSELR_SQ3 | ADC_CHSELR_SQ4 | ADC_CHSELR_SQ5\
+ | ADC_CHSELR_SQ6 | ADC_CHSELR_SQ7 | ADC_CHSELR_SQ8)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_LowPower_DPD ADC low power and deep power down selection
+ * @{
+ */
+#define ADC_LOW_POWER_NONE (0x00000000UL) /*!< Both Low Power Auto Off and Deep Power Down is Disabled*/
+#define ADC_LOW_POWER_AUTOFF (ADC4_PW_AUTOFF) /*!< Low Power Auto Off Enabled and Deep Power Down is Disabled*/
+#define ADC_LOW_POWER_DPD (ADC4_PW_DPD) /*!< Low Power Auto Off Disabled and Deep Power Down is Enabaled*/
+#define ADC_LOW_POWER_AUTOFF_DPD (ADC4_PW_AUTOFF | ADC4_PW_DPD) /*!< Low Power Auto Off Disabled and Deep Power Down is Enabaled*/
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_VrefProt ADC VREF+ protection mode selection
+ * @{
+ */
+#define ADC_VREF_PPROT_NONE (0x00000000UL) /*!< No VREF protection is applied*/
+#define ADC_VREF_PPROT_VREFPROT (ADC4_PW_VREFPROT) /*!< VREF+ protection when multiple ADCs are working simultaneously and a clock divider is used.*/
+#define ADC_VREF_PPROT_VREFSECSMP (ADC4_PW_VREFSECSMP) /*!< VREF+ protection when multiple ADCs are working simultaneously and a clock divider of 1 is used.*/
+#define ADC_VREF_PPROT_VREF_VREFSECSMP (ADC4_PW_VREFPROT | ADC4_PW_VREFSECSMP) /*!< Both VREF+ protection when multiple ADCs are working simultaneously and VREF+ second sample protection.*/
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source
+ * @{
+ */
+/* ADC group regular trigger sources for all ADC instances */
+#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger internal: SW start. */
+#define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11 event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_EXT_IT15 (LL_ADC_REG_TRIG_EXT_EXTI_LINE15) /*!< ADC group regular conversion trigger from external peripheral: HRTIM TRG1 event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_LPTIM1_CH1 (LL_ADC_REG_TRIG_EXT_LPTIM1_CH1) /*!< ADC group regular conversion trigger from external peripheral: LPTIM1 CH1 event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_LPTIM2_CH1 (LL_ADC_REG_TRIG_EXT_LPTIM2_CH1) /*!< ADC group regular conversion trigger from external peripheral: LPTIM2 CH1 event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_LPTIM3_CH1 (LL_ADC_REG_TRIG_EXT_LPTIM3_CH1) /*!< ADC group regular conversion trigger from external peripheral: LPTIM3 CH1 event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_LPTIM4_OUT (LL_ADC_REG_TRIG_EXT_LPTIM4_OUT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM3 event OUT. Trigger edge set to rising edge (default setting). */
+
+#define ADC4_EXTERNALTRIG_T1_CC4 (LL_ADC_REG_TRIG_EXT_TIM1_CH4_ADC4) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC4_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2_ADC4)
+#if defined(TIM2)
+#define ADC4_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO_ADC4)
+#endif /* TIM2 */
+#if defined(TIM15)
+#define ADC4_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO_ADC4)
+#endif /* TIM5 */
+#if defined(TIM6)
+#define ADC4_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC4)
+#endif /* TIM6 */
+
+#if defined(LPTIM1)
+#define ADC4_EXTERNALTRIG_LPTIM1_CH1 (LL_ADC_REG_TRIG_EXT_LPTIM1_CH1_ADC4)
+#endif /* LPTIM1 */
+
+#if defined(LPTIM3)
+#define ADC4_EXTERNALTRIG_LPTIM3_CH2 (LL_ADC_REG_TRIG_EXT_LPTIM3_CH2_ADC4)
+#endif /* LPTIM3 */
+#define ADC4_EXTERNALTRIG_EXT_IT15 (LL_ADC_REG_TRIG_EXT_EXTI_LINE15_ADC4)
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected)
+ * @{
+ */
+#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< Regular conversions hardware trigger detection disabled */
+#define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion trigger polarity set to rising edge */
+#define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion trigger polarity set to falling edge */
+#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions
+ * @{
+ */
+#define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /*!< End of unitary conversion flag */
+#define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /*!< End of sequence conversions flag */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
+ * @{
+ */
+#define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case of overrun: data preserved */
+#define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case of overrun: data overwritten */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
+ * @{
+ */
+#define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */
+#define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */
+#define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */
+#define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */
+#define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */
+#define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */
+#define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */
+#define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */
+#define ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9) /*!< ADC group regular sequencer rank 9 */
+#define ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */
+#define ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */
+#define ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */
+#define ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */
+#define ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */
+#define ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */
+#define ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
+ * @{
+ */
+#define ADC4_RANK_CHANNEL_NUMBER (0x00000001U) /*!< Setting relevant if parameter "ScanConvMode" is set to sequencer not fully configurable: Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */
+#define ADC4_RANK_NONE (0x00000002U) /*!< Setting relevant if parameter "ScanConvMode" is set to sequencer not fully configurable: Disable the selected rank (selected channel) from sequencer */
+
+#define ADC4_REGULAR_RANK_1 (LL_ADC_REG_RANK_1_ADC4) /*!< ADC group regular sequencer rank 1 */
+#define ADC4_REGULAR_RANK_2 (LL_ADC_REG_RANK_2_ADC4) /*!< ADC group regular sequencer rank 2 */
+#define ADC4_REGULAR_RANK_3 (LL_ADC_REG_RANK_3_ADC4) /*!< ADC group regular sequencer rank 3 */
+#define ADC4_REGULAR_RANK_4 (LL_ADC_REG_RANK_4_ADC4) /*!< ADC group regular sequencer rank 4 */
+#define ADC4_REGULAR_RANK_5 (LL_ADC_REG_RANK_5_ADC4) /*!< ADC group regular sequencer rank 5 */
+#define ADC4_REGULAR_RANK_6 (LL_ADC_REG_RANK_6_ADC4) /*!< ADC group regular sequencer rank 6 */
+#define ADC4_REGULAR_RANK_7 (LL_ADC_REG_RANK_7_ADC4) /*!< ADC group regular sequencer rank 7 */
+#define ADC4_REGULAR_RANK_8 (LL_ADC_REG_RANK_8_ADC4) /*!< ADC group regular sequencer rank 8 */
+
+/**
+ * @}
+ */
+/** @defgroup ADC_HAL_EC_SAMPLINGTIME_COMMON ADC instance - Sampling time common to a group of channels
+ * @{
+ */
+#define ADC4_SAMPLINGTIME_COMMON_1 (LL_ADC_SAMPLINGTIME_COMMON_1) /*!< Set sampling time common to a group of channels: sampling time nb 1 */
+#define ADC4_SAMPLINGTIME_COMMON_2 (LL_ADC_SAMPLINGTIME_COMMON_2) /*!< Set sampling time common to a group of channels: sampling time nb 2 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
+ * @{
+ */
+#define ADC_SAMPLETIME_5CYCLE (LL_ADC_SAMPLINGTIME_5CYCLE) /*!< Sampling time 5 ADC clock cycles */
+#define ADC_SAMPLETIME_6CYCLES (LL_ADC_SAMPLINGTIME_6CYCLES) /*!< Sampling time 6 ADC clock cycles */
+#define ADC_SAMPLETIME_12CYCLES (LL_ADC_SAMPLINGTIME_12CYCLES) /*!< Sampling time 12 ADC clock cycles */
+#define ADC_SAMPLETIME_20CYCLES (LL_ADC_SAMPLINGTIME_20CYCLES) /*!< Sampling time 20 ADC clock cycles */
+#define ADC_SAMPLETIME_36CYCLES (LL_ADC_SAMPLINGTIME_36CYCLES) /*!< Sampling time 36 ADC clock cycles */
+#define ADC_SAMPLETIME_68CYCLES (LL_ADC_SAMPLINGTIME_68CYCLES) /*!< Sampling time 68 ADC clock cycles */
+#define ADC_SAMPLETIME_391CYCLES_5 (LL_ADC_SAMPLINGTIME_391CYCLES_5)/*!< Sampling time 391.5 ADC clock cycles */
+#define ADC_SAMPLETIME_814CYCLES (LL_ADC_SAMPLINGTIME_814CYCLES) /*!< Sampling time 814 ADC clock cycles */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
+ * @{
+ */
+#define ADC4_SAMPLETIME_1CYCLE_5 (LL_ADC4_SAMPLINGTIME_1CYCLE_5) /*!< Sampling time 1.5 ADC clock cycle */
+#define ADC4_SAMPLETIME_3CYCLES_5 (LL_ADC4_SAMPLINGTIME_3CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles */
+#define ADC4_SAMPLETIME_7CYCLES_5 (LL_ADC4_SAMPLINGTIME_7CYCLES_5) /*!< Sampling time 7.5 ADC clock cycles */
+#define ADC4_SAMPLETIME_12CYCLES_5 (LL_ADC4_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */
+#define ADC4_SAMPLETIME_19CYCLES_5 (LL_ADC4_SAMPLINGTIME_19CYCLES_5) /*!< Sampling time 19.5 ADC clock cycles */
+#define ADC4_SAMPLETIME_39CYCLES_5 (LL_ADC4_SAMPLINGTIME_39CYCLES_5) /*!< Sampling time 39.5 ADC clock cycles */
+#define ADC4_SAMPLETIME_79CYCLES_5 (LL_ADC4_SAMPLINGTIME_79CYCLES_5) /*!< Sampling time 79.5 ADC clock cycles */
+#define ADC4_SAMPLETIME_160CYCLES_5 (LL_ADC4_SAMPLINGTIME_160CYCLES_5) /*!< Sampling time 160.5 ADC clock cycles */
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Calibration_Mode ADC Extended Calibration mode offset mode or linear mode
+ * @{
+ */
+#define ADC_CALIB_OFFSET (LL_ADC_CALIB_OFFSET)
+#define ADC_CALIB_OFFSET_LINEARITY (LL_ADC_CALIB_OFFSET_LINEARITY)
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Calibration_Linearity_Index ADC indexes for linear calibration
+ * @{
+ */
+#define ADC_CALIB_OFFSET_INDEX LL_ADC_CALIB_OFFSET_INDEX /*!< Offset Calibration Index */
+#define ADC_CALIB_LINEARITY_INDEX1 LL_ADC_CALIB_LINEARITY_INDEX1 /*!< Linearity Calibration Index 1*/
+#define ADC_CALIB_LINEARITY_INDEX2 LL_ADC_CALIB_LINEARITY_INDEX2 /*!< Linearity Calibration Index 1*/
+#define ADC_CALIB_LINEARITY_INDEX3 LL_ADC_CALIB_LINEARITY_INDEX3 /*!< Linearity Calibration Index 1*/
+#define ADC_CALIB_LINEARITY_INDEX4 LL_ADC_CALIB_LINEARITY_INDEX4 /*!< Linearity Calibration Index 1*/
+#define ADC_CALIB_LINEARITY_INDEX5 LL_ADC_CALIB_LINEARITY_INDEX5 /*!< Linearity Calibration Index 1*/
+#define ADC_CALIB_LINEARITY_INDEX6 LL_ADC_CALIB_LINEARITY_INDEX6 /*!< Linearity Calibration Index 1*/
+#define ADC_CALIB_LINEARITY_INDEX7 LL_ADC_CALIB_LINEARITY_INDEX7 /*!< Linearity Calibration Index 1*/
+#define ADC_CALIB_INTEROFFSET_INDEX LL_ADC_CALIB_INTEROFFSET_INDEX /*!< Linearity Calibration Index 1*/
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number
+ * @{
+ */
+/* Note: VrefInt, TempSensor and Vbat internal channels are not available on */
+/* all ADC instances (refer to Reference Manual). */
+#define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
+#define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
+#define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
+#define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
+#define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
+#define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
+#define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
+#define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
+#define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
+#define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
+#define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
+#define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
+#define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
+#define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
+#define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
+#define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
+#define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
+#define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
+#define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
+#define ADC_CHANNEL_19 (LL_ADC_CHANNEL_19) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN19 */
+#define ADC_CHANNEL_20 (LL_ADC_CHANNEL_20) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN20 */
+#define ADC_CHANNEL_21 (LL_ADC_CHANNEL_21) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN21 */
+#define ADC_CHANNEL_22 (LL_ADC_CHANNEL_22) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN22 */
+#define ADC_CHANNEL_23 (LL_ADC_CHANNEL_23) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN23 */
+#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */
+#define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< ADC internal channel connected to Temperature sensor. */
+#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda. */
+
+#define ADC_CHANNEL_DAC1CH1_ADC4 (LL_ADC_CHANNEL_DAC1CH1_ADC4) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC4 */
+#define ADC_CHANNEL_DAC1CH2_ADC4 (LL_ADC_CHANNEL_DAC1CH2_ADC4) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC4 */
+
+#define ADC4_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR_ADC4) /*!< ADC internal channel connected to Temperature sensor, channel specific to ADC4. */
+#define ADC4_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT_ADC4) /*!< ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, channel specific to ADC4. */
+
+#define ADC_CHANNEL_VCORE (LL_ADC_CHANNEL_VCORE) /*!< ADC internal channel connected to Vcore, channel specific to ADC4. */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_ConversionDataManagement ADC Conversion Data Management
+ * @{
+ */
+#define ADC_CONVERSIONDATA_DR ((uint32_t)0x00000000) /*!< Regular Conversion data stored in DR register only */
+#define ADC_CONVERSIONDATA_MDF ((uint32_t)ADC_CFGR1_DMNGT_1) /*!< MDF mode selected */
+#define ADC_CONVERSIONDATA_DMA_ONESHOT ((uint32_t)ADC_CFGR1_DMNGT_0) /*!< DMA one shot mode selected */
+#define ADC_CONVERSIONDATA_DMA_CIRCULAR ((uint32_t)(ADC_CFGR1_DMNGT_0 | ADC_CFGR1_DMNGT_1)) /*!< DMA circular mode selected */
+/**
+ * @}
+ */
+/** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
+ * @{
+ */
+#define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */
+#define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */
+#define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_analog_watchdog_filtering_config ADC Analog Watchdog filtering configuration
+ * @{
+ */
+#define ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog wathdog no filtering, one out-of-window sample is needed to raise flag or interrupt */
+#define ADC_AWD_FILTERING_2SAMPLES ((ADC_HTR_AWDFILT_0)) /*!< ADC analog wathdog 2 consecutives out-of-window samples are needed to raise flag or interrupt */
+#define ADC_AWD_FILTERING_3SAMPLES ((ADC_HTR_AWDFILT_1)) /*!< ADC analog wathdog 3 consecutives out-of-window samples are needed to raise flag or interrupt */
+#define ADC_AWD_FILTERING_4SAMPLES ((ADC_HTR_AWDFILT_1 | ADC_HTR_AWDFILT_0)) /*!< ADC analog wathdog 4 consecutives out-of-window samples are needed to raise flag or interrupt */
+#define ADC_AWD_FILTERING_5SAMPLES ((ADC_HTR_AWDFILT_2)) /*!< ADC analog wathdog 5 consecutives out-of-window samples are needed to raise flag or interrupt */
+#define ADC_AWD_FILTERING_6SAMPLES ((ADC_HTR_AWDFILT_2 | ADC_HTR_AWDFILT_0)) /*!< ADC analog wathdog 6 consecutives out-of-window samples are needed to raise flag or interrupt */
+#define ADC_AWD_FILTERING_7SAMPLES ((ADC_HTR_AWDFILT_2 | ADC_HTR_AWDFILT_1)) /*!< ADC analog wathdog 7 consecutives out-of-window samples are needed to raise flag or interrupt */
+#define ADC_AWD_FILTERING_8SAMPLES ((ADC_HTR_AWDFILT_2 | ADC_HTR_AWDFILT_1 | ADC_HTR_AWDFILT_0)) /*!< ADC analog wathdog 8 consecutives out-of-window samples are needed to raise flag or interrupt */
+/**
+ * @}
+ */
+
+
+
+/** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode
+ * @{
+ */
+#define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< No analog watchdog selected */
+#define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR1_AWD1SGL | ADC_CFGR1_AWD1EN) /*!< Analog watchdog applied to a regular group single channel */
+#define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR1_AWD1SGL | ADC_CFGR1_JAWD1EN) /*!< Analog watchdog applied to an injected group single channel */
+#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR1_AWD1SGL | ADC_CFGR1_AWD1EN | ADC_CFGR1_JAWD1EN) /*!< Analog watchdog applied to a regular and injected groups single channel */
+#define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR1_AWD1EN) /*!< Analog watchdog applied to regular group all channels */
+#define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR1_JAWD1EN) /*!< Analog watchdog applied to injected group all channels */
+#define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR1_AWD1EN | ADC_CFGR1_JAWD1EN) /*!< Analog watchdog applied to regular and injected groups all channels */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio
+ * @{
+ */
+#define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+/**
+ * @}
+ */
+/** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift
+ * @{
+ */
+#define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
+#define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
+#define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
+#define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
+#define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
+#define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
+#define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
+#define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
+#define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
+#define ADC_RIGHTBITSHIFT_9 (LL_ADC_OVS_SHIFT_RIGHT_9) /*!< ADC oversampling shift of 9 (sum of the ADC conversions data is divided by 512 to result as the ADC oversampling conversion data) */
+#define ADC_RIGHTBITSHIFT_10 (LL_ADC_OVS_SHIFT_RIGHT_10)/*!< ADC oversampling shift of 10 (sum of the ADC conversions data is divided by 1024 to result as the ADC oversampling conversion data) */
+#define ADC_RIGHTBITSHIFT_11 (LL_ADC_OVS_SHIFT_RIGHT_11)/*!< ADC oversampling shift of 11 (sum of the ADC conversions data is divided by 2048 to result as the ADC oversampling conversion data) */
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Left_Bit_Shift ADC Extended Oversampling left Shift
+ * @{
+ */
+#define ADC_LEFTBITSHIFT_NONE (LL_ADC_LEFT_BIT_SHIFT_NONE) /*!< ADC No bit shift */
+#define ADC_LEFTBITSHIFT_1 (LL_ADC_LEFT_BIT_SHIFT_1) /*!< ADC 1 bit shift */
+#define ADC_LEFTBITSHIFT_2 (LL_ADC_LEFT_BIT_SHIFT_2) /*!< ADC 2 bits shift */
+#define ADC_LEFTBITSHIFT_3 (LL_ADC_LEFT_BIT_SHIFT_3) /*!< ADC 3 bits shift */
+#define ADC_LEFTBITSHIFT_4 (LL_ADC_LEFT_BIT_SHIFT_4) /*!< ADC 4 bits shift */
+#define ADC_LEFTBITSHIFT_5 (LL_ADC_LEFT_BIT_SHIFT_5) /*!< ADC 5 bits shift */
+#define ADC_LEFTBITSHIFT_6 (LL_ADC_LEFT_BIT_SHIFT_6) /*!< ADC 6 bits shift */
+#define ADC_LEFTBITSHIFT_7 (LL_ADC_LEFT_BIT_SHIFT_7) /*!< ADC 7 bits shift */
+#define ADC_LEFTBITSHIFT_8 (LL_ADC_LEFT_BIT_SHIFT_8) /*!< ADC 8 bits shift */
+#define ADC_LEFTBITSHIFT_9 (LL_ADC_LEFT_BIT_SHIFT_9) /*!< ADC 9 bits shift */
+#define ADC_LEFTBITSHIFT_10 (LL_ADC_LEFT_BIT_SHIFT_10) /*!< ADC 10 bits shift */
+#define ADC_LEFTBITSHIFT_11 (LL_ADC_LEFT_BIT_SHIFT_11) /*!< ADC 11 bits shift */
+#define ADC_LEFTBITSHIFT_12 (LL_ADC_LEFT_BIT_SHIFT_12) /*!< ADC 12 bits shift */
+#define ADC_LEFTBITSHIFT_13 (LL_ADC_LEFT_BIT_SHIFT_13) /*!< ADC 13 bits shift */
+#define ADC_LEFTBITSHIFT_14 (LL_ADC_LEFT_BIT_SHIFT_14) /*!< ADC 14 bits shift */
+#define ADC_LEFTBITSHIFT_15 (LL_ADC_LEFT_BIT_SHIFT_15) /*!< ADC 15 bits shift */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
+ * @{
+ */
+#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
+#define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_OVS_SCOPE_REG Oversampling - Oversampling scope for ADC group regular
+ * @{
+ */
+#define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained during injection sequence */
+#define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED) /*!< Oversampling buffer zeroed during injection sequence */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode
+ * @{
+ */
+#define ADC_TRIGGER_FREQ_HIGH (LL_ADC_TRIGGER_FREQ_HIGH) /*!< ADC trigger frequency mode set to high frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */
+#define ADC_TRIGGER_FREQ_LOW (LL_ADC_TRIGGER_FREQ_LOW) /*!< ADC trigger frequency mode set to low frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Event_type ADC Event type
+ * @{
+ */
+#define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */
+#define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */
+#define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */
+#define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */
+#define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */
+#define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */
+/**
+ * @}
+ */
+#define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */
+
+/** @defgroup ADC_interrupts_definition ADC interrupts definition
+ * @{
+ */
+#define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */
+#define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */
+#define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */
+#define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */
+#define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */
+#define ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */
+#define ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt source */
+#define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */
+#define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */
+#define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */
+#define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */
+
+#define ADC_IT_AWD ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_flags_definition ADC flags definition
+ * @{
+ */
+#define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */
+#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */
+#define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */
+#define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */
+#define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */
+#define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */
+#define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */
+#define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */
+#define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */
+#define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */
+#define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Macros ADC Private Macros
+ * @{
+ */
+/* Macro reserved for internal HAL driver usage, not intended to be used in */
+/* code of final user. */
+
+/**
+ * @brief Verify the ADC data conversion setting.
+ * @param DATA : programmed DATA conversion mode.
+ * @retval SET (DATA is a valid value) or RESET (DATA is invalid)
+ */
+#define IS_ADC_CONVERSIONDATAMGT(DATA) \
+ ((((DATA) == ADC_CONVERSIONDATA_DR)) || \
+ (((DATA) == ADC_CONVERSIONDATA_MDF)) || \
+ (((DATA) == ADC_CONVERSIONDATA_DMA_ONESHOT)) || \
+ (((DATA) == ADC_CONVERSIONDATA_DMA_CIRCULAR)))
+
+/**
+ * @brief Return resolution bits in CFGR register RES[1:0] field.
+ * @param __HANDLE__ ADC handle
+ * @retval Value of bitfield RES in CFGR register.
+ */
+#define ADC_GET_RESOLUTION(__HANDLE__) \
+ (LL_ADC_GetResolution((__HANDLE__)->Instance))
+
+/**
+ * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").
+ * @param __HANDLE__ ADC handle
+ * @retval None
+ */
+#define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
+
+/**
+ * @brief Verification of ADC state: enabled or disabled.
+ * @param __HANDLE__ ADC handle
+ * @retval SET (ADC enabled) or RESET (ADC disabled)
+ */
+#define ADC_IS_ENABLE(__HANDLE__) \
+ (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
+ ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \
+ ) ? SET : RESET)
+
+/**
+ * @brief Enable ADC overrun mode.
+ * @param _OVERRUN_MODE_ Overrun mode.
+ * @retval Overrun bit setting to be programmed into CFGR register
+ */
+/* Note: Bit ADC_CFGR1_OVRMOD not used directly in constant */
+/* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it */
+/* as the default case to be compliant with other STM32 devices. */
+#define ADC_CFGR_OVERRUN(_OVERRUN_MODE_) \
+ ( ( (_OVERRUN_MODE_) != (ADC_OVR_DATA_PRESERVED) \
+ )? (ADC_CFGR1_OVRMOD) : (0x00000000UL) \
+ )
+
+/* Note: Scan mode set using this macro (instead of parameter direct set) */
+/* due to different modes on other STM32 devices: */
+/* if scan mode is disabled, sequencer is set to fully configurable */
+/* with setting of only rank 1 enabled afterwards. */
+#define ADC_SCAN_SEQ_MODE(_SCAN_MODE_) \
+ ( (((_SCAN_MODE_) & ADC4_SCAN_SEQ_FIXED_INT) != 0UL \
+ )? \
+ ((_SCAN_MODE_) & (~ADC4_SCAN_SEQ_FIXED_INT)) \
+ : \
+ (ADC4_CFGR1_CHSELRMOD) \
+ )
+
+/**
+ * @brief Check if conversion is on going on regular group.
+ * @param __HANDLE__ ADC handle
+ * @retval Value "0" (no conversion is on going) or value "1" (conversion is on going)
+ */
+#define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \
+ (LL_ADC_REG_IsConversionOngoing((__HANDLE__)->Instance))
+
+
+/**
+ * @brief Simultaneously clear and set specific bits of the handle State.
+ * @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
+ * the first parameter is the ADC handle State, the second parameter is the
+ * bit field to clear, the third and last parameter is the bit field to set.
+ * @retval None
+ */
+#define ADC_STATE_CLR_SET MODIFY_REG
+
+/**
+ * @brief Verify that a given value is aligned with the ADC resolution range.
+ * @param __ADCx__ ADC instance
+ * @param __RESOLUTION__ ADC resolution (14, 12, 10, 8 or 6 bits).
+ * @param __ADC_VALUE__ value checked against the resolution.
+ * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__)
+ */
+#define IS_ADC_RANGE(__ADCx__, __RESOLUTION__, __ADC_VALUE__) \
+ ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__ADCx__, __RESOLUTION__))
+
+/**
+ * @brief Verify the length of the scheduled regular conversions group.
+ * @param __LENGTH__ number of programmed conversions.
+ * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions)
+ * or RESET (__LENGTH__ is null or too large)
+ */
+#define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL)))
+
+/** @defgroup ADC_regular_nb_conv_verification ADC4 Regular Conversion Number Verification
+ * @{
+ */
+#define IS_ADC4_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= 1UL) && ((LENGTH) <= 8UL))
+/**
+ * @}
+ */
+
+/**
+ * @brief Verify the number of scheduled regular conversions in discontinuous mode.
+ * @param NUMBER number of scheduled regular conversions in discontinuous mode.
+ * @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode)
+ * or RESET (NUMBER is null or too large)
+ */
+#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL)))
+
+
+/**
+ * @brief Verify the ADC clock setting.
+ * @param __ADC_CLOCK__ programmed ADC clock.
+ * @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid)
+ */
+#define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1) || \
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2) || \
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4) || \
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6) || \
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8) || \
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10) || \
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12) || \
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16) || \
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32) || \
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64) || \
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128) || \
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) )
+
+/**
+ * @brief Verify the ADC resolution setting.
+ * @param __RESOLUTION__ programmed ADC resolution.
+ * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)
+ */
+#define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_14B) || \
+ ((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
+ ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
+ ((__RESOLUTION__) == ADC_RESOLUTION_8B) || \
+ ((__RESOLUTION__) == ADC_RESOLUTION_6B) )
+
+/**
+ * @brief Verify the ADC resolution setting when limited to 6 or 8 bits.
+ * @param __RESOLUTION__ programmed ADC resolution when limited to 6 or 8 bits.
+ * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)
+ */
+#define IS_ADC_RESOLUTION_8_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B))
+
+/**
+ * @brief Verify the ADC resolution setting.
+ * @param __RESOLUTION__ programmed ADC resolution.
+ * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)
+ */
+#define IS_ADC4_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC4_RESOLUTION_12B) || \
+ ((__RESOLUTION__) == ADC4_RESOLUTION_10B) || \
+ ((__RESOLUTION__) == ADC4_RESOLUTION_8B) || \
+ ((__RESOLUTION__) == ADC4_RESOLUTION_6B) )
+
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
+ ((ALIGN) == ADC_DATAALIGN_LEFT) )
+
+/**
+ * @brief Verify the ADC gain compensation.
+ * @param __GAIN_COMPENSATION__ programmed ADC gain compensation coefficient.
+ * @retval SET (__GAIN_COMPENSATION__ is a valid value) or RESET (__GAIN_COMPENSATION__ is invalid)
+ */
+#define IS_ADC_GAIN_COMPENSATION(__GAIN_COMPENSATION__) ((__GAIN_COMPENSATION__) <= 16393UL)
+
+/**
+ * @brief Verify the ADC scan mode.
+ * @param __SCAN_MODE__ programmed ADC scan mode.
+ * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid)
+ */
+#define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \
+ ((__SCAN_MODE__) == ADC_SCAN_ENABLE) )
+
+#define IS_ADC4_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC4_SCAN_DISABLE) || \
+ ((SCAN_MODE) == ADC4_SCAN_ENABLE) || \
+ ((SCAN_MODE) == ADC_SCAN_SEQ_FIXED) || \
+ ((SCAN_MODE) == ADC_SCAN_SEQ_FIXED_BACKWARD) )
+
+/**
+ * @brief Verify the ADC edge trigger setting for regular group.
+ * @param __EDGE__ programmed ADC edge trigger setting.
+ * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
+ */
+#define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
+ ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
+ ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
+ ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) )
+
+/**
+ * @brief Verify the ADC regular conversions external trigger.
+ * @param __REGTRIG__ programmed ADC regular conversions external trigger.
+ * @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid)
+ */
+#define IS_ADC_EXTTRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT15) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM1_CH1) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM2_CH1) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM3_CH1) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM4_OUT) || \
+ ((__REGTRIG__) == ADC_SOFTWARE_START) )
+
+
+#define IS_ADC4_EXTTRIG(REGTRIG) (((REGTRIG) == ADC4_EXTERNALTRIG_T1_TRGO2) || \
+ ((REGTRIG) == ADC4_EXTERNALTRIG_T1_CC4) || \
+ ((REGTRIG) == ADC4_EXTERNALTRIG_T2_TRGO) || \
+ ((REGTRIG) == ADC4_EXTERNALTRIG_T15_TRGO) || \
+ ((REGTRIG) == ADC4_EXTERNALTRIG_T6_TRGO) || \
+ ((REGTRIG) == ADC4_EXTERNALTRIG_LPTIM1_CH1) || \
+ ((REGTRIG) == ADC4_EXTERNALTRIG_LPTIM3_CH2) || \
+ ((REGTRIG) == ADC4_EXTERNALTRIG_EXT_IT15) || \
+ ((REGTRIG) == ADC_SOFTWARE_START) )
+
+/**
+ * @brief Verify the ADC regular conversions check for converted data availability.
+ * @param __EOC_SELECTION__ converted data availability check.
+ * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid)
+ */
+#define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV) || \
+ ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV) )
+
+/**
+ * @brief Verify the ADC regular conversions overrun handling.
+ * @param __OVR__ ADC regular conversions overrun handling.
+ * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid)
+ */
+#define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED) || \
+ ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) )
+
+/**
+ * @brief Verify the ADC conversions sampling time.
+ * @param __TIME__ ADC conversions sampling time.
+ * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid)
+ */
+#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_5CYCLE) || \
+ ((__TIME__) == ADC_SAMPLETIME_6CYCLES) || \
+ ((__TIME__) == ADC_SAMPLETIME_12CYCLES) || \
+ ((__TIME__) == ADC_SAMPLETIME_20CYCLES) || \
+ ((__TIME__) == ADC_SAMPLETIME_36CYCLES) || \
+ ((__TIME__) == ADC_SAMPLETIME_68CYCLES) || \
+ ((__TIME__) == ADC_SAMPLETIME_391CYCLES_5) || \
+ ((__TIME__) == ADC_SAMPLETIME_814CYCLES) )
+
+#define IS_ADC4_SAMPLE_TIME(TIME) (((TIME) == ADC4_SAMPLETIME_1CYCLE_5) || \
+ ((TIME) == ADC4_SAMPLETIME_3CYCLES_5) || \
+ ((TIME) == ADC4_SAMPLETIME_7CYCLES_5) || \
+ ((TIME) == ADC4_SAMPLETIME_12CYCLES_5) || \
+ ((TIME) == ADC4_SAMPLETIME_19CYCLES_5) || \
+ ((TIME) == ADC4_SAMPLETIME_39CYCLES_5) || \
+ ((TIME) == ADC4_SAMPLETIME_79CYCLES_5) || \
+ ((TIME) == ADC4_SAMPLETIME_160CYCLES_5) )
+
+/**
+ * @brief Verify the ADC regular channel setting.
+ * @param __CHANNEL__ programmed ADC regular channel.
+ * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
+ */
+#define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_16) )
+
+
+#define IS_ADC4_REGULAR_RANK(RANK) (((RANK) == ADC4_REGULAR_RANK_1 ) || \
+ ((RANK) == ADC4_REGULAR_RANK_2 ) || \
+ ((RANK) == ADC4_REGULAR_RANK_3 ) || \
+ ((RANK) == ADC4_REGULAR_RANK_4 ) || \
+ ((RANK) == ADC4_REGULAR_RANK_5 ) || \
+ ((RANK) == ADC4_REGULAR_RANK_6 ) || \
+ ((RANK) == ADC4_REGULAR_RANK_7 ) || \
+ ((RANK) == ADC4_REGULAR_RANK_8 ) )
+
+#define IS_ADC4_REGULAR_RANK_SEQ_FIXED(RANK) (((RANK) == ADC4_RANK_CHANNEL_NUMBER) || \
+ ((RANK) == ADC4_RANK_NONE) )
+
+
+#define IS_ADC_TRIGGER_FREQ(TRIGGER_FREQ) (((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_HIGH) || \
+ ((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_LOW) )
+
+#define IS_ADC4_LOW_POWER(__LP_MODE__) (((__LP_MODE__) == ADC_LOW_POWER_NONE) || \
+ ((__LP_MODE__) == ADC_LOW_POWER_AUTOFF) || \
+ ((__LP_MODE__) == ADC_LOW_POWER_DPD) || \
+ ((__LP_MODE__) == ADC_LOW_POWER_AUTOFF_DPD) )
+
+#define IS_ADC4_VREF_PROT(__VREF_PROT__) (((__VREF_PROT__) == ADC_VREF_PPROT_NONE) || \
+ ((__VREF_PROT__) == ADC_VREF_PPROT_VREFPROT) || \
+ ((__VREF_PROT__) == ADC_VREF_PPROT_VREFSECSMP) || \
+ ((__VREF_PROT__) == ADC_VREF_PPROT_VREF_VREFSECSMP) )
+
+/**
+ * @}
+ */
+
+
+/* Private constants ---------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Constants ADC Private Constants
+ * @{
+ */
+
+/* Fixed timeout values for ADC conversion (including sampling time) */
+/* Maximum sampling time is 810.5 ADC clock cycle */
+/* Maximum conversion time is 16.5 + Maximum sampling time */
+/* or 16.5 + 810.5 = 827 ADC clock cycles */
+/* Minimum ADC Clock frequency is 0.35 MHz */
+/* Maximum conversion time is */
+/* 653 / 0.14 MHz = 4.66 ms */
+#define ADC_STOP_CONVERSION_TIMEOUT ( 5UL) /*!< ADC stop time-out value */
+
+/* Delay for temperature sensor stabilization time. */
+/* Maximum delay is 120us (refer device datasheet, parameter tSTART). */
+/* Unit: us */
+#define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US)
+
+/* Delay for ADC voltage regulator startup time */
+/* Maximum delay is 10 microseconds */
+/* (refer device RM, parameter Tadcvreg_stup). */
+#define ADC_STAB_DELAY_US ((uint32_t) 10) /*!< ADC voltage regulator startup time */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Macros ADC Exported Macros
+ * @{
+ */
+/* Macro for internal HAL driver usage, and possibly can be used into code of */
+/* final user. */
+
+/** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags.
+ * @{
+ */
+
+/** @brief Reset ADC handle state.
+ * @param __HANDLE__ ADC handle
+ * @retval None
+ */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
+ do{ \
+ (__HANDLE__)->State = HAL_ADC_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
+ ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+/**
+ * @brief Enable ADC interrupt.
+ * @param __HANDLE__ ADC handle
+ * @param __INTERRUPT__ ADC Interrupt
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_IT_RDY ADC Ready interrupt source
+ * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source
+ * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source
+ * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
+ * @arg @ref ADC_IT_OVR ADC overrun interrupt source
+ * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source
+ * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
+ * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
+ * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
+ * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
+ * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
+ * @retval None
+ */
+#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
+
+/**
+ * @brief Disable ADC interrupt.
+ * @param __HANDLE__ ADC handle
+ * @param __INTERRUPT__ ADC Interrupt
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_IT_RDY ADC Ready interrupt source
+ * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source
+ * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source
+ * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
+ * @arg @ref ADC_IT_OVR ADC overrun interrupt source
+ * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source
+ * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
+ * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
+ * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
+ * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
+ * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
+ * @retval None
+ */
+#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
+
+/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
+ * @param __HANDLE__ ADC handle
+ * @param __INTERRUPT__ ADC interrupt source to check
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_IT_RDY ADC Ready interrupt source
+ * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source
+ * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source
+ * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
+ * @arg @ref ADC_IT_OVR ADC overrun interrupt source
+ * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source
+ * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
+ * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
+ * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
+ * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
+ * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
+ * @retval State of interruption (SET or RESET)
+ */
+#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified ADC flag is set or not.
+ * @param __HANDLE__ ADC handle
+ * @param __FLAG__ ADC flag
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_FLAG_RDY ADC Ready flag
+ * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag
+ * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag
+ * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
+ * @arg @ref ADC_FLAG_OVR ADC overrun flag
+ * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag
+ * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag
+ * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
+ * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
+ * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
+ * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag.
+ * @retval State of flag (TRUE or FALSE).
+ */
+#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
+ ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clear the specified ADC flag.
+ * @param __HANDLE__ ADC handle
+ * @param __FLAG__ ADC flag
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_FLAG_RDY ADC Ready flag
+ * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag
+ * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag
+ * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
+ * @arg @ref ADC_FLAG_OVR ADC overrun flag
+ * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag
+ * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag
+ * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
+ * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
+ * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
+ * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag.
+ * @retval None
+ */
+/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */
+#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+ (((__HANDLE__)->Instance->ISR) = (__FLAG__))
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro
+ * @{
+ */
+
+/**
+ * @brief Helper macro to get ADC channel number in decimal format
+ * from literals ADC_CHANNEL_x.
+ * @note Example:
+ * __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4)
+ * will return decimal number "4".
+ * @note The input can be a value from functions where a channel
+ * number is returned, either defined with number
+ * or with bitfield (only one bit must be set).
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref ADC_CHANNEL_0 (3)
+ * @arg @ref ADC_CHANNEL_1 (3)
+ * @arg @ref ADC_CHANNEL_2 (3)
+ * @arg @ref ADC_CHANNEL_3 (3)
+ * @arg @ref ADC_CHANNEL_4 (3)
+ * @arg @ref ADC_CHANNEL_5 (3)
+ * @arg @ref ADC_CHANNEL_6
+ * @arg @ref ADC_CHANNEL_7
+ * @arg @ref ADC_CHANNEL_8
+ * @arg @ref ADC_CHANNEL_9
+ * @arg @ref ADC_CHANNEL_10
+ * @arg @ref ADC_CHANNEL_11
+ * @arg @ref ADC_CHANNEL_12
+ * @arg @ref ADC_CHANNEL_13
+ * @arg @ref ADC_CHANNEL_14
+ * @arg @ref ADC_CHANNEL_15
+ * @arg @ref ADC_CHANNEL_16
+ * @arg @ref ADC_CHANNEL_17
+ * @arg @ref ADC_CHANNEL_18
+ * @arg @ref ADC_CHANNEL_VREFINT (1)
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref ADC_CHANNEL_VBAT (1)
+ * @arg @ref ADC_CHANNEL_DAC1CH1_ADC4 (2)
+ * @arg @ref ADC_CHANNEL_DAC1CH2_ADC4 (2)
+ *
+ * (1) On STM32U5, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32U5, parameter available only on ADC instance: ADC4.\n
+ * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).
+ * @retval Value between Min_Data=0 and Max_Data=18
+ */
+#define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
+ __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))
+
+/**
+ * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x
+ * from number in decimal format.
+ * @note Example:
+ * __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4)
+ * will return a data equivalent to "ADC_CHANNEL_4".
+ * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
+ * @retval Returned value can be one of the following values:
+ * @arg @ref ADC_CHANNEL_0 (3)
+ * @arg @ref ADC_CHANNEL_1 (3)
+ * @arg @ref ADC_CHANNEL_2 (3)
+ * @arg @ref ADC_CHANNEL_3 (3)
+ * @arg @ref ADC_CHANNEL_4 (3)
+ * @arg @ref ADC_CHANNEL_5 (3)
+ * @arg @ref ADC_CHANNEL_6
+ * @arg @ref ADC_CHANNEL_7
+ * @arg @ref ADC_CHANNEL_8
+ * @arg @ref ADC_CHANNEL_9
+ * @arg @ref ADC_CHANNEL_10
+ * @arg @ref ADC_CHANNEL_11
+ * @arg @ref ADC_CHANNEL_12
+ * @arg @ref ADC_CHANNEL_13
+ * @arg @ref ADC_CHANNEL_14
+ * @arg @ref ADC_CHANNEL_15
+ * @arg @ref ADC_CHANNEL_16
+ * @arg @ref ADC_CHANNEL_17
+ * @arg @ref ADC_CHANNEL_18
+ * @arg @ref ADC_CHANNEL_VREFINT (1)
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref ADC_CHANNEL_VBAT (1)
+ * @arg @ref ADC_CHANNEL_DAC1CH1_ADC4 (2)
+ * @arg @ref ADC_CHANNEL_DAC1CH2_ADC4 (2)
+ * @arg @ref ADC4_CHANNEL_TEMPSENSOR (2)
+ * @arg @ref ADC4_CHANNEL_VBAT (2)
+ * @arg @ref ADC_CHANNEL_VCORE (2)
+ *
+ * (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.\n
+ * (2) On STM32U5, parameter available only on ADC instance: ADC4.\n
+ * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).\n
+ * (1, 2) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ */
+#define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
+ __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))
+
+/**
+ * @brief Helper macro to determine whether the selected channel
+ * corresponds to literal definitions of driver.
+ * @note The different literal definitions of ADC channels are:
+ * - ADC internal channel:
+ * ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...
+ * - ADC external channel (channel connected to a GPIO pin):
+ * ADC_CHANNEL_1, ADC_CHANNEL_2, ...
+ * @note The channel parameter must be a value defined from literal
+ * definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
+ * ADC_CHANNEL_TEMPSENSOR, ...),
+ * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...),
+ * must not be a value from functions where a channel number is
+ * returned from ADC registers,
+ * because internal and external channels share the same channel
+ * number in ADC registers. The differentiation is made only with
+ * parameters definitions of driver.
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref ADC_CHANNEL_0 (3)
+ * @arg @ref ADC_CHANNEL_1 (3)
+ * @arg @ref ADC_CHANNEL_2 (3)
+ * @arg @ref ADC_CHANNEL_3 (3)
+ * @arg @ref ADC_CHANNEL_4 (3)
+ * @arg @ref ADC_CHANNEL_5 (3)
+ * @arg @ref ADC_CHANNEL_6
+ * @arg @ref ADC_CHANNEL_7
+ * @arg @ref ADC_CHANNEL_8
+ * @arg @ref ADC_CHANNEL_9
+ * @arg @ref ADC_CHANNEL_10
+ * @arg @ref ADC_CHANNEL_11
+ * @arg @ref ADC_CHANNEL_12
+ * @arg @ref ADC_CHANNEL_13
+ * @arg @ref ADC_CHANNEL_14
+ * @arg @ref ADC_CHANNEL_15
+ * @arg @ref ADC_CHANNEL_16
+ * @arg @ref ADC_CHANNEL_17
+ * @arg @ref ADC_CHANNEL_18
+ * @arg @ref ADC_CHANNEL_VREFINT (1)
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref ADC_CHANNEL_VBAT (1)
+ * @arg @ref ADC_CHANNEL_DAC1CH1_ADC4 (2)
+ * @arg @ref ADC_CHANNEL_DAC1CH2_ADC4 (2)
+ * @arg @ref ADC4_CHANNEL_TEMPSENSOR (2)
+ * @arg @ref ADC4_CHANNEL_VBAT (2)
+ * @arg @ref ADC_CHANNEL_VCORE (2)
+ *
+ * (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.\n
+ * (2) On STM32U5, parameter available only on ADC instance: ADC4.\n
+ * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).
+ * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel
+ * (channel connected to a GPIO pin).
+ * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
+ */
+#define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
+ __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))
+
+/**
+ * @brief Helper macro to convert a channel defined from parameter
+ * definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
+ * ADC_CHANNEL_TEMPSENSOR, ...),
+ * to its equivalent parameter definition of a ADC external channel
+ * (ADC_CHANNEL_1, ADC_CHANNEL_2, ...).
+ * @note The channel parameter can be, additionally to a value
+ * defined from parameter definition of a ADC internal channel
+ * (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...),
+ * a value defined from parameter definition of
+ * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
+ * or a value from functions where a channel number is returned
+ * from ADC registers.
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref ADC_CHANNEL_0 (3)
+ * @arg @ref ADC_CHANNEL_1 (3)
+ * @arg @ref ADC_CHANNEL_2 (3)
+ * @arg @ref ADC_CHANNEL_3 (3)
+ * @arg @ref ADC_CHANNEL_4 (3)
+ * @arg @ref ADC_CHANNEL_5 (3)
+ * @arg @ref ADC_CHANNEL_6
+ * @arg @ref ADC_CHANNEL_7
+ * @arg @ref ADC_CHANNEL_8
+ * @arg @ref ADC_CHANNEL_9
+ * @arg @ref ADC_CHANNEL_10
+ * @arg @ref ADC_CHANNEL_11
+ * @arg @ref ADC_CHANNEL_12
+ * @arg @ref ADC_CHANNEL_13
+ * @arg @ref ADC_CHANNEL_14
+ * @arg @ref ADC_CHANNEL_15
+ * @arg @ref ADC_CHANNEL_16
+ * @arg @ref ADC_CHANNEL_17
+ * @arg @ref ADC_CHANNEL_18
+ * @arg @ref ADC_CHANNEL_VREFINT (1)
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref ADC_CHANNEL_VBAT (1)
+ * @arg @ref ADC_CHANNEL_DAC1CH1_ADC4 (2)
+ * @arg @ref ADC_CHANNEL_DAC1CH2_ADC4 (2)
+ * @arg @ref ADC4_CHANNEL_TEMPSENSOR (2)
+ * @arg @ref ADC4_CHANNEL_VBAT (2)
+ * @arg @ref ADC_CHANNEL_VCORE (2)
+ *
+ * (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.\n
+ * (2) On STM32U5, parameter available only on ADC instance: ADC4.
+ * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).\n
+ * @retval Returned value can be one of the following values:
+ * @arg @ref ADC_CHANNEL_0
+ * @arg @ref ADC_CHANNEL_1
+ * @arg @ref ADC_CHANNEL_2
+ * @arg @ref ADC_CHANNEL_3
+ * @arg @ref ADC_CHANNEL_4
+ * @arg @ref ADC_CHANNEL_5
+ * @arg @ref ADC_CHANNEL_6
+ * @arg @ref ADC_CHANNEL_7
+ * @arg @ref ADC_CHANNEL_8
+ * @arg @ref ADC_CHANNEL_9
+ * @arg @ref ADC_CHANNEL_10
+ * @arg @ref ADC_CHANNEL_11
+ * @arg @ref ADC_CHANNEL_12
+ * @arg @ref ADC_CHANNEL_13
+ * @arg @ref ADC_CHANNEL_14
+ * @arg @ref ADC_CHANNEL_15
+ * @arg @ref ADC_CHANNEL_16
+ * @arg @ref ADC_CHANNEL_17
+ * @arg @ref ADC_CHANNEL_18
+ */
+#define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
+ __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))
+
+/**
+ * @brief Helper macro to determine whether the internal channel
+ * selected is available on the ADC instance selected.
+ * @note The channel parameter must be a value defined from parameter
+ * definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
+ * ADC_CHANNEL_TEMPSENSOR, ...),
+ * must not be a value defined from parameter definition of
+ * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
+ * or a value from functions where a channel number is
+ * returned from ADC registers,
+ * because internal and external channels share the same channel
+ * number in ADC registers. The differentiation is made only with
+ * parameters definitions of driver.
+ * @param __ADC_INSTANCE__ ADC instance
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref ADC_CHANNEL_VREFINT (1)
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref ADC_CHANNEL_VBAT (1)
+ * @arg @ref ADC_CHANNEL_DAC1CH1_ADC4 (2)
+ * @arg @ref ADC_CHANNEL_DAC1CH2_ADC4 (2)
+ * @arg @ref ADC4_CHANNEL_TEMPSENSOR (2)
+ * @arg @ref ADC4_CHANNEL_VBAT (2)
+ * @arg @ref ADC_CHANNEL_VCORE (2)
+ *
+ * (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.\n
+ * (2) On STM32U5, parameter available only on ADC instance: ADC4.\n
+ * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
+ * Value "1" if the internal channel selected is available on the ADC instance selected.
+ */
+#define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
+ __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Helper macro to get the ADC multimode conversion data of ADC master
+ * or ADC slave from raw value with both ADC conversion data concatenated.
+ * @note This macro is intended to be used when multimode transfer by DMA
+ * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
+ * In this case the transferred data need to processed with this macro
+ * to separate the conversion data of ADC master and ADC slave.
+ * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_MASTER
+ * @arg @ref LL_ADC_MULTI_SLAVE
+ * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+#define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
+ __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__))
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @brief Helper macro to select the ADC common instance
+ * to which is belonging the selected ADC instance.
+ * @note ADC common register instance can be used for:
+ * - Set parameters common to several ADC instances
+ * - Multimode (for devices with several ADC instances)
+ * Refer to functions having argument "ADCxy_COMMON" as parameter.
+ * @param __ADCx__ ADC instance
+ * @retval ADC common register instance
+ */
+#define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \
+ __LL_ADC_COMMON_INSTANCE((__ADCx__))
+
+/**
+ * @brief Helper macro to check if all ADC instances sharing the same
+ * ADC common instance are disabled.
+ * @note This check is required by functions with setting conditioned to
+ * ADC state:
+ * All ADC instances of the ADC common group must be disabled.
+ * Refer to functions having argument "ADCxy_COMMON" as parameter.
+ * @note On devices with only 1 ADC common instance, parameter of this macro
+ * is useless and can be ignored (parameter kept for compatibility
+ * with devices featuring several ADC common instances).
+ * @param __ADCXY_COMMON__ ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Value "0" if all ADC instances sharing the same ADC common instance
+ * are disabled.
+ * Value "1" if at least one ADC instance sharing the same ADC common instance
+ * is enabled.
+ */
+#define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
+ __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))
+
+/**
+ * @brief Helper macro to define the ADC conversion data full-scale digital
+ * value corresponding to the selected ADC resolution.
+ * @note ADC conversion data full-scale corresponds to voltage range
+ * determined by analog voltage references Vref+ and Vref-
+ * (refer to reference manual).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref ADC_RESOLUTION_14B
+ * @arg @ref ADC_RESOLUTION_12B
+ * @arg @ref ADC_RESOLUTION_10B
+ * @arg @ref ADC_RESOLUTION_8B
+ * @arg @ref ADC_RESOLUTION_6B
+ *
+ * (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.\n
+ * (2) On STM32U5, parameter available only on ADC instance: ADC4.\n
+ * @retval ADC conversion data full-scale digital value
+ */
+#define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
+ __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))
+
+/**
+ * @brief Helper macro to convert the ADC conversion data from
+ * a resolution to another resolution.
+ * @param __ADCx__ ADC instance
+ * @param __DATA__ ADC conversion data to be converted
+ * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_RESOLUTION_14B (1)
+ * @arg @ref ADC_RESOLUTION_12B (1)(2)
+ * @arg @ref ADC_RESOLUTION_10B (1)(2)
+ * @arg @ref ADC_RESOLUTION_8B (1)(2)
+ * @arg @ref ADC_RESOLUTION_6B (2)
+ *
+ * (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.\n
+ * (2) On STM32U5, parameter available only on ADC instance: ADC4.\n
+ * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_RESOLUTION_14B (1)
+ * @arg @ref ADC_RESOLUTION_12B (1)(2)
+ * @arg @ref ADC_RESOLUTION_10B (1)(2)
+ * @arg @ref ADC_RESOLUTION_8B (1)(2)
+ * @arg @ref ADC_RESOLUTION_6B (2)
+ *
+ * (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.\n
+ * (2) On STM32U5, parameter available only on ADC instance: ADC4.\n
+ * @retval ADC conversion data to the requested resolution
+ */
+#define __HAL_ADC_CONVERT_DATA_RESOLUTION(__ADCx__, __DATA__,\
+ __ADC_RESOLUTION_CURRENT__,\
+ __ADC_RESOLUTION_TARGET__) \
+__LL_ADC_CONVERT_DATA_RESOLUTION((__ADCx__), (__DATA__),\
+ (__ADC_RESOLUTION_CURRENT__),\
+ (__ADC_RESOLUTION_TARGET__))
+
+/**
+ * @brief Helper macro to calculate the voltage (unit: mVolt)
+ * corresponding to a ADC conversion data (unit: digital value).
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @param __ADCx__ ADC instance
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+ * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
+ * (unit: digital value).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref ADC_RESOLUTION_14B (1)
+ * @arg @ref ADC_RESOLUTION_12B (1)(2)
+ * @arg @ref ADC_RESOLUTION_10B (1)(2)
+ * @arg @ref ADC_RESOLUTION_8B (1)(2)
+ * @arg @ref ADC_RESOLUTION_6B (2)
+ *
+ * (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.\n
+ * (2) On STM32U5, parameter available only on ADC instance: ADC4.\n
+ * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+ */
+#define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__ADCx__, __VREFANALOG_VOLTAGE__, \
+ __ADC_DATA__, \
+ __ADC_RESOLUTION__) \
+__LL_ADC_CALC_DATA_TO_VOLTAGE((__ADCx__), (__VREFANALOG_VOLTAGE__), \
+ (__ADC_DATA__), \
+ (__ADC_RESOLUTION__))
+
+/**
+ * @brief Helper macro to calculate analog reference voltage (Vref+)
+ * (unit: mVolt) from ADC conversion data of internal voltage
+ * reference VrefInt.
+ * @note Computation is using VrefInt calibration value
+ * stored in system memory for each device during production.
+ * @note This voltage depends on user board environment: voltage level
+ * connected to pin Vref+.
+ * On devices with small package, the pin Vref+ is not present
+ * and internally bonded to pin Vdda.
+ * @note On this STM32 series, calibration data of internal voltage reference
+ * VrefInt corresponds to a resolution of 12 bits,
+ * this is the recommended ADC resolution to convert voltage of
+ * internal voltage reference VrefInt.
+ * Otherwise, this macro performs the processing to scale
+ * ADC conversion data to 12 bits.
+ * @param __ADCx__ ADC instance
+ * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
+ * of internal voltage reference VrefInt (unit: digital value).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref ADC_RESOLUTION_14B (1)
+ * @arg @ref ADC_RESOLUTION_12B (1)(2)
+ * @arg @ref ADC_RESOLUTION_10B (1)(2)
+ * @arg @ref ADC_RESOLUTION_8B (1)(2)
+ * @arg @ref ADC_RESOLUTION_6B (2)
+ *
+ * (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.\n
+ * (2) On STM32U5, parameter available only on ADC instance: ADC4.\n
+ * @retval Analog reference voltage (unit: mV)
+ */
+#define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__ADCx__, __VREFINT_ADC_DATA__, \
+ __ADC_RESOLUTION__) \
+__LL_ADC_CALC_VREFANALOG_VOLTAGE((__ADCx__),(__VREFINT_ADC_DATA__), \
+ (__ADC_RESOLUTION__))
+
+/**
+ * @brief Helper macro to calculate the temperature (unit: degree Celsius)
+ * from ADC conversion data of internal temperature sensor.
+ * @note Computation is using temperature sensor calibration values
+ * stored in system memory for each device during production.
+ * @note Calculation formula:
+ * Temperature = ((TS_ADC_DATA - TS_CAL1)
+ * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
+ * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
+ * with TS_ADC_DATA = temperature sensor raw data measured by ADC
+ * Avg_Slope = (TS_CAL2 - TS_CAL1)
+ * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
+ * TS_CAL1 = equivalent TS_ADC_DATA at temperature
+ * TEMP_DEGC_CAL1 (calibrated in factory)
+ * TS_CAL2 = equivalent TS_ADC_DATA at temperature
+ * TEMP_DEGC_CAL2 (calibrated in factory)
+ * Caution: Calculation relevancy under reserve that calibration
+ * parameters are correct (address and data).
+ * To calculate temperature using temperature sensor
+ * datasheet typical values (generic values less, therefore
+ * less accurate than calibrated values),
+ * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
+ * @note As calculation input, the analog reference voltage (Vref+) must be
+ * defined as it impacts the ADC LSB equivalent voltage.
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @note On this STM32 series, calibration data of temperature sensor
+ * corresponds to a resolution of 12 bits,
+ * this is the recommended ADC resolution to convert voltage of
+ * temperature sensor.
+ * Otherwise, this macro performs the processing to scale
+ * ADC conversion data to 12 bits.
+ * @param __ADCx__ ADC instance
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+ * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
+ * temperature sensor (unit: digital value).
+ * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
+ * sensor voltage has been measured.
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_RESOLUTION_14B (1)
+ * @arg @ref ADC_RESOLUTION_12B (1)(2)
+ * @arg @ref ADC_RESOLUTION_10B (1)(2)
+ * @arg @ref ADC_RESOLUTION_8B (1)(2)
+ * @arg @ref ADC_RESOLUTION_6B (2)
+ *
+ * (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.\n
+ * (2) On STM32U5, parameter available only on ADC instance: ADC4.\n
+ * @retval Temperature (unit: degree Celsius)
+ */
+#define __HAL_ADC_CALC_TEMPERATURE(__ADCx__, __VREFANALOG_VOLTAGE__,\
+ __TEMPSENSOR_ADC_DATA__,\
+ __ADC_RESOLUTION__) \
+__LL_ADC_CALC_TEMPERATURE((__ADCx__), (__VREFANALOG_VOLTAGE__),\
+ (__TEMPSENSOR_ADC_DATA__),\
+ (__ADC_RESOLUTION__))
+
+/**
+ * @brief Helper macro to calculate the temperature (unit: degree Celsius)
+ * from ADC conversion data of internal temperature sensor.
+ * @note Computation is using temperature sensor typical values
+ * (refer to device datasheet).
+ * @note Calculation formula:
+ * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
+ * / Avg_Slope + CALx_TEMP
+ * with TS_ADC_DATA = temperature sensor raw data measured by ADC
+ * (unit: digital value)
+ * Avg_Slope = temperature sensor slope
+ * (unit: uV/Degree Celsius)
+ * TS_TYP_CALx_VOLT = temperature sensor digital value at
+ * temperature CALx_TEMP (unit: mV)
+ * Caution: Calculation relevancy under reserve the temperature sensor
+ * of the current device has characteristics in line with
+ * datasheet typical values.
+ * If temperature sensor calibration values are available on
+ * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
+ * temperature calculation will be more accurate using
+ * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
+ * @note As calculation input, the analog reference voltage (Vref+) must be
+ * defined as it impacts the ADC LSB equivalent voltage.
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @note ADC measurement data must correspond to a resolution of 12bits
+ * (full scale digital value 4095). If not the case, the data must be
+ * preliminarily rescaled to an equivalent resolution of 12 bits.
+ * @param __ADCx__ ADC instance
+ * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value
+ * (unit: uV/DegCelsius).
+ * On STM32U5, refer to device datasheet parameter "Avg_Slope".
+ * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value
+ * (at temperature and Vref+ defined in parameters below) (unit: mV).
+ * Refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
+ * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage
+ * (see parameter above) is corresponding (unit: mV)
+ * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
+ * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
+ * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_RESOLUTION_14B (1)
+ * @arg @ref ADC_RESOLUTION_12B (1)(2)
+ * @arg @ref ADC_RESOLUTION_10B (1)(2)
+ * @arg @ref ADC_RESOLUTION_8B (1)(2)
+ * @arg @ref ADC_RESOLUTION_6B (2)
+ *
+ * (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.\n
+ * (2) On STM32U5, parameter available only on ADC instance: ADC4.\n
+ * @retval Temperature (unit: degree Celsius)
+ */
+#define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__ADCx__, __TEMPSENSOR_TYP_AVGSLOPE__,\
+ __TEMPSENSOR_TYP_CALX_V__,\
+ __TEMPSENSOR_CALX_TEMP__,\
+ __VREFANALOG_VOLTAGE__,\
+ __TEMPSENSOR_ADC_DATA__,\
+ __ADC_RESOLUTION__) \
+__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__ADCx__), (__TEMPSENSOR_TYP_AVGSLOPE__),\
+ (__TEMPSENSOR_TYP_CALX_V__),\
+ (__TEMPSENSOR_CALX_TEMP__),\
+ (__VREFANALOG_VOLTAGE__),\
+ (__TEMPSENSOR_ADC_DATA__),\
+ (__ADC_RESOLUTION__))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Include ADC HAL Extended module */
+#include "stm32u5xx_hal_adc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup ADC_Exported_Functions_Group1
+ * @brief Initialization and Configuration functions
+ * @{
+ */
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
+void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc);
+void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc);
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/* Callbacks Register/UnRegister functions ***********************************/
+HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
+ pADC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Exported_Functions_Group2
+ * @brief IO operation functions
+ * @{
+ */
+/* IO operation functions *****************************************************/
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout);
+
+/* Non-blocking mode: Interruption */
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc);
+
+/* Non-blocking mode: DMA */
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, const uint32_t *pData, uint32_t Length);
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc);
+
+/* ADC retrieve conversion value intended to be used with polling or interruption */
+uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc);
+
+/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc);
+void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc);
+void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc);
+void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc);
+void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *pConfig);
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig);
+
+/**
+ * @}
+ */
+
+/* Peripheral State functions *************************************************/
+/** @addtogroup ADC_Exported_Functions_Group4
+ * @{
+ */
+uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc);
+uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions -----------------------------------------------------------*/
+/** @addtogroup ADC_Private_Functions ADC Private Functions
+ * @{
+ */
+HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup);
+HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc);
+void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
+void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
+void ADC_DMAError(DMA_HandleTypeDef *hdma);
+void ADC_ConfigureBoostMode(ADC_HandleTypeDef *hadc);
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32U5xx_HAL_ADC_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_adc_ex.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_adc_ex.h
new file mode 100644
index 00000000..a16a4af1
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_adc_ex.h
@@ -0,0 +1,1282 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_adc_ex.h
+ * @author MCD Application Team
+ * @brief Header file of ADC HAL extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_ADC_EX_H
+#define STM32U5xx_HAL_ADC_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup ADCEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ADCEx_Exported_Types ADC Extended Exported Types
+ * @{
+ */
+
+/**
+ * @brief ADC Injected Conversion Oversampling structure definition
+ */
+typedef struct
+{
+ uint32_t Ratio; /*!< Configures the oversampling ratio.
+ This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
+
+ uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
+ This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
+} ADC_InjOversamplingTypeDef;
+
+/**
+ * @brief Structure definition of ADC group injected and ADC channel affected to ADC group injected
+ * @note Parameters of this structure are shared within 2 scopes:
+ * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff,
+ * InjectedOffsetNumber, InjectedOffset
+ * - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion,
+ * InjectedDiscontinuousConvMode, AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv,
+ * ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling.
+ * @note The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
+ * ADC state can be either:
+ * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter
+ * 'InjectedSingleDiff')
+ * - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling':
+ * ADC enabled without conversion on going on injected group.
+ * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv':
+ * ADC enabled without conversion on going on regular and injected groups.
+ * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv',
+ * 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going on ADC groups
+ * regular and injected.
+ * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+ * without error reporting (as it can be the expected behavior in case of intended action to update another
+ * parameter (which fulfills the ADC state condition) on the fly).
+ */
+typedef struct
+{
+ uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected.
+ This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
+ Note: Depending on devices and ADC instances, some channels may not be
+ available on device package pins. Refer to device datasheet for channels
+ availability. */
+
+ uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer.
+ This parameter must be a value of @ref ADC_INJ_SEQ_RANKS.
+ Note: to disable a channel or change order of conversion sequencer,
+ rank containing a previous channel setting can be overwritten by
+ the new channel setting (or parameter number of
+ conversions adjusted) */
+
+ uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
+ Unit: ADC clock cycles.
+ Conversion time is the addition of sampling time and processing time
+ (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits,
+ 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
+ This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME.
+ Caution: This parameter applies to a channel that can be used in a
+ regular and/or injected group. It overwrites the last setting.
+ Note: In case of usage of internal measurement channels
+ (VrefInt/Vbat/TempSensor), sampling time constraints must be
+ respected (sampling time can be adjusted in function of ADC clock
+ frequency and sampling time setting);
+ Refer to device datasheet for timings values. */
+
+ uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input.
+ In differential mode: Differential measurement is between the selected
+ channel 'i' (positive input) and channel 'i+1' (negative input).
+ Only channel 'i' has to be configured, channel 'i+1' is configured
+ automatically.
+ This parameter must be a value of:
+ @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING.
+ Caution: This parameter applies to a channel that can be used in a
+ regular and/or injected group.
+ It overwrites the last setting.
+ Note: Refer to Reference Manual to ensure the selected channel is
+ available in differential mode.
+ Note: When configuring a channel 'i' in differential mode, the channel
+ 'i+1' is not usable separately.
+ Note: This parameter must be modified when ADC is disabled (before ADC
+ start conversion or after ADC stop conversion).
+ If ADC is enabled, this parameter setting is bypassed without error
+ reporting (as it can be the expected behavior in case of another parameter
+ update on the fly) */
+
+ uint32_t InjectedOffsetNumber; /*!< Selects the offset number.
+ This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB.
+ Caution: Only one offset is allowed per channel. This parameter overwrites
+ the last setting. */
+
+ uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data.
+ Offset value must be a positive number.
+ Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter
+ must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF,
+ 0xFF or 0x3F respectively.
+ Note: This parameter must be modified when no conversion is on going on
+ both regular and injected groups (ADC disabled, or ADC enabled
+ without continuous mode or external trigger that could launch a
+ conversion). */
+
+ FunctionalState InjectedOffsetSignedSaturation; /*!< Specifies whether the Signed saturation feature is used or not.
+ This parameter is applied only for 14-bit or 8-bit resolution.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t InjectedOffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added
+ (positive sign) from or to the raw converted data.
+ This parameter can be a value of @ref ADCEx_OffsetSign.
+ Note:
+ - This parameter must be modified when no conversion is on going on both
+ regular and injected groups (ADC disabled, or ADC enabled without
+ continuous mode or external trigger that could launch a conversion).
+ - This parameter is specific to ADC1 only. */
+
+ FunctionalState InjectedOffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow.
+ This parameter value can be ENABLE or DISABLE.
+ Note:
+ - This parameter must be modified when no conversion is on going
+ on both regular and injected groups (ADC disabled, or ADC
+ enabled without continuous mode or external trigger that could
+ launch a conversion).
+ - This parameter is specific to ADC1 only. */
+
+
+ uint32_t InjectedLeftBitShift; /*!< Configures the left shifting applied to the final result with or without
+ oversampling.
+ This parameter can be a value of @ref ADCEx_Left_Bit_Shift */
+
+ uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within
+ the ADC group injected sequencer.
+ To use the injected group sequencer and convert several ranks,
+ parameter 'ScanConvMode' must be enabled.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 4.
+ Caution: this setting impacts the entire injected group.
+ Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the
+ configuration of other channels previously set. */
+
+ FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected
+ is performed in Complete-sequence/Discontinuous-sequence
+ (main sequence subdivided in successive parts).
+ Discontinuous mode is used only if sequencer is enabled
+ (parameter 'ScanConvMode').
+ If sequencer is disabled, this parameter is discarded.
+ Discontinuous mode can be enabled only if continuous
+ mode is disabled.
+ This parameter can be set to ENABLE or DISABLE.
+ Note: This parameter must be modified when ADC is disabled
+ (before ADC start conversion or after ADC stop conversion).
+ Note: For injected group, discontinuous mode converts the
+ sequence channel by channel (discontinuous length
+ fixed to 1 rank).
+ Caution: this setting impacts the entire injected group.
+ Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the
+ configuration of other channels previously set. */
+
+ FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion
+ after regular one
+ This parameter can be set to ENABLE or DISABLE.
+ Note: To use Automatic injected conversion, discontinuous mode must be
+ disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode'
+ set to DISABLE)
+ Note: To use Automatic injected conversion, injected group external triggers
+ must be disabled ('ExternalTrigInjecConv' set to
+ ADC_INJECTED_SOFTWARE_START)
+ Note: In case of DMA used with regular group: if DMA configured in normal
+ mode (single shot) JAUTO will be stopped upon DMA transfer complete.
+ To maintain JAUTO always enabled,
+ DMA must be configured in circular mode.
+ Caution: this setting impacts the entire injected group.
+ Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration
+ of other channels previously set. */
+
+ uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of
+ injected group.
+ If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled
+ and software trigger is used instead.
+ This parameter can be a value of @ref ADC_injected_external_trigger_source.
+ Caution: this setting impacts the entire injected group. Therefore, call of
+ HAL_ADCEx_InjectedConfigChannel() to configure a channel on
+ injected group can impact the configuration of other channels
+ previously set. */
+
+ uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group.
+ This parameter can be a value of @ref ADC_injected_external_trigger_edge.
+ If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter
+ is discarded.
+ Caution: this setting impacts the entire injected group.
+ Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a
+ channel on injected group can impact the configuration of other
+ channels previously set. */
+
+ FunctionalState InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled.
+ This parameter can be set to ENABLE or DISABLE.
+ Note: This parameter can be modified only if there is no conversion is
+ ongoing (both ADSTART and JADSTART cleared). */
+
+ ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters.
+ Caution: this setting overwrites the previous oversampling
+ configuration if oversampling already enabled.
+ Note: This parameter can be modified only if there is no
+ conversion is ongoing (both ADSTART and
+ JADSTART cleared).*/
+} ADC_InjectionConfTypeDef;
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Structure definition of ADC multimode
+ * @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs
+ * state (both Master and Slave ADCs).
+ * Both Master and Slave ADCs must be disabled.
+ */
+typedef struct
+{
+ uint32_t Mode; /*!< Configures the ADC to operate in independent or multimode.
+ This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */
+
+ uint32_t DualModeData; /*!< Configures the Dual ADC Mode Data Format:
+ This parameter can be a value of @ref ADCEx_Dual_Mode_Data_Format */
+
+ uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
+ This parameter can be a value of @ref ADC_HAL_EC_MULTI_TWOSMP_DELAY.
+ Delay range depends on selected resolution:
+ from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits,
+ from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits. */
+} ADC_MultiModeTypeDef;
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants
+ * @{
+ */
+
+/** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source
+ * @{
+ */
+/* ADC group regular trigger sources for all ADC instances */
+#define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /*!< Software triggers injected group conversion start */
+#define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_LPTIM1_CH2 (LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2) /*!< ADC group injected conversion trigger from external peripheral: LPTIM1 CH2 event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_LPTIM2_CH2 (LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2) /*!< ADC group injected conversion trigger from external peripheral: LPTIM2 CH2 event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_LPTIM3_CH1 (LL_ADC_INJ_TRIG_EXT_LPTIM3_CH1) /*!< ADC group injected conversion trigger from external peripheral: LPTIM3 CH1 event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_LPTIM4_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM4_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM4 OUT event. Trigger edge set to rising edge (default setting). */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected)
+ * @{
+ */
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions hardware trigger detection disabled */
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
+ * @{
+ */
+#define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
+#define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_OFFSET_NB ADC instance - Offset number
+ * @{
+ */
+#define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected ADC channel */
+#define ADC_OFFSET_1 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
+#define ADC_OFFSET_2 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
+#define ADC_OFFSET_3 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
+#define ADC_OFFSET_4 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
+/**
+ * @}
+ */
+/** @defgroup ADCEx_OffsetSign ADC Extended Offset Sign
+ * @{
+ */
+#define ADC_OFFSET_SIGN_NEGATIVE LL_ADC_OFFSET_SIGN_NEGATIVE /*!< Offset sign negative, offset is subtracted */
+#define ADC_OFFSET_SIGN_POSITIVE LL_ADC_OFFSET_SIGN_POSITIVE /*!< Offset sign positive, offset is added */
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
+ * @{
+ */
+#define ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */
+#define ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */
+#define ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */
+#define ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */
+/**
+ * @}
+ */
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/** @defgroup ADC_HAL_EC_MULTI_MODE Multimode - Mode
+ * @{
+ */
+#define ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT) /*!< ADC dual mode disabled (ADC independent mode) */
+#define ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT) /*!< ADC dual mode enabled: group regular simultaneous */
+#define ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL) /*!< ADC dual mode enabled: Combined group regular interleaved */
+#define ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT) /*!< ADC dual mode enabled: group injected simultaneous */
+#define ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
+#define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
+#define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
+#define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION Multimode - DMA transfer mode depending on ADC resolution
+ * @{
+ */
+#define ADC_DMAACCESSMODE_DISABLED (0x00000000UL) /*!< DMA multimode disabled: each ADC uses its own DMA channel */
+#define ADC_DMAACCESSMODE_12_10_BITS (ADC_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution */
+#define ADC_DMAACCESSMODE_8_6_BITS (ADC_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution */
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Dual_Mode_Data_Format ADC Extended Dual Mode Data Formatting
+ * @{
+ */
+#define ADC_DUALMODEDATAFORMAT_DISABLED (0x00000000UL) /*!< Dual ADC mode without data packing: ADCx_CDR and ADCx_CDR2 registers not used */
+#define ADC_DUALMODEDATAFORMAT_32_10_BITS (ADC_CCR_DAMDF_1) /*!< Data formatting mode for 32 down to 10-bit resolution */
+#define ADC_DUALMODEDATAFORMAT_8_BITS ((ADC_CCR_DAMDF_0 |ADC_CCR_DAMDF_1)) /*!< Data formatting mode for 8-bit resolution */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
+ * @{
+ */
+#define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */
+#define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */
+
+/**
+ * @}
+ */
+
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups
+ * @{
+ */
+#define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */
+#define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on all STM32 devices)*/
+#define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_CFGR_fields ADCx CFGR fields
+ * @{
+ */
+#define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\
+ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\
+ ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\
+ ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\
+ ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\
+ ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN )
+/**
+ * @}
+ */
+
+/** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields
+ * @{
+ */
+#define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\
+ ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\
+ ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\
+ ADC_SMPR1_SMP0)
+/**
+ * @}
+ */
+#if defined(ADC4_CFGR1_DMAEN)
+/** @defgroup ADC4_CFGR_fields_2 ADC4 CFGR sub fields
+ * @{
+ */
+/* ADC4_CFGR1 fields of parameters that can be updated when no conversion
+ (neither regular nor injected) is on-going */
+#define ADC4_CFGR_FIELDS_2 ((ADC4_CFGR1_DMACFG | ADC4_CFGR1_WAIT))
+/**
+ * @}
+ */
+#endif /* ADC4_CFGR1_DMAEN */
+
+/** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields
+ * @{
+ */
+/* ADC_CFGR1 fields of parameters that can be updated when no conversion
+ (neither regular nor injected) is on-going */
+#define ADC_CFGR_FIELDS_2 ((uint32_t)(ADC_CFGR1_DMNGT | ADC_CFGR1_AUTDLY))
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/** @defgroup ADCEx_Exported_Macro ADC Extended Exported Macros
+ * @{
+ */
+
+/** @brief Force ADC instance in multimode mode independent (multimode disable).
+ * @note This macro must be used only in case of transition from multimode
+ * to mode independent and in case of unknown previous state,
+ * to ensure ADC configuration is in mode independent.
+ * @note Standard way of multimode configuration change is done from
+ * HAL ADC handle of ADC master using function
+ * "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )".
+ * Usage of this macro is not the Standard way of multimode
+ * configuration and can lead to have HAL ADC handles status
+ * misaligned. Usage of this macro must be limited to cases
+ * mentioned above.
+ * @param __HANDLE__ ADC handle.
+ * @retval None
+ */
+#define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__) \
+ LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT)
+
+/**
+ * @}
+ */
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros
+ * @{
+ */
+/* Macro reserved for internal HAL driver usage, not intended to be used in */
+/* code of final user. */
+
+/**
+ * @brief Test if conversion trigger of injected group is software start
+ * or external trigger.
+ * @param __HANDLE__ ADC handle.
+ * @retval SET (software start) or RESET (external trigger).
+ */
+#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
+ (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL)
+
+/**
+ * @brief Check if conversion is on going on regular or injected groups.
+ * @param __HANDLE__ ADC handle.
+ * @retval SET (conversion is on going) or RESET (no conversion is on going).
+ */
+#define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__) \
+ (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == 0UL \
+ ) ? RESET : SET)
+
+/**
+ * @brief Check if conversion is on going on injected group.
+ * @param __HANDLE__ ADC handle.
+ * @retval Value "0" (no conversion is on going) or value "1" (conversion is on going)
+ */
+#define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) \
+ (LL_ADC_INJ_IsConversionOngoing((__HANDLE__)->Instance))
+
+/**
+ * @brief Check whether or not ADC is independent.
+ * @param __HANDLE__ ADC handle.
+ * @note When multimode feature is not available, the macro always returns SET.
+ * @retval SET (ADC is independent) or RESET (ADC is not).
+ */
+#define ADC_IS_INDEPENDENT(__HANDLE__) \
+ ( ( ( ((__HANDLE__)->Instance) == ADC3) \
+ )? \
+ SET \
+ : \
+ RESET \
+ )
+
+/**
+ * @brief Set the selected injected Channel rank.
+ * @param __CHANNELNB__ Channel number.
+ * @param __RANKNB__ Rank number.
+ * @retval None
+ */
+#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__)& ADC_CHANNEL_ID_NUMBER_MASK)\
+ >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__)\
+ & ADC_INJ_RANK_ID_JSQR_MASK))
+
+
+/**
+ * @brief Configure ADC discontinuous conversion mode for injected group
+ * @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode.
+ * @retval None
+ */
+#define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__)\
+ ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR1_JDISCEN_Pos)
+
+/**
+ * @brief Configure ADC discontinuous conversion mode for regular group
+ * @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode.
+ * @retval None
+ */
+#define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR1_DISCEN_Pos)
+
+/**
+ * @brief Configure the number of discontinuous conversions for regular group.
+ * @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions.
+ * @retval None
+ */
+#define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__)\
+ (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR1_DISCNUM_Pos)
+
+/**
+ * @brief Configure the ADC auto delay mode.
+ * @param __AUTOWAIT__ Auto delay bit enable or disable.
+ * @retval None
+ */
+#define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC4_CFGR1_WAIT_Pos)
+
+/**
+ * @brief Enable the ADC auto off mode.
+ * @param _AUTOOFF_ Auto off bit enable or disable.
+ * @retval None
+ */
+#define ADC4_CFGR_AUTOOFF(_AUTOOFF_)((_AUTOOFF_) << ADC4_PW_AUTOOFF_Pos)
+
+/**
+ * @brief Configure the ADC auto delay mode.
+ * @param __AUTDLY__ Auto delay bit enable or disable.
+ * @retval None
+ */
+#define ADC_CFGR_AUTODELAY(__AUTDLY__) ((__AUTDLY__) << ADC_CFGR1_AUTDLY_Pos)
+
+/**
+ * @brief Configure ADC continuous conversion mode.
+ * @param __CONTINUOUS_MODE__ Continuous mode.
+ * @retval None
+ */
+#define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR1_CONT_Pos)
+
+/**
+ * @brief Enable the ADC DMA continuous request.
+ * @param __HANDLE__ ADC handle.
+ * @param __DMACONTREQ_MODE__: DMA continuous request mode.
+ * @retval None
+ */
+#define ADC_CFGR_DMACONTREQ(__HANDLE__,__DMACONTREQ_MODE__) \
+ ( (((__HANDLE__)->Instance == ADC1) \
+ )? \
+ ((__DMACONTREQ_MODE__)) \
+ : \
+ ((__DMACONTREQ_MODE__) << 1U) \
+ )
+
+
+/**
+ * @brief Configure the channel number into offset OFRx register.
+ * @param __CHANNEL__ ADC Channel.
+ * @retval None
+ */
+#define ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << ADC_OFR1_OFFSET1_CH_Pos)
+
+/**
+ * @brief Configure the channel number into differential mode selection register.
+ * @param __CHANNEL__ ADC Channel.
+ * @retval None
+ */
+#define ADC_DIFSEL_CHANNEL(__CHANNEL__) (1UL << (__CHANNEL__))
+
+/**
+ * @brief Configure calibration factor in differential mode to be set into calibration register.
+ * @param __CALIBRATION_FACTOR__ Calibration factor value.
+ * @retval None
+ */
+#define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__)\
+ (((__CALIBRATION_FACTOR__)& (ADC_CALFACT_CALFACT_D_Pos >> ADC_CALFACT_CALFACT_D_Pos) )\
+ << ADC_CALFACT_CALFACT_D_Pos)
+
+/**
+ * @brief Calibration factor in differential mode to be retrieved from calibration register.
+ * @param __CALIBRATION_FACTOR__ Calibration factor value.
+ * @retval None
+ */
+#define ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> ADC_CALFACT_CALFACT_D_Pos)
+
+/**
+ * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
+ * @param __THRESHOLD__ Threshold value.
+ * @retval None
+ */
+#define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16UL)
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Configure the ADC DMA continuous request for ADC multimode.
+ * @param __DMACONTREQ_MODE__ DMA continuous request mode.
+ * @retval None
+ */
+#define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos)
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @brief Shift the offset in function of the selected ADC resolution.
+ * @note Offset has to be left-aligned on bit 15, the LSB (right bits) are set to 0
+ * If resolution 14 bits, no shift.
+ * If resolution 12 bits, shift of 2 ranks on the left.
+ * If resolution 10 bits, shift of 4 ranks on the left.
+ * If resolution 8 bits, shift of 6 ranks on the left.
+ * If resolution 6 bits, shift of 8 ranks on the left.
+ * therefore, shift = (14 - resolution) = 14 - (14 - (((RES[2:0]) >> 2)*2))
+ * @param __HANDLE__: ADC handle
+ * @param __OFFSET__: Value to be shifted
+ * @retval None
+ */
+#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \
+ (((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES)>> 2UL)*2UL)))
+
+/**
+ * @brief Shift the AWD1 threshold in function of the selected ADC resolution.
+ * @note Thresholds have to be left-aligned on bit 15, the LSB (right bits) are set to 0.
+ * If resolution 14 bits, no shift.
+ * If resolution 12 bits, shift of 2 ranks on the left.
+ * If resolution 10 bits, shift of 4 ranks on the left.
+ * If resolution 8 bits, shift of 6 ranks on the left.
+ * If resolution 6 bits, shift of 8 ranks on the left.
+ * therefore, shift = (14 - resolution) = 14 - (14- (((RES[2:0]) >> 2)*2))
+ * @param __HANDLE__: ADC handle
+ * @param __THRESHOLD__: Value to be shifted
+ * @retval None
+ */
+#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
+ (((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES)>> 2UL)*2UL)) )
+
+/**
+ * @brief Shift the AWD2 and AWD3 threshold in function of the selected ADC resolution.
+ * @note Thresholds have to be left-aligned on bit 15, the LSB (right bits) are set to 0.
+ * If resolution 16 bits, no shift.
+ * If resolution 14 bits, shift of 2 ranks on the left.
+ * If resolution 12 bits, shift of 4 ranks on the left.
+ * If resolution 10 bits, shift of 6 ranks on the left.
+ * If resolution 8 bits, shift of 8 ranks on the left.
+ * therefore, shift = (16 - resolution) = 16 - (16- (((RES[2:0]) >> 2)*2))
+ * @param __HANDLE__: ADC handle
+ * @param __THRESHOLD__: Value to be shifted
+ * @retval None
+ */
+#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
+ ( ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES)>> 2UL)*2UL)))
+/**
+ * @brief Clear Common Control Register.
+ * @param __HANDLE__ ADC handle.
+ * @retval None
+ */
+/**
+ * @brief Report common register to ADC1 and ADC2
+ * @param __HANDLE__: ADC handle
+ * @retval Common control register
+ */
+#define ADC12_COMMON_REGISTER(__HANDLE__) (ADC12_COMMON)
+/**
+ * @brief Report common register to ADC4
+ * @param __HANDLE__: ADC handle
+ * @retval Common control register
+ */
+#define ADC4_COMMON_REGISTER(__HANDLE__) (ADC4_COMMON)
+/**
+ * @brief Report Master Instance
+ * @param __HANDLE__: ADC handle
+ * @note return same instance if ADC of input handle is independent ADC
+ * @retval Master Instance
+ */
+#define ADC_MASTER_REGISTER(__HANDLE__) \
+ ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC4)) \
+ )? \
+ ((__HANDLE__)->Instance) \
+ : \
+ (ADC1) \
+ )
+
+/**
+ * @brief Check whether or not dual regular conversions are enabled
+ * @param __HANDLE__: ADC handle
+ * @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular
+ * conversions are enabled)
+ */
+#define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__) \
+ ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \
+ )? \
+ ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) && \
+ ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) && \
+ ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) ) \
+ : \
+ RESET \
+ )
+
+/**
+ * @brief Verification of condition for ADC start conversion: ADC must be in non-MultiMode or
+ * MultiMode with handle of ADC master
+ * @param __HANDLE__: ADC handle
+ * @retval SET (non-MultiMode or Master handle) or RESET (handle of Slave ADC in MultiMode)
+ */
+#define ADC12_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
+ ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2) \
+ )? \
+ SET \
+ : \
+ ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == RESET) \
+ )
+
+/**
+ * @brief Verification of condition for ADC start conversion: ADC must be in non-MultiMode or
+ * MultiMode with handle of ADC master
+ * @param __HANDLE__: ADC handle
+ * @retval SET (non-MultiMode or Master handle) or RESET (handle of Slave ADC in MultiMode)
+ */
+#define ADC4_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
+ ( ( ((__HANDLE__)->Instance == ADC4) \
+ )? \
+ SET \
+ : \
+ ((ADC4_COMMON->CCR & ADC_CCR_DUAL) == RESET) \
+ )
+
+/**
+ * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled
+ * @param __HANDLE__: ADC handle
+ * @retval SET (Independent or Master, or Slave without dual regular conversions enabled) or
+ * RESET (Slave ADC with dual regular conversions enabled)
+ */
+
+#define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) \
+ ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC4) \
+ )? \
+ SET \
+ : \
+ ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \
+ ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \
+ ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) ))
+
+/**
+ * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled
+ * @param __HANDLE__: ADC handle
+ * @retval SET (non-MultiMode or Master, or Slave without dual injected conversions enabled) or
+ * RESET (Slave ADC with dual injected conversions enabled)
+ */
+
+#define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) \
+ ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC4) \
+ )? \
+ SET \
+ : \
+ ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \
+ ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT) || \
+ ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) ))
+
+#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) \
+ CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_PRESC | \
+ ADC_CCR_VBATEN | \
+ ADC_CCR_VSENSEEN | \
+ ADC_CCR_VREFEN )
+
+/**
+ * @brief Set handle instance of the ADC slave associated to the ADC master.
+ * @param __HANDLE_MASTER__ ADC master handle.
+ * @param __HANDLE_SLAVE__ ADC slave handle.
+ * @note if __HANDLE_MASTER__ is the handle of a slave ADC (ADC2) or an independent ADC,
+ * __HANDLE_SLAVE__ instance is set to NULL.
+ * @retval None
+ */
+#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \
+ ((((__HANDLE_MASTER__)->Instance == ADC1)) \
+ ? ((__HANDLE_SLAVE__)->Instance = ADC2) \
+ : ((__HANDLE_SLAVE__)->Instance = NULL))
+
+
+/**
+ * @brief Verify the ADC instance connected to the temperature sensor.
+ * @param __HANDLE__ ADC handle.
+ * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
+ */
+#if defined(ADC2)
+#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) ||\
+ (((__HANDLE__)->Instance) == ADC2) ||\
+ (((__HANDLE__)->Instance) == ADC4) )
+#else
+#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) ||\
+ (((__HANDLE__)->Instance) == ADC4) )
+#endif /* ADC2 */
+
+/**
+ * @brief Verify the ADC instance connected to the battery voltage VBAT.
+ * @param __HANDLE__ ADC handle.
+ * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
+ */
+#if defined(ADC2)
+#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) ||\
+ (((__HANDLE__)->Instance) == ADC2) ||\
+ (((__HANDLE__)->Instance) == ADC4) )
+#else
+#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) ||\
+ (((__HANDLE__)->Instance) == ADC4) )
+#endif /* ADC2 */
+
+/**
+ * @brief Verify the ADC instance connected to the internal voltage reference VREFINT.
+ * @param __HANDLE__ ADC handle.
+ * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
+ */
+#if defined(ADC2)
+#define ADC_VREFINT_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) ||\
+ (((__HANDLE__)->Instance) == ADC2) ||\
+ (((__HANDLE__)->Instance) == ADC4) )
+#else
+#define ADC_VREFINT_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) ||\
+ (((__HANDLE__)->Instance) == ADC4) )
+#endif /* ADC2 */
+
+/**
+ * @brief Verify the ADC instance connected to the internal Vcore.
+ * @param __HANDLE__ ADC handle.
+ * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
+ */
+#define ADC_VCORE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC4)
+
+/**
+ * @brief Verify the length of scheduled injected conversions group.
+ * @param __LENGTH__ number of programmed conversions.
+ * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or
+ * RESET (__LENGTH__ is null or too large)
+ */
+#define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))
+
+/**
+ * @brief Calibration factor size verification (7 bits maximum).
+ * @param __CALIBRATION_FACTOR__ Calibration factor value.
+ * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)
+ */
+#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))
+
+
+/**
+ * @brief Verify the ADC channel setting.
+ * @param __CHANNEL__ programmed ADC channel.
+ * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
+ */
+#define IS_ADC_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_0) || \
+ ((__CHANNEL__) == ADC_CHANNEL_1) || \
+ ((__CHANNEL__) == ADC_CHANNEL_2) || \
+ ((__CHANNEL__) == ADC_CHANNEL_3) || \
+ ((__CHANNEL__) == ADC_CHANNEL_4) || \
+ ((__CHANNEL__) == ADC_CHANNEL_5) || \
+ ((__CHANNEL__) == ADC_CHANNEL_6) || \
+ ((__CHANNEL__) == ADC_CHANNEL_7) || \
+ ((__CHANNEL__) == ADC_CHANNEL_8) || \
+ ((__CHANNEL__) == ADC_CHANNEL_9) || \
+ ((__CHANNEL__) == ADC_CHANNEL_10) || \
+ ((__CHANNEL__) == ADC_CHANNEL_11) || \
+ ((__CHANNEL__) == ADC_CHANNEL_12) || \
+ ((__CHANNEL__) == ADC_CHANNEL_13) || \
+ ((__CHANNEL__) == ADC_CHANNEL_14) || \
+ ((__CHANNEL__) == ADC_CHANNEL_15) || \
+ ((__CHANNEL__) == ADC_CHANNEL_16) || \
+ ((__CHANNEL__) == ADC_CHANNEL_17) || \
+ ((__CHANNEL__) == ADC_CHANNEL_18) || \
+ ((__CHANNEL__) == ADC_CHANNEL_19) || \
+ ((__CHANNEL__) == ADC_CHANNEL_20) || \
+ ((__CHANNEL__) == ADC_CHANNEL_21) || \
+ ((__CHANNEL__) == ADC_CHANNEL_22) || \
+ ((__CHANNEL__) == ADC_CHANNEL_23) || \
+ ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
+ ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC4)|| \
+ ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC4)|| \
+ ((__CHANNEL__) == ADC4_CHANNEL_TEMPSENSOR) || \
+ ((__CHANNEL__) == ADC4_CHANNEL_VBAT) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VCORE) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VREFINT) )
+
+/**
+ * @brief Verify the ADC channel setting in differential mode for ADC1.
+ * @param __CHANNEL__: programmed ADC channel.
+ * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
+ */
+#define IS_ADC1_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \
+ ((__CHANNEL__) == ADC_CHANNEL_2) || \
+ ((__CHANNEL__) == ADC_CHANNEL_3) ||\
+ ((__CHANNEL__) == ADC_CHANNEL_4) ||\
+ ((__CHANNEL__) == ADC_CHANNEL_5) ||\
+ ((__CHANNEL__) == ADC_CHANNEL_6) ||\
+ ((__CHANNEL__) == ADC_CHANNEL_7) ||\
+ ((__CHANNEL__) == ADC_CHANNEL_8) ||\
+ ((__CHANNEL__) == ADC_CHANNEL_9) ||\
+ ((__CHANNEL__) == ADC_CHANNEL_10) ||\
+ ((__CHANNEL__) == ADC_CHANNEL_11) ||\
+ ((__CHANNEL__) == ADC_CHANNEL_12) ||\
+ ((__CHANNEL__) == ADC_CHANNEL_13) ||\
+ ((__CHANNEL__) == ADC_CHANNEL_14) ||\
+ ((__CHANNEL__) == ADC_CHANNEL_15) ||\
+ ((__CHANNEL__) == ADC_CHANNEL_16) ||\
+ ((__CHANNEL__) == ADC_CHANNEL_17) )
+
+
+/**
+ * @brief Verify the ADC single-ended input or differential mode setting.
+ * @param __SING_DIFF__ programmed channel setting.
+ * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid)
+ */
+#define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \
+ ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) )
+
+
+/**
+ * @brief Verify the ADC offset sign setting.
+ * @param __OFFSET_SIGN__ ADC offset sign.
+ * @retval SET (__OFFSET_SIGN__ is valid) or RESET (__OFFSET_SIGN__ is invalid)
+ */
+#define IS_ADC_OFFSET_SIGN(__OFFSET_SIGN__) (((__OFFSET_SIGN__) == ADC_OFFSET_SIGN_NEGATIVE) || \
+ ((__OFFSET_SIGN__) == ADC_OFFSET_SIGN_POSITIVE) )
+/**
+ * @brief Verify the ADC offset management setting.
+ * @param __OFFSET_NUMBER__ ADC offset management.
+ * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid)
+ */
+#define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \
+ ((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \
+ ((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \
+ ((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \
+ ((__OFFSET_NUMBER__) == ADC_OFFSET_4) )
+
+/**
+ * @brief Verify the ADC injected channel setting.
+ * @param __CHANNEL__ programmed ADC injected channel.
+ * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
+ */
+#define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \
+ ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \
+ ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \
+ ((__CHANNEL__) == ADC_INJECTED_RANK_4) )
+
+/**
+ * @brief Verify the ADC injected conversions external trigger.
+ * @param __INJTRIG__ programmed ADC injected conversions external trigger.
+ * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid)
+ */
+#define IS_ADC_EXTTRIGINJEC(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM1_CH2) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM2_CH2) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM3_CH1) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM4_OUT) || \
+ ((__INJTRIG__) == ADC_SOFTWARE_START) )
+
+/**
+ * @brief Verify the ADC edge trigger setting for injected group.
+ * @param __EDGE__ programmed ADC edge trigger setting.
+ * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
+ */
+#define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \
+ ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \
+ ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \
+ ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Verify the ADC multimode setting.
+ * @param __MODE__ programmed ADC multimode setting.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \
+ ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
+ ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
+ ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \
+ ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \
+ ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \
+ ((__MODE__) == ADC_DUALMODE_INTERL) || \
+ ((__MODE__) == ADC_DUALMODE_ALTERTRIG) )
+
+/**
+ * @brief Verify the ADC dual data mode setting.
+ * @param MODE: programmed ADC dual mode setting.
+ * @retval SET (MODE is valid) or RESET (MODE is invalid)
+ */
+#define IS_ADC_DUAL_DATA_MODE(MODE) (((MODE) == ADC_DUALMODEDATAFORMAT_DISABLED) || \
+ ((MODE) == ADC_DUALMODEDATAFORMAT_32_10_BITS) || \
+ ((MODE) == ADC_DUALMODEDATAFORMAT_8_BITS) )
+
+/**
+ * @brief Verify the ADC multimode delay setting.
+ * @param __DELAY__ programmed ADC multimode delay setting.
+ * @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid)
+ */
+#define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) )
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @brief Verify the ADC analog watchdog setting.
+ * @param __WATCHDOG__ programmed ADC analog watchdog setting.
+ * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid)
+ */
+#define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \
+ ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \
+ ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) )
+
+/**
+ * @brief Verify the ADC analog watchdog mode setting.
+ * @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting.
+ * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid)
+ */
+#define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \
+ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
+ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
+ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)|| \
+ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \
+ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
+ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
+
+/**
+ * @brief Verify the ADC analog watchdog filtering setting.
+ * @param __FILTERING_MODE__ programmed ADC analog watchdog mode setting.
+ * @retval SET (__FILTERING_MODE__ is valid) or RESET (__FILTERING_MODE__ is invalid)
+ */
+#define IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(__FILTERING_MODE__) \
+ (((__FILTERING_MODE__) == ADC_AWD_FILTERING_NONE) || \
+ ((__FILTERING_MODE__) == ADC_AWD_FILTERING_2SAMPLES) || \
+ ((__FILTERING_MODE__) == ADC_AWD_FILTERING_3SAMPLES) || \
+ ((__FILTERING_MODE__) == ADC_AWD_FILTERING_4SAMPLES) || \
+ ((__FILTERING_MODE__) == ADC_AWD_FILTERING_5SAMPLES) || \
+ ((__FILTERING_MODE__) == ADC_AWD_FILTERING_6SAMPLES) || \
+ ((__FILTERING_MODE__) == ADC_AWD_FILTERING_7SAMPLES) || \
+ ((__FILTERING_MODE__) == ADC_AWD_FILTERING_8SAMPLES) )
+
+
+
+/**
+ * @brief Verify the ADC conversion (regular or injected or both).
+ * @param __CONVERSION__ ADC conversion group.
+ * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid)
+ */
+#define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \
+ ((__CONVERSION__) == ADC_INJECTED_GROUP) || \
+ ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) )
+
+/**
+ * @brief Verify the ADC event type.
+ * @param __EVENT__ ADC event.
+ * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid)
+ */
+#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \
+ ((__EVENT__) == ADC_AWD_EVENT) || \
+ ((__EVENT__) == ADC_AWD2_EVENT) || \
+ ((__EVENT__) == ADC_AWD3_EVENT) || \
+ ((__EVENT__) == ADC_OVR_EVENT) || \
+ ((__EVENT__) == ADC_JQOVF_EVENT) )
+
+/**
+ * @brief Verify the ADC oversampling ratio.
+ * @param RATIO: programmed ADC oversampling ratio.
+ * @retval SET (RATIO is a valid value) or RESET (RATIO is invalid)
+ */
+#define IS_ADC_OVERSAMPLING_RATIO(RATIO) ((RATIO) < 1024UL)
+
+/**
+ * @brief Verify the ADC oversampling shift.
+ * @param __SHIFT__ programmed ADC oversampling shift.
+ * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid)
+ */
+#define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 ))
+
+/**
+ * @brief Verify the ADC oversampling triggered mode.
+ * @param __MODE__ programmed ADC oversampling triggered mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
+ ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
+
+/**
+ * @brief Verify the ADC oversampling regular conversion resumed or continued mode.
+ * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \
+ ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) )
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADCEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup ADCEx_Exported_Functions_Group1
+ * @{
+ */
+/* IO operation functions *****************************************************/
+
+/* ADC calibration */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t CalibrationMode,
+ uint32_t SingleDiff);
+uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
+HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t *pLinearCalib_Buffer);
+HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff,
+ uint32_t CalibrationFactor);
+HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t *pLinearCalib_Buffer);
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
+
+/* Non-blocking mode: Interruption */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/* ADC multimode */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, const uint32_t *pData, uint32_t Length);
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
+uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc);
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/* ADC retrieve conversion value intended to be used with polling or interruption */
+uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank);
+
+/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
+void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc);
+void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc);
+void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc);
+void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc);
+void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc);
+
+/* ADC group regular conversions stop */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc);
+#if defined(ADC_MULTIMODE_SUPPORT)
+HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc);
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADCEx_Exported_Functions_Group2
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,
+ ADC_InjectionConfTypeDef *pConfigInjected);
+#if defined(ADC_MULTIMODE_SUPPORT)
+HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *pMultimode);
+#endif /* ADC_MULTIMODE_SUPPORT */
+HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_ADC_EX_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_comp.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_comp.h
new file mode 100644
index 00000000..b5c68740
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_comp.h
@@ -0,0 +1,762 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_comp.h
+ * @author MCD Application Team
+ * @brief Header file of COMP HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_COMP_H
+#define STM32U5xx_HAL_COMP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+#if defined (COMP1) || defined (COMP2)
+
+/** @addtogroup COMP
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup COMP_Exported_Types COMP Exported Types
+ * @{
+ */
+
+/**
+ * @brief COMP Init structure definition
+ */
+typedef struct
+{
+
+ uint32_t WindowMode; /*!< Set window mode of a pair of comparators instances
+ (2 consecutive instances odd and even COMP and COMP).
+ Note: HAL COMP driver allows to set window mode from any COMP
+ instance of the pair of COMP instances composing window mode.
+ This parameter can be a value of @ref COMP_WindowMode */
+
+ uint32_t WindowOutput; /*!< Set window mode output.
+ This parameter can be a value of @ref COMP_WindowOutput */
+
+ uint32_t Mode; /*!< Set comparator operating mode to adjust power and speed.
+ Note: For the characteristics of comparator power modes
+ (propagation delay and power consumption), refer to device datasheet.
+ This parameter can be a value of @ref COMP_PowerMode */
+
+ uint32_t InputPlus; /*!< Set comparator input plus (non-inverting input).
+ This parameter can be a value of @ref COMP_InputPlus */
+
+ uint32_t InputMinus; /*!< Set comparator input minus (inverting input).
+ This parameter can be a value of @ref COMP_InputMinus */
+
+ uint32_t Hysteresis; /*!< Set comparator hysteresis mode of the input minus.
+ This parameter can be a value of @ref COMP_Hysteresis */
+
+ uint32_t OutputPol; /*!< Set comparator output polarity.
+ This parameter can be a value of @ref COMP_OutputPolarity */
+
+ uint32_t BlankingSrce; /*!< Set comparator blanking source.
+ This parameter can be a value of @ref COMP_BlankingSrce */
+
+ uint32_t TriggerMode; /*!< Set the comparator output triggering External Interrupt Line (EXTI).
+ This parameter can be a value of @ref COMP_EXTI_TriggerMode */
+
+} COMP_InitTypeDef;
+
+/**
+ * @brief HAL COMP state machine: HAL COMP states definition
+ */
+#define COMP_STATE_BITFIELD_LOCK (0x10U)
+typedef enum
+{
+ HAL_COMP_STATE_RESET = 0x00U, /*!< COMP not yet initialized */
+ HAL_COMP_STATE_RESET_LOCKED = (HAL_COMP_STATE_RESET | COMP_STATE_BITFIELD_LOCK), /*!< COMP not yet initialized and configuration is locked */
+ HAL_COMP_STATE_READY = 0x01U, /*!< COMP initialized and ready for use */
+ HAL_COMP_STATE_READY_LOCKED = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK), /*!< COMP initialized but configuration is locked */
+ HAL_COMP_STATE_BUSY = 0x02U, /*!< COMP is running */
+ HAL_COMP_STATE_BUSY_LOCKED = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK) /*!< COMP is running and configuration is locked */
+} HAL_COMP_StateTypeDef;
+
+/**
+ * @brief COMP Handle Structure definition
+ */
+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
+typedef struct __COMP_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
+{
+ COMP_TypeDef *Instance; /*!< Register base address */
+ COMP_InitTypeDef Init; /*!< COMP required parameters */
+ HAL_LockTypeDef Lock; /*!< Locking object */
+ __IO HAL_COMP_StateTypeDef State; /*!< COMP communication state */
+ __IO uint32_t ErrorCode; /*!< COMP error code */
+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
+ void (* TriggerCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP trigger callback */
+ void (* MspInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp Init callback */
+ void (* MspDeInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp DeInit callback */
+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
+} COMP_HandleTypeDef;
+
+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL COMP Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_COMP_TRIGGER_CB_ID = 0x00U, /*!< COMP trigger callback ID */
+ HAL_COMP_MSPINIT_CB_ID = 0x01U, /*!< COMP Msp Init callback ID */
+ HAL_COMP_MSPDEINIT_CB_ID = 0x02U /*!< COMP Msp DeInit callback ID */
+} HAL_COMP_CallbackIDTypeDef;
+
+/**
+ * @brief HAL COMP Callback pointer definition
+ */
+typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer to a COMP callback function */
+
+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup COMP_Exported_Constants COMP Exported Constants
+ * @{
+ */
+
+/** @defgroup COMP_Error_Code COMP Error Code
+ * @{
+ */
+#define HAL_COMP_ERROR_NONE (0x00UL) /*!< No error */
+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
+#define HAL_COMP_ERROR_INVALID_CALLBACK (0x01UL) /*!< Invalid Callback error */
+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_WindowMode COMP Window Mode
+ * @{
+ */
+#define COMP_WINDOWMODE_DISABLE (0x00000000UL) /*!< Window mode disable: Comparators instances pair COMP1 and COMP2 are independent */
+#define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE) /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */
+#define COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON (COMP_CSR_WINMODE | COMP_WINDOWMODE_COMP2) /*!< Window mode enable: if used from COMP1 or COMP2 instance, comparators instances pair COMP1 and COMP2 have their input plus connected together, the common input is COMP2 input plus (COMP1 input plus is no more accessible) */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_WindowOutput COMP Window output
+ * @{
+ */
+#define COMP_WINDOWOUTPUT_EACH_COMP (0x00000000UL) /*!< Window output default mode: Comparators output are indicating each their own state. To know window mode state: each comparator output must be read, if "((COMPx exclusive or COMPy) == 1)" then monitored signal is within comparators window. */
+#define COMP_WINDOWOUTPUT_COMP1 (COMP_CSR_WINOUT) /*!< Window output synthetized on COMP1 output: COMP1 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). */
+#define COMP_WINDOWOUTPUT_COMP2 (COMP_CSR_WINOUT | COMP_WINDOWMODE_COMP2) /*!< Window output synthetized on COMP2 output: COMP2 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). */
+#define COMP_WINDOWOUTPUT_BOTH (0x00000001UL) /*!< Window output synthetized on both comparators output of pair of comparator selected (COMP1 and COMP2): both comparators outputs are no more indicating their own state, but global window mode state (logical high means monitored signal is within comparators window). This is a specific configuration (technically possible but not relevant from application point of view: 2 comparators output used for the same signal level), standard configuration for window mode is one of the settings above. */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_PowerMode COMP power mode
+ * @{
+ */
+/* Note: For the characteristics of comparator power modes */
+/* (propagation delay and power consumption), */
+/* refer to device datasheet. */
+#define COMP_POWERMODE_HIGHSPEED (0x00000000UL) /*!< High Speed */
+#define COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0) /*!< Medium Speed */
+#define COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_PWRMODE_1 | COMP_CSR_PWRMODE_0) /*!< Ultra-low power */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_InputPlus COMP input plus (non-inverting input)
+ * @{
+ */
+#define COMP_INPUT_PLUS_IO1 ((uint32_t)0x00000000) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2) */
+#define COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0) /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2) */
+#define COMP_INPUT_PLUS_IO3 (COMP_CSR_INPSEL_1) /*!< Comparator input plus connected to IO3 (pin PA2 for COMP1) */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_InputMinus COMP input minus (inverting input)
+ * @{
+ */
+#define COMP_INPUT_MINUS_1_4VREFINT ((uint32_t)0x00000000 ) /*!< Comparator input minus connected to 1/4 VrefInt */
+#define COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to 1/2 VrefInt */
+#define COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to 3/4 VrefInt */
+#define COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to VrefInt */
+#define COMP_INPUT_MINUS_DAC1_CH1 (COMP_CSR_INMSEL_2 ) /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) */
+#define COMP_INPUT_MINUS_DAC1_CH2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */
+#define COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB7 for COMP2) */
+#define COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PB3 for COMP2) */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_Hysteresis COMP hysteresis
+ * @{
+ */
+#define COMP_HYSTERESIS_NONE ((uint32_t)0x00000000) /*!< No hysteresis */
+#define COMP_HYSTERESIS_LOW (COMP_CSR_HYST_0) /*!< Hysteresis level low */
+#define COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1) /*!< Hysteresis level medium */
+#define COMP_HYSTERESIS_HIGH (COMP_CSR_HYST ) /*!< Hysteresis level high */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_OutputPolarity COMP Output Polarity
+ * @{
+ */
+#define COMP_OUTPUTPOL_NONINVERTED (0x00000000UL) /*!< COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus) */
+#define COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY) /*!< COMP output level is inverted (comparator output is low when the input plus is at a higher voltage than the input minus) */
+/**
+ * @}
+ */
+
+
+/** @defgroup COMP_BlankingSrce COMP Blanking Source
+ * @{
+ */
+#define COMP_BLANKINGSRC_NONE ((uint32_t)0x00000000) /*!< No blanking source */
+#define COMP_BLANKINGSRC_TIM1_OC5 (COMP_CSR_BLANKSEL_0) /*!< TIM1 OC5 selected as blanking source for COMP1 */
+#define COMP_BLANKINGSRC_TIM2_OC3 (COMP_CSR_BLANKSEL_1) /*!< TIM2 OC3 selected as blanking source for COMP1 */
+#define COMP_BLANKINGSRC_TIM3_OC3 (COMP_CSR_BLANKSEL_2) /*!< TIM3 OC3 selected as blanking source for COMP1 */
+#define COMP_BLANKINGSRC_TIM3_OC4 (COMP_CSR_BLANKSEL_0) /*!< TIM3 OC4 selected as blanking source for COMP2 */
+#define COMP_BLANKINGSRC_TIM8_OC5 (COMP_CSR_BLANKSEL_1) /*!< TIM8 OC5 selected as blanking source for COMP2 */
+#define COMP_BLANKINGSRC_TIM15_OC1 (COMP_CSR_BLANKSEL_2) /*!< TIM15 OC1 selected as blanking source for COMP2 */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_OutputLevel COMP Output Level
+ * @{
+ */
+/* Note: Comparator output level values are fixed to "0" and "1", */
+/* corresponding COMP register bit is managed by HAL function to match */
+/* with these values (independently of bit position in register). */
+
+/* When output polarity is not inverted, comparator output is low when
+ the input plus is at a lower voltage than the input minus */
+#define COMP_OUTPUT_LEVEL_LOW (0x00000000UL)
+/* When output polarity is not inverted, comparator output is high when
+ the input plus is at a higher voltage than the input minus */
+#define COMP_OUTPUT_LEVEL_HIGH (0x00000001UL)
+/**
+ * @}
+ */
+
+/** @defgroup COMP_EXTI_TriggerMode COMP output to EXTI
+ * @{
+ */
+#define COMP_TRIGGERMODE_NONE (0x00000000UL) /*!< Comparator output triggering no External Interrupt Line */
+#define COMP_TRIGGERMODE_IT_RISING (COMP_EXTI_IT | COMP_EXTI_RISING) /*!< Comparator output triggering External Interrupt Line event with interruption, on rising edge */
+#define COMP_TRIGGERMODE_IT_FALLING (COMP_EXTI_IT | COMP_EXTI_FALLING) /*!< Comparator output triggering External Interrupt Line event with interruption, on falling edge */
+#define COMP_TRIGGERMODE_IT_RISING_FALLING (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING) /*!< Comparator output triggering External Interrupt Line event with interruption, on both rising and falling edges */
+#define COMP_TRIGGERMODE_EVENT_RISING (COMP_EXTI_EVENT | COMP_EXTI_RISING) /*!< Comparator output triggering External Interrupt Line event only (without interruption), on rising edge */
+#define COMP_TRIGGERMODE_EVENT_FALLING (COMP_EXTI_EVENT | COMP_EXTI_FALLING) /*!< Comparator output triggering External Interrupt Line event only (without interruption), on falling edge */
+#define COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING) /*!< Comparator output triggering External Interrupt Line event only (without interruption), on both rising and falling edges */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup COMP_Exported_Macros COMP Exported Macros
+ * @{
+ */
+
+/** @defgroup COMP_Handle_Management COMP Handle Management
+ * @{
+ */
+
+/** @brief Reset COMP handle state.
+ * @param __HANDLE__ COMP handle
+ * @retval None
+ */
+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
+#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_COMP_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
+
+/**
+ * @brief Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE").
+ * @param __HANDLE__ COMP handle
+ * @retval None
+ */
+#define COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE)
+
+/**
+ * @brief Enable the specified comparator.
+ * @param __HANDLE__ COMP handle
+ * @retval None
+ */
+#define __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
+
+/**
+ * @brief Disable the specified comparator.
+ * @param __HANDLE__ COMP handle
+ * @retval None
+ */
+#define __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
+
+/**
+ * @brief Lock the specified comparator configuration.
+ * @note Using this macro induce HAL COMP handle state machine being no
+ * more in line with COMP instance state.
+ * To keep HAL COMP handle state machine updated, it is recommended
+ * to use function "HAL_COMP_Lock')".
+ * @param __HANDLE__ COMP handle
+ * @retval None
+ */
+#define __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK)
+
+/**
+ * @brief Check whether the specified comparator is locked.
+ * @param __HANDLE__ COMP handle
+ * @retval Value 0 if COMP instance is not locked, value 1 if COMP instance is locked
+ */
+#define __HAL_COMP_IS_LOCKED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK)\
+ == COMP_CSR_LOCK)
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_Exti_Management COMP external interrupt line management
+ * @{
+ */
+
+/**
+ * @brief Enable the COMP1 EXTI line rising edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP1)
+
+
+/**
+ * @brief Disable the COMP1 EXTI line rising edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP1)
+
+/**
+ * @brief Enable the COMP1 EXTI line falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1)
+
+/**
+ * @brief Disable the COMP1 EXTI line falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1)
+
+
+/**
+ * @brief Enable the COMP1 EXTI line rising & falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
+ __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE(); \
+ } while(0)
+
+
+/**
+ * @brief Disable the COMP1 EXTI line rising & falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
+ __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0)
+
+/**
+ * @brief Enable the COMP1 EXTI line in interrupt mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, COMP_EXTI_LINE_COMP1)
+
+/**
+ * @brief Disable the COMP1 EXTI line in interrupt mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, COMP_EXTI_LINE_COMP1)
+
+/**
+ * @brief Enable the COMP1 EXTI Line in event mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP1)
+
+/**
+ * @brief Disable the COMP1 EXTI Line in event mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP1)
+
+/**
+ * @brief Check whether the COMP1 EXTI line rising flag is set or not.
+ * @retval RESET or SET
+ */
+#define __HAL_COMP_COMP1_EXTI_GET_RISING_FLAG() READ_BIT(EXTI->RPR1, COMP_EXTI_LINE_COMP1)
+
+/**
+ * @brief Check whether the COMP1 EXTI line falling flag is set or not.
+ * @retval RESET or SET
+ */
+#define __HAL_COMP_COMP1_EXTI_GET_FALLING_FLAG() READ_BIT(EXTI->FPR1, COMP_EXTI_LINE_COMP1)
+
+/**
+ * @brief Clear the COMP1 EXTI rasing flag.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG() WRITE_REG(EXTI->RPR1, COMP_EXTI_LINE_COMP1)
+
+/**
+ * @brief Clear the COMP1 EXTI falling flag.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_CLEAR_FALLING_FLAG() WRITE_REG(EXTI->FPR1, COMP_EXTI_LINE_COMP1)
+
+
+/**
+ * @brief Generate a software interrupt on the COMP1 EXTI line.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP1)
+
+
+/**
+ * @brief Enable the COMP2 EXTI line rising edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2)
+
+/**
+ * @brief Disable the COMP2 EXTI line rising edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2)
+
+/**
+ * @brief Enable the COMP2 EXTI line falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2)
+
+/**
+ * @brief Disable the COMP2 EXTI line falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2)
+
+/**
+ * @brief Enable the COMP2 EXTI line rising & falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
+ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); \
+ } while(0)
+
+/**
+ * @brief Disable the COMP2 EXTI line rising & falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
+ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0)
+/**
+ * @brief Enable the COMP2 EXTI line in interrupt mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, COMP_EXTI_LINE_COMP2)
+
+/**
+ * @brief Disable the COMP2 EXTI line in interrupt mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, COMP_EXTI_LINE_COMP2)
+
+/**
+ * @brief Enable the COMP2 EXTI Line in event mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP2)
+
+/**
+ * @brief Disable the COMP2 EXTI Line in event mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP2)
+
+/**
+ * @brief Check whether the COMP2 EXTI line rasing flag is set or not.
+ * @retval RESET or SET
+ */
+#define __HAL_COMP_COMP2_EXTI_GET_RISING_FLAG() READ_BIT(EXTI->RPR1, COMP_EXTI_LINE_COMP2)
+
+/**
+ * @brief Check whether the COMP2 EXTI line falling flag is set or not.
+ * @retval RESET or SET
+ */
+#define __HAL_COMP_COMP2_EXTI_GET_FALLING_FLAG() READ_BIT(EXTI->FPR1, COMP_EXTI_LINE_COMP2)
+
+
+/**
+ * @brief Clear the the COMP2 EXTI rasing flag.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_CLEAR_RISING_FLAG() WRITE_REG(EXTI->RPR1, COMP_EXTI_LINE_COMP2)
+
+/**
+ * @brief Clear the the COMP2 EXTI falling flag.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_CLEAR_FALLING_FLAG() WRITE_REG(EXTI->FPR1, COMP_EXTI_LINE_COMP2)
+
+/**
+ * @brief Generate a software interrupt on the COMP2 EXTI line.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP2)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private types -------------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup COMP_Private_Constants COMP Private Constants
+ * @{
+ */
+
+/** @defgroup COMP_WindowMode_Instance_Differentiator COMP window mode instance differentiator
+ * @{
+ */
+#define COMP_WINDOWMODE_COMP2 0x00001000U /*!< COMP window mode using common input of COMP instance: COMP2 */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_ExtiLine COMP EXTI Lines
+ * @{
+ */
+#define COMP_EXTI_LINE_COMP1 (EXTI_IMR1_IM17) /*!< EXTI line 17 connected to COMP1 output */
+#define COMP_EXTI_LINE_COMP2 (EXTI_IMR1_IM18) /*!< EXTI line 18 connected to COMP2 output */
+/**
+ * @}
+ */
+/** @defgroup COMP_ExtiLine COMP EXTI Lines
+ * @{
+ */
+#define COMP_EXTI_IT (0x00000001UL) /*!< EXTI line event with interruption */
+#define COMP_EXTI_EVENT (0x00000002UL) /*!< EXTI line event only (without interruption) */
+#define COMP_EXTI_RISING (0x00000010UL) /*!< EXTI line event on rising edge */
+#define COMP_EXTI_FALLING (0x00000020UL) /*!< EXTI line event on falling edge */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup COMP_Private_Macros COMP Private Macros
+ * @{
+ */
+
+/** @defgroup COMP_GET_EXTI_LINE COMP private macros to get EXTI line associated with comparators
+ * @{
+ */
+/**
+ * @brief Get the specified EXTI line for a comparator instance.
+ * @param __INSTANCE__ specifies the COMP instance.
+ * @retval value of @ref COMP_ExtiLine
+ */
+#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 : \
+ COMP_EXTI_LINE_COMP2)
+/**
+ * @}
+ */
+
+/** @defgroup COMP_IS_COMP_Private_Definitions COMP private macros to check input parameters
+ * @{
+ */
+#define IS_COMP_WINDOWMODE(__INSTANCE__, __WINMODE__) (((__WINMODE__) == COMP_WINDOWMODE_DISABLE) ||\
+ ((__WINMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)||\
+ ((__WINMODE__) == COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON))
+
+#define IS_COMP_WINDOWOUTPUT(__WINDOWOUTPUT__) (((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_EACH_COMP) || \
+ ((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_COMP1) || \
+ ((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_COMP2) || \
+ ((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_BOTH))
+
+#define IS_COMP_POWERMODE(__POWERMODE__) (((__POWERMODE__) == COMP_POWERMODE_HIGHSPEED) || \
+ ((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED) || \
+ ((__POWERMODE__) == COMP_POWERMODE_ULTRALOWPOWER))
+
+
+#define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \
+ ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2) || \
+ ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO3))
+
+#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) ||\
+ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) ||\
+ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) ||\
+ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) ||\
+ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) ||\
+ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) ||\
+ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) ||\
+ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2))
+
+
+#define IS_COMP_HYSTERESIS(__HYSTERESIS__) (((__HYSTERESIS__) == COMP_HYSTERESIS_NONE) || \
+ ((__HYSTERESIS__) == COMP_HYSTERESIS_LOW) || \
+ ((__HYSTERESIS__) == COMP_HYSTERESIS_MEDIUM) || \
+ ((__HYSTERESIS__) == COMP_HYSTERESIS_HIGH))
+
+#define IS_COMP_OUTPUTPOL(__POL__) (((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \
+ ((__POL__) == COMP_OUTPUTPOL_INVERTED))
+
+#define IS_COMP_BLANKINGSRCE(__SOURCE__) (((__SOURCE__) == COMP_BLANKINGSRC_NONE) || \
+ ((__SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5) || \
+ ((__SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3) || \
+ ((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3) || \
+ ((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4) || \
+ ((__SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5) || \
+ ((__SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1))
+
+
+#define IS_COMP_TRIGGERMODE(__MODE__) (((__MODE__) == COMP_TRIGGERMODE_NONE) || \
+ ((__MODE__) == COMP_TRIGGERMODE_IT_RISING) || \
+ ((__MODE__) == COMP_TRIGGERMODE_IT_FALLING) || \
+ ((__MODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING) || \
+ ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING) || \
+ ((__MODE__) == COMP_TRIGGERMODE_EVENT_FALLING) || \
+ ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING))
+
+#define IS_COMP_OUTPUT_LEVEL(__OUTPUT_LEVEL__) (((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_LOW) || \
+ ((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_HIGH))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup COMP_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup COMP_Exported_Functions_Group1
+ * @{
+ */
+
+/* Initialization and de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp);
+HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp);
+void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);
+void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);
+
+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
+/* Callbacks Register/UnRegister functions ***********************************/
+HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID,
+ pCOMP_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/* IO operation functions *****************************************************/
+/** @addtogroup COMP_Exported_Functions_Group2
+ * @{
+ */
+HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp);
+HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp);
+void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp);
+/**
+ * @}
+ */
+
+/* Peripheral Control functions ************************************************/
+/** @addtogroup COMP_Exported_Functions_Group3
+ * @{
+ */
+HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp);
+uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp);
+/* Callback in interrupt mode */
+void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);
+/**
+ * @}
+ */
+
+/* Peripheral State functions **************************************************/
+/** @addtogroup COMP_Exported_Functions_Group4
+ * @{
+ */
+HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);
+uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* COMP1 || COMP2 */
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_COMP_H */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_conf_template.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_conf_template.h
new file mode 100644
index 00000000..e62e0a61
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_conf_template.h
@@ -0,0 +1,474 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_conf_template.h
+ * @author MCD Application Team
+ * @brief HAL configuration template file.
+ * This file should be copied to the application folder and renamed
+ * to stm32u5xx_hal_conf.h.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_CONF_H
+#define STM32U5xx_HAL_CONF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_COMP_MODULE_ENABLED
+#define HAL_CORDIC_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_CRC_MODULE_ENABLED
+#define HAL_CRYP_MODULE_ENABLED
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_DCACHE_MODULE_ENABLED
+#define HAL_DCMI_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_DMA2D_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_FDCAN_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_FMAC_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_GTZC_MODULE_ENABLED
+#define HAL_HASH_MODULE_ENABLED
+#define HAL_HCD_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_ICACHE_MODULE_ENABLED
+#define HAL_IRDA_MODULE_ENABLED
+#define HAL_IWDG_MODULE_ENABLED
+#define HAL_LPTIM_MODULE_ENABLED
+#define HAL_MDF_MODULE_ENABLED
+#define HAL_MMC_MODULE_ENABLED
+#define HAL_NAND_MODULE_ENABLED
+#define HAL_NOR_MODULE_ENABLED
+#define HAL_OPAMP_MODULE_ENABLED
+#define HAL_OSPI_MODULE_ENABLED
+#define HAL_OTFDEC_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+#define HAL_PKA_MODULE_ENABLED
+#define HAL_PSSI_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RAMCFG_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_SAI_MODULE_ENABLED
+#define HAL_SD_MODULE_ENABLED
+#define HAL_SMARTCARD_MODULE_ENABLED
+#define HAL_SMBUS_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_SRAM_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_TSC_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+#define HAL_WWDG_MODULE_ENABLED
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSE is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSE_VALUE)
+#define HSE_VALUE 16000000UL /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSE_STARTUP_TIMEOUT)
+#define HSE_STARTUP_TIMEOUT 100UL /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal Multiple Speed oscillator (MSI) default value.
+ * This value is the default MSI range value after Reset.
+ */
+#if !defined (MSI_VALUE)
+#define MSI_VALUE 4000000UL /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSI is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSI_VALUE)
+#define HSI_VALUE 16000000UL /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG.
+ * This internal oscillator is mainly dedicated to provide a high precision clock to
+ * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
+ * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
+ * which is subject to manufacturing process variations.
+ */
+#if !defined (HSI48_VALUE)
+#define HSI48_VALUE 48000000UL /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.
+ The real value my vary depending on manufacturing process variations.*/
+#endif /* HSI48_VALUE */
+
+/**
+ * @brief Internal Low Speed oscillator (LSI) value.
+ */
+#if !defined (LSI_VALUE)
+#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz. The real value may
+vary depending on the variations in voltage and temperature.*/
+
+#if !defined (LSI_STARTUP_TIMEOUT)
+#define LSI_STARTUP_TIMEOUT 130UL /*!< Time out for LSI start up, in ms */
+#endif /* LSI_STARTUP_TIMEOUT */
+
+/**
+ * @brief External Low Speed oscillator (LSE) value.
+ * This value is used by the UART, RTC HAL module to compute the system frequency
+ */
+#if !defined (LSE_VALUE)
+#define LSE_VALUE 32768UL /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief External clock source for SAI1 peripheral
+ * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
+ * frequency.
+ */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+#define EXTERNAL_SAI1_CLOCK_VALUE 48000UL /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+ === you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+ * @brief This is the HAL system configuration section
+ */
+#define VDD_VALUE 3300UL /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY ((1UL<<__NVIC_PRIO_BITS) - 1UL) /*!< tick interrupt priority (lowest by default) */
+#define USE_RTOS 0U
+#define PREFETCH_ENABLE 1U /*!< Enable prefetch */
+
+/* ########################## Assert Selection ############################## */
+/**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * HAL drivers code
+ */
+/* #define USE_FULL_ASSERT 1U */
+
+/* ################## Register callback feature configuration ############### */
+/**
+ * @brief Set below the peripheral configuration to "1U" to add the support
+ * of HAL callback registration/unregistration feature for the HAL
+ * driver(s). This allows user application to provide specific callback
+ * functions thanks to HAL_PPP_RegisterCallback() rather than overwriting
+ * the default weak callback functions (see each stm32u5xx_hal_ppp.h file
+ * for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef
+ * for each PPP peripheral).
+ */
+#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
+#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */
+#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U /* CORDIC register callback disabled */
+#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */
+#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
+#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */
+#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */
+#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */
+#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */
+#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U /* FMAC register callback disabled */
+#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */
+#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */
+#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
+#define USE_HAL_IWDG_REGISTER_CALLBACKS 0U /* IWDG register callback disabled */
+#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */
+#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */
+#define USE_HAL_MDF_REGISTER_CALLBACKS 0U /* MDF register callback disabled */
+#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */
+#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */
+#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */
+#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */
+#define USE_HAL_OTFDEC_REGISTER_CALLBACKS 0U /* OTFDEC register callback disabled */
+#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */
+#define USE_HAL_PKA_REGISTER_CALLBACKS 0U /* PKA register callback disabled */
+#define USE_HAL_RAMCFG_REGISTER_CALLBACKS 0U /* RAMCFG register callback disabled */
+#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */
+#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
+#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */
+#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */
+#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */
+#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
+#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */
+#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
+#define USE_HAL_TSC_REGISTER_CALLBACKS 0U /* TSC register callback disabled */
+#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
+#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
+#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+#define USE_SPI_CRC 1U
+
+/* ################## SDMMC peripheral configuration ######################### */
+
+#define USE_SD_TRANSCEIVER 0U
+
+
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Include module's header file
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+#include "stm32u5xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+#include "stm32u5xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_ICACHE_MODULE_ENABLED
+#include "stm32u5xx_hal_icache.h"
+#endif /* HAL_ICACHE_MODULE_ENABLED */
+
+#ifdef HAL_DCACHE_MODULE_ENABLED
+#include "stm32u5xx_hal_dcache.h"
+#endif /* HAL_DCACHE_MODULE_ENABLED */
+
+#ifdef HAL_GTZC_MODULE_ENABLED
+#include "stm32u5xx_hal_gtzc.h"
+#endif /* HAL_GTZC_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+#include "stm32u5xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+#include "stm32u5xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+#include "stm32u5xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+#include "stm32u5xx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+#include "stm32u5xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+#include "stm32u5xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+#include "stm32u5xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+#include "stm32u5xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+#include "stm32u5xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+#include "stm32u5xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+#include "stm32u5xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+#include "stm32u5xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+#include "stm32u5xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+#include "stm32u5xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+#include "stm32u5xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+#include "stm32u5xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+#include "stm32u5xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32u5xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+#include "stm32u5xx_hal_opamp.h"
+#endif /* HAL_OPAMP_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+#include "stm32u5xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+#include "stm32u5xx_hal_ospi.h"
+#endif /* HAL_OSPI_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+#include "stm32u5xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+#include "stm32u5xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+#include "stm32u5xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+#include "stm32u5xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+#include "stm32u5xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+#include "stm32u5xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+#include "stm32u5xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+#include "stm32u5xx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+#include "stm32u5xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+#include "stm32u5xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+#include "stm32u5xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+#include "stm32u5xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+#include "stm32u5xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+#include "stm32u5xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+#include "stm32u5xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_CORDIC_MODULE_ENABLED
+#include "stm32u5xx_hal_cordic.h"
+#endif /* HAL_CORDIC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+#include "stm32u5xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+#include "stm32u5xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+#include "stm32u5xx_hal_fdcan.h"
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+
+#ifdef HAL_FMAC_MODULE_ENABLED
+#include "stm32u5xx_hal_fmac.h"
+#endif /* HAL_FMAC_MODULE_ENABLED */
+
+#ifdef HAL_OTFDEC_MODULE_ENABLED
+#include "stm32u5xx_hal_otfdec.h"
+#endif /* HAL_OTFDEC_MODULE_ENABLED */
+
+#ifdef HAL_PSSI_MODULE_ENABLED
+#include "stm32u5xx_hal_pssi.h"
+#endif /* HAL_PSSI_MODULE_ENABLED */
+
+#ifdef HAL_RAMCFG_MODULE_ENABLED
+#include "stm32u5xx_hal_ramcfg.h"
+#endif /* HAL_RAMCFG_MODULE_ENABLED */
+
+#ifdef HAL_MDF_MODULE_ENABLED
+#include "stm32u5xx_hal_mdf.h"
+#endif /* HAL_MDF_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t *file, uint32_t line);
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_CONF_H */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cordic.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cordic.h
new file mode 100644
index 00000000..a03db89c
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cordic.h
@@ -0,0 +1,609 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_cordic.h
+ * @author MCD Application Team
+ * @brief This file contains all the functions prototypes for the CORDIC firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_CORDIC_H
+#define STM32U5xx_HAL_CORDIC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+#if defined(CORDIC)
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CORDIC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CORDIC_Exported_Types CORDIC Exported Types
+ * @{
+ */
+
+/**
+ * @brief CORDIC HAL State Structure definition
+ */
+typedef enum
+{
+ HAL_CORDIC_STATE_RESET = 0x00U, /*!< CORDIC not yet initialized or disabled */
+ HAL_CORDIC_STATE_READY = 0x01U, /*!< CORDIC initialized and ready for use */
+ HAL_CORDIC_STATE_BUSY = 0x02U, /*!< CORDIC internal process is ongoing */
+ HAL_CORDIC_STATE_ERROR = 0x03U /*!< CORDIC error state */
+} HAL_CORDIC_StateTypeDef;
+
+/**
+ * @brief CORDIC Handle Structure definition
+ */
+#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
+typedef struct __CORDIC_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
+{
+ CORDIC_TypeDef *Instance; /*!< Register base address */
+
+ int32_t *pInBuff; /*!< Pointer to CORDIC input data buffer */
+
+ int32_t *pOutBuff; /*!< Pointer to CORDIC output data buffer */
+
+ uint32_t NbCalcToOrder; /*!< Remaining number of calculation to order */
+
+ uint32_t NbCalcToGet; /*!< Remaining number of calculation result to get */
+
+ uint32_t DMADirection; /*!< Direction of CORDIC DMA transfers */
+
+ DMA_HandleTypeDef *hdmaIn; /*!< CORDIC peripheral input data DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmaOut; /*!< CORDIC peripheral output data DMA handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< CORDIC locking object */
+
+ __IO HAL_CORDIC_StateTypeDef State; /*!< CORDIC state */
+
+ __IO uint32_t ErrorCode; /*!< CORDIC peripheral error code
+ This parameter can be a value of @ref CORDIC_Error_Code */
+
+#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
+ void (* ErrorCallback)(struct __CORDIC_HandleTypeDef *hcordic); /*!< CORDIC error callback */
+ void (* CalculateCpltCallback)(struct __CORDIC_HandleTypeDef *hcordic); /*!< CORDIC calculate complete callback */
+
+ void (* MspInitCallback)(struct __CORDIC_HandleTypeDef *hcordic); /*!< CORDIC Msp Init callback */
+ void (* MspDeInitCallback)(struct __CORDIC_HandleTypeDef *hcordic); /*!< CORDIC Msp DeInit callback */
+
+#endif /* (USE_HAL_CORDIC_REGISTER_CALLBACKS) */
+
+} CORDIC_HandleTypeDef;
+
+/**
+ * @brief CORDIC Config Structure definition
+ */
+typedef struct
+{
+ uint32_t Function; /*!< Function
+ This parameter can be a value of @ref CORDIC_Function */
+
+ uint32_t Scale; /*!< Scaling factor
+ This parameter can be a value of @ref CORDIC_Scale */
+
+ uint32_t InSize; /*!< Width of input data
+ This parameter can be a value of @ref CORDIC_In_Size */
+
+ uint32_t OutSize; /*!< Width of output data
+ This parameter can be a value of @ref CORDIC_Out_Size */
+
+ uint32_t NbWrite; /*!< Number of 32-bit write expected for one calculation
+ This parameter can be a value of @ref CORDIC_Nb_Write */
+
+ uint32_t NbRead; /*!< Number of 32-bit read expected after one calculation
+ This parameter can be a value of @ref CORDIC_Nb_Read */
+
+ uint32_t Precision; /*!< Number of cycles for calculation
+ This parameter can be a value of @ref CORDIC_Precision_In_Cycles_Number */
+
+} CORDIC_ConfigTypeDef;
+
+#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
+/**
+ * @brief HAL CORDIC Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_CORDIC_ERROR_CB_ID = 0x00U, /*!< CORDIC error callback ID */
+ HAL_CORDIC_CALCULATE_CPLT_CB_ID = 0x01U, /*!< CORDIC calculate complete callback ID */
+
+ HAL_CORDIC_MSPINIT_CB_ID = 0x02U, /*!< CORDIC MspInit callback ID */
+ HAL_CORDIC_MSPDEINIT_CB_ID = 0x03U, /*!< CORDIC MspDeInit callback ID */
+
+} HAL_CORDIC_CallbackIDTypeDef;
+
+/**
+ * @brief HAL CORDIC Callback pointer definition
+ */
+typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< pointer to a CORDIC callback function */
+
+#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CORDIC_Exported_Constants CORDIC Exported Constants
+ * @{
+ */
+
+/** @defgroup CORDIC_Error_Code CORDIC Error code
+ * @{
+ */
+#define HAL_CORDIC_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
+#define HAL_CORDIC_ERROR_PARAM ((uint32_t)0x00000001U) /*!< Wrong parameter error */
+#define HAL_CORDIC_ERROR_NOT_READY ((uint32_t)0x00000002U) /*!< Peripheral not ready */
+#define HAL_CORDIC_ERROR_TIMEOUT ((uint32_t)0x00000004U) /*!< Timeout error */
+#define HAL_CORDIC_ERROR_DMA ((uint32_t)0x00000008U) /*!< DMA error */
+#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
+#define HAL_CORDIC_ERROR_INVALID_CALLBACK ((uint32_t)0x00000010U) /*!< Invalid Callback error */
+#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_Function CORDIC Function
+ * @{
+ */
+#define CORDIC_FUNCTION_COSINE (0x00000000U) /*!< Cosine */
+#define CORDIC_FUNCTION_SINE ((uint32_t)(CORDIC_CSR_FUNC_0)) /*!< Sine */
+#define CORDIC_FUNCTION_PHASE ((uint32_t)(CORDIC_CSR_FUNC_1)) /*!< Phase */
+#define CORDIC_FUNCTION_MODULUS ((uint32_t)(CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0)) /*!< Modulus */
+#define CORDIC_FUNCTION_ARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2)) /*!< Arctangent */
+#define CORDIC_FUNCTION_HCOSINE ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_0)) /*!< Hyperbolic Cosine */
+#define CORDIC_FUNCTION_HSINE ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1)) /*!< Hyperbolic Sine */
+#define CORDIC_FUNCTION_HARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))/*!< Hyperbolic Arctangent */
+#define CORDIC_FUNCTION_NATURALLOG ((uint32_t)(CORDIC_CSR_FUNC_3)) /*!< Natural Logarithm */
+#define CORDIC_FUNCTION_SQUAREROOT ((uint32_t)(CORDIC_CSR_FUNC_3 | CORDIC_CSR_FUNC_0)) /*!< Square Root */
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_Precision_In_Cycles_Number CORDIC Precision in Cycles Number
+ * @{
+ */
+/* Note: 1 cycle corresponds to 4 algorithm iterations */
+#define CORDIC_PRECISION_1CYCLE ((uint32_t)(CORDIC_CSR_PRECISION_0))
+#define CORDIC_PRECISION_2CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_1))
+#define CORDIC_PRECISION_3CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
+#define CORDIC_PRECISION_4CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2))
+#define CORDIC_PRECISION_5CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))
+#define CORDIC_PRECISION_6CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))
+#define CORDIC_PRECISION_7CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2\
+ | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
+#define CORDIC_PRECISION_8CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3))
+#define CORDIC_PRECISION_9CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_0))
+#define CORDIC_PRECISION_10CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1))
+#define CORDIC_PRECISION_11CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
+ | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
+#define CORDIC_PRECISION_12CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2))
+#define CORDIC_PRECISION_13CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
+ | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))
+#define CORDIC_PRECISION_14CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
+ | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))
+#define CORDIC_PRECISION_15CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
+ | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1\
+ |CORDIC_CSR_PRECISION_0))
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_Scale CORDIC Scaling factor
+ * @{
+ */
+/* Scale factor value 'n' implies that the input data have been multiplied
+ by a factor 2exp(-n), and/or the output data need to be multiplied by 2exp(n). */
+#define CORDIC_SCALE_0 (0x00000000U)
+#define CORDIC_SCALE_1 ((uint32_t)(CORDIC_CSR_SCALE_0))
+#define CORDIC_SCALE_2 ((uint32_t)(CORDIC_CSR_SCALE_1))
+#define CORDIC_SCALE_3 ((uint32_t)(CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0))
+#define CORDIC_SCALE_4 ((uint32_t)(CORDIC_CSR_SCALE_2))
+#define CORDIC_SCALE_5 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_0))
+#define CORDIC_SCALE_6 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1))
+#define CORDIC_SCALE_7 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0))
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_Interrupts_Enable CORDIC Interrupts Enable bit
+ * @{
+ */
+#define CORDIC_IT_IEN CORDIC_CSR_IEN /*!< Result ready interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_DMAR DMA Read Request Enable bit
+ * @{
+ */
+#define CORDIC_DMA_REN CORDIC_CSR_DMAREN /*!< DMA Read requests enable */
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_DMAW DMA Write Request Enable bit
+ * @{
+ */
+#define CORDIC_DMA_WEN CORDIC_CSR_DMAWEN /*!< DMA Write channel enable */
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_Nb_Write CORDIC Number of 32-bit write required for one calculation
+ * @{
+ */
+#define CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one
+ 32-bit data input (Q1.31 format), or two 16-bit
+ data input (Q1.15 format) packed in one 32 bits
+ Data */
+#define CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bits data input
+ (Q1.31 format) */
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_Nb_Read CORDIC Number of 32-bit read required after one calculation
+ * @{
+ */
+#define CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one
+ 32-bit data output (Q1.31 format), or two 16-bit
+ data output (Q1.15 format) packed in one 32 bits
+ Data */
+#define CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output
+ (Q1.31 format) */
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_In_Size CORDIC input data size
+ * @{
+ */
+#define CORDIC_INSIZE_32BITS (0x00000000U) /*!< 32 bits input data size (Q1.31 format) */
+#define CORDIC_INSIZE_16BITS CORDIC_CSR_ARGSIZE /*!< 16 bits input data size (Q1.15 format) */
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_Out_Size CORDIC Results Size
+ * @{
+ */
+#define CORDIC_OUTSIZE_32BITS (0x00000000U) /*!< 32 bits output data size (Q1.31 format) */
+#define CORDIC_OUTSIZE_16BITS CORDIC_CSR_RESSIZE /*!< 16 bits output data size (Q1.15 format) */
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_Flags CORDIC status flags
+ * @{
+ */
+#define CORDIC_FLAG_RRDY CORDIC_CSR_RRDY /*!< Result Ready Flag */
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_DMA_Direction CORDIC DMA direction
+ * @{
+ */
+#define CORDIC_DMA_DIR_NONE ((uint32_t)0x00000000U) /*!< DMA direction : none */
+#define CORDIC_DMA_DIR_IN ((uint32_t)0x00000001U) /*!< DMA direction : Input of CORDIC */
+#define CORDIC_DMA_DIR_OUT ((uint32_t)0x00000002U) /*!< DMA direction : Output of CORDIC */
+#define CORDIC_DMA_DIR_IN_OUT ((uint32_t)0x00000003U) /*!< DMA direction : Input and Output of CORDIC */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CORDIC_Exported_Macros CORDIC Exported Macros
+ * @{
+ */
+
+/** @brief Reset CORDIC handle state.
+ * @param __HANDLE__ CORDIC handle
+ * @retval None
+ */
+#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
+#define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_CORDIC_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CORDIC_STATE_RESET)
+#endif /*USE_HAL_CORDIC_REGISTER_CALLBACKS */
+
+/**
+ * @brief Enable the CORDIC interrupt when result is ready
+ * @param __HANDLE__ CORDIC handle.
+ * @param __INTERRUPT__ CORDIC Interrupt.
+ * This parameter can be one of the following values:
+ * @arg @ref CORDIC_IT_IEN Enable Interrupt
+ * @retval None
+ */
+#define __HAL_CORDIC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->CSR) |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the CORDIC interrupt
+ * @param __HANDLE__ CORDIC handle.
+ * @param __INTERRUPT__ CORDIC Interrupt.
+ * This parameter can be one of the following values:
+ * @arg @ref CORDIC_IT_IEN Enable Interrupt
+ * @retval None
+ */
+#define __HAL_CORDIC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->CSR) &= ~(__INTERRUPT__))
+
+/** @brief Check whether the specified CORDIC interrupt occurred or not.
+ Dummy macro as no interrupt status flag.
+ * @param __HANDLE__ CORDIC handle.
+ * @param __INTERRUPT__ CORDIC interrupt to check
+ * @retval SET (interrupt occurred) or RESET (interrupt did not occurred)
+ */
+#define __HAL_CORDIC_GET_IT(__HANDLE__, __INTERRUPT__) /* Dummy macro */
+
+/** @brief Clear specified CORDIC interrupt status. Dummy macro as no
+ interrupt status flag.
+ * @param __HANDLE__ CORDIC handle.
+ * @param __INTERRUPT__ CORDIC interrupt to clear
+ * @retval None
+ */
+#define __HAL_CORDIC_CLEAR_IT(__HANDLE__, __INTERRUPT__) /* Dummy macro */
+
+/** @brief Check whether the specified CORDIC status flag is set or not.
+ * @param __HANDLE__ CORDIC handle.
+ * @param __FLAG__ CORDIC flag to check
+ * This parameter can be one of the following values:
+ * @arg @ref CORDIC_FLAG_RRDY Result Ready Flag
+ * @retval SET (flag is set) or RESET (flag is reset)
+ */
+#define __HAL_CORDIC_GET_FLAG(__HANDLE__, __FLAG__) \
+ ((((__HANDLE__)->Instance->CSR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear specified CORDIC status flag. Dummy macro as no
+ flag can be cleared.
+ * @param __HANDLE__ CORDIC handle.
+ * @param __FLAG__ CORDIC flag to clear
+ * This parameter can be one of the following values:
+ * @arg @ref CORDIC_FLAG_RRDY Result Ready Flag
+ * @retval None
+ */
+#define __HAL_CORDIC_CLEAR_FLAG(__HANDLE__, __FLAG__) /* Dummy macro */
+
+/** @brief Check whether the specified CORDIC interrupt is enabled or not.
+ * @param __HANDLE__ CORDIC handle.
+ * @param __INTERRUPT__ CORDIC interrupt to check
+ * This parameter can be one of the following values:
+ * @arg @ref CORDIC_IT_IEN Enable Interrupt
+ * @retval FlagStatus
+ */
+#define __HAL_CORDIC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->CSR) & (__INTERRUPT__))
+
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup CORDIC_Private_Macros CORDIC Private Macros
+ * @{
+ */
+
+/**
+ * @brief Verify the CORDIC function.
+ * @param __FUNCTION__ Name of the function.
+ * @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
+ */
+#define IS_CORDIC_FUNCTION(__FUNCTION__) (((__FUNCTION__) == CORDIC_FUNCTION_COSINE) || \
+ ((__FUNCTION__) == CORDIC_FUNCTION_SINE) || \
+ ((__FUNCTION__) == CORDIC_FUNCTION_PHASE) || \
+ ((__FUNCTION__) == CORDIC_FUNCTION_MODULUS) || \
+ ((__FUNCTION__) == CORDIC_FUNCTION_ARCTANGENT) || \
+ ((__FUNCTION__) == CORDIC_FUNCTION_HCOSINE) || \
+ ((__FUNCTION__) == CORDIC_FUNCTION_HSINE) || \
+ ((__FUNCTION__) == CORDIC_FUNCTION_HARCTANGENT) || \
+ ((__FUNCTION__) == CORDIC_FUNCTION_NATURALLOG) || \
+ ((__FUNCTION__) == CORDIC_FUNCTION_SQUAREROOT))
+
+
+/**
+ * @brief Verify the CORDIC precision.
+ * @param __PRECISION__ CORDIC Precision in Cycles Number.
+ * @retval SET (__PRECISION__ is a valid value) or RESET (__PRECISION__ is invalid)
+ */
+#define IS_CORDIC_PRECISION(__PRECISION__) (((__PRECISION__) == CORDIC_PRECISION_1CYCLE) || \
+ ((__PRECISION__) == CORDIC_PRECISION_2CYCLES) || \
+ ((__PRECISION__) == CORDIC_PRECISION_3CYCLES) || \
+ ((__PRECISION__) == CORDIC_PRECISION_4CYCLES) || \
+ ((__PRECISION__) == CORDIC_PRECISION_5CYCLES) || \
+ ((__PRECISION__) == CORDIC_PRECISION_6CYCLES) || \
+ ((__PRECISION__) == CORDIC_PRECISION_7CYCLES) || \
+ ((__PRECISION__) == CORDIC_PRECISION_8CYCLES) || \
+ ((__PRECISION__) == CORDIC_PRECISION_9CYCLES) || \
+ ((__PRECISION__) == CORDIC_PRECISION_10CYCLES) || \
+ ((__PRECISION__) == CORDIC_PRECISION_11CYCLES) || \
+ ((__PRECISION__) == CORDIC_PRECISION_12CYCLES) || \
+ ((__PRECISION__) == CORDIC_PRECISION_13CYCLES) || \
+ ((__PRECISION__) == CORDIC_PRECISION_14CYCLES) || \
+ ((__PRECISION__) == CORDIC_PRECISION_15CYCLES))
+
+/**
+ * @brief Verify the CORDIC scaling factor.
+ * @param __SCALE__ Number of cycles for calculation, 1 cycle corresponding to 4 algorithm iterations.
+ * @retval SET (__SCALE__ is a valid value) or RESET (__SCALE__ is invalid)
+ */
+#define IS_CORDIC_SCALE(__SCALE__) (((__SCALE__) == CORDIC_SCALE_0) || \
+ ((__SCALE__) == CORDIC_SCALE_1) || \
+ ((__SCALE__) == CORDIC_SCALE_2) || \
+ ((__SCALE__) == CORDIC_SCALE_3) || \
+ ((__SCALE__) == CORDIC_SCALE_4) || \
+ ((__SCALE__) == CORDIC_SCALE_5) || \
+ ((__SCALE__) == CORDIC_SCALE_6) || \
+ ((__SCALE__) == CORDIC_SCALE_7))
+
+/**
+ * @brief Verify the CORDIC number of 32-bits write expected for one calculation.
+ * @param __NBWRITE__ Number of 32-bits write expected for one calculation.
+ * @retval SET (__NBWRITE__ is a valid value) or RESET (__NBWRITE__ is invalid)
+ */
+#define IS_CORDIC_NBWRITE(__NBWRITE__) (((__NBWRITE__) == CORDIC_NBWRITE_1) || \
+ ((__NBWRITE__) == CORDIC_NBWRITE_2))
+
+/**
+ * @brief Verify the CORDIC number of 32-bits read expected after one calculation.
+ * @param __NBREAD__ Number of 32-bits read expected after one calculation.
+ * @retval SET (__NBREAD__ is a valid value) or RESET (__NBREAD__ is invalid)
+ */
+#define IS_CORDIC_NBREAD(__NBREAD__) (((__NBREAD__) == CORDIC_NBREAD_1) || \
+ ((__NBREAD__) == CORDIC_NBREAD_2))
+
+/**
+ * @brief Verify the CORDIC input data size for one calculation.
+ * @param __INSIZE__ input data size for one calculation.
+ * @retval SET (__INSIZE__ is a valid value) or RESET (__INSIZE__ is invalid)
+ */
+#define IS_CORDIC_INSIZE(__INSIZE__) (((__INSIZE__) == CORDIC_INSIZE_32BITS) || \
+ ((__INSIZE__) == CORDIC_INSIZE_16BITS))
+
+/**
+ * @brief Verify the CORDIC output data size for one calculation.
+ * @param __OUTSIZE__ output data size for one calculation.
+ * @retval SET (__OUTSIZE__ is a valid value) or RESET (__OUTSIZE__ is invalid)
+ */
+#define IS_CORDIC_OUTSIZE(__OUTSIZE__) (((__OUTSIZE__) == CORDIC_OUTSIZE_32BITS) || \
+ ((__OUTSIZE__) == CORDIC_OUTSIZE_16BITS))
+
+/**
+ * @brief Verify the CORDIC DMA transfer Direction.
+ * @param __DMADIR__ DMA transfer direction.
+ * @retval SET (__DMADIR__ is a valid value) or RESET (__DMADIR__ is invalid)
+ */
+#define IS_CORDIC_DMA_DIRECTION(__DMADIR__) (((__DMADIR__) == CORDIC_DMA_DIR_IN) || \
+ ((__DMADIR__) == CORDIC_DMA_DIR_OUT) || \
+ ((__DMADIR__) == CORDIC_DMA_DIR_IN_OUT))
+
+/**
+ * @}
+ */
+
+/** @addtogroup CORDIC_Exported_Functions
+ * @{
+ */
+/* Exported functions ------------------------------------------------------- */
+
+/** @addtogroup CORDIC_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions ******************************/
+HAL_StatusTypeDef HAL_CORDIC_Init(CORDIC_HandleTypeDef *hcordic);
+HAL_StatusTypeDef HAL_CORDIC_DeInit(CORDIC_HandleTypeDef *hcordic);
+void HAL_CORDIC_MspInit(CORDIC_HandleTypeDef *hcordic);
+void HAL_CORDIC_MspDeInit(CORDIC_HandleTypeDef *hcordic);
+
+#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
+/* Callbacks Register/UnRegister functions ***********************************/
+HAL_StatusTypeDef HAL_CORDIC_RegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID,
+ pCORDIC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_CORDIC_UnRegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID);
+/**
+ * @}
+ */
+
+/** @addtogroup CORDIC_Exported_Functions_Group2
+ * @{
+ */
+#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, CORDIC_ConfigTypeDef *sConfig);
+HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
+ uint32_t NbCalc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
+ uint32_t NbCalc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
+ uint32_t NbCalc);
+HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
+ uint32_t NbCalc, uint32_t DMADirection);
+/**
+ * @}
+ */
+
+/** @addtogroup CORDIC_Exported_Functions_Group3
+ * @{
+ */
+/* Callback functions *********************************************************/
+void HAL_CORDIC_ErrorCallback(CORDIC_HandleTypeDef *hcordic);
+void HAL_CORDIC_CalculateCpltCallback(CORDIC_HandleTypeDef *hcordic);
+/**
+ * @}
+ */
+
+/** @addtogroup CORDIC_Exported_Functions_Group4
+ * @{
+ */
+/* IRQ handler management *****************************************************/
+void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic);
+/**
+ * @}
+ */
+
+/** @addtogroup CORDIC_Exported_Functions_Group5
+ * @{
+ */
+/* Peripheral State functions *************************************************/
+HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(CORDIC_HandleTypeDef *hcordic);
+uint32_t HAL_CORDIC_GetError(CORDIC_HandleTypeDef *hcordic);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* CORDIC */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_CORDIC_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cortex.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cortex.h
new file mode 100644
index 00000000..0cbe97f0
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cortex.h
@@ -0,0 +1,378 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_cortex.h
+ * @author MCD Application Team
+ * @brief Header file of CORTEX HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32U5xx_HAL_CORTEX_H
+#define __STM32U5xx_HAL_CORTEX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CORTEX CORTEX
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
+ * @{
+ */
+
+/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
+ * @{
+ */
+typedef struct
+{
+ uint8_t Enable; /*!< Specifies the status of the region.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
+ uint8_t Number; /*!< Specifies the index of the region to protect.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Number */
+ uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
+ uint32_t LimitAddress; /*!< Specifies the limit address of the region to protect. */
+ uint8_t AttributesIndex; /*!< Specifies the memory attributes index.
+ This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */
+ uint8_t AccessPermission; /*!< Specifies the region access permission type. This parameter
+ can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
+ uint8_t DisableExec; /*!< Specifies the instruction access status.
+ This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
+ uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
+ This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
+} MPU_Region_InitTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Attributes_Initialization_Structure_definition MPU Attributes
+ * Initialization Structure Definition
+ * @{
+ */
+typedef struct
+{
+ uint8_t Number; /*!< Specifies the number of the memory attributes to configure.
+ This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */
+
+ uint8_t Attributes; /*!< Specifies the memory attributes value. Attributes This parameter
+ can be a combination of @ref CORTEX_MPU_Attributes */
+
+} MPU_Attributes_InitTypeDef;
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
+ * @{
+ */
+
+/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
+ * @{
+ */
+#define NVIC_PRIORITYGROUP_0 0x7U /*!< 0 bit for pre-emption priority,
+ 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1 0x6U /*!< 1 bit for pre-emption priority,
+ 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2 0x5U /*!< 2 bits for pre-emption priority,
+ 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3 0x4U /*!< 3 bits for pre-emption priority,
+ 1 bit for subpriority */
+#define NVIC_PRIORITYGROUP_4 0x3U /*!< 4 bits for pre-emption priority,
+ 0 bit for subpriority */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
+ * @{
+ */
+#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x0U /*!< AHB clock divided by 8 selected as SysTick clock source */
+#define SYSTICK_CLKSOURCE_LSI 0x1U /*!< LSI clock selected as SysTick clock source */
+#define SYSTICK_CLKSOURCE_LSE 0x2U /*!< LSE clock selected as SysTick clock source */
+#define SYSTICK_CLKSOURCE_HCLK 0x4U /*!< AHB clock selected as SysTick clock source */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
+ * @{
+ */
+#define MPU_HFNMI_PRIVDEF_NONE 0U
+#define MPU_HARDFAULT_NMI 2U
+#define MPU_PRIVILEGED_DEFAULT 4U
+#define MPU_HFNMI_PRIVDEF 6U
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
+ * @{
+ */
+#define MPU_REGION_ENABLE 1U
+#define MPU_REGION_DISABLE 0U
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
+ * @{
+ */
+#define MPU_INSTRUCTION_ACCESS_ENABLE 0U
+#define MPU_INSTRUCTION_ACCESS_DISABLE 1U
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
+ * @{
+ */
+#define MPU_ACCESS_NOT_SHAREABLE 0U
+#define MPU_ACCESS_OUTER_SHAREABLE 1U
+#define MPU_ACCESS_INNER_SHAREABLE 3U
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
+ * @{
+ */
+#define MPU_REGION_PRIV_RW 0U
+#define MPU_REGION_ALL_RW 1U
+#define MPU_REGION_PRIV_RO 2U
+#define MPU_REGION_ALL_RO 3U
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
+ * @{
+ */
+#define MPU_REGION_NUMBER0 0U
+#define MPU_REGION_NUMBER1 1U
+#define MPU_REGION_NUMBER2 2U
+#define MPU_REGION_NUMBER3 3U
+#define MPU_REGION_NUMBER4 4U
+#define MPU_REGION_NUMBER5 5U
+#define MPU_REGION_NUMBER6 6U
+#define MPU_REGION_NUMBER7 7U
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Attributes_Number CORTEX MPU Memory Attributes Number
+ * @{
+ */
+#define MPU_ATTRIBUTES_NUMBER0 0U
+#define MPU_ATTRIBUTES_NUMBER1 1U
+#define MPU_ATTRIBUTES_NUMBER2 2U
+#define MPU_ATTRIBUTES_NUMBER3 3U
+#define MPU_ATTRIBUTES_NUMBER4 4U
+#define MPU_ATTRIBUTES_NUMBER5 5U
+#define MPU_ATTRIBUTES_NUMBER6 6U
+#define MPU_ATTRIBUTES_NUMBER7 7U
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Attributes CORTEX MPU Attributes
+ * @{
+ */
+#define MPU_DEVICE_nGnRnE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */
+#define MPU_DEVICE_nGnRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */
+#define MPU_DEVICE_nGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */
+#define MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */
+
+#define MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */
+#define MPU_NOT_CACHEABLE 0x4U /* Normal memory, non-cacheable. */
+#define MPU_WRITE_BACK 0x4U /* Normal memory, write-back. */
+
+#define MPU_TRANSIENT 0x0U /* Normal memory, transient. */
+#define MPU_NON_TRANSIENT 0x8U /* Normal memory, non-transient. */
+
+#define MPU_NO_ALLOCATE 0x0U /* Normal memory, no allocate. */
+#define MPU_W_ALLOCATE 0x1U /* Normal memory, write allocate. */
+#define MPU_R_ALLOCATE 0x2U /* Normal memory, read allocate. */
+#define MPU_RW_ALLOCATE 0x3U /* Normal memory, read/write allocate. */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
+ * @{
+ */
+#define OUTER(__ATTR__) ((__ATTR__) << 4U)
+#define INNER_OUTER(__ATTR__) ((__ATTR__) | ((__ATTR__) << 4U))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
+ * @{
+ */
+
+/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
+ * @{
+ */
+/* Initialization and Configuration functions *****************************/
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SystemReset(void);
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
+ * @brief Cortex control functions
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+uint32_t HAL_NVIC_GetPriorityGrouping(void);
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *const pPreemptPriority,
+ uint32_t *const pSubPriority);
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
+void HAL_SYSTICK_IRQHandler(void);
+void HAL_SYSTICK_Callback(void);
+
+void HAL_MPU_Enable(uint32_t MPU_Control);
+void HAL_MPU_Disable(void);
+void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *const pMPU_RegionInit);
+void HAL_MPU_ConfigMemoryAttributes(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit);
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/* MPU_NS Control functions ***********************************************/
+void HAL_MPU_Enable_NS(uint32_t MPU_Control);
+void HAL_MPU_Disable_NS(void);
+void HAL_MPU_ConfigRegion_NS(const MPU_Region_InitTypeDef *const pMPU_RegionInit);
+void HAL_MPU_ConfigMemoryAttributes_NS(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit);
+#endif /* __ARM_FEATURE_CMSE */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
+ * @{
+ */
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_1) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_2) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_3) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < (1UL<<__NVIC_PRIO_BITS))
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < (1UL<<__NVIC_PRIO_BITS))
+
+#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn)
+
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_LSI) || \
+ ((SOURCE) == SYSTICK_CLKSOURCE_LSE) || \
+ ((SOURCE) == SYSTICK_CLKSOURCE_HCLK)|| \
+ ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define IS_MPU_INSTANCE(INSTANCE) (((INSTANCE) == MPU) || ((INSTANCE) == MPU_NS))
+#endif /* __ARM_FEATURE_CMSE */
+
+#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
+ ((STATE) == MPU_REGION_DISABLE))
+
+#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
+ ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
+
+#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_OUTER_SHAREABLE) || \
+ ((STATE) == MPU_ACCESS_INNER_SHAREABLE) || \
+ ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
+
+#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_PRIV_RW) || \
+ ((TYPE) == MPU_REGION_ALL_RW) || \
+ ((TYPE) == MPU_REGION_PRIV_RO) || \
+ ((TYPE) == MPU_REGION_ALL_RO))
+
+#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
+ ((NUMBER) == MPU_REGION_NUMBER1) || \
+ ((NUMBER) == MPU_REGION_NUMBER2) || \
+ ((NUMBER) == MPU_REGION_NUMBER3) || \
+ ((NUMBER) == MPU_REGION_NUMBER4) || \
+ ((NUMBER) == MPU_REGION_NUMBER5) || \
+ ((NUMBER) == MPU_REGION_NUMBER6) || \
+ ((NUMBER) == MPU_REGION_NUMBER7))
+
+#define IS_MPU_ATTRIBUTES_NUMBER(NUMBER) (((NUMBER) == MPU_ATTRIBUTES_NUMBER0) || \
+ ((NUMBER) == MPU_ATTRIBUTES_NUMBER1) || \
+ ((NUMBER) == MPU_ATTRIBUTES_NUMBER2) || \
+ ((NUMBER) == MPU_ATTRIBUTES_NUMBER3) || \
+ ((NUMBER) == MPU_ATTRIBUTES_NUMBER4) || \
+ ((NUMBER) == MPU_ATTRIBUTES_NUMBER5) || \
+ ((NUMBER) == MPU_ATTRIBUTES_NUMBER6) || \
+ ((NUMBER) == MPU_ATTRIBUTES_NUMBER7))
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32U5xx_HAL_CORTEX_H */
+
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_crc.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_crc.h
new file mode 100644
index 00000000..a92999a8
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_crc.h
@@ -0,0 +1,342 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_crc.h
+ * @author MCD Application Team
+ * @brief Header file of CRC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_CRC_H
+#define STM32U5xx_HAL_CRC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CRC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CRC_Exported_Types CRC Exported Types
+ * @{
+ */
+
+/**
+ * @brief CRC HAL State Structure definition
+ */
+typedef enum
+{
+ HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */
+ HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */
+ HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */
+ HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */
+ HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */
+} HAL_CRC_StateTypeDef;
+
+/**
+ * @brief CRC Init Structure definition
+ */
+typedef struct
+{
+ uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
+ If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
+ X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 +
+ X^4 + X^2+ X +1.
+ In that case, there is no need to set GeneratingPolynomial field.
+ If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and
+ CRCLength fields must be set. */
+
+ uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
+ If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
+ 0xFFFFFFFF value. In that case, there is no need to set InitValue field. If
+ otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */
+
+ uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree
+ respectively equal to 7, 8, 16 or 32. This field is written in normal,
+ representation e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1
+ is written 0x65. No need to specify it if DefaultPolynomialUse is set to
+ DEFAULT_POLYNOMIAL_ENABLE. */
+
+ uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
+ Value can be either one of
+ @arg @ref CRC_POLYLENGTH_32B (32-bit CRC),
+ @arg @ref CRC_POLYLENGTH_16B (16-bit CRC),
+ @arg @ref CRC_POLYLENGTH_8B (8-bit CRC),
+ @arg @ref CRC_POLYLENGTH_7B (7-bit CRC). */
+
+ uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
+ is set to DEFAULT_INIT_VALUE_ENABLE. */
+
+ uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
+ Can be either one of the following values
+ @arg @ref CRC_INPUTDATA_INVERSION_NONE no input data inversion
+ @arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D
+ becomes 0x58D43CB2
+ @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion,
+ 0x1A2B3C4D becomes 0xD458B23C
+ @arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D
+ becomes 0xB23CD458 */
+
+ uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
+ Can be either
+ @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion,
+ @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted
+ into 0x22CC4488 */
+} CRC_InitTypeDef;
+
+/**
+ * @brief CRC Handle Structure definition
+ */
+typedef struct
+{
+ CRC_TypeDef *Instance; /*!< Register base address */
+
+ CRC_InitTypeDef Init; /*!< CRC configuration parameters */
+
+ HAL_LockTypeDef Lock; /*!< CRC Locking object */
+
+ __IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
+
+ uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
+ Can be either
+ @arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes
+ (8-bit data)
+ @arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of
+ half-words (16-bit data)
+ @arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words
+ (32-bit data)
+
+ Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization
+ error must occur if InputBufferFormat is not one of the three values listed
+ above */
+} CRC_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRC_Exported_Constants CRC Exported Constants
+ * @{
+ */
+
+/** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial
+ * @{
+ */
+#define DEFAULT_CRC32_POLY 0x04C11DB7U /*!< X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Default_InitValue Default CRC computation initialization value
+ * @{
+ */
+#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Initial CRC default value */
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used
+ * @{
+ */
+#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U) /*!< Enable default generating polynomial 0x04C11DB7 */
+#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U) /*!< Disable default generating polynomial 0x04C11DB7 */
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used
+ * @{
+ */
+#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U) /*!< Enable initial CRC default value */
+#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U) /*!< Disable initial CRC default value */
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the peripheral
+ * @{
+ */
+#define CRC_POLYLENGTH_32B 0x00000000U /*!< Resort to a 32-bit long generating polynomial */
+#define CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< Resort to a 16-bit long generating polynomial */
+#define CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< Resort to a 8-bit long generating polynomial */
+#define CRC_POLYLENGTH_7B CRC_CR_POLYSIZE /*!< Resort to a 7-bit long generating polynomial */
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
+ * @{
+ */
+#define HAL_CRC_LENGTH_32B 32U /*!< 32-bit long CRC */
+#define HAL_CRC_LENGTH_16B 16U /*!< 16-bit long CRC */
+#define HAL_CRC_LENGTH_8B 8U /*!< 8-bit long CRC */
+#define HAL_CRC_LENGTH_7B 7U /*!< 7-bit long CRC */
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Input_Buffer_Format Input Buffer Format
+ * @{
+ */
+/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
+ * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
+ * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
+ * the CRC APIs to provide a correct result */
+#define CRC_INPUTDATA_FORMAT_UNDEFINED 0x00000000U /*!< Undefined input data format */
+#define CRC_INPUTDATA_FORMAT_BYTES 0x00000001U /*!< Input data in byte format */
+#define CRC_INPUTDATA_FORMAT_HALFWORDS 0x00000002U /*!< Input data in half-word format */
+#define CRC_INPUTDATA_FORMAT_WORDS 0x00000003U /*!< Input data in word format */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CRC_Exported_Macros CRC Exported Macros
+ * @{
+ */
+
+/** @brief Reset CRC handle state.
+ * @param __HANDLE__ CRC handle.
+ * @retval None
+ */
+#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
+
+/**
+ * @brief Reset CRC Data Register.
+ * @param __HANDLE__ CRC handle
+ * @retval None
+ */
+#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
+
+/**
+ * @brief Set CRC INIT non-default value
+ * @param __HANDLE__ CRC handle
+ * @param __INIT__ 32-bit initial value
+ * @retval None
+ */
+#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
+
+/**
+ * @brief Store data in the Independent Data (ID) register.
+ * @param __HANDLE__ CRC handle
+ * @param __VALUE__ Value to be stored in the ID register
+ * @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
+ * @retval None
+ */
+#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
+
+/**
+ * @brief Return the data stored in the Independent Data (ID) register.
+ * @param __HANDLE__ CRC handle
+ * @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
+ * @retval Value of the ID register
+ */
+#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
+/**
+ * @}
+ */
+
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup CRC_Private_Macros CRC Private Macros
+ * @{
+ */
+
+#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
+ ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
+
+#define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
+ ((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
+
+#define IS_CRC_POL_LENGTH(LENGTH) (((LENGTH) == CRC_POLYLENGTH_32B) || \
+ ((LENGTH) == CRC_POLYLENGTH_16B) || \
+ ((LENGTH) == CRC_POLYLENGTH_8B) || \
+ ((LENGTH) == CRC_POLYLENGTH_7B))
+
+#define IS_CRC_INPUTDATA_FORMAT(FORMAT) (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \
+ ((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
+ ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))
+
+/**
+ * @}
+ */
+
+/* Include CRC HAL Extended module */
+#include "stm32u5xx_hal_crc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRC_Exported_Functions CRC Exported Functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
+HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc);
+void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
+void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
+/**
+ * @}
+ */
+
+/* Peripheral Control functions ***********************************************/
+/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
+ * @{
+ */
+uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
+/**
+ * @}
+ */
+
+/* Peripheral State and Error functions ***************************************/
+/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
+ * @{
+ */
+HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_CRC_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_crc_ex.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_crc_ex.h
new file mode 100644
index 00000000..89c5c441
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_crc_ex.h
@@ -0,0 +1,150 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_crc_ex.h
+ * @author MCD Application Team
+ * @brief Header file of CRC HAL extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_CRC_EX_H
+#define STM32U5xx_HAL_CRC_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CRCEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants
+ * @{
+ */
+
+/** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes
+ * @{
+ */
+#define CRC_INPUTDATA_INVERSION_NONE 0x00000000U /*!< No input data inversion */
+#define CRC_INPUTDATA_INVERSION_BYTE CRC_CR_REV_IN_0 /*!< Byte-wise input data inversion */
+#define CRC_INPUTDATA_INVERSION_HALFWORD CRC_CR_REV_IN_1 /*!< HalfWord-wise input data inversion */
+#define CRC_INPUTDATA_INVERSION_WORD CRC_CR_REV_IN /*!< Word-wise input data inversion */
+/**
+ * @}
+ */
+
+/** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes
+ * @{
+ */
+#define CRC_OUTPUTDATA_INVERSION_DISABLE 0x00000000U /*!< No output data inversion */
+#define CRC_OUTPUTDATA_INVERSION_ENABLE CRC_CR_REV_OUT /*!< Bit-wise output data inversion */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Set CRC output reversal
+ * @param __HANDLE__ CRC handle
+ * @retval None
+ */
+#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
+
+/**
+ * @brief Unset CRC output reversal
+ * @param __HANDLE__ CRC handle
+ * @retval None
+ */
+#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
+
+/**
+ * @brief Set CRC non-default polynomial
+ * @param __HANDLE__ CRC handle
+ * @param __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial
+ * @retval None
+ */
+#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
+
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup CRCEx_Private_Macros CRC Extended Private Macros
+ * @{
+ */
+
+#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \
+ ((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \
+ ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
+ ((MODE) == CRC_INPUTDATA_INVERSION_WORD))
+
+#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
+ ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup CRCEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup CRCEx_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
+HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
+HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_CRC_EX_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cryp.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cryp.h
new file mode 100644
index 00000000..8da0eaee
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cryp.h
@@ -0,0 +1,669 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_cryp.h
+ * @author MCD Application Team
+ * @brief Header file of CRYP HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_CRYP_H
+#define STM32U5xx_HAL_CRYP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+#if defined(AES)
+
+/** @defgroup CRYP CRYP
+ * @brief CRYP HAL module driver.
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup CRYP_Exported_Types CRYP Exported Types
+ * @{
+ */
+
+/**
+ * @brief CRYP Init Structure definition
+ */
+
+typedef struct
+{
+ uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
+ This parameter can be a value of @ref CRYP_Data_Type */
+ uint32_t KeySize; /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
+ 128 or 256 bit key length in TinyAES This parameter can be a value
+ of @ref CRYP_Key_Size */
+ uint32_t *pKey; /*!< The key used for encryption/decryption */
+ uint32_t *pInitVect; /*!< The initialization vector used also as initialization
+ counter in CTR mode */
+ uint32_t Algorithm; /*!< DES/ TDES Algorithm ECB/CBC
+ AES Algorithm ECB/CBC/CTR/GCM or CCM
+ This parameter can be a value of @ref CRYP_Algorithm_Mode */
+ uint32_t *Header; /*!< used only in AES GCM and CCM Algorithm for authentication,
+ GCM : also known as Additional Authentication Data
+ CCM : named B1 composed of the associated data length and Associated Data. */
+ uint32_t HeaderSize; /*!< The size of header buffer */
+ uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */
+ uint32_t DataWidthUnit; /*!< Payload Data Width Unit, this parameter can be value of @ref CRYP_Data_Width_Unit */
+ uint32_t HeaderWidthUnit; /*!< Header Width Unit, this parameter can be value of @ref CRYP_Header_Width_Unit */
+ uint32_t KeyIVConfigSkip; /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization
+ Vector only once and to skip configuration for consecutive processings.
+ This parameter can be a value of @ref CRYP_Configuration_Skip */
+ uint32_t KeyMode; /*!< Key mode selection, this parameter can be value of @ref CRYP_Key_Mode */
+ uint32_t KeySelect; /*!< Only for SAES : Key selection, this parameter can be value of @ref CRYP_Key_Select */
+ uint32_t KeyProtection; /*!< Only for SAES : Key protection, this parameter can be value of @ref CRYP_Key_Protection */
+
+} CRYP_ConfigTypeDef;
+
+
+/**
+ * @brief CRYP State Structure definition
+ */
+
+typedef enum
+{
+ HAL_CRYP_STATE_RESET = 0x00U, /*!< CRYP not yet initialized or disabled */
+ HAL_CRYP_STATE_READY = 0x01U, /*!< CRYP initialized and ready for use */
+ HAL_CRYP_STATE_BUSY = 0x02U, /*!< CRYP BUSY, internal processing is ongoing */
+#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
+ HAL_CRYP_STATE_SUSPENDED = 0x03U, /*!< CRYP suspended */
+#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
+} HAL_CRYP_STATETypeDef;
+
+#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
+/**
+ * @brief HAL CRYP mode suspend definitions
+ */
+typedef enum
+{
+ HAL_CRYP_SUSPEND_NONE = 0x00U, /*!< CRYP processing suspension not requested */
+ HAL_CRYP_SUSPEND = 0x01U /*!< CRYP processing suspension requested */
+} HAL_SuspendTypeDef;
+#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
+
+/**
+ * @brief CRYP handle Structure definition
+ */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+typedef struct __CRYP_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+{
+ AES_TypeDef *Instance; /*!< AES Register base address */
+
+ CRYP_ConfigTypeDef Init; /*!< CRYP required parameters */
+ uint32_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
+
+ uint32_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
+
+ __IO uint16_t CrypHeaderCount; /*!< Counter of header data in words */
+
+ __IO uint16_t CrypInCount; /*!< Counter of input data in words */
+
+ __IO uint16_t CrypOutCount; /*!< Counter of output data in words */
+
+ uint16_t Size; /*!< length of input data in word or in byte, according to DataWidthUnit */
+
+ uint32_t Phase; /*!< CRYP peripheral phase */
+
+ DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< CRYP locking object */
+
+ __IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */
+
+ __IO uint32_t ErrorCode; /*!< CRYP peripheral error code */
+
+ uint32_t KeyIVConfig; /*!< CRYP peripheral Key and IV configuration flag, used when
+ configuration can be skipped */
+
+ uint32_t SizesSum; /*!< Sum of successive payloads lengths (in bytes), stored
+ for a single signature computation after several
+ messages processing */
+
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ void (*InCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Input FIFO transfer completed callback */
+ void (*OutCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Output FIFO transfer completed callback */
+ void (*ErrorCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Error callback */
+
+ void (* MspInitCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Msp Init callback */
+ void (* MspDeInitCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Msp DeInit callback */
+
+#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
+
+#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
+
+ __IO HAL_SuspendTypeDef SuspendRequest; /*!< CRYP peripheral suspension request flag */
+
+ CRYP_ConfigTypeDef Init_saved; /*!< copy of CRYP required parameters when processing is suspended */
+
+ uint32_t *pCrypInBuffPtr_saved; /*!< copy of CRYP input pointer when processing is suspended */
+
+ uint32_t *pCrypOutBuffPtr_saved; /*!< copy of CRYP output pointer when processing is suspended */
+
+ uint32_t CrypInCount_saved; /*!< copy of CRYP input data counter when processing is suspended */
+
+ uint32_t CrypOutCount_saved; /*!< copy of CRYP output data counter when processing is suspended */
+
+ uint32_t Phase_saved; /*!< copy of CRYP authentication phase when processing is suspended */
+
+ __IO HAL_CRYP_STATETypeDef State_saved; /*!< copy of CRYP peripheral state when processing is suspended */
+
+ uint32_t IV_saved[4]; /*!< copy of Initialisation Vector registers */
+
+ uint32_t SUSPxR_saved[8]; /*!< copy of suspension registers */
+
+ uint32_t CR_saved; /*!< copy of CRYP control register when processing is suspended*/
+
+ uint32_t Key_saved[8]; /*!< copy of key registers */
+
+ uint16_t Size_saved; /*!< copy of input buffer size */
+
+ uint16_t CrypHeaderCount_saved; /*!< copy of CRYP header data counter when processing is suspended */
+
+ uint32_t SizesSum_saved; /*!< copy of SizesSum when processing is suspended */
+
+ uint32_t ResumingFlag; /*!< resumption flag to bypass steps already carried out */
+#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
+
+} CRYP_HandleTypeDef;
+
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+
+/**
+ * @brief HAL CRYP Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_CRYP_MSPINIT_CB_ID = 0x00U, /*!< CRYP MspInit callback ID */
+ HAL_CRYP_MSPDEINIT_CB_ID = 0x01U, /*!< CRYP MspDeInit callback ID */
+ HAL_CRYP_INPUT_COMPLETE_CB_ID = 0x02U, /*!< CRYP Input FIFO transfer completed callback ID */
+ HAL_CRYP_OUTPUT_COMPLETE_CB_ID = 0x03U, /*!< CRYP Output FIFO transfer completed callback ID */
+ HAL_CRYP_ERROR_CB_ID = 0x04U, /*!< CRYP Error callback ID */
+} HAL_CRYP_CallbackIDTypeDef;
+
+/**
+ * @brief HAL CRYP Callback pointer definition
+ */
+typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< pointer to a common CRYP callback function */
+
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRYP_Exported_Constants CRYP Exported Constants
+ * @{
+ */
+
+/** @defgroup CRYP_Error_Definition CRYP Error Definition
+ * @{
+ */
+#define HAL_CRYP_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_CRYP_ERROR_WRITE 0x00000001U /*!< Write error */
+#define HAL_CRYP_ERROR_READ 0x00000002U /*!< Read error */
+#define HAL_CRYP_ERROR_DMA 0x00000004U /*!< DMA error */
+#define HAL_CRYP_ERROR_BUSY 0x00000008U /*!< Busy flag error */
+#define HAL_CRYP_ERROR_TIMEOUT 0x00000010U /*!< Timeout error */
+#define HAL_CRYP_ERROR_NOT_SUPPORTED 0x00000020U /*!< Not supported mode */
+#define HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U /*!< Sequence are not respected only for GCM or CCM */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+#define HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U) /*!< Invalid Callback error */
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+#define HAL_CRYP_ERROR_KEY 0x00000100U /*!< Key error */
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Data_Width_Unit CRYP Data Width Unit
+ * @{
+ */
+
+#define CRYP_DATAWIDTHUNIT_WORD 0x00000000U /*!< By default, size unit is word */
+#define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U /*!< By default, size unit is byte */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Header_Width_Unit CRYP Header Width Unit
+ * @{
+ */
+
+#define CRYP_HEADERWIDTHUNIT_WORD 0x00000000U /*!< By default, header size unit is word */
+#define CRYP_HEADERWIDTHUNIT_BYTE 0x00000001U /*!< By default, header size unit is byte */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Algorithm_Mode CRYP Algorithm Mode
+ * @{
+ */
+
+#define CRYP_AES_ECB 0x00000000U /*!< Electronic codebook chaining algorithm */
+#define CRYP_AES_CBC AES_CR_CHMOD_0 /*!< Cipher block chaining algorithm */
+#define CRYP_AES_CTR AES_CR_CHMOD_1 /*!< Counter mode chaining algorithm */
+#define CRYP_AES_GCM_GMAC (AES_CR_CHMOD_0 | AES_CR_CHMOD_1) /*!< Galois counter mode - Galois message authentication code */
+#define CRYP_AES_CCM AES_CR_CHMOD_2 /*!< Counter with Cipher Mode */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Key_Size CRYP Key Size
+ * @{
+ */
+
+#define CRYP_KEYSIZE_128B 0x00000000U /*!< 128-bit long key */
+#define CRYP_KEYSIZE_256B AES_CR_KEYSIZE /*!< 256-bit long key */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Key_Mode CRYP Key Mode
+ * @{
+ */
+
+#define CRYP_KEYMODE_NORMAL 0x00000000U /*!< Normal key usage, Key registers are freely usable */
+#define CRYP_KEYMODE_SHARED AES_CR_KMOD_1 /*!< Shared key */
+#define CRYP_KEYMODE_WRAPPED AES_CR_KMOD_0 /*!< Only for SAES, Wrapped key: to encrypt or decrypt AES keys */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Key_Select CRYP Key Select
+ * @{
+ */
+
+#define CRYP_KEYSEL_NORMAL 0x00000000U /*!< Normal key, key registers SAES_KEYx or CRYP_KEYx */
+#define CRYP_KEYSEL_HW AES_CR_KEYSEL_0 /*!< Only for SAES, Hardware key : derived hardware unique key (DHUK 256-bit) */
+#define CRYP_KEYSEL_SW AES_CR_KEYSEL_1 /*!< Only for SAES, Software key : boot hardware key BHK (256-bit) */
+#define CRYP_KEYSEL_HSW AES_CR_KEYSEL_2 /*!< Only for SAES, DHUK XOR BHK Hardware unique key XOR software key */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Key_ShareID CRYP Key Share ID
+ * @{
+ */
+
+#define CRYP_KSHAREID_AES 0x00000000U /*!< Share SAES Key with AES peripheral */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Key_Protection CRYP Key Protection
+ * @{
+ */
+
+#define CRYP_KEYPROT_ENABLE AES_CR_KEYPROT /*!< Only for SAES, Key protection between 2 applications with different security contexts */
+#define CRYP_KEYPROT_DISABLE 0x00000000U /*!< Only for SAES, Key not protected between 2 applications with different security contexts */
+/**
+ * @}
+ */
+
+
+/** @defgroup CRYP_Data_Type CRYP Data Type
+ * @{
+ */
+
+#define CRYP_NO_SWAP 0x00000000U /*!< 32-bit data type (no swapping) */
+#define CRYP_HALFWORD_SWAP AES_CR_DATATYPE_0 /*!< 16-bit data type (half-word swapping) */
+#define CRYP_BYTE_SWAP AES_CR_DATATYPE_1 /*!< 8-bit data type (byte swapping) */
+#define CRYP_BIT_SWAP AES_CR_DATATYPE /*!< 1-bit data type (bit swapping) */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Interrupt CRYP Interrupt
+ * @{
+ */
+#define CRYP_IT_CCFIE AES_IER_CCFIE /*!< Computation Complete interrupt enable */
+#define CRYP_IT_RWEIE AES_IER_RWEIE /*!< Read or write Error interrupt enable */
+#define CRYP_IT_KEIE AES_IER_KEIE /*!< Key error interrupt enable */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Flags CRYP Flags
+ * @{
+ */
+
+#define CRYP_FLAG_BUSY AES_SR_BUSY /*!< GCM process suspension forbidden
+ also set when transferring a shared key from SAES peripheral */
+#define CRYP_FLAG_WRERR (AES_SR_WRERR | 0x80000000U) /*!< Write Error flag */
+#define CRYP_FLAG_RDERR (AES_SR_RDERR | 0x80000000U) /*!< Read error flag */
+#define CRYP_FLAG_CCF AES_SR_CCF /*!< Computation completed flag as AES_ISR_CCF */
+#define CRYP_FLAG_KEYVALID AES_SR_KEYVALID /*!< Key Valid flag */
+#define CRYP_FLAG_KEIF AES_ISR_KEIF /*Key error interrupt flag */
+#define CRYP_FLAG_RWEIF AES_ISR_RWEIF /*Read or write error Interrupt flag */
+
+
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_CLEAR_Flags CRYP CLEAR Flags
+ * @{
+ */
+
+#define CRYP_CLEAR_CCF AES_ICR_CCF /* Computation Complete Flag Clear */
+#define CRYP_CLEAR_RWEIF AES_ICR_RWEIF /* Clear Error Flag : RWEIF in AES_ISR and
+ both RDERR and WRERR flags in AES_SR */
+#define CRYP_CLEAR_KEIF AES_ICR_KEIF /* Clear Key Error Flag: KEIF in AES_ISR */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Configuration_Skip CRYP Key and IV Configuration Skip Mode
+ * @{
+ */
+
+#define CRYP_KEYIVCONFIG_ALWAYS 0x00000000U /*!< Peripheral Key and IV configuration to do systematically */
+#define CRYP_KEYIVCONFIG_ONCE 0x00000001U /*!< Peripheral Key and IV configuration to do only once */
+#define CRYP_KEYNOCONFIG 0x00000002U /*!< Peripheral Key configuration to not do */
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CRYP_Exported_Macros CRYP Exported Macros
+ * @{
+ */
+
+/** @brief Reset CRYP handle state
+ * @param __HANDLE__ specifies the CRYP handle.
+ * @retval None
+ */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) do{\
+ (__HANDLE__)->State = HAL_CRYP_STATE_RESET;\
+ (__HANDLE__)->MspInitCallback = NULL;\
+ (__HANDLE__)->MspDeInitCallback = NULL;\
+ }while(0U)
+#else
+#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_CRYP_STATE_RESET)
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+
+/**
+ * @brief Enable/Disable the CRYP peripheral.
+ * @param __HANDLE__ specifies the CRYP handle.
+ * @retval None
+ */
+
+#define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= AES_CR_EN)
+#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~AES_CR_EN)
+
+
+/** @brief Check whether the specified CRYP status flag is set or not.
+ * @param __HANDLE__ specifies the CRYP handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values for TinyAES:
+ * @arg @ref CRYP_FLAG_KEYVALID Key valid flag
+ * @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden or
+ * transferring a shared key from SAES IP.
+ * @arg @ref CRYP_FLAG_WRERR Write Error flag
+ * @arg @ref CRYP_FLAG_RDERR Read Error flag
+ * @arg @ref CRYP_FLAG_CCF Computation Complete flag
+ * @arg @ref CRYP_FLAG_KEIF Key error flag
+ * @arg @ref CRYP_FLAG_RWEIF Read/write Error flag
+
+ * @retval The state of __FLAG__ (TRUE or FALSE).
+ */
+
+#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (\
+ ((__FLAG__) == CRYP_FLAG_KEYVALID )?(((__HANDLE__)->Instance->SR \
+ & (CRYP_FLAG_KEYVALID)) == (CRYP_FLAG_KEYVALID)) : \
+ ((__FLAG__) == CRYP_FLAG_BUSY )?(((__HANDLE__)->Instance->SR \
+ & (CRYP_FLAG_BUSY)) == (CRYP_FLAG_BUSY)) : \
+ ((__FLAG__) == CRYP_FLAG_WRERR )?(((__HANDLE__)->Instance->SR \
+ & (CRYP_FLAG_WRERR & 0x7FFFFFFFU)) == \
+ (CRYP_FLAG_WRERR & 0x7FFFFFFFU)) : \
+ ((__FLAG__) == CRYP_FLAG_RDERR )?(((__HANDLE__)->Instance->SR \
+ & (CRYP_FLAG_RDERR & 0x7FFFFFFFU)) == \
+ (CRYP_FLAG_RDERR & 0x7FFFFFFFU)) : \
+ ((__FLAG__) == CRYP_FLAG_KEIF )?(((__HANDLE__)->Instance->ISR \
+ & (CRYP_FLAG_KEIF)) == (CRYP_FLAG_KEIF)) : \
+ ((__FLAG__) == CRYP_FLAG_RWEIF )?(((__HANDLE__)->Instance->ISR \
+ & (CRYP_FLAG_RWEIF)) == (CRYP_FLAG_RWEIF)) : \
+ (((__HANDLE__)->Instance->ISR & (CRYP_FLAG_CCF)) == (CRYP_FLAG_CCF)))
+
+/** @brief Clear the CRYP pending status flag.
+ * @param __HANDLE__ specifies the CRYP handle.
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be one of the following values:
+ * @arg @ref CRYP_CLEAR_RWEIF Read (RDERR), Write (WRERR) or Read/write (RWEIF) Error Flag Clear
+ * @arg @ref CRYP_CLEAR_CCF Computation Complete Flag (CCF) Clear
+ * @arg @ref CRYP_CLEAR_KEIF Key error interrupt flag clear
+ * @retval None
+ */
+
+#define __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT((__HANDLE__)->Instance->ICR, (__FLAG__))
+
+
+/** @brief Check whether the specified CRYP interrupt source is enabled or not.
+ * @param __HANDLE__ specifies the CRYP handle.
+ * @param __INTERRUPT__ CRYP interrupt source to check
+ * This parameter can be one of the following values for TinyAES:
+ * @arg @ref CRYP_IT_RWEIE Error interrupt (used for RDERR and WRERR)
+ * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
+ * @arg @ref CRYP_IT_KEIE Key error interrupt
+ * @retval State of interruption (TRUE or FALSE).
+ */
+
+#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER\
+ & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+ * @brief Enable the CRYP interrupt.
+ * @param __HANDLE__ specifies the CRYP handle.
+ * @param __INTERRUPT__ CRYP Interrupt.
+ * This parameter can be one of the following values for TinyAES:
+ * @arg @ref CRYP_IT_RWEIE Error interrupt (used for RDERR and WRERR)
+ * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
+ * @arg @ref CRYP_IT_KEIE Key error interrupt
+ * @retval None
+ */
+
+#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the CRYP interrupt.
+ * @param __HANDLE__ specifies the CRYP handle.
+ * @param __INTERRUPT__ CRYP Interrupt.
+ * This parameter can be one of the following values for TinyAES:
+ * @arg @ref CRYP_IT_RWEIE Error interrupt (used for RDERR and WRERR)
+ * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
+ * @arg @ref CRYP_IT_KEIE Key error interrupt
+ * @retval None
+ */
+
+#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
+
+/**
+ * @}
+ */
+
+/* Include CRYP HAL Extended module */
+#include "stm32u5xx_hal_cryp_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
+ * @{
+ */
+
+/** @addtogroup CRYP_Exported_Functions_Group1
+ * @{
+ */
+HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
+HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
+HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
+HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID,
+ pCRYP_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
+void HAL_CRYP_ProcessSuspend(CRYP_HandleTypeDef *hcryp);
+HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp);
+HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp);
+#endif /* defined (USE_HAL_CRYP_SUSPEND_RESUME) */
+/**
+ * @}
+ */
+
+/** @addtogroup CRYP_Exported_Functions_Group2
+ * @{
+ */
+
+/* encryption/decryption ***********************************/
+HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint16_t Size, uint32_t *pOutput,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint16_t Size, uint32_t *pOutput,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint16_t Size, uint32_t *pOutput);
+HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint16_t Size, uint32_t *pOutput);
+HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint16_t Size, uint32_t *pOutput);
+HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint16_t Size, uint32_t *pOutput);
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup CRYP_Exported_Functions_Group3
+ * @{
+ */
+/* Interrupt Handler functions **********************************************/
+void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
+HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
+uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup CRYP_Private_Macros CRYP Private Macros
+ * @{
+ */
+
+#define IS_CRYP_INSTANCE(INSTANCE)(((INSTANCE) == AES) || \
+ ((INSTANCE) == SAES))
+
+#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_AES_ECB) || \
+ ((ALGORITHM) == CRYP_AES_CBC) || \
+ ((ALGORITHM) == CRYP_AES_CTR) || \
+ ((ALGORITHM) == CRYP_AES_GCM_GMAC)|| \
+ ((ALGORITHM) == CRYP_AES_CCM))
+
+
+#define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B) || \
+ ((KEYSIZE) == CRYP_KEYSIZE_256B))
+
+#define IS_CRYP_DATATYPE(DATATYPE)(((DATATYPE) == CRYP_NO_SWAP) || \
+ ((DATATYPE) == CRYP_HALFWORD_SWAP) || \
+ ((DATATYPE) == CRYP_BYTE_SWAP) || \
+ ((DATATYPE) == CRYP_BIT_SWAP))
+
+#define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \
+ ((CONFIG) == CRYP_KEYIVCONFIG_ONCE))
+
+#define IS_CRYP_BUFFERSIZE(ALGO, DATAWIDTH, SIZE) \
+ (((((ALGO) == CRYP_AES_CTR)) && \
+ ((((DATAWIDTH) == CRYP_DATAWIDTHUNIT_WORD) && (((SIZE) % 4U) == 0U)) || \
+ (((DATAWIDTH) == CRYP_DATAWIDTHUNIT_BYTE) && (((SIZE) % 16U) == 0U)))) || \
+ (((ALGO) == CRYP_AES_ECB) || ((ALGO) == CRYP_AES_CBC) || \
+ ((ALGO)== CRYP_AES_GCM_GMAC) || ((ALGO) == CRYP_AES_CCM)))
+
+
+/**
+ * @}
+ */
+
+
+/* Private constants ---------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup CRYP_Private_Defines CRYP Private Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CRYP_Private_Functions CRYP Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* AES */
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_CRYP_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cryp_ex.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cryp_ex.h
new file mode 100644
index 00000000..3cbd5f59
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cryp_ex.h
@@ -0,0 +1,98 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_cryp_ex.h
+ * @author MCD Application Team
+ * @brief Header file of CRYPEx HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_CRYP_EX_H
+#define STM32U5xx_HAL_CRYP_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+#if defined(AES)
+
+/** @defgroup CRYPEx CRYPEx
+ * @brief CRYP Extension HAL module driver.
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
+ * @{
+ */
+
+/** @addtogroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *pAuthTag, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *pAuthTag, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/** @addtogroup CRYPEx_Exported_Functions_Group2 Wrap and Unwrap key functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_CRYPEx_UnwrapKey(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_WrapKey(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint32_t *pOutput, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/** @addtogroup CRYPEx_Exported_Functions_Group3 Encrypt/Decrypt Shared key functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_CRYPEx_EncryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_t *pKey, uint32_t *pOutput, uint32_t ID,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_DecryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_t *pKey, uint32_t ID, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* AES */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_CRYP_EX_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dac.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dac.h
new file mode 100644
index 00000000..a00bb9be
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dac.h
@@ -0,0 +1,570 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_dac.h
+ * @author MCD Application Team
+ * @brief Header file of DAC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_DAC_H
+#define STM32U5xx_HAL_DAC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+#if defined(DAC1)
+
+/** @addtogroup DAC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Types DAC Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */
+ HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */
+ HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */
+ HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */
+ HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */
+
+} HAL_DAC_StateTypeDef;
+
+/**
+ * @brief DAC handle Structure definition
+ */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+typedef struct __DAC_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+{
+ DAC_TypeDef *Instance; /*!< Register base address */
+
+ __IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */
+
+ HAL_LockTypeDef Lock; /*!< DAC locking object */
+
+ DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */
+
+ DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
+
+ __IO uint32_t ErrorCode; /*!< DAC Error code */
+
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
+ void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
+ void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
+ void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
+
+ void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
+ void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
+ void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
+ void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
+
+
+ void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac);
+ void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
+} DAC_HandleTypeDef;
+
+/**
+ * @brief DAC Configuration sample and hold Channel structure definition
+ */
+typedef struct
+{
+ uint32_t DAC_SampleTime ; /*!< Specifies the Sample time for the selected channel.
+ This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
+
+ uint32_t DAC_HoldTime ; /*!< Specifies the hold time for the selected channel
+ This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
+
+ uint32_t DAC_RefreshTime ; /*!< Specifies the refresh time for the selected channel
+ This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 255 */
+} DAC_SampleAndHoldConfTypeDef;
+
+/**
+ * @brief DAC Configuration regular Channel structure definition
+ */
+typedef struct
+{
+ uint32_t DAC_HighFrequency; /*!< Specifies the frequency interface mode
+ This parameter can be a value of @ref DAC_HighFrequency */
+
+ uint32_t DAC_AutonomousMode; /*!< Specifies whether the autonomous mode state
+ This parameter can be a value of @ref DACx_Autonomous_mode */
+
+ FunctionalState DAC_DMADoubleDataMode; /*!< Specifies if DMA double data mode should be enabled or not for the selected channel.
+ This parameter can be ENABLE or DISABLE */
+
+ FunctionalState DAC_SignedFormat; /*!< Specifies if signed format should be used or not for the selected channel.
+ This parameter can be ENABLE or DISABLE */
+
+ uint32_t DAC_SampleAndHold; /*!< Specifies whether the DAC mode.
+ This parameter can be a value of @ref DAC_SampleAndHold */
+
+ uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
+ This parameter can be a value of @ref DAC_trigger_selection */
+
+ uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+ This parameter can be a value of @ref DAC_output_buffer */
+
+ uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral .
+ This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */
+
+ uint32_t DAC_UserTrimming; /*!< Specifies the trimming mode
+ This parameter must be a value of @ref DAC_UserTrimming
+ DAC_UserTrimming is either factory or user trimming */
+
+ uint32_t DAC_TrimmingValue; /*!< Specifies the offset trimming value
+ i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
+ DAC_SampleAndHoldConfTypeDef DAC_SampleAndHoldConfig; /*!< Sample and Hold settings */
+} DAC_ChannelConfTypeDef;
+
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL DAC Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_DAC_CH1_COMPLETE_CB_ID = 0x00U, /*!< DAC CH1 Complete Callback ID */
+ HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, /*!< DAC CH1 half Complete Callback ID */
+ HAL_DAC_CH1_ERROR_ID = 0x02U, /*!< DAC CH1 error Callback ID */
+ HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U, /*!< DAC CH1 underrun Callback ID */
+
+ HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, /*!< DAC CH2 Complete Callback ID */
+ HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */
+ HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */
+ HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */
+
+ HAL_DAC_MSPINIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */
+ HAL_DAC_MSPDEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */
+ HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */
+} HAL_DAC_CallbackIDTypeDef;
+
+/**
+ * @brief HAL DAC Callback pointer definition
+ */
+typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Constants DAC Exported Constants
+ * @{
+ */
+
+/** @defgroup DAC_Error_Code DAC Error Code
+ * @{
+ */
+#define HAL_DAC_ERROR_NONE 0x00U /*!< No error */
+#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DMA underrun error */
+#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DMA underrun error */
+#define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */
+#define HAL_DAC_ERROR_TIMEOUT 0x08U /*!< Timeout error */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+#define HAL_DAC_ERROR_INVALID_CALLBACK 0x10U /*!< Invalid callback error */
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_trigger_selection DAC trigger selection
+ * @{
+ */
+#define DAC_TRIGGER_NONE 0x00000000UL /*!< conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */
+#define DAC_TRIGGER_SOFTWARE ( DAC_CR_TEN1) /*!< conversion started by software trigger for DAC channel */
+#define DAC_TRIGGER_T1_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel. */
+#define DAC_TRIGGER_T2_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T4_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T5_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T15_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TEN1) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_LPTIM1_CH1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< LPTIM1 CH1 selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_LPTIM3_CH1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< LPTIM3 CH1 selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_output_buffer DAC output buffer
+ * @{
+ */
+#define DAC_OUTPUTBUFFER_ENABLE 0x00000000U
+#define DAC_OUTPUTBUFFER_DISABLE (DAC_MCR_MODE1_1)
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Channel_selection DAC Channel selection
+ * @{
+ */
+#define DAC_CHANNEL_1 0x00000000U
+
+#define DAC_CHANNEL_2 0x00000010U
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_data_alignment DAC data alignment
+ * @{
+ */
+#define DAC_ALIGN_12B_R 0x00000000U
+#define DAC_ALIGN_12B_L 0x00000004U
+#define DAC_ALIGN_8B_R 0x00000008U
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_flags_definition DAC flags definition
+ * @{
+ */
+#define DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)
+
+#define DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)
+
+#define DAC_FLAG_DAC1RDY (DAC_SR_DAC1RDY)
+
+#define DAC_FLAG_DAC2RDY (DAC_SR_DAC2RDY)
+
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_IT_definition DAC IT definition
+ * @{
+ */
+#define DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1)
+
+#define DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2)
+
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral
+ * @{
+ */
+#define DAC_CHIPCONNECT_EXTERNAL (1UL << 0)
+#define DAC_CHIPCONNECT_INTERNAL (1UL << 1)
+#define DAC_CHIPCONNECT_BOTH (1UL << 2)
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_UserTrimming DAC User Trimming
+ * @{
+ */
+#define DAC_TRIMMING_FACTORY (0x00000000UL) /*!< Factory trimming */
+#define DAC_TRIMMING_USER (0x00000001UL) /*!< User trimming */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_SampleAndHold DAC power mode
+ * @{
+ */
+#define DAC_SAMPLEANDHOLD_DISABLE (0x00000000UL)
+#define DAC_SAMPLEANDHOLD_ENABLE (DAC_MCR_MODE1_2)
+
+/**
+ * @}
+ */
+/** @defgroup DAC_HighFrequency DAC high frequency interface mode
+ * @{
+ */
+#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE 0x00000000UL /*!< High frequency interface mode disabled */
+#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ (DAC_MCR_HFSEL_0) /*!< High frequency interface mode compatible to AHB>80MHz enabled */
+#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ (DAC_MCR_HFSEL_1) /*!< High frequency interface mode compatible to AHB>160MHz enabled */
+#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC 0x00000002UL /*!< High frequency interface mode automatic */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Macros DAC Exported Macros
+ * @{
+ */
+
+/** @brief Reset DAC handle state.
+ * @param __HANDLE__ specifies the DAC handle.
+ * @retval None
+ */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_DAC_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
+/** @brief Enable the DAC channel.
+ * @param __HANDLE__ specifies the DAC handle.
+ * @param __DAC_Channel__ specifies the DAC channel
+ * @retval None
+ */
+#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
+ ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
+
+/** @brief Disable the DAC channel.
+ * @param __HANDLE__ specifies the DAC handle
+ * @param __DAC_Channel__ specifies the DAC channel.
+ * @retval None
+ */
+#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
+ ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
+
+/** @brief Set DHR12R1 alignment.
+ * @param __ALIGNMENT__ specifies the DAC alignment
+ * @retval None
+ */
+#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__))
+
+
+/** @brief Set DHR12R2 alignment.
+ * @param __ALIGNMENT__ specifies the DAC alignment
+ * @retval None
+ */
+#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__))
+
+
+/** @brief Set DHR12RD alignment.
+ * @param __ALIGNMENT__ specifies the DAC alignment
+ * @retval None
+ */
+#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__))
+
+/** @brief Enable the DAC interrupt.
+ * @param __HANDLE__ specifies the DAC handle
+ * @param __INTERRUPT__ specifies the DAC interrupt.
+ * This parameter can be any combination of the following values:
+ * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
+ * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
+ * @retval None
+ */
+#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
+
+/** @brief Disable the DAC interrupt.
+ * @param __HANDLE__ specifies the DAC handle
+ * @param __INTERRUPT__ specifies the DAC interrupt.
+ * This parameter can be any combination of the following values:
+ * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
+ * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
+ * @retval None
+ */
+#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
+
+/** @brief Check whether the specified DAC interrupt source is enabled or not.
+ * @param __HANDLE__ DAC handle
+ * @param __INTERRUPT__ DAC interrupt source to check
+ * This parameter can be any combination of the following values:
+ * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
+ * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
+ * @retval State of interruption (SET or RESET)
+ */
+#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\
+ & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief Get the selected DAC's flag status.
+ * @param __HANDLE__ specifies the DAC handle.
+ * @param __FLAG__ specifies the DAC flag to get.
+ * This parameter can be any combination of the following values:
+ * @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
+ * @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag
+ * @arg DAC_FLAG_DAC1RDY DAC channel 1 ready status flag
+ * @arg DAC_FLAG_DAC2RDY DAC channel 2 ready status flag
+ * @retval None
+ */
+#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the DAC's flag.
+ * @param __HANDLE__ specifies the DAC handle.
+ * @param __FLAG__ specifies the DAC flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
+ * @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag
+ * @retval None
+ */
+#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+
+/** @defgroup DAC_Private_Macros DAC Private Macros
+ * @{
+ */
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
+ ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
+
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
+ ((CHANNEL) == DAC_CHANNEL_2))
+
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
+ ((ALIGN) == DAC_ALIGN_12B_L) || \
+ ((ALIGN) == DAC_ALIGN_8B_R))
+
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL)
+
+#define IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x000000FFUL)
+
+/**
+ * @}
+ */
+
+/* Include DAC HAL Extended module */
+#include "stm32u5xx_hal_dac_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup DAC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DAC_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac);
+HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac);
+void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac);
+void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac);
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Exported_Functions_Group2
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
+ uint32_t Alignment);
+HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
+void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);
+HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
+
+void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac);
+void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac);
+void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
+void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
+
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+/* DAC callback registering/unregistering */
+HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
+ pDAC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Exported_Functions_Group4
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac);
+uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Private_Functions DAC Private Functions
+ * @{
+ */
+void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
+void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
+void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* DAC1 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32U5xx_HAL_DAC_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dac_ex.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dac_ex.h
new file mode 100644
index 00000000..773529fe
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dac_ex.h
@@ -0,0 +1,282 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_dac_ex.h
+ * @author MCD Application Team
+ * @brief Header file of DAC HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_DAC_EX_H
+#define STM32U5xx_HAL_DAC_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+#if defined(DAC1)
+
+/** @addtogroup DACEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief DAC Autonomous Mode Configuration structure definition
+ */
+typedef struct
+{
+ uint32_t AutonomousModeState; /*!< Specifies the autonomous mode state.
+ This parameter can be a value of @ref DACx_Autonomous_mode */
+
+} DAC_AutonomousModeConfTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
+ * @{
+ */
+
+/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude
+ * @{
+ */
+#define DAC_LFSRUNMASK_BIT0 0x00000000UL /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TRIANGLEAMPLITUDE_1 0x00000000UL /*!< Select max triangle amplitude of 1 */
+#define DAC_TRIANGLEAMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
+#define DAC_TRIANGLEAMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 7 */
+#define DAC_TRIANGLEAMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
+#define DAC_TRIANGLEAMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Select max triangle amplitude of 31 */
+#define DAC_TRIANGLEAMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
+#define DAC_TRIANGLEAMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 127 */
+#define DAC_TRIANGLEAMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
+#define DAC_TRIANGLEAMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Select max triangle amplitude of 511 */
+#define DAC_TRIANGLEAMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TRIANGLEAMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TRIANGLEAMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
+
+/**
+ * @}
+ */
+
+/** @defgroup DACx_Autonomous_mode DACx Autonomous Mode
+ * @brief DAC Autonomous mode
+ * @{
+ */
+#define DAC_AUTONOMOUS_MODE_DISABLE 0x00000000U /*!< Autonomous mode disable */
+#define DAC_AUTONOMOUS_MODE_ENABLE DAC_AUTOCR_AUTOMODE /*!< Autonomous mode enable */
+/**
+ * @}
+ */
+
+/** @defgroup DACx_Trigger_Stop_mode DACx Trigger Stop Mode
+ * @brief DAC Trigger stop mode
+ * @{
+ */
+#define DAC_TRIGGER_STOP_LPTIM1_CH1 DAC_TRIGGER_LPTIM1_CH1 /*!< LPTIM1 output selected as DAC trigger in stop mode */
+#define DAC_TRIGGER_STOP_LPTIM3_CH1 DAC_TRIGGER_LPTIM3_CH1 /*!< LPTIM3 output selected as DAC trigger in stop mode */
+#define DAC_TRIGGER_STOP_EXT_IT9 DAC_TRIGGER_EXT_IT9 /*!< EXTI line 9 selected as DAC trigger in stop mode */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+
+/* Private macro -------------------------------------------------------------*/
+
+/** @defgroup DACEx_Private_Macros DACEx Private Macros
+ * @{
+ */
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
+ ((TRIGGER) == DAC_TRIGGER_T1_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_LPTIM1_CH1) || \
+ ((TRIGGER) == DAC_TRIGGER_LPTIM3_CH1) || \
+ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+ ((TRIGGER) == DAC_TRIGGER_STOP_LPTIM1_CH1) || \
+ ((TRIGGER) == DAC_TRIGGER_STOP_LPTIM3_CH1) || \
+ ((TRIGGER) == DAC_TRIGGER_STOP_EXT_IT9) || \
+ ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+
+#define IS_DAC_HIGH_FREQUENCY_MODE(MODE) (((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE) || \
+ ((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ) || \
+ ((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ) || \
+ ((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC))
+
+#define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x000003FFU)
+
+#define IS_DAC_HOLDTIME(TIME) ((TIME) <= 0x000003FFU)
+
+#define IS_DAC_SAMPLEANDHOLD(MODE) (((MODE) == DAC_SAMPLEANDHOLD_DISABLE) || \
+ ((MODE) == DAC_SAMPLEANDHOLD_ENABLE))
+
+#define IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
+
+#define IS_DAC_NEWTRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
+
+#define IS_DAC_CHIP_CONNECTION(CONNECT) (((CONNECT) == DAC_CHIPCONNECT_EXTERNAL) || \
+ ((CONNECT) == DAC_CHIPCONNECT_INTERNAL) || \
+ ((CONNECT) == DAC_CHIPCONNECT_BOTH))
+
+#define IS_DAC_TRIMMING(TRIMMING) (((TRIMMING) == DAC_TRIMMING_FACTORY) || \
+ ((TRIMMING) == DAC_TRIMMING_USER))
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
+
+#define IS_DAC_AUTONOMOUS(AUTONOMOUS) (((AUTONOMOUS) == DAC_AUTONOMOUS_MODE_DISABLE) || \
+ ((AUTONOMOUS) == DAC_AUTONOMOUS_MODE_ENABLE))
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/* Extended features functions ***********************************************/
+
+/** @addtogroup DACEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DACEx_Exported_Functions_Group2
+ * @{
+ */
+/* IO operation functions *****************************************************/
+
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
+
+HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac);
+HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac);
+HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
+ uint32_t Alignment);
+HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac);
+
+void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac);
+void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac);
+void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac);
+void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup DACEx_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+
+HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel,
+ uint32_t NewTrimmingValue);
+uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel);
+
+/* Autonomous Mode Control functions **********************************************/
+HAL_StatusTypeDef HAL_DACEx_SetConfigAutonomousMode(DAC_HandleTypeDef *hdac, DAC_AutonomousModeConfTypeDef *sConfig);
+HAL_StatusTypeDef HAL_DACEx_GetConfigAutonomousMode(DAC_HandleTypeDef *hdac, DAC_AutonomousModeConfTypeDef *sConfig);
+HAL_StatusTypeDef HAL_DACEx_ClearConfigAutonomousMode(DAC_HandleTypeDef *hdac);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DACEx_Private_Functions
+ * @{
+ */
+
+/* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */
+/* are called by HAL_DAC_Start_DMA */
+void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
+void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
+void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* DAC1 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_DAC_EX_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dcache.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dcache.h
new file mode 100644
index 00000000..8450ec18
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dcache.h
@@ -0,0 +1,325 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_dcache.h
+ * @author MCD Application Team
+ * @brief Header file of DCACHE HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion ------------------------------------*/
+#ifndef STM32U5xx_HAL_DCACHE_H
+#define STM32U5xx_HAL_DCACHE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes -----------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DCACHE
+ * @{
+ */
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup DCACHE_Exported_Types DCACHE Exported Types
+ * @{
+ */
+
+/**
+ * @brief DCACHE Init structure definition
+ */
+typedef struct
+{
+ uint32_t ReadBurstType; /*!< Burst type to be applied for Data Cache */
+} DCACHE_InitTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_DCACHE_STATE_RESET = 0x00U, /* !< DCACHE not yet initialized or disabled */
+ HAL_DCACHE_STATE_READY = 0x01U, /* !< Peripheral initialized and ready for use */
+ HAL_DCACHE_STATE_BUSY = 0x02U, /* !< An internal process is ongoing */
+ HAL_DCACHE_STATE_TIMEOUT = 0x05U, /* !< Timeout state */
+ HAL_DCACHE_STATE_ERROR = 0x06U, /* !< DCACHE state error */
+
+} HAL_DCACHE_StateTypeDef;
+
+/** @defgroup DCACHE_Configuration_Structure_definition DCACHE Configuration Structure definition
+ * @brief DCACHE Configuration Structure definition
+ * @{
+ */
+typedef struct __DCACHE_HandleTypeDef
+{
+ DCACHE_TypeDef *Instance; /*!< DCACHE register base address. */
+ DCACHE_InitTypeDef Init; /*!< DCACHE Initialization Structure. */
+
+ void (* ErrorCallback)(struct __DCACHE_HandleTypeDef *hdcache);
+ void (* CleanByAddrCallback)(struct __DCACHE_HandleTypeDef *hdcache);
+ void (* InvalidateByAddrCallback)(struct __DCACHE_HandleTypeDef *hdcache);
+ void (* InvalidateCompleteCallback)(struct __DCACHE_HandleTypeDef *hdcache);
+ void (* CleanAndInvalidateByAddrCallback)(struct __DCACHE_HandleTypeDef *hdcache);
+
+ void (* MspInitCallback)(struct __DCACHE_HandleTypeDef *hdcache);
+ void (* MspDeInitCallback)(struct __DCACHE_HandleTypeDef *hdcache);
+
+ __IO HAL_DCACHE_StateTypeDef State;
+ __IO uint32_t ErrorCode;
+
+} DCACHE_HandleTypeDef;
+
+/**
+ * @brief HAL DCACHE Callback pointer definition
+ */
+/*!< Pointer to a DCACHE common callback function */
+typedef void (*pDCACHE_CallbackTypeDef)(DCACHE_HandleTypeDef *hdcache);
+
+/**
+ * @brief HAL DCACHE Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_DCACHE_CLEAN_BY_ADDRESS_CB_ID = 0x00U, /*!< DCACHE Clean By Address callback ID */
+ HAL_DCACHE_INVALIDATE_BY_ADDRESS_CB_ID = 0x01U, /*!< DCACHE Invalidate By Address callback ID */
+ HAL_DCACHE_CLEAN_AND_INVALIDATE_BY_ADDRESS_CB_ID = 0x02U, /*!< DCACHE Clean And Invalidate By Address callback ID */
+ HAL_DCACHE_INVALIDATE_COMPLETE_CB_ID = 0x03U, /*!< DCACHE Invalidate Complete ID */
+ HAL_DCACHE_ERROR_CB_ID = 0x04U, /*!< DCACHE Error callback ID */
+
+ HAL_DCACHE_MSPINIT_CB_ID = 0x05U, /*!< DCACHE Msp Init callback ID */
+ HAL_DCACHE_MSPDEINIT_CB_ID = 0x06U /*!< DCACHE Msp DeInit callback ID */
+
+} HAL_DCACHE_CallbackIDTypeDef;
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported constants -------------------------------------------------------*/
+/** @defgroup DCACHE_Exported_Constants DCACHE Exported Constants
+ * @{
+ */
+
+/** @defgroup DCACHE_Error_Code DCACHE Error Code
+ * @{
+ */
+#define HAL_DCACHE_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_DCACHE_ERROR_TIMEOUT 0x00000010U /*!< Timeout error */
+#define HAL_DCACHE_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid callback error */
+/**
+ * @}
+ */
+
+/** @defgroup DCACHE_Monitor_Type Monitor type
+ * @{
+ */
+#define DCACHE_MONITOR_READ_HIT DCACHE_CR_RHITMEN /*!< Read Hit monitoring */
+#define DCACHE_MONITOR_READ_MISS DCACHE_CR_RMISSMEN /*!< Read Miss monitoring */
+#define DCACHE_MONITOR_WRITE_HIT DCACHE_CR_WHITMEN /*!< Write Hit monitoring */
+#define DCACHE_MONITOR_WRITE_MISS DCACHE_CR_WMISSMEN /*!< Write Miss monitoring */
+#define DCACHE_MONITOR_ALL (DCACHE_CR_RHITMEN | DCACHE_CR_RMISSMEN | \
+ DCACHE_CR_WHITMEN | DCACHE_CR_WMISSMEN)
+/**
+ * @}
+ */
+
+/** @defgroup DCACHE_Read_Burst_Type Remapped Output burst type
+ * @{
+ */
+#define DCACHE_READ_BURST_WRAP 0U /*!< WRAP */
+#define DCACHE_READ_BURST_INCR DCACHE_CR_HBURST /*!< INCR */
+/**
+ * @}
+ */
+
+/** @defgroup DCACHE_Interrupts Interrupts
+ * @{
+ */
+#define DCACHE_IT_BUSYEND DCACHE_IER_BSYENDIE /*!< Busy end interrupt */
+#define DCACHE_IT_ERROR DCACHE_IER_ERRIE /*!< Cache error interrupt */
+#define DCACHE_IT_CMDEND DCACHE_IER_CMDENDIE /*!< Command end interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup DCACHE_Flags Flags
+ * @{
+ */
+#define DCACHE_FLAG_BUSY DCACHE_SR_BUSYF /*!< Busy flag */
+#define DCACHE_FLAG_BUSYEND DCACHE_SR_BSYENDF /*!< Busy end flag */
+#define DCACHE_FLAG_ERROR DCACHE_SR_ERRF /*!< Cache error flag */
+#define DCACHE_FLAG_BUSYCMD DCACHE_SR_BUSYCMDF /*!< Busy command flag */
+#define DCACHE_FLAG_CMDEND DCACHE_SR_CMDENDF /*!< Command end flag */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros ----------------------------------------------------------*/
+/** @defgroup DCACHE_Exported_Macros DCACHE Exported Macros
+ * @{
+ */
+
+/** @brief Enable DCACHE interrupts.
+ * @param __HANDLE__ specifies the DCACHE handle.
+ * @param __INTERRUPT__ specifies the DCACHE interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg @ref DCACHE_IT_BUSYEND Busy end interrupt
+ * @arg @ref DCACHE_IT_ERROR Cache error interrupt
+ * @arg @ref DCACHE_IT_CMDEND Cache Command end interrupt
+ * @retval None
+ */
+#define __HAL_DCACHE_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))
+
+/** @brief Disable DCACHE interrupts.
+ * @param __HANDLE__ specifies the DCACHE handle.
+ * @param __INTERRUPT__ specifies the DCACHE interrupt sources to be disabled.
+ * This parameter can be any combination of the following values:
+ * @arg @ref DCACHE_IT_BUSYEND Busy end interrupt
+ * @arg @ref DCACHE_IT_ERROR Cache error interrupt
+ * @arg @ref DCACHE_IT_CMDEND Cache Command end interrupt
+ * @retval None
+ */
+#define __HAL_DCACHE_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))
+
+/** @brief Check whether the specified DCACHE interrupt source is enabled or not.
+ * @param __HANDLE__ specifies the DCACHE handle.
+ * @param __INTERRUPT__ specifies the DCACHE interrupt source to check.
+ * This parameter can be any combination of the following values:
+ * @arg @ref DCACHE_IT_BUSYEND Busy end interrupt
+ * @arg @ref DCACHE_IT_ERROR Cache error interrupt
+ * @arg @ref DCACHE_IT_CMDEND Cache Command end interrupt
+ *
+ * @retval The state of __INTERRUPT__ (SET or RESET).
+ */
+#define __HAL_DCACHE_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+ ((READ_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Check whether the selected DCACHE flag is set or not.
+ * @param __HANDLE__ specifies the DCACHE handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref DCACHE_FLAG_BUSY Busy flag
+ * @arg @ref DCACHE_FLAG_BUSYEND Busy end flag
+ * @arg @ref DCACHE_FLAG_ERROR Cache error flag
+ * @arg @ref DCACHE_FLAG_BUSYCMD Cache Busy command flag
+ * @arg @ref DCACHE_FLAG_CMDEND Cache command end flag
+ * @retval The state of __FLAG__ (0 or 1).
+ */
+#define __HAL_DCACHE_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? 1U : 0U)
+
+/** @brief Clear the selected DCACHE flags.
+ * @param __HANDLE__ specifies the DCACHE handle.
+ * @param __FLAG__ specifies the DCACHE flags to clear.
+ * This parameter can be any combination of the following values:
+ * @arg @ref DCACHE_FLAG_BUSYEND Busy end flag
+ * @arg @ref DCACHE_FLAG_ERROR Cache error flag
+ * @arg @ref DCACHE_FLAG_CMDEND Cache command end flag
+ */
+#define __HAL_DCACHE_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
+
+/**
+ * @}
+ */
+
+/* Exported functions -------------------------------------------------------*/
+/** @defgroup DCACHE_Exported_Functions DCACHE Exported Functions
+ * @{
+ */
+/* Initialization and de-initialization functions ***/
+HAL_StatusTypeDef HAL_DCACHE_Init(DCACHE_HandleTypeDef *hdcache);
+HAL_StatusTypeDef HAL_DCACHE_DeInit(DCACHE_HandleTypeDef *hdcache);
+void HAL_DCACHE_MspInit(DCACHE_HandleTypeDef *hdcache);
+void HAL_DCACHE_MspDeInit(DCACHE_HandleTypeDef *hdcache);
+
+/* Peripheral Control functions ***/
+HAL_StatusTypeDef HAL_DCACHE_Enable(DCACHE_HandleTypeDef *hdcache);
+HAL_StatusTypeDef HAL_DCACHE_Disable(DCACHE_HandleTypeDef *hdcache);
+HAL_StatusTypeDef HAL_DCACHE_SetReadBurstType(DCACHE_HandleTypeDef *hdcache, uint32_t ReadBrustType);
+
+/*** Cache maintenance in blocking mode (Polling) ***/
+HAL_StatusTypeDef HAL_DCACHE_Invalidate(DCACHE_HandleTypeDef *hdcache);
+HAL_StatusTypeDef HAL_DCACHE_InvalidateByAddr(DCACHE_HandleTypeDef *hdcache, const uint32_t *const pAddr,
+ uint32_t dSize);
+HAL_StatusTypeDef HAL_DCACHE_CleanByAddr(DCACHE_HandleTypeDef *hdcache, const uint32_t *const pAddr, uint32_t dSize);
+HAL_StatusTypeDef HAL_DCACHE_CleanInvalidByAddr(DCACHE_HandleTypeDef *hdcache, const uint32_t *const pAddr,
+ uint32_t dSize);
+
+/*** Cache maintenance in non-blocking mode (Interrupt) ***/
+HAL_StatusTypeDef HAL_DCACHE_Invalidate_IT(DCACHE_HandleTypeDef *hdcache);
+HAL_StatusTypeDef HAL_DCACHE_InvalidateByAddr_IT(DCACHE_HandleTypeDef *hdcache, const uint32_t *const pAddr,
+ uint32_t dSize);
+HAL_StatusTypeDef HAL_DCACHE_CleanByAddr_IT(DCACHE_HandleTypeDef *hdcache, const uint32_t *const pAddr,
+ uint32_t dSize);
+HAL_StatusTypeDef HAL_DCACHE_CleanInvalidByAddr_IT(DCACHE_HandleTypeDef *hdcache, const uint32_t *const pAddr,
+ uint32_t dSize);
+
+/*** IRQHandler and Callbacks ***/
+void HAL_DCACHE_IRQHandler(DCACHE_HandleTypeDef *hdcache);
+void HAL_DCACHE_ErrorCallback(DCACHE_HandleTypeDef *hdcache);
+void HAL_DCACHE_CleanByAddrCallback(DCACHE_HandleTypeDef *hdcache);
+void HAL_DCACHE_InvalidateByAddrCallback(DCACHE_HandleTypeDef *hdcache);
+void HAL_DCACHE_InvalidateCompleteCallback(DCACHE_HandleTypeDef *hdcache);
+void HAL_DCACHE_CleanAndInvalidateByAddrCallback(DCACHE_HandleTypeDef *hdcache);
+
+/* Callbacks Register/UnRegister functions ***/
+HAL_StatusTypeDef HAL_DCACHE_RegisterCallback(DCACHE_HandleTypeDef *hdcache, HAL_DCACHE_CallbackIDTypeDef CallbackID,
+ pDCACHE_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_DCACHE_UnRegisterCallback(DCACHE_HandleTypeDef *hdcache, HAL_DCACHE_CallbackIDTypeDef CallbackID);
+
+/*** Performance instruction cache monitoring functions ***/
+uint32_t HAL_DCACHE_Monitor_GetReadHitValue(DCACHE_HandleTypeDef *hdcache);
+uint32_t HAL_DCACHE_Monitor_GetReadMissValue(DCACHE_HandleTypeDef *hdcache);
+uint32_t HAL_DCACHE_Monitor_GetWriteHitValue(DCACHE_HandleTypeDef *hdcache);
+uint32_t HAL_DCACHE_Monitor_GetWriteMissValue(DCACHE_HandleTypeDef *hdcache);
+HAL_StatusTypeDef HAL_DCACHE_Monitor_Reset(DCACHE_HandleTypeDef *hdcache, uint32_t MonitorType);
+HAL_StatusTypeDef HAL_DCACHE_Monitor_Start(DCACHE_HandleTypeDef *hdcache, uint32_t MonitorType);
+HAL_StatusTypeDef HAL_DCACHE_Monitor_Stop(DCACHE_HandleTypeDef *hdcache, uint32_t MonitorType);
+
+/* Peripheral State functions ***************************************************/
+HAL_DCACHE_StateTypeDef HAL_DCACHE_GetState(DCACHE_HandleTypeDef *hdcache);
+uint32_t HAL_DCACHE_GetError(DCACHE_HandleTypeDef *hdcache);
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_DCACHE_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dcmi.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dcmi.h
new file mode 100644
index 00000000..d0bf18c8
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dcmi.h
@@ -0,0 +1,699 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_dcmi.h
+ * @author MCD Application Team
+ * @brief Header file of DCMI HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_DCMI_H
+#define STM32U5xx_HAL_DCMI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+#if defined (DCMI)
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DCMI DCMI
+ * @brief DCMI HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DCMI_Exported_Types DCMI Exported Types
+ * @{
+ */
+/**
+ * @brief HAL DCMI State structures definition
+ */
+typedef enum
+{
+ HAL_DCMI_STATE_RESET = 0x00U, /*!< DCMI not yet initialized or disabled */
+ HAL_DCMI_STATE_READY = 0x01U, /*!< DCMI initialized and ready for use */
+ HAL_DCMI_STATE_BUSY = 0x02U, /*!< DCMI internal processing is ongoing */
+ HAL_DCMI_STATE_TIMEOUT = 0x03U, /*!< DCMI timeout state */
+ HAL_DCMI_STATE_ERROR = 0x04U, /*!< DCMI error state */
+ HAL_DCMI_STATE_SUSPENDED = 0x05U /*!< DCMI suspend state */
+} HAL_DCMI_StateTypeDef;
+
+/**
+ * @brief DCMI Embedded Synchronisation CODE Init structure definition
+ */
+typedef struct
+{
+ uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */
+ uint8_t LineStartCode; /*!< Specifies the code of the line start delimiter. */
+ uint8_t LineEndCode; /*!< Specifies the code of the line end delimiter. */
+ uint8_t FrameEndCode; /*!< Specifies the code of the frame end delimiter. */
+} DCMI_CodesInitTypeDef;
+
+/**
+ * @brief DCMI Embedded Synchronisation UNMASK Init structure definition
+ */
+typedef struct
+{
+ uint8_t FrameStartUnmask; /*!< Specifies the frame start delimiter unmask. */
+ uint8_t LineStartUnmask; /*!< Specifies the line start delimiter unmask. */
+ uint8_t LineEndUnmask; /*!< Specifies the line end delimiter unmask. */
+ uint8_t FrameEndUnmask; /*!< Specifies the frame end delimiter unmask. */
+} DCMI_SyncUnmaskTypeDef;
+/**
+ * @brief DCMI Init structure definition
+ */
+typedef struct
+{
+ uint32_t SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded.
+ This parameter can be a value of @ref DCMI_Synchronization_Mode */
+
+ uint32_t PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising.
+ This parameter can be a value of @ref DCMI_PIXCK_Polarity */
+
+ uint32_t VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low.
+ This parameter can be a value of @ref DCMI_VSYNC_Polarity */
+
+ uint32_t HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low.
+ This parameter can be a value of @ref DCMI_HSYNC_Polarity */
+
+ uint32_t CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.
+ This parameter can be a value of @ref DCMI_Capture_Rate */
+
+ uint32_t ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
+ This parameter can be a value of @ref DCMI_Extended_Data_Mode */
+
+ DCMI_CodesInitTypeDef SyncroCode; /*!< Specifies the code of the line/frame start delimiter and the
+ line/frame end delimiter */
+
+ uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode.
+ This parameter can be a value of @ref DCMI_MODE_JPEG */
+
+ uint32_t ByteSelectMode; /*!< Specifies the data to be captured by the interface
+ This parameter can be a value of @ref DCMI_Byte_Select_Mode */
+
+ uint32_t ByteSelectStart; /*!< Specifies if the data to be captured by the interface is even or odd
+ This parameter can be a value of @ref DCMI_Byte_Select_Start */
+
+ uint32_t LineSelectMode; /*!< Specifies the line of data to be captured by the interface
+ This parameter can be a value of @ref DCMI_Line_Select_Mode */
+
+ uint32_t LineSelectStart; /*!< Specifies if the line of data to be captured by the interface is even or odd
+ This parameter can be a value of @ref DCMI_Line_Select_Start */
+} DCMI_InitTypeDef;
+
+/**
+ * @brief DCMI handle Structure definition
+ */
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+typedef struct __DCMI_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
+{
+ DCMI_TypeDef *Instance; /*!< DCMI Register base address */
+
+ DCMI_InitTypeDef Init; /*!< DCMI parameters */
+
+ HAL_LockTypeDef Lock; /*!< DCMI locking object */
+
+ __IO HAL_DCMI_StateTypeDef State; /*!< DCMI state */
+
+ __IO uint32_t XferCount; /*!< DMA transfer counter */
+
+ __IO uint32_t XferSize; /*!< DMA transfer size */
+
+ uint32_t XferTransferNumber; /*!< DMA transfer number */
+
+ uint32_t pBuffPtr; /*!< Pointer to DMA output buffer */
+
+ DMA_HandleTypeDef *DMA_Handle; /*!< Pointer to the DMA handler */
+
+ __IO uint32_t ErrorCode; /*!< DCMI Error code */
+
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+ void (* FrameEventCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Frame Event Callback */
+ void (* VsyncEventCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Vsync Event Callback */
+ void (* LineEventCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Line Event Callback */
+ void (* ErrorCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Error Callback */
+ void (* MspInitCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Msp Init callback */
+ void (* MspDeInitCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Msp DeInit callback */
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
+} DCMI_HandleTypeDef;
+
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL DCMI Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_DCMI_FRAME_EVENT_CB_ID = 0x00U, /*!< DCMI Frame Event Callback ID */
+ HAL_DCMI_VSYNC_EVENT_CB_ID = 0x01U, /*!< DCMI Vsync Event Callback ID */
+ HAL_DCMI_LINE_EVENT_CB_ID = 0x02U, /*!< DCMI Line Event Callback ID */
+ HAL_DCMI_ERROR_CB_ID = 0x03U, /*!< DCMI Error Callback ID */
+ HAL_DCMI_MSPINIT_CB_ID = 0x04U, /*!< DCMI MspInit callback ID */
+ HAL_DCMI_MSPDEINIT_CB_ID = 0x05U /*!< DCMI MspDeInit callback ID */
+
+} HAL_DCMI_CallbackIDTypeDef;
+
+/**
+ * @brief HAL DCMI Callback pointer definition
+ */
+typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi); /*!< pointer to a DCMI callback function */
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
+
+
+/**
+ * @}
+ */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DCMI_Exported_Constants DCMI Exported Constants
+ * @{
+ */
+
+/** @defgroup DCMI_Error_Code DCMI Error Code
+ * @{
+ */
+#define HAL_DCMI_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_DCMI_ERROR_OVR (0x00000001U) /*!< Overrun error */
+#define HAL_DCMI_ERROR_SYNC (0x00000002U) /*!< Synchronization error */
+#define HAL_DCMI_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
+#define HAL_DCMI_ERROR_DMA (0x00000040U) /*!< DMA error */
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+#define HAL_DCMI_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid callback error */
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_Capture_Mode DCMI Capture Mode
+ * @{
+ */
+#define DCMI_MODE_CONTINUOUS (0x00000000U) /*!< The received data are transferred continuously
+ into the destination memory through the DMA */
+#define DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM) /*!< Once activated, the interface waits for the start of
+ frame and then transfers a single frame
+ through the DMA */
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_Synchronization_Mode DCMI Synchronization Mode
+ * @{
+ */
+#define DCMI_SYNCHRO_HARDWARE (0x00000000U) /*!< Hardware synchronization data capture (frame/line start/stop)
+ is synchronized with the HSYNC/VSYNC signals */
+#define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS) /*!< Embedded synchronization data capture is synchronized
+ with synchronization codes embedded in the data flow */
+
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_PIXCK_Polarity DCMI PIXCK Polarity
+ * @{
+ */
+#define DCMI_PCKPOLARITY_FALLING (0x00000000U) /*!< Pixel clock active on Falling edge */
+#define DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL) /*!< Pixel clock active on Rising edge */
+
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_VSYNC_Polarity DCMI VSYNC Polarity
+ * @{
+ */
+#define DCMI_VSPOLARITY_LOW (0x00000000U) /*!< Vertical synchronization active Low */
+#define DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL) /*!< Vertical synchronization active High */
+
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_HSYNC_Polarity DCMI HSYNC Polarity
+ * @{
+ */
+#define DCMI_HSPOLARITY_LOW (0x00000000U) /*!< Horizontal synchronization active Low */
+#define DCMI_HSPOLARITY_HIGH ((uint32_t)DCMI_CR_HSPOL) /*!< Horizontal synchronization active High */
+
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_MODE_JPEG DCMI MODE JPEG
+ * @{
+ */
+#define DCMI_JPEG_DISABLE (0x00000000U) /*!< Mode JPEG Disabled */
+#define DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG) /*!< Mode JPEG Enabled */
+
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_Capture_Rate DCMI Capture Rate
+ * @{
+ */
+#define DCMI_CR_ALL_FRAME (0x00000000U) /*!< All frames are captured */
+#define DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0) /*!< Every alternate frame captured */
+#define DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1) /*!< One frame in 4 frames captured */
+
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_Extended_Data_Mode DCMI Extended Data Mode
+ * @{
+ */
+#define DCMI_EXTEND_DATA_8B (0x00000000U) /*!< Interface captures 8-bit data on every pixel clock */
+#define DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0) /*!< Interface captures 10-bit data on every pixel clock */
+#define DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1) /*!< Interface captures 12-bit data on every pixel clock */
+#define DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 |\
+ DCMI_CR_EDM_1)) /*!< Interface captures 14-bit data on every pixel clock */
+
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_Window_Coordinate DCMI Window Coordinate
+ * @{
+ */
+#define DCMI_WINDOW_COORDINATE (0x3FFFU) /*!< Window coordinate */
+
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_Window_Height DCMI Window Height
+ * @{
+ */
+#define DCMI_WINDOW_HEIGHT (0x1FFFU) /*!< Window Height */
+
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_interrupt_sources DCMI interrupt sources
+ * @{
+ */
+#define DCMI_IT_FRAME ((uint32_t)DCMI_IER_FRAME_IE) /*!< Capture complete interrupt */
+#define DCMI_IT_OVR ((uint32_t)DCMI_IER_OVR_IE) /*!< Overrun interrupt */
+#define DCMI_IT_ERR ((uint32_t)DCMI_IER_ERR_IE) /*!< Synchronization error interrupt */
+#define DCMI_IT_VSYNC ((uint32_t)DCMI_IER_VSYNC_IE) /*!< VSYNC interrupt */
+#define DCMI_IT_LINE ((uint32_t)DCMI_IER_LINE_IE) /*!< Line interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_Flags DCMI Flags
+ * @{
+ */
+
+/**
+ * @brief DCMI SR register
+ */
+#define DCMI_FLAG_HSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC) /*!< HSYNC pin state (active line / synchronization
+ between lines) */
+#define DCMI_FLAG_VSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC) /*!< VSYNC pin state (active frame / synchronization
+ between frames) */
+#define DCMI_FLAG_FNE ((uint32_t)DCMI_SR_INDEX|DCMI_SR_FNE) /*!< FIFO not empty flag */
+/**
+ * @brief DCMI RIS register
+ */
+#define DCMI_FLAG_FRAMERI ((uint32_t)DCMI_RIS_FRAME_RIS) /*!< Frame capture complete interrupt flag */
+#define DCMI_FLAG_OVRRI ((uint32_t)DCMI_RIS_OVR_RIS) /*!< Overrun interrupt flag */
+#define DCMI_FLAG_ERRRI ((uint32_t)DCMI_RIS_ERR_RIS) /*!< Synchronization error interrupt flag */
+#define DCMI_FLAG_VSYNCRI ((uint32_t)DCMI_RIS_VSYNC_RIS) /*!< VSYNC interrupt flag */
+#define DCMI_FLAG_LINERI ((uint32_t)DCMI_RIS_LINE_RIS) /*!< Line interrupt flag */
+/**
+ * @brief DCMI MIS register
+ */
+#define DCMI_FLAG_FRAMEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS) /*!< DCMI Frame capture complete masked
+ interrupt status */
+#define DCMI_FLAG_OVRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS ) /*!< DCMI Overrun masked interrupt status */
+#define DCMI_FLAG_ERRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS ) /*!< DCMI Synchronization error masked interrupt status */
+#define DCMI_FLAG_VSYNCMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS) /*!< DCMI VSYNC masked interrupt status */
+#define DCMI_FLAG_LINEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_LINE_MIS ) /*!< DCMI Line masked interrupt status */
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_Byte_Select_Mode DCMI Byte Select Mode
+ * @{
+ */
+#define DCMI_BSM_ALL (0x00000000U) /*!< Interface captures all received data */
+#define DCMI_BSM_OTHER ((uint32_t)DCMI_CR_BSM_0) /*!< Interface captures every other byte
+ from the received data */
+#define DCMI_BSM_ALTERNATE_4 ((uint32_t)DCMI_CR_BSM_1) /*!< Interface captures one byte out of four */
+#define DCMI_BSM_ALTERNATE_2 ((uint32_t)(DCMI_CR_BSM_0 |\
+ DCMI_CR_BSM_1)) /*!< Interface captures two bytes out of four */
+
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_Byte_Select_Start DCMI Byte Select Start
+ * @{
+ */
+#define DCMI_OEBS_ODD (0x00000000U) /*!< Interface captures first data from the frame/line start,
+ second one being dropped */
+#define DCMI_OEBS_EVEN ((uint32_t)DCMI_CR_OEBS) /*!< Interface captures second data from
+ the frame/line start, first one being dropped */
+
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_Line_Select_Mode DCMI Line Select Mode
+ * @{
+ */
+#define DCMI_LSM_ALL (0x00000000U) /*!< Interface captures all received lines */
+#define DCMI_LSM_ALTERNATE_2 ((uint32_t)DCMI_CR_LSM) /*!< Interface captures one line out of two */
+
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_Line_Select_Start DCMI Line Select Start
+ * @{
+ */
+#define DCMI_OELS_ODD (0x00000000U) /*!< Interface captures first line from the frame start,
+ second one being dropped */
+#define DCMI_OELS_EVEN ((uint32_t)DCMI_CR_OELS) /*!< Interface captures second line from the frame start,
+ first one being dropped */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DCMI_Exported_Macros DCMI Exported Macros
+ * @{
+ */
+
+/** @brief Reset DCMI handle state
+ * @param __HANDLE__ specifies the DCMI handle.
+ * @retval None
+ */
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_DCMI_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET)
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
+
+/**
+ * @brief Enable the DCMI.
+ * @param __HANDLE__ DCMI handle
+ * @retval None
+ */
+#define __HAL_DCMI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE)
+
+/**
+ * @brief Disable the DCMI.
+ * @param __HANDLE__ DCMI handle
+ * @retval None
+ */
+#define __HAL_DCMI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE))
+
+/* Interrupt & Flag management */
+/**
+ * @brief Get the DCMI pending flag.
+ * @param __HANDLE__ DCMI handle
+ * @param __FLAG__ Get the specified flag.
+ * This parameter can be one of the following values (no combination allowed)
+ * @arg DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines)
+ * @arg DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames)
+ * @arg DCMI_FLAG_FNE: FIFO empty flag
+ * @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
+ * @arg DCMI_FLAG_OVRRI: Overrun flag mask
+ * @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
+ * @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
+ * @arg DCMI_FLAG_LINERI: Line flag mask
+ * @arg DCMI_FLAG_FRAMEMI: DCMI Capture complete masked interrupt status
+ * @arg DCMI_FLAG_OVRMI: DCMI Overrun masked interrupt status
+ * @arg DCMI_FLAG_ERRMI: DCMI Synchronization error masked interrupt status
+ * @arg DCMI_FLAG_VSYNCMI: DCMI VSYNC masked interrupt status
+ * @arg DCMI_FLAG_LINEMI: DCMI Line masked interrupt status
+ * @retval The state of FLAG.
+ */
+#define __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)\
+ ((((__FLAG__) & (DCMI_SR_INDEX|DCMI_MIS_INDEX)) == 0x0)? ((__HANDLE__)->Instance->RIS & (__FLAG__)) :\
+ (((__FLAG__) & DCMI_SR_INDEX) == 0x0)? ((__HANDLE__)->Instance->MIS & (__FLAG__)) :\
+ ((__HANDLE__)->Instance->SR & (__FLAG__)))
+
+/**
+ * @brief Clear the DCMI pending flags.
+ * @param __HANDLE__ DCMI handle
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
+ * @arg DCMI_FLAG_OVFRI: Overflow flag mask
+ * @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
+ * @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
+ * @arg DCMI_FLAG_LINERI: Line flag mask
+ * @retval None
+ */
+#define __HAL_DCMI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/**
+ * @brief Enable the specified DCMI interrupts.
+ * @param __HANDLE__ DCMI handle
+ * @param __INTERRUPT__ specifies the DCMI interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
+ * @arg DCMI_IT_OVF: Overflow interrupt mask
+ * @arg DCMI_IT_ERR: Synchronization error interrupt mask
+ * @arg DCMI_IT_VSYNC: VSYNC interrupt mask
+ * @arg DCMI_IT_LINE: Line interrupt mask
+ * @retval None
+ */
+#define __HAL_DCMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the specified DCMI interrupts.
+ * @param __HANDLE__ DCMI handle
+ * @param __INTERRUPT__ specifies the DCMI interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
+ * @arg DCMI_IT_OVF: Overflow interrupt mask
+ * @arg DCMI_IT_ERR: Synchronization error interrupt mask
+ * @arg DCMI_IT_VSYNC: VSYNC interrupt mask
+ * @arg DCMI_IT_LINE: Line interrupt mask
+ * @retval None
+ */
+#define __HAL_DCMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified DCMI interrupt has occurred or not.
+ * @param __HANDLE__ DCMI handle
+ * @param __INTERRUPT__ specifies the DCMI interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
+ * @arg DCMI_IT_OVF: Overflow interrupt mask
+ * @arg DCMI_IT_ERR: Synchronization error interrupt mask
+ * @arg DCMI_IT_VSYNC: VSYNC interrupt mask
+ * @arg DCMI_IT_LINE: Line interrupt mask
+ * @retval The state of INTERRUPT.
+ */
+#define __HAL_DCMI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MISR & (__INTERRUPT__))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DCMI_Exported_Functions DCMI Exported Functions
+ * @{
+ */
+
+/** @addtogroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi);
+void HAL_DCMI_MspInit(DCMI_HandleTypeDef *hdcmi);
+void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef *hdcmi);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID,
+ pDCMI_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @addtogroup DCMI_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef *hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length);
+HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef *hdcmi);
+void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi);
+void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi);
+void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi);
+void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi);
+void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);
+/**
+ * @}
+ */
+
+/** @addtogroup DCMI_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize,
+ uint32_t YSize);
+HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask);
+
+/**
+ * @}
+ */
+
+/** @addtogroup DCMI_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
+/* Peripheral State functions *************************************************/
+HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi);
+uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DCMI_Private_Constants DCMI Private Constants
+ * @{
+ */
+/** @defgroup DCMI_MIS_INDEX DCMI Mis Index
+ * @{
+ */
+#define DCMI_MIS_INDEX ((uint32_t)0x1000) /*!< DCMI MIS register index */
+
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_SR_INDEX DCMI SR Index
+ * @{
+ */
+#define DCMI_SR_INDEX ((uint32_t)0x2000) /*!< DCMI SR register index */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup DCMI_Private_Macros DCMI Private Macros
+ * @{
+ */
+#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_MODE_CONTINUOUS) || \
+ ((MODE) == DCMI_MODE_SNAPSHOT))
+
+#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \
+ ((MODE) == DCMI_SYNCHRO_EMBEDDED))
+
+#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \
+ ((POLARITY) == DCMI_PCKPOLARITY_RISING))
+
+#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPOLARITY_LOW) || \
+ ((POLARITY) == DCMI_VSPOLARITY_HIGH))
+
+#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPOLARITY_LOW) || \
+ ((POLARITY) == DCMI_HSPOLARITY_HIGH))
+
+#define IS_DCMI_MODE_JPEG(JPEG_MODE)(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \
+ ((JPEG_MODE) == DCMI_JPEG_ENABLE))
+
+#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CR_ALL_FRAME) || \
+ ((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \
+ ((RATE) == DCMI_CR_ALTERNATE_4_FRAME))
+
+#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_EXTEND_DATA_8B) || \
+ ((DATA) == DCMI_EXTEND_DATA_10B) || \
+ ((DATA) == DCMI_EXTEND_DATA_12B) || \
+ ((DATA) == DCMI_EXTEND_DATA_14B))
+
+#define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)
+
+#define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)
+
+#define IS_DCMI_BYTE_SELECT_MODE(MODE)(((MODE) == DCMI_BSM_ALL) || \
+ ((MODE) == DCMI_BSM_OTHER) || \
+ ((MODE) == DCMI_BSM_ALTERNATE_4) || \
+ ((MODE) == DCMI_BSM_ALTERNATE_2))
+
+#define IS_DCMI_BYTE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OEBS_ODD) || \
+ ((POLARITY) == DCMI_OEBS_EVEN))
+
+#define IS_DCMI_LINE_SELECT_MODE(MODE)(((MODE) == DCMI_LSM_ALL) || \
+ ((MODE) == DCMI_LSM_ALTERNATE_2))
+
+#define IS_DCMI_LINE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OELS_ODD) || \
+ ((POLARITY) == DCMI_OELS_EVEN))
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup DCMI_Private_Functions DCMI Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+#endif /* DCMI */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_DCMI_H */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_def.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_def.h
new file mode 100644
index 00000000..e5a72691
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_def.h
@@ -0,0 +1,227 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_def.h
+ * @author MCD Application Team
+ * @brief This file contains HAL common defines, enumeration, macros and
+ * structures definitions.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32U5xx_HAL_DEF
+#define __STM32U5xx_HAL_DEF
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#include
+#endif /* __ARM_FEATURE_CMSE */
+
+#include "stm32u5xx.h"
+#include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */
+#include
+#include
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief HAL Status structures definition
+ */
+typedef enum
+{
+ HAL_OK = 0x00,
+ HAL_ERROR = 0x01,
+ HAL_BUSY = 0x02,
+ HAL_TIMEOUT = 0x03
+} HAL_StatusTypeDef;
+
+/**
+ * @brief HAL Lock structures definition
+ */
+typedef enum
+{
+ HAL_UNLOCKED = 0x00,
+ HAL_LOCKED = 0x01
+} HAL_LockTypeDef;
+
+/* Exported macros -----------------------------------------------------------*/
+
+#define HAL_MAX_DELAY 0xFFFFFFFFU
+
+#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))
+#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
+
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
+ do{ \
+ (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
+ (__DMA_HANDLE__).Parent = (__HANDLE__); \
+ } while(0)
+
+#define UNUSED(x) ((void)(x))
+
+/** @brief Reset the Handle's State field.
+ * @param __HANDLE__: specifies the Peripheral Handle.
+ * @note This macro can be used for the following purpose:
+ * - When the Handle is declared as local variable; before passing it as parameter
+ * to HAL_PPP_Init() for the first time, it is mandatory to use this macro
+ * to set to 0 the Handle's "State" field.
+ * Otherwise, "State" field may have any random value and the first time the function
+ * HAL_PPP_Init() is called, the low level hardware initialization will be missed
+ * (i.e. HAL_PPP_MspInit() will not be executed).
+ * - When there is a need to reconfigure the low level hardware: instead of calling
+ * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
+ * In this later function, when the Handle's "State" field is set to 0, it will execute the function
+ * HAL_PPP_MspInit() which will reconfigure the low level hardware.
+ * @retval None
+ */
+#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
+
+#if (USE_RTOS == 1)
+/* Reserved for future use */
+#error " USE_RTOS should be 0 in the current HAL release "
+#else
+#define __HAL_LOCK(__HANDLE__) \
+ do{ \
+ if((__HANDLE__)->Lock == HAL_LOCKED) \
+ { \
+ return HAL_BUSY; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Lock = HAL_LOCKED; \
+ } \
+ }while (0)
+
+#define __HAL_UNLOCK(__HANDLE__) \
+ do{ \
+ (__HANDLE__)->Lock = HAL_UNLOCKED; \
+ }while (0)
+#endif /* USE_RTOS */
+
+#if defined ( __GNUC__ )
+#ifndef __weak
+#define __weak __attribute__((weak))
+#endif /* __weak */
+#ifndef __packed
+#define __packed __attribute__((__packed__))
+#endif /* __packed */
+#endif /* __GNUC__ */
+
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#ifndef __weak
+#define __weak __attribute__((weak))
+#endif /* __weak */
+#ifndef __packed
+#define __packed __attribute__((packed))
+#endif /* __packed */
+#endif /* __ARMCC_VERSION */
+
+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used
+ instead */
+#if defined (__GNUC__) /* GNU Compiler */
+#ifndef __ALIGN_END
+#define __ALIGN_END __attribute__ ((aligned (4)))
+#endif /* __ALIGN_END */
+#ifndef __ALIGN_BEGIN
+#define __ALIGN_BEGIN
+#endif /* __ALIGN_BEGIN */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#ifndef __ALIGN_END
+#define __ALIGN_END __ALIGNED(4)
+#endif /* __ALIGN_END */
+#ifndef __ALIGN_BEGIN
+#define __ALIGN_BEGIN
+#endif /* __ALIGN_BEGIN */
+#else
+#ifndef __ALIGN_END
+#define __ALIGN_END
+#endif /* __ALIGN_END */
+#ifndef __ALIGN_BEGIN
+#if defined (__CC_ARM) /* ARM Compiler */
+#define __ALIGN_BEGIN __align(4)
+#elif defined (__ICCARM__) /* IAR Compiler */
+#define __ALIGN_BEGIN
+#endif /* __CC_ARM */
+#endif /* __ALIGN_BEGIN */
+#endif /* __GNUC__ */
+
+/* Macro to get variable aligned on 32-bytes,needed for cache maintenance purpose */
+#if defined (__GNUC__) /* GNU Compiler */
+#define ALIGN_32BYTES(buf) buf __attribute__ ((aligned (32)))
+#elif defined (__ICCARM__) /* IAR Compiler */
+#define ALIGN_32BYTES(buf) _Pragma("data_alignment=32") buf
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#define ALIGN_32BYTES(buf) __ALIGNED(32) buf
+#elif defined (__CC_ARM) /* ARM Compiler */
+#define ALIGN_32BYTES(buf) __align(32) buf
+#endif /* __GNUC__ */
+
+/**
+ * @brief __RAM_FUNC definition
+ */
+#if defined ( __CC_ARM ) || ((__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+
+/* ARM Compiler
+ ------------
+ RAM functions are defined using the toolchain options.
+ Functions that are executed in RAM should reside in a separate source module.
+ Using the 'Options for File' dialog you can simply change the 'Code / Const'
+ area of a module to a memory space in physical RAM.
+ Available memory areas are declared in the 'Target' tab of the 'Options for Target'
+ dialog.
+*/
+#define __RAM_FUNC HAL_StatusTypeDef
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+ ---------------
+ RAM functions are defined using a specific toolchain keyword "__ramfunc".
+*/
+#define __RAM_FUNC __ramfunc HAL_StatusTypeDef
+
+#elif defined ( __GNUC__ )
+/* GNU Compiler
+ ------------
+ RAM functions are defined using a specific toolchain attribute
+ "__attribute__((section(".RamFunc")))".
+*/
+#define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc")))
+
+#endif /* __RAM_FUNC */
+
+/**
+ * @brief __NOINLINE definition
+ */
+#if defined ( __CC_ARM ) || ((__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ )
+/* ARM & GNUCompiler
+ ----------------
+*/
+#define __NOINLINE __attribute__ ( (noinline) )
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+ ---------------
+*/
+#define __NOINLINE _Pragma("optimize = no_inline")
+
+#endif /* __NOINLINE */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ___STM32U5xx_HAL_DEF */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma.h
new file mode 100644
index 00000000..0d910fe7
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma.h
@@ -0,0 +1,891 @@
+/**
+ **********************************************************************************************************************
+ * @file stm32u5xx_hal_dma.h
+ * @author MCD Application Team
+ * @brief Header file of DMA HAL module.
+ **********************************************************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ **********************************************************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/
+#ifndef STM32U5xx_HAL_DMA_H
+#define STM32U5xx_HAL_DMA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ----------------------------------------------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DMA
+ * @{
+ */
+
+
+/* Exported types ----------------------------------------------------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Types DMA Exported Types
+ * @brief DMA Exported Types
+ * @{
+ */
+
+/**
+ * @brief DMA Transfer Configuration Structure definition.
+ */
+typedef struct
+{
+ uint32_t Request; /*!< Specifies the DMA channel request.
+ This parameter can be a value of @ref DMA_Request_Selection */
+
+ uint32_t BlkHWRequest; /*!< Specifies the Block hardware request mode for DMA channel.
+ Block Hardware request feature can be used only with dedicated peripherals.
+ This parameter can be a value of @ref DMA_Block_Request */
+
+ uint32_t Direction; /*!< Specifies the transfer direction for DMA channel.
+ This parameter can be a value of @ref DMA_Transfer_Direction */
+
+ uint32_t SrcInc; /*!< Specifies the source increment mode for the DMA channel.
+ This parameter can be a value of @ref DMA_Source_Increment_Mode */
+
+ uint32_t DestInc; /*!< Specifies the destination increment mode for the DMA channel.
+ This parameter can be a value of @ref DMA_Destination_Increment_Mode */
+
+ uint32_t SrcDataWidth; /*!< Specifies the source data width for the DMA channel.
+ This parameter can be a value of @ref DMA_Source_Data_Width */
+
+ uint32_t DestDataWidth; /*!< Specifies the destination data width for the DMA channel.
+ This parameter can be a value of @ref DMA_Destination_Data_Width */
+
+ uint32_t Priority; /*!< Specifies the priority level for the DMA channel.
+ This parameter can be a value of @ref DMA_Priority_Level */
+
+ uint32_t SrcBurstLength; /*!< Specifies the source burst length (number of beats within a burst) for the DMA
+ channel.
+ This parameter can be a value between 1 and 64 */
+
+ uint32_t DestBurstLength; /*!< Specifies the destination burst length (number of beats within a burst) for the
+ DMA channel.
+ This parameter can be a value between 1 and 64 */
+
+ uint32_t TransferAllocatedPort; /*!< Specifies the transfer allocated ports.
+ This parameter can be a combination of @ref DMA_Transfer_Allocated_Port */
+
+ uint32_t TransferEventMode; /*!< Specifies the transfer event mode for the DMA channel.
+ This parameter can be a value of @ref DMA_Transfer_Event_Mode */
+
+ uint32_t Mode; /*!< Specifies the transfer mode for the DMA channel.
+ This parameter can be a value of @ref DMA_Transfer_Mode */
+
+} DMA_InitTypeDef;
+
+/**
+ * @brief DMA Linked-List Configuration Structure Definition.
+ */
+typedef struct
+{
+ uint32_t Priority; /*!< Specifies the priority level for the DMA channel.
+ This parameter can be a value of @ref DMA_Priority_Level */
+
+ uint32_t LinkStepMode; /*!< Specifies the link step mode for the DMA channel.
+ This parameter can be a value of @ref DMAEx_Link_Step_Mode */
+
+ uint32_t LinkAllocatedPort; /*!< Specifies the linked-list allocated port for the DMA channel.
+ This parameter can be a value of @ref DMAEx_Link_Allocated_Port */
+
+ uint32_t TransferEventMode; /*!< Specifies the transfer event mode for the DMA channel.
+ This parameter can be a value of @ref DMA_Transfer_Event_Mode */
+
+ uint32_t LinkedListMode; /*!< Specifies linked-list transfer mode for the DMA channel.
+ This parameter can be a value of @ref DMAEx_LinkedList_Mode */
+
+} DMA_InitLinkedListTypeDef;
+
+/**
+ * @brief HAL DMA State Enumeration Definition.
+ */
+typedef enum
+{
+ HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
+ HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
+ HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
+ HAL_DMA_STATE_ERROR = 0x03U, /*!< DMA error state */
+ HAL_DMA_STATE_ABORT = 0x04U, /*!< DMA Abort state */
+ HAL_DMA_STATE_SUSPEND = 0x05U, /*!< DMA Suspend state */
+
+} HAL_DMA_StateTypeDef;
+
+/**
+ * @brief HAL DMA Level Complete Enumeration Definition.
+ */
+typedef enum
+{
+ HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full channel transfer */
+ HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half channel transfer */
+
+} HAL_DMA_LevelCompleteTypeDef;
+
+/**
+ * @brief HAL DMA Callbacks IDs Enumeration Definition.
+ */
+typedef enum
+{
+ HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Complete transfer callback ID */
+ HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half complete transfer callback ID */
+ HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error transfer callback ID */
+ HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort transfer callback ID */
+ HAL_DMA_XFER_SUSPEND_CB_ID = 0x04U, /*!< Suspend transfer callback ID */
+ HAL_DMA_XFER_ALL_CB_ID = 0x05U /*!< All callback ID */
+
+} HAL_DMA_CallbackIDTypeDef;
+
+/**
+ * @brief DMA handle Structure definition
+ */
+typedef struct __DMA_HandleTypeDef
+{
+ DMA_Channel_TypeDef *Instance; /*!< Register the DMA channel base address */
+
+ DMA_InitTypeDef Init; /*!< DMA channel init parameters */
+
+ DMA_InitLinkedListTypeDef InitLinkedList; /*!< DMA channel linked-list init parameters */
+
+ HAL_LockTypeDef Lock; /*!< DMA locking object */
+
+ uint32_t Mode; /*!< DMA transfer mode */
+
+ __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
+
+ __IO uint32_t ErrorCode; /*!< DMA error code */
+
+ void *Parent; /*!< Parent object state */
+
+ void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */
+
+ void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA half transfer complete callback */
+
+ void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */
+
+ void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer Abort callback */
+
+ void (* XferSuspendCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer Suspend callback */
+
+ struct __DMA_QListTypeDef *LinkedListQueue; /*!< DMA linked-list queue */
+
+} DMA_HandleTypeDef;
+/**
+ * @}
+ */
+
+
+/* Exported constants ------------------------------------------------------------------------------------------------*/
+/** @defgroup DMA_Exported_Constants DMA Exported Constants
+ * @brief DMA Exported constants
+ * @{
+ */
+
+/** @defgroup DMA_Error_Codes DMA Error Codes
+ * @brief DMA Error Codes
+ * @{
+ */
+#define HAL_DMA_ERROR_NONE (0x0000U) /*!< No error */
+#define HAL_DMA_ERROR_DTE (0x0001U) /*!< Data transfer error */
+#define HAL_DMA_ERROR_ULE (0x0002U) /*!< Update linked-list item error */
+#define HAL_DMA_ERROR_USE (0x0004U) /*!< User setting error */
+#define HAL_DMA_ERROR_TO (0x0008U) /*!< Trigger overrun error */
+#define HAL_DMA_ERROR_TIMEOUT (0x0010U) /*!< Timeout error */
+#define HAL_DMA_ERROR_NO_XFER (0x0020U) /*!< No transfer ongoing error */
+#define HAL_DMA_ERROR_BUSY (0x0040U) /*!< Busy error */
+#define HAL_DMA_ERROR_INVALID_CALLBACK (0x0080U) /*!< Invalid callback error */
+#define HAL_DMA_ERROR_NOT_SUPPORTED (0x0100U) /*!< Not supported mode */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Interrupt_Enable_Definition DMA Interrupt Enable Definition
+ * @brief DMA Interrupt Enable Definition
+ * @{
+ */
+#define DMA_IT_TC DMA_CCR_TCIE /*!< Transfer complete interrupt */
+#define DMA_IT_HT DMA_CCR_HTIE /*!< Half transfer complete interrupt */
+#define DMA_IT_DTE DMA_CCR_DTEIE /*!< Data transfer error interrupt */
+#define DMA_IT_ULE DMA_CCR_ULEIE /*!< Update linked-list item error interrupt */
+#define DMA_IT_USE DMA_CCR_USEIE /*!< User eetting error interrupt */
+#define DMA_IT_SUSP DMA_CCR_SUSPIE /*!< Completed suspension interrupt */
+#define DMA_IT_TO DMA_CCR_TOIE /*!< Trigger overrun interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Flag_Definition DMA Flag Definition
+ * @brief DMA Flag Definition
+ * @{
+ */
+#define DMA_FLAG_IDLE DMA_CSR_IDLEF /*!< Idle flag */
+#define DMA_FLAG_TC DMA_CSR_TCF /*!< Transfer complete flag */
+#define DMA_FLAG_HT DMA_CSR_HTF /*!< Half transfer complete flag */
+#define DMA_FLAG_DTE DMA_CSR_DTEF /*!< Data transfer error flag */
+#define DMA_FLAG_ULE DMA_CSR_ULEF /*!< Update linked-list item error flag */
+#define DMA_FLAG_USE DMA_CSR_USEF /*!< User setting error flag */
+#define DMA_FLAG_SUSP DMA_CSR_SUSPF /*!< Completed suspension flag */
+#define DMA_FLAG_TO DMA_CSR_TOF /*!< Trigger overrun flag */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Request_Selection DMA Request Selection
+ * @brief DMA Request Selection
+ * @{
+ */
+/* GPDMA1 requests */
+#define GPDMA1_REQUEST_ADC1 (0U) /*!< GPDMA1 HW request is ADC1 */
+#define GPDMA1_REQUEST_ADC4 (1U) /*!< GPDMA1 HW request is ADC4 */
+#define GPDMA1_REQUEST_DAC1_CH1 (2U) /*!< GPDMA1 HW request is DAC1_CH1 */
+#define GPDMA1_REQUEST_DAC1_CH2 (3U) /*!< GPDMA1 HW request is DAC1_CH2 */
+#define GPDMA1_REQUEST_TIM6_UP (4U) /*!< GPDMA1 HW request is TIM6_UP */
+#define GPDMA1_REQUEST_TIM7_UP (5U) /*!< GPDMA1 HW request is TIM7_UP */
+#define GPDMA1_REQUEST_SPI1_RX (6U) /*!< GPDMA1 HW request is SPI1_RX */
+#define GPDMA1_REQUEST_SPI1_TX (7U) /*!< GPDMA1 HW request is SPI1_TX */
+#define GPDMA1_REQUEST_SPI2_RX (8U) /*!< GPDMA1 HW request is SPI2_RX */
+#define GPDMA1_REQUEST_SPI2_TX (9U) /*!< GPDMA1 HW request is SPI2_TX */
+#define GPDMA1_REQUEST_SPI3_RX (10U) /*!< GPDMA1 HW request is SPI3_RX */
+#define GPDMA1_REQUEST_SPI3_TX (11U) /*!< GPDMA1 HW request is SPI3_TX */
+#define GPDMA1_REQUEST_I2C1_RX (12U) /*!< GPDMA1 HW request is I2C1_RX */
+#define GPDMA1_REQUEST_I2C1_TX (13U) /*!< GPDMA1 HW request is I2C1_TX */
+#define GPDMA1_REQUEST_I2C1_EVC (14U) /*!< GPDMA1 HW request is I2C1_EVC */
+#define GPDMA1_REQUEST_I2C2_RX (15U) /*!< GPDMA1 HW request is I2C2_RX */
+#define GPDMA1_REQUEST_I2C2_TX (16U) /*!< GPDMA1 HW request is I2C2_TX */
+#define GPDMA1_REQUEST_I2C2_EVC (17U) /*!< GPDMA1 HW request is I2C2_EVC */
+#define GPDMA1_REQUEST_I2C3_RX (18U) /*!< GPDMA1 HW request is I2C3_RX */
+#define GPDMA1_REQUEST_I2C3_TX (19U) /*!< GPDMA1 HW request is I2C3_TX */
+#define GPDMA1_REQUEST_I2C3_EVC (20U) /*!< GPDMA1 HW request is I2C3_EVC */
+#define GPDMA1_REQUEST_I2C4_RX (21U) /*!< GPDMA1 HW request is I2C4_RX */
+#define GPDMA1_REQUEST_I2C4_TX (22U) /*!< GPDMA1 HW request is I2C4_TX */
+#define GPDMA1_REQUEST_I2C4_EVC (23U) /*!< GPDMA1 HW request is I2C4_EVC */
+#define GPDMA1_REQUEST_USART1_RX (24U) /*!< GPDMA1 HW request is USART1_RX */
+#define GPDMA1_REQUEST_USART1_TX (25U) /*!< GPDMA1 HW request is USART1_TX */
+#define GPDMA1_REQUEST_USART2_RX (26U) /*!< GPDMA1 HW request is USART2_RX */
+#define GPDMA1_REQUEST_USART2_TX (27U) /*!< GPDMA1 HW request is USART2_TX */
+#define GPDMA1_REQUEST_USART3_RX (28U) /*!< GPDMA1 HW request is USART3_RX */
+#define GPDMA1_REQUEST_USART3_TX (29U) /*!< GPDMA1 HW request is USART3_TX */
+#define GPDMA1_REQUEST_UART4_RX (30U) /*!< GPDMA1 HW request is UART4_RX */
+#define GPDMA1_REQUEST_UART4_TX (31U) /*!< GPDMA1 HW request is UART4_TX */
+#define GPDMA1_REQUEST_UART5_RX (32U) /*!< GPDMA1 HW request is UART5_RX */
+#define GPDMA1_REQUEST_UART5_TX (33U) /*!< GPDMA1 HW request is UART5_TX */
+#define GPDMA1_REQUEST_LPUART1_RX (34U) /*!< GPDMA1 HW request is LPUART1_RX */
+#define GPDMA1_REQUEST_LPUART1_TX (35U) /*!< GPDMA1 HW request is LPUART1_TX */
+#define GPDMA1_REQUEST_SAI1_A (36U) /*!< GPDMA1 HW request is SAI1_A */
+#define GPDMA1_REQUEST_SAI1_B (37U) /*!< GPDMA1 HW request is SAI1_B */
+#define GPDMA1_REQUEST_SAI2_A (38U) /*!< GPDMA1 HW request is SAI2_A */
+#define GPDMA1_REQUEST_SAI2_B (39U) /*!< GPDMA1 HW request is SAI2_B */
+#define GPDMA1_REQUEST_OCTOSPI1 (40U) /*!< GPDMA1 HW request is OCTOSPI1 */
+#define GPDMA1_REQUEST_OCTOSPI2 (41U) /*!< GPDMA1 HW request is OCTOSPI2 */
+#define GPDMA1_REQUEST_TIM1_CH1 (42U) /*!< GPDMA1 HW request is TIM1_CH1 */
+#define GPDMA1_REQUEST_TIM1_CH2 (43U) /*!< GPDMA1 HW request is TIM1_CH2 */
+#define GPDMA1_REQUEST_TIM1_CH3 (44U) /*!< GPDMA1 HW request is TIM1_CH3 */
+#define GPDMA1_REQUEST_TIM1_CH4 (45U) /*!< GPDMA1 HW request is TIM1_CH4 */
+#define GPDMA1_REQUEST_TIM1_UP (46U) /*!< GPDMA1 HW request is TIM1_UP */
+#define GPDMA1_REQUEST_TIM1_TRIG (47U) /*!< GPDMA1 HW request is TIM1_TRIG */
+#define GPDMA1_REQUEST_TIM1_COM (48U) /*!< GPDMA1 HW request is TIM1_COM */
+#define GPDMA1_REQUEST_TIM8_CH1 (49U) /*!< GPDMA1 HW request is TIM8_CH1 */
+#define GPDMA1_REQUEST_TIM8_CH2 (50U) /*!< GPDMA1 HW request is TIM8_CH2 */
+#define GPDMA1_REQUEST_TIM8_CH3 (51U) /*!< GPDMA1 HW request is TIM8_CH3 */
+#define GPDMA1_REQUEST_TIM8_CH4 (52U) /*!< GPDMA1 HW request is TIM8_CH4 */
+#define GPDMA1_REQUEST_TIM8_UP (53U) /*!< GPDMA1 HW request is TIM8_UP */
+#define GPDMA1_REQUEST_TIM8_TRIG (54U) /*!< GPDMA1 HW request is TIM8_TRIG */
+#define GPDMA1_REQUEST_TIM8_COM (55U) /*!< GPDMA1 HW request is TIM8_COM */
+#define GPDMA1_REQUEST_TIM2_CH1 (56U) /*!< GPDMA1 HW request is TIM2_CH1 */
+#define GPDMA1_REQUEST_TIM2_CH2 (57U) /*!< GPDMA1 HW request is TIM2_CH2 */
+#define GPDMA1_REQUEST_TIM2_CH3 (58U) /*!< GPDMA1 HW request is TIM2_CH3 */
+#define GPDMA1_REQUEST_TIM2_CH4 (59U) /*!< GPDMA1 HW request is TIM2_CH4 */
+#define GPDMA1_REQUEST_TIM2_UP (60U) /*!< GPDMA1 HW request is TIM2_UP */
+#define GPDMA1_REQUEST_TIM3_CH1 (61U) /*!< GPDMA1 HW request is TIM3_CH1 */
+#define GPDMA1_REQUEST_TIM3_CH2 (62U) /*!< GPDMA1 HW request is TIM3_CH2 */
+#define GPDMA1_REQUEST_TIM3_CH3 (63U) /*!< GPDMA1 HW request is TIM3_CH3 */
+#define GPDMA1_REQUEST_TIM3_CH4 (64U) /*!< GPDMA1 HW request is TIM3_CH4 */
+#define GPDMA1_REQUEST_TIM3_UP (65U) /*!< GPDMA1 HW request is TIM3_UP */
+#define GPDMA1_REQUEST_TIM3_TRIG (66U) /*!< GPDMA1 HW request is TIM3_TRIG */
+#define GPDMA1_REQUEST_TIM4_CH1 (67U) /*!< GPDMA1 HW request is TIM4_CH1 */
+#define GPDMA1_REQUEST_TIM4_CH2 (68U) /*!< GPDMA1 HW request is TIM4_CH2 */
+#define GPDMA1_REQUEST_TIM4_CH3 (69U) /*!< GPDMA1 HW request is TIM4_CH3 */
+#define GPDMA1_REQUEST_TIM4_CH4 (70U) /*!< GPDMA1 HW request is TIM4_CH4 */
+#define GPDMA1_REQUEST_TIM4_UP (71U) /*!< GPDMA1 HW request is TIM4_UP */
+#define GPDMA1_REQUEST_TIM5_CH1 (72U) /*!< GPDMA1 HW request is TIM5_CH1 */
+#define GPDMA1_REQUEST_TIM5_CH2 (73U) /*!< GPDMA1 HW request is TIM5_CH2 */
+#define GPDMA1_REQUEST_TIM5_CH3 (74U) /*!< GPDMA1 HW request is TIM5_CH3 */
+#define GPDMA1_REQUEST_TIM5_CH4 (75U) /*!< GPDMA1 HW request is TIM5_CH4 */
+#define GPDMA1_REQUEST_TIM5_UP (76U) /*!< GPDMA1 HW request is TIM5_UP */
+#define GPDMA1_REQUEST_TIM5_TRIG (77U) /*!< GPDMA1 HW request is TIM5_TRIG */
+#define GPDMA1_REQUEST_TIM15_CH1 (78U) /*!< GPDMA1 HW request is TIM15_CH1 */
+#define GPDMA1_REQUEST_TIM15_UP (79U) /*!< GPDMA1 HW request is TIM15_UP */
+#define GPDMA1_REQUEST_TIM15_TRIG (80U) /*!< GPDMA1 HW request is TIM15_TRIG */
+#define GPDMA1_REQUEST_TIM15_COM (81U) /*!< GPDMA1 HW request is TIM15_COM */
+#define GPDMA1_REQUEST_TIM16_CH1 (82U) /*!< GPDMA1 HW request is TIM16_CH1 */
+#define GPDMA1_REQUEST_TIM16_UP (83U) /*!< GPDMA1 HW request is TIM16_UP */
+#define GPDMA1_REQUEST_TIM17_CH1 (84U) /*!< GPDMA1 HW request is TIM17_CH1 */
+#define GPDMA1_REQUEST_TIM17_UP (85U) /*!< GPDMA1 HW request is TIM17_UP */
+#define GPDMA1_REQUEST_DCMI (86U) /*!< GPDMA1 HW request is DCMI */
+#define GPDMA1_REQUEST_AES_IN (87U) /*!< GPDMA1 HW request is AES_IN */
+#define GPDMA1_REQUEST_AES_OUT (88U) /*!< GPDMA1 HW request is AES_OUT */
+#define GPDMA1_REQUEST_HASH_IN (89U) /*!< GPDMA1 HW request is HASH_IN */
+#define GPDMA1_REQUEST_UCPD1_TX (90U) /*!< GPDMA1 HW request is UCPD1_TX */
+#define GPDMA1_REQUEST_UCPD1_RX (91U) /*!< GPDMA1 HW request is UCPD1_RX */
+#define GPDMA1_REQUEST_MDF1_FLT0 (92U) /*!< GPDMA1 HW request is MDF1_FLT0 */
+#define GPDMA1_REQUEST_MDF1_FLT1 (93U) /*!< GPDMA1 HW request is MDF1_FLT1 */
+#define GPDMA1_REQUEST_MDF1_FLT2 (94U) /*!< GPDMA1 HW request is MDF1_FLT2 */
+#define GPDMA1_REQUEST_MDF1_FLT3 (95U) /*!< GPDMA1 HW request is MDF1_FLT3 */
+#define GPDMA1_REQUEST_MDF1_FLT4 (96U) /*!< GPDMA1 HW request is MDF1_FLT4 */
+#define GPDMA1_REQUEST_MDF1_FLT5 (97U) /*!< GPDMA1 HW request is MDF1_FLT5 */
+#define GPDMA1_REQUEST_ADF1_FLT0 (98U) /*!< GPDMA1 HW request is ADF1_FLT0 */
+#define GPDMA1_REQUEST_FMAC_READ (99U) /*!< GPDMA1 HW request is FMAC_READ */
+#define GPDMA1_REQUEST_FMAC_WRITE (100U) /*!< GPDMA1 HW request is FMAC_WRITE */
+#define GPDMA1_REQUEST_CORDIC_READ (101U) /*!< GPDMA1 HW request is CORDIC_READ */
+#define GPDMA1_REQUEST_CORDIC_WRITE (102U) /*!< GPDMA1 HW request is CORDIC_WRITE */
+#define GPDMA1_REQUEST_SAES_IN (103U) /*!< GPDMA1 HW request is SAES_IN */
+#define GPDMA1_REQUEST_SAES_OUT (104U) /*!< GPDMA1 HW request is SAES_OUT */
+#define GPDMA1_REQUEST_LPTIM1_IC1 (105U) /*!< GPDMA1 HW request is LPTIM1_IC1 */
+#define GPDMA1_REQUEST_LPTIM1_IC2 (106U) /*!< GPDMA1 HW request is LPTIM1_IC2 */
+#define GPDMA1_REQUEST_LPTIM1_UE (107U) /*!< GPDMA1 HW request is LPTIM1_UE */
+#define GPDMA1_REQUEST_LPTIM2_IC1 (108U) /*!< GPDMA1 HW request is LPTIM2_IC1 */
+#define GPDMA1_REQUEST_LPTIM2_IC2 (109U) /*!< GPDMA1 HW request is LPTIM2_IC2 */
+#define GPDMA1_REQUEST_LPTIM2_UE (110U) /*!< GPDMA1 HW request is LPTIM2_UE */
+#define GPDMA1_REQUEST_LPTIM3_IC1 (111U) /*!< GPDMA1 HW request is LPTIM3_IC1 */
+#define GPDMA1_REQUEST_LPTIM3_IC2 (112U) /*!< GPDMA1 HW request is LPTIM3_IC2 */
+#define GPDMA1_REQUEST_LPTIM3_UE (113U) /*!< GPDMA1 HW request is LPTIM3_UE */
+
+/* LPDMA1 requests */
+#define LPDMA1_REQUEST_LPUART1_RX (0U) /*!< LPDMA1 HW request is LPUART1_RX */
+#define LPDMA1_REQUEST_LPUART1_TX (1U) /*!< LPDMA1 HW request is LPUART1_TX */
+#define LPDMA1_REQUEST_SPI3_RX (2U) /*!< LPDMA1 HW request is SPI3_RX */
+#define LPDMA1_REQUEST_SPI3_TX (3U) /*!< LPDMA1 HW request is SPI3_TX */
+#define LPDMA1_REQUEST_I2C3_RX (4U) /*!< LPDMA1 HW request is I2C3_RX */
+#define LPDMA1_REQUEST_I2C3_TX (5U) /*!< LPDMA1 HW request is I2C3_TX */
+#define LPDMA1_REQUEST_I2C3_EVC (6U) /*!< LPDMA1 HW request is I2C3_EVC */
+#define LPDMA1_REQUEST_ADC4 (7U) /*!< LPDMA1 HW request is ADC4 */
+#define LPDMA1_REQUEST_DAC1_CH1 (8U) /*!< LPDMA1 HW request is DAC1_CH1 */
+#define LPDMA1_REQUEST_DAC1_CH2 (9U) /*!< LPDMA1 HW request is DAC1_CH2 */
+#define LPDMA1_REQUEST_ADF1_FLT0 (10U) /*!< LPDMA1 HW request is ADF1_FLT0 */
+#define LPDMA1_REQUEST_LPTIM1_IC1 (11U) /*!< LPDMA1 HW request is LPTIM1_IC1 */
+#define LPDMA1_REQUEST_LPTIM1_IC2 (12U) /*!< LPDMA1 HW request is LPTIM1_IC2 */
+#define LPDMA1_REQUEST_LPTIM1_UE (13U) /*!< LPDMA1 HW request is LPTIM1_UE */
+#define LPDMA1_REQUEST_LPTIM3_IC1 (14U) /*!< LPDMA1 HW request is LPTIM3_IC1 */
+#define LPDMA1_REQUEST_LPTIM3_IC2 (15U) /*!< LPDMA1 HW request is LPTIM3_IC2 */
+#define LPDMA1_REQUEST_LPTIM3_UE (16U) /*!< LPDMA1 HW request is LPTIM3_UE */
+
+/* Software request */
+#define DMA_REQUEST_SW DMA_CTR2_SWREQ /*!< DMA SW request */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Block_Request DMA Block Request
+ * @brief DMA Block Request
+ * @{
+ */
+#define DMA_BREQ_SINGLE_BURST 0x00000000U /*!< Hardware request protocol at a single / burst level */
+#define DMA_BREQ_BLOCK DMA_CTR2_BREQ /*!< Hardware request protocol at a block level */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Transfer_Direction DMA Transfer Direction
+ * @brief DMA transfer direction
+ * @{
+ */
+#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
+#define DMA_MEMORY_TO_PERIPH DMA_CTR2_DREQ /*!< Memory to peripheral direction */
+#define DMA_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Source_Increment_Mode DMA Source Increment Mode
+ * @brief DMA Source Increment Mode
+ * @{
+ */
+#define DMA_SINC_FIXED 0x00000000U /*!< Source fixed single / burst */
+#define DMA_SINC_INCREMENTED DMA_CTR1_SINC /*!< Source incremented single / burst */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Destination_Increment_Mode DMA Destination Increment Mode
+ * @brief DMA Destination Increment Mode
+ * @{
+ */
+#define DMA_DINC_FIXED 0x00000000U /*!< Destination fixed single / burst */
+#define DMA_DINC_INCREMENTED DMA_CTR1_DINC /*!< Destination incremented single / burst */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Source_Data_Width DMA Source Data Width
+ * @brief DMA Source Data Width
+ * @{
+ */
+#define DMA_SRC_DATAWIDTH_BYTE 0x00000000U /*!< Source data width : Byte */
+#define DMA_SRC_DATAWIDTH_HALFWORD DMA_CTR1_SDW_LOG2_0 /*!< Source data width : HalfWord */
+#define DMA_SRC_DATAWIDTH_WORD DMA_CTR1_SDW_LOG2_1 /*!< Source data width : Word */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Destination_Data_Width DMA destination Data Width
+ * @brief DMA destination Data Width
+ * @{
+ */
+#define DMA_DEST_DATAWIDTH_BYTE 0x00000000U /*!< Destination data width : Byte */
+#define DMA_DEST_DATAWIDTH_HALFWORD DMA_CTR1_DDW_LOG2_0 /*!< Destination data width : HalfWord */
+#define DMA_DEST_DATAWIDTH_WORD DMA_CTR1_DDW_LOG2_1 /*!< Destination data width : Word */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Priority_Level DMA Priority Level
+ * @brief DMA Priority Level
+ * @{
+ */
+#define DMA_LOW_PRIORITY_LOW_WEIGHT 0x00000000U /*!< Priority level : Low Priority, Low weight */
+#define DMA_LOW_PRIORITY_MID_WEIGHT DMA_CCR_PRIO_0 /*!< Priority level : Low Priority, Mid weight */
+#define DMA_LOW_PRIORITY_HIGH_WEIGHT DMA_CCR_PRIO_1 /*!< Priority level : Low Priority, High weight */
+#define DMA_HIGH_PRIORITY DMA_CCR_PRIO /*!< Priority level : HIGH Priority */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Transfer_Allocated_Port DMA Transfer Allocated Port
+ * @brief DMA Transfer Allocated Port
+ * @{
+ */
+#define DMA_SRC_ALLOCATED_PORT0 0x00000000U /*!< Source allocated Port 0 */
+#define DMA_SRC_ALLOCATED_PORT1 DMA_CTR1_SAP /*!< Source allocated Port 1 */
+#define DMA_DEST_ALLOCATED_PORT0 0x00000000U /*!< Destination allocated Port 0 */
+#define DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP /*!< Destination allocated Port 1 */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Transfer_Event_Mode DMA Transfer Event Mode
+ * @brief DMA Transfer Event Mode
+ * @{
+ */
+#define DMA_TCEM_BLOCK_TRANSFER 0x00000000U /*!< The TC event is generated at the end of each block and the
+ HT event is generated at the half of each block */
+#define DMA_TCEM_REPEATED_BLOCK_TRANSFER DMA_CTR2_TCEM_0 /*!< The TC event is generated at the end of the repeated block
+ and the HT event is generated at the half of the repeated
+ block */
+#define DMA_TCEM_EACH_LL_ITEM_TRANSFER DMA_CTR2_TCEM_1 /*!< The TC event is generated at the end of each linked-list
+ item and the HT event is generated at the half of each
+ linked-list item */
+#define DMA_TCEM_LAST_LL_ITEM_TRANSFER DMA_CTR2_TCEM /*!< The TC event is generated at the end of the last
+ linked-list item and the HT event is generated at the half
+ of the last linked-list item */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Transfer_Mode DMA Transfer Mode
+ * @brief DMA Transfer Mode
+ * @{
+ */
+#define DMA_NORMAL (0x00U) /*!< Normal DMA transfer */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Channel_Attributes DMA Channel Attributes
+ * @brief DMA Channel Security and Privilege Attributes
+ * @note Secure and non-secure attributes are only available from the secure world when TZEN = 1
+ * @{
+ */
+#define DMA_CHANNEL_PRIV (DMA_CHANNEL_ATTR_PRIV_MASK | 0x01U) /*!< Channel is privileged */
+#define DMA_CHANNEL_NPRIV (DMA_CHANNEL_ATTR_PRIV_MASK) /*!< Channel is unprivileged */
+
+#define DMA_CHANNEL_SEC (DMA_CHANNEL_ATTR_SEC_MASK | 0x02U) /*!< Channel is secure */
+#define DMA_CHANNEL_NSEC (DMA_CHANNEL_ATTR_SEC_MASK) /*!< Channel is non-secure */
+#define DMA_CHANNEL_SRC_SEC (DMA_CHANNEL_ATTR_SEC_SRC_MASK | 0x04U) /*!< Channel source is secure */
+#define DMA_CHANNEL_SRC_NSEC (DMA_CHANNEL_ATTR_SEC_SRC_MASK) /*!< Channel source is non-secure */
+#define DMA_CHANNEL_DEST_SEC (DMA_CHANNEL_ATTR_SEC_DEST_MASK | 0x08U) /*!< Channel destination is secure */
+#define DMA_CHANNEL_DEST_NSEC (DMA_CHANNEL_ATTR_SEC_DEST_MASK) /*!< Channel destination is non-secure */
+
+#define DMA_CHANNEL_ATTRIBUTE_UNLOCKED (0x00U) /*!< Channel attribute is unlocked */
+#define DMA_CHANNEL_ATTRIBUTE_LOCKED (0x01U) /*!< Channel attribute is locked */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ----------------------------------------------------------------------------------------------------*/
+/** @defgroup DMA_Exported_Macros DMA Exported Macros
+ * @brief DMA Exported Macros
+ * @{
+ */
+
+/** @brief Reset DMA handle state.
+ * @param __HANDLE__ : DMA handle.
+ * @retval None.
+ */
+#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) \
+ ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
+
+/**
+ * @brief Enable the specified DMA Channel.
+ * @param __HANDLE__ : DMA handle.
+ * @retval None
+ */
+#define __HAL_DMA_ENABLE(__HANDLE__) \
+ ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
+
+/**
+ * @brief Disable the specified DMA Channel.
+ * @param __HANDLE__ : DMA handle.
+ * @retval None
+ */
+#define __HAL_DMA_DISABLE(__HANDLE__) \
+ ((__HANDLE__)->Instance->CCR |= (DMA_CCR_SUSP | DMA_CCR_RESET))
+
+/**
+ * @brief Get the DMA channel pending flags.
+ * @param __HANDLE__ : DMA handle.
+ * @param __FLAG__ : Get the specified flag.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_FLAG_TC : Transfer Complete flag.
+ * @arg DMA_FLAG_HT : Half Transfer Complete flag.
+ * @arg DMA_FLAG_DTE : Data Transfer Error flag.
+ * @arg DMA_FLAG_ULE : Update linked-list Error flag.
+ * @arg DMA_FLAG_USE : User Setting Error flag.
+ * @arg DMA_FLAG_TO : Trigger Overrun flag.
+ * @arg DMA_FLAG_SUSP : Completed Suspension flag.
+ * @arg DMA_FLAG_IDLEF : Idle flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) \
+ ((__HANDLE__)->Instance->CSR & (__FLAG__))
+
+/**
+ * @brief Clear the DMA Channel pending flags.
+ * @param __HANDLE__ : DMA handle.
+ * @param __FLAG__ : Specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_FLAG_TC : Transfer Complete flag.
+ * @arg DMA_FLAG_HT : Half Transfer Complete flag.
+ * @arg DMA_FLAG_DTE : Data Transfer Error flag.
+ * @arg DMA_FLAG_ULE : Update Linked-List Error flag.
+ * @arg DMA_FLAG_USE : User Setting Error flag.
+ * @arg DMA_FLAG_TO : Trigger Overrun flag.
+ * @arg DMA_FLAG_SUSP : Completed Suspension flag.
+ * @retval None
+ */
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+ ((__HANDLE__)->Instance->CFCR = (__FLAG__))
+
+/**
+ * @brief Enable the specified DMA Channel interrupts.
+ * @param __HANDLE__ : DMA handle.
+ * @param __INTERRUPT__ : Specifies the DMA interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_IT_TC : Transfer Complete interrupt.
+ * @arg DMA_IT_HT : Half Transfer Complete interrupt.
+ * @arg DMA_IT_DTE : Data Transfer Error interrupt.
+ * @arg DMA_IT_ULE : Update Linked-List Error interrupt.
+ * @arg DMA_IT_USE : User Setting Error interrupt.
+ * @arg DMA_IT_TO : Trigger Overrun interrupt.
+ * @arg DMA_IT_SUSP : Completed Suspension interrupt.
+ * @retval None
+ */
+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
+ ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the specified DMA Channel interrupts.
+ * @param __HANDLE__ : DMA handle.
+ * @param __INTERRUPT__ : specifies the DMA interrupt sources to be disabled.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_IT_TC : Transfer Complete interrupt.
+ * @arg DMA_IT_HT : Half Transfer Complete interrupt.
+ * @arg DMA_IT_DTE : Data Transfer Error interrupt.
+ * @arg DMA_IT_ULE : Update Linked-List Error interrupt.
+ * @arg DMA_IT_USE : User Setting Error interrupt.
+ * @arg DMA_IT_TO : Trigger Overrun interrupt.
+ * @arg DMA_IT_SUSP : Completed Suspension interrupt.
+ * @retval None
+ */
+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
+ ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Checks whether the specified DMA Channel interrupt is enabled or not.
+ * @param __HANDLE__ : DMA handle.
+ * @param __INTERRUPT__ : specifies the DMA interrupt source to check.
+ * @arg DMA_IT_TC : Transfer Complete interrupt.
+ * @arg DMA_IT_HT : Half Transfer Complete interrupt.
+ * @arg DMA_IT_DTE : Data Transfer Error interrupt.
+ * @arg DMA_IT_ULE : Update Linked-List Error interrupt.
+ * @arg DMA_IT_USE : User Setting Error interrupt.
+ * @arg DMA_IT_TO : Trigger Overrun interrupt.
+ * @arg DMA_IT_SUSP : Completed Suspension interrupt.
+ * @retval The state of DMA_IT (SET or RESET).
+ */
+#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
+
+/**
+ * @brief Writes the block number of bytes to be transferred from the source on the DMA Channel.
+ * @param __HANDLE__ : DMA handle.
+ * @param __COUNTER__ : Number of data bytes to be transferred from the source (from 0 to 65535).
+ */
+#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) \
+ MODIFY_REG((__HANDLE__)->Instance->CBR1, DMA_CBR1_BNDT, (__COUNTER__))
+
+/**
+ * @brief Returns the number of remaining data bytes in the current DMA Channel transfer.
+ * @param __HANDLE__ : DMA handle.
+ * @retval The number of remaining data units in the current DMA Stream transfer.
+ */
+#define __HAL_DMA_GET_COUNTER(__HANDLE__) \
+ (((__HANDLE__)->Instance->CBR1) & DMA_CBR1_BNDT)
+/**
+ * @}
+ */
+
+
+/* Include DMA HAL Extension module */
+#include "stm32u5xx_hal_dma_ex.h"
+
+
+/* Exported functions ------------------------------------------------------------------------------------------------*/
+/** @defgroup DMA_Exported_Functions DMA Exported Functions
+ * @brief DMA Exported Functions
+ * @{
+ */
+
+/** @defgroup DMA_Exported_Functions_Group1 Initialization and De-Initialization Functions
+ * @brief Initialization and De-Initialization Functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma);
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma);
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Exported_Functions_Group2 I/O Operation Functions
+ * @brief I/O Operation Functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *const hdma,
+ uint32_t SrcAddress,
+ uint32_t DstAddress,
+ uint32_t SrcDataSize);
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *const hdma,
+ uint32_t SrcAddress,
+ uint32_t DstAddress,
+ uint32_t SrcDataSize);
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *const hdma);
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *const hdma);
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *const hdma,
+ HAL_DMA_LevelCompleteTypeDef CompleteLevel,
+ uint32_t Timeout);
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma);
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *const hdma,
+ HAL_DMA_CallbackIDTypeDef CallbackID,
+ void (*const pCallback)(DMA_HandleTypeDef *const _hdma));
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *const hdma,
+ HAL_DMA_CallbackIDTypeDef CallbackID);
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Exported_Functions_Group3 State and Error Functions
+ * @brief State and Error Functions
+ * @{
+ */
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef const *const hdma);
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef const *const hdma);
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Exported_Functions_Group4 DMA Attributes Functions
+ * @brief DMA Attributes Functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *const hdma,
+ uint32_t ChannelAttributes);
+HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *const hdma,
+ uint32_t *const pChannelAttributes);
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const hdma);
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *const hdma,
+ uint32_t *const pLockState);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private constants -------------------------------------------------------------------------------------------------*/
+/** @defgroup DMA_Private_Constants DMA Private Constants
+ * @brief DMA Private Constants
+ * @{
+ */
+#define HAL_TIMEOUT_DMA_ABORT (0x00000005U) /* DMA channel abort timeout 5 milli-second */
+#define HAL_DMA_CHANNEL_START (0x00000050U) /* DMA channel offset */
+#define HAL_DMA_CHANNEL_SIZE (0x00000080U) /* DMA channel size */
+#define HAL_DMA_OFFSET_MASK (0x00000FFFU) /* DMA channel offset mask */
+#define DMA_CHANNEL_ATTR_PRIV_MASK (0x00000010U) /* DMA channel privilege mask */
+#define DMA_CHANNEL_ATTR_SEC_MASK (0x00000020U) /* DMA channel secure mask */
+#define DMA_CHANNEL_ATTR_SEC_SRC_MASK (0x00000040U) /* DMA channel source secure mask */
+#define DMA_CHANNEL_ATTR_SEC_DEST_MASK (0x00000080U) /* DMA channel destination secure mask */
+#define DMA_CHANNEL_ATTR_VALUE_MASK (0x0000000FU) /* DMA channel attributes value mask */
+#define DMA_CHANNEL_ATTR_ITEM_MASK (0x000000F0U) /* DMA channel attributes item mask */
+#define DMA_CHANNEL_BURST_MIN (0x00000001U) /* DMA channel minimum burst size */
+#define DMA_CHANNEL_BURST_MAX (0x00000040U) /* DMA channel maximum burst size */
+/**
+ * @}
+ */
+
+
+/* Private macros ----------------------------------------------------------------------------------------------------*/
+/** @defgroup DMA_Private_Macros DMA Private Macros
+ * @brief DMA Private Macros
+ * @{
+ */
+#define GET_DMA_INSTANCE(__HANDLE__) \
+ ((DMA_TypeDef *)((uint32_t)((__HANDLE__)->Instance) & (~HAL_DMA_OFFSET_MASK)))
+
+#define GET_DMA_CHANNEL(__HANDLE__) \
+ ((((uint32_t)((__HANDLE__)->Instance) & HAL_DMA_OFFSET_MASK) - HAL_DMA_CHANNEL_START) / HAL_DMA_CHANNEL_SIZE)
+
+#define IS_DMA_MODE(MODE) \
+ ((MODE) == DMA_NORMAL)
+
+#define IS_DMA_DIRECTION(DIRECTION) \
+ (((DIRECTION) == DMA_PERIPH_TO_MEMORY) || \
+ ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
+ ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
+
+#define IS_DMA_LEVEL_COMPLETE(LEVEL) \
+ (((LEVEL) == HAL_DMA_FULL_TRANSFER) || \
+ ((LEVEL) == HAL_DMA_HALF_TRANSFER))
+
+#define IS_DMA_SOURCE_INC(INC) \
+ (((INC) == DMA_SINC_FIXED) || \
+ ((INC) == DMA_SINC_INCREMENTED))
+
+#define IS_DMA_DESTINATION_INC(INC) \
+ (((INC) == DMA_DINC_FIXED) || \
+ ((INC) == DMA_DINC_INCREMENTED))
+
+#define IS_DMA_SOURCE_DATA_WIDTH(WIDTH) \
+ (((WIDTH) == DMA_SRC_DATAWIDTH_BYTE) || \
+ ((WIDTH) == DMA_SRC_DATAWIDTH_HALFWORD) || \
+ ((WIDTH) == DMA_SRC_DATAWIDTH_WORD))
+
+#define IS_DMA_DESTINATION_DATA_WIDTH(WIDTH) \
+ (((WIDTH) == DMA_DEST_DATAWIDTH_BYTE) || \
+ ((WIDTH) == DMA_DEST_DATAWIDTH_HALFWORD) || \
+ ((WIDTH) == DMA_DEST_DATAWIDTH_WORD))
+
+#define IS_DMA_BURST_LENGTH(LENGTH) \
+ (((LENGTH) >= DMA_CHANNEL_BURST_MIN) && \
+ ((LENGTH) <= DMA_CHANNEL_BURST_MAX))
+
+#define IS_DMA_PRIORITY(PRIORITY) \
+ (((PRIORITY) == DMA_LOW_PRIORITY_LOW_WEIGHT) || \
+ ((PRIORITY) == DMA_LOW_PRIORITY_MID_WEIGHT) || \
+ ((PRIORITY) == DMA_LOW_PRIORITY_HIGH_WEIGHT) || \
+ ((PRIORITY) == DMA_HIGH_PRIORITY))
+
+#define IS_DMA_TRANSFER_ALLOCATED_PORT(ALLOCATED_PORT) \
+ (((ALLOCATED_PORT) & (~(DMA_CTR1_SAP | DMA_CTR1_DAP))) == 0U)
+
+#define IS_DMA_REQUEST(REQUEST) \
+ (((REQUEST) == DMA_REQUEST_SW) || \
+ ((REQUEST) <= GPDMA1_REQUEST_LPTIM3_UE))
+
+#define IS_DMA_BLOCK_HW_REQUEST(MODE) \
+ (((MODE) == DMA_BREQ_SINGLE_BURST) || \
+ ((MODE) == DMA_BREQ_BLOCK))
+
+#define IS_DMA_TCEM_EVENT_MODE(MODE) \
+ (((MODE) == DMA_TCEM_BLOCK_TRANSFER) || \
+ ((MODE) == DMA_TCEM_REPEATED_BLOCK_TRANSFER) || \
+ ((MODE) == DMA_TCEM_EACH_LL_ITEM_TRANSFER) || \
+ ((MODE) == DMA_TCEM_LAST_LL_ITEM_TRANSFER))
+
+#define IS_DMA_BLOCK_SIZE(SIZE) \
+ (((SIZE) > 0U) && ((SIZE) <= DMA_CBR1_BNDT))
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define IS_DMA_ATTRIBUTES(ATTRIBUTE) \
+ (((ATTRIBUTE) != 0U) && (((ATTRIBUTE) & (~(DMA_CHANNEL_ATTR_VALUE_MASK | DMA_CHANNEL_ATTR_ITEM_MASK))) == 0U) && \
+ (((((ATTRIBUTE) & DMA_CHANNEL_ATTR_ITEM_MASK) >> 4U) | ((ATTRIBUTE) & DMA_CHANNEL_ATTR_VALUE_MASK)) == \
+ (((ATTRIBUTE) & DMA_CHANNEL_ATTR_ITEM_MASK) >> 4U)))
+#else
+#define IS_DMA_ATTRIBUTES(ATTRIBUTE) \
+ (((ATTRIBUTE) == DMA_CHANNEL_PRIV) || \
+ ((ATTRIBUTE) == DMA_CHANNEL_NPRIV))
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define IS_DMA_GLOBAL_ACTIVE_FLAG(INSTANCE, GLOBAL_FLAG) \
+ (((INSTANCE)->SMISR & (GLOBAL_FLAG)))
+#else
+#define IS_DMA_GLOBAL_ACTIVE_FLAG(INSTANCE, GLOBAL_FLAG) \
+ (((INSTANCE)->MISR & (GLOBAL_FLAG)))
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/**
+ * @}
+ */
+
+
+/* Private functions -------------------------------------------------------------------------------------------------*/
+/** @defgroup DMA_Private_Functions DMA Private Functions
+ * @brief DMA Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_DMA_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma2d.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma2d.h
new file mode 100644
index 00000000..c12d8b34
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma2d.h
@@ -0,0 +1,701 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_dma2d.h
+ * @author MCD Application Team
+ * @brief Header file of DMA2D HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_DMA2D_H
+#define STM32U5xx_HAL_DMA2D_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+#if defined (DMA2D)
+
+/** @addtogroup DMA2D DMA2D
+ * @brief DMA2D HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DMA2D_Exported_Types DMA2D Exported Types
+ * @{
+ */
+#define MAX_DMA2D_LAYER 2U /*!< DMA2D maximum number of layers */
+
+/**
+ * @brief DMA2D CLUT Structure definition
+ */
+typedef struct
+{
+ uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/
+
+ uint32_t CLUTColorMode; /*!< Configures the DMA2D CLUT color mode.
+ This parameter can be one value of @ref DMA2D_CLUT_CM. */
+
+ uint32_t Size; /*!< Configures the DMA2D CLUT size.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
+} DMA2D_CLUTCfgTypeDef;
+
+/**
+ * @brief DMA2D Init structure definition
+ */
+typedef struct
+{
+ uint32_t Mode; /*!< Configures the DMA2D transfer mode.
+ This parameter can be one value of @ref DMA2D_Mode. */
+
+ uint32_t ColorMode; /*!< Configures the color format of the output image.
+ This parameter can be one value of @ref DMA2D_Output_Color_Mode. */
+
+ uint32_t OutputOffset; /*!< Specifies the Offset value.
+ This parameter must be a number between
+ Min_Data = 0x0000 and Max_Data = 0x3FFF. */
+ uint32_t AlphaInverted; /*!< Select regular or inverted alpha value for the output pixel format converter.
+ This parameter can be one value of @ref DMA2D_Alpha_Inverted. */
+
+ uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR)
+ for the output pixel format converter.
+ This parameter can be one value of @ref DMA2D_RB_Swap. */
+
+
+ uint32_t BytesSwap; /*!< Select byte regular mode or bytes swap mode (two by two).
+ This parameter can be one value of @ref DMA2D_Bytes_Swap. */
+
+ uint32_t LineOffsetMode; /*!< Configures how is expressed the line offset for the foreground, background and output.
+ This parameter can be one value of @ref DMA2D_Line_Offset_Mode. */
+
+} DMA2D_InitTypeDef;
+
+
+/**
+ * @brief DMA2D Layer structure definition
+ */
+typedef struct
+{
+ uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset.
+ This parameter must be a number between
+ Min_Data = 0x0000 and Max_Data = 0x3FFF. */
+
+ uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode.
+ This parameter can be one value of @ref DMA2D_Input_Color_Mode. */
+
+ uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode.
+ This parameter can be one value of @ref DMA2D_Alpha_Mode. */
+
+ uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value
+ in case of A8 or A4 color mode.
+ This parameter must be a number between Min_Data = 0x00
+ and Max_Data = 0xFF except for the color modes detailed below.
+ @note In case of A8 or A4 color mode (ARGB),
+ this parameter must be a number between
+ Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where
+ - InputAlpha[24:31] is the alpha value ALPHA[0:7]
+ - InputAlpha[16:23] is the red value RED[0:7]
+ - InputAlpha[8:15] is the green value GREEN[0:7]
+ - InputAlpha[0:7] is the blue value BLUE[0:7]. */
+ uint32_t AlphaInverted; /*!< Select regular or inverted alpha value.
+ This parameter can be one value of @ref DMA2D_Alpha_Inverted. */
+
+ uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR).
+ This parameter can be one value of @ref DMA2D_RB_Swap. */
+
+
+} DMA2D_LayerCfgTypeDef;
+
+/**
+ * @brief HAL DMA2D State structures definition
+ */
+typedef enum
+{
+ HAL_DMA2D_STATE_RESET = 0x00U, /*!< DMA2D not yet initialized or disabled */
+ HAL_DMA2D_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
+ HAL_DMA2D_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
+ HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
+ HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */
+ HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */
+} HAL_DMA2D_StateTypeDef;
+
+/**
+ * @brief DMA2D handle Structure definition
+ */
+typedef struct __DMA2D_HandleTypeDef
+{
+ DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */
+
+ DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */
+
+ void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer complete callback. */
+
+ void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer error callback. */
+
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+ void (* LineEventCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D line event callback. */
+
+ void (* CLUTLoadingCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D CLUT loading completion callback */
+
+ void (* MspInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp Init callback. */
+
+ void (* MspDeInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp DeInit callback. */
+
+#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
+
+ DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */
+
+ HAL_LockTypeDef Lock; /*!< DMA2D lock. */
+
+ __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */
+
+ __IO uint32_t ErrorCode; /*!< DMA2D error code. */
+} DMA2D_HandleTypeDef;
+
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL DMA2D Callback pointer definition
+ */
+typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef *hdma2d); /*!< Pointer to a DMA2D common callback function */
+#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants
+ * @{
+ */
+
+/** @defgroup DMA2D_Error_Code DMA2D Error Code
+ * @{
+ */
+#define HAL_DMA2D_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_DMA2D_ERROR_TE 0x00000001U /*!< Transfer error */
+#define HAL_DMA2D_ERROR_CE 0x00000002U /*!< Configuration error */
+#define HAL_DMA2D_ERROR_CAE 0x00000004U /*!< CLUT access error */
+#define HAL_DMA2D_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+#define HAL_DMA2D_ERROR_INVALID_CALLBACK 0x00000040U /*!< Invalid callback error */
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Mode DMA2D Mode
+ * @{
+ */
+#define DMA2D_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */
+#define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */
+#define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */
+#define DMA2D_R2M (DMA2D_CR_MODE_1 | DMA2D_CR_MODE_0) /*!< DMA2D register to memory transfer mode */
+#define DMA2D_M2M_BLEND_FG DMA2D_CR_MODE_2 /*!< DMA2D memory to memory with blending transfer mode and fixed color FG */
+#define DMA2D_M2M_BLEND_BG (DMA2D_CR_MODE_2 | DMA2D_CR_MODE_0) /*!< DMA2D memory to memory with blending transfer mode and fixed color BG */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode
+ * @{
+ */
+#define DMA2D_OUTPUT_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D color mode */
+#define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 DMA2D color mode */
+#define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 DMA2D color mode */
+#define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */
+#define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 DMA2D color mode */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode
+ * @{
+ */
+#define DMA2D_INPUT_ARGB8888 0x00000000U /*!< ARGB8888 color mode */
+#define DMA2D_INPUT_RGB888 0x00000001U /*!< RGB888 color mode */
+#define DMA2D_INPUT_RGB565 0x00000002U /*!< RGB565 color mode */
+#define DMA2D_INPUT_ARGB1555 0x00000003U /*!< ARGB1555 color mode */
+#define DMA2D_INPUT_ARGB4444 0x00000004U /*!< ARGB4444 color mode */
+#define DMA2D_INPUT_L8 0x00000005U /*!< L8 color mode */
+#define DMA2D_INPUT_AL44 0x00000006U /*!< AL44 color mode */
+#define DMA2D_INPUT_AL88 0x00000007U /*!< AL88 color mode */
+#define DMA2D_INPUT_L4 0x00000008U /*!< L4 color mode */
+#define DMA2D_INPUT_A8 0x00000009U /*!< A8 color mode */
+#define DMA2D_INPUT_A4 0x0000000AU /*!< A4 color mode */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode
+ * @{
+ */
+#define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */
+#define DMA2D_REPLACE_ALPHA 0x00000001U /*!< Replace original alpha channel value by programmed alpha value */
+#define DMA2D_COMBINE_ALPHA 0x00000002U /*!< Replace original alpha channel value by programmed alpha value
+ with original alpha channel value */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Alpha_Inverted DMA2D Alpha Inversion
+ * @{
+ */
+#define DMA2D_REGULAR_ALPHA 0x00000000U /*!< No modification of the alpha channel value */
+#define DMA2D_INVERTED_ALPHA 0x00000001U /*!< Invert the alpha channel value */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap
+ * @{
+ */
+#define DMA2D_RB_REGULAR 0x00000000U /*!< Select regular mode (RGB or ARGB) */
+#define DMA2D_RB_SWAP 0x00000001U /*!< Select swap mode (BGR or ABGR) */
+/**
+ * @}
+ */
+
+
+
+/** @defgroup DMA2D_Line_Offset_Mode DMA2D Line Offset Mode
+ * @{
+ */
+#define DMA2D_LOM_PIXELS 0x00000000U /*!< Line offsets expressed in pixels */
+#define DMA2D_LOM_BYTES DMA2D_CR_LOM /*!< Line offsets expressed in bytes */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Bytes_Swap DMA2D Bytes Swap
+ * @{
+ */
+#define DMA2D_BYTES_REGULAR 0x00000000U /*!< Bytes in regular order in output FIFO */
+#define DMA2D_BYTES_SWAP DMA2D_OPFCCR_SB /*!< Bytes are swapped two by two in output FIFO */
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode
+ * @{
+ */
+#define DMA2D_CCM_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D CLUT color mode */
+#define DMA2D_CCM_RGB888 0x00000001U /*!< RGB888 DMA2D CLUT color mode */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Interrupts DMA2D Interrupts
+ * @{
+ */
+#define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */
+#define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */
+#define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */
+#define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */
+#define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */
+#define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Flags DMA2D Flags
+ * @{
+ */
+#define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */
+#define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */
+#define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */
+#define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */
+#define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */
+/**
+ * @}
+ */
+
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL DMA2D common Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_DMA2D_MSPINIT_CB_ID = 0x00U, /*!< DMA2D MspInit callback ID */
+ HAL_DMA2D_MSPDEINIT_CB_ID = 0x01U, /*!< DMA2D MspDeInit callback ID */
+ HAL_DMA2D_TRANSFERCOMPLETE_CB_ID = 0x02U, /*!< DMA2D transfer complete callback ID */
+ HAL_DMA2D_TRANSFERERROR_CB_ID = 0x03U, /*!< DMA2D transfer error callback ID */
+ HAL_DMA2D_LINEEVENT_CB_ID = 0x04U, /*!< DMA2D line event callback ID */
+ HAL_DMA2D_CLUTLOADINGCPLT_CB_ID = 0x05U, /*!< DMA2D CLUT loading completion callback ID */
+} HAL_DMA2D_CallbackIDTypeDef;
+#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
+
+
+/**
+ * @}
+ */
+/* Exported macros ------------------------------------------------------------*/
+/** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros
+ * @{
+ */
+
+/** @brief Reset DMA2D handle state
+ * @param __HANDLE__ specifies the DMA2D handle.
+ * @retval None
+ */
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ }while(0)
+#else
+#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
+#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
+
+
+/**
+ * @brief Enable the DMA2D.
+ * @param __HANDLE__ DMA2D handle
+ * @retval None.
+ */
+#define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
+
+
+/* Interrupt & Flag management */
+/**
+ * @brief Get the DMA2D pending flags.
+ * @param __HANDLE__ DMA2D handle
+ * @param __FLAG__ flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg DMA2D_FLAG_CE: Configuration error flag
+ * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
+ * @arg DMA2D_FLAG_CAE: CLUT access error flag
+ * @arg DMA2D_FLAG_TW: Transfer Watermark flag
+ * @arg DMA2D_FLAG_TC: Transfer complete flag
+ * @arg DMA2D_FLAG_TE: Transfer error flag
+ * @retval The state of FLAG.
+ */
+#define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
+
+/**
+ * @brief Clear the DMA2D pending flags.
+ * @param __HANDLE__ DMA2D handle
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DMA2D_FLAG_CE: Configuration error flag
+ * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
+ * @arg DMA2D_FLAG_CAE: CLUT access error flag
+ * @arg DMA2D_FLAG_TW: Transfer Watermark flag
+ * @arg DMA2D_FLAG_TC: Transfer complete flag
+ * @arg DMA2D_FLAG_TE: Transfer error flag
+ * @retval None
+ */
+#define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
+
+/**
+ * @brief Enable the specified DMA2D interrupts.
+ * @param __HANDLE__ DMA2D handle
+ * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg DMA2D_IT_CE: Configuration error interrupt mask
+ * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
+ * @arg DMA2D_IT_CAE: CLUT access error interrupt mask
+ * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
+ * @arg DMA2D_IT_TC: Transfer complete interrupt mask
+ * @arg DMA2D_IT_TE: Transfer error interrupt mask
+ * @retval None
+ */
+#define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the specified DMA2D interrupts.
+ * @param __HANDLE__ DMA2D handle
+ * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be disabled.
+ * This parameter can be any combination of the following values:
+ * @arg DMA2D_IT_CE: Configuration error interrupt mask
+ * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
+ * @arg DMA2D_IT_CAE: CLUT access error interrupt mask
+ * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
+ * @arg DMA2D_IT_TC: Transfer complete interrupt mask
+ * @arg DMA2D_IT_TE: Transfer error interrupt mask
+ * @retval None
+ */
+#define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified DMA2D interrupt source is enabled or not.
+ * @param __HANDLE__ DMA2D handle
+ * @param __INTERRUPT__ specifies the DMA2D interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg DMA2D_IT_CE: Configuration error interrupt mask
+ * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
+ * @arg DMA2D_IT_CAE: CLUT access error interrupt mask
+ * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
+ * @arg DMA2D_IT_TC: Transfer complete interrupt mask
+ * @arg DMA2D_IT_TE: Transfer error interrupt mask
+ * @retval The state of INTERRUPT source.
+ */
+#define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions
+ * @{
+ */
+
+/** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions *******************************/
+HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d);
+void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d);
+void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d);
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID,
+ pDMA2D_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
+ uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
+ uint32_t DstAddress, uint32_t Width, uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
+ uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
+ uint32_t DstAddress, uint32_t Width, uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg,
+ uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg,
+ uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
+void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
+void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d);
+void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d);
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+
+/* Peripheral Control functions *************************************************/
+HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
+HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime);
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
+ * @{
+ */
+
+/* Peripheral State functions ***************************************************/
+HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
+uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+
+/** @addtogroup DMA2D_Private_Constants DMA2D Private Constants
+ * @{
+ */
+
+/** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark
+ * @{
+ */
+#define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW /*!< DMA2D maximum line watermark */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Color_Value DMA2D Color Value
+ * @{
+ */
+#define DMA2D_COLOR_VALUE 0x000000FFU /*!< Color value mask */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers
+ * @{
+ */
+#define DMA2D_MAX_LAYER 2U /*!< DMA2D maximum number of layers */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Layers DMA2D Layers
+ * @{
+ */
+#define DMA2D_BACKGROUND_LAYER 0x00000000U /*!< DMA2D Background Layer (layer 0) */
+#define DMA2D_FOREGROUND_LAYER 0x00000001U /*!< DMA2D Foreground Layer (layer 1) */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Offset DMA2D Offset
+ * @{
+ */
+#define DMA2D_OFFSET DMA2D_FGOR_LO /*!< maximum Line Offset */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Size DMA2D Size
+ * @{
+ */
+#define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D maximum number of pixels per line */
+#define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D maximum number of lines */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size
+ * @{
+ */
+#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8U) /*!< DMA2D maximum CLUT size */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMA2D_Private_Macros DMA2D Private Macros
+ * @{
+ */
+#define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER)\
+ || ((LAYER) == DMA2D_FOREGROUND_LAYER))
+
+#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
+ ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M) || \
+ ((MODE) == DMA2D_M2M_BLEND_FG) || ((MODE) == DMA2D_M2M_BLEND_BG))
+
+#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || \
+ ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \
+ ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || \
+ ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
+ ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))
+
+#define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE)
+#define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE)
+#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
+#define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
+
+#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || \
+ ((INPUT_CM) == DMA2D_INPUT_RGB888) || \
+ ((INPUT_CM) == DMA2D_INPUT_RGB565) || \
+ ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
+ ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || \
+ ((INPUT_CM) == DMA2D_INPUT_L8) || \
+ ((INPUT_CM) == DMA2D_INPUT_AL44) || \
+ ((INPUT_CM) == DMA2D_INPUT_AL88) || \
+ ((INPUT_CM) == DMA2D_INPUT_L4) || \
+ ((INPUT_CM) == DMA2D_INPUT_A8) || \
+ ((INPUT_CM) == DMA2D_INPUT_A4))
+
+#define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
+ ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \
+ ((AlphaMode) == DMA2D_COMBINE_ALPHA))
+
+#define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \
+ ((Alpha_Inverted) == DMA2D_INVERTED_ALPHA))
+
+#define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \
+ ((RB_Swap) == DMA2D_RB_SWAP))
+
+#define IS_DMA2D_LOM_MODE(LOM) (((LOM) == DMA2D_LOM_PIXELS) || \
+ ((LOM) == DMA2D_LOM_BYTES))
+
+#define IS_DMA2D_BYTES_SWAP(BYTES_SWAP) (((BYTES_SWAP) == DMA2D_BYTES_REGULAR) || \
+ ((BYTES_SWAP) == DMA2D_BYTES_SWAP))
+
+
+#define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
+#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
+#define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)
+#define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
+ ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
+ ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
+#define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
+ ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
+ ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (DMA2D) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_DMA2D_H */
+
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma_ex.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma_ex.h
new file mode 100644
index 00000000..41e7026f
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma_ex.h
@@ -0,0 +1,686 @@
+/**
+ **********************************************************************************************************************
+ * @file stm32u5xx_hal_dma_ex.h
+ * @author MCD Application Team
+ * @brief Header file of DMA HAL extension module.
+ **********************************************************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ **********************************************************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/
+#ifndef STM32U5xx_HAL_DMA_EX_H
+#define STM32U5xx_HAL_DMA_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ----------------------------------------------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DMAEx
+ * @{
+ */
+
+/* Exported types ----------------------------------------------------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
+ * @brief DMAEx Exported types
+ * @{
+ */
+
+/**
+ * @brief DMAEx Data Handling Configuration Structure Definition.
+ */
+typedef struct
+{
+ uint32_t DataExchange; /*!< Specifies the DMA channel data exchange mode.
+ This parameter can be a value of @ref DMAEx_Data_Exchange */
+
+ uint32_t DataAlignment; /*!< Specifies the DMA channel data padding and alignment mode
+ This parameter can be a value of @ref DMAEx_Data_Alignment */
+
+} DMA_DataHandlingConfTypeDef;
+
+/**
+ * @brief DMAEx Trigger Configuration Structure Definition.
+ */
+typedef struct
+{
+ uint32_t TriggerMode; /*!< Specifies the DMA channel trigger mode.
+ This parameter can be a value of @ref DMAEx_Trigger_Mode */
+
+ uint32_t TriggerPolarity; /*!< Specifies the DMA channel trigger event polarity.
+ This parameter can be a value of @ref DMAEx_Trigger_Polarity */
+
+ uint32_t TriggerSelection; /*!< Specifies the DMA channel trigger event selection.
+ This parameter can be a value of @ref DMAEx_Trigger_Selection */
+
+} DMA_TriggerConfTypeDef;
+
+/**
+ * @brief DMAEx Repeated Block Configuration Structure Definition.
+ */
+typedef struct
+{
+ uint32_t RepeatCount; /*!< Specifies the DMA channel repeat count (the number of repetitions of block).
+ This parameter can be a value between 1 and 2048 */
+
+ int32_t SrcAddrOffset; /*!< Specifies the DMA channel single/burst source address offset :
+ This parameter can be a value between -8191 and 8191.
+ * If source address offset > 0 => Increment the source address by offset from where
+ the last single/burst transfer ends.
+ * If source address offset < 0 => Decrement the source address by offset from where
+ the last single/burst transfer ends.
+ * If source address offset == 0 => The next single/burst source address starts from
+ where the last transfer ends */
+
+ int32_t DestAddrOffset; /*!< Specifies the DMA channel single/burst destination address offset signed value :
+ This parameter can be a value between -8191 and 8191.
+ * If destination address offset > 0 => Increment the destination address by offset
+ from where the last single/burst transfer ends.
+ * If destination address offset < 0 => Decrement the destination address by offset
+ from where the last single/burst transfer ends.
+ * If destination address offset == 0 => The next single/burst destination address
+ starts from where the last transfer ends. */
+
+ int32_t BlkSrcAddrOffset; /*!< Specifies the DMA channel block source address offset signed value :
+ This parameter can be a value between -65535 and 65535.
+ * If block source address offset > 0 => Increment the block source address by offset
+ from where the last block ends.
+ * If block source address offset < 0 => Decrement the next block source address by
+ offset from where the last block ends.
+ * If block source address offset == 0 => the next block source address starts from
+ where the last block ends */
+
+ int32_t BlkDestAddrOffset; /*!< Specifies the DMA channel block destination address offset signed value :
+ This parameter can be a value between -65535 and 65535.
+ * If block destination address offset > 0 => Increment the block destination address
+ by offset from where the last block ends.
+ * If block destination address offset < 0 => Decrement the next block destination
+ address by offset from where the last block ends.
+ * If block destination address offset == 0 => the next block destination address
+ starts from where the last block ends */
+
+} DMA_RepeatBlockConfTypeDef;
+
+/**
+ * @brief DMAEx Queue State Enumeration Definition.
+ */
+typedef enum
+{
+ HAL_DMA_QUEUE_STATE_RESET = 0x00U, /*!< DMA queue empty */
+ HAL_DMA_QUEUE_STATE_READY = 0x01U, /*!< DMA queue ready for use */
+ HAL_DMA_QUEUE_STATE_BUSY = 0x02U /*!< DMA queue execution on going */
+
+} HAL_DMA_QStateTypeDef;
+
+/**
+ * @brief DMAEx Linked-List Node Configuration Structure Definition.
+ */
+typedef struct
+{
+ uint32_t NodeType; /*!< Specifies the DMA channel node type.
+ This parameter can be a value of @ref DMAEx_Node_Type */
+
+ DMA_InitTypeDef Init; /*!< Specifies the DMA channel basic configuration */
+
+ DMA_DataHandlingConfTypeDef DataHandlingConfig; /*!< Specifies the DMA channel data handling channel configuration */
+
+ DMA_TriggerConfTypeDef TriggerConfig; /*!< Specifies the DMA channel trigger configuration */
+
+ DMA_RepeatBlockConfTypeDef RepeatBlockConfig; /*!< Specifies the DMA channel repeated block configuration */
+
+ uint32_t SrcAddress; /*!< Specifies the source memory address */
+ uint32_t DstAddress; /*!< Specifies the destination memory address */
+ uint32_t DataSize; /*!< Specifies the source data size in bytes */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ uint32_t SrcSecure; /*!< Specifies the source security attribute */
+ uint32_t DestSecure; /*!< Specifies the destination security attribute */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+} DMA_NodeConfTypeDef;
+
+/**
+ * @brief DMAEx Linked-List Node Structure Definition.
+ */
+typedef struct
+{
+ uint32_t LinkRegisters[8U]; /*!< Physical Node register description */
+ uint32_t NodeInfo; /*!< Node information */
+
+} DMA_NodeTypeDef;
+
+/**
+ * @brief DMAEx Linked-List Queue Structure Definition.
+ */
+typedef struct __DMA_QListTypeDef
+{
+ DMA_NodeTypeDef *Head; /*!< Specifies the queue head node */
+
+ DMA_NodeTypeDef *FirstCircularNode; /*!< Specifies the queue first circular node */
+
+ uint32_t NodeNumber; /*!< Specifies the queue node number */
+
+ __IO HAL_DMA_QStateTypeDef State; /*!< Specifies the queue state */
+
+ __IO uint32_t ErrorCode; /*!< Specifies the queue error code */
+
+ __IO uint32_t Type; /*!< Specifies whether the queue is static or dynamic */
+
+} DMA_QListTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants ------------------------------------------------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
+ * @brief DMAEx Exported Constants
+ * @{
+ */
+
+/** @defgroup Queue_Error_Codes Queue Error Codes
+ * @brief Queue Error Codes
+ * @{
+ */
+#define HAL_DMA_QUEUE_ERROR_NONE (0x00U) /*!< No error */
+#define HAL_DMA_QUEUE_ERROR_BUSY (0x01U) /*!< Error busy */
+#define HAL_DMA_QUEUE_ERROR_EMPTY (0x02U) /*!< Error unallowed operation for empty queue */
+#define HAL_DMA_QUEUE_ERROR_UNSUPPORTED (0x03U) /*!< Error unsupported feature */
+#define HAL_DMA_QUEUE_ERROR_INVALIDTYPE (0x04U) /*!< Error incompatible node type or circular initialization
+ and queue circular types are incompatible */
+#define HAL_DMA_QUEUE_ERROR_OUTOFRANGE (0x05U) /*!< Error out of range node memory */
+#define HAL_DMA_QUEUE_ERROR_NOTFOUND (0x06U) /*!< Error node not found in queue */
+/**
+ * @}
+ */
+
+/** @defgroup DMAEx_LinkedList_Mode DMAEx LinkedList Mode
+ * @brief DMAEx LinkedList Mode
+ * @{
+ */
+#define DMA_LINKEDLIST_NORMAL DMA_LINKEDLIST /*!< Linear linked-list DMA channel transfer */
+#define DMA_LINKEDLIST_CIRCULAR (DMA_LINKEDLIST | (0x01U)) /*!< Circular linked-list DMA channel transfer */
+/**
+ * @}
+ */
+
+/** @defgroup DMAEx_Data_Alignment DMAEx Data Alignment
+ * @brief DMAEx Data Alignment
+ * @{
+ */
+#define DMA_DATA_RIGHTALIGN_ZEROPADDED 0x00000000U /*!< If source data width < destination data width
+ => Right aligned padded with 0 up to destination data
+ width */
+#define DMA_DATA_RIGHTALIGN_LEFTTRUNC 0x00000000U /*!< If source data width > destination data width
+ => Right aligned left Truncated down to destination
+ data width */
+#define DMA_DATA_RIGHTALIGN_SIGNEXT DMA_CTR1_PAM_0 /*!< If source data width < destination data width
+ => Right Aligned padded with sign extended up to
+ destination data width */
+#define DMA_DATA_LEFTALIGN_RIGHTTRUNC DMA_CTR1_PAM_0 /*!< If source data width > destination data width
+ => Left Aligned Right Truncated down to the
+ destination data width */
+#define DMA_DATA_PACK DMA_CTR1_PAM_1 /*!< If source data width < destination data width
+ => Packed at the destination data width
+ (Available only for GPDMA) */
+#define DMA_DATA_UNPACK DMA_CTR1_PAM_1 /*!< If source data width > destination data width
+ => Unpacked at the destination data width
+ (Available only for GPDMA) */
+/**
+ * @}
+ */
+
+/** @defgroup DMAEx_Data_Exchange DMAEx Data Exchange
+ * @brief DMAEx Data Exchange
+ * @{
+ */
+#define DMA_EXCHANGE_NONE 0x00000000U /*!< No data exchange */
+#define DMA_EXCHANGE_DEST_BYTE DMA_CTR1_DBX /*!< Destination Byte exchange when destination data width is > Byte */
+#define DMA_EXCHANGE_DEST_HALFWORD DMA_CTR1_DHX /*!< Destination Half-Word exchange when destination data width is > Half-Word */
+#define DMA_EXCHANGE_SRC_BYTE DMA_CTR1_SBX /*!< Source Byte endianness exchange when source data width is word */
+/**
+ * @}
+ */
+
+/** @defgroup DMAEx_Trigger_Polarity DMAEx Trigger Polarity
+ * @brief DMAEx Trigger Polarity
+ * @{
+ */
+#define DMA_TRIG_POLARITY_MASKED 0x00000000U /*!< No trigger of the selected DMA request. Masked trigger event */
+#define DMA_TRIG_POLARITY_RISING DMA_CTR2_TRIGPOL_0 /*!< Trigger of the selected DMA request on the rising edge of the selected trigger event input */
+#define DMA_TRIG_POLARITY_FALLING DMA_CTR2_TRIGPOL_1 /*!< Trigger of the selected DMA request on the falling edge of the selected trigger event input */
+/**
+ * @}
+ */
+
+/** @defgroup DMAEx_Trigger_Mode DMAEx Trigger Mode
+ * @brief DMAEx Trigger Mode
+ * @{
+ */
+#define DMA_TRIGM_BLOCK_TRANSFER 0x00000000U /*!< A block transfer is conditioned by (at least) one hit trigger */
+#define DMA_TRIGM_REPEATED_BLOCK_TRANSFER DMA_CTR2_TRIGM_0 /*!< A repeated block transfer is conditioned by (at least) one hit trigger */
+#define DMA_TRIGM_LLI_LINK_TRANSFER DMA_CTR2_TRIGM_1 /*!< A LLI link transfer is conditioned by (at least) one hit trigger */
+#define DMA_TRIGM_SINGLE_BURST_TRANSFER DMA_CTR2_TRIGM /*!< A single/burst transfer is conditioned by (at least) one hit trigger */
+/**
+ * @}
+ */
+
+/** @defgroup DMAEx_Trigger_Selection DMAEx Trigger Selection
+ * @brief DMAEx Trigger Selection
+ * @{
+ */
+/* GPDMA1 triggers */
+#define GPDMA1_TRIGGER_EXTI_LINE0 (0U) /*!< GPDMA1 HW Trigger signal is EXTI_LINE0 */
+#define GPDMA1_TRIGGER_EXTI_LINE1 (1U) /*!< GPDMA1 HW Trigger signal is EXTI_LINE1 */
+#define GPDMA1_TRIGGER_EXTI_LINE2 (2U) /*!< GPDMA1 HW Trigger signal is EXTI_LINE2 */
+#define GPDMA1_TRIGGER_EXTI_LINE3 (3U) /*!< GPDMA1 HW Trigger signal is EXTI_LINE3 */
+#define GPDMA1_TRIGGER_EXTI_LINE4 (4U) /*!< GPDMA1 HW Trigger signal is EXTI_LINE4 */
+#define GPDMA1_TRIGGER_EXTI_LINE5 (5U) /*!< GPDMA1 HW Trigger signal is EXTI_LINE5 */
+#define GPDMA1_TRIGGER_EXTI_LINE6 (6U) /*!< GPDMA1 HW Trigger signal is EXTI_LINE6 */
+#define GPDMA1_TRIGGER_EXTI_LINE7 (7U) /*!< GPDMA1 HW Trigger signal is EXTI_LINE7 */
+#define GPDMA1_TRIGGER_TAMP_TRG1 (8U) /*!< GPDMA1 HW Trigger signal is TAMP_TRG1 */
+#define GPDMA1_TRIGGER_TAMP_TRG2 (9U) /*!< GPDMA1 HW Trigger signal is TAMP_TRG2 */
+#define GPDMA1_TRIGGER_TAMP_TRG3 (10U) /*!< GPDMA1 HW Trigger signal is TAMP_TRG3 */
+#define GPDMA1_TRIGGER_LPTIM1_CH1 (11U) /*!< GPDMA1 HW Trigger signal is LPTIM1_CH1 */
+#define GPDMA1_TRIGGER_LPTIM1_CH2 (12U) /*!< GPDMA1 HW Trigger signal is LPTIM1_CH2 */
+#define GPDMA1_TRIGGER_LPTIM2_CH1 (13U) /*!< GPDMA1 HW Trigger signal is LPTIM2_CH1 */
+#define GPDMA1_TRIGGER_LPTIM2_CH2 (14U) /*!< GPDMA1 HW Trigger signal is LPTIM2_CH2 */
+#define GPDMA1_TRIGGER_LPTIM4_OUT (15U) /*!< GPDMA1 HW Trigger signal is LPTIM4_OUT */
+#define GPDMA1_TRIGGER_COMP1_OUT (16U) /*!< GPDMA1 HW Trigger signal is COMP1_OUT */
+#define GPDMA1_TRIGGER_COMP2_OUT (17U) /*!< GPDMA1 HW Trigger signal is COMP2_OUT */
+#define GPDMA1_TRIGGER_RTC_ALRA_TRG (18U) /*!< GPDMA1 HW Trigger signal is RTC_ALRA_TRG */
+#define GPDMA1_TRIGGER_RTC_ALRB_TRG (19U) /*!< GPDMA1 HW Trigger signal is RTC_ALRB_TRG */
+#define GPDMA1_TRIGGER_RTC_WUT_TRG (20U) /*!< GPDMA1 HW Trigger signal is RTC_WUT_TRG */
+#define GPDMA1_TRIGGER_GPDMA1_CH0_TCF (22U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */
+#define GPDMA1_TRIGGER_GPDMA1_CH1_TCF (23U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */
+#define GPDMA1_TRIGGER_GPDMA1_CH2_TCF (24U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH2_TCF */
+#define GPDMA1_TRIGGER_GPDMA1_CH3_TCF (25U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH3_TCF */
+#define GPDMA1_TRIGGER_GPDMA1_CH4_TCF (26U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */
+#define GPDMA1_TRIGGER_GPDMA1_CH5_TCF (27U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */
+#define GPDMA1_TRIGGER_GPDMA1_CH6_TCF (28U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */
+#define GPDMA1_TRIGGER_GPDMA1_CH7_TCF (29U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */
+#define GPDMA1_TRIGGER_GPDMA1_CH8_TCF (30U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH8_TCF */
+#define GPDMA1_TRIGGER_GPDMA1_CH9_TCF (31U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH9_TCF */
+#define GPDMA1_TRIGGER_GPDMA1_CH10_TCF (32U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH10_TCF */
+#define GPDMA1_TRIGGER_GPDMA1_CH11_TCF (33U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH11_TCF */
+#define GPDMA1_TRIGGER_GPDMA1_CH12_TCF (34U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH12_TCF */
+#define GPDMA1_TRIGGER_GPDMA1_CH13_TCF (35U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH13_TCF */
+#define GPDMA1_TRIGGER_GPDMA1_CH14_TCF (36U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH14_TCF */
+#define GPDMA1_TRIGGER_GPDMA1_CH15_TCF (37U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH15_TCF */
+#define GPDMA1_TRIGGER_LPDMA1_CH0_TCF (38U) /*!< GPDMA1 HW Trigger signal is LPDMA1_CH0_TCF */
+#define GPDMA1_TRIGGER_LPDMA1_CH1_TCF (39U) /*!< GPDMA1 HW Trigger signal is LPDMA1_CH1_TCF */
+#define GPDMA1_TRIGGER_LPDMA1_CH2_TCF (40U) /*!< GPDMA1 HW Trigger signal is LPDMA1_CH2_TCF */
+#define GPDMA1_TRIGGER_LPDMA1_CH3_TCF (41U) /*!< GPDMA1 HW Trigger signal is LPDMA1_CH3_TCF */
+#define GPDMA1_TRIGGER_TIM2_TRGO (42U) /*!< GPDMA1 HW Trigger signal is TIM2_TRGO */
+#define GPDMA1_TRIGGER_TIM15_TRGO (43U) /*!< GPDMA1 HW Trigger signal is TIM15_TRGO */
+#define GPDMA1_TRIGGER_ADC4_AWD1 (57U) /*!< GPDMA1 HW Trigger signal is ADC4_AWD1 */
+#define GPDMA1_TRIGGER_ADC1_AWD1 (58U) /*!< GPDMA1 HW Trigger signal is ADC1_AWD1 */
+
+/* LPDMA1 triggers */
+#define LPDMA1_TRIGGER_EXTI_LINE0 (0U) /*!< LPDMA1 HW Trigger signal is EXTI_LINE0 */
+#define LPDMA1_TRIGGER_EXTI_LINE1 (1U) /*!< LPDMA1 HW Trigger signal is EXTI_LINE1 */
+#define LPDMA1_TRIGGER_EXTI_LINE2 (2U) /*!< LPDMA1 HW Trigger signal is EXTI_LINE2 */
+#define LPDMA1_TRIGGER_EXTI_LINE3 (3U) /*!< LPDMA1 HW Trigger signal is EXTI_LINE3 */
+#define LPDMA1_TRIGGER_EXTI_LINE4 (4U) /*!< LPDMA1 HW Trigger signal is EXTI_LINE4 */
+#define LPDMA1_TRIGGER_TAMP_TRG1 (5U) /*!< LPDMA1 HW Trigger signal is TAMP_TRG1 */
+#define LPDMA1_TRIGGER_TAMP_TRG2 (6U) /*!< LPDMA1 HW Trigger signal is TAMP_TRG2 */
+#define LPDMA1_TRIGGER_TAMP_TRG3 (7U) /*!< LPDMA1 HW Trigger signal is TAMP_TRG3 */
+#define LPDMA1_TRIGGER_LPTIM1_CH1 (8U) /*!< LPDMA1 HW Trigger signal is LPTIM1_CH1 */
+#define LPDMA1_TRIGGER_LPTIM1_CH2 (9U) /*!< LPDMA1 HW Trigger signal is LPTIM1_CH2 */
+#define LPDMA1_TRIGGER_LPTIM3_CH1 (10U) /*!< LPDMA1 HW Trigger signal is LPTIM3_CH1 */
+#define LPDMA1_TRIGGER_LPTIM4_OUT (11U) /*!< LPDMA1 HW Trigger signal is LPTIM4_OUT */
+#define LPDMA1_TRIGGER_COMP1_OUT (12U) /*!< LPDMA1 HW Trigger signal is COMP1_OUT */
+#define LPDMA1_TRIGGER_COMP2_OUT (13U) /*!< LPDMA1 HW Trigger signal is COMP2_OUT */
+#define LPDMA1_TRIGGER_RTC_ALRA_TRG (14U) /*!< LPDMA1 HW Trigger signal is RTC_ALRA_TRG */
+#define LPDMA1_TRIGGER_RTC_ALRB_TRG (15U) /*!< LPDMA1 HW Trigger signal is RTC_ALRB_TRG */
+#define LPDMA1_TRIGGER_RTC_WUT_TRG (16U) /*!< LPDMA1 HW Trigger signal is RTC_WUT_TRG */
+#define LPDMA1_TRIGGER_ADC4_AWD1 (17U) /*!< LPDMA1 HW Trigger signal is ADC4_AWD1 */
+#define LPDMA1_TRIGGER_LPDMA1_CH0_TCF (18U) /*!< LPDMA1 HW Trigger signal is LPDMA1_CH0_TCF */
+#define LPDMA1_TRIGGER_LPDMA1_CH1_TCF (19U) /*!< LPDMA1 HW Trigger signal is LPDMA1_CH1_TCF */
+#define LPDMA1_TRIGGER_LPDMA1_CH2_TCF (20U) /*!< LPDMA1 HW Trigger signal is LPDMA1_CH2_TCF */
+#define LPDMA1_TRIGGER_LPDMA1_CH3_TCF (21U) /*!< LPDMA1 HW Trigger signal is LPDMA1_CH3_TCF */
+#define LPDMA1_TRIGGER_GPDMA1_CH0_TCF (22U) /*!< LPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */
+#define LPDMA1_TRIGGER_GPDMA1_CH1_TCF (23U) /*!< LPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */
+#define LPDMA1_TRIGGER_GPDMA1_CH4_TCF (24U) /*!< LPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */
+#define LPDMA1_TRIGGER_GPDMA1_CH5_TCF (25U) /*!< LPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */
+#define LPDMA1_TRIGGER_GPDMA1_CH6_TCF (26U) /*!< LPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */
+#define LPDMA1_TRIGGER_GPDMA1_CH7_TCF (27U) /*!< LPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */
+#define LPDMA1_TRIGGER_GPDMA1_CH12_TCF (28U) /*!< LPDMA1 HW Trigger signal is GPDMA1_CH12_TCF */
+#define LPDMA1_TRIGGER_GPDMA1_CH13_TCF (29U) /*!< LPDMA1 HW Trigger signal is GPDMA1_CH13_TCF */
+#define LPDMA1_TRIGGER_TIM2_TRGO (30U) /*!< LPDMA1 HW Trigger signal is TIM2_TRGO */
+#define LPDMA1_TRIGGER_TIM15_TRGO (31U) /*!< LPDMA1 HW Trigger signal is TIM15_TRGO */
+/**
+ * @}
+ */
+
+/** @defgroup DMAEx_Node_Type DMAEx Node Type
+ * @brief DMAEx Node Type
+ * @{
+ */
+#define DMA_LPDMA_LINEAR_NODE (DMA_CHANNEL_TYPE_LPDMA | DMA_CHANNEL_TYPE_LINEAR_ADDR) /*!< Defines the LPDMA linear addressing node type */
+#define DMA_GPDMA_LINEAR_NODE (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_LINEAR_ADDR) /*!< Defines the GPDMA linear addressing node type */
+#define DMA_GPDMA_2D_NODE (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_2D_ADDR) /*!< Defines the GPDMA 2 dimension addressing node type */
+/**
+ * @}
+ */
+
+/** @defgroup DMAEx_Link_Allocated_Port DMAEx Linked-List Allocated Port
+ * @brief DMAEx Linked-List Allocated Port
+ * @{
+ */
+#define DMA_LINK_ALLOCATED_PORT0 0x00000000U /*!< Link allocated port 0 */
+#define DMA_LINK_ALLOCATED_PORT1 DMA_CCR_LAP /*!< Link allocated port 1 */
+/**
+ * @}
+ */
+
+/** @defgroup DMAEx_Link_Step_Mode DMAEx Link Step Mode
+ * @brief DMAEx Link Step Mode
+ * @{
+ */
+#define DMA_LSM_FULL_EXECUTION 0x00000000U /*!< Channel is executed for the full linked-list */
+#define DMA_LSM_1LINK_EXECUTION DMA_CCR_LSM /*!< Channel is executed once for the current LLI */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions ------------------------------------------------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
+ * @brief DMAEx Exported functions
+ * @{
+ */
+
+/** @defgroup DMAEx_Exported_Functions_Group1 Linked-List Initialization and De-Initialization Functions
+ * @brief Linked-List Initialization and De-Initialization Functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_DMAEx_List_Init(DMA_HandleTypeDef *const hdma);
+HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma);
+/**
+ * @}
+ */
+
+/** @defgroup DMAEx_Exported_Functions_Group2 Linked-List I/O Operation Functions
+ * @brief Linked-List I/O Operation Functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_DMAEx_List_Start(DMA_HandleTypeDef *const hdma);
+HAL_StatusTypeDef HAL_DMAEx_List_Start_IT(DMA_HandleTypeDef *const hdma);
+/**
+ * @}
+ */
+
+/** @defgroup DMAEx_Exported_Functions_Group3 Linked-List Management Functions
+ * @brief Linked-List Management Functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig,
+ DMA_NodeTypeDef *const pNode);
+HAL_StatusTypeDef HAL_DMAEx_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig,
+ DMA_NodeTypeDef const *const pNode);
+
+HAL_StatusTypeDef HAL_DMAEx_List_InsertNode(DMA_QListTypeDef *const pQList,
+ DMA_NodeTypeDef *const pPrevNode,
+ DMA_NodeTypeDef *const pNewNode);
+HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Head(DMA_QListTypeDef *const pQList,
+ DMA_NodeTypeDef *const pNewNode);
+HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Tail(DMA_QListTypeDef *const pQList,
+ DMA_NodeTypeDef *const pNewNode);
+
+HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode(DMA_QListTypeDef *const pQList,
+ DMA_NodeTypeDef *const pNode);
+HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Head(DMA_QListTypeDef *const pQList);
+HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Tail(DMA_QListTypeDef *const pQList);
+
+HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode(DMA_QListTypeDef *const pQList,
+ DMA_NodeTypeDef *const pOldNode,
+ DMA_NodeTypeDef *const pNewNode);
+HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Head(DMA_QListTypeDef *const pQList,
+ DMA_NodeTypeDef *const pNewNode);
+HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Tail(DMA_QListTypeDef *const pQList,
+ DMA_NodeTypeDef *const pNewNode);
+
+HAL_StatusTypeDef HAL_DMAEx_List_ResetQ(DMA_QListTypeDef *const pQList);
+
+HAL_StatusTypeDef HAL_DMAEx_List_InsertQ(DMA_QListTypeDef *const pSrcQList,
+ DMA_NodeTypeDef const *const pPrevNode,
+ DMA_QListTypeDef *const pDestQList);
+HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Head(DMA_QListTypeDef *const pSrcQList,
+ DMA_QListTypeDef *const pDestQList);
+HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Tail(DMA_QListTypeDef *const pSrcQList,
+ DMA_QListTypeDef *const pDestQList);
+
+HAL_StatusTypeDef HAL_DMAEx_List_SetCircularModeConfig(DMA_QListTypeDef *const pQList,
+ DMA_NodeTypeDef *const pFirstCircularNode);
+HAL_StatusTypeDef HAL_DMAEx_List_SetCircularMode(DMA_QListTypeDef *const pQList);
+HAL_StatusTypeDef HAL_DMAEx_List_ClearCircularMode(DMA_QListTypeDef *const pQList);
+
+HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToDynamic(DMA_QListTypeDef *const pQList);
+HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToStatic(DMA_QListTypeDef *const pQList);
+
+HAL_StatusTypeDef HAL_DMAEx_List_LinkQ(DMA_HandleTypeDef *const hdma,
+ DMA_QListTypeDef *const pQList);
+HAL_StatusTypeDef HAL_DMAEx_List_UnLinkQ(DMA_HandleTypeDef *const hdma);
+/**
+ * @}
+ */
+
+/** @defgroup DMAEx_Exported_Functions_Group4 Data Handling, Repeated Block and Trigger Configuration Functions
+ * @brief Data Handling, Repeated Block and Trigger Configuration Functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_DMAEx_ConfigDataHandling(DMA_HandleTypeDef *const hdma,
+ DMA_DataHandlingConfTypeDef const *const pConfigDataHandling);
+HAL_StatusTypeDef HAL_DMAEx_ConfigTrigger(DMA_HandleTypeDef *const hdma,
+ DMA_TriggerConfTypeDef const *const pConfigTrigger);
+HAL_StatusTypeDef HAL_DMAEx_ConfigRepeatBlock(DMA_HandleTypeDef *const hdma,
+ DMA_RepeatBlockConfTypeDef const *const pConfigRepeatBlock);
+/**
+ * @}
+ */
+
+/** @defgroup DMAEx_Exported_Functions_Group5 Suspend and Resume Operation Functions
+ * @brief Suspend and Resume Operation Functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_DMAEx_Suspend(DMA_HandleTypeDef *const hdma);
+HAL_StatusTypeDef HAL_DMAEx_Suspend_IT(DMA_HandleTypeDef *const hdma);
+HAL_StatusTypeDef HAL_DMAEx_Resume(DMA_HandleTypeDef *const hdma);
+/**
+ * @}
+ */
+
+/** @defgroup DMAEx_Exported_Functions_Group6 FIFO Status Function
+ * @brief FIFO Status Function
+ * @{
+ */
+uint32_t HAL_DMAEx_GetFifoLevel(DMA_HandleTypeDef const *const hdma);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -----------------------------------------------------------------------------------------------------*/
+/** @defgroup DMAEx_Private_Types DMAEx Private Types
+ * @brief DMAEx Private Types
+ * @{
+ */
+
+/**
+ * @brief DMA Node in Queue Information Structure Definition.
+ */
+typedef struct
+{
+ uint32_t cllr_offset; /* CLLR register offset */
+
+ uint32_t previousnode_addr; /* Previous node address */
+
+ uint32_t currentnode_pos; /* Current node position */
+
+ uint32_t currentnode_addr; /* Current node address */
+
+ uint32_t nextnode_addr; /* Next node address */
+
+} DMA_NodeInQInfoTypeDef;
+/**
+ * @}
+ */
+
+/* Private constants -------------------------------------------------------------------------------------------------*/
+/** @defgroup DMAEx_Private_Constants DMAEx Private Constants
+ * @brief DMAEx Private Constants
+ * @{
+ */
+#define DMA_LINKEDLIST (0x0080U) /* DMA channel linked-list mode */
+
+#define DMA_CHANNEL_TYPE_LINEAR_ADDR (0x0001U) /* DMA channel linear addressing mode */
+#define DMA_CHANNEL_TYPE_2D_ADDR (0x0002U) /* DMA channel 2D addressing mode */
+#define DMA_CHANNEL_TYPE_LPDMA (0x0010U) /* LPDMA channel node */
+#define DMA_CHANNEL_TYPE_GPDMA (0x0020U) /* GPDMA channel node */
+
+#define NODE_TYPE_MASK (0x00FFU) /* DMA channel node type */
+#define NODE_CLLR_IDX (0x0700U) /* DMA channel node CLLR index mask */
+#define NODE_CLLR_IDX_POS (0x0008U) /* DMA channel node CLLR index position */
+
+#define NODE_STATIC_FORMAT (0x0000U) /* DMA channel node static format */
+#define NODE_DYNAMIC_FORMAT (0x0001U) /* DMA channel node dynamic format */
+
+#define UPDATE_CLLR_POSITION (0x0000U) /* DMA channel update CLLR position */
+#define UPDATE_CLLR_VALUE (0x0001U) /* DMA channel update CLLR value */
+
+#define LASTNODE_ISNOT_CIRCULAR (0x0000U) /* Last node is not first circular node */
+#define LASTNODE_IS_CIRCULAR (0x0001U) /* Last node is first circular node */
+
+#define QUEUE_TYPE_STATIC (0x0000U) /* DMA channel static queue */
+#define QUEUE_TYPE_DYNAMIC (0x0001U) /* DMA channel dynamic queue */
+
+#define NODE_CTR1_DEFAULT_OFFSET (0x0000U) /* CTR1 default offset */
+#define NODE_CTR2_DEFAULT_OFFSET (0x0001U) /* CTR2 default offset */
+#define NODE_CBR1_DEFAULT_OFFSET (0x0002U) /* CBR1 default offset */
+#define NODE_CSAR_DEFAULT_OFFSET (0x0003U) /* CSAR default offset */
+#define NODE_CDAR_DEFAULT_OFFSET (0x0004U) /* CDAR default offset */
+#define NODE_CTR3_DEFAULT_OFFSET (0x0005U) /* CTR3 2D addressing default offset */
+#define NODE_CBR2_DEFAULT_OFFSET (0x0006U) /* CBR2 2D addressing default offset */
+#define NODE_CLLR_2D_DEFAULT_OFFSET (0x0007U) /* CLLR 2D addressing default offset */
+#define NODE_CLLR_LINEAR_DEFAULT_OFFSET (0x0005U) /* CLLR linear addressing default offset */
+
+#define DMA_BURST_ADDR_OFFSET_MIN (-8192L) /* DMA burst minimum address offset */
+#define DMA_BURST_ADDR_OFFSET_MAX (8192L) /* DMA burst maximum address offset */
+#define DMA_BLOCK_ADDR_OFFSET_MIN (-65536L) /* DMA block minimum address offset */
+#define DMA_BLOCK_ADDR_OFFSET_MAX (65536L) /* DMA block maximum address offset */
+/**
+ * @}
+ */
+
+/* Private macros ----------------------------------------------------------------------------------------------------*/
+/** @defgroup DMAEx_Private_Macros DMAEx Private Macros
+ * @brief DMAEx Private Macros
+ * @{
+ */
+#define IS_DMA_DATA_ALIGNMENT(ALIGNMENT) \
+ (((ALIGNMENT) == DMA_DATA_RIGHTALIGN_ZEROPADDED) || \
+ ((ALIGNMENT) == DMA_DATA_RIGHTALIGN_SIGNEXT) || \
+ ((ALIGNMENT) == DMA_DATA_PACK))
+
+#define IS_DMA_DATA_EXCHANGE(EXCHANGE) \
+ (((EXCHANGE) & (~(DMA_EXCHANGE_SRC_BYTE | DMA_EXCHANGE_DEST_BYTE | DMA_EXCHANGE_DEST_HALFWORD))) == 0U)
+
+#define IS_DMA_REPEAT_COUNT(COUNT) \
+ (((COUNT) > 0U) && ((COUNT) <= (DMA_CBR1_BRC >> DMA_CBR1_BRC_Pos)))
+
+#define IS_DMA_BURST_ADDR_OFFSET(BURST_ADDR_OFFSET) \
+ (((BURST_ADDR_OFFSET) > DMA_BURST_ADDR_OFFSET_MIN) && \
+ ((BURST_ADDR_OFFSET) < DMA_BURST_ADDR_OFFSET_MAX))
+
+#define IS_DMA_BLOCK_ADDR_OFFSET(BLOCK_ADDR_OFFSET) \
+ (((BLOCK_ADDR_OFFSET) > DMA_BLOCK_ADDR_OFFSET_MIN) && \
+ ((BLOCK_ADDR_OFFSET) < DMA_BLOCK_ADDR_OFFSET_MAX))
+
+#define IS_DMA_LINK_ALLOCATED_PORT(LINK_ALLOCATED_PORT) \
+ (((LINK_ALLOCATED_PORT) & (~(DMA_CCR_LAP))) == 0U)
+
+#define IS_DMA_LINK_STEP_MODE(MODE) \
+ (((MODE) == DMA_LSM_FULL_EXECUTION) || \
+ ((MODE) == DMA_LSM_1LINK_EXECUTION))
+
+#define IS_DMA_TRIGGER_MODE(MODE) \
+ (((MODE) == DMA_TRIGM_BLOCK_TRANSFER) || \
+ ((MODE) == DMA_TRIGM_REPEATED_BLOCK_TRANSFER) || \
+ ((MODE) == DMA_TRIGM_LLI_LINK_TRANSFER) || \
+ ((MODE) == DMA_TRIGM_SINGLE_BURST_TRANSFER))
+
+#define IS_DMA_TCEM_LINKEDLIST_EVENT_MODE(MODE) \
+ (((MODE) == DMA_TCEM_BLOCK_TRANSFER) || \
+ ((MODE) == DMA_TCEM_REPEATED_BLOCK_TRANSFER) || \
+ ((MODE) == DMA_TCEM_EACH_LL_ITEM_TRANSFER) || \
+ ((MODE) == DMA_TCEM_LAST_LL_ITEM_TRANSFER))
+
+#define IS_DMA_LINKEDLIST_MODE(MODE) \
+ (((MODE) == DMA_LINKEDLIST_NORMAL) || \
+ ((MODE) == DMA_LINKEDLIST_CIRCULAR))
+
+#define IS_DMA_TRIGGER_POLARITY(POLARITY) \
+ (((POLARITY) == DMA_TRIG_POLARITY_MASKED) || \
+ ((POLARITY) == DMA_TRIG_POLARITY_RISING) || \
+ ((POLARITY) == DMA_TRIG_POLARITY_FALLING))
+
+#define IS_DMA_TRIGGER_SELECTION(TRIGGER) \
+ ((TRIGGER) <= GPDMA1_TRIGGER_ADC1_AWD1)
+
+#define IS_DMA_NODE_TYPE(TYPE) \
+ (((TYPE) == DMA_LPDMA_LINEAR_NODE) || \
+ ((TYPE) == DMA_GPDMA_LINEAR_NODE) || \
+ ((TYPE) == DMA_GPDMA_2D_NODE))
+/**
+ * @}
+ */
+
+
+/* Private functions -------------------------------------------------------------------------------------------------*/
+/** @defgroup DMAEx_Private_Functions DMAEx Private Functions
+ * @brief DMAEx Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* STM32U5xx_HAL_DMA_EX_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_exti.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_exti.h
new file mode 100644
index 00000000..7fd63183
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_exti.h
@@ -0,0 +1,347 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_exti.h
+ * @author MCD Application Team
+ * @brief Header file of EXTI HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_EXTI_H
+#define STM32U5xx_HAL_EXTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup EXTI EXTI
+ * @brief EXTI HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup EXTI_Exported_Types EXTI Exported Types
+ * @{
+ */
+typedef enum
+{
+ HAL_EXTI_COMMON_CB_ID = 0x00U,
+ HAL_EXTI_RISING_CB_ID = 0x01U,
+ HAL_EXTI_FALLING_CB_ID = 0x02U,
+} EXTI_CallbackIDTypeDef;
+
+
+/**
+ * @brief EXTI Handle structure definition
+ */
+typedef struct
+{
+ uint32_t Line; /*!< Exti line number */
+ void (* RisingCallback)(void); /*!< Exti rising callback */
+ void (* FallingCallback)(void); /*!< Exti falling callback */
+} EXTI_HandleTypeDef;
+
+/**
+ * @brief EXTI Configuration structure definition
+ */
+typedef struct
+{
+ uint32_t Line; /*!< The Exti line to be configured. This parameter
+ can be a value of @ref EXTI_Line */
+ uint32_t Mode; /*!< The Exit Mode to be configured for a core.
+ This parameter can be a combination of @ref EXTI_Mode */
+ uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
+ can be a value of @ref EXTI_Trigger */
+ uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
+ This parameter is only possible for line 0 to 15. It
+ can be a value of @ref EXTI_GPIOSel */
+} EXTI_ConfigTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
+ * @{
+ */
+
+/** @defgroup EXTI_Line EXTI Line
+ * @{
+ */
+#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | 0x00U)
+#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | 0x01U)
+#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | 0x02U)
+#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | 0x03U)
+#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | 0x04U)
+#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | 0x05U)
+#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | 0x06U)
+#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | 0x07U)
+#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | 0x08U)
+#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | 0x09U)
+#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | 0x0AU)
+#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | 0x0BU)
+#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | 0x0CU)
+#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | 0x0DU)
+#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | 0x0EU)
+#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | 0x0FU)
+#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10U)
+#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | 0x11U)
+#define EXTI_LINE_18 (EXTI_DIRECT | EXTI_REG1 | 0x12U)
+#define EXTI_LINE_19 (EXTI_DIRECT | EXTI_REG1 | 0x13U)
+#define EXTI_LINE_20 (EXTI_DIRECT | EXTI_REG1 | 0x14U)
+#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | 0x15U)
+#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | 0x16U)
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Mode EXTI Mode
+ * @{
+ */
+#define EXTI_MODE_NONE 0x00000000U
+#define EXTI_MODE_INTERRUPT 0x00000001U
+#define EXTI_MODE_EVENT 0x00000002U
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Trigger EXTI Trigger
+ * @{
+ */
+#define EXTI_TRIGGER_NONE 0x00000000U
+#define EXTI_TRIGGER_RISING 0x00000001U
+#define EXTI_TRIGGER_FALLING 0x00000002U
+#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_GPIOSel EXTI GPIOSel
+ * @brief
+ * @{
+ */
+#define EXTI_GPIOA 0x00000000U
+#define EXTI_GPIOB 0x00000001U
+#define EXTI_GPIOC 0x00000002U
+#define EXTI_GPIOD 0x00000003U
+#define EXTI_GPIOE 0x00000004U
+#define EXTI_GPIOF 0x00000005U
+#define EXTI_GPIOG 0x00000006U
+#define EXTI_GPIOH 0x00000007U
+#define EXTI_GPIOI 0x00000008U
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Line_attributes EXTI line attributes
+ * @brief EXTI line secure or non-secure and privileged or non-privileged attributes
+ * @note secure and non-secure attributes are only available from secure state when the system
+ * implement the security (TZEN=1)
+ * @{
+ */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/*!< Secure line attribute */
+#define EXTI_LINE_SEC (EXTI_LINE_ATTR_SEC_MASK | 0x00000001U)
+/*!< Non-secure line attribute */
+#define EXTI_LINE_NSEC (EXTI_LINE_ATTR_SEC_MASK | 0x00000000U)
+#endif /* __ARM_FEATURE_CMSE */
+/*!< Privileged line attribute */
+#define EXTI_LINE_PRIV (EXTI_LINE_ATTR_PRIV_MASK | 0x00000002U)
+/*!< Non-privileged line attribute */
+#define EXTI_LINE_NPRIV (EXTI_LINE_ATTR_PRIV_MASK | 0x00000000U)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Private constants --------------------------------------------------------*/
+/** @defgroup EXTI_Private_Constants EXTI Private Constants
+ * @{
+ */
+/**
+ * @brief EXTI Line property definition
+ */
+#define EXTI_PROPERTY_SHIFT 24U
+#define EXTI_DIRECT (0x01U << EXTI_PROPERTY_SHIFT)
+#define EXTI_CONFIG (0x02U << EXTI_PROPERTY_SHIFT)
+#define EXTI_GPIO ((0x04U << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
+#define EXTI_RESERVED (0x08U << EXTI_PROPERTY_SHIFT)
+#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
+
+/**
+ * @brief EXTI Register and bit usage
+ */
+#define EXTI_REG_SHIFT 16U
+#define EXTI_REG1 (0x00U << EXTI_REG_SHIFT)
+#define EXTI_REG2 (0x01U << EXTI_REG_SHIFT)
+#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2)
+#define EXTI_PIN_MASK 0x0000001FU
+
+/**
+ * @brief EXTI Mask for interrupt & event mode
+ */
+#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
+
+/**
+ * @brief EXTI Mask for trigger possibilities
+ */
+#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
+
+/**
+ * @brief EXTI Line number
+ */
+#define EXTI_LINE_NB 23U
+
+/**
+ * @brief EXTI Mask for secure & privilege attributes
+ */
+#define EXTI_LINE_ATTR_SEC_MASK 0x100U
+#define EXTI_LINE_ATTR_PRIV_MASK 0x200U
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup EXTI_Private_Macros EXTI Private Macros
+ * @{
+ */
+#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | \
+ EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00U) \
+ &&((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
+ (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
+ (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
+ (((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \
+ (((EXTI_LINE_NB / 32U) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32U))))
+
+#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00U) && \
+ (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00U))
+
+#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U)
+
+#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) (((__EXTI_LINE__) == EXTI_TRIGGER_RISING) || \
+ ((__EXTI_LINE__) == EXTI_TRIGGER_FALLING))
+
+#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00U)
+
+#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
+ ((__PORT__) == EXTI_GPIOB) || \
+ ((__PORT__) == EXTI_GPIOC) || \
+ ((__PORT__) == EXTI_GPIOD) || \
+ ((__PORT__) == EXTI_GPIOE) || \
+ ((__PORT__) == EXTI_GPIOF) || \
+ ((__PORT__) == EXTI_GPIOG) || \
+ ((__PORT__) == EXTI_GPIOH) || \
+ ((__PORT__) == EXTI_GPIOI))
+
+#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U)
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+#define IS_EXTI_LINE_ATTRIBUTES(__ATTRIBUTES__) (((((__ATTRIBUTES__) & EXTI_LINE_SEC) == EXTI_LINE_SEC) || \
+ (((__ATTRIBUTES__) & EXTI_LINE_NSEC) == EXTI_LINE_NSEC) || \
+ (((__ATTRIBUTES__) & EXTI_LINE_PRIV) == EXTI_LINE_PRIV) || \
+ (((__ATTRIBUTES__) & EXTI_LINE_NPRIV) == EXTI_LINE_NPRIV)) && \
+ (((__ATTRIBUTES__) & ~(EXTI_LINE_SEC|EXTI_LINE_NSEC|EXTI_LINE_PRIV| \
+ EXTI_LINE_NPRIV)) == 0U))
+
+#else
+
+#define IS_EXTI_LINE_ATTRIBUTES(__ATTRIBUTES__) (((((__ATTRIBUTES__) & EXTI_LINE_PRIV) == EXTI_LINE_PRIV) || \
+ (((__ATTRIBUTES__) & EXTI_LINE_NPRIV) == EXTI_LINE_NPRIV)) && \
+ (((__ATTRIBUTES__) & ~(EXTI_LINE_PRIV|EXTI_LINE_NPRIV)) == 0U))
+
+#endif /* __ARM_FEATURE_CMSE */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
+ * @brief EXTI Exported Functions
+ * @{
+ */
+
+/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
+ * @brief Configuration functions
+ * @{
+ */
+/* Configuration functions ****************************************************/
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID,
+ void (*pPendingCbfn)(void));
+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
+ * @brief IO operation functions
+ * @{
+ */
+/* IO operation functions *****************************************************/
+void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
+uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
+void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
+void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Exported_Functions_Group3 EXTI line attributes management functions
+ * @{
+ */
+
+/* EXTI line attributes management functions **********************************/
+void HAL_EXTI_ConfigLineAttributes(uint32_t ExtiLine, uint32_t LineAttributes);
+HAL_StatusTypeDef HAL_EXTI_GetConfigLineAttributes(uint32_t ExtiLine, uint32_t *pLineAttributes);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_EXTI_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_fdcan.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_fdcan.h
new file mode 100644
index 00000000..4cf16d6b
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_fdcan.h
@@ -0,0 +1,1431 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_fdcan.h
+ * @author MCD Application Team
+ * @brief Header file of FDCAN HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_FDCAN_H
+#define STM32U5xx_HAL_FDCAN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+#if defined(FDCAN1)
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FDCAN
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FDCAN_Exported_Types FDCAN Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_FDCAN_STATE_RESET = 0x00U, /*!< FDCAN not yet initialized or disabled */
+ HAL_FDCAN_STATE_READY = 0x01U, /*!< FDCAN initialized and ready for use */
+ HAL_FDCAN_STATE_BUSY = 0x02U, /*!< FDCAN process is ongoing */
+ HAL_FDCAN_STATE_ERROR = 0x03U /*!< FDCAN error state */
+} HAL_FDCAN_StateTypeDef;
+
+/**
+ * @brief FDCAN Init structure definition
+ */
+typedef struct
+{
+ uint32_t ClockDivider; /*!< Specifies the FDCAN kernel clock divider.
+ The clock is common to all FDCAN instances.
+ This parameter is applied only at initialisation of
+ first FDCAN instance.
+ This parameter can be a value of @ref FDCAN_clock_divider. */
+
+ uint32_t FrameFormat; /*!< Specifies the FDCAN frame format.
+ This parameter can be a value of @ref FDCAN_frame_format */
+
+ uint32_t Mode; /*!< Specifies the FDCAN mode.
+ This parameter can be a value of @ref FDCAN_operating_mode */
+
+ FunctionalState AutoRetransmission; /*!< Enable or disable the automatic retransmission mode.
+ This parameter can be set to ENABLE or DISABLE */
+
+ FunctionalState TransmitPause; /*!< Enable or disable the Transmit Pause feature.
+ This parameter can be set to ENABLE or DISABLE */
+
+ FunctionalState ProtocolException; /*!< Enable or disable the Protocol Exception Handling.
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t NominalPrescaler; /*!< Specifies the value by which the oscillator frequency is
+ divided for generating the nominal bit time quanta.
+ This parameter must be a number between 1 and 512 */
+
+ uint32_t NominalSyncJumpWidth; /*!< Specifies the maximum number of time quanta the FDCAN
+ hardware is allowed to lengthen or shorten a bit to perform
+ resynchronization.
+ This parameter must be a number between 1 and 128 */
+
+ uint32_t NominalTimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1.
+ This parameter must be a number between 2 and 256 */
+
+ uint32_t NominalTimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2.
+ This parameter must be a number between 2 and 128 */
+
+ uint32_t DataPrescaler; /*!< Specifies the value by which the oscillator frequency is
+ divided for generating the data bit time quanta.
+ This parameter must be a number between 1 and 32 */
+
+ uint32_t DataSyncJumpWidth; /*!< Specifies the maximum number of time quanta the FDCAN
+ hardware is allowed to lengthen or shorten a data bit to
+ perform resynchronization.
+ This parameter must be a number between 1 and 16 */
+
+ uint32_t DataTimeSeg1; /*!< Specifies the number of time quanta in Data Bit Segment 1.
+ This parameter must be a number between 1 and 32 */
+
+ uint32_t DataTimeSeg2; /*!< Specifies the number of time quanta in Data Bit Segment 2.
+ This parameter must be a number between 1 and 16 */
+
+ uint32_t StdFiltersNbr; /*!< Specifies the number of standard Message ID filters.
+ This parameter must be a number between 0 and 28 */
+
+ uint32_t ExtFiltersNbr; /*!< Specifies the number of extended Message ID filters.
+ This parameter must be a number between 0 and 8 */
+
+ uint32_t TxFifoQueueMode; /*!< Tx FIFO/Queue Mode selection.
+ This parameter can be a value of @ref FDCAN_txFifoQueue_Mode */
+
+} FDCAN_InitTypeDef;
+
+/**
+ * @brief FDCAN filter structure definition
+ */
+typedef struct
+{
+ uint32_t IdType; /*!< Specifies the identifier type.
+ This parameter can be a value of @ref FDCAN_id_type */
+
+ uint32_t FilterIndex; /*!< Specifies the filter which will be initialized.
+ This parameter must be a number between:
+ - 0 and (SRAMCAN_FLS_NBR-1), if IdType is FDCAN_STANDARD_ID
+ - 0 and (SRAMCAN_FLE_NBR-1), if IdType is FDCAN_EXTENDED_ID */
+
+ uint32_t FilterType; /*!< Specifies the filter type.
+ This parameter can be a value of @ref FDCAN_filter_type.
+ The value FDCAN_FILTER_RANGE_NO_EIDM is permitted
+ only when IdType is FDCAN_EXTENDED_ID. */
+
+ uint32_t FilterConfig; /*!< Specifies the filter configuration.
+ This parameter can be a value of @ref FDCAN_filter_config */
+
+ uint32_t FilterID1; /*!< Specifies the filter identification 1.
+ This parameter must be a number between:
+ - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+ - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */
+
+ uint32_t FilterID2; /*!< Specifies the filter identification 2.
+ This parameter must be a number between:
+ - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+ - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */
+
+} FDCAN_FilterTypeDef;
+
+/**
+ * @brief FDCAN Tx header structure definition
+ */
+typedef struct
+{
+ uint32_t Identifier; /*!< Specifies the identifier.
+ This parameter must be a number between:
+ - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+ - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */
+
+ uint32_t IdType; /*!< Specifies the identifier type for the message that will be
+ transmitted.
+ This parameter can be a value of @ref FDCAN_id_type */
+
+ uint32_t TxFrameType; /*!< Specifies the frame type of the message that will be transmitted.
+ This parameter can be a value of @ref FDCAN_frame_type */
+
+ uint32_t DataLength; /*!< Specifies the length of the frame that will be transmitted.
+ This parameter can be a value of @ref FDCAN_data_length_code */
+
+ uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
+ This parameter can be a value of @ref FDCAN_error_state_indicator */
+
+ uint32_t BitRateSwitch; /*!< Specifies whether the Tx frame will be transmitted with or without
+ bit rate switching.
+ This parameter can be a value of @ref FDCAN_bit_rate_switching */
+
+ uint32_t FDFormat; /*!< Specifies whether the Tx frame will be transmitted in classic or
+ FD format.
+ This parameter can be a value of @ref FDCAN_format */
+
+ uint32_t TxEventFifoControl; /*!< Specifies the event FIFO control.
+ This parameter can be a value of @ref FDCAN_EFC */
+
+ uint32_t MessageMarker; /*!< Specifies the message marker to be copied into Tx Event FIFO
+ element for identification of Tx message status.
+ This parameter must be a number between 0 and 0xFF */
+
+} FDCAN_TxHeaderTypeDef;
+
+/**
+ * @brief FDCAN Rx header structure definition
+ */
+typedef struct
+{
+ uint32_t Identifier; /*!< Specifies the identifier.
+ This parameter must be a number between:
+ - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+ - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */
+
+ uint32_t IdType; /*!< Specifies the identifier type of the received message.
+ This parameter can be a value of @ref FDCAN_id_type */
+
+ uint32_t RxFrameType; /*!< Specifies the the received message frame type.
+ This parameter can be a value of @ref FDCAN_frame_type */
+
+ uint32_t DataLength; /*!< Specifies the received frame length.
+ This parameter can be a value of @ref FDCAN_data_length_code */
+
+ uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
+ This parameter can be a value of @ref FDCAN_error_state_indicator */
+
+ uint32_t BitRateSwitch; /*!< Specifies whether the Rx frame is received with or without bit
+ rate switching.
+ This parameter can be a value of @ref FDCAN_bit_rate_switching */
+
+ uint32_t FDFormat; /*!< Specifies whether the Rx frame is received in classic or FD
+ format.
+ This parameter can be a value of @ref FDCAN_format */
+
+ uint32_t RxTimestamp; /*!< Specifies the timestamp counter value captured on start of frame
+ reception.
+ This parameter must be a number between 0 and 0xFFFF */
+
+ uint32_t FilterIndex; /*!< Specifies the index of matching Rx acceptance filter element.
+ This parameter must be a number between:
+ - 0 and (SRAMCAN_FLS_NBR-1), if IdType is FDCAN_STANDARD_ID
+ - 0 and (SRAMCAN_FLE_NBR-1), if IdType is FDCAN_EXTENDED_ID */
+
+ uint32_t IsFilterMatchingFrame; /*!< Specifies whether the accepted frame did not match any Rx filter.
+ Acceptance of non-matching frames may be enabled via
+ HAL_FDCAN_ConfigGlobalFilter().
+ This parameter can be 0 or 1 */
+
+} FDCAN_RxHeaderTypeDef;
+
+/**
+ * @brief FDCAN Tx event FIFO structure definition
+ */
+typedef struct
+{
+ uint32_t Identifier; /*!< Specifies the identifier.
+ This parameter must be a number between:
+ - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+ - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */
+
+ uint32_t IdType; /*!< Specifies the identifier type for the transmitted message.
+ This parameter can be a value of @ref FDCAN_id_type */
+
+ uint32_t TxFrameType; /*!< Specifies the frame type of the transmitted message.
+ This parameter can be a value of @ref FDCAN_frame_type */
+
+ uint32_t DataLength; /*!< Specifies the length of the transmitted frame.
+ This parameter can be a value of @ref FDCAN_data_length_code */
+
+ uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
+ This parameter can be a value of @ref FDCAN_error_state_indicator */
+
+ uint32_t BitRateSwitch; /*!< Specifies whether the Tx frame is transmitted with or without bit
+ rate switching.
+ This parameter can be a value of @ref FDCAN_bit_rate_switching */
+
+ uint32_t FDFormat; /*!< Specifies whether the Tx frame is transmitted in classic or FD
+ format.
+ This parameter can be a value of @ref FDCAN_format */
+
+ uint32_t TxTimestamp; /*!< Specifies the timestamp counter value captured on start of frame
+ transmission.
+ This parameter must be a number between 0 and 0xFFFF */
+
+ uint32_t MessageMarker; /*!< Specifies the message marker copied into Tx Event FIFO element
+ for identification of Tx message status.
+ This parameter must be a number between 0 and 0xFF */
+
+ uint32_t EventType; /*!< Specifies the event type.
+ This parameter can be a value of @ref FDCAN_event_type */
+
+} FDCAN_TxEventFifoTypeDef;
+
+/**
+ * @brief FDCAN High Priority Message Status structure definition
+ */
+typedef struct
+{
+ uint32_t FilterList; /*!< Specifies the filter list of the matching filter element.
+ This parameter can be:
+ - 0 : Standard Filter List
+ - 1 : Extended Filter List */
+
+ uint32_t FilterIndex; /*!< Specifies the index of matching filter element.
+ This parameter can be a number between:
+ - 0 and (SRAMCAN_FLS_NBR-1), if FilterList is 0 (Standard)
+ - 0 and (SRAMCAN_FLE_NBR-1), if FilterList is 1 (Extended) */
+
+ uint32_t MessageStorage; /*!< Specifies the HP Message Storage.
+ This parameter can be a value of @ref FDCAN_hp_msg_storage */
+
+ uint32_t MessageIndex; /*!< Specifies the Index of Rx FIFO element to which the
+ message was stored.
+ This parameter is valid only when MessageStorage is:
+ FDCAN_HP_STORAGE_RXFIFO0
+ or
+ FDCAN_HP_STORAGE_RXFIFO1 */
+
+} FDCAN_HpMsgStatusTypeDef;
+
+/**
+ * @brief FDCAN Protocol Status structure definition
+ */
+typedef struct
+{
+ uint32_t LastErrorCode; /*!< Specifies the type of the last error that occurred on the FDCAN bus.
+ This parameter can be a value of @ref FDCAN_protocol_error_code */
+
+ uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase
+ of a CAN FD format frame with its BRS flag set.
+ This parameter can be a value of @ref FDCAN_protocol_error_code */
+
+ uint32_t Activity; /*!< Specifies the FDCAN module communication state.
+ This parameter can be a value of @ref FDCAN_communication_state */
+
+ uint32_t ErrorPassive; /*!< Specifies the FDCAN module error status.
+ This parameter can be:
+ - 0 : The FDCAN is in Error_Active state
+ - 1 : The FDCAN is in Error_Passive state */
+
+ uint32_t Warning; /*!< Specifies the FDCAN module warning status.
+ This parameter can be:
+ - 0 : error counters (RxErrorCnt and TxErrorCnt)
+ are below the Error_Warning limit of 96
+ - 1 : at least one of error counters has reached the Error_Warning limit of 96 */
+
+ uint32_t BusOff; /*!< Specifies the FDCAN module Bus_Off status.
+ This parameter can be:
+ - 0 : The FDCAN is not in Bus_Off state
+ - 1 : The FDCAN is in Bus_Off state */
+
+ uint32_t RxESIflag; /*!< Specifies ESI flag of last received CAN FD message.
+ This parameter can be:
+ - 0 : Last received CAN FD message did not have its ESI flag set
+ - 1 : Last received CAN FD message had its ESI flag set */
+
+ uint32_t RxBRSflag; /*!< Specifies BRS flag of last received CAN FD message.
+ This parameter can be:
+ - 0 : Last received CAN FD message did not have its BRS flag set
+ - 1 : Last received CAN FD message had its BRS flag set */
+
+ uint32_t RxFDFflag; /*!< Specifies if CAN FD message (FDF flag set) has been received
+ since last protocol status.This parameter can be:
+ - 0 : No CAN FD message received
+ - 1 : CAN FD message received */
+
+ uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception status.
+ This parameter can be:
+ - 0 : No protocol exception event occurred since last read access
+ - 1 : Protocol exception event occurred */
+
+ uint32_t TDCvalue; /*!< Specifies the Transmitter Delay Compensation Value.
+ This parameter can be a number between 0 and 127 */
+
+} FDCAN_ProtocolStatusTypeDef;
+
+/**
+ * @brief FDCAN Error Counters structure definition
+ */
+typedef struct
+{
+ uint32_t TxErrorCnt; /*!< Specifies the Transmit Error Counter Value.
+ This parameter can be a number between 0 and 255 */
+
+ uint32_t RxErrorCnt; /*!< Specifies the Receive Error Counter Value.
+ This parameter can be a number between 0 and 127 */
+
+ uint32_t RxErrorPassive; /*!< Specifies the Receive Error Passive status.
+ This parameter can be:
+ - 0 : The Receive Error Counter (RxErrorCnt) is below the error passive level of 128
+ - 1 : The Receive Error Counter (RxErrorCnt)
+ has reached the error passive level of 128 */
+
+ uint32_t ErrorLogging; /*!< Specifies the Transmit/Receive error logging counter value.
+ This parameter can be a number between 0 and 255.
+ This counter is incremented each time when a FDCAN protocol error causes the TxErrorCnt
+ or the RxErrorCnt to be incremented. The counter stops at 255; the next increment of
+ TxErrorCnt or RxErrorCnt sets interrupt flag FDCAN_FLAG_ERROR_LOGGING_OVERFLOW */
+
+} FDCAN_ErrorCountersTypeDef;
+
+/**
+ * @brief FDCAN Message RAM blocks
+ */
+typedef struct
+{
+ uint32_t StandardFilterSA; /*!< Specifies the Standard Filter List Start Address.
+ This parameter must be a 32-bit word address */
+
+ uint32_t ExtendedFilterSA; /*!< Specifies the Extended Filter List Start Address.
+ This parameter must be a 32-bit word address */
+
+ uint32_t RxFIFO0SA; /*!< Specifies the Rx FIFO 0 Start Address.
+ This parameter must be a 32-bit word address */
+
+ uint32_t RxFIFO1SA; /*!< Specifies the Rx FIFO 1 Start Address.
+ This parameter must be a 32-bit word address */
+
+ uint32_t TxEventFIFOSA; /*!< Specifies the Tx Event FIFO Start Address.
+ This parameter must be a 32-bit word address */
+
+ uint32_t TxFIFOQSA; /*!< Specifies the Tx FIFO/Queue Start Address.
+ This parameter must be a 32-bit word address */
+
+} FDCAN_MsgRamAddressTypeDef;
+
+/**
+ * @brief FDCAN handle structure definition
+ */
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+typedef struct __FDCAN_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+{
+ FDCAN_GlobalTypeDef *Instance; /*!< Register base address */
+
+ FDCAN_InitTypeDef Init; /*!< FDCAN required parameters */
+
+ FDCAN_MsgRamAddressTypeDef msgRam; /*!< FDCAN Message RAM blocks */
+
+ uint32_t LatestTxFifoQRequest; /*!< FDCAN Tx buffer index
+ of latest Tx FIFO/Queue request */
+
+ __IO HAL_FDCAN_StateTypeDef State; /*!< FDCAN communication state */
+
+ HAL_LockTypeDef Lock; /*!< FDCAN locking object */
+
+ __IO uint32_t ErrorCode; /*!< FDCAN Error code */
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+ void (* TxEventFifoCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs); /*!< FDCAN Tx Event Fifo callback */
+ void (* RxFifo0Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs); /*!< FDCAN Rx Fifo 0 callback */
+ void (* RxFifo1Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs); /*!< FDCAN Rx Fifo 1 callback */
+ void (* TxFifoEmptyCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Tx Fifo Empty callback */
+ void (* TxBufferCompleteCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< FDCAN Tx Buffer complete callback */
+ void (* TxBufferAbortCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< FDCAN Tx Buffer abort callback */
+ void (* HighPriorityMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN High priority message callback */
+ void (* TimestampWraparoundCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Timestamp wraparound callback */
+ void (* TimeoutOccurredCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Timeout occurred callback */
+ void (* ErrorCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Error callback */
+ void (* ErrorStatusCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs); /*!< FDCAN Error status callback */
+
+ void (* MspInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Msp Init callback */
+ void (* MspDeInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Msp DeInit callback */
+
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+} FDCAN_HandleTypeDef;
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+/**
+ * @brief HAL FDCAN common Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_FDCAN_TX_FIFO_EMPTY_CB_ID = 0x00U, /*!< FDCAN Tx Fifo Empty callback ID */
+ HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID = 0x01U, /*!< FDCAN High priority message callback ID */
+ HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID = 0x02U, /*!< FDCAN Timestamp wraparound callback ID */
+ HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID = 0x03U, /*!< FDCAN Timeout occurred callback ID */
+ HAL_FDCAN_ERROR_CALLBACK_CB_ID = 0x04U, /*!< FDCAN Error callback ID */
+
+ HAL_FDCAN_MSPINIT_CB_ID = 0x05U, /*!< FDCAN MspInit callback ID */
+ HAL_FDCAN_MSPDEINIT_CB_ID = 0x06U, /*!< FDCAN MspDeInit callback ID */
+
+} HAL_FDCAN_CallbackIDTypeDef;
+
+/**
+ * @brief HAL FDCAN Callback pointer definition
+ */
+typedef void (*pFDCAN_CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan); /*!< pointer to a common FDCAN callback function */
+typedef void (*pFDCAN_TxEventFifoCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs); /*!< pointer to Tx event Fifo FDCAN callback function */
+typedef void (*pFDCAN_RxFifo0CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs); /*!< pointer to Rx Fifo 0 FDCAN callback function */
+typedef void (*pFDCAN_RxFifo1CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs); /*!< pointer to Rx Fifo 1 FDCAN callback function */
+typedef void (*pFDCAN_TxBufferCompleteCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< pointer to Tx Buffer complete FDCAN callback function */
+typedef void (*pFDCAN_TxBufferAbortCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< pointer to Tx Buffer abort FDCAN callback function */
+typedef void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs); /*!< pointer to Error Status callback function */
+
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FDCAN_Exported_Constants FDCAN Exported Constants
+ * @{
+ */
+
+/** @defgroup HAL_FDCAN_Error_Code HAL FDCAN Error Code
+ * @{
+ */
+#define HAL_FDCAN_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
+#define HAL_FDCAN_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */
+#define HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U) /*!< Peripheral not initialized */
+#define HAL_FDCAN_ERROR_NOT_READY ((uint32_t)0x00000004U) /*!< Peripheral not ready */
+#define HAL_FDCAN_ERROR_NOT_STARTED ((uint32_t)0x00000008U) /*!< Peripheral not started */
+#define HAL_FDCAN_ERROR_NOT_SUPPORTED ((uint32_t)0x00000010U) /*!< Mode not supported */
+#define HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U) /*!< Parameter error */
+#define HAL_FDCAN_ERROR_PENDING ((uint32_t)0x00000040U) /*!< Pending operation */
+#define HAL_FDCAN_ERROR_RAM_ACCESS ((uint32_t)0x00000080U) /*!< Message RAM Access Failure */
+#define HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U) /*!< Put element in full FIFO */
+#define HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U) /*!< Get element from empty FIFO */
+#define HAL_FDCAN_ERROR_LOG_OVERFLOW FDCAN_IR_ELO /*!< Overflow of CAN Error Logging Counter */
+#define HAL_FDCAN_ERROR_RAM_WDG FDCAN_IR_WDI /*!< Message RAM Watchdog event occurred */
+#define HAL_FDCAN_ERROR_PROTOCOL_ARBT FDCAN_IR_PEA /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is used) */
+#define HAL_FDCAN_ERROR_PROTOCOL_DATA FDCAN_IR_PED /*!< Protocol Error in Data Phase (Data Bit Time is used) */
+#define HAL_FDCAN_ERROR_RESERVED_AREA FDCAN_IR_ARA /*!< Access to Reserved Address */
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+#define HAL_FDCAN_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100U) /*!< Invalid Callback error */
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_frame_format FDCAN Frame Format
+ * @{
+ */
+#define FDCAN_FRAME_CLASSIC ((uint32_t)0x00000000U) /*!< Classic mode */
+#define FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE) /*!< FD mode without BitRate Switching */
+#define FDCAN_FRAME_FD_BRS ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE)) /*!< FD mode with BitRate Switching */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_operating_mode FDCAN Operating Mode
+ * @{
+ */
+#define FDCAN_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */
+#define FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U) /*!< Restricted Operation mode */
+#define FDCAN_MODE_BUS_MONITORING ((uint32_t)0x00000002U) /*!< Bus Monitoring mode */
+#define FDCAN_MODE_INTERNAL_LOOPBACK ((uint32_t)0x00000003U) /*!< Internal LoopBack mode */
+#define FDCAN_MODE_EXTERNAL_LOOPBACK ((uint32_t)0x00000004U) /*!< External LoopBack mode */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_clock_divider FDCAN Clock Divider
+ * @{
+ */
+#define FDCAN_CLOCK_DIV1 ((uint32_t)0x00000000U) /*!< Divide kernel clock by 1 */
+#define FDCAN_CLOCK_DIV2 ((uint32_t)0x00000001U) /*!< Divide kernel clock by 2 */
+#define FDCAN_CLOCK_DIV4 ((uint32_t)0x00000002U) /*!< Divide kernel clock by 4 */
+#define FDCAN_CLOCK_DIV6 ((uint32_t)0x00000003U) /*!< Divide kernel clock by 6 */
+#define FDCAN_CLOCK_DIV8 ((uint32_t)0x00000004U) /*!< Divide kernel clock by 8 */
+#define FDCAN_CLOCK_DIV10 ((uint32_t)0x00000005U) /*!< Divide kernel clock by 10 */
+#define FDCAN_CLOCK_DIV12 ((uint32_t)0x00000006U) /*!< Divide kernel clock by 12 */
+#define FDCAN_CLOCK_DIV14 ((uint32_t)0x00000007U) /*!< Divide kernel clock by 14 */
+#define FDCAN_CLOCK_DIV16 ((uint32_t)0x00000008U) /*!< Divide kernel clock by 16 */
+#define FDCAN_CLOCK_DIV18 ((uint32_t)0x00000009U) /*!< Divide kernel clock by 18 */
+#define FDCAN_CLOCK_DIV20 ((uint32_t)0x0000000AU) /*!< Divide kernel clock by 20 */
+#define FDCAN_CLOCK_DIV22 ((uint32_t)0x0000000BU) /*!< Divide kernel clock by 22 */
+#define FDCAN_CLOCK_DIV24 ((uint32_t)0x0000000CU) /*!< Divide kernel clock by 24 */
+#define FDCAN_CLOCK_DIV26 ((uint32_t)0x0000000DU) /*!< Divide kernel clock by 26 */
+#define FDCAN_CLOCK_DIV28 ((uint32_t)0x0000000EU) /*!< Divide kernel clock by 28 */
+#define FDCAN_CLOCK_DIV30 ((uint32_t)0x0000000FU) /*!< Divide kernel clock by 30 */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_txFifoQueue_Mode FDCAN Tx FIFO/Queue Mode
+ * @{
+ */
+#define FDCAN_TX_FIFO_OPERATION ((uint32_t)0x00000000U) /*!< FIFO mode */
+#define FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM) /*!< Queue mode */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_id_type FDCAN ID Type
+ * @{
+ */
+#define FDCAN_STANDARD_ID ((uint32_t)0x00000000U) /*!< Standard ID element */
+#define FDCAN_EXTENDED_ID ((uint32_t)0x40000000U) /*!< Extended ID element */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_frame_type FDCAN Frame Type
+ * @{
+ */
+#define FDCAN_DATA_FRAME ((uint32_t)0x00000000U) /*!< Data frame */
+#define FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U) /*!< Remote frame */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_data_length_code FDCAN Data Length Code
+ * @{
+ */
+#define FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U) /*!< 0 bytes data field */
+#define FDCAN_DLC_BYTES_1 ((uint32_t)0x00010000U) /*!< 1 bytes data field */
+#define FDCAN_DLC_BYTES_2 ((uint32_t)0x00020000U) /*!< 2 bytes data field */
+#define FDCAN_DLC_BYTES_3 ((uint32_t)0x00030000U) /*!< 3 bytes data field */
+#define FDCAN_DLC_BYTES_4 ((uint32_t)0x00040000U) /*!< 4 bytes data field */
+#define FDCAN_DLC_BYTES_5 ((uint32_t)0x00050000U) /*!< 5 bytes data field */
+#define FDCAN_DLC_BYTES_6 ((uint32_t)0x00060000U) /*!< 6 bytes data field */
+#define FDCAN_DLC_BYTES_7 ((uint32_t)0x00070000U) /*!< 7 bytes data field */
+#define FDCAN_DLC_BYTES_8 ((uint32_t)0x00080000U) /*!< 8 bytes data field */
+#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U) /*!< 12 bytes data field */
+#define FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U) /*!< 16 bytes data field */
+#define FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U) /*!< 20 bytes data field */
+#define FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U) /*!< 24 bytes data field */
+#define FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U) /*!< 32 bytes data field */
+#define FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U) /*!< 48 bytes data field */
+#define FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U) /*!< 64 bytes data field */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_error_state_indicator FDCAN Error State Indicator
+ * @{
+ */
+#define FDCAN_ESI_ACTIVE ((uint32_t)0x00000000U) /*!< Transmitting node is error active */
+#define FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U) /*!< Transmitting node is error passive */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_bit_rate_switching FDCAN Bit Rate Switching
+ * @{
+ */
+#define FDCAN_BRS_OFF ((uint32_t)0x00000000U) /*!< FDCAN frames transmitted/received without bit rate switching */
+#define FDCAN_BRS_ON ((uint32_t)0x00100000U) /*!< FDCAN frames transmitted/received with bit rate switching */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_format FDCAN format
+ * @{
+ */
+#define FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U) /*!< Frame transmitted/received in Classic CAN format */
+#define FDCAN_FD_CAN ((uint32_t)0x00200000U) /*!< Frame transmitted/received in FDCAN format */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_EFC FDCAN Event FIFO control
+ * @{
+ */
+#define FDCAN_NO_TX_EVENTS ((uint32_t)0x00000000U) /*!< Do not store Tx events */
+#define FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U) /*!< Store Tx events */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_filter_type FDCAN Filter Type
+ * @{
+ */
+#define FDCAN_FILTER_RANGE ((uint32_t)0x00000000U) /*!< Range filter from FilterID1 to FilterID2 */
+#define FDCAN_FILTER_DUAL ((uint32_t)0x00000001U) /*!< Dual ID filter for FilterID1 or FilterID2 */
+#define FDCAN_FILTER_MASK ((uint32_t)0x00000002U) /*!< Classic filter: FilterID1 = filter, FilterID2 = mask */
+#define FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U) /*!< Range filter from FilterID1 to FilterID2, EIDM mask not applied */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_filter_config FDCAN Filter Configuration
+ * @{
+ */
+#define FDCAN_FILTER_DISABLE ((uint32_t)0x00000000U) /*!< Disable filter element */
+#define FDCAN_FILTER_TO_RXFIFO0 ((uint32_t)0x00000001U) /*!< Store in Rx FIFO 0 if filter matches */
+#define FDCAN_FILTER_TO_RXFIFO1 ((uint32_t)0x00000002U) /*!< Store in Rx FIFO 1 if filter matches */
+#define FDCAN_FILTER_REJECT ((uint32_t)0x00000003U) /*!< Reject ID if filter matches */
+#define FDCAN_FILTER_HP ((uint32_t)0x00000004U) /*!< Set high priority if filter matches */
+#define FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U) /*!< Set high priority and store in FIFO 0 if filter matches */
+#define FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U) /*!< Set high priority and store in FIFO 1 if filter matches */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Tx_location FDCAN Tx Location
+ * @{
+ */
+#define FDCAN_TX_BUFFER0 ((uint32_t)0x00000001U) /*!< Add message to Tx Buffer 0 */
+#define FDCAN_TX_BUFFER1 ((uint32_t)0x00000002U) /*!< Add message to Tx Buffer 1 */
+#define FDCAN_TX_BUFFER2 ((uint32_t)0x00000004U) /*!< Add message to Tx Buffer 2 */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Rx_location FDCAN Rx Location
+ * @{
+ */
+#define FDCAN_RX_FIFO0 ((uint32_t)0x00000040U) /*!< Get received message from Rx FIFO 0 */
+#define FDCAN_RX_FIFO1 ((uint32_t)0x00000041U) /*!< Get received message from Rx FIFO 1 */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_event_type FDCAN Event Type
+ * @{
+ */
+#define FDCAN_TX_EVENT ((uint32_t)0x00400000U) /*!< Tx event */
+#define FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U) /*!< Transmission in spite of cancellation */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_hp_msg_storage FDCAN High Priority Message Storage
+ * @{
+ */
+#define FDCAN_HP_STORAGE_NO_FIFO ((uint32_t)0x00000000U) /*!< No FIFO selected */
+#define FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U) /*!< FIFO message lost */
+#define FDCAN_HP_STORAGE_RXFIFO0 ((uint32_t)0x00000080U) /*!< Message stored in FIFO 0 */
+#define FDCAN_HP_STORAGE_RXFIFO1 ((uint32_t)0x000000C0U) /*!< Message stored in FIFO 1 */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_protocol_error_code FDCAN protocol error code
+ * @{
+ */
+#define FDCAN_PROTOCOL_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error occurred */
+#define FDCAN_PROTOCOL_ERROR_STUFF ((uint32_t)0x00000001U) /*!< Stuff error */
+#define FDCAN_PROTOCOL_ERROR_FORM ((uint32_t)0x00000002U) /*!< Form error */
+#define FDCAN_PROTOCOL_ERROR_ACK ((uint32_t)0x00000003U) /*!< Acknowledge error */
+#define FDCAN_PROTOCOL_ERROR_BIT1 ((uint32_t)0x00000004U) /*!< Bit 1 (recessive) error */
+#define FDCAN_PROTOCOL_ERROR_BIT0 ((uint32_t)0x00000005U) /*!< Bit 0 (dominant) error */
+#define FDCAN_PROTOCOL_ERROR_CRC ((uint32_t)0x00000006U) /*!< CRC check sum error */
+#define FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U) /*!< No change since last read */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_communication_state FDCAN communication state
+ * @{
+ */
+#define FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U) /*!< Node is synchronizing on CAN communication */
+#define FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U) /*!< Node is neither receiver nor transmitter */
+#define FDCAN_COM_STATE_RX ((uint32_t)0x00000010U) /*!< Node is operating as receiver */
+#define FDCAN_COM_STATE_TX ((uint32_t)0x00000018U) /*!< Node is operating as transmitter */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Rx_FIFO_operation_mode FDCAN FIFO operation mode
+ * @{
+ */
+#define FDCAN_RX_FIFO_BLOCKING ((uint32_t)0x00000000U) /*!< Rx FIFO blocking mode */
+#define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x00000001U) /*!< Rx FIFO overwrite mode */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Non_Matching_Frames FDCAN non-matching frames
+ * @{
+ */
+#define FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U) /*!< Accept in Rx FIFO 0 */
+#define FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U) /*!< Accept in Rx FIFO 1 */
+#define FDCAN_REJECT ((uint32_t)0x00000002U) /*!< Reject */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Reject_Remote_Frames FDCAN reject remote frames
+ * @{
+ */
+#define FDCAN_FILTER_REMOTE ((uint32_t)0x00000000U) /*!< Filter remote frames */
+#define FDCAN_REJECT_REMOTE ((uint32_t)0x00000001U) /*!< Reject all remote frames */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Interrupt_Line FDCAN interrupt line
+ * @{
+ */
+#define FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U) /*!< Interrupt Line 0 */
+#define FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U) /*!< Interrupt Line 1 */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Timestamp FDCAN timestamp
+ * @{
+ */
+#define FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U) /*!< Timestamp counter value incremented according to TCP */
+#define FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U) /*!< External timestamp counter value used */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Timestamp_Prescaler FDCAN timestamp prescaler
+ * @{
+ */
+#define FDCAN_TIMESTAMP_PRESC_1 ((uint32_t)0x00000000U) /*!< Timestamp counter time unit in equal to CAN bit time */
+#define FDCAN_TIMESTAMP_PRESC_2 ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 2 */
+#define FDCAN_TIMESTAMP_PRESC_3 ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 3 */
+#define FDCAN_TIMESTAMP_PRESC_4 ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 4 */
+#define FDCAN_TIMESTAMP_PRESC_5 ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 5 */
+#define FDCAN_TIMESTAMP_PRESC_6 ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 6 */
+#define FDCAN_TIMESTAMP_PRESC_7 ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 7 */
+#define FDCAN_TIMESTAMP_PRESC_8 ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 8 */
+#define FDCAN_TIMESTAMP_PRESC_9 ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 9 */
+#define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 10 */
+#define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 11 */
+#define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 12 */
+#define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 13 */
+#define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 14 */
+#define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 15 */
+#define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 16 */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Timeout_Operation FDCAN timeout operation
+ * @{
+ */
+#define FDCAN_TIMEOUT_CONTINUOUS ((uint32_t)0x00000000U) /*!< Timeout continuous operation */
+#define FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U) /*!< Timeout controlled by Tx Event FIFO */
+#define FDCAN_TIMEOUT_RX_FIFO0 ((uint32_t)0x00000004U) /*!< Timeout controlled by Rx FIFO 0 */
+#define FDCAN_TIMEOUT_RX_FIFO1 ((uint32_t)0x00000006U) /*!< Timeout controlled by Rx FIFO 1 */
+/**
+ * @}
+ */
+
+/** @defgroup Interrupt_Masks Interrupt masks
+ * @{
+ */
+#define FDCAN_IR_MASK ((uint32_t)0x00FFFFFFU) /*!< FDCAN interrupts mask */
+#define FDCAN_ILS_MASK ((uint32_t)0x0000007FU) /*!< FDCAN interrupts group mask */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_flags FDCAN Flags
+ * @{
+ */
+#define FDCAN_FLAG_TX_COMPLETE FDCAN_IR_TC /*!< Transmission Completed */
+#define FDCAN_FLAG_TX_ABORT_COMPLETE FDCAN_IR_TCF /*!< Transmission Cancellation Finished */
+#define FDCAN_FLAG_TX_FIFO_EMPTY FDCAN_IR_TFE /*!< Tx FIFO Empty */
+#define FDCAN_FLAG_RX_HIGH_PRIORITY_MSG FDCAN_IR_HPM /*!< High priority message received */
+#define FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST FDCAN_IR_TEFL /*!< Tx Event FIFO element lost */
+#define FDCAN_FLAG_TX_EVT_FIFO_FULL FDCAN_IR_TEFF /*!< Tx Event FIFO full */
+#define FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA FDCAN_IR_TEFN /*!< Tx Handler wrote Tx Event FIFO element */
+#define FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST FDCAN_IR_RF0L /*!< Rx FIFO 0 message lost */
+#define FDCAN_FLAG_RX_FIFO0_FULL FDCAN_IR_RF0F /*!< Rx FIFO 0 full */
+#define FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE FDCAN_IR_RF0N /*!< New message written to Rx FIFO 0 */
+#define FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST FDCAN_IR_RF1L /*!< Rx FIFO 1 message lost */
+#define FDCAN_FLAG_RX_FIFO1_FULL FDCAN_IR_RF1F /*!< Rx FIFO 1 full */
+#define FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE FDCAN_IR_RF1N /*!< New message written to Rx FIFO 1 */
+#define FDCAN_FLAG_RAM_ACCESS_FAILURE FDCAN_IR_MRAF /*!< Message RAM access failure occurred */
+#define FDCAN_FLAG_ERROR_LOGGING_OVERFLOW FDCAN_IR_ELO /*!< Overflow of FDCAN Error Logging Counter occurred */
+#define FDCAN_FLAG_ERROR_PASSIVE FDCAN_IR_EP /*!< Error_Passive status changed */
+#define FDCAN_FLAG_ERROR_WARNING FDCAN_IR_EW /*!< Error_Warning status changed */
+#define FDCAN_FLAG_BUS_OFF FDCAN_IR_BO /*!< Bus_Off status changed */
+#define FDCAN_FLAG_RAM_WATCHDOG FDCAN_IR_WDI /*!< Message RAM Watchdog event due to missing READY */
+#define FDCAN_FLAG_ARB_PROTOCOL_ERROR FDCAN_IR_PEA /*!< Protocol error in arbitration phase detected */
+#define FDCAN_FLAG_DATA_PROTOCOL_ERROR FDCAN_IR_PED /*!< Protocol error in data phase detected */
+#define FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA /*!< Access to reserved address occurred */
+#define FDCAN_FLAG_TIMESTAMP_WRAPAROUND FDCAN_IR_TSW /*!< Timestamp counter wrapped around */
+#define FDCAN_FLAG_TIMEOUT_OCCURRED FDCAN_IR_TOO /*!< Timeout reached */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Interrupts FDCAN Interrupts
+ * @{
+ */
+
+/** @defgroup FDCAN_Tx_Interrupts FDCAN Tx Interrupts
+ * @{
+ */
+#define FDCAN_IT_TX_COMPLETE FDCAN_IE_TCE /*!< Transmission Completed */
+#define FDCAN_IT_TX_ABORT_COMPLETE FDCAN_IE_TCFE /*!< Transmission Cancellation Finished */
+#define FDCAN_IT_TX_FIFO_EMPTY FDCAN_IE_TFEE /*!< Tx FIFO Empty */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Rx_Interrupts FDCAN Rx Interrupts
+ * @{
+ */
+#define FDCAN_IT_RX_HIGH_PRIORITY_MSG FDCAN_IE_HPME /*!< High priority message received */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Counter_Interrupts FDCAN Counter Interrupts
+ * @{
+ */
+#define FDCAN_IT_TIMESTAMP_WRAPAROUND FDCAN_IE_TSWE /*!< Timestamp counter wrapped around */
+#define FDCAN_IT_TIMEOUT_OCCURRED FDCAN_IE_TOOE /*!< Timeout reached */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Tx_Event_Fifo_Interrupts FDCAN Tx Event FIFO Interrupts
+ * @{
+ */
+#define FDCAN_IT_TX_EVT_FIFO_ELT_LOST FDCAN_IE_TEFLE /*!< Tx Event FIFO element lost */
+#define FDCAN_IT_TX_EVT_FIFO_FULL FDCAN_IE_TEFFE /*!< Tx Event FIFO full */
+#define FDCAN_IT_TX_EVT_FIFO_NEW_DATA FDCAN_IE_TEFNE /*!< Tx Handler wrote Tx Event FIFO element */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Rx_Fifo0_Interrupts FDCAN Rx FIFO 0 Interrupts
+ * @{
+ */
+#define FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE /*!< Rx FIFO 0 message lost */
+#define FDCAN_IT_RX_FIFO0_FULL FDCAN_IE_RF0FE /*!< Rx FIFO 0 full */
+#define FDCAN_IT_RX_FIFO0_NEW_MESSAGE FDCAN_IE_RF0NE /*!< New message written to Rx FIFO 0 */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Rx_Fifo1_Interrupts FDCAN Rx FIFO 1 Interrupts
+ * @{
+ */
+#define FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE /*!< Rx FIFO 1 message lost */
+#define FDCAN_IT_RX_FIFO1_FULL FDCAN_IE_RF1FE /*!< Rx FIFO 1 full */
+#define FDCAN_IT_RX_FIFO1_NEW_MESSAGE FDCAN_IE_RF1NE /*!< New message written to Rx FIFO 1 */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Error_Interrupts FDCAN Error Interrupts
+ * @{
+ */
+#define FDCAN_IT_RAM_ACCESS_FAILURE FDCAN_IE_MRAFE /*!< Message RAM access failure occurred */
+#define FDCAN_IT_ERROR_LOGGING_OVERFLOW FDCAN_IE_ELOE /*!< Overflow of FDCAN Error Logging Counter occurred */
+#define FDCAN_IT_RAM_WATCHDOG FDCAN_IE_WDIE /*!< Message RAM Watchdog event due to missing READY */
+#define FDCAN_IT_ARB_PROTOCOL_ERROR FDCAN_IE_PEAE /*!< Protocol error in arbitration phase detected */
+#define FDCAN_IT_DATA_PROTOCOL_ERROR FDCAN_IE_PEDE /*!< Protocol error in data phase detected */
+#define FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE /*!< Access to reserved address occurred */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Error_Status_Interrupts FDCAN Error Status Interrupts
+ * @{
+ */
+#define FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE /*!< Error_Passive status changed */
+#define FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE /*!< Error_Warning status changed */
+#define FDCAN_IT_BUS_OFF FDCAN_IE_BOE /*!< Bus_Off status changed */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Interrupts_List FDCAN Interrupts List
+ * @{
+ */
+#define FDCAN_IT_LIST_RX_FIFO0 (FDCAN_IT_RX_FIFO0_MESSAGE_LOST | \
+ FDCAN_IT_RX_FIFO0_FULL | \
+ FDCAN_IT_RX_FIFO0_NEW_MESSAGE) /*!< RX FIFO 0 Interrupts List */
+#define FDCAN_IT_LIST_RX_FIFO1 (FDCAN_IT_RX_FIFO1_MESSAGE_LOST | \
+ FDCAN_IT_RX_FIFO1_FULL | \
+ FDCAN_IT_RX_FIFO1_NEW_MESSAGE) /*!< RX FIFO 1 Interrupts List */
+#define FDCAN_IT_LIST_SMSG (FDCAN_IT_TX_ABORT_COMPLETE | \
+ FDCAN_IT_TX_COMPLETE | \
+ FDCAN_IT_RX_HIGH_PRIORITY_MSG) /*!< Status Message Interrupts List */
+#define FDCAN_IT_LIST_TX_FIFO_ERROR (FDCAN_IT_TX_EVT_FIFO_ELT_LOST | \
+ FDCAN_IT_TX_EVT_FIFO_FULL | \
+ FDCAN_IT_TX_EVT_FIFO_NEW_DATA | \
+ FDCAN_IT_TX_FIFO_EMPTY) /*!< TX FIFO Error Interrupts List */
+#define FDCAN_IT_LIST_MISC (FDCAN_IT_TIMEOUT_OCCURRED | \
+ FDCAN_IT_RAM_ACCESS_FAILURE | \
+ FDCAN_IT_TIMESTAMP_WRAPAROUND) /*!< Misc. Interrupts List */
+#define FDCAN_IT_LIST_BIT_LINE_ERROR (FDCAN_IT_ERROR_PASSIVE | \
+ FDCAN_IT_ERROR_LOGGING_OVERFLOW) /*!< Bit and Line Error Interrupts List */
+#define FDCAN_IT_LIST_PROTOCOL_ERROR (FDCAN_IT_RESERVED_ADDRESS_ACCESS | \
+ FDCAN_IT_DATA_PROTOCOL_ERROR | \
+ FDCAN_IT_ARB_PROTOCOL_ERROR | \
+ FDCAN_IT_RAM_WATCHDOG | \
+ FDCAN_IT_BUS_OFF | \
+ FDCAN_IT_ERROR_WARNING) /*!< Protocol Error Interrupts List */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Interrupts_Group FDCAN Interrupts Group
+ * @{
+ */
+#define FDCAN_IT_GROUP_RX_FIFO0 FDCAN_ILS_RXFIFO0 /*!< RX FIFO 0 Interrupts Group:
+ RF0LL: Rx FIFO 0 Message Lost
+ RF0FL: Rx FIFO 0 is Full
+ RF0NL: Rx FIFO 0 Has New Message */
+#define FDCAN_IT_GROUP_RX_FIFO1 FDCAN_ILS_RXFIFO1 /*!< RX FIFO 1 Interrupts Group:
+ RF1LL: Rx FIFO 1 Message Lost
+ RF1FL: Rx FIFO 1 is Full
+ RF1NL: Rx FIFO 1 Has New Message */
+#define FDCAN_IT_GROUP_SMSG FDCAN_ILS_SMSG /*!< Status Message Interrupts Group:
+ TCFL: Transmission Cancellation Finished
+ TCL: Transmission Completed
+ HPML: High Priority Message */
+#define FDCAN_IT_GROUP_TX_FIFO_ERROR FDCAN_ILS_TFERR /*!< TX FIFO Error Interrupts Group:
+ TEFLL: Tx Event FIFO Element Lost
+ TEFFL: Tx Event FIFO Full
+ TEFNL: Tx Event FIFO New Entry
+ TFEL: Tx FIFO Empty Interrupt Line */
+#define FDCAN_IT_GROUP_MISC FDCAN_ILS_MISC /*!< Misc. Interrupts Group:
+ TOOL: Timeout Occurred
+ MRAFL: Message RAM Access Failure
+ TSWL: Timestamp Wraparound */
+#define FDCAN_IT_GROUP_BIT_LINE_ERROR FDCAN_ILS_BERR /*!< Bit and Line Error Interrupts Group:
+ EPL: Error Passive
+ ELOL: Error Logging Overflow */
+#define FDCAN_IT_GROUP_PROTOCOL_ERROR FDCAN_ILS_PERR /*!< Protocol Error Group:
+ ARAL: Access to Reserved Address Line
+ PEDL: Protocol Error in Data Phase Line
+ PEAL: Protocol Error in Arbitration Phase Line
+ WDIL: Watchdog Interrupt Line
+ BOL: Bus_Off Status
+ EWL: Warning Status */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup FDCAN_Exported_Macros FDCAN Exported Macros
+ * @{
+ */
+
+/** @brief Reset FDCAN handle state.
+ * @param __HANDLE__ FDCAN handle.
+ * @retval None
+ */
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_FDCAN_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FDCAN_STATE_RESET)
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+/**
+ * @brief Enable the specified FDCAN interrupts.
+ * @param __HANDLE__ FDCAN handle.
+ * @param __INTERRUPT__ FDCAN interrupt.
+ * This parameter can be any combination of @arg FDCAN_Interrupts
+ * @retval None
+ */
+#define __HAL_FDCAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (__HANDLE__)->Instance->IE |= (__INTERRUPT__)
+
+/**
+ * @brief Disable the specified FDCAN interrupts.
+ * @param __HANDLE__ FDCAN handle.
+ * @param __INTERRUPT__ FDCAN interrupt.
+ * This parameter can be any combination of @arg FDCAN_Interrupts
+ * @retval None
+ */
+#define __HAL_FDCAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
+ ((__HANDLE__)->Instance->IE) &= ~(__INTERRUPT__)
+
+/**
+ * @brief Check whether the specified FDCAN interrupt is set or not.
+ * @param __HANDLE__ FDCAN handle.
+ * @param __INTERRUPT__ FDCAN interrupt.
+ * This parameter can be one of @arg FDCAN_Interrupts
+ * @retval ITStatus
+ */
+#define __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IR & (__INTERRUPT__))
+
+/**
+ * @brief Clear the specified FDCAN interrupts.
+ * @param __HANDLE__ FDCAN handle.
+ * @param __INTERRUPT__ specifies the interrupts to clear.
+ * This parameter can be any combination of @arg FDCAN_Interrupts
+ * @retval None
+ */
+#define __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__) \
+ ((__HANDLE__)->Instance->IR) = (__INTERRUPT__)
+
+/**
+ * @brief Check whether the specified FDCAN flag is set or not.
+ * @param __HANDLE__ FDCAN handle.
+ * @param __FLAG__ FDCAN flag.
+ * This parameter can be one of @arg FDCAN_flags
+ * @retval FlagStatus
+ */
+#define __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IR & (__FLAG__))
+
+/**
+ * @brief Clear the specified FDCAN flags.
+ * @param __HANDLE__ FDCAN handle.
+ * @param __FLAG__ specifies the flags to clear.
+ * This parameter can be any combination of @arg FDCAN_flags
+ * @retval None
+ */
+#define __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+ ((__HANDLE__)->Instance->IR) = (__FLAG__)
+
+/** @brief Check if the specified FDCAN interrupt source is enabled or disabled.
+ * @param __HANDLE__ FDCAN handle.
+ * @param __INTERRUPT__ specifies the FDCAN interrupt source to check.
+ * This parameter can be a value of @arg FDCAN_Interrupts
+ * @retval ITStatus
+ */
+#define __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IE & (__INTERRUPT__))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FDCAN_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup FDCAN_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+/* Callbacks Register/UnRegister functions ***********************************/
+HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID,
+ pFDCAN_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan,
+ pFDCAN_TxEventFifoCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan,
+ pFDCAN_RxFifo0CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan,
+ pFDCAN_RxFifo1CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan,
+ pFDCAN_TxBufferCompleteCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan,
+ pFDCAN_TxBufferAbortCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan,
+ pFDCAN_ErrorStatusCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @addtogroup FDCAN_Exported_Functions_Group2
+ * @{
+ */
+/* Configuration functions ****************************************************/
+HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig);
+HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd,
+ uint32_t NonMatchingExt, uint32_t RejectRemoteStd,
+ uint32_t RejectRemoteExt);
+HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask);
+HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode);
+HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue);
+HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler);
+HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation);
+HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
+uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation,
+ uint32_t TimeoutPeriod);
+HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
+uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset,
+ uint32_t TdcFilter);
+HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);
+/**
+ * @}
+ */
+
+/** @addtogroup FDCAN_Exported_Functions_Group3
+ * @{
+ */
+/* Control functions **********************************************************/
+HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader,
+ uint8_t *pTxData);
+uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);
+HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation,
+ FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData);
+HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent);
+HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan,
+ FDCAN_HpMsgStatusTypeDef *HpMsgStatus);
+HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus);
+HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters);
+uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex);
+uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo);
+uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan);
+uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
+/**
+ * @}
+ */
+
+/** @addtogroup FDCAN_Exported_Functions_Group4
+ * @{
+ */
+/* Interrupts management ******************************************************/
+HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine);
+HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs,
+ uint32_t BufferIndexes);
+HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs);
+void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan);
+/**
+ * @}
+ */
+
+/** @addtogroup FDCAN_Exported_Functions_Group5
+ * @{
+ */
+/* Callback functions *********************************************************/
+void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);
+void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);
+void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);
+void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);
+void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);
+void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs);
+/**
+ * @}
+ */
+
+/** @addtogroup FDCAN_Exported_Functions_Group6
+ * @{
+ */
+/* Peripheral State functions *************************************************/
+uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan);
+HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Variables FDCAN Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Constants FDCAN Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Macros FDCAN Private Macros
+ * @{
+ */
+#define IS_FDCAN_FRAME_FORMAT(FORMAT) (((FORMAT) == FDCAN_FRAME_CLASSIC ) || \
+ ((FORMAT) == FDCAN_FRAME_FD_NO_BRS) || \
+ ((FORMAT) == FDCAN_FRAME_FD_BRS ))
+#define IS_FDCAN_MODE(MODE) (((MODE) == FDCAN_MODE_NORMAL ) || \
+ ((MODE) == FDCAN_MODE_RESTRICTED_OPERATION) || \
+ ((MODE) == FDCAN_MODE_BUS_MONITORING ) || \
+ ((MODE) == FDCAN_MODE_INTERNAL_LOOPBACK ) || \
+ ((MODE) == FDCAN_MODE_EXTERNAL_LOOPBACK ))
+#define IS_FDCAN_CKDIV(CKDIV) (((CKDIV) == FDCAN_CLOCK_DIV1 ) || \
+ ((CKDIV) == FDCAN_CLOCK_DIV2 ) || \
+ ((CKDIV) == FDCAN_CLOCK_DIV4 ) || \
+ ((CKDIV) == FDCAN_CLOCK_DIV6 ) || \
+ ((CKDIV) == FDCAN_CLOCK_DIV8 ) || \
+ ((CKDIV) == FDCAN_CLOCK_DIV10) || \
+ ((CKDIV) == FDCAN_CLOCK_DIV12) || \
+ ((CKDIV) == FDCAN_CLOCK_DIV14) || \
+ ((CKDIV) == FDCAN_CLOCK_DIV16) || \
+ ((CKDIV) == FDCAN_CLOCK_DIV18) || \
+ ((CKDIV) == FDCAN_CLOCK_DIV20) || \
+ ((CKDIV) == FDCAN_CLOCK_DIV22) || \
+ ((CKDIV) == FDCAN_CLOCK_DIV24) || \
+ ((CKDIV) == FDCAN_CLOCK_DIV26) || \
+ ((CKDIV) == FDCAN_CLOCK_DIV28) || \
+ ((CKDIV) == FDCAN_CLOCK_DIV30))
+#define IS_FDCAN_NOMINAL_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 512U))
+#define IS_FDCAN_NOMINAL_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 128U))
+#define IS_FDCAN_NOMINAL_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 256U))
+#define IS_FDCAN_NOMINAL_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 128U))
+#define IS_FDCAN_DATA_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 32U))
+#define IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U))
+#define IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U))
+#define IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U))
+#define IS_FDCAN_MAX_VALUE(VALUE, _MAX_) ((VALUE) <= (_MAX_))
+#define IS_FDCAN_MIN_VALUE(VALUE, _MIN_) ((VALUE) >= (_MIN_))
+#define IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE) (((MODE) == FDCAN_TX_FIFO_OPERATION ) || \
+ ((MODE) == FDCAN_TX_QUEUE_OPERATION))
+#define IS_FDCAN_ID_TYPE(ID_TYPE) (((ID_TYPE) == FDCAN_STANDARD_ID) || \
+ ((ID_TYPE) == FDCAN_EXTENDED_ID))
+#define IS_FDCAN_FILTER_CFG(CONFIG) (((CONFIG) == FDCAN_FILTER_DISABLE ) || \
+ ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0 ) || \
+ ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1 ) || \
+ ((CONFIG) == FDCAN_FILTER_REJECT ) || \
+ ((CONFIG) == FDCAN_FILTER_HP ) || \
+ ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0_HP) || \
+ ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1_HP))
+#define IS_FDCAN_TX_LOCATION(LOCATION) (((LOCATION) == FDCAN_TX_BUFFER0 ) || ((LOCATION) == FDCAN_TX_BUFFER1 ) || \
+ ((LOCATION) == FDCAN_TX_BUFFER2 ))
+#define IS_FDCAN_TX_LOCATION_LIST(LOCATION) (((LOCATION) >= FDCAN_TX_BUFFER0) && \
+ ((LOCATION) <= (FDCAN_TX_BUFFER0 | FDCAN_TX_BUFFER1 | FDCAN_TX_BUFFER2)))
+#define IS_FDCAN_RX_FIFO(FIFO) (((FIFO) == FDCAN_RX_FIFO0) || \
+ ((FIFO) == FDCAN_RX_FIFO1))
+#define IS_FDCAN_RX_FIFO_MODE(MODE) (((MODE) == FDCAN_RX_FIFO_BLOCKING ) || \
+ ((MODE) == FDCAN_RX_FIFO_OVERWRITE))
+#define IS_FDCAN_STD_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE) || \
+ ((TYPE) == FDCAN_FILTER_DUAL ) || \
+ ((TYPE) == FDCAN_FILTER_MASK ))
+#define IS_FDCAN_EXT_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE ) || \
+ ((TYPE) == FDCAN_FILTER_DUAL ) || \
+ ((TYPE) == FDCAN_FILTER_MASK ) || \
+ ((TYPE) == FDCAN_FILTER_RANGE_NO_EIDM))
+#define IS_FDCAN_FRAME_TYPE(TYPE) (((TYPE) == FDCAN_DATA_FRAME ) || \
+ ((TYPE) == FDCAN_REMOTE_FRAME))
+#define IS_FDCAN_DLC(DLC) (((DLC) == FDCAN_DLC_BYTES_0 ) || \
+ ((DLC) == FDCAN_DLC_BYTES_1 ) || \
+ ((DLC) == FDCAN_DLC_BYTES_2 ) || \
+ ((DLC) == FDCAN_DLC_BYTES_3 ) || \
+ ((DLC) == FDCAN_DLC_BYTES_4 ) || \
+ ((DLC) == FDCAN_DLC_BYTES_5 ) || \
+ ((DLC) == FDCAN_DLC_BYTES_6 ) || \
+ ((DLC) == FDCAN_DLC_BYTES_7 ) || \
+ ((DLC) == FDCAN_DLC_BYTES_8 ) || \
+ ((DLC) == FDCAN_DLC_BYTES_12) || \
+ ((DLC) == FDCAN_DLC_BYTES_16) || \
+ ((DLC) == FDCAN_DLC_BYTES_20) || \
+ ((DLC) == FDCAN_DLC_BYTES_24) || \
+ ((DLC) == FDCAN_DLC_BYTES_32) || \
+ ((DLC) == FDCAN_DLC_BYTES_48) || \
+ ((DLC) == FDCAN_DLC_BYTES_64))
+#define IS_FDCAN_ESI(ESI) (((ESI) == FDCAN_ESI_ACTIVE ) || \
+ ((ESI) == FDCAN_ESI_PASSIVE))
+#define IS_FDCAN_BRS(BRS) (((BRS) == FDCAN_BRS_OFF) || \
+ ((BRS) == FDCAN_BRS_ON ))
+#define IS_FDCAN_FDF(FDF) (((FDF) == FDCAN_CLASSIC_CAN) || \
+ ((FDF) == FDCAN_FD_CAN ))
+#define IS_FDCAN_EFC(EFC) (((EFC) == FDCAN_NO_TX_EVENTS ) || \
+ ((EFC) == FDCAN_STORE_TX_EVENTS))
+#define IS_FDCAN_IT(IT) (((IT) & ~(FDCAN_IR_MASK)) == 0U)
+#define IS_FDCAN_IT_GROUP(IT_GROUP) (((IT_GROUP) & ~(FDCAN_ILS_MASK)) == 0U)
+#define IS_FDCAN_NON_MATCHING(DESTINATION) (((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO0) || \
+ ((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO1) || \
+ ((DESTINATION) == FDCAN_REJECT ))
+#define IS_FDCAN_REJECT_REMOTE(DESTINATION) (((DESTINATION) == FDCAN_FILTER_REMOTE) || \
+ ((DESTINATION) == FDCAN_REJECT_REMOTE))
+#define IS_FDCAN_IT_LINE(IT_LINE) (((IT_LINE) == FDCAN_INTERRUPT_LINE0) || \
+ ((IT_LINE) == FDCAN_INTERRUPT_LINE1))
+#define IS_FDCAN_TIMESTAMP(OPERATION) (((OPERATION) == FDCAN_TIMESTAMP_INTERNAL) || \
+ ((OPERATION) == FDCAN_TIMESTAMP_EXTERNAL))
+#define IS_FDCAN_TIMESTAMP_PRESCALER(PRESCALER) (((PRESCALER) == FDCAN_TIMESTAMP_PRESC_1 ) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_2 ) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_3 ) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_4 ) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_5 ) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_6 ) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_7 ) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_8 ) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_9 ) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_10) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_11) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_12) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_13) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_14) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_15) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_16))
+#define IS_FDCAN_TIMEOUT(OPERATION) (((OPERATION) == FDCAN_TIMEOUT_CONTINUOUS ) || \
+ ((OPERATION) == FDCAN_TIMEOUT_TX_EVENT_FIFO) || \
+ ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO0 ) || \
+ ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO1 ))
+/**
+ * @}
+ */
+
+/* Private functions prototypes ----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* FDCAN1 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_FDCAN_H */
+
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_flash.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_flash.h
new file mode 100644
index 00000000..f83f65ea
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_flash.h
@@ -0,0 +1,1120 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_flash.h
+ * @author MCD Application Team
+ * @brief Header file of FLASH HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_FLASH_H
+#define STM32U5xx_HAL_FLASH_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FLASH
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Types FLASH Exported Types
+ * @{
+ */
+
+/**
+ * @brief FLASH Erase structure definition
+ */
+typedef struct
+{
+ uint32_t TypeErase; /*!< Mass erase or page erase.
+ This parameter can be a value of @ref FLASH_Type_Erase */
+ uint32_t Banks; /*!< Select bank to erase.
+ This parameter must be a value of @ref FLASH_Banks
+ (FLASH_BANK_BOTH should be used only for mass erase) */
+ uint32_t Page; /*!< Initial Flash page to erase when page erase is disabled
+ This parameter must be a value between 0 and (max number of pages in the bank - 1)
+ (eg : 127 for 2MB dual bank) */
+ uint32_t NbPages; /*!< Number of pages to be erased. This parameter must be a value between 1 and
+ (max number of pages in the bank - value of initial page)*/
+} FLASH_EraseInitTypeDef;
+
+/**
+ * @brief FLASH Option Bytes Program structure definition
+ */
+typedef struct
+{
+ uint32_t OptionType; /*!< Option byte to be configured.
+ This parameter can be a combination of the values of @ref FLASH_OB_Type */
+ uint32_t WRPArea; /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP).
+ Only one WRP area could be programmed at the same time.
+ This parameter can be value of @ref FLASH_OB_WRP_Area */
+ uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP).
+ This parameter must be a value between 0 and (max number of pages in the bank - 1) */
+ uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP).
+ This parameter must be a value between WRPStartOffset
+ and (max number of pages in the bank - 1) */
+ FunctionalState WRPLock; /*!< Write protection lock (used for OPTIONBYTE_WRP).
+ This parameter can be set to ENABLE or DISABLE */
+ uint32_t RDPLevel; /*!< Set the read protection level (used for OPTIONBYTE_RDP).
+ This parameter can be a value of @ref FLASH_OB_Read_Protection */
+ uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).
+ This parameter can be a combination of @ref FLASH_OB_USER_Type */
+ uint32_t USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER).
+ This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,
+ @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
+ @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM134_RST,
+ @ref FLASH_OB_USER_IWDG_SW, @ref FLASH_OB_USER_IWDG_STOP,
+ @ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_WWDG_SW,
+ @ref FLASH_OB_USER_SWAP_BANK, @ref FLASH_OB_USER_DUALBANK,
+ @ref FLASH_OB_USER_BKPRAM_RST, @ref FLASH_OB_USER_SRAM3_ECC,
+ @ref FLASH_OB_USER_SRAM2_ECC, @ref FLASH_OB_USER_SRAM2_RST,
+ @ref FLASH_OB_USER_nSWBOOT0, @ref FLASH_OB_USER_nBOOT0,
+ @ref FLASH_OB_USER_PA15_PUPEN, @ref FLASH_OB_USER_IO_VDD_HSLV,
+ @ref FLASH_OB_USER_IO_VDDIO2_HSLV, @ref FLASH_OB_USER_TZEN */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ uint32_t WMSecConfig; /*!< Configuration of the Watermark-based Secure Area (used for OPTIONBYTE_WMSEC).
+ This parameter must be a value of @ref FLASH_OB_WMSEC */
+ uint32_t WMSecStartPage; /*!< Start page of secure area (used for OPTIONBYTE_WMSEC).
+ This parameter must be a value between 0 and (max number of pages in the bank - 1) */
+ uint32_t WMSecEndPage; /*!< End page of secure area (used for OPTIONBYTE_WMSEC). This parameter must be a value
+ between WMSecStartPage and (max number of pages in the bank - 1) */
+ uint32_t WMHDPEndPage; /*!< End page of the secure hide protection (used for OPTIONBYTE_WMSEC).
+ This parameter must be a value between WMSecStartPage and WMSecEndPage */
+ uint32_t BootLock; /*!< Configuration of the boot lock (used for OPTIONBYTE_BOOT_LOCK).
+ This parameter must be a value of @ref FLASH_OB_BOOT_LOCK */
+#endif /* __ARM_FEATURE_CMSE */
+ uint32_t BootAddrConfig; /*!< Configuration of the Boot address (used for OPTIONBYTE_BOOTADDR).
+ This parameter must be a value of @ref FLASH_OB_BOOTADDR */
+ uint32_t BootAddr; /*!< Boot address (used for OPTIONBYTE_BOOTADDR).
+ This parameter must be a value between 0x0 and 0xFFFFFF00 */
+ uint32_t RDPKeyType; /*!< Configuration of the RDP OEM keys (used for OPTIONBYTE_RDPKEY).
+ This parameter can be a value of @ref FLASH_OB_RDP_Key_Type */
+ uint32_t RDPKey1; /*!< Value of the RDP OEM key 1 (used for OPTIONBYTE_RDPKEY) */
+ uint32_t RDPKey2; /*!< Value of the RDP OEM key 2 (used for OPTIONBYTE_RDPKEY) */
+} FLASH_OBProgramInitTypeDef;
+
+/**
+ * @brief FLASH handle Structure definition
+ */
+typedef struct
+{
+ HAL_LockTypeDef Lock; /* FLASH locking object */
+ uint32_t ErrorCode; /* FLASH error code */
+ uint32_t ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing
+ or not in IT context */
+ uint32_t Address; /* Internal variable to save address selected for program
+ in IT context */
+ uint32_t Bank; /* Internal variable to save current bank selected during erase
+ in IT context */
+ uint32_t Page; /* Internal variable to define the current page which is being erased
+ in IT context */
+ uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */
+} FLASH_ProcessTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
+ * @{
+ */
+
+/** @defgroup FLASH_Flags FLASH Flags Definition
+ * @{
+ */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define FLASH_FLAG_EOP FLASH_SECSR_EOP /*!< FLASH End of operation flag */
+#define FLASH_FLAG_OPERR FLASH_SECSR_OPERR /*!< FLASH Operation error flag */
+#define FLASH_FLAG_PROGERR FLASH_SECSR_PROGERR /*!< FLASH Programming error flag */
+#define FLASH_FLAG_WRPERR FLASH_SECSR_WRPERR /*!< FLASH Write protection error flag */
+#define FLASH_FLAG_PGAERR FLASH_SECSR_PGAERR /*!< FLASH Programming alignment error flag */
+#define FLASH_FLAG_SIZERR FLASH_SECSR_SIZERR /*!< FLASH Size error flag */
+#define FLASH_FLAG_PGSERR FLASH_SECSR_PGSERR /*!< FLASH Programming sequence error flag */
+#define FLASH_FLAG_OPTWERR FLASH_NSSR_OPTWERR /*!< FLASH Option modification error flag */
+#define FLASH_FLAG_BSY FLASH_SECSR_BSY /*!< FLASH Busy flag */
+#define FLASH_FLAG_WDW FLASH_SECSR_WDW /*!< FLASH Wait Data to Write flag */
+#define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction */
+#define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC detection */
+
+#define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \
+ FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR)
+#define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)
+#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_OPTWERR | FLASH_FLAG_ECCR_ERRORS)
+#else
+#define FLASH_FLAG_EOP FLASH_NSSR_EOP /*!< FLASH End of operation flag */
+#define FLASH_FLAG_OPERR FLASH_NSSR_OPERR /*!< FLASH Operation error flag */
+#define FLASH_FLAG_PROGERR FLASH_NSSR_PROGERR /*!< FLASH Programming error flag */
+#define FLASH_FLAG_WRPERR FLASH_NSSR_WRPERR /*!< FLASH Write protection error flag */
+#define FLASH_FLAG_PGAERR FLASH_NSSR_PGAERR /*!< FLASH Programming alignment error flag */
+#define FLASH_FLAG_SIZERR FLASH_NSSR_SIZERR /*!< FLASH Size error flag */
+#define FLASH_FLAG_PGSERR FLASH_NSSR_PGSERR /*!< FLASH Programming sequence error flag */
+#define FLASH_FLAG_OPTWERR FLASH_NSSR_OPTWERR /*!< FLASH Option modification error flag */
+#define FLASH_FLAG_BSY FLASH_NSSR_BSY /*!< FLASH Busy flag */
+#define FLASH_FLAG_WDW FLASH_NSSR_WDW /*!< FLASH Wait Data to Write flag */
+#define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction */
+#define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC detection */
+
+#define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \
+ FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \
+ FLASH_FLAG_OPTWERR)
+#define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)
+#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_ECCR_ERRORS)
+#endif /* __ARM_FEATURE_CMSE */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition
+ * @brief FLASH Interrupt definition
+ * @{
+ */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define FLASH_IT_EOP FLASH_SECCR_EOPIE /*!< End of FLASH Operation Interrupt source */
+#define FLASH_IT_OPERR FLASH_SECCR_ERRIE /*!< Error Interrupt source */
+#define FLASH_IT_ECCC (FLASH_ECCR_ECCIE >> 24) /*!< ECC Correction Interrupt source */
+#else
+#define FLASH_IT_EOP FLASH_NSCR_EOPIE /*!< End of FLASH Operation Interrupt source */
+#define FLASH_IT_OPERR FLASH_NSCR_ERRIE /*!< Error Interrupt source */
+#define FLASH_IT_ECCC (FLASH_ECCR_ECCIE >> 24) /*!< ECC Correction Interrupt source */
+#endif /* __ARM_FEATURE_CMSE */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Error FLASH Error
+ * @{
+ */
+#define HAL_FLASH_ERROR_NONE 0x00000000U
+#define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR
+#define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR
+#define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR
+#define HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR
+#define HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR
+#define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR
+#define HAL_FLASH_ERROR_OPTW FLASH_FLAG_OPTWERR
+#define HAL_FLASH_ERROR_ECCC FLASH_FLAG_ECCC
+#define HAL_FLASH_ERROR_ECCD FLASH_FLAG_ECCD
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Type_Erase FLASH Erase Type
+ * @{
+ */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define FLASH_TYPEERASE_PAGES FLASH_SECCR_PER /*!< Secure pages erase
+ activation */
+#define FLASH_TYPEERASE_PAGES_NS (FLASH_NSCR_PER | FLASH_NON_SECURE_MASK) /*!< Non-secure pages erase
+ activation */
+#define FLASH_TYPEERASE_MASSERASE (FLASH_SECCR_MER1 | FLASH_SECCR_MER2) /*!< Secure flash mass erase
+ activation */
+#define FLASH_TYPEERASE_MASSERASE_NS (FLASH_NSCR_MER1 | FLASH_NSCR_MER2 | FLASH_NON_SECURE_MASK) /*!< Non-secure flash
+ mass erase activation */
+#else
+#define FLASH_TYPEERASE_PAGES FLASH_NSCR_PER /*!< Pages erase activation */
+#define FLASH_TYPEERASE_MASSERASE (FLASH_NSCR_MER1 | FLASH_NSCR_MER2) /*!< Flash mass erase activation */
+#endif /* __ARM_FEATURE_CMSE */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Banks FLASH Banks
+ * @{
+ */
+#define FLASH_BANK_1 0x00000001U /*!< Bank 1 */
+#define FLASH_BANK_2 0x00000002U /*!< Bank 2 */
+#define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Type_Program FLASH Program Type
+ * @{
+ */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define FLASH_TYPEPROGRAM_QUADWORD FLASH_SECCR_PG /*!< Program a quad-word (128-bit)
+ at a specified secure address */
+#define FLASH_TYPEPROGRAM_QUADWORD_NS (FLASH_NSCR_PG | FLASH_NON_SECURE_MASK) /*!< Program a quad-word (128-bit)
+ at a specified non-secure address */
+#define FLASH_TYPEPROGRAM_BURST (FLASH_SECCR_PG | FLASH_SECCR_BWR) /*!< Program a burst (8xquad-word)
+ at a specified secure address */
+#define FLASH_TYPEPROGRAM_BURST_NS (FLASH_NSCR_PG | FLASH_NSCR_BWR | FLASH_NON_SECURE_MASK) /*!< Program a burst
+(8xquad-word) at a specified non-secure address */
+#else
+#define FLASH_TYPEPROGRAM_QUADWORD FLASH_NSCR_PG /*!ACR, FLASH_ACR_LATENCY, (__LATENCY__))
+
+/**
+ * @brief Get the FLASH Latency.
+ * @retval FLASH Latency
+ * This return value can be one of the following values :
+ * @arg FLASH_LATENCY_0: FLASH Zero wait state
+ * @arg FLASH_LATENCY_1: FLASH One wait state
+ * @arg FLASH_LATENCY_2: FLASH Two wait states
+ * @arg FLASH_LATENCY_3: FLASH Three wait states
+ * @arg FLASH_LATENCY_4: FLASH Four wait states
+ * @arg FLASH_LATENCY_5: FLASH Five wait states
+ * @arg FLASH_LATENCY_6: FLASH Six wait states
+ * @arg FLASH_LATENCY_7: FLASH Seven wait states
+ * @arg FLASH_LATENCY_8: FLASH Eight wait states
+ * @arg FLASH_LATENCY_9: FLASH Nine wait states
+ * @arg FLASH_LATENCY_10: FLASH Ten wait states
+ * @arg FLASH_LATENCY_11: FLASH Eleven wait states
+ * @arg FLASH_LATENCY_12: FLASH Twelve wait states
+ * @arg FLASH_LATENCY_13: FLASH Thirteen wait states
+ * @arg FLASH_LATENCY_14: FLASH Fourteen wait states
+ * @arg FLASH_LATENCY_15: FLASH Fifteen wait states
+ */
+#define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)
+
+/**
+ * @brief Enable the FLASH prefetch buffer.
+ * @retval None
+ */
+#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
+
+/**
+ * @brief Disable the FLASH prefetch buffer.
+ * @retval None
+ */
+#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
+
+/**
+ * @brief Enable the FLASH power down during Low-Power sleep mode
+ * @retval none
+ */
+#define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
+
+/**
+ * @brief Disable the FLASH power down during Low-Power sleep mode
+ * @retval none
+ */
+#define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Interrupt FLASH Interrupts Macros
+ * @brief macros to handle FLASH interrupts
+ * @{
+ */
+
+/**
+ * @brief Enable the specified FLASH interrupt.
+ * @param __INTERRUPT__ FLASH interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
+ * @arg FLASH_IT_OPERR: Error Interrupt
+ * @arg FLASH_IT_ECCC: ECC Correction Interrupt
+ * @retval none
+ */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/* Enable secure FLASH interrupts from the secure world */
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \
+ { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); } \
+ if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \
+ { SET_BIT(FLASH->SECCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
+ } while(0)
+/* Enable non-secure FLASH interrupts from the secure world */
+#define __HAL_FLASH_ENABLE_IT_NS(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \
+ { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); } \
+ if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \
+ { SET_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
+ } while(0)
+#else
+/* Enable non-secure FLASH interrupts from the non-secure world */
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \
+ { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); } \
+ if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \
+ { SET_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
+ } while(0)
+#endif /* __ARM_FEATURE_CMSE */
+
+/**
+ * @brief Disable the specified FLASH interrupt.
+ * @param __INTERRUPT__ FLASH interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
+ * @arg FLASH_IT_OPERR: Error Interrupt
+ * @arg FLASH_IT_ECCC: ECC Correction Interrupt
+ * @retval none
+ */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/* Disable secure FLASH interrupts from the secure world */
+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \
+ { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); } \
+ if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \
+ { CLEAR_BIT(FLASH->SECCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC)));}\
+ } while(0)
+/* Disable non-secure FLASH interrupts from the secure world */
+#define __HAL_FLASH_DISABLE_IT_NS(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \
+ { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); } \
+ if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \
+ { CLEAR_BIT(FLASH->NSCR, ((__INTERRUPT__) & \
+ (~FLASH_IT_ECCC))); }\
+ } while(0)
+#else
+/* Disable non-secure FLASH interrupts from the non-secure world */
+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \
+ { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
+ if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \
+ { CLEAR_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
+ } while(0)
+#endif /* __ARM_FEATURE_CMSE */
+
+/**
+ * @brief Check whether the specified FLASH flag is set or not.
+ * @param __FLAG__ specifies the FLASH flag to check.
+ * This parameter can be one of the following values:
+ * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
+ * @arg FLASH_FLAG_OPERR: FLASH Operation error flag
+ * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
+ * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag
+ * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
+ * @arg FLASH_FLAG_SIZERR: FLASH Size error flag
+ * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
+ * @arg FLASH_FLAG_OPTWERR: FLASH Option modification error flag
+ * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag
+ * @arg FLASH_FLAG_WDW: FLASH Wait Data to Write flag
+ * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected
+ * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected
+ * @retval The new state of FLASH_FLAG (SET or RESET).
+ */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/* Get secure FLASH flags from the secure world */
+#define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) ? \
+ (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \
+ ((((__FLAG__) & (FLASH_FLAG_OPTWERR)) != 0U) ? \
+ (READ_BIT(FLASH->NSSR, (__FLAG__)) == (__FLAG__)) : \
+ (READ_BIT(FLASH->SECSR, (__FLAG__)) == (__FLAG__))))
+/* Get non-secure FLASH flags from the secure world */
+#define __HAL_FLASH_GET_FLAG_NS(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) ? \
+ (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \
+ (READ_BIT(FLASH->NSSR, (__FLAG__)) == (__FLAG__)))
+#else
+/* Get non-secure FLASH flags from the non-secure world */
+#define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) ? \
+ (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \
+ (READ_BIT(FLASH->NSSR, (__FLAG__)) == (__FLAG__)))
+#endif /* __ARM_FEATURE_CMSE */
+
+/**
+ * @brief Clear the FLASH's pending flags.
+ * @param __FLAG__ specifies the FLASH flags to clear.
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
+ * @arg FLASH_FLAG_OPERR: FLASH Operation error flag
+ * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
+ * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag
+ * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
+ * @arg FLASH_FLAG_SIZERR: FLASH Size error flag
+ * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
+ * @arg FLASH_FLAG_OPTWERR: FLASH Option modification error flag (Only in non-secure)
+ * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected
+ * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected
+ * @arg FLASH_FLAG_ALL_ERRORS: FLASH All errors flags
+ * @retval None
+ */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/* Clear secure FLASH flags from the secure world */
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) \
+ { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\
+ if(((__FLAG__) & FLASH_FLAG_OPTWERR) != 0U) \
+ { SET_BIT(FLASH->NSSR, ((__FLAG__) & (FLASH_FLAG_OPTWERR))); }\
+ if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS | \
+ FLASH_FLAG_OPTWERR)) != 0U) \
+ { WRITE_REG(FLASH->SECSR, ((__FLAG__) & \
+ ~(FLASH_FLAG_ECCR_ERRORS | FLASH_FLAG_OPTWERR))); }\
+ } while(0)
+/* Clear non-secure FLASH flags from the secure world */
+#define __HAL_FLASH_CLEAR_FLAG_NS(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) \
+ { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\
+ if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) \
+ { WRITE_REG(FLASH->NSSR, ((__FLAG__) & \
+ ~(FLASH_FLAG_ECCR_ERRORS))); }\
+ } while(0)
+#else
+/* Clear non-secure FLASH flags from the non-secure world */
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) \
+ { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\
+ if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) \
+ { WRITE_REG(FLASH->NSSR, ((__FLAG__) & \
+ ~(FLASH_FLAG_ECCR_ERRORS))); }\
+ } while(0)
+#endif /* __ARM_FEATURE_CMSE */
+/**
+ * @}
+ */
+
+/* Include FLASH HAL Extended module */
+#include "stm32u5xx_hal_flash_ex.h"
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASH_Exported_Functions
+ * @{
+ */
+
+/* Program operation functions ***********************************************/
+/** @addtogroup FLASH_Exported_Functions_Group1
+ * @{
+ */
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t DataAddress);
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t DataAddress);
+/* FLASH IRQ handler method */
+void HAL_FLASH_IRQHandler(void);
+/* Callbacks in non blocking modes */
+void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
+void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
+/**
+ * @}
+ */
+
+/* Peripheral Control functions **********************************************/
+/** @addtogroup FLASH_Exported_Functions_Group2
+ * @{
+ */
+HAL_StatusTypeDef HAL_FLASH_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_Lock(void);
+/* Option bytes control */
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
+/**
+ * @}
+ */
+
+/* Peripheral State functions ************************************************/
+/** @addtogroup FLASH_Exported_Functions_Group3
+ * @{
+ */
+uint32_t HAL_FLASH_GetError(void);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @addtogroup FLASH_Private_Variables FLASH Private Variables
+ * @{
+ */
+extern FLASH_ProcessTypeDef pFlash;
+/**
+ * @}
+ */
+
+/* Private constants --------------------------------------------------------*/
+/** @defgroup FLASH_Private_Constants FLASH Private Constants
+ * @{
+ */
+
+#define FLASH_TIMEOUT_VALUE 1000U /* 1 s */
+
+#define FLASH_NON_SECURE_MASK 0x80000000U
+
+#define FLASH_NB_WORDS_IN_BURST 32
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FLASH_Private_Macros FLASH Private Macros
+ * @{
+ */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \
+ ((VALUE) == FLASH_TYPEERASE_PAGES_NS) || \
+ ((VALUE) == FLASH_TYPEERASE_MASSERASE) || \
+ ((VALUE) == FLASH_TYPEERASE_MASSERASE_NS))
+#else
+#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \
+ ((VALUE) == FLASH_TYPEERASE_MASSERASE))
+#endif /* __ARM_FEATURE_CMSE */
+
+#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
+ ((BANK) == FLASH_BANK_2) || \
+ ((BANK) == FLASH_BANK_BOTH))
+
+#define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \
+ ((BANK) == FLASH_BANK_2))
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_QUADWORD) || \
+ ((VALUE) == FLASH_TYPEPROGRAM_QUADWORD_NS) || \
+ ((VALUE) == FLASH_TYPEPROGRAM_BURST) || \
+ ((VALUE) == FLASH_TYPEPROGRAM_BURST_NS))
+#else
+#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_QUADWORD) || \
+ ((VALUE) == FLASH_TYPEPROGRAM_BURST))
+#endif /* __ARM_FEATURE_CMSE */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE+FLASH_SIZE))) || \
+ (((ADDRESS) >= FLASH_BASE_NS) && ((ADDRESS) < (FLASH_BASE_NS+FLASH_SIZE))))
+#else
+#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE+FLASH_SIZE)))
+#endif /* __ARM_FEATURE_CMSE */
+
+#define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_OTP_BASE)\
+ && ((ADDRESS) < (FLASH_OTP_BASE + FLASH_OTP_SIZE)))
+
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) ((IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS)) || (IS_FLASH_OTP_ADDRESS(ADDRESS)))
+
+#define IS_FLASH_PAGE(PAGE) ((PAGE) < FLASH_PAGE_NB)
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | \
+ OPTIONBYTE_WMSEC | OPTIONBYTE_BOOT_LOCK | OPTIONBYTE_BOOTADDR | \
+ OPTIONBYTE_RDPKEY)))
+#else
+#define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | \
+ OPTIONBYTE_BOOTADDR | OPTIONBYTE_RDPKEY)))
+#endif /* __ARM_FEATURE_CMSE */
+
+#define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \
+ ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB))
+
+#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
+ ((LEVEL) == OB_RDP_LEVEL_0_5) ||\
+ ((LEVEL) == OB_RDP_LEVEL_1) ||\
+ ((LEVEL) == OB_RDP_LEVEL_2))
+
+#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= 0x1FFFFFU) && ((TYPE) != 0U))
+
+#define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \
+ ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \
+ ((LEVEL) == OB_BOR_LEVEL_4))
+
+#define IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST))
+
+#define IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST))
+
+#define IS_OB_USER_SHUTDOWN(VALUE) (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST))
+
+#define IS_OB_USER_SRAM134_RST(VALUE) (((VALUE) == OB_SRAM134_RST_ERASE) || ((VALUE) == OB_SRAM134_RST_NOT_ERASE))
+
+#define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW))
+
+#define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN))
+
+#define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN))
+
+#define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW))
+
+#define IS_OB_USER_SWAP_BANK(VALUE) (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE))
+
+#define IS_OB_USER_DUALBANK(VALUE) (((VALUE) == OB_DUALBANK_SINGLE) || ((VALUE) == OB_DUALBANK_DUAL))
+
+#define IS_OB_USER_BKPRAM_ECC(VALUE) (((VALUE) == OB_BKPRAM_ECC_ENABLE) || ((VALUE) == OB_BKPRAM_ECC_DISABLE))
+
+#define IS_OB_USER_SRAM3_ECC(VALUE) (((VALUE) == OB_SRAM3_ECC_ENABLE) || ((VALUE) == OB_SRAM3_ECC_DISABLE))
+
+#define IS_OB_USER_SRAM2_ECC(VALUE) (((VALUE) == OB_SRAM2_ECC_ENABLE) || ((VALUE) == OB_SRAM2_ECC_DISABLE))
+
+#define IS_OB_USER_SRAM2_RST(VALUE) (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE))
+
+#define IS_OB_USER_SWBOOT0(VALUE) (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN))
+
+#define IS_OB_USER_BOOT0(VALUE) (((VALUE) == OB_NBOOT0_RESET) || ((VALUE) == OB_NBOOT0_SET))
+
+#define IS_OB_USER_PA15_PUPEN(VALUE) (((VALUE) == OB_PA15_PUP_DISABLE) || ((VALUE) == OB_PA15_PUP_ENABLE))
+
+#define IS_OB_USER_IO_VDD_HSLV(VALUE) (((VALUE) == OB_IO_VDD_HSLV_DISABLE) || ((VALUE) == OB_IO_VDD_HSLV_ENABLE))
+
+#define IS_OB_USER_IO_VDDIO2_HSLV(VALUE) (((VALUE) == OB_IO_VDDIO2_HSLV_DISABLE)\
+ || ((VALUE) == OB_IO_VDDIO2_HSLV_ENABLE))
+
+#define IS_OB_USER_TZEN(VALUE) (((VALUE) == OB_TZEN_DISABLE) || ((VALUE) == OB_TZEN_ENABLE))
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define IS_OB_BOOT_LOCK(VALUE) (((VALUE) == OB_BOOT_LOCK_DISABLE) || ((VALUE) == OB_BOOT_LOCK_ENABLE))
+
+#define IS_OB_WMSEC_CONFIG(CFG) ((((CFG) & 0x7F3U) != 0U) && \
+ (((CFG) & 0x3U) != 0U) && (((CFG) & 0xFFFFF80CU) == 0U))
+
+#define IS_OB_WMSEC_AREA_EXCLUSIVE(WMSEC) (((((WMSEC) & OB_WMSEC_AREA1) != 0U) && \
+ (((WMSEC) & OB_WMSEC_AREA2) == 0U)) || \
+ ((((WMSEC) & OB_WMSEC_AREA2) != 0U) && \
+ (((WMSEC) & OB_WMSEC_AREA1) == 0U)))
+#endif /* __ARM_FEATURE_CMSE */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define IS_OB_BOOTADDR_CONFIG(CFG) (((CFG) == OB_BOOTADDR_NS0) || ((CFG) == OB_BOOTADDR_NS1) || \
+ ((CFG) == OB_BOOTADDR_SEC0))
+#else
+#define IS_OB_BOOTADDR_CONFIG(CFG) (((CFG) == OB_BOOTADDR_NS0) || ((CFG) == OB_BOOTADDR_NS1))
+#endif /* __ARM_FEATURE_CMSE */
+
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || \
+ ((LATENCY) == FLASH_LATENCY_2) || ((LATENCY) == FLASH_LATENCY_3) || \
+ ((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5) || \
+ ((LATENCY) == FLASH_LATENCY_6) || ((LATENCY) == FLASH_LATENCY_7) || \
+ ((LATENCY) == FLASH_LATENCY_8) || ((LATENCY) == FLASH_LATENCY_9) || \
+ ((LATENCY) == FLASH_LATENCY_10) || ((LATENCY) == FLASH_LATENCY_11) || \
+ ((LATENCY) == FLASH_LATENCY_12) || ((LATENCY) == FLASH_LATENCY_13) || \
+ ((LATENCY) == FLASH_LATENCY_14) || ((LATENCY) == FLASH_LATENCY_15))
+
+#define IS_OB_RDP_KEY_TYPE(TYPE) (((TYPE) == OB_RDP_KEY_OEM1) || \
+ ((TYPE) == OB_RDP_KEY_OEM2))
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define IS_FLASH_SECURE_OPERATION() ((pFlash.ProcedureOnGoing & FLASH_NON_SECURE_MASK) == 0U)
+#else
+#define IS_FLASH_SECURE_OPERATION() (0U)
+#endif /* __ARM_FEATURE_CMSE */
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup FLASH_Private_Functions FLASH Private Functions
+ * @{
+ */
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_FLASH_H */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_flash_ex.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_flash_ex.h
new file mode 100644
index 00000000..6add95ac
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_flash_ex.h
@@ -0,0 +1,240 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_flash_ex.h
+ * @author MCD Application Team
+ * @brief Header file of FLASH HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_FLASH_EX_H
+#define STM32U5xx_HAL_FLASH_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FLASHEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @addtogroup FLASHEx_Exported_Types FLASHEx Exported Types
+ * @{
+ */
+
+/**
+ * @brief FLASHEx Block-based attributes structure definition
+ */
+
+typedef struct
+{
+ uint32_t Bank; /*!< Selection of the associated bank of Block-based Area.
+ This parameter must be a value of @ref FLASH_Banks */
+ uint32_t BBAttributesType; /*!< Block-Based Attributes type. This parameter must
+ be a value of @ref FLASH_BB_Attributes */
+ uint32_t BBAttributes_array[FLASH_BLOCKBASED_NB_REG]; /*!< Each bit specifies the block-based attribute configuration
+ of a page: 0 means page non-protected, 1 means page
+ protected. Protection (secure or privilege) depends
+ on BBAttributesType value */
+} FLASH_BBAttributesTypeDef;
+
+
+/**
+ * @brief FLASHEx Operation structure definition
+ */
+typedef struct
+{
+ uint32_t OperationType; /*!< Flash operation Type.
+ This parameter must be a value of @ref FLASH_Operation_Type */
+ uint32_t FlashArea; /*!< Flash operation memory area.
+ This parameter must be a value of @ref FLASH_Operation_Area */
+ uint32_t Address; /*!< Flash operation Address offset.
+ This parameter is given by bank, and must be a value between 0x0 and 0xFFFF0 */
+} FLASH_OperationTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @addtogroup FLASHEx_Exported_Constants
+ * @{
+ */
+/** @defgroup PRIV_MODE_CFG FLASH privilege mode configuration
+ * @{
+ */
+#define FLASH_NSPRIV_GRANTED 0x00000000U /*!< access to non-secure Flash registers is granted
+ to privileged or unprivileged access */
+#define FLASH_NSPRIV_DENIED FLASH_PRIVCFGR_NSPRIV /*!< access to non-secure Flash registers is denied
+ to non-privilege access */
+#define FLASH_SPRIV_GRANTED 0x00000000U /*!< access to secure Flash registers is granted to privileged
+ or unprivileged access */
+#define FLASH_SPRIV_DENIED FLASH_PRIVCFGR_SPRIV /*!< access to secure Flash registers is denied
+ to non-privilege access */
+/**
+ * @}
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/** @defgroup SEC_INVERSION_CFG FLASH security inversion configuration
+ * @{
+ */
+#define FLASH_INV_DISABLE 0x00000000U /*!< Security state of Flash is not inverted */
+#define FLASH_INV_ENABLE FLASH_SECCR_INV /*!< Security state of Flash is inverted */
+/**
+ * @}
+ */
+#endif /* __ARM_FEATURE_CMSE */
+
+/** @defgroup FLASH_LPM_CFG FLASH LPM configuration
+ * @{
+ */
+#define FLASH_LPM_DISABLE 0x00000000U /*!< Flash is in normal read mode */
+#define FLASH_LPM_ENABLE FLASH_ACR_LPM /*!< Flash is in low-power read mode */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_BB_Attributes FLASH Block-Base Attributes
+ * @{
+ */
+#define FLASH_BB_SEC 0x01U /*!< Flash Block-Based Security Attributes */
+#define FLASH_BB_PRIV 0x02U /*!< Flash Block-Based Privilege Attributes */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Operation_Type FLASH Operation Type
+ * @{
+ */
+#define FLASH_OPERATION_TYPE_NONE 00000000U /*!< No Flash operation */
+#define FLASH_OPERATION_TYPE_QUADWORD FLASH_OPSR_CODE_OP_0 /*!< Single write operation */
+#define FLASH_OPERATION_TYPE_BURST FLASH_OPSR_CODE_OP_1 /*!< Burst write operation */
+#define FLASH_OPERATION_TYPE_PAGEERASE (FLASH_OPSR_CODE_OP_1 | FLASH_OPSR_CODE_OP_0) /*!< Page erase operation */
+#define FLASH_OPERATION_TYPE_BANKERASE FLASH_OPSR_CODE_OP_2 /*!< Bank erase operation */
+#define FLASH_OPERATION_TYPE_MASSERASE (FLASH_OPSR_CODE_OP_2 | FLASH_OPSR_CODE_OP_0) /*!< Mass erase operation */
+#define FLASH_OPERATION_TYPE_OPTIONCHANGE (FLASH_OPSR_CODE_OP_2 | FLASH_OPSR_CODE_OP_1) /*!< Option change operation */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Operation_Area FLASH Operation Area
+ * @{
+ */
+#define FLASH_OPERATION_AREA_BANK_1 00000000U /*!< Operation in Bank 1 */
+#define FLASH_OPERATION_AREA_BANK_2 FLASH_OPSR_BK_OP /*!< Operation in Bank 2 */
+#define FLASH_OPERATION_AREA_SYSF FLASH_OPSR_SYSF_OP /*!< Operation in System Flash memory */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASHEx_Exported_Functions
+ * @{
+ */
+
+/* Extended Program operation functions *************************************/
+/** @addtogroup FLASHEx_Exported_Functions_Group1
+ * @{
+ */
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
+HAL_StatusTypeDef HAL_FLASHEx_ConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes);
+void HAL_FLASHEx_GetConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes);
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+void HAL_FLASHEx_EnableSecHideProtection(uint32_t Banks);
+#endif /* __ARM_FEATURE_CMSE */
+/**
+ * @}
+ */
+
+/** @addtogroup FLASHEx_Exported_Functions_Group2
+ * @{
+ */
+void HAL_FLASHEx_ConfigPrivMode(uint32_t PrivMode);
+uint32_t HAL_FLASHEx_GetPrivMode(void);
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+HAL_StatusTypeDef HAL_FLASHEx_ConfigSecInversion(uint32_t SecInvState);
+uint32_t HAL_FLASHEx_GetSecInversion(void);
+#endif /* __ARM_FEATURE_CMSE */
+HAL_StatusTypeDef HAL_FLASHEx_EnablePowerDown(uint32_t Banks);
+HAL_StatusTypeDef HAL_FLASHEx_ConfigLowPowerRead(uint32_t ConfigLPM);
+uint32_t HAL_FLASHEx_GetLowPowerRead(void);
+void HAL_FLASHEx_GetOperation(FLASH_OperationTypeDef *pFlashOperation);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private function ----------------------------------------------------------*/
+/** @addtogroup FLASHEx_Private_Functions FLASHEx Private Functions
+ * @{
+ */
+void FLASH_PageErase(uint32_t Page, uint32_t Banks);
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Macros FLASH Private Macros
+ * @{
+ */
+#define IS_FLASH_BB_EXCLUSIVE(CFG) (((CFG) == FLASH_BB_SEC) || \
+ ((CFG) == FLASH_BB_PRIV))
+
+#define IS_FLASH_CFGPRIVMODE(CFG) (((CFG) & 0xFFFFFFFCU) == 0U)
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define IS_FLASH_CFGSECINV(CFG) (((CFG) == FLASH_INV_DISABLE) || \
+ ((CFG) == FLASH_INV_ENABLE))
+#endif /* __ARM_FEATURE_CMSE */
+
+#define IS_FLASH_CFGLPM(CFG) (((CFG) == FLASH_LPM_DISABLE) || \
+ ((CFG) == FLASH_LPM_ENABLE))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_FLASH_EX_H */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_fmac.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_fmac.h
new file mode 100644
index 00000000..4e9bb73d
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_fmac.h
@@ -0,0 +1,690 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_fmac.h
+ * @author MCD Application Team
+ * @brief Header for stm32u5xx_hal_fmac.c module
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_FMAC_H
+#define STM32U5xx_HAL_FMAC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+#if defined(FMAC)
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FMAC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FMAC_Exported_Types FMAC Exported Types
+ * @{
+ */
+
+/**
+ * @brief FMAC HAL State Structure definition
+ */
+typedef enum
+{
+ HAL_FMAC_STATE_RESET = 0x00U, /*!< FMAC not yet initialized or disabled */
+ HAL_FMAC_STATE_READY = 0x20U, /*!< FMAC initialized and ready for use */
+ HAL_FMAC_STATE_BUSY = 0x24U, /*!< FMAC internal process is ongoing */
+ HAL_FMAC_STATE_BUSY_RD = 0x25U, /*!< FMAC reading configuration is ongoing */
+ HAL_FMAC_STATE_BUSY_WR = 0x26U, /*!< FMAC writing configuration is ongoing */
+ HAL_FMAC_STATE_TIMEOUT = 0xA0U, /*!< FMAC in Timeout state */
+ HAL_FMAC_STATE_ERROR = 0xE0U /*!< FMAC in Error state */
+} HAL_FMAC_StateTypeDef;
+
+/**
+ * @brief FMAC Handle Structure definition
+ */
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+typedef struct __FMAC_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
+{
+ FMAC_TypeDef *Instance; /*!< Register base address */
+
+ uint32_t FilterParam; /*!< Filter configuration (operation and parameters).
+ Set to 0 if no valid configuration was applied. */
+
+ uint8_t InputAccess; /*!< Access to the input buffer (internal memory area): DMA, IT, Polling, None.
+ This parameter can be a value of @ref FMAC_Buffer_Access. */
+
+ uint8_t OutputAccess; /*!< Access to the output buffer (internal memory area): DMA, IT, Polling, None.
+ This parameter can be a value of @ref FMAC_Buffer_Access. */
+
+ int16_t *pInput; /*!< Pointer to FMAC input data buffer */
+
+ uint16_t InputCurrentSize; /*!< Number of the input elements already written into FMAC */
+
+ uint16_t *pInputSize; /*!< Number of input elements to write (memory allocated to pInput).
+ In case of early interruption of the filter operation,
+ its value will be updated. */
+
+ int16_t *pOutput; /*!< Pointer to FMAC output data buffer */
+
+ uint16_t OutputCurrentSize; /*!< Number of the output elements already read from FMAC */
+
+ uint16_t *pOutputSize; /*!< Number of output elements to read (memory allocated to pOutput).
+ In case of early interruption of the filter operation,
+ its value will be updated. */
+
+ DMA_HandleTypeDef *hdmaIn; /*!< FMAC peripheral input data DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmaOut; /*!< FMAC peripheral output data DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmaPreload; /*!< FMAC peripheral preloaded data (X1, X2 and Y) DMA handle parameters */
+
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+ void (* ErrorCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC error callback */
+
+ void (* HalfGetDataCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC get half data callback */
+
+ void (* GetDataCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC get data callback */
+
+ void (* HalfOutputDataReadyCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC half output data ready callback */
+
+ void (* OutputDataReadyCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC output data ready callback */
+
+ void (* FilterConfigCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC filter configuration callback */
+
+ void (* FilterPreloadCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC filter preload callback */
+
+ void (* MspInitCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC Msp Init callback */
+
+ void (* MspDeInitCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC Msp DeInit callback */
+
+#endif /* (USE_HAL_FMAC_REGISTER_CALLBACKS) */
+
+ HAL_LockTypeDef Lock; /*!< FMAC locking object */
+
+ __IO HAL_FMAC_StateTypeDef State; /*!< FMAC state related to global handle management
+ This parameter can be a value of @ref HAL_FMAC_StateTypeDef */
+
+ __IO HAL_FMAC_StateTypeDef RdState; /*!< FMAC state related to read operations (access to Y buffer)
+ This parameter can be a value of @ref HAL_FMAC_StateTypeDef */
+
+ __IO HAL_FMAC_StateTypeDef WrState; /*!< FMAC state related to write operations (access to X1 buffer)
+ This parameter can be a value of @ref HAL_FMAC_StateTypeDef */
+
+ __IO uint32_t ErrorCode; /*!< FMAC peripheral error code
+ This parameter can be a value of @ref FMAC_Error_Code */
+
+} FMAC_HandleTypeDef;
+
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief FMAC Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_FMAC_ERROR_CB_ID = 0x00U, /*!< FMAC error callback ID */
+ HAL_FMAC_HALF_GET_DATA_CB_ID = 0x01U, /*!< FMAC get half data callback ID */
+ HAL_FMAC_GET_DATA_CB_ID = 0x02U, /*!< FMAC get data callback ID */
+ HAL_FMAC_HALF_OUTPUT_DATA_READY_CB_ID = 0x03U, /*!< FMAC half output data ready callback ID */
+ HAL_FMAC_OUTPUT_DATA_READY_CB_ID = 0x04U, /*!< FMAC output data ready callback ID */
+ HAL_FMAC_FILTER_CONFIG_CB_ID = 0x05U, /*!< FMAC filter configuration callback ID */
+ HAL_FMAC_FILTER_PRELOAD_CB_ID = 0x06U, /*!< FMAC filter preload callback ID */
+
+ HAL_FMAC_MSPINIT_CB_ID = 0x07U, /*!< FMAC MspInit callback ID */
+ HAL_FMAC_MSPDEINIT_CB_ID = 0x08U, /*!< FMAC MspDeInit callback ID */
+} HAL_FMAC_CallbackIDTypeDef;
+
+/**
+ * @brief HAL FMAC Callback pointer definition
+ */
+typedef void (*pFMAC_CallbackTypeDef)(FMAC_HandleTypeDef *hfmac); /*!< pointer to an FMAC callback function */
+
+#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
+
+/**
+ * @brief FMAC Filter Configuration Structure definition
+ */
+typedef struct
+{
+ uint8_t InputBaseAddress; /*!< Base address of the input buffer (X1) within the internal memory (0x00 to 0xFF).
+ Ignored if InputBufferSize is set to 0
+ (previous configuration kept).
+ Note: the buffers can overlap or even coincide exactly. */
+
+ uint8_t InputBufferSize; /*!< Number of 16-bit words allocated to the input buffer (including the optional "headroom").
+ 0 if a previous configuration should be kept. */
+
+ uint32_t InputThreshold; /*!< Input threshold: the buffer full flag will be set if the number of free spaces
+ in the buffer is lower than this threshold.
+ This parameter can be a value
+ of @ref FMAC_Data_Buffer_Threshold. */
+
+ uint8_t CoeffBaseAddress; /*!< Base address of the coefficient buffer (X2) within the internal memory (0x00 to 0xFF).
+ Ignored if CoeffBufferSize is set to 0
+ (previous configuration kept).
+ Note: the buffers can overlap or even coincide exactly. */
+
+ uint8_t CoeffBufferSize; /*!< Number of 16-bit words allocated to the coefficient buffer.
+ 0 if a previous configuration should be kept. */
+
+ uint8_t OutputBaseAddress; /*!< Base address of the output buffer (Y) within the internal memory (0x00 to 0xFF).
+ Ignored if OuputBufferSize is set to 0
+ (previous configuration kept).
+ Note: the buffers can overlap or even coincide exactly. */
+
+ uint8_t OutputBufferSize; /*!< Number of 16-bit words allocated to the output buffer (including the optional "headroom").
+ 0 if a previous configuration should be kept. */
+
+ uint32_t OutputThreshold; /*!< Output threshold: the buffer empty flag will be set if the number of unread values
+ in the buffer is lower than this threshold.
+ This parameter can be a value
+ of @ref FMAC_Data_Buffer_Threshold. */
+
+ int16_t *pCoeffA; /*!< [IIR only] Initialization of the coefficient vector A.
+ If not needed, it should be set to NULL. */
+
+ uint8_t CoeffASize; /*!< Size of the coefficient vector A. */
+
+ int16_t *pCoeffB; /*!< Initialization of the coefficient vector B.
+ If not needed (re-use of a previously loaded buffer),
+ it should be set to NULL. */
+
+ uint8_t CoeffBSize; /*!< Size of the coefficient vector B. */
+
+ uint8_t InputAccess; /*!< Access to the input buffer (internal memory area): DMA, IT, Polling, None.
+ This parameter can be a value of @ref FMAC_Buffer_Access. */
+
+ uint8_t OutputAccess; /*!< Access to the output buffer (internal memory area): DMA, IT, Polling, None.
+ This parameter can be a value of @ref FMAC_Buffer_Access. */
+
+ uint32_t Clip; /*!< Enable or disable the clipping feature. If the q1.15 range is exceeded, wrapping
+ is done when the clipping feature is disabled
+ and saturation is done when the clipping feature is enabled.
+ This parameter can be a value of @ref FMAC_Clip_State. */
+
+ uint32_t Filter; /*!< Filter type.
+ This parameter can be a value
+ of @ref FMAC_Functions (filter related values). */
+
+ uint8_t P; /*!< Parameter P (vector length, number of filter taps, etc.). */
+
+ uint8_t Q; /*!< Parameter Q (vector length, etc.). Ignored if not needed. */
+
+ uint8_t R; /*!< Parameter R (gain, etc.). Ignored if not needed. */
+
+} FMAC_FilterConfigTypeDef;
+
+/**
+ * @}
+ */
+
+
+/* Exported constants --------------------------------------------------------*/
+
+
+/** @defgroup FMAC_Exported_Constants FMAC Exported Constants
+ * @{
+ */
+
+/** @defgroup FMAC_Error_Code FMAC Error code
+ * @{
+ */
+#define HAL_FMAC_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_FMAC_ERROR_SAT 0x00000001U /*!< Saturation error */
+#define HAL_FMAC_ERROR_UNFL 0x00000002U /*!< Underflow error */
+#define HAL_FMAC_ERROR_OVFL 0x00000004U /*!< Overflow error */
+#define HAL_FMAC_ERROR_DMA 0x00000008U /*!< DMA error */
+#define HAL_FMAC_ERROR_RESET 0x00000010U /*!< Reset error */
+#define HAL_FMAC_ERROR_PARAM 0x00000020U /*!< Parameter error */
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+#define HAL_FMAC_ERROR_INVALID_CALLBACK 0x00000040U /*!< Invalid Callback error */
+#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
+#define HAL_FMAC_ERROR_TIMEOUT 0x00000080U /*!< Timeout error */
+
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_Functions FMAC Functions
+ * @{
+ */
+#define FMAC_FUNC_LOAD_X1 (FMAC_PARAM_FUNC_0) /*!< Load X1 buffer */
+#define FMAC_FUNC_LOAD_X2 (FMAC_PARAM_FUNC_1) /*!< Load X2 buffer */
+#define FMAC_FUNC_LOAD_Y (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0) /*!< Load Y buffer */
+#define FMAC_FUNC_CONVO_FIR (FMAC_PARAM_FUNC_3) /*!< Convolution (FIR filter) */
+#define FMAC_FUNC_IIR_DIRECT_FORM_1 (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0) /*!< IIR filter (direct form 1) */
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_Data_Buffer_Threshold FMAC Data Buffer Threshold
+ * @{
+ * @note This parameter sets a watermark for buffer full (input) or buffer empty (output).
+ */
+#define FMAC_THRESHOLD_1 0x00000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 1.
+ Output: Buffer empty flag set if the number
+ of unread values in the buffer is less than 1. */
+#define FMAC_THRESHOLD_2 0x01000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 2.
+ Output: Buffer empty flag set if the number
+ of unread values in the buffer is less than 2. */
+#define FMAC_THRESHOLD_4 0x02000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 4.
+ Output: Buffer empty flag set if the number
+ of unread values in the buffer is less than 4. */
+#define FMAC_THRESHOLD_8 0x03000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 8.
+ Output: Buffer empty flag set if the number
+ of unread values in the buffer is less than 8. */
+#define FMAC_THRESHOLD_NO_VALUE 0xFFFFFFFFU /*!< The configured threshold value shouldn't be changed */
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_Buffer_Access FMAC Buffer Access
+ * @{
+ */
+#define FMAC_BUFFER_ACCESS_NONE 0x00U /*!< Buffer handled by an external IP (ADC for instance) */
+#define FMAC_BUFFER_ACCESS_DMA 0x01U /*!< Buffer accessed through DMA */
+#define FMAC_BUFFER_ACCESS_POLLING 0x02U /*!< Buffer accessed through polling */
+#define FMAC_BUFFER_ACCESS_IT 0x03U /*!< Buffer accessed through interruptions */
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_Clip_State FMAC Clip State
+ * @{
+ */
+#define FMAC_CLIP_DISABLED 0x00000000U /*!< Clipping disabled */
+#define FMAC_CLIP_ENABLED FMAC_CR_CLIPEN /*!< Clipping enabled */
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_Flags FMAC status flags
+ * @{
+ */
+#define FMAC_FLAG_YEMPTY FMAC_SR_YEMPTY /*!< Y Buffer Empty Flag */
+#define FMAC_FLAG_X1FULL FMAC_SR_X1FULL /*!< X1 Buffer Full Flag */
+#define FMAC_FLAG_OVFL FMAC_SR_OVFL /*!< Overflow Error Flag */
+#define FMAC_FLAG_UNFL FMAC_SR_UNFL /*!< Underflow Error Flag */
+#define FMAC_FLAG_SAT FMAC_SR_SAT /*!< Saturation Error Flag (this helps in debugging a filter) */
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_Interrupts_Enable FMAC Interrupts Enable bit
+ * @{
+ */
+#define FMAC_IT_RIEN FMAC_CR_RIEN /*!< Read Interrupt Enable */
+#define FMAC_IT_WIEN FMAC_CR_WIEN /*!< Write Interrupt Enable */
+#define FMAC_IT_OVFLIEN FMAC_CR_OVFLIEN /*!< Overflow Error Interrupt Enable */
+#define FMAC_IT_UNFLIEN FMAC_CR_UNFLIEN /*!< Underflow Error Interrupt Enable */
+#define FMAC_IT_SATIEN FMAC_CR_SATIEN /*!< Saturation Error Interrupt Enable (this helps in debugging a filter) */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* External variables --------------------------------------------------------*/
+/** @defgroup FMAC_External_variables FMAC External variables
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup FMAC_Exported_Macros FMAC Exported Macros
+ * @{
+ */
+
+/** @brief Reset FMAC handle state.
+ * @param __HANDLE__ FMAC handle.
+ * @retval None
+ */
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+#define __HAL_FMAC_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_FMAC_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0U)
+#else
+#define __HAL_FMAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMAC_STATE_RESET)
+#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
+
+/**
+ * @brief Enable the specified FMAC interrupt
+ * @param __HANDLE__ FMAC handle.
+ * @param __INTERRUPT__ FMAC Interrupt.
+ * This parameter can be any combination of the following values:
+ * @arg @ref FMAC_IT_RIEN Read interrupt enable
+ * @arg @ref FMAC_IT_WIEN Write interrupt enable
+ * @arg @ref FMAC_IT_OVFLIEN Overflow error interrupt enable
+ * @arg @ref FMAC_IT_UNFLIEN Underflow error interrupt enable
+ * @arg @ref FMAC_IT_SATIEN Saturation error interrupt enable (this helps in debugging a filter)
+ * @retval None
+ */
+#define __HAL_FMAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the FMAC interrupt
+ * @param __HANDLE__ FMAC handle.
+ * @param __INTERRUPT__ FMAC Interrupt.
+ * This parameter can be any combination of the following values:
+ * @arg @ref FMAC_IT_RIEN Read interrupt enable
+ * @arg @ref FMAC_IT_WIEN Write interrupt enable
+ * @arg @ref FMAC_IT_OVFLIEN Overflow error interrupt enable
+ * @arg @ref FMAC_IT_UNFLIEN Underflow error interrupt enable
+ * @arg @ref FMAC_IT_SATIEN Saturation error interrupt enable (this helps in debugging a filter)
+ * @retval None
+ */
+#define __HAL_FMAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
+
+/** @brief Check whether the specified FMAC interrupt occurred or not.
+ * @param __HANDLE__ FMAC handle.
+ * @param __INTERRUPT__ FMAC interrupt to check.
+ * This parameter can be any combination of the following values:
+ * @arg @ref FMAC_FLAG_YEMPTY Y Buffer Empty Flag
+ * @arg @ref FMAC_FLAG_X1FULL X1 Buffer Full Flag
+ * @arg @ref FMAC_FLAG_OVFL Overflow Error Flag
+ * @arg @ref FMAC_FLAG_UNFL Underflow Error Flag
+ * @arg @ref FMAC_FLAG_SAT Saturation Error Flag
+ * @retval SET (interrupt occurred) or RESET (interrupt did not occurred)
+ */
+#define __HAL_FMAC_GET_IT(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->SR) &= ~(__INTERRUPT__))
+
+/** @brief Clear specified FMAC interrupt status. Dummy macro as the
+ interrupt status flags are read-only.
+ * @param __HANDLE__ FMAC handle.
+ * @param __INTERRUPT__ FMAC interrupt to clear.
+ * @retval None
+ */
+#define __HAL_FMAC_CLEAR_IT(__HANDLE__, __INTERRUPT__) /* Dummy macro */
+
+/** @brief Check whether the specified FMAC status flag is set or not.
+ * @param __HANDLE__ FMAC handle.
+ * @param __FLAG__ FMAC flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg @ref FMAC_FLAG_YEMPTY Y Buffer Empty Flag
+ * @arg @ref FMAC_FLAG_X1FULL X1 Buffer Full Flag
+ * @arg @ref FMAC_FLAG_OVFL Overflow Error Flag
+ * @arg @ref FMAC_FLAG_UNFL Underflow Error Flag
+ * @arg @ref FMAC_FLAG_SAT Saturation error Flag
+ * @retval SET (flag is set) or RESET (flag is reset)
+ */
+#define __HAL_FMAC_GET_FLAG(__HANDLE__, __FLAG__) \
+ ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear specified FMAC status flag. Dummy macro as no
+ flag can be cleared.
+ * @param __HANDLE__ FMAC handle.
+ * @param __FLAG__ FMAC flag to clear.
+ * @retval None
+ */
+#define __HAL_FMAC_CLEAR_FLAG(__HANDLE__, __FLAG__) /* Dummy macro */
+
+/** @brief Check whether the specified FMAC interrupt is enabled or not.
+ * @param __HANDLE__ FMAC handle.
+ * @param __INTERRUPT__ FMAC interrupt to check.
+ * This parameter can be one of the following values:
+ * @arg @ref FMAC_IT_RIEN Read interrupt enable
+ * @arg @ref FMAC_IT_WIEN Write interrupt enable
+ * @arg @ref FMAC_IT_OVFLIEN Overflow error interrupt enable
+ * @arg @ref FMAC_IT_UNFLIEN Underflow error interrupt enable
+ * @arg @ref FMAC_IT_SATIEN Saturation error interrupt enable (this helps in debugging a filter)
+ * @retval FlagStatus
+ */
+#define __HAL_FMAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->CR) & (__INTERRUPT__))
+
+/**
+ * @}
+ */
+
+/* Private Macros-----------------------------------------------------------*/
+/** @addtogroup FMAC_Private_Macros FMAC Private Macros
+ * @{
+ */
+
+/**
+ * @brief Verify the FMAC function.
+ * @param __FUNCTION__ ID of the function.
+ * @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
+ */
+#define IS_FMAC_FUNCTION(__FUNCTION__) (((__FUNCTION__) == FMAC_FUNC_LOAD_X1) || \
+ ((__FUNCTION__) == FMAC_FUNC_LOAD_X2) || \
+ ((__FUNCTION__) == FMAC_FUNC_LOAD_Y) || \
+ ((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \
+ ((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1))
+
+/**
+ * @brief Verify the FMAC load function used for input data, output data or coefficients.
+ * @param __FUNCTION__ ID of the load function.
+ * @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
+ */
+#define IS_FMAC_LOAD_FUNCTION(__FUNCTION__) (((__FUNCTION__) == FMAC_FUNC_LOAD_X1) || \
+ ((__FUNCTION__) == FMAC_FUNC_LOAD_X2) || \
+ ((__FUNCTION__) == FMAC_FUNC_LOAD_Y))
+
+/**
+ * @brief Verify the FMAC load function used with N values as input or output data.
+ * @param __FUNCTION__ ID of the load function.
+ * @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
+ */
+#define IS_FMAC_N_LOAD_FUNCTION(__FUNCTION__) (((__FUNCTION__) == FMAC_FUNC_LOAD_X1) || \
+ ((__FUNCTION__) == FMAC_FUNC_LOAD_Y))
+
+/**
+ * @brief Verify the FMAC load function used with N + M values as coefficients.
+ * @param __FUNCTION__ ID of the load function.
+ * @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
+ */
+#define IS_FMAC_N_M_LOAD_FUNCTION(__FUNCTION__) ((__FUNCTION__) == FMAC_FUNC_LOAD_X2)
+
+/**
+ * @brief Verify the FMAC filter function.
+ * @param __FUNCTION__ ID of the filter function.
+ * @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
+ */
+#define IS_FMAC_FILTER_FUNCTION(__FUNCTION__) (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \
+ ((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1))
+
+
+/**
+ * @brief Verify the FMAC threshold.
+ * @param __THRESHOLD__ Value of the threshold.
+ * @retval SET (__THRESHOLD__ is a valid value) or RESET (__THRESHOLD__ is invalid)
+ */
+#define IS_FMAC_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == FMAC_THRESHOLD_1) || \
+ ((__THRESHOLD__) == FMAC_THRESHOLD_2) || \
+ ((__THRESHOLD__) == FMAC_THRESHOLD_4) || \
+ ((__THRESHOLD__) == FMAC_THRESHOLD_NO_VALUE) || \
+ ((__THRESHOLD__) == FMAC_THRESHOLD_8))
+
+/**
+ * @brief Verify the FMAC filter parameter P.
+ * @param __P__ Value of the filter parameter P.
+ * @param __FUNCTION__ ID of the filter function.
+ * @retval SET (__P__ is a valid value) or RESET (__P__ is invalid)
+ */
+#define IS_FMAC_PARAM_P(__FUNCTION__, __P__) ( (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) && \
+ (((__P__) >= 2U) && ((__P__) <= 127U))) || \
+ (((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \
+ (((__P__) >= 2U) && ((__P__) <= 64U))) )
+
+/**
+ * @brief Verify the FMAC filter parameter Q.
+ * @param __Q__ Value of the filter parameter Q.
+ * @param __FUNCTION__ ID of the filter function.
+ * @retval SET (__Q__ is a valid value) or RESET (__Q__ is invalid)
+ */
+#define IS_FMAC_PARAM_Q(__FUNCTION__, __Q__) ( ((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \
+ (((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \
+ (((__Q__) >= 1U) && ((__Q__) <= 63U))) )
+
+/**
+ * @brief Verify the FMAC filter parameter R.
+ * @param __R__ Value of the filter parameter.
+ * @param __FUNCTION__ ID of the filter function.
+ * @retval SET (__R__ is a valid value) or RESET (__R__ is invalid)
+ */
+#define IS_FMAC_PARAM_R(__FUNCTION__, __R__) ( (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \
+ ((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1)) && \
+ ((__R__) <= 7U))
+
+/**
+ * @brief Verify the FMAC buffer access.
+ * @param __BUFFER_ACCESS__ Type of access.
+ * @retval SET (__BUFFER_ACCESS__ is a valid value) or RESET (__BUFFER_ACCESS__ is invalid)
+ */
+#define IS_FMAC_BUFFER_ACCESS(__BUFFER_ACCESS__) (((__BUFFER_ACCESS__) == FMAC_BUFFER_ACCESS_NONE) || \
+ ((__BUFFER_ACCESS__) == FMAC_BUFFER_ACCESS_DMA) || \
+ ((__BUFFER_ACCESS__) == FMAC_BUFFER_ACCESS_POLLING) || \
+ ((__BUFFER_ACCESS__) == FMAC_BUFFER_ACCESS_IT))
+
+/**
+ * @brief Verify the FMAC clip feature.
+ * @param __CLIP_STATE__ Clip state.
+ * @retval SET (__CLIP_STATE__ is a valid value) or RESET (__CLIP_STATE__ is invalid)
+ */
+#define IS_FMAC_CLIP_STATE(__CLIP_STATE__) (((__CLIP_STATE__) == FMAC_CLIP_DISABLED) || \
+ ((__CLIP_STATE__) == FMAC_CLIP_ENABLED))
+
+/**
+ * @brief Check whether the threshold is applicable.
+ * @param __SIZE__ Size of the matching buffer.
+ * @param __WM__ Watermark value.
+ * @param __ACCESS__ Access to the buffer (polling, it, dma, none).
+ * @retval THRESHOLD
+ */
+#define IS_FMAC_THRESHOLD_APPLICABLE(__SIZE__, __WM__, __ACCESS__) \
+ (( (__SIZE__) >= (((__WM__) == FMAC_THRESHOLD_1)? 1U: \
+ ((__WM__) == FMAC_THRESHOLD_2)? 2U: \
+ ((__WM__) == FMAC_THRESHOLD_4)? 4U:8U))&& \
+ ((((__ACCESS__) == FMAC_BUFFER_ACCESS_DMA)&& \
+ ((__WM__) == FMAC_THRESHOLD_1))|| \
+ ((__ACCESS__ )!= FMAC_BUFFER_ACCESS_DMA)))
+
+/**
+ * @}
+ */
+
+/* Exported functions ------------------------------------------------------- */
+/** @addtogroup FMAC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup FMAC_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_FMAC_Init(FMAC_HandleTypeDef *hfmac);
+HAL_StatusTypeDef HAL_FMAC_DeInit(FMAC_HandleTypeDef *hfmac);
+void HAL_FMAC_MspInit(FMAC_HandleTypeDef *hfmac);
+void HAL_FMAC_MspDeInit(FMAC_HandleTypeDef *hfmac);
+
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+/* Callbacks Register/UnRegister functions ***********************************/
+HAL_StatusTypeDef HAL_FMAC_RegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_CallbackIDTypeDef CallbackID,
+ pFMAC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FMAC_UnRegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @addtogroup FMAC_Exported_Functions_Group2
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig);
+HAL_StatusTypeDef HAL_FMAC_FilterConfig_DMA(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig);
+HAL_StatusTypeDef HAL_FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
+ int16_t *pOutput, uint8_t OutputSize);
+HAL_StatusTypeDef HAL_FMAC_FilterPreload_DMA(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
+ int16_t *pOutput, uint8_t OutputSize);
+HAL_StatusTypeDef HAL_FMAC_FilterStart(FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize);
+HAL_StatusTypeDef HAL_FMAC_AppendFilterData(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint16_t *pInputSize);
+HAL_StatusTypeDef HAL_FMAC_ConfigFilterOutputBuffer(FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize);
+HAL_StatusTypeDef HAL_FMAC_PollFilterData(FMAC_HandleTypeDef *hfmac, uint32_t Timeout);
+HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac);
+/**
+ * @}
+ */
+
+/** @addtogroup FMAC_Exported_Functions_Group3
+ * @{
+ */
+/* Callback functions *********************************************************/
+void HAL_FMAC_ErrorCallback(FMAC_HandleTypeDef *hfmac);
+void HAL_FMAC_HalfGetDataCallback(FMAC_HandleTypeDef *hfmac);
+void HAL_FMAC_GetDataCallback(FMAC_HandleTypeDef *hfmac);
+void HAL_FMAC_HalfOutputDataReadyCallback(FMAC_HandleTypeDef *hfmac);
+void HAL_FMAC_OutputDataReadyCallback(FMAC_HandleTypeDef *hfmac);
+void HAL_FMAC_FilterConfigCallback(FMAC_HandleTypeDef *hfmac);
+void HAL_FMAC_FilterPreloadCallback(FMAC_HandleTypeDef *hfmac);
+/**
+ * @}
+ */
+
+/** @addtogroup FMAC_Exported_Functions_Group4
+ * @{
+ */
+/* IRQ handler management *****************************************************/
+void HAL_FMAC_IRQHandler(FMAC_HandleTypeDef *hfmac);
+/**
+ * @}
+ */
+
+/** @addtogroup FMAC_Exported_Functions_Group5
+ * @{
+ */
+/* Peripheral State functions *************************************************/
+HAL_FMAC_StateTypeDef HAL_FMAC_GetState(FMAC_HandleTypeDef *hfmac);
+uint32_t HAL_FMAC_GetError(FMAC_HandleTypeDef *hfmac);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* FMAC */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_FMAC_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gpio.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gpio.h
new file mode 100644
index 00000000..bf9d576e
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gpio.h
@@ -0,0 +1,388 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_gpio.h
+ * @author MCD Application Team
+ * @brief Header file of GPIO HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_GPIO_H
+#define STM32U5xx_HAL_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup GPIO GPIO
+ * @brief GPIO HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Types GPIO Exported Types
+ * @{
+ */
+/**
+ * @brief GPIO Init structure definition
+ */
+typedef struct
+{
+ uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
+ This parameter can be a value of @ref GPIO_pins */
+
+ uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref GPIO_mode */
+
+ uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
+ This parameter can be a value of @ref GPIO_pull */
+
+ uint32_t Speed; /*!< Specifies the speed for the selected pins.
+ This parameter can be a value of @ref GPIO_speed */
+
+ uint32_t Alternate; /*!< Peripheral to be connected to the selected pins
+ This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
+} GPIO_InitTypeDef;
+
+/**
+ * @brief GPIO Bit SET and Bit RESET enumeration
+ */
+typedef enum
+{
+ GPIO_PIN_RESET = 0U,
+ GPIO_PIN_SET
+} GPIO_PinState;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
+ * @{
+ */
+/** @defgroup GPIO_pins GPIO pins
+ * @{
+ */
+#define GPIO_PIN_0 ((uint16_t)0x0001)
+#define GPIO_PIN_1 ((uint16_t)0x0002)
+#define GPIO_PIN_2 ((uint16_t)0x0004)
+#define GPIO_PIN_3 ((uint16_t)0x0008)
+#define GPIO_PIN_4 ((uint16_t)0x0010)
+#define GPIO_PIN_5 ((uint16_t)0x0020)
+#define GPIO_PIN_6 ((uint16_t)0x0040)
+#define GPIO_PIN_7 ((uint16_t)0x0080)
+#define GPIO_PIN_8 ((uint16_t)0x0100)
+#define GPIO_PIN_9 ((uint16_t)0x0200)
+#define GPIO_PIN_10 ((uint16_t)0x0400)
+#define GPIO_PIN_11 ((uint16_t)0x0800)
+#define GPIO_PIN_12 ((uint16_t)0x1000)
+#define GPIO_PIN_13 ((uint16_t)0x2000)
+#define GPIO_PIN_14 ((uint16_t)0x4000)
+#define GPIO_PIN_15 ((uint16_t)0x8000)
+#define GPIO_PIN_ALL ((uint16_t)0xFFFF)
+
+#define GPIO_PIN_MASK (0x0000FFFFU)
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_mode GPIO mode
+ * @brief GPIO Configuration Mode
+ * Elements values convention: 0xX0yz00YZ
+ * - X : GPIO mode or EXTI Mode
+ * - y : External IT or Event trigger detection
+ * - z : IO configuration on External IT or Event
+ * - Y : Output type (Push Pull or Open Drain)
+ * - Z : IO Direction mode (Input, Output, (Alternate or Analog) not applicable in case of LPGPIO)
+ * @{
+ */
+/*!< Input Floating Mode */
+#define GPIO_MODE_INPUT (0x00000000U)
+/*!< Output Push Pull Mode */
+#define GPIO_MODE_OUTPUT_PP (0x00000001U)
+/*!< Output Open Drain Mode */
+#define GPIO_MODE_OUTPUT_OD (0x00000011U)
+/*!< Alternate Function Push Pull Mode */
+#define GPIO_MODE_AF_PP (0x00000002U)
+/*!< Alternate Function Open Drain Mode */
+#define GPIO_MODE_AF_OD (0x00000012U)
+/*!< Analog Mode */
+#define GPIO_MODE_ANALOG (0x00000003U)
+/*!< External Interrupt Mode with Rising edge trigger detection */
+#define GPIO_MODE_IT_RISING (0x10110000U)
+/*!< External Interrupt Mode with Falling edge trigger detection */
+#define GPIO_MODE_IT_FALLING (0x10210000U)
+/*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define GPIO_MODE_IT_RISING_FALLING (0x10310000U)
+/*!< External Event Mode with Rising edge trigger detection */
+#define GPIO_MODE_EVT_RISING (0x10120000U)
+/*!< External Event Mode with Falling edge trigger detection */
+#define GPIO_MODE_EVT_FALLING (0x10220000U)
+/*!< External Event Mode with Rising/Falling edge trigger detection */
+#define GPIO_MODE_EVT_RISING_FALLING (0x10320000U)
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_speed GPIO speed
+ * @brief GPIO Output Maximum frequency
+ * @{
+ */
+#define GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Low speed */
+#define GPIO_SPEED_FREQ_MEDIUM (0x00000001U) /*!< Medium speed */
+#define GPIO_SPEED_FREQ_HIGH (0x00000002U) /*!< High speed */
+#define GPIO_SPEED_FREQ_VERY_HIGH (0x00000003U) /*!< Very-high speed */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_pull GPIO pull
+ * @brief GPIO Pull-Up or Pull-Down Activation
+ * @{
+ */
+#define GPIO_NOPULL (0x00000000U) /*!< No Pull-up or Pull-down activation */
+#define GPIO_PULLUP (0x00000001U) /*!< Pull-up activation */
+#define GPIO_PULLDOWN (0x00000002U) /*!< Pull-down activation */
+/**
+ * @}
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/** @defgroup GPIO_attributes GPIO attributes
+ * @brief GPIO pin secure or non-secure attributes
+ * @{
+ */
+#define GPIO_PIN_SEC (0x00000001U) /*!< Secure pin attribute */
+#define GPIO_PIN_NSEC (0x00000000U) /*!< Non-secure pin attribute */
+/**
+ * @}
+ */
+
+#endif /* __ARM_FEATURE_CMSE */
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Check whether the specified EXTI line is rising edge asserted or not.
+ * @param __EXTI_LINE__: specifies the EXTI line to check.
+ * This parameter can be GPIO_PIN_x where x can be(0..15)
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).
+ */
+#define __HAL_GPIO_EXTI_GET_RISING_IT(__EXTI_LINE__) (EXTI->RPR1 & (__EXTI_LINE__))
+
+/**
+ * @brief Clear the EXTI's line rising pending bits.
+ * @param __EXTI_LINE__: specifies the EXTI lines to clear.
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_CLEAR_RISING_IT(__EXTI_LINE__) (EXTI->RPR1 = (__EXTI_LINE__))
+
+/**
+ * @brief Check whether the specified EXTI line is falling edge asserted or not.
+ * @param __EXTI_LINE__: specifies the EXTI line to check.
+ * This parameter can be GPIO_PIN_x where x can be(0..15)
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).
+ */
+#define __HAL_GPIO_EXTI_GET_FALLING_IT(__EXTI_LINE__) (EXTI->FPR1 & (__EXTI_LINE__))
+
+/**
+ * @brief Clear the EXTI's line falling pending bits.
+ * @param __EXTI_LINE__: specifies the EXTI lines to clear.
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_CLEAR_FALLING_IT(__EXTI_LINE__) (EXTI->FPR1 = (__EXTI_LINE__))
+
+/**
+ * @brief Check whether the specified EXTI line is asserted or not.
+ * @param __EXTI_LINE__: specifies the EXTI line to check.
+ * This parameter can be GPIO_PIN_x where x can be(0..15)
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).
+ */
+#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (__HAL_GPIO_EXTI_GET_RISING_IT(__EXTI_LINE__) || \
+ __HAL_GPIO_EXTI_GET_FALLING_IT(__EXTI_LINE__))
+
+/**
+ * @brief Clear the EXTI's line pending bits.
+ * @param __EXTI_LINE__: specifies the EXTI lines to clear.
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) \
+ do { \
+ __HAL_GPIO_EXTI_CLEAR_RISING_IT(__EXTI_LINE__); \
+ __HAL_GPIO_EXTI_CLEAR_FALLING_IT(__EXTI_LINE__); \
+ } while(0)
+
+
+/**
+ * @brief Generate a Software interrupt on selected EXTI line(s).
+ * @param __EXTI_LINE__: specifies the EXTI line to set.
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 = (__EXTI_LINE__))
+
+/**
+ * @brief Check whether the specified EXTI line flag is set or not.
+ * @param __EXTI_LINE__ specifies the EXTI line flag to check.
+ * This parameter can be GPIO_PIN_x where x can be(0..15)
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).
+ */
+#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__)
+
+/**
+ * @brief Clear the EXTI line pending flags.
+ * @param __EXTI_LINE__ specifies the EXTI lines flags to clear.
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__)
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup GPIO_Private_Macros GPIO Private Macros
+ * @{
+ */
+#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
+
+#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
+ (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
+
+#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\
+ ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\
+ ((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\
+ ((__MODE__) == GPIO_MODE_AF_PP) ||\
+ ((__MODE__) == GPIO_MODE_AF_OD) ||\
+ ((__MODE__) == GPIO_MODE_IT_RISING) ||\
+ ((__MODE__) == GPIO_MODE_IT_FALLING) ||\
+ ((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\
+ ((__MODE__) == GPIO_MODE_EVT_RISING) ||\
+ ((__MODE__) == GPIO_MODE_EVT_FALLING) ||\
+ ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
+ ((__MODE__) == GPIO_MODE_ANALOG))
+
+#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\
+ ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\
+ ((__SPEED__) == GPIO_SPEED_FREQ_HIGH) ||\
+ ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH))
+
+#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\
+ ((__PULL__) == GPIO_PULLUP) || \
+ ((__PULL__) == GPIO_PULLDOWN))
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+#define IS_GPIO_PIN_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == GPIO_PIN_SEC) ||\
+ ((__ATTRIBUTES__) == GPIO_PIN_NSEC))
+
+#endif /* __ARM_FEATURE_CMSE */
+
+/**
+ * @}
+ */
+
+/* Include GPIO HAL Extended module */
+#include "stm32u5xx_hal_gpio_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
+ * @brief GPIO Exported Functions
+ * @{
+ */
+
+/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions *****************************/
+void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init);
+void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
+ * @brief IO operation functions
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
+void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_EnableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_DisableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin);
+
+/**
+ * @}
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/** @defgroup GPIO_Exported_Functions_Group3 IO attributes management functions
+ * @{
+ */
+
+/* IO attributes management functions *****************************************/
+void HAL_GPIO_ConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t PinAttributes);
+HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t *pPinAttributes);
+
+/**
+ * @}
+ */
+
+#endif /* __ARM_FEATURE_CMSE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_GPIO_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gpio_ex.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gpio_ex.h
new file mode 100644
index 00000000..f6a02b2f
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gpio_ex.h
@@ -0,0 +1,274 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_gpio_ex.h
+ * @author MCD Application Team
+ * @brief Header file of GPIO HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_GPIO_EX_H
+#define STM32U5xx_HAL_GPIO_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup GPIOEx GPIOEx
+ * @brief GPIO Extended HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup LPGPIO_MapTypeDef GPIO/Ex Exported Types
+ * @{
+ */
+typedef struct
+{
+ GPIO_TypeDef *GPIO_PORT;
+ uint32_t Pin_Pos;
+} LPGPIO_MapTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
+ * @{
+ */
+
+/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection
+ * @{
+ */
+
+#if (defined(STM32U575xx) || defined(STM32U585xx))
+/*--------------STM32U575xx/STM32U585xx---------------------------*/
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+#define GPIO_AF0_LPTIM1 ((uint8_t)0x00) /* LPTIM1 Alternate Function mapping */
+#define GPIO_AF0_CSLEEP ((uint8_t)0x00) /* CSLEEP Alternate Function mapping */
+#define GPIO_AF0_CSTOP ((uint8_t)0x00) /* CSTOP Alternate Function mapping */
+#define GPIO_AF0_SRDSTOP ((uint8_t)0x00) /* SRDSTOP Alternate Function mapping */
+#define GPIO_AF0_CRS ((uint8_t)0x00) /* CRS Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM5 ((uint8_t)0x01) /* TIM5 Alternate Function mapping */
+#define GPIO_AF1_TIM8 ((uint8_t)0x01) /* TIM8 Alternate Function mapping */
+#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
+#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */
+
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
+#define GPIO_AF2_LPTIM2 ((uint8_t)0x02) /* LPTIM2 Alternate Function mapping */
+#define GPIO_AF2_LPTIM3 ((uint8_t)0x02) /* LPTIM3 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_I2C4 ((uint8_t)0x03) /* I2C4 Alternate Function mapping */
+#define GPIO_AF3_OCTOSPI1 ((uint8_t)0x03) /* OCTOSPI1 Alternate Function mapping */
+#define GPIO_AF3_SAI1 ((uint8_t)0x03) /* SAI1 Alternate Function mapping */
+#define GPIO_AF3_SPI2 ((uint8_t)0x03) /* SPI2 Alternate Function mapping */
+#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
+#define GPIO_AF3_TIM8_COMP1 ((uint8_t)0x03) /* TIM8/COMP1 Break in Alternate Function mapping */
+#define GPIO_AF3_TIM8_COMP2 ((uint8_t)0x03) /* TIM8/COMP2 Break in Alternate Function mapping */
+#define GPIO_AF3_TIM1_COMP1 ((uint8_t)0x03) /* TIM1/COMP1 Break in Alternate Function mapping */
+#define GPIO_AF3_TIM1_COMP2 ((uint8_t)0x03) /* TIM1/COMP2 Break in Alternate Function mapping */
+#define GPIO_AF3_USART2 ((uint8_t)0x03) /* USART2 Alternate Function mapping */
+#define GPIO_AF3_ADF1 ((uint8_t)0x03) /* ADF1 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
+#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */
+#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */
+#define GPIO_AF4_PSSI ((uint8_t)0x04) /* PSSI Alternate Function mapping */
+#define GPIO_AF4_DCMI ((uint8_t)0x04) /* DCMI Alternate Function mapping */
+#define GPIO_AF4_LPTIM3 ((uint8_t)0x04) /* LPTIM3 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_DFSDM1 ((uint8_t)0x05) /* DFSDM1 Alternate Function mapping */
+#define GPIO_AF5_I2C4 ((uint8_t)0x05) /* I2C4 Alternate Function mapping */
+#define GPIO_AF5_PSSI ((uint8_t)0x05) /* PSSI Alternate Function mapping */
+#define GPIO_AF5_OCTOSPI1 ((uint8_t)0x05) /* OCTOSPI1 Alternate Function mapping */
+#define GPIO_AF5_OCTOSPI2 ((uint8_t)0x05) /* OCTOSPI2 Alternate Function mapping */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */
+#define GPIO_AF5_DCMI ((uint8_t)0x05) /* DCMI Alternate Function mapping */
+#define GPIO_AF5_MDF1 ((uint8_t)0x05) /* MDF1 Alternate Function mapping */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_OCTOSPI1 ((uint8_t)0x06) /* OCTOSPI1 Alternate Function mapping */
+#define GPIO_AF6_OCTOSPI2 ((uint8_t)0x06) /* OCTOSPI2 Alternate Function mapping */
+#define GPIO_AF6_MDF1 ((uint8_t)0x06) /* MDF1 Alternate Function mapping */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */
+#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
+#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
+#define GPIO_AF8_SDMMC1 ((uint8_t)0x08) /* SDMMC1 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */
+#define GPIO_AF9_TSC ((uint8_t)0x09) /* TSC Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_DCMI ((uint8_t)0x0A) /* DCMI Alternate Function mapping */
+#define GPIO_AF10_PSSI ((uint8_t)0x0A) /* PSSI Alternate Function mapping */
+#define GPIO_AF10_USB ((uint8_t)0x0A) /* USB Alternate Function mapping */
+#define GPIO_AF10_OCTOSPI1 ((uint8_t)0x0A) /* OCTOSPI1 Alternate Function mapping */
+#define GPIO_AF10_OCTOSPI2 ((uint8_t)0x0A) /* OCTOSPI2 Alternate Function mapping */
+#define GPIO_AF10_CRS ((uint8_t)0x0A) /* CRS Alternate Function mapping */
+
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_UCPD1 ((uint8_t)0x0B) /*!< UCPD1 Alternate Function mapping */
+#define GPIO_AF11_SDMMC2 ((uint8_t)0x0B) /*!< SDMMC2 Alternate Function mapping */
+#define GPIO_AF11_LPGPIO ((uint8_t)0x0B) /*!< LPGPIO Alternate Function mapping */
+#define GPIO_AF11_FMC_NBL1 ((uint8_t)0x0B) /*!< FMC_NBL1 Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */
+#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */
+#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */
+#define GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM1/COMP1 Break in Alternate Function mapping */
+#define GPIO_AF12_TIM1_COMP2 ((uint8_t)0x0C) /* TIM1/COMP2 Break in Alternate Function mapping */
+#define GPIO_AF12_TIM8_COMP2 ((uint8_t)0x0C) /* TIM8/COMP2 Break in Alternate Function mapping */
+#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */
+#define GPIO_AF12_SDMMC2 ((uint8_t)0x0C) /* SDMMC2 Alternate Function mapping */
+
+/**
+ * @brief AF 13 selection
+ */
+#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */
+#define GPIO_AF13_SAI2 ((uint8_t)0x0D) /* SAI2 Alternate Function mapping */
+#define GPIO_AF13_TIM8_COMP1 ((uint8_t)0x0D) /* TIM8/COMP1 Break in Alternate Function mapping */
+#define GPIO_AF13_LPTIM4 ((uint8_t)0x0D) /* LPTIM4 Alternate Function mapping */
+#define GPIO_AF13_LPTIM2 ((uint8_t)0x0D) /* LPTIM2 Alternate Function mapping */
+
+/**
+ * @brief AF 14 selection
+ */
+#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */
+#define GPIO_AF14_LPTIM3 ((uint8_t)0x0E) /* LPTIM3 Alternate Function mapping */
+#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */
+#define GPIO_AF14_TIM8_COMP2 ((uint8_t)0x0E) /* TIM8/COMP2 Break in Alternate Function mapping */
+#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */
+#define GPIO_AF14_TIM15_COMP1 ((uint8_t)0x0E) /* TIM15/COMP1 Alternate Function mapping */
+#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */
+#define GPIO_AF14_TIM16_COMP1 ((uint8_t)0x0E) /* TIM16/COMP1 Alternate Function mapping */
+#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /* TIM17 Alternate Function mapping */
+#define GPIO_AF14_TIM17_COMP1 ((uint8_t)0x0E) /* TIM17/COMP1 Alternate Function mapping */
+#define GPIO_AF14_SDMMC2 ((uint8_t)0x0E) /* SDMMC2 Alternate Function mapping */
+
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)
+
+#endif /* (defined(STM32U575xx) || defined(STM32U585xx)) */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros
+ * @{
+ */
+
+/** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index
+ * @{
+ */
+#if (defined(STM32U575xx) || defined(STM32U585xx))
+
+#define GPIO_GET_INDEX(__GPIOx__) (((uint32_t )(__GPIOx__) & (~GPIOA_BASE)) >> 10)
+
+#endif /* (defined(STM32U575xx) || defined(STM32U585xx)) */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_GPIO_EX_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gtzc.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gtzc.h
new file mode 100644
index 00000000..0c2b9201
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gtzc.h
@@ -0,0 +1,590 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_gtzc.h
+ * @author MCD Application Team
+ * @brief Header file of GTZC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_GTZC_H
+#define STM32U5xx_HAL_GTZC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup GTZC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup GTZC_Exported_Types GTZC Exported Types
+ * @{
+ */
+
+/*!< Values needed for MPCBB_Attribute_ConfigTypeDef structure sizing */
+#define GTZC_MCPBB_NB_VCTR_REG_MAX (32U)
+#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX (1U)
+typedef struct
+{
+ uint32_t MPCBB_SecConfig_array[GTZC_MCPBB_NB_VCTR_REG_MAX]; /*!< Each element specifies secure access mode for
+ a super-block. Each bit corresponds to a block
+ inside the super-block. 0 means non-secure,
+ 1 means secure */
+ uint32_t MPCBB_PrivConfig_array[GTZC_MCPBB_NB_VCTR_REG_MAX]; /*!< Each element specifies privilege access mode for
+ a super-block. Each bit corresponds to a block
+ inside the super-block. 0 means non-privilege,
+ 1 means privilege */
+ uint32_t MPCBB_LockConfig_array[GTZC_MCPBB_NB_LCK_VCTR_REG_MAX]; /*!< Each bit specifies the lock configuration of
+ a super-block (32 blocks). 0 means unlocked,
+ 1 means locked */
+} MPCBB_Attribute_ConfigTypeDef;
+
+typedef struct
+{
+ uint32_t SecureRWIllegalMode; /*!< Secure read/write illegal access
+ field. It can be a value of @ref GTZC_MPCBB_SecureRWIllegalMode */
+ uint32_t InvertSecureState; /*!< Default security state field (can be inverted or not).
+ It can be a value of @ref GTZC_MPCBB_InvertSecureState */
+ MPCBB_Attribute_ConfigTypeDef AttributeConfig; /*!< MPCBB attribute configuration sub-structure */
+} MPCBB_ConfigTypeDef;
+
+typedef struct
+{
+ uint32_t AreaId; /*!< Area identifier field. It can be a value of @ref
+ GTZC_MPCWM_AreaId */
+ uint32_t Offset; /*!< Offset of the watermark area, starting from the selected
+ memory base address. It must aligned on 128KB for FMC
+ and OCTOSPI memories, and on 32-byte for BKPSRAM */
+ uint32_t Length; /*!< Length of the watermark area, starting from the selected
+ Offset. It must aligned on 128KB for FMC and OCTOSPI
+ memories, and on 32-byte for BKPSRAM */
+ uint32_t Attribute; /*!< Attributes of the watermark area. It can be a value
+ of @ref GTZC_MPCWM_Attribute */
+ uint32_t Lock; /*!< Lock of the watermark area. It can be a value
+ of @ref GTZC_MPCWM_Lock */
+ uint32_t AreaStatus; /*!< Status of the watermark area. It can be set to
+ ENABLE or DISABLE */
+} MPCWM_ConfigTypeDef;
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+
+/** @defgroup GTZC_Private_Constants GTZC Private Constants
+ * @{
+ */
+
+/** @defgroup GTZC_Private_PeriphId_composition GTZC Peripheral identifier composition
+ * @{
+ */
+
+/* composition definition for Peripheral identifier parameter (PeriphId) used in
+ * HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes()
+ * functions and also in all HAL_GTZC_TZIC relative functions.
+ * Bitmap Definition
+ * bits[31:28] Field "register". Define the register index a peripheral belongs to.
+ * Each bit is dedicated to a single register.
+ * bit[5] Field "all peripherals". If this bit is set then the PeriphId targets
+ * all peripherals within all registers.
+ * bits[4:0] Field "bit position". Define the bit position within the
+ * register dedicated to the peripheral, value from 0 to 31.
+ */
+#define GTZC_PERIPH_REG_SHIFT (28U)
+#define GTZC_PERIPH_REG (0xF0000000U)
+#define GTZC1_PERIPH_REG1 (0x00000000U)
+#define GTZC1_PERIPH_REG2 (0x10000000U)
+#define GTZC1_PERIPH_REG3 (0x20000000U)
+#define GTZC1_PERIPH_REG4 (0x30000000U)
+#define GTZC2_PERIPH_REG1 (0x40000000U)
+#define GTZC2_PERIPH_REG2 (0x50000000U)
+#define GTZC_PERIPH_BIT_POSITION (0x0000001FU)
+
+/**
+ * @}
+ */
+
+/** @defgroup GTZC_Private_Attributes_Msk GTZC Attributes Masks
+ * @{
+ */
+#define GTZC_ATTR_SEC_MASK 0x100U
+#define GTZC_ATTR_PRIV_MASK 0x200U
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GTZC_Exported_Constants GTZC Exported Constants
+ * @{
+ */
+
+/** @defgroup GTZC_MPCBB_SecureRWIllegalMode GTZC MPCBB SRWILADIS values
+ * @{
+ */
+
+#define GTZC_MPCBB_SRWILADIS_ENABLE (0U)
+#define GTZC_MPCBB_SRWILADIS_DISABLE (GTZC_MPCBB_CR_SRWILADIS_Msk)
+
+/**
+ * @}
+ */
+
+/** @defgroup GTZC_MPCBB_InvertSecureState GTZC MPCBB INVSECSTATE values
+ * @{
+ */
+
+#define GTZC_MPCBB_INVSECSTATE_NOT_INVERTED (0U)
+#define GTZC_MPCBB_INVSECSTATE_INVERTED (GTZC_MPCBB_CR_INVSECSTATE_Msk)
+
+/**
+ * @}
+ */
+
+/** @defgroup GTZC_MPCWM_AreaId GTZC MPCWM area identifier values
+ * @{
+ */
+
+#define GTZC_TZSC_MPCWM_ID1 (0U)
+#define GTZC_TZSC_MPCWM_ID2 (1U)
+
+/**
+ * @}
+ */
+
+/** @defgroup GTZC_TZSC_TZIC_PeriphId GTZC TZSC and TZIC Peripheral identifier values
+ * @{
+ */
+/* GTZC1 */
+#define GTZC_PERIPH_TIM2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM2_Pos)
+#define GTZC_PERIPH_TIM3 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM3_Pos)
+#define GTZC_PERIPH_TIM4 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM4_Pos)
+#define GTZC_PERIPH_TIM5 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM5_Pos)
+#define GTZC_PERIPH_TIM6 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM6_Pos)
+#define GTZC_PERIPH_TIM7 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM7_Pos)
+#define GTZC_PERIPH_WWDG (GTZC1_PERIPH_REG1 | GTZC_CFGR1_WWDG_Pos)
+#define GTZC_PERIPH_IWDG (GTZC1_PERIPH_REG1 | GTZC_CFGR1_IWDG_Pos)
+#define GTZC_PERIPH_SPI2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_SPI2_Pos)
+#define GTZC_PERIPH_USART2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_USART2_Pos)
+#define GTZC_PERIPH_USART3 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_USART3_Pos)
+#define GTZC_PERIPH_UART4 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UART4_Pos)
+#define GTZC_PERIPH_UART5 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UART5_Pos)
+#define GTZC_PERIPH_I2C1 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I2C1_Pos)
+#define GTZC_PERIPH_I2C2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I2C2_Pos)
+#define GTZC_PERIPH_CRS (GTZC1_PERIPH_REG1 | GTZC_CFGR1_CRS_Pos)
+#define GTZC_PERIPH_I2C4 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I2C4_Pos)
+#define GTZC_PERIPH_LPTIM2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_LPTIM2_Pos)
+#define GTZC_PERIPH_FDCAN1 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_FDCAN1_Pos)
+#define GTZC_PERIPH_UCPD1 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UCPD1_Pos)
+#define GTZC_PERIPH_TIM1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM1_Pos)
+#define GTZC_PERIPH_SPI1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SPI1_Pos)
+#define GTZC_PERIPH_TIM8 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM8_Pos)
+#define GTZC_PERIPH_USART1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_USART1_Pos)
+#define GTZC_PERIPH_TIM15 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM15_Pos)
+#define GTZC_PERIPH_TIM16 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM16_Pos)
+#define GTZC_PERIPH_TIM17 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM17_Pos)
+#define GTZC_PERIPH_SAI1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SAI1_Pos)
+#define GTZC_PERIPH_SAI2 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SAI2_Pos)
+#define GTZC_PERIPH_MDF1 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_MDF1_Pos)
+#define GTZC_PERIPH_CORDIC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_CORDIC_Pos)
+#define GTZC_PERIPH_FMAC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_FMAC_Pos)
+#define GTZC_PERIPH_CRC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_CRC_Pos)
+#define GTZC_PERIPH_TSC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_TSC_Pos)
+#define GTZC_PERIPH_DMA2D (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DMA2D_Pos)
+#define GTZC_PERIPH_ICACHE_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_ICACHE_REG_Pos)
+#define GTZC_PERIPH_DCACHE1_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DCACHE1_REG_Pos)
+#define GTZC_PERIPH_ADC12 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_ADC12_Pos)
+#define GTZC_PERIPH_DCMI (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DCMI_Pos)
+#define GTZC_PERIPH_OTG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_OTG_Pos)
+#define GTZC_PERIPH_AES (GTZC1_PERIPH_REG3 | GTZC_CFGR3_AES_Pos)
+#define GTZC_PERIPH_HASH (GTZC1_PERIPH_REG3 | GTZC_CFGR3_HASH_Pos)
+#define GTZC_PERIPH_RNG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_RNG_Pos)
+#define GTZC_PERIPH_PKA (GTZC1_PERIPH_REG3 | GTZC_CFGR3_PKA_Pos)
+#define GTZC_PERIPH_SAES (GTZC1_PERIPH_REG3 | GTZC_CFGR3_SAES_Pos)
+#define GTZC_PERIPH_OCTOSPIM (GTZC1_PERIPH_REG3 | GTZC_CFGR3_OCTOSPIM_Pos)
+#define GTZC_PERIPH_SDMMC1 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_SDMMC1_Pos)
+#define GTZC_PERIPH_SDMMC2 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_SDMMC2_Pos)
+#define GTZC_PERIPH_FSMC_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_FSMC_REG_Pos)
+#define GTZC_PERIPH_OCTOSPI1_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_OCTOSPI1_REG_Pos)
+#define GTZC_PERIPH_OCTOSPI2_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_OCTOSPI2_REG_Pos)
+#define GTZC_PERIPH_RAMCFG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_RAMCFG_Pos)
+#define GTZC_PERIPH_GPDMA1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_GPDMA1_Pos)
+#define GTZC_PERIPH_FLASH_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_FLASH_REG_Pos)
+#define GTZC_PERIPH_FLASH (GTZC1_PERIPH_REG4 | GTZC_CFGR4_FLASH_Pos)
+#define GTZC_PERIPH_OTFDEC2 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OTFDEC2_Pos)
+#define GTZC_PERIPH_OTFDEC1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OTFDEC1_Pos)
+#define GTZC_PERIPH_TZSC1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_TZSC1_Pos)
+#define GTZC_PERIPH_TZIC1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_TZIC1_Pos)
+#define GTZC_PERIPH_OCTOSPI1_MEM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OCTOSPI1_MEM_Pos)
+#define GTZC_PERIPH_FSMC_MEM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_FSMC_MEM_Pos)
+#define GTZC_PERIPH_BKPSRAM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_BKPSRAM_Pos)
+#define GTZC_PERIPH_OCTOSPI2_MEM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OCTOSPI2_MEM_Pos)
+#define GTZC_PERIPH_SRAM1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM1_Pos)
+#define GTZC_PERIPH_MPCBB1_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB1_REG_Pos)
+#define GTZC_PERIPH_SRAM2 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM2_Pos)
+#define GTZC_PERIPH_MPCBB2_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB2_REG_Pos)
+#define GTZC_PERIPH_SRAM3 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM3_Pos)
+#define GTZC_PERIPH_MPCBB3_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB3_REG_Pos)
+
+/* GTZC2 */
+#define GTZC_PERIPH_SPI3 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_SPI3_Pos)
+#define GTZC_PERIPH_LPUART1 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_LPUART1_Pos)
+#define GTZC_PERIPH_I2C3 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_I2C3_Pos)
+#define GTZC_PERIPH_LPTIM1 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_LPTIM1_Pos)
+#define GTZC_PERIPH_LPTIM3 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_LPTIM3_Pos)
+#define GTZC_PERIPH_LPTIM4 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_LPTIM4_Pos)
+#define GTZC_PERIPH_OPAMP (GTZC2_PERIPH_REG1 | GTZC_CFGR1_OPAMP_Pos)
+#define GTZC_PERIPH_COMP (GTZC2_PERIPH_REG1 | GTZC_CFGR1_COMP_Pos)
+#define GTZC_PERIPH_ADC4 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_ADC4_Pos)
+#define GTZC_PERIPH_VREFBUF (GTZC2_PERIPH_REG1 | GTZC_CFGR1_VREFBUF_Pos)
+#define GTZC_PERIPH_DAC1 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_DAC1_Pos)
+#define GTZC_PERIPH_ADF1 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_ADF1_Pos)
+#define GTZC_PERIPH_SYSCFG (GTZC2_PERIPH_REG2 | GTZC_CFGR2_SYSCFG_Pos)
+#define GTZC_PERIPH_RTC (GTZC2_PERIPH_REG2 | GTZC_CFGR2_RTC_Pos)
+#define GTZC_PERIPH_TAMP (GTZC2_PERIPH_REG2 | GTZC_CFGR2_TAMP_Pos)
+#define GTZC_PERIPH_PWR (GTZC2_PERIPH_REG2 | GTZC_CFGR2_PWR_Pos)
+#define GTZC_PERIPH_RCC (GTZC2_PERIPH_REG2 | GTZC_CFGR2_RCC_Pos)
+#define GTZC_PERIPH_LPDMA1 (GTZC2_PERIPH_REG2 | GTZC_CFGR2_LPDMA1_Pos)
+#define GTZC_PERIPH_EXTI (GTZC2_PERIPH_REG2 | GTZC_CFGR2_EXTI_Pos)
+#define GTZC_PERIPH_TZSC2 (GTZC2_PERIPH_REG2 | GTZC_CFGR2_TZSC2_Pos)
+#define GTZC_PERIPH_TZIC2 (GTZC2_PERIPH_REG2 | GTZC_CFGR2_TZIC2_Pos)
+#define GTZC_PERIPH_SRAM4 (GTZC2_PERIPH_REG2 | GTZC_CFGR2_SRAM4_Pos)
+#define GTZC_PERIPH_MPCBB4_REG (GTZC2_PERIPH_REG2 | GTZC_CFGR2_MPCBB4_REG_Pos)
+
+#define GTZC_PERIPH_ALL (0x00000020U)
+
+/* Note that two maximum values are also defined here:
+ * - max number of securable AHB/APB peripherals or masters
+ * (used in TZSC sub-block)
+ * - max number of securable and TrustZone-aware AHB/APB peripherals or masters
+ * (used in TZIC sub-block)
+ */
+#define GTZC_TZSC_PERIPH_NUMBER (HAL_GTZC_TZSC_GET_ARRAY_INDEX(GTZC_PERIPH_ADF1 + 1U))
+#define GTZC_TZIC_PERIPH_NUMBER (HAL_GTZC_TZIC_GET_ARRAY_INDEX(GTZC_PERIPH_MPCBB4_REG + 1U))
+
+/**
+ * @}
+ */
+
+/** @defgroup GTZC_TZSC_PeriphAttributes GTZC TZSC peripheral attribute values
+ * @{
+ */
+
+/* user-oriented definitions for attribute parameter (PeriphAttributes) used in
+ * HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes()
+ * functions
+ */
+#define GTZC_TZSC_PERIPH_SEC (GTZC_ATTR_SEC_MASK | 0x00000001U) /*!< Secure attribute */
+#define GTZC_TZSC_PERIPH_NSEC (GTZC_ATTR_SEC_MASK | 0x00000000U) /*!< Non-secure attribute */
+#define GTZC_TZSC_PERIPH_PRIV (GTZC_ATTR_PRIV_MASK | 0x00000002U) /*!< Privilege attribute */
+#define GTZC_TZSC_PERIPH_NPRIV (GTZC_ATTR_PRIV_MASK | 0x00000000U) /*!< Non-privilege attribute */
+
+/**
+ * @}
+ */
+
+/** @defgroup GTZC_TZSC_Lock GTZC TZSC lock values
+ * @{
+ */
+
+/* user-oriented definitions for HAL_GTZC_TZSC_GetLock() returned value */
+#define GTZC_TZSC_LOCK_OFF (0U)
+#define GTZC_TZSC_LOCK_ON GTZC_TZSC_CR_LCK_Msk
+
+/**
+ * @}
+ */
+
+/** @defgroup GTZC_MPCWM_Group GTZC MPCWM values
+ * @{
+ */
+
+/* user-oriented definitions for TZSC_MPCWM */
+#define GTZC_TZSC_MPCWM_GRANULARITY_1 0x00020000U /* OCTOSPI & FMC granularity: 128 kbytes */
+#define GTZC_TZSC_MPCWM_GRANULARITY_2 0x00000020U /* BKPSRAM granularity: 32 bytes */
+
+/**
+ * @}
+ */
+
+/** @defgroup GTZC_MPCWM_Lock GTZC MPCWM Lock values
+ * @{
+ */
+
+/* user-oriented definitions for TZSC_MPCWM */
+#define GTZC_TZSC_MPCWM_LOCK_OFF (0U)
+#define GTZC_TZSC_MPCWM_LOCK_ON GTZC_TZSC_MPCWM_CFGR_SRLOCK_Msk
+
+/**
+ * @}
+ */
+
+/** @defgroup GTZC_MPCWM_Attribute GTZC MPCWM Attribute values
+ * @{
+ */
+
+/* user-oriented definitions for TZSC_MPCWM */
+#define GTZC_TZSC_MPCWM_REGION_NSEC (0U)
+#define GTZC_TZSC_MPCWM_REGION_SEC (1U)
+#define GTZC_TZSC_MPCWM_REGION_NPRIV (0U)
+#define GTZC_TZSC_MPCWM_REGION_PRIV (2U)
+
+/**
+ * @}
+ */
+
+/** @defgroup GTZC_MPCBB_Group GTZC MPCBB values
+ * @{
+ */
+
+/* user-oriented definitions for MPCBB */
+#define GTZC_MPCBB_BLOCK_SIZE 0x200U /* 512 Bytes */
+#define GTZC_MPCBB_SUPERBLOCK_SIZE (GTZC_MPCBB_BLOCK_SIZE * 32U) /* 16 KBytes */
+#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED (0U)
+#define GTZC_MCPBB_SUPERBLOCK_LOCKED (1U)
+
+#define GTZC_MCPBB_BLOCK_NSEC (GTZC_ATTR_SEC_MASK | 0U)
+#define GTZC_MCPBB_BLOCK_SEC (GTZC_ATTR_SEC_MASK | 1U)
+#define GTZC_MCPBB_BLOCK_NPRIV (GTZC_ATTR_PRIV_MASK | 0U)
+#define GTZC_MCPBB_BLOCK_PRIV (GTZC_ATTR_PRIV_MASK | 2U)
+
+/* user-oriented definitions for HAL_GTZC_MPCBB_GetLock() returned value */
+#define GTZC_MCPBB_LOCK_OFF (0U)
+#define GTZC_MCPBB_LOCK_ON (1U)
+
+/**
+ * @}
+ */
+
+/** @defgroup GTZC_TZIC_Flag GTZC TZIC flag values
+ * @{
+ */
+
+/* user-oriented definitions for HAL_GTZC_TZIC_GetFlag() flag parameter */
+#define GTZC_TZIC_NO_ILA_EVENT (0U)
+#define GTZC_TZIC_ILA_EVENT_PENDING (1U)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup GTZC_Private_Macros GTZC Private Macros
+ * @{
+ */
+
+/* retrieve information to access register for a specific PeriphId */
+#define GTZC_GET_REG_INDEX(periph_id)\
+ (((periph_id) & GTZC_PERIPH_REG) >> GTZC_PERIPH_REG_SHIFT)
+#define GTZC_GET_REG_INDEX_IN_INSTANCE(periph_id)\
+ ((((periph_id) & GTZC_PERIPH_REG) <= GTZC1_PERIPH_REG4) ? \
+ (((periph_id) & GTZC_PERIPH_REG) >> GTZC_PERIPH_REG_SHIFT) : \
+ ((((periph_id) & GTZC_PERIPH_REG) >> GTZC_PERIPH_REG_SHIFT) - 4U))
+#define GTZC_GET_PERIPH_POS(periph_id) ((periph_id) & GTZC_PERIPH_BIT_POSITION)
+
+#define IS_GTZC_BASE_ADDRESS(mem, address)\
+ ( ( (uint32_t)(address) == (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) || \
+ ( (uint32_t)(address) == (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) )
+
+#define GTZC_MEM_SIZE(mem)\
+ ( mem ## _SIZE )
+
+#define GTZC_BASE_ADDRESS_S(mem)\
+ ( mem ## _BASE_S )
+
+#define GTZC_BASE_ADDRESS_NS(mem)\
+ ( mem ## _BASE_NS )
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup GTZC_Exported_Macros GTZC Exported Macros
+ * @{
+ */
+
+/* user-oriented macro to get array index of a specific PeriphId
+ * in case of GTZC_PERIPH_ALL usage in the two following functions:
+ * HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes()
+ */
+#define HAL_GTZC_TZSC_GET_ARRAY_INDEX(periph_id) \
+ (uint32_t)((HAL_GTZC_TZSC_GET_INSTANCE(periph_id) == GTZC_TZSC1)? \
+ ((GTZC_GET_REG_INDEX(periph_id) * 32U) + GTZC_GET_PERIPH_POS(periph_id)) : \
+ (((GTZC_GET_REG_INDEX(periph_id) - 1U) * 32U) + GTZC_GET_PERIPH_POS(periph_id) ))
+
+#define HAL_GTZC_TZIC_GET_ARRAY_INDEX(periph_id) \
+ ( (GTZC_GET_REG_INDEX((periph_id)) * 32U) + GTZC_GET_PERIPH_POS((periph_id)) )
+
+/* user-oriented macro to get TZSC instance of a specific PeriphId */
+#define HAL_GTZC_TZSC_GET_INSTANCE(periph_id) \
+ ((GTZC_GET_REG_INDEX(periph_id) <= (GTZC1_PERIPH_REG4 >> GTZC_PERIPH_REG_SHIFT))? \
+ GTZC_TZSC1 : GTZC_TZSC2)
+
+/* user-oriented macro to get TZIC instance of a specific PeriphId */
+#define HAL_GTZC_TZIC_GET_INSTANCE(periph_id) \
+ ((GTZC_GET_REG_INDEX(periph_id) <= (GTZC1_PERIPH_REG4>> GTZC_PERIPH_REG_SHIFT))? \
+ GTZC_TZIC1 : GTZC_TZIC2)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup GTZC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup GTZC_Exported_Functions_Group1
+ * @brief TZSC Initialization and Configuration functions
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId,
+ uint32_t PeriphAttributes);
+HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId,
+ uint32_t *PeriphAttributes);
+
+/**
+ * @}
+ */
+
+#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/** @addtogroup GTZC_Exported_Functions_Group2
+ * @brief MPCWM Initialization and Configuration functions
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress,
+ MPCWM_ConfigTypeDef *pMPCWM_Desc);
+HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress,
+ MPCWM_ConfigTypeDef *pMPCWM_Desc);
+/**
+ * @}
+ */
+
+/** @addtogroup GTZC_Exported_Functions_Group3
+ * @brief TZSC and TZSC-MPCWM Lock functions
+ * @{
+ */
+
+void HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSC_Instance);
+uint32_t HAL_GTZC_TZSC_GetLock(GTZC_TZSC_TypeDef *TZSC_Instance);
+
+/**
+ * @}
+ */
+#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/** @addtogroup GTZC_Exported_Functions_Group4
+ * @brief MPCBB Initialization and Configuration functions
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress,
+ MPCBB_ConfigTypeDef *pMPCBB_desc);
+HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress,
+ MPCBB_ConfigTypeDef *pMPCBB_desc);
+HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress,
+ uint32_t NbBlocks,
+ uint32_t *pMemAttributes);
+HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress,
+ uint32_t NbBlocks,
+ uint32_t *pMemAttributes);
+
+#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress,
+ uint32_t NbSuperBlocks,
+ uint32_t *pLockAttributes);
+HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress,
+ uint32_t NbSuperBlocks,
+ uint32_t *pLockAttributes);
+HAL_StatusTypeDef HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress);
+HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress,
+ uint32_t *pLockState);
+#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/**
+ * @}
+ */
+
+#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/** @addtogroup GTZC_Exported_Functions_Group5
+ * @brief TZIC functions
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId);
+HAL_StatusTypeDef HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId);
+HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *pFlag);
+HAL_StatusTypeDef HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId);
+
+/**
+ * @}
+ */
+
+/** @addtogroup GTZC_Exported_Functions_Group6
+ * @brief IRQ related Functions
+ * @{
+ */
+
+void HAL_GTZC_IRQHandler(void);
+void HAL_GTZC_TZIC_Callback(uint32_t PeriphId);
+
+/**
+ * @}
+ */
+
+#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_GTZC_H */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_hash.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_hash.h
new file mode 100644
index 00000000..2f02a3f6
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_hash.h
@@ -0,0 +1,629 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_hash.h
+ * @author MCD Application Team
+ * @brief Header file of HASH HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_HASH_H
+#define STM32U5xx_HAL_HASH_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+#if defined (HASH)
+/** @addtogroup HASH
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup HASH_Exported_Types HASH Exported Types
+ * @{
+ */
+
+/**
+ * @brief HASH Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit data.
+ This parameter can be a value of @ref HASH_Data_Type. */
+
+ uint32_t KeySize; /*!< The key size is used only in HMAC operation. */
+
+ uint8_t *pKey; /*!< The key is used only in HMAC operation. */
+
+} HASH_InitTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_HASH_STATE_RESET = 0x00U, /*!< Peripheral is not initialized */
+ HAL_HASH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
+ HAL_HASH_STATE_BUSY = 0x02U, /*!< Processing (hashing) is ongoing */
+ HAL_HASH_STATE_TIMEOUT = 0x06U, /*!< Timeout state */
+ HAL_HASH_STATE_ERROR = 0x07U, /*!< Error state */
+ HAL_HASH_STATE_SUSPENDED = 0x08U /*!< Suspended state */
+} HAL_HASH_StateTypeDef;
+
+/**
+ * @brief HAL phase structures definition
+ */
+typedef enum
+{
+ HAL_HASH_PHASE_READY = 0x01U, /*!< HASH peripheral is ready to start */
+ HAL_HASH_PHASE_PROCESS = 0x02U, /*!< HASH peripheral is in HASH processing phase */
+ HAL_HASH_PHASE_HMAC_STEP_1 = 0x03U, /*!< HASH peripheral is in HMAC step 1 processing phase
+ (step 1 consists in entering the inner hash function key) */
+ HAL_HASH_PHASE_HMAC_STEP_2 = 0x04U, /*!< HASH peripheral is in HMAC step 2 processing phase
+ (step 2 consists in entering the message text) */
+ HAL_HASH_PHASE_HMAC_STEP_3 = 0x05U /*!< HASH peripheral is in HMAC step 3 processing phase
+ (step 3 consists in entering the outer hash function key) */
+} HAL_HASH_PhaseTypeDef;
+
+/**
+ * @brief HAL HASH mode suspend definitions
+ */
+typedef enum
+{
+ HAL_HASH_SUSPEND_NONE = 0x00U, /*!< HASH peripheral suspension not requested */
+ HAL_HASH_SUSPEND = 0x01U /*!< HASH peripheral suspension is requested */
+} HAL_HASH_SuspendTypeDef;
+
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
+/**
+ * @brief HAL HASH common Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_HASH_MSPINIT_CB_ID = 0x00U, /*!< HASH MspInit callback ID */
+ HAL_HASH_MSPDEINIT_CB_ID = 0x01U, /*!< HASH MspDeInit callback ID */
+ HAL_HASH_INPUTCPLT_CB_ID = 0x02U, /*!< HASH input completion callback ID */
+ HAL_HASH_DGSTCPLT_CB_ID = 0x03U, /*!< HASH digest computation completion callback ID */
+ HAL_HASH_ERROR_CB_ID = 0x04U, /*!< HASH error callback ID */
+} HAL_HASH_CallbackIDTypeDef;
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+
+
+/**
+ * @brief HASH Handle Structure definition
+ */
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+typedef struct __HASH_HandleTypeDef
+#else
+typedef struct
+#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
+{
+ HASH_InitTypeDef Init; /*!< HASH required parameters */
+
+ uint8_t *pHashInBuffPtr; /*!< Pointer to input buffer */
+
+ uint8_t *pHashOutBuffPtr; /*!< Pointer to output buffer (digest) */
+
+ uint8_t *pHashKeyBuffPtr; /*!< Pointer to key buffer (HMAC only) */
+
+ uint8_t *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */
+
+ uint32_t HashBuffSize; /*!< Size of buffer to be processed */
+
+ __IO uint32_t HashInCount; /*!< Counter of inputted data */
+
+ __IO uint32_t HashITCounter; /*!< Counter of issued interrupts */
+
+ __IO uint32_t HashKeyCount; /*!< Counter for Key inputted data (HMAC only) */
+
+ HAL_StatusTypeDef Status; /*!< HASH peripheral status */
+
+ HAL_HASH_PhaseTypeDef Phase; /*!< HASH peripheral phase */
+
+ DMA_HandleTypeDef *hdmain; /*!< HASH In DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< Locking object */
+
+ __IO HAL_HASH_StateTypeDef State; /*!< HASH peripheral state */
+
+ HAL_HASH_SuspendTypeDef SuspendRequest; /*!< HASH peripheral suspension request flag */
+
+ FlagStatus DigestCalculationDisable; /*!< Digest calculation phase skip (MDMAT bit control) for multi-buffers DMA-based HMAC computation */
+
+ __IO uint32_t NbWordsAlreadyPushed; /*!< Numbers of words already pushed in FIFO before inputting new block */
+
+ __IO uint32_t ErrorCode; /*!< HASH Error code */
+
+ __IO uint32_t Accumulation; /*!< HASH multi buffers accumulation flag */
+
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+ void (* InCpltCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH input completion callback */
+
+ void (* DgstCpltCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH digest computation completion callback */
+
+ void (* ErrorCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH error callback */
+
+ void (* MspInitCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH Msp Init callback */
+
+ void (* MspDeInitCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH Msp DeInit callback */
+
+#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
+} HASH_HandleTypeDef;
+
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
+/**
+ * @brief HAL HASH Callback pointer definition
+ */
+typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef *hhash); /*!< pointer to a HASH common callback functions */
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HASH_Exported_Constants HASH Exported Constants
+ * @{
+ */
+
+/** @defgroup HASH_Algo_Selection HASH algorithm selection
+ * @{
+ */
+#define HASH_ALGOSELECTION_SHA1 0x00000000U /*!< HASH function is SHA1 */
+#define HASH_ALGOSELECTION_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */
+#define HASH_ALGOSELECTION_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */
+#define HASH_ALGOSELECTION_SHA256 HASH_CR_ALGO /*!< HASH function is SHA256 */
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Algorithm_Mode HASH algorithm mode
+ * @{
+ */
+#define HASH_ALGOMODE_HASH 0x00000000U /*!< Algorithm is HASH */
+#define HASH_ALGOMODE_HMAC HASH_CR_MODE /*!< Algorithm is HMAC */
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Data_Type HASH input data type
+ * @{
+ */
+#define HASH_DATATYPE_32B 0x00000000U /*!< 32-bit data. No swapping */
+#define HASH_DATATYPE_16B HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */
+#define HASH_DATATYPE_8B HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */
+#define HASH_DATATYPE_1B HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */
+/**
+ * @}
+ */
+
+/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode HMAC key length type
+ * @{
+ */
+#define HASH_HMAC_KEYTYPE_SHORTKEY 0x00000000U /*!< HMAC Key size is <= 64 bytes */
+#define HASH_HMAC_KEYTYPE_LONGKEY HASH_CR_LKEY /*!< HMAC Key size is > 64 bytes */
+/**
+ * @}
+ */
+
+/** @defgroup HASH_flags_definition HASH flags definitions
+ * @{
+ */
+#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : a new block can be entered in the Peripheral */
+#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */
+#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
+#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy, processing a block of data */
+#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : the input buffer contains at least one word of data */
+
+/**
+ * @}
+ */
+
+/** @defgroup HASH_interrupts_definition HASH interrupts definitions
+ * @{
+ */
+#define HASH_IT_DINI HASH_IMR_DINIE /*!< A new block can be entered into the input buffer (DIN) */
+#define HASH_IT_DCI HASH_IMR_DCIE /*!< Digest calculation complete */
+
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Error_Definition HASH Error Definition
+ * @{
+ */
+#define HAL_HASH_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_HASH_ERROR_IT 0x00000001U /*!< IT-based process error */
+#define HAL_HASH_ERROR_DMA 0x00000002U /*!< DMA-based process error */
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
+#define HAL_HASH_ERROR_INVALID_CALLBACK 0x00000004U /*!< Invalid Callback error */
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup HASH_Exported_Macros HASH Exported Macros
+ * @{
+ */
+
+/** @brief Check whether or not the specified HASH flag is set.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
+ * @arg @ref HASH_FLAG_DCIS Digest calculation complete.
+ * @arg @ref HASH_FLAG_DMAS DMA interface is enabled (DMAE=1) or a transfer is ongoing.
+ * @arg @ref HASH_FLAG_BUSY The hash core is Busy : processing a block of data.
+ * @arg @ref HASH_FLAG_DINNE DIN not empty : the input buffer contains at least one word of data.
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_HASH_GET_FLAG(__FLAG__) (((__FLAG__) > 8U) ? \
+ ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
+ ((HASH->SR & (__FLAG__)) == (__FLAG__)) )
+
+
+/** @brief Clear the specified HASH flag.
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be one of the following values:
+ * @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
+ * @arg @ref HASH_FLAG_DCIS Digest calculation complete
+ * @retval None
+ */
+#define __HAL_HASH_CLEAR_FLAG(__FLAG__) CLEAR_BIT(HASH->SR, (__FLAG__))
+
+
+/** @brief Enable the specified HASH interrupt.
+ * @param __INTERRUPT__ specifies the HASH interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN)
+ * @arg @ref HASH_IT_DCI Digest calculation complete
+ * @retval None
+ */
+#define __HAL_HASH_ENABLE_IT(__INTERRUPT__) SET_BIT(HASH->IMR, (__INTERRUPT__))
+
+/** @brief Disable the specified HASH interrupt.
+ * @param __INTERRUPT__ specifies the HASH interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN)
+ * @arg @ref HASH_IT_DCI Digest calculation complete
+ * @retval None
+ */
+#define __HAL_HASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(HASH->IMR, (__INTERRUPT__))
+
+/** @brief Reset HASH handle state.
+ * @param __HANDLE__ HASH handle.
+ * @retval None
+ */
+
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) do{\
+ (__HANDLE__)->State = HAL_HASH_STATE_RESET;\
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ }while(0)
+#else
+#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET)
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+
+
+/** @brief Reset HASH handle status.
+ * @param __HANDLE__ HASH handle.
+ * @retval None
+ */
+#define __HAL_HASH_RESET_HANDLE_STATUS(__HANDLE__) ((__HANDLE__)->Status = HAL_OK)
+
+/**
+ * @brief Enable the multi-buffer DMA transfer mode.
+ * @note This bit is set when hashing large files when multiple DMA transfers are needed.
+ * @retval None
+ */
+#define __HAL_HASH_SET_MDMAT() SET_BIT(HASH->CR, HASH_CR_MDMAT)
+
+/**
+ * @brief Disable the multi-buffer DMA transfer mode.
+ * @retval None
+ */
+#define __HAL_HASH_RESET_MDMAT() CLEAR_BIT(HASH->CR, HASH_CR_MDMAT)
+
+
+/**
+ * @brief Start the digest computation.
+ * @retval None
+ */
+#define __HAL_HASH_START_DIGEST() SET_BIT(HASH->STR, HASH_STR_DCAL)
+
+/**
+ * @brief Set the number of valid bits in the last word written in data register DIN.
+ * @param __SIZE__ size in bytes of last data written in Data register.
+ * @retval None
+ */
+#define __HAL_HASH_SET_NBVALIDBITS(__SIZE__) MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * ((__SIZE__) % 4U))
+
+/**
+ * @brief Reset the HASH core.
+ * @retval None
+ */
+#define __HAL_HASH_INIT() SET_BIT(HASH->CR, HASH_CR_INIT)
+
+/**
+ * @}
+ */
+
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup HASH_Private_Macros HASH Private Macros
+ * @{
+ */
+/**
+ * @brief Return digest length in bytes.
+ * @retval Digest length
+ */
+#define HASH_DIGEST_LENGTH() ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA1) ? 20U : \
+ ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ? 28U : \
+ ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ? 32U : 16U ) ) )
+/**
+ * @brief Return number of words already pushed in the FIFO.
+ * @retval Number of words already pushed in the FIFO
+ */
+#define HASH_NBW_PUSHED() ((READ_BIT(HASH->CR, HASH_CR_NBW)) >> 8U)
+
+/**
+ * @brief Ensure that HASH input data type is valid.
+ * @param __DATATYPE__ HASH input data type.
+ * @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)
+ */
+#define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \
+ ((__DATATYPE__) == HASH_DATATYPE_16B)|| \
+ ((__DATATYPE__) == HASH_DATATYPE_8B) || \
+ ((__DATATYPE__) == HASH_DATATYPE_1B))
+
+/**
+ * @brief Ensure that input data buffer size is valid for multi-buffer HASH
+ * processing in DMA mode.
+ * @note This check is valid only for multi-buffer HASH processing in DMA mode.
+ * @param __SIZE__ input data buffer size.
+ * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
+ */
+#define IS_HASH_DMA_MULTIBUFFER_SIZE(__SIZE__) ((READ_BIT(HASH->CR, HASH_CR_MDMAT) == 0U) || (((__SIZE__) % 4U) == 0U))
+
+/**
+ * @brief Ensure that input data buffer size is valid for multi-buffer HMAC
+ * processing in DMA mode.
+ * @note This check is valid only for multi-buffer HMAC processing in DMA mode.
+ * @param __HANDLE__ HASH handle.
+ * @param __SIZE__ input data buffer size.
+ * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
+ */
+#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET)\
+ || (((__SIZE__) % 4U) == 0U))
+/**
+ * @brief Ensure that handle phase is set to HASH processing.
+ * @param __HANDLE__ HASH handle.
+ * @retval SET (handle phase is set to HASH processing) or RESET (handle phase is not set to HASH processing)
+ */
+#define IS_HASH_PROCESSING(__HANDLE__) ((__HANDLE__)->Phase == HAL_HASH_PHASE_PROCESS)
+
+/**
+ * @brief Ensure that handle phase is set to HMAC processing.
+ * @param __HANDLE__ HASH handle.
+ * @retval SET (handle phase is set to HMAC processing) or RESET (handle phase is not set to HMAC processing)
+ */
+#define IS_HMAC_PROCESSING(__HANDLE__) (((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || \
+ ((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_2) || \
+ ((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
+
+/**
+ * @}
+ */
+
+/* Include HASH HAL Extended module */
+#include "stm32u5xx_hal_hash_ex.h"
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup HASH_Exported_Functions HASH Exported Functions
+ * @{
+ */
+
+/** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization/de-initialization methods **********************************/
+HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash);
+HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash);
+void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash);
+void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);
+void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash);
+void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);
+void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID,
+ pHASH_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode
+ * @{
+ */
+
+
+/* HASH processing using polling *********************************************/
+HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout);
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup HASH_Exported_Functions_Group3 HASH processing functions in interrupt mode
+ * @{
+ */
+
+/* HASH processing using IT **************************************************/
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
+HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
+void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
+/**
+ * @}
+ */
+
+/** @addtogroup HASH_Exported_Functions_Group4 HASH processing functions in DMA mode
+ * @{
+ */
+
+/* HASH processing using DMA *************************************************/
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HASH_Exported_Functions_Group5 HMAC processing functions in polling mode
+ * @{
+ */
+
+/* HASH-MAC processing using polling *****************************************/
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HASH_Exported_Functions_Group6 HMAC processing functions in interrupt mode
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode
+ * @{
+ */
+
+/* HASH-HMAC processing using DMA ********************************************/
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HASH_Exported_Functions_Group8 Peripheral states functions
+ * @{
+ */
+
+
+/* Peripheral State methods **************************************************/
+HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
+HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash);
+void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer);
+void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer);
+void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
+HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
+uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions -----------------------------------------------------------*/
+
+/** @addtogroup HASH_Private_Functions HASH Private Functions
+ * @{
+ */
+
+/* Private functions */
+HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout, uint32_t Algorithm);
+HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Algorithm);
+HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* HASH*/
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32U5xx_HAL_HASH_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_hash_ex.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_hash_ex.h
new file mode 100644
index 00000000..3e26a61c
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_hash_ex.h
@@ -0,0 +1,174 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_hash_ex.h
+ * @author MCD Application Team
+ * @brief Header file of HASH HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_HASH_EX_H
+#define STM32U5xx_HAL_HASH_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+#if defined (HASH)
+/** @addtogroup HASHEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup HASHEx_Exported_Functions HASH Extended Exported Functions
+ * @{
+ */
+
+/** @addtogroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode
+ * @{
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode
+ * @{
+ */
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/** @addtogroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HASHEx_Exported_Functions_Group7 Multi-buffer HMAC extended processing functions in DMA mode
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+
+HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* HASH*/
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32U5xx_HAL_HASH_EX_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_hcd.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_hcd.h
new file mode 100644
index 00000000..7f87724b
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_hcd.h
@@ -0,0 +1,315 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_hcd.h
+ * @author MCD Application Team
+ * @brief Header file of HCD HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_HCD_H
+#define STM32U5xx_HAL_HCD_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_ll_usb.h"
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup HCD HCD
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup HCD_Exported_Types HCD Exported Types
+ * @{
+ */
+
+/** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition
+ * @{
+ */
+typedef enum
+{
+ HAL_HCD_STATE_RESET = 0x00,
+ HAL_HCD_STATE_READY = 0x01,
+ HAL_HCD_STATE_ERROR = 0x02,
+ HAL_HCD_STATE_BUSY = 0x03,
+ HAL_HCD_STATE_TIMEOUT = 0x04
+} HCD_StateTypeDef;
+
+typedef USB_OTG_GlobalTypeDef HCD_TypeDef;
+typedef USB_OTG_CfgTypeDef HCD_InitTypeDef;
+typedef USB_OTG_HCTypeDef HCD_HCTypeDef;
+typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef;
+typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition
+ * @{
+ */
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+typedef struct __HCD_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+{
+ HCD_TypeDef *Instance; /*!< Register base address */
+ HCD_InitTypeDef Init; /*!< HCD required parameters */
+ HCD_HCTypeDef hc[16]; /*!< Host channels parameters */
+ HAL_LockTypeDef Lock; /*!< HCD peripheral status */
+ __IO HCD_StateTypeDef State; /*!< HCD communication state */
+ __IO uint32_t ErrorCode; /*!< HCD Error code */
+ void *pData; /*!< Pointer Stack Handler */
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+ void (* SOFCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD SOF callback */
+ void (* ConnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Connect callback */
+ void (* DisconnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Disconnect callback */
+ void (* PortEnabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Enable callback */
+ void (* PortDisabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Disable callback */
+ void (* HC_NotifyURBChangeCallback)(struct __HCD_HandleTypeDef *hhcd, uint8_t chnum,
+ HCD_URBStateTypeDef urb_state); /*!< USB OTG HCD Host Channel Notify URB Change callback */
+
+ void (* MspInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp Init callback */
+ void (* MspDeInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp DeInit callback */
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+} HCD_HandleTypeDef;
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup HCD_Exported_Constants HCD Exported Constants
+ * @{
+ */
+
+/** @defgroup HCD_Speed HCD Speed
+ * @{
+ */
+#define HCD_SPEED_HIGH USBH_HS_SPEED
+#define HCD_SPEED_FULL USBH_FSLS_SPEED
+#define HCD_SPEED_LOW USBH_FSLS_SPEED
+/**
+ * @}
+ */
+
+/** @defgroup HCD_Device_Speed HCD Device Speed
+ * @{
+ */
+#define HCD_DEVICE_SPEED_HIGH 0U
+#define HCD_DEVICE_SPEED_FULL 1U
+#define HCD_DEVICE_SPEED_LOW 2U
+/**
+ * @}
+ */
+
+/** @defgroup HCD_PHY_Module HCD PHY Module
+ * @{
+ */
+#define HCD_PHY_ULPI 1U
+#define HCD_PHY_EMBEDDED 2U
+/**
+ * @}
+ */
+
+/** @defgroup HCD_Error_Code_definition HCD Error Code definition
+ * @brief HCD Error Code definition
+ * @{
+ */
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+#define HAL_HCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup HCD_Exported_Macros HCD Exported Macros
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+#define __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
+
+#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\
+ & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
+#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
+
+#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
+#define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
+#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
+#define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
+#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup HCD_Exported_Functions HCD Exported Functions
+ * @{
+ */
+
+/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
+ uint8_t epnum, uint8_t dev_address,
+ uint8_t speed, uint8_t ep_type, uint16_t mps);
+
+HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
+void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+/** @defgroup HAL_HCD_Callback_ID_enumeration_definition HAL USB OTG HCD Callback ID enumeration definition
+ * @brief HAL USB OTG HCD Callback ID enumeration definition
+ * @{
+ */
+typedef enum
+{
+ HAL_HCD_SOF_CB_ID = 0x01, /*!< USB HCD SOF callback ID */
+ HAL_HCD_CONNECT_CB_ID = 0x02, /*!< USB HCD Connect callback ID */
+ HAL_HCD_DISCONNECT_CB_ID = 0x03, /*!< USB HCD Disconnect callback ID */
+ HAL_HCD_PORT_ENABLED_CB_ID = 0x04, /*!< USB HCD Port Enable callback ID */
+ HAL_HCD_PORT_DISABLED_CB_ID = 0x05, /*!< USB HCD Port Disable callback ID */
+
+ HAL_HCD_MSPINIT_CB_ID = 0x06, /*!< USB HCD MspInit callback ID */
+ HAL_HCD_MSPDEINIT_CB_ID = 0x07 /*!< USB HCD MspDeInit callback ID */
+
+} HAL_HCD_CallbackIDTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HAL_HCD_Callback_pointer_definition HAL USB OTG HCD Callback pointer definition
+ * @brief HAL USB OTG HCD Callback pointer definition
+ * @{
+ */
+
+typedef void (*pHCD_CallbackTypeDef)(HCD_HandleTypeDef *hhcd); /*!< pointer to a common USB OTG HCD callback function */
+typedef void (*pHCD_HC_NotifyURBChangeCallbackTypeDef)(HCD_HandleTypeDef *hhcd,
+ uint8_t epnum,
+ HCD_URBStateTypeDef urb_state); /*!< pointer to USB OTG HCD host channel callback */
+/**
+ * @}
+ */
+
+HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd,
+ HAL_HCD_CallbackIDTypeDef CallbackID,
+ pHCD_CallbackTypeDef pCallback);
+
+HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd,
+ HAL_HCD_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd,
+ pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback);
+
+HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/* I/O operation functions ***************************************************/
+/** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
+ uint8_t direction, uint8_t ep_type,
+ uint8_t token, uint8_t *pbuff,
+ uint16_t length, uint8_t do_ping);
+
+/* Non-Blocking mode: Interrupt */
+void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum,
+ HCD_URBStateTypeDef urb_state);
+/**
+ * @}
+ */
+
+/* Peripheral Control functions **********************************************/
+/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
+/**
+ * @}
+ */
+
+/* Peripheral State functions ************************************************/
+/** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
+HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
+HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
+uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup HCD_Private_Macros HCD Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+/* Private functions prototypes ----------------------------------------------*/
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_HCD_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_i2c.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_i2c.h
new file mode 100644
index 00000000..8b816c6e
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_i2c.h
@@ -0,0 +1,818 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_i2c.h
+ * @author MCD Application Team
+ * @brief Header file of I2C HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_I2C_H
+#define STM32U5xx_HAL_I2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup I2C
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup I2C_Exported_Types I2C Exported Types
+ * @{
+ */
+
+/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
+ * @brief I2C Configuration Structure definition
+ * @{
+ */
+typedef struct
+{
+ uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
+ This parameter calculated by referring to I2C initialization
+ section in Reference manual */
+
+ uint32_t OwnAddress1; /*!< Specifies the first device own address.
+ This parameter can be a 7-bit or 10-bit address. */
+
+ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
+ This parameter can be a value of @ref I2C_ADDRESSING_MODE */
+
+ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
+ This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
+
+ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
+ This parameter can be a 7-bit address. */
+
+ uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
+ This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
+
+ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
+ This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
+
+ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
+ This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
+
+} I2C_InitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_state_structure_definition HAL state structure definition
+ * @brief HAL State structure definition
+ * @note HAL I2C State value coding follow below described bitmap :\n
+ * b7-b6 Error information\n
+ * 00 : No Error\n
+ * 01 : Abort (Abort user request on going)\n
+ * 10 : Timeout\n
+ * 11 : Error\n
+ * b5 Peripheral initialization status\n
+ * 0 : Reset (peripheral not initialized)\n
+ * 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
+ * b4 (not used)\n
+ * x : Should be set to 0\n
+ * b3\n
+ * 0 : Ready or Busy (No Listen mode ongoing)\n
+ * 1 : Listen (peripheral in Address Listen Mode)\n
+ * b2 Intrinsic process state\n
+ * 0 : Ready\n
+ * 1 : Busy (peripheral busy with some configuration or internal operations)\n
+ * b1 Rx state\n
+ * 0 : Ready (no Rx operation ongoing)\n
+ * 1 : Busy (Rx operation ongoing)\n
+ * b0 Tx state\n
+ * 0 : Ready (no Tx operation ongoing)\n
+ * 1 : Busy (Tx operation ongoing)
+ * @{
+ */
+typedef enum
+{
+ HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
+ HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
+ HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
+ HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
+ HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
+ HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
+ HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
+ process is ongoing */
+ HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
+ process is ongoing */
+ HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
+ HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
+ HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
+
+} HAL_I2C_StateTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_mode_structure_definition HAL mode structure definition
+ * @brief HAL Mode structure definition
+ * @note HAL I2C Mode value coding follow below described bitmap :\n
+ * b7 (not used)\n
+ * x : Should be set to 0\n
+ * b6\n
+ * 0 : None\n
+ * 1 : Memory (HAL I2C communication is in Memory Mode)\n
+ * b5\n
+ * 0 : None\n
+ * 1 : Slave (HAL I2C communication is in Slave Mode)\n
+ * b4\n
+ * 0 : None\n
+ * 1 : Master (HAL I2C communication is in Master Mode)\n
+ * b3-b2-b1-b0 (not used)\n
+ * xxxx : Should be set to 0000
+ * @{
+ */
+typedef enum
+{
+ HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
+ HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
+ HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
+ HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
+
+} HAL_I2C_ModeTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Error_Code_definition I2C Error Code definition
+ * @brief I2C Error Code definition
+ * @{
+ */
+#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */
+#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */
+#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */
+#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */
+#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
+#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
+#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */
+#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
+ * @brief I2C handle Structure definition
+ * @{
+ */
+typedef struct __I2C_HandleTypeDef
+{
+ I2C_TypeDef *Instance; /*!< I2C registers base address */
+
+ I2C_InitTypeDef Init; /*!< I2C communication parameters */
+
+ uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
+
+ uint16_t XferSize; /*!< I2C transfer size */
+
+ __IO uint16_t XferCount; /*!< I2C transfer counter */
+
+ __IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can
+ be a value of @ref I2C_XFEROPTIONS */
+
+ __IO uint32_t PreviousState; /*!< I2C communication Previous state */
+
+ HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */
+
+ DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< I2C locking object */
+
+ __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
+
+ __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
+
+ __IO uint32_t ErrorCode; /*!< I2C Error code */
+
+ __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */
+ void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Rx Transfer completed callback */
+ void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Tx Transfer completed callback */
+ void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Rx Transfer completed callback */
+ void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Listen Complete callback */
+ void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Tx Transfer completed callback */
+ void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Rx Transfer completed callback */
+ void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Error callback */
+ void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Abort callback */
+
+ void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< I2C Slave Address Match callback */
+
+ void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp Init callback */
+ void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp DeInit callback */
+
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+} I2C_HandleTypeDef;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL I2C Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */
+ HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */
+ HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */
+ HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */
+ HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */
+ HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */
+ HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */
+ HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */
+ HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */
+
+ HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */
+ HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */
+
+} HAL_I2C_CallbackIDTypeDef;
+
+/**
+ * @brief HAL I2C Callback pointer definition
+ */
+typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */
+typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */
+
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Constants I2C Exported Constants
+ * @{
+ */
+
+/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options
+ * @{
+ */
+#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
+#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
+#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
+#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
+#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
+#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)
+
+/* List of XferOptions in usage of :
+ * 1- Restart condition in all use cases (direction change or not)
+ */
+#define I2C_OTHER_FRAME (0x000000AAU)
+#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
+ * @{
+ */
+#define I2C_ADDRESSINGMODE_7BIT (0x00000001U)
+#define I2C_ADDRESSINGMODE_10BIT (0x00000002U)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
+ * @{
+ */
+#define I2C_DUALADDRESS_DISABLE (0x00000000U)
+#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
+/**
+ * @}
+ */
+
+/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
+ * @{
+ */
+#define I2C_OA2_NOMASK ((uint8_t)0x00U)
+#define I2C_OA2_MASK01 ((uint8_t)0x01U)
+#define I2C_OA2_MASK02 ((uint8_t)0x02U)
+#define I2C_OA2_MASK03 ((uint8_t)0x03U)
+#define I2C_OA2_MASK04 ((uint8_t)0x04U)
+#define I2C_OA2_MASK05 ((uint8_t)0x05U)
+#define I2C_OA2_MASK06 ((uint8_t)0x06U)
+#define I2C_OA2_MASK07 ((uint8_t)0x07U)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
+ * @{
+ */
+#define I2C_GENERALCALL_DISABLE (0x00000000U)
+#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
+/**
+ * @}
+ */
+
+/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
+ * @{
+ */
+#define I2C_NOSTRETCH_DISABLE (0x00000000U)
+#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
+/**
+ * @}
+ */
+
+/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
+ * @{
+ */
+#define I2C_MEMADD_SIZE_8BIT (0x00000001U)
+#define I2C_MEMADD_SIZE_16BIT (0x00000002U)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
+ * @{
+ */
+#define I2C_DIRECTION_TRANSMIT (0x00000000U)
+#define I2C_DIRECTION_RECEIVE (0x00000001U)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
+ * @{
+ */
+#define I2C_RELOAD_MODE I2C_CR2_RELOAD
+#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
+#define I2C_SOFTEND_MODE (0x00000000U)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
+ * @{
+ */
+#define I2C_NO_STARTSTOP (0x00000000U)
+#define I2C_GENERATE_NO_START_READ (uint32_t)(0x80000000U | I2C_CR2_RD_WRN)
+#define I2C_GENERATE_NO_START_WRITE (uint32_t)(0x80000000U)
+#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
+#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
+#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
+ * @brief I2C Interrupt definition
+ * Elements values convention: 0xXXXXXXXX
+ * - XXXXXXXX : Interrupt control mask
+ * @{
+ */
+#define I2C_IT_ERRI I2C_CR1_ERRIE
+#define I2C_IT_TCI I2C_CR1_TCIE
+#define I2C_IT_STOPI I2C_CR1_STOPIE
+#define I2C_IT_NACKI I2C_CR1_NACKIE
+#define I2C_IT_ADDRI I2C_CR1_ADDRIE
+#define I2C_IT_RXI I2C_CR1_RXIE
+#define I2C_IT_TXI I2C_CR1_TXIE
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Flag_definition I2C Flag definition
+ * @{
+ */
+#define I2C_FLAG_TXE I2C_ISR_TXE
+#define I2C_FLAG_TXIS I2C_ISR_TXIS
+#define I2C_FLAG_RXNE I2C_ISR_RXNE
+#define I2C_FLAG_ADDR I2C_ISR_ADDR
+#define I2C_FLAG_AF I2C_ISR_NACKF
+#define I2C_FLAG_STOPF I2C_ISR_STOPF
+#define I2C_FLAG_TC I2C_ISR_TC
+#define I2C_FLAG_TCR I2C_ISR_TCR
+#define I2C_FLAG_BERR I2C_ISR_BERR
+#define I2C_FLAG_ARLO I2C_ISR_ARLO
+#define I2C_FLAG_OVR I2C_ISR_OVR
+#define I2C_FLAG_PECERR I2C_ISR_PECERR
+#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
+#define I2C_FLAG_ALERT I2C_ISR_ALERT
+#define I2C_FLAG_BUSY I2C_ISR_BUSY
+#define I2C_FLAG_DIR I2C_ISR_DIR
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Macros I2C Exported Macros
+ * @{
+ */
+
+/** @brief Reset I2C handle state.
+ * @param __HANDLE__ specifies the I2C Handle.
+ * @retval None
+ */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_I2C_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+
+/** @brief Enable the specified I2C interrupt.
+ * @param __HANDLE__ specifies the I2C Handle.
+ * @param __INTERRUPT__ specifies the interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg @ref I2C_IT_ERRI Errors interrupt enable
+ * @arg @ref I2C_IT_TCI Transfer complete interrupt enable
+ * @arg @ref I2C_IT_STOPI STOP detection interrupt enable
+ * @arg @ref I2C_IT_NACKI NACK received interrupt enable
+ * @arg @ref I2C_IT_ADDRI Address match interrupt enable
+ * @arg @ref I2C_IT_RXI RX interrupt enable
+ * @arg @ref I2C_IT_TXI TX interrupt enable
+ *
+ * @retval None
+ */
+#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
+
+/** @brief Disable the specified I2C interrupt.
+ * @param __HANDLE__ specifies the I2C Handle.
+ * @param __INTERRUPT__ specifies the interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg @ref I2C_IT_ERRI Errors interrupt enable
+ * @arg @ref I2C_IT_TCI Transfer complete interrupt enable
+ * @arg @ref I2C_IT_STOPI STOP detection interrupt enable
+ * @arg @ref I2C_IT_NACKI NACK received interrupt enable
+ * @arg @ref I2C_IT_ADDRI Address match interrupt enable
+ * @arg @ref I2C_IT_RXI RX interrupt enable
+ * @arg @ref I2C_IT_TXI TX interrupt enable
+ *
+ * @retval None
+ */
+#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
+
+/** @brief Check whether the specified I2C interrupt source is enabled or not.
+ * @param __HANDLE__ specifies the I2C Handle.
+ * @param __INTERRUPT__ specifies the I2C interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg @ref I2C_IT_ERRI Errors interrupt enable
+ * @arg @ref I2C_IT_TCI Transfer complete interrupt enable
+ * @arg @ref I2C_IT_STOPI STOP detection interrupt enable
+ * @arg @ref I2C_IT_NACKI NACK received interrupt enable
+ * @arg @ref I2C_IT_ADDRI Address match interrupt enable
+ * @arg @ref I2C_IT_RXI RX interrupt enable
+ * @arg @ref I2C_IT_TXI TX interrupt enable
+ *
+ * @retval The new state of __INTERRUPT__ (SET or RESET).
+ */
+#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \
+ (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Check whether the specified I2C flag is set or not.
+ * @param __HANDLE__ specifies the I2C Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref I2C_FLAG_TXE Transmit data register empty
+ * @arg @ref I2C_FLAG_TXIS Transmit interrupt status
+ * @arg @ref I2C_FLAG_RXNE Receive data register not empty
+ * @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
+ * @arg @ref I2C_FLAG_AF Acknowledge failure received flag
+ * @arg @ref I2C_FLAG_STOPF STOP detection flag
+ * @arg @ref I2C_FLAG_TC Transfer complete (master mode)
+ * @arg @ref I2C_FLAG_TCR Transfer complete reload
+ * @arg @ref I2C_FLAG_BERR Bus error
+ * @arg @ref I2C_FLAG_ARLO Arbitration lost
+ * @arg @ref I2C_FLAG_OVR Overrun/Underrun
+ * @arg @ref I2C_FLAG_PECERR PEC error in reception
+ * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
+ * @arg @ref I2C_FLAG_ALERT SMBus alert
+ * @arg @ref I2C_FLAG_BUSY Bus busy
+ * @arg @ref I2C_FLAG_DIR Transfer direction (slave mode)
+ *
+ * @retval The new state of __FLAG__ (SET or RESET).
+ */
+#define I2C_FLAG_MASK (0x0001FFFFU)
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \
+ (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+
+/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
+ * @param __HANDLE__ specifies the I2C Handle.
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg @ref I2C_FLAG_TXE Transmit data register empty
+ * @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
+ * @arg @ref I2C_FLAG_AF Acknowledge failure received flag
+ * @arg @ref I2C_FLAG_STOPF STOP detection flag
+ * @arg @ref I2C_FLAG_BERR Bus error
+ * @arg @ref I2C_FLAG_ARLO Arbitration lost
+ * @arg @ref I2C_FLAG_OVR Overrun/Underrun
+ * @arg @ref I2C_FLAG_PECERR PEC error in reception
+ * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
+ * @arg @ref I2C_FLAG_ALERT SMBus alert
+ *
+ * @retval None
+ */
+#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \
+ ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
+ ((__HANDLE__)->Instance->ICR = (__FLAG__)))
+
+/** @brief Enable the specified I2C peripheral.
+ * @param __HANDLE__ specifies the I2C Handle.
+ * @retval None
+ */
+#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+
+/** @brief Disable the specified I2C peripheral.
+ * @param __HANDLE__ specifies the I2C Handle.
+ * @retval None
+ */
+#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+
+/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.
+ * @param __HANDLE__ specifies the I2C Handle.
+ * @retval None
+ */
+#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
+/**
+ * @}
+ */
+
+/* Include I2C HAL Extended module */
+#include "stm32u5xx_hal_i2c_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2C_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+/* Initialization and de-initialization functions******************************/
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
+ pI2C_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+/* IO operation functions ****************************************************/
+/******* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
+ uint32_t Timeout);
+
+/******* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
+
+/******* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions);
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
+void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
+ * @{
+ */
+/* Peripheral State, Mode and Error functions *********************************/
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Constants I2C Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2C_Private_Macro I2C Private Macros
+ * @{
+ */
+
+#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
+ ((MODE) == I2C_ADDRESSINGMODE_10BIT))
+
+#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
+ ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
+
+#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
+ ((MASK) == I2C_OA2_MASK01) || \
+ ((MASK) == I2C_OA2_MASK02) || \
+ ((MASK) == I2C_OA2_MASK03) || \
+ ((MASK) == I2C_OA2_MASK04) || \
+ ((MASK) == I2C_OA2_MASK05) || \
+ ((MASK) == I2C_OA2_MASK06) || \
+ ((MASK) == I2C_OA2_MASK07))
+
+#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
+ ((CALL) == I2C_GENERALCALL_ENABLE))
+
+#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
+ ((STRETCH) == I2C_NOSTRETCH_ENABLE))
+
+#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
+ ((SIZE) == I2C_MEMADD_SIZE_16BIT))
+
+#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
+ ((MODE) == I2C_AUTOEND_MODE) || \
+ ((MODE) == I2C_SOFTEND_MODE))
+
+#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
+ ((REQUEST) == I2C_GENERATE_START_READ) || \
+ ((REQUEST) == I2C_GENERATE_START_WRITE) || \
+ ((REQUEST) == I2C_GENERATE_NO_START_READ) || \
+ ((REQUEST) == I2C_GENERATE_NO_START_WRITE)|| \
+ ((REQUEST) == I2C_NO_STARTSTOP))
+
+#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
+ ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
+ ((REQUEST) == I2C_NEXT_FRAME) || \
+ ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
+ ((REQUEST) == I2C_LAST_FRAME) || \
+ ((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \
+ IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
+
+#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \
+ ((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
+
+#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
+ (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
+ I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
+ I2C_CR2_RD_WRN)))
+
+#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U))
+#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U))
+#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
+#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
+#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
+
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
+
+#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \
+ (uint16_t)(0xFF00U))) >> 8U)))
+#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
+
+#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \
+ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
+ (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
+ (~I2C_CR2_RD_WRN)) : \
+ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
+ (I2C_CR2_ADD10) | (I2C_CR2_START)) & \
+ (~I2C_CR2_RD_WRN)))
+
+#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
+ ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
+#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
+/**
+ * @}
+ */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Functions I2C Private Functions
+ * @{
+ */
+/* Private functions are defined in stm32u5xx_hal_i2c.c file */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32U5xx_HAL_I2C_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_i2c_ex.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_i2c_ex.h
new file mode 100644
index 00000000..f32174df
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_i2c_ex.h
@@ -0,0 +1,308 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_i2c_ex.h
+ * @author MCD Application Team
+ * @brief Header file of I2C HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_I2C_EX_H
+#define STM32U5xx_HAL_I2C_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup I2CEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup I2C_Exported_Types I2C Exported Types
+ * @{
+ */
+
+/** @defgroup I2C_Autonomous_Mode_Configuration_Structure_definition I2C Autonomous Mode Configuration Structure
+ definition
+ * @brief I2C Autonomous Mode Configuration structure definition
+ * @{
+ */
+typedef struct
+{
+ uint32_t TriggerState; /*!< Specifies the trigger state. This parameter can be a value
+ of @ref I2CEx_AutonomousMode_FunctionalState */
+
+ uint32_t TriggerSelection; /*!< Specifies the autonomous mode trigger signal selection. This parameter
+ can be a value of @ref I2CEx_AutonomousMode_TriggerSelection */
+
+ uint32_t TriggerPolarity; /*!< Specifies the autonomous mode trigger signal polarity sensitivity. This parameter
+ can be a value of @ref I2CEx_AutonomousMode_TriggerPolarity */
+
+} I2C_AutonomousModeConfTypeDef;
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
+ * @{
+ */
+
+/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
+ * @{
+ */
+#define I2C_ANALOGFILTER_ENABLE 0x00000000U
+#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
+/**
+ * @}
+ */
+
+/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
+ * @{
+ */
+#define I2C_FASTMODEPLUS_ENABLE 0x00000000U /*!< Enable Fast Mode Plus */
+#define I2C_FASTMODEPLUS_DISABLE 0x00000001U /*!< Disable Fast Mode Plus */
+/**
+ * @}
+ */
+
+/** @defgroup I2CEx_AutonomousMode_FunctionalState I2C Extended Autonomous Mode State
+ * @{
+ */
+#define I2C_AUTO_MODE_DISABLE (0x00000000U) /* Autonomous mode disable */
+#define I2C_AUTO_MODE_ENABLE I2C_AUTOCR_TRIGEN /* Autonomous mode enable */
+/**
+ * @}
+ */
+
+/** @defgroup I2CEx_AutonomousMode_TriggerSelection I2C Extended Autonomous Mode Trigger Selection
+ * @{
+ */
+#define I2C_TRIG_GRP1 (0x10000000U) /* Trigger Group for I2C1, I2C2 and I2C4 */
+#define I2C_TRIG_GRP2 (0x20000000U) /* Trigger Group for I2C3 */
+
+/* HW Trigger signal is GPDMA_CH0_TRG */
+#define I2C_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x00000000U))
+/* HW Trigger signal is GPDMA_CH1_TRG */
+#define I2C_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is GPDMA_CH2_TRG */
+#define I2C_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is GPDMA_CH3_TRG */
+#define I2C_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is EXTI5_TRG */
+#define I2C_GRP1_EXTI5_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is EXTI9_TRG */
+#define I2C_GRP1_EXTI9_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is LPTIM1_CH1_TRG */
+#define I2C_GRP1_LPTIM1_CH1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is LPTIM2_CH1_TRG */
+#define I2C_GRP1_LPTIM2_CH1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is COMP1_TRG */
+#define I2C_GRP1_COMP1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is COMP2_TRG */
+#define I2C_GRP1_COMP2_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is RTC_ALRA_TRG */
+#define I2C_GRP1_RTC_ALRA_TRG (uint32_t)(I2C_TRIG_GRP1 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is RTC_WUT_TRG */
+#define I2C_GRP1_RTC_WUT_TRG (uint32_t)(I2C_TRIG_GRP1 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos))
+
+/* HW Trigger signal is LPDMA_CH0_TRG */
+#define I2C_GRP2_LPDMA_CH0_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x00000000U))
+/* HW Trigger signal is LPDMA_CH1_TRG */
+#define I2C_GRP2_LPDMA_CH1_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is LPDMA_CH2_TRG */
+#define I2C_GRP2_LPDMA_CH2_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is LPDMA_CH3_TRG */
+#define I2C_GRP2_LPDMA_CH3_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is EXTI5_TRG */
+#define I2C_GRP2_EXTI5_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is EXTI8_TRG */
+#define I2C_GRP2_EXTI8_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is LPTIM1_CH1_TRG */
+#define I2C_GRP2_LPTIM1_CH1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is LPTIM3_CH1_TRG */
+#define I2C_GRP2_LPTIM3_CH1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is COMP1_TRG */
+#define I2C_GRP2_COMP1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is COMP2_TRG */
+#define I2C_GRP2_COMP2_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is RTC_ALRA_TRG */
+#define I2C_GRP2_RTC_ALRA_TRG (uint32_t)(I2C_TRIG_GRP2 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is RTC_WUT_TRG */
+#define I2C_GRP2_RTC_WUT_TRG (uint32_t)(I2C_TRIG_GRP2 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos))
+/**
+ * @}
+ */
+
+/** @defgroup I2CEx_AutonomousMode_TriggerPolarity I2C Extended Autonomous Mode Trigger Polarity
+ * @{
+ */
+#define I2C_TRIG_POLARITY_RISING (0x00000000U) /* I2C HW Trigger signal on rising edge */
+#define I2C_TRIG_POLARITY_FALLING I2C_AUTOCR_TRIGPOL /* I2C HW Trigger signal on falling edge */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
+ * @{
+ */
+
+/** @addtogroup I2CEx_Exported_Functions_Group1 I2C Extended Filter Mode Functions
+ * @{
+ */
+/* Peripheral Control functions ************************************************/
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
+/**
+ * @}
+ */
+
+/** @addtogroup I2CEx_Exported_Functions_Group2 I2C Extended WakeUp Mode Functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
+/**
+ * @}
+ */
+
+/** @addtogroup I2CEx_Exported_Functions_Group3 I2C Extended FastModePlus Functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_I2CEx_ConfigFastModePlus(I2C_HandleTypeDef *hi2c, uint32_t FastModePlus);
+/**
+ * @}
+ */
+
+/** @addtogroup I2CEx_Exported_Functions_Group4 I2C Extended Autonomous Mode Functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_I2CEx_SetConfigAutonomousMode(I2C_HandleTypeDef *hi2c, I2C_AutonomousModeConfTypeDef *sConfig);
+HAL_StatusTypeDef HAL_I2CEx_GetConfigAutonomousMode(I2C_HandleTypeDef *hi2c, I2C_AutonomousModeConfTypeDef *sConfig);
+HAL_StatusTypeDef HAL_I2CEx_ClearConfigAutonomousMode(I2C_HandleTypeDef *hi2c);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
+ * @{
+ */
+#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
+ ((FILTER) == I2C_ANALOGFILTER_DISABLE))
+
+#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
+
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) (((__CONFIG__) == (I2C_FASTMODEPLUS_ENABLE)) || \
+ ((__CONFIG__) == (I2C_FASTMODEPLUS_DISABLE)))
+
+#define IS_I2C_AUTO_MODE(__MODE__) (((__MODE__) == I2C_AUTO_MODE_DISABLE) || \
+ ((__MODE__) == I2C_AUTO_MODE_ENABLE))
+
+#define IS_I2C_TRIG_SOURCE(__INSTANCE__, __SOURCE__) (((__INSTANCE__) == I2C3) ? \
+ IS_I2C_GRP2_TRIG_SOURCE(__SOURCE__) : \
+ IS_I2C_GRP1_TRIG_SOURCE(__SOURCE__))
+
+#define IS_I2C_GRP1_TRIG_SOURCE(__SOURCE__) (((__SOURCE__) == I2C_GRP1_GPDMA_CH0_TCF_TRG ) || \
+ ((__SOURCE__) == I2C_GRP1_GPDMA_CH1_TCF_TRG ) || \
+ ((__SOURCE__) == I2C_GRP1_GPDMA_CH2_TCF_TRG ) || \
+ ((__SOURCE__) == I2C_GRP1_GPDMA_CH3_TCF_TRG ) || \
+ ((__SOURCE__) == I2C_GRP1_EXTI5_TRG ) || \
+ ((__SOURCE__) == I2C_GRP1_EXTI9_TRG ) || \
+ ((__SOURCE__) == I2C_GRP1_LPTIM1_CH1_TRG ) || \
+ ((__SOURCE__) == I2C_GRP1_LPTIM2_CH1_TRG ) || \
+ ((__SOURCE__) == I2C_GRP1_COMP1_TRG ) || \
+ ((__SOURCE__) == I2C_GRP1_COMP2_TRG ) || \
+ ((__SOURCE__) == I2C_GRP1_RTC_ALRA_TRG ) || \
+ ((__SOURCE__) == I2C_GRP1_RTC_WUT_TRG ))
+
+#define IS_I2C_GRP2_TRIG_SOURCE(__SOURCE__) (((__SOURCE__) == I2C_GRP2_LPDMA_CH0_TCF_TRG ) || \
+ ((__SOURCE__) == I2C_GRP2_LPDMA_CH1_TCF_TRG ) || \
+ ((__SOURCE__) == I2C_GRP2_LPDMA_CH2_TCF_TRG ) || \
+ ((__SOURCE__) == I2C_GRP2_LPDMA_CH3_TCF_TRG ) || \
+ ((__SOURCE__) == I2C_GRP2_EXTI5_TRG ) || \
+ ((__SOURCE__) == I2C_GRP2_EXTI8_TRG ) || \
+ ((__SOURCE__) == I2C_GRP2_LPTIM1_CH1_TRG ) || \
+ ((__SOURCE__) == I2C_GRP2_LPTIM3_CH1_TRG ) || \
+ ((__SOURCE__) == I2C_GRP2_COMP1_TRG ) || \
+ ((__SOURCE__) == I2C_GRP2_COMP2_TRG ) || \
+ ((__SOURCE__) == I2C_GRP2_RTC_ALRA_TRG ) || \
+ ((__SOURCE__) == I2C_GRP2_RTC_WUT_TRG ))
+
+#define IS_I2C_AUTO_MODE_TRG_POL(__POLARITY__) (((__POLARITY__) == I2C_TRIG_POLARITY_RISING) || \
+ ((__POLARITY__) == I2C_TRIG_POLARITY_FALLING))
+/**
+ * @}
+ */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
+ * @{
+ */
+/* Private functions are defined in stm32u5xx_hal_i2c_ex.c file */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_I2C_EX_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_icache.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_icache.h
new file mode 100644
index 00000000..fa066e32
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_icache.h
@@ -0,0 +1,291 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_icache.h
+ * @author MCD Application Team
+ * @brief Header file of ICACHE HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion ------------------------------------*/
+#ifndef STM32U5xx_HAL_ICACHE_H
+#define STM32U5xx_HAL_ICACHE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes -----------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup ICACHE
+ * @{
+ */
+
+/* Exported types -----------------------------------------------------------*/
+/** @defgroup ICACHE_Exported_Types ICACHE Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL ICACHE region configuration structure definition
+ */
+typedef struct
+{
+ uint32_t BaseAddress; /*!< Configures the Base address of Region i to be remapped */
+
+ uint32_t RemapAddress; /*!< Configures the Remap address of Region i to be remapped */
+
+ uint32_t Size; /*!< Configures the Region size.
+ This parameter can be a value of @ref ICACHE_Region_Size */
+
+ uint32_t TrafficRoute; /*!< Selects the traffic route.
+ This parameter can be a value of @ref ICACHE_Traffic_Route */
+
+ uint32_t OutputBurstType; /*!< Selects the output burst type.
+ This parameter can be a value of @ref ICACHE_Output_Burst_Type */
+} ICACHE_RegionConfigTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants -------------------------------------------------------*/
+/** @defgroup ICACHE_Exported_Constants ICACHE Exported Constants
+ * @{
+ */
+
+/** @defgroup ICACHE_WaysSelection Ways selection
+ * @{
+ */
+#define ICACHE_1WAY 0U /*!< 1-way cache (direct mapped cache) */
+#define ICACHE_2WAYS ICACHE_CR_WAYSEL /*!< 2-ways set associative cache (default) */
+/**
+ * @}
+ */
+
+/** @defgroup ICACHE_Monitor_Type Monitor type
+ * @{
+ */
+#define ICACHE_MONITOR_HIT_MISS (ICACHE_CR_HITMEN | ICACHE_CR_MISSMEN) /*!< Hit & Miss monitoring */
+#define ICACHE_MONITOR_HIT ICACHE_CR_HITMEN /*!< Hit monitoring */
+#define ICACHE_MONITOR_MISS ICACHE_CR_MISSMEN /*!< Miss monitoring */
+/**
+ * @}
+ */
+
+/** @defgroup ICACHE_Region Remapped Region number
+ * @{
+ */
+#define ICACHE_REGION_0 0U /*!< Region 0 */
+#define ICACHE_REGION_1 1U /*!< Region 1 */
+#define ICACHE_REGION_2 2U /*!< Region 2 */
+#define ICACHE_REGION_3 3U /*!< Region 3 */
+/**
+ * @}
+ */
+
+/** @defgroup ICACHE_Region_Size Remapped Region size
+ * @{
+ */
+#define ICACHE_REGIONSIZE_2MB 1U /*!< Region size 2MB */
+#define ICACHE_REGIONSIZE_4MB 2U /*!< Region size 4MB */
+#define ICACHE_REGIONSIZE_8MB 3U /*!< Region size 8MB */
+#define ICACHE_REGIONSIZE_16MB 4U /*!< Region size 16MB */
+#define ICACHE_REGIONSIZE_32MB 5U /*!< Region size 32MB */
+#define ICACHE_REGIONSIZE_64MB 6U /*!< Region size 64MB */
+#define ICACHE_REGIONSIZE_128MB 7U /*!< Region size 128MB */
+/**
+ * @}
+ */
+
+/** @defgroup ICACHE_Traffic_Route Remapped Traffic route
+ * @{
+ */
+#define ICACHE_MASTER1_PORT 0U /*!< Master1 port */
+#define ICACHE_MASTER2_PORT ICACHE_CRRx_MSTSEL /*!< Master2 port */
+/**
+ * @}
+ */
+
+/** @defgroup ICACHE_Output_Burst_Type Remapped Output burst type
+ * @{
+ */
+#define ICACHE_OUTPUT_BURST_WRAP 0U /*!< WRAP */
+#define ICACHE_OUTPUT_BURST_INCR ICACHE_CRRx_HBURST /*!< INCR */
+/**
+ * @}
+ */
+
+/** @defgroup ICACHE_Interrupts Interrupts
+ * @{
+ */
+#define ICACHE_IT_BUSYEND ICACHE_IER_BSYENDIE /*!< Busy end interrupt */
+#define ICACHE_IT_ERROR ICACHE_IER_ERRIE /*!< Cache error interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup ICACHE_Flags Flags
+ * @{
+ */
+#define ICACHE_FLAG_BUSY ICACHE_SR_BUSYF /*!< Busy flag */
+#define ICACHE_FLAG_BUSYEND ICACHE_SR_BSYENDF /*!< Busy end flag */
+#define ICACHE_FLAG_ERROR ICACHE_SR_ERRF /*!< Cache error flag */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros ----------------------------------------------------------*/
+/** @defgroup ICACHE_Exported_Macros ICACHE Exported Macros
+ * @{
+ */
+
+/** @defgroup ICACHE_Flags_Interrupts_Management Flags and Interrupts Management
+ * @brief macros to manage the specified ICACHE flags and interrupts.
+ * @{
+ */
+
+/** @brief Enable ICACHE interrupts.
+ * @param __INTERRUPT__ specifies the ICACHE interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg @ref ICACHE_IT_BUSYEND Busy end interrupt
+ * @arg @ref ICACHE_IT_ERROR Cache error interrupt
+ */
+#define __HAL_ICACHE_ENABLE_IT(__INTERRUPT__) SET_BIT(ICACHE->IER, (__INTERRUPT__))
+
+/** @brief Disable ICACHE interrupts.
+ * @param __INTERRUPT__ specifies the ICACHE interrupt sources to be disabled.
+ * This parameter can be any combination of the following values:
+ * @arg @ref ICACHE_IT_BUSYEND Busy end interrupt
+ * @arg @ref ICACHE_IT_ERROR Cache error interrupt
+ */
+#define __HAL_ICACHE_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(ICACHE->IER, (__INTERRUPT__))
+
+/** @brief Check whether the specified ICACHE interrupt source is enabled or not.
+ * @param __INTERRUPT__ specifies the ICACHE interrupt source to check.
+ * This parameter can be any combination of the following values:
+ * @arg @ref ICACHE_IT_BUSYEND Busy end interrupt
+ * @arg @ref ICACHE_IT_ERROR Cache error interrupt
+ * @retval The state of __INTERRUPT__ (0 or 1).
+ */
+#define __HAL_ICACHE_GET_IT_SOURCE(__INTERRUPT__) \
+ ((READ_BIT(ICACHE->IER, (__INTERRUPT__)) == (__INTERRUPT__)) ? 1U : 0U)
+
+/** @brief Check whether the selected ICACHE flag is set or not.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref ICACHE_FLAG_BUSY Busy flag
+ * @arg @ref ICACHE_FLAG_BUSYEND Busy end flag
+ * @arg @ref ICACHE_FLAG_ERROR Cache error flag
+ * @retval The state of __FLAG__ (0 or 1).
+ */
+#define __HAL_ICACHE_GET_FLAG(__FLAG__) ((READ_BIT(ICACHE->SR, (__FLAG__)) != 0U) ? 1U : 0U)
+
+/** @brief Clear the selected ICACHE flags.
+ * @param __FLAG__ specifies the ICACHE flags to clear.
+ * This parameter can be any combination of the following values:
+ * @arg @ref ICACHE_FLAG_BUSYEND Busy end flag
+ * @arg @ref ICACHE_FLAG_ERROR Cache error flag
+ */
+#define __HAL_ICACHE_CLEAR_FLAG(__FLAG__) WRITE_REG(ICACHE->FCR, (__FLAG__))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions -------------------------------------------------------*/
+/** @addtogroup ICACHE_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup ICACHE_Exported_Functions_Group1
+ * @brief Initialization and control functions
+ * @{
+ */
+/* Peripheral Control functions **********************************************/
+HAL_StatusTypeDef HAL_ICACHE_Enable(void);
+HAL_StatusTypeDef HAL_ICACHE_Disable(void);
+HAL_StatusTypeDef HAL_ICACHE_ConfigAssociativityMode(uint32_t AssociativityMode);
+HAL_StatusTypeDef HAL_ICACHE_DeInit(void);
+
+/******* Invalidate in blocking mode (Polling) */
+HAL_StatusTypeDef HAL_ICACHE_Invalidate(void);
+/******* Invalidate in non-blocking mode (Interrupt) */
+HAL_StatusTypeDef HAL_ICACHE_Invalidate_IT(void);
+/******* Wait for Invalidate complete in blocking mode (Polling) */
+HAL_StatusTypeDef HAL_ICACHE_WaitForInvalidateComplete(void);
+
+/******* Performance instruction cache monitoring functions */
+HAL_StatusTypeDef HAL_ICACHE_Monitor_Start(uint32_t MonitorType);
+HAL_StatusTypeDef HAL_ICACHE_Monitor_Stop(uint32_t MonitorType);
+HAL_StatusTypeDef HAL_ICACHE_Monitor_Reset(uint32_t MonitorType);
+uint32_t HAL_ICACHE_Monitor_GetHitValue(void);
+uint32_t HAL_ICACHE_Monitor_GetMissValue(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup ICACHE_Exported_Functions_Group2
+ * @brief IRQ and callback functions
+ * @{
+ */
+/******* IRQHandler and Callbacks used in non-blocking mode (Interrupt) */
+void HAL_ICACHE_IRQHandler(void);
+void HAL_ICACHE_InvalidateCompleteCallback(void);
+void HAL_ICACHE_ErrorCallback(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup ICACHE_Exported_Functions_Group3
+ * @brief Memory remapped regions functions
+ * @{
+ */
+/******* Memory remapped regions functions */
+HAL_StatusTypeDef HAL_ICACHE_EnableRemapRegion(uint32_t Region, const ICACHE_RegionConfigTypeDef *const pRegionConfig);
+HAL_StatusTypeDef HAL_ICACHE_DisableRemapRegion(uint32_t Region);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_ICACHE_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_irda.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_irda.h
new file mode 100644
index 00000000..fb6a20e8
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_irda.h
@@ -0,0 +1,891 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_irda.h
+ * @author MCD Application Team
+ * @brief Header file of IRDA HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_IRDA_H
+#define STM32U5xx_HAL_IRDA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup IRDA
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup IRDA_Exported_Types IRDA Exported Types
+ * @{
+ */
+
+/**
+ * @brief IRDA Init Structure definition
+ */
+typedef struct
+{
+ uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate.
+ The baud rate register is computed using the following formula:
+ Baud Rate Register = ((usart_ker_ckpres) / ((hirda->Init.BaudRate)))
+ where usart_ker_ckpres is the IRDA input clock divided by a prescaler */
+
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref IRDAEx_Word_Length */
+
+ uint32_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref IRDA_Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits). */
+
+ uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref IRDA_Transfer_Mode */
+
+ uint8_t Prescaler; /*!< Specifies the Prescaler value for dividing the UART/USART source clock
+ to achieve low-power frequency.
+ @note Prescaler value 0 is forbidden */
+
+ uint16_t PowerMode; /*!< Specifies the IRDA power mode.
+ This parameter can be a value of @ref IRDA_Low_Power */
+
+ uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the IRDA clock source.
+ This parameter can be a value of @ref IRDA_ClockPrescaler. */
+
+} IRDA_InitTypeDef;
+
+/**
+ * @brief HAL IRDA State definition
+ * @note HAL IRDA State value is a combination of 2 different substates:
+ * gState and RxState (see @ref IRDA_State_Definition).
+ * - gState contains IRDA state information related to global Handle management
+ * and also information related to Tx operations.
+ * gState value coding follow below described bitmap :
+ * b7-b6 Error information
+ * 00 : No Error
+ * 01 : (Not Used)
+ * 10 : Timeout
+ * 11 : Error
+ * b5 Peripheral initialization status
+ * 0 : Reset (Peripheral not initialized)
+ * 1 : Init done (Peripheral initialized. HAL IRDA Init function already called)
+ * b4-b3 (not used)
+ * xx : Should be set to 00
+ * b2 Intrinsic process state
+ * 0 : Ready
+ * 1 : Busy (Peripheral busy with some configuration or internal operations)
+ * b1 (not used)
+ * x : Should be set to 0
+ * b0 Tx state
+ * 0 : Ready (no Tx operation ongoing)
+ * 1 : Busy (Tx operation ongoing)
+ * - RxState contains information related to Rx operations.
+ * RxState value coding follow below described bitmap :
+ * b7-b6 (not used)
+ * xx : Should be set to 00
+ * b5 Peripheral initialization status
+ * 0 : Reset (Peripheral not initialized)
+ * 1 : Init done (Peripheral initialized)
+ * b4-b2 (not used)
+ * xxx : Should be set to 000
+ * b1 Rx state
+ * 0 : Ready (no Rx operation ongoing)
+ * 1 : Busy (Rx operation ongoing)
+ * b0 (not used)
+ * x : Should be set to 0.
+ */
+typedef uint32_t HAL_IRDA_StateTypeDef;
+
+/**
+ * @brief IRDA clock sources definition
+ */
+typedef enum
+{
+ IRDA_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
+ IRDA_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
+ IRDA_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
+ IRDA_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
+ IRDA_CLOCKSOURCE_LSE = 0x10U, /*!< LSE clock source */
+ IRDA_CLOCKSOURCE_UNDEFINED = 0x20U /*!< Undefined clock source */
+} IRDA_ClockSourceTypeDef;
+
+/**
+ * @brief IRDA handle Structure definition
+ */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+typedef struct __IRDA_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+{
+ USART_TypeDef *Instance; /*!< USART registers base address */
+
+ IRDA_InitTypeDef Init; /*!< IRDA communication parameters */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */
+
+ uint16_t TxXferSize; /*!< IRDA Tx Transfer size */
+
+ __IO uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /*!< Pointer to IRDA Rx transfer Buffer */
+
+ uint16_t RxXferSize; /*!< IRDA Rx Transfer size */
+
+ __IO uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */
+
+ uint16_t Mask; /*!< USART RX RDR register mask */
+
+ DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< IRDA Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< Locking object */
+
+ __IO HAL_IRDA_StateTypeDef gState; /*!< IRDA state information related to global Handle management
+ and also related to Tx operations.
+ This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
+
+ __IO HAL_IRDA_StateTypeDef RxState; /*!< IRDA state information related to Rx operations.
+ This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
+
+ __IO uint32_t ErrorCode; /*!< IRDA Error code */
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ void (* TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Half Complete Callback */
+
+ void (* TxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Complete Callback */
+
+ void (* RxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Half Complete Callback */
+
+ void (* RxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Complete Callback */
+
+ void (* ErrorCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Error Callback */
+
+ void (* AbortCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Complete Callback */
+
+ void (* AbortTransmitCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Transmit Complete Callback */
+
+ void (* AbortReceiveCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Receive Complete Callback */
+
+
+ void (* MspInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp Init callback */
+
+ void (* MspDeInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp DeInit callback */
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+
+} IRDA_HandleTypeDef;
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL IRDA Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_IRDA_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< IRDA Tx Half Complete Callback ID */
+ HAL_IRDA_TX_COMPLETE_CB_ID = 0x01U, /*!< IRDA Tx Complete Callback ID */
+ HAL_IRDA_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< IRDA Rx Half Complete Callback ID */
+ HAL_IRDA_RX_COMPLETE_CB_ID = 0x03U, /*!< IRDA Rx Complete Callback ID */
+ HAL_IRDA_ERROR_CB_ID = 0x04U, /*!< IRDA Error Callback ID */
+ HAL_IRDA_ABORT_COMPLETE_CB_ID = 0x05U, /*!< IRDA Abort Complete Callback ID */
+ HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< IRDA Abort Transmit Complete Callback ID */
+ HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< IRDA Abort Receive Complete Callback ID */
+
+ HAL_IRDA_MSPINIT_CB_ID = 0x08U, /*!< IRDA MspInit callback ID */
+ HAL_IRDA_MSPDEINIT_CB_ID = 0x09U /*!< IRDA MspDeInit callback ID */
+
+} HAL_IRDA_CallbackIDTypeDef;
+
+/**
+ * @brief HAL IRDA Callback pointer definition
+ */
+typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer to an IRDA callback function */
+
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IRDA_Exported_Constants IRDA Exported Constants
+ * @{
+ */
+
+/** @defgroup IRDA_State_Definition IRDA State Code Definition
+ * @{
+ */
+#define HAL_IRDA_STATE_RESET 0x00000000U /*!< Peripheral is not initialized
+ Value is allowed for gState and RxState */
+#define HAL_IRDA_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use
+ Value is allowed for gState and RxState */
+#define HAL_IRDA_STATE_BUSY 0x00000024U /*!< An internal process is ongoing
+ Value is allowed for gState only */
+#define HAL_IRDA_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing
+ Value is allowed for gState only */
+#define HAL_IRDA_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing
+ Value is allowed for RxState only */
+#define HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing
+ Not to be used for neither gState nor RxState.
+ Value is result of combination (Or) between
+ gState and RxState values */
+#define HAL_IRDA_STATE_TIMEOUT 0x000000A0U /*!< Timeout state
+ Value is allowed for gState only */
+#define HAL_IRDA_STATE_ERROR 0x000000E0U /*!< Error
+ Value is allowed for gState only */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Error_Definition IRDA Error Code Definition
+ * @{
+ */
+#define HAL_IRDA_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_IRDA_ERROR_PE (0x00000001U) /*!< Parity error */
+#define HAL_IRDA_ERROR_NE (0x00000002U) /*!< Noise error */
+#define HAL_IRDA_ERROR_FE (0x00000004U) /*!< frame error */
+#define HAL_IRDA_ERROR_ORE (0x00000008U) /*!< Overrun error */
+#define HAL_IRDA_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
+#define HAL_IRDA_ERROR_BUSY (0x00000020U) /*!< Busy Error */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+#define HAL_IRDA_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Parity IRDA Parity
+ * @{
+ */
+#define IRDA_PARITY_NONE 0x00000000U /*!< No parity */
+#define IRDA_PARITY_EVEN USART_CR1_PCE /*!< Even parity */
+#define IRDA_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
+ * @{
+ */
+#define IRDA_MODE_RX USART_CR1_RE /*!< RX mode */
+#define IRDA_MODE_TX USART_CR1_TE /*!< TX mode */
+#define IRDA_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Low_Power IRDA Low Power
+ * @{
+ */
+#define IRDA_POWERMODE_NORMAL 0x00000000U /*!< IRDA normal power mode */
+#define IRDA_POWERMODE_LOWPOWER USART_CR3_IRLP /*!< IRDA low power mode */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_ClockPrescaler IRDA Clock Prescaler
+ * @{
+ */
+#define IRDA_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */
+#define IRDA_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */
+#define IRDA_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */
+#define IRDA_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */
+#define IRDA_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */
+#define IRDA_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */
+#define IRDA_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */
+#define IRDA_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */
+#define IRDA_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */
+#define IRDA_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */
+#define IRDA_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */
+#define IRDA_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_State IRDA State
+ * @{
+ */
+#define IRDA_STATE_DISABLE 0x00000000U /*!< IRDA disabled */
+#define IRDA_STATE_ENABLE USART_CR1_UE /*!< IRDA enabled */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Mode IRDA Mode
+ * @{
+ */
+#define IRDA_MODE_DISABLE 0x00000000U /*!< Associated UART disabled in IRDA mode */
+#define IRDA_MODE_ENABLE USART_CR3_IREN /*!< Associated UART enabled in IRDA mode */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_One_Bit IRDA One Bit Sampling
+ * @{
+ */
+#define IRDA_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disabled */
+#define IRDA_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enabled */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_DMA_Tx IRDA DMA Tx
+ * @{
+ */
+#define IRDA_DMA_TX_DISABLE 0x00000000U /*!< IRDA DMA TX disabled */
+#define IRDA_DMA_TX_ENABLE USART_CR3_DMAT /*!< IRDA DMA TX enabled */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_DMA_Rx IRDA DMA Rx
+ * @{
+ */
+#define IRDA_DMA_RX_DISABLE 0x00000000U /*!< IRDA DMA RX disabled */
+#define IRDA_DMA_RX_ENABLE USART_CR3_DMAR /*!< IRDA DMA RX enabled */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Request_Parameters IRDA Request Parameters
+ * @{
+ */
+#define IRDA_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */
+#define IRDA_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */
+#define IRDA_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Flags IRDA Flags
+ * Elements values convention: 0xXXXX
+ * - 0xXXXX : Flag mask in the ISR register
+ * @{
+ */
+#define IRDA_FLAG_REACK USART_ISR_REACK /*!< IRDA receive enable acknowledge flag */
+#define IRDA_FLAG_TEACK USART_ISR_TEACK /*!< IRDA transmit enable acknowledge flag */
+#define IRDA_FLAG_BUSY USART_ISR_BUSY /*!< IRDA busy flag */
+#define IRDA_FLAG_ABRF USART_ISR_ABRF /*!< IRDA auto Baud rate flag */
+#define IRDA_FLAG_ABRE USART_ISR_ABRE /*!< IRDA auto Baud rate error */
+#define IRDA_FLAG_TXE USART_ISR_TXE_TXFNF /*!< IRDA transmit data register empty */
+#define IRDA_FLAG_TC USART_ISR_TC /*!< IRDA transmission complete */
+#define IRDA_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< IRDA read data register not empty */
+#define IRDA_FLAG_ORE USART_ISR_ORE /*!< IRDA overrun error */
+#define IRDA_FLAG_NE USART_ISR_NE /*!< IRDA noise error */
+#define IRDA_FLAG_FE USART_ISR_FE /*!< IRDA frame error */
+#define IRDA_FLAG_PE USART_ISR_PE /*!< IRDA parity error */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Interrupt_definition IRDA Interrupts Definition
+ * Elements values convention: 0000ZZZZ0XXYYYYYb
+ * - YYYYY : Interrupt source position in the XX register (5bits)
+ * - XX : Interrupt source register (2bits)
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
+ * - ZZZZ : Flag position in the ISR register(4bits)
+ * @{
+ */
+#define IRDA_IT_PE 0x0028U /*!< IRDA Parity error interruption */
+#define IRDA_IT_TXE 0x0727U /*!< IRDA Transmit data register empty interruption */
+#define IRDA_IT_TC 0x0626U /*!< IRDA Transmission complete interruption */
+#define IRDA_IT_RXNE 0x0525U /*!< IRDA Read data register not empty interruption */
+#define IRDA_IT_IDLE 0x0424U /*!< IRDA Idle interruption */
+
+/* Elements values convention: 000000000XXYYYYYb
+ - YYYYY : Interrupt source position in the XX register (5bits)
+ - XX : Interrupt source register (2bits)
+ - 01: CR1 register
+ - 10: CR2 register
+ - 11: CR3 register */
+#define IRDA_IT_ERR 0x0060U /*!< IRDA Error interruption */
+
+/* Elements values convention: 0000ZZZZ00000000b
+ - ZZZZ : Flag position in the ISR register(4bits) */
+#define IRDA_IT_ORE 0x0300U /*!< IRDA Overrun error interruption */
+#define IRDA_IT_NE 0x0200U /*!< IRDA Noise error interruption */
+#define IRDA_IT_FE 0x0100U /*!< IRDA Frame error interruption */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags
+ * @{
+ */
+#define IRDA_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
+#define IRDA_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
+#define IRDA_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */
+#define IRDA_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
+#define IRDA_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
+#define IRDA_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Interruption_Mask IRDA interruptions flags mask
+ * @{
+ */
+#define IRDA_IT_MASK 0x001FU /*!< IRDA Interruptions flags mask */
+#define IRDA_CR_MASK 0x00E0U /*!< IRDA control register mask */
+#define IRDA_CR_POS 5U /*!< IRDA control register position */
+#define IRDA_ISR_MASK 0x1F00U /*!< IRDA ISR register mask */
+#define IRDA_ISR_POS 8U /*!< IRDA ISR register position */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
+ * @{
+ */
+
+/** @brief Reset IRDA handle state.
+ * @param __HANDLE__ IRDA handle.
+ * @retval None
+ */
+#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
+#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0U)
+#else
+#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
+ } while(0U)
+#endif /*USE_HAL_IRDA_REGISTER_CALLBACKS */
+
+/** @brief Flush the IRDA DR register.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) \
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
+ SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
+ } while(0U)
+
+/** @brief Clear the specified IRDA pending flag.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg @ref IRDA_CLEAR_PEF
+ * @arg @ref IRDA_CLEAR_FEF
+ * @arg @ref IRDA_CLEAR_NEF
+ * @arg @ref IRDA_CLEAR_OREF
+ * @arg @ref IRDA_CLEAR_TCF
+ * @arg @ref IRDA_CLEAR_IDLEF
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief Clear the IRDA PE pending flag.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
+
+
+/** @brief Clear the IRDA FE pending flag.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
+
+/** @brief Clear the IRDA NE pending flag.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
+
+/** @brief Clear the IRDA ORE pending flag.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
+
+/** @brief Clear the IRDA IDLE pending flag.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
+
+/** @brief Check whether the specified IRDA flag is set or not.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref IRDA_FLAG_REACK Receive enable acknowledge flag
+ * @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag
+ * @arg @ref IRDA_FLAG_BUSY Busy flag
+ * @arg @ref IRDA_FLAG_ABRF Auto Baud rate detection flag
+ * @arg @ref IRDA_FLAG_ABRE Auto Baud rate detection error flag
+ * @arg @ref IRDA_FLAG_TXE Transmit data register empty flag
+ * @arg @ref IRDA_FLAG_TC Transmission Complete flag
+ * @arg @ref IRDA_FLAG_RXNE Receive data register not empty flag
+ * @arg @ref IRDA_FLAG_ORE OverRun Error flag
+ * @arg @ref IRDA_FLAG_NE Noise Error flag
+ * @arg @ref IRDA_FLAG_FE Framing Error flag
+ * @arg @ref IRDA_FLAG_PE Parity Error flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+
+/** @brief Enable the specified IRDA interrupt.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @param __INTERRUPT__ specifies the IRDA interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref IRDA_IT_TC Transmission complete interrupt
+ * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref IRDA_IT_IDLE Idle line detection interrupt
+ * @arg @ref IRDA_IT_PE Parity Error interrupt
+ * @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \
+ ((__HANDLE__)->Instance->CR1 |= (1U << \
+ ((__INTERRUPT__) & IRDA_IT_MASK))):\
+ ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \
+ ((__HANDLE__)->Instance->CR2 |= (1U << \
+ ((__INTERRUPT__) & IRDA_IT_MASK))):\
+ ((__HANDLE__)->Instance->CR3 |= (1U << \
+ ((__INTERRUPT__) & IRDA_IT_MASK))))
+
+/** @brief Disable the specified IRDA interrupt.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @param __INTERRUPT__ specifies the IRDA interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref IRDA_IT_TC Transmission complete interrupt
+ * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref IRDA_IT_IDLE Idle line detection interrupt
+ * @arg @ref IRDA_IT_PE Parity Error interrupt
+ * @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \
+ ((__HANDLE__)->Instance->CR1 &= ~ (1U << \
+ ((__INTERRUPT__) & IRDA_IT_MASK))): \
+ ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \
+ ((__HANDLE__)->Instance->CR2 &= ~ (1U << \
+ ((__INTERRUPT__) & IRDA_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 &= ~ (1U << \
+ ((__INTERRUPT__) & IRDA_IT_MASK))))
+
+/** @brief Check whether the specified IRDA interrupt has occurred or not.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @param __INTERRUPT__ specifies the IRDA interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref IRDA_IT_TC Transmission complete interrupt
+ * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref IRDA_IT_IDLE Idle line detection interrupt
+ * @arg @ref IRDA_IT_ORE OverRun Error interrupt
+ * @arg @ref IRDA_IT_NE Noise Error interrupt
+ * @arg @ref IRDA_IT_FE Framing Error interrupt
+ * @arg @ref IRDA_IT_PE Parity Error interrupt
+ * @retval The new state of __IT__ (SET or RESET).
+ */
+#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) \
+ ((((__HANDLE__)->Instance->ISR& (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>>IRDA_ISR_POS))) != 0U) ? SET : RESET)
+
+/** @brief Check whether the specified IRDA interrupt source is enabled or not.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @param __INTERRUPT__ specifies the IRDA interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref IRDA_IT_TC Transmission complete interrupt
+ * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref IRDA_IT_IDLE Idle line detection interrupt
+ * @arg @ref IRDA_IT_ERR Framing, overrun or noise error interrupt
+ * @arg @ref IRDA_IT_PE Parity Error interrupt
+ * @retval The new state of __IT__ (SET or RESET).
+ */
+#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+ ((((((((__INTERRUPT__) & IRDA_CR_MASK) >>IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 :(((((__INTERRUPT__) \
+ & IRDA_CR_MASK) >> IRDA_CR_POS)== 0x02U)? (__HANDLE__)->Instance->CR2 :(__HANDLE__)->Instance->CR3)) \
+ & (0x01U <<(((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
+
+/** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
+ * to clear the corresponding interrupt
+ * This parameter can be one of the following values:
+ * @arg @ref IRDA_CLEAR_PEF Parity Error Clear Flag
+ * @arg @ref IRDA_CLEAR_FEF Framing Error Clear Flag
+ * @arg @ref IRDA_CLEAR_NEF Noise detected Clear Flag
+ * @arg @ref IRDA_CLEAR_OREF OverRun Error Clear Flag
+ * @arg @ref IRDA_CLEAR_TCF Transmission Complete Clear Flag
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+
+
+/** @brief Set a specific IRDA request flag.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @param __REQ__ specifies the request flag to set
+ * This parameter can be one of the following values:
+ * @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request
+ * @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request
+ * @arg @ref IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request
+ * @retval None
+ */
+#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
+
+/** @brief Enable the IRDA one bit sample method.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief Disable the IRDA one bit sample method.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
+ &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
+
+/** @brief Enable UART/USART associated to IRDA Handle.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+
+/** @brief Disable UART/USART associated to IRDA Handle.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @addtogroup IRDA_Private_Macros
+ * @{
+ */
+
+/** @brief Ensure that IRDA Baud rate is less or equal to maximum value.
+ * @param __BAUDRATE__ specifies the IRDA Baudrate set by the user.
+ * @retval True or False
+ */
+#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U)
+
+/** @brief Ensure that IRDA prescaler value is strictly larger than 0.
+ * @param __PRESCALER__ specifies the IRDA prescaler value set by the user.
+ * @retval True or False
+ */
+#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U)
+
+/** @brief Ensure that IRDA frame parity is valid.
+ * @param __PARITY__ IRDA frame parity.
+ * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+ */
+#define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \
+ ((__PARITY__) == IRDA_PARITY_EVEN) || \
+ ((__PARITY__) == IRDA_PARITY_ODD))
+
+/** @brief Ensure that IRDA communication mode is valid.
+ * @param __MODE__ IRDA communication mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__)\
+ & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
+
+/** @brief Ensure that IRDA power mode is valid.
+ * @param __MODE__ IRDA power mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
+ ((__MODE__) == IRDA_POWERMODE_NORMAL))
+
+/** @brief Ensure that IRDA clock Prescaler is valid.
+ * @param __CLOCKPRESCALER__ IRDA clock Prescaler value.
+ * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
+ */
+#define IS_IRDA_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV1) || \
+ ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV2) || \
+ ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV4) || \
+ ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV6) || \
+ ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV8) || \
+ ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV10) || \
+ ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV12) || \
+ ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV16) || \
+ ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV32) || \
+ ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV64) || \
+ ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV128) || \
+ ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV256))
+
+/** @brief Ensure that IRDA state is valid.
+ * @param __STATE__ IRDA state mode.
+ * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
+ */
+#define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \
+ ((__STATE__) == IRDA_STATE_ENABLE))
+
+/** @brief Ensure that IRDA associated UART/USART mode is valid.
+ * @param __MODE__ IRDA associated UART/USART mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_IRDA_MODE(__MODE__) (((__MODE__) == IRDA_MODE_DISABLE) || \
+ ((__MODE__) == IRDA_MODE_ENABLE))
+
+/** @brief Ensure that IRDA sampling rate is valid.
+ * @param __ONEBIT__ IRDA sampling rate.
+ * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
+ */
+#define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
+ ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))
+
+/** @brief Ensure that IRDA DMA TX mode is valid.
+ * @param __DMATX__ IRDA DMA TX mode.
+ * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
+ */
+#define IS_IRDA_DMA_TX(__DMATX__) (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
+ ((__DMATX__) == IRDA_DMA_TX_ENABLE))
+
+/** @brief Ensure that IRDA DMA RX mode is valid.
+ * @param __DMARX__ IRDA DMA RX mode.
+ * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
+ */
+#define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
+ ((__DMARX__) == IRDA_DMA_RX_ENABLE))
+
+/** @brief Ensure that IRDA request is valid.
+ * @param __PARAM__ IRDA request.
+ * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+ */
+#define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \
+ ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
+ ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))
+/**
+ * @}
+ */
+
+/* Include IRDA HAL Extended module */
+#include "stm32u5xx_hal_irda_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
+ * @{
+ */
+
+/** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+/* Callbacks Register/UnRegister functions ***********************************/
+HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID,
+ pIRDA_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
+
+void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda);
+
+/**
+ * @}
+ */
+
+/* Peripheral Control functions ************************************************/
+
+/** @addtogroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
+ * @{
+ */
+
+/* Peripheral State and Error functions ***************************************/
+HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
+uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_IRDA_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_irda_ex.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_irda_ex.h
new file mode 100644
index 00000000..759eddcf
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_irda_ex.h
@@ -0,0 +1,392 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_irda_ex.h
+ * @author MCD Application Team
+ * @brief Header file of IRDA HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_IRDA_EX_H
+#define STM32U5xx_HAL_IRDA_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup IRDAEx IRDAEx
+ * @brief IRDA Extended HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IRDAEx_Extended_Exported_Constants IRDAEx Extended Exported Constants
+ * @{
+ */
+
+/** @defgroup IRDAEx_Word_Length IRDAEx Word Length
+ * @{
+ */
+#define IRDA_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long frame */
+#define IRDA_WORDLENGTH_8B 0x00000000U /*!< 8-bit long frame */
+#define IRDA_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long frame */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros
+ * @{
+ */
+
+/** @brief Report the IRDA clock source.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @param __CLOCKSOURCE__ output variable.
+ * @retval IRDA clocking source, written in __CLOCKSOURCE__.
+ */
+#if defined(USART6)
+#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK2: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
+ case RCC_USART3CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART3CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART3CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART3CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == UART4) \
+ { \
+ switch(__HAL_RCC_GET_UART4_SOURCE()) \
+ { \
+ case RCC_UART4CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_UART4CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_UART4CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_UART4CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == UART5) \
+ { \
+ switch(__HAL_RCC_GET_UART5_SOURCE()) \
+ { \
+ case RCC_UART5CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_UART5CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_UART5CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_UART5CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART6) \
+ { \
+ switch(__HAL_RCC_GET_USART6_SOURCE()) \
+ { \
+ case RCC_USART6CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART6CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART6CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART6CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0U)
+#else
+#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK2: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
+ case RCC_USART3CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART3CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART3CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART3CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == UART4) \
+ { \
+ switch(__HAL_RCC_GET_UART4_SOURCE()) \
+ { \
+ case RCC_UART4CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_UART4CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_UART4CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_UART4CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == UART5) \
+ { \
+ switch(__HAL_RCC_GET_UART5_SOURCE()) \
+ { \
+ case RCC_UART5CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_UART5CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_UART5CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_UART5CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0U)
+#endif /* USART6 */
+
+/** @brief Compute the mask to apply to retrieve the received data
+ * according to the word length and to the parity bits activation.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field.
+ */
+#define IRDA_MASK_COMPUTATION(__HANDLE__) \
+ do { \
+ if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x01FFU ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x00FFU ; \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x00FFU ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x007FU ; \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x007FU ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x003FU ; \
+ } \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x0000U; \
+ } \
+ } while(0U)
+
+/** @brief Ensure that IRDA frame length is valid.
+ * @param __LENGTH__ IRDA frame length.
+ * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+ */
+#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \
+ ((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
+ ((__LENGTH__) == IRDA_WORDLENGTH_9B))
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_IRDA_EX_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_iwdg.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_iwdg.h
new file mode 100644
index 00000000..90f3f7ea
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_iwdg.h
@@ -0,0 +1,292 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_iwdg.h
+ * @author MCD Application Team
+ * @brief Header file of IWDG HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_IWDG_H
+#define STM32U5xx_HAL_IWDG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup IWDG IWDG
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Types IWDG Exported Types
+ * @{
+ */
+
+/**
+ * @brief IWDG Init structure definition
+ */
+typedef struct
+{
+ uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
+ This parameter can be a value of @ref IWDG_Prescaler */
+
+ uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
+
+ uint32_t Window; /*!< Specifies the window value to be compared to the down-counter.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
+
+ uint32_t EWI; /*!< Specifies if IWDG Early Wakeup Interrupt is enable or not and the comparator value.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF
+ value 0 means that EWI is disabled */
+} IWDG_InitTypeDef;
+
+/**
+ * @brief IWDG Handle Structure definition
+ */
+#if (USE_HAL_IWDG_REGISTER_CALLBACKS == 1)
+typedef struct __IWDG_HandleTypeDef
+#else
+typedef struct
+#endif /* (USE_HAL_IWDG_REGISTER_CALLBACKS) */
+{
+ IWDG_TypeDef *Instance; /*!< Register base address */
+
+ IWDG_InitTypeDef Init; /*!< IWDG required parameters */
+
+#if (USE_HAL_IWDG_REGISTER_CALLBACKS == 1)
+ void (* EwiCallback)(struct __IWDG_HandleTypeDef *hiwdg); /*!< IWDG Early WakeUp Interrupt callback */
+ void (* MspInitCallback)(struct __IWDG_HandleTypeDef *hiwdg); /*!< IWDG Msp Init callback */
+#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */
+} IWDG_HandleTypeDef;
+
+#if (USE_HAL_IWDG_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL IWDG common Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_IWDG_EWI_CB_ID = 0x00U, /*!< IWDG EWI callback ID */
+ HAL_IWDG_MSPINIT_CB_ID = 0x01U, /*!< IWDG MspInit callback ID */
+} HAL_IWDG_CallbackIDTypeDef;
+
+/**
+ * @brief HAL IWDG Callback pointer definition
+ */
+typedef void (*pIWDG_CallbackTypeDef)(IWDG_HandleTypeDef *hppp); /*!< pointer to a IWDG common callback functions */
+#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */
+
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
+ * @{
+ */
+
+/** @defgroup IWDG_Prescaler IWDG Prescaler
+ * @{
+ */
+#define IWDG_PRESCALER_4 0x00000000u /*!< IWDG prescaler set to 4 */
+#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */
+#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */
+#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */
+#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
+#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
+#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
+#define IWDG_PRESCALER_512 (IWDG_PR_PR_2 | IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 512 */
+#define IWDG_PRESCALER_1024 IWDG_PR_PR_3 /*!< IWDG prescaler set to 1024 */
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Window_option IWDG Window option
+ * @{
+ */
+#define IWDG_WINDOW_DISABLE IWDG_WINR_WIN
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_EWI_Mode IWDG Early Wakeup Interrupt Mode
+ * @{
+ */
+#define IWDG_EWI_DISABLE 0x00000000u /*!< EWI Disable */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Enable the IWDG peripheral.
+ * @param __HANDLE__ IWDG handle
+ * @retval None
+ */
+#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
+
+/**
+ * @brief Reload IWDG counter with value defined in the reload register
+ * (write access to IWDG_PR, IWDG_RLR, IWDG_WINR and EWCR registers disabled).
+ * @param __HANDLE__ IWDG handle
+ * @retval None
+ */
+#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
+ * @{
+ */
+
+/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
+ * @{
+ */
+/* Initialization/Start functions ********************************************/
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
+void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg);
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_IWDG_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_IWDG_RegisterCallback(IWDG_HandleTypeDef *hiwdg, HAL_IWDG_CallbackIDTypeDef CallbackID,
+ pIWDG_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_IWDG_UnRegisterCallback(IWDG_HandleTypeDef *hiwdg, HAL_IWDG_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+/* I/O operation functions ****************************************************/
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
+void HAL_IWDG_IRQHandler(IWDG_HandleTypeDef *hiwdg);
+void HAL_IWDG_EarlyWakeupCallback(IWDG_HandleTypeDef *hiwdg);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup IWDG_Private_Constants IWDG Private Constants
+ * @{
+ */
+
+/**
+ * @brief IWDG Key Register BitMask
+ */
+#define IWDG_KEY_RELOAD 0x0000AAAAu /*!< IWDG Reload Counter Enable */
+#define IWDG_KEY_ENABLE 0x0000CCCCu /*!< IWDG Peripheral Enable */
+#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u /*!< IWDG KR Write Access Enable */
+#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u /*!< IWDG KR Write Access Disable */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup IWDG_Private_Macros IWDG Private Macros
+ * @{
+ */
+
+/**
+ * @brief Enable write access to IWDG_PR, IWDG_RLR, IWDG_WINR and EWCR registers.
+ * @param __HANDLE__ IWDG handle
+ * @retval None
+ */
+#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
+
+/**
+ * @brief Disable write access to IWDG_PR, IWDG_RLR, IWDG_WINR and EWCR registers.
+ * @param __HANDLE__ IWDG handle
+ * @retval None
+ */
+#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
+
+/**
+ * @brief Check IWDG prescaler value.
+ * @param __PRESCALER__ IWDG prescaler value
+ * @retval None
+ */
+#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_8) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_16) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_32) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_64) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
+ ((__PRESCALER__) == IWDG_PRESCALER_256)|| \
+ ((__PRESCALER__) == IWDG_PRESCALER_512)|| \
+ ((__PRESCALER__) == IWDG_PRESCALER_1024))
+
+/**
+ * @brief Check IWDG reload value.
+ * @param __RELOAD__ IWDG reload value
+ * @retval None
+ */
+#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
+
+/**
+ * @brief Check IWDG window value.
+ * @param __WINDOW__ IWDG window value
+ * @retval None
+ */
+#define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
+
+/**
+ * @brief Check IWDG ewi value.
+ * @param __EWI__ IWDG ewi value
+ * @retval None
+ */
+#define IS_IWDG_EWI(__EWI__) ((__EWI__) <= IWDG_EWCR_EWIT)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_IWDG_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_lptim.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_lptim.h
new file mode 100644
index 00000000..e5326e29
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_lptim.h
@@ -0,0 +1,1175 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_lptim.h
+ * @author MCD Application Team
+ * @brief Header file of LPTIM HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_LPTIM_H
+#define STM32U5xx_HAL_LPTIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+#if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3) || defined (LPTIM4)
+
+/** @addtogroup LPTIM
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup LPTIM_Exported_Types LPTIM Exported Types
+ * @{
+ */
+
+/**
+ * @brief LPTIM Clock configuration definition
+ */
+typedef struct
+{
+ uint32_t Source; /*!< Selects the clock source.
+ This parameter can be a value of @ref LPTIM_Clock_Source */
+
+ uint32_t Prescaler; /*!< Specifies the counter clock Prescaler.
+ This parameter can be a value of @ref LPTIM_Clock_Prescaler */
+
+} LPTIM_ClockConfigTypeDef;
+
+/**
+ * @brief LPTIM Clock configuration definition
+ */
+typedef struct
+{
+ uint32_t Polarity; /*!< Selects the polarity of the active edge for the counter unit
+ if the ULPTIM input is selected.
+ Note: This parameter is used only when Ultra low power clock source is used.
+ Note: If the polarity is configured on 'both edges', an auxiliary clock
+ (one of the Low power oscillator) must be active.
+ This parameter can be a value of @ref LPTIM_Clock_Polarity */
+
+ uint32_t SampleTime; /*!< Selects the clock sampling time to configure the clock glitch filter.
+ Note: This parameter is used only when Ultra low power clock source is used.
+ This parameter can be a value of @ref LPTIM_Clock_Sample_Time */
+
+} LPTIM_ULPClockConfigTypeDef;
+
+/**
+ * @brief LPTIM Trigger configuration definition
+ */
+typedef struct
+{
+ uint32_t Source; /*!< Selects the Trigger source.
+ This parameter can be a value of @ref LPTIM_Trigger_Source */
+
+ uint32_t ActiveEdge; /*!< Selects the Trigger active edge.
+ Note: This parameter is used only when an external trigger is used.
+ This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */
+
+ uint32_t SampleTime; /*!< Selects the trigger sampling time to configure the clock glitch filter.
+ Note: This parameter is used only when an external trigger is used.
+ This parameter can be a value of @ref LPTIM_Trigger_Sample_Time */
+} LPTIM_TriggerConfigTypeDef;
+
+/**
+ * @brief LPTIM Initialization Structure definition
+ */
+typedef struct
+{
+ LPTIM_ClockConfigTypeDef Clock; /*!< Specifies the clock parameters */
+
+ LPTIM_ULPClockConfigTypeDef UltraLowPowerClock;/*!< Specifies the Ultra Low Power clock parameters */
+
+ LPTIM_TriggerConfigTypeDef Trigger; /*!< Specifies the Trigger parameters */
+
+ uint32_t Period; /*!< Specifies the period value to be loaded into the active
+ Auto-Reload Register at the next update event.
+ This parameter can be a number between
+ Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+ uint32_t UpdateMode; /*!< Specifies whether the update of the autoreload and the compare
+ values is done immediately or after the end of current period.
+ This parameter can be a value of @ref LPTIM_Updating_Mode */
+
+ uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event
+ or each external event.
+ This parameter can be a value of @ref LPTIM_Counter_Source */
+
+ uint32_t Input1Source; /*!< Specifies source selected for input1 (GPIO or comparator output).
+ This parameter can be a value of @ref LPTIM_Input1_Source */
+
+ uint32_t Input2Source; /*!< Specifies source selected for input2 (GPIO or comparator output).
+ Note: This parameter is used only for encoder feature so is used only
+ for LPTIM1 instance.
+ This parameter can be a value of @ref LPTIM_Input2_Source */
+
+ uint32_t RepetitionCounter;/*!< Specifies the repetition counter value.
+ Each time the RCR downcounter reaches zero, an update event is
+ generated and counting restarts from the RCR value (N).
+ Note: When using repetition counter the UpdateMode field must be
+ set to LPTIM_UPDATE_ENDOFPERIOD otherwise unpredictable
+ behavior may occur.
+ This parameter must be a number between Min_Data = 0x00 and
+ Max_Data = 0xFF. */
+} LPTIM_InitTypeDef;
+
+/**
+ * @brief LPTIM Output Compare Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+ uint32_t OCPolarity; /*!< Specifies the output polarity.
+ This parameter can be a value of @ref LPTIM_Output_Compare_Polarity */
+} LPTIM_OC_ConfigTypeDef;
+
+/**
+ * @brief LPTIM Input Capture Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t ICInputSource; /*!< Specifies source selected for IC channel.
+ This parameter can be a value of @ref LPTIM_Input_Capture_Source */
+
+ uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref LPTIM_Input_Capture_Prescaler */
+
+ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref LPTIM_Input_Capture_Polarity */
+
+ uint32_t ICFilter; /*!< Specifies the input capture filter.
+ This parameter can be a value of @ref LPTIM_Input_Capture_Filter */
+} LPTIM_IC_ConfigTypeDef;
+
+/**
+ * @brief HAL LPTIM State structure definition
+ */
+typedef enum
+{
+ HAL_LPTIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
+ HAL_LPTIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
+ HAL_LPTIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
+ HAL_LPTIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
+ HAL_LPTIM_STATE_ERROR = 0x04U /*!< Internal Process is ongoing */
+} HAL_LPTIM_StateTypeDef;
+
+/**
+ * @brief HAL Active channel structures definition
+ */
+typedef enum
+{
+ HAL_LPTIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
+ HAL_LPTIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
+ HAL_LPTIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */
+} HAL_LPTIM_ActiveChannel;
+
+/**
+ * @brief LPTIM Channel States definition
+ */
+typedef enum
+{
+ HAL_LPTIM_CHANNEL_STATE_RESET = 0x00U, /*!< LPTIM Channel initial state */
+ HAL_LPTIM_CHANNEL_STATE_READY = 0x01U, /*!< LPTIM Channel ready for use */
+ HAL_LPTIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the LPTIM channel */
+} HAL_LPTIM_ChannelStateTypeDef;
+
+/**
+ * @brief LPTIM handle Structure definition
+ */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+typedef struct __LPTIM_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+{
+ LPTIM_TypeDef *Instance; /*!< Register base address */
+
+ LPTIM_InitTypeDef Init; /*!< LPTIM required parameters */
+
+ HAL_LPTIM_ActiveChannel Channel; /*!< Active channel */
+
+ DMA_HandleTypeDef *hdma[3]; /*!< DMA Handlers array, This array is accessed by a @ref LPTIM_DMA_Handle_index */
+
+ HAL_StatusTypeDef Status; /*!< LPTIM peripheral status */
+
+ HAL_LockTypeDef Lock; /*!< LPTIM locking object */
+
+ __IO HAL_LPTIM_StateTypeDef State; /*!< LPTIM peripheral state */
+
+ __IO HAL_LPTIM_ChannelStateTypeDef ChannelState[2]; /*!< LPTIM channel operation state */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ void (* MspInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp Init Callback */
+ void (* MspDeInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp DeInit Callback */
+ void (* CompareMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Compare match Callback */
+ void (* AutoReloadMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Auto-reload match Callback */
+ void (* TriggerCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< External trigger event detection Callback */
+ void (* CompareWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Compare register write complete Callback */
+ void (* AutoReloadWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Auto-reload register write complete Callback */
+ void (* DirectionUpCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Up-counting direction change Callback */
+ void (* DirectionDownCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Down-counting direction change Callback */
+ void (* UpdateEventCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Update event detection Callback */
+ void (* RepCounterWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Repetition counter register write complete Callback */
+ void (* UpdateEventHalfCpltCallback)(struct __LPTIM_HandleTypeDef *hlptim);/*!< Update event half complete detection Callback */
+ void (* IC_CaptureCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Input capture Callback */
+ void (* IC_CaptureHalfCpltCallback)(struct __LPTIM_HandleTypeDef *htim); /*!< Input Capture half complete Callback */
+ void (* IC_OverCaptureCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Over capture Callback */
+ void (* ErrorCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Error Callback */
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+} LPTIM_HandleTypeDef;
+
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL LPTIM Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_LPTIM_MSPINIT_CB_ID = 0x00U, /*!< LPTIM Base Msp Init Callback ID */
+ HAL_LPTIM_MSPDEINIT_CB_ID = 0x01U, /*!< LPTIM Base Msp DeInit Callback ID */
+ HAL_LPTIM_COMPARE_MATCH_CB_ID = 0x02U, /*!< Compare match Callback ID */
+ HAL_LPTIM_AUTORELOAD_MATCH_CB_ID = 0x03U, /*!< Auto-reload match Callback ID */
+ HAL_LPTIM_TRIGGER_CB_ID = 0x04U, /*!< External trigger event detection Callback ID */
+ HAL_LPTIM_COMPARE_WRITE_CB_ID = 0x05U, /*!< Compare register write complete Callback ID */
+ HAL_LPTIM_AUTORELOAD_WRITE_CB_ID = 0x06U, /*!< Auto-reload register write complete Callback ID */
+ HAL_LPTIM_DIRECTION_UP_CB_ID = 0x07U, /*!< Up-counting direction change Callback ID */
+ HAL_LPTIM_DIRECTION_DOWN_CB_ID = 0x08U, /*!< Down-counting direction change Callback ID */
+ HAL_LPTIM_UPDATE_EVENT_CB_ID = 0x09U, /*!< Update event detection Callback ID */
+ HAL_LPTIM_REP_COUNTER_WRITE_CB_ID = 0x0AU, /*!< Repetition counter register write complete Callback ID */
+ HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID = 0x0BU, /*!< Update event half complete detection Callback ID */
+ HAL_LPTIM_IC_CAPTURE_CB_ID = 0x0CU, /*!< Input capture Callback ID */
+ HAL_LPTIM_IC_CAPTURE_HALF_CB_ID = 0x0DU, /*!< Input capture half complete Callback ID */
+ HAL_LPTIM_OVER_CAPTURE_CB_ID = 0x0EU, /*!< Over capture Callback ID */
+ HAL_LPTIM_ERROR_CB_ID = 0x0FU, /*!< LPTIM Error Callback ID */
+} HAL_LPTIM_CallbackIDTypeDef;
+
+/**
+ * @brief HAL TIM Callback pointer definition
+ */
+typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< pointer to the LPTIM callback function */
+
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants
+ * @{
+ */
+
+/** @defgroup LPTIM_Clock_Source LPTIM Clock Source
+ * @{
+ */
+#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC 0x00000000U
+#define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler
+ * @{
+ */
+#define LPTIM_PRESCALER_DIV1 0x00000000U
+#define LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
+#define LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
+#define LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1)
+#define LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
+#define LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2)
+#define LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2)
+#define LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time
+ * @{
+ */
+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 0x00000000U
+#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0
+#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1
+#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity
+ * @{
+ */
+#define LPTIM_CLOCKPOLARITY_RISING 0x00000000U
+#define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0
+#define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source
+ * @{
+ */
+#define LPTIM_TRIGSOURCE_SOFTWARE 0x0000FFFFU
+#define LPTIM_TRIGSOURCE_0 0x00000000U
+#define LPTIM_TRIGSOURCE_1 LPTIM_CFGR_TRIGSEL_0
+#define LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1
+#define LPTIM_TRIGSOURCE_3 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
+#define LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2
+#define LPTIM_TRIGSOURCE_5 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
+#define LPTIM_TRIGSOURCE_6 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)
+#define LPTIM_TRIGSOURCE_7 LPTIM_CFGR_TRIGSEL
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_External_Trigger_Polarity LPTIM External Trigger Polarity
+ * @{
+ */
+#define LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0
+#define LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1
+#define LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time
+ * @{
+ */
+#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 0x00000000U
+#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0
+#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1
+#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Updating_Mode LPTIM Updating Mode
+ * @{
+ */
+
+#define LPTIM_UPDATE_IMMEDIATE 0x00000000U
+#define LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Counter_Source LPTIM Counter Source
+ * @{
+ */
+
+#define LPTIM_COUNTERSOURCE_INTERNAL 0x00000000U
+#define LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Input1_Source LPTIM Input1 Source
+ * @{
+ */
+
+#define LPTIM_INPUT1SOURCE_GPIO 0x00000000U /*!< For LPTIM1, LPTIM2, LPTIM3 and LPTIM4 */
+#define LPTIM_INPUT1SOURCE_COMP1 LPTIM_CFGR2_IN1SEL_0 /*!< For LPTIM1, LPTIM2, LPTIM3 and LPTIM4 */
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Input2_Source LPTIM Input2 Source
+ * @{
+ */
+
+#define LPTIM_INPUT2SOURCE_GPIO 0x00000000U /*!< For LPTIM1 and LPTIM2 */
+#define LPTIM_INPUT2SOURCE_COMP2 LPTIM_CFGR2_IN2SEL_0 /*!< For LPTIM1 and LPTIM2 */
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Flag_Definition LPTIM Flags Definition
+ * @{
+ */
+
+#define LPTIM_FLAG_CC1O LPTIM_ISR_CC1OF
+#define LPTIM_FLAG_CC2O LPTIM_ISR_CC2OF
+#define LPTIM_FLAG_CC1 LPTIM_ISR_CC1IF
+#define LPTIM_FLAG_CC2 LPTIM_ISR_CC2IF
+#define LPTIM_FLAG_CMP1OK LPTIM_ISR_CMP1OK
+#define LPTIM_FLAG_CMP2OK LPTIM_ISR_CMP2OK
+#define LPTIM_FLAG_DIEROK LPTIM_ISR_DIEROK
+#define LPTIM_FLAG_REPOK LPTIM_ISR_REPOK
+#define LPTIM_FLAG_UPDATE LPTIM_ISR_UE
+#define LPTIM_FLAG_DOWN LPTIM_ISR_DOWN
+#define LPTIM_FLAG_UP LPTIM_ISR_UP
+#define LPTIM_FLAG_ARROK LPTIM_ISR_ARROK
+#define LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG
+#define LPTIM_FLAG_ARRM LPTIM_ISR_ARRM
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_DMA_sources LPTIM DMA Sources
+ * @{
+ */
+#define LPTIM_DMA_UPDATE LPTIM_DIER_UEDE /*!< DMA request is triggered by the update event */
+#define LPTIM_DMA_CC1 LPTIM_DIER_CC1DE /*!< DMA request is triggered by the capture 1 event */
+#define LPTIM_DMA_CC2 LPTIM_DIER_CC2DE /*!< DMA request is triggered by the capture 2 event */
+
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_DMA_Handle_index LPTIM DMA Handle Index
+ * @{
+ */
+#define LPTIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */
+#define LPTIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Update event 1 DMA request */
+#define LPTIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Update event 2 DMA request */
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition
+ * @{
+ */
+#define LPTIM_IT_CC1O LPTIM_DIER_CC1OIE
+#define LPTIM_IT_CC2O LPTIM_DIER_CC2OIE
+#define LPTIM_IT_CC1 LPTIM_DIER_CC1IE
+#define LPTIM_IT_CC2 LPTIM_DIER_CC2IE
+#define LPTIM_IT_CMP1OK LPTIM_DIER_CMP1OKIE
+#define LPTIM_IT_CMP2OK LPTIM_DIER_CMP2OKIE
+#define LPTIM_IT_REPOK LPTIM_DIER_REPOKIE
+#define LPTIM_IT_UPDATE LPTIM_DIER_UEIE
+#define LPTIM_IT_DOWN LPTIM_DIER_DOWNIE
+#define LPTIM_IT_UP LPTIM_DIER_UPIE
+#define LPTIM_IT_ARROK LPTIM_DIER_ARROKIE
+#define LPTIM_IT_EXTTRIG LPTIM_DIER_EXTTRIGIE
+#define LPTIM_IT_ARRM LPTIM_DIER_ARRMIE
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Channel LPTIM Channel
+ * @{
+ */
+#define LPTIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */
+#define LPTIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */
+#define LPTIM_CHANNEL_ALL 0x00000013U /*!< Global Capture/compare channel identifier */
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Output_Compare_Polarity LPTIM Output Compare Polarity
+ * @{
+ */
+#define LPTIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */
+#define LPTIM_OCPOLARITY_LOW 0x00000001U /*!< Capture/Compare output polarity */
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Input_Capture_Prescaler LPTIM Input Capture Prescaler
+ * @{
+ */
+#define LPTIM_ICPSC_DIV1 0x00000000UL /*!< Capture performed each time an edge is detected on the capture input */
+#define LPTIM_ICPSC_DIV2 LPTIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */
+#define LPTIM_ICPSC_DIV4 LPTIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */
+#define LPTIM_ICPSC_DIV8 (LPTIM_CCMR1_IC1PSC_0|LPTIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 8 events */
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Input_Capture_Polarity LPTIM Input Capture Polarity
+ * @{
+ */
+#define LPTIM_ICPOLARITY_RISING 0x00000000UL /*!< Capture/Compare input rising polarity */
+#define LPTIM_ICPOLARITY_FALLING LPTIM_CCMR1_CC1P_0 /*!< Capture/Compare input falling polarity */
+#define LPTIM_ICPOLARITY_RISING_FALLING (LPTIM_CCMR1_CC1P_0|LPTIM_CCMR1_CC1P_1) /*!< Capture/Compare input rising and falling polarities */
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Input_Capture_Filter LPTIM Input Capture Filter
+ * @{
+ */
+#define LPTIM_ICFLT_CLOCK_DIV1 0x00000000UL /*!< any external input capture signal level change is considered as a valid transition */
+#define LPTIM_ICFLT_CLOCK_DIV2 LPTIM_CCMR1_IC1F_0 /*!< external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition */
+#define LPTIM_ICFLT_CLOCK_DIV4 LPTIM_CCMR1_IC1F_1 /*!< external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition */
+#define LPTIM_ICFLT_CLOCK_DIV8 (LPTIM_CCMR1_IC1F_0|LPTIM_CCMR1_IC1F_1) /*!< external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition */
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Input_Capture_Source LPTIM Input Capture Source
+ * @{
+ */
+#define LPTIM_IC1SOURCE_GPIO 0x00000000UL /*!< For LPTIM1, LPTIM2 and LPTIM3 */
+#define LPTIM_IC1SOURCE_COMP1 LPTIM_CFGR2_IC1SEL_0 /*!< For LPTIM1, LPTIM2 and LPTIM3 */
+#define LPTIM_IC1SOURCE_COMP2 LPTIM_CFGR2_IC1SEL_1 /*!< For LPTIM1, LPTIM2 and LPTIM3 */
+#define LPTIM_IC2SOURCE_GPIO 0x00000000UL /*!< For LPTIM1, LPTIM2 and LPTIM3 */
+#define LPTIM_IC2SOURCE_LSI LPTIM_CFGR2_IC2SEL_0 /*!< For LPTIM1 */
+#define LPTIM_IC2SOURCE_LSE LPTIM_CFGR2_IC2SEL_1 /*!< For LPTIM1 */
+#define LPTIM_IC2SOURCE_HSI_256 LPTIM_CFGR2_IC2SEL_0 /*!< For LPTIM2 */
+#define LPTIM_IC2SOURCE_MSIS_1024 LPTIM_CFGR2_IC2SEL_1 /*!< For LPTIM2 */
+#define LPTIM_IC2SOURCE_MSIS_4 (LPTIM_CFGR2_IC2SEL_0|LPTIM_CFGR2_IC2SEL_1) /*!< For LPTIM2 */
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros
+ * @{
+ */
+
+/** @brief Reset LPTIM handle state.
+ * @param __HANDLE__ LPTIM handle
+ * @retval None
+ */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \
+ (__HANDLE__)->ChannelState[0] = HAL_LPTIM_CHANNEL_STATE_RESET;\
+ (__HANDLE__)->ChannelState[1] = HAL_LPTIM_CHANNEL_STATE_RESET;\
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \
+ (__HANDLE__)->ChannelState[0] = HAL_LPTIM_CHANNEL_STATE_RESET;\
+ (__HANDLE__)->ChannelState[1] = HAL_LPTIM_CHANNEL_STATE_RESET;\
+ } while(0)
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+
+/**
+ * @brief Enable the LPTIM peripheral.
+ * @param __HANDLE__ LPTIM handle
+ * @retval None
+ */
+#define __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
+
+/**
+ * @brief Disable the LPTIM peripheral.
+ * @param __HANDLE__ LPTIM handle
+ * @retval None
+ */
+#define __HAL_LPTIM_DISABLE(__HANDLE__) \
+ do { \
+ if (((__HANDLE__)->Instance->CCMR1 & LPTIM_CCMR1_CC1E) == 0UL) \
+ { \
+ if(((__HANDLE__)->Instance->CCMR1 & LPTIM_CCMR1_CC2E) == 0UL) \
+ { \
+ (__HANDLE__)->Instance->CR &= ~(LPTIM_CR_ENABLE); \
+ } \
+ } \
+ } while(0)
+
+/**
+ * @brief Start the LPTIM peripheral in Continuous mode.
+ * @param __HANDLE__ LPTIM handle
+ * @retval None
+ */
+#define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)
+/**
+ * @brief Start the LPTIM peripheral in single mode.
+ * @param __HANDLE__ LPTIM handle
+ * @retval None
+ */
+#define __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)
+
+/**
+ * @brief Reset the LPTIM Counter register in synchronous mode.
+ * @param __HANDLE__ LPTIM handle
+ * @retval None
+ */
+#define __HAL_LPTIM_RESET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_COUNTRST)
+
+/**
+ * @brief Reset after read of the LPTIM Counter register in asynchronous mode.
+ * @param __HANDLE__ LPTIM handle
+ * @retval None
+ */
+#define __HAL_LPTIM_RESET_COUNTER_AFTERREAD(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_RSTARE)
+
+/**
+ * @brief Write the passed parameter in the Autoreload register.
+ * @param __HANDLE__ LPTIM handle
+ * @param __VALUE__ Autoreload value
+ * @retval None
+ * @note The ARR register can only be modified when the LPTIM instance is enabled.
+ */
+#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
+
+/**
+ * @brief Write the passed parameter in the Compare register.
+ * @param __HANDLE__ LPTIM handle
+ * @param __VALUE__ Compare value
+ * @param __CHANNEL__ TIM Channel to be configured
+ * @retval None
+ * @note The CCRx registers can only be modified when the LPTIM instance is enabled.
+ */
+#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __CHANNEL__, __VALUE__) \
+ (((__CHANNEL__) == LPTIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__VALUE__)) :\
+ ((__CHANNEL__) == LPTIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__VALUE__)) : 0U)
+
+/**
+ * @brief Write the passed parameter in the Repetition register.
+ * @param __HANDLE__ LPTIM handle
+ * @param __VALUE__ Repetition value
+ * @retval None
+ */
+#define __HAL_LPTIM_REPETITIONCOUNTER_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->RCR = (__VALUE__))
+
+/**
+ * @brief Return the current Repetition value.
+ * @param __HANDLE__ LPTIM handle
+ * @retval Repetition register value
+ * @note The RCR register can only be modified when the LPTIM instance is enabled.
+ */
+#define __HAL_LPTIM_REPETITIONCOUNTER_GET(__HANDLE__) ((__HANDLE__)->Instance->RCR)
+
+/**
+ * @brief Enable the LPTIM signal input/output on the corresponding pin.
+ * @param __HANDLE__ LPTIM handle
+ * @param __CHANNEL__ LPTIM Channels to be enabled.
+ * This parameter can be one of the following values:
+ * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
+ * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
+ * @retval None
+ */
+#define __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(__HANDLE__, __CHANNEL__) \
+ do { \
+ switch (__CHANNEL__) \
+ { \
+ case LPTIM_CHANNEL_1: \
+ ((__HANDLE__)->Instance->CCMR1 |= LPTIM_CCMR1_CC1E); \
+ break; \
+ case LPTIM_CHANNEL_2: \
+ ((__HANDLE__)->Instance->CCMR1 |= LPTIM_CCMR1_CC2E); \
+ break; \
+ default: \
+ break; \
+ } \
+ } \
+ while(0)
+
+/**
+ * @brief Disable the LPTIM signal input/output on the corresponding pin.
+ * @param __HANDLE__ LPTIM handle
+ * @param __CHANNEL__ LPTIM Channels to be disabled.
+ * This parameter can be one of the following values:
+ * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
+ * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
+ * @retval None
+ */
+#define __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(__HANDLE__, __CHANNEL__) \
+ do { \
+ switch (__CHANNEL__) \
+ { \
+ case LPTIM_CHANNEL_1: \
+ ((__HANDLE__)->Instance->CCMR1 &= ~LPTIM_CCMR1_CC1E); \
+ break; \
+ case LPTIM_CHANNEL_2: \
+ ((__HANDLE__)->Instance->CCMR1 &= ~LPTIM_CCMR1_CC2E); \
+ break; \
+ default: \
+ break; \
+ } \
+ } \
+ while(0)
+
+/**
+ * @brief Check whether the specified LPTIM flag is set or not.
+ * @param __HANDLE__ LPTIM handle
+ * @param __FLAG__ LPTIM flag to check
+ * This parameter can be a value of:
+ * @arg LPTIM_FLAG_REPOK : Repetition register update OK Flag.
+ * @arg LPTIM_FLAG_UPDATE : Update event Flag.
+ * @arg LPTIM_FLAG_DOWN : Counter direction change up Flag.
+ * @arg LPTIM_FLAG_UP : Counter direction change down to up Flag.
+ * @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
+ * @arg LPTIM_FLAG_CMPOK : Compare register update OK Flag.
+ * @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
+ * @arg LPTIM_FLAG_ARRM : Autoreload match Flag.
+ * @arg LPTIM_FLAG_CMPM : Compare match Flag.
+ * @retval The state of the specified flag (SET or RESET).
+ */
+#define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clear the specified LPTIM flag.
+ * @param __HANDLE__ LPTIM handle.
+ * @param __FLAG__ LPTIM flag to clear.
+ * This parameter can be a value of:
+ * @arg LPTIM_FLAG_REPOK : Repetition register update OK Flag.
+ * @arg LPTIM_FLAG_UPDATE : Update event Flag.
+ * @arg LPTIM_FLAG_DOWN : Counter direction change up Flag.
+ * @arg LPTIM_FLAG_UP : Counter direction change down to up Flag.
+ * @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
+ * @arg LPTIM_FLAG_CMPOK : Compare register update OK Flag.
+ * @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
+ * @arg LPTIM_FLAG_ARRM : Autoreload match Flag.
+ * @arg LPTIM_FLAG_CMPM : Compare match Flag.
+ * @retval None.
+ */
+#define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/**
+ * @brief Enable the specified LPTIM interrupt.
+ * @param __HANDLE__ LPTIM handle.
+ * @param __INTERRUPT__ LPTIM interrupt to set.
+ * This parameter can be a value of:
+ * @arg LPTIM_IT_REPOK : Repetition register update OK Interrupt.
+ * @arg LPTIM_IT_UPDATE : Update event register Interrupt.
+ * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
+ * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
+ * @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
+ * @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
+ * @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
+ * @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
+ * @arg LPTIM_IT_CMPM : Compare match Interrupt.
+ * @retval None.
+ * @note The LPTIM interrupts can only be enabled when the LPTIM instance is enabled.
+ */
+#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the specified LPTIM interrupt.
+ * @param __HANDLE__ LPTIM handle.
+ * @param __INTERRUPT__ LPTIM interrupt to set.
+ * This parameter can be a value of:
+ * @arg LPTIM_IT_REPOK : Repetition register update OK Interrupt.
+ * @arg LPTIM_IT_UPDATE : Update event register Interrupt.
+ * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
+ * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
+ * @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
+ * @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
+ * @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
+ * @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
+ * @arg LPTIM_IT_CMPM : Compare match Interrupt.
+ * @retval None.
+ * @note The LPTIM interrupts can only be disabled when the LPTIM instance is enabled.
+ */
+#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= (~(__INTERRUPT__)))
+
+/** @brief Enable the specified DMA request.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __DMA__ specifies the LPTIM DMA request to enable.
+ * This parameter can be one of the following values:
+ * @arg LPTIM_DMA_UPDATE: Update DMA request
+ * @arg LPTIM_DMA_CC1: Capture/Compare 1 DMA request
+ * @arg LPTIM_DMA_CC2: Capture/Compare 2 DMA request
+ * @retval None
+ */
+#define __HAL_LPTIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
+
+/** @brief Disable the specified DMA request.
+ * @param __HANDLE__ specifies the LPTIM Handle.
+ * @param __DMA__ specifies the LPTIM DMA request to disable.
+ * This parameter can be one of the following values:
+ * @arg LPTIM_DMA_UPDATE: Update DMA request
+ * @arg LPTIM_DMA_CC1: Capture/Compare 1 DMA request
+ * @arg LPTIM_DMA_CC2: Capture/Compare 2 DMA request
+ * @retval None
+ */
+#define __HAL_LPTIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
+
+/**
+ * @brief Check whether the specified LPTIM interrupt source is enabled or not.
+ * @param __HANDLE__ LPTIM handle.
+ * @param __INTERRUPT__ LPTIM interrupt to check.
+ * This parameter can be a value of:
+ * @arg LPTIM_IT_REPOK : Repetition register update OK Interrupt.
+ * @arg LPTIM_IT_UPDATE : Update event register Interrupt.
+ * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
+ * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
+ * @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
+ * @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
+ * @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
+ * @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
+ * @arg LPTIM_IT_CMPM : Compare match Interrupt.
+ * @retval Interrupt status.
+ */
+
+#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER\
+ & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
+ * @{
+ */
+
+/** @addtogroup LPTIM_Exported_Functions_Group1
+ * @brief Initialization and Configuration functions.
+ * @{
+ */
+/* Initialization/de-initialization functions ********************************/
+HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
+HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
+
+/* MSP functions *************************************************************/
+void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
+/**
+ * @}
+ */
+
+/** @addtogroup LPTIM_Exported_Functions_Group2
+ * @brief Start-Stop operation functions.
+ * @{
+ */
+/* Config functions **********************************************************/
+HAL_StatusTypeDef HAL_LPTIM_OC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, LPTIM_OC_ConfigTypeDef *sConfig,
+ uint32_t Channel);
+
+/* Start/Stop operation functions *********************************************/
+/* ################################# PWM Mode ################################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
+HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
+HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
+HAL_StatusTypeDef HAL_LPTIM_PWM_Start_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel, uint32_t *pData,
+ uint32_t Length);
+HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
+
+/* ############################# One Pulse Mode ##############################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
+
+/* ############################## Set once Mode ##############################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
+
+/* ############################### Encoder Mode ##############################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim);
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim);
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+
+/* ############################# Time out Mode ##############################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Timeout);
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Timeout);
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+
+/* ############################## Counter Mode ###############################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim);
+HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim);
+HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+
+/* ############################## Input Capture Mode ###############################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_IC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, LPTIM_IC_ConfigTypeDef *sConfig,
+ uint32_t Channel);
+HAL_StatusTypeDef HAL_LPTIM_IC_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
+HAL_StatusTypeDef HAL_LPTIM_IC_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_IC_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
+HAL_StatusTypeDef HAL_LPTIM_IC_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
+HAL_StatusTypeDef HAL_LPTIM_IC_Start_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel, uint32_t *pData,
+ uint32_t Length);
+HAL_StatusTypeDef HAL_LPTIM_IC_Stop_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup LPTIM_Exported_Functions_Group3
+ * @brief Read operation functions.
+ * @{
+ */
+/* Reading operation functions ************************************************/
+uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
+uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
+uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup LPTIM_Exported_Functions_Group4
+ * @brief LPTIM IRQ handler and callback functions.
+ * @{
+ */
+/* LPTIM IRQ functions *******************************************************/
+void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
+
+/* CallBack functions ********************************************************/
+void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_ErrorCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_UpdateEventCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_UpdateEventHalfCpltCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_RepCounterWriteCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_IC_CaptureCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_IC_CaptureHalfCpltCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_IC_OverCaptureCallback(LPTIM_HandleTypeDef *hlptim);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID,
+ pLPTIM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @addtogroup LPTIM_Group5
+ * @brief Peripheral State functions.
+ * @{
+ */
+/* Peripheral State functions ************************************************/
+HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Types LPTIM Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Variables LPTIM Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Constants LPTIM Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Macros LPTIM Private Macros
+ * @{
+ */
+
+#define IS_LPTIM_CLOCK_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
+ ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))
+
+
+#define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LPTIM_PRESCALER_DIV1 ) || \
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV2 ) || \
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV4 ) || \
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV8 ) || \
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV16 ) || \
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV32 ) || \
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV64 ) || \
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV128))
+
+#define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)
+#define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
+ ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS) || \
+ ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS) || \
+ ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))
+
+#define IS_LPTIM_CLOCK_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING) || \
+ ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
+ ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))
+
+#define IS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
+ ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
+ ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
+ ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
+ ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
+ ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
+ ((__TRIG__) == LPTIM_TRIGSOURCE_5) || \
+ ((__TRIG__) == LPTIM_TRIGSOURCE_6) || \
+ ((__TRIG__) == LPTIM_TRIGSOURCE_7))
+
+#define IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING ) || \
+ ((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING ) || \
+ ((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))
+
+#define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
+ ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS ) || \
+ ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS ) || \
+ ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS ))
+
+#define IS_LPTIM_UPDATE_MODE(__MODE__) (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
+ ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))
+
+#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
+ ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
+
+#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFFUL)
+
+#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL)
+
+#define IS_LPTIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0x0000FFFFUL)
+
+#define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL)
+
+#define IS_LPTIM_CHANNELS(__INSTANCE__, __CHANNEL__) (((__CHANNEL__) == LPTIM_CHANNEL_1) || \
+ ((__CHANNEL__) == LPTIM_CHANNEL_2))
+
+#define IS_LPTIM_OC_POLARITY(__OCPOLARITY__) (((__OCPOLARITY__) == LPTIM_OCPOLARITY_LOW) || \
+ ((__OCPOLARITY__) == LPTIM_OCPOLARITY_HIGH))
+#define IS_LPTIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LPTIM_ICPSC_DIV1) ||\
+ ((__PRESCALER__) == LPTIM_ICPSC_DIV2) ||\
+ ((__PRESCALER__) == LPTIM_ICPSC_DIV4) ||\
+ ((__PRESCALER__) == LPTIM_ICPSC_DIV8))
+
+#define IS_LPTIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ICPOLARITY_RISING) || \
+ ((__POLARITY__) == LPTIM_ICPOLARITY_FALLING) ||\
+ ((__POLARITY__) == LPTIM_ICPOLARITY_RISING_FALLING))
+
+#define IS_LPTIM_IC_FILTER(__FILTER__) (((__FILTER__) == LPTIM_ICFLT_CLOCK_DIV1) ||\
+ ((__FILTER__) == LPTIM_ICFLT_CLOCK_DIV2) ||\
+ ((__FILTER__) == LPTIM_ICFLT_CLOCK_DIV4) ||\
+ ((__FILTER__) == LPTIM_ICFLT_CLOCK_DIV8))
+
+#define IS_LPTIM_REPETITION(__REPETITION__) ((__REPETITION__) <= 0x000000FFUL)
+
+#define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \
+ ((((__INSTANCE__) == LPTIM1) || \
+ ((__INSTANCE__) == LPTIM2) || \
+ ((__INSTANCE__) == LPTIM3) || \
+ ((__INSTANCE__) == LPTIM4)) && \
+ (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
+ ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1)))
+
+#define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \
+ ((((__INSTANCE__) == LPTIM1) || \
+ ((__INSTANCE__) == LPTIM2)) && \
+ (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \
+ ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2)))
+
+#define IS_LPTIM_IC1_SOURCE(__INSTANCE__, __SOURCE__) \
+ ((((__INSTANCE__) == LPTIM1) || \
+ ((__INSTANCE__) == LPTIM2)|| \
+ ((__INSTANCE__) == LPTIM3)) && \
+ (((__SOURCE__) == LPTIM_IC1SOURCE_GPIO) || \
+ ((__SOURCE__) == LPTIM_IC1SOURCE_COMP1) || \
+ ((__SOURCE__) == LPTIM_IC1SOURCE_COMP2)))
+
+#define IS_LPTIM_IC2_SOURCE(__INSTANCE__, __SOURCE__) \
+ ((((__INSTANCE__) == LPTIM1) && \
+ (((__SOURCE__) == LPTIM_IC2SOURCE_GPIO) || \
+ ((__SOURCE__) == LPTIM_IC2SOURCE_LSI) || \
+ ((__SOURCE__) == LPTIM_IC2SOURCE_LSE))) \
+ || \
+ (((__INSTANCE__) == LPTIM2) && \
+ (((__SOURCE__) == LPTIM_IC2SOURCE_GPIO) || \
+ ((__SOURCE__) == LPTIM_IC2SOURCE_HSI_256) || \
+ ((__SOURCE__) == LPTIM_IC2SOURCE_MSIS_1024)|| \
+ ((__SOURCE__) == LPTIM_IC2SOURCE_MSIS_4))) \
+ || \
+ (((__INSTANCE__) == LPTIM3) && \
+ ((__SOURCE__) == LPTIM_IC2SOURCE_GPIO)))
+
+#define LPTIM_CHANNEL_STATE_GET(__INSTANCE__, __CHANNEL__)\
+ (((__CHANNEL__) == LPTIM_CHANNEL_1) ? (__INSTANCE__)->ChannelState[0] :\
+ (__INSTANCE__)->ChannelState[1])
+
+#define LPTIM_CHANNEL_STATE_SET(__INSTANCE__, __CHANNEL__, __CHANNEL_STATE__) \
+ (((__CHANNEL__) == LPTIM_CHANNEL_1) ? ((__INSTANCE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
+ ((__INSTANCE__)->ChannelState[1] = (__CHANNEL_STATE__)))
+
+#define LPTIM_CHANNEL_STATE_SET_ALL(__INSTANCE__, __CHANNEL_STATE__) do { \
+ (__INSTANCE__)->ChannelState[0] =\
+ (__CHANNEL_STATE__); \
+ (__INSTANCE__)->ChannelState[1] =\
+ (__CHANNEL_STATE__); \
+ } while(0)
+
+#define IS_LPTIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
+ (((((__INSTANCE__) == LPTIM1_NS) || ((__INSTANCE__) == LPTIM1_S)) && \
+ (((__CHANNEL__) == LPTIM_CHANNEL_1) || \
+ ((__CHANNEL__) == LPTIM_CHANNEL_2) || \
+ ((__CHANNEL__) == LPTIM_CHANNEL_ALL))) \
+ || \
+ ((((__INSTANCE__) == LPTIM2_NS) || ((__INSTANCE__) == LPTIM2_S)) && \
+ (((__CHANNEL__) == LPTIM_CHANNEL_1) || \
+ ((__CHANNEL__) == LPTIM_CHANNEL_2) || \
+ ((__CHANNEL__) == LPTIM_CHANNEL_ALL))) \
+ || \
+ ((((__INSTANCE__) == LPTIM3_NS) || ((__INSTANCE__) == LPTIM3_S)) && \
+ (((__CHANNEL__) == LPTIM_CHANNEL_1) || \
+ ((__CHANNEL__) == LPTIM_CHANNEL_2) || \
+ ((__CHANNEL__) == LPTIM_CHANNEL_ALL))) \
+ || \
+ ((((__INSTANCE__) == LPTIM4_NS) || ((__INSTANCE__) == LPTIM4_S)) && \
+ ((__CHANNEL__) == LPTIM_CHANNEL_1)))
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* LPTIM1 || LPTIM2 || LPTIM3 || LPTIM4 */
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_LPTIM_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_mdf.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_mdf.h
new file mode 100644
index 00000000..5ab4ebad
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_mdf.h
@@ -0,0 +1,1155 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_mdf.h
+ * @author MCD Application Team
+ * @brief Header file of MDF HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_MDF_H
+#define STM32U5xx_HAL_MDF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup MDF
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup MDF_Exported_Types MDF Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL MDF states definition
+ */
+typedef enum
+{
+ HAL_MDF_STATE_RESET = 0x00U, /*!< MDF not initialized */
+ HAL_MDF_STATE_READY = 0x01U, /*!< MDF initialized and ready for use */
+ HAL_MDF_STATE_ACQUISITION = 0x02U, /*!< MDF acquisition in progress */
+ HAL_MDF_STATE_ERROR = 0xFFU /*!< MDF state error */
+} HAL_MDF_StateTypeDef;
+
+/**
+ * @brief MDF clock trigger structure definition
+ */
+typedef struct
+{
+ FunctionalState Activation; /*!< Output clock trigger enable/disable */
+ uint32_t Source; /*!< Output clock trigger source.
+ This parameter can be a value of @ref MDF_ClockTriggerSource */
+ uint32_t Edge; /*!< Output clock trigger edge.
+ This parameter can be a value of @ref MDF_ClockTriggerEdge */
+} MDF_ClockTriggerTypeDef;
+
+/**
+ * @brief MDF output clock structure definition
+ */
+typedef struct
+{
+ FunctionalState Activation; /*!< Output clock enable/disable */
+ uint32_t Pins; /*!< Output clock pins.
+ This parameter can be a value of @ref MDF_OuputClockPins */
+ uint32_t Divider; /*!< Output clock divider.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
+ MDF_ClockTriggerTypeDef Trigger; /*!< Output clock trigger parameters */
+} MDF_OutputClockTypeDef;
+
+/**
+ * @brief MDF common parameters structure definition
+ */
+typedef struct
+{
+ uint32_t InterleavedFilters; /*!< Number of filters in interleaved mode with filter 0.
+ This parameter must be a number between Min_Data = 0
+ and Max_Data = 5.
+ @note This parameter is not used for ADF instance */
+ uint32_t ProcClockDivider; /*!< Processing clock divider.
+ This parameter must be a number between Min_Data = 1
+ and Max_Data = 128 */
+ MDF_OutputClockTypeDef OutputClock; /*!< Output clock parameters */
+} MDF_CommonParamTypeDef;
+
+/**
+ * @brief MDF serial interface structure definition
+ */
+typedef struct
+{
+ FunctionalState Activation; /*!< Serial interface enable/disable */
+ uint32_t Mode; /*!< Serial interface mode.
+ This parameter can be a value of @ref MDF_SitfMode */
+ uint32_t ClockSource; /*!< Serial interface clock source.
+ This parameter can be a value of @ref MDF_SitfClockSource */
+ uint32_t Threshold; /*!< SPI threshold for clock absence detection or Manchester symbol threshold.
+ This parameter must be a number between Min_Data = 4 and Max_Data = 31 */
+} MDF_SerialInterfaceTypeDef;
+
+/**
+ * @brief MDF init structure definition
+ */
+typedef struct
+{
+ MDF_CommonParamTypeDef CommonParam; /*!< MDF common parameters */
+ MDF_SerialInterfaceTypeDef SerialInterface; /*!< MDF serial interface parameters */
+ uint32_t FilterBistream; /*!< MDF filter bitstream selection.
+ This parameter can be a value of @ref MDF_FilterBitstream */
+} MDF_InitTypeDef;
+
+/**
+ * @brief MDF handle structure definition
+ */
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+typedef struct __MDF_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+{
+ MDF_Filter_TypeDef *Instance; /*!< MDF instance */
+ MDF_InitTypeDef Init; /*!< MDF init parameters */
+ DMA_HandleTypeDef *hdma; /*!< Pointer on DMA handler for acquisitions */
+ __IO HAL_MDF_StateTypeDef State; /*!< MDF state */
+ __IO uint32_t ErrorCode; /*!< MDF error code */
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+ void (*OldCallback)(struct __MDF_HandleTypeDef *hmdf,
+ uint32_t Threshold); /*!< MDF out-off limit detector callback.
+ @note Not used for ADF instance */
+ void (*AcqCpltCallback)(struct __MDF_HandleTypeDef *hmdf); /*!< MDF acquisition complete callback */
+ void (*AcqHalfCpltCallback)(struct __MDF_HandleTypeDef *hmdf); /*!< MDF acquisition half complete callback */
+ void (*SndLvCallback)(struct __MDF_HandleTypeDef *hmdf,
+ uint32_t SoundLevel,
+ uint32_t AmbientNoise); /*!< MDF sound level callback.
+ @note Not used for MDF instance */
+ void (*SadCallback)(struct __MDF_HandleTypeDef *hmdf); /*!< MDF sound activity detector callback.
+ @note Not used for MDF instance */
+ void (*ErrorCallback)(struct __MDF_HandleTypeDef *hmdf); /*!< MDF error callback */
+ void (*MspInitCallback)(struct __MDF_HandleTypeDef *hmdf); /*!< MDF MSP init callback */
+ void (*MspDeInitCallback)(struct __MDF_HandleTypeDef *hmdf); /*!< MDF MSP de-init callback */
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+} MDF_HandleTypeDef;
+
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+/**
+ * @brief MDF callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_MDF_OLD_CB_ID = 0x00U, /*!< MDF out-off limit detector callback ID.
+ @note Not used for ADF instance */
+ HAL_MDF_ACQ_COMPLETE_CB_ID = 0x01U, /*!< MDF acquisition complete callback ID */
+ HAL_MDF_ACQ_HALFCOMPLETE_CB_ID = 0x02U, /*!< MDF acquisition half complete callback ID */
+ HAL_MDF_SNDLVL_CB_ID = 0x03U, /*!< MDF sound level callback ID.
+ @note Not used for MDF instance */
+ HAL_MDF_SAD_CB_ID = 0x04U, /*!< MDF sound activity detector callback ID.
+ @note Not used for MDF instance */
+ HAL_MDF_ERROR_CB_ID = 0x05U, /*!< MDF error callback ID */
+ HAL_MDF_MSPINIT_CB_ID = 0x06U, /*!< MDF MSP init callback ID */
+ HAL_MDF_MSPDEINIT_CB_ID = 0x07U /*!< MDF MSP de-init callback ID */
+} HAL_MDF_CallbackIDTypeDef;
+
+/**
+ * @brief MDF callback pointers definition
+ */
+typedef void (*pMDF_CallbackTypeDef)(MDF_HandleTypeDef *hmdf);
+typedef void (*pMDF_OldCallbackTypeDef)(MDF_HandleTypeDef *hmdf, uint32_t Threshold);
+typedef void (*pMDF_SndLvlCallbackTypeDef)(MDF_HandleTypeDef *hmdf, uint32_t SoundLevel, uint32_t AmbientNoise);
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+
+/**
+ * @brief MDF reshape filter structure definition
+ */
+typedef struct
+{
+ FunctionalState Activation; /*!< Reshape filter enable/disable */
+ uint32_t DecimationRatio; /*!< Reshape filter decimation ratio.
+ This parameter can be a value of @ref MDF_ReshapeDecimationRatio */
+} MDF_ReshapeFilterTypeDef;
+
+/**
+ * @brief MDF high pass filter structure definition
+ */
+typedef struct
+{
+ FunctionalState Activation; /*!< High pass filter enable/disable */
+ uint32_t CutOffFrequency; /*!< High pass filter cut-off frequency.
+ This parameter can be a value of @ref MDF_HighPassCutOffFreq */
+} MDF_HighPassFilterTypeDef;
+
+/**
+ * @brief MDF integrator structure definition
+ */
+typedef struct
+{
+ FunctionalState Activation; /*!< Integrator enable/disable */
+ uint32_t Value; /*!< Integrator value.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 128 */
+ uint32_t OutputDivision; /*!< Integrator output division.
+ This parameter can be a value of @ref MDF_IntegratorOutputDiv */
+} MDF_IntegratorTypeDef;
+
+/**
+ * @brief MDF sound activity structure definition
+ */
+typedef struct
+{
+ FunctionalState Activation; /*!< Sound activity detector enable/disable */
+ uint32_t Mode; /*!< Sound activity detector mode.
+ This parameter can be a value of @ref MDF_SadMode */
+ uint32_t FrameSize; /*!< Size of one frame to compute short-term signal level.
+ This parameter can be a value of @ref MDF_SadFrameSize */
+ FunctionalState Hysteresis; /*!< Hysteresis enable/disable.
+ @note This parameter is not used if Mode is set
+ to MDF_SAD_AMBIENT_NOISE_ESTIMATOR */
+ uint32_t SoundTriggerEvent; /*!< Sound trigger event configuration.
+ This parameter can be a value of @ref MDF_SadSoundTriggerEvent */
+ uint32_t DataMemoryTransfer; /*!< Data memory transfer mode.
+ This parameter can be a value of @ref MDF_SadDataMemoryTransfer */
+ uint32_t MinNoiseLevel; /*!< Minimum noise level.
+ This parameter must be a number between Min_Data = 0
+ and Max_Data = 8191 */
+ uint32_t HangoverWindow; /*!< Hangover time window in frames.
+ This parameter can be a value of @ref MDF_SadHangoverWindow */
+ uint32_t LearningFrames; /*!< Number of learning frames for the first estimation of noise level.
+ This parameter can be a value of @ref MDF_SadLearningFrames */
+ uint32_t AmbientNoiseSlope; /*!< Ambient noise slope control.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 7.
+ @note This parameter is not used if Mode is set
+ to MDF_SAD_SOUND_DETECTOR */
+ uint32_t SignalNoiseThreshold; /*!< Signal to noise threshold.
+ This parameter can be a value of @ref MDF_SadSignalNoiseThreshold */
+ FunctionalState SoundLevelInterrupt; /*!< Sound level interrupt enable/disable.
+ @note This interrupt is mainly used for debug purpose*/
+
+} MDF_SoundActivityTypeDef;
+
+/**
+ * @brief MDF filter trigger structure definition
+ */
+typedef struct
+{
+ uint32_t Source; /*!< Filter trigger source.
+ This parameter can be a value of @ref MDF_FilterTriggerSource */
+ uint32_t Edge; /*!< Filter trigger edge.
+ This parameter can be a value of @ref MDF_FilterTriggerEdge */
+} MDF_FilterTriggerTypeDef;
+
+/**
+ * @brief MDF filter configuration structure definition
+ */
+typedef struct
+{
+ uint32_t DataSource; /*!< Filter data source.
+ This parameter can be a value of @ref MDF_DataSource */
+ uint32_t Delay; /*!< Delay to apply on data source in number of samples.
+ This parameter must be a number between Min_Data = 0
+ and Max_Data = 127 */
+ uint32_t CicMode; /*!< CIC filter mode.
+ This parameter can be a value of @ref MDF_CicMode */
+ uint32_t DecimationRatio; /*!< Filter decimation ratio.
+ This parameter must be a number between Min_Data = 2
+ and Max_Data = 512 */
+ int32_t Offset; /*!< Filter offset error compensation.
+ This parameter must be a number between Min_Data = -33554432
+ and Max_Data = 33554431.
+ @note This parameter is not used for ADF instance */
+ int32_t Gain; /*!< Filter gain in step of around 3db (from -48db to 72dB).
+ This parameter must be a number between Min_Data = -16
+ and Max_Data = 24 */
+ MDF_ReshapeFilterTypeDef ReshapeFilter; /*!< Reshape filter configuration */
+ MDF_HighPassFilterTypeDef HighPassFilter; /*!< High pass filter configuration */
+ MDF_IntegratorTypeDef Integrator; /*!< Integrator configuration.
+ @note This parameter is not used for ADF instance */
+ MDF_SoundActivityTypeDef SoundActivity; /*!< Sound activity detector configuration.
+ @note This parameter is not used for MDF instance */
+ uint32_t AcquisitionMode; /*!< Filter acquisition mode.
+ This parameter can be a value of @ref MDF_AcquisitionMode */
+ uint32_t FifoThreshold; /*!< Filter RXFIFO threshold.
+ This parameter can be a value of @ref MDF_FifoThreshold */
+ uint32_t DiscardSamples; /*!< Number of samples to discard after filter enable.
+ This parameter must be a number between Min_Data = 0
+ and Max_Data = 255 */
+ MDF_FilterTriggerTypeDef Trigger; /*!< Filter trigger configuration.
+ @note This parameter is not used if AcquisitionMode is set
+ to MDF_MODE_ASYNC_CONT or MDF_MODE_ASYNC_SINGLE */
+ uint32_t SnapshotFormat; /*!< Snapshot format.
+ This parameter can be a value of @ref MDF_SnapshotFormat.
+ @note This parameter is used only if AcquisitionMode is set
+ to MDF_MODE_SYNC_SNAPSHOT and for MDF instance */
+} MDF_FilterConfigTypeDef;
+
+/**
+ * @brief MDF snapshot parameters structure definition
+ */
+typedef struct
+{
+ int32_t Value; /*!< Snapshot acquisition value on 16 or 23 MSB depending on snapshot format */
+ uint32_t DecimationCounter; /*!< Decimation counter value when snapshot trigger occurs */
+ uint32_t IntegratorCounter; /*!< Integrator counter value when snapshot trigger occurs.
+ This value is available only if snapshot format is 16 bits resolution */
+} MDF_SnapshotParamTypeDef;
+
+/**
+ * @brief MDF DMA configuration structure definition
+ */
+typedef struct
+{
+ uint32_t Address; /*!< DMA destination address */
+ uint32_t DataLength; /*!< Length of data to transfer in bytes */
+ FunctionalState MsbOnly; /*!< Transfer only the 16MSB of the acquistion data */
+} MDF_DmaConfigTypeDef;
+
+/**
+ * @brief MDF short-circuit detector configuration structure definition
+ */
+typedef struct
+{
+ uint32_t Threshold; /*!< Short-circuit detector threshold.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 256 */
+ uint32_t BreakSignal; /*!< Break signal assignment for short-circuit detector.
+ This parameter can be a values combination of @ref MDF_BreakSignals */
+} MDF_ScdConfigTypeDef;
+
+/**
+ * @brief MDF out-off limit detector configuration structure definition
+ */
+typedef struct
+{
+ uint32_t OldCicMode; /*!< Out-off limit detector CIC filter mode.
+ This parameter can be a value of @ref MDF_OldCicMode */
+ uint32_t OldDecimationRatio; /*!< Out-off limit detector decimation ratio.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
+ int32_t HighThreshold; /*!< Out-off limit detector high threshold.
+ This parameter must be a number between Min_Data = -33554432
+ and Max_Data = 33554431 */
+ int32_t LowThreshold; /*!< Out-off limit detector low threshold.
+ This parameter must be a number between Min_Data = -33554432
+ and Max_Data = 33554431 */
+ uint32_t OldEventConfig; /*!< Out-off limit event configuration.
+ This parameter can be a value of @ref MDF_OldEventConfig */
+ uint32_t BreakSignal; /*!< Break signal assignment for out-off limit detector.
+ This parameter can be a values combination of @ref MDF_BreakSignals */
+} MDF_OldConfigTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup MDF_Exported_Constants MDF Exported Constants
+ * @{
+ */
+
+/** @defgroup MDF_ErrorCode MDF error code
+ * @{
+ */
+#define MDF_ERROR_NONE 0x00000000U /*!< No error */
+#define MDF_ERROR_ACQUISITION_OVERFLOW 0x00000001U /*!< Overflow occurs during acquisition */
+#define MDF_ERROR_RSF_OVERRUN 0x00000002U /*!< Overrun occurs on reshape filter */
+#define MDF_ERROR_CLOCK_ABSENCE 0x00000004U /*!< Clock absence detection occurs */
+#define MDF_ERROR_SHORT_CIRCUIT 0x00000008U /*!< Short circuit detection occurs.
+ @note Not used for ADF instance */
+#define MDF_ERROR_SATURATION 0x00000010U /*!< Saturation detection occurs */
+#define MDF_ERROR_OUT_OFF_LIMIT 0x00000020U /*!< Out-off limit detection occurs.
+ @note Not used for ADF instance */
+#define MDF_ERROR_DMA 0x00000040U /*!< DMA error occurs */
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+#define MDF_ERROR_INVALID_CALLBACK 0x00000080U /*!< Invalid callback error occurs */
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup MDF_ClockTriggerSource MDF output clock trigger source
+ * @{
+ */
+#define MDF_CLOCK_TRIG_TRGO 0x00000000U
+#define MDF_CLOCK_TRIG_TIM1_TRGO MDF_CKGCR_TRGSRC_1 /*!< @note Not available for ADF instance */
+#define MDF_CLOCK_TRIG_TIM1_TRGO2 (MDF_CKGCR_TRGSRC_0 | \
+ MDF_CKGCR_TRGSRC_1) /*!< @note Not available for ADF instance */
+#define MDF_CLOCK_TRIG_TIM8_TRGO MDF_CKGCR_TRGSRC_2 /*!< @note Not available for ADF instance */
+#define MDF_CLOCK_TRIG_TIM8_TRGO2 (MDF_CKGCR_TRGSRC_0 | \
+ MDF_CKGCR_TRGSRC_2) /*!< @note Not available for ADF instance */
+#define MDF_CLOCK_TRIG_TIM3_TRGO (MDF_CKGCR_TRGSRC_1 | \
+ MDF_CKGCR_TRGSRC_2) /*!< @note Not available for ADF instance */
+#define MDF_CLOCK_TRIG_TIM4_TRGO (MDF_CKGCR_TRGSRC_0 | \
+ MDF_CKGCR_TRGSRC_1 | \
+ MDF_CKGCR_TRGSRC_2) /*!< @note Not available for ADF instance */
+#define MDF_CLOCK_TRIG_TIM16_OC1 MDF_CKGCR_TRGSRC_3 /*!< @note Not available for ADF instance */
+#define MDF_CLOCK_TRIG_TIM6_TRGO (MDF_CKGCR_TRGSRC_0 | \
+ MDF_CKGCR_TRGSRC_3) /*!< @note Not available for ADF instance */
+#define MDF_CLOCK_TRIG_TIM7_TRGO (MDF_CKGCR_TRGSRC_1 | \
+ MDF_CKGCR_TRGSRC_3) /*!< @note Not available for ADF instance */
+#define MDF_CLOCK_TRIG_SAD_DET (MDF_CKGCR_TRGSRC_0 | \
+ MDF_CKGCR_TRGSRC_1 | \
+ MDF_CKGCR_TRGSRC_3) /*!< @note Not available for ADF instance */
+#define MDF_CLOCK_TRIG_EXTI11 (MDF_CKGCR_TRGSRC_2 | \
+ MDF_CKGCR_TRGSRC_3) /*!< @note Not available for ADF instance */
+#define MDF_CLOCK_TRIG_EXTI15 (MDF_CKGCR_TRGSRC_0 | \
+ MDF_CKGCR_TRGSRC_2 | \
+ MDF_CKGCR_TRGSRC_3)
+#define MDF_CLOCK_TRIG_LPTIM1_OUT (MDF_CKGCR_TRGSRC_1 | \
+ MDF_CKGCR_TRGSRC_2 | \
+ MDF_CKGCR_TRGSRC_3) /*!< @note Not available for ADF instance */
+#define MDF_CLOCK_TRIG_SAD_TRGO MDF_CKGCR_TRGSRC /*!< @note Not available for ADF instance */
+/**
+ * @}
+ */
+
+/** @defgroup MDF_ClockTriggerEdge MDF output clock trigger edge
+ * @{
+ */
+#define MDF_CLOCK_TRIG_RISING_EDGE 0x00000000U /*!< Rising edge */
+#define MDF_CLOCK_TRIG_FALLING_EDGE MDF_CKGCR_TRGSENS /*!< Falling edge */
+/**
+ * @}
+ */
+
+/** @defgroup MDF_OuputClockPins MDF output clock pins
+ * @{
+ */
+#define MDF_OUTPUT_CLOCK_0 MDF_CKGCR_CCK0DIR /*!< MDF_CCK0 is used as output clock */
+#define MDF_OUTPUT_CLOCK_1 MDF_CKGCR_CCK1DIR /*!< MDF_CCK1 is used as output clock */
+#define MDF_OUTPUT_CLOCK_ALL (MDF_CKGCR_CCK0DIR | \
+ MDF_CKGCR_CCK1DIR) /*!< MDF_CCK0 and MDF_CCK1 are used as output clock */
+/**
+ * @}
+ */
+
+/** @defgroup MDF_SitfMode MDF serial interface mode
+ * @{
+ */
+#define MDF_SITF_LF_MASTER_SPI_MODE 0x00000000U /*!< Low frequency master SPI mode */
+#define MDF_SITF_NORMAL_SPI_MODE MDF_SITFCR_SITFMOD_0 /*!< Normal SPI mode */
+#define MDF_SITF_MANCHESTER_FALLING_MODE MDF_SITFCR_SITFMOD_1 /*!< Manchester mode rising edge logic 0
+ and falling edge logic 1 */
+#define MDF_SITF_MANCHESTER_RISING_MODE MDF_SITFCR_SITFMOD /*!< Manchester mode rising edge logic 1
+ and falling edge logic 0 */
+/**
+ * @}
+ */
+
+/** @defgroup MDF_SitfClockSource MDF serial interface clock source
+ * @{
+ */
+#define MDF_SITF_CCK0_SOURCE 0x00000000U /*!< Common clock 0 source */
+#define MDF_SITF_CCK1_SOURCE MDF_SITFCR_SCKSRC_0 /*!< Common clock 1 source */
+#define MDF_SITF_CKI_SOURCE MDF_SITFCR_SCKSRC_1 /*!< Dedicated input clock source.
+ @note Not available for ADF instance */
+/**
+ * @}
+ */
+
+/** @defgroup MDF_FilterBitstream MDF filter bitstream
+ * @{
+ */
+#define MDF_BITSTREAM0_RISING 0x00000000U
+#define MDF_BITSTREAM0_FALLING MDF_BSMXCR_BSSEL_0
+#define MDF_BITSTREAM1_RISING MDF_BSMXCR_BSSEL_1 /*!< @note Not available for ADF instance */
+#define MDF_BITSTREAM1_FALLING (MDF_BSMXCR_BSSEL_0 | \
+ MDF_BSMXCR_BSSEL_1) /*!< @note Not available for ADF instance */
+#define MDF_BITSTREAM2_RISING MDF_BSMXCR_BSSEL_2 /*!< @note Not available for ADF instance */
+#define MDF_BITSTREAM2_FALLING (MDF_BSMXCR_BSSEL_0 | \
+ MDF_BSMXCR_BSSEL_2) /*!< @note Not available for ADF instance */
+#define MDF_BITSTREAM3_RISING (MDF_BSMXCR_BSSEL_1 | \
+ MDF_BSMXCR_BSSEL_2) /*!< @note Not available for ADF instance */
+#define MDF_BITSTREAM3_FALLING (MDF_BSMXCR_BSSEL_0 | \
+ MDF_BSMXCR_BSSEL_1 | \
+ MDF_BSMXCR_BSSEL_2) /*!< @note Not available for ADF instance */
+#define MDF_BITSTREAM4_RISING MDF_BSMXCR_BSSEL_3 /*!< @note Not available for ADF instance */
+#define MDF_BITSTREAM4_FALLING (MDF_BSMXCR_BSSEL_0 | \
+ MDF_BSMXCR_BSSEL_3) /*!< @note Not available for ADF instance */
+#define MDF_BITSTREAM5_RISING (MDF_BSMXCR_BSSEL_1 | \
+ MDF_BSMXCR_BSSEL_3) /*!< @note Not available for ADF instance */
+#define MDF_BITSTREAM5_FALLING (MDF_BSMXCR_BSSEL_0 | \
+ MDF_BSMXCR_BSSEL_1 | \
+ MDF_BSMXCR_BSSEL_3) /*!< @note Not available for ADF instance */
+/**
+ * @}
+ */
+
+/** @defgroup MDF_ReshapeDecimationRatio MDF reshape filter decimation ratio
+ * @{
+ */
+#define MDF_RSF_DECIMATION_RATIO_4 0x00000000U /*!< Reshape filter decimation ratio is 4 */
+#define MDF_RSF_DECIMATION_RATIO_1 MDF_DFLTRSFR_RSFLTD /*!< Reshape filter decimation ratio is 1 */
+/**
+ * @}
+ */
+
+/** @defgroup MDF_HighPassCutOffFreq MDF high pass filter cut-off frequency
+ * @{
+ */
+#define MDF_HPF_CUTOFF_0_000625FPCM 0x00000000U /*!< Cut-off frequency of 0.000625xFpcm */
+#define MDF_HPF_CUTOFF_0_00125FPCM MDF_DFLTRSFR_HPFC_0 /*!< Cut-off frequency of 0.00125xFpcm */
+#define MDF_HPF_CUTOFF_0_0025FPCM MDF_DFLTRSFR_HPFC_1 /*!< Cut-off frequency of 0.0025xFpcm */
+#define MDF_HPF_CUTOFF_0_0095FPCM MDF_DFLTRSFR_HPFC /*!< Cut-off frequency of 0.0095xFpcm */
+/**
+ * @}
+ */
+
+/** @defgroup MDF_IntegratorOutputDiv MDF integrator output division
+ * @{
+ */
+#define MDF_INTEGRATOR_OUTPUT_DIV_128 0x00000000U /*!< Integrator data outputs divided by 128 */
+#define MDF_INTEGRATOR_OUTPUT_DIV_32 MDF_DFLTINTR_INTDIV_0 /*!< Integrator data outputs divided by 32 */
+#define MDF_INTEGRATOR_OUTPUT_DIV_4 MDF_DFLTINTR_INTDIV_1 /*!< Integrator data outputs divided by 4 */
+#define MDF_INTEGRATOR_OUTPUT_NO_DIV MDF_DFLTINTR_INTDIV /*!< Integrator data outputs not divided */
+/**
+ * @}
+ */
+
+/** @defgroup MDF_SadMode MDF sound activity detector mode
+ * @{
+ */
+#define MDF_SAD_VOICE_ACTIVITY_DETECTOR 0x00000000U /*!< Voice activity detector */
+#define MDF_SAD_SOUND_DETECTOR MDF_SADCR_SADMOD_0 /*!< Sound detector */
+#define MDF_SAD_AMBIENT_NOISE_DETECTOR MDF_SADCR_SADMOD /*!< Ambient noise detector */
+/**
+ * @}
+ */
+
+/** @defgroup MDF_SadFrameSize MDF sound activity detector frame size
+ * @{
+ */
+#define MDF_SAD_8_PCM_SAMPLES 0x00000000U /*!< Frame size of 8 PCM samples */
+#define MDF_SAD_16_PCM_SAMPLES MDF_SADCR_FRSIZE_0 /*!< Frame size of 16 PCM samples */
+#define MDF_SAD_32_PCM_SAMPLES MDF_SADCR_FRSIZE_1 /*!< Frame size of 32 PCM samples */
+#define MDF_SAD_64_PCM_SAMPLES (MDF_SADCR_FRSIZE_0 | MDF_SADCR_FRSIZE_1) /*!< Frame size of 64 PCM samples */
+#define MDF_SAD_128_PCM_SAMPLES MDF_SADCR_FRSIZE_2 /*!< Frame size of 128 PCM samples */
+#define MDF_SAD_256_PCM_SAMPLES (MDF_SADCR_FRSIZE_0 | MDF_SADCR_FRSIZE_2) /*!< Frame size of 256 PCM samples */
+#define MDF_SAD_512_PCM_SAMPLES MDF_SADCR_FRSIZE /*!< Frame size of 512 PCM samples */
+/**
+ * @}
+ */
+
+/** @defgroup MDF_SadSoundTriggerEvent MDF sound activity detector trigger event
+ * @{
+ */
+#define MDF_SAD_ENTER_DETECT 0x00000000U /*!< Event when SAD enters in detect state */
+#define MDF_SAD_ENTER_EXIT_DETECT MDF_SADCR_DETCFG /*!< Event when SAD enters or exits from detect state */
+/**
+ * @}
+ */
+
+/** @defgroup MDF_SadDataMemoryTransfer MDF sound activity detector data memory transfer mode
+ * @{
+ */
+#define MDF_SAD_NO_MEMORY_TRANSFER 0x00000000U /*!< No memory transfer */
+#define MDF_SAD_MEMORY_TRANSFER_IN_DETECT MDF_SADCR_DATCAP_0 /*!< Memory transfer only in detect state */
+#define MDF_SAD_MEMORY_TRANSFER_ALWAYS MDF_SADCR_DATCAP /*!< Memory transfer always */
+/**
+ * @}
+ */
+
+/** @defgroup MDF_SadHangoverWindow MDF sound activity detector data hangover time window
+ * @{
+ */
+#define MDF_SAD_HANGOVER_4_FRAMES 0x00000000U /*!< Hangover window of 4 frames */
+#define MDF_SAD_HANGOVER_8_FRAMES MDF_SADCFGR_HGOVR_0 /*!< Hangover window of 8 frames */
+#define MDF_SAD_HANGOVER_16_FRAMES MDF_SADCFGR_HGOVR_1 /*!< Hangover window of 16 frames */
+#define MDF_SAD_HANGOVER_32_FRAMES (MDF_SADCFGR_HGOVR_0 | \
+ MDF_SADCFGR_HGOVR_1) /*!< Hangover window of 32 frames */
+#define MDF_SAD_HANGOVER_64_FRAMES MDF_SADCFGR_HGOVR_2 /*!< Hangover window of 64 frames */
+#define MDF_SAD_HANGOVER_128_FRAMES (MDF_SADCFGR_HGOVR_0 | \
+ MDF_SADCFGR_HGOVR_2) /*!< Hangover window of 128 frames */
+#define MDF_SAD_HANGOVER_256_FRAMES (MDF_SADCFGR_HGOVR_1 | \
+ MDF_SADCFGR_HGOVR_2) /*!< Hangover window of 256 frames */
+#define MDF_SAD_HANGOVER_512_FRAMES (MDF_SADCFGR_HGOVR_0 | \
+ MDF_SADCFGR_HGOVR_1 | \
+ MDF_SADCFGR_HGOVR_2) /*!< Hangover window of 512 frames */
+/**
+ * @}
+ */
+
+/** @defgroup MDF_SadLearningFrames MDF sound activity detector data learning frames
+ * @{
+ */
+#define MDF_SAD_LEARNING_2_FRAMES 0x00000000U /*!< 2 learning frames */
+#define MDF_SAD_LEARNING_4_FRAMES MDF_SADCFGR_LFRNB_0 /*!< 4 learning frames */
+#define MDF_SAD_LEARNING_8_FRAMES MDF_SADCFGR_LFRNB_1 /*!< 8 learning frames */
+#define MDF_SAD_LEARNING_16_FRAMES (MDF_SADCFGR_LFRNB_0 | MDF_SADCFGR_LFRNB_1) /*!< 16 learning frames */
+#define MDF_SAD_LEARNING_32_FRAMES MDF_SADCFGR_LFRNB /*!< 32 learning frames */
+/**
+ * @}
+ */
+
+/** @defgroup MDF_SadSignalNoiseThreshold MDF sound activity detector data signal to noise threshold
+ * @{
+ */
+#define MDF_SAD_SIGNAL_NOISE_3_5DB 0x00000000U /*!< Signal to noise threshold is 3.5dB */
+#define MDF_SAD_SIGNAL_NOISE_6DB MDF_SADCFGR_SNTHR_0 /*!< Signal to noise threshold is 6dB */
+#define MDF_SAD_SIGNAL_NOISE_9_5DB MDF_SADCFGR_SNTHR_1 /*!< Signal to noise threshold is 9.5dB */
+#define MDF_SAD_SIGNAL_NOISE_12DB (MDF_SADCFGR_SNTHR_0 | \
+ MDF_SADCFGR_SNTHR_1) /*!< Signal to noise threshold is 12dB */
+#define MDF_SAD_SIGNAL_NOISE_15_6DB MDF_SADCFGR_SNTHR_2 /*!< Signal to noise threshold is 15.6dB */
+#define MDF_SAD_SIGNAL_NOISE_18DB (MDF_SADCFGR_SNTHR_0 | \
+ MDF_SADCFGR_SNTHR_2) /*!< Signal to noise threshold is 18dB */
+#define MDF_SAD_SIGNAL_NOISE_21_6DB (MDF_SADCFGR_SNTHR_1 | \
+ MDF_SADCFGR_SNTHR_2) /*!< Signal to noise threshold is 21.6dB */
+#define MDF_SAD_SIGNAL_NOISE_24_1DB (MDF_SADCFGR_SNTHR_0 | \
+ MDF_SADCFGR_SNTHR_1 | \
+ MDF_SADCFGR_SNTHR_2) /*!< Signal to noise threshold is 24.1dB */
+#define MDF_SAD_SIGNAL_NOISE_27_6DB MDF_SADCFGR_SNTHR_3 /*!< Signal to noise threshold is 27.6dB */
+#define MDF_SAD_SIGNAL_NOISE_30_1DB (MDF_SADCFGR_SNTHR_0 | \
+ MDF_SADCFGR_SNTHR_3) /*!< Signal to noise threshold is 30.1dB */
+/**
+ * @}
+ */
+
+/** @defgroup MDF_FilterTriggerSource MDF filter trigger source
+ * @{
+ */
+#define MDF_FILTER_TRIG_TRGO 0x00000000U
+#define MDF_FILTER_TRIG_OLD_EVENT MDF_DFLTCR_TRGSRC_0 /*!< @note Not available for ADF instance */
+#define MDF_FILTER_TRIG_TIM1_TRGO MDF_DFLTCR_TRGSRC_1 /*!< @note Not available for ADF instance */
+#define MDF_FILTER_TRIG_TIM1_TRGO2 (MDF_DFLTCR_TRGSRC_0 | \
+ MDF_DFLTCR_TRGSRC_1) /*!< @note Not available for ADF instance */
+#define MDF_FILTER_TRIG_TIM8_TRGO MDF_DFLTCR_TRGSRC_2 /*!< @note Not available for ADF instance */
+#define MDF_FILTER_TRIG_TIM8_TRGO2 (MDF_DFLTCR_TRGSRC_0 | \
+ MDF_DFLTCR_TRGSRC_2) /*!< @note Not available for ADF instance */
+#define MDF_FILTER_TRIG_TIM3_TRGO (MDF_DFLTCR_TRGSRC_1 | \
+ MDF_DFLTCR_TRGSRC_2) /*!< @note Not available for ADF instance */
+#define MDF_FILTER_TRIG_TIM4_TRGO (MDF_DFLTCR_TRGSRC_0 | \
+ MDF_DFLTCR_TRGSRC_1 | \
+ MDF_DFLTCR_TRGSRC_2) /*!< @note Not available for ADF instance */
+#define MDF_FILTER_TRIG_TIM16_OC1 MDF_DFLTCR_TRGSRC_3 /*!< @note Not available for ADF instance */
+#define MDF_FILTER_TRIG_TIM6_TRGO (MDF_DFLTCR_TRGSRC_0 | \
+ MDF_DFLTCR_TRGSRC_3) /*!< @note Not available for ADF instance */
+#define MDF_FILTER_TRIG_TIM7_TRGO (MDF_DFLTCR_TRGSRC_1 | \
+ MDF_DFLTCR_TRGSRC_3) /*!< @note Not available for ADF instance */
+#define MDF_FILTER_TRIG_ADF_SAD_DET (MDF_DFLTCR_TRGSRC_0 | \
+ MDF_DFLTCR_TRGSRC_1 | \
+ MDF_DFLTCR_TRGSRC_3) /*!< @note Not available for ADF instance */
+#define MDF_FILTER_TRIG_EXTI11 (MDF_DFLTCR_TRGSRC_2 | \
+ MDF_DFLTCR_TRGSRC_3) /*!< @note Not available for ADF instance */
+#define MDF_FILTER_TRIG_EXTI15 (MDF_DFLTCR_TRGSRC_0 | \
+ MDF_DFLTCR_TRGSRC_2 | \
+ MDF_DFLTCR_TRGSRC_3)
+#define MDF_FILTER_TRIG_LPTIM1_OUT (MDF_DFLTCR_TRGSRC_1 | \
+ MDF_DFLTCR_TRGSRC_2 | \
+ MDF_DFLTCR_TRGSRC_3) /*!< @note Not available for ADF instance */
+#define MDF_FILTER_TRIG_ADF_TRGO MDF_DFLTCR_TRGSRC /*!< @note Not available for ADF instance */
+/**
+ * @}
+ */
+
+/** @defgroup MDF_FilterTriggerEdge MDF filter trigger edge
+ * @{
+ */
+#define MDF_FILTER_TRIG_RISING_EDGE 0x00000000U /*!< Rising edge */
+#define MDF_FILTER_TRIG_FALLING_EDGE MDF_DFLTCR_TRGSENS /*!< Falling edge */
+/**
+ * @}
+ */
+
+/** @defgroup MDF_DataSource MDF data source
+ * @{
+ */
+#define MDF_DATA_SOURCE_BSMX 0x00000000U /*!< Data from bitstream matrix */
+#define MDF_DATA_SOURCE_ADCITF1 MDF_DFLTCICR_DATSRC_1 /*!< Data from ADC interface 1.
+ @note Not available for ADF instance */
+#define MDF_DATA_SOURCE_ADCITF2 MDF_DFLTCICR_DATSRC /*!< Data from ADC interface 2.
+ @note Not available for ADF instance */
+/**
+ * @}
+ */
+
+/** @defgroup MDF_CicMode MDF CIC mode
+ * @{
+ */
+#define MDF_TWO_FILTERS_MCIC_FASTSINC 0x00000000U /*!< Two filters, main filter in FastSinc order.
+ @note Not available for ADF instance */
+#define MDF_TWO_FILTERS_MCIC_SINC1 MDF_DFLTCICR_CICMOD_0 /*!< Two filters, main filter in Sinc1 order.
+ @note Not available for ADF instance */
+#define MDF_TWO_FILTERS_MCIC_SINC2 MDF_DFLTCICR_CICMOD_1 /*!< Two filters, main filter in Sinc2 order.
+ @note Not available for ADF instance */
+#define MDF_TWO_FILTERS_MCIC_SINC3 (MDF_DFLTCICR_CICMOD_0 | \
+ MDF_DFLTCICR_CICMOD_1) /*!< Two filters, main filter in Sinc3 order.
+ @note Not available for ADF instance */
+#define MDF_ONE_FILTER_SINC4 MDF_DFLTCICR_CICMOD_2 /*!< One filter in Sinc4 order */
+#define MDF_ONE_FILTER_SINC5 (MDF_DFLTCICR_CICMOD_0 | \
+ MDF_DFLTCICR_CICMOD_2) /*!< One filter in Sinc5 order */
+/**
+ * @}
+ */
+
+/** @defgroup MDF_AcquisitionMode MDF acquisition mode
+ * @{
+ */
+#define MDF_MODE_ASYNC_CONT 0x00000000U /*!< Asynchronous, continuous acquisition mode */
+#define MDF_MODE_ASYNC_SINGLE MDF_DFLTCR_ACQMOD_0 /*!< Asynchronous, single-shot acquisition mode.
+ @note Not available for ADF instance with SAD usage */
+#define MDF_MODE_SYNC_CONT MDF_DFLTCR_ACQMOD_1 /*!< Synchronous, continuous acquisition mode */
+#define MDF_MODE_SYNC_SINGLE (MDF_DFLTCR_ACQMOD_0 | \
+ MDF_DFLTCR_ACQMOD_1) /*!< Synchronous, single-shot acquisition mode.
+ @note Not available for ADF instance with SAD usage*/
+#define MDF_MODE_WINDOW_CONT MDF_DFLTCR_ACQMOD_2 /*!< Window, continuous acquisition mode.
+ @note Not available for ADF instance with SAD usage*/
+#define MDF_MODE_SYNC_SNAPSHOT (MDF_DFLTCR_ACQMOD_0 | \
+ MDF_DFLTCR_ACQMOD_2) /*!< Synchronous, snapshot acquisition mode.
+ @note Not available for ADF instance */
+/**
+ * @}
+ */
+
+/** @defgroup MDF_FifoThreshold MDF RXFIFO threshold
+ * @{
+ */
+#define MDF_FIFO_THRESHOLD_NOT_EMPTY 0x00000000U /*!< Event generated when RXFIFO is not empty */
+#define MDF_FIFO_THRESHOLD_HALF_FULL MDF_DFLTCR_FTH /*!< Event generated when RXFIFO is half_full */
+/**
+ * @}
+ */
+
+/** @defgroup MDF_SnapshotFormat MDF snapshot format
+ * @{
+ */
+#define MDF_SNAPSHOT_23BITS 0x00000000U /*!< Snapshot data resolution of 23 bits */
+#define MDF_SNAPSHOT_16BITS MDF_DFLTCR_SNPSFMT /*!< Snapshot data resolution of 16 bits */
+/**
+ * @}
+ */
+
+/** @defgroup MDF_BreakSignals MDF break signals
+ * @{
+ */
+#define MDF_NO_BREAK_SIGNAL 0x00000000U /*!< No break signal */
+#define MDF_TIM1_BREAK_SIGNAL 0x00000001U /*!< TIM1_BREAK signal */
+#define MDF_TIM1_BREAK2_SIGNAL 0x00000002U /*!< TIM1_BREAK2 signal */
+#define MDF_TIM8_BREAK_SIGNAL 0x00000004U /*!< TIM8_BREAK signal */
+#define MDF_TIM8_BREAK2_SIGNAL 0x00000008U /*!< TIM8_BREAK2 signal */
+/**
+ * @}
+ */
+
+/** @defgroup MDF_OldCicMode MDF out-off limit detector CIC mode
+ * @{
+ */
+#define MDF_OLD_FILTER_FASTSINC 0x00000000U /*!< Out-off limit detector filter in FastSinc order */
+#define MDF_OLD_FILTER_SINC1 MDF_OLDCR_ACICN_0 /*!< Out-off limit detector filter in Sinc1 order */
+#define MDF_OLD_FILTER_SINC2 MDF_OLDCR_ACICN_1 /*!< Out-off limit detector filter in Sinc2 order */
+#define MDF_OLD_FILTER_SINC3 MDF_OLDCR_ACICN /*!< Out-off limit detector filter in Sinc3 order */
+/**
+ * @}
+ */
+
+/** @defgroup MDF_OldEventConfig MDF out-off limit detector event configuration
+ * @{
+ */
+#define MDF_OLD_SIGNAL_OUTSIDE_THRESHOLDS 0x00000000U /*!< Out-off limit detector event is generated
+ if signal is outside thresholds */
+#define MDF_OLD_SIGNAL_IN_THRESHOLDS MDF_OLDCR_THINB /*!< Out-off limit detector event is generated
+ if signal is in thresholds */
+/**
+ * @}
+ */
+
+/** @defgroup MDF_OldThresholdInfo MDF out-off limit detector threshold information
+ * @{
+ */
+#define MDF_OLD_IN_THRESHOLDS 0x00000000U /*!< The signal was in thresholds when out-off limit detection occurs */
+#define MDF_OLD_HIGH_THRESHOLD 0x00000001U /*!< The signal was higher than high threshold
+ when out-off limit detection occurs */
+#define MDF_OLD_LOW_THRESHOLD 0x00000002U /*!< The signal was lower than low threshold
+ when out-off limit detection occurs */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup MDF_Exported_Macros MDF Exported Macros
+ * @{
+ */
+
+/** @brief Reset MDF handle state.
+ * @param __HANDLE__ MDF handle.
+ * @retval None
+ */
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+#define __HAL_MDF_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_MDF_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
+#define __HAL_MDF_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MDF_STATE_RESET)
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup MDF_Exported_Functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+/** @addtogroup MDF_Exported_Functions_Group1
+ * @{
+ */
+HAL_StatusTypeDef HAL_MDF_Init(MDF_HandleTypeDef *hmdf);
+HAL_StatusTypeDef HAL_MDF_DeInit(MDF_HandleTypeDef *hmdf);
+void HAL_MDF_MspInit(MDF_HandleTypeDef *hmdf);
+void HAL_MDF_MspDeInit(MDF_HandleTypeDef *hmdf);
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_MDF_RegisterCallback(MDF_HandleTypeDef *hmdf,
+ HAL_MDF_CallbackIDTypeDef CallbackID,
+ pMDF_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_MDF_UnRegisterCallback(MDF_HandleTypeDef *hmdf,
+ HAL_MDF_CallbackIDTypeDef CallbackID);
+HAL_StatusTypeDef HAL_MDF_RegisterOldCallback(MDF_HandleTypeDef *hmdf,
+ pMDF_OldCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_MDF_UnRegisterOldCallback(MDF_HandleTypeDef *hmdf);
+HAL_StatusTypeDef HAL_MDF_RegisterSndLvlCallback(MDF_HandleTypeDef *hmdf,
+ pMDF_SndLvlCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_MDF_UnRegisterSndLvlCallback(MDF_HandleTypeDef *hmdf);
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/* Acquisition functions *****************************************************/
+/** @addtogroup MDF_Exported_Functions_Group2
+ * @{
+ */
+HAL_StatusTypeDef HAL_MDF_AcqStart(MDF_HandleTypeDef *hmdf, MDF_FilterConfigTypeDef *pFilterConfig);
+HAL_StatusTypeDef HAL_MDF_PollForAcq(MDF_HandleTypeDef *hmdf, uint32_t Timeout);
+HAL_StatusTypeDef HAL_MDF_PollForSnapshotAcq(MDF_HandleTypeDef *hmdf, uint32_t Timeout);
+HAL_StatusTypeDef HAL_MDF_GetAcqValue(MDF_HandleTypeDef *hmdf, int32_t *pValue);
+HAL_StatusTypeDef HAL_MDF_GetSnapshotAcqValue(MDF_HandleTypeDef *hmdf, MDF_SnapshotParamTypeDef *pSnapshotParam);
+HAL_StatusTypeDef HAL_MDF_AcqStop(MDF_HandleTypeDef *hmdf);
+HAL_StatusTypeDef HAL_MDF_AcqStart_IT(MDF_HandleTypeDef *hmdf, MDF_FilterConfigTypeDef *pFilterConfig);
+HAL_StatusTypeDef HAL_MDF_AcqStop_IT(MDF_HandleTypeDef *hmdf);
+HAL_StatusTypeDef HAL_MDF_AcqStart_DMA(MDF_HandleTypeDef *hmdf, MDF_FilterConfigTypeDef *pFilterConfig,
+ MDF_DmaConfigTypeDef *pDmaConfig);
+HAL_StatusTypeDef HAL_MDF_AcqStop_DMA(MDF_HandleTypeDef *hmdf);
+HAL_StatusTypeDef HAL_MDF_GenerateTrgo(MDF_HandleTypeDef *hmdf);
+HAL_StatusTypeDef HAL_MDF_SetDelay(MDF_HandleTypeDef *hmdf, uint32_t Delay);
+HAL_StatusTypeDef HAL_MDF_GetDelay(MDF_HandleTypeDef *hmdf, uint32_t *pDelay);
+HAL_StatusTypeDef HAL_MDF_SetGain(MDF_HandleTypeDef *hmdf, int32_t Gain);
+HAL_StatusTypeDef HAL_MDF_GetGain(MDF_HandleTypeDef *hmdf, int32_t *pGain);
+HAL_StatusTypeDef HAL_MDF_SetOffset(MDF_HandleTypeDef *hmdf, int32_t Offset);
+HAL_StatusTypeDef HAL_MDF_GetOffset(MDF_HandleTypeDef *hmdf, int32_t *pOffset);
+HAL_StatusTypeDef HAL_MDF_PollForSndLvl(MDF_HandleTypeDef *hmdf, uint32_t Timeout, uint32_t *pSoundLevel,
+ uint32_t *pAmbientNoise);
+HAL_StatusTypeDef HAL_MDF_PollForSad(MDF_HandleTypeDef *hmdf, uint32_t Timeout);
+void HAL_MDF_AcqCpltCallback(MDF_HandleTypeDef *hmdf);
+void HAL_MDF_AcqHalfCpltCallback(MDF_HandleTypeDef *hmdf);
+void HAL_MDF_SndLvlCallback(MDF_HandleTypeDef *hmdf, uint32_t SoundLevel, uint32_t AmbientNoise);
+void HAL_MDF_SadCallback(MDF_HandleTypeDef *hmdf);
+/**
+ * @}
+ */
+
+/* Clock absence detection functions *****************************************/
+/** @addtogroup MDF_Exported_Functions_Group3
+ * @{
+ */
+HAL_StatusTypeDef HAL_MDF_PollForCkab(MDF_HandleTypeDef *hmdf, uint32_t Timeout);
+HAL_StatusTypeDef HAL_MDF_CkabStart_IT(MDF_HandleTypeDef *hmdf);
+HAL_StatusTypeDef HAL_MDF_CkabStop_IT(MDF_HandleTypeDef *hmdf);
+/**
+ * @}
+ */
+
+/* Short circuit detection functions *****************************************/
+/** @addtogroup MDF_Exported_Functions_Group4
+ * @{
+ */
+HAL_StatusTypeDef HAL_MDF_ScdStart(MDF_HandleTypeDef *hmdf, MDF_ScdConfigTypeDef *pScdConfig);
+HAL_StatusTypeDef HAL_MDF_PollForScd(MDF_HandleTypeDef *hmdf, uint32_t Timeout);
+HAL_StatusTypeDef HAL_MDF_ScdStop(MDF_HandleTypeDef *hmdf);
+HAL_StatusTypeDef HAL_MDF_ScdStart_IT(MDF_HandleTypeDef *hmdf, MDF_ScdConfigTypeDef *pScdConfig);
+HAL_StatusTypeDef HAL_MDF_ScdStop_IT(MDF_HandleTypeDef *hmdf);
+/**
+ * @}
+ */
+
+/* Out-off limit detection functions *****************************************/
+/** @addtogroup MDF_Exported_Functions_Group5
+ * @{
+ */
+HAL_StatusTypeDef HAL_MDF_OldStart(MDF_HandleTypeDef *hmdf, MDF_OldConfigTypeDef *pOldConfig);
+HAL_StatusTypeDef HAL_MDF_PollForOld(MDF_HandleTypeDef *hmdf, uint32_t Timeout, uint32_t *pThresholdInfo);
+HAL_StatusTypeDef HAL_MDF_OldStop(MDF_HandleTypeDef *hmdf);
+HAL_StatusTypeDef HAL_MDF_OldStart_IT(MDF_HandleTypeDef *hmdf, MDF_OldConfigTypeDef *pOldConfig);
+HAL_StatusTypeDef HAL_MDF_OldStop_IT(MDF_HandleTypeDef *hmdf);
+void HAL_MDF_OldCallback(MDF_HandleTypeDef *hmdf, uint32_t ThresholdInfo);
+/**
+ * @}
+ */
+
+/* Generic functions *********************************************************/
+/** @addtogroup MDF_Exported_Functions_Group6
+ * @{
+ */
+void HAL_MDF_IRQHandler(MDF_HandleTypeDef *hmdf);
+void HAL_MDF_ErrorCallback(MDF_HandleTypeDef *hmdf);
+HAL_MDF_StateTypeDef HAL_MDF_GetState(MDF_HandleTypeDef *hmdf);
+uint32_t HAL_MDF_GetError(MDF_HandleTypeDef *hmdf);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup MDF_Private_Macros MDF Private Macros
+ * @{
+ */
+#define IS_MDF_INSTANCE(PARAM) (((PARAM) == MDF1_Filter0) || \
+ ((PARAM) == MDF1_Filter1) || \
+ ((PARAM) == MDF1_Filter2) || \
+ ((PARAM) == MDF1_Filter3) || \
+ ((PARAM) == MDF1_Filter4) || \
+ ((PARAM) == MDF1_Filter5))
+
+#define IS_ADF_INSTANCE(PARAM) ((PARAM) == ADF1_Filter0)
+
+#define IS_MDF_FILTER_BITSTREAM(PARAM) (((PARAM) == MDF_BITSTREAM0_RISING) || \
+ ((PARAM) == MDF_BITSTREAM0_FALLING) || \
+ ((PARAM) == MDF_BITSTREAM1_RISING) || \
+ ((PARAM) == MDF_BITSTREAM1_FALLING) || \
+ ((PARAM) == MDF_BITSTREAM2_RISING) || \
+ ((PARAM) == MDF_BITSTREAM2_FALLING) || \
+ ((PARAM) == MDF_BITSTREAM3_RISING) || \
+ ((PARAM) == MDF_BITSTREAM3_FALLING) || \
+ ((PARAM) == MDF_BITSTREAM4_RISING) || \
+ ((PARAM) == MDF_BITSTREAM4_FALLING) || \
+ ((PARAM) == MDF_BITSTREAM5_RISING) || \
+ ((PARAM) == MDF_BITSTREAM5_FALLING))
+
+#define IS_MDF_INTERLEAVED_FILTERS(PARAM) ((PARAM) <= 5U)
+
+#define IS_MDF_PROC_CLOCK_DIVIDER(PARAM) ((1U <= (PARAM)) && ((PARAM) <= 128U))
+
+#define IS_MDF_OUTPUT_CLOCK_PINS(PARAM) (((PARAM) == MDF_OUTPUT_CLOCK_0) || \
+ ((PARAM) == MDF_OUTPUT_CLOCK_1) || \
+ ((PARAM) == MDF_OUTPUT_CLOCK_ALL))
+
+#define IS_MDF_OUTPUT_CLOCK_DIVIDER(PARAM) ((1U <= (PARAM)) && ((PARAM) <= 16U))
+
+#define IS_MDF_OUTPUT_CLOCK_TRIGGER_SOURCE(PARAM) (((PARAM) == MDF_CLOCK_TRIG_TRGO) || \
+ ((PARAM) == MDF_CLOCK_TRIG_TIM1_TRGO) || \
+ ((PARAM) == MDF_CLOCK_TRIG_TIM1_TRGO2) || \
+ ((PARAM) == MDF_CLOCK_TRIG_TIM8_TRGO) || \
+ ((PARAM) == MDF_CLOCK_TRIG_TIM8_TRGO2) || \
+ ((PARAM) == MDF_CLOCK_TRIG_TIM3_TRGO) || \
+ ((PARAM) == MDF_CLOCK_TRIG_TIM4_TRGO) || \
+ ((PARAM) == MDF_CLOCK_TRIG_TIM16_OC1) || \
+ ((PARAM) == MDF_CLOCK_TRIG_TIM6_TRGO) || \
+ ((PARAM) == MDF_CLOCK_TRIG_TIM7_TRGO) || \
+ ((PARAM) == MDF_CLOCK_TRIG_SAD_DET) || \
+ ((PARAM) == MDF_CLOCK_TRIG_EXTI11) || \
+ ((PARAM) == MDF_CLOCK_TRIG_EXTI15) || \
+ ((PARAM) == MDF_CLOCK_TRIG_LPTIM1_OUT) || \
+ ((PARAM) == MDF_CLOCK_TRIG_SAD_TRGO))
+
+#define IS_ADF_OUTPUT_CLOCK_TRIGGER_SOURCE(PARAM) (((PARAM) == MDF_CLOCK_TRIG_TRGO) || \
+ ((PARAM) == MDF_CLOCK_TRIG_EXTI15))
+
+#define IS_MDF_OUTPUT_CLOCK_TRIGGER_EDGE(PARAM) (((PARAM) == MDF_CLOCK_TRIG_RISING_EDGE) || \
+ ((PARAM) == MDF_CLOCK_TRIG_FALLING_EDGE))
+
+#define IS_MDF_SITF_MODE(PARAM) (((PARAM) == MDF_SITF_LF_MASTER_SPI_MODE) || \
+ ((PARAM) == MDF_SITF_NORMAL_SPI_MODE) || \
+ ((PARAM) == MDF_SITF_MANCHESTER_FALLING_MODE) || \
+ ((PARAM) == MDF_SITF_MANCHESTER_RISING_MODE))
+
+#define IS_MDF_SITF_CLOCK_SOURCE(PARAM) (((PARAM) == MDF_SITF_CCK0_SOURCE) || \
+ ((PARAM) == MDF_SITF_CCK1_SOURCE) || \
+ ((PARAM) == MDF_SITF_CKI_SOURCE))
+
+#define IS_MDF_SITF_THRESHOLD(PARAM) ((4U <= (PARAM)) && ((PARAM) <= 31U))
+
+#define IS_MDF_CIC_MODE(PARAM) (((PARAM) == MDF_TWO_FILTERS_MCIC_FASTSINC) || \
+ ((PARAM) == MDF_TWO_FILTERS_MCIC_SINC1) || \
+ ((PARAM) == MDF_TWO_FILTERS_MCIC_SINC2) || \
+ ((PARAM) == MDF_TWO_FILTERS_MCIC_SINC3) || \
+ ((PARAM) == MDF_ONE_FILTER_SINC4) || \
+ ((PARAM) == MDF_ONE_FILTER_SINC5))
+
+#define IS_ADF_CIC_MODE(PARAM) (((PARAM) == MDF_ONE_FILTER_SINC4) || \
+ ((PARAM) == MDF_ONE_FILTER_SINC5))
+
+#define IS_MDF_ACQUISITION_MODE(PARAM) (((PARAM) == MDF_MODE_ASYNC_CONT) || \
+ ((PARAM) == MDF_MODE_ASYNC_SINGLE) || \
+ ((PARAM) == MDF_MODE_SYNC_CONT) || \
+ ((PARAM) == MDF_MODE_SYNC_SINGLE) || \
+ ((PARAM) == MDF_MODE_WINDOW_CONT) || \
+ ((PARAM) == MDF_MODE_SYNC_SNAPSHOT))
+
+#define IS_ADF_ACQUISITION_MODE(PARAM) (((PARAM) == MDF_MODE_ASYNC_CONT) || \
+ ((PARAM) == MDF_MODE_ASYNC_SINGLE) || \
+ ((PARAM) == MDF_MODE_SYNC_CONT) || \
+ ((PARAM) == MDF_MODE_SYNC_SINGLE) || \
+ ((PARAM) == MDF_MODE_WINDOW_CONT))
+
+#define IS_MDF_DISCARD_SAMPLES(PARAM) ((PARAM) <= 255U)
+
+#define IS_MDF_FIFO_THRESHOLD(PARAM) (((PARAM) == MDF_FIFO_THRESHOLD_NOT_EMPTY) || \
+ ((PARAM) == MDF_FIFO_THRESHOLD_HALF_FULL))
+
+#define IS_MDF_TRIGGER_SOURCE(PARAM) (((PARAM) == MDF_FILTER_TRIG_TRGO) || \
+ ((PARAM) == MDF_FILTER_TRIG_OLD_EVENT) || \
+ ((PARAM) == MDF_FILTER_TRIG_TIM1_TRGO) || \
+ ((PARAM) == MDF_FILTER_TRIG_TIM1_TRGO2) || \
+ ((PARAM) == MDF_FILTER_TRIG_TIM8_TRGO) || \
+ ((PARAM) == MDF_FILTER_TRIG_TIM8_TRGO2) || \
+ ((PARAM) == MDF_FILTER_TRIG_TIM3_TRGO) || \
+ ((PARAM) == MDF_FILTER_TRIG_TIM4_TRGO) || \
+ ((PARAM) == MDF_FILTER_TRIG_TIM16_OC1) || \
+ ((PARAM) == MDF_FILTER_TRIG_TIM6_TRGO) || \
+ ((PARAM) == MDF_FILTER_TRIG_TIM7_TRGO) || \
+ ((PARAM) == MDF_FILTER_TRIG_ADF_SAD_DET) || \
+ ((PARAM) == MDF_FILTER_TRIG_EXTI11) || \
+ ((PARAM) == MDF_FILTER_TRIG_EXTI15) || \
+ ((PARAM) == MDF_FILTER_TRIG_LPTIM1_OUT) || \
+ ((PARAM) == MDF_FILTER_TRIG_ADF_TRGO))
+
+#define IS_ADF_TRIGGER_SOURCE(PARAM) (((PARAM) == MDF_FILTER_TRIG_TRGO) || \
+ ((PARAM) == MDF_FILTER_TRIG_EXTI15))
+
+#define IS_MDF_TRIGGER_EDGE(PARAM) (((PARAM) == MDF_FILTER_TRIG_RISING_EDGE) || \
+ ((PARAM) == MDF_FILTER_TRIG_FALLING_EDGE))
+
+#define IS_MDF_SNAPSHOT_FORMAT(PARAM) (((PARAM) == MDF_SNAPSHOT_23BITS) || \
+ ((PARAM) == MDF_SNAPSHOT_16BITS))
+
+#define IS_MDF_DATA_SOURCE(PARAM) (((PARAM) == MDF_DATA_SOURCE_BSMX) || \
+ ((PARAM) == MDF_DATA_SOURCE_ADCITF1) || \
+ ((PARAM) == MDF_DATA_SOURCE_ADCITF2))
+
+#define IS_ADF_DATA_SOURCE(PARAM) ((PARAM) == MDF_DATA_SOURCE_BSMX)
+
+#define IS_MDF_DECIMATION_RATIO(PARAM) ((2U <= (PARAM)) && ((PARAM) <= 512U))
+
+#define IS_MDF_GAIN(PARAM) ((-16 <= (PARAM)) && ((PARAM) <= 24))
+
+#define IS_MDF_DELAY(PARAM) ((PARAM) <= 127U)
+
+#define IS_MDF_OFFSET(PARAM) ((-33554432 <= (PARAM)) && ((PARAM) <= 33554431))
+
+#define IS_MDF_RSF_DECIMATION_RATIO(PARAM) (((PARAM) == MDF_RSF_DECIMATION_RATIO_4) || \
+ ((PARAM) == MDF_RSF_DECIMATION_RATIO_1))
+
+#define IS_MDF_HPF_CUTOFF_FREQ(PARAM) (((PARAM) == MDF_HPF_CUTOFF_0_000625FPCM) || \
+ ((PARAM) == MDF_HPF_CUTOFF_0_00125FPCM) || \
+ ((PARAM) == MDF_HPF_CUTOFF_0_0025FPCM) || \
+ ((PARAM) == MDF_HPF_CUTOFF_0_0095FPCM))
+
+#define IS_MDF_INTEGRATOR_VALUE(PARAM) ((2U <= (PARAM)) && ((PARAM) <= 128U))
+
+#define IS_MDF_INTEGRATOR_OUTPUT_DIV(PARAM) (((PARAM) == MDF_INTEGRATOR_OUTPUT_DIV_128) || \
+ ((PARAM) == MDF_INTEGRATOR_OUTPUT_DIV_32) || \
+ ((PARAM) == MDF_INTEGRATOR_OUTPUT_DIV_4) || \
+ ((PARAM) == MDF_INTEGRATOR_OUTPUT_NO_DIV))
+
+#define IS_MDF_SAD_MODE(PARAM) (((PARAM) == MDF_SAD_VOICE_ACTIVITY_DETECTOR) || \
+ ((PARAM) == MDF_SAD_SOUND_DETECTOR) || \
+ ((PARAM) == MDF_SAD_AMBIENT_NOISE_DETECTOR))
+
+#define IS_MDF_SAD_FRAME_SIZE(PARAM) (((PARAM) == MDF_SAD_8_PCM_SAMPLES) || \
+ ((PARAM) == MDF_SAD_16_PCM_SAMPLES) || \
+ ((PARAM) == MDF_SAD_32_PCM_SAMPLES) || \
+ ((PARAM) == MDF_SAD_64_PCM_SAMPLES) || \
+ ((PARAM) == MDF_SAD_128_PCM_SAMPLES) || \
+ ((PARAM) == MDF_SAD_256_PCM_SAMPLES) || \
+ ((PARAM) == MDF_SAD_512_PCM_SAMPLES))
+
+#define IS_MDF_SAD_SOUND_TRIGGER(PARAM) (((PARAM) == MDF_SAD_ENTER_DETECT) || \
+ ((PARAM) == MDF_SAD_ENTER_EXIT_DETECT))
+
+#define IS_MDF_SAD_DATA_MEMORY_TRANSFER(PARAM) (((PARAM) == MDF_SAD_NO_MEMORY_TRANSFER) || \
+ ((PARAM) == MDF_SAD_MEMORY_TRANSFER_IN_DETECT) || \
+ ((PARAM) == MDF_SAD_MEMORY_TRANSFER_ALWAYS))
+
+#define IS_MDF_SAD_MIN_NOISE_LEVEL(PARAM) ((PARAM) <= 8191U)
+
+#define IS_MDF_SAD_HANGOVER_WINDOW(PARAM) (((PARAM) == MDF_SAD_HANGOVER_4_FRAMES) || \
+ ((PARAM) == MDF_SAD_HANGOVER_8_FRAMES) || \
+ ((PARAM) == MDF_SAD_HANGOVER_16_FRAMES) || \
+ ((PARAM) == MDF_SAD_HANGOVER_32_FRAMES) || \
+ ((PARAM) == MDF_SAD_HANGOVER_64_FRAMES) || \
+ ((PARAM) == MDF_SAD_HANGOVER_128_FRAMES) || \
+ ((PARAM) == MDF_SAD_HANGOVER_256_FRAMES) || \
+ ((PARAM) == MDF_SAD_HANGOVER_512_FRAMES))
+
+#define IS_MDF_SAD_LEARNING_FRAMES(PARAM) (((PARAM) == MDF_SAD_LEARNING_2_FRAMES) || \
+ ((PARAM) == MDF_SAD_LEARNING_4_FRAMES) || \
+ ((PARAM) == MDF_SAD_LEARNING_8_FRAMES) || \
+ ((PARAM) == MDF_SAD_LEARNING_16_FRAMES) || \
+ ((PARAM) == MDF_SAD_LEARNING_32_FRAMES))
+
+#define IS_MDF_SAD_AMBIENT_NOISE_SLOPE(PARAM) ((PARAM) <= 7U)
+
+#define IS_MDF_SAD_SIGNAL_NOISE_THRESHOLD(PARAM) (((PARAM) == MDF_SAD_SIGNAL_NOISE_3_5DB) || \
+ ((PARAM) == MDF_SAD_SIGNAL_NOISE_6DB) || \
+ ((PARAM) == MDF_SAD_SIGNAL_NOISE_9_5DB) || \
+ ((PARAM) == MDF_SAD_SIGNAL_NOISE_12DB) || \
+ ((PARAM) == MDF_SAD_SIGNAL_NOISE_15_6DB) || \
+ ((PARAM) == MDF_SAD_SIGNAL_NOISE_18DB) || \
+ ((PARAM) == MDF_SAD_SIGNAL_NOISE_21_6DB) || \
+ ((PARAM) == MDF_SAD_SIGNAL_NOISE_24_1DB) || \
+ ((PARAM) == MDF_SAD_SIGNAL_NOISE_27_6DB) || \
+ ((PARAM) == MDF_SAD_SIGNAL_NOISE_30_1DB))
+
+#define IS_MDF_SCD_THRESHOLD(PARAM) ((2U <= (PARAM)) && ((PARAM) <= 256U))
+
+#define IS_MDF_BREAK_SIGNAL(PARAM) ((PARAM) <= 15U)
+
+#define IS_MDF_OLD_CIC_MODE(PARAM) (((PARAM) == MDF_OLD_FILTER_FASTSINC) || \
+ ((PARAM) == MDF_OLD_FILTER_SINC1) || \
+ ((PARAM) == MDF_OLD_FILTER_SINC2) || \
+ ((PARAM) == MDF_OLD_FILTER_SINC3))
+
+#define IS_MDF_OLD_DECIMATION_RATIO(PARAM) ((1U <= (PARAM)) && ((PARAM) <= 32U))
+
+#define IS_MDF_OLD_THRESHOLD(PARAM) ((-33554432 <= (PARAM)) && ((PARAM) <= 33554431))
+
+#define IS_MDF_OLD_EVENT_CONFIG(PARAM) (((PARAM) == MDF_OLD_SIGNAL_OUTSIDE_THRESHOLDS) || \
+ ((PARAM) == MDF_OLD_SIGNAL_IN_THRESHOLDS))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_MDF_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_mmc.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_mmc.h
new file mode 100644
index 00000000..9f63d6d5
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_mmc.h
@@ -0,0 +1,809 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_mmc.h
+ * @author MCD Application Team
+ * @brief Header file of MMC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_MMC_H
+#define STM32U5xx_HAL_MMC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_ll_sdmmc.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup MMC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup MMC_Exported_Types MMC Exported Types
+ * @{
+ */
+
+/** @defgroup MMC_Exported_Types_Group1 MMC State enumeration structure
+ * @{
+ */
+typedef enum
+{
+ HAL_MMC_STATE_RESET = ((uint32_t)0x00000000U), /*!< MMC not yet initialized or disabled */
+ HAL_MMC_STATE_READY = ((uint32_t)0x00000001U), /*!< MMC initialized and ready for use */
+ HAL_MMC_STATE_TIMEOUT = ((uint32_t)0x00000002U), /*!< MMC Timeout state */
+ HAL_MMC_STATE_BUSY = ((uint32_t)0x00000003U), /*!< MMC process ongoing */
+ HAL_MMC_STATE_PROGRAMMING = ((uint32_t)0x00000004U), /*!< MMC Programming State */
+ HAL_MMC_STATE_RECEIVING = ((uint32_t)0x00000005U), /*!< MMC Receinving State */
+ HAL_MMC_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< MMC Transfer State */
+ HAL_MMC_STATE_ERROR = ((uint32_t)0x0000000FU) /*!< MMC is in error state */
+} HAL_MMC_StateTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Types_Group2 MMC Card State enumeration structure
+ * @{
+ */
+typedef uint32_t HAL_MMC_CardStateTypeDef;
+
+#define HAL_MMC_CARD_READY 0x00000001U /*!< Card state is ready */
+#define HAL_MMC_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state */
+#define HAL_MMC_CARD_STANDBY 0x00000003U /*!< Card is in standby state */
+#define HAL_MMC_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */
+#define HAL_MMC_CARD_SENDING 0x00000005U /*!< Card is sending an operation */
+#define HAL_MMC_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */
+#define HAL_MMC_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */
+#define HAL_MMC_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */
+#define HAL_MMC_CARD_ERROR 0x000000FFU /*!< Card response Error */
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Types_Group3 MMC Handle Structure definition
+ * @{
+ */
+#define MMC_InitTypeDef SDMMC_InitTypeDef
+#define MMC_TypeDef SDMMC_TypeDef
+
+/**
+ * @brief MMC Card Information Structure definition
+ */
+typedef struct
+{
+ uint32_t CardType; /*!< Specifies the card Type */
+
+ uint32_t Class; /*!< Specifies the class of the card class */
+
+ uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */
+
+ uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */
+
+ uint32_t BlockSize; /*!< Specifies one block size in bytes */
+
+ uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */
+
+ uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */
+
+} HAL_MMC_CardInfoTypeDef;
+
+/**
+ * @brief MMC handle Structure definition
+ */
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+typedef struct __MMC_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+{
+ MMC_TypeDef *Instance; /*!< MMC registers base address */
+
+ MMC_InitTypeDef Init; /*!< MMC required parameters */
+
+ HAL_LockTypeDef Lock; /*!< MMC locking object */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */
+
+ uint32_t TxXferSize; /*!< MMC Tx Transfer size */
+
+ uint8_t *pRxBuffPtr; /*!< Pointer to MMC Rx transfer Buffer */
+
+ uint32_t RxXferSize; /*!< MMC Rx Transfer size */
+
+ __IO uint32_t Context; /*!< MMC transfer context */
+
+ __IO HAL_MMC_StateTypeDef State; /*!< MMC card State */
+
+ __IO uint32_t ErrorCode; /*!< MMC Card Error codes */
+
+ HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */
+
+ uint32_t CSD[4U]; /*!< MMC card specific data table */
+
+ uint32_t CID[4U]; /*!< MMC card identification number table */
+
+ uint32_t Ext_CSD[128];
+
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+ void (* TxCpltCallback)(struct __MMC_HandleTypeDef *hmmc);
+ void (* RxCpltCallback)(struct __MMC_HandleTypeDef *hmmc);
+ void (* ErrorCallback)(struct __MMC_HandleTypeDef *hmmc);
+ void (* AbortCpltCallback)(struct __MMC_HandleTypeDef *hmmc);
+ void (* Read_DMALnkLstBufCpltCallback)(struct __MMC_HandleTypeDef *hmmc);
+ void (* Write_DMALnkLstBufCpltCallback)(struct __MMC_HandleTypeDef *hmmc);
+
+ void (* MspInitCallback)(struct __MMC_HandleTypeDef *hmmc);
+ void (* MspDeInitCallback)(struct __MMC_HandleTypeDef *hmmc);
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+} MMC_HandleTypeDef;
+
+
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Types_Group4 Card Specific Data: CSD Register
+ * @{
+ */
+typedef struct
+{
+ __IO uint8_t CSDStruct; /*!< CSD structure */
+ __IO uint8_t SysSpecVersion; /*!< System specification version */
+ __IO uint8_t Reserved1; /*!< Reserved */
+ __IO uint8_t TAAC; /*!< Data read access time 1 */
+ __IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */
+ __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */
+ __IO uint16_t CardComdClasses; /*!< Card command classes */
+ __IO uint8_t RdBlockLen; /*!< Max. read data block length */
+ __IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */
+ __IO uint8_t WrBlockMisalign; /*!< Write block misalignment */
+ __IO uint8_t RdBlockMisalign; /*!< Read block misalignment */
+ __IO uint8_t DSRImpl; /*!< DSR implemented */
+ __IO uint8_t Reserved2; /*!< Reserved */
+ __IO uint32_t DeviceSize; /*!< Device Size */
+ __IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */
+ __IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */
+ __IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */
+ __IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */
+ __IO uint8_t DeviceSizeMul; /*!< Device size multiplier */
+ __IO uint8_t EraseGrSize; /*!< Erase group size */
+ __IO uint8_t EraseGrMul; /*!< Erase group size multiplier */
+ __IO uint8_t WrProtectGrSize; /*!< Write protect group size */
+ __IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */
+ __IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */
+ __IO uint8_t WrSpeedFact; /*!< Write speed factor */
+ __IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */
+ __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
+ __IO uint8_t Reserved3; /*!< Reserved */
+ __IO uint8_t ContentProtectAppli; /*!< Content protection application */
+ __IO uint8_t FileFormatGroup; /*!< File format group */
+ __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
+ __IO uint8_t PermWrProtect; /*!< Permanent write protection */
+ __IO uint8_t TempWrProtect; /*!< Temporary write protection */
+ __IO uint8_t FileFormat; /*!< File format */
+ __IO uint8_t ECC; /*!< ECC code */
+ __IO uint8_t CSD_CRC; /*!< CSD CRC */
+ __IO uint8_t Reserved4; /*!< Always 1 */
+
+} HAL_MMC_CardCSDTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Types_Group5 Card Identification Data: CID Register
+ * @{
+ */
+typedef struct
+{
+ __IO uint8_t ManufacturerID; /*!< Manufacturer ID */
+ __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */
+ __IO uint32_t ProdName1; /*!< Product Name part1 */
+ __IO uint8_t ProdName2; /*!< Product Name part2 */
+ __IO uint8_t ProdRev; /*!< Product Revision */
+ __IO uint32_t ProdSN; /*!< Product Serial Number */
+ __IO uint8_t Reserved1; /*!< Reserved1 */
+ __IO uint16_t ManufactDate; /*!< Manufacturing Date */
+ __IO uint8_t CID_CRC; /*!< CID CRC */
+ __IO uint8_t Reserved2; /*!< Always 1 */
+
+} HAL_MMC_CardCIDTypeDef;
+/**
+ * @}
+ */
+
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+/** @defgroup MMC_Exported_Types_Group6 MMC Callback ID enumeration definition
+ * @{
+ */
+typedef enum
+{
+ HAL_MMC_TX_CPLT_CB_ID = 0x00U, /*!< MMC Tx Complete Callback ID */
+ HAL_MMC_RX_CPLT_CB_ID = 0x01U, /*!< MMC Rx Complete Callback ID */
+ HAL_MMC_ERROR_CB_ID = 0x02U, /*!< MMC Error Callback ID */
+ HAL_MMC_ABORT_CB_ID = 0x03U, /*!< MMC Abort Callback ID */
+ HAL_MMC_READ_DMA_LNKLST_BUF_CPLT_CB_ID = 0x04U, /*!< MMC DMA Rx Linked List Node buffer Callback ID */
+ HAL_MMC_WRITE_DMA_LNKLST_BUF_CPLT_CB_ID = 0x05U, /*!< MMC DMA Tx Linked List Node buffer Callback ID */
+
+ HAL_MMC_MSP_INIT_CB_ID = 0x10U, /*!< MMC MspInit Callback ID */
+ HAL_MMC_MSP_DEINIT_CB_ID = 0x11U /*!< MMC MspDeInit Callback ID */
+} HAL_MMC_CallbackIDTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Types_Group7 MMC Callback pointer definition
+ * @{
+ */
+typedef void (*pMMC_CallbackTypeDef)(MMC_HandleTypeDef *hmmc);
+/**
+ * @}
+ */
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup MMC_Exported_Constants Exported Constants
+ * @{
+ */
+
+#define MMC_BLOCKSIZE ((uint32_t)512U) /*!< Block size is 512 bytes */
+
+/** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition
+ * @{
+ */
+#define HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */
+#define HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */
+#define HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */
+#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */
+#define HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */
+#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */
+#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */
+#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */
+#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the */
+/*!< number of transferred bytes does not match the block length */
+#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */
+#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */
+#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */
+#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock */
+/*!< command or if there was an attempt to access a locked card */
+#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */
+#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */
+#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */
+#define HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */
+#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */
+#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */
+#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */
+#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */
+#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */
+#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */
+#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out */
+/*!< of erase sequence command was received */
+#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */
+#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */
+#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */
+#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */
+#define HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */
+#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */
+#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
+#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
+#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
+
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+#define HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Constansts_Group2 MMC context enumeration
+ * @{
+ */
+#define MMC_CONTEXT_NONE ((uint32_t)0x00000000U) /*!< None */
+#define MMC_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U) /*!< Read single block operation */
+#define MMC_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U) /*!< Read multiple blocks operation */
+#define MMC_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U) /*!< Write single block operation */
+#define MMC_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U) /*!< Write multiple blocks operation */
+#define MMC_CONTEXT_IT ((uint32_t)0x00000008U) /*!< Process in Interrupt mode */
+#define MMC_CONTEXT_DMA ((uint32_t)0x00000080U) /*!< Process in DMA mode */
+
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Constansts_Group3 MMC Voltage mode
+ * @{
+ */
+/**
+ * @brief
+ */
+#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< High voltage in byte mode */
+#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< Dual voltage in byte mode */
+#define MMC_LOW_VOLTAGE_RANGE 0x80000080U /*!< Low voltage in byte mode */
+#define EMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< High voltage in sector mode */
+#define EMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< Dual voltage in sector mode */
+#define EMMC_LOW_VOLTAGE_RANGE 0xC0000080U /*!< Low voltage in sector mode */
+#define MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Constansts_Group4 MMC Memory Cards
+ * @{
+ */
+#define MMC_LOW_CAPACITY_CARD ((uint32_t)0x00000000U) /*!< MMC Card Capacity <=2Gbytes */
+#define MMC_HIGH_CAPACITY_CARD ((uint32_t)0x00000001U) /*!< MMC Card Capacity >2Gbytes and <2Tbytes */
+
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Constansts_Group5 MMC Erase Type
+ * @{
+ */
+#define HAL_MMC_ERASE 0x00000000U /*!< Erase the erase groups identified by CMD35 & 36 */
+#define HAL_MMC_TRIM 0x00000001U /*!< Erase the write blocks identified by CMD35 & 36 */
+#define HAL_MMC_DISCARD 0x00000003U /*!< Discard the write blocks identified by CMD35 & 36 */
+#define HAL_MMC_SECURE_ERASE 0x80000000U /*!< Perform a secure purge according SRT on the erase groups identified by CMD35 & 36 */
+#define HAL_MMC_SECURE_TRIM_STEP1 0x80000001U /*!< Mark the write blocks identified by CMD35 & 36 for secure erase */
+#define HAL_MMC_SECURE_TRIM_STEP2 0x80008000U /*!< Perform a secure purge according SRT on the write blocks previously identified */
+
+#define IS_MMC_ERASE_TYPE(TYPE) (((TYPE) == HAL_MMC_ERASE) || \
+ ((TYPE) == HAL_MMC_TRIM) || \
+ ((TYPE) == HAL_MMC_DISCARD) || \
+ ((TYPE) == HAL_MMC_SECURE_ERASE) || \
+ ((TYPE) == HAL_MMC_SECURE_TRIM_STEP1) || \
+ ((TYPE) == HAL_MMC_SECURE_TRIM_STEP2))
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Constansts_Group6 MMC Secure Removal Type
+ * @{
+ */
+#define HAL_MMC_SRT_ERASE 0x00000001U /*!< Information removed by an erase */
+#define HAL_MMC_SRT_WRITE_CHAR_ERASE 0x00000002U /*!< Information removed by an overwriting with a character followed by an erase */
+#define HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM 0x00000004U /*!< Information removed by an overwriting with a character, its complement then a random character */
+#define HAL_MMC_SRT_VENDOR_DEFINED 0x00000008U /*!< Information removed using a vendor defined */
+
+
+#define IS_MMC_SRT_TYPE(TYPE) (((TYPE) == HAL_MMC_SRT_ERASE) || \
+ ((TYPE) == HAL_MMC_SRT_WRITE_CHAR_ERASE) || \
+ ((TYPE) == HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM) || \
+ ((TYPE) == HAL_MMC_SRT_VENDOR_DEFINED))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup MMC_Exported_macros MMC Exported Macros
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+/** @brief Reset MMC handle state.
+ * @param __HANDLE__ MMC Handle.
+ * @retval None
+ */
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_MMC_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MMC_STATE_RESET)
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+
+/**
+ * @brief Enable the MMC device interrupt.
+ * @param __HANDLE__ MMC Handle.
+ * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
+ * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
+ * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
+ * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
+ * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
+ * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+ * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
+ * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
+ * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
+ * @retval None
+ */
+#define __HAL_MMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+ * @brief Disable the MMC device interrupt.
+ * @param __HANDLE__ MMC Handle.
+ * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
+ * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
+ * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
+ * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
+ * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
+ * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+ * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
+ * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
+ * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
+ * @retval None
+ */
+#define __HAL_MMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified MMC flag is set or not.
+ * @param __HANDLE__ MMC Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
+ * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+ * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
+ * @arg SDMMC_FLAG_DTIMEOUT: Data timeout
+ * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
+ * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
+ * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
+ * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
+ * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
+ * @arg SDMMC_FLAG_DHOLD: Data transfer Hold
+ * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
+ * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
+ * @arg SDMMC_FLAG_DPSMACT: Data path state machine active
+ * @arg SDMMC_FLAG_CPSMACT: Command path state machine active
+ * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
+ * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
+ * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full
+ * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full
+ * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty
+ * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty
+ * @arg SDMMC_FLAG_BUSYD0: Inverted value of SDMMC_D0 line (Busy)
+ * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected
+ * @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received
+ * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received
+ * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
+ * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion
+ * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure
+ * @arg SDMMC_FLAG_IDMATE: IDMA transfer error
+ * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete
+ * @retval The new state of MMC FLAG (SET or RESET).
+ */
+#define __HAL_MMC_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
+
+/**
+ * @brief Clear the MMC's pending flags.
+ * @param __HANDLE__ MMC Handle.
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
+ * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+ * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
+ * @arg SDMMC_FLAG_DTIMEOUT: Data timeout
+ * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
+ * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
+ * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
+ * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
+ * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
+ * @arg SDMMC_FLAG_DHOLD: Data transfer Hold
+ * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
+ * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
+ * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected
+ * @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received
+ * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received
+ * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
+ * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion
+ * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure
+ * @arg SDMMC_FLAG_IDMATE: IDMA transfer error
+ * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete
+ * @retval None
+ */
+#define __HAL_MMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
+
+/**
+ * @brief Check whether the specified MMC interrupt has occurred or not.
+ * @param __HANDLE__ MMC Handle.
+ * @param __INTERRUPT__ specifies the SDMMC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
+ * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
+ * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
+ * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
+ * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
+ * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+ * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
+ * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
+ * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
+ * @retval The new state of MMC IT (SET or RESET).
+ */
+#define __HAL_MMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+ * @brief Clear the MMC's interrupt pending bits.
+ * @param __HANDLE__ MMC Handle.
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
+ * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
+ * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
+ * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
+ * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
+ * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+ * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
+ * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
+ * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
+ * @retval None
+ */
+#define __HAL_MMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+ * @}
+ */
+
+/* Include MMC HAL Extension module */
+#include "stm32u5xx_hal_mmc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup MMC_Exported_Functions MMC Exported Functions
+ * @{
+ */
+
+/** @defgroup MMC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc);
+HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc);
+HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc);
+void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc);
+void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc);
+
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks, uint32_t Timeout);
+HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks, uint32_t Timeout);
+HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
+/* Non-Blocking mode: IT */
+HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks);
+
+void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc);
+
+/* Callback in non blocking modes (DMA) */
+void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc);
+void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc);
+void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc);
+void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc);
+
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+/* MMC callback registering/unregistering */
+HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId,
+ pMMC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId);
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode);
+HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint32_t SpeedMode);
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Functions_Group4 MMC card related functions
+ * @{
+ */
+HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc);
+HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID);
+HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD);
+HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo);
+HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtCSD, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Functions_Group5 Peripheral State and Errors functions
+ * @{
+ */
+HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc);
+uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc);
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Functions_Group6 Peripheral Abort management
+ * @{
+ */
+HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc);
+HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc);
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Functions_Group7 Peripheral Erase management
+ * @{
+ */
+HAL_StatusTypeDef HAL_MMC_EraseSequence(MMC_HandleTypeDef *hmmc, uint32_t EraseType, uint32_t BlockStartAdd,
+ uint32_t BlockEndAdd);
+HAL_StatusTypeDef HAL_MMC_Sanitize(MMC_HandleTypeDef *hmmc);
+HAL_StatusTypeDef HAL_MMC_ConfigSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t SRTMode);
+HAL_StatusTypeDef HAL_MMC_GetSupportedSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t *SupportedSRT);
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup MMC_Private_Types MMC Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup MMC_Private_Defines MMC Private Defines
+ * @{
+ */
+#define MMC_EXT_CSD_DATA_SEC_SIZE_INDEX 61
+#define MMC_EXT_CSD_DATA_SEC_SIZE_POS 8
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup MMC_Private_Variables MMC Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup MMC_Private_Constants MMC Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup MMC_Private_Macros MMC Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup MMC_Private_Functions_Prototypes MMC Private Functions Prototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup MMC_Private_Functions MMC Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32U5xx_HAL_MMC_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_mmc_ex.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_mmc_ex.h
new file mode 100644
index 00000000..eb8fd77a
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_mmc_ex.h
@@ -0,0 +1,121 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_mmc_ex.h
+ * @author MCD Application Team
+ * @brief Header file of SD HAL extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_MMC_EX_H
+#define STM32U5xx_HAL_MMC_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup MMCEx
+ * @brief SD HAL extended module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup MMCEx_Exported_Types MMCEx Exported Types
+ * @{
+ */
+
+/** @defgroup MMCEx_Exported_Types_Group1 Linked List Wrapper
+ * @{
+ */
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* -----------------Linked List Wrapper --------------------------------------*/
+
+#define MMC_DMALinkNodeTypeDef SDMMC_DMALinkNodeTypeDef
+#define MMC_DMALinkNodeConfTypeDef SDMMC_DMALinkNodeConfTypeDef
+#define MMC_DMALinkedListTypeDef SDMMC_DMALinkedListTypeDef
+/* ----------------- Linked Aliases ------------------------------------------*/
+#define HAL_MMCx_DMALinkedList_WriteCpltCallback HAL_MMC_TxCpltCallback
+#define HAL_MMCx_DMALinkedList_ReadCpltCallback HAL_MMC_RxCpltCallback
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup MMCEx_Exported_Functions MMCEx Exported Functions
+ * @{
+ */
+
+/** @defgroup MMCEx_Exported_Functions_Group1 MultiBuffer functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_ReadBlocks(MMC_HandleTypeDef *hmmc, SDMMC_DMALinkedListTypeDef *pLinkedList,
+ uint32_t BlockAdd, uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_WriteBlocks(MMC_HandleTypeDef *hmmc, SDMMC_DMALinkedListTypeDef *pLinkedList,
+ uint32_t BlockAdd, uint32_t NumberOfBlocks);
+
+HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_BuildNode(MMC_DMALinkNodeTypeDef *pNode,
+ MMC_DMALinkNodeConfTypeDef *pNodeConf);
+HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_InsertNode(MMC_DMALinkedListTypeDef *pLinkedList,
+ MMC_DMALinkNodeTypeDef *pPrevNode,
+ MMC_DMALinkNodeTypeDef *pNewNode);
+HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_RemoveNode(MMC_DMALinkedListTypeDef *pLinkedList,
+ MMC_DMALinkNodeTypeDef *pNode);
+HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_LockNode(MMC_DMALinkNodeTypeDef *pNode);
+HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_UnlockNode(MMC_DMALinkNodeTypeDef *pNode);
+HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_EnableCircularMode(SDMMC_DMALinkedListTypeDef *pLinkedList);
+HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_DisableCircularMode(SDMMC_DMALinkedListTypeDef *pLinkedList);
+
+void HAL_MMCEx_Read_DMALnkLstBufCpltCallback(MMC_HandleTypeDef *hmmc);
+void HAL_MMCEx_Write_DMALnkLstBufCpltCallback(MMC_HandleTypeDef *hmmc);
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions prototypes ----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32U5xx_HAL_MMCEx_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_nand.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_nand.h
new file mode 100644
index 00000000..a36c6dd0
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_nand.h
@@ -0,0 +1,378 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_nand.h
+ * @author MCD Application Team
+ * @brief Header file of NAND HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_NAND_H
+#define STM32U5xx_HAL_NAND_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_ll_fmc.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup NAND
+ * @{
+ */
+
+/* Exported typedef ----------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup NAND_Exported_Types NAND Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL NAND State structures definition
+ */
+typedef enum
+{
+ HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */
+ HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */
+ HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */
+ HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */
+} HAL_NAND_StateTypeDef;
+
+/**
+ * @brief NAND Memory electronic signature Structure definition
+ */
+typedef struct
+{
+ /*State = HAL_NAND_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
+#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup NAND_Exported_Functions NAND Exported Functions
+ * @{
+ */
+
+/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions ********************************/
+HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing,
+ FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
+HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
+
+HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
+
+HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
+
+void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
+void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
+void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
+void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
+
+/**
+ * @}
+ */
+
+/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
+ * @{
+ */
+
+/* IO operation functions ****************************************************/
+HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
+
+HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
+ uint32_t NumPageToRead);
+HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
+ uint32_t NumPageToWrite);
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+ uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+ uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
+
+HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
+ uint32_t NumPageToRead);
+HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
+ uint32_t NumPageToWrite);
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+ uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+ uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
+
+HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
+
+uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
+
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+/* NAND callback registering/unregistering */
+HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId,
+ pNAND_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId);
+#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+
+/* NAND Control functions ****************************************************/
+HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
+HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
+HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
+
+/**
+ * @}
+ */
+
+/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
+/* NAND State functions *******************************************************/
+HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
+uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup NAND_Private_Constants NAND Private Constants
+ * @{
+ */
+#define NAND_DEVICE 0x80000000UL
+#define NAND_WRITE_TIMEOUT 0x01000000UL
+
+#define CMD_AREA (1UL<<16U) /* A16 = CLE high */
+#define ADDR_AREA (1UL<<17U) /* A17 = ALE high */
+
+#define NAND_CMD_AREA_A ((uint8_t)0x00)
+#define NAND_CMD_AREA_B ((uint8_t)0x01)
+#define NAND_CMD_AREA_C ((uint8_t)0x50)
+#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
+
+#define NAND_CMD_WRITE0 ((uint8_t)0x80)
+#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
+#define NAND_CMD_ERASE0 ((uint8_t)0x60)
+#define NAND_CMD_ERASE1 ((uint8_t)0xD0)
+#define NAND_CMD_READID ((uint8_t)0x90)
+#define NAND_CMD_STATUS ((uint8_t)0x70)
+#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
+#define NAND_CMD_RESET ((uint8_t)0xFF)
+
+/* NAND memory status */
+#define NAND_VALID_ADDRESS 0x00000100UL
+#define NAND_INVALID_ADDRESS 0x00000200UL
+#define NAND_TIMEOUT_ERROR 0x00000400UL
+#define NAND_BUSY 0x00000000UL
+#define NAND_ERROR 0x00000001UL
+#define NAND_READY 0x00000040UL
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup NAND_Private_Macros NAND Private Macros
+ * @{
+ */
+
+/**
+ * @brief NAND memory address computation.
+ * @param __ADDRESS__ NAND memory address.
+ * @param __HANDLE__ NAND handle.
+ * @retval NAND Raw address value
+ */
+#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
+ (((__ADDRESS__)->Block + \
+ (((__ADDRESS__)->Plane) * \
+ ((__HANDLE__)->Config.PlaneSize))) * \
+ ((__HANDLE__)->Config.BlockSize)))
+
+/**
+ * @brief NAND memory Column address computation.
+ * @param __HANDLE__ NAND handle.
+ * @retval NAND Raw address value
+ */
+#define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
+
+/**
+ * @brief NAND memory address cycling.
+ * @param __ADDRESS__ NAND memory address.
+ * @retval NAND address cycling value.
+ */
+#define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
+#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
+#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
+#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
+
+/**
+ * @brief NAND memory Columns cycling.
+ * @param __ADDRESS__ NAND memory address.
+ * @retval NAND Column address cycling value.
+ */
+#define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) & 0xFFU) /* 1st Column addressing cycle */
+#define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_NAND_H */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_nor.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_nor.h
new file mode 100644
index 00000000..ee1e563f
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_nor.h
@@ -0,0 +1,325 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_nor.h
+ * @author MCD Application Team
+ * @brief Header file of NOR HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_NOR_H
+#define STM32U5xx_HAL_NOR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_ll_fmc.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup NOR
+ * @{
+ */
+
+/* Exported typedef ----------------------------------------------------------*/
+/** @defgroup NOR_Exported_Types NOR Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL SRAM State structures definition
+ */
+typedef enum
+{
+ HAL_NOR_STATE_RESET = 0x00U, /*!< NOR not yet initialized or disabled */
+ HAL_NOR_STATE_READY = 0x01U, /*!< NOR initialized and ready for use */
+ HAL_NOR_STATE_BUSY = 0x02U, /*!< NOR internal processing is ongoing */
+ HAL_NOR_STATE_ERROR = 0x03U, /*!< NOR error state */
+ HAL_NOR_STATE_PROTECTED = 0x04U /*!< NOR NORSRAM device write protected */
+} HAL_NOR_StateTypeDef;
+
+/**
+ * @brief FMC NOR Status typedef
+ */
+typedef enum
+{
+ HAL_NOR_STATUS_SUCCESS = 0U,
+ HAL_NOR_STATUS_ONGOING,
+ HAL_NOR_STATUS_ERROR,
+ HAL_NOR_STATUS_TIMEOUT
+} HAL_NOR_StatusTypeDef;
+
+/**
+ * @brief FMC NOR ID typedef
+ */
+typedef struct
+{
+ uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */
+
+ uint16_t Device_Code1;
+
+ uint16_t Device_Code2;
+
+ uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory.
+ These codes can be accessed by performing read operations with specific
+ control signals and addresses set.They can also be accessed by issuing
+ an Auto Select command */
+} NOR_IDTypeDef;
+
+/**
+ * @brief FMC NOR CFI typedef
+ */
+typedef struct
+{
+ /*!< Defines the information stored in the memory's Common flash interface
+ which contains a description of various electrical and timing parameters,
+ density information and functions supported by the memory */
+
+ uint16_t CFI_1;
+
+ uint16_t CFI_2;
+
+ uint16_t CFI_3;
+
+ uint16_t CFI_4;
+} NOR_CFITypeDef;
+
+/**
+ * @brief NOR handle Structure definition
+ */
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+typedef struct __NOR_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
+
+{
+ FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
+
+ FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
+
+ FMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */
+
+ HAL_LockTypeDef Lock; /*!< NOR locking object */
+
+ __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
+
+ uint32_t CommandSet; /*!< NOR algorithm command set and control */
+
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+ void (* MspInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp Init callback */
+ void (* MspDeInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp DeInit callback */
+#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
+} NOR_HandleTypeDef;
+
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL NOR Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_NOR_MSP_INIT_CB_ID = 0x00U, /*!< NOR MspInit Callback ID */
+ HAL_NOR_MSP_DEINIT_CB_ID = 0x01U /*!< NOR MspDeInit Callback ID */
+} HAL_NOR_CallbackIDTypeDef;
+
+/**
+ * @brief HAL NOR Callback pointer definition
+ */
+typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor);
+#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup NOR_Exported_Macros NOR Exported Macros
+ * @{
+ */
+/** @brief Reset NOR handle state
+ * @param __HANDLE__ specifies the NOR handle.
+ * @retval None
+ */
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_NOR_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
+#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup NOR_Exported_Functions NOR Exported Functions
+ * @{
+ */
+
+/** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions ********************************/
+HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing,
+ FMC_NORSRAM_TimingTypeDef *ExtTiming);
+HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
+void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
+void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
+void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions
+ * @{
+ */
+
+/* I/O operation functions ***************************************************/
+HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
+HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
+HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
+HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
+
+HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
+ uint32_t uwBufferSize);
+HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
+ uint32_t uwBufferSize);
+
+HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
+HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
+HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
+
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+/* NOR callback registering/unregistering */
+HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId,
+ pNOR_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId);
+#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions
+ * @{
+ */
+
+/* NOR Control functions *****************************************************/
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
+/**
+ * @}
+ */
+
+/** @addtogroup NOR_Exported_Functions_Group4 NOR State functions
+ * @{
+ */
+
+/* NOR State functions ********************************************************/
+HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
+HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup NOR_Private_Constants NOR Private Constants
+ * @{
+ */
+/* NOR device IDs addresses */
+#define MC_ADDRESS ((uint16_t)0x0000)
+#define DEVICE_CODE1_ADDR ((uint16_t)0x0001)
+#define DEVICE_CODE2_ADDR ((uint16_t)0x000E)
+#define DEVICE_CODE3_ADDR ((uint16_t)0x000F)
+
+/* NOR CFI IDs addresses */
+#define CFI1_ADDRESS ((uint16_t)0x0061)
+#define CFI2_ADDRESS ((uint16_t)0x0062)
+#define CFI3_ADDRESS ((uint16_t)0x0063)
+#define CFI4_ADDRESS ((uint16_t)0x0064)
+
+/* NOR operation wait timeout */
+#define NOR_TMEOUT ((uint16_t)0xFFFF)
+
+/* NOR memory data width */
+#define NOR_MEMORY_8B ((uint8_t)0x00)
+#define NOR_MEMORY_16B ((uint8_t)0x01)
+
+/* NOR memory device read/write start address */
+#define NOR_MEMORY_ADRESS1 (0x60000000U)
+#define NOR_MEMORY_ADRESS2 (0x64000000U)
+#define NOR_MEMORY_ADRESS3 (0x68000000U)
+#define NOR_MEMORY_ADRESS4 (0x6C000000U)
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup NOR_Private_Macros NOR Private Macros
+ * @{
+ */
+/**
+ * @brief NOR memory address shifting.
+ * @param __NOR_ADDRESS NOR base address
+ * @param __NOR_MEMORY_WIDTH_ NOR memory width
+ * @param __ADDRESS__ NOR memory address
+ * @retval NOR shifted address value
+ */
+#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \
+ ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \
+ ((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))): \
+ ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
+
+/**
+ * @brief NOR memory write data to specified address.
+ * @param __ADDRESS__ NOR memory address
+ * @param __DATA__ Data to write
+ * @retval None
+ */
+#define NOR_WRITE(__ADDRESS__, __DATA__) do{ \
+ (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \
+ __DSB(); \
+ } while(0)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_NOR_H */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_opamp.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_opamp.h
new file mode 100644
index 00000000..abca37a1
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_opamp.h
@@ -0,0 +1,438 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_opamp.h
+ * @author MCD Application Team
+ * @brief Header file of OPAMP HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_OPAMP_H
+#define STM32U5xx_HAL_OPAMP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup OPAMP
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup OPAMP_Exported_Types OPAMP Exported Types
+ * @{
+ */
+
+/**
+ * @brief OPAMP Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t PowerSupplyRange; /*!< Specifies the power supply range: above or under 2.4V.
+ This parameter is not used, but kept for compatibility with other families.
+ Caution: Whatever this parameter, the effective PowerSupplyRange is
+ forced to OPAMP_POWERSUPPLY_HIGH in HAL_OPAMP_Init.
+ This parameter applies to the both OPAMP instances. */
+
+ uint32_t PowerMode; /*!< Specifies the power mode Normal or Low-Power and the speed mode Normal or High.
+ This parameter must be a value of @ref OPAMP_PowerMode */
+
+ uint32_t Mode; /*!< Specifies the OPAMP mode (Standalone, Follower or PGA)
+ This parameter must be a value of @ref OPAMP_Mode */
+
+ uint32_t InvertingInput; /*!< Specifies the inverting input in Standalone & PGA modes.
+ In Follower mode this parameter is Not Applicable.
+ This parameter must be a value of @ref OPAMP_InvertingInput */
+
+ uint32_t NonInvertingInput; /*!< Specifies the non inverting input of the opamp.
+ This parameter must be a value of @ref OPAMP_NonInvertingInput */
+
+ uint32_t PgaGain; /*!< Specifies the gain (2, 4, 8 or 16 ) in PGA mode
+ i.e. when mode is OPAMP_PGA_MODE.
+ This parameter must be a value of @ref OPAMP_PgaGain */
+
+ uint32_t UserTrimming; /*!< Specifies the trimming mode is either factory or user trimming
+ This parameter must be a value of @ref OPAMP_UserTrimming.*/
+
+ uint32_t TrimmingValueP; /*!< Specifies the offset trimming value (PMOS)
+ i.e. when UserTrimming is OPAMP_TRIMMING_USER.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 31
+ 16 is typical default value */
+
+ uint32_t TrimmingValueN; /*!< Specifies the offset trimming value (NMOS)
+ i.e. when UserTrimming is OPAMP_TRIMMING_USER.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 31
+ 16 is typical default value */
+
+ uint32_t TrimmingValuePLowPower; /*!< Specifies the offset trimming value (PMOS) in lowpower mode
+ i.e. when UserTrimming is OPAMP_TRIMMING_USER.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 31
+ 16 is typical default value */
+
+ uint32_t TrimmingValueNLowPower; /*!< Specifies the offset trimming value (NMOS) in lowpower mode
+ i.e. when UserTrimming is OPAMP_TRIMMING_USER.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 31
+ 16 is typical default value */
+
+} OPAMP_InitTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+
+typedef enum
+{
+ HAL_OPAMP_STATE_RESET = 0x00000000, /*!< OPAMP is not yet Initialized */
+ HAL_OPAMP_STATE_READY = 0x00000001, /*!< OPAMP is initialized and ready for use */
+ HAL_OPAMP_STATE_CALIBBUSY = 0x00000002, /*!< OPAMP is enabled in auto calibration mode */
+ HAL_OPAMP_STATE_BUSY = 0x00000004, /*!< OPAMP is enabled and running in normal mode */
+ HAL_OPAMP_STATE_BUSYLOCKED = 0x00000005 /*!< OPAMP is locked. Only system reset allows reconfiguring the opamp */
+
+} HAL_OPAMP_StateTypeDef;
+
+/**
+ * @brief OPAMP Handle Structure definition
+ */
+#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
+typedef struct __OPAMP_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
+{
+ OPAMP_TypeDef *Instance; /*!< OPAMP instance's registers base address */
+ OPAMP_InitTypeDef Init; /*!< OPAMP required parameters */
+ HAL_StatusTypeDef Status; /*!< OPAMP peripheral status */
+ HAL_LockTypeDef Lock; /*!< Locking object */
+ __IO HAL_OPAMP_StateTypeDef State; /*!< OPAMP communication state */
+
+#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
+ void (* MspInitCallback)(struct __OPAMP_HandleTypeDef *hopamp);
+ void (* MspDeInitCallback)(struct __OPAMP_HandleTypeDef *hopamp);
+#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
+
+} OPAMP_HandleTypeDef;
+
+/**
+ * @brief HAl_OPAMP_TrimmingValueTypeDef definition
+ */
+
+typedef uint32_t HAL_OPAMP_TrimmingValueTypeDef;
+
+#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL OPAMP Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_OPAMP_MSP_INIT_CB_ID = 0x01U, /*!< OPAMP MspInit Callback ID */
+ HAL_OPAMP_MSP_DEINIT_CB_ID = 0x02U, /*!< OPAMP MspDeInit Callback ID */
+ HAL_OPAMP_ALL_CB_ID = 0x03U /*!< OPAMP All ID */
+
+} HAL_OPAMP_CallbackIDTypeDef;
+
+/**
+ * @brief HAL OPAMP Callback pointer definition
+ */
+typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp);
+#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup OPAMP_Exported_Constants OPAMP Exported Constants
+ * @{
+ */
+
+/** @defgroup OPAMP_Mode OPAMP Mode
+ * @{
+ */
+#define OPAMP_STANDALONE_MODE 0x00000000U /*!< standalone mode */
+#define OPAMP_PGA_MODE OPAMP_CSR_OPAMODE_1 /*!< PGA mode */
+#define OPAMP_FOLLOWER_MODE OPAMP_CSR_OPAMODE /*!< follower mode */
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_NonInvertingInput OPAMP Non Inverting Input
+ * @{
+ */
+
+#define OPAMP_NONINVERTINGINPUT_IO0 0x00000000U /*!< OPAMP non-inverting input connected to dedicated IO pin */
+#define OPAMP_NONINVERTINGINPUT_DAC_CH OPAMP_CSR_VP_SEL /*!< OPAMP non-inverting input connected internally to DAC channel */
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_InvertingInput OPAMP Inverting Input
+ * @{
+ */
+
+#define OPAMP_INVERTINGINPUT_IO0 0x00000000U /*!< OPAMP inverting input connected to dedicated IO pin low-leakage */
+#define OPAMP_INVERTINGINPUT_IO1 OPAMP_CSR_VM_SEL_0 /*!< OPAMP inverting input connected to alternative IO pin available on some device packages */
+#define OPAMP_INVERTINGINPUT_CONNECT_NO OPAMP_CSR_VM_SEL_1 /*!< OPAMP inverting input not connected externally (PGA mode only) */
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_PgaGain OPAMP Pga Gain
+ * @{
+ */
+
+#define OPAMP_PGA_GAIN_2 0x00000000U /*!< PGA gain = 2 */
+#define OPAMP_PGA_GAIN_4 OPAMP_CSR_PGA_GAIN_0 /*!< PGA gain = 4 */
+#define OPAMP_PGA_GAIN_8 OPAMP_CSR_PGA_GAIN_1 /*!< PGA gain = 8 */
+#define OPAMP_PGA_GAIN_16 (OPAMP_CSR_PGA_GAIN_0 | OPAMP_CSR_PGA_GAIN_1) /*!< PGA gain = 16 */
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_PowerMode OPAMP PowerMode
+ * @{
+ */
+#define OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED 0x00000000U /*!< OPAMP power mode normal speed normal */
+#define OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED OPAMP_CSR_HSM /*!< OPAMP power mode normal speed high */
+#define OPAMP_POWERMODE_LOWPOWER_NORMALSPEED OPAMP_CSR_OPALPM /*!< OPAMP power mode low-power speed normal */
+#define OPAMP_POWERMODE_LOWPOWER_HIGHSPEED (OPAMP_CSR_OPALPM | OPAMP_CSR_HSM) /*!< OPAMP power mode low-power speed high */
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_PowerSupplyRange OPAMP PowerSupplyRange
+ * @{
+ */
+#define OPAMP_POWERSUPPLY_LOW 0x00000000U /*!< Power supply range low (VDDA lower than 2.4V) */
+#define OPAMP_POWERSUPPLY_HIGH OPAMP_CSR_OPARANGE /*!< Power supply range high (VDDA higher than 2.4V) */
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_UserTrimming OPAMP User Trimming
+ * @{
+ */
+#define OPAMP_TRIMMING_FACTORY 0x00000000U /*!< Factory trimming */
+#define OPAMP_TRIMMING_USER OPAMP_CSR_USERTRIM /*!< User trimming */
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_FactoryTrimming OPAMP Factory Trimming
+ * @{
+ */
+#define OPAMP_FACTORYTRIMMING_DUMMY 0xFFFFFFFFU /*!< Dummy value if trimming value could not be retrieved */
+#define OPAMP_FACTORYTRIMMING_N 0U /*!< Offset trimming N */
+#define OPAMP_FACTORYTRIMMING_P 1U /*!< Offset trimming P */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup OPAMP_Private_Constants OPAMP Private Constants
+ * @brief OPAMP Private constants and defines
+ * @{
+ */
+
+/* NONINVERTING bit position in OTR & LPOTR */
+#define OPAMP_INPUT_NONINVERTING ((uint32_t) 8) /*!< Non inverting input */
+
+/* Offset trimming time: during calibration, minimum time needed between two */
+/* steps to have 1 mV accuracy. */
+/* Refer to datasheet, electrical characteristics: parameter tOFFTRIM Typ=1ms.*/
+/* Unit: ms. */
+#define OPAMP_TRIMMING_DELAY ((uint32_t) 1)
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup OPAMP_Exported_Macros OPAMP Exported Macros
+ * @{
+ */
+
+/** @brief Reset OPAMP handle state.
+ * @param __HANDLE__: OPAMP handle.
+ * @retval None
+ */
+#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
+#define __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_OPAMP_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OPAMP_STATE_RESET)
+#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
+
+
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+
+/** @defgroup OPAMP_Private_Macros OPAMP Private Macros
+ * @{
+ */
+
+#define IS_OPAMP_FUNCTIONAL_NORMALMODE(INPUT) (((INPUT) == OPAMP_STANDALONE_MODE) || \
+ ((INPUT) == OPAMP_PGA_MODE) || \
+ ((INPUT) == OPAMP_FOLLOWER_MODE))
+
+#define IS_OPAMP_INVERTING_INPUT_STANDALONE(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \
+ ((INPUT) == OPAMP_INVERTINGINPUT_IO1))
+
+
+#define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NONINVERTINGINPUT_IO0) || \
+ ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH))
+
+#define IS_OPAMP_INVERTING_INPUT_PGA(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \
+ ((INPUT) == OPAMP_INVERTINGINPUT_IO1) || \
+ ((INPUT) == OPAMP_INVERTINGINPUT_CONNECT_NO))
+
+#define IS_OPAMP_PGA_GAIN(GAIN) (((GAIN) == OPAMP_PGA_GAIN_2) || \
+ ((GAIN) == OPAMP_PGA_GAIN_4) || \
+ ((GAIN) == OPAMP_PGA_GAIN_8) || \
+ ((GAIN) == OPAMP_PGA_GAIN_16))
+
+#define IS_OPAMP_POWERMODE(POWERMODE) (((POWERMODE) == OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED) || \
+ ((POWERMODE) == OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED) || \
+ ((POWERMODE) == OPAMP_POWERMODE_LOWPOWER_NORMALSPEED) || \
+ ((POWERMODE) == OPAMP_POWERMODE_LOWPOWER_HIGHSPEED))
+
+#define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_TRIMMING_FACTORY) || \
+ ((TRIMMING) == OPAMP_TRIMMING_USER))
+
+
+#define IS_OPAMP_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 31U)
+
+#define IS_OPAMP_FACTORYTRIMMING(TRIMMING) (((TRIMMING) == OPAMP_FACTORYTRIMMING_N) || \
+ ((TRIMMING) == OPAMP_FACTORYTRIMMING_P))
+
+/**
+ * @}
+ */
+
+/* Include OPAMP HAL Extended module */
+#include "stm32u5xx_hal_opamp_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup OPAMP_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup OPAMP_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp);
+HAL_StatusTypeDef HAL_OPAMP_DeInit(OPAMP_HandleTypeDef *hopamp);
+void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef *hopamp);
+void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp);
+/**
+ * @}
+ */
+
+/** @addtogroup OPAMP_Exported_Functions_Group2
+ * @{
+ */
+
+/* I/O operation functions *****************************************************/
+HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp);
+HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp);
+HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp);
+
+/**
+ * @}
+ */
+
+/** @addtogroup OPAMP_Exported_Functions_Group3
+ * @{
+ */
+
+/* Peripheral Control functions ************************************************/
+HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp);
+HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset(OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset);
+
+/**
+ * @}
+ */
+
+/** @addtogroup OPAMP_Exported_Functions_Group4
+ * @{
+ */
+
+/* Peripheral State functions **************************************************/
+HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp);
+
+/**
+ * @}
+ */
+
+/** @addtogroup OPAMP_Exported_Functions_Group5
+ * @{
+ */
+
+/* Peripheral Callback functions **************************************************/
+#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_OPAMP_RegisterCallback(OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackID,
+ pOPAMP_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_OPAMP_UnRegisterCallback(OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_OPAMP_H */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_opamp_ex.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_opamp_ex.h
new file mode 100644
index 00000000..99947b3c
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_opamp_ex.h
@@ -0,0 +1,81 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_opamp_ex.h
+ * @author MCD Application Team
+ * @brief Header file of OPAMP HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_OPAMP_EX_H
+#define STM32U5xx_HAL_OPAMP_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup OPAMPEx
+ * @{
+ */
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup OPAMPEx_Exported_Functions OPAMPEx Exported Functions
+ * @{
+ */
+
+/* I/O operation functions *****************************************************/
+/** @addtogroup OPAMPEx_Exported_Functions_Group1 Extended Input and Output operation functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2);
+
+/**
+ * @}
+ */
+
+/* Peripheral Control functions ************************************************/
+/** @addtogroup OPAMPEx_Exported_Functions_Group2
+ * @{
+ */
+HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef *hopamp);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_OPAMP_EX_H */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_ospi.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_ospi.h
new file mode 100644
index 00000000..027c7cf9
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_ospi.h
@@ -0,0 +1,1097 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_ospi.h
+ * @author MCD Application Team
+ * @brief Header file of OSPI HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_OSPI_H
+#define STM32U5xx_HAL_OSPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+#include "stm32u5xx_ll_dlyb.h"
+
+#if defined(OCTOSPI) || defined(OCTOSPI1) || defined(OCTOSPI2)
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup OSPI
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup OSPI_Exported_Types OSPI Exported Types
+ * @{
+ */
+#define HAL_OSPI_DLYB_CfgTypeDef LL_DLYB_CfgTypeDef
+
+/**
+ * @brief OSPI Init structure definition
+ */
+typedef struct
+{
+ uint32_t FifoThreshold; /*!< This is the threshold used by the Peripheral to generate the interrupt
+ indicating that data are available in reception or free place
+ is available in transmission.
+ This parameter can be a value between 1 and 32 */
+ uint32_t DualQuad; /*!< It enables or not the dual-quad mode which allow to access up to
+ quad mode on two different devices to increase the throughput.
+ This parameter can be a value of @ref OSPI_DualQuad */
+ uint32_t MemoryType; /*!< It indicates the external device type connected to the OSPI.
+ This parameter can be a value of @ref OSPI_MemoryType */
+ uint32_t DeviceSize; /*!< It defines the size of the external device connected to the OSPI,
+ it corresponds to the number of address bits required to access
+ the external device.
+ This parameter can be a value between 1 and 32 */
+ uint32_t ChipSelectHighTime; /*!< It defines the minimum number of clocks which the chip select
+ must remain high between commands.
+ This parameter can be a value between 1 and 8 */
+ uint32_t FreeRunningClock; /*!< It enables or not the free running clock.
+ This parameter can be a value of @ref OSPI_FreeRunningClock */
+ uint32_t ClockMode; /*!< It indicates the level of clock when the chip select is released.
+ This parameter can be a value of @ref OSPI_ClockMode */
+ uint32_t WrapSize; /*!< It indicates the wrap-size corresponding the external device configuration.
+ This parameter can be a value of @ref OSPI_WrapSize */
+ uint32_t ClockPrescaler; /*!< It specifies the prescaler factor used for generating
+ the external clock based on the AHB clock.
+ This parameter can be a value between 1 and 256 */
+ uint32_t SampleShifting; /*!< It allows to delay to 1/2 cycle the data sampling in order
+ to take in account external signal delays.
+ This parameter can be a value of @ref OSPI_SampleShifting */
+ uint32_t DelayHoldQuarterCycle; /*!< It allows to hold to 1/4 cycle the data.
+ This parameter can be a value of @ref OSPI_DelayHoldQuarterCycle */
+ uint32_t ChipSelectBoundary; /*!< It enables the transaction boundary feature and
+ defines the boundary of bytes to release the chip select.
+ This parameter can be a value between 0 and 31 */
+ uint32_t DelayBlockBypass; /*!< It enables the delay block bypass, so the sampling is not affected
+ by the delay block.
+ This parameter can be a value of @ref OSPI_DelayBlockBypass */
+ uint32_t MaxTran; /*!< It enables the communication regulation feature. The chip select is
+ released every MaxTran+1 bytes when the other OctoSPI request the access
+ to the bus.
+ This parameter can be a value between 0 and 255 */
+ uint32_t Refresh; /*!< It enables the refresh rate feature. The chip select is released every
+ Refresh+1 clock cycles.
+ This parameter can be a value between 0 and 0xFFFFFFFF */
+} OSPI_InitTypeDef;
+
+/**
+ * @brief HAL OSPI Handle Structure definition
+ */
+#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
+typedef struct __OSPI_HandleTypeDef
+#else
+typedef struct
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
+{
+ OCTOSPI_TypeDef *Instance; /*!< OSPI registers base address */
+ OSPI_InitTypeDef Init; /*!< OSPI initialization parameters */
+ uint8_t *pBuffPtr; /*!< Address of the OSPI buffer for transfer */
+ __IO uint32_t XferSize; /*!< Number of data to transfer */
+ __IO uint32_t XferCount; /*!< Counter of data transferred */
+ DMA_HandleTypeDef *hdma; /*!< Handle of the DMA channel used for the transfer */
+ __IO uint32_t State; /*!< Internal state of the OSPI HAL driver */
+ __IO uint32_t ErrorCode; /*!< Error code in case of HAL driver internal error */
+ uint32_t Timeout; /*!< Timeout used for the OSPI external device access */
+#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
+ void (* ErrorCallback)(struct __OSPI_HandleTypeDef *hospi);
+ void (* AbortCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
+ void (* FifoThresholdCallback)(struct __OSPI_HandleTypeDef *hospi);
+ void (* CmdCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
+ void (* RxCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
+ void (* TxCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
+ void (* RxHalfCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
+ void (* TxHalfCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
+ void (* StatusMatchCallback)(struct __OSPI_HandleTypeDef *hospi);
+ void (* TimeOutCallback)(struct __OSPI_HandleTypeDef *hospi);
+
+ void (* MspInitCallback)(struct __OSPI_HandleTypeDef *hospi);
+ void (* MspDeInitCallback)(struct __OSPI_HandleTypeDef *hospi);
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
+} OSPI_HandleTypeDef;
+
+/**
+ * @brief HAL OSPI Regular Command Structure definition
+ */
+typedef struct
+{
+ uint32_t OperationType; /*!< It indicates if the configuration applies to the common registers or
+ to the registers for the write operation (these registers are only
+ used for memory-mapped mode).
+ This parameter can be a value of @ref OSPI_OperationType */
+ uint32_t FlashId; /*!< It indicates which external device is selected for this command (it
+ applies only if Dualquad is disabled in the initialization structure).
+ This parameter can be a value of @ref OSPI_FlashID */
+ uint32_t Instruction; /*!< It contains the instruction to be sent to the device.
+ This parameter can be a value between 0 and 0xFFFFFFFF */
+ uint32_t InstructionMode; /*!< It indicates the mode of the instruction.
+ This parameter can be a value of @ref OSPI_InstructionMode */
+ uint32_t InstructionSize; /*!< It indicates the size of the instruction.
+ This parameter can be a value of @ref OSPI_InstructionSize */
+ uint32_t InstructionDtrMode; /*!< It enables or not the DTR mode for the instruction phase.
+ This parameter can be a value of @ref OSPI_InstructionDtrMode */
+ uint32_t Address; /*!< It contains the address to be sent to the device.
+ This parameter can be a value between 0 and 0xFFFFFFFF */
+ uint32_t AddressMode; /*!< It indicates the mode of the address.
+ This parameter can be a value of @ref OSPI_AddressMode */
+ uint32_t AddressSize; /*!< It indicates the size of the address.
+ This parameter can be a value of @ref OSPI_AddressSize */
+ uint32_t AddressDtrMode; /*!< It enables or not the DTR mode for the address phase.
+ This parameter can be a value of @ref OSPI_AddressDtrMode */
+ uint32_t AlternateBytes; /*!< It contains the alternate bytes to be sent to the device.
+ This parameter can be a value between 0 and 0xFFFFFFFF */
+ uint32_t AlternateBytesMode; /*!< It indicates the mode of the alternate bytes.
+ This parameter can be a value of @ref OSPI_AlternateBytesMode */
+ uint32_t AlternateBytesSize; /*!< It indicates the size of the alternate bytes.
+ This parameter can be a value of @ref OSPI_AlternateBytesSize */
+ uint32_t AlternateBytesDtrMode; /*!< It enables or not the DTR mode for the alternate bytes phase.
+ This parameter can be a value of @ref OSPI_AlternateBytesDtrMode */
+ uint32_t DataMode; /*!< It indicates the mode of the data.
+ This parameter can be a value of @ref OSPI_DataMode */
+ uint32_t NbData; /*!< It indicates the number of data transferred with this command.
+ This field is only used for indirect mode.
+ This parameter can be a value between 1 and 0xFFFFFFFF */
+ uint32_t DataDtrMode; /*!< It enables or not the DTR mode for the data phase.
+ This parameter can be a value of @ref OSPI_DataDtrMode */
+ uint32_t DummyCycles; /*!< It indicates the number of dummy cycles inserted before data phase.
+ This parameter can be a value between 0 and 31 */
+ uint32_t DQSMode; /*!< It enables or not the data strobe management.
+ This parameter can be a value of @ref OSPI_DQSMode */
+ uint32_t SIOOMode; /*!< It enables or not the SIOO mode.
+ This parameter can be a value of @ref OSPI_SIOOMode */
+} OSPI_RegularCmdTypeDef;
+
+/**
+ * @brief HAL OSPI Hyperbus Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t RWRecoveryTime; /*!< It indicates the number of cycles for the device read write recovery time.
+ This parameter can be a value between 0 and 255 */
+ uint32_t AccessTime; /*!< It indicates the number of cycles for the device access time.
+ This parameter can be a value between 0 and 255 */
+ uint32_t WriteZeroLatency; /*!< It enables or not the latency for the write access.
+ This parameter can be a value of @ref OSPI_WriteZeroLatency */
+ uint32_t LatencyMode; /*!< It configures the latency mode.
+ This parameter can be a value of @ref OSPI_LatencyMode */
+} OSPI_HyperbusCfgTypeDef;
+
+/**
+ * @brief HAL OSPI Hyperbus Command Structure definition
+ */
+typedef struct
+{
+ uint32_t AddressSpace; /*!< It indicates the address space accessed by the command.
+ This parameter can be a value of @ref OSPI_AddressSpace */
+ uint32_t Address; /*!< It contains the address to be sent tot he device.
+ This parameter can be a value between 0 and 0xFFFFFFFF */
+ uint32_t AddressSize; /*!< It indicates the size of the address.
+ This parameter can be a value of @ref OSPI_AddressSize */
+ uint32_t NbData; /*!< It indicates the number of data transferred with this command.
+ This field is only used for indirect mode.
+ This parameter can be a value between 1 and 0xFFFFFFFF
+ In case of autopolling mode, this parameter can be any value between 1 and 4 */
+ uint32_t DQSMode; /*!< It enables or not the data strobe management.
+ This parameter can be a value of @ref OSPI_DQSMode */
+} OSPI_HyperbusCmdTypeDef;
+
+/**
+ * @brief HAL OSPI Auto Polling mode configuration structure definition
+ */
+typedef struct
+{
+ uint32_t Match; /*!< Specifies the value to be compared with the masked status register to get a match.
+ This parameter can be any value between 0 and 0xFFFFFFFF */
+ uint32_t Mask; /*!< Specifies the mask to be applied to the status bytes received.
+ This parameter can be any value between 0 and 0xFFFFFFFF */
+ uint32_t MatchMode; /*!< Specifies the method used for determining a match.
+ This parameter can be a value of @ref OSPI_MatchMode */
+ uint32_t AutomaticStop; /*!< Specifies if automatic polling is stopped after a match.
+ This parameter can be a value of @ref OSPI_AutomaticStop */
+ uint32_t Interval; /*!< Specifies the number of clock cycles between two read during automatic polling phases.
+ This parameter can be any value between 0 and 0xFFFF */
+} OSPI_AutoPollingTypeDef;
+
+/**
+ * @brief HAL OSPI Memory Mapped mode configuration structure definition
+ */
+typedef struct
+{
+ uint32_t TimeOutActivation; /*!< Specifies if the timeout counter is enabled to release the chip select.
+ This parameter can be a value of @ref OSPI_TimeOutActivation */
+ uint32_t TimeOutPeriod; /*!< Specifies the number of clock to wait when the FIFO is full before to release the chip select.
+ This parameter can be any value between 0 and 0xFFFF */
+} OSPI_MemoryMappedTypeDef;
+
+/**
+ * @brief HAL OSPI IO Manager Configuration structure definition
+ */
+typedef struct
+{
+ uint32_t ClkPort; /*!< It indicates which port of the OSPI IO Manager is used for the CLK pins.
+ This parameter can be a value between 1 and 8 */
+ uint32_t DQSPort; /*!< It indicates which port of the OSPI IO Manager is used for the DQS pin.
+ This parameter can be a value between 0 and 8, 0 means that signal not used */
+ uint32_t NCSPort; /*!< It indicates which port of the OSPI IO Manager is used for the NCS pin.
+ This parameter can be a value between 1 and 8 */
+ uint32_t IOLowPort; /*!< It indicates which port of the OSPI IO Manager is used for the IO[3:0] pins.
+ This parameter can be a value of @ref OSPIM_IOPort */
+ uint32_t IOHighPort; /*!< It indicates which port of the OSPI IO Manager is used for the IO[7:4] pins.
+ This parameter can be a value of @ref OSPIM_IOPort */
+ uint32_t Req2AckTime; /*!< It indicates the minimum switching duration (in number of clock cycles) expected
+ if some signals are multiplexed in the OSPI IO Manager with the other OSPI.
+ This parameter can be a value between 1 and 256 */
+} OSPIM_CfgTypeDef;
+
+#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
+/**
+ * @brief HAL OSPI Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_OSPI_ERROR_CB_ID = 0x00U, /*!< OSPI Error Callback ID */
+ HAL_OSPI_ABORT_CB_ID = 0x01U, /*!< OSPI Abort Callback ID */
+ HAL_OSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< OSPI FIFO Threshold Callback ID */
+ HAL_OSPI_CMD_CPLT_CB_ID = 0x03U, /*!< OSPI Command Complete Callback ID */
+ HAL_OSPI_RX_CPLT_CB_ID = 0x04U, /*!< OSPI Rx Complete Callback ID */
+ HAL_OSPI_TX_CPLT_CB_ID = 0x05U, /*!< OSPI Tx Complete Callback ID */
+ HAL_OSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< OSPI Rx Half Complete Callback ID */
+ HAL_OSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< OSPI Tx Half Complete Callback ID */
+ HAL_OSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< OSPI Status Match Callback ID */
+ HAL_OSPI_TIMEOUT_CB_ID = 0x09U, /*!< OSPI Timeout Callback ID */
+
+ HAL_OSPI_MSP_INIT_CB_ID = 0x0AU, /*!< OSPI MspInit Callback ID */
+ HAL_OSPI_MSP_DEINIT_CB_ID = 0x0BU /*!< OSPI MspDeInit Callback ID */
+} HAL_OSPI_CallbackIDTypeDef;
+
+/**
+ * @brief HAL OSPI Callback pointer definition
+ */
+typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi);
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup OSPI_Exported_Constants OSPI Exported Constants
+ * @{
+ */
+
+/** @defgroup OSPI_State OSPI State
+ * @{
+ */
+#define HAL_OSPI_STATE_RESET ((uint32_t)0x00000000U) /*!< Initial state */
+#define HAL_OSPI_STATE_HYPERBUS_INIT ((uint32_t)0x00000001U) /*!< Initialization done in hyperbus mode but timing configuration not done */
+#define HAL_OSPI_STATE_READY ((uint32_t)0x00000002U) /*!< Driver ready to be used */
+#define HAL_OSPI_STATE_CMD_CFG ((uint32_t)0x00000004U) /*!< Command (regular or hyperbus) configured, ready for an action */
+#define HAL_OSPI_STATE_READ_CMD_CFG ((uint32_t)0x00000014U) /*!< Read command configuration done, not the write command configuration */
+#define HAL_OSPI_STATE_WRITE_CMD_CFG ((uint32_t)0x00000024U) /*!< Write command configuration done, not the read command configuration */
+#define HAL_OSPI_STATE_BUSY_CMD ((uint32_t)0x00000008U) /*!< Command without data on-going */
+#define HAL_OSPI_STATE_BUSY_TX ((uint32_t)0x00000018U) /*!< Indirect Tx on-going */
+#define HAL_OSPI_STATE_BUSY_RX ((uint32_t)0x00000028U) /*!< Indirect Rx on-going */
+#define HAL_OSPI_STATE_BUSY_AUTO_POLLING ((uint32_t)0x00000048U) /*!< Auto-polling on-going */
+#define HAL_OSPI_STATE_BUSY_MEM_MAPPED ((uint32_t)0x00000088U) /*!< Memory-mapped on-going */
+#define HAL_OSPI_STATE_ABORT ((uint32_t)0x00000100U) /*!< Abort on-going */
+#define HAL_OSPI_STATE_ERROR ((uint32_t)0x00000200U) /*!< Blocking error, driver should be re-initialized */
+/**
+ * @}
+ */
+
+/** @defgroup OSPI_ErrorCode OSPI Error Code
+ * @{
+ */
+#define HAL_OSPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
+#define HAL_OSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */
+#define HAL_OSPI_ERROR_TRANSFER ((uint32_t)0x00000002U) /*!< Transfer error */
+#define HAL_OSPI_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */
+#define HAL_OSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /*!< Invalid parameters error */
+#define HAL_OSPI_ERROR_INVALID_SEQUENCE ((uint32_t)0x00000010U) /*!< Sequence of the state machine is incorrect */
+#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
+#define HAL_OSPI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid callback error */
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/
+/**
+ * @}
+ */
+
+/** @defgroup OSPI_DualQuad OSPI Dual-Quad
+ * @{
+ */
+#define HAL_OSPI_DUALQUAD_DISABLE ((uint32_t)0x00000000U) /*!< Dual-Quad mode disabled */
+#define HAL_OSPI_DUALQUAD_ENABLE ((uint32_t)OCTOSPI_CR_DQM) /*!< Dual-Quad mode enabled */
+/**
+ * @}
+ */
+
+/** @defgroup OSPI_MemoryType OSPI Memory Type
+ * @{
+ */
+#define HAL_OSPI_MEMTYPE_MICRON ((uint32_t)0x00000000U) /*!< Micron mode */
+#define HAL_OSPI_MEMTYPE_MACRONIX ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< Macronix mode */
+#define HAL_OSPI_MEMTYPE_APMEMORY ((uint32_t)OCTOSPI_DCR1_MTYP_1) /*!< AP Memory mode */
+#define HAL_OSPI_MEMTYPE_MACRONIX_RAM ((uint32_t)(OCTOSPI_DCR1_MTYP_1 | OCTOSPI_DCR1_MTYP_0)) /*!< Macronix RAM mode */
+#define HAL_OSPI_MEMTYPE_HYPERBUS ((uint32_t)OCTOSPI_DCR1_MTYP_2) /*!< Hyperbus mode */
+/**
+ * @}
+ */
+
+/** @defgroup OSPI_FreeRunningClock OSPI Free Running Clock
+ * @{
+ */
+#define HAL_OSPI_FREERUNCLK_DISABLE ((uint32_t)0x00000000U) /*!< CLK is not free running */
+#define HAL_OSPI_FREERUNCLK_ENABLE ((uint32_t)OCTOSPI_DCR1_FRCK) /*!< CLK is free running (always provided) */
+/**
+ * @}
+ */
+
+/** @defgroup OSPI_ClockMode OSPI Clock Mode
+ * @{
+ */
+#define HAL_OSPI_CLOCK_MODE_0 ((uint32_t)0x00000000U) /*!< CLK must stay low while nCS is high */
+#define HAL_OSPI_CLOCK_MODE_3 ((uint32_t)OCTOSPI_DCR1_CKMODE) /*!< CLK must stay high while nCS is high */
+/**
+ * @}
+ */
+
+/** @defgroup OSPI_WrapSize OSPI Wrap-Size
+ * @{
+ */
+#define HAL_OSPI_WRAP_NOT_SUPPORTED ((uint32_t)0x00000000U) /*!< wrapped reads are not supported by the memory */
+#define HAL_OSPI_WRAP_16_BYTES ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_1) /*!< external memory supports wrap size of 16 bytes */
+#define HAL_OSPI_WRAP_32_BYTES ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_1)) /*!< external memory supports wrap size of 32 bytes */
+#define HAL_OSPI_WRAP_64_BYTES ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_2) /*!< external memory supports wrap size of 64 bytes */
+#define HAL_OSPI_WRAP_128_BYTES ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_2)) /*!< external memory supports wrap size of 128 bytes */
+/**
+ * @}
+ */
+
+/** @defgroup OSPI_SampleShifting OSPI Sample Shifting
+ * @{
+ */
+#define HAL_OSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U) /*!< No shift */
+#define HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)OCTOSPI_TCR_SSHIFT) /*!< 1/2 cycle shift */
+/**
+ * @}
+ */
+
+/** @defgroup OSPI_DelayHoldQuarterCycle OSPI Delay Hold Quarter Cycle
+ * @{
+ */
+#define HAL_OSPI_DHQC_DISABLE ((uint32_t)0x00000000U) /*!< No Delay */
+#define HAL_OSPI_DHQC_ENABLE ((uint32_t)OCTOSPI_TCR_DHQC) /*!< Delay Hold 1/4 cycle */
+/**
+ * @}
+ */
+
+/** @defgroup OSPI_DelayBlockBypass OSPI Delay Block Bypaas
+ * @{
+ */
+#define HAL_OSPI_DELAY_BLOCK_USED ((uint32_t)0x00000000U) /*!< Sampling clock is delayed by the delay block */
+#define HAL_OSPI_DELAY_BLOCK_BYPASSED ((uint32_t)OCTOSPI_DCR1_DLYBYP) /*!< Delay block is bypassed */
+/**
+ * @}
+ */
+
+/** @defgroup OSPI_OperationType OSPI Operation Type
+ * @{
+ */
+#define HAL_OSPI_OPTYPE_COMMON_CFG ((uint32_t)0x00000000U) /*!< Common configuration (indirect or auto-polling mode) */
+#define HAL_OSPI_OPTYPE_READ_CFG ((uint32_t)0x00000001U) /*!< Read configuration (memory-mapped mode) */
+#define HAL_OSPI_OPTYPE_WRITE_CFG ((uint32_t)0x00000002U) /*!< Write configuration (memory-mapped mode) */
+#define HAL_OSPI_OPTYPE_WRAP_CFG ((uint32_t)0x00000003U) /*!< Wrap configuration (memory-mapped mode) */
+/**
+ * @}
+ */
+
+/** @defgroup OSPI_FlashID OSPI Flash Id
+ * @{
+ */
+#define HAL_OSPI_FLASH_ID_1 ((uint32_t)0x00000000U) /*!< FLASH 1 selected */
+#define HAL_OSPI_FLASH_ID_2 ((uint32_t)OCTOSPI_CR_FSEL) /*!< FLASH 2 selected */
+/**
+ * @}
+ */
+
+/** @defgroup OSPI_InstructionMode OSPI Instruction Mode
+ * @{
+ */
+#define HAL_OSPI_INSTRUCTION_NONE ((uint32_t)0x00000000U) /*!< No instruction */
+#define HAL_OSPI_INSTRUCTION_1_LINE ((uint32_t)OCTOSPI_CCR_IMODE_0) /*!< Instruction on a single line */
+#define HAL_OSPI_INSTRUCTION_2_LINES ((uint32_t)OCTOSPI_CCR_IMODE_1) /*!< Instruction on two lines */
+#define HAL_OSPI_INSTRUCTION_4_LINES ((uint32_t)(OCTOSPI_CCR_IMODE_0 | OCTOSPI_CCR_IMODE_1)) /*!< Instruction on four lines */
+#define HAL_OSPI_INSTRUCTION_8_LINES ((uint32_t)OCTOSPI_CCR_IMODE_2) /*!< Instruction on eight lines */
+/**
+ * @}
+ */
+
+/** @defgroup OSPI_InstructionSize OSPI Instruction Size
+ * @{
+ */
+#define HAL_OSPI_INSTRUCTION_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit instruction */
+#define HAL_OSPI_INSTRUCTION_16_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_0) /*!< 16-bit instruction */
+#define HAL_OSPI_INSTRUCTION_24_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_1) /*!< 24-bit instruction */
+#define HAL_OSPI_INSTRUCTION_32_BITS ((uint32_t)OCTOSPI_CCR_ISIZE) /*!< 32-bit instruction */
+/**
+ * @}
+ */
+
+/** @defgroup OSPI_InstructionDtrMode OSPI Instruction DTR Mode
+ * @{
+ */
+#define HAL_OSPI_INSTRUCTION_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for instruction phase */
+#define HAL_OSPI_INSTRUCTION_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_IDTR) /*!< DTR mode enabled for instruction phase */
+/**
+ * @}
+ */
+
+/** @defgroup OSPI_AddressMode OSPI Address Mode
+ * @{
+ */
+#define HAL_OSPI_ADDRESS_NONE ((uint32_t)0x00000000U) /*!< No address */
+#define HAL_OSPI_ADDRESS_1_LINE ((uint32_t)OCTOSPI_CCR_ADMODE_0) /*!< Address on a single line */
+#define HAL_OSPI_ADDRESS_2_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_1) /*!< Address on two lines */
+#define HAL_OSPI_ADDRESS_4_LINES ((uint32_t)(OCTOSPI_CCR_ADMODE_0 | OCTOSPI_CCR_ADMODE_1)) /*!< Address on four lines */
+#define HAL_OSPI_ADDRESS_8_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_2) /*!< Address on eight lines */
+/**
+ * @}
+ */
+
+/** @defgroup OSPI_AddressSize OSPI Address Size
+ * @{
+ */
+#define HAL_OSPI_ADDRESS_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit address */
+#define HAL_OSPI_ADDRESS_16_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_0) /*!< 16-bit address */
+#define HAL_OSPI_ADDRESS_24_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_1) /*!< 24-bit address */
+#define HAL_OSPI_ADDRESS_32_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE) /*!< 32-bit address */
+/**
+ * @}
+ */
+
+/** @defgroup OSPI_AddressDtrMode OSPI Address DTR Mode
+ * @{
+ */
+#define HAL_OSPI_ADDRESS_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for address phase */
+#define HAL_OSPI_ADDRESS_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ADDTR) /*!< DTR mode enabled for address phase */
+/**
+ * @}
+ */
+
+/** @defgroup OSPI_AlternateBytesMode OSPI Alternate Bytes Mode
+ * @{
+ */
+#define HAL_OSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000U) /*!< No alternate bytes */
+#define HAL_OSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)OCTOSPI_CCR_ABMODE_0) /*!< Alternate bytes on a single line */
+#define HAL_OSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_1) /*!< Alternate bytes on two lines */
+#define HAL_OSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)(OCTOSPI_CCR_ABMODE_0 | OCTOSPI_CCR_ABMODE_1)) /*!< Alternate bytes on four lines */
+#define HAL_OSPI_ALTERNATE_BYTES_8_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_2) /*!< Alternate bytes on eight lines */
+/**
+ * @}
+ */
+
+/** @defgroup OSPI_AlternateBytesSize OSPI Alternate Bytes Size
+ * @{
+ */
+#define HAL_OSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit alternate bytes */
+#define HAL_OSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_0) /*!< 16-bit alternate bytes */
+#define HAL_OSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_1) /*!< 24-bit alternate bytes */
+#define HAL_OSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE) /*!< 32-bit alternate bytes */
+/**
+ * @}
+ */
+
+/** @defgroup OSPI_AlternateBytesDtrMode OSPI Alternate Bytes DTR Mode
+ * @{
+ */
+#define HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for alternate bytes phase */
+#define HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ABDTR) /*!< DTR mode enabled for alternate bytes phase */
+/**
+ * @}
+ */
+
+/** @defgroup OSPI_DataMode OSPI Data Mode
+ * @{
+ */
+#define HAL_OSPI_DATA_NONE ((uint32_t)0x00000000U) /*!< No data */
+#define HAL_OSPI_DATA_1_LINE ((uint32_t)OCTOSPI_CCR_DMODE_0) /*!< Data on a single line */
+#define HAL_OSPI_DATA_2_LINES ((uint32_t)OCTOSPI_CCR_DMODE_1) /*!< Data on two lines */
+#define HAL_OSPI_DATA_4_LINES ((uint32_t)(OCTOSPI_CCR_DMODE_0 | OCTOSPI_CCR_DMODE_1)) /*!< Data on four lines */
+#define HAL_OSPI_DATA_8_LINES ((uint32_t)OCTOSPI_CCR_DMODE_2) /*!< Data on eight lines */
+/**
+ * @}
+ */
+
+/** @defgroup OSPI_DataDtrMode OSPI Data DTR Mode
+ * @{
+ */
+#define HAL_OSPI_DATA_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for data phase */
+#define HAL_OSPI_DATA_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_DDTR) /*!< DTR mode enabled for data phase */
+/**
+ * @}
+ */
+
+/** @defgroup OSPI_DQSMode OSPI DQS Mode
+ * @{
+ */
+#define HAL_OSPI_DQS_DISABLE ((uint32_t)0x00000000U) /*!< DQS disabled */
+#define HAL_OSPI_DQS_ENABLE ((uint32_t)OCTOSPI_CCR_DQSE) /*!< DQS enabled */
+/**
+ * @}
+ */
+
+/** @defgroup OSPI_SIOOMode OSPI SIOO Mode
+ * @{
+ */
+#define HAL_OSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000U) /*!< Send instruction on every transaction */
+#define HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)OCTOSPI_CCR_SIOO) /*!< Send instruction only for the first command */
+/**
+ * @}
+ */
+
+/** @defgroup OSPI_WriteZeroLatency OSPI Hyperbus Write Zero Latency Activation
+ * @{
+ */
+#define HAL_OSPI_LATENCY_ON_WRITE ((uint32_t)0x00000000U) /*!< Latency on write accesses */
+#define HAL_OSPI_NO_LATENCY_ON_WRITE ((uint32_t)OCTOSPI_HLCR_WZL) /*!< No latency on write accesses */
+/**
+ * @}
+ */
+
+/** @defgroup OSPI_LatencyMode OSPI Hyperbus Latency Mode
+ * @{
+ */
+#define HAL_OSPI_VARIABLE_LATENCY ((uint32_t)0x00000000U) /*!< Variable initial latency */
+#define HAL_OSPI_FIXED_LATENCY ((uint32_t)OCTOSPI_HLCR_LM) /*!< Fixed latency */
+/**
+ * @}
+ */
+
+/** @defgroup OSPI_AddressSpace OSPI Hyperbus Address Space
+ * @{
+ */
+#define HAL_OSPI_MEMORY_ADDRESS_SPACE ((uint32_t)0x00000000U) /*!< HyperBus memory mode */
+#define HAL_OSPI_REGISTER_ADDRESS_SPACE ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< HyperBus register mode */
+/**
+ * @}
+ */
+
+/** @defgroup OSPI_MatchMode OSPI Match Mode
+ * @{
+ */
+#define HAL_OSPI_MATCH_MODE_AND ((uint32_t)0x00000000U) /*!< AND match mode between unmasked bits */
+#define HAL_OSPI_MATCH_MODE_OR ((uint32_t)OCTOSPI_CR_PMM) /*!< OR match mode between unmasked bits */
+/**
+ * @}
+ */
+
+/** @defgroup OSPI_AutomaticStop OSPI Automatic Stop
+ * @{
+ */
+#define HAL_OSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000U) /*!< AutoPolling stops only with abort or OSPI disabling */
+#define HAL_OSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)OCTOSPI_CR_APMS) /*!< AutoPolling stops as soon as there is a match */
+/**
+ * @}
+ */
+
+/** @defgroup OSPI_TimeOutActivation OSPI Timeout Activation
+ * @{
+ */
+#define HAL_OSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000U) /*!< Timeout counter disabled, nCS remains active */
+#define HAL_OSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)OCTOSPI_CR_TCEN) /*!< Timeout counter enabled, nCS released when timeout expires */
+/**
+ * @}
+ */
+
+/** @defgroup OSPI_Flags OSPI Flags
+ * @{
+ */
+#define HAL_OSPI_FLAG_BUSY OCTOSPI_SR_BUSY /*!< Busy flag: operation is ongoing */
+#define HAL_OSPI_FLAG_TO OCTOSPI_SR_TOF /*!< Timeout flag: timeout occurs in memory-mapped mode */
+#define HAL_OSPI_FLAG_SM OCTOSPI_SR_SMF /*!< Status match flag: received data matches in autopolling mode */
+#define HAL_OSPI_FLAG_FT OCTOSPI_SR_FTF /*!< Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete */
+#define HAL_OSPI_FLAG_TC OCTOSPI_SR_TCF /*!< Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted */
+#define HAL_OSPI_FLAG_TE OCTOSPI_SR_TEF /*!< Transfer error flag: invalid address is being accessed */
+/**
+ * @}
+ */
+
+/** @defgroup OSPI_Interrupts OSPI Interrupts
+ * @{
+ */
+#define HAL_OSPI_IT_TO OCTOSPI_CR_TOIE /*!< Interrupt on the timeout flag */
+#define HAL_OSPI_IT_SM OCTOSPI_CR_SMIE /*!< Interrupt on the status match flag */
+#define HAL_OSPI_IT_FT OCTOSPI_CR_FTIE /*!< Interrupt on the fifo threshold flag */
+#define HAL_OSPI_IT_TC OCTOSPI_CR_TCIE /*!< Interrupt on the transfer complete flag */
+#define HAL_OSPI_IT_TE OCTOSPI_CR_TEIE /*!< Interrupt on the transfer error flag */
+/**
+ * @}
+ */
+
+/** @defgroup OSPI_Timeout_definition OSPI Timeout definition
+ * @{
+ */
+#define HAL_OSPI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000U) /* 5 s */
+/**
+ * @}
+ */
+
+/** @defgroup OSPIM_IOPort OSPI IO Manager IO Port
+ * @{
+ */
+#define HAL_OSPIM_IOPORT_NONE ((uint32_t)0x00000000U) /*!< IOs not used */
+#define HAL_OSPIM_IOPORT_1_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x1U)) /*!< Port 1 - IO[3:0] */
+#define HAL_OSPIM_IOPORT_1_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x1U)) /*!< Port 1 - IO[7:4] */
+#define HAL_OSPIM_IOPORT_2_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x2U)) /*!< Port 2 - IO[3:0] */
+#define HAL_OSPIM_IOPORT_2_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x2U)) /*!< Port 2 - IO[7:4] */
+#define HAL_OSPIM_IOPORT_3_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x3U)) /*!< Port 3 - IO[3:0] */
+#define HAL_OSPIM_IOPORT_3_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x3U)) /*!< Port 3 - IO[7:4] */
+#define HAL_OSPIM_IOPORT_4_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x4U)) /*!< Port 4 - IO[3:0] */
+#define HAL_OSPIM_IOPORT_4_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x4U)) /*!< Port 4 - IO[7:4] */
+#define HAL_OSPIM_IOPORT_5_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x5U)) /*!< Port 5 - IO[3:0] */
+#define HAL_OSPIM_IOPORT_5_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x5U)) /*!< Port 5 - IO[7:4] */
+#define HAL_OSPIM_IOPORT_6_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x6U)) /*!< Port 6 - IO[3:0] */
+#define HAL_OSPIM_IOPORT_6_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x6U)) /*!< Port 6 - IO[7:4] */
+#define HAL_OSPIM_IOPORT_7_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x7U)) /*!< Port 7 - IO[3:0] */
+#define HAL_OSPIM_IOPORT_7_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x7U)) /*!< Port 7 - IO[7:4] */
+#define HAL_OSPIM_IOPORT_8_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x8U)) /*!< Port 8 - IO[3:0] */
+#define HAL_OSPIM_IOPORT_8_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x8U)) /*!< Port 8 - IO[7:4] */
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup OSPI_Exported_Macros OSPI Exported Macros
+ * @{
+ */
+/** @brief Reset OSPI handle state.
+ * @param __HANDLE__ specifies the OSPI Handle.
+ * @retval None
+ */
+#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
+#define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_OSPI_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OSPI_STATE_RESET)
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
+
+/** @brief Enable the OSPI peripheral.
+ * @param __HANDLE__ specifies the OSPI Handle.
+ * @retval None
+ */
+#define __HAL_OSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN)
+
+/** @brief Disable the OSPI peripheral.
+ * @param __HANDLE__ specifies the OSPI Handle.
+ * @retval None
+ */
+#define __HAL_OSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN)
+
+/** @brief Enable the specified OSPI interrupt.
+ * @param __HANDLE__ specifies the OSPI Handle.
+ * @param __INTERRUPT__ specifies the OSPI interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt
+ * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt
+ * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt
+ * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt
+ * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt
+ * @retval None
+ */
+#define __HAL_OSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
+
+
+/** @brief Disable the specified OSPI interrupt.
+ * @param __HANDLE__ specifies the OSPI Handle.
+ * @param __INTERRUPT__ specifies the OSPI interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt
+ * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt
+ * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt
+ * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt
+ * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt
+ * @retval None
+ */
+#define __HAL_OSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
+
+/** @brief Check whether the specified OSPI interrupt source is enabled or not.
+ * @param __HANDLE__ specifies the OSPI Handle.
+ * @param __INTERRUPT__ specifies the OSPI interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt
+ * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt
+ * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt
+ * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt
+ * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_OSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR,(__INTERRUPT__)) \
+ == (__INTERRUPT__))
+
+/**
+ * @brief Check whether the selected OSPI flag is set or not.
+ * @param __HANDLE__ specifies the OSPI Handle.
+ * @param __FLAG__ specifies the OSPI flag to check.
+ * This parameter can be one of the following values:
+ * @arg HAL_OSPI_FLAG_BUSY: OSPI Busy flag
+ * @arg HAL_OSPI_FLAG_TO: OSPI Timeout flag
+ * @arg HAL_OSPI_FLAG_SM: OSPI Status match flag
+ * @arg HAL_OSPI_FLAG_FT: OSPI FIFO threshold flag
+ * @arg HAL_OSPI_FLAG_TC: OSPI Transfer complete flag
+ * @arg HAL_OSPI_FLAG_TE: OSPI Transfer error flag
+ * @retval None
+ */
+#define __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) \
+ != 0U) ? SET : RESET)
+
+/** @brief Clears the specified OSPI's flag status.
+ * @param __HANDLE__ specifies the OSPI Handle.
+ * @param __FLAG__ specifies the OSPI clear register flag that needs to be set
+ * This parameter can be one of the following values:
+ * @arg HAL_OSPI_FLAG_TO: OSPI Timeout flag
+ * @arg HAL_OSPI_FLAG_SM: OSPI Status match flag
+ * @arg HAL_OSPI_FLAG_TC: OSPI Transfer complete flag
+ * @arg HAL_OSPI_FLAG_TE: OSPI Transfer error flag
+ * @retval None
+ */
+#define __HAL_OSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup OSPI_Exported_Functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions ********************************/
+/** @addtogroup OSPI_Exported_Functions_Group1
+ * @{
+ */
+HAL_StatusTypeDef HAL_OSPI_Init(OSPI_HandleTypeDef *hospi);
+void HAL_OSPI_MspInit(OSPI_HandleTypeDef *hospi);
+HAL_StatusTypeDef HAL_OSPI_DeInit(OSPI_HandleTypeDef *hospi);
+void HAL_OSPI_MspDeInit(OSPI_HandleTypeDef *hospi);
+
+/**
+ * @}
+ */
+
+/* IO operation functions *****************************************************/
+/** @addtogroup OSPI_Exported_Functions_Group2
+ * @{
+ */
+/* OSPI IRQ handler function */
+void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi);
+
+/* OSPI command configuration functions */
+HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout);
+HAL_StatusTypeDef HAL_OSPI_Command_IT(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd);
+HAL_StatusTypeDef HAL_OSPI_HyperbusCfg(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout);
+HAL_StatusTypeDef HAL_OSPI_HyperbusCmd(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCmdTypeDef *cmd, uint32_t Timeout);
+
+/* OSPI indirect mode functions */
+HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_OSPI_Transmit_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData);
+HAL_StatusTypeDef HAL_OSPI_Receive_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData);
+HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData);
+HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData);
+
+/* OSPI status flag polling mode functions */
+HAL_StatusTypeDef HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
+HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg);
+
+/* OSPI memory-mapped mode functions */
+HAL_StatusTypeDef HAL_OSPI_MemoryMapped(OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg);
+
+/* Callback functions in non-blocking modes ***********************************/
+void HAL_OSPI_ErrorCallback(OSPI_HandleTypeDef *hospi);
+void HAL_OSPI_AbortCpltCallback(OSPI_HandleTypeDef *hospi);
+void HAL_OSPI_FifoThresholdCallback(OSPI_HandleTypeDef *hospi);
+
+/* OSPI indirect mode functions */
+void HAL_OSPI_CmdCpltCallback(OSPI_HandleTypeDef *hospi);
+void HAL_OSPI_RxCpltCallback(OSPI_HandleTypeDef *hospi);
+void HAL_OSPI_TxCpltCallback(OSPI_HandleTypeDef *hospi);
+void HAL_OSPI_RxHalfCpltCallback(OSPI_HandleTypeDef *hospi);
+void HAL_OSPI_TxHalfCpltCallback(OSPI_HandleTypeDef *hospi);
+
+/* OSPI status flag polling mode functions */
+void HAL_OSPI_StatusMatchCallback(OSPI_HandleTypeDef *hospi);
+
+/* OSPI memory-mapped mode functions */
+void HAL_OSPI_TimeOutCallback(OSPI_HandleTypeDef *hospi);
+
+#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
+/* OSPI callback registering/unregistering */
+HAL_StatusTypeDef HAL_OSPI_RegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID,
+ pOSPI_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID);
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
+/**
+ * @}
+ */
+
+/* Peripheral Control and State functions ************************************/
+/** @addtogroup OSPI_Exported_Functions_Group3
+ * @{
+ */
+HAL_StatusTypeDef HAL_OSPI_Abort(OSPI_HandleTypeDef *hospi);
+HAL_StatusTypeDef HAL_OSPI_Abort_IT(OSPI_HandleTypeDef *hospi);
+HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold(OSPI_HandleTypeDef *hospi, uint32_t Threshold);
+uint32_t HAL_OSPI_GetFifoThreshold(OSPI_HandleTypeDef *hospi);
+HAL_StatusTypeDef HAL_OSPI_SetTimeout(OSPI_HandleTypeDef *hospi, uint32_t Timeout);
+uint32_t HAL_OSPI_GetError(OSPI_HandleTypeDef *hospi);
+uint32_t HAL_OSPI_GetState(OSPI_HandleTypeDef *hospi);
+
+/**
+ * @}
+ */
+
+/* OSPI IO Manager configuration function ************************************/
+/** @addtogroup OSPI_Exported_Functions_Group4
+ * @{
+ */
+HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout);
+
+/**
+ * @}
+ */
+
+
+/* OSPI Delay Block function ************************************/
+/** @addtogroup OSPI_Exported_Functions_Group5 Delay Block function
+ * @{
+ */
+HAL_StatusTypeDef HAL_OSPI_DLYB_SetConfig(OSPI_HandleTypeDef *hospi, HAL_OSPI_DLYB_CfgTypeDef *pdlyb_cfg);
+HAL_StatusTypeDef HAL_OSPI_DLYB_GetConfig(OSPI_HandleTypeDef *hospi, HAL_OSPI_DLYB_CfgTypeDef *pdlyb_cfg);
+HAL_StatusTypeDef HAL_OSPI_DLYB_GetClockPeriod(OSPI_HandleTypeDef *hospi, HAL_OSPI_DLYB_CfgTypeDef *pdlyb_cfg);
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* End of exported functions -------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/**
+ @cond 0
+ */
+#define IS_OSPI_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) >= 1U) && ((THRESHOLD) <= 32U))
+
+#define IS_OSPI_DUALQUAD_MODE(MODE) (((MODE) == HAL_OSPI_DUALQUAD_DISABLE) || \
+ ((MODE) == HAL_OSPI_DUALQUAD_ENABLE))
+
+#define IS_OSPI_MEMORY_TYPE(TYPE) (((TYPE) == HAL_OSPI_MEMTYPE_MICRON) || \
+ ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX) || \
+ ((TYPE) == HAL_OSPI_MEMTYPE_APMEMORY) || \
+ ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX_RAM) || \
+ ((TYPE) == HAL_OSPI_MEMTYPE_HYPERBUS))
+
+#define IS_OSPI_DEVICE_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 32U))
+
+#define IS_OSPI_CS_HIGH_TIME(TIME) (((TIME) >= 1U) && ((TIME) <= 8U))
+
+#define IS_OSPI_FREE_RUN_CLK(CLK) (((CLK) == HAL_OSPI_FREERUNCLK_DISABLE) || \
+ ((CLK) == HAL_OSPI_FREERUNCLK_ENABLE))
+
+#define IS_OSPI_CLOCK_MODE(MODE) (((MODE) == HAL_OSPI_CLOCK_MODE_0) || \
+ ((MODE) == HAL_OSPI_CLOCK_MODE_3))
+
+#define IS_OSPI_WRAP_SIZE(SIZE) (((SIZE) == HAL_OSPI_WRAP_NOT_SUPPORTED) || \
+ ((SIZE) == HAL_OSPI_WRAP_16_BYTES) || \
+ ((SIZE) == HAL_OSPI_WRAP_32_BYTES) || \
+ ((SIZE) == HAL_OSPI_WRAP_64_BYTES) || \
+ ((SIZE) == HAL_OSPI_WRAP_128_BYTES))
+
+#define IS_OSPI_CLK_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 256U))
+
+#define IS_OSPI_SAMPLE_SHIFTING(CYCLE) (((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_NONE) || \
+ ((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE))
+
+#define IS_OSPI_DHQC(CYCLE) (((CYCLE) == HAL_OSPI_DHQC_DISABLE) || \
+ ((CYCLE) == HAL_OSPI_DHQC_ENABLE))
+
+#define IS_OSPI_OPERATION_TYPE(TYPE) (((TYPE) == HAL_OSPI_OPTYPE_COMMON_CFG) || \
+ ((TYPE) == HAL_OSPI_OPTYPE_READ_CFG) || \
+ ((TYPE) == HAL_OSPI_OPTYPE_WRITE_CFG) || \
+ ((TYPE) == HAL_OSPI_OPTYPE_WRAP_CFG))
+
+#define IS_OSPI_FLASH_ID(FLASHID) (((FLASHID) == HAL_OSPI_FLASH_ID_1) || \
+ ((FLASHID) == HAL_OSPI_FLASH_ID_2))
+
+#define IS_OSPI_INSTRUCTION_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_NONE) || \
+ ((MODE) == HAL_OSPI_INSTRUCTION_1_LINE) || \
+ ((MODE) == HAL_OSPI_INSTRUCTION_2_LINES) || \
+ ((MODE) == HAL_OSPI_INSTRUCTION_4_LINES) || \
+ ((MODE) == HAL_OSPI_INSTRUCTION_8_LINES))
+
+#define IS_OSPI_INSTRUCTION_SIZE(SIZE) (((SIZE) == HAL_OSPI_INSTRUCTION_8_BITS) || \
+ ((SIZE) == HAL_OSPI_INSTRUCTION_16_BITS) || \
+ ((SIZE) == HAL_OSPI_INSTRUCTION_24_BITS) || \
+ ((SIZE) == HAL_OSPI_INSTRUCTION_32_BITS))
+
+#define IS_OSPI_INSTRUCTION_DTR_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_DTR_DISABLE) || \
+ ((MODE) == HAL_OSPI_INSTRUCTION_DTR_ENABLE))
+
+#define IS_OSPI_ADDRESS_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_NONE) || \
+ ((MODE) == HAL_OSPI_ADDRESS_1_LINE) || \
+ ((MODE) == HAL_OSPI_ADDRESS_2_LINES) || \
+ ((MODE) == HAL_OSPI_ADDRESS_4_LINES) || \
+ ((MODE) == HAL_OSPI_ADDRESS_8_LINES))
+
+#define IS_OSPI_ADDRESS_SIZE(SIZE) (((SIZE) == HAL_OSPI_ADDRESS_8_BITS) || \
+ ((SIZE) == HAL_OSPI_ADDRESS_16_BITS) || \
+ ((SIZE) == HAL_OSPI_ADDRESS_24_BITS) || \
+ ((SIZE) == HAL_OSPI_ADDRESS_32_BITS))
+
+#define IS_OSPI_ADDRESS_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_DTR_DISABLE) || \
+ ((MODE) == HAL_OSPI_ADDRESS_DTR_ENABLE))
+
+#define IS_OSPI_ALT_BYTES_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_NONE) || \
+ ((MODE) == HAL_OSPI_ALTERNATE_BYTES_1_LINE) || \
+ ((MODE) == HAL_OSPI_ALTERNATE_BYTES_2_LINES) || \
+ ((MODE) == HAL_OSPI_ALTERNATE_BYTES_4_LINES) || \
+ ((MODE) == HAL_OSPI_ALTERNATE_BYTES_8_LINES))
+
+#define IS_OSPI_ALT_BYTES_SIZE(SIZE) (((SIZE) == HAL_OSPI_ALTERNATE_BYTES_8_BITS) || \
+ ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_16_BITS) || \
+ ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_24_BITS) || \
+ ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_32_BITS))
+
+#define IS_OSPI_ALT_BYTES_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE) || \
+ ((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE))
+
+#define IS_OSPI_DATA_MODE(MODE) (((MODE) == HAL_OSPI_DATA_NONE) || \
+ ((MODE) == HAL_OSPI_DATA_1_LINE) || \
+ ((MODE) == HAL_OSPI_DATA_2_LINES) || \
+ ((MODE) == HAL_OSPI_DATA_4_LINES) || \
+ ((MODE) == HAL_OSPI_DATA_8_LINES))
+
+#define IS_OSPI_NUMBER_DATA(NUMBER) ((NUMBER) >= 1U)
+
+#define IS_OSPI_DATA_DTR_MODE(MODE) (((MODE) == HAL_OSPI_DATA_DTR_DISABLE) || \
+ ((MODE) == HAL_OSPI_DATA_DTR_ENABLE))
+
+#define IS_OSPI_DUMMY_CYCLES(NUMBER) ((NUMBER) <= 31U)
+
+#define IS_OSPI_DQS_MODE(MODE) (((MODE) == HAL_OSPI_DQS_DISABLE) || \
+ ((MODE) == HAL_OSPI_DQS_ENABLE))
+
+#define IS_OSPI_SIOO_MODE(MODE) (((MODE) == HAL_OSPI_SIOO_INST_EVERY_CMD) || \
+ ((MODE) == HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD))
+
+#define IS_OSPI_RW_RECOVERY_TIME(NUMBER) ((NUMBER) <= 255U)
+
+#define IS_OSPI_ACCESS_TIME(NUMBER) ((NUMBER) <= 255U)
+
+#define IS_OSPI_WRITE_ZERO_LATENCY(MODE) (((MODE) == HAL_OSPI_LATENCY_ON_WRITE) || \
+ ((MODE) == HAL_OSPI_NO_LATENCY_ON_WRITE))
+
+#define IS_OSPI_LATENCY_MODE(MODE) (((MODE) == HAL_OSPI_VARIABLE_LATENCY) || \
+ ((MODE) == HAL_OSPI_FIXED_LATENCY))
+
+#define IS_OSPI_ADDRESS_SPACE(SPACE) (((SPACE) == HAL_OSPI_MEMORY_ADDRESS_SPACE) || \
+ ((SPACE) == HAL_OSPI_REGISTER_ADDRESS_SPACE))
+
+#define IS_OSPI_MATCH_MODE(MODE) (((MODE) == HAL_OSPI_MATCH_MODE_AND) || \
+ ((MODE) == HAL_OSPI_MATCH_MODE_OR))
+
+#define IS_OSPI_AUTOMATIC_STOP(MODE) (((MODE) == HAL_OSPI_AUTOMATIC_STOP_ENABLE) || \
+ ((MODE) == HAL_OSPI_AUTOMATIC_STOP_DISABLE))
+
+#define IS_OSPI_INTERVAL(INTERVAL) ((INTERVAL) <= 0xFFFFU)
+
+#define IS_OSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U))
+
+#define IS_OSPI_TIMEOUT_ACTIVATION(MODE) (((MODE) == HAL_OSPI_TIMEOUT_COUNTER_DISABLE) || \
+ ((MODE) == HAL_OSPI_TIMEOUT_COUNTER_ENABLE))
+
+#define IS_OSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU)
+
+#define IS_OSPI_CS_BOUNDARY(BOUNDARY) ((BOUNDARY) <= 31U)
+
+#define IS_OSPI_DLYBYP(MODE) (((MODE) == HAL_OSPI_DELAY_BLOCK_USED) || \
+ ((MODE) == HAL_OSPI_DELAY_BLOCK_BYPASSED))
+
+#define IS_OSPI_MAXTRAN(NB_BYTES) ((NB_BYTES) <= 255U)
+
+#define IS_OSPIM_PORT(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U))
+
+#define IS_OSPIM_DQS_PORT(NUMBER) ((NUMBER) <= 8U)
+
+#define IS_OSPIM_IO_PORT(PORT) (((PORT) == HAL_OSPIM_IOPORT_NONE) || \
+ ((PORT) == HAL_OSPIM_IOPORT_1_LOW) || \
+ ((PORT) == HAL_OSPIM_IOPORT_1_HIGH) || \
+ ((PORT) == HAL_OSPIM_IOPORT_2_LOW) || \
+ ((PORT) == HAL_OSPIM_IOPORT_2_HIGH) || \
+ ((PORT) == HAL_OSPIM_IOPORT_3_LOW) || \
+ ((PORT) == HAL_OSPIM_IOPORT_3_HIGH) || \
+ ((PORT) == HAL_OSPIM_IOPORT_4_LOW) || \
+ ((PORT) == HAL_OSPIM_IOPORT_4_HIGH) || \
+ ((PORT) == HAL_OSPIM_IOPORT_5_LOW) || \
+ ((PORT) == HAL_OSPIM_IOPORT_5_HIGH) || \
+ ((PORT) == HAL_OSPIM_IOPORT_6_LOW) || \
+ ((PORT) == HAL_OSPIM_IOPORT_6_HIGH) || \
+ ((PORT) == HAL_OSPIM_IOPORT_7_LOW) || \
+ ((PORT) == HAL_OSPIM_IOPORT_7_HIGH) || \
+ ((PORT) == HAL_OSPIM_IOPORT_8_LOW) || \
+ ((PORT) == HAL_OSPIM_IOPORT_8_HIGH))
+
+#if defined (OCTOSPIM_CR_MUXEN)
+#define IS_OSPIM_REQ2ACKTIME(TIME) (((TIME) >= 1U) && ((TIME) <= 256U))
+#endif /*(OCTOSPIM_CR_MUXEN)*/
+/**
+ @endcond
+ */
+
+/* End of private macros -----------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* OCTOSPI || OCTOSPI1 || OCTOSPI2 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_OSPI_H */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_otfdec.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_otfdec.h
new file mode 100644
index 00000000..495005cb
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_otfdec.h
@@ -0,0 +1,487 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_otfdec.h
+ * @author MCD Application Team
+ * @brief Header file of OTFDEC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_OTFDEC_H
+#define STM32U5xx_HAL_OTFDEC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+#if defined(OTFDEC1)
+
+/** @addtogroup OTFDEC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup OTFDEC_Exported_Types OTFDEC Exported Types
+ * @{
+ */
+
+/** @defgroup OTFDEC_Exported_Types_Group1 OTFDEC region configuration definitions
+ * @{
+ */
+
+/**
+ * @brief OTFDEC region configuration structure definition
+ */
+typedef struct
+{
+ uint32_t Nonce[2]; /*!< OTFDEC region nonce */
+
+ uint32_t StartAddress; /*!< OTFDEC region start address */
+
+ uint32_t EndAddress; /*!< OTFDEC region end address */
+
+ uint16_t Version; /*!< OTFDEC region firmware version */
+
+} OTFDEC_RegionConfigTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup OTFDEC_Exported_Types_Group2 OTFDEC Peripheral handle definitions
+ * @{
+ */
+
+/**
+ * @brief OTFDEC states structure definition
+ */
+typedef enum
+{
+ HAL_OTFDEC_STATE_RESET = 0x00U, /*!< OTFDEC not yet initialized or disabled */
+ HAL_OTFDEC_STATE_READY = 0x01U, /*!< OTFDEC initialized and ready for use */
+ HAL_OTFDEC_STATE_BUSY = 0x02U, /*!< OTFDEC internal processing is ongoing */
+} HAL_OTFDEC_StateTypeDef;
+
+/**
+ * @brief OTFDEC handle structure definition
+ */
+#if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)
+typedef struct __OTFDEC_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */
+{
+ OTFDEC_TypeDef *Instance; /*!< OTFDEC registers base address */
+
+ HAL_OTFDEC_StateTypeDef State; /*!< OTFDEC state */
+
+ HAL_LockTypeDef Lock; /*!< OTFDEC locking object */
+
+ __IO uint32_t ErrorCode; /*!< OTFDEC error code */
+
+#if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)
+ void (* ErrorCallback)(struct __OTFDEC_HandleTypeDef *hotfdec); /*!< OTFDEC error callback */
+
+ void (* MspInitCallback)(struct __OTFDEC_HandleTypeDef *hotfdec); /*!< OTFDEC Msp Init callback */
+
+ void (* MspDeInitCallback)(struct __OTFDEC_HandleTypeDef *hotfdec); /*!< OTFDEC Msp DeInit callback */
+#endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */
+
+} OTFDEC_HandleTypeDef;
+
+#if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL OTFDEC Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_OTFDEC_ERROR_CB_ID = 0x00U, /*!< OTFDEC error callback ID */
+ HAL_OTFDEC_MSPINIT_CB_ID = 0x01U, /*!< OTFDEC Msp DeInit callback ID */
+ HAL_OTFDEC_MSPDEINIT_CB_ID = 0x02U /*!< OTFDEC Msp DeInit callback ID */
+} HAL_OTFDEC_CallbackIDTypeDef;
+
+/**
+ * @brief HAL OTFDEC Callback pointer definition
+ */
+typedef void (*pOTFDEC_CallbackTypeDef)(OTFDEC_HandleTypeDef *hotfdec); /*!< pointer to a OTFDEC callback function */
+
+#endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup OTFDEC_Exported_Constants OTFDEC Exported Constants
+ * @{
+ */
+
+/** @defgroup OTFDEC_Interrupts OTFDEC Interrupts
+ * @{
+ */
+#define OTFDEC_SEC_ERROR_INT (OTFDEC_IER_SEIE ) /*!< OTFDEC security error interrupt */
+#define OTFDEC_EXE_ERROR_INT ( OTFDEC_IER_XONEIE ) /*!< OTFDEC execution error interrupt */
+#define OTFDEC_KEY_ERROR_INT ( OTFDEC_IER_KEIE) /*!< OTFDEC key error interrupt */
+#define OTFDEC_SEC_EXE_ERROR_INT (OTFDEC_IER_SEIE|OTFDEC_IER_XONEIE ) /*!< OTFDEC security and execution errors interrupts */
+#define OTFDEC_SEC_KEY_ERROR_INT (OTFDEC_IER_SEIE| OTFDEC_IER_KEIE) /*!< OTFDEC security and key errors interrupts */
+#define OTFDEC_EXE_KEY_ERROR_INT ( OTFDEC_IER_XONEIE|OTFDEC_IER_KEIE) /*!< OTFDEC execution and key errors interrupts */
+#define OTFDEC_ALL_INT (OTFDEC_IER_SEIE|OTFDEC_IER_XONEIE|OTFDEC_IER_KEIE) /*!< OTFDEC all interrupts */
+/**
+ * @}
+ */
+
+/** @defgroup OTFDEC_Region_Enable OTFDEC Region Enable
+ * @{
+ */
+#define OTFDEC_REG_CONFIGR_REG_DISABLE 0x00000000U /*!< OTFDEC region encryption or on-the-fly decryption disable */
+#define OTFDEC_REG_CONFIGR_REG_ENABLE OTFDEC_REG_CONFIGR_REG_EN /*!< OTFDEC region encryption or on-the-fly decryption enable */
+/**
+ * @}
+ */
+
+/** @defgroup OTFDEC_Region_Configuration_Lock OTFDEC Region Configuration Lock
+ * @{
+ */
+#define OTFDEC_REG_CONFIGR_LOCK_DISABLE 0x00000000U /*!< OTFDEC region configuration lock disable */
+#define OTFDEC_REG_CONFIGR_LOCK_ENABLE OTFDEC_REG_CONFIGR_CONFIGLOCK /*!< OTFDEC region configuration lock enable */
+/**
+ * @}
+ */
+
+/** @defgroup OTFDEC_Region_Operating_Mode OTFDEC Region Operating Mode
+ * @{
+ */
+#define OTFDEC_REG_MODE_INSTRUCTION_OR_DATA_ACCESSES OTFDEC_REG_CONFIGR_MODE_1 /*!< All read accesses are decrypted */
+#define OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY_WITH_CIPHER OTFDEC_REG_CONFIGR_MODE /*!< Only instruction accesses are decrypted with proprietary cipher activated */
+/**
+ * @}
+ */
+
+/** @defgroup OTFDEC_Error_Definition OTFDEC Error Definition
+ * @{
+ */
+#define HAL_OTFDEC_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
+#define HAL_OTFDEC_SECURITY_ERROR ((uint32_t)0x00000001U) /*!< Security error */
+#define HAL_OTFDEC_EXECUTE_ERROR ((uint32_t)0x00000002U) /*!< Execute-only Execute-Never error */
+#define HAL_OTFDEC_KEY_ERROR ((uint32_t)0x00000004U) /*!< Key error */
+#if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)
+#define HAL_OTFDEC_ERROR_INVALID_CALLBACK ((uint32_t)0x00000008U) /*!< Invalid Callback error */
+#endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup OTFDEC_Regions_Index OTFDEC Regions Index
+ * @{
+ */
+#define OTFDEC_REGION1 ((uint32_t)0x00000000U) /*!< OTFDEC region 1 */
+#define OTFDEC_REGION2 ((uint32_t)0x00000001U) /*!< OTFDEC region 2 */
+#define OTFDEC_REGION3 ((uint32_t)0x00000002U) /*!< OTFDEC region 3 */
+#define OTFDEC_REGION4 ((uint32_t)0x00000003U) /*!< OTFDEC region 4 */
+/**
+ * @}
+ */
+
+/** @defgroup OTFDEC_Configuration_Attributes OTFDEC Configuration Attributes
+ * @{
+ */
+#define OTFDEC_ATTRIBUTE_NPRIV ((uint32_t)0x00000000U) /*!< Non-privileged access protection */
+#define OTFDEC_ATTRIBUTE_PRIV OTFDEC_PRIVCFGR_PRIV /*!< Privileged access protection */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup OTFDEC_Exported_Macros OTFDEC Exported Macros
+ * @{
+ */
+
+/** @brief Reset OTFDEC handle state.
+ * @param __HANDLE__ pointer to an OTFDEC_HandleTypeDef structure that contains
+ * the configuration information for OTFDEC module
+ * @retval None
+ */
+#if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)
+#define __HAL_OTFDEC_RESET_HANDLE_STATE(__HANDLE__) \
+ do{ \
+ (__HANDLE__)->State = HAL_OTFDEC_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_OTFDEC_RESET_HANDLE_STATE(__HANDLE__) \
+ ((__HANDLE__)->State = HAL_OTFDEC_STATE_RESET)
+#endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */
+
+/**
+ * @brief Enable OTFDEC peripheral interrupts combination
+ * @param __HANDLE__ pointer to an OTFDEC_HandleTypeDef structure that contains
+ * the configuration information for OTFDEC module
+ * @param __INTERRUPT__ mask on enabled interrupts
+ * This parameter can be one of the following values:
+ * @arg @ref OTFDEC_SEC_ERROR_INT OTFDEC security error interrupt
+ * @arg @ref OTFDEC_EXE_ERROR_INT OTFDEC execution error interrupt
+ * @arg @ref OTFDEC_KEY_ERROR_INT OTFDEC key error interrupt
+ * @arg @ref OTFDEC_SEC_EXE_ERROR_INT OTFDEC security and execution errors interrupts
+ * @arg @ref OTFDEC_SEC_KEY_ERROR_INT OTFDEC security and key errors interrupts
+ * @arg @ref OTFDEC_EXE_KEY_ERROR_INT OTFDEC execution and key errors interrupts
+ * @arg @ref OTFDEC_ALL_INT OTFDEC all interrupts
+ * @retval None
+ */
+#define __HAL_OTFDEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT(((__HANDLE__)->Instance->IER), (__INTERRUPT__))
+
+/**
+ * @brief Disable OTFDEC peripheral interrupts combination
+ * @param __HANDLE__ pointer to an OTFDEC_HandleTypeDef structure that contains
+ * the configuration information for OTFDEC module
+ * @param __INTERRUPT__ mask on disabled interrupts
+ * This parameter can be one of the following values:
+ * @arg @ref OTFDEC_SEC_ERROR_INT OTFDEC security error interrupt
+ * @arg @ref OTFDEC_EXE_ERROR_INT OTFDEC execution error interrupt
+ * @arg @ref OTFDEC_KEY_ERROR_INT OTFDEC key error interrupt
+ * @arg @ref OTFDEC_SEC_EXE_ERROR_INT OTFDEC security and execution errors interrupts
+ * @arg @ref OTFDEC_SEC_KEY_ERROR_INT OTFDEC security and key errors interrupts
+ * @arg @ref OTFDEC_EXE_KEY_ERROR_INT OTFDEC execution and key errors interrupts
+ * @arg @ref OTFDEC_ALL_INT OTFDEC all interrupts
+ * @retval None
+ */
+#define __HAL_OTFDEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT(((__HANDLE__)->Instance->IER), (__INTERRUPT__))
+
+/** @brief Check whether the specified combination of OTFDEC interrupt flags is set or not.
+ * @param __HANDLE__ pointer to an OTFDEC_HandleTypeDef structure that contains
+ * the configuration information for OTFDEC module
+ * @param __FLAG__ mask on combination of interrupts flags
+ * This parameter can be one of the following values:
+ * @arg @ref OTFDEC_SEC_ERROR_INT OTFDEC security error interrupt flag
+ * @arg @ref OTFDEC_EXE_ERROR_INT OTFDEC execution error interrupt flag
+ * @arg @ref OTFDEC_KEY_ERROR_INT OTFDEC key error interrupt flag
+ * @arg @ref OTFDEC_SEC_EXE_ERROR_INT OTFDEC security and execution errors interrupts flags
+ * @arg @ref OTFDEC_SEC_KEY_ERROR_INT OTFDEC security and key errors interrupts flags
+ * @arg @ref OTFDEC_EXE_KEY_ERROR_INT OTFDEC execution and key errors interrupts flag
+ * @arg @ref OTFDEC_ALL_INT OTFDEC all interrupts flags
+ * @retval The state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_OTFDEC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the specified combination of OTFDEC interrupt flags.
+ * @param __HANDLE__ pointer to an OTFDEC_HandleTypeDef structure that contains
+ * the configuration information for OTFDEC module
+ * @param __FLAG__ mask on combination of interrupts flags
+ * This parameter can be one of the following values:
+ * @arg @ref OTFDEC_SEC_ERROR_INT OTFDEC security error interrupt flag
+ * @arg @ref OTFDEC_EXE_ERROR_INT OTFDEC execution error interrupt flag
+ * @arg @ref OTFDEC_KEY_ERROR_INT OTFDEC key error interrupt flag
+ * @arg @ref OTFDEC_SEC_EXE_ERROR_INT OTFDEC security and execution errors interrupts flags
+ * @arg @ref OTFDEC_SEC_KEY_ERROR_INT OTFDEC security and key errors interrupts flags
+ * @arg @ref OTFDEC_EXE_KEY_ERROR_INT OTFDEC execution and key errors interrupts flag
+ * @arg @ref OTFDEC_ALL_INT OTFDEC all interrupts flags
+ * @retval None
+ */
+#define __HAL_OTFDEC_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT((__HANDLE__)->Instance->ICR, (__FLAG__))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup OTFDEC_Exported_Functions OTFDEC Exported Functions
+ * @{
+ */
+
+/** @addtogroup OTFDEC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_OTFDEC_Init(OTFDEC_HandleTypeDef *hotfdec);
+HAL_StatusTypeDef HAL_OTFDEC_DeInit(OTFDEC_HandleTypeDef *hotfdec);
+void HAL_OTFDEC_MspInit(OTFDEC_HandleTypeDef *hotfdec);
+void HAL_OTFDEC_MspDeInit(OTFDEC_HandleTypeDef *hotfdec);
+
+#if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)
+/* Callbacks Register/UnRegister functions ***********************************/
+HAL_StatusTypeDef HAL_OTFDEC_RegisterCallback(OTFDEC_HandleTypeDef *hotfdec, HAL_OTFDEC_CallbackIDTypeDef CallbackID,
+ pOTFDEC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_OTFDEC_UnRegisterCallback(OTFDEC_HandleTypeDef *hotfdec, HAL_OTFDEC_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+
+/** @addtogroup OTFDEC_Exported_Functions_Group2 OTFDEC IRQ handler management
+ * @{
+ */
+void HAL_OTFDEC_IRQHandler(OTFDEC_HandleTypeDef *hotfdec);
+void HAL_OTFDEC_ErrorCallback(OTFDEC_HandleTypeDef *hotfdec);
+/**
+ * @}
+ */
+
+/** @addtogroup OTFDEC_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_OTFDEC_RegionKeyLock(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex);
+HAL_StatusTypeDef HAL_OTFDEC_RegionSetKey(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t *pKey);
+HAL_StatusTypeDef HAL_OTFDEC_RegionSetMode(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t mode);
+HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex,
+ OTFDEC_RegionConfigTypeDef *Config, uint32_t lock);
+uint32_t HAL_OTFDEC_KeyCRCComputation(uint32_t *pKey);
+HAL_StatusTypeDef HAL_OTFDEC_RegionEnable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex);
+HAL_StatusTypeDef HAL_OTFDEC_RegionDisable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex);
+HAL_StatusTypeDef HAL_OTFDEC_ConfigAttributes(OTFDEC_HandleTypeDef *hotfdec, uint32_t Attributes);
+HAL_StatusTypeDef HAL_OTFDEC_EnableEnciphering(OTFDEC_HandleTypeDef *hotfdec);
+HAL_StatusTypeDef HAL_OTFDEC_DisableEnciphering(OTFDEC_HandleTypeDef *hotfdec);
+HAL_StatusTypeDef HAL_OTFDEC_Cipher(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t *input,
+ uint32_t *output, uint32_t size, uint32_t start_address);
+/**
+ * @}
+ */
+
+/** @addtogroup @addtogroup OTFDEC_Exported_Functions_Group4 Peripheral State and Status functions
+ * @{
+ */
+HAL_OTFDEC_StateTypeDef HAL_OTFDEC_GetState(OTFDEC_HandleTypeDef *hotfdec);
+HAL_StatusTypeDef HAL_OTFDEC_GetConfigAttributes(OTFDEC_HandleTypeDef *hotfdec, uint32_t *Attributes);
+uint32_t HAL_OTFDEC_RegionGetKeyCRC(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex);
+HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex,
+ OTFDEC_RegionConfigTypeDef *Config);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup OTFDEC_Private_Types OTFDEC Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup OTFDEC_Private_Variables OTFDEC Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup OTFDEC_Private_Constants OTFDEC Private Constants
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup OTFDEC_Private_Macros OTFDEC Private Macros
+ * @{
+ */
+
+/**
+ * @brief Verify the OTFDEC peripheral interrupts parameter.
+ * @param __INT__ OTFDEC peripheral set of interrupts parameter
+ * @retval SET (__INT__ is valid) or RESET (__INT__ is invalid)
+ */
+#define IS_OTFDEC_INTERRUPTS(__INT__) (((__INT__) == OTFDEC_SEC_ERROR_INT) || \
+ ((__INT__) == OTFDEC_EXE_ERROR_INT) || \
+ ((__INT__) == OTFDEC_KEY_ERROR_INT) || \
+ ((__INT__) == OTFDEC_SEC_EXE_ERROR_INT) || \
+ ((__INT__) == OTFDEC_SEC_KEY_ERROR_INT) || \
+ ((__INT__) == OTFDEC_EXE_KEY_ERROR_INT) || \
+ ((__INT__) == OTFDEC_ALL_INT) )
+
+/**
+ * @brief Verify the OTFDEC region configuration lock parameter.
+ * @param __LOCK__ OTFDEC region lock parameter.
+ * @retval SET (__LOCK__ is valid) or RESET (__LOCK__ is invalid)
+ */
+#define IS_OTFDEC_REGION_CONFIG_LOCK(__LOCK__) (((__LOCK__) == OTFDEC_REG_CONFIGR_LOCK_DISABLE) || \
+ ((__LOCK__) == OTFDEC_REG_CONFIGR_LOCK_ENABLE) )
+
+/**
+ * @brief Verify the OTFDEC region operating mode.
+ * @param __MODE__ OTFDEC region operating mode parameter.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_OTFDEC_REGION_OPERATING_MODE(__MODE__) \
+ (((__MODE__)== OTFDEC_REG_MODE_INSTRUCTION_OR_DATA_ACCESSES) || \
+ ((__MODE__) == OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY_WITH_CIPHER))
+
+/**
+ * @brief Verify the OTFDEC region index.
+ * @param __INDEX__ OTFDEC region index
+ * @retval SET (__INDEX__ is valid) or RESET (__INDEX__ is invalid)
+ */
+#define IS_OTFDEC_REGIONINDEX(__INDEX__) (((__INDEX__) == OTFDEC_REGION1) || \
+ ((__INDEX__) == OTFDEC_REGION2) || \
+ ((__INDEX__) == OTFDEC_REGION3) || \
+ ((__INDEX__) == OTFDEC_REGION4) )
+
+/**
+ * @brief Verify the OTFDEC configuration attributes.
+ * @param __ATTRIBUTE__ OTFDEC region index
+ * @retval SET (__ATTRIBUTE__ is valid) or RESET (__ATTRIBUTE__ is invalid)
+ */
+#define IS_OTFDEC_ATTRIBUTE(__ATTRIBUTE__) (((__ATTRIBUTE__) == OTFDEC_ATTRIBUTE_PRIV) || \
+ ((__ATTRIBUTE__) == OTFDEC_ATTRIBUTE_NPRIV) )
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup OTFDEC_Private_Functions OTFDEC Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* OTFDEC1 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_OTFDEC_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pcd.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pcd.h
new file mode 100644
index 00000000..9ff6bb81
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pcd.h
@@ -0,0 +1,435 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_pcd.h
+ * @author MCD Application Team
+ * @brief Header file of PCD HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_PCD_H
+#define STM32U5xx_HAL_PCD_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_ll_usb.h"
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PCD
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup PCD_Exported_Types PCD Exported Types
+ * @{
+ */
+
+/**
+ * @brief PCD State structure definition
+ */
+typedef enum
+{
+ HAL_PCD_STATE_RESET = 0x00,
+ HAL_PCD_STATE_READY = 0x01,
+ HAL_PCD_STATE_ERROR = 0x02,
+ HAL_PCD_STATE_BUSY = 0x03,
+ HAL_PCD_STATE_TIMEOUT = 0x04
+} PCD_StateTypeDef;
+
+/* Device LPM suspend state */
+typedef enum
+{
+ LPM_L0 = 0x00, /* on */
+ LPM_L1 = 0x01, /* LPM L1 sleep */
+ LPM_L2 = 0x02, /* suspend */
+ LPM_L3 = 0x03, /* off */
+} PCD_LPM_StateTypeDef;
+
+typedef enum
+{
+ PCD_LPM_L0_ACTIVE = 0x00, /* on */
+ PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
+} PCD_LPM_MsgTypeDef;
+
+typedef enum
+{
+ PCD_BCD_ERROR = 0xFF,
+ PCD_BCD_CONTACT_DETECTION = 0xFE,
+ PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD,
+ PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC,
+ PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB,
+ PCD_BCD_DISCOVERY_COMPLETED = 0x00,
+
+} PCD_BCD_MsgTypeDef;
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+typedef USB_OTG_GlobalTypeDef PCD_TypeDef;
+typedef USB_OTG_CfgTypeDef PCD_InitTypeDef;
+typedef USB_OTG_EPTypeDef PCD_EPTypeDef;
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+/**
+ * @brief PCD Handle Structure definition
+ */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+typedef struct __PCD_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+ PCD_TypeDef *Instance; /*!< Register base address */
+ PCD_InitTypeDef Init; /*!< PCD required parameters */
+ __IO uint8_t USB_Address; /*!< USB Address */
+ PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */
+ PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */
+ HAL_LockTypeDef Lock; /*!< PCD peripheral status */
+ __IO PCD_StateTypeDef State; /*!< PCD communication state */
+ __IO uint32_t ErrorCode; /*!< PCD Error code */
+ uint32_t Setup[12]; /*!< Setup packet buffer */
+ PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
+ uint32_t BESL;
+
+
+ uint32_t lpm_active; /*!< Enable or disable the Link Power Management .
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t battery_charging_active; /*!< Enable or disable Battery charging.
+ This parameter can be set to ENABLE or DISABLE */
+ void *pData; /*!< Pointer to upper stack Handler */
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD SOF callback */
+ void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Setup Stage callback */
+ void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Reset callback */
+ void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Suspend callback */
+ void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Resume callback */
+ void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Connect callback */
+ void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Disconnect callback */
+
+ void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data OUT Stage callback */
+ void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data IN Stage callback */
+ void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO OUT Incomplete callback */
+ void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO IN Incomplete callback */
+ void (* BCDCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /*!< USB OTG PCD BCD callback */
+ void (* LPMCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< USB OTG PCD LPM callback */
+
+ void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp Init callback */
+ void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp DeInit callback */
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+} PCD_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Include PCD HAL Extended module */
+#include "stm32u5xx_hal_pcd_ex.h"
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PCD_Exported_Constants PCD Exported Constants
+ * @{
+ */
+
+/** @defgroup PCD_Speed PCD Speed
+ * @{
+ */
+#define PCD_SPEED_HIGH USBD_HS_SPEED
+#define PCD_SPEED_HIGH_IN_FULL USBD_HSINFS_SPEED
+#define PCD_SPEED_FULL USBD_FS_SPEED
+/**
+ * @}
+ */
+
+/** @defgroup PCD_PHY_Module PCD PHY Module
+ * @{
+ */
+#define PCD_PHY_ULPI 1U
+#define PCD_PHY_EMBEDDED 2U
+#define PCD_PHY_UTMI 3U
+/**
+ * @}
+ */
+
+/** @defgroup PCD_Error_Code_definition PCD Error Code definition
+ * @brief PCD Error Code definition
+ * @{
+ */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+#define HAL_PCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup PCD_Exported_Macros PCD Exported Macros
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
+
+#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \
+ ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
+
+#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__))
+#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
+
+#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) \
+ *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK)
+
+#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) \
+ *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
+
+#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) \
+ ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PCD_Exported_Functions PCD Exported Functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions ********************************/
+/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+/** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition
+ * @brief HAL USB OTG PCD Callback ID enumeration definition
+ * @{
+ */
+typedef enum
+{
+ HAL_PCD_SOF_CB_ID = 0x01, /*!< USB PCD SOF callback ID */
+ HAL_PCD_SETUPSTAGE_CB_ID = 0x02, /*!< USB PCD Setup Stage callback ID */
+ HAL_PCD_RESET_CB_ID = 0x03, /*!< USB PCD Reset callback ID */
+ HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */
+ HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */
+ HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */
+ HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */
+
+ HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */
+ HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */
+
+} HAL_PCD_CallbackIDTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition
+ * @brief HAL USB OTG PCD Callback pointer definition
+ * @{
+ */
+
+typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd); /*!< pointer to a common USB OTG PCD callback function */
+typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data OUT Stage callback */
+typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data IN Stage callback */
+typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */
+typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO IN Incomplete callback */
+typedef void (*pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< pointer to USB OTG PCD LPM callback */
+typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /*!< pointer to USB OTG PCD BCD callback */
+
+/**
+ * @}
+ */
+
+HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
+ HAL_PCD_CallbackIDTypeDef CallbackID,
+ pPCD_CallbackTypeDef pCallback);
+
+HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd,
+ HAL_PCD_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_DataOutStageCallbackTypeDef pCallback);
+
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_DataInStageCallbackTypeDef pCallback);
+
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_IsoOutIncpltCallbackTypeDef pCallback);
+
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_IsoInIncpltCallbackTypeDef pCallback);
+
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_BcdCallbackTypeDef pCallback);
+
+HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_LpmCallbackTypeDef pCallback);
+
+HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/* I/O operation functions ***************************************************/
+/* Non-Blocking mode: Interrupt */
+/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
+
+void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
+
+void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+/**
+ * @}
+ */
+
+/* Peripheral Control functions **********************************************/
+/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
+ uint16_t ep_mps, uint8_t ep_type);
+
+HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
+ uint8_t *pBuf, uint32_t len);
+
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
+ uint8_t *pBuf, uint32_t len);
+
+
+HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+
+uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+/**
+ * @}
+ */
+
+/* Peripheral State functions ************************************************/
+/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup PCD_Private_Constants PCD Private Constants
+ * @{
+ */
+/**
+ * @}
+ */
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+#ifndef USB_OTG_DOEPINT_OTEPSPR
+#define USB_OTG_DOEPINT_OTEPSPR (0x1UL << 5) /*!< Status Phase Received interrupt */
+#endif /* defined USB_OTG_DOEPINT_OTEPSPR */
+
+#ifndef USB_OTG_DOEPMSK_OTEPSPRM
+#define USB_OTG_DOEPMSK_OTEPSPRM (0x1UL << 5) /*!< Setup Packet Received interrupt mask */
+#endif /* defined USB_OTG_DOEPMSK_OTEPSPRM */
+
+#ifndef USB_OTG_DOEPINT_NAK
+#define USB_OTG_DOEPINT_NAK (0x1UL << 13) /*!< NAK interrupt */
+#endif /* defined USB_OTG_DOEPINT_NAK */
+
+#ifndef USB_OTG_DOEPMSK_NAKM
+#define USB_OTG_DOEPMSK_NAKM (0x1UL << 13) /*!< OUT Packet NAK interrupt mask */
+#endif /* defined USB_OTG_DOEPMSK_NAKM */
+
+#ifndef USB_OTG_DOEPINT_STPKTRX
+#define USB_OTG_DOEPINT_STPKTRX (0x1UL << 15) /*!< Setup Packet Received interrupt */
+#endif /* defined USB_OTG_DOEPINT_STPKTRX */
+
+#ifndef USB_OTG_DOEPMSK_NYETM
+#define USB_OTG_DOEPMSK_NYETM (0x1UL << 14) /*!< Setup Packet Received interrupt mask */
+#endif /* defined USB_OTG_DOEPMSK_NYETM */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PCD_Private_Macros PCD Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_PCD_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pcd_ex.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pcd_ex.h
new file mode 100644
index 00000000..d47dfaad
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pcd_ex.h
@@ -0,0 +1,88 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_pcd_ex.h
+ * @author MCD Application Team
+ * @brief Header file of PCD HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_PCD_EX_H
+#define STM32U5xx_HAL_PCD_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PCDEx
+ * @{
+ */
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
+ * @{
+ */
+/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
+ * @{
+ */
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
+HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+
+HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
+
+#if defined (STM32U575xx) || defined (STM32U585xx) || defined (STM32U595xx) || defined (STM32U5A5xx) || defined (STM32U599xx) || defined (STM32U5A9xx)
+HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
+void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
+#endif /* defined (STM32U575xx) || defined (STM32U585xx) || defined (STM32U595xx) || defined (STM32U5A5xx) || defined (STM32U599xx) || defined (STM32U5A9xx) */
+void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
+void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32U5xx_HAL_PCD_EX_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pka.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pka.h
new file mode 100644
index 00000000..eb7af5a4
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pka.h
@@ -0,0 +1,654 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_pka.h
+ * @author MCD Application Team
+ * @brief Header file of PKA HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_PKA_H
+#define STM32U5xx_HAL_PKA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+#if defined(PKA) && defined(HAL_PKA_MODULE_ENABLED)
+
+/** @addtogroup PKA
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup PKA_Exported_Types PKA Exported Types
+ * @{
+ */
+
+/** @defgroup HAL_state_structure_definition HAL state structure definition
+ * @brief HAL State structures definition
+ * @{
+ */
+typedef enum
+{
+ HAL_PKA_STATE_RESET = 0x00U, /*!< PKA not yet initialized or disabled */
+ HAL_PKA_STATE_READY = 0x01U, /*!< PKA initialized and ready for use */
+ HAL_PKA_STATE_BUSY = 0x02U, /*!< PKA internal processing is ongoing */
+ HAL_PKA_STATE_ERROR = 0x03U, /*!< PKA error state */
+}
+HAL_PKA_StateTypeDef;
+
+/**
+ * @}
+ */
+
+#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
+/** @defgroup HAL_callback_id HAL callback ID enumeration
+ * @{
+ */
+typedef enum
+{
+ HAL_PKA_OPERATION_COMPLETE_CB_ID = 0x00U, /*!< PKA End of operation callback ID */
+ HAL_PKA_ERROR_CB_ID = 0x01U, /*!< PKA Error callback ID */
+ HAL_PKA_MSPINIT_CB_ID = 0x02U, /*!< PKA Msp Init callback ID */
+ HAL_PKA_MSPDEINIT_CB_ID = 0x03U /*!< PKA Msp DeInit callback ID */
+} HAL_PKA_CallbackIDTypeDef;
+
+/**
+ * @}
+ */
+
+#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
+
+/** @defgroup PKA_Error_Code_definition PKA Error Code definition
+ * @brief PKA Error Code definition
+ * @{
+ */
+#define HAL_PKA_ERROR_NONE (0x00000000U)
+#define HAL_PKA_ERROR_ADDRERR (0x00000001U)
+#define HAL_PKA_ERROR_RAMERR (0x00000002U)
+#define HAL_PKA_ERROR_TIMEOUT (0x00000004U)
+#define HAL_PKA_ERROR_OPERATION (0x00000008U)
+#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
+#define HAL_PKA_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */
+#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup PKA_handle_Structure_definition PKA handle Structure definition
+ * @brief PKA handle Structure definition
+ * @{
+ */
+#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
+typedef struct __PKA_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
+{
+ PKA_TypeDef *Instance; /*!< Register base address */
+ __IO HAL_PKA_StateTypeDef State; /*!< PKA state */
+ __IO uint32_t ErrorCode; /*!< PKA Error code */
+#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
+ void (* OperationCpltCallback)(struct __PKA_HandleTypeDef *hpka); /*!< PKA End of operation callback */
+ void (* ErrorCallback)(struct __PKA_HandleTypeDef *hpka); /*!< PKA Error callback */
+ void (* MspInitCallback)(struct __PKA_HandleTypeDef *hpka); /*!< PKA Msp Init callback */
+ void (* MspDeInitCallback)(struct __PKA_HandleTypeDef *hpka); /*!< PKA Msp DeInit callback */
+#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
+} PKA_HandleTypeDef;
+/**
+ * @}
+ */
+
+#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
+/** @defgroup PKA_Callback_definition PKA Callback pointer definition
+ * @brief PKA Callback pointer definition
+ * @{
+ */
+typedef void (*pPKA_CallbackTypeDef)(PKA_HandleTypeDef *hpka); /*!< Pointer to a PKA callback function */
+/**
+ * @}
+ */
+#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
+/** @defgroup PKA_Operation PKA operation structure definition
+ * @brief Input and output data definition
+ * @{
+ */
+
+typedef struct
+{
+ uint32_t scalarMulSize; /*!< Number of element in scalarMul array */
+ uint32_t modulusSize; /*!< Number of element in modulus, coefA, pointX and pointY arrays */
+ uint32_t coefSign; /*!< Curve coefficient a sign */
+ const uint8_t *coefA; /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */
+ const uint8_t *coefB; /*!< pointer to curve coefficient b */
+ const uint8_t *modulus; /*!< Pointer to curve modulus value p (Array of modulusSize elements) */
+ const uint8_t *pointX; /*!< Pointer to point P coordinate xP (Array of modulusSize elements) */
+ const uint8_t *pointY; /*!< Pointer to point P coordinate yP (Array of modulusSize elements) */
+ const uint8_t *scalarMul; /*!< Pointer to scalar multiplier k (Array of scalarMulSize elements) */
+ const uint8_t *primeOrder; /*!< pointer to order of the curve */
+} PKA_ECCMulInTypeDef;
+
+typedef struct
+{
+ uint32_t modulusSize; /*!< Number of element in coefA, coefB, modulus, pointX and pointY arrays */
+ uint32_t coefSign; /*!< Curve coefficient a sign */
+ const uint8_t *coefA; /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */
+ const uint8_t *coefB; /*!< Pointer to curve coefficient b (Array of modulusSize elements) */
+ const uint8_t *modulus; /*!< Pointer to curve modulus value p (Array of modulusSize elements) */
+ const uint8_t *pointX; /*!< Pointer to point P coordinate xP (Array of modulusSize elements) */
+ const uint8_t *pointY; /*!< Pointer to point P coordinate yP (Array of modulusSize elements) */
+ const uint32_t *pMontgomeryParam; /*!< pointer to montgomery param R2 (modulus N) */
+} PKA_PointCheckInTypeDef;
+
+typedef struct
+{
+ uint32_t size; /*!< Number of element in popA array */
+ const uint8_t *pOpDp; /*!< Pointer to operand dP (Array of size/2 elements) */
+ const uint8_t *pOpDq; /*!< Pointer to operand dQ (Array of size/2 elements) */
+ const uint8_t *pOpQinv; /*!< Pointer to operand qinv (Array of size/2 elements) */
+ const uint8_t *pPrimeP; /*!< Pointer to prime p (Array of size/2 elements) */
+ const uint8_t *pPrimeQ; /*!< Pointer to prime Q (Array of size/2 elements) */
+ const uint8_t *popA; /*!< Pointer to operand A (Array of size elements) */
+} PKA_RSACRTExpInTypeDef;
+
+typedef struct
+{
+ uint32_t primeOrderSize; /*!< Number of element in primeOrder array */
+ uint32_t modulusSize; /*!< Number of element in modulus array */
+ uint32_t coefSign; /*!< Curve coefficient a sign */
+ const uint8_t *coef; /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */
+ const uint8_t *modulus; /*!< Pointer to curve modulus value p (Array of modulusSize elements) */
+ const uint8_t *basePointX; /*!< Pointer to curve base point xG (Array of modulusSize elements) */
+ const uint8_t *basePointY; /*!< Pointer to curve base point yG (Array of modulusSize elements) */
+ const uint8_t *pPubKeyCurvePtX; /*!< Pointer to public-key curve point xQ (Array of modulusSize elements) */
+ const uint8_t *pPubKeyCurvePtY; /*!< Pointer to public-key curve point yQ (Array of modulusSize elements) */
+ const uint8_t *RSign; /*!< Pointer to signature part r (Array of primeOrderSize elements) */
+ const uint8_t *SSign; /*!< Pointer to signature part s (Array of primeOrderSize elements) */
+ const uint8_t *hash; /*!< Pointer to hash of the message e (Array of primeOrderSize elements) */
+ const uint8_t *primeOrder; /*!< Pointer to order of the curve n (Array of primeOrderSize elements) */
+} PKA_ECDSAVerifInTypeDef;
+
+typedef struct
+{
+ uint32_t primeOrderSize; /*!< Number of element in primeOrder array */
+ uint32_t modulusSize; /*!< Number of element in modulus array */
+ uint32_t coefSign; /*!< Curve coefficient a sign */
+ const uint8_t *coef; /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */
+ const uint8_t *coefB; /*!< Pointer to B coefficient (Array of modulusSize elements) */
+ const uint8_t *modulus; /*!< Pointer to curve modulus value p (Array of modulusSize elements) */
+ const uint8_t *integer; /*!< Pointer to random integer k (Array of primeOrderSize elements) */
+ const uint8_t *basePointX; /*!< Pointer to curve base point xG (Array of modulusSize elements) */
+ const uint8_t *basePointY; /*!< Pointer to curve base point yG (Array of modulusSize elements) */
+ const uint8_t *hash; /*!< Pointer to hash of the message (Array of primeOrderSize elements) */
+ const uint8_t *privateKey; /*!< Pointer to private key d (Array of primeOrderSize elements) */
+ const uint8_t *primeOrder; /*!< Pointer to order of the curve n (Array of primeOrderSize elements) */
+} PKA_ECDSASignInTypeDef;
+
+typedef struct
+{
+ uint8_t *RSign; /*!< Pointer to signature part r (Array of modulusSize elements) */
+ uint8_t *SSign; /*!< Pointer to signature part s (Array of modulusSize elements) */
+} PKA_ECDSASignOutTypeDef;
+
+typedef struct
+{
+ uint8_t *ptX; /*!< Pointer to point P coordinate xP (Array of modulusSize elements) */
+ uint8_t *ptY; /*!< Pointer to point P coordinate yP (Array of modulusSize elements) */
+} PKA_ECDSASignOutExtParamTypeDef, PKA_ECCMulOutTypeDef, PKA_ECCProjective2AffineOutTypeDef,
+PKA_ECCDoubleBaseLadderOutTypeDef;
+
+typedef struct
+{
+ uint8_t *ptX; /*!< pointer to point P coordinate xP */
+ uint8_t *ptY; /*!< pointer to point P coordinate yP */
+ uint8_t *ptZ; /*!< pointer to point P coordinate zP */
+} PKA_ECCCompleteAdditionOutTypeDef;
+
+typedef struct
+{
+ uint32_t expSize; /*!< Number of element in pExp array */
+ uint32_t OpSize; /*!< Number of element in pOp1 and pMod arrays */
+ const uint8_t *pExp; /*!< Pointer to Exponent (Array of expSize elements) */
+ const uint8_t *pOp1; /*!< Pointer to Operand (Array of OpSize elements) */
+ const uint8_t *pMod; /*!< Pointer to modulus (Array of OpSize elements) */
+} PKA_ModExpInTypeDef;
+
+typedef struct
+{
+ uint32_t expSize; /*!< Size of the operand in bytes */
+ uint32_t OpSize; /*!< Size of the operand in bytes */
+ const uint8_t *pOp1; /*!< Pointer to Operand 1 */
+ const uint8_t *pExp; /*!< Pointer to Exponent */
+ const uint8_t *pMod; /*!< Pointer to Operand 1 */
+ const uint8_t *pPhi; /*!< Pointer to Phi value */
+} PKA_ModExpProtectModeInTypeDef;
+
+typedef struct
+{
+ uint32_t expSize; /*!< Number of element in pExp and pMontgomeryParam arrays */
+ uint32_t OpSize; /*!< Number of element in pOp1 and pMod arrays */
+ const uint8_t *pExp; /*!< Pointer to Exponent (Array of expSize elements) */
+ const uint8_t *pOp1; /*!< Pointer to Operand (Array of OpSize elements) */
+ const uint8_t *pMod; /*!< Pointer to modulus (Array of OpSize elements) */
+ const uint32_t *pMontgomeryParam; /*!< Pointer to Montgomery parameter (Array of expSize/4 elements) */
+} PKA_ModExpFastModeInTypeDef;
+
+typedef struct
+{
+ uint32_t size; /*!< Number of element in pOp1 array */
+ const uint8_t *pOp1; /*!< Pointer to Operand (Array of size elements) */
+} PKA_MontgomeryParamInTypeDef;
+
+typedef struct
+{
+ uint32_t size; /*!< Number of element in pOp1 and pOp2 arrays */
+ const uint32_t *pOp1; /*!< Pointer to Operand 1 (Array of size elements) */
+ const uint32_t *pOp2; /*!< Pointer to Operand 2 (Array of size elements) */
+} PKA_AddInTypeDef, PKA_SubInTypeDef, PKA_MulInTypeDef, PKA_CmpInTypeDef;
+
+typedef struct
+{
+ uint32_t size; /*!< Number of element in pOp1 array */
+ const uint32_t *pOp1; /*!< Pointer to Operand 1 (Array of size elements) */
+ const uint8_t *pMod; /*!< Pointer to modulus value n (Array of size*4 elements) */
+} PKA_ModInvInTypeDef;
+
+typedef struct
+{
+ uint32_t OpSize; /*!< Number of element in pOp1 array */
+ uint32_t modSize; /*!< Number of element in pMod array */
+ const uint32_t *pOp1; /*!< Pointer to Operand 1 (Array of OpSize elements) */
+ const uint8_t *pMod; /*!< Pointer to modulus value n (Array of modSize elements) */
+} PKA_ModRedInTypeDef;
+
+typedef struct
+{
+ uint32_t size; /*!< Number of element in pOp1 and pOp2 arrays */
+ const uint32_t *pOp1; /*!< Pointer to Operand 1 (Array of size elements) */
+ const uint32_t *pOp2; /*!< Pointer to Operand 2 (Array of size elements) */
+ const uint8_t *pOp3; /*!< Pointer to Operand 3 (Array of size*4 elements) */
+} PKA_ModAddInTypeDef, PKA_ModSubInTypeDef, PKA_MontgomeryMulInTypeDef;
+
+typedef struct
+{
+ uint32_t primeOrderSize; /*!< curve prime order n length */
+ uint32_t modulusSize; /*!< curve modulus p length */
+ uint32_t coefSign; /*!< curve coefficient a sign */
+ const uint8_t *coefA; /*!< pointer to curve coefficient |a| */
+ const uint8_t *modulus; /*!< pointer to curve modulus value p */
+ const uint8_t *integerK; /*!< pointer to cryptographically secure random integer k */
+ const uint8_t *integerM; /*!< pointer to cryptographically secure random integer m */
+ const uint8_t *basePointX1; /*!< pointer to curve base first point coordinate x */
+ const uint8_t *basePointY1; /*!< pointer to curve base first point coordinate y */
+ const uint8_t *basePointZ1; /*!< pointer to curve base first point coordinate z */
+ const uint8_t *basePointX2; /*!< pointer to curve base second point coordinate x */
+ const uint8_t *basePointY2; /*!< pointer to curve base second point coordinate y */
+ const uint8_t *basePointZ2; /*!< pointer to curve base second point coordinate z */
+} PKA_ECCDoubleBaseLadderInTypeDef;
+
+typedef struct
+{
+ uint32_t modulusSize; /*!< curve modulus p length */
+ const uint8_t *modulus; /*!< pointer to curve modulus value p */
+ const uint8_t *basePointX; /*!< pointer to curve base point coordinate x */
+ const uint8_t *basePointY; /*!< pointer to curve base point coordinate y */
+ const uint8_t *basePointZ; /*!< pointer to curve base point coordinate z */
+ const uint32_t *pMontgomeryParam; /*!< pointer to montgomery parameter R2 modulus n*/
+} PKA_ECCProjective2AffineInTypeDef;
+
+typedef struct
+{
+ uint32_t modulusSize; /*!< curve modulus p length */
+ uint32_t coefSign; /*!< curve coefficient a sign */
+ const uint8_t *modulus; /*!< pointer to curve modulus value p */
+ const uint8_t *coefA; /*!< pointer to curve coefficient |a| */
+ const uint8_t *basePointX1; /*!< pointer to curve base first point coordinate x */
+ const uint8_t *basePointY1; /*!< pointer to curve base first point coordinate y */
+ const uint8_t *basePointZ1; /*!< pointer to curve base first point coordinate z */
+ const uint8_t *basePointX2; /*!< pointer to curve base second point coordinate x */
+ const uint8_t *basePointY2; /*!< pointer to curve base second point coordinate y */
+ const uint8_t *basePointZ2; /*!< pointer to curve base second point coordinate z */
+} PKA_ECCCompleteAdditionInTypeDef;
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PKA_Exported_Constants PKA Exported Constants
+ * @{
+ */
+
+/** @defgroup PKA_Mode PKA mode
+ * @{
+ */
+#define PKA_MODE_MONTGOMERY_PARAM (0x00000001U)
+#define PKA_MODE_MODULAR_EXP (0x00000000U)
+#define PKA_MODE_MODULAR_EXP_FAST_MODE (0x00000002U)
+#define PKA_MODE_ECC_MUL (0x00000020U)
+#define PKA_MODE_ECDSA_SIGNATURE (0x00000024U)
+#define PKA_MODE_ECDSA_VERIFICATION (0x00000026U)
+#define PKA_MODE_POINT_CHECK (0x00000028U)
+#define PKA_MODE_RSA_CRT_EXP (0x00000007U)
+#define PKA_MODE_MODULAR_INV (0x00000008U)
+#define PKA_MODE_ARITHMETIC_ADD (0x00000009U)
+#define PKA_MODE_ARITHMETIC_SUB (0x0000000AU)
+#define PKA_MODE_ARITHMETIC_MUL (0x0000000BU)
+#define PKA_MODE_COMPARISON (0x0000000CU)
+#define PKA_MODE_MODULAR_RED (0x0000000DU)
+#define PKA_MODE_MODULAR_ADD (0x0000000EU)
+#define PKA_MODE_MODULAR_SUB (0x0000000FU)
+#define PKA_MODE_MONTGOMERY_MUL (0x00000010U)
+#define PKA_MODE_ECC_PROJECTIVE_AFF (0x0000002FU)
+#define PKA_MODE_DOUBLE_BASE_LADDER (0x00000027U)
+#define PKA_MODE_ECC_COMPLETE_ADD (0x00000023U)
+#define PKA_MODE_MODULAR_EXP_PROTECT (0x00000003U)
+/**
+ * @}
+ */
+
+/** @defgroup PKA_Interrupt_configuration_definition PKA Interrupt configuration definition
+ * @brief PKA Interrupt definition
+ * @{
+ */
+#define PKA_IT_PROCEND PKA_CR_PROCENDIE
+#define PKA_IT_ADDRERR PKA_CR_ADDRERRIE
+#define PKA_IT_RAMERR PKA_CR_RAMERRIE
+#define PKA_IT_OPERR PKA_CR_OPERRIE
+
+/**
+ * @}
+ */
+
+/** @defgroup PKA_Flag_definition PKA Flag definition
+ * @{
+ */
+#define PKA_FLAG_PROCEND PKA_SR_PROCENDF
+#define PKA_FLAG_ADDRERR PKA_SR_ADDRERRF
+#define PKA_FLAG_RAMERR PKA_SR_RAMERRF
+#define PKA_FLAG_OPERR PKA_SR_OPERRF
+
+/**
+ * @}
+ */
+
+/** @defgroup PKA_Operation_Status PKA Operation Status
+ * @{
+ */
+#define PKA_NO_ERROR 0xD60DUL
+#define PKA_FAILED_COMPUTATION 0xCBC9UL
+#define PKA_RPART_SIGNATURE_NULL 0xA3B7UL
+#define PKA_SPART_SIGNATURE_NULL 0xF946UL
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup PKA_Exported_Macros PKA Exported Macros
+ * @{
+ */
+
+/** @brief Reset PKA handle state.
+ * @param __HANDLE__ specifies the PKA Handle
+ * @retval None
+ */
+#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
+#define __HAL_PKA_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_PKA_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_PKA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PKA_STATE_RESET)
+#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
+
+/** @brief Enable the specified PKA interrupt.
+ * @param __HANDLE__ specifies the PKA Handle
+ * @param __INTERRUPT__ specifies the interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg @ref PKA_IT_PROCEND End Of Operation interrupt enable
+ * @arg @ref PKA_IT_ADDRERR Address error interrupt enable
+ * @arg @ref PKA_IT_RAMERR RAM error interrupt enable
+ * @arg @ref PKA_IT_OPERR Operation error interrupt enable
+ * @retval None
+ */
+#define __HAL_PKA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/** @brief Disable the specified PKA interrupt.
+ * @param __HANDLE__ specifies the PKA Handle
+ * @param __INTERRUPT__ specifies the interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg @ref PKA_IT_PROCEND End Of Operation interrupt enable
+ * @arg @ref PKA_IT_ADDRERR Address error interrupt enable
+ * @arg @ref PKA_IT_RAMERR RAM error interrupt enable
+ * @arg @ref PKA_IT_OPERR Operation error interrupt enable
+ * @retval None
+ */
+#define __HAL_PKA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= (~(__INTERRUPT__)))
+
+/** @brief Check whether the specified PKA interrupt source is enabled or not.
+ * @param __HANDLE__ specifies the PKA Handle
+ * @param __INTERRUPT__ specifies the PKA interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg @ref PKA_IT_PROCEND End Of Operation interrupt enable
+ * @arg @ref PKA_IT_ADDRERR Address error interrupt enable
+ * @arg @ref PKA_IT_RAMERR RAM error interrupt enable
+ * @arg @ref PKA_IT_OPERR Operation error interrupt enable
+ * @retval The new state of __INTERRUPT__ (SET or RESET)
+ */
+#define __HAL_PKA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR\
+ & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Check whether the specified PKA flag is set or not.
+ * @param __HANDLE__ specifies the PKA Handle
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref PKA_FLAG_PROCEND End Of Operation
+ * @arg @ref PKA_FLAG_ADDRERR Address error
+ * @arg @ref PKA_FLAG_RAMERR RAM error
+ * @arg @ref PKA_FLAG_OPERR Operation error
+ * @retval The new state of __FLAG__ (SET or RESET)
+ */
+#define __HAL_PKA_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR)\
+ & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+
+/** @brief Clear the PKA pending flags which are cleared by writing 1 in a specific bit.
+ * @param __HANDLE__ specifies the PKA Handle
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg @ref PKA_FLAG_PROCEND End Of Operation
+ * @arg @ref PKA_FLAG_ADDRERR Address error
+ * @arg @ref PKA_FLAG_RAMERR RAM error
+ * @arg @ref PKA_FLAG_OPERR Operation error
+ * @retval None
+ */
+#define __HAL_PKA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
+
+/** @brief Enable the specified PKA peripheral.
+ * @param __HANDLE__ specifies the PKA Handle
+ * @retval None
+ */
+#define __HAL_PKA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR, PKA_CR_EN))
+
+/** @brief Disable the specified PKA peripheral.
+ * @param __HANDLE__ specifies the PKA Handle
+ * @retval None
+ */
+#define __HAL_PKA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR, PKA_CR_EN))
+
+/** @brief Start a PKA operation.
+ * @param __HANDLE__ specifies the PKA Handle
+ * @retval None
+ */
+#define __HAL_PKA_START(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR, PKA_CR_START))
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PKA_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup PKA_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_PKA_Init(PKA_HandleTypeDef *hpka);
+HAL_StatusTypeDef HAL_PKA_DeInit(PKA_HandleTypeDef *hpka);
+void HAL_PKA_MspInit(PKA_HandleTypeDef *hpka);
+void HAL_PKA_MspDeInit(PKA_HandleTypeDef *hpka);
+
+#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
+/* Callbacks Register/UnRegister functions ***********************************/
+HAL_StatusTypeDef HAL_PKA_RegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID,
+ pPKA_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PKA_UnRegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @addtogroup PKA_Exported_Functions_Group2
+ * @{
+ */
+/* IO operation functions *****************************************************/
+/* High Level Functions *******************************************************/
+HAL_StatusTypeDef HAL_PKA_ModExp(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in, uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_ModExp_IT(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in);
+HAL_StatusTypeDef HAL_PKA_ModExpFastMode(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in, uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_ModExpFastMode_IT(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in);
+HAL_StatusTypeDef HAL_PKA_ModExpProtectMode(PKA_HandleTypeDef *hpka, PKA_ModExpProtectModeInTypeDef *in,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_ModExpProtectMode_IT(PKA_HandleTypeDef *hpka, PKA_ModExpProtectModeInTypeDef *in);
+void HAL_PKA_ModExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes);
+
+HAL_StatusTypeDef HAL_PKA_ECDSASign(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in, uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_ECDSASign_IT(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in);
+void HAL_PKA_ECDSASign_GetResult(PKA_HandleTypeDef *hpka, PKA_ECDSASignOutTypeDef *out,
+ PKA_ECDSASignOutExtParamTypeDef *outExt);
+
+HAL_StatusTypeDef HAL_PKA_ECDSAVerif(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in, uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_ECDSAVerif_IT(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in);
+uint32_t HAL_PKA_ECDSAVerif_IsValidSignature(PKA_HandleTypeDef const *const hpka);
+
+HAL_StatusTypeDef HAL_PKA_RSACRTExp(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in, uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_RSACRTExp_IT(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in);
+void HAL_PKA_RSACRTExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes);
+
+HAL_StatusTypeDef HAL_PKA_PointCheck(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in, uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_PointCheck_IT(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in);
+uint32_t HAL_PKA_PointCheck_IsOnCurve(PKA_HandleTypeDef const *const hpka);
+
+HAL_StatusTypeDef HAL_PKA_ECCMul(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in, uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_ECCMul_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in);
+void HAL_PKA_ECCMul_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCMulOutTypeDef *out);
+
+HAL_StatusTypeDef HAL_PKA_Add(PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in, uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_Add_IT(PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in);
+HAL_StatusTypeDef HAL_PKA_Sub(PKA_HandleTypeDef *hpka, PKA_SubInTypeDef *in, uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_Sub_IT(PKA_HandleTypeDef *hpka, PKA_SubInTypeDef *in);
+HAL_StatusTypeDef HAL_PKA_Cmp(PKA_HandleTypeDef *hpka, PKA_CmpInTypeDef *in, uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_Cmp_IT(PKA_HandleTypeDef *hpka, PKA_CmpInTypeDef *in);
+HAL_StatusTypeDef HAL_PKA_Mul(PKA_HandleTypeDef *hpka, PKA_MulInTypeDef *in, uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_Mul_IT(PKA_HandleTypeDef *hpka, PKA_MulInTypeDef *in);
+HAL_StatusTypeDef HAL_PKA_ModAdd(PKA_HandleTypeDef *hpka, PKA_ModAddInTypeDef *in, uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_ModAdd_IT(PKA_HandleTypeDef *hpka, PKA_ModAddInTypeDef *in);
+HAL_StatusTypeDef HAL_PKA_ModSub(PKA_HandleTypeDef *hpka, PKA_ModSubInTypeDef *in, uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_ModSub_IT(PKA_HandleTypeDef *hpka, PKA_ModSubInTypeDef *in);
+HAL_StatusTypeDef HAL_PKA_ModInv(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in, uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_ModInv_IT(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in);
+HAL_StatusTypeDef HAL_PKA_ModRed(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in, uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_ModRed_IT(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in);
+HAL_StatusTypeDef HAL_PKA_MontgomeryMul(PKA_HandleTypeDef *hpka, PKA_MontgomeryMulInTypeDef *in, uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_MontgomeryMul_IT(PKA_HandleTypeDef *hpka, PKA_MontgomeryMulInTypeDef *in);
+void HAL_PKA_Arithmetic_GetResult(PKA_HandleTypeDef *hpka, uint32_t *pRes);
+
+HAL_StatusTypeDef HAL_PKA_MontgomeryParam(PKA_HandleTypeDef *hpka, PKA_MontgomeryParamInTypeDef *in, uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_MontgomeryParam_IT(PKA_HandleTypeDef *hpka, PKA_MontgomeryParamInTypeDef *in);
+void HAL_PKA_MontgomeryParam_GetResult(PKA_HandleTypeDef *hpka, uint32_t *pRes);
+
+HAL_StatusTypeDef HAL_PKA_ECCDoubleBaseLadder(PKA_HandleTypeDef *hpka, PKA_ECCDoubleBaseLadderInTypeDef *in,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_ECCDoubleBaseLadder_IT(PKA_HandleTypeDef *hpka, PKA_ECCDoubleBaseLadderInTypeDef *in);
+void HAL_PKA_ECCDoubleBaseLadder_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCDoubleBaseLadderOutTypeDef *out);
+
+HAL_StatusTypeDef HAL_PKA_ECCProjective2Affine(PKA_HandleTypeDef *hpka, PKA_ECCProjective2AffineInTypeDef *in,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_ECCProjective2Affine_IT(PKA_HandleTypeDef *hpka, PKA_ECCProjective2AffineInTypeDef *in);
+void HAL_PKA_ECCProjective2Affine_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCProjective2AffineOutTypeDef *out);
+
+HAL_StatusTypeDef HAL_PKA_ECCCompleteAddition(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditionInTypeDef *in,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_ECCCompleteAddition_IT(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditionInTypeDef *in);
+void HAL_PKA_ECCCompleteAddition_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditionOutTypeDef *out);
+
+HAL_StatusTypeDef HAL_PKA_Abort(PKA_HandleTypeDef *hpka);
+void HAL_PKA_RAMReset(PKA_HandleTypeDef *hpka);
+void HAL_PKA_OperationCpltCallback(PKA_HandleTypeDef *hpka);
+void HAL_PKA_ErrorCallback(PKA_HandleTypeDef *hpka);
+void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka);
+/**
+ * @}
+ */
+
+/** @addtogroup PKA_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+HAL_PKA_StateTypeDef HAL_PKA_GetState(PKA_HandleTypeDef *hpka);
+uint32_t HAL_PKA_GetError(PKA_HandleTypeDef *hpka);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(PKA) && defined(HAL_PKA_MODULE_ENABLED) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_PKA_H */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pssi.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pssi.h
new file mode 100644
index 00000000..6790e517
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pssi.h
@@ -0,0 +1,516 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_pssi.h
+ * @author MCD Application Team
+ * @brief Header file of PSSI HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_PSSI_H
+#define STM32U5xx_HAL_PSSI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+#if defined(PSSI)
+/** @addtogroup PSSI PSSI
+ * @brief PSSI HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup PSSI_Exported_Types PSSI Exported Types
+ * @{
+ */
+
+
+/**
+ * @brief PSSI Init structure definition
+ */
+typedef struct
+{
+ uint32_t DataWidth; /* !< Configures the parallel bus width 8 lines or 16 lines */
+ uint32_t BusWidth; /* !< Configures the parallel bus width 8 lines or 16 lines */
+ uint32_t ControlSignal; /* !< Configures Data enable and Data ready */
+ uint32_t ClockPolarity; /* !< Configures the PSSI Input Clock polarity */
+ uint32_t DataEnablePolarity; /* !< Configures the PSSI Data Enable polarity */
+ uint32_t ReadyPolarity; /* !< Configures the PSSI Ready polarity */
+
+} PSSI_InitTypeDef;
+
+
+/**
+ * @brief HAL PSSI State structures definition
+ */
+typedef enum
+{
+ HAL_PSSI_STATE_RESET = 0x00U, /* !< PSSI not yet initialized or disabled */
+ HAL_PSSI_STATE_READY = 0x01U, /* !< Peripheral initialized and ready for use */
+ HAL_PSSI_STATE_BUSY = 0x02U, /* !< An internal process is ongoing */
+ HAL_PSSI_STATE_BUSY_TX = 0x03U, /* !< Transmit process is ongoing */
+ HAL_PSSI_STATE_BUSY_RX = 0x04U, /* !< Receive process is ongoing */
+ HAL_PSSI_STATE_TIMEOUT = 0x05U, /* !< Timeout state */
+ HAL_PSSI_STATE_ERROR = 0x06U, /* !< PSSI state error */
+ HAL_PSSI_STATE_ABORT = 0x07U, /* !< PSSI process is aborted */
+
+} HAL_PSSI_StateTypeDef;
+
+/**
+ * @brief PSSI handle Structure definition
+ */
+typedef struct __PSSI_HandleTypeDef
+{
+ PSSI_TypeDef *Instance; /*!< PSSI register base address. */
+ PSSI_InitTypeDef Init; /*!< PSSI Initialization Structure. */
+ uint32_t *pBuffPtr; /*!< PSSI Data buffer. */
+ uint32_t XferCount; /*!< PSSI transfer count */
+ uint32_t XferSize; /*!< PSSI transfer size */
+ DMA_HandleTypeDef *hdmatx; /*!< PSSI Tx DMA Handle parameters */
+ DMA_HandleTypeDef *hdmarx; /*!< PSSI Rx DMA Handle parameters */
+
+ void (* TxCpltCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI transfer complete callback. */
+ void (* RxCpltCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI transfer complete callback. */
+ void (* ErrorCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI transfer complete callback. */
+ void (* AbortCpltCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI transfer error callback. */
+
+ void (* MspInitCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI Msp Init callback. */
+ void (* MspDeInitCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI Msp DeInit callback. */
+
+ HAL_LockTypeDef Lock; /*!< PSSI lock. */
+ __IO HAL_PSSI_StateTypeDef State; /*!< PSSI transfer state. */
+ __IO uint32_t ErrorCode; /*!< PSSI error code. */
+
+} PSSI_HandleTypeDef;
+
+
+/**
+ * @brief HAL PSSI Callback pointer definition
+ */
+typedef void (*pPSSI_CallbackTypeDef)(PSSI_HandleTypeDef *hpssi); /*!< Pointer to a PSSI common callback function */
+
+/**
+ * @brief HAL PSSI Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_PSSI_TX_COMPLETE_CB_ID = 0x00U, /*!< PSSI Tx Transfer completed callback ID */
+ HAL_PSSI_RX_COMPLETE_CB_ID = 0x01U, /*!< PSSI Rx Transfer completed callback ID */
+ HAL_PSSI_ERROR_CB_ID = 0x03U, /*!< PSSI Error callback ID */
+ HAL_PSSI_ABORT_CB_ID = 0x04U, /*!< PSSI Abort callback ID */
+
+ HAL_PSSI_MSPINIT_CB_ID = 0x05U, /*!< PSSI Msp Init callback ID */
+ HAL_PSSI_MSPDEINIT_CB_ID = 0x06U /*!< PSSI Msp DeInit callback ID */
+
+} HAL_PSSI_CallbackIDTypeDef;
+
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PSSI_Exported_Constants PSSI Exported Constants
+ * @{
+ */
+
+/** @defgroup PSSI_Error_Code PSSI Error Code
+ * @{
+ */
+#define HAL_PSSI_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_PSSI_ERROR_NOT_SUPPORTED 0x00000001U /*!< Not supported operation */
+#define HAL_PSSI_ERROR_UNDER_RUN 0x00000002U /*!< FIFO Under-run error */
+#define HAL_PSSI_ERROR_OVER_RUN 0x00000004U /*!< FIFO Over-run error */
+#define HAL_PSSI_ERROR_DMA 0x00000008U /*!< Dma error */
+#define HAL_PSSI_ERROR_TIMEOUT 0x00000010U /*!< Timeout error */
+#define HAL_PSSI_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid callback error */
+
+
+/**
+ * @}
+ */
+
+/** @defgroup PSSI_DATA_WIDTH PSSI Data Width
+ * @{
+ */
+
+#define HAL_PSSI_8BITS 0x00000000U /*!< 8 Bits */
+#define HAL_PSSI_16BITS 0x00000001U /*!< 16 Bits */
+#define HAL_PSSI_32BITS 0x00000002U /*!< 32 Bits */
+/**
+ * @}
+ */
+
+/** @defgroup PSSI_BUS_WIDTH PSSI Bus Width
+ * @{
+ */
+
+#define HAL_PSSI_8LINES 0x00000000U /*!< 8 data lines */
+#define HAL_PSSI_16LINES PSSI_CR_EDM /*!< 16 data lines */
+/**
+ * @}
+ */
+/** @defgroup PSSI_MODE PSSI mode
+ * @{
+ */
+#define HAL_PSSI_UNIDIRECTIONAL 0x00000000U /*!< Uni-directional mode */
+#define HAL_PSSI_BIDIRECTIONAL 0x00000001U /*!< Bi-directional mode */
+/**
+ * @}
+ */
+
+/** @defgroup ControlSignal_Configuration ControlSignal Configuration
+ * @{
+ */
+#define HAL_PSSI_DE_RDY_DISABLE (0x0U << PSSI_CR_DERDYCFG_Pos) /*!< Neither DE nor RDY are enabled */
+#define HAL_PSSI_RDY_ENABLE (0x1U << PSSI_CR_DERDYCFG_Pos) /*!< Only RDY enabled */
+#define HAL_PSSI_DE_ENABLE (0x2U << PSSI_CR_DERDYCFG_Pos) /*!< Only DE enabled */
+#define HAL_PSSI_DE_RDY_ALT_ENABLE (0x3U << PSSI_CR_DERDYCFG_Pos) /*!< Both RDY and DE alternate functions enabled */
+#define HAL_PSSI_MAP_RDY_BIDIR_ENABLE (0x4U << PSSI_CR_DERDYCFG_Pos) /*!< Bi-directional on RDY pin */
+#define HAL_PSSI_RDY_MAP_ENABLE (0x5U << PSSI_CR_DERDYCFG_Pos) /*!< Only RDY enabled, mapped to DE pin */
+#define HAL_PSSI_DE_MAP_ENABLE (0x6U << PSSI_CR_DERDYCFG_Pos) /*!< Only DE enabled, mapped to RDY pin */
+#define HAL_PSSI_MAP_DE_BIDIR_ENABLE (0x7U << PSSI_CR_DERDYCFG_Pos) /*!< Bi-directional on DE pin */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup Data_Enable_Polarity Data Enable Polarity
+ * @{
+ */
+#define HAL_PSSI_DEPOL_ACTIVE_LOW 0x0U /*!< Active Low */
+#define HAL_PSSI_DEPOL_ACTIVE_HIGH PSSI_CR_DEPOL /*!< Active High */
+/**
+ * @}
+ */
+/** @defgroup Reday_Polarity Reday Polarity
+ * @{
+ */
+#define HAL_PSSI_RDYPOL_ACTIVE_LOW 0x0U /*!< Active Low */
+#define HAL_PSSI_RDYPOL_ACTIVE_HIGH PSSI_CR_RDYPOL /*!< Active High */
+/**
+ * @}
+ */
+
+/** @defgroup Clock_Polarity Clock Polarity
+ * @{
+ */
+#define HAL_PSSI_FALLING_EDGE 0x0U /*!< Fallling Edge */
+#define HAL_PSSI_RISING_EDGE 0x1U /*!< Rising Edge */
+
+
+/**
+ * @}
+ */
+
+
+/** @defgroup PSSI_DEFINITION PSSI definitions
+ * @{
+ */
+
+#define PSSI_MAX_NBYTE_SIZE 0x10000U /* 64 KB */
+#define PSSI_TIMEOUT_TRANSMIT 0x0000FFFFU /*!< Timeout Value */
+
+#define PSSI_CR_OUTEN_INPUT 0x00000000U /*!< Input Mode */
+#define PSSI_CR_OUTEN_OUTPUT PSSI_CR_OUTEN /*!< Output Mode */
+
+#define PSSI_CR_DMA_ENABLE PSSI_CR_DMAEN /*!< DMA Mode Enable */
+#define PSSI_CR_DMA_DISABLE (~PSSI_CR_DMAEN) /*!< DMA Mode Disable*/
+
+#define PSSI_CR_16BITS PSSI_CR_EDM /*!< 16 Lines Mode */
+#define PSSI_CR_8BITS (~PSSI_CR_EDM) /*!< 8 Lines Mode */
+
+#define PSSI_FLAG_RTT1B PSSI_SR_RTT1B /*!< 1 Byte Fifo Flag*/
+#define PSSI_FLAG_RTT4B PSSI_SR_RTT4B /*!< 4 Bytes Fifo Flag*/
+
+
+
+/**
+ * @}
+ */
+
+/** @defgroup PSSI_Interrupts PSSI Interrupts
+ * @{
+ */
+
+#define PSSI_FLAG_OVR_RIS PSSI_RIS_OVR_RIS /*!< Overrun, Underrun errors flag */
+#define PSSI_FLAG_MASK PSSI_RIS_OVR_RIS_Msk /*!< Overrun, Underrun errors Mask */
+#define PSSI_FLAG_OVR_MIS PSSI_MIS_OVR_MIS /*!< Overrun, Underrun masked errors flag */
+/**
+ * @}
+ */
+
+
+
+/**
+ * @}
+ */
+/* Exported macros ------------------------------------------------------------*/
+/** @defgroup PSSI_Exported_Macros PSSI Exported Macros
+ * @{
+ */
+
+/** @brief Reset PSSI handle state
+ * @param __HANDLE__ specifies the PSSI handle.
+ * @retval None
+ */
+
+#define HAL_PSSI_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_PSSI_STATE_RESET;\
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ }while(0)
+
+
+/**
+ * @brief Enable the PSSI.
+ * @param __HANDLE__ PSSI handle
+ * @retval None.
+ */
+#define HAL_PSSI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= PSSI_CR_ENABLE)
+/**
+ * @brief Disable the PSSI.
+ * @param __HANDLE__ PSSI handle
+ * @retval None.
+ */
+#define HAL_PSSI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~PSSI_CR_ENABLE))
+
+/* PSSI pripheral STATUS */
+/**
+ * @brief Get the PSSI pending flags.
+ * @param __HANDLE__ PSSI handle
+ * @param __FLAG__ flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg PSSI_FLAG_RTT1B: FIFO is ready to transfer one byte
+ * @arg PSSI_FLAG_RTT4B: FIFO is ready to transfer four bytes
+ * @retval The state of FLAG.
+ */
+
+#define HAL_PSSI_GET_STATUS(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR & (__FLAG__))
+
+
+
+/* Interrupt & Flag management */
+/**
+ * @brief Get the PSSI pending flags.
+ * @param __HANDLE__ PSSI handle
+ * @param __FLAG__ flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg PSSI_FLAG_OVR_RIS: Data Buffer overrun/underrun error flag
+ * @retval The state of FLAG.
+ */
+#define HAL_PSSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->RIS & (__FLAG__))
+
+/**
+ * @brief Clear the PSSI pending flags.
+ * @param __HANDLE__ PSSI handle
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg PSSI_FLAG_OVR_RIS: Data Buffer overrun/underrun error flag
+ * @retval None
+ */
+#define HAL_PSSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/**
+ * @brief Enable the specified PSSI interrupts.
+ * @param __HANDLE__ PSSI handle
+ * @param __INTERRUPT__ specifies the PSSI interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg PSSI_FLAG_OVR_RIS: Configuration error mask
+ * @retval None
+ */
+#define HAL_PSSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the specified PSSI interrupts.
+ * @param __HANDLE__ PSSI handle
+ * @param __INTERRUPT__ specifies the PSSI interrupt sources to be disabled.
+ * This parameter can be any combination of the following values:
+ * @arg PSSI_IT_OVR_IE: Configuration error mask
+ * @retval None
+ */
+#define HAL_PSSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified PSSI interrupt source is enabled or not.
+ * @param __HANDLE__ PSSI handle
+ * @param __INTERRUPT__ specifies the PSSI interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg PSSI_IT_OVR_IE: Data Buffer overrun/underrun error interrupt mask
+ * @retval The state of INTERRUPT source.
+ */
+#define HAL_PSSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
+
+
+/**
+ * @brief Check whether the PSSI Control signal is valid.
+ * @param __CONTROL__ Control signals configuration
+ * @retval Valid or not.
+ */
+
+#define IS_PSSI_CONTROL_SIGNAL(__CONTROL__) (((__CONTROL__) == HAL_PSSI_DE_RDY_DISABLE ) || \
+ ((__CONTROL__) == HAL_PSSI_RDY_ENABLE ) || \
+ ((__CONTROL__) == HAL_PSSI_DE_ENABLE ) || \
+ ((__CONTROL__) == HAL_PSSI_DE_RDY_ALT_ENABLE ) || \
+ ((__CONTROL__) == HAL_PSSI_MAP_RDY_BIDIR_ENABLE ) || \
+ ((__CONTROL__) == HAL_PSSI_RDY_MAP_ENABLE ) || \
+ ((__CONTROL__) == HAL_PSSI_DE_MAP_ENABLE ) || \
+ ((__CONTROL__) == HAL_PSSI_MAP_DE_BIDIR_ENABLE ))
+
+
+
+/**
+ * @brief Check whether the PSSI Bus Width is valid.
+ * @param __BUSWIDTH__ PSSI Bush width
+ * @retval Valid or not.
+ */
+
+#define IS_PSSI_BUSWIDTH(__BUSWIDTH__) (((__BUSWIDTH__) == HAL_PSSI_8LINES ) || \
+ ((__BUSWIDTH__) == HAL_PSSI_16LINES ))
+
+/**
+ * @brief Check whether the PSSI Clock Polarity is valid.
+ * @param __CLOCKPOL__ PSSI Clock Polarity
+ * @retval Valid or not.
+ */
+
+#define IS_PSSI_CLOCK_POLARITY(__CLOCKPOL__) (((__CLOCKPOL__) == HAL_PSSI_FALLING_EDGE ) || \
+ ((__CLOCKPOL__) == HAL_PSSI_RISING_EDGE ))
+
+
+/**
+ * @brief Check whether the PSSI Data Enable Polarity is valid.
+ * @param __DEPOL__ PSSI DE Polarity
+ * @retval Valid or not.
+ */
+
+#define IS_PSSI_DE_POLARITY(__DEPOL__) (((__DEPOL__) == HAL_PSSI_DEPOL_ACTIVE_LOW ) || \
+ ((__DEPOL__) == HAL_PSSI_DEPOL_ACTIVE_HIGH ))
+
+/**
+ * @brief Check whether the PSSI Ready Polarity is valid.
+ * @param __RDYPOL__ PSSI RDY Polarity
+ * @retval Valid or not.
+ */
+
+#define IS_PSSI_RDY_POLARITY(__RDYPOL__) (((__RDYPOL__) == HAL_PSSI_RDYPOL_ACTIVE_LOW ) || \
+ ((__RDYPOL__) == HAL_PSSI_RDYPOL_ACTIVE_HIGH ))
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PSSI_Exported_Functions PSSI Exported Functions
+ * @{
+ */
+
+/** @addtogroup PSSI_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions *******************************/
+HAL_StatusTypeDef HAL_PSSI_Init(PSSI_HandleTypeDef *hpssi);
+HAL_StatusTypeDef HAL_PSSI_DeInit(PSSI_HandleTypeDef *hpssi);
+void HAL_PSSI_MspInit(PSSI_HandleTypeDef *hpssi);
+void HAL_PSSI_MspDeInit(PSSI_HandleTypeDef *hpssi);
+/* Callbacks Register/UnRegister functions ***********************************/
+
+HAL_StatusTypeDef HAL_PSSI_RegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID,
+ pPSSI_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID);
+
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup PSSI_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_PSSI_Transmit_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size);
+HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size);
+HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi);
+
+/**
+ * @}
+ */
+
+/** @addtogroup PSSI_Exported_Functions_Group3 Peripheral State and Error functions
+ * @{
+ */
+
+/* Peripheral State functions ***************************************************/
+HAL_PSSI_StateTypeDef HAL_PSSI_GetState(PSSI_HandleTypeDef *hpssi);
+uint32_t HAL_PSSI_GetError(PSSI_HandleTypeDef *hpssi);
+
+/**
+ * @}
+ */
+
+/** @addtogroup PSSI_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+
+void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi);
+void HAL_PSSI_TxCpltCallback(PSSI_HandleTypeDef *hpssi);
+void HAL_PSSI_RxCpltCallback(PSSI_HandleTypeDef *hpssi);
+void HAL_PSSI_ErrorCallback(PSSI_HandleTypeDef *hpssi);
+void HAL_PSSI_AbortCpltCallback(PSSI_HandleTypeDef *hpssi);
+
+
+/**
+ * @}
+ */
+
+
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+
+
+/* Private macros ------------------------------------------------------------*/
+
+
+/**
+ * @}
+ */
+#endif /* PSSI */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_PSSI_H */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pwr.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pwr.h
new file mode 100644
index 00000000..ac4a1efc
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pwr.h
@@ -0,0 +1,773 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_pwr.h
+ * @author MCD Application Team
+ * @brief Header file of PWR HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_PWR_H
+#define STM32U5xx_HAL_PWR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PWR
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Types PWR Exported Types
+ * @{
+ */
+
+/**
+ * @brief PWR PVD configuration structure definition
+ */
+typedef struct
+{
+ uint32_t PVDLevel; /*!< Specifies the PVD detection level.
+ This parameter can be a value of
+ @ref PWR_PVD_Detection_Level. */
+
+ uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref PWR_PVD_Mode. */
+} PWR_PVDTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Constants PWR Exported Constants
+ * @{
+ */
+
+/** @defgroup PWR_PVD_Detection_Level Programmable Voltage Detection Level
+ * @{
+ */
+#define PWR_PVDLEVEL_0 0x00000000UL /*!< PVD threshold around 2.0 V */
+#define PWR_PVDLEVEL_1 (PWR_SVMCR_PVDLS_0) /*!< PVD threshold around 2.2 V */
+#define PWR_PVDLEVEL_2 (PWR_SVMCR_PVDLS_1) /*!< PVD threshold around 2.4 V */
+#define PWR_PVDLEVEL_3 (PWR_SVMCR_PVDLS_0 | PWR_SVMCR_PVDLS_1) /*!< PVD threshold around 2.5 V */
+#define PWR_PVDLEVEL_4 (PWR_SVMCR_PVDLS_2) /*!< PVD threshold around 2.6 V */
+#define PWR_PVDLEVEL_5 (PWR_SVMCR_PVDLS_0 | PWR_SVMCR_PVDLS_2) /*!< PVD threshold around 2.8 V */
+#define PWR_PVDLEVEL_6 (PWR_SVMCR_PVDLS_1 | PWR_SVMCR_PVDLS_2) /*!< PVD threshold around 2.9 V */
+#define PWR_PVDLEVEL_7 (PWR_SVMCR_PVDLS) /*!< External input analog voltage
+ (compared internally to VREFINT) */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_PVD_Mode PWR PVD Mode
+ * @{
+ */
+#define PWR_PVD_MODE_NORMAL (0x00U) /*!< Basic Mode is used */
+#define PWR_PVD_MODE_IT_RISING (0x05U) /*!< External Interrupt Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_IT_FALLING (0x06U) /*!< External Interrupt Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_IT_RISING_FALLING (0x07U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING (0x09U) /*!< Event Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_EVENT_FALLING (0x0AU) /*!< Event Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x0BU) /*!< Event Mode with Rising/Falling edge trigger detection */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Regulator_In_LowPower_Mode PWR Regulator State in Sleep/Stop Mode
+ * @{
+ */
+#define PWR_MAINREGULATOR_ON (0x00U) /*!< Main Regulator ON in Run Mode */
+#define PWR_LOWPOWERREGULATOR_ON (0x00U) /*!< Main Regulator ON in Low Power Mode */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Sleep_Mode_Entry PWR Sleep Mode Entry
+ * @{
+ */
+#define PWR_SLEEPENTRY_WFI (0x01U) /*!< Wait For Interruption instruction to enter Sleep mode */
+#define PWR_SLEEPENTRY_WFE (0x02U) /*!< Wait For Event instruction to enter Sleep mode */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Stop_Mode_Entry PWR Stop Mode Entry
+ * @{
+ */
+#define PWR_STOPENTRY_WFI (0x01U) /*!< Wait For Interruption instruction to enter Stop mode */
+#define PWR_STOPENTRY_WFE (0x02U) /*!< Wait For Event instruction to enter Stop mode */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Flags PWR Flags
+ * @{
+ */
+#define PWR_FLAG_VOSRDY (0x01U) /*!< Voltage scaling ready flag */
+#define PWR_FLAG_BOOSTRDY (0x02U) /*!< EPOD booster ready flag */
+#define PWR_FLAG_STOPF (0x03U) /*!< Stop flag */
+#define PWR_FLAG_SBF (0x04U) /*!< Standby flag */
+#define PWR_FLAG_VDDA2RDY (0x05U) /*!< VDDA ready flag (versus 1.8 V threshold) */
+#define PWR_FLAG_VDDA1RDY (0x06U) /*!< VDDA ready flag (versus 1.6 V threshold) */
+#define PWR_FLAG_VDDIO2RDY (0x07U) /*!< VDDIO2 ready flag */
+#define PWR_FLAG_VDDUSBRDY (0x08U) /*!< VDDUSB ready flag */
+#define PWR_FLAG_ACTVOSRDY (0x09U) /*!< Currently applied VOS ready flag */
+#define PWR_FLAG_PVDO (0x0AU) /*!< VDD voltage detector output flag */
+#define PWR_FLAG_REGS (0x0BU) /*!< Regulator selection flag */
+#define PWR_FLAG_TEMPH (0x0CU) /*!< Temperature level flag (versus high threshold) */
+#define PWR_FLAG_TEMPL (0x0DU) /*!< Temperature level flag (versus low threshold) */
+#define PWR_FLAG_VBATH (0x0EU) /*!< Backup domain voltage level flag (versus high threshold) */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_WakeUp_Lines_Flags PWR Wakeup Lines Flags
+ * @{
+ */
+#define PWR_WAKEUP_FLAG1 (0x10U) /*!< Wakeup flag 1 */
+#define PWR_WAKEUP_FLAG2 (0x20U) /*!< Wakeup flag 2 */
+#define PWR_WAKEUP_FLAG3 (0x30U) /*!< Wakeup flag 3 */
+#define PWR_WAKEUP_FLAG4 (0x40U) /*!< Wakeup flag 4 */
+#define PWR_WAKEUP_FLAG5 (0x50U) /*!< Wakeup flag 5 */
+#define PWR_WAKEUP_FLAG6 (0x60U) /*!< Wakeup flag 6 */
+#define PWR_WAKEUP_FLAG7 (0x70U) /*!< Wakeup flag 7 */
+#define PWR_WAKEUP_FLAG8 (0x80U) /*!< Wakeup flag 8 */
+#define PWR_WAKEUP_ALL_FLAG (0x90U) /*!< Wakeup flag all */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_WakeUp_Pin_High_Polarity PWR Wake Up Pins High Polarity
+ * @{
+ */
+#define PWR_WAKEUP_PIN1_HIGH_0 (PWR_WUCR1_WUPEN1 | PWR_WAKEUP1_SOURCE_SELECTION_0) /*!< PA0 : Wakeup pin 1 (high polarity) */
+#define PWR_WAKEUP_PIN1_HIGH_1 (PWR_WUCR1_WUPEN1 | PWR_WAKEUP1_SOURCE_SELECTION_1) /*!< PB2 : Wakeup pin 1 (high polarity) */
+#define PWR_WAKEUP_PIN1_HIGH_2 (PWR_WUCR1_WUPEN1 | PWR_WAKEUP1_SOURCE_SELECTION_2) /*!< PE4 : Wakeup pin 1 (high polarity) */
+
+#define PWR_WAKEUP_PIN2_HIGH_0 (PWR_WUCR1_WUPEN2 | PWR_WAKEUP2_SOURCE_SELECTION_0) /*!< PA4 : Wakeup pin 2 (high polarity) */
+#define PWR_WAKEUP_PIN2_HIGH_1 (PWR_WUCR1_WUPEN2 | PWR_WAKEUP2_SOURCE_SELECTION_1) /*!< PC13 : Wakeup pin 2 (high polarity) */
+#define PWR_WAKEUP_PIN2_HIGH_2 (PWR_WUCR1_WUPEN2 | PWR_WAKEUP2_SOURCE_SELECTION_2) /*!< PE5 : Wakeup pin 2 (high polarity) */
+
+#define PWR_WAKEUP_PIN3_HIGH_0 (PWR_WUCR1_WUPEN3 | PWR_WAKEUP3_SOURCE_SELECTION_0) /*!< PE6 : Wakeup pin 3 (high polarity) */
+#define PWR_WAKEUP_PIN3_HIGH_1 (PWR_WUCR1_WUPEN3 | PWR_WAKEUP3_SOURCE_SELECTION_1) /*!< PA1 : Wakeup pin 3 (high polarity) */
+#define PWR_WAKEUP_PIN3_HIGH_2 (PWR_WUCR1_WUPEN3 | PWR_WAKEUP3_SOURCE_SELECTION_2) /*!< PB6 : Wakeup pin 3 (high polarity) */
+
+#define PWR_WAKEUP_PIN4_HIGH_0 (PWR_WUCR1_WUPEN4 | PWR_WAKEUP4_SOURCE_SELECTION_0) /*!< PA2 : Wakeup pin 4 (high polarity) */
+#define PWR_WAKEUP_PIN4_HIGH_1 (PWR_WUCR1_WUPEN4 | PWR_WAKEUP4_SOURCE_SELECTION_1) /*!< PB1 : Wakeup pin 4 (high polarity) */
+#define PWR_WAKEUP_PIN4_HIGH_2 (PWR_WUCR1_WUPEN4 | PWR_WAKEUP4_SOURCE_SELECTION_2) /*!< PB7 : Wakeup pin 4 (high polarity) */
+
+#define PWR_WAKEUP_PIN5_HIGH_0 (PWR_WUCR1_WUPEN5 | PWR_WAKEUP5_SOURCE_SELECTION_0) /*!< PC5 : Wakeup pin 5 (high polarity) */
+#define PWR_WAKEUP_PIN5_HIGH_1 (PWR_WUCR1_WUPEN5 | PWR_WAKEUP5_SOURCE_SELECTION_1) /*!< PA3 : Wakeup pin 5 (high polarity) */
+#define PWR_WAKEUP_PIN5_HIGH_2 (PWR_WUCR1_WUPEN5 | PWR_WAKEUP5_SOURCE_SELECTION_2) /*!< PB8 : Wakeup pin 5 (high polarity) */
+
+#define PWR_WAKEUP_PIN6_HIGH_0 (PWR_WUCR1_WUPEN6 | PWR_WAKEUP6_SOURCE_SELECTION_0) /*!< PB5 : Wakeup pin 6 (high polarity) */
+#define PWR_WAKEUP_PIN6_HIGH_1 (PWR_WUCR1_WUPEN6 | PWR_WAKEUP6_SOURCE_SELECTION_1) /*!< PA5 : Wakeup pin 6 (high polarity) */
+#define PWR_WAKEUP_PIN6_HIGH_2 (PWR_WUCR1_WUPEN6 | PWR_WAKEUP6_SOURCE_SELECTION_2) /*!< PE7 : Wakeup pin 6 (high polarity) */
+#define PWR_WAKEUP_PIN6_HIGH_3 (PWR_WUCR1_WUPEN6 | PWR_WAKEUP6_SOURCE_SELECTION_3) /*!< RTC : Wakeup pin 6 (high polarity) */
+
+#define PWR_WAKEUP_PIN7_HIGH_0 (PWR_WUCR1_WUPEN7 | PWR_WAKEUP7_SOURCE_SELECTION_0) /*!< PB15 : Wakeup pin 7 (high polarity) */
+#define PWR_WAKEUP_PIN7_HIGH_1 (PWR_WUCR1_WUPEN7 | PWR_WAKEUP7_SOURCE_SELECTION_1) /*!< PA6 : Wakeup pin 7 (high polarity) */
+#define PWR_WAKEUP_PIN7_HIGH_2 (PWR_WUCR1_WUPEN7 | PWR_WAKEUP7_SOURCE_SELECTION_2) /*!< PE8 : Wakeup pin 7 (high polarity) */
+#define PWR_WAKEUP_PIN7_HIGH_3 (PWR_WUCR1_WUPEN7 | PWR_WAKEUP7_SOURCE_SELECTION_3) /*!< RTC : Wakeup pin 7 (high polarity) */
+
+#define PWR_WAKEUP_PIN8_HIGH_0 (PWR_WUCR1_WUPEN8 | PWR_WAKEUP8_SOURCE_SELECTION_0) /*!< PF2 : Wakeup pin 8 (high polarity) */
+#define PWR_WAKEUP_PIN8_HIGH_1 (PWR_WUCR1_WUPEN8 | PWR_WAKEUP8_SOURCE_SELECTION_1) /*!< PA7 : Wakeup pin 8 (high polarity) */
+#define PWR_WAKEUP_PIN8_HIGH_2 (PWR_WUCR1_WUPEN8 | PWR_WAKEUP8_SOURCE_SELECTION_2) /*!< PB10 : Wakeup pin 8 (high polarity) */
+#define PWR_WAKEUP_PIN8_HIGH_3 (PWR_WUCR1_WUPEN8 | PWR_WAKEUP8_SOURCE_SELECTION_3) /*!< RTC : Wakeup pin 8 (high polarity) */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_WakeUp_Pin_Low_Polarity PWR Wake Up Pins Low Polarity
+ * @{
+ */
+#define PWR_WAKEUP_PIN1_LOW_0 (PWR_WUCR1_WUPEN1 | PWR_WAKEUP1_POLARITY_LOW | PWR_WAKEUP1_SOURCE_SELECTION_0) /*!< PA0 : Wakeup pin 1 (low polarity) */
+#define PWR_WAKEUP_PIN1_LOW_1 (PWR_WUCR1_WUPEN1 | PWR_WAKEUP1_POLARITY_LOW | PWR_WAKEUP1_SOURCE_SELECTION_1) /*!< PB2 : Wakeup pin 1 (low polarity) */
+#define PWR_WAKEUP_PIN1_LOW_2 (PWR_WUCR1_WUPEN1 | PWR_WAKEUP1_POLARITY_LOW | PWR_WAKEUP1_SOURCE_SELECTION_2) /*!< PE4 : Wakeup pin 1 (low polarity) */
+
+#define PWR_WAKEUP_PIN2_LOW_0 (PWR_WUCR1_WUPEN2 | PWR_WAKEUP2_POLARITY_LOW | PWR_WAKEUP2_SOURCE_SELECTION_0) /*!< PA4 : Wakeup pin 2 (low polarity) */
+#define PWR_WAKEUP_PIN2_LOW_1 (PWR_WUCR1_WUPEN2 | PWR_WAKEUP2_POLARITY_LOW | PWR_WAKEUP2_SOURCE_SELECTION_1) /*!< PC13 : Wakeup pin 2 (low polarity) */
+#define PWR_WAKEUP_PIN2_LOW_2 (PWR_WUCR1_WUPEN2 | PWR_WAKEUP2_POLARITY_LOW | PWR_WAKEUP2_SOURCE_SELECTION_2) /*!< PE5 : Wakeup pin 2 (low polarity) */
+
+#define PWR_WAKEUP_PIN3_LOW_0 (PWR_WUCR1_WUPEN3 | PWR_WAKEUP3_POLARITY_LOW | PWR_WAKEUP3_SOURCE_SELECTION_0) /*!< PE6 : Wakeup pin 3 (low polarity) */
+#define PWR_WAKEUP_PIN3_LOW_1 (PWR_WUCR1_WUPEN3 | PWR_WAKEUP3_POLARITY_LOW | PWR_WAKEUP3_SOURCE_SELECTION_1) /*!< PA1 : Wakeup pin 3 (low polarity) */
+#define PWR_WAKEUP_PIN3_LOW_2 (PWR_WUCR1_WUPEN3 | PWR_WAKEUP3_POLARITY_LOW | PWR_WAKEUP3_SOURCE_SELECTION_2) /*!< PB6 : Wakeup pin 3 (low polarity) */
+
+#define PWR_WAKEUP_PIN4_LOW_0 (PWR_WUCR1_WUPEN4 | PWR_WAKEUP4_POLARITY_LOW | PWR_WAKEUP4_SOURCE_SELECTION_0) /*!< PA2 : Wakeup pin 4 (low polarity) */
+#define PWR_WAKEUP_PIN4_LOW_1 (PWR_WUCR1_WUPEN4 | PWR_WAKEUP4_POLARITY_LOW | PWR_WAKEUP4_SOURCE_SELECTION_1) /*!< PB1 : Wakeup pin 4 (low polarity) */
+#define PWR_WAKEUP_PIN4_LOW_2 (PWR_WUCR1_WUPEN4 | PWR_WAKEUP4_POLARITY_LOW | PWR_WAKEUP4_SOURCE_SELECTION_2) /*!< PB7 : Wakeup pin 4 (low polarity) */
+
+#define PWR_WAKEUP_PIN5_LOW_0 (PWR_WUCR1_WUPEN5 | PWR_WAKEUP5_POLARITY_LOW | PWR_WAKEUP5_SOURCE_SELECTION_0) /*!< PC5 : Wakeup pin 5 (low polarity) */
+#define PWR_WAKEUP_PIN5_LOW_1 (PWR_WUCR1_WUPEN5 | PWR_WAKEUP5_POLARITY_LOW | PWR_WAKEUP5_SOURCE_SELECTION_1) /*!< PA3 : Wakeup pin 5 (low polarity) */
+#define PWR_WAKEUP_PIN5_LOW_2 (PWR_WUCR1_WUPEN5 | PWR_WAKEUP5_POLARITY_LOW | PWR_WAKEUP5_SOURCE_SELECTION_2) /*!< PB8 : Wakeup pin 5 (low polarity) */
+
+#define PWR_WAKEUP_PIN6_LOW_0 (PWR_WUCR1_WUPEN6 | PWR_WAKEUP6_POLARITY_LOW | PWR_WAKEUP6_SOURCE_SELECTION_0) /*!< PB5 : Wakeup pin 6 (low polarity) */
+#define PWR_WAKEUP_PIN6_LOW_1 (PWR_WUCR1_WUPEN6 | PWR_WAKEUP6_POLARITY_LOW | PWR_WAKEUP6_SOURCE_SELECTION_1) /*!< PA5 : Wakeup pin 6 (low polarity) */
+#define PWR_WAKEUP_PIN6_LOW_2 (PWR_WUCR1_WUPEN6 | PWR_WAKEUP6_POLARITY_LOW | PWR_WAKEUP6_SOURCE_SELECTION_2) /*!< PE7 : Wakeup pin 6 (low polarity) */
+#define PWR_WAKEUP_PIN6_LOW_3 (PWR_WUCR1_WUPEN6 | PWR_WAKEUP6_POLARITY_LOW | PWR_WAKEUP6_SOURCE_SELECTION_3) /*!< RTC : Wakeup pin 6 (low polarity) */
+
+#define PWR_WAKEUP_PIN7_LOW_0 (PWR_WUCR1_WUPEN7 | PWR_WAKEUP7_POLARITY_LOW | PWR_WAKEUP7_SOURCE_SELECTION_0) /*!< PB15 : Wakeup pin 7 (low polarity) */
+#define PWR_WAKEUP_PIN7_LOW_1 (PWR_WUCR1_WUPEN7 | PWR_WAKEUP7_POLARITY_LOW | PWR_WAKEUP7_SOURCE_SELECTION_1) /*!< PA6 : Wakeup pin 7 (low polarity) */
+#define PWR_WAKEUP_PIN7_LOW_2 (PWR_WUCR1_WUPEN7 | PWR_WAKEUP7_POLARITY_LOW | PWR_WAKEUP7_SOURCE_SELECTION_2) /*!< PE8 : Wakeup pin 7 (low polarity) */
+#define PWR_WAKEUP_PIN7_LOW_3 (PWR_WUCR1_WUPEN7 | PWR_WAKEUP7_POLARITY_LOW | PWR_WAKEUP7_SOURCE_SELECTION_3) /*!< RTC : Wakeup pin 7 (low polarity) */
+
+#define PWR_WAKEUP_PIN8_LOW_0 (PWR_WUCR1_WUPEN8 | PWR_WAKEUP8_POLARITY_LOW | PWR_WAKEUP8_SOURCE_SELECTION_0) /*!< PF2 : Wakeup pin 8 (low polarity) */
+#define PWR_WAKEUP_PIN8_LOW_1 (PWR_WUCR1_WUPEN8 | PWR_WAKEUP8_POLARITY_LOW | PWR_WAKEUP8_SOURCE_SELECTION_1) /*!< PA7 : Wakeup pin 8 (low polarity) */
+#define PWR_WAKEUP_PIN8_LOW_2 (PWR_WUCR1_WUPEN8 | PWR_WAKEUP8_POLARITY_LOW | PWR_WAKEUP8_SOURCE_SELECTION_2) /*!< PB10 : Wakeup pin 8 (low polarity) */
+#define PWR_WAKEUP_PIN8_LOW_3 (PWR_WUCR1_WUPEN8 | PWR_WAKEUP8_POLARITY_LOW | PWR_WAKEUP8_SOURCE_SELECTION_3) /*!< RTC : Wakeup pin 8 (low polarity) */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_WakeUp_Pins PWR Wake Up Pins (Default polarity and default pin selection)
+ * @{
+ */
+#define PWR_WAKEUP_PIN1 (PWR_WUCR1_WUPEN1) /*!< PA0 : Wakeup pin 1 (high polarity) */
+#define PWR_WAKEUP_PIN2 (PWR_WUCR1_WUPEN2) /*!< PA4 : Wakeup pin 2 (high polarity) */
+#define PWR_WAKEUP_PIN3 (PWR_WUCR1_WUPEN3) /*!< PE6 : Wakeup pin 3 (high polarity) */
+#define PWR_WAKEUP_PIN4 (PWR_WUCR1_WUPEN4) /*!< PA2 : Wakeup pin 4 (high polarity) */
+#define PWR_WAKEUP_PIN5 (PWR_WUCR1_WUPEN5) /*!< PC5 : Wakeup pin 5 (high polarity) */
+#define PWR_WAKEUP_PIN6 (PWR_WUCR1_WUPEN6) /*!< PB5 : Wakeup pin 6 (high polarity) */
+#define PWR_WAKEUP_PIN7 (PWR_WUCR1_WUPEN7) /*!< PB15 : Wakeup pin 7 (high polarity) */
+#define PWR_WAKEUP_PIN8 (PWR_WUCR1_WUPEN8) /*!< PF2 : Wakeup pin 8 (high polarity) */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Items PWR Items
+ * @{
+ */
+#define PWR_WKUP1 (PWR_SECCFGR_WUP1SEC) /*!< WUP1 secure protection */
+#define PWR_WKUP2 (PWR_SECCFGR_WUP2SEC) /*!< WUP2 secure protection */
+#define PWR_WKUP3 (PWR_SECCFGR_WUP3SEC) /*!< WUP3 secure protection */
+#define PWR_WKUP4 (PWR_SECCFGR_WUP4SEC) /*!< WUP4 secure protection */
+#define PWR_WKUP5 (PWR_SECCFGR_WUP5SEC) /*!< WUP5 secure protection */
+#define PWR_WKUP6 (PWR_SECCFGR_WUP6SEC) /*!< WUP6 secure protection */
+#define PWR_WKUP7 (PWR_SECCFGR_WUP7SEC) /*!< WUP7 secure protection */
+#define PWR_WKUP8 (PWR_SECCFGR_WUP8SEC) /*!< WUP8 secure protection */
+#define PWR_LPM (PWR_SECCFGR_LPMSEC) /*!< Low power modes secure protection */
+#define PWR_VDM (PWR_SECCFGR_VDMSEC) /*!< Voltage detection and monitoring secure protection */
+#define PWR_VB (PWR_SECCFGR_VBSEC) /*!< Backup domain secure protection */
+#define PWR_APC (PWR_SECCFGR_APCSEC) /*!< Pull-up/pull-down secure protection */
+#define PWR_ALL (PWR_WKUP1 | PWR_WKUP2 | PWR_WKUP3 | PWR_WKUP4 | \
+ PWR_WKUP5 | PWR_WKUP7 | PWR_WKUP6 | PWR_WKUP8 | \
+ PWR_LPM | PWR_VDM | PWR_VB | PWR_APC)
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Attributes PWR Attributes
+ * @brief PWR Privilege/NPrivilege and Secure/NSecure Attributes
+ * @{
+ */
+#define PWR_NSEC_PRIV (PWR_ITEM_ATTR_NSEC_PRIV_MASK | 0x01U) /*!< NSecure and Privileged attribute */
+#define PWR_NSEC_NPRIV (PWR_ITEM_ATTR_NSEC_PRIV_MASK) /*!< NSecure and NPrivileged attribute */
+#define PWR_SEC_PRIV (PWR_ITEM_ATTR_SEC_PRIV_MASK | 0x02U) /*!< Secure and Privileged attribute */
+#define PWR_SEC_NPRIV (PWR_ITEM_ATTR_SEC_PRIV_MASK) /*!< Secure and NPrivileged attribute */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Macros PWR Exported Macros
+ * @{
+ */
+
+/** @brief Check PWR flags are set or not.
+ * @param __FLAG__ : Specifies the flag to check.
+ * This parameter can be one of the following values :
+ * @arg @ref PWR_FLAG_VOSRDY : Voltage scaling ready flag.
+ * Indicates that the Vcore level at or above VOS selected level.
+ * @arg @ref PWR_FLAG_BOOSTRDY : EPOD booster ready flag.
+ * Indicates that EPOD booster ready,
+ * frequency could be higher than 50 MHz.
+ * @arg @ref PWR_FLAG_STOPF : Stop flag.
+ * Indicates that the device was resumed from Stop mode.
+ * @arg @ref PWR_FLAG_SBF : Standby flag.
+ * Indicates that the device was resumed from Standby mode.
+ * @arg @ref PWR_FLAG_VDDA2RDY : VDDA2 ready flag (versus 1.8 V threshold).
+ * Indicates that VDDA is equal or above the threshold
+ * of the VDDA voltage monitor 2 (around 1.8 V).
+ * @arg @ref PWR_FLAG_VDDA1RDY : VDDA1 ready flag (versus 1.6 V threshold).
+ * Indicates that VDDA is equal or above the threshold
+ * of the VDDA voltage monitor 1 (around 1.6 V).
+ * @arg @ref PWR_FLAG_VDDIO2RDY : VDDIO2 ready flag (versus 0.9 V threshold).
+ * Indicates that VDDIO2 is equal or above the threshold
+ * of the VDDIO2 voltage monitor (around 0.9 V).
+ * @arg @ref PWR_FLAG_VDDUSBRDY : VDDUSB ready flag (versus 1.2 V threshold).
+ * Indicates that VDDUSB is equal or above the threshold
+ * of the VDDUSB voltage monitor (around 1.2 V).
+ * @arg @ref PWR_FLAG_ACTVOSRDY : Currently applied VOS ready flag.
+ * Indicates that Vcore is equal to the current
+ * voltage scaling provided by ACTVOS.
+ * @arg @ref PWR_FLAG_PVDO VDD : Voltage detector output flag.
+ * Indicates that Vdd is equal or above
+ * the PVD threshold selected by PVDLS.
+ * @arg @ref PWR_FLAG_REGS : Regulator selection flag.
+ * Indicates the regulator selected.
+ * @arg @ref PWR_FLAG_TEMPH : Temperature level flag (versus high threshold).
+ * Indicates the temperature is equal or above high threshold.
+ * @arg @ref PWR_FLAG_TEMPL : Temperature level flag (versus low threshold).
+ * Indicates the temperature is equal or above low threshold.
+ * @arg @ref PWR_FLAG_VBATH : Backup domain voltage level flag (versus high threshold).
+ * Indicates the backup domain voltage
+ * level is equal or above high threshold.
+ * @arg @ref PWR_WAKEUP_FLAG1 : Wakeup flag 1.
+ * Indicates that a wakeup event was received from the WKUP line 1.
+ * @arg @ref PWR_WAKEUP_FLAG2 : Wakeup flag 2.
+ * Indicates that a wakeup event was received from the WKUP line 2.
+ * @arg @ref PWR_WAKEUP_FLAG3 : Wakeup flag 3.
+ * Indicates that a wakeup event was received from the WKUP line 3.
+ * @arg @ref PWR_WAKEUP_FLAG4 : Wakeup flag 4.
+ * Indicates that a wakeup event was received from the WKUP line 4.
+ * @arg @ref PWR_WAKEUP_FLAG5 : Wakeup flag 5.
+ * Indicates that a wakeup event was received from the WKUP line 5.
+ * @arg @ref PWR_WAKEUP_FLAG6 : Wakeup flag 6.
+ * Indicates that a wakeup event was received from the WKUP line 6.
+ * @arg @ref PWR_WAKEUP_FLAG7 : Wakeup flag 7.
+ * Indicates that a wakeup event was received from the WKUP line 7.
+ * @arg @ref PWR_WAKEUP_FLAG8 : Wakeup flag 8.
+ * Indicates that a wakeup event was received from the WKUP line 8.
+ * @retval The state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_PWR_GET_FLAG(__FLAG__) \
+ ( \
+ ((__FLAG__) == PWR_FLAG_VOSRDY) ? (READ_BIT(PWR->VOSR, PWR_VOSR_VOSRDY) == PWR_VOSR_VOSRDY) : \
+ ((__FLAG__) == PWR_FLAG_BOOSTRDY) ? (READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTRDY) == PWR_VOSR_BOOSTRDY) : \
+ ((__FLAG__) == PWR_FLAG_STOPF) ? (READ_BIT(PWR->SR, PWR_SR_STOPF) == PWR_SR_STOPF) : \
+ ((__FLAG__) == PWR_FLAG_SBF) ? (READ_BIT(PWR->SR, PWR_SR_SBF) == PWR_SR_SBF) : \
+ ((__FLAG__) == PWR_FLAG_VDDA2RDY) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDA2RDY) == PWR_SVMSR_VDDA2RDY) : \
+ ((__FLAG__) == PWR_FLAG_VDDA1RDY) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDA1RDY) == PWR_SVMSR_VDDA1RDY) : \
+ ((__FLAG__) == PWR_FLAG_VDDIO2RDY) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDIO2RDY) == PWR_SVMSR_VDDIO2RDY) : \
+ ((__FLAG__) == PWR_FLAG_VDDUSBRDY) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDUSBRDY) == PWR_SVMSR_VDDUSBRDY) : \
+ ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY) == PWR_SVMSR_ACTVOSRDY) : \
+ ((__FLAG__) == PWR_FLAG_PVDO) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_PVDO) == PWR_SVMSR_PVDO) : \
+ ((__FLAG__) == PWR_FLAG_REGS) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_REGS) == PWR_SVMSR_REGS) : \
+ ((__FLAG__) == PWR_FLAG_TEMPH) ? (READ_BIT(PWR->BDSR, PWR_BDSR_TEMPH) == PWR_BDSR_TEMPH) : \
+ ((__FLAG__) == PWR_FLAG_TEMPL) ? (READ_BIT(PWR->BDSR, PWR_BDSR_TEMPL) == PWR_BDSR_TEMPL) : \
+ ((__FLAG__) == PWR_FLAG_VBATH) ? (READ_BIT(PWR->BDSR, PWR_BDSR_VBATH) == PWR_BDSR_VBATH) : \
+ ((__FLAG__) == PWR_WAKEUP_FLAG1) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) == PWR_WUSR_WUF1) : \
+ ((__FLAG__) == PWR_WAKEUP_FLAG2) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) == PWR_WUSR_WUF2) : \
+ ((__FLAG__) == PWR_WAKEUP_FLAG3) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) == PWR_WUSR_WUF3) : \
+ ((__FLAG__) == PWR_WAKEUP_FLAG4) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) == PWR_WUSR_WUF4) : \
+ ((__FLAG__) == PWR_WAKEUP_FLAG5) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) == PWR_WUSR_WUF5) : \
+ ((__FLAG__) == PWR_WAKEUP_FLAG6) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) == PWR_WUSR_WUF6) : \
+ ((__FLAG__) == PWR_WAKEUP_FLAG7) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) == PWR_WUSR_WUF7) : \
+ (READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == PWR_WUSR_WUF8))
+
+/** @brief Clear PWR flags.
+ * @param __FLAG__ : Specifies the flag to clear.
+ * This parameter can be one of the following values :
+ * @arg @ref PWR_FLAG_STOPF : Stop flag.
+ * Indicates that the device was resumed from Stop mode.
+ * @arg @ref PWR_FLAG_SBF : Standby flag.
+ * Indicates that the device was resumed from Standby mode.
+ * @arg @ref PWR_WAKEUP_FLAG1 : Wakeup flag 1.
+ * Indicates that a wakeup event was received from the WKUP line 1.
+ * @arg @ref PWR_WAKEUP_FLAG2 : Wakeup flag 2.
+ * Indicates that a wakeup event was received from the WKUP line 2.
+ * @arg @ref PWR_WAKEUP_FLAG3 : Wakeup flag 3.
+ * Indicates that a wakeup event was received from the WKUP line 3.
+ * @arg @ref PWR_WAKEUP_FLAG4 : Wakeup flag 4.
+ * Indicates that a wakeup event was received from the WKUP line 4.
+ * @arg @ref PWR_WAKEUP_FLAG5 : Wakeup flag 5.
+ * Indicates that a wakeup event was received from the WKUP line 5.
+ * @arg @ref PWR_WAKEUP_FLAG6 : Wakeup flag 6.
+ * Indicates that a wakeup event was received from the WKUP line 6.
+ * @arg @ref PWR_WAKEUP_FLAG7 : Wakeup flag 7.
+ * Indicates that a wakeup event was received from the WKUP line 7.
+ * @arg @ref PWR_WAKEUP_FLAG8 : Wakeup flag 8.
+ * Indicates that a wakeup event was received from the WKUP line 8.
+ * @retval None.
+ */
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__) \
+ ( \
+ ((__FLAG__) == PWR_FLAG_STOPF) ? (SET_BIT(PWR->SR, PWR_SR_CSSF)) : \
+ ((__FLAG__) == PWR_FLAG_SBF) ? (SET_BIT(PWR->SR, PWR_SR_CSSF)) : \
+ ((__FLAG__) == PWR_WAKEUP_FLAG1) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF1)) : \
+ ((__FLAG__) == PWR_WAKEUP_FLAG2) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF2)) : \
+ ((__FLAG__) == PWR_WAKEUP_FLAG3) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF3)) : \
+ ((__FLAG__) == PWR_WAKEUP_FLAG4) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF4)) : \
+ ((__FLAG__) == PWR_WAKEUP_FLAG5) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF5)) : \
+ ((__FLAG__) == PWR_WAKEUP_FLAG6) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF6)) : \
+ ((__FLAG__) == PWR_WAKEUP_FLAG7) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF7)) : \
+ ((__FLAG__) == PWR_WAKEUP_FLAG8) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF8)) : \
+ (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF)))
+
+/**
+ * @brief Enable the PVD Extended Interrupt Line.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Disable the PVD Extended Interrupt Line.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Enable the PVD Event Line.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Disable the PVD Event Line.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Enable the PVD Extended Interrupt Rising Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Disable the PVD Extended Interrupt Rising Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Enable the PVD Extended Interrupt Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Disable the PVD Extended Interrupt Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
+ do \
+ { \
+ __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \
+ } while(0)
+
+/**
+ * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
+ do \
+ { \
+ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0)
+
+/**
+ * @brief Generate a Software Interrupt on selected EXTI line.
+ * @retval None
+ */
+#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Check whether or not the PVD EXTI Interrupt flag is set.
+ * @retval EXTI PVD Line Status.
+ */
+#define __HAL_PWR_PVD_EXTI_GET_FLAG() ((EXTI->RPR1 | EXTI->FPR1) & PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Clear the PVD EXTI Interrupt flag.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() \
+ do \
+ { \
+ WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_PVD); \
+ WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_PVD); \
+ } while(0)
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+
+/** @addtogroup PWR_Private_Constants PWR Private Constants
+ * @{
+ */
+/* Define PVD extended interrupts and event line */
+#define PWR_EXTI_LINE_PVD (0x00010000UL) /*!< PVD EXTI Line */
+
+/* Defines wake up lines shift */
+#define PWR_WUP_POLARITY_SHIFT (0x08U) /*!< Internal constant used to retrieve wakeup signal polarity */
+#define PWR_WUP_SELECT_SIGNAL_SHIFT (0x10U) /*!< Internal constant used to retrieve wakeup signal selection */
+
+/* Defines wake up lines mask */
+#define PWR_EWUP_MASK (0x000000FFUL) /*!< Internal constant used to retrieve wakeup signal enable */
+#define PWR_WUP_POLARITY_MASK (0x0000FF00UL) /*!< Internal constant used to retrieve wakeup signal polarity */
+#define PWR_WUP_SELECT_MASK (0xFFFF0000UL) /*!< Internal constant used to retrieve wakeup signal selection */
+
+/* Defines wake up lines selection */
+#define PWR_WAKEUP1_SOURCE_SELECTION_0 (0U)
+#define PWR_WAKEUP1_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL1_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */
+#define PWR_WAKEUP1_SOURCE_SELECTION_2 (PWR_WUCR3_WUSEL1_1 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */
+#define PWR_WAKEUP2_SOURCE_SELECTION_0 (0U) /*!< Internal constant used to retrieve wakeup signal selection */
+#define PWR_WAKEUP2_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL2_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */
+#define PWR_WAKEUP2_SOURCE_SELECTION_2 (PWR_WUCR3_WUSEL2_1 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */
+#define PWR_WAKEUP3_SOURCE_SELECTION_0 (0U) /*!< Internal constant used to retrieve wakeup signal selection */
+#define PWR_WAKEUP3_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL3_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */
+#define PWR_WAKEUP3_SOURCE_SELECTION_2 (PWR_WUCR3_WUSEL3_1 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */
+#define PWR_WAKEUP4_SOURCE_SELECTION_0 (0U) /*!< Internal constant used to retrieve wakeup signal selection */
+#define PWR_WAKEUP4_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL4_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */
+#define PWR_WAKEUP4_SOURCE_SELECTION_2 (PWR_WUCR3_WUSEL4_1 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */
+#define PWR_WAKEUP5_SOURCE_SELECTION_0 (0U) /*!< Internal constant used to retrieve wakeup signal selection */
+#define PWR_WAKEUP5_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL5_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */
+#define PWR_WAKEUP5_SOURCE_SELECTION_2 (PWR_WUCR3_WUSEL5_1 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */
+#define PWR_WAKEUP6_SOURCE_SELECTION_0 (0U) /*!< Internal constant used to retrieve wakeup signal selection */
+#define PWR_WAKEUP6_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL6_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */
+#define PWR_WAKEUP6_SOURCE_SELECTION_2 (PWR_WUCR3_WUSEL6_1 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */
+#define PWR_WAKEUP6_SOURCE_SELECTION_3 ((PWR_WUCR3_WUSEL6_0 | PWR_WUCR3_WUSEL6_1) << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */
+#define PWR_WAKEUP7_SOURCE_SELECTION_0 (0U) /*!< Internal constant used to retrieve wakeup signal selection */
+#define PWR_WAKEUP7_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL7_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */
+#define PWR_WAKEUP7_SOURCE_SELECTION_2 (PWR_WUCR3_WUSEL7_1 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */
+#define PWR_WAKEUP7_SOURCE_SELECTION_3 ((PWR_WUCR3_WUSEL7_0 | PWR_WUCR3_WUSEL7_1) << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */
+#define PWR_WAKEUP8_SOURCE_SELECTION_0 (0U) /*!< Internal constant used to retrieve wakeup signal selection */
+#define PWR_WAKEUP8_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL8_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */
+#define PWR_WAKEUP8_SOURCE_SELECTION_2 (PWR_WUCR3_WUSEL8_1 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */
+#define PWR_WAKEUP8_SOURCE_SELECTION_3 ((PWR_WUCR3_WUSEL8_0 | PWR_WUCR3_WUSEL8_1) << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */
+
+/* Defines wake up lines low polarity */
+#define PWR_WAKEUP1_POLARITY_LOW (PWR_WUCR2_WUPP1 << PWR_WUP_POLARITY_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */
+#define PWR_WAKEUP2_POLARITY_LOW (PWR_WUCR2_WUPP2 << PWR_WUP_POLARITY_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */
+#define PWR_WAKEUP3_POLARITY_LOW (PWR_WUCR2_WUPP3 << PWR_WUP_POLARITY_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */
+#define PWR_WAKEUP4_POLARITY_LOW (PWR_WUCR2_WUPP4 << PWR_WUP_POLARITY_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */
+#define PWR_WAKEUP5_POLARITY_LOW (PWR_WUCR2_WUPP5 << PWR_WUP_POLARITY_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */
+#define PWR_WAKEUP6_POLARITY_LOW (PWR_WUCR2_WUPP6 << PWR_WUP_POLARITY_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */
+#define PWR_WAKEUP7_POLARITY_LOW (PWR_WUCR2_WUPP7 << PWR_WUP_POLARITY_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */
+#define PWR_WAKEUP8_POLARITY_LOW (PWR_WUCR2_WUPP8 << PWR_WUP_POLARITY_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */
+
+/* Defines attribute */
+#define PWR_ITEM_ATTR_NSEC_PRIV_MASK (0x10U) /*!< NSecure Privilege / NPrivilege attribute item mask */
+#define PWR_ITEM_ATTR_SEC_PRIV_MASK (0x20U) /*!< Secure Privilege / NPrivilege attribute item mask */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup PWR_Private_Macros PWR Private Macros
+ * @{
+ */
+/* Wake up pins check macro */
+#define IS_PWR_WAKEUP_PIN(PIN) \
+ (((PIN) == PWR_WAKEUP_PIN1_HIGH_0) ||\
+ ((PIN) == PWR_WAKEUP_PIN1_HIGH_1) ||\
+ ((PIN) == PWR_WAKEUP_PIN1_HIGH_2) ||\
+ ((PIN) == PWR_WAKEUP_PIN2_HIGH_0) ||\
+ ((PIN) == PWR_WAKEUP_PIN2_HIGH_1) ||\
+ ((PIN) == PWR_WAKEUP_PIN2_HIGH_2) ||\
+ ((PIN) == PWR_WAKEUP_PIN3_HIGH_0) ||\
+ ((PIN) == PWR_WAKEUP_PIN3_HIGH_1) ||\
+ ((PIN) == PWR_WAKEUP_PIN3_HIGH_2) ||\
+ ((PIN) == PWR_WAKEUP_PIN4_HIGH_0) ||\
+ ((PIN) == PWR_WAKEUP_PIN4_HIGH_1) ||\
+ ((PIN) == PWR_WAKEUP_PIN4_HIGH_2) ||\
+ ((PIN) == PWR_WAKEUP_PIN5_HIGH_0) ||\
+ ((PIN) == PWR_WAKEUP_PIN5_HIGH_1) ||\
+ ((PIN) == PWR_WAKEUP_PIN5_HIGH_2) ||\
+ ((PIN) == PWR_WAKEUP_PIN6_HIGH_0) ||\
+ ((PIN) == PWR_WAKEUP_PIN6_HIGH_1) ||\
+ ((PIN) == PWR_WAKEUP_PIN6_HIGH_2) ||\
+ ((PIN) == PWR_WAKEUP_PIN6_HIGH_3) ||\
+ ((PIN) == PWR_WAKEUP_PIN7_HIGH_0) ||\
+ ((PIN) == PWR_WAKEUP_PIN7_HIGH_1) ||\
+ ((PIN) == PWR_WAKEUP_PIN7_HIGH_2) ||\
+ ((PIN) == PWR_WAKEUP_PIN7_HIGH_3) ||\
+ ((PIN) == PWR_WAKEUP_PIN8_HIGH_0) ||\
+ ((PIN) == PWR_WAKEUP_PIN8_HIGH_1) ||\
+ ((PIN) == PWR_WAKEUP_PIN8_HIGH_2) ||\
+ ((PIN) == PWR_WAKEUP_PIN8_HIGH_3) ||\
+ ((PIN) == PWR_WAKEUP_PIN1_LOW_0) ||\
+ ((PIN) == PWR_WAKEUP_PIN1_LOW_1) ||\
+ ((PIN) == PWR_WAKEUP_PIN1_LOW_2) ||\
+ ((PIN) == PWR_WAKEUP_PIN2_LOW_0) ||\
+ ((PIN) == PWR_WAKEUP_PIN2_LOW_1) ||\
+ ((PIN) == PWR_WAKEUP_PIN2_LOW_2) ||\
+ ((PIN) == PWR_WAKEUP_PIN3_LOW_0) ||\
+ ((PIN) == PWR_WAKEUP_PIN3_LOW_1) ||\
+ ((PIN) == PWR_WAKEUP_PIN3_LOW_2) ||\
+ ((PIN) == PWR_WAKEUP_PIN4_LOW_0) ||\
+ ((PIN) == PWR_WAKEUP_PIN4_LOW_1) ||\
+ ((PIN) == PWR_WAKEUP_PIN4_LOW_2) ||\
+ ((PIN) == PWR_WAKEUP_PIN5_LOW_0) ||\
+ ((PIN) == PWR_WAKEUP_PIN5_LOW_1) ||\
+ ((PIN) == PWR_WAKEUP_PIN5_LOW_2) ||\
+ ((PIN) == PWR_WAKEUP_PIN6_LOW_0) ||\
+ ((PIN) == PWR_WAKEUP_PIN6_LOW_1) ||\
+ ((PIN) == PWR_WAKEUP_PIN6_LOW_2) ||\
+ ((PIN) == PWR_WAKEUP_PIN6_LOW_3) ||\
+ ((PIN) == PWR_WAKEUP_PIN7_LOW_0) ||\
+ ((PIN) == PWR_WAKEUP_PIN7_LOW_1) ||\
+ ((PIN) == PWR_WAKEUP_PIN7_LOW_2) ||\
+ ((PIN) == PWR_WAKEUP_PIN7_LOW_3) ||\
+ ((PIN) == PWR_WAKEUP_PIN8_LOW_0) ||\
+ ((PIN) == PWR_WAKEUP_PIN8_LOW_1) ||\
+ ((PIN) == PWR_WAKEUP_PIN8_LOW_2) ||\
+ ((PIN) == PWR_WAKEUP_PIN8_LOW_3) ||\
+ ((PIN) == PWR_WAKEUP_PIN1) ||\
+ ((PIN) == PWR_WAKEUP_PIN2) ||\
+ ((PIN) == PWR_WAKEUP_PIN3) ||\
+ ((PIN) == PWR_WAKEUP_PIN4) ||\
+ ((PIN) == PWR_WAKEUP_PIN5) ||\
+ ((PIN) == PWR_WAKEUP_PIN6) ||\
+ ((PIN) == PWR_WAKEUP_PIN7) ||\
+ ((PIN) == PWR_WAKEUP_PIN8))
+
+/* PVD level check macro */
+#define IS_PWR_PVD_LEVEL(LEVEL) \
+ (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1) ||\
+ ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3) ||\
+ ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5) ||\
+ ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
+
+/* PVD mode check macro */
+#define IS_PWR_PVD_MODE(MODE) \
+ (((MODE) == PWR_PVD_MODE_NORMAL) ||\
+ ((MODE) == PWR_PVD_MODE_IT_RISING) ||\
+ ((MODE) == PWR_PVD_MODE_IT_FALLING) ||\
+ ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) ||\
+ ((MODE) == PWR_PVD_MODE_EVENT_RISING) ||\
+ ((MODE) == PWR_PVD_MODE_EVENT_FALLING) ||\
+ ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING))
+
+/* Sleep mode entry check macro */
+#define IS_PWR_SLEEP_ENTRY(ENTRY) \
+ (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
+
+/* Stop mode entry check macro */
+#define IS_PWR_STOP_ENTRY(ENTRY) \
+ (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
+
+/* PWR items check macro */
+#define IS_PWR_ITEMS_ATTRIBUTES(ITEM) \
+ ((((ITEM) & (~PWR_ALL)) == 0U) && ((ITEM) != 0U))
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/* PWR attribute check macro (Secure) */
+#define IS_PWR_ATTRIBUTES(ATTRIBUTES) \
+ ((((~(((ATTRIBUTES) & 0xF0U) >> 4U)) & ((ATTRIBUTES) & 0x0FU)) == 0U) && (((ATTRIBUTES) & 0xFFFFFFCCU) == 0U))
+#else
+/* PWR attribute check macro (NSecure) */
+#define IS_PWR_ATTRIBUTES(ATTRIBUTES) \
+ (((ATTRIBUTES) == PWR_NSEC_NPRIV) || ((ATTRIBUTES) == PWR_NSEC_PRIV))
+#endif /* __ARM_FEATURE_CMSE */
+/**
+ * @}
+ */
+
+/* Include PWR HAL Extended module */
+#include "stm32u5xx_hal_pwr_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup PWR_Exported_Functions PWR Exported Functions
+ * @{
+ */
+
+/** @addtogroup PWR_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+void HAL_PWR_DeInit(void);
+void HAL_PWR_EnableBkUpAccess(void);
+void HAL_PWR_DisableBkUpAccess(void);
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Exported_Functions_Group2
+ * @{
+ */
+/* Programmable voltage detector functions ************************************/
+HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *pConfigPVD);
+void HAL_PWR_EnablePVD(void);
+void HAL_PWR_DisablePVD(void);
+
+/* Wake up pins configuration functions ***************************************/
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPin);
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPin);
+
+/* Low power modes configuration functions ************************************/
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SleepEntry);
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t StopEntry);
+void HAL_PWR_EnterSTANDBYMode(void);
+
+/* Sleep on exit and sev on pending configuration functions *******************/
+void HAL_PWR_EnableSleepOnExit(void);
+void HAL_PWR_DisableSleepOnExit(void);
+void HAL_PWR_EnableSEVOnPend(void);
+void HAL_PWR_DisableSEVOnPend(void);
+
+/* Interrupt handler functions ************************************************/
+void HAL_PWR_PVD_IRQHandler(void);
+void HAL_PWR_PVDCallback(void);
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Exported_Functions_Group3
+ * @{
+ */
+/* Privileges and security configuration functions ****************************/
+void HAL_PWR_ConfigAttributes(uint32_t Item, uint32_t Attributes);
+HAL_StatusTypeDef HAL_PWR_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* STM32U5xx_HAL_PWR_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pwr_ex.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pwr_ex.h
new file mode 100644
index 00000000..88c5d5fe
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pwr_ex.h
@@ -0,0 +1,929 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_pwr_ex.h
+ * @author MCD Application Team
+ * @brief Header file of PWR HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_PWR_EX_H
+#define STM32U5xx_HAL_PWR_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PWREx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup PWREx_Exported_Types PWR Extended Exported Types
+ * @{
+ */
+
+/**
+ * @brief PWR PVM configuration structure definition
+ */
+typedef struct
+{
+ uint32_t PVMType; /*!< Specifies which voltage is monitored.
+ This parameter can be a value of
+ @ref PWREx_PVM_Type. */
+
+ uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
+ This parameter can be a value of
+ @ref PWREx_PVM_Mode. */
+} PWR_PVMTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants
+ * @{
+ */
+
+/** @defgroup PWREx_PVM_Type PWR Extended Voltage Monitoring Type
+ * @{
+ */
+#define PWR_UVM PWR_SVMCR_UVMEN /*!< Independent USB voltage monitor (VDDUSB versus 1.2 V) */
+#define PWR_IO2VM PWR_SVMCR_IO2VMEN /*!< Independent VDDIO2 voltage monitor (VDDIO2 versus 0.9 V) */
+#define PWR_AVM1 PWR_SVMCR_AVM1EN /*!< Independent VDDA voltage monitor (VDDA versus 1.6 V) */
+#define PWR_AVM2 PWR_SVMCR_AVM2EN /*!< Independent VDDA voltage monitor (VDDA versus 1.8 V) */
+/**
+ * @}
+ */
+
+/** @defgroup PWREx_PVM_Mode PWR Extended PVM Interrupt and Event Mode
+ * @{
+ */
+#define PWR_PVM_MODE_NORMAL (0x00U) /*!< Basic Mode is used */
+#define PWR_PVM_MODE_IT_RISING (0x05U) /*!< External Interrupt Mode with Rising edge trigger detection */
+#define PWR_PVM_MODE_IT_FALLING (0x06U) /*!< External Interrupt Mode with Falling edge trigger detection */
+#define PWR_PVM_MODE_IT_RISING_FALLING (0x07U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_PVM_MODE_EVENT_RISING (0x09U) /*!< Event Mode with Rising edge trigger detection */
+#define PWR_PVM_MODE_EVENT_FALLING (0x0AU) /*!< Event Mode with Falling edge trigger detection */
+#define PWR_PVM_MODE_EVENT_RISING_FALLING (0x0BU) /*!< Event Mode with Rising/Falling edge trigger detection */
+/**
+ * @}
+ */
+
+/** @defgroup PWREx_SRD_State PWREx SRD Domain State
+ * @{
+ */
+#define PWR_SRD_DOMAIN_STOP (0U) /*!< SRD in Stop mode when system goes to Stop 0/1/2 mode */
+#define PWR_SRD_DOMAIN_RUN PWR_CR2_SRDRUN /*!< SRD in Run mode when system goes to Stop 0/1/2 mode */
+/**
+ * @}
+ */
+
+/** @defgroup PWREx_RAM_Contents_Stop_Retention PWR Extended RAM Contents Stop Retention
+ * @{
+ */
+/* SRAM1 pages retention defines */
+#define PWR_SRAM1_PAGE1_STOP_RETENTION (SRAM1_ID | PAGE01_ID) /*!< SRAM1 page 1 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM1_PAGE2_STOP_RETENTION (SRAM1_ID | PAGE02_ID) /*!< SRAM1 page 2 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM1_PAGE3_STOP_RETENTION (SRAM1_ID | PAGE03_ID) /*!< SRAM1 page 3 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM1_FULL_STOP_RETENTION (SRAM1_ID | 0x07U) /*!< SRAM1 all pages retention in Stop modes (Stop 0, 1, 2, 3) */
+
+/* SRAM2 pages retention defines */
+#define PWR_SRAM2_PAGE1_STOP_RETENTION (SRAM2_ID | PAGE01_ID) /*!< SRAM2 page 1 (8 KB) retention in Stop modes (Stop 0, 1, 2) */
+#define PWR_SRAM2_PAGE2_STOP_RETENTION (SRAM2_ID | PAGE02_ID) /*!< SRAM2 page 2 (54 KB) retention in Stop modes (Stop 0, 1, 2) */
+#define PWR_SRAM2_FULL_STOP_RETENTION (SRAM2_ID | 0x03U) /*!< SRAM2 all pages retention in Stop modes (Stop 0, 1, 2) */
+
+/* SRAM3 pages retention defines */
+#define PWR_SRAM3_PAGE1_STOP_RETENTION (SRAM3_ID | PAGE01_ID) /*!< SRAM3 page 1 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM3_PAGE2_STOP_RETENTION (SRAM3_ID | PAGE02_ID) /*!< SRAM3 page 2 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM3_PAGE3_STOP_RETENTION (SRAM3_ID | PAGE03_ID) /*!< SRAM3 page 3 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM3_PAGE4_STOP_RETENTION (SRAM3_ID | PAGE04_ID) /*!< SRAM3 page 4 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM3_PAGE5_STOP_RETENTION (SRAM3_ID | PAGE05_ID) /*!< SRAM3 page 5 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM3_PAGE6_STOP_RETENTION (SRAM3_ID | PAGE06_ID) /*!< SRAM3 page 6 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM3_PAGE7_STOP_RETENTION (SRAM3_ID | PAGE07_ID) /*!< SRAM3 page 7 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM3_PAGE8_STOP_RETENTION (SRAM3_ID | PAGE08_ID) /*!< SRAM3 page 8 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_SRAM3_FULL_STOP_RETENTION (SRAM3_ID | 0xFFU) /*!< SRAM3 all pages retention in Stop modes (Stop 0, 1, 2, 3) */
+
+/* SRAM4 page retention defines */
+#define PWR_SRAM4_FULL_STOP_RETENTION (SRAM4_ID | PAGE01_ID) /*!< SRAM4 retention in Stop modes (Stop 0, 1, 2, 3) */
+
+/* Cache RAMs retention defines */
+#define PWR_ICACHE_FULL_STOP_RETENTION (ICACHERAM_ID | PAGE01_ID) /*!< ICACHE page retention in Stop modes (Stop 0, 1, 2, 3) */
+#define PWR_DCACHE1_FULL_STOP_RETENTION (DCACHE1RAM_ID | PAGE01_ID) /*!< DCACHE1 page retention in Stop modes (Stop 0, 1, 2, 3) */
+
+/* DMA2D RAM retention defines */
+#define PWR_DMA2DRAM_FULL_STOP_RETENTION (DMA2DRAM_ID | PAGE01_ID) /*!< DMA2D RAM retention in Stop modes (Stop 0, 1, 2, 3) */
+
+/* FMAC, FDCAN and USB RAMs retention defines */
+#define PWR_PERIPHRAM_FULL_STOP_RETENTION (PERIPHRAM_ID | PAGE01_ID) /*!< FMAC, FDCAN and USB RAM retention in Stop modes (Stop 0, 1, 2, 3) */
+
+/* PKA32 RAM retention defines */
+#define PWR_PKA32RAM_FULL_STOP_RETENTION (PKARAM_ID | PAGE01_ID) /*!< PKA32 RAM retention in Stop modes (Stop 0, 1, 2, 3) */
+/**
+ * @}
+ */
+
+/** @defgroup PWREx_SRAM2_Contents_Standby_Retention PWR Extended SRAM2 Contents Standby Retention
+ * @note For some products of the U5 family (please see the Reference Manual),
+ * the SRAM2 content is preserved based on the same defines in Stop 3 mode.
+ * @{
+ */
+#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_CR1_RRSB1 /*!< SRAM2 page 1 (8 KB) retention in Stop 3 and Standby modes */
+#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_CR1_RRSB2 /*!< SRAM2 page 2 (54 KB) retention in Stop 3 and Standby modes */
+#define PWR_SRAM2_FULL_STANDBY_RETENTION (PWR_CR1_RRSB1 | PWR_CR1_RRSB2) /*!< SRAM2 all pages retention in Stop 3 and Standby modes */
+/**
+ * @}
+ */
+
+/** @defgroup PWREx_SRAMx_Contents_Run_Retention PWR Extended SRAM Contents Run Retention
+ * @{
+ */
+#define PWR_SRAM1_FULL_RUN_RETENTION PWR_CR1_SRAM1PD /*!< SRAM1 full retention in Run mode */
+#define PWR_SRAM2_FULL_RUN_RETENTION PWR_CR1_SRAM2PD /*!< SRAM2 full retention in Run mode */
+#define PWR_SRAM3_FULL_RUN_RETENTION PWR_CR1_SRAM3PD /*!< SRAM3 full retention in Run mode */
+#define PWR_SRAM4_FULL_RUN_RETENTION PWR_CR1_SRAM4PD /*!< SRAM4 full retention in Run mode */
+/**
+ * @}
+ */
+
+/** @defgroup PWREx_Supply_Configuration PWR Extended Supply Configuration
+ * @{
+ */
+#define PWR_LDO_SUPPLY (0U) /*!< LDO supply */
+#define PWR_SMPS_SUPPLY (PWR_CR3_REGSEL) /*!< SMPS supply */
+/**
+ * @}
+ */
+
+/** @defgroup PWREx_Regulator_Voltage_Scale PWR Extended Regulator Voltage Scale
+ * @{
+ */
+#define PWR_REGULATOR_VOLTAGE_SCALE1 (PWR_VOSR_VOS_0 | PWR_VOSR_VOS_1) /*!< Voltage scaling range 1 */
+#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_VOSR_VOS_1 /*!< Voltage scaling range 2 */
+#define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_VOSR_VOS_0 /*!< Voltage scaling range 3 */
+#define PWR_REGULATOR_VOLTAGE_SCALE4 (0U) /*!< Voltage scaling range 4 */
+/**
+ * @}
+ */
+
+/** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR Extended Battery Charging Resistor Selection
+ * @{
+ */
+#define PWR_BATTERY_CHARGING_RESISTOR_5 (0U) /*!< VBAT charging through a 5 kOhms resistor */
+#define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_BDCR2_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */
+/**
+ * @}
+ */
+
+/** @defgroup PWREx_VBAT_Battery_Charging_State PWR Extended Battery Charging State
+ * @{
+ */
+#define PWR_BATTERY_CHARGING_DISABLE (0U) /*!< Disable battery charging */
+#define PWR_BATTERY_CHARGING_ENABLE PWR_BDCR2_VBE /*!< Enable battery charging */
+/**
+ * @}
+ */
+
+/** @defgroup PWREx_GPIO_Port PWR Extended GPIO Port
+ * @{
+ */
+#define PWR_GPIO_A (0x00U) /*!< GPIO port A */
+#define PWR_GPIO_B (0x01U) /*!< GPIO port B */
+#define PWR_GPIO_C (0x02U) /*!< GPIO port C */
+#define PWR_GPIO_D (0x03U) /*!< GPIO port D */
+#define PWR_GPIO_E (0x04U) /*!< GPIO port E */
+#define PWR_GPIO_F (0x05U) /*!< GPIO port F */
+#define PWR_GPIO_G (0x06U) /*!< GPIO port G */
+#define PWR_GPIO_H (0x07U) /*!< GPIO port H */
+#define PWR_GPIO_I (0x08U) /*!< GPIO port I */
+/**
+ * @}
+ */
+
+/** @defgroup PWREx_GPIO_Pin_Mask PWR Extended GPIO Pin Mask
+ * @{
+ */
+#define PWR_GPIO_BIT_0 (0x0001U) /*!< GPIO port I/O pin 0 */
+#define PWR_GPIO_BIT_1 (0x0002U) /*!< GPIO port I/O pin 1 */
+#define PWR_GPIO_BIT_2 (0x0004U) /*!< GPIO port I/O pin 2 */
+#define PWR_GPIO_BIT_3 (0x0008U) /*!< GPIO port I/O pin 3 */
+#define PWR_GPIO_BIT_4 (0x0010U) /*!< GPIO port I/O pin 4 */
+#define PWR_GPIO_BIT_5 (0x0020U) /*!< GPIO port I/O pin 5 */
+#define PWR_GPIO_BIT_6 (0x0040U) /*!< GPIO port I/O pin 6 */
+#define PWR_GPIO_BIT_7 (0x0080U) /*!< GPIO port I/O pin 7 */
+#define PWR_GPIO_BIT_8 (0x0100U) /*!< GPIO port I/O pin 8 */
+#define PWR_GPIO_BIT_9 (0x0200U) /*!< GPIO port I/O pin 9 */
+#define PWR_GPIO_BIT_10 (0x0400U) /*!< GPIO port I/O pin 10 */
+#define PWR_GPIO_BIT_11 (0x0800U) /*!< GPIO port I/O pin 11 */
+#define PWR_GPIO_BIT_12 (0x1000U) /*!< GPIO port I/O pin 12 */
+#define PWR_GPIO_BIT_13 (0x2000U) /*!< GPIO port I/O pin 13 */
+#define PWR_GPIO_BIT_14 (0x4000U) /*!< GPIO port I/O pin 14 */
+#define PWR_GPIO_BIT_15 (0x8000U) /*!< GPIO port I/O pin 15 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Enable the UVM Extended Interrupt Line.
+ * @retval None.
+ */
+#define __HAL_PWR_UVM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_UVM)
+
+/**
+ * @brief Disable the UVM Extended Interrupt Line.
+ * @retval None.
+ */
+#define __HAL_PWR_UVM_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_UVM)
+
+/**
+ * @brief Enable the UVM Event Line.
+ * @retval None.
+ */
+#define __HAL_PWR_UVM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_UVM)
+
+/**
+ * @brief Disable the UVM Event Line.
+ * @retval None.
+ */
+#define __HAL_PWR_UVM_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_UVM)
+
+/**
+ * @brief Enable the UVM Extended Interrupt Rising Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_UVM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_UVM)
+
+/**
+ * @brief Disable the UVM Extended Interrupt Rising Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_UVM_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_UVM)
+
+/**
+ * @brief Enable the UVM Extended Interrupt Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_UVM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_UVM)
+
+/**
+ * @brief Disable the UVM Extended Interrupt Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_UVM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_UVM)
+
+/**
+ * @brief Enable the UVM Extended Interrupt Rising & Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_UVM_EXTI_ENABLE_RISING_FALLING_EDGE() \
+ do \
+ { \
+ __HAL_PWR_UVM_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_PWR_UVM_EXTI_ENABLE_FALLING_EDGE(); \
+ } while(0)
+
+/**
+ * @brief Disable the UVM Extended Interrupt Rising & Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_UVM_EXTI_DISABLE_RISING_FALLING_EDGE() \
+ do \
+ { \
+ __HAL_PWR_UVM_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_PWR_UVM_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0)
+
+/**
+ * @brief Generate a Software Interrupt on UVM EXTI Line.
+ * @retval None
+ */
+#define __HAL_PWR_UVM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_UVM)
+
+/**
+ * @brief Check whether the specified UVM EXTI flag is set or not.
+ * @retval EXTI UVM Line Status.
+ */
+#define __HAL_PWR_UVM_EXTI_GET_FLAG() ((EXTI->RPR1 | EXTI->FPR1) & PWR_EXTI_LINE_UVM)
+
+/**
+ * @brief Clear the UVM EXTI flag.
+ * @retval None.
+ */
+#define __HAL_PWR_UVM_EXTI_CLEAR_FLAG() \
+ do \
+ { \
+ WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_UVM); \
+ WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_UVM); \
+ } while(0)
+
+/**
+ * @brief Enable the IO2VM Extended Interrupt Line.
+ * @retval None.
+ */
+#define __HAL_PWR_IO2VM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_IO2VM)
+
+/**
+ * @brief Disable the IO2VM Extended Interrupt Line.
+ * @retval None.
+ */
+#define __HAL_PWR_IO2VM_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_IO2VM)
+
+/**
+ * @brief Enable the IO2VM Event Line.
+ * @retval None.
+ */
+#define __HAL_PWR_IO2VM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_IO2VM)
+
+/**
+ * @brief Disable the IO2VM Event Line.
+ * @retval None.
+ */
+#define __HAL_PWR_IO2VM_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_IO2VM)
+
+/**
+ * @brief Enable the IO2VM Extended Interrupt Rising Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_IO2VM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_IO2VM)
+
+/**
+ * @brief Disable the IO2VM Extended Interrupt Rising Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_IO2VM_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_IO2VM)
+
+/**
+ * @brief Enable the IO2VM Extended Interrupt Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_IO2VM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_IO2VM)
+
+/**
+ * @brief Disable the IO2VM Extended Interrupt Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_IO2VM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_IO2VM)
+
+/**
+ * @brief Enable the IO2VM Extended Interrupt Rising & Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_IO2VM_EXTI_ENABLE_RISING_FALLING_EDGE() \
+ do \
+ { \
+ __HAL_PWR_IO2VM_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_PWR_IO2VM_EXTI_ENABLE_FALLING_EDGE(); \
+ } while(0)
+
+/**
+ * @brief Disable the IO2VM Extended Interrupt Rising & Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_IO2VM_EXTI_DISABLE_RISING_FALLING_EDGE() \
+ do \
+ { \
+ __HAL_PWR_IO2VM_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_PWR_IO2VM_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0)
+
+/**
+ * @brief Generate a Software Interrupt on IO2VM EXTI Line.
+ * @retval None
+ */
+#define __HAL_PWR_IO2VM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_IO2VM)
+
+/**
+ * @brief Check whether the specified IO2VM EXTI flag is set or not.
+ * @retval EXTI IO2VM Line Status.
+ */
+#define __HAL_PWR_IO2VM_EXTI_GET_FLAG() ((EXTI->RPR1 | EXTI->FPR1) & PWR_EXTI_LINE_IO2VM)
+
+/**
+ * @brief Clear the IO2VM EXTI flag.
+ * @retval None.
+ */
+#define __HAL_PWR_IO2VM_EXTI_CLEAR_FLAG() \
+ do \
+ { \
+ WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_IO2VM); \
+ WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_IO2VM); \
+ } while(0)
+
+/**
+ * @brief Enable the AVM1 Extended Interrupt Line.
+ * @retval None.
+ */
+#define __HAL_PWR_AVM1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVM1)
+
+/**
+ * @brief Disable the AVM1 Extended Interrupt Line.
+ * @retval None.
+ */
+#define __HAL_PWR_AVM1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVM1)
+
+/**
+ * @brief Enable the AVM1 Event Line.
+ * @retval None.
+ */
+#define __HAL_PWR_AVM1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVM1)
+
+/**
+ * @brief Disable the AVM1 Event Line.
+ * @retval None.
+ */
+#define __HAL_PWR_AVM1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVM1)
+
+/**
+ * @brief Enable the AVM1 Extended Interrupt Rising Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_AVM1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVM1)
+
+/**
+ * @brief Disable the AVM1 Extended Interrupt Rising Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_AVM1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVM1)
+
+/**
+ * @brief Enable the AVM1 Extended Interrupt Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_AVM1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVM1)
+
+/**
+ * @brief Disable the AVM1 Extended Interrupt Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_AVM1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVM1)
+
+/**
+ * @brief Enable the AVM1 Extended Interrupt Rising & Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_AVM1_EXTI_ENABLE_RISING_FALLING_EDGE() \
+ do \
+ { \
+ __HAL_PWR_AVM1_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_PWR_AVM1_EXTI_ENABLE_FALLING_EDGE(); \
+ } while(0)
+
+/**
+ * @brief Disable the AVM1 Extended Interrupt Rising & Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_AVM1_EXTI_DISABLE_RISING_FALLING_EDGE() \
+ do \
+ { \
+ __HAL_PWR_AVM1_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_PWR_AVM1_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0)
+
+/**
+ * @brief Generate a Software Interrupt on AVM1 EXTI Line.
+ * @retval None
+ */
+#define __HAL_PWR_AVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_AVM1)
+
+/**
+ * @brief Check whether the specified AVM1 EXTI flag is set or not.
+ * @retval EXTI AVM1 Line Status.
+ */
+#define __HAL_PWR_AVM1_EXTI_GET_FLAG() ((EXTI->RPR1 | EXTI->FPR1) & PWR_EXTI_LINE_AVM1)
+
+/**
+ * @brief Clear the AVM1 EXTI flag.
+ * @retval None.
+ */
+#define __HAL_PWR_AVM1_EXTI_CLEAR_FLAG() \
+ do \
+ { \
+ WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_AVM1); \
+ WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_AVM1); \
+ } while(0)
+
+/**
+ * @brief Enable the AVM2 Extended Interrupt Line.
+ * @retval None.
+ */
+#define __HAL_PWR_AVM2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVM2)
+
+/**
+ * @brief Disable the AVM2 Extended Interrupt Line.
+ * @retval None.
+ */
+#define __HAL_PWR_AVM2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVM2)
+
+/**
+ * @brief Enable the AVM2 Event Line.
+ * @retval None.
+ */
+#define __HAL_PWR_AVM2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVM2)
+
+/**
+ * @brief Disable the AVM2 Event Line.
+ * @retval None.
+ */
+#define __HAL_PWR_AVM2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVM2)
+
+/**
+ * @brief Enable the AVM2 Extended Interrupt Rising Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_AVM2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVM2)
+
+/**
+ * @brief Disable the AVM2 Extended Interrupt Rising Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_AVM2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVM2)
+
+/**
+ * @brief Enable the AVM2 Extended Interrupt Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_AVM2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVM2)
+
+/**
+ * @brief Disable the AVM2 Extended Interrupt Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_AVM2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVM2)
+
+/**
+ * @brief Enable the AVM2 Extended Interrupt Rising & Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_AVM2_EXTI_ENABLE_RISING_FALLING_EDGE() \
+ do \
+ { \
+ __HAL_PWR_AVM2_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_PWR_AVM2_EXTI_ENABLE_FALLING_EDGE(); \
+ } while(0)
+
+/**
+ * @brief Disable the AVM2 Extended Interrupt Rising & Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_AVM2_EXTI_DISABLE_RISING_FALLING_EDGE() \
+ do \
+ { \
+ __HAL_PWR_AVM2_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_PWR_AVM2_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0)
+
+/**
+ * @brief Generate a Software Interrupt on AVM2 EXTI Line.
+ * @retval None
+ */
+#define __HAL_PWR_AVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_AVM2)
+
+/**
+ * @brief Check whether the specified AVM2 EXTI flag is set or not.
+ * @retval EXTI AVM2 Line Status.
+ */
+#define __HAL_PWR_AVM2_EXTI_GET_FLAG() ((EXTI->RPR1 | EXTI->FPR1) & PWR_EXTI_LINE_AVM2)
+
+/**
+ * @brief Clear the AVM2 EXTI flag.
+ * @retval None.
+ */
+#define __HAL_PWR_AVM2_EXTI_CLEAR_FLAG() \
+ do \
+ { \
+ WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_AVM2); \
+ WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_AVM2); \
+ } while(0)
+
+/**
+ * @brief Configure the main internal regulator output voltage.
+ * @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but
+ * doesn't check whether or not VOSREADY flag is set. User may resort
+ * to __HAL_PWR_GET_FLAG() macro to check VOSF bit state.
+ * @param __REGULATOR__ : Specifies the regulator output voltage to achieve a
+ * tradeoff between performance and power consumption.
+ * This parameter can be one of the following values :
+ * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output scale 1.
+ * Provides a typical output voltage at 1.2 V.
+ * Used when system clock frequency is up to 160 MHz.
+ * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output scale 2.
+ * Provides a typical output voltage at 1.1 V.
+ * Used when system clock frequency is up to 100 MHz.
+ * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output scale 3.
+ * Provides a typical output voltage at 1.0 V.
+ * Used when system clock frequency is up to 50 MHz.
+ * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE4 : Regulator voltage output scale 4.
+ * Provides a typical output voltage at 0.9 V.
+ * Used when system clock frequency is up to 24 MHz.
+ * @retval None.
+ */
+#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \
+ do \
+ { \
+ __IO uint32_t tmpreg; \
+ MODIFY_REG(PWR->VOSR, PWR_VOSR_VOS, (__REGULATOR__)); \
+ tmpreg = READ_BIT(PWR->VOSR, PWR_VOSR_VOS); \
+ UNUSED(tmpreg); \
+ } while(0)
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+
+/** @addtogroup PWREx_Private_Constants PWR Extended Private Constants
+ * @{
+ */
+/* PVM extended interrupts and event lines defines */
+#define PWR_EXTI_LINE_UVM (0x00080000UL) /* UVM EXTI Line */
+#define PWR_EXTI_LINE_IO2VM (0x00100000UL) /* IO2VM EXTI Line */
+#define PWR_EXTI_LINE_AVM1 (0x00200000UL) /* AVM1 EXTI Line */
+#define PWR_EXTI_LINE_AVM2 (0x00400000UL) /* AVM2 EXTI Line */
+
+/* SRAM retention IDs */
+#define SRAM_ID_MASK (0xFFFFUL << 16U)
+#define SRAM1_ID (0x01UL << 16U)
+#define SRAM2_ID (0x01UL << 17U)
+#define SRAM3_ID (0x01UL << 18U)
+#define SRAM4_ID (0x01UL << 19U)
+#define ICACHERAM_ID (0x01UL << 20U)
+#define DCACHE1RAM_ID (0x01UL << 21U)
+#define DMA2DRAM_ID (0x01UL << 22U)
+#define PERIPHRAM_ID (0x01UL << 23U)
+#define PKARAM_ID (0x01UL << 24U)
+
+/* SRAM page retention IDs */
+#define PAGE01_ID (0x01UL << 0U)
+#define PAGE02_ID (0x01UL << 1U)
+#define PAGE03_ID (0x01UL << 2U)
+#define PAGE04_ID (0x01UL << 3U)
+#define PAGE05_ID (0x01UL << 4U)
+#define PAGE06_ID (0x01UL << 5U)
+#define PAGE07_ID (0x01UL << 6U)
+#define PAGE08_ID (0x01UL << 7U)
+#define PAGE09_ID (0x01UL << 8U)
+#define PAGE10_ID (0x01UL << 9U)
+#define PAGE11_ID (0x01UL << 10U)
+#define PAGE12_ID (0x01UL << 11U)
+#define PAGE13_ID (0x01UL << 12U)
+
+/* All available RAM retention in Run mode define */
+#define PWR_ALL_RAM_RUN_RETENTION_MASK (PWR_SRAM1_FULL_RUN_RETENTION | PWR_SRAM2_FULL_RUN_RETENTION | \
+ PWR_SRAM3_FULL_RUN_RETENTION | PWR_SRAM4_FULL_RUN_RETENTION)
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+
+/** @addtogroup PWREx_Private_Macros PWR Extended Private Macros
+ * @{
+ */
+/* PVM type check macro */
+#define IS_PWR_PVM_TYPE(TYPE) \
+ (((TYPE) == PWR_UVM ) ||\
+ ((TYPE) == PWR_IO2VM) ||\
+ ((TYPE) == PWR_AVM1) ||\
+ ((TYPE) == PWR_AVM2))
+
+/* PVM mode check macro */
+#define IS_PWR_PVM_MODE(MODE) \
+ (((MODE) == PWR_PVM_MODE_NORMAL) ||\
+ ((MODE) == PWR_PVM_MODE_IT_RISING) ||\
+ ((MODE) == PWR_PVM_MODE_IT_FALLING) ||\
+ ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) ||\
+ ((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\
+ ((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\
+ ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING))
+
+/* SRD state check macro */
+#define IS_PWR_SRD_STATE(SRD_STATE) \
+ (((SRD_STATE) == PWR_SRD_DOMAIN_STOP) ||\
+ ((SRD_STATE) == PWR_SRD_DOMAIN_RUN))
+
+/* Supply selection check macro */
+#define IS_PWR_SUPPLY(PWR_SOURCE) \
+ (((PWR_SOURCE) == PWR_LDO_SUPPLY) ||\
+ ((PWR_SOURCE) == PWR_SMPS_SUPPLY))
+
+/* Voltage scaling range check macro */
+#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) \
+ (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) ||\
+ ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2) ||\
+ ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE3) ||\
+ ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE4))
+
+/* Battery charging resistor selection check macro */
+#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) \
+ (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
+ ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
+
+/* Battery charging activation check macro */
+#define IS_PWR_BATTERY_CHARGING(CHARGING) \
+ (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\
+ ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE))
+
+/* GPIO port check macro */
+#define IS_PWR_GPIO_PORT(GPIO_PORT) \
+ (((GPIO_PORT) == PWR_GPIO_A) ||\
+ ((GPIO_PORT) == PWR_GPIO_B) ||\
+ ((GPIO_PORT) == PWR_GPIO_C) ||\
+ ((GPIO_PORT) == PWR_GPIO_D) ||\
+ ((GPIO_PORT) == PWR_GPIO_E) ||\
+ ((GPIO_PORT) == PWR_GPIO_F) ||\
+ ((GPIO_PORT) == PWR_GPIO_G) ||\
+ ((GPIO_PORT) == PWR_GPIO_H) ||\
+ ((GPIO_PORT) == PWR_GPIO_I))
+
+/* GPIO pin mask check macro */
+#define IS_PWR_GPIO_PIN_MASK(BIT_MASK) \
+ ((((BIT_MASK) & GPIO_PIN_MASK) != 0U) && ((BIT_MASK) <= GPIO_PIN_MASK))
+
+/* SRAM2 retention in Standby mode check macro */
+#define IS_PWR_SRAM2_STANDBY_RETENTION(CONTENT) \
+ (((CONTENT) == PWR_SRAM2_PAGE1_STANDBY_RETENTION) ||\
+ ((CONTENT) == PWR_SRAM2_PAGE2_STANDBY_RETENTION) ||\
+ ((CONTENT) == PWR_SRAM2_FULL_STANDBY_RETENTION))
+
+/* RAMs retention in Stop mode check macros */
+#define IS_PWR_SRAM1_STOP_RETENTION(RAMCONTENT) \
+ ((((RAMCONTENT) & (~PWR_SRAM1_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U))
+
+#define IS_PWR_SRAM2_STOP_RETENTION(RAMCONTENT) \
+ ((((RAMCONTENT) & (~PWR_SRAM2_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U))
+
+#define IS_PWR_SRAM3_STOP_RETENTION(RAMCONTENT) \
+ ((((RAMCONTENT) & (~PWR_SRAM3_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U))
+
+#define IS_PWR_SRAM4_STOP_RETENTION(RAMCONTENT) \
+ ((((RAMCONTENT) & (~PWR_SRAM4_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U))
+
+#define IS_PWR_ICACHE_STOP_RETENTION(RAMCONTENT) \
+ ((((RAMCONTENT) & (~PWR_ICACHE_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U))
+
+#define IS_PWR_DCACHE1_STOP_RETENTION(RAMCONTENT) \
+ ((((RAMCONTENT) & (~PWR_DCACHE1_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U))
+
+#define IS_PWR_DMA2DRAM_STOP_RETENTION(RAMCONTENT) \
+ ((((RAMCONTENT) & (~PWR_DMA2DRAM_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U))
+
+#define IS_PWR_PERIPHRAM_STOP_RETENTION(RAMCONTENT) \
+ ((((RAMCONTENT) & (~PWR_PERIPHRAM_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U))
+
+#define IS_PWR_PKA32RAM_STOP_RETENTION(RAMCONTENT) \
+ ((((RAMCONTENT) & (~PWR_PKA32RAM_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U))
+
+/* RAMs retention in Run mode check macro */
+#define IS_PWR_RAM_RUN_RETENTION(RAMCONTENT) \
+ ((((RAMCONTENT) & (~PWR_ALL_RAM_RUN_RETENTION_MASK)) == 0U) && ((RAMCONTENT) != 0U))
+/**
+ * @}
+ */
+
+/** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions
+ * @{
+ */
+
+/** @addtogroup PWREx_Exported_Functions_Group1 Power Supply Control Functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
+uint32_t HAL_PWREx_GetVoltageRange(void);
+HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource);
+uint32_t HAL_PWREx_GetSupplyConfig(void);
+void HAL_PWREx_EnableFastSoftStart(void);
+void HAL_PWREx_DisableFastSoftStart(void);
+/**
+ * @}
+ */
+
+/** @addtogroup PWREx_Exported_Functions_Group2 Low Power Control Functions
+ * @{
+ */
+void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry);
+void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry);
+void HAL_PWREx_EnterSTOP3Mode(uint8_t STOPEntry);
+void HAL_PWREx_EnterSHUTDOWNMode(void);
+void HAL_PWREx_ConfigSRDDomain(uint32_t SRDState);
+void HAL_PWREx_EnableUltraLowPowerMode(void);
+void HAL_PWREx_DisableUltraLowPowerMode(void);
+void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin);
+void HAL_PWREx_S3WUCallback(uint32_t WakeUpPin);
+/**
+ * @}
+ */
+
+/** @addtogroup PWREx_Exported_Functions_Group3 Voltage Monitoring Functions
+ * @{
+ */
+void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue);
+void HAL_PWREx_DisableBatteryCharging(void);
+void HAL_PWREx_EnableVddUSB(void);
+void HAL_PWREx_DisableVddUSB(void);
+void HAL_PWREx_EnableVddIO2(void);
+void HAL_PWREx_DisableVddIO2(void);
+void HAL_PWREx_EnableVddA(void);
+void HAL_PWREx_DisableVddA(void);
+void HAL_PWREx_EnableUVM(void);
+void HAL_PWREx_DisableUVM(void);
+void HAL_PWREx_EnableIO2VM(void);
+void HAL_PWREx_DisableIO2VM(void);
+void HAL_PWREx_EnableAVM1(void);
+void HAL_PWREx_DisableAVM1(void);
+void HAL_PWREx_EnableAVM2(void);
+void HAL_PWREx_DisableAVM2(void);
+HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *pConfigPVM);
+void HAL_PWREx_EnableMonitoring(void);
+void HAL_PWREx_DisableMonitoring(void);
+void HAL_PWREx_EnableUCPDStandbyMode(void);
+void HAL_PWREx_DisableUCPDStandbyMode(void);
+void HAL_PWREx_EnableUCPDDeadBattery(void);
+void HAL_PWREx_DisableUCPDDeadBattery(void);
+void HAL_PWREx_PVD_PVM_IRQHandler(void);
+void HAL_PWREx_UVMCallback(void);
+void HAL_PWREx_IO2VMCallback(void);
+void HAL_PWREx_AVM1Callback(void);
+void HAL_PWREx_AVM2Callback(void);
+/**
+ * @}
+ */
+
+/** @addtogroup PWREx_Exported_Functions_Group4 Memories Retention Functions
+ * @{
+ */
+void HAL_PWREx_EnableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages);
+void HAL_PWREx_DisableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages);
+void HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection);
+void HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection);
+void HAL_PWREx_EnableRAMsContentRunRetention(uint32_t RAMSelection);
+void HAL_PWREx_DisableRAMsContentRunRetention(uint32_t RAMSelection);
+void HAL_PWREx_EnableFlashFastWakeUp(void);
+void HAL_PWREx_DisableFlashFastWakeUp(void);
+void HAL_PWREx_EnableSRAM4FastWakeUp(void);
+void HAL_PWREx_DisableSRAM4FastWakeUp(void);
+HAL_StatusTypeDef HAL_PWREx_EnableBkupRAMRetention(void);
+void HAL_PWREx_DisableBkupRAMRetention(void);
+/**
+ * @}
+ */
+
+/** @addtogroup PWREx_Exported_Functions_Group5 I/O Pull-Up Pull-Down Configuration Functions
+ * @{
+ */
+void HAL_PWREx_EnablePullUpPullDownConfig(void);
+void HAL_PWREx_DisablePullUpPullDownConfig(void);
+HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_Pin);
+HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_Pin);
+HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPIO_Pin);
+HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPIO_Pin);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* STM32U5xx_HAL_PWR_EX_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_ramcfg.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_ramcfg.h
new file mode 100644
index 00000000..e2979770
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_ramcfg.h
@@ -0,0 +1,431 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_ramcfg.h
+ * @author MCD Application Team
+ * @brief Header file of RAMCFG HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_RAMCFG_H
+#define STM32U5xx_HAL_RAMCFG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup RAMCFG
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup RAMCFG_Exported_Types RAMCFG Exported Types
+ * @brief RAMCFG Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL RAMCFG State Enumeration Definition
+ */
+typedef enum
+{
+ HAL_RAMCFG_STATE_RESET = 0x00U, /*!< RAMCFG not yet initialized or disabled */
+ HAL_RAMCFG_STATE_READY = 0x01U, /*!< RAMCFG initialized and ready for use */
+ HAL_RAMCFG_STATE_BUSY = 0x02U, /*!< RAMCFG process is ongoing */
+ HAL_RAMCFG_STATE_ERROR = 0x03U, /*!< RAMCFG error state */
+} HAL_RAMCFG_StateTypeDef;
+
+#if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL RAMCFG Callbacks IDs Enumeration Definition
+ */
+typedef enum
+{
+ HAL_RAMCFG_MSPINIT_CB_ID = 0x00U, /*!< RAMCFG MSP Init Callback ID */
+ HAL_RAMCFG_MSPDEINIT_CB_ID = 0x01U, /*!< RAMCFG MSP DeInit Callback ID */
+ HAL_RAMCFG_SE_DETECT_CB_ID = 0x02U, /*!< RAMCFG Single Error Detect Callback ID */
+ HAL_RAMCFG_DE_DETECT_CB_ID = 0x03U, /*!< RAMCFG Double Error Detect Callback ID */
+ HAL_RAMCFG_ALL_CB_ID = 0x04U, /*!< RAMCFG All callback ID */
+} HAL_RAMCFG_CallbackIDTypeDef;
+#endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */
+
+/**
+ * @brief RAMCFG Handle Structure Definition
+ */
+#if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1)
+typedef struct __RAMCFG_HandleTypeDef
+#else
+typedef struct
+#endif /* (USE_HAL_RAMCFG_REGISTER_CALLBACKS) */
+{
+ RAMCFG_TypeDef *Instance; /*!< RAMCFG Register Base Address */
+ __IO HAL_RAMCFG_StateTypeDef State; /*!< RAMCFG State */
+ __IO uint32_t ErrorCode; /*!< RAMCFG Error Code */
+#if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1)
+ void (* MspInitCallback)(struct __RAMCFG_HandleTypeDef *hramcfg); /*!< RAMCFG MSP Init Callback */
+ void (* MspDeInitCallback)(struct __RAMCFG_HandleTypeDef *hramcfg); /*!< RAMCFG MSP DeInit Callback */
+ void (* DetectSingleErrorCallback)(struct __RAMCFG_HandleTypeDef *hramcfg);/*!< RAMCFG Single Error Detect Callback */
+ void (* DetectDoubleErrorCallback)(struct __RAMCFG_HandleTypeDef *hramcfg);/*!< RAMCFG Double Error Detect Callback */
+#endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */
+} RAMCFG_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup RAMCFG_Exported_Constants RAMCFG Exported Constants
+ * @brief RAMCFG Exported Constants
+ * @{
+ */
+
+/** @defgroup RAMCFG_Error_Codes RAMCFG Error Codes
+ * @brief RAMCFG Error Codes
+ * @{
+ */
+#define HAL_RAMCFG_ERROR_NONE 0x00000000U /*!< RAMCFG No Error */
+#define HAL_RAMCFG_ERROR_TIMEOUT 0x00000001U /*!< RAMCFG Timeout Error */
+#define HAL_RAMCFG_ERROR_BUSY 0x00000002U /*!< RAMCFG Busy Error */
+#if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1)
+#define HAL_RAMCFG_ERROR_INVALID_CALLBACK 0x00000003U /*!< Invalid Callback error */
+#endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup RAMCFG_Interrupt RAMCFG Interrupts
+ * @brief RAMCFG Interrupts
+ * @{
+ */
+#define RAMCFG_IT_SINGLEERR RAMCFG_IER_SEIE /* RAMCFG Single Error Interrupt */
+#define RAMCFG_IT_DOUBLEERR RAMCFG_IER_DEIE /* RAMCFG Double Error Interrupt */
+#define RAMCFG_IT_NMIERR RAMCFG_IER_ECCNMI /* RAMCFG Double Error redirected to NMI Interrupt */
+#define RAMCFG_IT_ALL (RAMCFG_IER_SEIE | \
+ RAMCFG_IER_DEIE | \
+ RAMCFG_IER_ECCNMI) /* RAMCFG All RAMCFG interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup RAMCFG_FLAG RAMCFG Monitor Flags
+ * @brief RAMCFG Monitor Flags
+ * @{
+ */
+#define RAMCFG_FLAG_SINGLEERR RAMCFG_ISR_SEDC /* RAMCFG Single Error Detected and Corrected Flag */
+#define RAMCFG_FLAG_DOUBLEERR RAMCFG_ISR_DED /* RAMCFG Double Error Detected Flag */
+#define RAMCFG_FLAG_SRAMBUSY RAMCFG_ISR_SRAMBUSY /* RAMCFG SRAM busy Flag */
+#define RAMCFG_FLAGS_ALL (RAMCFG_ISR_SEDC | \
+ RAMCFG_ISR_DED | \
+ RAMCFG_ISR_SRAMBUSY) /* RAMCFG All Flags */
+/**
+ * @}
+ */
+
+/** @defgroup RAMCFG_WaitState RAMCFG Wait State
+ * @brief RAMCFG Wait State
+ * @{
+ */
+#define RAMCFG_WAITSTATE_0 (0U) /* RAMCFG 0 Wait State */
+#define RAMCFG_WAITSTATE_1 (RAMCFG_CR_WSC_0) /* RAMCFG 1 Wait State */
+#define RAMCFG_WAITSTATE_2 (RAMCFG_CR_WSC_1) /* RAMCFG 2 Wait State */
+#define RAMCFG_WAITSTATE_3 (RAMCFG_CR_WSC_0 | RAMCFG_CR_WSC_1) /* RAMCFG 3 Wait State */
+#define RAMCFG_WAITSTATE_4 (RAMCFG_CR_WSC_2) /* RAMCFG 4 Wait State */
+#define RAMCFG_WAITSTATE_5 (RAMCFG_CR_WSC_0 | RAMCFG_CR_WSC_2) /* RAMCFG 5 Wait State */
+#define RAMCFG_WAITSTATE_6 (RAMCFG_CR_WSC_1 | RAMCFG_CR_WSC_2) /* RAMCFG 6 Wait State */
+#define RAMCFG_WAITSTATE_7 (RAMCFG_CR_WSC_0 | RAMCFG_CR_WSC_1 | RAMCFG_CR_WSC_2) /* RAMCFG 7 Wait State */
+/**
+ * @}
+ */
+
+/** @defgroup RAMCFG_Keys RAMCFG Keys
+ * @brief RAMCFG Keys
+ * @{
+ */
+#define RAMCFG_ERASE_KEY1 (0xCAU) /* RAMCFG launch Erase Key 1 */
+#define RAMCFG_ERASE_KEY2 (0x53U) /* RAMCFG launch Erase Key 2 */
+
+#define RAMCFG_ECC_KEY1 (0xAEU) /* RAMCFG launch ECC Key 1 */
+#define RAMCFG_ECC_KEY2 (0x75U) /* RAMCFG launch ECC Key 2 */
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+
+
+
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup RAMCFG_Exported_Macros RAMCFG Exported Macros
+ * @brief RAMCFG Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Enable the specified RAMCFG interrupts.
+ * @param __HANDLE__ : Specifies RAMCFG handle.
+ * @param __INTERRUPT__: Specifies the RAMCFG interrupt sources to be enabled.
+ * This parameter can be one of the following values:
+ * @arg RAMCFG_IT_SINGLEERR : Single Error Interrupt Mask.
+ * @arg RAMCFG_IT_DOUBLEERR : Double Error Interrupt Mask.
+ * @arg RAMCFG_IT_NMIERR : Double Error Interrupt redirection to NMI Mask.
+ * @arg RAMCFG_IT_ALL : All Interrupt Mask.
+ * @retval None
+ */
+#define __HAL_RAMCFG_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
+ ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the specified RAMCFG interrupts.
+ * @note This macros is used only to disable RAMCFG_IT_SINGLEERR and RAMCFG_IT_DOUBLEERR
+ * interrupts. RAMCFG_IT_NMIERR interrupt can only be disabled by global peripheral reset or system reset.
+ * @param __HANDLE__ : Specifies RAMCFG handle.
+ * @param __INTERRUPT__: Specifies the RAMCFG interrupt sources to be disabled.
+ * This parameter can be one of the following values:
+ * @arg RAMCFG_IT_SINGLEERR : Single Error Interrupt Mask.
+ * @arg RAMCFG_IT_DOUBLEERR : Double Error Interrupt Mask.
+ * @retval None
+ */
+#define __HAL_RAMCFG_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
+ ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified RAMCFG interrupt source is enabled or not.
+ * @param __HANDLE__ : Specifies the RAMCFG Handle.
+ * @param __INTERRUPT__ : Specifies the RAMCFG interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg RAMCFG_IT_SINGLEERR : Single Error Interrupt Mask.
+ * @arg RAMCFG_IT_DOUBLEERR : Double Error Interrupt Mask.
+ * @arg RAMCFG_IT_NMIERR : Double Error Interrupt Redirection to NMI Mask.
+ * @retval The new state of __INTERRUPT__ (SET or RESET).
+ */
+#define __HAL_RAMCFG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+ ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? 1U : 0U)
+
+/**
+ * @brief Get the RAMCFG pending flags.
+ * @param __HANDLE__ : Specifies RAMCFG handle.
+ * @param __FLAG__ : Specifies the flag to be checked.
+ * This parameter can be one of the following values:
+ * @arg RAMCFG_FLAG_SINGLEERR : Single Error Detected and Corrected Flag.
+ * @arg RAMCFG_FLAG_DOUBLEERR : Double Error Detected Flag.
+ * @arg RAMCFG_FLAG_SRAMBUSY : SRAM Busy Flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __HAL_RAMCFG_GET_FLAG(__HANDLE__, __FLAG__) \
+ (READ_BIT((__HANDLE__)->Instance->ISR, (__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clear the RAMCFG pending flags.
+ * @param __HANDLE__ : Specifies RAMCFG handle.
+ * @param __FLAG__ : Specifies the flag to be cleared.
+ * This parameter can be any combination of the following values:
+ * @arg RAMCFG_FLAG_SINGLEERR : Single Error Detected and Corrected Flag.
+ * @arg RAMCFG_FLAG_DOUBLEERR : Double Error Detected Flag.
+ * @retval None.
+ */
+#define __HAL_RAMCFG_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+ ((__HANDLE__)->Instance->ICR |= (__FLAG__))
+
+/** @brief Reset the RAMCFG handle state.
+ * @param __HANDLE__ : Specifies the RAMCFG Handle.
+ * @retval None.
+ */
+#if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1)
+#define __HAL_RAMCFG_RESET_HANDLE_STATE(__HANDLE__) \
+ do{\
+ (__HANDLE__)->State = HAL_RAMCFG_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ }while(0)
+#else
+#define __HAL_RAMCFG_RESET_HANDLE_STATE(__HANDLE__) \
+ do{\
+ (__HANDLE__)->State = HAL_RAMCFG_STATE_RESET; \
+ }while(0)
+#endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup RAMCFG_Exported_Functions RAMCFG Exported Functions
+ * @brief RAMCFG Exported Functions
+ * @{
+ */
+
+/** @defgroup RAMCFG_Exported_Functions_Group1 Initialization and De-Initialization Functions
+ * @brief Initialization and De-Initialization Functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_RAMCFG_Init(RAMCFG_HandleTypeDef *hramcfg);
+HAL_StatusTypeDef HAL_RAMCFG_DeInit(RAMCFG_HandleTypeDef *hramcfg);
+void HAL_RAMCFG_MspInit(RAMCFG_HandleTypeDef *hramcfg);
+void HAL_RAMCFG_MspDeInit(RAMCFG_HandleTypeDef *hramcfg);
+/**
+ * @}
+ */
+
+/** @defgroup RAMCFG_Exported_Functions_Group2 ECC Operation Functions
+ * @brief ECC Operation Functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_RAMCFG_StartECC(RAMCFG_HandleTypeDef *hramcfg);
+HAL_StatusTypeDef HAL_RAMCFG_StopECC(RAMCFG_HandleTypeDef *hramcfg);
+HAL_StatusTypeDef HAL_RAMCFG_EnableNotification(RAMCFG_HandleTypeDef *hramcfg, uint32_t Notifications);
+HAL_StatusTypeDef HAL_RAMCFG_DisableNotification(RAMCFG_HandleTypeDef *hramcfg, uint32_t Notifications);
+uint32_t HAL_RAMCFG_IsECCSingleErrorDetected(RAMCFG_HandleTypeDef *hramcfg);
+uint32_t HAL_RAMCFG_IsECCDoubleErrorDetected(RAMCFG_HandleTypeDef *hramcfg);
+uint32_t HAL_RAMCFG_GetSingleErrorAddress(RAMCFG_HandleTypeDef *hramcfg);
+uint32_t HAL_RAMCFG_GetDoubleErrorAddress(RAMCFG_HandleTypeDef *hramcfg);
+/**
+ * @}
+ */
+
+/** @defgroup RAMCFG_Exported_Functions_Group3 Configure Wait State Functions
+ * @brief Configure Wait State Functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_RAMCFG_ConfigWaitState(RAMCFG_HandleTypeDef *hramcfg, uint32_t WaitState);
+uint32_t HAL_RAMCFG_GetWaitState(RAMCFG_HandleTypeDef *hramcfg);
+/**
+ * @}
+ */
+
+/** @defgroup RAMCFG_Exported_Functions_Group4 Write Protection Functions
+ * @brief Write Protection Functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_RAMCFG_EnableWriteProtection(RAMCFG_HandleTypeDef *hramcfg, uint32_t StartPage, uint32_t NbPage);
+/**
+ * @}
+ */
+
+/** @defgroup RAMCFG_Exported_Functions_Group5 Erase Operation Functions
+ * @brief Erase Operation Functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_RAMCFG_Erase(RAMCFG_HandleTypeDef *hramcfg);
+/**
+ * @}
+ */
+
+/** @defgroup RAMCFG_Exported_Functions_Group6 Handle Interrupt and Callbacks Functions
+ * @brief Handle Interrupt and Callbacks Functions
+ * @{
+ */
+void HAL_RAMCFG_IRQHandler(RAMCFG_HandleTypeDef *hramcfg);
+void HAL_RAMCFG_DetectSingleErrorCallback(RAMCFG_HandleTypeDef *hramcfg);
+void HAL_RAMCFG_DetectDoubleErrorCallback(RAMCFG_HandleTypeDef *hramcfg);
+#if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_RAMCFG_RegisterCallback(RAMCFG_HandleTypeDef *hramcfg,
+ HAL_RAMCFG_CallbackIDTypeDef CallbackID,
+ void (* pCallback)(RAMCFG_HandleTypeDef *_hramcfg));
+HAL_StatusTypeDef HAL_RAMCFG_UnRegisterCallback(RAMCFG_HandleTypeDef *hramcfg, HAL_RAMCFG_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup RAMCFG_Exported_Functions_Group7 State and Error Functions
+ * @brief State and Error Functions
+ * @{
+ */
+uint32_t HAL_RAMCFG_GetError(RAMCFG_HandleTypeDef *hramcfg);
+HAL_RAMCFG_StateTypeDef HAL_RAMCFG_GetState(RAMCFG_HandleTypeDef *hramcfg);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private Constants ---------------------------------------------------------*/
+
+/** @defgroup RAMCFG_Private_Constants RAMCFG Private Defines and Constants
+ * @brief RAMCFG Private Defines and Constants
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup RAMCFG_Private_Macros RAMCFG Private Macros
+ * @brief RAMCFG Private Macros
+ * @{
+ */
+#define IS_RAMCFG_INTERRUPT(INTERRUPT) \
+ (((INTERRUPT) != 0U) && (((INTERRUPT) & ~(RAMCFG_IT_SINGLEERR | RAMCFG_IT_DOUBLEERR | RAMCFG_IT_NMIERR)) == 0U))
+
+
+#define IS_RAMCFG_WAITSTATE(WAITSTATE) \
+ (((WAITSTATE) == RAMCFG_WAITSTATE_0) || ((WAITSTATE) == RAMCFG_WAITSTATE_1) || \
+ ((WAITSTATE) == RAMCFG_WAITSTATE_2) || ((WAITSTATE) == RAMCFG_WAITSTATE_3) || \
+ ((WAITSTATE) == RAMCFG_WAITSTATE_4) || ((WAITSTATE) == RAMCFG_WAITSTATE_5) || \
+ ((WAITSTATE) == RAMCFG_WAITSTATE_6) || ((WAITSTATE) == RAMCFG_WAITSTATE_7))
+
+#define IS_RAMCFG_WRITEPROTECTION_PAGE(PAGE) ((PAGE) <= 64U)
+
+
+
+/**
+ * @}
+ */
+
+
+
+
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup RAMCFG_Private_Functions RAMCFG Private Functions
+ * @brief RAMCFG Private Functions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32U5xx_HAL_RAMCFG_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rcc.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rcc.h
new file mode 100644
index 00000000..b1e1636a
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rcc.h
@@ -0,0 +1,3943 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_rcc.h
+ * @author MCD Application Team
+ * @brief Header file of RCC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_RCC_H
+#define STM32U5xx_HAL_RCC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup RCC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RCC_Exported_Types RCC Exported Types
+ * @{
+ */
+
+/**
+ * @brief RCC PLL configuration structure definition
+ */
+typedef struct
+{
+ uint32_t PLLState; /*!< The new state of the PLL.
+ This parameter can be a value of @ref RCC_PLL_Config */
+
+ uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
+ This parameter must be a value of @ref RCC_PLL_Clock_Source */
+
+ uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
+
+ uint32_t PLLMBOOST; /*!< PLLMBOOST: Prescaler for EPOD booster input clock.
+ This parameter must be a value of @ref RCC_PLLMBOOST_EPOD_Clock_Divider */
+
+ uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
+ This parameter must be a number between Min_Data = 4 and Max_Data = 512 */
+
+ uint32_t PLLP; /*!< PLLP: Division factor for system clock.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 128
+ odd division factors are not allowed */
+
+ uint32_t PLLQ; /*!< PLLQ: Division factor for peripheral clocks.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
+
+ uint32_t PLLR; /*!< PLLR: Division factor for peripheral clocks.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 128 */
+
+ uint32_t PLLRGE; /*!< PLLRGE: PLL1 clock Input range
+ This parameter must be a value of @ref RCC_PLL_VCI_Range */
+
+ uint32_t PLLFRACN; /*!< PLLFRACN: Specifies Fractional Part Of The Multiplication Factor for
+ PLL1 VCO It should be a value between 0 and 32767 */
+
+} RCC_PLLInitTypeDef;
+
+/**
+ * @brief RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition
+ */
+typedef struct
+{
+ uint32_t OscillatorType; /*!< The oscillators to be configured.
+ This parameter can be a value of @ref RCC_Oscillator_Type */
+
+ uint32_t HSEState; /*!< The new state of the HSE.
+ This parameter can be a value of @ref RCC_HSE_Config */
+
+ uint32_t LSEState; /*!< The new state of the LSE.
+ This parameter can be a value of @ref RCC_LSE_Config */
+
+ uint32_t HSIState; /*!< The new state of the HSI.
+ This parameter can be a value of @ref RCC_HSI_Config */
+
+ uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F
+ on the other devices */
+
+ uint32_t LSIState; /*!< The new state of the LSI.
+ This parameter can be a value of @ref RCC_LSI_Config */
+
+ uint32_t LSIDiv; /*!< The division factor of the LSI.
+ This parameter can be a value of @ref RCC_LSI_Div */
+
+ uint32_t MSIState; /*!< The new state of the MSI.
+ This parameter can be a value of @ref RCC_MSI_Config */
+
+ uint32_t MSICalibrationValue; /*!< The calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT).
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+
+ uint32_t MSIClockRange; /*!< The MSI frequency range.
+ This parameter can be a value of @ref RCC_MSI_Clock_Range */
+
+ uint32_t MSIKClockRange; /*!< The MSIK frequency range.
+ This parameter can be a value of @ref RCC_MSIk_Clock_Range */
+
+ uint32_t HSI48State; /*!< The new state of the HSI48.
+ This parameter can be a value of @ref RCC_HSI48_Config */
+
+ uint32_t SHSIState; /*!< The new state of the SHSI.
+ This parameter can be a value of @ref RCC_SHSI_Config */
+
+ uint32_t MSIKState; /*!< The new state of the MSIK.
+ This parameter can be a value of @ref RCC_MSIK_Config */
+
+ RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */
+
+} RCC_OscInitTypeDef;
+
+/**
+ * @brief RCC System, AHB and APB busses clock configuration structure definition
+ */
+typedef struct
+{
+ uint32_t ClockType; /*!< The clock to be configured.
+ This parameter can be a value of @ref RCC_System_Clock_Type */
+
+ uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK).
+ This parameter can be a value of @ref RCC_System_Clock_Source */
+
+ uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock
+ (SYSCLK).
+ This parameter can be a value of @ref RCC_AHB_Clock_Source */
+
+ uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+ This parameter can be a value of @ref RCC_APB1_APB2_APB3_Clock_Source */
+
+ uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
+ This parameter can be a value of @ref RCC_APB1_APB2_APB3_Clock_Source */
+
+ uint32_t APB3CLKDivider; /*!< The APB3 clock (PCLK3) divider. This clock is derived from the AHB clock (HCLK).
+ This parameter can be a value of @ref RCC_APB1_APB2_APB3_Clock_Source */
+} RCC_ClkInitTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCC_Exported_Constants RCC Exported Constants
+ * @{
+ */
+#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
+#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
+#define MSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
+
+/* Defines used for Flags */
+#define CR_REG_INDEX (1U)
+#define BDCR_REG_INDEX (2U)
+#define CSR_REG_INDEX (3U)
+#define CRRCR_REG_INDEX (4U)
+
+#define RCC_FLAG_MASK (0x1FU)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Reset_Flag Reset Flag
+ * @{
+ */
+#define RCC_RESET_FLAG_OBL RCC_CSR_OBLRSTF /*!< Option Byte Loader reset flag */
+#define RCC_RESET_FLAG_PIN RCC_CSR_PINRSTF /*!< PIN reset flag */
+#define RCC_RESET_FLAG_PWR RCC_CSR_BORRSTF /*!< BOR or POR/PDR reset flag */
+#define RCC_RESET_FLAG_SW RCC_CSR_SFTRSTF /*!< Software Reset flag */
+#define RCC_RESET_FLAG_IWDG RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
+#define RCC_RESET_FLAG_WWDG RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
+#define RCC_RESET_FLAG_LPWR RCC_CSR_LPWRRSTF /*!< Low power reset flag */
+#define RCC_RESET_FLAG_ALL (RCC_RESET_FLAG_OBL | RCC_RESET_FLAG_PIN | RCC_RESET_FLAG_PWR | \
+ RCC_RESET_FLAG_SW | RCC_RESET_FLAG_IWDG | RCC_RESET_FLAG_WWDG | \
+ RCC_RESET_FLAG_LPWR)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Timeout_Value Timeout Values
+ * @{
+ */
+#define RCC_DBP_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
+#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Oscillator_Type Oscillator Type
+ * @{
+ */
+#define RCC_OSCILLATORTYPE_NONE 0x0UL /*!< Oscillator configuration unchanged */
+#define RCC_OSCILLATORTYPE_HSE 0x1UL /*!< HSE to configure */
+#define RCC_OSCILLATORTYPE_HSI 0x2UL /*!< HSI to configure */
+#define RCC_OSCILLATORTYPE_LSE 0x4UL /*!< LSE to configure */
+#define RCC_OSCILLATORTYPE_LSI 0x8UL /*!< LSI to configure */
+#define RCC_OSCILLATORTYPE_MSI 0x10UL /*!< MSI to configure */
+#define RCC_OSCILLATORTYPE_HSI48 0x20UL /*!< HSI48 to configure */
+#define RCC_OSCILLATORTYPE_MSIK 0x040U /*!< MSIK to configure */
+#define RCC_OSCILLATORTYPE_SHSI 0x80UL /*!< SHSI to configure */
+/* Defines Oscillator Masks */
+#define RCC_OSCILLATORTYPE_ALL (RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSI | \
+ RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_MSIK | \
+ RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_SHSI) /*!< All Oscillator to configure */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSE_Config HSE Config
+ * @{
+ */
+#define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */
+#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */
+#define RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< External clock source for HSE clock */
+#define RCC_HSE_BYPASS_DIGITAL (RCC_CR_HSEEXT | RCC_CR_HSEBYP | RCC_CR_HSEON)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSE_Config LSE Config
+ * @{
+ */
+#define RCC_LSE_OFF 0U /*!< LSE clock deactivation */
+#define RCC_LSE_ON_RTC_ONLY RCC_BDCR_LSEON /*!< LSE clock activation for RTC only */
+#define RCC_LSE_ON (RCC_BDCR_LSESYSEN | RCC_BDCR_LSEON) /*!< LSE clock activation for RCC and peripherals */
+#define RCC_LSE_BYPASS_RTC_ONLY (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */
+#define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSESYSEN | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSI_Config HSI Config
+ * @{
+ */
+#define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */
+#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
+#define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSI_Config LSI Config
+ * @{
+ */
+#define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */
+#define RCC_LSI_ON RCC_BDCR_LSION /*!< LSI clock activation */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSI_Div LSI Div
+ * @{
+ */
+#define RCC_LSI_DIV1 0U /*!< LSI clock is not divided */
+#define RCC_LSI_DIV128 RCC_BDCR_LSIPREDIV /*!< LSI clock is divided by 128 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MSI_Config MSI Config
+ * @{
+ */
+#define RCC_MSI_OFF 0x00000000U /*!< MSI clock deactivation */
+#define RCC_MSI_ON RCC_CR_MSISON /*!< MSI clock activation */
+
+#define RCC_MSICALIBRATION_DEFAULT 0x10U /*!< Default MSI calibration trimming value */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSI48_Config HSI48 Config
+ * @{
+ */
+#define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */
+#define RCC_HSI48_ON RCC_CR_HSI48ON /*!< HSI48 clock activation */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MSIK_Config MSIK Config
+ * @{
+ */
+#define RCC_MSIK_OFF 0x00000000U /*!< MSIK clock deactivation */
+#define RCC_MSIK_ON RCC_CR_MSIKON /*!< MSIK clock activation */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_SHSI_Config SHSI Config
+ * @{
+ */
+#define RCC_SHSI_OFF 0x00000000U /*!< SHSI clock deactivation */
+#define RCC_SHSI_ON RCC_CR_SHSION /*!< SHSI clock activation */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Config RCC PLL Config
+ * @{
+ */
+#define RCC_PLL_NONE 0x00000000U
+#define RCC_PLL_OFF 0x00000001U
+#define RCC_PLL_ON 0x00000002U
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Clock_Output RCC PLL Clock Output
+ * @{
+ */
+#define RCC_PLL1_DIVP RCC_PLL1CFGR_PLL1PEN
+#define RCC_PLL1_DIVQ RCC_PLL1CFGR_PLL1QEN
+#define RCC_PLL1_DIVR RCC_PLL1CFGR_PLL1REN
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLLMBOOST_EPOD_Clock_Divider PLLMBOOST EPOD Clock Divider
+ * @{
+ */
+#define RCC_PLLMBOOST_DIV1 0x00000000U
+#define RCC_PLLMBOOST_DIV2 RCC_PLL1CFGR_PLL1MBOOST_0
+#define RCC_PLLMBOOST_DIV4 RCC_PLL1CFGR_PLL1MBOOST_1
+#define RCC_PLLMBOOST_DIV6 (RCC_PLL1CFGR_PLL1MBOOST_1 | RCC_PLL1CFGR_PLL1MBOOST_0)
+#define RCC_PLLMBOOST_DIV8 RCC_PLL1CFGR_PLL1MBOOST_2
+#define RCC_PLLMBOOST_DIV10 (RCC_PLL1CFGR_PLL1MBOOST_2 | RCC_PLL1CFGR_PLL1MBOOST_0)
+#define RCC_PLLMBOOST_DIV12 (RCC_PLL1CFGR_PLL1MBOOST_2 | RCC_PLL1CFGR_PLL1MBOOST_1)
+#define RCC_PLLMBOOST_DIV14 (RCC_PLL1CFGR_PLL1MBOOST_2 | RCC_PLL1CFGR_PLL1MBOOST_1| RCC_PLL1CFGR_PLL1MBOOST_0)
+#define RCC_PLLMBOOST_DIV16 RCC_PLL1CFGR_PLL1MBOOST_3
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_VCI_Range RCC PLL1 VCI Range
+ * @{
+ */
+#define RCC_PLLVCIRANGE_0 0x00000000U
+#define RCC_PLLVCIRANGE_1 (RCC_PLL1CFGR_PLL1RGE_1 | RCC_PLL1CFGR_PLL1RGE_0)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Clock_Source RCC PLL Clock Source
+ * @{
+ */
+#define RCC_PLLSOURCE_NONE 0x00000000U
+#define RCC_PLLSOURCE_MSI RCC_PLL1CFGR_PLL1SRC_0
+#define RCC_PLLSOURCE_HSI RCC_PLL1CFGR_PLL1SRC_1
+#define RCC_PLLSOURCE_HSE (RCC_PLL1CFGR_PLL1SRC_0 | RCC_PLL1CFGR_PLL1SRC_1)
+/**
+ * @}
+ */
+
+
+/** @defgroup RCC_MSI_Clock_Range MSI Clock Range
+ * @{
+ */
+#define RCC_MSIRANGE_0 0x00000000U /*!< MSI = 48 MHz */
+#define RCC_MSIRANGE_1 RCC_ICSCR1_MSISRANGE_0 /*!< MSI = 24 MHz */
+#define RCC_MSIRANGE_2 RCC_ICSCR1_MSISRANGE_1 /*!< MSI = 16 MHz */
+#define RCC_MSIRANGE_3 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1) /*!< MSI = 12 MHz */
+#define RCC_MSIRANGE_4 RCC_ICSCR1_MSISRANGE_2 /*!< MSI = 4 MHz */
+#define RCC_MSIRANGE_5 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_2) /*!< MSI = 2 MHz */
+#define RCC_MSIRANGE_6 (RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_2) /*!< MSI = 1.33 MHz */
+#define RCC_MSIRANGE_7 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_2) /*!< MSI = 1 MHz */
+#define RCC_MSIRANGE_8 RCC_ICSCR1_MSISRANGE_3 /*!< MSI = 3.072 MHz */
+#define RCC_MSIRANGE_9 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 1.536 MHz */
+#define RCC_MSIRANGE_10 (RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 1.024 MHz */
+#define RCC_MSIRANGE_11 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 768 KHz */
+#define RCC_MSIRANGE_12 (RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 400 KHz */
+#define RCC_MSIRANGE_13 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 200 KHz */
+#define RCC_MSIRANGE_14 (RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 133 KHz */
+#define RCC_MSIRANGE_15 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1| RCC_ICSCR1_MSISRANGE_2 |\
+ RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 100 KHz */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MSIk_Clock_Range MSIK Clock Range
+ * @{
+ */
+#define RCC_MSIKRANGE_0 0x00000000U /*!< MSIk = 48 MHz */
+#define RCC_MSIKRANGE_1 RCC_ICSCR1_MSIKRANGE_0 /*!< MSIk = 24 MHz */
+#define RCC_MSIKRANGE_2 RCC_ICSCR1_MSIKRANGE_1 /*!< MSIk = 16 MHz */
+#define RCC_MSIKRANGE_3 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1) /*!< MSIk = 12 MHz */
+#define RCC_MSIKRANGE_4 RCC_ICSCR1_MSIKRANGE_2 /*!< MSIk = 4 MHz */
+#define RCC_MSIKRANGE_5 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIk = 2 MHz */
+#define RCC_MSIKRANGE_6 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIk = 1.33 MHz */
+#define RCC_MSIKRANGE_7 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIk = 1 MHz */
+#define RCC_MSIKRANGE_8 RCC_ICSCR1_MSIKRANGE_3 /*!< MSIk = 3.072 MHz */
+#define RCC_MSIKRANGE_9 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 1.536 MHz */
+#define RCC_MSIKRANGE_10 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 1.024 MHz */
+#define RCC_MSIKRANGE_11 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 768 KHz */
+#define RCC_MSIKRANGE_12 (RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 400 KHz */
+#define RCC_MSIKRANGE_13 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 200 KHz */
+#define RCC_MSIKRANGE_14 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 133 KHz */
+#define RCC_MSIKRANGE_15 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2 |\
+ RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 100 KHz */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_System_Clock_Type System Clock Type
+ * @{
+ */
+#define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */
+#define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */
+#define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */
+#define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */
+#define RCC_CLOCKTYPE_PCLK3 0x00000010U /*!< PCLK3 to configure */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_System_Clock_Source System Clock Source
+ * @{
+ */
+#define RCC_SYSCLKSOURCE_MSI 0x00000000U /*!< MSI selection as system clock */
+#define RCC_SYSCLKSOURCE_HSI RCC_CFGR1_SW_0 /*!< HSI selection as system clock */
+#define RCC_SYSCLKSOURCE_HSE RCC_CFGR1_SW_1 /*!< HSE selection as system clock */
+#define RCC_SYSCLKSOURCE_PLLCLK (RCC_CFGR1_SW_0 | RCC_CFGR1_SW_1) /*!< PLL1 selection as system clock */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
+ * @{
+ */
+#define RCC_SYSCLKSOURCE_STATUS_MSI 0x00000000U /*!< MSI used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR1_SWS_0 /*!< HSI used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR1_SWS_1 /*!< HSE used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_PLLCLK (RCC_CFGR1_SWS_0 | RCC_CFGR1_SWS_1) /*!< PLL1 used as system clock */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
+ * @{
+ */
+#define RCC_SYSCLK_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_SYSCLK_DIV2 RCC_CFGR2_HPRE_3 /*!< SYSCLK divided by 2 */
+#define RCC_SYSCLK_DIV4 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 4 */
+#define RCC_SYSCLK_DIV8 (RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 8 */
+#define RCC_SYSCLK_DIV16 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 16 */
+#define RCC_SYSCLK_DIV64 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 64 */
+#define RCC_SYSCLK_DIV128 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 128 */
+#define RCC_SYSCLK_DIV256 (RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 256 */
+#define RCC_SYSCLK_DIV512 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 512 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_APB2_APB3_Clock_Source APB1 APB2 APB3 Clock Source
+ * @{
+ */
+#define RCC_HCLK_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_HCLK_DIV2 RCC_CFGR2_PPRE1_2 /*!< HCLK divided by 2 */
+#define RCC_HCLK_DIV4 (RCC_CFGR2_PPRE1_0 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 4 */
+#define RCC_HCLK_DIV8 (RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 8 */
+#define RCC_HCLK_DIV16 (RCC_CFGR2_PPRE1_0 | RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 16 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
+ * @{
+ */
+#define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U /*!< No clock used as RTC clock */
+#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
+#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MCO_Index MCO Index
+ * @{
+ */
+#define RCC_MCO1 0x00000000U
+#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
+ * @{
+ */
+#define RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO1 output disabled, no clock on MCO1 */
+#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR1_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
+#define RCC_MCO1SOURCE_MSI RCC_CFGR1_MCOSEL_1 /*!< MSI selection as MCO1 source */
+#define RCC_MCO1SOURCE_HSI (RCC_CFGR1_MCOSEL_0| RCC_CFGR1_MCOSEL_1) /*!< HSI selection as MCO1 source */
+#define RCC_MCO1SOURCE_HSE RCC_CFGR1_MCOSEL_2 /*!< HSE selection as MCO1 source */
+#define RCC_MCO1SOURCE_PLL1CLK (RCC_CFGR1_MCOSEL_0|RCC_CFGR1_MCOSEL_2) /*!< PLL1CLK selection as MCO1 source */
+#define RCC_MCO1SOURCE_LSI (RCC_CFGR1_MCOSEL_1|RCC_CFGR1_MCOSEL_2) /*!< LSI selection as MCO1 source */
+#define RCC_MCO1SOURCE_LSE (RCC_CFGR1_MCOSEL_0|RCC_CFGR1_MCOSEL_1|RCC_CFGR1_MCOSEL_2) /*!< LSE selection as MCO1 source */
+#define RCC_MCO1SOURCE_HSI48 RCC_CFGR1_MCOSEL_3 /*!< HSI48 selection as MCO1 source */
+#define RCC_MCO1SOURCE_MSIK (RCC_CFGR1_MCOSEL_0| RCC_CFGR1_MCOSEL_3) /*!< MSIK selection as MCO1 source */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler
+ * @{
+ */
+#define RCC_MCODIV_1 0x00000000U /*!< MCO is divided by 1 */
+#define RCC_MCODIV_2 RCC_CFGR1_MCOPRE_0 /*!< MCO is divided by 2 */
+#define RCC_MCODIV_4 RCC_CFGR1_MCOPRE_1 /*!< MCO is divided by 4 */
+#define RCC_MCODIV_8 (RCC_CFGR1_MCOPRE_0 | RCC_CFGR1_MCOPRE_1)/*!< MCO is divided by 8 */
+#define RCC_MCODIV_16 RCC_CFGR1_MCOPRE_2 /*!< MCO is divided by 16 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Interrupt Interrupts
+ * @{
+ */
+#define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */
+#define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
+#define RCC_IT_MSIRDY RCC_CIFR_MSISRDYF /*!< MSI Ready Interrupt flag */
+#define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */
+#define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */
+#define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
+#define RCC_IT_PLLRDY RCC_CIFR_PLL1RDYF /*!< PLL1 Ready Interrupt flag */
+#define RCC_IT_PLL2RDY RCC_CIFR_PLL2RDYF /*!< PLL2 Ready Interrupt flag */
+#define RCC_IT_PLL3RDY RCC_CIFR_PLL3RDYF /*!< PLL3 Ready Interrupt flag */
+#define RCC_IT_CSS RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */
+#define RCC_IT_MSIKRDY RCC_CIFR_MSIKRDYF /*!< MSIK Ready Interrupt flag */
+#define RCC_IT_SHSIRDY RCC_CIFR_SHSIRDYF /*!< SHSI Ready Interrupt flag */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Flag Flags
+ * Elements values convention: XXXYYYYYb
+ * - YYYYY : Flag position in the register
+ * - XXX : Register index
+ * - 001: CR register
+ * - 010: BDCR register
+ * - 011: CSR register
+ * - 100: CRRCR register
+ * @{
+ */
+/* Flags in the CR register */
+#define RCC_FLAG_MSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_MSISRDY_Pos)) /*!< MSI Ready flag */
+#define RCC_FLAG_MSIKRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_MSIKRDY_Pos)) /*!< MSI Ready flag */
+#define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< HSI Ready flag */
+#define RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< HSE Ready flag */
+#define RCC_FLAG_PLL1RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL1RDY_Pos)) /*!< PLL Ready flag */
+#define RCC_FLAG_PLL2RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL2RDY_Pos)) /*!< PLL2 Ready flag */
+#define RCC_FLAG_PLL3RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL3RDY_Pos)) /*!< PLL3 Ready flag */
+#define RCC_FLAG_SHSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_SHSIRDY_Pos)) /*!< SHSI Ready flag */
+#define RCC_FLAG_HSI48RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSI48RDY_Pos)) /*!< HSI48 Ready flag */
+
+/* Flags in the BDCR register */
+#define RCC_FLAG_LSERDY ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) /*!< LSE Ready flag */
+#define RCC_FLAG_LSESYSRDY ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSESYSRDY_Pos)) /*!< LSESYS Ready flag */
+#define RCC_FLAG_LSECSSD ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos)) /*!< LSE Clock Security System Interrupt flag */
+#define RCC_FLAG_LSIRDY ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSIRDY_Pos)) /*!< LSI Ready flag */
+
+/* Flags in the CSR register */
+#define RCC_FLAG_RMVF ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_RMVF_Pos)) /*!< Remove reset flag */
+#define RCC_FLAG_OBLRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos)) /*!< Option Byte Loader reset flag */
+#define RCC_FLAG_PINRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)) /*!< PIN reset flag */
+#define RCC_FLAG_BORRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos)) /*!< BOR reset flag */
+#define RCC_FLAG_SFTRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)) /*!< Software Reset flag */
+#define RCC_FLAG_IWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */
+#define RCC_FLAG_WWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */
+#define RCC_FLAG_LPWRRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSEDrive_Config LSE Drive Config
+ * @{
+ */
+#define RCC_LSEDRIVE_LOW 0x00000000U /*!< LSE low drive capability */
+#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */
+#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */
+#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock
+ * @{
+ */
+#define RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U /*!< MSI selection after wake-up from STOP */
+#define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR1_STOPWUCK /*!< HSI selection after wake-up from STOP */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Stop_KernelWakeUpClock RCC Stop KernelWakeUpClock
+ * @{
+ */
+#define RCC_STOP_KERWAKEUPCLOCK_MSI 0x00000000U /*!< MSI kernel clock selection after wake-up from STOP */
+#define RCC_STOP_KERWAKEUPCLOCK_HSI RCC_CFGR1_STOPKERWUCK /*!< HSI kernel clock selection after wake-up from STOP */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_items RCC items
+ * @brief RCC items to configure attributes on
+ * @{
+ */
+#define RCC_HSI RCC_SECCFGR_HSISEC
+#define RCC_HSE RCC_SECCFGR_HSESEC
+#define RCC_MSI RCC_SECCFGR_MSISEC
+#define RCC_LSI RCC_SECCFGR_LSISEC
+#define RCC_LSE RCC_SECCFGR_LSESEC
+#define RCC_SYSCLK RCC_SECCFGR_SYSCLKSEC
+#define RCC_PRESC RCC_SECCFGR_PRESCSEC
+#define RCC_PLL1 RCC_SECCFGR_PLL1SEC
+#define RCC_PLL2 RCC_SECCFGR_PLL2SEC
+#define RCC_PLL3 RCC_SECCFGR_PLL3SEC
+#define RCC_CLK48M RCC_SECCFGR_CLK48MSEC
+#define RCC_HSI48 RCC_SECCFGR_HSI48SEC
+#define RCC_RMVF RCC_SECCFGR_RMVFSEC
+#define RCC_ALL (RCC_HSI|RCC_HSE|RCC_MSI|RCC_LSI|RCC_LSE|RCC_HSI48| \
+ RCC_SYSCLK|RCC_PRESC|RCC_PLL1|RCC_PLL2| \
+ RCC_PLL3|RCC_CLK48M|RCC_RMVF)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_attributes RCC attributes
+ * @brief RCC privilege/non-privilege and secure/non-secure attributes
+ * @{
+ */
+#define RCC_NSEC_PRIV 0x00000001U /*!< Non-secure Privilege attribute item */
+#define RCC_NSEC_NPRIV 0x00000002U /*!< Non-secure Non-privilege attribute item */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define RCC_SEC_PRIV 0x00000010U /*!< Secure Privilege attribute item */
+#define RCC_SEC_NPRIV 0x00000020U /*!< Secure Non-privilege attribute item */
+#endif /* __ARM_FEATURE_CMSE */
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Macros RCC Exported Macros
+ * @{
+ */
+
+/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
+ * @brief Enable or disable the AHB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_GPDMA1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_CORDIC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_FMAC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TSC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_CRC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_RAMCFG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_FLASH_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_MDF1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_GTZC1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_DCACHE1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_SRAM1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_GPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN)
+
+#define __HAL_RCC_CORDIC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN)
+
+#define __HAL_RCC_FMAC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN)
+
+#define __HAL_RCC_MDF1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN)
+
+#define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN)
+
+#define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN)
+
+#define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN)
+
+#define __HAL_RCC_RAMCFG_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN)
+
+#define __HAL_RCC_DMA2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN)
+
+#define __HAL_RCC_GTZC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN)
+
+#define __HAL_RCC_BKPSRAM_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN)
+
+#define __HAL_RCC_DCACHE1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN)
+
+#define __HAL_RCC_SRAM1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
+ * @brief Enable or disable the AHB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_DCMI_PSSI_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_USB_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#if defined(AES)
+#define __HAL_RCC_AES_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+#endif /* AES */
+
+#if defined(HASH)
+#define __HAL_RCC_HASH_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+#endif /* HASH */
+
+#define __HAL_RCC_RNG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_PKA_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_SAES_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_OSPIM_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_OTFDEC1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_OTFDEC2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_SRAM2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_SRAM3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_FMC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_OSPI1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_OSPI2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN)
+
+#define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN)
+
+#define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN)
+
+#define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN)
+
+#define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN)
+
+#define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN)
+
+#define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN)
+
+#define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN)
+
+#define __HAL_RCC_GPIOI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN)
+
+#define __HAL_RCC_ADC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC1EN)
+
+#define __HAL_RCC_DCMI_PSSI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN)
+
+#define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN)
+
+#if defined(AES)
+#define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN)
+#endif /* AES */
+
+#if defined(HASH)
+#define __HAL_RCC_HASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN)
+#endif /* HASH */
+
+#define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN)
+
+#define __HAL_RCC_PKA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN)
+
+#define __HAL_RCC_SAES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN)
+
+#define __HAL_RCC_OSPIM_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN)
+
+#define __HAL_RCC_OTFDEC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN)
+
+#define __HAL_RCC_OTFDEC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN)
+
+#define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN)
+
+#define __HAL_RCC_SDMMC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN)
+
+#define __HAL_RCC_SRAM2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN)
+
+#define __HAL_RCC_SRAM3_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN)
+
+#define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN)
+
+#define __HAL_RCC_OSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN)
+
+#define __HAL_RCC_OSPI2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN)
+/**
+ * @}
+ */
+
+/** @defgroup BUS AHB APB Peripheral Clock Enable Disable
+ * @{
+ */
+#define __HAL_RCC_AHB1_CLK_DISABLE() SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS);
+
+#define __HAL_RCC_AHB2_1_CLK_DISABLE() SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1);
+
+#define __HAL_RCC_AHB2_2_CLK_DISABLE() SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2);
+
+#define __HAL_RCC_AHB3_CLK_DISABLE() SET_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS);
+
+#define __HAL_RCC_APB1_CLK_DISABLE() SET_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS);
+
+#define __HAL_RCC_APB2_CLK_DISABLE() SET_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS);
+
+#define __HAL_RCC_APB3_CLK_DISABLE() SET_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS);
+
+#define __HAL_RCC_AHB1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); \
+ tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_AHB2_1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); \
+ tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_AHB2_2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); \
+ tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+
+#define __HAL_RCC_AHB3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ CLEAR_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); \
+ tmpreg = READ_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_APB1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); \
+ tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_APB2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); \
+ tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_APB3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ CLEAR_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); \
+ tmpreg = READ_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3ENR Peripheral Clock Enable Disable
+ * @brief Enable or disable the AHB3ENR peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_LPGPIO1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_PWR_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_ADC4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_DAC1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_LPDMA1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_ADF1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_GTZC2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_SRAM4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_LPGPIO1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN)
+
+#define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN)
+
+#define __HAL_RCC_ADC4_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN)
+
+#define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN)
+
+#define __HAL_RCC_LPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN)
+
+#define __HAL_RCC_ADF1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN)
+
+#define __HAL_RCC_GTZC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN)
+
+#define __HAL_RCC_SRAM4_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
+ * @brief Enable or disable the APB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_USART2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_USART3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_UART4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_UART5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_CRS_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_I2C4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_DTS_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_DTSEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_DTSEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_FDCAN1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_UCPD_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN)
+
+#define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN)
+
+#define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN)
+
+#define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN)
+
+#define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN)
+
+#define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN)
+
+#define __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN)
+
+#define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN)
+
+#define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN)
+
+#define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN)
+
+#define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN)
+
+#define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN)
+
+#define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN)
+
+#define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN)
+
+#define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN)
+
+#define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN)
+
+#define __HAL_RCC_DTS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2 , RCC_APB1ENR2_DTSEN)
+
+#define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN)
+
+#define __HAL_RCC_FDCAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN)
+
+#define __HAL_RCC_UCPD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
+ * @brief Enable or disable the APB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+
+#define __HAL_RCC_USART1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_SAI2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN)
+
+#define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN)
+
+#define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN)
+
+#define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN)
+
+#define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN)
+
+#define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN)
+
+#define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN)
+
+#define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN)
+
+#define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB3_Clock_Enable_Disable APB3 Peripheral Clock Enable Disable
+ * @brief Enable or disable the APB3 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_LPUART1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_LPTIM3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_LPTIM4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_OPAMP_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_COMP_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_VREF_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN)
+
+#define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN)
+
+#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN)
+
+#define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN)
+
+#define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN)
+
+#define __HAL_RCC_LPTIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN)
+
+#define __HAL_RCC_LPTIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN)
+
+#define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN)
+
+#define __HAL_RCC_COMP_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN)
+
+#define __HAL_RCC_VREF_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN)
+
+#define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status
+ * @brief Check whether the AHB1 peripheral clock is enabled or not.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_GPDMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) != 0U)
+
+#define __HAL_RCC_CORDIC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) != 0U)
+
+#define __HAL_RCC_FMAC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) != 0U)
+
+#define __HAL_RCC_MDF1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN) != 0U)
+
+#define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U)
+
+#define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U)
+
+#define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != 0U)
+
+#define __HAL_RCC_RAMCFG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) != 0U)
+
+#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) != 0U)
+
+#define __HAL_RCC_GTZC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN) != 0U)
+
+#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN) != 0U)
+
+#define __HAL_RCC_DCACHE1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN) != 0U)
+
+#define __HAL_RCC_SRAM1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) != 0U)
+
+#define __HAL_RCC_GPDMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) == 0U)
+
+#define __HAL_RCC_CORDIC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) == 0U)
+
+#define __HAL_RCC_FMAC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) == 0U)
+
+#define __HAL_RCC_MDF1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN) == 0U)
+
+#define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == 0U)
+
+#define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U)
+
+#define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == 0U)
+
+#define __HAL_RCC_RAMCFG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) == 0U)
+
+#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) == 0U)
+
+#define __HAL_RCC_GTZC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN) == 0U)
+
+#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN) == 0U)
+
+#define __HAL_RCC_DCACHE1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN) == 0U)
+
+#define __HAL_RCC_SRAM1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) == 0U)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status
+ * @brief Check whether the AHB2 peripheral clock is enabled or not.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN) != 0U)
+
+#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN) != 0U)
+
+#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN) != 0U)
+
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN) != 0U)
+
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN) != 0U)
+
+#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN) != 0U)
+
+#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN) != 0U)
+
+#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN) != 0U)
+
+#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN) != 0U)
+
+#define __HAL_RCC_ADC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC1EN) != 0U)
+
+#define __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN) != 0U)
+
+#define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) != 0U)
+
+#if defined(AES)
+#define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN) != 0U)
+#endif /* AES */
+
+#if defined(HASH)
+#define __HAL_RCC_HASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN) != 0U)
+#endif /* HASH */
+
+#define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN) != 0U)
+
+#define __HAL_RCC_PKA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN) != 0U)
+
+#define __HAL_RCC_SAES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN) != 0U)
+
+#define __HAL_RCC_OSPIM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN) != 0U)
+
+#define __HAL_RCC_OTFDEC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN) != 0U)
+
+#define __HAL_RCC_OTFDEC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN) != 0U)
+
+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN) != 0U)
+
+#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN) != 0U)
+
+#define __HAL_RCC_SRAM2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN) != 0U)
+
+#define __HAL_RCC_SRAM3_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN) != 0U)
+
+#define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN) != 0U)
+
+#define __HAL_RCC_OSPI1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN) != 0U)
+
+#define __HAL_RCC_OSPI2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN) != 0U)
+
+#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN) == 0U)
+
+#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN) == 0U)
+
+#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN) == 0U)
+
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN) == 0U)
+
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN) == 0U)
+
+#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN) == 0U)
+
+#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN) == 0U)
+
+#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN) == 0U)
+
+#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN) == 0U)
+
+#define __HAL_RCC_ADC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC1EN) == 0U)
+
+#define __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN) == 0U)
+
+#define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) == 0U)
+
+#if defined(AES)
+#define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN) == 0U)
+#endif /* AES */
+
+#if defined(HASH)
+#define __HAL_RCC_HASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN) == 0U)
+#endif /* HASH */
+
+#define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN) == 0U)
+
+#define __HAL_RCC_PKA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN) == 0U)
+
+#define __HAL_RCC_SAES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN) == 0U)
+
+#define __HAL_RCC_OSPIM_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN) == 0U)
+
+#define __HAL_RCC_OTFDEC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN) == 0U)
+
+#define __HAL_RCC_OTFDEC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN) == 0U)
+
+#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN) == 0U)
+
+#define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN) == 0U)
+
+#define __HAL_RCC_SRAM2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN) == 0U)
+
+#define __HAL_RCC_SRAM3_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN) == 0U)
+
+#define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN) == 0U)
+
+#define __HAL_RCC_OSPI1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN) == 0U)
+
+#define __HAL_RCC_OSPI2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN) == 0U)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status
+ * @brief Check whether the AHB3 peripheral clock is enabled or not.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_LPGPIO1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN) != 0U)
+
+#define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN) != 0U)
+
+#define __HAL_RCC_ADC4_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN) != 0U)
+
+#define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN) != 0U)
+
+#define __HAL_RCC_LPDMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN) != 0U)
+
+#define __HAL_RCC_ADF1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN) != 0U)
+
+#define __HAL_RCC_GTZC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN) != 0U)
+
+#define __HAL_RCC_SRAM4_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN) != 0U)
+
+#define __HAL_RCC_LPGPIO1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN) == 0U)
+
+#define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN) == 0U)
+
+#define __HAL_RCC_ADC4_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN) == 0U)
+
+#define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN) == 0U)
+
+#define __HAL_RCC_LPDMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN) == 0U)
+
+#define __HAL_RCC_ADF1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN) == 0U)
+
+#define __HAL_RCC_GTZC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN) == 0U)
+
+#define __HAL_RCC_SRAM4_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN) == 0U)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status
+ * @brief Check whether the APB1 peripheral clock is enabled or not.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U)
+
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U)
+
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != 0U)
+
+#define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U)
+
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != 0U)
+
+#define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != 0U)
+
+#define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U)
+
+#define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U)
+
+#define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U)
+
+#define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U)
+
+#define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != 0U)
+
+#define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != 0U)
+
+#define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != 0U)
+
+#define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != 0U)
+
+#define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != 0U)
+
+#define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != 0U)
+
+#define __HAL_RCC_DTS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_DTSEN) != 0U)
+
+#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != 0U)
+
+#define __HAL_RCC_FDCAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN) != 0U)
+
+#define __HAL_RCC_UCPD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) != 0U)
+
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == 0U)
+
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == 0U)
+
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == 0U)
+
+#define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == 0U)
+
+#define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == 0U)
+
+#define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == 0U)
+
+#define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == 0U)
+
+#define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == 0U)
+
+#define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == 0U)
+
+#define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == 0U)
+
+#define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == 0U)
+
+#define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == 0U)
+
+#define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == 0U)
+
+#define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == 0U)
+
+#define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == 0U)
+
+#define __HAL_RCC_DTS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_DTSEN) == 0U)
+
+#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == 0U)
+
+#define __HAL_RCC_FDCAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN) == 0U)
+
+#define __HAL_RCC_UCPD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) == 0U)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status
+ * @brief Check whether the APB2 peripheral clock is enabled or not.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U)
+
+#define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U)
+
+#define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != 0U)
+
+#define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U)
+
+#define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U)
+
+#define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U)
+
+#define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U)
+
+#define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U)
+
+#define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != 0U)
+
+#define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U)
+
+#define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U)
+
+#define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U)
+
+#define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U)
+
+#define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U)
+
+#define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U)
+
+#define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U)
+
+#define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U)
+
+#define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == 0U)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB3_Peripheral_Clock_Enable_Disable_Status APB3 Peripheral Clock Enabled or Disabled Status
+ * @brief Check whether the APB3 peripheral clock is enabled or not.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN) != 0U)
+
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN) != 0U)
+
+#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN) != 0U)
+
+#define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN) != 0U)
+
+#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN) != 0U)
+
+#define __HAL_RCC_LPTIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN) != 0U)
+
+#define __HAL_RCC_LPTIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN) != 0U)
+
+#define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN) != 0U)
+
+#define __HAL_RCC_COMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN) != 0U)
+
+#define __HAL_RCC_VREF_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN) != 0U)
+
+#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) != 0U)
+
+#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN) == 0U)
+
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN) == 0U)
+
+#define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN) == 0U)
+
+#define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN) == 0U)
+
+#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN) == 0U)
+
+#define __HAL_RCC_LPTIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN) == 0U)
+
+#define __HAL_RCC_LPTIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN) == 0U)
+
+#define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN) == 0U)
+
+#define __HAL_RCC_COMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN) == 0U)
+
+#define __HAL_RCC_VREF_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN) == 0U)
+
+#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) == 0U)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset
+ * @brief Force or release AHB1 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x0007100FU)
+
+#define __HAL_RCC_GPDMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST)
+
+#define __HAL_RCC_CORDIC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST)
+
+#define __HAL_RCC_FMAC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST)
+
+#define __HAL_RCC_MDF1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_MDF1RST)
+
+#define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
+
+#define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
+
+#define __HAL_RCC_RAMCFG_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_RAMCFGRST)
+
+#define __HAL_RCC_DMA2D_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST)
+
+#define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U)
+
+#define __HAL_RCC_GPDMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST)
+
+#define __HAL_RCC_CORDIC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST)
+
+#define __HAL_RCC_FMAC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST)
+
+#define __HAL_RCC_MDF1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_MDF1RST)
+
+#define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
+
+#define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
+
+#define __HAL_RCC_RAMCFG_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_RAMCFGRST)
+
+#define __HAL_RCC_DMA2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset
+ * @brief Force or release AHB2 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_AHB2_FORCE_RESET() do{\
+ WRITE_REG(RCC->AHB2RSTR1, 0x19BF55FFU);\
+ WRITE_REG(RCC->AHB2RSTR2, 0x00000111U);\
+ }while(0)
+
+#define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOARST)
+
+#define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOBRST)
+
+#define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOCRST)
+
+#define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIODRST)
+
+#define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOERST)
+
+#define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOFRST)
+
+#define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOGRST)
+
+#define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOHRST)
+
+#define __HAL_RCC_GPIOI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOIRST)
+
+#define __HAL_RCC_ADC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_ADC1RST)
+
+#define __HAL_RCC_DCMI_PSSI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_DCMI_PSSIRST)
+
+#define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTGRST)
+
+#define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_AESRST)
+
+#define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_HASHRST)
+
+#define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_RNGRST)
+
+#define __HAL_RCC_PKA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_PKARST)
+
+#define __HAL_RCC_SAES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SAESRST)
+
+#define __HAL_RCC_OSPIM_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OCTOSPIMRST)
+
+#define __HAL_RCC_OTFDEC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC1RST)
+
+#define __HAL_RCC_OTFDEC2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC2RST)
+
+#define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC1RST)
+
+#define __HAL_RCC_SDMMC2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC2RST)
+
+#define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_FSMCRST)
+
+#define __HAL_RCC_OSPI1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI1RST)
+
+#define __HAL_RCC_OSPI2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI2RST)
+
+#define __HAL_RCC_AHB2_RELEASE_RESET() do{\
+ WRITE_REG(RCC->AHB2RSTR1, 0x00000000U);\
+ WRITE_REG(RCC->AHB2RSTR2, 0x00000000U);\
+ }while(0)
+
+#define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOARST)
+
+#define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOBRST)
+
+#define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOCRST)
+
+#define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIODRST)
+
+#define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOERST)
+
+#define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOFRST)
+
+#define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOGRST)
+
+#define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOHRST)
+
+#define __HAL_RCC_GPIOI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOIRST)
+
+#define __HAL_RCC_ADC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_ADC1RST)
+
+#define __HAL_RCC_DCMI_PSSI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_DCMI_PSSIRST)
+
+#define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTGRST)
+
+#define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_AESRST)
+
+#define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_HASHRST)
+
+#define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_RNGRST)
+
+#define __HAL_RCC_PKA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_PKARST)
+
+#define __HAL_RCC_SAES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SAESRST)
+
+#define __HAL_RCC_OSPIM_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OCTOSPIMRST)
+
+#define __HAL_RCC_OTFDEC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC1RST)
+
+#define __HAL_RCC_OTFDEC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC2RST)
+
+#define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC1RST)
+
+#define __HAL_RCC_SDMMC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC2RST)
+
+#define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_FSMCRST)
+
+#define __HAL_RCC_OSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI1RST)
+
+#define __HAL_RCC_OSPI2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI2RST)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset
+ * @brief Force or release AHB3 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000661U)
+
+#define __HAL_RCC_LPGPIO1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_LPGPIO1RST)
+
+#define __HAL_RCC_ADC4_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_ADC4RST)
+
+#define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_DAC1RST)
+
+#define __HAL_RCC_LPDMA1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_LPDMA1RST)
+
+#define __HAL_RCC_ADF1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_ADF1RST)
+
+#define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000U)
+
+#define __HAL_RCC_LPGPIO1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_LPGPIO1RST)
+
+#define __HAL_RCC_ADC4_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_ADC4RST)
+
+#define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_DAC1RST)
+
+#define __HAL_RCC_LPDMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_LPDMA1RST)
+
+#define __HAL_RCC_ADF1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_ADF1RST)
+/**
+ * @}
+ */
+/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
+ * @brief Force or release APB1 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_APB1_FORCE_RESET() do { \
+ WRITE_REG(RCC->APB1RSTR1, 0x027E403FU); \
+ WRITE_REG(RCC->APB1RSTR2, 0x00800222U); \
+ } while(0)
+
+#define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
+
+#define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
+
+#define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
+
+#define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
+
+#define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
+
+#define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
+
+#define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
+
+#define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
+
+#define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
+
+#define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
+
+#define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
+
+#define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
+
+#define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
+
+#define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
+
+#define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)
+
+#define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
+
+#define __HAL_RCC_FDCAN1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_FDCAN1RST)
+
+#define __HAL_RCC_UCPD_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST)
+
+#define __HAL_RCC_APB1_RELEASE_RESET() do { \
+ WRITE_REG(RCC->APB1RSTR1, 0x00000000U); \
+ WRITE_REG(RCC->APB1RSTR2, 0x00000000U); \
+ } while(0)
+
+#define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
+
+#define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
+
+#define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
+
+#define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
+
+#define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
+
+#define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
+
+#define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
+
+#define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
+
+#define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
+
+#define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
+
+#define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
+
+#define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
+
+#define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
+
+#define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
+
+#define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)
+
+#define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
+
+#define __HAL_RCC_FDCAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_FDCAN1RST)
+
+#define __HAL_RCC_UCPD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
+ * @brief Force or release APB2 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00677800U)
+
+#define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
+
+#define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
+
+#define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
+
+#define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
+
+#define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
+
+#define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
+
+#define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
+
+#define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
+
+#define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
+
+#define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U)
+
+#define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
+
+#define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
+
+#define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
+
+#define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
+
+#define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
+
+#define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
+
+#define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
+
+#define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
+
+#define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB3_Force_Release_Reset APB3 Peripheral Force Release Reset
+ * @brief Force or release APB3 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_APB3_FORCE_RESET() WRITE_REG(RCC->APB3RSTR, 0x0010F8E2U)
+
+#define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_SYSCFGRST)
+
+#define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_SPI3RST)
+
+#define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPUART1RST)
+
+#define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I2C3RST)
+
+#define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM1RST)
+
+#define __HAL_RCC_LPTIM3_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM3RST)
+
+#define __HAL_RCC_LPTIM4_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM4RST)
+
+#define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_OPAMPRST)
+
+#define __HAL_RCC_COMP_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_COMPRST)
+
+#define __HAL_RCC_VREF_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_VREFRST)
+
+#define __HAL_RCC_APB3_RELEASE_RESET() WRITE_REG(RCC->APB3RSTR, 0x00000000U)
+
+#define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_SYSCFGRST)
+
+#define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_SPI3RST)
+
+#define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPUART1RST)
+
+#define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I2C3RST)
+
+#define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM1RST)
+
+#define __HAL_RCC_LPTIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM3RST)
+
+#define __HAL_RCC_LPTIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM4RST)
+
+#define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_OPAMPRST)
+
+#define __HAL_RCC_COMP_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_COMPRST)
+
+#define __HAL_RCC_VREF_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_VREFRST)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB1_Peripheral_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable
+ * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep and Stop) mode.
+ * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock
+ * is enabled only when a peripheral requests AHB clock.
+ * @{
+ */
+#define __HAL_RCC_GPDMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPDMA1SMEN)
+
+#define __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN)
+
+#define __HAL_RCC_FMAC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN)
+
+#define __HAL_RCC_MDF1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_MDF1SMEN)
+
+#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
+
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
+
+#define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
+
+#define __HAL_RCC_RAMCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_RAMCFGSMEN)
+
+#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN)
+
+#define __HAL_RCC_GTZC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZC1SMEN)
+
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_BKPSRAMSMEN)
+
+#define __HAL_RCC_ICACHE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_ICACHESMEN)
+
+#define __HAL_RCC_DCACHE1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DCACHE1SMEN)
+
+#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
+
+#define __HAL_RCC_GPDMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPDMA1SMEN)
+
+#define __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN)
+
+#define __HAL_RCC_FMAC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN)
+
+#define __HAL_RCC_MDF1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_MDF1SMEN)
+
+#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
+
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
+
+#define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
+
+#define __HAL_RCC_RAMCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_RAMCFGSMEN)
+
+#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN)
+
+#define __HAL_RCC_GTZC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZC1SMEN)
+
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_BKPSRAMSMEN)
+
+#define __HAL_RCC_ICACHE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_ICACHESMEN)
+
+#define __HAL_RCC_DCACHE1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DCACHE1SMEN)
+
+#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB2_Peripheral_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable
+ * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep and Stop) mode.
+ * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock
+ * is enabled only when a peripheral requests AHB clock.
+ * @{
+ */
+#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOASMEN)
+
+#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOBSMEN)
+
+#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOCSMEN)
+
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIODSMEN)
+
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOESMEN)
+
+#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOFSMEN)
+
+#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOGSMEN)
+
+#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOHSMEN)
+
+#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOISMEN)
+
+#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_ADC1SMEN)
+
+#define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_DCMI_PSSISMEN)
+
+#define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTGSMEN)
+
+#if defined(AES)
+#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_AESSMEN);
+#endif /* AES */
+
+#if defined(HASH)
+#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_HASHSMEN)
+#endif /* HASH */
+
+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_RNGSMEN)
+
+#define __HAL_RCC_PKA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_PKASMEN)
+
+#define __HAL_RCC_SAES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SAESSMEN)
+
+#define __HAL_RCC_OCTOSPIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OCTOSPIMSMEN)
+
+#define __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTFDEC1SMEN)
+
+#define __HAL_RCC_OTFDEC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTFDEC2SMEN)
+
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SDMMC1SMEN)
+
+#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SDMMC2SMEN)
+
+#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SRAM2SMEN)
+
+#define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SRAM3SMEN)
+
+#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_FSMCSMEN)
+
+#define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_OCTOSPI1SMEN)
+
+#define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_OCTOSPI2SMEN)
+
+#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOASMEN)
+
+#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOBSMEN)
+
+#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOCSMEN)
+
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIODSMEN)
+
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOESMEN)
+
+#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOFSMEN)
+
+#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOGSMEN)
+
+#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOHSMEN)
+
+#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOISMEN)
+
+#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_ADC1SMEN)
+
+#define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_DCMI_PSSISMEN)
+
+#define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTGSMEN)
+
+#if defined(AES)
+#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_AESSMEN);
+#endif /* AES */
+
+#if defined(HASH)
+#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_HASHSMEN)
+#endif /* HASH */
+
+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_RNGSMEN)
+
+#define __HAL_RCC_PKA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_PKASMEN)
+
+#define __HAL_RCC_SAES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SAESSMEN)
+
+#define __HAL_RCC_OCTOSPIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OCTOSPIMSMEN)
+
+#define __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTFDEC1SMEN)
+
+#define __HAL_RCC_OTFDEC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTFDEC2SMEN)
+
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SDMMC1SMEN)
+
+#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SDMMC2SMEN)
+
+#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SRAM2SMEN)
+
+#define __HAL_RCC_SRAM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SRAM3SMEN)
+
+#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_FSMCSMEN)
+
+#define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_OCTOSPI1SMEN)
+
+#define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_OCTOSPI2SMEN)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3SMENR Peripheral Clock Sleep Enable Disable
+ * @brief Enable or disable the AHB3SMENR peripheral clock during Low Power (Sleep and STOP ) mode.
+ * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock
+ * is enabled only when a peripheral requests AHB clock.
+ * @{
+ */
+#define __HAL_RCC_LPGPIO1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPGPIO1SMEN)
+
+#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_PWRSMEN)
+
+#define __HAL_RCC_ADC4_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_ADC4SMEN)
+
+#define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_DAC1SMEN)
+
+#define __HAL_RCC_LPDMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPDMA1SMEN)
+
+#define __HAL_RCC_ADF1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_ADF1SMEN)
+
+#define __HAL_RCC_GTZC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_GTZC2SMEN)
+
+#define __HAL_RCC_SRAM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_SRAM4SMEN)
+
+#define __HAL_RCC_LPGPIO1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPGPIO1SMEN)
+
+#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_PWRSMEN)
+
+#define __HAL_RCC_ADC4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_ADC4SMEN)
+
+#define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_DAC1SMEN)
+
+#define __HAL_RCC_LPDMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPDMA1SMEN)
+
+#define __HAL_RCC_ADF1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_ADF1SMEN)
+
+#define __HAL_RCC_GTZC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_GTZC2SMEN)
+
+#define __HAL_RCC_SRAM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_SRAM4SMEN)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
+ * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep and Stop) mode.
+ * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock
+ * is enabled only when a peripheral requests APB clock.
+ * @{
+ */
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
+
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
+
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
+
+#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
+
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
+
+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
+
+#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
+
+#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
+
+#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
+
+#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
+
+#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
+
+#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
+
+#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
+
+#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
+
+#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
+
+#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)
+
+#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
+
+#define __HAL_RCC_FDCAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_FDCAN1SMEN)
+
+#define __HAL_RCC_UCPD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN)
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
+
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
+
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
+
+#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
+
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
+
+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
+
+#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
+
+#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
+
+#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
+
+#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
+
+#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
+
+#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
+
+#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
+
+#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
+
+#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
+
+#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)
+
+#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
+
+#define __HAL_RCC_FDCAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_FDCAN1SMEN)
+
+#define __HAL_RCC_UCPD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
+ * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep and Stop) mode.
+ * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP or STOP mode, the pseripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock
+ * is enabled only when a peripheral requests APB clock.
+ * @{
+ */
+#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
+
+#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
+
+#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
+
+#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
+
+#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
+
+#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
+
+#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
+
+#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
+
+#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
+
+#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
+
+#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
+
+#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
+
+#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
+
+#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
+
+#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
+
+#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
+
+#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
+
+#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB3_Clock_Sleep_Enable_Disable APB3 Peripheral Clock Sleep Enable Disable
+ * @brief Enable or disable the APB3 peripheral clock during Low Power (Sleep and Stop) mode.
+ * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock
+ * is enabled only when a peripheral requests APB clock.
+ * @{
+ */
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_SYSCFGSMEN)
+
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_SPI3SMEN)
+
+#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPUART1SMEN)
+
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_I2C3SMEN)
+
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM1SMEN)
+
+#define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM3SMEN)
+
+#define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM4SMEN)
+
+#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_OPAMPSMEN)
+
+#define __HAL_RCC_COMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_COMPSMEN)
+
+#define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_VREFSMEN)
+
+#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_RTCAPBSMEN)
+
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_SYSCFGSMEN)
+
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_SPI3SMEN)
+
+#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPUART1SMEN)
+
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_I2C3SMEN)
+
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM1SMEN)
+
+#define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM3SMEN)
+
+#define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM4SMEN)
+
+#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_OPAMPSMEN)
+
+#define __HAL_RCC_COMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_COMPSMEN)
+
+#define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_VREFSMEN)
+
+#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_RTCAPBSMEN)
+/**
+ * @}
+ */
+
+/** @brief Enable or disable peripheral bus clock when SRD domain is in DRUN
+ * @note After reset, peripheral clock is disabled when CPUs are in CSTOP
+ * @{
+ */
+#define __HAL_RCC_SPI3_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_SPI3AMEN)
+
+#define __HAL_RCC_LPUART1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPUART1AMEN)
+
+#define __HAL_RCC_I2C3_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_I2C3AMEN)
+
+#define __HAL_RCC_LPTIM1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM1AMEN)
+
+#define __HAL_RCC_LPTIM3_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM3AMEN)
+
+#define __HAL_RCC_LPTIM4_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM4AMEN)
+
+#define __HAL_RCC_OPAMP_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_OPAMPAMEN)
+
+#define __HAL_RCC_COMP12_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_COMPAMEN)
+
+#define __HAL_RCC_ADC4_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_ADC4AMEN)
+
+#define __HAL_RCC_VREF_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_VREFAMEN)
+
+#define __HAL_RCC_RTCAPB_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_RTCAPBAMEN)
+
+#define __HAL_RCC_LPGPIO1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPGPIO1AMEN)
+
+#define __HAL_RCC_DAC1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_DAC1AMEN)
+
+#define __HAL_RCC_LPDMA1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPDMA1AMEN)
+
+#define __HAL_RCC_ADF1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_ADF1AMEN)
+
+#define __HAL_RCC_SRAM4_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_SRAM4AMEN)
+
+
+#define __HAL_RCC_SPI3_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_SPI3AMEN)
+
+#define __HAL_RCC_LPUART1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPUART1AMEN)
+
+#define __HAL_RCC_I2C3_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_I2C3AMEN)
+
+#define __HAL_RCC_LPTIM1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM1AMEN)
+
+#define __HAL_RCC_LPTIM3_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM3AMEN)
+
+#define __HAL_RCC_LPTIM4_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM4AMEN)
+
+#define __HAL_RCC_OPAMP_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_OPAMPAMEN)
+
+#define __HAL_RCC_COMP12_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_COMPAMEN)
+
+#define __HAL_RCC_ADC4_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_ADC4AMEN)
+
+#define __HAL_RCC_VREF_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_VREFAMEN)
+
+#define __HAL_RCC_RTCAPB_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_RTCAPBAMEN)
+
+#define __HAL_RCC_LPGPIO1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPGPIO1AMEN)
+
+#define __HAL_RCC_DAC1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_DAC1AMEN)
+
+#define __HAL_RCC_LPDMA1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPDMA1AMEN)
+
+#define __HAL_RCC_ADF1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_ADF1AMEN)
+
+#define __HAL_RCC_SRAM4_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_SRAM4AMEN)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset
+ * @{
+ */
+
+/** @brief Macros to force or release the Backup domain reset.
+ * @note This function resets the RTC peripheral (including the backup registers)
+ * and the RTC clock source selection in RCC_CSR register.
+ * @note The BKPSRAM is not affected by this reset.
+ * @retval None
+ */
+#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
+
+#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
+ * @{
+ */
+
+/** @brief Macros to enable or disable the RTC clock.
+ * @note As the RTC is in the Backup domain and write access is denied to
+ * this domain after reset, you have to enable write access using
+ * HAL_PWR_EnableBkUpAccess() function before to configure the RTC
+ * (to be done once after reset).
+ * @note These macros must be used after the RTC clock source was selected.
+ * @retval None
+ */
+#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
+
+#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
+
+/**
+ * @}
+ */
+
+/** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI).
+ * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
+ * It is used (enabled by hardware) as system clock source after startup
+ * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
+ * of the HSE used directly or indirectly as system clock (if the Clock
+ * Security System CSS is enabled).
+ * @note HSI can not be stopped if it is used as system clock source. In this case,
+ * you have to select another source of the system clock then stop the HSI.
+ * @note After enabling the HSI, the application software should wait on HSIRDY
+ * flag to be set indicating that HSI clock is stable and can be used as
+ * system clock source.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
+ * clock cycles.
+ * @retval None
+ */
+#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
+
+#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
+
+/** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value.
+ * @note The calibration is used to compensate for the variations in voltage
+ * and temperature that influence the frequency of the internal HSI RC.
+ * @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value
+ * (default is RCC_HSICALIBRATION_DEFAULT).
+ * This parameter must be a number between 0 and 0x20.
+ * @retval None
+ */
+#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \
+ MODIFY_REG(RCC->ICSCR3, RCC_ICSCR3_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_ICSCR3_HSITRIM_Pos)
+
+
+/**
+ * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
+ * in STOP mode to be quickly available as kernel clock for USARTs, LPUART and I2Cs.
+ * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication
+ * speed because of the HSI startup time.
+ * @note The enable of this function has not effect on the HSION bit.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
+
+#define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
+
+/**
+ * @brief Macros to enable or disable the force of the Internal Multi Speed kernel oscillator (MSIK)
+ * in STOP mode to be quickly available as kernel clock for USARTs, LPUART and I2Cs.
+ * @note Keeping the MSIK ON in STOP mode allows to avoid slowing down the communication
+ * speed because of the MSIK startup time.
+ * @note The enable of this function has not effect on the MSIKON bit.
+ * @note The MSIKERON must be configured at 0 before entreing stop 3 mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+#define __HAL_RCC_MSIKSTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSIKERON)
+
+#define __HAL_RCC_MSIKSTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSIKERON)
+
+/**
+ * @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI).
+ * @note The MSI is stopped by hardware when entering STOP and STANDBY modes.
+ * It is used (enabled by hardware) as system clock source after
+ * startup from Reset, wakeup from STOP and STANDBY mode, or in case
+ * of failure of the HSE used directly or indirectly as system clock
+ * (if the Clock Security System CSS is enabled).
+ * @note MSI can not be stopped if it is used as system clock source.
+ * In this case, you have to select another source of the system
+ * clock then stop the MSI.
+ * @note After enabling the MSI, the application software should wait on
+ * MSIRDY flag to be set indicating that MSI clock is stable and can
+ * be used as system clock source.
+ * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
+ * clock cycles.
+ * @retval None
+ */
+#define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSISON)
+
+#define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSISON)
+
+/**
+ * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode
+ * @note After restart from Reset , the MSI clock is around 4 MHz.
+ * After stop the startup clock can be MSI (at any of its possible
+ * frequencies, the one that was used before entering stop mode) or HSI.
+ * After Standby its frequency can be selected between 4 possible values
+ * (1, 3.072, 4 or 8 MHz).
+ * @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready
+ * (MSIRDY=1).
+ * @note The MSI clock range after reset can be modified on the fly.
+ * @param __MSIRANGEVALUE__: specifies the MSI clock range.
+ * This parameter must be one of the following values:
+ * @arg @ref RCC_MSIRANGE_0 MSI clock is around 48 MHz
+ * @arg @ref RCC_MSIRANGE_1 MSI clock is around 24 KHz
+ * @arg @ref RCC_MSIRANGE_2 MSI clock is around 16 MHz
+ * @arg @ref RCC_MSIRANGE_3 MSI clock is around 12 MHz
+ * @arg @ref RCC_MSIRANGE_4 MSI clock is around 4 MHz (default after Reset)
+ * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz
+ * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.33 MHz
+ * @arg @ref RCC_MSIRANGE_7 MSI clock is around 1 MHz
+ * @arg @ref RCC_MSIRANGE_8 MSI clock is around 3.072 MHz
+ * @arg @ref RCC_MSIRANGE_9 MSI clock is around 1.536 MHz
+ * @arg @ref RCC_MSIRANGE_10 MSI clock is around 1.024 MHz
+ * @arg @ref RCC_MSIRANGE_11 MSI clock is around 768 KHz
+ * @arg @ref RCC_MSIRANGE_12 MSI clock is around 400 KHz
+ * @arg @ref RCC_MSIRANGE_13 MSI clock is around 200 KHz
+ * @arg @ref RCC_MSIRANGE_14 MSI clock is around 133 KHz
+ * @arg @ref RCC_MSIRANGE_15 MSI clock is around 100 KHz
+ * @retval None
+ */
+#define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \
+ do { \
+ SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL); \
+ MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSISRANGE, (__MSIRANGEVALUE__)); \
+ } while(0)
+/**
+ * @brief Macro configures the Internal Multi Speed kernel oscillator (MSIK) clock range in run mode
+ * @note After restart from Reset , the MSIK clock is around 4 MHz.
+ * After stop the startup clock can be MSIK (at any of its possible
+ * frequencies, the one that was used before entering stop mode) or HSI.
+ * After Standby its frequency can be selected between 4 possible values
+ * (1, 3.072, 4 or 8 MHz).
+ * @note MSIKRANGE can be modified when MSIK is OFF (MSIKON=0) or when MSIK is ready
+ * (MSIKRDY=1).
+ * @note The MSI clock range after reset can be modified on the fly.
+ * @param __MSIKRANGEVALUE__: specifies the MSI clock range.
+ * @arg @ref RCC_MSIKRANGE_0 MSIK clock is around 48 MHz
+ * @arg @ref RCC_MSIKRANGE_1 MSIK clock is around 24 KHz
+ * @arg @ref RCC_MSIKRANGE_2 MSIK clock is around 16 MHz
+ * @arg @ref RCC_MSIKRANGE_3 MSIK clock is around 12 MHz
+ * @arg @ref RCC_MSIKRANGE_4 MSIK clock is around 4 MHz (default after Reset)
+ * @arg @ref RCC_MSIKRANGE_5 MSIK clock is around 2 MHz
+ * @arg @ref RCC_MSIKRANGE_6 MSIK clock is around 1.33 MHz
+ * @arg @ref RCC_MSIKRANGE_7 MSIK clock is around 1 MHz
+ * @arg @ref RCC_MSIKRANGE_8 MSIK clock is around 3.072 MHz
+ * @arg @ref RCC_MSIKRANGE_9 MSIK clock is around 1.536 MHz
+ * @arg @ref RCC_MSIKRANGE_10 MSIK clock is around 1.024 MHz
+ * @arg @ref RCC_MSIKRANGE_11 MSIK clock is around 768 KHz
+ * @arg @ref RCC_MSIKRANGE_12 MSIK clock is around 400 KHz
+ * @arg @ref RCC_MSIKRANGE_13 MSIK clock is around 200 KHz
+ * @arg @ref RCC_MSIKRANGE_14 MSIK clock is around 133 KHz
+ * @arg @ref RCC_MSIKRANGE_15 MSIK clock is around 100 KHz
+ * @retval None
+ */
+#define __HAL_RCC_MSIK_RANGE_CONFIG(__MSIKRANGEVALUE__) \
+ do { \
+ SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL); \
+ MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSIKRANGE, (__MSIKRANGEVALUE__)); \
+ } while(0)
+
+/** @brief Macros to enable or disable the MSI bias mode selection.
+ * @note By default the MSI bias is in continuous mode in order to maintain
+ * the output clocks accuracy.
+ * @note Setting this bit reduces the MSI consumption under range 4 but decrease its accuracy.
+ * @retval None
+ */
+#define __HAL_RCC_MSIBIAS_SELECTION_ENABLE() SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIBIAS)
+
+#define __HAL_RCC_MSIBIAS_SELECTION_DISABLE() CLEAR_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIBIAS)
+
+/** @brief Macros to enable or disable LSE clock glitch filter .
+ * @note The glitches on LSE can be filtred by setting the LSEGFON.
+ * @note LSEGFON must be written when the LSE is disabled (LSEON = 0 and LSERDY = 0).
+ * @retval None
+ */
+
+#define __HAL_RCC_LSE_GLITCHFILTER_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_LSEGFON )
+
+#define __HAL_RCC_LSE_GLITCHFILTER_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEGFON )
+/**
+ * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode
+ * After Standby its frequency can be selected between 5 possible values (4, 2, 1.5, 1, or 3.072 MHz).
+ * @param __MSIRANGEVALUE__: specifies the MSI clock range.
+ * This parameter must be one of the following values:
+ * @arg @ref RCC_MSIRANGE_4 MSI clock is around 4 MHz (default after Reset)
+ * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz
+ * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.5 MHz
+ * @arg @ref RCC_MSIRANGE_7 MSI clock is around 1 MHz
+ * @arg @ref RCC_MSIRANGE_8 MSI clock is around 3.072 MHz
+ * @retval None
+ */
+#define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) do {SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL);\
+ MODIFY_REG(RCC->CSR, RCC_CSR_MSISSRANGE,\
+ (__MSIRANGEVALUE__) >> (RCC_ICSCR1_MSISRANGE_Pos -\
+ RCC_CSR_MSISSRANGE_Pos));\
+ } while(0)
+/**
+ * @brief Macro configures the Internal Multi Speed oscillator (MSIK) clock range after Standby mode
+ * After Standby its frequency can be selected between 5 possible values (4, 2, 1.5, 1, or 3.072 MHz).
+ * @param __MSIRANGEVALUE__: specifies the MSI clock range.
+ * This parameter must be one of the following values:
+ * @arg @ref RCC_MSIRANGE_4 MSI clock is around 4 MHz (default after Reset)
+ * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz
+ * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.5 MHz
+ * @arg @ref RCC_MSIRANGE_7 MSI clock is around 1 MHz
+ * @arg @ref RCC_MSIRANGE_8 MSI clock is around 3.072 MHz
+ * @retval None
+ */
+#define __HAL_RCC_MSIK_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) do {SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL); \
+ MODIFY_REG(RCC->CSR, RCC_CSR_MSISSRANGE,\
+ (__MSIRANGEVALUE__) >> (RCC_ICSCR1_MSISRANGE_Pos -\
+ RCC_CSR_MSISSRANGE_Pos));\
+ } while(0)
+
+/** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode
+ * @retval MSI clock range.
+ * This parameter must be one of the following values:
+ * @arg @ref RCC_MSIRANGE_0 MSI clock is around 48 MHz
+ * @arg @ref RCC_MSIRANGE_1 MSI clock is around 24 KHz
+ * @arg @ref RCC_MSIRANGE_2 MSI clock is around 16 MHz
+ * @arg @ref RCC_MSIRANGE_3 MSI clock is around 12 MHz
+ * @arg @ref RCC_MSIRANGE_4 MSI clock is around 4 MHz
+ * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz
+ * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.33 MHz
+ * @arg @ref RCC_MSIRANGE_7 MSI clock is around 1 MHz
+ * @arg @ref RCC_MSIRANGE_8 MSI clock is around 3.072 MHz
+ * @arg @ref RCC_MSIRANGE_9 MSI clock is around 1.536 MHz
+ * @arg @ref RCC_MSIRANGE_10 MSI clock is around 1.024 MHz
+ * @arg @ref RCC_MSIRANGE_11 MSI clock is around 768 KHz
+ * @arg @ref RCC_MSIRANGE_12 MSI clock is around 400 KHz
+ * @arg @ref RCC_MSIRANGE_13 MSI clock is around 200 KHz
+ * @arg @ref RCC_MSIRANGE_14 MSI clock is around 133 KHz
+ * @arg @ref RCC_MSIRANGE_15 MSI clock is around 100 KHz
+ */
+#define __HAL_RCC_GET_MSI_RANGE() ((READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL) != 0U) ? \
+ (uint32_t)(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSISRANGE)) : \
+ (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISSRANGE) << \
+ (RCC_ICSCR1_MSISRANGE_Pos - RCC_CSR_MSISSRANGE_Pos)))
+
+/** @brief Macro to get the Internal Multi Speed kernel oscillator (MSIK) clock range in run mode
+ * @retval MSIK clock range.
+ * This parameter must be one of the following values:
+ * @arg @ref RCC_MSIRANGE_0 MSI clock is around 48 MHz
+ * @arg @ref RCC_MSIRANGE_1 MSI clock is around 24 KHz
+ * @arg @ref RCC_MSIRANGE_2 MSI clock is around 16 MHz
+ * @arg @ref RCC_MSIRANGE_3 MSI clock is around 12 MHz
+ * @arg @ref RCC_MSIRANGE_4 MSI clock is around 4 MHz
+ * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz
+ * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.33 MHz
+ * @arg @ref RCC_MSIRANGE_7 MSI clock is around 1 MHz
+ * @arg @ref RCC_MSIRANGE_8 MSI clock is around 3.072 MHz
+ * @arg @ref RCC_MSIRANGE_9 MSI clock is around 1.536 MHz
+ * @arg @ref RCC_MSIRANGE_10 MSI clock is around 1.024 MHz
+ * @arg @ref RCC_MSIRANGE_11 MSI clock is around 768 KHz
+ * @arg @ref RCC_MSIRANGE_12 MSI clock is around 400 KHz
+ * @arg @ref RCC_MSIRANGE_13 MSI clock is around 200 KHz
+ * @arg @ref RCC_MSIRANGE_14 MSI clock is around 133 KHz
+ * @arg @ref RCC_MSIRANGE_15 MSI clock is around 100 KHz
+ */
+#define __HAL_RCC_GET_MSIK_RANGE() ((READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL) != 0U) ? \
+ (uint32_t)(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIKRANGE)) : \
+ (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSIKSRANGE) << \
+ (RCC_ICSCR1_MSIKRANGE_Pos - RCC_CSR_MSIKSRANGE_Pos)))
+
+/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
+ * @note After enabling the LSI, the application software should wait on
+ * LSIRDY flag to be set indicating that LSI clock is stable and can
+ * be used to clock the IWDG and/or the RTC.
+ * @note LSI can not be disabled if the IWDG is running.
+ * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
+ * clock cycles.
+ * @retval None
+ */
+#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_LSION)
+
+#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSION|RCC_BDCR_LSIPREDIV)
+
+/**
+ * @brief Macro to configure the External High Speed oscillator (HSE).
+ * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
+ * supported by this macro. User should request a transition to HSE Off
+ * first and then HSE On or HSE Bypass.
+ * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
+ * software should wait on HSERDY flag to be set indicating that HSE clock
+ * is stable and can be used to clock the PLL and/or system clock.
+ * @note HSE state can not be changed if it is used directly or through the
+ * PLL as system clock. In this case, you have to select another source
+ * of the system clock then change the HSE state (ex. disable it).
+ * @note The HSE is stopped by hardware when entering STOP and STANDBY or shutdown modes.
+ * @param __STATE__: specifies the new state of the HSE.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after
+ * 6 HSE oscillator clock cycles.
+ * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator.
+ * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock.
+ * @arg @ref RCC_HSE_BYPASS_DIGITAL HSE oscillator bypassed through I/O Schmitt trigger .
+ * @retval None
+ */
+#define __HAL_RCC_HSE_CONFIG(__STATE__) \
+ do { \
+ if((__STATE__) == RCC_HSE_ON) \
+ { \
+ SET_BIT(RCC->CR, RCC_CR_HSEON); \
+ } \
+ else if((__STATE__) == RCC_HSE_BYPASS) \
+ { \
+ SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \
+ SET_BIT(RCC->CR, RCC_CR_HSEON); \
+ } \
+ else if((__STATE__) == RCC_HSE_BYPASS_DIGITAL) \
+ { \
+ SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
+ SET_BIT(RCC->CR, RCC_CR_HSEEXT); \
+ SET_BIT(RCC->CR, RCC_CR_HSEON); \
+ } \
+ else \
+ { \
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
+ } \
+ } while(0)
+
+/** @brief Macro to enable or disable the LSE system clock.
+ * @note This clock can be used by any peripheral when its source clock is the LSE or at system
+ * in case of one of the LSCOSEL, MCO, MSI PLL mode or CSS on LSE is needed.
+ * @note The LSESYS clock can be generated even if LSESYSEN= 0 if the LSE clock is requested by
+ * the CSS on LSE, by a peripheral or any other source clock using LSE.
+ * @retval None
+ */
+#define __HAL_RCC_LSESYS_ENABLE() SET_BIT(RCC->BDCR,RCC_BDCR_LSESYSEN)
+
+#define __HAL_RCC_LSESYS_DISABLE() CLEAR_BIT(RCC->BDCR,RCC_BDCR_LSESYSEN)
+
+
+/** @brief Macro to set Low-speed clock (LSI) divider.
+ * @note This bit can be written only when the LSI is disabled (LSION = 0 and LSIRDY = 0).
+ * The LSIPREDIV cannot be changed if the LSI is used by the IWDG or by the RTC.
+ *
+ * @param __DIVIDER__ : specifies the divider value
+ * This parameter can be one of the following values
+ * @arg @ref RCC_LSI_DIV1
+ * @arg @ref RCC_LSI_DIV128
+ * @retval None
+ */
+#define __HAL_RCC_LSI_DIV_CONFIG(__DIVIDER__) \
+ do { \
+ if((__DIVIDER__) == RCC_LSI_DIV128) \
+ { \
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSIPREDIV); \
+ } \
+ else \
+ { \
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSIPREDIV); \
+ } \
+ } while(0)
+
+/**
+ * @brief Macro to configure the External Low Speed oscillator (LSE).
+ * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
+ * supported by this macro. User should request a transition to LSE Off
+ * first and then LSE On or LSE Bypass.
+ * @note As the LSE is in the Backup domain and write access is denied to
+ * this domain after reset, you have to enable write access using
+ * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
+ * (to be done once after reset).
+ * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
+ * software should wait on LSERDY flag to be set indicating that LSE clock
+ * is stable and can be used to clock the RTC.
+ * @param __STATE__: specifies the new state of the LSE.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after
+ * 6 LSE oscillator clock cycles.
+ * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator.
+ * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
+ * @retval None
+ */
+#define __HAL_RCC_LSE_CONFIG(__STATE__) \
+ do { \
+ if((__STATE__) == RCC_LSE_ON) \
+ { \
+ SET_BIT(RCC->BDCR,RCC_BDCR_LSEON); \
+ } \
+ else if((__STATE__) == RCC_LSE_BYPASS) \
+ { \
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
+ } \
+ else \
+ { \
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
+ } \
+ } while(0)
+
+/** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48).
+ * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
+ * @note After enabling the HSI48, the application software should wait on HSI48RDY
+ * flag to be set indicating that HSI48 clock is stable.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSI48ON)
+
+#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON)
+
+/** @brief Macros to enable or disable the Internal multi-speed RC oscillator clock (MSIK).
+ * @note if the peripheral requests its kernel clock in Stop 0 or Stop 1 mode,MSIK is woken up
+ * @note After enabling the MSIK, the application software should wait on MSIKRDY
+ * flag to be set indicating that MSIK clock is stable.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+#define __HAL_RCC_MSIK_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSIKON)
+
+#define __HAL_RCC_MSIK_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSIKON)
+
+/** @brief Macros to enable or disable the secure Internal High Speed oscillator (SHSI).
+ * @note The SHSI is stopped by hardware when entering STOP and STANDBY modes.
+ * @note After enabling the SHSI, the application software should wait on SHSI
+ * flag to be set indicating that SHSI clock is stable.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+#define __HAL_RCC_SHSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_SHSION)
+
+#define __HAL_RCC_SHSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_SHSION)
+
+/** @brief Macros to configure the RTC clock (RTCCLK).
+ * @note As the RTC clock configuration bits are in the Backup domain and write
+ * access is denied to this domain after reset, you have to enable write
+ * access using the Power Backup Access macro before to configure
+ * the RTC clock source (to be done once after reset).
+ * @note Once the RTC clock is configured it cannot be changed unless the
+ * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
+ * a Power On Reset (POR).
+ *
+ * @param __RTC_CLKSOURCE__: specifies the RTC clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock.
+ * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
+ * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
+ * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected
+ *
+ * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
+ * work in STOP and STANDBY modes, and can be used as wakeup source.
+ * However, when the HSE clock is used as RTC clock source, the RTC
+ * cannot be used in STOP and STANDBY modes.
+ * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
+ * RTC clock source).
+ * @retval None
+ */
+#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \
+ MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
+
+/** @brief Macro to get the RTC clock source.
+ * @retval The returned value can be one of the following:
+ * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock.
+ * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
+ * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
+ * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected
+ */
+#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
+
+/** @brief Macros to enable or disable the main PLL.
+ * @note After enabling the main PLL, the application software should wait on
+ * PLLRDY flag to be set indicating that PLL clock is stable and can
+ * be used as system clock source.
+ * @note The main PLL can not be disabled if it is used as system clock source
+ * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
+ */
+#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL1ON)
+#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON)
+
+/**
+ * @brief Enables or disables each clock output (PLL_P_CLK, PLL_Q_CLK, PLL_R_CLK)
+ * @note Enabling/disabling Those Clocks can be any time without the need to stop the PLL,
+ * This is mainly used to save Power.
+ * @param __PLL1_CLOCKOUT__: specifies the PLL clock to be outputted
+ * This parameter can be one of the following values:
+ * @arg RCC_PLL1_DIVP: This clock is used to generate an accurate clock to achieve,
+ * high-quality audio performance on SAI interface.
+ * @arg RCC_PLL1_DIVQ: This Clock is used to generate the clock for the USB FS(48 MHz),
+ * the random analog generator (<=48 MHz) and the OCTOSPI1/2.
+ * @arg RCC_PLL1_DIVR: This Clock is used to generate the high speed system clock (up to 160MHz)
+ * @retval None
+ *
+ */
+#define __HAL_RCC_PLLCLKOUT_ENABLE(__PLL1_CLOCKOUT__) SET_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__))
+
+#define __HAL_RCC_PLLCLKOUT_DISABLE(__PLL1_CLOCKOUT__) CLEAR_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__))
+
+/**
+ * @brief Macro to get the PLL clock output enable status.
+ * @param __PLL1_CLOCKOUT__ specifies the PLL1 clock to be output.
+ * This parameter can be one of the following values:
+ * @arg RCC_PLL1_DIVP: This clock is used to generate an accurate clock to achieve,
+ * high-quality audio performance on SAI interface.
+ * @arg RCC_PLL1_DIVQ: This Clock is used to generate the clock for the USB FS(48 MHz),
+ * the random analog generator (<=48 MHz) and the OCTOSPI1/2.
+ * @arg RCC_PLL1_DIVR: This Clock is used to generate the high speed system clock (up to 160MHz)
+ * @retval SET / RESET
+ */
+#define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLL1_CLOCKOUT__) READ_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__))
+
+/**
+ * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO
+ * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL1
+ * @retval None
+ */
+#define __HAL_RCC_PLLFRACN_ENABLE() SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN)
+
+#define __HAL_RCC_PLLFRACN_DISABLE() CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN)
+
+/**
+ * @brief Macro to configure the main PLL clock source, multiplication and division factors.
+ * @note This function must be used only when the main PLL is disabled.
+ *
+ * @param __PLL1SOURCE__: specifies the PLL entry clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_PLLSOURCE_MSI: MSI oscillator clock selected as PLL clock entry
+ * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
+ * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
+ * @note This clock source (__PLL1SOURCE__) is common for the main PLL1 (main PLL) and PLL2 & PLL3 .
+ *
+ * @param __PLL1MBOOST__: specifies the division factor for the EPOD clock
+ * This parameter must be a value of @ref RCC_PLLMBOOST_EPOD_Clock_Divider.
+ *
+ * @param __PLL1M__: specifies the division factor for PLL VCO input clock
+ * This parameter must be a number between 1 and 63.
+ * @note You have to set the PLLM parameter correctly to ensure that the VCO input
+ * frequency ranges from 1 to 16 MHz.
+ *
+ * @param __PLL1N__: specifies the multiplication factor for PLL VCO output clock
+ * This parameter must be a number between 4 and 512.
+ * @note You have to set the PLLN parameter correctly to ensure that the VCO
+ * output frequency is between 128 and 544 MHz(Voltage range 1 or 2)
+ * between 128 and 330 MHZ (Voltage range 3) and not allowed for Voltage range 4.
+ *
+ * @param __PLL1P__: specifies the division factor for system clock.
+ * This parameter must be a number between 2 and 128 (where odd numbers not allowed)
+ *
+ * @param __PLL1Q__: specifies the division factor for peripheral kernel clocks
+ * This parameter must be a number between 1 and 128
+ *
+ * @param __PLL1R__: specifies the division factor for peripheral kernel clocks
+ * This parameter must be a number between 1 and 128
+ *
+ * @retval None
+ */
+#define __HAL_RCC_PLL_CONFIG(__PLL1SOURCE__, __PLL1MBOOST__,__PLL1M__, __PLL1N__, __PLL1P__, __PLL1Q__, __PLL1R__) \
+ do{ MODIFY_REG(RCC->PLL1CFGR,(RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M|\
+ RCC_PLL1CFGR_PLL1MBOOST), ((__PLL1SOURCE__) << RCC_PLL1CFGR_PLL1SRC_Pos) |\
+ (((__PLL1M__) - 1U) << RCC_PLL1CFGR_PLL1M_Pos) | (__PLL1MBOOST__));\
+ MODIFY_REG(RCC->PLL1DIVR ,(RCC_PLL1DIVR_PLL1N | RCC_PLL1DIVR_PLL1P | RCC_PLL1DIVR_PLL1Q |\
+ RCC_PLL1DIVR_PLL1R), ( (((__PLL1N__) - 1U ) & RCC_PLL1DIVR_PLL1N) |\
+ ((((__PLL1P__) -1U ) << RCC_PLL1DIVR_PLL1P_Pos) & \
+ RCC_PLL1DIVR_PLL1P) | \
+ ((((__PLL1Q__) -1U) << RCC_PLL1DIVR_PLL1Q_Pos) & \
+ RCC_PLL1DIVR_PLL1Q) |\
+ ((((__PLL1R__)- 1U) << RCC_PLL1DIVR_PLL1R_Pos) & \
+ RCC_PLL1DIVR_PLL1R))); \
+ } while(0)
+
+/** @brief Macro to configure the PLLs clock source.
+ * @note This function must be used only when all PLLs are disabled.
+ * @param __PLL1SOURCE__: specifies the PLLs entry clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_PLLSOURCE_MSI: MSI oscillator clock selected as PLL clock entry
+ * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
+ * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
+ */
+#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLL1SOURCE__) MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC, (__PLL1SOURCE__))
+
+/**
+ * @brief Macro to configure the main PLL clock Fractional Part Of The Multiplication Factor
+ * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO
+ * @param __PLL1FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL1 VCO
+ * It should be a value between 0 and 8191
+ * @note Warning: The software has to set correctly these bits to insure that the VCO
+ * output frequency is between its valid frequency range, which is:
+ * 192 to 836 MHz if PLL1VCOSEL = 0
+ * 150 to 420 MHz if PLL1VCOSEL = 1.
+ * @retval None
+ */
+#define __HAL_RCC_PLLFRACN_CONFIG(__PLL1FRACN__) MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_PLL1FRACN,\
+ (uint32_t)(__PLL1FRACN__) << \
+ RCC_PLL1FRACR_PLL1FRACN_Pos)
+
+/** @brief Macro to select the PLL1 reference frequency range.
+ * @param __PLL1VCIRange__: specifies the PLL1 input frequency range
+ * This parameter can be one of the following values:
+ * @arg RCC_PLLVCIRANGE_0: Range frequency is between 4 and 8 MHz
+ * @arg RCC_PLLVCIRANGE_1: Range frequency is between 8 and 16 MHz
+ * @retval None
+ */
+#define __HAL_RCC_PLL_VCIRANGE(__PLL1VCIRange__) \
+ MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RGE, (__PLL1VCIRange__))
+
+/** @brief Macro to get the oscillator used as PLL1 clock source.
+ * @retval The oscillator used as PLL1 clock source. The returned value can be one
+ * of the following:
+ * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.
+ * - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source.
+ * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
+ * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
+ */
+#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC))
+
+/**
+ * @brief Macro to configure the system clock source.
+ * @param __SYSCLKSOURCE__: specifies the system clock source.
+ * This parameter can be one of the following values:
+ * - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source.
+ * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
+ * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
+ * - RCC_SYSCLKSOURCE_PLL1CLK: PLL1 output is used as system clock source.
+ * @retval None
+ */
+#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
+ MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SW, (__SYSCLKSOURCE__))
+
+/** @brief Macro to get the clock source used as system clock.
+ * @retval The clock source used as system clock. The returned value can be one
+ * of the following:
+ * - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock.
+ * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
+ * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
+ * - RCC_SYSCLKSOURCE_STATUS_PLL1CLK: PLL1 used as system clock.
+ */
+#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR1 & RCC_CFGR1_SWS))
+
+/**
+ * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability.
+ * @note As the LSE is in the Backup domain and write access is denied to
+ * this domain after reset, you have to enable write access using
+ * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
+ * (to be done once after reset).
+ * @note The LSE drive can be decreased to the lower drive capability (LSEDRV = 0)
+ * when the LSE is ON. However, once LSEDRV is selected, the drive
+ * capability can not be increased if LSEON = 1.
+ * @param __LSEDRIVE__: specifies the new state of the LSE drive capability.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability.
+ * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability.
+ * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability.
+ * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability.
+ * @retval None
+ */
+#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
+ MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__))
+
+/**
+ * @brief Macro to configure the wake up from stop clock.
+ * @note The selected clock is also used as emergency clock for the clock security system on HSE.
+ * @param __STOPWUCLK__: specifies the clock source used after wake up from stop.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source and CSS backup clock
+ * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source and CSS backup clock
+ * @retval None
+ */
+#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \
+ MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPWUCK, (__STOPWUCLK__))
+
+/**
+ * @brief Macro to configure the Kernel wake up from stop clock.
+ * @param __RCC_STOPKERWUCLK__: specifies the Kernel clock source used after wake up from stop
+ * This parameter can be one of the following values:
+ * @arg RCC_STOP_KERWAKEUPCLOCK_MSI: MSI selected as Kernel clock source
+ * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI selected as Kernel clock source
+ * @retval None
+ */
+#define __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__RCC_STOPKERWUCLK__) \
+ MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPKERWUCK, (__RCC_STOPKERWUCLK__))
+
+/** @brief Macro to configure the MCO clock.
+ * @param __MCOCLKSOURCE__ specifies the MCO clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled
+ * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source
+ * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source
+ * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
+ * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee
+ * @arg @ref RCC_MCO1SOURCE_PLL1CLK Main PLL clock selected as MCO source
+ * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
+ * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
+ * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48
+ * @param __MCODIV__ specifies the MCO clock prescaler.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1
+ * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2
+ * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4
+ * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8
+ * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16
+ */
+#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
+ MODIFY_REG(RCC->CFGR1, (RCC_CFGR1_MCOSEL | RCC_CFGR1_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
+
+/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
+ * @brief macros to manage the specified RCC Flags and interrupts.
+ * @{
+ */
+
+/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
+ * the selected interrupts).
+ * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
+ * @arg @ref RCC_IT_LSERDY LSE ready interrupt
+ * @arg @ref RCC_IT_MSIRDY HSI ready interrupt
+ * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
+ * @arg @ref RCC_IT_HSERDY HSE ready interrupt
+ * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
+ * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt
+ * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt
+ * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
+ * @retval None
+ */
+#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
+
+/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
+ * the selected interrupts).
+ * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
+ * This parameter can be any combination of the following values:
+ * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
+ * @arg @ref RCC_IT_LSERDY LSE ready interrupt
+ * @arg @ref RCC_IT_MSIRDY HSI ready interrupt
+ * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
+ * @arg @ref RCC_IT_HSERDY HSE ready interrupt
+ * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
+ * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt
+ * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt
+ * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
+ * @retval None
+ */
+#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
+
+/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
+ * bits to clear the selected interrupt pending bits.
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
+ * @arg @ref RCC_IT_LSERDY LSE ready interrupt
+ * @arg @ref RCC_IT_MSIRDY MSI ready interrupt
+ * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
+ * @arg @ref RCC_IT_HSERDY HSE ready interrupt
+ * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
+ * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt
+ * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt
+ * @arg @ref RCC_IT_CSS HSE Clock security system interrupt
+ * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
+ * @arg @ref RCC_IT_MSIKRDY MSIK ready interrupt
+ * @arg @ref RCC_IT_SHSIRDY SHSI ready interrupt
+ * @retval None
+ */
+#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__))
+
+/** @brief Check whether the RCC interrupt has occurred or not.
+ * @param __INTERRUPT__: specifies the RCC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
+ * @arg @ref RCC_IT_LSERDY LSE ready interrupt
+ * @arg @ref RCC_IT_MSIRDY MSI ready interrupt
+ * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
+ * @arg @ref RCC_IT_HSERDY HSE ready interrupt
+ * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
+ * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt
+ * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt
+ * @arg @ref RCC_IT_CSS HSE Clock security system interrupt
+ * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
+ * @arg @ref RCC_IT_MSIKRDY MSIK ready interrupt
+ * @arg @ref RCC_IT_SHSIRDY SHSI ready interrupt
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief Set RMVF bit to clear the reset flags.
+ * The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST,
+ * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
+ * @retval None
+ */
+#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
+
+/** @brief Check whether the selected RCC flag is set or not.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready
+ * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready
+ * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready
+ * @arg @ref RCC_FLAG_PLL1RDY Main PLL1 clock ready
+ * @arg @ref RCC_FLAG_PLL2RDY PLL2 clock ready
+ * @arg @ref RCC_FLAG_PLL3RDY PLL3 clock ready
+ * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready
+ * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready
+ * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection
+ * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready
+ * @arg @ref RCC_FLAG_BORRST BOR reset
+ * @arg @ref RCC_FLAG_OBLRST OBLRST reset
+ * @arg @ref RCC_FLAG_PINRST Pin reset
+ * @arg @ref RCC_FLAG_RMVF Remove reset Flag
+ * @arg @ref RCC_FLAG_SFTRST Software reset
+ * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset
+ * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset
+ * @arg @ref RCC_FLAG_LPWRRST Low Power reset
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_RCC_GET_FLAG(__FLAG__) ((((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \
+ ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
+ ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \
+ (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U)
+/**
+ * @}
+ */
+#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_MSI) || \
+ ((SOURCE) == RCC_PLLSOURCE_HSI) || \
+ ((SOURCE) == RCC_PLLSOURCE_NONE) || \
+ ((SOURCE) == RCC_PLLSOURCE_HSE))
+
+#define IS_RCC_PLLM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 16U))
+#define IS_RCC_PLLN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))
+#define IS_RCC_PLLP_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
+#define IS_RCC_PLLQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
+#define IS_RCC_PLLR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
+#define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) ||\
+ ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI))
+
+#define IS_RCC_STOP_KERWAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_MSI) || \
+ ((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_HSI))
+#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \
+ ((__RANGE__) == RCC_MSIRANGE_1) || \
+ ((__RANGE__) == RCC_MSIRANGE_2) || \
+ ((__RANGE__) == RCC_MSIRANGE_3) || \
+ ((__RANGE__) == RCC_MSIRANGE_4) || \
+ ((__RANGE__) == RCC_MSIRANGE_5) || \
+ ((__RANGE__) == RCC_MSIRANGE_6) || \
+ ((__RANGE__) == RCC_MSIRANGE_7) || \
+ ((__RANGE__) == RCC_MSIRANGE_8) || \
+ ((__RANGE__) == RCC_MSIRANGE_9) || \
+ ((__RANGE__) == RCC_MSIRANGE_10) || \
+ ((__RANGE__) == RCC_MSIRANGE_11) || \
+ ((__RANGE__) == RCC_MSIRANGE_12) || \
+ ((__RANGE__) == RCC_MSIRANGE_13) || \
+ ((__RANGE__) == RCC_MSIRANGE_14) || \
+ ((__RANGE__) == RCC_MSIRANGE_15))
+
+#define IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_4) || \
+ ((__RANGE__) == RCC_MSIRANGE_5) || \
+ ((__RANGE__) == RCC_MSIRANGE_6) || \
+ ((__RANGE__) == RCC_MSIRANGE_7) || \
+ ((__RANGE__) == RCC_MSIRANGE_8))
+
+#define IS_RCC_MSIK_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIKRANGE_0) || \
+ ((__RANGE__) == RCC_MSIKRANGE_1) || \
+ ((__RANGE__) == RCC_MSIKRANGE_2) || \
+ ((__RANGE__) == RCC_MSIKRANGE_3) || \
+ ((__RANGE__) == RCC_MSIKRANGE_4) || \
+ ((__RANGE__) == RCC_MSIKRANGE_5) || \
+ ((__RANGE__) == RCC_MSIKRANGE_6) || \
+ ((__RANGE__) == RCC_MSIKRANGE_7) || \
+ ((__RANGE__) == RCC_MSIKRANGE_8) || \
+ ((__RANGE__) == RCC_MSIKRANGE_9) || \
+ ((__RANGE__) == RCC_MSIKRANGE_10) || \
+ ((__RANGE__) == RCC_MSIKRANGE_11) || \
+ ((__RANGE__) == RCC_MSIKRANGE_12) || \
+ ((__RANGE__) == RCC_MSIKRANGE_13) || \
+ ((__RANGE__) == RCC_MSIKRANGE_14) || \
+ ((__RANGE__) == RCC_MSIKRANGE_15))
+/**
+ * @}
+ */
+
+/* Include RCC HAL Extended module */
+#include "stm32u5xx_hal_rcc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RCC_Exported_Functions_Group1
+ * @{
+ */
+
+/* Initialization and de-initialization functions ******************************/
+HAL_StatusTypeDef HAL_RCC_DeInit(void);
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct);
+HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *const pRCC_ClkInitStruct, uint32_t FLatency);
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Exported_Functions_Group2
+ * @{
+ */
+
+/* Peripheral Control functions **********************************************/
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
+void HAL_RCC_EnableCSS(void);
+uint32_t HAL_RCC_GetSysClockFreq(void);
+uint32_t HAL_RCC_GetHCLKFreq(void);
+uint32_t HAL_RCC_GetPCLK1Freq(void);
+uint32_t HAL_RCC_GetPCLK2Freq(void);
+uint32_t HAL_RCC_GetPCLK3Freq(void);
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct);
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *pRCC_ClkInitStruct, uint32_t *pFLatency);
+uint32_t HAL_RCC_GetResetSource(void);
+/* CSS NMI IRQ handler */
+void HAL_RCC_NMI_IRQHandler(void);
+/* User Callbacks in non blocking mode (IT mode) */
+void HAL_RCC_CSSCallback(void);
+
+/**
+ * @}
+ */
+
+/* Attributes management functions ********************************************/
+void HAL_RCC_ConfigAttributes(uint32_t Item, uint32_t Attributes);
+HAL_StatusTypeDef HAL_RCC_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_RCC_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rcc_ex.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rcc_ex.h
new file mode 100644
index 00000000..e32ee69f
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rcc_ex.h
@@ -0,0 +1,2005 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_rcc_ex.h
+ * @author MCD Application Team
+ * @brief Header file of RCC HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_RCC_EX_H
+#define STM32U5xx_HAL_RCC_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup RCCEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
+ * @{
+ */
+
+/**
+ * @brief PLL2 Clock structure definition
+ */
+typedef struct
+{
+ uint32_t PLL2Source; /*!< RCC_PLL2Source: PLL2 entry clock source.
+ This parameter must be a value of @ref RCC_PLL_Clock_Source */
+
+ uint32_t PLL2M; /*!< PLL2M: Division factor for PLL2 VCO input clock.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 63 */
+
+ uint32_t PLL2N; /*!< PLL2N: Multiplication factor for PLL2 VCO output clock.
+ This parameter must be a number between Min_Data = 4 and Max_Data = 512 */
+
+ uint32_t PLL2P; /*!< PLL2P: Division factor for system clock.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 128 */
+
+ uint32_t PLL2Q; /*!< PLL2Q: Division factor for peripheral clocks.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
+
+ uint32_t PLL2R; /*!< PLL2R: Division factor for peripheral clocks.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 128
+ odd division factors are not allowed */
+
+ uint32_t PLL2RGE; /*!= RCC_MSIRANGE_12) \
+ {\
+ MODIFY_REG((RCC->ICSCR2), (RCC_ICSCR2_MSITRIM3), ((uint32_t)(__MSICALIBRATIONVALUE__)<<\
+ RCC_ICSCR2_MSITRIM3_Pos));\
+ }\
+ else if(__MSIRANGE__ >= RCC_MSIRANGE_8)\
+ {\
+ MODIFY_REG((RCC->ICSCR2), (RCC_ICSCR2_MSITRIM2), ((uint32_t)(__MSICALIBRATIONVALUE__)<<\
+ RCC_ICSCR2_MSITRIM2_Pos));\
+ }\
+ else if(__MSIRANGE__ >= RCC_MSIRANGE_4)\
+ {\
+ MODIFY_REG((RCC->ICSCR2), (RCC_ICSCR2_MSITRIM1), ((uint32_t)(__MSICALIBRATIONVALUE__)<<\
+ RCC_ICSCR2_MSITRIM1_Pos));\
+ } \
+ else /* if(__MSIRANGE__ >= RCC_MSIRANGE_0) */\
+ { \
+ MODIFY_REG((RCC->ICSCR2), (RCC_ICSCR2_MSITRIM0), ((uint32_t)(__MSICALIBRATIONVALUE__)<<\
+ RCC_ICSCR2_MSITRIM0_Pos));\
+ } \
+ } while(0)
+
+/** @brief Macro to configure timer input capture clock source.
+ * @param __TIMICSOURCE__ : specifies the TIMIC clock source
+ * This parameter can be one or a combination of the following values:
+ * @arg RCC_TIMIC_HSI_256: HSI/256 selected for Timer16/17 and LPTimer2
+ * @arg RCC_TIMIC_MSI_1024: MSIS/1024 selected for Timer16/17 and LPTimer2
+ * @arg RCC_TIMIC_MSI_4: MSIS/4 selected for Timer16/17 and LPTimer2
+ * @arg RCC_TIMIC_MSIK_1024: MSIK/1024 selected for Timer16/17 and LPTimer2
+ * @arg RCC_TIMIC_MSIK_4 : MSIK/4 selected for Timer16/17 and LPTimer2
+ * @note combination to be avoid :
+ * RCC_TIMIC_MSI_1024 and RCC_TIMIC_MSIK_1024
+ * RCC_TIMIC_MSI_4 and RCC_TIMIC_MSIK_4
+ * @retval None
+ */
+#define __HAL_RCC_TIMIC_CLK_CONFIG(__TIMICSOURCE__) \
+ do \
+ { \
+ /*Disable All TIMIC SOURCE*/ \
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL,(0x00000000)); \
+ /*Select TIMIC clock SOURCE*/ \
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL,(uint32_t)(__TIMICSOURCE__));\
+ } while(0)
+
+/** @brief Macro to disable timer input capture clock source.
+ * @retval None
+ */
+#define __HAL_RCC_TIMIC_CLK_DISABLE() MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL,(0x00000000))
+
+/** @brief Macros to enable or disable the PLL2.
+ * @note After enabling PLL2, the application software should wait on
+ * PLL2RDY flag to be set indicating that PLL2 clock is stable and can
+ * be used as kernel clock source.
+ * @note The PLL2 is disabled by hardware when entering STOP and STANDBY modes.
+ * @retval None
+ */
+#define __HAL_RCC_PLL2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL2ON)
+#define __HAL_RCC_PLL2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON)
+
+/** @brief Macro to configure the PLL2 clock source.
+ * @note This function must be used only when all PLL2 is disabled.
+ * @param __PLL2SOURCE__: specifies the PLL2 entry clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_PLLSOURCE_MSI: MSI oscillator clock selected as PLL2 clock entry
+ * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL2 clock entry
+ * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL2 clock entry
+ */
+#define __HAL_RCC_PLL2_PLLSOURCE_CONFIG(__PLL2SOURCE__) MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC,\
+ (__PLL2SOURCE__))
+
+/** @brief Macro to get the oscillator used as PLL2 clock source.
+ * @retval The oscillator used as PLL2 clock source. The returned value can be one
+ * of the following:
+ * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.
+ * - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source.
+ * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
+ * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
+ */
+#define __HAL_RCC_GET_PLL2_OSCSOURCE() ((uint32_t)(RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC))
+
+/** @brief Macro to configures the PLL2 source, multiplication and division factors.
+ * @note This function must be used only when PLL2 is disabled.
+ * @param __PLL2SOURCE__: specifies the PLL2 entry clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL2 clock entry
+ * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL2 clock entry
+ * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL2 clock entry
+ * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL2 clock entry
+ * @param __PLL2M__ specifies the division factor of PLL2 input clock.
+ * This parameter must be a number between Min_Data = 1 and Max_Data = 16
+ * @param __PLL2N__: specifies the multiplication factor for PLL2 VCO output clock
+ * This parameter must be a number between 4 and 512.
+ * @note You have to set the PLL2N parameter correctly to ensure that the VCO
+ * output frequency is between 64 and 344 MHz.
+ * PLL2 clock frequency = f(PLL2) multiplied by PLL2N
+ * @param __PLL2P__: specifies the division factor for peripheral kernel clocks
+ * This parameter must be a number between 1 and 128
+ * @param __PLL2Q__: specifies the division factor for peripheral kernel clocks
+ * This parameter must be a number between 1 and 128
+ * @param __PLL2R__: specifies the division factor for peripheral kernel clocks
+ * This parameter must be a number between 1 and 128
+ * @retval None
+ */
+#define __HAL_RCC_PLL2_CONFIG(__PLL2SOURCE__, __PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__, __PLL2R__) \
+ do \
+ { \
+ MODIFY_REG(RCC->PLL2CFGR,(RCC_PLL2CFGR_PLL2SRC|RCC_PLL2CFGR_PLL2M), ((__PLL2SOURCE__)<< RCC_PLL2CFGR_PLL2SRC_Pos) |\
+ (((__PLL2M__) - 1U) << RCC_PLL2CFGR_PLL2M_Pos));\
+ MODIFY_REG(RCC->PLL2DIVR ,(RCC_PLL2DIVR_PLL2N|RCC_PLL2DIVR_PLL2P|RCC_PLL2DIVR_PLL2Q|\
+ RCC_PLL2DIVR_PLL2R), ((((__PLL2N__) - 1U) & RCC_PLL2DIVR_PLL2N) | ((((__PLL2P__) -1U)<< \
+ RCC_PLL2DIVR_PLL2P_Pos) & RCC_PLL2DIVR_PLL2P) |\
+ ((((__PLL2Q__) -1U) << RCC_PLL2DIVR_PLL2Q_Pos)& \
+ RCC_PLL2DIVR_PLL2Q) | ((((__PLL2R__)- 1U) << \
+ RCC_PLL2DIVR_PLL2R_Pos) & \
+ RCC_PLL2DIVR_PLL2R))); \
+ } while(0)
+
+/**
+ * @brief Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK)
+ * @note Enabling/disabling Those Clocks can be any time without the need to stop the PLL2,
+ * This is mainly used to save Power.
+ * @param __PLL2_CLOCKOUT__ specifies the PLL2 clock outputted.
+ * This parameter can be one or a combination of the following values:
+ * @arg RCC_PLL2_DIVP: This clock is used to generate an accurate clock to achieve
+ * high-quality audio performance on SAI interface.
+ * @arg RCC_PLL2_DIVQ: This clock is used to generate the clock for the USB FS (48 MHz),
+ * the random number generator (<=48 MHz).
+ * @arg RCC_PLL2_DIVR: Clock used to clock ADC peripheral.
+ * @retval None
+ */
+#define __HAL_RCC_PLL2CLKOUT_ENABLE(__PLL2_CLOCKOUT__) SET_BIT(RCC->PLL2CFGR, (__PLL2_CLOCKOUT__))
+#define __HAL_RCC_PLL2CLKOUT_DISABLE(__PLL2_CLOCKOUT__) CLEAR_BIT(RCC->PLL2CFGR, (__PLL2_CLOCKOUT__))
+
+/**
+ * @brief Macro to get the PLL2 clock output enable status.
+ * @param __PLL2_CLOCKOUT__ specifies the PLL2 clock to be outputted.
+ * This parameter can be one of the following values:
+ * This parameter can be one or a combination of the following values:
+ * @arg RCC_PLL2_DIVP: This clock is used to generate an accurate clock to achieve
+ * high-quality audio performance on SAI interface.
+ * @arg RCC_PLL2_DIVQ: This clock is used to generate the clock for the USB FS (48 MHz),
+ * the random number generator (<=48 MHz).
+ * @arg RCC_PLL2_DIVR: Clock used to clock ADC peripheral.
+ * @retval SET / RESET
+ */
+#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG(__PLL2_CLOCKOUT__) READ_BIT(RCC->PLL2CFGR, (__PLL2_CLOCKOUT__))
+
+/**
+ * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO
+ * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL2
+ * @retval None
+ */
+#define __HAL_RCC_PLL2FRACN_ENABLE() SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN)
+#define __HAL_RCC_PLL2FRACN_DISABLE() CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN)
+
+/**
+ * @brief Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor
+ * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO
+ * @param __PLL2FRACN__: Specifies Fractional Part Of The Multiplication factor for PLL2 VCO
+ * It should be a value between 0 and 8191
+ * @note Warning: the software has to set correctly these bits to insure that the VCO
+ * output frequency is between its valid frequency range, which is:
+ * 192 to 836 MHz if PLL2VCOSEL = 0
+ * 150 to 420 MHz if PLL2VCOSEL = 1
+ * @retval None
+ */
+#define __HAL_RCC_PLL2FRACN_CONFIG(__PLL2FRACN__) MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_PLL2FRACN,\
+ (uint32_t)(__PLL2FRACN__) << RCC_PLL2FRACR_PLL2FRACN_Pos)
+
+/** @brief Macro to select the PLL2 reference frequency range.
+ * @param __PLL2VCIRange__: specifies the PLL2 input frequency range
+ * This parameter can be one of the following values:
+ * @arg RCC_PLLVCIRANGE_0: Range frequency is between 4 and 8 MHz
+ * @arg RCC_PLLVCIRANGE_1: Range frequency is between 8 and 16 MHz
+ * @retval None
+ */
+#define __HAL_RCC_PLL2_VCIRANGE(__PLL2VCIRange__) \
+ MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2RGE, (__PLL2VCIRange__))
+
+/** @brief Macros to enable or disable the main PLL3.
+ * @note After enabling PLL3, the application software should wait on
+ * PLL3RDY flag to be set indicating that PLL3 clock is stable and can
+ * be used as kernel clock source.
+ * @note PLL3 is disabled by hardware when entering STOP and STANDBY modes.
+ */
+#define __HAL_RCC_PLL3_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL3ON)
+#define __HAL_RCC_PLL3_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON)
+
+/** @brief Macro to configure the PLL3 clock source.
+ * @note This function must be used only when all PLL3 is disabled.
+ * @param __PLL3SOURCE__: specifies the PLL3 entry clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_PLLSOURCE_MSI: MSI oscillator clock selected as PLL3 clock entry
+ * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL3 clock entry
+ * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL3 clock entry
+ *
+ */
+#define __HAL_RCC_PLL3_PLLSOURCE_CONFIG(__PLL3SOURCE__) MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3SRC, \
+ (__PLL3SOURCE__))
+
+/** @brief Macro to get the oscillator used as PLL3 clock source.
+ * @retval The oscillator used as PLL3 clock source. The returned value can be one
+ * of the following:
+ * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.
+ * - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source.
+ * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
+ * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
+ */
+#define __HAL_RCC_GET_PLL3_OSCSOURCE() ((uint32_t)(RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3SRC))
+
+/** @brief Macro to configures the PLL3 source, multiplication and division factors.
+ * @note This function must be used only when PLL3 is disabled.
+ *
+ * @param __PLL3SOURCE__: specifies the PLL3 entry clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL3 clock entry
+ * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL3 clock entry
+ * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL3 clock entry
+ * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL3 clock entry
+ * @param __PLL3M__ specifies the division factor of PLL3 input clock.
+ * This parameter must be a number between Min_Data = 1 and Max_Data = 16
+ * @param __PLL3N__: specifies the multiplication factor for PLL3 VCO output clock
+ * This parameter must be a number between 4 and 512.
+ * @note You have to set the PLL3N parameter correctly to ensure that the VCO
+ * output frequency is between 64 and 344 MHz.
+ * PLL3 clock frequency = f(PLL3) multiplied by PLL3N
+ * @param __PLL3P__: specifies the division factor for peripheral kernel clocks
+ * This parameter must be a number between 1 and 128
+ * @param __PLL3Q__: specifies the division factor for peripheral kernel clocks
+ * This parameter must be a number between 1 and 128
+ * @param __PLL3R__: specifies the division factor for peripheral kernel clocks
+ * This parameter must be a number between 1 and 128
+ * @retval None
+ */
+#define __HAL_RCC_PLL3_CONFIG(__PLL3SOURCE__, __PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__, __PLL3R__) \
+ do\
+ {\
+ MODIFY_REG(RCC->PLL3CFGR,(RCC_PLL3CFGR_PLL3SRC|RCC_PLL3CFGR_PLL3M), ((__PLL3SOURCE__) << RCC_PLL3CFGR_PLL3SRC_Pos)|\
+ (((__PLL3M__) - 1U) << RCC_PLL3CFGR_PLL3M_Pos));\
+ MODIFY_REG(RCC->PLL3DIVR ,(RCC_PLL3DIVR_PLL3N|RCC_PLL3DIVR_PLL3P|RCC_PLL3DIVR_PLL3Q|RCC_PLL3DIVR_PLL3R),\
+ ((((__PLL3N__) - 1U) & RCC_PLL3DIVR_PLL3N) | ((((__PLL3P__) -1U) << RCC_PLL3DIVR_PLL3P_Pos) &\
+ RCC_PLL3DIVR_PLL3P) | ((((__PLL3Q__) -1U) << \
+ RCC_PLL3DIVR_PLL3Q_Pos) & \
+ RCC_PLL3DIVR_PLL3Q) | \
+ ((((__PLL3R__)- 1U) << RCC_PLL3DIVR_PLL3R_Pos) & RCC_PLL3DIVR_PLL3R))); \
+ } while(0)
+
+/**
+ * @brief Macro to configures PLL3 clock Fractional Part of The Multiplication Factor
+ * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO
+ * @param __PLL3FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL3 VCO
+ * It should be a value between 0 and 8191
+ * @note Warning: the software has to set correctly these bits to insure that the VCO
+ * output frequency is between its valid frequency range, which is:
+ * 192 to 836 MHz if PLL3VCOSEL = 0
+ * 150 to 420 MHz if PLL3VCOSEL = 1
+ * @retval None
+ */
+#define __HAL_RCC_PLL3FRACN_CONFIG(__PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_PLL3FRACN, \
+ (uint32_t)(__PLL3FRACN__) << RCC_PLL3FRACR_PLL3FRACN_Pos)
+
+/** @brief Macro to select the PLL3 reference frequency range.
+ * @param __PLL3VCIRange__: specifies the PLL1 input frequency range
+ * This parameter can be one of the following values:
+ * @arg RCC_PLLVCIRANGE_0: Range frequency is between 4 and 8 MHz
+ * @arg RCC_PLLVCIRANGE_1: Range frequency is between 8 and 16 MHz
+ * @retval None
+ */
+#define __HAL_RCC_PLL3_VCIRANGE(__PLL3VCIRange__) \
+ MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3RGE, (__PLL3VCIRange__))
+
+/**
+ * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO
+ * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL3
+ * @retval None
+ */
+#define __HAL_RCC_PLL3FRACN_ENABLE() SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN)
+#define __HAL_RCC_PLL3FRACN_DISABLE() CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN)
+
+/**
+ * @brief Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK)
+ * @note Enabling/disabling Those Clocks can be any time without the need to stop the PLL3,
+ * This is mainly used to save Power.
+ * @param __PLL3_CLOCKOUT__: specifies the PLL3 clock to be outputted
+ * This parameter can be one of the following values:
+ * @arg RCC_PLL3_DIVP: This clock is used to generate an accurate clock to achieve
+ * high-quality audio performance on SAI interface.
+ * @retval None
+ */
+#define __HAL_RCC_PLL3CLKOUT_ENABLE(__PLL3_CLOCKOUT__) SET_BIT(RCC->PLL3CFGR, (__PLL3_CLOCKOUT__))
+#define __HAL_RCC_PLL3CLKOUT_DISABLE(__PLL3_CLOCKOUT__) CLEAR_BIT(RCC->PLL3CFGR, (__PLL3_CLOCKOUT__))
+
+/**
+ * @brief Macro to get clock output enable status (PLL3_SAI2).
+ * @param __PLL3_CLOCKOUT__ specifies the PLL3 clock to be outputted.
+ * This parameter can be one of the following values:
+ * @arg RCC_PLL3_DIVP: This clock is used to generate an accurate clock to achieve
+ * high-quality audio performance on SAI interface.
+ * @retval SET / RESET
+ */
+#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG(__PLL3_CLOCKOUT__) READ_BIT(RCC->PLL3CFGR, (__PLL3_CLOCKOUT__))
+
+/** @brief Macro to configure the ADC1, ADC4 and DAC interface clock.
+ * @param __ADCDAC_CLKSOURCE__ specifies the ADC1, ADC4 and DAC digital interface clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_ADCDACCLKSOURCE_HCLK clock selected as ADC1, ADC4 and DAC clock
+ * @arg @ref RCC_ADCDACCLKSOURCE_SYSCLK clock selected as ADC1, ADC4 and DAC clock
+ * @arg @ref RCC_ADCDACCLKSOURCE_PLL2 clock selected as ADC1, ADC4 and DAC clock
+ * @arg @ref RCC_ADCDACCLKSOURCE_HSE clock selected as ADC1, ADC4 and DAC clock
+ * @arg @ref RCC_ADCDACCLKSOURCE_HSI clock selected as ADC1, ADC4 and DAC clock
+ * @arg @ref RCC_ADCDACCLKSOURCE_MSIK clock selected as ADC1, ADC4 and DAC clock
+ * @retval None
+ */
+#define __HAL_RCC_ADCDAC_CONFIG(__ADCDAC_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_ADCDACSEL, (uint32_t)(__ADCDAC_CLKSOURCE__))
+
+/** @brief Macro to get the ADCDAC clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_ADCDACCLKSOURCE_HCLK clock used as ADC1, ADC4 and DAC clock
+ * @arg @ref RCC_ADCDACCLKSOURCE_SYSCLK clock used as ADC1, ADC4 and DAC clock
+ * @arg @ref RCC_ADCDACCLKSOURCE_PLL2 clock used as ADC1, ADC4 and DAC clock
+ * @arg @ref RCC_ADCDACCLKSOURCE_HSE clock used as ADC1, ADC4 and DAC clock
+ * @arg @ref RCC_ADCDACCLKSOURCE_HSI clock used as ADC1, ADC4 and DAC clock
+ * @arg @ref RCC_ADCDACCLKSOURCE_MSIK clock used as ADC1, ADC4 and DAC clock
+ */
+#define __HAL_RCC_GET_ADCDAC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_ADCDACSEL)))
+
+/** @brief Macro to configure the CLK48 source (CLK48CLK).
+ * @param __CLK48_SOURCE__: specifies the CLK48 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_CLK48CLKSOURCE_HSI48: HSI48 selected as CLK48 source
+ * @arg RCC_CLK48CLKSOURCE_PLL2 : PLL2 selected as CLK48 source
+ * @arg RCC_CLK48CLKSOURCE_PLL1 : PLL1 selected as CLK48 source
+ * @arg RCC_CLK48CLKSOURCE_MSIK : MSIK selected as CLK48 source
+ */
+#define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL, (uint32_t)(__CLK48_SOURCE__))
+
+/** @brief macro to get the CLK48 source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_CLK48CLKSOURCE_HSI48: HSI48 used as CLK48 source
+ * @arg RCC_CLK48CLKSOURCE_PLL2 : PLL2 used as CLK48 source
+ * @arg RCC_CLK48CLKSOURCE_PLL1 : PLL1 used as CLK48 source
+ * @arg RCC_CLK48CLKSOURCE_MSIK : MSIK used as CLK48 source
+ */
+#define __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL)))
+
+/** @brief Macro to configure the FDCAN1 kernel clock (FDCAN1CLK).
+ * @param __FDCAN1_CLKSOURCE__ specifies the FDCAN1 kernel clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_FDCAN1CLKSOURCE_HSE HSE selected as FDCAN1 kernel clock
+ * @arg @ref RCC_FDCAN1CLKSOURCE_PLL1 PLL1 Clock selected as FDCAN1 kernel clock
+ * @arg @ref RCC_FDCAN1CLKSOURCE_PLL2 PLL2 Clock selected as FDCAN1 kernel clock
+ * @retval None
+ */
+#define __HAL_RCC_FDCAN1_CONFIG(__FDCAN1_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_FDCANSEL, (uint32_t)(__FDCAN1_CLKSOURCE__))
+
+/** @brief Macro to get the FDCAN1 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_FDCAN1CLKSOURCE_HSE HSE selected as FDCAN1 kernel clock
+ * @arg @ref RCC_FDCAN1CLKSOURCE_PLL1 PLL1 Clock selected as FDCAN1 kernel clock
+ * @arg @ref RCC_FDCAN1CLKSOURCE_PLL2 PLL2 Clock selected as FDCAN1 kernel clock
+ */
+#define __HAL_RCC_GET_FDCAN1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_FDCANSEL)))
+
+/** @brief Macro to configure the LPTIM34 clock (LPTIM34CLK).
+ * @param __LPTIM34_CLKSOURCE__ specifies the LPTIM34 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_LPTIM34CLKSOURCE_MSIK MSIK selected as LPTIM34 clock
+ * @arg @ref RCC_LPTIM34CLKSOURCE_LSI LSI selected as LPTIM34 clock
+ * @arg @ref RCC_LPTIM34CLKSOURCE_HSI HSI selected as LPTIM34 clock
+ * @arg @ref RCC_LPTIM34CLKSOURCE_LSE LSE selected as LPTIM34 clock
+ * @retval None
+ */
+#define __HAL_RCC_LPTIM34_CONFIG(__LPTIM34_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_LPTIM34SEL, (uint32_t)(__LPTIM34_CLKSOURCE__))
+
+/** @brief Macro to get the LPTIM34 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_LPTIM34CLKSOURCE_MSIK MSIK selected as LPTIM34 clock
+ * @arg @ref RCC_LPTIM34CLKSOURCE_LSI LSI selected as LPTIM34 clock
+ * @arg @ref RCC_LPTIM34CLKSOURCE_HSI HSI selected as LPTIM34 clock
+ * @arg @ref RCC_LPTIM34CLKSOURCE_LSE LSE selected as LPTIM34 clock
+ */
+#define __HAL_RCC_GET_LPTIM34_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_LPTIM34SEL)))
+
+/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK).
+ * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_LPTIM1CLKSOURCE_MSIK MSIK selected as LPTIM1 clock
+ * @arg @ref RCC_LPTIM1CLKSOURCE_LSI LSI selected as LPTIM1 clock
+ * @arg @ref RCC_LPTIM1CLKSOURCE_HSI HSI selected as LPTIM1 clock
+ * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock
+ * @retval None
+ */
+#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
+
+/** @brief Macro to get the LPTIM1 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_LPTIM1CLKSOURCE_MSIK MSIK selected as LPTIM1 clock
+ * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock
+ * @arg @ref RCC_LPTIM1CLKSOURCE_HSI HSI selected as LPTIM1 clock
+ * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock
+ */
+#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_LPTIM1SEL)))
+
+/** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK).
+ * @param __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock
+ * @arg @ref RCC_LPTIM2CLKSOURCE_LSI LSI selected as LPTIM2 clock
+ * @arg @ref RCC_LPTIM2CLKSOURCE_HSI HSI selected as LPTIM2 clock
+ * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock
+ * @retval None
+ */
+#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__))
+
+/** @brief Macro to get the LPTIM2 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock
+ * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock
+ * @arg @ref RCC_LPTIM2CLKSOURCE_HSI HSI selected as LPTIM2 clock
+ * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock
+ */
+#define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_LPTIM2SEL)))
+
+/** @brief macro to configure the SPI1 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_SPI1CLKSOURCE_PCLK2 : PCLK2 Clock selected as SPI1 clock
+ * @arg RCC_SPI1CLKSOURCE_SYSCLK : SYSCLK Clock selected as SPI1 clock
+ * @arg RCC_SPI1CLKSOURCE_HSI : HSI Clock selected as SPI1 clock
+ * @arg RCC_SPI1CLKSOURCE_MSIK : MSIK Clock selected as SPI1 clock
+ */
+
+#define __HAL_RCC_SPI1_CONFIG(__SPI1CLKSource__) \
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SPI1SEL, (uint32_t)(__SPI1CLKSource__))
+
+/** @brief macro to get the SPI1 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_SPI1CLKSOURCE_PCLK2 : PCLK2 Clock used as SPI1 clock
+ * @arg RCC_SPI1CLKSOURCE_SYSCLK : SYSCLK Clock used as SPI1 clock
+ * @arg RCC_SPI1CLKSOURCE_HSI : HSI Clock used as SPI1 clock
+ * @arg RCC_SPI1CLKSOURCE_MSIK : MSIK Clock used as SPI1 clock
+ */
+#define __HAL_RCC_GET_SPI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_SPI1SEL)))
+
+/** @brief macro to configure the SPI2 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_SPI2CLKSOURCE_PCLK3 : PCLK3 selected as SPI2 clock
+ * @arg RCC_SPI2CLKSOURCE_SYSCLK : SYSCLK Clock selected as SPI2 clock
+ * @arg RCC_SPI2CLKSOURCE_HSI : HSI Clock selected as SPI2 clock
+ * @arg RCC_SPI2CLKSOURCE_MSIK : MSIK Clock selected as SPI2 clock
+ */
+
+#define __HAL_RCC_SPI2_CONFIG(__SPI2CLKSource__) \
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SPI2SEL, (uint32_t)(__SPI2CLKSource__))
+
+/** @brief macro to get the SPI2 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_SPI2CLKSOURCE_PCLK1 : PCLK1 Clock used as SPI2 clock
+ * @arg RCC_SPI2CLKSOURCE_SYSCLK : SYSCLK Clock used as SPI2 clock
+ * @arg RCC_SPI2CLKSOURCE_HSI : HSI Clock used as SPI2 clock
+ * @arg RCC_SPI2CLKSOURCE_MSIK : MSIK Clock used as SPI2 clock
+ */
+#define __HAL_RCC_GET_SPI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_SPI2SEL)))
+
+/** @brief macro to configure the SPI3 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_SPI3CLKSOURCE_PCLK3 : PCLK3 selected as SPI3 clock
+ * @arg RCC_SPI3CLKSOURCE_SYSCLK : SYSCLK Clock selected as SPI3 clock
+ * @arg RCC_SPI3CLKSOURCE_HSI : HSI Clock selected as SPI3 clock
+ * @arg RCC_SPI3CLKSOURCE_MSIK : MSIK Clock selected as SPI3 clock
+ */
+#define __HAL_RCC_SPI3_CONFIG(__SPI3CLKSource__) \
+ MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_SPI3SEL, (uint32_t)(__SPI3CLKSource__))
+
+/** @brief macro to get the SPI3 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_SPI3CLKSOURCE_PCLK3 : PCLK3 used as SPI3 clock
+ * @arg RCC_SPI3CLKSOURCE_SYSCLK : SYSCLK Clock used as SPI3 clock
+ * @arg RCC_SPI3CLKSOURCE_HSI : HSI Clock used as SPI3 clock
+ * @arg RCC_SPI3CLKSOURCE_MSIK : MSIK Clock used as SPI3 clock
+ */
+#define __HAL_RCC_GET_SPI3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_SPI3SEL)))
+
+
+/** @brief Macro to configure the I2C1 clock (I2C1CLK).
+ * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
+ * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
+ * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
+ * @arg @ref RCC_I2C1CLKSOURCE_MSIK MSIK selected as I2C1 clock
+ * @retval None
+ */
+#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
+
+/** @brief Macro to get the I2C1 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
+ * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
+ * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
+ * @arg @ref RCC_I2C1CLKSOURCE_MSIK MSIK selected as I2C1 clock
+ */
+#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_I2C1SEL)))
+
+/** @brief Macro to configure the I2C2 clock (I2C2CLK).
+ * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock
+ * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
+ * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
+ * @arg @ref RCC_I2C2CLKSOURCE_MSIK MSIK selected as I2C2 clock
+ * @retval None
+ */
+#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))
+
+/** @brief Macro to get the I2C2 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock
+ * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
+ * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
+ * @arg @ref RCC_I2C2CLKSOURCE_MSIK MSIK selected as I2C2 clock
+ */
+#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_I2C2SEL)))
+
+/** @brief Macro to configure the I2C3 clock (I2C3CLK).
+ * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_I2C3CLKSOURCE_PCLK3 : PCLK3 selected as I2C3 clock
+ * @arg @ref RCC_I2C3CLKSOURCE_HSI : HSI selected as I2C3 clock
+ * @arg @ref RCC_I2C3CLKSOURCE_MSIK : MSIK selected as I2C3 clock
+ * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK : System Clock selected as I2C3 clock
+ * @retval None
+ */
+#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
+
+/** @brief Macro to get the I2C3 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_I2C3CLKSOURCE_PCLK3 : PCLK3 used as I2C3 clock
+ * @arg @ref RCC_I2C3CLKSOURCE_HSI : HSI used as I2C3 clock
+ * @arg @ref RCC_I2C3CLKSOURCE_MSIK : MSIK used as I2C3 clock
+ * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK : System Clock used as I2C3 clock
+ */
+#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_I2C3SEL)))
+
+/** @brief Macro to configure the I2C4 clock (I2C4CLK).
+ * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock
+ * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock
+ * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock
+ * @arg @ref RCC_I2C4CLKSOURCE_MSIK MSIK selected as I2C4 clock
+ * @retval None
+ */
+#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__))
+
+/** @brief Macro to get the I2C4 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock
+ * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock
+ * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock
+ * @arg @ref RCC_I2C4CLKSOURCE_MSIK MSIK selected as I2C4 clock
+ */
+#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_I2C4SEL)))
+
+/** @brief Macro to configure the USART1 clock (USART1CLK).
+ * @param __USART1_CLKSOURCE__ specifies the USART1 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK1 selected as USART1 clock
+ * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
+ * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
+ * @arg @ref RCC_USART1CLKSOURCE_LSE SE selected as USART1 clock
+ * @retval None
+ */
+#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
+
+/** @brief Macro to get the USART1 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK1 selected as USART1 clock
+ * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
+ * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
+ * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
+ */
+#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART1SEL)))
+
+/** @brief Macro to configure the USART2 clock (USART2CLK).
+ * @param __USART2_CLKSOURCE__ specifies the USART2 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
+ * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
+ * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
+ * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
+ * @retval None
+ */
+#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
+
+/** @brief Macro to get the USART2 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
+ * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
+ * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
+ * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
+ */
+#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART2SEL)))
+
+/** @brief Macro to configure the USART3 clock (USART3CLK).
+ *
+ * @param __USART3_CLKSOURCE__ specifies the USART3 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
+ * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
+ * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
+ * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
+ * @retval None
+ */
+#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))
+
+/** @brief Macro to get the USART3 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
+ * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
+ * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
+ * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
+ */
+#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART3SEL)))
+
+/** @brief Macro to configure the UART4 clock (UART4CLK).
+ *
+ * @param __UART4_CLKSOURCE__ specifies the UART4 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
+ * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
+ * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
+ * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
+ * @retval None
+ */
+#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))
+
+/** @brief Macro to get the UART4 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
+ * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
+ * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
+ * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
+ */
+#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART4SEL)))
+
+/** @brief Macro to configure the UART5 clock (UART5CLK).
+ * @param __UART5_CLKSOURCE__ specifies the UART5 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
+ * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
+ * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock
+ * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
+ * @retval None
+ */
+#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))
+
+/** @brief Macro to get the UART5 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
+ * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
+ * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock
+ * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
+ */
+#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART5SEL)))
+
+/** @brief Macro to configure the LPUART1 clock (LPUART1CLK).
+ *
+ * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_LPUART1CLKSOURCE_PCLK3 PCLK3 selected as LPUART1 clock
+ * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
+ * @arg @ref RCC_LPUART1CLKSOURCE_MSIK MSIK selected as LPUART1 clock
+ * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
+ * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
+ * @retval None
+ */
+#define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__))
+
+/** @brief Macro to get the LPUART1 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_LPUART1CLKSOURCE_PCLK3 PCLK3 selected as LPUART1 clock
+ * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
+ * @arg @ref RCC_LPUART1CLKSOURCE_MSIK MSIK selected as LPUART1 clock
+ * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
+ * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
+ */
+#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_LPUART1SEL)))
+
+
+/** @brief Macro to configure the OctoSPI clock.
+ * @param __OSPI_CLKSOURCE__ specifies the OctoSPI clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_OSPICLKSOURCE_SYSCLK System Clock selected as OctoSPI clock
+ * @arg @ref RCC_OSPICLKSOURCE_MSIK MSIK clock selected as OctoSPI clock
+ * @arg @ref RCC_OSPICLKSOURCE_PLL1 PLL1 Q divider clock selected as OctoSPI clock
+ * @arg @ref RCC_OSPICLKSOURCE_PLL2 PLL2 Q divider clock selected as OctoSPI clock
+ * @retval None
+ */
+#define __HAL_RCC_OSPI_CONFIG(__OSPI_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OCTOSPISEL, (uint32_t)(__OSPI_CLKSOURCE__))
+
+/** @brief Macro to get the OctoSPI clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_OSPICLKSOURCE_SYSCLK System Clock selected as OctoSPI clock
+ * @arg @ref RCC_OSPICLKSOURCE_MSIK MSIK clock selected as OctoSPI clock
+ * @arg @ref RCC_OSPICLKSOURCE_PLL1 PLL1 Q divider clock selected as OctoSPI clock
+ * @arg @ref RCC_OSPICLKSOURCE_PLL2 PLL2 Q divider clock selected as OctoSPI clock
+ */
+#define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_OCTOSPISEL)))
+
+/** @brief Macro to configure the SDMMC1/2 clock (SDMMCCLK).
+ * @param __SDMMC_CLKSOURCE__: specifies the SDMMC1/2 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SDMMCCLKSOURCE_CLK48: CLK48 selected as SDMMC1/2 clock
+ * @arg RCC_SDMMCCLKSOURCE_PLL1: PLL1 P selected as SDMMC1/2 clock
+ */
+#define __HAL_RCC_SDMMC_CONFIG(__SDMMC_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL, (uint32_t)(__SDMMC_CLKSOURCE__))
+
+/** @brief macro to get the SDMMC1/2 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_SDMMCCLKSOURCE_CLK48: CLK48 selected as SDMMC1/2 clock
+ * @arg RCC_SDMMCCLKSOURCE_PLL1: PLL1 P selected as SDMMC1/2 clock
+ */
+#define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL)))
+
+/** @brief macro to configure the RNG clock (RNGCLK).
+ * @param __RNG_CLKSource__: specifies the RNG clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
+ * @arg RCC_RNGCLKSOURCE_HSI48_DIV2: HSI48/2 selected as RNG clock
+ * @arg RCC_RNGCLKSOURCE_HSI: HSI selected as RNG clock
+ */
+#define __HAL_RCC_RNG_CONFIG(__RNG_CLKSource__) \
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_RNGSEL, (uint32_t)(__RNG_CLKSource__))
+
+/** @brief macro to get the RNG clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
+ * @arg RCC_RNGCLKSOURCE_HSI48_DIV2: HSI48/2 selected as RNG clock
+ * @arg RCC_RNGCLKSOURCE_HSI: HSI selected as RNG clock
+ */
+#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_RNGSEL)))
+
+/** @brief macro to configure the SAES clock (SAESCLK).
+ * @param __SAES_CLKSource__: specifies the SAES clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SAESCLKSOURCE_SHSI: SHSI selected as SAES clock
+ * @arg RCC_SAESCLKSOURCE_SHSI_DIV2: SHSI/2 selected as SAES clock
+ */
+#define __HAL_RCC_SAES_CONFIG(__SAES_CLKSource__) \
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAESSEL, (uint32_t)(__SAES_CLKSource__))
+
+/** @brief macro to get the SAES clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_SAESCLKSOURCE_SHSI: SHSI selected as SAES clock
+ * @arg RCC_SAESCLKSOURCE_SHSI_DIV2: SHSI/2 selected as SAES clock
+ */
+#define __HAL_RCC_GET_SAES_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAESSEL)))
+
+/**
+ * @brief Macro to configure the SAI1 clock source.
+ * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived
+ * from the PLL2, system PLL or external clock (through a dedicated pin).
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_SAI1CLKSOURCE_PLL2 SAI1 clock = PLL2 "P" clock (PLL2CLK)
+ * @arg @ref RCC_SAI1CLKSOURCE_PLL3 SAI1 clock = PLL3 "P" clock (PLL3CLK)
+ * @arg @ref RCC_SAI1CLKSOURCE_PLL1 SAI1 clock = PLL1 "P" clock (PLL1CLK)
+ * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK)
+ * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI16
+ *
+ * @note HSI16 is automatically set as SAI1 clock source when PLL are disabled for devices without PLL3.
+ * @retval None
+ */
+#define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL, (uint32_t)(__SAI1_CLKSOURCE__))
+
+/** @brief Macro to get the SAI1 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_SAI1CLKSOURCE_PLL2 SAI1 clock = PLL2 "P" clock (PLL2CLK)
+ * @arg @ref RCC_SAI1CLKSOURCE_PLL3 SAI1 clock = PLL3 "P" clock (PLL3CLK)
+ * @arg @ref RCC_SAI1CLKSOURCE_PLL1 SAI1 clock = PLL "P" clock (PLL1CLK)
+ * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK)
+ * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI16
+ * @note Despite returned values RCC_SAI1CLKSOURCE_PLL2 or RCC_SAI1CLKSOURCE_PLL, HSI16 is automatically set as SAI1
+ * clock source when PLLs are disabled for devices without PLL3.
+ */
+#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL)))
+
+/**
+ * @brief Macro to configure the SAI2 clock source.
+ * @param __SAI2_CLKSOURCE__ defines the SAI2 clock source. This clock is derived
+ * from the PLL3, system PLL or external clock (through a dedicated pin).
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_SAI2CLKSOURCE_PLL2 SAI2 clock = PLL2 "P" clock (PLL2CLK)
+ * @arg @ref RCC_SAI2CLKSOURCE_PLL3 SAI2 clock = PLL3 "P" clock (PLL3CLK)
+ * @arg @ref RCC_SAI2CLKSOURCE_PLL1 SAI2 clock = PLL1 "P" clock (PLL1CLK)
+ * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK)
+ * @arg @ref RCC_SAI2CLKSOURCE_HSI SAI2 clock = HSI16
+ * @retval None
+ */
+#define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL, (uint32_t)(__SAI2_CLKSOURCE__))
+
+/** @brief Macro to get the SAI2 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_SAI2CLKSOURCE_PLL2 SAI2 clock = PLL2 "P" clock (PLL2CLK)
+ * @arg @ref RCC_SAI2CLKSOURCE_PLL3 SAI2 clock = PLL3 "P" clock (PLL3CLK)
+ * @arg @ref RCC_SAI2CLKSOURCE_PLL1 SAI2 clock = PLL1 "P" clock (PLL1CLK)
+ * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK)
+ * @arg @ref RCC_SAI2CLKSOURCE_HSI SAI2 clock = HSI16
+ */
+#define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL)))
+
+/** @brief Macro to configure the MDF1 clock.
+ * @param __MDF1_CLKSOURCE__ specifies the MDF1 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MDF1CLKSOURCE_HCLK HCLK Clock selected as MDF1 clock
+ * @arg @ref RCC_MDF1CLKSOURCE_PLL1 PLL1 P Clock selected as MDF1 clock
+ * @arg @ref RCC_MDF1CLKSOURCE_PLL3 PLL3 Q Clock selected as MDF1 clock
+ * @arg @ref RCC_MDF1CLKSOURCE_PIN External Clock (SAI1_EXTCLK) selected as MDF1 clock
+ * @arg @ref RCC_MDF1CLKSOURCE_MSIK MSIK Clock selected as MDF1 clock
+ * @retval None
+ */
+#define __HAL_RCC_MDF1_CONFIG(__MDF1_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_MDF1SEL, (uint32_t)(__MDF1_CLKSOURCE__))
+
+/** @brief Macro to get the MDF1 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_MDF1CLKSOURCE_HCLK HCLK Clock used as MDF1 clock
+ * @arg @ref RCC_MDF1CLKSOURCE_PLL1 PLL1 Clock used as MDF1 clock
+ * @arg @ref RCC_MDF1CLKSOURCE_PLL3 PLL3 Clock used as MDF1 clock
+ * @arg @ref RCC_MDF1CLKSOURCE_PIN External Clock (SAI1_EXTCLK) used as MDF1 clock
+ * @arg @ref RCC_MDF1CLKSOURCE_MSIK MSIK Clock used as MDF1 clock
+ */
+#define __HAL_RCC_GET_MDF1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_MDF1SEL)))
+
+/** @brief Macro to configure the ADF1 clock.
+ * @param __ADF1_CLKSOURCE__ specifies the ADF1 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_ADF1CLKSOURCE_HCLK HCLK Clock selected as ADF1 clock
+ * @arg @ref RCC_ADF1CLKSOURCE_PLL1 PLL1 P Clock selected as ADF1 clock
+ * @arg @ref RCC_ADF1CLKSOURCE_PLL3 PLL3 Q Clock selected as ADF1 clock
+ * @arg @ref RCC_ADF1CLKSOURCE_PIN External Clock (SAI1_EXTCLK) selected as ADF1 clock
+ * @arg @ref RCC_ADF1CLKSOURCE_MSIK MSI Clock selected as ADF1 clock
+ * @retval None
+ */
+#define __HAL_RCC_ADF1_CONFIG(__ADF1_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_ADF1SEL, (uint32_t)(__ADF1_CLKSOURCE__))
+
+/** @brief Macro to get the ADF1 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_ADF1CLKSOURCE_HCLK HCLK Clock used as ADF1 clock
+ * @arg @ref RCC_ADF1CLKSOURCE_PLL1 PLL1 P Clock used as ADF1 clock
+ * @arg @ref RCC_ADF1CLKSOURCE_PLL3 PLL3 Q Clock used as ADF1 clock
+ * @arg @ref RCC_ADF1CLKSOURCE_PIN External Clock (SAI1_EXTCLK) used as ADF1 clock
+ * @arg @ref RCC_ADF1CLKSOURCE_MSIK MSI Clock used as ADF1 clock
+ */
+#define __HAL_RCC_GET_ADF1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_ADF1SEL)))
+
+/** @brief Macro to configure the DAC1 interface clock.
+ * @param __DAC1_CLKSOURCE__ specifies the DAC1 digital interface clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_DAC1CLKSOURCE_LSE LSE clock selected as DAC1 clock
+ * @arg @ref RCC_DAC1CLKSOURCE_LSI LSI clock selected as DAC1 clock
+ * @retval None
+ */
+#define __HAL_RCC_DAC1_CONFIG(__DAC1_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_DAC1SEL, (uint32_t)(__DAC1_CLKSOURCE__))
+
+/** @brief Macro to get the DAC1 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_DAC1CLKSOURCE_LSE LSE clock selected as DAC1 clock
+ * @arg @ref RCC_DAC1CLKSOURCE_LSI LSI clock selected as DAC1 clock
+ */
+#define __HAL_RCC_GET_DAC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_DAC1SEL)))
+
+#if defined(CRS)
+
+/**
+ * @brief Enable the specified CRS interrupts.
+ * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
+ * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
+ * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
+ * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
+ * @retval None
+ */
+#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
+
+/**
+ * @brief Disable the specified CRS interrupts.
+ * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled.
+ * This parameter can be any combination of the following values:
+ * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
+ * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
+ * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
+ * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
+ * @retval None
+ */
+#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__))
+
+/** @brief Check whether the CRS interrupt has occurred or not.
+ * @param __INTERRUPT__ specifies the CRS interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
+ * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
+ * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
+ * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
+ * @retval The new state of __INTERRUPT__ (SET or RESET).
+ */
+#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET)
+
+/** @brief Clear the CRS interrupt pending bits
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
+ * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
+ * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
+ * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
+ * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt
+ * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt
+ * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt
+ */
+#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
+
+#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \
+ if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \
+ { \
+ WRITE_REG(CRS->ICR, CRS_ICR_ERRC |\
+ ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
+ } \
+ else \
+ { \
+ WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
+ } \
+ } while(0)
+
+/**
+ * @brief Check whether the specified CRS flag is set or not.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
+ * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
+ * @arg @ref RCC_CRS_FLAG_ERR Error
+ * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
+ * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
+ * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
+ * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
+ * @retval The new state of _FLAG_ (TRUE or FALSE).
+ */
+#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clear the CRS specified FLAG.
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
+ * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
+ * @arg @ref RCC_CRS_FLAG_ERR Error
+ * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
+ * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
+ * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
+ * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
+ * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently
+ * RCC_CRS_FLAG_ERR
+ * @retval None
+ */
+#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | \
+ RCC_CRS_FLAG_SYNCMISS))
+
+#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \
+ if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \
+ { \
+ WRITE_REG(CRS->ICR, CRS_ICR_ERRC | \
+ ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
+ } \
+ else \
+ { \
+ WRITE_REG(CRS->ICR, (__FLAG__)); \
+ } \
+ } while(0)
+
+/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
+ * @{
+ */
+/**
+ * @brief Enable the oscillator clock for frequency error counter.
+ * @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
+ * @retval None
+ */
+#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)
+
+/**
+ * @brief Disable the oscillator clock for frequency error counter.
+ * @retval None
+ */
+#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
+
+/**
+ * @brief Enable the automatic hardware adjustment of TRIM bits.
+ * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
+ * @retval None
+ */
+#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
+
+/**
+ * @brief Enable or disable the automatic hardware adjustment of TRIM bits.
+ * @retval None
+ */
+#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
+
+/**
+ * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
+ * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
+ * of the synchronization source after prescaling. It is then decreased by one in order to
+ * reach the expected synchronization on the zero value. The formula is the following:
+ * RELOAD = (fTARGET / fSYNC) -1
+ * @param __FTARGET__ Target frequency (value in Hz)
+ * @param __FSYNC__ Synchronization signal frequency (value in Hz)
+ * @retval None
+ */
+#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
+
+
+/**
+ * @}
+ */
+
+#endif /* CRS */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCCEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RCCEx_Exported_Functions_Group1
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit);
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit);
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
+void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks);
+void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks);
+void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks);
+/**
+ * @}
+ */
+
+/** @addtogroup RCCEx_Exported_Functions_Group2
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init);
+HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void);
+HAL_StatusTypeDef HAL_RCCEx_EnablePLL3(RCC_PLL3InitTypeDef *PLL3Init);
+HAL_StatusTypeDef HAL_RCCEx_DisablePLL3(void);
+HAL_StatusTypeDef HAL_RCCEx_EnableMSIPLLFastStartup(void);
+HAL_StatusTypeDef HAL_RCCEx_DisableMSIPLLFastStartup(void);
+HAL_StatusTypeDef HAL_RCCEx_EnableMSIPLLModeSelection(uint32_t MSIPLLModeSelection);
+void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk);
+void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk);
+void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange);
+void HAL_RCCEx_EnableLSECSS(void);
+void HAL_RCCEx_DisableLSECSS(void);
+void HAL_RCCEx_LSECSS_IRQHandler(void);
+void HAL_RCCEx_LSECSS_Callback(void);
+void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource);
+void HAL_RCCEx_DisableLSCO(void);
+void HAL_RCCEx_EnableMSIPLLMode(void);
+void HAL_RCCEx_DisableMSIPLLMode(void);
+
+/**
+ * @}
+ */
+
+#if defined(CRS)
+
+/** @addtogroup RCCEx_Exported_Functions_Group3
+ * @{
+ */
+void HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef *const pInit);
+void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
+void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
+uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
+void HAL_RCCEx_CRS_IRQHandler(void);
+void HAL_RCCEx_CRS_SyncOkCallback(void);
+void HAL_RCCEx_CRS_SyncWarnCallback(void);
+void HAL_RCCEx_CRS_ExpectedSyncCallback(void);
+void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
+/**
+ * @}
+ */
+
+#endif /* CRS */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_RCC_EX_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rng.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rng.h
new file mode 100644
index 00000000..1a07a943
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rng.h
@@ -0,0 +1,388 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_rng.h
+ * @author MCD Application Team
+ * @brief Header file of RNG HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_RNG_H
+#define STM32U5xx_HAL_RNG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+#if defined (RNG)
+
+/** @defgroup RNG RNG
+ * @brief RNG HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup RNG_Exported_Types RNG Exported Types
+ * @{
+ */
+
+/** @defgroup RNG_Exported_Types_Group1 RNG Init Structure definition
+ * @{
+ */
+typedef struct
+{
+ uint32_t ClockErrorDetection; /*!< CED Clock error detection */
+} RNG_InitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup RNG_Exported_Types_Group2 RNG State Structure definition
+ * @{
+ */
+typedef enum
+{
+ HAL_RNG_STATE_RESET = 0x00U, /*!< RNG not yet initialized or disabled */
+ HAL_RNG_STATE_READY = 0x01U, /*!< RNG initialized and ready for use */
+ HAL_RNG_STATE_BUSY = 0x02U, /*!< RNG internal process is ongoing */
+ HAL_RNG_STATE_TIMEOUT = 0x03U, /*!< RNG timeout state */
+ HAL_RNG_STATE_ERROR = 0x04U /*!< RNG error state */
+
+} HAL_RNG_StateTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup RNG_Exported_Types_Group3 RNG Handle Structure definition
+ * @{
+ */
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+typedef struct __RNG_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+{
+ RNG_TypeDef *Instance; /*!< Register base address */
+
+ RNG_InitTypeDef Init; /*!< RNG configuration parameters */
+
+ HAL_LockTypeDef Lock; /*!< RNG locking object */
+
+ __IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */
+
+ __IO uint32_t ErrorCode; /*!< RNG Error code */
+
+ uint32_t RandomNumber; /*!< Last Generated RNG Data */
+
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+ void (* ReadyDataCallback)(struct __RNG_HandleTypeDef *hrng, uint32_t random32bit); /*!< RNG Data Ready Callback */
+ void (* ErrorCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Error Callback */
+
+ void (* MspInitCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Msp Init callback */
+ void (* MspDeInitCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Msp DeInit callback */
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+
+} RNG_HandleTypeDef;
+
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL RNG Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_RNG_ERROR_CB_ID = 0x00U, /*!< RNG Error Callback ID */
+
+ HAL_RNG_MSPINIT_CB_ID = 0x01U, /*!< RNG MspInit callback ID */
+ HAL_RNG_MSPDEINIT_CB_ID = 0x02U /*!< RNG MspDeInit callback ID */
+
+} HAL_RNG_CallbackIDTypeDef;
+
+/**
+ * @brief HAL RNG Callback pointer definition
+ */
+typedef void (*pRNG_CallbackTypeDef)(RNG_HandleTypeDef *hrng); /*!< pointer to a common RNG callback function */
+typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t random32bit); /*!< pointer to an RNG Data Ready specific callback function */
+
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RNG_Exported_Constants RNG Exported Constants
+ * @{
+ */
+
+/** @defgroup RNG_Exported_Constants_Group1 RNG Interrupt definition
+ * @{
+ */
+#define RNG_IT_DRDY RNG_SR_DRDY /*!< Data Ready interrupt */
+#define RNG_IT_CEI RNG_SR_CEIS /*!< Clock error interrupt */
+#define RNG_IT_SEI RNG_SR_SEIS /*!< Seed error interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup RNG_Exported_Constants_Group2 RNG Flag definition
+ * @{
+ */
+#define RNG_FLAG_DRDY RNG_SR_DRDY /*!< Data ready */
+#define RNG_FLAG_CECS RNG_SR_CECS /*!< Clock error current status */
+#define RNG_FLAG_SECS RNG_SR_SECS /*!< Seed error current status */
+/**
+ * @}
+ */
+
+/** @defgroup RNG_Exported_Constants_Group3 RNG Clock Error Detection
+ * @{
+ */
+#define RNG_CED_ENABLE 0x00000000U /*!< Clock error detection Enabled */
+#define RNG_CED_DISABLE RNG_CR_CED /*!< Clock error detection Disabled */
+/**
+ * @}
+ */
+
+/** @defgroup RNG_Error_Definition RNG Error Definition
+ * @{
+ */
+#define HAL_RNG_ERROR_NONE 0x00000000U /*!< No error */
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+#define HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U /*!< Invalid Callback error */
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+#define HAL_RNG_ERROR_TIMEOUT 0x00000002U /*!< Timeout error */
+#define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */
+#define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */
+#define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup RNG_Exported_Macros RNG Exported Macros
+ * @{
+ */
+
+/** @brief Reset RNG handle state
+ * @param __HANDLE__ RNG Handle
+ * @retval None
+ */
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_RNG_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0U)
+#else
+#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+
+/**
+ * @brief Enables the RNG peripheral.
+ * @param __HANDLE__ RNG Handle
+ * @retval None
+ */
+#define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)
+
+/**
+ * @brief Disables the RNG peripheral.
+ * @param __HANDLE__ RNG Handle
+ * @retval None
+ */
+#define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
+
+/**
+ * @brief Check the selected RNG flag status.
+ * @param __HANDLE__ RNG Handle
+ * @param __FLAG__ RNG flag
+ * This parameter can be one of the following values:
+ * @arg RNG_FLAG_DRDY: Data ready
+ * @arg RNG_FLAG_CECS: Clock error current status
+ * @arg RNG_FLAG_SECS: Seed error current status
+ * @retval The new state of __FLAG__ (SET or RESET).
+ */
+#define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clears the selected RNG flag status.
+ * @param __HANDLE__ RNG handle
+ * @param __FLAG__ RNG flag to clear
+ * @note WARNING: This is a dummy macro for HAL code alignment,
+ * flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
+ * @retval None
+ */
+#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */
+
+/**
+ * @brief Enables the RNG interrupts.
+ * @param __HANDLE__ RNG Handle
+ * @retval None
+ */
+#define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)
+
+/**
+ * @brief Disables the RNG interrupts.
+ * @param __HANDLE__ RNG Handle
+ * @retval None
+ */
+#define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
+
+/**
+ * @brief Checks whether the specified RNG interrupt has occurred or not.
+ * @param __HANDLE__ RNG Handle
+ * @param __INTERRUPT__ specifies the RNG interrupt status flag to check.
+ * This parameter can be one of the following values:
+ * @arg RNG_IT_DRDY: Data ready interrupt
+ * @arg RNG_IT_CEI: Clock error interrupt
+ * @arg RNG_IT_SEI: Seed error interrupt
+ * @retval The new state of __INTERRUPT__ (SET or RESET).
+ */
+#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+ * @brief Clear the RNG interrupt status flags.
+ * @param __HANDLE__ RNG Handle
+ * @param __INTERRUPT__ specifies the RNG interrupt status flag to clear.
+ * This parameter can be one of the following values:
+ * @arg RNG_IT_CEI: Clock error interrupt
+ * @arg RNG_IT_SEI: Seed error interrupt
+ * @note RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.
+ * @retval None
+ */
+#define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
+
+/**
+ * @}
+ */
+
+/* Include RNG HAL Extended module */
+#include "stm32u5xx_hal_rng_ex.h"
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RNG_Exported_Functions RNG Exported Functions
+ * @{
+ */
+
+/** @defgroup RNG_Exported_Functions_Group1 Initialization and configuration functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
+HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng);
+void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
+void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID,
+ pRNG_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng);
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
+uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);
+
+void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
+void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
+void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit);
+
+/**
+ * @}
+ */
+
+/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
+ * @{
+ */
+HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
+uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup RNG_Private_Macros RNG Private Macros
+ * @{
+ */
+#define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \
+ ((IT) == RNG_IT_SEI))
+
+#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
+ ((FLAG) == RNG_FLAG_CECS) || \
+ ((FLAG) == RNG_FLAG_SECS))
+
+/**
+ * @brief Verify the RNG Clock Error Detection mode.
+ * @param __MODE__ RNG Clock Error Detection mode
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_RNG_CED(__MODE__) (((__MODE__) == RNG_CED_ENABLE) || \
+ ((__MODE__) == RNG_CED_DISABLE))
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup RNG_Private_Functions RNG Private functions
+ * @{
+ */
+HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng);
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+#endif /* RNG */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32U5xx_HAL_RNG_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rng_ex.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rng_ex.h
new file mode 100644
index 00000000..cf62366f
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rng_ex.h
@@ -0,0 +1,262 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_rng_ex.h
+ * @author MCD Application Team
+ * @brief Header file of RNG HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_RNG_EX_H
+#define STM32U5xx_HAL_RNG_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+#if defined(RNG)
+#if defined(RNG_CR_CONDRST)
+
+/** @defgroup RNGEx RNGEx
+ * @brief RNG Extension HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RNGEx_Exported_Types RNGEx Exported Types
+ * @brief RNGEx Exported types
+ * @{
+ */
+
+/**
+ * @brief RNGEX Configuration Structure definition
+ */
+
+typedef struct
+{
+ uint32_t Config1; /*!< Config1 must be a value between 0 and 0x3F */
+ uint32_t Config2; /*!< Config2 must be a value between 0 and 0x7 */
+ uint32_t Config3; /*!< Config3 must be a value between 0 and 0xF */
+ uint32_t ClockDivider; /*!< Clock Divider factor.This parameter can
+ be a value of @ref RNGEX_Clock_Divider_Factor */
+ uint32_t NistCompliance; /*!< NIST compliance.This parameter can be a
+ value of @ref RNGEX_NIST_Compliance */
+ uint32_t AutoReset; /*!< automatic reset When a noise source error occurs
+ value of @ref RNGEX_Auto_Reset */
+ uint32_t HealthTest; /*!< RNG health test control must be a value
+ between 0x0FFCABFF and 0x00005200 */
+} RNG_ConfigTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RNGEX_Exported_Constants RNGEX Exported Constants
+ * @{
+ */
+
+/** @defgroup RNGEX_Clock_Divider_Factor Value used to configure an internal
+ * programmable divider acting on the incoming RNG clock
+ * @{
+ */
+#define RNG_CLKDIV_BY_1 (0x00000000UL) /*!< No clock division */
+#define RNG_CLKDIV_BY_2 (RNG_CR_CLKDIV_0)
+/*!< 2 RNG clock cycles per internal RNG clock */
+#define RNG_CLKDIV_BY_4 (RNG_CR_CLKDIV_1)
+/*!< 4 RNG clock cycles per internal RNG clock */
+#define RNG_CLKDIV_BY_8 (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
+/*!< 8 RNG clock cycles per internal RNG clock */
+#define RNG_CLKDIV_BY_16 (RNG_CR_CLKDIV_2)
+/*!< 16 RNG clock cycles per internal RNG clock */
+#define RNG_CLKDIV_BY_32 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)
+/*!< 32 RNG clock cycles per internal RNG clock */
+#define RNG_CLKDIV_BY_64 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)
+/*!< 64 RNG clock cycles per internal RNG clock */
+#define RNG_CLKDIV_BY_128 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
+/*!< 128 RNG clock cycles per internal RNG clock */
+#define RNG_CLKDIV_BY_256 (RNG_CR_CLKDIV_3)
+/*!< 256 RNG clock cycles per internal RNG clock */
+#define RNG_CLKDIV_BY_512 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0)
+/*!< 512 RNG clock cycles per internal RNG clock */
+#define RNG_CLKDIV_BY_1024 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1)
+/*!< 1024 RNG clock cycles per internal RNG clock */
+#define RNG_CLKDIV_BY_2048 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
+/*!< 2048 RNG clock cycles per internal RNG clock */
+#define RNG_CLKDIV_BY_4096 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2)
+/*!< 4096 RNG clock cycles per internal RNG clock */
+#define RNG_CLKDIV_BY_8192 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)
+/*!< 8192 RNG clock cycles per internal RNG clock */
+#define RNG_CLKDIV_BY_16384 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)
+/*!< 16384 RNG clock cycles per internal RNG clock */
+#define RNG_CLKDIV_BY_32768 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
+/*!< 32768 RNG clock cycles per internal RNG clock */
+/**
+ * @}
+ */
+
+/** @defgroup RNGEX_NIST_Compliance NIST Compliance configuration
+ * @{
+ */
+#define RNG_NIST_COMPLIANT (0x00000000UL) /*!< NIST compliant configuration*/
+#define RNG_CUSTOM_NIST (RNG_CR_NISTC) /*!< Custom NIST configuration */
+
+/**
+ * @}
+ */
+/** @defgroup RNGEX_Auto_Reset Auto Reset configuration
+ * @{
+ */
+#define RNG_ARDIS_ENABLE (0x00000000UL) /*!< automatic reset after seed error*/
+#define RNG_ARDIS_DISABLE (RNG_CR_ARDIS) /*!< Disable automatic reset after seed error */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup RNGEx_Private_Types RNGEx Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup RNGEx_Private_Variables RNGEx Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RNGEx_Private_Constants RNGEx Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup RNGEx_Private_Macros RNGEx Private Macros
+ * @{
+ */
+
+#define IS_RNG_CLOCK_DIVIDER(__CLOCK_DIV__) (((__CLOCK_DIV__) == RNG_CLKDIV_BY_1) || \
+ ((__CLOCK_DIV__) == RNG_CLKDIV_BY_2) || \
+ ((__CLOCK_DIV__) == RNG_CLKDIV_BY_4) || \
+ ((__CLOCK_DIV__) == RNG_CLKDIV_BY_8) || \
+ ((__CLOCK_DIV__) == RNG_CLKDIV_BY_16) || \
+ ((__CLOCK_DIV__) == RNG_CLKDIV_BY_32) || \
+ ((__CLOCK_DIV__) == RNG_CLKDIV_BY_64) || \
+ ((__CLOCK_DIV__) == RNG_CLKDIV_BY_128) || \
+ ((__CLOCK_DIV__) == RNG_CLKDIV_BY_256) || \
+ ((__CLOCK_DIV__) == RNG_CLKDIV_BY_512) || \
+ ((__CLOCK_DIV__) == RNG_CLKDIV_BY_1024) || \
+ ((__CLOCK_DIV__) == RNG_CLKDIV_BY_2048) || \
+ ((__CLOCK_DIV__) == RNG_CLKDIV_BY_4096) || \
+ ((__CLOCK_DIV__) == RNG_CLKDIV_BY_8192) || \
+ ((__CLOCK_DIV__) == RNG_CLKDIV_BY_16384) || \
+ ((__CLOCK_DIV__) == RNG_CLKDIV_BY_32768))
+
+
+#define IS_RNG_NIST_COMPLIANCE(__NIST_COMPLIANCE__) (((__NIST_COMPLIANCE__) == RNG_NIST_COMPLIANT) || \
+ ((__NIST_COMPLIANCE__) == RNG_CUSTOM_NIST))
+
+#define IS_RNG_CONFIG1(__CONFIG1__) ((__CONFIG1__) <= 0x3FUL)
+
+#define IS_RNG_CONFIG2(__CONFIG2__) ((__CONFIG2__) <= 0x07UL)
+
+#define IS_RNG_CONFIG3(__CONFIG3__) ((__CONFIG3__) <= 0xFUL)
+#define IS_RNG_ARDIS(__ARDIS__) (((__ARDIS__) == RNG_ARDIS_ENABLE) || \
+ ((__ARDIS__) == RNG_ARDIS_DISABLE))
+
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup RNGEx_Private_Functions RNGEx Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RNGEx_Exported_Functions RNGEx Exported Functions
+ * @{
+ */
+
+/** @addtogroup RNGEx_Exported_Functions_Group1
+ * @{
+ */
+HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf);
+HAL_StatusTypeDef HAL_RNGEx_GetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf);
+HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng);
+
+/**
+ * @}
+ */
+
+/** @addtogroup RNGEx_Exported_Functions_Group2
+ * @{
+ */
+HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* RNG_CR_CONDRST */
+#endif /* RNG */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32U5xx_HAL_RNGEX_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rtc.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rtc.h
new file mode 100644
index 00000000..3aa5ee08
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rtc.h
@@ -0,0 +1,962 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_rtc.h
+ * @author MCD Application Team
+ * @brief Header file of RTC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_RTC_H
+#define STM32U5xx_HAL_RTC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup RTC RTC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RTC_Exported_Types RTC Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */
+ HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */
+ HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */
+ HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */
+ HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */
+
+} HAL_RTCStateTypeDef;
+
+/**
+ * @brief RTC Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t HourFormat; /*!< Specifies the RTC Hour Format.
+ This parameter can be a value of @ref RTC_Hour_Formats */
+
+ uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
+
+ uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
+
+ uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output.
+ This parameter can be a value of @ref RTCEx_Output_selection_Definitions */
+
+ uint32_t OutPutRemap; /*!< Specifies the remap for RTC output.
+ This parameter can be a value of @ref RTC_Output_ALARM_OUT_Remap */
+
+ uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal.
+ This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
+
+ uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode.
+ This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
+
+ uint32_t OutPutPullUp; /*!< Specifies the RTC Output Pull-Up mode.
+ This parameter can be a value of @ref RTC_Output_PullUp_ALARM_OUT */
+
+ uint32_t BinMode; /*!< Specifies the RTC binary mode.
+ This parameter can be a value of @ref RTCEx_Binary_Mode */
+
+ uint32_t BinMixBcdU; /*!< Specifies the BCD calendar update if and only if BinMode = RTC_BINARY_MIX.
+ This parameter can be a value of @ref RTCEx_Binary_mix_BCDU */
+} RTC_InitTypeDef;
+
+/**
+ * @brief RTC Time structure definition
+ */
+typedef struct
+{
+ uint8_t Hours; /*!< Specifies the RTC Time Hour.
+ This parameter must be a number between:
+ Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
+ This parameter must be a number between:
+ Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
+
+ uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
+
+ uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
+
+ uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
+ This parameter can be a value of @ref RTC_AM_PM_Definitions */
+
+ uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content.
+ This field is not used by HAL_RTC_SetTime.
+ If the free running 32 bit counter is not activated (mode binary none)
+ - This parameter corresponds to a time unit range
+ between [0-1] Second with [1 Sec / SecondFraction +1] granularity
+ else
+ - This parameter corresponds to the free running 32 bit counter. */
+
+ uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content
+ corresponding to Synchronous pre-scaler factor value (PREDIV_S)
+ This parameter corresponds to a time unit range between [0-1] Second
+ with [1 Sec / SecondFraction +1] granularity.
+ This field will be used only by HAL_RTC_GetTime function */
+
+ uint32_t DayLightSaving; /*!< This interface is deprecated. To manage Daylight SavingTime,use HAL_RTC_DST_xxx functions */
+
+ uint32_t StoreOperation; /*!< This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */
+} RTC_TimeTypeDef;
+
+/**
+ * @brief RTC Date structure definition
+ */
+typedef struct
+{
+ uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.
+ This parameter can be a value of @ref RTC_WeekDay_Definitions */
+
+ uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format).
+ This parameter can be a value of @ref RTC_Month_Date_Definitions */
+
+ uint8_t Date; /*!< Specifies the RTC Date.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
+
+ uint8_t Year; /*!< Specifies the RTC Date Year.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
+} RTC_DateTypeDef;
+
+/**
+ * @brief RTC Alarm structure definition
+ */
+typedef struct
+{
+ RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */
+
+ uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
+ This parameter can be a value of @ref RTC_AlarmMask_Definitions */
+
+ uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks.
+ if Binary mode is RTC_BINARY_ONLY or is RTC_BINARY_MIX
+ This parameter can be a value of
+ @ref RTCEx_Alarm_Sub_Seconds_binary_Masks_Definitions
+ else if Binary mode is RTC_BINARY_NONE
+ This parameter can be a value of
+ @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
+
+ uint32_t BinaryAutoClr; /*!< Clear synchronously counter (RTC_SSR) on binary alarm.
+ RTC_ALARMSUBSECONDBIN_AUTOCLR_YES must only be used if Binary mode
+ is RTC_BINARY_ONLY
+ This parameter can be a value of
+ @ref RTCEx_Alarm_Sub_Seconds_binary_Clear_Definitions */
+
+ uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
+ This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
+
+ uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
+ If the Alarm Date is selected, this parameter must be set to a value
+ in the 1-31 range.
+ If the Alarm WeekDay is selected, this parameter can be a value of
+ @ref RTC_WeekDay_Definitions */
+
+ uint32_t FlagAutoClr; /*!< Specifies the alarm trigger generation. This feature is meaningful
+ to avoid any RTC software execution after configuration.
+ This parameter can be a value of @ref RTC_ALARM_Flag_AutoClear_Definitions */
+
+ uint32_t Alarm; /*!< Specifies the alarm .
+ This parameter can be a value of @ref RTC_Alarms_Definitions */
+} RTC_AlarmTypeDef;
+
+/**
+ * @brief RTC Handle Structure definition
+ */
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+typedef struct __RTC_HandleTypeDef
+#else
+typedef struct
+#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
+{
+ RTC_TypeDef *Instance; /*!< Legacy register base address. Not used anymore, the driver directly uses cmsis base address */
+
+ RTC_InitTypeDef Init; /*!< RTC required parameters */
+
+ HAL_LockTypeDef Lock; /*!< RTC locking object */
+
+ __IO HAL_RTCStateTypeDef State; /*!< Time communication state */
+
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ void (* AlarmAEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm A Event callback */
+ void (* AlarmBEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm B Event callback */
+ void (* TimeStampEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC TimeStamp Event callback */
+ void (* WakeUpTimerEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC WakeUpTimer Event callback */
+ void (* SSRUEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC SSRU Event callback */
+ void (* Tamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 1 Event callback */
+ void (* Tamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 2 Event callback */
+ void (* Tamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 3 Event callback */
+ void (* Tamper4EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 4 Event callback */
+ void (* Tamper5EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 5 Event callback */
+ void (* Tamper6EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 6 Event callback */
+ void (* Tamper7EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 7 Event callback */
+ void (* Tamper8EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 8 Event callback */
+ void (* InternalTamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 1 Event callback */
+ void (* InternalTamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 2 Event callback */
+ void (* InternalTamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 3 Event callback */
+ void (* InternalTamper5EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 5 Event callback */
+ void (* InternalTamper6EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 6 Event callback */
+ void (* InternalTamper7EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 7 Event callback */
+ void (* InternalTamper8EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 8 Event callback */
+ void (* InternalTamper9EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 9 Event callback */
+ void (* InternalTamper11EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 11 Event callback */
+ void (* InternalTamper12EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 12 Event callback */
+ void (* InternalTamper13EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 13 Event callback */
+ void (* MspInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp Init callback */
+ void (* MspDeInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp DeInit callback */
+
+#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
+
+} RTC_HandleTypeDef;
+
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL RTC Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_RTC_ALARM_A_EVENT_CB_ID = 0U, /*!< RTC Alarm A Event Callback ID */
+ HAL_RTC_ALARM_B_EVENT_CB_ID = 1U, /*!< RTC Alarm B Event Callback ID */
+ HAL_RTC_TIMESTAMP_EVENT_CB_ID = 2U, /*!< RTC TimeStamp Event Callback ID */
+ HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 3U, /*!< RTC WakeUp Timer Event Callback ID */
+ HAL_RTC_SSRU_EVENT_CB_ID = 4U, /*!< RTC SSRU Event Callback ID */
+ HAL_RTC_TAMPER1_EVENT_CB_ID = 5U, /*!< RTC Tamper 1 Callback ID */
+ HAL_RTC_TAMPER2_EVENT_CB_ID = 6U, /*!< RTC Tamper 2 Callback ID */
+ HAL_RTC_TAMPER3_EVENT_CB_ID = 7U, /*!< RTC Tamper 3 Callback ID */
+ HAL_RTC_TAMPER4_EVENT_CB_ID = 8U, /*!< RTC Tamper 4 Callback ID */
+ HAL_RTC_TAMPER5_EVENT_CB_ID = 9U, /*!< RTC Tamper 5 Callback ID */
+ HAL_RTC_TAMPER6_EVENT_CB_ID = 10U, /*!< RTC Tamper 6 Callback ID */
+ HAL_RTC_TAMPER7_EVENT_CB_ID = 11U, /*!< RTC Tamper 7 Callback ID */
+ HAL_RTC_TAMPER8_EVENT_CB_ID = 12U, /*!< RTC Tamper 8 Callback ID */
+ HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID = 13U, /*!< RTC Internal Tamper 1 Callback ID */
+ HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID = 14U, /*!< RTC Internal Tamper 2 Callback ID */
+ HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID = 15U, /*!< RTC Internal Tamper 3 Callback ID */
+ HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID = 16U, /*!< RTC Internal Tamper 5 Callback ID */
+ HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID = 17U, /*!< RTC Internal Tamper 6 Callback ID */
+ HAL_RTC_INTERNAL_TAMPER7_EVENT_CB_ID = 18U, /*!< RTC Internal Tamper 7 Callback ID */
+ HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID = 19U, /*!< RTC Internal Tamper 8 Callback ID */
+ HAL_RTC_INTERNAL_TAMPER9_EVENT_CB_ID = 20U, /*!< RTC Internal Tamper 9 Callback ID */
+ HAL_RTC_INTERNAL_TAMPER11_EVENT_CB_ID = 21U, /*!< RTC Internal Tamper 11 Callback ID */
+ HAL_RTC_INTERNAL_TAMPER12_EVENT_CB_ID = 22U, /*!< RTC Internal Tamper 12 Callback ID */
+ HAL_RTC_INTERNAL_TAMPER13_EVENT_CB_ID = 23U, /*!< RTC Internal Tamper 13 Callback ID */
+ HAL_RTC_MSPINIT_CB_ID = 24U, /*!< RTC Msp Init callback ID */
+ HAL_RTC_MSPDEINIT_CB_ID = 25U /*!< RTC Msp DeInit callback ID */
+} HAL_RTC_CallbackIDTypeDef;
+
+/**
+ * @brief HAL RTC Callback pointer definition
+ */
+typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to an RTC callback function */
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RTC_Exported_Constants RTC Exported Constants
+ * @{
+ */
+
+/** @defgroup RTC_Hour_Formats RTC Hour Formats
+ * @{
+ */
+#define RTC_HOURFORMAT_24 0x00000000u
+#define RTC_HOURFORMAT_12 RTC_CR_FMT
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Output_selection_Definitions RTCEx Output Selection Definition
+ * @{
+ */
+#define RTC_OUTPUT_DISABLE 0x00000000u
+#define RTC_OUTPUT_ALARMA RTC_CR_OSEL_0
+#define RTC_OUTPUT_ALARMB RTC_CR_OSEL_1
+#define RTC_OUTPUT_WAKEUP RTC_CR_OSEL
+#define RTC_OUTPUT_TAMPER RTC_CR_TAMPOE
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
+ * @{
+ */
+#define RTC_OUTPUT_POLARITY_HIGH 0x00000000u
+#define RTC_OUTPUT_POLARITY_LOW RTC_CR_POL
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
+ * @{
+ */
+#define RTC_OUTPUT_TYPE_PUSHPULL 0x00000000u
+#define RTC_OUTPUT_TYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Output_PullUp_ALARM_OUT RTC Output Pull-Up ALARM OUT
+ * @{
+ */
+#define RTC_OUTPUT_PULLUP_NONE 0x00000000u
+#define RTC_OUTPUT_PULLUP_ON RTC_CR_TAMPALRM_PU
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Output_ALARM_OUT_Remap RTC Output ALARM OUT Remap
+ * @{
+ */
+#define RTC_OUTPUT_REMAP_NONE 0x00000000u
+#define RTC_OUTPUT_REMAP_POS1 RTC_CR_OUT2EN
+/**
+ * @}
+ */
+
+/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
+ * @{
+ */
+#define RTC_HOURFORMAT12_AM 0x0u
+#define RTC_HOURFORMAT12_PM 0x1u
+/**
+ * @}
+ */
+
+/** @defgroup RTC_DayLightSaving_Definitions RTC DayLightSaving Definitions
+ * @{
+ */
+#define RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H
+#define RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H
+#define RTC_DAYLIGHTSAVING_NONE 0x00000000u
+/**
+ * @}
+ */
+
+/** @defgroup RTC_StoreOperation_Definitions RTC StoreOperation Definitions
+ * @{
+ */
+#define RTC_STOREOPERATION_RESET 0x00000000u
+#define RTC_STOREOPERATION_SET RTC_CR_BKP
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
+ * @{
+ */
+#define RTC_FORMAT_BIN 0x00000000u
+#define RTC_FORMAT_BCD 0x00000001u
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
+ * @{
+ */
+
+/* Coded in BCD format */
+#define RTC_MONTH_JANUARY ((uint8_t)0x01U)
+#define RTC_MONTH_FEBRUARY ((uint8_t)0x02U)
+#define RTC_MONTH_MARCH ((uint8_t)0x03U)
+#define RTC_MONTH_APRIL ((uint8_t)0x04U)
+#define RTC_MONTH_MAY ((uint8_t)0x05U)
+#define RTC_MONTH_JUNE ((uint8_t)0x06U)
+#define RTC_MONTH_JULY ((uint8_t)0x07U)
+#define RTC_MONTH_AUGUST ((uint8_t)0x08U)
+#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09U)
+#define RTC_MONTH_OCTOBER ((uint8_t)0x10U)
+#define RTC_MONTH_NOVEMBER ((uint8_t)0x11U)
+#define RTC_MONTH_DECEMBER ((uint8_t)0x12U)
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
+ * @{
+ */
+#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01U)
+#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U)
+#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U)
+#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U)
+#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U)
+#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U)
+#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U)
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC AlarmDateWeekDay Definitions
+ * @{
+ */
+#define RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000u
+#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_AlarmMask_Definitions RTC AlarmMask Definitions
+ * @{
+ */
+#define RTC_ALARMMASK_NONE 0x00000000u
+#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
+#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
+#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
+#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
+#define RTC_ALARMMASK_ALL (RTC_ALARMMASK_DATEWEEKDAY | RTC_ALARMMASK_HOURS | \
+ RTC_ALARMMASK_MINUTES | RTC_ALARMMASK_SECONDS)
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
+ * @{
+ */
+#define RTC_ALARM_A RTC_CR_ALRAE
+#define RTC_ALARM_B RTC_CR_ALRBE
+
+/**
+ * @}
+ */
+/** @defgroup RTC_ALARM_Flag_AutoClear_Definitions RTC Alarms Flag Auto Clear Definitions
+ * @{
+ */
+#define ALARM_FLAG_AUTOCLR_ENABLE 0x00000001u
+#define ALARM_FLAG_AUTOCLR_DISABLE 0x00000000u
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
+ * @{
+ */
+#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000u /*!< All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm */
+#define RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0 /*!< SS[14:1] not used in Alarmcomparison. Only SS[0] is compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1 /*!< SS[14:2] not used in Alarm comparison. Only SS[1:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_3 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1) /*!< SS[14:3] not used in Alarm comparison. Only SS[2:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2 /*!< SS[14:4] not used in Alarm comparison. Only SS[3:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_5 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:5] not used in Alarm comparison. Only SS[4:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_6 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:6] not used in Alarm comparison. Only SS[5:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_7 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:7] not used in Alarm comparison. Only SS[6:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3 /*!< SS[14:8] not used in Alarm comparison. Only SS[7:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_9 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:9] not used in Alarm comparison. Only SS[8:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_10 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:10] not used in Alarm comparison. Only SS[9:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_11 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:11] not used in Alarm comparison. Only SS[10:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_12 (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:12] not used in Alarm comparison.Only SS[11:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_13 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:13] not used in Alarm comparison. Only SS[12:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14] not used in Alarm comparison. Only SS[13:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS /*!< SS[14:0] are compared and must match to activate alarm. */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
+ * @{
+ */
+#define RTC_IT_TS RTC_CR_TSIE /*!< Enable Timestamp Interrupt */
+#define RTC_IT_WUT RTC_CR_WUTIE /*!< Enable Wakeup timer Interrupt */
+#define RTC_IT_SSRU RTC_CR_SSRUIE /*!< Enable SSR Underflow Interrupt */
+#define RTC_IT_ALRA RTC_CR_ALRAIE /*!< Enable Alarm A Interrupt */
+#define RTC_IT_ALRB RTC_CR_ALRBIE /*!< Enable Alarm B Interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Interruption_Mask RTC Interruptions Flag Mask
+ * @{
+ */
+#define RTC_FLAG_MASK 0x001Fu /*!< RTC flags mask */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Flags_Definitions RTC Flags Definitions
+ * Elements values convention: 000000XX000YYYYYb
+ * - YYYYY : Interrupt flag position in the XX register (5bits)
+ * - XX : Interrupt status register (2bits)
+ * - 01: ICSR register
+ * - 10: SR register
+ * @{
+ */
+#define RTC_FLAG_RECALPF (0x00000100U | RTC_ICSR_RECALPF_Pos) /*!< Recalibration pending Flag */
+#define RTC_FLAG_INITF (0x00000100U | RTC_ICSR_INITF_Pos) /*!< Initialization flag */
+#define RTC_FLAG_RSF (0x00000100U | RTC_ICSR_RSF_Pos) /*!< Registers synchronization flag */
+#define RTC_FLAG_INITS (0x00000100U | RTC_ICSR_INITS_Pos) /*!< Initialization status flag */
+#define RTC_FLAG_SHPF (0x00000100U | RTC_ICSR_SHPF_Pos) /*!< Shift operation pending flag */
+#define RTC_FLAG_WUTWF (0x00000100U | RTC_ICSR_WUTWF_Pos) /*!< Wakeup timer write flag */
+#define RTC_FLAG_SSRUF (0x00000200U | RTC_SR_SSRUF_Pos) /*!< Clear SSR underflow flag */
+#define RTC_FLAG_ITSF (0x00000200U | RTC_SR_ITSF_Pos) /*!< Clear Internal Time-stamp flag */
+#define RTC_FLAG_TSOVF (0x00000200U | RTC_SR_TSOVF_Pos) /*!< Clear Time-stamp overflow flag */
+#define RTC_FLAG_TSF (0x00000200U | RTC_SR_TSF_Pos) /*!< Clear Time-stamp flag */
+#define RTC_FLAG_WUTF (0x00000200U | RTC_SR_WUTF_Pos) /*!< Clear Wakeup timer flag */
+#define RTC_FLAG_ALRBF (0x00000200U | RTC_SR_ALRBF_Pos) /*!< Clear Alarm B flag */
+#define RTC_FLAG_ALRAF (0x00000200U | RTC_SR_ALRAF_Pos) /*!< Clear Alarm A flag */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Clear_Flags_Definitions RTC Clear Flags Definitions
+ * @{
+ */
+#define RTC_CLEAR_SSRUF RTC_SCR_CSSRUF /*!< Clear SSR underflow flag */
+#define RTC_CLEAR_ITSF RTC_SCR_CITSF /*!< Clear Internal Time-stamp flag */
+#define RTC_CLEAR_TSOVF RTC_SCR_CTSOVF /*!< Clear Time-stamp overflow flag */
+#define RTC_CLEAR_TSF RTC_SCR_CTSF /*!< Clear Time-stamp flag */
+#define RTC_CLEAR_WUTF RTC_SCR_CWUTF /*!< Clear Wakeup timer flag */
+#define RTC_CLEAR_ALRBF RTC_SCR_CALRBF /*!< Clear Alarm B flag */
+#define RTC_CLEAR_ALRAF RTC_SCR_CALRAF /*!< Clear Alarm A flag */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup RTC_Exported_Macros RTC Exported Macros
+ * @{
+ */
+
+/** @brief Reset RTC handle state
+ * @param __HANDLE__ RTC handle.
+ * @retval None
+ */
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\
+ (__HANDLE__)->State = HAL_RTC_STATE_RESET;\
+ (__HANDLE__)->MspInitCallback = NULL;\
+ (__HANDLE__)->MspDeInitCallback = NULL;\
+ }while(0)
+#else
+#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+
+/**
+ * @brief Disable the write protection for RTC registers.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \
+ do{ \
+ RTC->WPR = 0xCAU; \
+ RTC->WPR = 0x53U; \
+ } while(0U)
+
+/**
+ * @brief Enable the write protection for RTC registers.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \
+ do{ \
+ RTC->WPR = 0xFFU; \
+ } while(0U)
+
+/**
+ * @brief Add 1 hour (summer time change).
+ * @note This interface is deprecated.
+ * To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __BKP__ Backup
+ * This parameter can be:
+ * @arg @ref RTC_STOREOPERATION_RESET
+ * @arg @ref RTC_STOREOPERATION_SET
+ * @retval None
+ */
+#define __HAL_RTC_DAYLIGHT_SAVING_TIME_ADD1H(__HANDLE__, __BKP__) \
+ do { \
+ __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__); \
+ SET_BIT(RTC->CR, RTC_CR_ADD1H); \
+ MODIFY_REG(RTC->CR, RTC_CR_BKP , (__BKP__)); \
+ __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__); \
+ } while(0);
+
+/**
+ * @brief Subtract 1 hour (winter time change).
+ * @note This interface is deprecated.
+ * To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __BKP__ Backup
+ * This parameter can be:
+ * @arg @ref RTC_STOREOPERATION_RESET
+ * @arg @ref RTC_STOREOPERATION_SET
+ * @retval None
+ */
+#define __HAL_RTC_DAYLIGHT_SAVING_TIME_SUB1H(__HANDLE__, __BKP__) \
+ do { \
+ __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__); \
+ SET_BIT(RTC->CR, RTC_CR_SUB1H); \
+ MODIFY_REG(RTC->CR, RTC_CR_BKP , (__BKP__)); \
+ __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__); \
+ } while(0);
+
+/**
+ * @brief Enable the RTC ALARMA peripheral.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_ALRAE))
+
+/**
+ * @brief Disable the RTC ALARMA peripheral.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_ALRAE))
+
+/**
+ * @brief Enable the RTC ALARMB peripheral.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_ALRBE))
+
+/**
+ * @brief Disable the RTC ALARMB peripheral.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_ALRBE))
+
+/**
+ * @brief Enable the RTC Alarm interrupt.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg @ref RTC_IT_ALRA Alarm A interrupt
+ * @arg @ref RTC_IT_ALRB Alarm B interrupt
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the RTC Alarm interrupt.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg @ref RTC_IT_ALRA Alarm A interrupt
+ * @arg @ref RTC_IT_ALRB Alarm B interrupt
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified RTC Alarm interrupt has occurred or not.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
+ * This parameter can be:
+ * @arg @ref RTC_IT_ALRA Alarm A interrupt
+ * @arg @ref RTC_IT_ALRB Alarm B interrupt
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) ((((RTC->MISR)& ((__INTERRUPT__)>> 12U)) != 0U) \
+ ? 1UL : 0UL)
+
+/**
+ * @brief Check whether the specified RTC Alarm interrupt has been enabled or not.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
+ * This parameter can be:
+ * @arg @ref RTC_IT_ALRA Alarm A interrupt
+ * @arg @ref RTC_IT_ALRB Alarm B interrupt
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((RTC->CR) & (__INTERRUPT__)) != 0U) \
+ ? 1UL : 0UL)
+
+/**
+ * @brief Get the selected RTC Alarms flag status.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC Alarm Flag sources to check.
+ * This parameter can be:
+ * @arg @ref RTC_FLAG_ALRAF
+ * @arg @ref RTC_FLAG_ALRBF
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
+
+/**
+ * @brief Clear the RTC Alarms pending flags.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC Alarm Flag sources to clear.
+ * This parameter can be:
+ * @arg @ref RTC_FLAG_ALRAF
+ * @arg @ref RTC_FLAG_ALRBF
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == RTC_FLAG_ALRAF) \
+ ? ((RTC->SCR = (RTC_CLEAR_ALRAF))) :\
+ (RTC->SCR = (RTC_CLEAR_ALRBF)))
+
+/**
+ * @}
+ */
+
+/* Include RTC HAL Extended module */
+#include "stm32u5xx_hal_rtc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RTC_Exported_Functions RTC Exported Functions
+ * @{
+ */
+
+/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
+
+void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
+void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID,
+ pRTC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
+ * @{
+ */
+/* RTC Time and Date functions ************************************************/
+HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
+void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc);
+void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc);
+void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc);
+void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc);
+uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc);
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
+ * @{
+ */
+/* RTC Alarm functions ********************************************************/
+HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
+HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm,
+ uint32_t Format);
+void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc);
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions
+ * @{
+ */
+/* Peripheral State functions *************************************************/
+HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RTC_Private_Constants RTC Private Constants
+ * @{
+ */
+/* Masks Definition */
+#define RTC_TR_RESERVED_MASK (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | \
+ RTC_TR_MNT | RTC_TR_MNU| RTC_TR_ST | \
+ RTC_TR_SU)
+#define RTC_DR_RESERVED_MASK (RTC_DR_YT | RTC_DR_YU | RTC_DR_WDU | \
+ RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | \
+ RTC_DR_DU)
+#define RTC_INIT_MASK 0xFFFFFFFFu
+#define RTC_RSF_MASK (~(RTC_ICSR_INIT | RTC_ICSR_RSF))
+
+#define RTC_TIMEOUT_VALUE 1000u
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup RTC_Private_Macros RTC Private Macros
+ * @{
+ */
+
+/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
+ * @{
+ */
+#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
+ ((OUTPUT) == RTC_OUTPUT_ALARMA) || \
+ ((OUTPUT) == RTC_OUTPUT_ALARMB) || \
+ ((OUTPUT) == RTC_OUTPUT_WAKEUP) || \
+ ((OUTPUT) == RTC_OUTPUT_TAMPER))
+
+#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \
+ ((FORMAT) == RTC_HOURFORMAT_24))
+
+#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
+ ((POL) == RTC_OUTPUT_POLARITY_LOW))
+
+#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
+ ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
+
+#define IS_RTC_OUTPUT_PULLUP(TYPE) (((TYPE) == RTC_OUTPUT_PULLUP_NONE) || \
+ ((TYPE) == RTC_OUTPUT_PULLUP_ON))
+
+#define IS_RTC_OUTPUT_REMAP(REMAP) (((REMAP) == RTC_OUTPUT_REMAP_NONE) || \
+ ((REMAP) == RTC_OUTPUT_REMAP_POS1))
+
+#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || \
+ ((PM) == RTC_HOURFORMAT12_PM))
+
+#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
+ ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
+ ((SAVE) == RTC_DAYLIGHTSAVING_NONE))
+
+#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
+ ((OPERATION) == RTC_STOREOPERATION_SET))
+
+#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || \
+ ((FORMAT) == RTC_FORMAT_BCD))
+
+#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99u)
+
+#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1u) && ((MONTH) <= 12u))
+
+#define IS_RTC_DATE(DATE) (((DATE) >= 1u) && ((DATE) <= 31u))
+
+#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+
+#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >0u) && ((DATE) <= 31u))
+
+#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+
+#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
+ ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
+
+#define IS_RTC_ALARM_MASK(MASK) (((MASK) & ~(RTC_ALARMMASK_ALL)) == 0UL)
+
+#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || \
+ ((ALARM) == RTC_ALARM_B))
+
+#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS)
+
+#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == 0UL) || \
+ (((MASK) >= RTC_ALARMSUBSECONDMASK_SS14_1) && \
+ ((MASK) <= RTC_ALARMSUBSECONDMASK_NONE)))
+
+#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (RTC_PRER_PREDIV_A >> RTC_PRER_PREDIV_A_Pos))
+
+#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (RTC_PRER_PREDIV_S >> RTC_PRER_PREDIV_S_Pos))
+
+#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0u) && ((HOUR) <= 12u))
+
+#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23u)
+
+#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59u)
+
+#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59u)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions -------------------------------------------------------------*/
+/** @defgroup RTC_Private_Functions RTC Private Functions
+ * @{
+ */
+HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc);
+uint8_t RTC_ByteToBcd2(uint8_t Value);
+uint8_t RTC_Bcd2ToByte(uint8_t Value);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_RTC_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rtc_ex.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rtc_ex.h
new file mode 100644
index 00000000..c1837547
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rtc_ex.h
@@ -0,0 +1,1783 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_rtc_ex.h
+ * @author MCD Application Team
+ * @brief Header file of RTC HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_RTC_EX_H
+#define STM32U5xx_HAL_RTC_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup RTCEx RTCEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RTCEx_Exported_Types RTCEx Exported Types
+ * @{
+ */
+
+/** @defgroup RTCEx_Tamper_structure_definition RTCEx Tamper structure definition
+ * @{
+ */
+typedef struct
+{
+ uint32_t Tamper; /*!< Specifies the Tamper Pin.
+ This parameter can be a value of @ref RTCEx_Tamper_Pins */
+
+ uint32_t Trigger; /*!< Specifies the Tamper Trigger.
+ This parameter can be a value of @ref RTCEx_Tamper_Trigger */
+
+ uint32_t NoErase; /*!< Specifies the Tamper no erase mode.
+ This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp */
+
+ uint32_t MaskFlag; /*!< Specifies the Tamper Flag masking.
+ This parameter can be a value of @ref RTCEx_Tamper_MaskFlag */
+
+ uint32_t Filter; /*!< Specifies the TAMP Filter Tamper.
+ This parameter can be a value of @ref RTCEx_Tamper_Filter */
+
+ uint32_t SamplingFrequency; /*!< Specifies the sampling frequency.
+ This parameter can be a value of
+ @ref RTCEx_Tamper_Sampling_Frequencies */
+
+ uint32_t PrechargeDuration; /*!< Specifies the Precharge Duration .
+ This parameter can be a value of
+ @ref RTCEx_Tamper_Pin_Precharge_Duration */
+
+ uint32_t TamperPullUp; /*!< Specifies the Tamper PullUp .
+ This parameter can be a value of @ref RTCEx_Tamper_Pull_UP */
+
+ uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection.
+ This parameter can be a value of
+ @ref RTCEx_Tamper_TimeStampOnTamperDetection */
+} RTC_TamperTypeDef;
+/**
+ * @}
+ */
+
+
+/** @defgroup RTCEx_Active_Seed_Size Seed size Definitions
+ * @{
+ */
+#define RTC_ATAMP_SEED_NB_UINT32 4U
+/**
+ * @}
+ */
+
+
+/** @defgroup RTCEx_ActiveTamper_structures_definition RTCEx Active Tamper structures definitions
+ * @{
+ */
+typedef struct
+{
+ uint32_t Enable; /*!< Specifies the Tamper input is active.
+ This parameter can be a value of @ref RTCEx_ActiveTamper_Enable */
+
+ uint32_t Interrupt; /*!< Specifies the interrupt mode
+ This parameter can be a value of @ref RTCEx_ActiveTamper_Interrupt */
+
+ uint32_t Output; /*!< Specifies the TAMP output to be compared with.
+ The same output can be used for several tamper inputs.
+ This parameter can be a value of @ref RTCEx_ActiveTamper_Sel */
+
+ uint32_t NoErase; /*!< Specifies the Tamper no erase mode.
+ This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp */
+
+ uint32_t MaskFlag; /*!< Specifies the Tamper Flag masking.
+ This parameter can be a value of @ref RTCEx_Tamper_MaskFlag */
+
+} RTC_ATampInputTypeDef;
+
+
+typedef struct
+{
+ uint32_t ActiveFilter; /*!< Specifies the Active tamper filter enable.
+ This parameter can be a value of @ref RTCEx_ActiveTamper_Filter */
+
+ uint32_t ActiveAsyncPrescaler; /*!< Specifies the Active Tamper asynchronous Prescaler clock.
+ This parameter can be a value of
+ @ref RTCEx_ActiveTamper_Async_prescaler */
+
+ uint32_t TimeStampOnTamperDetection; /*!< Specifies the timeStamp on tamper detection.
+ This parameter can be a value of
+ @ref RTCEx_Tamper_TimeStampOnTamperDetection */
+
+ uint32_t ActiveOutputChangePeriod; /*!< Specifies the Active Tamper output change period .
+ This parameter can be a value from 0 to 7. */
+
+ uint32_t Seed[RTC_ATAMP_SEED_NB_UINT32];
+ /*!< Specifies the RNG Seed value.
+ This parameter is an array of value from 0 to 0xFFFFFFFF. */
+
+ RTC_ATampInputTypeDef TampInput[RTC_TAMP_NB];
+ /*!< Specifies configuration of all active tampers.
+ The index of TampInput[RTC_TAMP_NB] can be a value of RTCEx_ActiveTamper_Sel */
+} RTC_ActiveTampersTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Internal_Tamper_structure_definition RTCEx Internal Tamper structure definition
+ * @{
+ */
+typedef struct
+{
+ uint32_t IntTamper; /*!< Specifies the Internal Tamper Pin.
+ This parameter can be a value of @ref RTCEx_Internal_Tamper_Pins */
+
+ uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection.
+ This parameter can be a value of
+ @ref RTCEx_Tamper_TimeStampOnTamperDetection */
+
+ uint32_t NoErase; /*!< Specifies the internal Tamper no erase mode.
+ This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp */
+
+} RTC_InternalTamperTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Secure_State_structure_definition RTCEx Secure structure definition
+ * @{
+ */
+typedef struct
+{
+ uint32_t rtcSecureFull; /*!< Specifies If the RTC is fully secure or not
+ This parameter can be a value of @ref RTCEx_RTC_Secure_Full */
+
+ uint32_t rtcNonSecureFeatures; /*!< Specifies the non-secure features.
+ This parameter is only relevant if RTC is not fully secure
+ (rtcSecureFull == RTC_SECURE_FULL_NO).
+ This parameter can be a combination of
+ @ref RTCEx_RTC_NonSecure_Features. */
+
+ uint32_t tampSecureFull; /*!< Specifies If the TAMP is fully secure or not execpt monotonic counters
+ and BackUp registers.
+ This parameter can be a value of @ref RTCEx_TAMP_Secure_Full */
+
+ uint32_t backupRegisterStartZone2; /*!< Specifies the backup register start zone 2
+ Zone 1 : read secure write secure.
+ Zone 2 : read non-secure write secure.
+ This parameter can be RTC_BKP_DRx where x can be from 0 to 31 to specify
+ the register.
+ Warning : this parameter is shared with RTC_PrivilegeStateTypeDef. */
+
+ uint32_t backupRegisterStartZone3; /*!< Specifies the backup register start zone 3
+ Zone 3 : read non-secure write non-secure
+ This parameter can be RTC_BKP_DRx where x can be from 0 to 31 to
+ specify the register.
+ Warning : this parameter is shared with RTC_PrivilegeStateTypeDef. */
+
+ uint32_t MonotonicCounterSecure; /*!< Specifies If the monotonic counter is secure or not
+ This parameter can be a value of
+ @ref RTCEx_TAMP_Monotonic_Counter_Secure */
+} RTC_SecureStateTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Privilege_State_structure_definition RTCEx Privilege structure definition
+ * @{
+ */
+typedef struct
+{
+ uint32_t rtcPrivilegeFull; /*!< Specifies If the RTC is fully privileged or not.
+ This parameter can be a value of @ref RTCEx_RTC_Privilege_Full. */
+
+ uint32_t rtcPrivilegeFeatures; /*!< Specifies the privileged features.
+ This parameter is only relevant if RTC is not fully privileged
+ (rtcPrivilegeFull == RTC_PRIVILEGE_FULL_NO).
+ This parameter can be a combination of
+ @ref RTCEx_RTC_Privilege_Features. */
+
+ uint32_t tampPrivilegeFull; /*!< Specifies If the TAMP is fully privileged or not execpt monotonic
+ counters and BackUp registers.
+ This parameter can be a value of @ref RTCEx_TAMP_Privilege_Full. */
+
+ uint32_t backupRegisterPrivZone; /*!< Specifies backup register zone to be privileged.
+ This parameter can be a combination of
+ @ref RTCEx_Backup_Reg_Privilege_zone.
+ Warning : this parameter is writable in secure mode or if trustzone is
+ disabled. */
+
+ uint32_t backupRegisterStartZone2; /*!< Specifies the backup register start zone 2.
+ Zone 1 : read secure write secure.
+ Zone 2 : read non-secure write secure.
+ This parameter can be RTC_BKP_DRx where x can be from 0 to 31 to specify
+ the register .
+ Warning : this parameter is writable in secure mode or if trustzone is
+ disabled.
+ Warning : this parameter is shared with RTC_SecureStateTypeDef */
+
+ uint32_t backupRegisterStartZone3; /*!< Specifies the backup register start zone 3.
+ Zone 3 : read non-secure write non-secure.
+ This parameter can be RTC_BKP_DRx where x can be from 0 to 31 to specify
+ the register.
+ Warning : this parameter is writable in secure mode or if trustzone is
+ disabled.
+ Warning : this parameter is shared with RTC_SecureStateTypeDef. */
+
+ uint32_t MonotonicCounterPrivilege; /*!< Specifies If the monotonic counter is privileged or not
+ This parameter can be a value of
+ @ref RTCEx_TAMP_Monotonic_Counter_Privilege */
+} RTC_PrivilegeStateTypeDef;
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants
+ * @{
+ */
+
+/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTCEx Time Stamp Edges definition
+ * @{
+ */
+#define RTC_TIMESTAMPEDGE_RISING 0x00000000u
+#define RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_TimeStamp_Pin_Selections RTCEx TimeStamp Pin Selection
+ * @{
+ */
+#define RTC_TIMESTAMPPIN_DEFAULT 0x00000000u
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definitions
+ * @{
+ */
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 0x00000000u
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1)
+#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS RTC_CR_WUCKSEL_2
+#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2)
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth calib period Definitions
+ * @{
+ */
+#define RTC_SMOOTHCALIB_PERIOD_32SEC 0x00000000u /*!< If RTCCLK = 32768 Hz, Smooth calibration
+ period is 32s, else 2exp20 RTCCLK pulses */
+#define RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< If RTCCLK = 32768 Hz, Smooth calibration
+ period is 16s, else 2exp19 RTCCLK pulses */
+#define RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< If RTCCLK = 32768 Hz, Smooth calibration
+ period is 8s, else 2exp18 RTCCLK pulses */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTCEx Smooth calib Plus pulses Definitions
+ * @{
+ */
+#define RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP /*!< The number of RTCCLK pulses added
+ during a X -second window = Y - CALM[8:0]
+ with Y = 512, 256, 128 when X = 32, 16, 8 */
+#define RTC_SMOOTHCALIB_PLUSPULSES_RESET 0x00000000u /*!< The number of RTCCLK pulses subbstited
+ during a 32-second window = CALM[8:0] */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Smooth_calib_low_power_Definitions RTCEx Smooth calib Low Power Definitions
+ * @{
+ */
+#define RTC_LPCAL_SET RTC_CALR_LPCAL /*!< Calibration window is 220 ck_apre,
+ which is the required configuration for
+ ultra-low consumption mode. */
+#define RTC_LPCAL_RESET 0x00000000u /*!< Calibration window is 220 RTCCLK,
+ which is a high-consumption mode.
+ This mode should be set only when less
+ than 32s calibration window is required. */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output selection Definitions
+ * @{
+ */
+#define RTC_CALIBOUTPUT_512HZ 0x00000000u
+#define RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL
+
+/**
+ * @}
+ */
+
+
+/** @defgroup RTCEx_Add_1_Second_Parameter_Definition RTCEx Add 1 Second Parameter Definitions
+ * @{
+ */
+#define RTC_SHIFTADD1S_RESET 0x00000000u
+#define RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Pins RTCEx Tamper Pins Definition
+ * @{
+ */
+#define RTC_TAMPER_1 TAMP_CR1_TAMP1E
+#define RTC_TAMPER_2 TAMP_CR1_TAMP2E
+#if (RTC_TAMP_NB == 3)
+#define RTC_TAMPER_3 TAMP_CR1_TAMP3E
+#define RTC_TAMPER_ALL (RTC_TAMPER_1 | RTC_TAMPER_2 | RTC_TAMPER_3 )
+#elif (RTC_TAMP_NB == 8)
+#define RTC_TAMPER_3 TAMP_CR1_TAMP3E
+#define RTC_TAMPER_4 TAMP_CR1_TAMP4E
+#define RTC_TAMPER_5 TAMP_CR1_TAMP5E
+#define RTC_TAMPER_6 TAMP_CR1_TAMP6E
+#define RTC_TAMPER_7 TAMP_CR1_TAMP7E
+#define RTC_TAMPER_8 TAMP_CR1_TAMP8E
+#define RTC_TAMPER_ALL (RTC_TAMPER_1 | RTC_TAMPER_2 |\
+ RTC_TAMPER_3 | RTC_TAMPER_4 |\
+ RTC_TAMPER_5 | RTC_TAMPER_6 |\
+ RTC_TAMPER_7 | RTC_TAMPER_8 )
+#else
+#define RTC_TAMPER_ALL (RTC_TAMPER_1 | RTC_TAMPER_2)
+#endif /* RTC_TAMP_NB */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Internal_Tamper_Pins RTCEx Internal Tamper Pins Definition
+ * @{
+ */
+#define RTC_INT_TAMPER_1 TAMP_CR1_ITAMP1E
+#define RTC_INT_TAMPER_2 TAMP_CR1_ITAMP2E
+#define RTC_INT_TAMPER_3 TAMP_CR1_ITAMP3E
+#define RTC_INT_TAMPER_5 TAMP_CR1_ITAMP5E
+#define RTC_INT_TAMPER_6 TAMP_CR1_ITAMP6E
+#define RTC_INT_TAMPER_7 TAMP_CR1_ITAMP7E
+#define RTC_INT_TAMPER_8 TAMP_CR1_ITAMP8E
+#define RTC_INT_TAMPER_9 TAMP_CR1_ITAMP9E
+#define RTC_INT_TAMPER_11 TAMP_CR1_ITAMP11E
+#define RTC_INT_TAMPER_12 TAMP_CR1_ITAMP12E
+#define RTC_INT_TAMPER_13 TAMP_CR1_ITAMP13E
+#define RTC_INT_TAMPER_ALL (RTC_INT_TAMPER_1 | RTC_INT_TAMPER_2 |\
+ RTC_INT_TAMPER_3 | RTC_INT_TAMPER_5 |\
+ RTC_INT_TAMPER_6 | RTC_INT_TAMPER_7 |\
+ RTC_INT_TAMPER_8 | RTC_INT_TAMPER_9 |\
+ RTC_INT_TAMPER_11|RTC_INT_TAMPER_12|\
+ RTC_INT_TAMPER_13)
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Trigger RTCEx Tamper Trigger
+ * @{
+ */
+#define RTC_TAMPERTRIGGER_RISINGEDGE 0x00u /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */
+#define RTC_TAMPERTRIGGER_FALLINGEDGE 0x01u /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */
+#define RTC_TAMPERTRIGGER_LOWLEVEL 0x02u /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */
+#define RTC_TAMPERTRIGGER_HIGHLEVEL 0x03u /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_MaskFlag RTCEx Tamper MaskFlag
+ * @{
+ */
+#define RTC_TAMPERMASK_FLAG_DISABLE 0x00u
+#define RTC_TAMPERMASK_FLAG_ENABLE 0x01u
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_EraseBackUp RTCEx Tamper EraseBackUp
+ * @{
+ */
+#define RTC_TAMPER_ERASE_BACKUP_ENABLE 0x00u
+#define RTC_TAMPER_ERASE_BACKUP_DISABLE 0x01u
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Filter RTCEx Tamper Filter
+ * @{
+ */
+#define RTC_TAMPERFILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */
+#define RTC_TAMPERFILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0 /*!< Tamper is activated after 2
+ consecutive samples at the active level */
+#define RTC_TAMPERFILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1 /*!< Tamper is activated after 4
+ consecutive samples at the active level */
+#define RTC_TAMPERFILTER_8SAMPLE TAMP_FLTCR_TAMPFLT /*!< Tamper is activated after 8
+ consecutive samples at the active level */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Sampling_Frequencies RTCEx Tamper Sampling Frequencies
+ * @{
+ */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 TAMP_FLTCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 TAMP_FLTCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 TAMP_FLTCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 512 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1 | \
+ TAMP_FLTCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 256 */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration RTCEx Tamper Pin Precharge Duration
+ * @{
+ */
+#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */
+#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */
+#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */
+#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK (TAMP_FLTCR_TAMPPRCH_0 | TAMP_FLTCR_TAMPPRCH_1) /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Pull_UP RTCEx Tamper Pull UP
+ * @{
+ */
+#define RTC_TAMPER_PULLUP_ENABLE 0x00000000u /*!< Tamper pins are pre-charged before sampling */
+#define RTC_TAMPER_PULLUP_DISABLE TAMP_FLTCR_TAMPPUDIS /*!< Tamper pins pre-charge is disabled */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection RTCEx Tamper TimeStamp On Tamper Detection Definitions
+ * @{
+ */
+#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000u /*!< TimeStamp on Tamper Detection event is not saved */
+#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE RTC_CR_TAMPTS /*!< TimeStamp on Tamper Detection event saved */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Internal_Tamper_Interrupt RTCEx Internal Tamper Interrupt
+ * @{
+ */
+#define RTC_IT_TAMP_1 TAMP_IER_TAMP1IE /*!< Tamper 1 Interrupt */
+#define RTC_IT_TAMP_2 TAMP_IER_TAMP2IE /*!< Tamper 2 Interrupt */
+#define RTC_IT_TAMP_3 TAMP_IER_TAMP3IE /*!< Tamper 3 Interrupt */
+#define RTC_IT_TAMP_4 TAMP_IER_TAMP4IE /*!< Tamper 4 Interrupt */
+#define RTC_IT_TAMP_5 TAMP_IER_TAMP5IE /*!< Tamper 5 Interrupt */
+#define RTC_IT_TAMP_6 TAMP_IER_TAMP6IE /*!< Tamper 6 Interrupt */
+#define RTC_IT_TAMP_7 TAMP_IER_TAMP7IE /*!< Tamper 7 Interrupt */
+#define RTC_IT_TAMP_8 TAMP_IER_TAMP8IE /*!< Tamper 8 Interrupt */
+#define RTC_IT_TAMP_ALL (RTC_IT_TAMP_1 | RTC_IT_TAMP_2 |\
+ RTC_IT_TAMP_3 | RTC_IT_TAMP_4 |\
+ RTC_IT_TAMP_5 | RTC_IT_TAMP_6 |\
+ RTC_IT_TAMP_7 | RTC_IT_TAMP_8 )
+
+#define RTC_IT_INT_TAMP_1 TAMP_IER_ITAMP1IE /*!< Tamper 1 internal Interrupt */
+#define RTC_IT_INT_TAMP_2 TAMP_IER_ITAMP2IE /*!< Tamper 2 internal Interrupt */
+#define RTC_IT_INT_TAMP_3 TAMP_IER_ITAMP3IE /*!< Tamper 3 internal Interrupt */
+#define RTC_IT_INT_TAMP_5 TAMP_IER_ITAMP5IE /*!< Tamper 5 internal Interrupt */
+#define RTC_IT_INT_TAMP_6 TAMP_IER_ITAMP6IE /*!< Tamper 6 internal Interrupt */
+#define RTC_IT_INT_TAMP_7 TAMP_IER_ITAMP7IE /*!< Tamper 7 internal Interrupt */
+#define RTC_IT_INT_TAMP_8 TAMP_IER_ITAMP8IE /*!< Tamper 8 internal Interrupt */
+#define RTC_IT_INT_TAMP_9 TAMP_IER_ITAMP9IE /*!< Tamper 9 internal Interrupt */
+#define RTC_IT_INT_TAMP_11 TAMP_IER_ITAMP11IE /*!< Tamper 11 internal Interrupt */
+#define RTC_IT_INT_TAMP_12 TAMP_IER_ITAMP9IE /*!< Tamper 12 internal Interrupt */
+#define RTC_IT_INT_TAMP_13 TAMP_IER_ITAMP11IE /*!< Tamper 13 internal Interrupt */
+#define RTC_IT_INT_TAMP_ALL (RTC_IT_INT_TAMP_1 | RTC_IT_INT_TAMP_2 |\
+ RTC_IT_INT_TAMP_3 | RTC_IT_INT_TAMP_5 |\
+ RTC_IT_INT_TAMP_6 | RTC_IT_INT_TAMP_7 |\
+ RTC_IT_INT_TAMP_8 | RTC_IT_INT_TAMP_9 |\
+ RTC_IT_INT_TAMP_11| RTC_IT_INT_TAMP_12|\
+ RTC_IT_INT_TAMP_13)
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Flags RTCEx Flags
+ * @{
+ */
+#define RTC_FLAG_TAMP_1 TAMP_SR_TAMP1F
+#define RTC_FLAG_TAMP_2 TAMP_SR_TAMP2F
+#define RTC_FLAG_TAMP_3 TAMP_SR_TAMP3F
+#define RTC_FLAG_TAMP_4 TAMP_SR_TAMP4F
+#define RTC_FLAG_TAMP_5 TAMP_SR_TAMP5F
+#define RTC_FLAG_TAMP_6 TAMP_SR_TAMP6F
+#define RTC_FLAG_TAMP_7 TAMP_SR_TAMP7F
+#define RTC_FLAG_TAMP_8 TAMP_SR_TAMP8F
+#define RTC_FLAG_TAMP_ALL (RTC_FLAG_TAMP_1 | RTC_FLAG_TAMP_2 | RTC_FLAG_TAMP_3 |\
+ RTC_FLAG_TAMP_4 | RTC_FLAG_TAMP_5 | RTC_FLAG_TAMP_6 |\
+ RTC_FLAG_TAMP_7 | RTC_FLAG_TAMP_8)
+
+
+#define RTC_FLAG_INT_TAMP_1 TAMP_SR_ITAMP1F
+#define RTC_FLAG_INT_TAMP_2 TAMP_SR_ITAMP2F
+#define RTC_FLAG_INT_TAMP_3 TAMP_SR_ITAMP3F
+#define RTC_FLAG_INT_TAMP_5 TAMP_SR_ITAMP5F
+#define RTC_FLAG_INT_TAMP_6 TAMP_SR_ITAMP6F
+#define RTC_FLAG_INT_TAMP_7 TAMP_SR_ITAMP7F
+#define RTC_FLAG_INT_TAMP_8 TAMP_SR_ITAMP8F
+#define RTC_FLAG_INT_TAMP_9 TAMP_SR_ITAMP9F
+#define RTC_FLAG_INT_TAMP_11 TAMP_SR_ITAMP11F
+#define RTC_FLAG_INT_TAMP_12 TAMP_SR_ITAMP12F
+#define RTC_FLAG_INT_TAMP_13 TAMP_SR_ITAMP13F
+#define RTC_FLAG_INT_TAMP_ALL (RTC_FLAG_INT_TAMP_1 | RTC_FLAG_INT_TAMP2 |\
+ RTC_FLAG_INT_TAMP_3 | RTC_FLAG_INT_TAMP5 |\
+ RTC_FLAG_INT_TAMP_6 | RTC_FLAG_INT_TAMP7 |\
+ RTC_FLAG_INT_TAMP_8 | RTC_FLAG_INT_TAMP9 |\
+ RTC_FLAG_INT_TAMP_11|RTC_FLAG_INT_TAMP_12|\
+ RTC_FLAG_INT_TAMP_13)
+/**
+ * @}
+ */
+
+
+/** @defgroup RTCEx_ActiveTamper_Enable RTCEx_ActiveTamper_Enable Definitions
+ * @{
+ */
+#define RTC_ATAMP_ENABLE 1u
+#define RTC_ATAMP_DISABLE 0u
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_ActiveTamper_Interrupt RTCEx_ActiveTamper_Interrupt Definitions
+ * @{
+ */
+#define RTC_ATAMP_INTERRUPT_ENABLE 1u
+#define RTC_ATAMP_INTERRUPT_DISABLE 0u
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_ActiveTamper_Filter RTCEx_ActiveTamper_Filter Definitions
+ * @{
+ */
+#define RTC_ATAMP_FILTER_ENABLE TAMP_ATCR1_FLTEN
+#define RTC_ATAMP_FILTER_DISABLE 0u
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_ActiveTamper_Async_prescaler RTCEx Active_Tamper_Asynchronous_Prescaler clock Definitions
+ * @{
+ */
+#define RTC_ATAMP_ASYNCPRES_RTCCLK 0u /*!< RTCCLK */
+#define RTC_ATAMP_ASYNCPRES_RTCCLK_2 TAMP_ATCR1_ATCKSEL_0 /*!< RTCCLK/2 */
+#define RTC_ATAMP_ASYNCPRES_RTCCLK_4 TAMP_ATCR1_ATCKSEL_1 /*!< RTCCLK/4 */
+#define RTC_ATAMP_ASYNCPRES_RTCCLK_8 (TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/8 */
+#define RTC_ATAMP_ASYNCPRES_RTCCLK_16 TAMP_ATCR1_ATCKSEL_2 /*!< RTCCLK/16 */
+#define RTC_ATAMP_ASYNCPRES_RTCCLK_32 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/32 */
+#define RTC_ATAMP_ASYNCPRES_RTCCLK_64 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1) /*!< RTCCLK/64 */
+#define RTC_ATAMP_ASYNCPRES_RTCCLK_128 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/128 */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_ActiveTamper_Sel RTCEx Active Tamper selection Definition
+ * @{
+ */
+#define RTC_ATAMP_1 0u /*!< Tamper 1 */
+#define RTC_ATAMP_2 1u /*!< Tamper 2 */
+#define RTC_ATAMP_3 2u /*!< Tamper 3 */
+#define RTC_ATAMP_4 3u /*!< Tamper 4 */
+#define RTC_ATAMP_5 4u /*!< Tamper 5 */
+#define RTC_ATAMP_6 5u /*!< Tamper 6 */
+#define RTC_ATAMP_7 6u /*!< Tamper 7 */
+#define RTC_ATAMP_8 7u /*!< Tamper 8 */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_MonotonicCounter_Instance RTCEx Monotonic Counter Instance Definition
+ * @{
+ */
+#define RTC_MONOTONIC_COUNTER_1 0u /*!< Monotonic counter 1 */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Backup_Registers RTCEx Backup Registers Definition
+ * @{
+ */
+#define RTC_BKP_NUMBER RTC_BKP_NB
+#define RTC_BKP_DR0 0x00u
+#define RTC_BKP_DR1 0x01u
+#define RTC_BKP_DR2 0x02u
+#define RTC_BKP_DR3 0x03u
+#define RTC_BKP_DR4 0x04u
+#define RTC_BKP_DR5 0x05u
+#define RTC_BKP_DR6 0x06u
+#define RTC_BKP_DR7 0x07u
+#define RTC_BKP_DR8 0x08u
+#define RTC_BKP_DR9 0x09u
+#define RTC_BKP_DR10 0x0Au
+#define RTC_BKP_DR11 0x0Bu
+#define RTC_BKP_DR12 0x0Cu
+#define RTC_BKP_DR13 0x0Du
+#define RTC_BKP_DR14 0x0Eu
+#define RTC_BKP_DR15 0x0Fu
+#define RTC_BKP_DR16 0x10u
+#define RTC_BKP_DR17 0x11u
+#define RTC_BKP_DR18 0x12u
+#define RTC_BKP_DR19 0x13u
+#define RTC_BKP_DR20 0x14u
+#define RTC_BKP_DR21 0x15u
+#define RTC_BKP_DR22 0x16u
+#define RTC_BKP_DR23 0x17u
+#define RTC_BKP_DR24 0x18u
+#define RTC_BKP_DR25 0x19u
+#define RTC_BKP_DR26 0x1Au
+#define RTC_BKP_DR27 0x1Bu
+#define RTC_BKP_DR28 0x1Cu
+#define RTC_BKP_DR29 0x1Du
+#define RTC_BKP_DR30 0x1Eu
+#define RTC_BKP_DR31 0x1Fu
+/**
+ * @}
+ */
+/** @defgroup RTCEx_Binary_Mode RTC Binary Mode (32-bit free-running counter configuration).
+ * Warning : It Should not be confused with the Binary format @ref RTC_Input_parameter_format_definitions.
+ * @{
+ */
+#define RTC_BINARY_NONE 0x00000000u /*!< Free running BCD calendar mode (Binary mode disabled). */
+#define RTC_BINARY_ONLY RTC_ICSR_BIN_0 /*!< Free running Binary mode (BCD mode disabled) */
+#define RTC_BINARY_MIX RTC_ICSR_BIN_1 /*!< Free running BCD calendar and Binary modes */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Binary_mix_BCDU If Binary mode is RTC_BINARY_MIX, the BCD calendar second is incremented
+ * using the SSR Least Significant Bits.
+ * @{
+ */
+#define RTC_BINARY_MIX_BCDU_0 0x00000000u /*!< The 1s BCD calendar increment is generated each time SS[7:0] = 0 */
+#define RTC_BINARY_MIX_BCDU_1 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[8:0] = 0 */
+#define RTC_BINARY_MIX_BCDU_2 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[9:0] = 0 */
+#define RTC_BINARY_MIX_BCDU_3 (0x3UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[10:0] = 0 */
+#define RTC_BINARY_MIX_BCDU_4 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[11:0] = 0 */
+#define RTC_BINARY_MIX_BCDU_5 (0x5UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[12:0] = 0 */
+#define RTC_BINARY_MIX_BCDU_6 (0x6UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[13:0] = 0 */
+#define RTC_BINARY_MIX_BCDU_7 (0x7UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[14:0] = 0 */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Alarm_Sub_Seconds_binary_Masks_Definitions RTC Alarm Sub Seconds with binary mode Masks Definitions
+ * @{
+ */
+#define RTC_ALARMSUBSECONDBINMASK_ALL 0x00000000u /*!< All Alarm SS fields are masked.There is no comparison on sub seconds for Alarm */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_1 (1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:1] are don't care in Alarm comparison. Only SS[0] is compared. */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_2 (2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:2] are don't care in Alarm comparison. Only SS[1:0] are compared */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_3 (3UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:3] are don't care in Alarm comparison. Only SS[2:0] are compared */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_4 (4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:4] are don't care in Alarm comparison. Only SS[3:0] are compared */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_5 (5UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:5] are don't care in Alarm comparison. Only SS[4:0] are compared */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_6 (6UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:6] are don't care in Alarm comparison. Only SS[5:0] are compared */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_7 (7UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:7] are don't care in Alarm comparison. Only SS[6:0] are compared */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_8 (8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:8] are don't care in Alarm comparison. Only SS[7:0] are compared */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_9 (9UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:9] are don't care in Alarm comparison. Only SS[8:0] are compared */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_10 (10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:10] are don't care in Alarm comparison. Only SS[9:0] are compared */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_11 (11UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:11] are don't care in Alarm comparison. Only SS[10:0] are compared */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_12 (12UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:12] are don't care in Alarm comparison.Only SS[11:0] are compared */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_13 (13UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:13] are don't care in Alarm comparison. Only SS[12:0] are compared */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_14 (14UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:14] are don't care in Alarm comparison. Only SS[13:0] are compared */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_15 (15UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:15] are don't care in Alarm comparison. Only SS[14:0] are compared */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_16 (16UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:16] are don't care in Alarm comparison. Only SS[15:0] are compared */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_17 (17UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:17] are don't care in Alarm comparison. Only SS[16:0] are compared */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_18 (18UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:18] are don't care in Alarm comparison. Only SS[17:0] are compared */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_19 (19UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:19] are don't care in Alarm comparison. Only SS[18:0] are compared */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_20 (20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:20] are don't care in Alarm comparison. Only SS[19:0] are compared */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_21 (21UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:21] are don't care in Alarm comparison. Only SS[20:0] are compared */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_22 (22UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:22] are don't care in Alarm comparison. Only SS[21:0] are compared */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_23 (23UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:23] are don't care in Alarm comparison. Only SS[22:0] are compared */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_24 (24UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:24] are don't care in Alarm comparison. Only SS[23:0] are compared */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_25 (25UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:25] are don't care in Alarm comparison. Only SS[24:0] are compared */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_26 (26UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:26] are don't care in Alarm comparison. Only SS[25:0] are compared */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_27 (27UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:27] are don't care in Alarm comparison. Only SS[26:0] are compared */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_28 (28UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:28] are don't care in Alarm comparison. Only SS[27:0] are compared */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_29 (29UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:29] are don't care in Alarm comparison. Only SS[28:0] are compared */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_30 (30UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:30] are don't care in Alarm comparison. Only SS[29:0] are compared */
+#define RTC_ALARMSUBSECONDBINMASK_SS31 (31UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31] is don't care in Alarm comparison. Only SS[30:0] are compared */
+#define RTC_ALARMSUBSECONDBINMASK_NONE (32UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:0] are compared and must match to activate alarm. */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Alarm_Sub_Seconds_binary_Clear_Definitions RTC Alarm Sub Seconds
+ * with binary mode auto clear Definitions
+ * @{
+ */
+#define RTC_ALARMSUBSECONDBIN_AUTOCLR_NO 0UL /*!< The synchronous Binary counter (SS[31:0] in RTC_SSR) is free-running. */
+#define RTC_ALARMSUBSECONDBIN_AUTOCLR_YES RTC_ALRMASSR_SSCLR /*!< The synchronous Binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRMABINR -> SS[31:0] value and is automatically reloaded with 0xFFFF FFFF whenreaching RTC_ALRMABINR -> SS[31:0]. */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_RTC_Secure_Full RTCEx Secure Definition
+ * @{
+ */
+#define RTC_SECURE_FULL_YES RTC_SECCFGR_SEC /*!< RTC full secure */
+#define RTC_SECURE_FULL_NO 0u /*!< RTC is not full secure, features can be unsecure. See RTC_LL_EC_UNSECURE_RTC_FEATURE */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_RTC_NonSecure_Features RTCEx Secure Features Definition
+ * @{
+ */
+
+#define RTC_NONSECURE_FEATURE_NONE (RTC_SECCFGR_INITSEC | RTC_SECCFGR_CALSEC | \
+ RTC_SECCFGR_TSSEC | RTC_SECCFGR_WUTSEC | \
+ RTC_SECCFGR_ALRASEC | RTC_SECCFGR_ALRBSEC)
+#define RTC_NONSECURE_FEATURE_INIT ~RTC_SECCFGR_INITSEC /*!< Initialization */
+#define RTC_NONSECURE_FEATURE_CAL ~RTC_SECCFGR_CALSEC /*!< Calibration */
+#define RTC_NONSECURE_FEATURE_TS ~RTC_SECCFGR_TSSEC /*!< Time stamp */
+#define RTC_NONSECURE_FEATURE_WUT ~RTC_SECCFGR_WUTSEC /*!< Wake up timer */
+#define RTC_NONSECURE_FEATURE_ALRA ~RTC_SECCFGR_ALRASEC /*!< Alarm A */
+#define RTC_NONSECURE_FEATURE_ALRB ~RTC_SECCFGR_ALRBSEC /*!< Alarm B */
+#define RTC_NONSECURE_FEATURE_ALL 0u
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_TAMP_Secure_Full RTCEx TAMP Secure Definition
+ * @{
+ */
+#define TAMP_SECURE_FULL_YES TAMP_SECCFGR_TAMPSEC /*!< TAMPER full secure */
+#define TAMP_SECURE_FULL_NO 0u /*!< TAMPER is not secure */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_TAMP_Monotonic_Counter_Secure RTCEx TAMP Monotonic Counter Secure Definition
+ * @{
+ */
+#define TAMP_MONOTONIC_CNT_SECURE_YES TAMP_SECCFGR_CNT1SEC /*!< TAMPER Monotonic Counter secure */
+#define TAMP_MONOTONIC_CNT_SECURE_NO 0u /*!< TAMPER Monotonic Counter is not secure */
+/**
+ * @}
+ */
+/** @defgroup RTCEx_RTC_Privilege_Full RTCEx Privilege Full Definition
+ * @{
+ */
+#define RTC_PRIVILEGE_FULL_YES RTC_PRIVCFGR_PRIV
+#define RTC_PRIVILEGE_FULL_NO 0u
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_RTC_Privilege_Features RTCEx Privilege Features Definition
+ * @{
+ */
+#define RTC_PRIVILEGE_FEATURE_NONE 0u
+#define RTC_PRIVILEGE_FEATURE_INIT RTC_PRIVCFGR_INITPRIV /*!< Initialization */
+#define RTC_PRIVILEGE_FEATURE_CAL RTC_PRIVCFGR_CALPRIV /*!< Calibration */
+#define RTC_PRIVILEGE_FEATURE_TS RTC_PRIVCFGR_TSPRIV /*!< Time stamp */
+#define RTC_PRIVILEGE_FEATURE_WUT RTC_PRIVCFGR_WUTPRIV /*!< Wake up timer */
+#define RTC_PRIVILEGE_FEATURE_ALRA RTC_PRIVCFGR_ALRAPRIV /*!< Alarm A */
+#define RTC_PRIVILEGE_FEATURE_ALRB RTC_PRIVCFGR_ALRBPRIV /*!< Alarm B */
+#define RTC_PRIVILEGE_FEATURE_ALL (RTC_PRIVCFGR_INITPRIV | RTC_PRIVCFGR_CALPRIV | \
+ RTC_PRIVCFGR_TSPRIV | RTC_PRIVCFGR_WUTPRIV | \
+ RTC_PRIVCFGR_ALRAPRIV | RTC_PRIVCFGR_ALRBPRIV)
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_TAMP_Privilege_Full RTCEx TAMP security Definition
+ * @{
+ */
+#define TAMP_PRIVILEGE_FULL_YES TAMP_PRIVCFGR_TAMPPRIV
+#define TAMP_PRIVILEGE_FULL_NO 0u
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_TAMP_Secret_Device_Conf_Erase RTCEx TAMP Secret Device Conf Erase Definition
+ * @{
+ */
+#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_ERCFGR0
+#define TAMP_SECRETDEVICE_ERASE_DISABLE 0u
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_TAMP_Monotonic_Counter_Privilege RTCEx TAMP Monotonic Counter Privilege Definition
+ * @{
+ */
+#define TAMP_MONOTONIC_CNT_PRIVILEGE_YES TAMP_PRIVCFGR_CNT1PRIV
+#define TAMP_MONOTONIC_CNT_PRIVILEGE_NO 0u
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Backup_Reg_Privilege_zone RTCEx Privilege Backup register privilege zone Definition
+ * @{
+ */
+#define RTC_PRIVILEGE_BKUP_ZONE_NONE 0u
+#define RTC_PRIVILEGE_BKUP_ZONE_1 TAMP_PRIVCFGR_BKPRWPRIV
+#define RTC_PRIVILEGE_BKUP_ZONE_2 TAMP_PRIVCFGR_BKPWPRIV
+#define RTC_PRIVILEGE_BKUP_ZONE_ALL (RTC_PRIVILEGE_BKUP_ZONE_1 | RTC_PRIVILEGE_BKUP_ZONE_2)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros
+ * @{
+ */
+
+/** @brief Clear the specified RTC pending flag.
+ * @param __HANDLE__ specifies the RTC Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg @ref RTC_CLEAR_ITSF Clear Internal Time-stamp flag
+ * @arg @ref RTC_CLEAR_TSOVF Clear Time-stamp overflow flag
+ * @arg @ref RTC_CLEAR_TSF Clear Time-stamp flag
+ * @arg @ref RTC_CLEAR_WUTF Clear Wakeup timer flag
+ * @arg @ref RTC_CLEAR_ALRBF Clear Alarm B flag
+ * @arg @ref RTC_CLEAR_ALRAF Clear Alarm A flag
+ * @retval None
+ */
+#define __HAL_RTC_CLEAR_FLAG(__HANDLE__, __FLAG__) (RTC->SCR = (__FLAG__))
+
+/** @brief Check whether the specified RTC flag is set or not.
+ * @param __HANDLE__ specifies the RTC Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg @ref RTC_FLAG_RECALPF Recalibration pending Flag
+ * @arg @ref RTC_FLAG_INITF Initialization flag
+ * @arg @ref RTC_FLAG_RSF Registers synchronization flag
+ * @arg @ref RTC_FLAG_INITS Initialization status flag
+ * @arg @ref RTC_FLAG_SHPF Shift operation pending flag
+ * @arg @ref RTC_FLAG_WUTWF Wakeup timer write flag
+ * @arg @ref RTC_FLAG_ALRAF Alarm A write flag
+ * @arg @ref RTC_FLAG_ALRBF Alarm B write flag
+ * @arg @ref RTC_FLAG_ITSF Internal Time-stamp flag
+ * @arg @ref RTC_FLAG_TSOVF Time-stamp overflow flag
+ * @arg @ref RTC_FLAG_TSF Time-stamp flag
+ * @arg @ref RTC_FLAG_WUTF Wakeup timer flag
+ * @arg @ref RTC_FLAG_ALRBF Alarm B flag
+ * @arg @ref RTC_FLAG_ALRAF Alarm A flag
+ * @retval None
+ */
+#define __HAL_RTC_GET_FLAG(__HANDLE__, __FLAG__) (((((__FLAG__)) >> 8U) == 1U) ? (RTC->ICSR &\
+ (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK))) : \
+ (RTC->SR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK))))
+
+/* ---------------------------------WAKEUPTIMER---------------------------------*/
+/** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer
+ * @{
+ */
+/**
+ * @brief Enable the RTC WakeUp Timer peripheral.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_WUTE))
+
+/**
+ * @brief Disable the RTC WakeUp Timer peripheral.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_WUTE))
+
+/**
+ * @brief Enable the RTC WakeUpTimer interrupt.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled.
+ * This parameter can be:
+ * @arg @ref RTC_IT_WUT WakeUpTimer interrupt
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the RTC WakeUpTimer interrupt.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be disabled.
+ * This parameter can be:
+ * @arg @ref RTC_IT_WUT WakeUpTimer interrupt
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(__INTERRUPT__))
+
+
+/**
+ * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt to check.
+ * This parameter can be:
+ * @arg @ref RTC_IT_WUT WakeUpTimer interrupt
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) ((((RTC->MISR) & ((__INTERRUPT__)>> 12U)) !=\
+ 0UL) ? 1UL : 0UL)
+/**
+ * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check.
+ * This parameter can be:
+ * @arg @ref RTC_IT_WUT WakeUpTimer interrupt
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((RTC->CR) & (__INTERRUPT__)) != \
+ 0UL) ? 1UL : 0UL)
+
+/**
+ * @brief Get the selected RTC WakeUpTimers flag status.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC WakeUpTimer Flag is pending or not.
+ * This parameter can be:
+ * @arg @ref RTC_FLAG_WUTF
+ * @arg @ref RTC_FLAG_WUTWF
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
+
+/**
+ * @brief Clear the RTC Wake Up timers pending flags.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC WakeUpTimer Flag to clear.
+ * This parameter can be:
+ * @arg @ref RTC_FLAG_WUTF
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_WUTF))
+/**
+ * @}
+ */
+/* ---------------------------------TIMESTAMP---------------------------------*/
+/** @defgroup RTCEx_Timestamp RTC Timestamp
+ * @{
+ */
+/**
+ * @brief Enable the RTC TimeStamp peripheral.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_TSE))
+
+/**
+ * @brief Disable the RTC TimeStamp peripheral.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_TSE))
+
+/**
+ * @brief Enable the RTC TimeStamp interrupt.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be enabled.
+ * This parameter can be:
+ * @arg @ref RTC_IT_TS TimeStamp interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the RTC TimeStamp interrupt.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be disabled.
+ * This parameter can be:
+ * @arg @ref RTC_IT_TS TimeStamp interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt to check.
+ * This parameter can be:
+ * @arg @ref RTC_IT_TS TimeStamp interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) ((((RTC->MISR) & ((__INTERRUPT__)>> 12U)) != \
+ 0U) ? 1UL : 0UL)
+/**
+ * @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check.
+ * This parameter can be:
+ * @arg @ref RTC_IT_TS TimeStamp interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((RTC->CR) & (__INTERRUPT__)) != 0U) ?\
+ 1UL : 0UL)
+
+/**
+ * @brief Get the selected RTC TimeStamps flag status.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC TimeStamp Flag is pending or not.
+ * This parameter can be:
+ * @arg @ref RTC_FLAG_TSF
+ * @arg @ref RTC_FLAG_TSOVF
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__),(__FLAG__)))
+
+/**
+ * @brief Clear the RTC Time Stamps pending flags.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC TimeStamp Flag to clear.
+ * This parameter can be:
+ * @arg @ref RTC_FLAG_TSF
+ * @arg @ref RTC_FLAG_TSOVF
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == RTC_FLAG_TSF) ? \
+ (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_TSF)) : \
+ (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_TSOVF)))
+
+/**
+ * @brief Enable the RTC internal TimeStamp peripheral.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_ITSE))
+
+/**
+ * @brief Disable the RTC internal TimeStamp peripheral.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_ITSE))
+
+/**
+ * @brief Get the selected RTC Internal Time Stamps flag status.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC Internal Time Stamp Flag is pending or not.
+ * This parameter can be:
+ * @arg @ref RTC_FLAG_ITSF
+ * @retval None
+ */
+#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__),\
+ (__FLAG__)))
+
+/**
+ * @brief Clear the RTC Internal Time Stamps pending flags.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC Internal Time Stamp Flag source to clear.
+ * This parameter can be:
+ * @arg @ref RTC_FLAG_ITSF
+ * @retval None
+ */
+#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__),\
+ RTC_CLEAR_ITSF))
+
+/**
+ * @brief Enable the RTC TimeStamp on Tamper detection.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPTS_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_TAMPTS))
+
+/**
+ * @brief Disable the RTC TimeStamp on Tamper detection.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPTS_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_TAMPTS))
+
+/**
+ * @brief Enable the RTC Tamper detection output.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPOE_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_TAMPOE))
+
+/**
+ * @brief Disable the RTC Tamper detection output.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPOE_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_TAMPOE))
+
+
+/**
+ * @}
+ */
+
+/* ------------------------------Calibration----------------------------------*/
+/** @defgroup RTCEx_Calibration RTC Calibration
+ * @{
+ */
+
+/**
+ * @brief Enable the RTC calibration output.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_COE))
+
+/**
+ * @brief Disable the calibration output.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_COE))
+
+
+/**
+ * @brief Enable the clock reference detection.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_REFCKON))
+
+/**
+ * @brief Disable the clock reference detection.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_REFCKON))
+
+
+/**
+ * @brief Get the selected RTC shift operations flag status.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC shift operation Flag is pending or not.
+ * This parameter can be:
+ * @arg @ref RTC_FLAG_SHPF
+ * @retval None
+ */
+#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
+/**
+ * @}
+ */
+
+/* ------------------------------Tamper----------------------------------*/
+/** @defgroup RTCEx_Tamper RTCEx tamper
+ * @{
+ */
+/**
+ * @brief Enable the TAMP Tamper input detection.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __TAMPER__ specifies the RTC Tamper source to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_TAMPER_ALL: All tampers
+ * @arg RTC_TAMPER_1: Tamper1
+ * @arg RTC_TAMPER_2: Tamper2
+ * @arg RTC_TAMPER_3: Tamper3
+ * @arg RTC_TAMPER_4: Tamper4
+ * @arg RTC_TAMPER_5: Tamper5
+ * @arg RTC_TAMPER_6: Tamper6
+ * @arg RTC_TAMPER_7: Tamper7
+ * @arg RTC_TAMPER_8: Tamper8
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_ENABLE(__HANDLE__, __TAMPER__) (TAMP->CR1 |= (__TAMPER__))
+
+/**
+ * @brief Disable the TAMP Tamper input detection.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __TAMPER__ specifies the RTC Tamper sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_TAMPER_ALL: All tampers
+ * @arg RTC_TAMPER_1: Tamper1
+ * @arg RTC_TAMPER_2: Tamper2
+ * @arg RTC_TAMPER_3: Tamper3
+ * @arg RTC_TAMPER_4: Tamper4
+ * @arg RTC_TAMPER_5: Tamper5
+ * @arg RTC_TAMPER_6: Tamper6
+ * @arg RTC_TAMPER_7: Tamper7
+ * @arg RTC_TAMPER_8: Tamper8
+ */
+#define __HAL_RTC_TAMPER_DISABLE(__HANDLE__, __TAMPER__) (TAMP->CR1 &= ~(__TAMPER__))
+
+/**************************************************************************************************/
+/**
+ * @brief Enable the TAMP Tamper interrupt.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_TAMP_ALL: All tampers interrupts
+ * @arg RTC_IT_TAMP_1: Tamper1 interrupt
+ * @arg RTC_IT_TAMP_2: Tamper2 interrupt
+ * @arg RTC_IT_TAMP_3: Tamper3 interrupt
+ * @arg RTC_IT_TAMP_4: Tamper4 interrupt
+ * @arg RTC_IT_TAMP_5: Tamper5 interrupt
+ * @arg RTC_IT_TAMP_6: Tamper6 interrupt
+ * @arg RTC_IT_TAMP_7: Tamper7 interrupt
+ * @arg RTC_IT_TAMP_8: Tamper8 interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) (TAMP->IER |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the TAMP Tamper interrupt.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_TAMP_ALL: All tampers interrupts
+ * @arg RTC_IT_TAMP_1: Tamper1 interrupt
+ * @arg RTC_IT_TAMP_2: Tamper2 interrupt
+ * @arg RTC_IT_TAMP_3: Tamper3 interrupt
+ * @arg RTC_IT_TAMP_4: Tamper4 interrupt
+ * @arg RTC_IT_TAMP_5: Tamper5 interrupt
+ * @arg RTC_IT_TAMP_6: Tamper6 interrupt
+ * @arg RTC_IT_TAMP_7: Tamper7 interrupt
+ * @arg RTC_IT_TAMP_8: Tamper8 interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) (TAMP->IER &= ~(__INTERRUPT__))
+
+/**************************************************************************************************/
+/**
+ * @brief Check whether the specified RTC Tamper interrupt has occurred or not.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC Tamper interrupt to check.
+ * This parameter can be:
+ * @arg RTC_IT_TAMP_ALL: All tampers interrupts
+ * @arg RTC_IT_TAMP_1: Tamper1 interrupt
+ * @arg RTC_IT_TAMP_2: Tamper2 interrupt
+ * @arg RTC_IT_TAMP_3: Tamper3 interrupt
+ * @arg RTC_IT_TAMP_4: Tamper4 interrupt
+ * @arg RTC_IT_TAMP_5: Tamper5 interrupt
+ * @arg RTC_IT_TAMP_6: Tamper6 interrupt
+ * @arg RTC_IT_TAMP_7: Tamper7 interrupt
+ * @arg RTC_IT_TAMP_8: Tamper8 interrupt
+ * @arg RTC_IT_INT_TAMP_ALL: All Internal Tamper interrupts
+ * @arg RTC_IT_INT_TAMP_1: Internal Tamper1 interrupt
+ * @arg RTC_IT_INT_TAMP_2: Internal Tamper2 interrupt
+ * @arg RTC_IT_INT_TAMP_3: Internal Tamper3 interrupt
+ * @arg RTC_IT_INT_TAMP_5: Internal Tamper5 interrupt
+ * @arg RTC_IT_INT_TAMP_6: Internal Tamper6 interrupt
+ * @arg RTC_IT_INT_TAMP_7: Internal Tamper7 interrupt
+ * @arg RTC_IT_INT_TAMP_8: Internal Tamper8 interrupt
+ * @arg RTC_IT_INT_TAMP_9: Internal Tamper9 interrupt
+ * @arg RTC_IT_INT_TAMP_11: Internal Tamper11 interrupt
+ * @arg RTC_IT_INT_TAMP_12: Internal Tamper12 interrupt
+ * @arg RTC_IT_INT_TAMP_13: Internal Tamper13 interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) ((((TAMP->MISR) & (__INTERRUPT__)) != 0U) ? 1UL : 0UL)
+
+/**
+ * @brief Check whether the specified RTC Tamper interrupt has been enabled or not.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC Tamper interrupt source to check.
+ * This parameter can be:
+ * @arg RTC_IT_TAMP_ALL: All tampers interrupts
+ * @arg RTC_IT_TAMP_1: Tamper1 interrupt
+ * @arg RTC_IT_TAMP_2: Tamper2 interrupt
+ * @arg RTC_IT_TAMP_3: Tamper3 interrupt
+ * @arg RTC_IT_TAMP_4: Tamper4 interrupt
+ * @arg RTC_IT_TAMP_5: Tamper5 interrupt
+ * @arg RTC_IT_TAMP_6: Tamper6 interrupt
+ * @arg RTC_IT_TAMP_7: Tamper7 interrupt
+ * @arg RTC_IT_TAMP_8: Tamper8 interrupt
+ * @arg RTC_IT_INT_TAMP_ALL: All internal tampers interrupts
+ * @arg RTC_IT_INT_TAMP_1: Internal Tamper1 interrupt
+ * @arg RTC_IT_INT_TAMP_2: Internal Tamper2 interrupt
+ * @arg RTC_IT_INT_TAMP_3: Internal Tamper3 interrupt
+ * @arg RTC_IT_INT_TAMP_5: Internal Tamper5 interrupt
+ * @arg RTC_IT_INT_TAMP_6: Internal Tamper6 interrupt
+ * @arg RTC_IT_INT_TAMP_7: Internal Tamper7 interrupt
+ * @arg RTC_IT_INT_TAMP_8: Internal Tamper8 interrupt
+ * @arg RTC_IT_INT_TAMP_9: Internal Tamper9 interrupt
+ * @arg RTC_IT_INT_TAMP_11: Internal Tamper11 interrupt
+ * @arg RTC_IT_INT_TAMP_12: Internal Tamper12 interrupt
+ * @arg RTC_IT_INT_TAMP_13: Internal Tamper13 interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((TAMP->IER) & (__INTERRUPT__)) != \
+ 0U) ? 1UL : 0UL)
+
+/**
+ * @brief Get the selected RTC Tampers flag status.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC Tamper Flag is pending or not.
+ * This parameter can be:
+ * @arg RTC_FLAG_TAMP_ALL: All tampers flag
+ * @arg RTC_FLAG_TAMP_1: Tamper1 flag
+ * @arg RTC_FLAG_TAMP_2: Tamper2 flag
+ * @arg RTC_FLAG_TAMP_3: Tamper3 flag
+ * @arg RTC_FLAG_TAMP_4: Tamper4 flag
+ * @arg RTC_FLAG_TAMP_5: Tamper5 flag
+ * @arg RTC_FLAG_TAMP_6: Tamper6 flag
+ * @arg RTC_FLAG_TAMP_7: Tamper7 flag
+ * @arg RTC_FLAG_TAMP_8: Tamper8 flag
+ * @arg RTC_FLAG_INT_TAMP_1: Internal Tamper1 flag
+ * @arg RTC_FLAG_INT_TAMP_2: Internal Tamper2 flag
+ * @arg RTC_FLAG_INT_TAMP_3: Internal Tamper3 flag
+ * @arg RTC_FLAG_INT_TAMP_5: Internal Tamper5 flag
+ * @arg RTC_FLAG_INT_TAMP_6: Internal Tamper6 flag
+ * @arg RTC_FLAG_INT_TAMP_7: Internal Tamper7 flag
+ * @arg RTC_FLAG_INT_TAMP_8: Internal Tamper8 flag
+ * @arg RTC_FLAG_INT_TAMP_9: Internal Tamper9 flag
+ * @arg RTC_FLAG_INT_TAMP_11: Internal Tamper11 flag
+ * @arg RTC_FLAG_INT_TAMP_12: Internal Tamper12 flag
+ * @arg RTC_FLAG_INT_TAMP_13: Internal Tamper13 flag
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((TAMP->SR) & (__FLAG__)) != 0U)
+
+/**
+ * @brief Clear the RTC Tamper's pending flags.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC Tamper Flag to clear.
+ * This parameter can be:
+ * @arg RTC_FLAG_TAMP_ALL: All tampers flag
+ * @arg RTC_FLAG_TAMP_1: Tamper1 flag
+ * @arg RTC_FLAG_TAMP_2: Tamper2 flag
+ * @arg RTC_FLAG_TAMP_3: Tamper3 flag
+ * @arg RTC_FLAG_TAMP_4: Tamper4 flag
+ * @arg RTC_FLAG_TAMP_5: Tamper5 flag
+ * @arg RTC_FLAG_TAMP_6: Tamper6 flag
+ * @arg RTC_FLAG_TAMP_7: Tamper7 flag
+ * @arg RTC_FLAG_TAMP_8: Tamper8 flag
+ * @arg RTC_FLAG_INT_TAMP_ALL: All Internal Tamper flags
+ * @arg RTC_FLAG_INT_TAMP_1: Internal Tamper1 flag
+ * @arg RTC_FLAG_INT_TAMP_2: Internal Tamper2 flag
+ * @arg RTC_FLAG_INT_TAMP_3: Internal Tamper3 flag
+ * @arg RTC_FLAG_INT_TAMP_5: Internal Tamper5 flag
+ * @arg RTC_FLAG_INT_TAMP_6: Internal Tamper6 flag
+ * @arg RTC_FLAG_INT_TAMP_7: Internal Tamper7 flag
+ * @arg RTC_FLAG_INT_TAMP_8: Internal Tamper8 flag
+ * @arg RTC_FLAG_INT_TAMP_9: Internal Tamper9 flag
+ * @arg RTC_FLAG_INT_TAMP_11: Internal Tamper11 flag
+ * @arg RTC_IT_INT_TAMP_12: Internal Tamper12 interrupt
+ * @arg RTC_IT_INT_TAMP_13: Internal Tamper13 interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((TAMP->SCR) = (__FLAG__))
+
+/**
+ * @}
+ */
+
+/* --------------------------------- SSR Underflow ---------------------------------*/
+/** @defgroup RTCEx_SSR_Underflow RTC SSR Underflow
+ * @{
+ */
+
+/**
+ * @brief Enable the RTC SSRU interrupt.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC SSRU interrupt sources to be enabled.
+ * This parameter can be:
+ * @arg @ref RTC_IT_SSRU SSRU interrupt
+ * @retval None
+ */
+#define __HAL_RTC_SSRU_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the RTC SSRU interrupt.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC SSRU interrupt sources to be disabled.
+ * This parameter can be:
+ * @arg @ref RTC_IT_SSRU SSRU interrupt
+ * @retval None
+ */
+#define __HAL_RTC_SSRU_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified RTC SSRU interrupt has occurred or not.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC SSRU interrupt to check.
+ * This parameter can be:
+ * @arg @ref RTC_IT_SSRU SSRU interrupt
+ * @retval None
+ */
+#define __HAL_RTC_SSRU_GET_IT(__HANDLE__, __INTERRUPT__) (((RTC->MISR) & ((__INTERRUPT__) >> 1) != 0U) \
+ ? 1U : 0U)
+/**
+ * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check.
+ * This parameter can be:
+ * @arg @ref RTC_IT_SSRU SSRU interrupt
+ * @retval None
+ */
+#define __HAL_RTC_SSRU_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((RTC->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
+
+/**
+ * @brief Get the selected RTC SSRU's flag status.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC SSRU Flag is pending or not.
+ * This parameter can be:
+ * @arg @ref RTC_FLAG_SSRUF
+ * @retval None
+ */
+#define __HAL_RTC_SSRU_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
+
+/**
+ * @brief Clear the RTC Wake Up timer's pending flags.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC SSRU Flag to clear.
+ * This parameter can be:
+ * @arg @ref RTC_FLAG_SSRUF
+ * @retval None
+ */
+#define __HAL_RTC_SSRU_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_SSRUF))
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
+ * @{
+ */
+
+/* RTC TimeStamp functions *****************************************/
+/** @defgroup RTCEx_Exported_Functions_Group1 Extended RTC TimeStamp functions
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge,
+ uint32_t RTC_TimeStampPin);
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge,
+ uint32_t RTC_TimeStampPin);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp,
+ RTC_DateTypeDef *sTimeStampDate, uint32_t Format);
+void HAL_RTCEx_TimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
+
+/**
+ * @}
+ */
+/* RTC Wake-up functions ******************************************************/
+/** @defgroup RTCEx_Exported_Functions_Group2 Extended RTC Wake-up functions
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock,
+ uint32_t WakeUpAutoClr);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
+uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/* Extended Control functions ************************************************/
+/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod,
+ uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue);
+HAL_StatusTypeDef HAL_RTCEx_SetLowPowerCalib(RTC_HandleTypeDef *hrtc, uint32_t LowPowerCalib);
+HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS);
+HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterIncrement(RTC_HandleTypeDef *hrtc, uint32_t Instance);
+HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(RTC_HandleTypeDef *hrtc, uint32_t Instance, uint32_t *Value);
+HAL_StatusTypeDef HAL_RTCEx_SetSSRU_IT(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateSSRU(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_SSRUIRQHandler(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_SSRUEventCallback(RTC_HandleTypeDef *hrtc);
+/**
+ * @}
+ */
+
+/* Extended RTC features functions *******************************************/
+/** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions
+ * @{
+ */
+
+void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Exported_Functions_Group5 Extended RTC Tamper functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper);
+HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, RTC_ActiveTampersTypeDef *sAllTamper);
+HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, uint32_t *pSeed);
+HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateActiveTampers(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_PollForTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t Tamper, uint32_t Timeout);
+HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper);
+HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(RTC_HandleTypeDef *hrtc, uint32_t IntTamper);
+HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t IntTamper, uint32_t Timeout);
+HAL_StatusTypeDef HAL_RTCEx_SetBoothardwareKey(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_GetActiveTampers(RTC_ActiveTampersTypeDef *sAllTamper);
+void HAL_RTCEx_GetInternalTampers(RTC_InternalTamperTypeDef *sIntTamper);
+void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_Tamper4EventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_Tamper5EventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_Tamper6EventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_Tamper7EventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_Tamper8EventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_InternalTamper1EventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_InternalTamper2EventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_InternalTamper3EventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_InternalTamper5EventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_InternalTamper6EventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_InternalTamper7EventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_InternalTamper8EventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_InternalTamper9EventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_InternalTamper11EventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_InternalTamper12EventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_InternalTamper13EventCallback(RTC_HandleTypeDef *hrtc);
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Exported_Functions_Group6 Extended RTC Backup register functions
+ * @{
+ */
+void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
+uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
+void HAL_RTCEx_BKUPErase(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_BKUPBlock_Enable(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_BKUPBlock_Disable(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_Erase_SecretDev_Conf(RTC_HandleTypeDef *hrtc, uint32_t SecretDeviceConf);
+uint32_t HAL_RTCEx_Get_Erase_SecretDev_Conf(void);
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Exported_Functions_Group7 Extended RTC secure functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_RTCEx_SecureModeGet(RTC_HandleTypeDef *hrtc, RTC_SecureStateTypeDef *secureState);
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+HAL_StatusTypeDef HAL_RTCEx_SecureModeSet(RTC_HandleTypeDef *hrtc, RTC_SecureStateTypeDef *secureState);
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Exported_Functions_Group8 Extended RTC privilege functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeSet(RTC_HandleTypeDef *hrtc, RTC_PrivilegeStateTypeDef *privilegeState);
+HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeGet(RTC_HandleTypeDef *hrtc, RTC_PrivilegeStateTypeDef *privilegeState);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup RTCEx_Private_Macros RTCEx Private Macros
+ * @{
+ */
+
+/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
+ * @{
+ */
+#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
+ ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
+
+
+#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
+
+
+
+#define IS_RTC_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
+ ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
+
+#define IS_RTC_TAMPER_TAMPERDETECTIONOUTPUT(MODE) (((MODE) == RTC_TAMPERDETECTIONOUTPUT_ENABLE) || \
+ ((MODE) == RTC_TAMPERDETECTIONOUTPUT_DISABLE))
+
+#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
+
+#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= RTC_WUTR_WUT)
+
+#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
+ ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
+ ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))
+
+#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
+ ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
+
+#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= RTC_CALR_CALM)
+
+#define IS_RTC_LOW_POWER_CALIB(LPCAL) (((LPCAL) == RTC_LPCAL_SET) || \
+ ((LPCAL) == RTC_LPCAL_RESET))
+
+
+#define IS_RTC_TAMPER(__TAMPER__) ((((__TAMPER__) & RTC_TAMPER_ALL) != 0x00U) && \
+ (((__TAMPER__) & ~RTC_TAMPER_ALL) == 0x00U))
+
+#define IS_RTC_INTERNAL_TAMPER(__INT_TAMPER__) ((((__INT_TAMPER__) & RTC_INT_TAMPER_ALL) != 0x00U) && \
+ (((__INT_TAMPER__) & ~RTC_INT_TAMPER_ALL) == 0x00U))
+
+#define IS_RTC_TAMPER_TRIGGER(__TRIGGER__) (((__TRIGGER__) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
+ ((__TRIGGER__) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
+ ((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
+ ((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL))
+
+#define IS_RTC_TAMPER_ERASE_MODE(__MODE__) (((__MODE__) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \
+ ((__MODE__) == RTC_TAMPER_ERASE_BACKUP_DISABLE))
+
+#define IS_RTC_TAMPER_MASKFLAG_STATE(__STATE__) (((__STATE__) == RTC_TAMPERMASK_FLAG_ENABLE) || \
+ ((__STATE__) == RTC_TAMPERMASK_FLAG_DISABLE))
+
+#define IS_RTC_TAMPER_FILTER(__FILTER__) (((__FILTER__) == RTC_TAMPERFILTER_DISABLE) || \
+ ((__FILTER__) == RTC_TAMPERFILTER_2SAMPLE) || \
+ ((__FILTER__) == RTC_TAMPERFILTER_4SAMPLE) || \
+ ((__FILTER__) == RTC_TAMPERFILTER_8SAMPLE))
+
+#define IS_RTC_TAMPER_SAMPLING_FREQ(__FREQ__) (((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
+ ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
+ ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
+ ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
+ ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
+ ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
+ ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \
+ ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
+
+#define IS_RTC_TAMPER_PRECHARGE_DURATION(__DURATION__) (((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
+ ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
+ ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
+ ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
+
+#define IS_RTC_TAMPER_PULLUP_STATE(__STATE__) (((__STATE__) == RTC_TAMPER_PULLUP_ENABLE) || \
+ ((__STATE__) == RTC_TAMPER_PULLUP_DISABLE))
+
+#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE)\
+ ||((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
+
+#define IS_RTC_BKP(__BKP__) ((__BKP__) < RTC_BKP_NUMBER)
+
+#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \
+ ((SEL) == RTC_SHIFTADD1S_SET))
+
+#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= RTC_SHIFTR_SUBFS)
+
+#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
+ ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))
+
+#define IS_RTC_SECURE_FULL(__STATE__) (((__STATE__) == RTC_SECURE_FULL_YES) || \
+ ((__STATE__) == RTC_SECURE_FULL_NO))
+
+#define IS_RTC_NONSECURE_FEATURES(__FEATURES__) (((__FEATURES__) & ~RTC_NONSECURE_FEATURE_NONE) == 0u)
+
+#define IS_TAMP_SECURE_FULL(__STATE__) (((__STATE__) == TAMP_SECURE_FULL_YES) || \
+ ((__STATE__) == TAMP_SECURE_FULL_NO))
+
+#define IS_TAMP_MONOTONIC_CNT_SECURE(__STATE__) (((__STATE__) == TAMP_MONOTONIC_CNT_SECURE_YES) || \
+ ((__STATE__) == TAMP_MONOTONIC_CNT_SECURE_NO))
+
+#define IS_RTC_PRIVILEGE_FULL(__STATE__) (((__STATE__) == RTC_PRIVILEGE_FULL_YES) || \
+ ((__STATE__) == RTC_PRIVILEGE_FULL_NO))
+
+#define IS_RTC_PRIVILEGE_FEATURES(__FEATURES__) (((__FEATURES__) & ~RTC_PRIVILEGE_FEATURE_ALL) == 0u)
+
+#define IS_TAMP_PRIVILEGE_FULL(__STATE__) (((__STATE__) == TAMP_PRIVILEGE_FULL_YES) || \
+ ((__STATE__) == TAMP_PRIVILEGE_FULL_NO))
+
+#define IS_TAMP_MONOTONIC_CNT_PRIVILEGE(__STATE__) (((__STATE__) == TAMP_MONOTONIC_CNT_PRIVILEGE_YES) || \
+ ((__STATE__) == TAMP_MONOTONIC_CNT_PRIVILEGE_NO))
+
+#define IS_RTC_PRIVILEGE_BKUP_ZONE(__ZONES__) (((__ZONES__) & ~RTC_PRIVILEGE_BKUP_ZONE_ALL) == 0u)
+
+#define IS_RTC_BINARY_MODE(MODE) (((MODE) == RTC_BINARY_NONE) || \
+ ((MODE) == RTC_BINARY_ONLY) || \
+ ((MODE) == RTC_BINARY_MIX ))
+
+#define IS_RTC_BINARY_MIX_BCDU(BDCU) (((BDCU) == RTC_BINARY_MIX_BCDU_0) || \
+ ((BDCU) == RTC_BINARY_MIX_BCDU_1) || \
+ ((BDCU) == RTC_BINARY_MIX_BCDU_2) || \
+ ((BDCU) == RTC_BINARY_MIX_BCDU_3) || \
+ ((BDCU) == RTC_BINARY_MIX_BCDU_4) || \
+ ((BDCU) == RTC_BINARY_MIX_BCDU_5) || \
+ ((BDCU) == RTC_BINARY_MIX_BCDU_6) || \
+ ((BDCU) == RTC_BINARY_MIX_BCDU_7))
+
+#define IS_RTC_ALARM_SUB_SECOND_BINARY_MASK(MASK) (((MASK) == 0u) || \
+ (((MASK) >= RTC_ALARMSUBSECONDBINMASK_SS31_1) &&\
+ ((MASK) <= RTC_ALARMSUBSECONDBINMASK_NONE)))
+
+#define IS_RTC_ALARMSUBSECONDBIN_AUTOCLR(SEL) (((SEL) == RTC_ALARMSUBSECONDBIN_AUTOCLR_NO) || \
+ ((SEL) == RTC_ALARMSUBSECONDBIN_AUTOCLR_YES))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_RTC_EX_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sai.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sai.h
new file mode 100644
index 00000000..69a799d7
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sai.h
@@ -0,0 +1,968 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_sai.h
+ * @author MCD Application Team
+ * @brief Header file of SAI HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_SAI_H
+#define STM32U5xx_HAL_SAI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SAI
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SAI_Exported_Types SAI Exported Types
+ * @{
+ */
+
+/** @defgroup SAI_PDM_Structure_definition SAI PDM Structure definition
+ * @brief SAI PDM Init structure definition
+ * @{
+ */
+typedef struct
+{
+ FunctionalState Activation; /*!< Enable/disable PDM interface */
+ uint32_t MicPairsNbr; /*!< Specifies the number of microphone pairs used.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 3. */
+ uint32_t ClockEnable; /*!< Specifies which clock must be enabled.
+ This parameter can be a values combination of @ref SAI_PDM_ClockEnable */
+} SAI_PdmInitTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Init_Structure_definition SAI Init Structure definition
+ * @brief SAI Init Structure definition
+ * @{
+ */
+typedef struct
+{
+ uint32_t AudioMode; /*!< Specifies the SAI Block audio Mode.
+ This parameter can be a value of @ref SAI_Block_Mode */
+
+ uint32_t Synchro; /*!< Specifies SAI Block synchronization
+ This parameter can be a value of @ref SAI_Block_Synchronization */
+
+ uint32_t SynchroExt; /*!< Specifies SAI external output synchronization, this setup is common
+ for BlockA and BlockB
+ This parameter can be a value of @ref SAI_Block_SyncExt
+ @note If both audio blocks of same SAI are used, this parameter has
+ to be set to the same value for each audio block */
+
+ uint32_t MckOutput; /*!< Specifies whether master clock output will be generated or not.
+ This parameter can be a value of @ref SAI_Block_MckOutput */
+
+ uint32_t OutputDrive; /*!< Specifies when SAI Block outputs are driven.
+ This parameter can be a value of @ref SAI_Block_Output_Drive
+ @note This value has to be set before enabling the audio block
+ but after the audio block configuration. */
+
+ uint32_t NoDivider; /*!< Specifies whether master clock will be divided or not.
+ This parameter can be a value of @ref SAI_Block_NoDivider
+ @note If bit NODIV in the SAI_xCR1 register is cleared, the frame length
+ should be aligned to a number equal to a power of 2, from 8 to 256.
+ If bit NODIV in the SAI_xCR1 register is set, the frame length can
+ take any of the values from 8 to 256. */
+
+ uint32_t FIFOThreshold; /*!< Specifies SAI Block FIFO threshold.
+ This parameter can be a value of @ref SAI_Block_Fifo_Threshold */
+
+ uint32_t AudioFrequency; /*!< Specifies the audio frequency sampling.
+ This parameter can be a value of @ref SAI_Audio_Frequency */
+
+ uint32_t Mckdiv; /*!< Specifies the master clock divider.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 63.
+ @note This parameter is used only if AudioFrequency is set to
+ SAI_AUDIO_FREQUENCY_MCKDIV otherwise it is internally computed. */
+
+ uint32_t MckOverSampling; /*!< Specifies the master clock oversampling.
+ This parameter can be a value of @ref SAI_Block_Mck_OverSampling */
+
+ uint32_t MonoStereoMode; /*!< Specifies if the mono or stereo mode is selected.
+ This parameter can be a value of @ref SAI_Mono_Stereo_Mode */
+
+ uint32_t CompandingMode; /*!< Specifies the companding mode type.
+ This parameter can be a value of @ref SAI_Block_Companding_Mode */
+
+ uint32_t TriState; /*!< Specifies the companding mode type.
+ This parameter can be a value of @ref SAI_TRIState_Management */
+
+ SAI_PdmInitTypeDef PdmInit; /*!< Specifies the PDM configuration. */
+
+ /* This part of the structure is automatically filled if your are using the high level initialisation
+ function HAL_SAI_InitProtocol */
+
+ uint32_t Protocol; /*!< Specifies the SAI Block protocol.
+ This parameter can be a value of @ref SAI_Block_Protocol */
+
+ uint32_t DataSize; /*!< Specifies the SAI Block data size.
+ This parameter can be a value of @ref SAI_Block_Data_Size */
+
+ uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
+ This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission */
+
+ uint32_t ClockStrobing; /*!< Specifies the SAI Block clock strobing edge sensitivity.
+ This parameter can be a value of @ref SAI_Block_Clock_Strobing */
+} SAI_InitTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_SAI_STATE_RESET = 0x00U, /*!< SAI not yet initialized or disabled */
+ HAL_SAI_STATE_READY = 0x01U, /*!< SAI initialized and ready for use */
+ HAL_SAI_STATE_BUSY = 0x02U, /*!< SAI internal process is ongoing */
+ HAL_SAI_STATE_BUSY_TX = 0x12U, /*!< Data transmission process is ongoing */
+ HAL_SAI_STATE_BUSY_RX = 0x22U, /*!< Data reception process is ongoing */
+} HAL_SAI_StateTypeDef;
+
+/**
+ * @brief SAI Callback prototype
+ */
+typedef void (*SAIcallback)(void);
+
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition
+ * @brief SAI Frame Init structure definition
+ * @note For SPDIF and AC97 protocol, these parameters are not used (set by hardware).
+ * @{
+ */
+typedef struct
+{
+
+ uint32_t FrameLength; /*!< Specifies the Frame length, the number of SCK clocks for each audio frame.
+ This parameter must be a number between Min_Data = 8 and Max_Data = 256.
+ @note If master clock MCLK_x pin is declared as an output, the frame length
+ should be aligned to a number equal to power of 2 in order to keep
+ in an audio frame, an integer number of MCLK pulses by bit Clock. */
+
+ uint32_t ActiveFrameLength; /*!< Specifies the Frame synchronization active level length.
+ This Parameter specifies the length in number of bit clock (SCK + 1)
+ of the active level of FS signal in audio frame.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
+
+ uint32_t FSDefinition; /*!< Specifies the Frame synchronization definition.
+ This parameter can be a value of @ref SAI_Block_FS_Definition */
+
+ uint32_t FSPolarity; /*!< Specifies the Frame synchronization Polarity.
+ This parameter can be a value of @ref SAI_Block_FS_Polarity */
+
+ uint32_t FSOffset; /*!< Specifies the Frame synchronization Offset.
+ This parameter can be a value of @ref SAI_Block_FS_Offset */
+
+} SAI_FrameInitTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition
+ * @brief SAI Block Slot Init Structure definition
+ * @note For SPDIF protocol, these parameters are not used (set by hardware).
+ * @note For AC97 protocol, only SlotActive parameter is used (the others are set by hardware).
+ * @{
+ */
+typedef struct
+{
+ uint32_t FirstBitOffset; /*!< Specifies the position of first data transfer bit in the slot.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 24 */
+
+ uint32_t SlotSize; /*!< Specifies the Slot Size.
+ This parameter can be a value of @ref SAI_Block_Slot_Size */
+
+ uint32_t SlotNumber; /*!< Specifies the number of slot in the audio frame.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
+
+ uint32_t SlotActive; /*!< Specifies the slots in audio frame that will be activated.
+ This parameter can be a value of @ref SAI_Block_Slot_Active */
+} SAI_SlotInitTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Handle_Structure_definition SAI Handle Structure definition
+ * @brief SAI handle Structure definition
+ * @{
+ */
+typedef struct __SAI_HandleTypeDef
+{
+ SAI_Block_TypeDef *Instance; /*!< SAI Blockx registers base address */
+
+ SAI_InitTypeDef Init; /*!< SAI communication parameters */
+
+ SAI_FrameInitTypeDef FrameInit; /*!< SAI Frame configuration parameters */
+
+ SAI_SlotInitTypeDef SlotInit; /*!< SAI Slot configuration parameters */
+
+ uint8_t *pBuffPtr; /*!< Pointer to SAI transfer Buffer */
+
+ uint16_t XferSize; /*!< SAI transfer size */
+
+ uint16_t XferCount; /*!< SAI transfer counter */
+
+ DMA_HandleTypeDef *hdmatx; /*!< SAI Tx DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< SAI Rx DMA handle parameters */
+
+ SAIcallback mutecallback; /*!< SAI mute callback */
+
+ void (*InterruptServiceRoutine)(struct __SAI_HandleTypeDef *hsai); /* function pointer for IRQ handler */
+
+ HAL_LockTypeDef Lock; /*!< SAI locking object */
+
+ __IO HAL_SAI_StateTypeDef State; /*!< SAI communication state */
+
+ __IO uint32_t ErrorCode; /*!< SAI Error code */
+
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ void (*RxCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI receive complete callback */
+ void (*RxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI receive half complete callback */
+ void (*TxCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI transmit complete callback */
+ void (*TxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI transmit half complete callback */
+ void (*ErrorCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI error callback */
+ void (*MspInitCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI MSP init callback */
+ void (*MspDeInitCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI MSP de-init callback */
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+} SAI_HandleTypeDef;
+
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+/**
+ * @brief SAI callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_SAI_RX_COMPLETE_CB_ID = 0x00U, /*!< SAI receive complete callback ID */
+ HAL_SAI_RX_HALFCOMPLETE_CB_ID = 0x01U, /*!< SAI receive half complete callback ID */
+ HAL_SAI_TX_COMPLETE_CB_ID = 0x02U, /*!< SAI transmit complete callback ID */
+ HAL_SAI_TX_HALFCOMPLETE_CB_ID = 0x03U, /*!< SAI transmit half complete callback ID */
+ HAL_SAI_ERROR_CB_ID = 0x04U, /*!< SAI error callback ID */
+ HAL_SAI_MSPINIT_CB_ID = 0x05U, /*!< SAI MSP init callback ID */
+ HAL_SAI_MSPDEINIT_CB_ID = 0x06U /*!< SAI MSP de-init callback ID */
+} HAL_SAI_CallbackIDTypeDef;
+
+/**
+ * @brief SAI callback pointer definition
+ */
+typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SAI_Exported_Constants SAI Exported Constants
+ * @{
+ */
+
+/** @defgroup SAI_Error_Code SAI Error Code
+ * @{
+ */
+#define HAL_SAI_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_SAI_ERROR_OVR 0x00000001U /*!< Overrun Error */
+#define HAL_SAI_ERROR_UDR 0x00000002U /*!< Underrun error */
+#define HAL_SAI_ERROR_AFSDET 0x00000004U /*!< Anticipated Frame synchronisation detection */
+#define HAL_SAI_ERROR_LFSDET 0x00000008U /*!< Late Frame synchronisation detection */
+#define HAL_SAI_ERROR_CNREADY 0x00000010U /*!< codec not ready */
+#define HAL_SAI_ERROR_WCKCFG 0x00000020U /*!< Wrong clock configuration */
+#define HAL_SAI_ERROR_TIMEOUT 0x00000040U /*!< Timeout error */
+#define HAL_SAI_ERROR_DMA 0x00000080U /*!< DMA error */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+#define HAL_SAI_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid callback error */
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_SyncExt SAI External synchronisation
+ * @{
+ */
+#define SAI_SYNCEXT_DISABLE 0U
+#define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1U
+#define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2U
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_MckOutput SAI Block Master Clock Output
+ * @{
+ */
+#define SAI_MCK_OUTPUT_DISABLE 0x00000000U
+#define SAI_MCK_OUTPUT_ENABLE SAI_xCR1_MCKEN
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Protocol SAI Supported protocol
+ * @{
+ */
+#define SAI_I2S_STANDARD 0U
+#define SAI_I2S_MSBJUSTIFIED 1U
+#define SAI_I2S_LSBJUSTIFIED 2U
+#define SAI_PCM_LONG 3U
+#define SAI_PCM_SHORT 4U
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Protocol_DataSize SAI protocol data size
+ * @{
+ */
+#define SAI_PROTOCOL_DATASIZE_16BIT 0U
+#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1U
+#define SAI_PROTOCOL_DATASIZE_24BIT 2U
+#define SAI_PROTOCOL_DATASIZE_32BIT 3U
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Audio_Frequency SAI Audio Frequency
+ * @{
+ */
+#define SAI_AUDIO_FREQUENCY_192K 192000U
+#define SAI_AUDIO_FREQUENCY_96K 96000U
+#define SAI_AUDIO_FREQUENCY_48K 48000U
+#define SAI_AUDIO_FREQUENCY_44K 44100U
+#define SAI_AUDIO_FREQUENCY_32K 32000U
+#define SAI_AUDIO_FREQUENCY_22K 22050U
+#define SAI_AUDIO_FREQUENCY_16K 16000U
+#define SAI_AUDIO_FREQUENCY_11K 11025U
+#define SAI_AUDIO_FREQUENCY_8K 8000U
+#define SAI_AUDIO_FREQUENCY_MCKDIV 0U
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Mck_OverSampling SAI Block Master Clock OverSampling
+ * @{
+ */
+#define SAI_MCK_OVERSAMPLING_DISABLE 0x00000000U
+#define SAI_MCK_OVERSAMPLING_ENABLE SAI_xCR1_OSR
+/**
+ * @}
+ */
+
+/** @defgroup SAI_PDM_ClockEnable SAI PDM Clock Enable
+ * @{
+ */
+#define SAI_PDM_CLOCK1_ENABLE SAI_PDMCR_CKEN1
+#define SAI_PDM_CLOCK2_ENABLE SAI_PDMCR_CKEN2
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Mode SAI Block Mode
+ * @{
+ */
+#define SAI_MODEMASTER_TX 0x00000000U
+#define SAI_MODEMASTER_RX SAI_xCR1_MODE_0
+#define SAI_MODESLAVE_TX SAI_xCR1_MODE_1
+#define SAI_MODESLAVE_RX (SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0)
+
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Protocol SAI Block Protocol
+ * @{
+ */
+#define SAI_FREE_PROTOCOL 0x00000000U
+#define SAI_SPDIF_PROTOCOL SAI_xCR1_PRTCFG_0
+#define SAI_AC97_PROTOCOL SAI_xCR1_PRTCFG_1
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Data_Size SAI Block Data Size
+ * @{
+ */
+#define SAI_DATASIZE_8 SAI_xCR1_DS_1
+#define SAI_DATASIZE_10 (SAI_xCR1_DS_1 | SAI_xCR1_DS_0)
+#define SAI_DATASIZE_16 SAI_xCR1_DS_2
+#define SAI_DATASIZE_20 (SAI_xCR1_DS_2 | SAI_xCR1_DS_0)
+#define SAI_DATASIZE_24 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1)
+#define SAI_DATASIZE_32 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0)
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission
+ * @{
+ */
+#define SAI_FIRSTBIT_MSB 0x00000000U
+#define SAI_FIRSTBIT_LSB SAI_xCR1_LSBFIRST
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Clock_Strobing SAI Block Clock Strobing
+ * @{
+ */
+#define SAI_CLOCKSTROBING_FALLINGEDGE 0U
+#define SAI_CLOCKSTROBING_RISINGEDGE 1U
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Synchronization SAI Block Synchronization
+ * @{
+ */
+#define SAI_ASYNCHRONOUS 0U /*!< Asynchronous */
+#define SAI_SYNCHRONOUS 1U /*!< Synchronous with other block of same SAI */
+#define SAI_SYNCHRONOUS_EXT_SAI1 2U /*!< Synchronous with other SAI, SAI1 */
+#define SAI_SYNCHRONOUS_EXT_SAI2 3U /*!< Synchronous with other SAI, SAI2 */
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Output_Drive SAI Block Output Drive
+ * @{
+ */
+#define SAI_OUTPUTDRIVE_DISABLE 0x00000000U
+#define SAI_OUTPUTDRIVE_ENABLE SAI_xCR1_OUTDRIV
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_NoDivider SAI Block NoDivider
+ * @{
+ */
+#define SAI_MASTERDIVIDER_ENABLE 0x00000000U
+#define SAI_MASTERDIVIDER_DISABLE SAI_xCR1_NODIV
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_FS_Definition SAI Block FS Definition
+ * @{
+ */
+#define SAI_FS_STARTFRAME 0x00000000U
+#define SAI_FS_CHANNEL_IDENTIFICATION SAI_xFRCR_FSDEF
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_FS_Polarity SAI Block FS Polarity
+ * @{
+ */
+#define SAI_FS_ACTIVE_LOW 0x00000000U
+#define SAI_FS_ACTIVE_HIGH SAI_xFRCR_FSPOL
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_FS_Offset SAI Block FS Offset
+ * @{
+ */
+#define SAI_FS_FIRSTBIT 0x00000000U
+#define SAI_FS_BEFOREFIRSTBIT SAI_xFRCR_FSOFF
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Slot_Size SAI Block Slot Size
+ * @{
+ */
+#define SAI_SLOTSIZE_DATASIZE 0x00000000U
+#define SAI_SLOTSIZE_16B SAI_xSLOTR_SLOTSZ_0
+#define SAI_SLOTSIZE_32B SAI_xSLOTR_SLOTSZ_1
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Slot_Active SAI Block Slot Active
+ * @{
+ */
+#define SAI_SLOT_NOTACTIVE 0x00000000U
+#define SAI_SLOTACTIVE_0 0x00000001U
+#define SAI_SLOTACTIVE_1 0x00000002U
+#define SAI_SLOTACTIVE_2 0x00000004U
+#define SAI_SLOTACTIVE_3 0x00000008U
+#define SAI_SLOTACTIVE_4 0x00000010U
+#define SAI_SLOTACTIVE_5 0x00000020U
+#define SAI_SLOTACTIVE_6 0x00000040U
+#define SAI_SLOTACTIVE_7 0x00000080U
+#define SAI_SLOTACTIVE_8 0x00000100U
+#define SAI_SLOTACTIVE_9 0x00000200U
+#define SAI_SLOTACTIVE_10 0x00000400U
+#define SAI_SLOTACTIVE_11 0x00000800U
+#define SAI_SLOTACTIVE_12 0x00001000U
+#define SAI_SLOTACTIVE_13 0x00002000U
+#define SAI_SLOTACTIVE_14 0x00004000U
+#define SAI_SLOTACTIVE_15 0x00008000U
+#define SAI_SLOTACTIVE_ALL 0x0000FFFFU
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Mono_Stereo_Mode SAI Mono Stereo Mode
+ * @{
+ */
+#define SAI_STEREOMODE 0x00000000U
+#define SAI_MONOMODE SAI_xCR1_MONO
+/**
+ * @}
+ */
+
+/** @defgroup SAI_TRIState_Management SAI TRIState Management
+ * @{
+ */
+#define SAI_OUTPUT_NOTRELEASED 0x00000000U
+#define SAI_OUTPUT_RELEASED SAI_xCR2_TRIS
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold
+ * @{
+ */
+#define SAI_FIFOTHRESHOLD_EMPTY 0x00000000U
+#define SAI_FIFOTHRESHOLD_1QF SAI_xCR2_FTH_0
+#define SAI_FIFOTHRESHOLD_HF SAI_xCR2_FTH_1
+#define SAI_FIFOTHRESHOLD_3QF (SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0)
+#define SAI_FIFOTHRESHOLD_FULL SAI_xCR2_FTH_2
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Companding_Mode SAI Block Companding Mode
+ * @{
+ */
+#define SAI_NOCOMPANDING 0x00000000U
+#define SAI_ULAW_1CPL_COMPANDING SAI_xCR2_COMP_1
+#define SAI_ALAW_1CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0)
+#define SAI_ULAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_CPL)
+#define SAI_ALAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL)
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Mute_Value SAI Block Mute Value
+ * @{
+ */
+#define SAI_ZERO_VALUE 0x00000000U
+#define SAI_LAST_SENT_VALUE SAI_xCR2_MUTEVAL
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Interrupts_Definition SAI Block Interrupts Definition
+ * @{
+ */
+#define SAI_IT_OVRUDR SAI_xIMR_OVRUDRIE
+#define SAI_IT_MUTEDET SAI_xIMR_MUTEDETIE
+#define SAI_IT_WCKCFG SAI_xIMR_WCKCFGIE
+#define SAI_IT_FREQ SAI_xIMR_FREQIE
+#define SAI_IT_CNRDY SAI_xIMR_CNRDYIE
+#define SAI_IT_AFSDET SAI_xIMR_AFSDETIE
+#define SAI_IT_LFSDET SAI_xIMR_LFSDETIE
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Flags_Definition SAI Block Flags Definition
+ * @{
+ */
+#define SAI_FLAG_OVRUDR SAI_xSR_OVRUDR
+#define SAI_FLAG_MUTEDET SAI_xSR_MUTEDET
+#define SAI_FLAG_WCKCFG SAI_xSR_WCKCFG
+#define SAI_FLAG_FREQ SAI_xSR_FREQ
+#define SAI_FLAG_CNRDY SAI_xSR_CNRDY
+#define SAI_FLAG_AFSDET SAI_xSR_AFSDET
+#define SAI_FLAG_LFSDET SAI_xSR_LFSDET
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Fifo_Status_Level SAI Block Fifo Status Level
+ * @{
+ */
+#define SAI_FIFOSTATUS_EMPTY 0x00000000U
+#define SAI_FIFOSTATUS_LESS1QUARTERFULL 0x00010000U
+#define SAI_FIFOSTATUS_1QUARTERFULL 0x00020000U
+#define SAI_FIFOSTATUS_HALFFULL 0x00030000U
+#define SAI_FIFOSTATUS_3QUARTERFULL 0x00040000U
+#define SAI_FIFOSTATUS_FULL 0x00050000U
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SAI_Exported_Macros SAI Exported Macros
+ * @brief macros to handle interrupts and specific configurations
+ * @{
+ */
+
+/** @brief Reset SAI handle state.
+ * @param __HANDLE__ specifies the SAI Handle.
+ * @retval None
+ */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_SAI_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET)
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+
+/** @brief Enable the specified SAI interrupts.
+ * @param __HANDLE__ specifies the SAI Handle.
+ * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
+ * @arg SAI_IT_MUTEDET: Mute detection interrupt enable
+ * @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
+ * @arg SAI_IT_FREQ: FIFO request interrupt enable
+ * @arg SAI_IT_CNRDY: Codec not ready interrupt enable
+ * @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
+ * @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
+ * @retval None
+ */
+#define __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
+
+/** @brief Disable the specified SAI interrupts.
+ * @param __HANDLE__ specifies the SAI Handle.
+ * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
+ * @arg SAI_IT_MUTEDET: Mute detection interrupt enable
+ * @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
+ * @arg SAI_IT_FREQ: FIFO request interrupt enable
+ * @arg SAI_IT_CNRDY: Codec not ready interrupt enable
+ * @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
+ * @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
+ * @retval None
+ */
+#define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))
+
+/** @brief Check whether the specified SAI interrupt source is enabled or not.
+ * @param __HANDLE__ specifies the SAI Handle.
+ * @param __INTERRUPT__ specifies the SAI interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
+ * @arg SAI_IT_MUTEDET: Mute detection interrupt enable
+ * @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
+ * @arg SAI_IT_FREQ: FIFO request interrupt enable
+ * @arg SAI_IT_CNRDY: Codec not ready interrupt enable
+ * @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
+ * @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & \
+ (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Check whether the specified SAI flag is set or not.
+ * @param __HANDLE__ specifies the SAI Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SAI_FLAG_OVRUDR: Overrun underrun flag.
+ * @arg SAI_FLAG_MUTEDET: Mute detection flag.
+ * @arg SAI_FLAG_WCKCFG: Wrong Clock Configuration flag.
+ * @arg SAI_FLAG_FREQ: FIFO request flag.
+ * @arg SAI_FLAG_CNRDY: Codec not ready flag.
+ * @arg SAI_FLAG_AFSDET: Anticipated frame synchronization detection flag.
+ * @arg SAI_FLAG_LFSDET: Late frame synchronization detection flag.
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the specified SAI pending flag.
+ * @param __HANDLE__ specifies the SAI Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg SAI_FLAG_OVRUDR: Clear Overrun underrun
+ * @arg SAI_FLAG_MUTEDET: Clear Mute detection
+ * @arg SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration
+ * @arg SAI_FLAG_FREQ: Clear FIFO request
+ * @arg SAI_FLAG_CNRDY: Clear Codec not ready
+ * @arg SAI_FLAG_AFSDET: Clear Anticipated frame synchronization detection
+ * @arg SAI_FLAG_LFSDET: Clear Late frame synchronization detection
+ *
+ * @retval None
+ */
+#define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
+
+/** @brief Enable SAI.
+ * @param __HANDLE__ specifies the SAI Handle.
+ * @retval None
+ */
+#define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN)
+
+/** @brief Disable SAI.
+ * @param __HANDLE__ specifies the SAI Handle.
+ * @retval None
+ */
+#define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN)
+
+/**
+ * @}
+ */
+
+/* Include SAI HAL Extension module */
+#include "stm32u5xx_hal_sai_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SAI_Exported_Functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions ********************************/
+/** @addtogroup SAI_Exported_Functions_Group1
+ * @{
+ */
+HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
+HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai);
+HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai);
+void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai);
+void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai);
+
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+/* SAI callbacks register/unregister functions ********************************/
+HAL_StatusTypeDef HAL_SAI_RegisterCallback(SAI_HandleTypeDef *hsai,
+ HAL_SAI_CallbackIDTypeDef CallbackID,
+ pSAI_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SAI_UnRegisterCallback(SAI_HandleTypeDef *hsai,
+ HAL_SAI_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/* I/O operation functions ***************************************************/
+/** @addtogroup SAI_Exported_Functions_Group2
+ * @{
+ */
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai);
+HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai);
+HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai);
+
+/* Abort function */
+HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai);
+
+/* Mute management */
+HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val);
+HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai);
+HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter);
+HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai);
+
+/* SAI IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
+void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai);
+void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai);
+void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai);
+void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai);
+void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai);
+void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai);
+/**
+ * @}
+ */
+
+/** @addtogroup SAI_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral State functions ************************************************/
+HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai);
+uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SAI_Private_Macros SAI Private Macros
+ * @{
+ */
+#define IS_SAI_BLOCK_SYNCEXT(STATE) (((STATE) == SAI_SYNCEXT_DISABLE) ||\
+ ((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE) ||\
+ ((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE))
+
+#define IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_I2S_STANDARD) ||\
+ ((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\
+ ((PROTOCOL) == SAI_I2S_LSBJUSTIFIED) ||\
+ ((PROTOCOL) == SAI_PCM_LONG) ||\
+ ((PROTOCOL) == SAI_PCM_SHORT))
+
+#define IS_SAI_PROTOCOL_DATASIZE(DATASIZE) (((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BIT) ||\
+ ((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) ||\
+ ((DATASIZE) == SAI_PROTOCOL_DATASIZE_24BIT) ||\
+ ((DATASIZE) == SAI_PROTOCOL_DATASIZE_32BIT))
+
+#define IS_SAI_AUDIO_FREQUENCY(AUDIO) (((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || \
+ ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \
+ ((AUDIO) == SAI_AUDIO_FREQUENCY_48K) || \
+ ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \
+ ((AUDIO) == SAI_AUDIO_FREQUENCY_32K) || \
+ ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \
+ ((AUDIO) == SAI_AUDIO_FREQUENCY_16K) || \
+ ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \
+ ((AUDIO) == SAI_AUDIO_FREQUENCY_8K) || \
+ ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV))
+
+#define IS_SAI_BLOCK_MCK_OVERSAMPLING(VALUE) (((VALUE) == SAI_MCK_OVERSAMPLING_DISABLE) || \
+ ((VALUE) == SAI_MCK_OVERSAMPLING_ENABLE))
+
+#define IS_SAI_PDM_MIC_PAIRS_NUMBER(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 3U))
+
+#define IS_SAI_PDM_CLOCK_ENABLE(CLOCK) (((CLOCK) != 0U) && \
+ (((CLOCK) & ~(SAI_PDM_CLOCK1_ENABLE | SAI_PDM_CLOCK2_ENABLE)) == 0U))
+
+#define IS_SAI_BLOCK_MODE(MODE) (((MODE) == SAI_MODEMASTER_TX) || \
+ ((MODE) == SAI_MODEMASTER_RX) || \
+ ((MODE) == SAI_MODESLAVE_TX) || \
+ ((MODE) == SAI_MODESLAVE_RX))
+
+#define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_FREE_PROTOCOL) || \
+ ((PROTOCOL) == SAI_AC97_PROTOCOL) || \
+ ((PROTOCOL) == SAI_SPDIF_PROTOCOL))
+
+#define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DATASIZE_8) || \
+ ((DATASIZE) == SAI_DATASIZE_10) || \
+ ((DATASIZE) == SAI_DATASIZE_16) || \
+ ((DATASIZE) == SAI_DATASIZE_20) || \
+ ((DATASIZE) == SAI_DATASIZE_24) || \
+ ((DATASIZE) == SAI_DATASIZE_32))
+
+#define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FIRSTBIT_MSB) || \
+ ((BIT) == SAI_FIRSTBIT_LSB))
+
+#define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \
+ ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE))
+
+#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS) || \
+ ((SYNCHRO) == SAI_SYNCHRONOUS) || \
+ ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) || \
+ ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2))
+
+#define IS_SAI_BLOCK_MCK_OUTPUT(VALUE) (((VALUE) == SAI_MCK_OUTPUT_ENABLE) || \
+ ((VALUE) == SAI_MCK_OUTPUT_DISABLE))
+
+#define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \
+ ((DRIVE) == SAI_OUTPUTDRIVE_ENABLE))
+
+#define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \
+ ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE))
+
+#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63U)
+
+#define IS_SAI_BLOCK_MUTE_VALUE(VALUE) (((VALUE) == SAI_ZERO_VALUE) || \
+ ((VALUE) == SAI_LAST_SENT_VALUE))
+
+#define IS_SAI_BLOCK_COMPANDING_MODE(MODE) (((MODE) == SAI_NOCOMPANDING) || \
+ ((MODE) == SAI_ULAW_1CPL_COMPANDING) || \
+ ((MODE) == SAI_ALAW_1CPL_COMPANDING) || \
+ ((MODE) == SAI_ULAW_2CPL_COMPANDING) || \
+ ((MODE) == SAI_ALAW_2CPL_COMPANDING))
+
+#define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY) || \
+ ((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF) || \
+ ((THRESHOLD) == SAI_FIFOTHRESHOLD_HF) || \
+ ((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF) || \
+ ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL))
+
+#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\
+ ((STATE) == SAI_OUTPUT_RELEASED))
+
+#define IS_SAI_MONO_STEREO_MODE(MODE) (((MODE) == SAI_MONOMODE) ||\
+ ((MODE) == SAI_STEREOMODE))
+
+#define IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) <= SAI_SLOTACTIVE_ALL)
+
+#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1U <= (NUMBER)) && ((NUMBER) <= 16U))
+
+#define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \
+ ((SIZE) == SAI_SLOTSIZE_16B) || \
+ ((SIZE) == SAI_SLOTSIZE_32B))
+
+#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24U)
+
+#define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \
+ ((OFFSET) == SAI_FS_BEFOREFIRSTBIT))
+
+#define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ACTIVE_LOW) || \
+ ((POLARITY) == SAI_FS_ACTIVE_HIGH))
+
+#define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \
+ ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION))
+
+#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 63U)
+
+#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8U <= (LENGTH)) && ((LENGTH) <= 256U))
+
+#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1U <= (LENGTH)) && ((LENGTH) <= 128U))
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup SAI_Private_Functions SAI Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_SAI_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sai_ex.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sai_ex.h
new file mode 100644
index 00000000..bb81be74
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sai_ex.h
@@ -0,0 +1,102 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_sai_ex.h
+ * @author MCD Application Team
+ * @brief Header file of SAI HAL extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_SAI_EX_H
+#define STM32U5xx_HAL_SAI_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SAIEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SAIEx_Exported_Types SAIEx Exported Types
+ * @{
+ */
+
+/**
+ * @brief PDM microphone delay structure definition
+ */
+typedef struct
+{
+ uint32_t MicPair; /*!< Specifies which pair of microphones is selected.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 3. */
+
+ uint32_t LeftDelay; /*!< Specifies the delay in PDM clock unit to apply on left microphone.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 7. */
+
+ uint32_t RightDelay; /*!< Specifies the delay in PDM clock unit to apply on right microphone.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 7. */
+} SAIEx_PdmMicDelayParamTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SAIEx_Exported_Functions SAIEx Extended Exported Functions
+ * @{
+ */
+
+/** @addtogroup SAIEx_Exported_Functions_Group1 Peripheral Control functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup SAIEx_Private_Macros SAIEx Extended Private Macros
+ * @{
+ */
+#define IS_SAI_PDM_MIC_DELAY(VALUE) ((VALUE) <= 7U)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_SAI_EX_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sd.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sd.h
new file mode 100644
index 00000000..94f68ab2
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sd.h
@@ -0,0 +1,796 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_sd.h
+ * @author MCD Application Team
+ * @brief Header file of SD HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_SD_H
+#define STM32U5xx_HAL_SD_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_ll_sdmmc.h"
+#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2) || defined (DLYB_SDMMC3)
+#include "stm32u5xx_ll_dlyb.h"
+#endif /* (DLYB_SDMMC1) || (DLYB_SDMMC2) */
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SD SD
+ * @brief SD HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SD_Exported_Types SD Exported Types
+ * @{
+ */
+
+/** @defgroup SD_Exported_Types_Group1 SD State enumeration structure
+ * @{
+ */
+typedef enum
+{
+ HAL_SD_STATE_RESET = ((uint32_t)0x00000000U), /*!< SD not yet initialized or disabled */
+ HAL_SD_STATE_READY = ((uint32_t)0x00000001U), /*!< SD initialized and ready for use */
+ HAL_SD_STATE_TIMEOUT = ((uint32_t)0x00000002U), /*!< SD Timeout state */
+ HAL_SD_STATE_BUSY = ((uint32_t)0x00000003U), /*!< SD process ongoing */
+ HAL_SD_STATE_PROGRAMMING = ((uint32_t)0x00000004U), /*!< SD Programming State */
+ HAL_SD_STATE_RECEIVING = ((uint32_t)0x00000005U), /*!< SD Receiving State */
+ HAL_SD_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< SD Transfer State */
+ HAL_SD_STATE_ERROR = ((uint32_t)0x0000000FU) /*!< SD is in error state */
+} HAL_SD_StateTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure
+ * @{
+ */
+typedef uint32_t HAL_SD_CardStateTypeDef;
+
+#define HAL_SD_CARD_READY 0x00000001U /*!< Card state is ready */
+#define HAL_SD_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state */
+#define HAL_SD_CARD_STANDBY 0x00000003U /*!< Card is in standby state */
+#define HAL_SD_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */
+#define HAL_SD_CARD_SENDING 0x00000005U /*!< Card is sending an operation */
+#define HAL_SD_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */
+#define HAL_SD_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */
+#define HAL_SD_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */
+#define HAL_SD_CARD_ERROR 0x000000FFU /*!< Card response Error */
+/**
+ * @}
+ */
+
+/** @defgroup SD_Exported_Types_Group3 SD Handle Structure definition
+ * @{
+ */
+#define SD_InitTypeDef SDMMC_InitTypeDef
+#define SD_TypeDef SDMMC_TypeDef
+
+/**
+ * @brief SD Card Information Structure definition
+ */
+typedef struct
+{
+ uint32_t CardType; /*!< Specifies the card Type */
+
+ uint32_t CardVersion; /*!< Specifies the card version */
+
+ uint32_t Class; /*!< Specifies the class of the card class */
+
+ uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */
+
+ uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */
+
+ uint32_t BlockSize; /*!< Specifies one block size in bytes */
+
+ uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */
+
+ uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */
+
+ uint32_t CardSpeed; /*!< Specifies the card Speed */
+
+} HAL_SD_CardInfoTypeDef;
+
+/**
+ * @brief SD handle Structure definition
+ */
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+typedef struct __SD_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+{
+ SD_TypeDef *Instance; /*!< SD registers base address */
+
+ SD_InitTypeDef Init; /*!< SD required parameters */
+
+ HAL_LockTypeDef Lock; /*!< SD locking object */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */
+
+ uint32_t TxXferSize; /*!< SD Tx Transfer size */
+
+ uint8_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */
+
+ uint32_t RxXferSize; /*!< SD Rx Transfer size */
+
+ __IO uint32_t Context; /*!< SD transfer context */
+
+ __IO HAL_SD_StateTypeDef State; /*!< SD card State */
+
+ __IO uint32_t ErrorCode; /*!< SD Card Error codes */
+
+ HAL_SD_CardInfoTypeDef SdCard; /*!< SD Card information */
+
+ uint32_t CSD[4]; /*!< SD card specific data table */
+
+ uint32_t CID[4]; /*!< SD card identification number table */
+
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+ void (* TxCpltCallback)(struct __SD_HandleTypeDef *hsd);
+ void (* RxCpltCallback)(struct __SD_HandleTypeDef *hsd);
+ void (* ErrorCallback)(struct __SD_HandleTypeDef *hsd);
+ void (* AbortCpltCallback)(struct __SD_HandleTypeDef *hsd);
+ void (* Read_DMALnkLstBufCpltCallback)(struct __SD_HandleTypeDef *hsd);
+ void (* Write_DMALnkLstBufCpltCallback)(struct __SD_HandleTypeDef *hsd);
+#if (USE_SD_TRANSCEIVER != 0U)
+ void (* DriveTransceiver_1_8V_Callback)(FlagStatus status);
+#endif /* USE_SD_TRANSCEIVER */
+
+ void (* MspInitCallback)(struct __SD_HandleTypeDef *hsd);
+ void (* MspDeInitCallback)(struct __SD_HandleTypeDef *hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+} SD_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup SD_Exported_Types_Group4 Card Specific Data: CSD Register
+ * @{
+ */
+typedef struct
+{
+ __IO uint8_t CSDStruct; /*!< CSD structure */
+ __IO uint8_t SysSpecVersion; /*!< System specification version */
+ __IO uint8_t Reserved1; /*!< Reserved */
+ __IO uint8_t TAAC; /*!< Data read access time 1 */
+ __IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */
+ __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */
+ __IO uint16_t CardComdClasses; /*!< Card command classes */
+ __IO uint8_t RdBlockLen; /*!< Max. read data block length */
+ __IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */
+ __IO uint8_t WrBlockMisalign; /*!< Write block misalignment */
+ __IO uint8_t RdBlockMisalign; /*!< Read block misalignment */
+ __IO uint8_t DSRImpl; /*!< DSR implemented */
+ __IO uint8_t Reserved2; /*!< Reserved */
+ __IO uint32_t DeviceSize; /*!< Device Size */
+ __IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */
+ __IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */
+ __IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */
+ __IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */
+ __IO uint8_t DeviceSizeMul; /*!< Device size multiplier */
+ __IO uint8_t EraseGrSize; /*!< Erase group size */
+ __IO uint8_t EraseGrMul; /*!< Erase group size multiplier */
+ __IO uint8_t WrProtectGrSize; /*!< Write protect group size */
+ __IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */
+ __IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */
+ __IO uint8_t WrSpeedFact; /*!< Write speed factor */
+ __IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */
+ __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
+ __IO uint8_t Reserved3; /*!< Reserved */
+ __IO uint8_t ContentProtectAppli; /*!< Content protection application */
+ __IO uint8_t FileFormatGroup; /*!< File format group */
+ __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
+ __IO uint8_t PermWrProtect; /*!< Permanent write protection */
+ __IO uint8_t TempWrProtect; /*!< Temporary write protection */
+ __IO uint8_t FileFormat; /*!< File format */
+ __IO uint8_t ECC; /*!< ECC code */
+ __IO uint8_t CSD_CRC; /*!< CSD CRC */
+ __IO uint8_t Reserved4; /*!< Always 1 */
+} HAL_SD_CardCSDTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup SD_Exported_Types_Group5 Card Identification Data: CID Register
+ * @{
+ */
+typedef struct
+{
+ __IO uint8_t ManufacturerID; /*!< Manufacturer ID */
+ __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */
+ __IO uint32_t ProdName1; /*!< Product Name part1 */
+ __IO uint8_t ProdName2; /*!< Product Name part2 */
+ __IO uint8_t ProdRev; /*!< Product Revision */
+ __IO uint32_t ProdSN; /*!< Product Serial Number */
+ __IO uint8_t Reserved1; /*!< Reserved1 */
+ __IO uint16_t ManufactDate; /*!< Manufacturing Date */
+ __IO uint8_t CID_CRC; /*!< CID CRC */
+ __IO uint8_t Reserved2; /*!< Always 1 */
+
+} HAL_SD_CardCIDTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup SD_Exported_Types_Group6 SD Card Status returned by ACMD13
+ * @{
+ */
+typedef struct
+{
+ __IO uint8_t DataBusWidth; /*!< Shows the currently defined data bus width */
+ __IO uint8_t SecuredMode; /*!< Card is in secured mode of operation */
+ __IO uint16_t CardType; /*!< Carries information about card type */
+ __IO uint32_t ProtectedAreaSize; /*!< Carries information about the capacity of protected area */
+ __IO uint8_t SpeedClass; /*!< Carries information about the speed class of the card */
+ __IO uint8_t PerformanceMove; /*!< Carries information about the card's performance move */
+ __IO uint8_t AllocationUnitSize; /*!< Carries information about the card's allocation unit size */
+ __IO uint16_t EraseSize; /*!< Determines the number of AUs to be erased in one operation */
+ __IO uint8_t EraseTimeout; /*!< Determines the timeout for any number of AU erase */
+ __IO uint8_t EraseOffset; /*!< Carries information about the erase offset */
+ __IO uint8_t UhsSpeedGrade; /*!< Carries information about the speed grade of UHS card */
+ __IO uint8_t UhsAllocationUnitSize; /*!< Carries information about the UHS card's allocation unit size */
+ __IO uint8_t VideoSpeedClass; /*!< Carries information about the Video Speed Class of UHS card */
+} HAL_SD_CardStatusTypeDef;
+/**
+ * @}
+ */
+
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+/** @defgroup SD_Exported_Types_Group7 SD Callback ID enumeration definition
+ * @{
+ */
+typedef enum
+{
+ HAL_SD_TX_CPLT_CB_ID = 0x00U, /*!< SD Tx Complete Callback ID */
+ HAL_SD_RX_CPLT_CB_ID = 0x01U, /*!< SD Rx Complete Callback ID */
+ HAL_SD_ERROR_CB_ID = 0x02U, /*!< SD Error Callback ID */
+ HAL_SD_ABORT_CB_ID = 0x03U, /*!< SD Abort Callback ID */
+ HAL_SD_READ_DMA_LNKLST_BUF_CPLT_CB_ID = 0x04U, /*!< SD DMA Rx Linked List Node buffer Callback ID */
+ HAL_SD_WRITE_DMA_LNKLST_BUF_CPLT_CB_ID = 0x05U, /*!< SD DMA Tx Linked List Node buffer Callback ID */
+
+ HAL_SD_MSP_INIT_CB_ID = 0x10U, /*!< SD MspInit Callback ID */
+ HAL_SD_MSP_DEINIT_CB_ID = 0x11U /*!< SD MspDeInit Callback ID */
+} HAL_SD_CallbackIDTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup SD_Exported_Types_Group8 SD Callback pointer definition
+ * @{
+ */
+typedef void (*pSD_CallbackTypeDef)(SD_HandleTypeDef *hsd);
+#if (USE_SD_TRANSCEIVER != 0U)
+typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status);
+#endif /* USE_SD_TRANSCEIVER */
+/**
+ * @}
+ */
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SD_Exported_Constants Exported Constants
+ * @{
+ */
+
+#define BLOCKSIZE ((uint32_t)512U) /*!< Block size is 512 bytes */
+
+/** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition
+ * @{
+ */
+#define HAL_SD_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */
+#define HAL_SD_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */
+#define HAL_SD_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */
+#define HAL_SD_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */
+#define HAL_SD_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */
+#define HAL_SD_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */
+#define HAL_SD_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */
+#define HAL_SD_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */
+#define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the */
+ /*!< number of transferred bytes does not match the block length */
+#define HAL_SD_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */
+#define HAL_SD_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */
+#define HAL_SD_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */
+#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock */
+ /*!< command or if there was an attempt to access a locked card */
+#define HAL_SD_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */
+#define HAL_SD_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */
+#define HAL_SD_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */
+#define HAL_SD_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */
+#define HAL_SD_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */
+#define HAL_SD_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */
+#define HAL_SD_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */
+#define HAL_SD_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */
+#define HAL_SD_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */
+#define HAL_SD_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */
+#define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out */
+ /*!< of erase sequence command was received */
+#define HAL_SD_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */
+#define HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */
+#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */
+#define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */
+#define HAL_SD_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */
+#define HAL_SD_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */
+#define HAL_SD_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
+#define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
+#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
+
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+#define HAL_SD_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup SD_Exported_Constansts_Group2 SD context enumeration
+ * @{
+ */
+#define SD_CONTEXT_NONE ((uint32_t)0x00000000U) /*!< None */
+#define SD_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U) /*!< Read single block operation */
+#define SD_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U) /*!< Read multiple blocks operation */
+#define SD_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U) /*!< Write single block operation */
+#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U) /*!< Write multiple blocks operation */
+#define SD_CONTEXT_IT ((uint32_t)0x00000008U) /*!< Process in Interrupt mode */
+#define SD_CONTEXT_DMA ((uint32_t)0x00000080U) /*!< Process in DMA mode */
+
+/**
+ * @}
+ */
+
+/** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards
+ * @{
+ */
+#define CARD_NORMAL_SPEED ((uint32_t)0x00000000U) /*!< Normal Speed Card <12.5Mo/s , Spec Version 1.01 */
+#define CARD_HIGH_SPEED ((uint32_t)0x00000100U) /*!< High Speed Card <25Mo/s , Spec version 2.00 */
+#define CARD_ULTRA_HIGH_SPEED ((uint32_t)0x00000200U) /*!< UHS-I SD Card <50Mo/s for SDR50, DDR5 Cards
+ and <104Mo/s for SDR104, Spec version 3.01 */
+
+#define CARD_SDSC ((uint32_t)0x00000000U) /*!< SD Standard Capacity <2Go */
+#define CARD_SDHC_SDXC ((uint32_t)0x00000001U) /*!< SD High Capacity <32Go, SD Extended Capacity <2To */
+#define CARD_SECURED ((uint32_t)0x00000003U)
+
+/**
+ * @}
+ */
+
+/** @defgroup SD_Exported_Constansts_Group4 SD Supported Version
+ * @{
+ */
+#define CARD_V1_X ((uint32_t)0x00000000U)
+#define CARD_V2_X ((uint32_t)0x00000001U)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SD_Exported_macros SD Exported Macros
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+/** @brief Reset SD handle state.
+ * @param __HANDLE__ SD Handle.
+ * @retval None
+ */
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_SD_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SD_STATE_RESET)
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+
+/**
+ * @brief Enable the SD device interrupt.
+ * @param __HANDLE__ SD Handle.
+ * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
+ * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
+ * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
+ * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
+ * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
+ * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
+ * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+ * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
+ * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
+ * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
+ * @retval None
+ */
+#define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+ * @brief Disable the SD device interrupt.
+ * @param __HANDLE__ SD Handle.
+ * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
+ * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
+ * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
+ * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
+ * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
+ * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
+ * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+ * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
+ * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
+ * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
+ * @retval None
+ */
+#define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified SD flag is set or not.
+ * @param __HANDLE__ SD Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
+ * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+ * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
+ * @arg SDMMC_FLAG_DTIMEOUT: Data timeout
+ * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
+ * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
+ * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
+ * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
+ * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
+ * @arg SDMMC_FLAG_DHOLD: Data transfer Hold
+ * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
+ * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
+ * @arg SDMMC_FLAG_DPSMACT: Data path state machine active
+ * @arg SDMMC_FLAG_CPSMACT: Command path state machine active
+ * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
+ * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
+ * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full
+ * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full
+ * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty
+ * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty
+ * @arg SDMMC_FLAG_BUSYD0: Inverted value of SDMMC_D0 line (Busy)
+ * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected
+ * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received
+ * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received
+ * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
+ * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion
+ * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure
+ * @arg SDMMC_FLAG_IDMATE: IDMA transfer error
+ * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete
+ * @retval The new state of SD FLAG (SET or RESET).
+ */
+#define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
+
+/**
+ * @brief Clear the SD's pending flags.
+ * @param __HANDLE__ SD Handle.
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
+ * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+ * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
+ * @arg SDMMC_FLAG_DTIMEOUT: Data timeout
+ * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
+ * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
+ * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
+ * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
+ * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
+ * @arg SDMMC_FLAG_DHOLD: Data transfer Hold
+ * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
+ * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
+ * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected
+ * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received
+ * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received
+ * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
+ * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion
+ * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure
+ * @arg SDMMC_FLAG_IDMATE: IDMA transfer error
+ * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete
+ * @retval None
+ */
+#define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
+
+/**
+ * @brief Check whether the specified SD interrupt has occurred or not.
+ * @param __HANDLE__ SD Handle.
+ * @param __INTERRUPT__ specifies the SDMMC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
+ * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
+ * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
+ * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
+ * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
+ * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
+ * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+ * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
+ * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
+ * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
+ * @retval The new state of SD IT (SET or RESET).
+ */
+#define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+ * @brief Clear the SD's interrupt pending bits.
+ * @param __HANDLE__ SD Handle.
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
+ * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
+ * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
+ * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
+ * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
+ * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
+ * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+ * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
+ * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
+ * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
+ * @retval None
+ */
+#define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+ * @}
+ */
+
+/* Include SD HAL Extension module */
+#include "stm32u5xx_hal_sd_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SD_Exported_Functions SD Exported Functions
+ * @{
+ */
+
+/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd);
+void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
+void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
+/**
+ * @}
+ */
+
+/** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
+/* Non-Blocking mode: IT */
+HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks);
+
+void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
+
+/* Callback in non blocking modes (DMA) */
+void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd);
+void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd);
+void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd);
+void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd);
+
+#if (USE_SD_TRANSCEIVER != 0U)
+/* Callback to switch in 1.8V mode */
+void HAL_SD_DriveTransceiver_1_8V_Callback(FlagStatus status);
+#endif /* USE_SD_TRANSCEIVER */
+
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+/* SD callback registering/unregistering */
+HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID,
+ pSD_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID);
+
+#if (USE_SD_TRANSCEIVER != 0U)
+HAL_StatusTypeDef HAL_SD_RegisterTransceiverCallback(SD_HandleTypeDef *hsd, pSD_TransceiverCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SD_UnRegisterTransceiverCallback(SD_HandleTypeDef *hsd);
+#endif /* USE_SD_TRANSCEIVER */
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode);
+HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t SpeedMode);
+/**
+ * @}
+ */
+
+/** @defgroup SD_Exported_Functions_Group4 SD card related functions
+ * @{
+ */
+HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID);
+HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD);
+HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus);
+HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo);
+/**
+ * @}
+ */
+
+/** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions
+ * @{
+ */
+HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd);
+uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd);
+/**
+ * @}
+ */
+
+/** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management
+ * @{
+ */
+HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd);
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup SD_Private_Types SD Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup SD_Private_Defines SD Private Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup SD_Private_Variables SD Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SD_Private_Constants SD Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SD_Private_Macros SD Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup SD_Private_Functions SD Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32U5xx_HAL_SD_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sd_ex.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sd_ex.h
new file mode 100644
index 00000000..82868d6e
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sd_ex.h
@@ -0,0 +1,117 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_sd_ex.h
+ * @author MCD Application Team
+ * @brief Header file of SD HAL extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_SD_EX_H
+#define STM32U5xx_HAL_SD_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SDEx
+ * @brief SD HAL extended module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SDEx_Exported_Types SDEx Exported Types
+ * @{
+ */
+
+/** @defgroup SDEx_Exported_Types_Group1 Linked List Wrapper
+ * @{
+ */
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* -----------------Linked List Wrapper --------------------------------------*/
+
+#define SD_DMALinkNodeTypeDef SDMMC_DMALinkNodeTypeDef
+#define SD_DMALinkNodeConfTypeDef SDMMC_DMALinkNodeConfTypeDef
+#define SD_DMALinkedListTypeDef SDMMC_DMALinkedListTypeDef
+/* ----------------- Linked Aliases ------------------------------------------*/
+#define HAL_SDEx_DMALinkedList_WriteCpltCallback HAL_SD_TxCpltCallback
+#define HAL_SDEx_DMALinkedList_ReadCpltCallback HAL_SD_RxCpltCallback
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SDEx_Exported_Functions SDEx Exported Functions
+ * @{
+ */
+/** @defgroup SDEx_Exported_Functions_Group1 Linked List functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_SDEx_DMALinkedList_ReadBlocks(SD_HandleTypeDef *hsd, SD_DMALinkedListTypeDef *pLinkedList,
+ uint32_t BlockAdd, uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_SDEx_DMALinkedList_WriteBlocks(SD_HandleTypeDef *hsd, SD_DMALinkedListTypeDef *pLinkedList,
+ uint32_t BlockAdd, uint32_t NumberOfBlocks);
+
+HAL_StatusTypeDef HAL_SDEx_DMALinkedList_BuildNode(SD_DMALinkNodeTypeDef *pNode, SD_DMALinkNodeConfTypeDef *pNodeConf);
+HAL_StatusTypeDef HAL_SDEx_DMALinkedList_InsertNode(SD_DMALinkedListTypeDef *pLinkedList,
+ SD_DMALinkNodeTypeDef *pPrevNode, SD_DMALinkNodeTypeDef *pNewNode);
+HAL_StatusTypeDef HAL_SDEx_DMALinkedList_RemoveNode(SD_DMALinkedListTypeDef *pLinkedList, SD_DMALinkNodeTypeDef *pNode);
+HAL_StatusTypeDef HAL_SDEx_DMALinkedList_LockNode(SD_DMALinkNodeTypeDef *pNode);
+HAL_StatusTypeDef HAL_SDEx_DMALinkedList_UnlockNode(SD_DMALinkNodeTypeDef *pNode);
+HAL_StatusTypeDef HAL_SDEx_DMALinkedList_EnableCircularMode(SD_DMALinkedListTypeDef *pLinkedList);
+HAL_StatusTypeDef HAL_SDEx_DMALinkedList_DisableCircularMode(SD_DMALinkedListTypeDef *pLinkedList);
+
+void HAL_SDEx_Read_DMALnkLstBufCpltCallback(SD_HandleTypeDef *hsd);
+void HAL_SDEx_Write_DMALnkLstBufCpltCallback(SD_HandleTypeDef *hsd);
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions prototypes ----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* stm32u5xx_HAL_SD_EX_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_smartcard.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_smartcard.h
new file mode 100644
index 00000000..f18abfc3
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_smartcard.h
@@ -0,0 +1,1305 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_smartcard.h
+ * @author MCD Application Team
+ * @brief Header file of SMARTCARD HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_SMARTCARD_H
+#define STM32U5xx_HAL_SMARTCARD_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SMARTCARD
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
+ * @{
+ */
+
+/**
+ * @brief SMARTCARD Init Structure definition
+ */
+typedef struct
+{
+ uint32_t BaudRate; /*!< Configures the SmartCard communication baud rate.
+ The baud rate register is computed using the following formula:
+ Baud Rate Register = ((usart_ker_ckpres) / ((hsmartcard->Init.BaudRate)))
+ where usart_ker_ckpres is the USART input clock divided by a prescaler */
+
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter @ref SMARTCARD_Word_Length can only be
+ set to 9 (8 data + 1 parity bits). */
+
+ uint32_t StopBits; /*!< Specifies the number of stop bits.
+ This parameter can be a value of @ref SMARTCARD_Stop_Bits. */
+
+ uint16_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref SMARTCARD_Parity
+ @note The parity is enabled by default (PCE is forced to 1).
+ Since the WordLength is forced to 8 bits + parity, M is
+ forced to 1 and the parity bit is the 9th bit. */
+
+ uint16_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref SMARTCARD_Mode */
+
+ uint16_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
+ This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
+
+ uint16_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref SMARTCARD_Clock_Phase */
+
+ uint16_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+ This parameter can be a value of @ref SMARTCARD_Last_Bit */
+
+ uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote
+ is selected. Selecting the single sample method increases
+ the receiver tolerance to clock deviations. This parameter can be a value
+ of @ref SMARTCARD_OneBit_Sampling. */
+
+ uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler.
+ This parameter can be any value from 0x01 to 0x1F. Prescaler value is
+ multiplied by 2 to give the division factor of the source clock frequency */
+
+ uint8_t GuardTime; /*!< Specifies the SmartCard Guard Time applied after stop bits. */
+
+ uint16_t NACKEnable; /*!< Specifies whether the SmartCard NACK transmission is enabled
+ in case of parity error.
+ This parameter can be a value of @ref SMARTCARD_NACK_Enable */
+
+ uint32_t TimeOutEnable; /*!< Specifies whether the receiver timeout is enabled.
+ This parameter can be a value of @ref SMARTCARD_Timeout_Enable*/
+
+ uint32_t TimeOutValue; /*!< Specifies the receiver time out value in number of baud blocks:
+ it is used to implement the Character Wait Time (CWT) and
+ Block Wait Time (BWT). It is coded over 24 bits. */
+
+ uint8_t BlockLength; /*!< Specifies the SmartCard Block Length in T=1 Reception mode.
+ This parameter can be any value from 0x0 to 0xFF */
+
+ uint8_t AutoRetryCount; /*!< Specifies the SmartCard auto-retry count (number of retries in
+ receive and transmit mode). When set to 0, retransmission is
+ disabled. Otherwise, its maximum value is 7 (before signalling
+ an error) */
+
+ uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the USART clock source.
+ This parameter can be a value of @ref SMARTCARD_ClockPrescaler. */
+
+} SMARTCARD_InitTypeDef;
+
+/**
+ * @brief SMARTCARD advanced features initialization structure definition
+ */
+typedef struct
+{
+ uint32_t AdvFeatureInit; /*!< Specifies which advanced SMARTCARD features is initialized. Several
+ advanced features may be initialized at the same time. This parameter
+ can be a value of @ref SMARTCARDEx_Advanced_Features_Initialization_Type */
+
+ uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted.
+ This parameter can be a value of @ref SMARTCARD_Tx_Inv */
+
+ uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted.
+ This parameter can be a value of @ref SMARTCARD_Rx_Inv */
+
+ uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic
+ vs negative/inverted logic).
+ This parameter can be a value of @ref SMARTCARD_Data_Inv */
+
+ uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped.
+ This parameter can be a value of @ref SMARTCARD_Rx_Tx_Swap */
+
+ uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled.
+ This parameter can be a value of @ref SMARTCARD_Overrun_Disable */
+
+ uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error.
+ This parameter can be a value of @ref SMARTCARD_DMA_Disable_on_Rx_Error */
+
+ uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
+ This parameter can be a value of @ref SMARTCARD_MSB_First */
+
+ uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when
+ relevant flag is available) or once guard time period has elapsed.
+ This parameter can be a value
+ of @ref SMARTCARDEx_Transmission_Completion_Indication. */
+} SMARTCARD_AdvFeatureInitTypeDef;
+
+/**
+ * @brief HAL SMARTCARD State definition
+ * @note HAL SMARTCARD State value is a combination of 2 different substates:
+ * gState and RxState (see @ref SMARTCARD_State_Definition).
+ * - gState contains SMARTCARD state information related to global Handle management
+ * and also information related to Tx operations.
+ * gState value coding follow below described bitmap :
+ * b7-b6 Error information
+ * 00 : No Error
+ * 01 : (Not Used)
+ * 10 : Timeout
+ * 11 : Error
+ * b5 Peripheral initialization status
+ * 0 : Reset (Peripheral not initialized)
+ * 1 : Init done (Peripheral initialized. HAL SMARTCARD Init function already called)
+ * b4-b3 (not used)
+ * xx : Should be set to 00
+ * b2 Intrinsic process state
+ * 0 : Ready
+ * 1 : Busy (Peripheral busy with some configuration or internal operations)
+ * b1 (not used)
+ * x : Should be set to 0
+ * b0 Tx state
+ * 0 : Ready (no Tx operation ongoing)
+ * 1 : Busy (Tx operation ongoing)
+ * - RxState contains information related to Rx operations.
+ * RxState value coding follow below described bitmap :
+ * b7-b6 (not used)
+ * xx : Should be set to 00
+ * b5 Peripheral initialization status
+ * 0 : Reset (Peripheral not initialized)
+ * 1 : Init done (Peripheral initialized)
+ * b4-b2 (not used)
+ * xxx : Should be set to 000
+ * b1 Rx state
+ * 0 : Ready (no Rx operation ongoing)
+ * 1 : Busy (Rx operation ongoing)
+ * b0 (not used)
+ * x : Should be set to 0.
+ */
+typedef uint32_t HAL_SMARTCARD_StateTypeDef;
+
+/**
+ * @brief SMARTCARD handle Structure definition
+ */
+typedef struct __SMARTCARD_HandleTypeDef
+{
+ USART_TypeDef *Instance; /*!< USART registers base address */
+
+ SMARTCARD_InitTypeDef Init; /*!< SmartCard communication parameters */
+
+ SMARTCARD_AdvFeatureInitTypeDef AdvancedInit; /*!< SmartCard advanced features initialization parameters */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */
+
+ uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */
+
+ __IO uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /*!< Pointer to SmartCard Rx transfer Buffer */
+
+ uint16_t RxXferSize; /*!< SmartCard Rx Transfer size */
+
+ __IO uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */
+
+ uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */
+
+ uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */
+
+ uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used.
+ This parameter can be a value of
+ @ref SMARTCARDEx_FIFO_mode. */
+
+ void (*RxISR)(struct __SMARTCARD_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
+
+ void (*TxISR)(struct __SMARTCARD_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
+
+ DMA_HandleTypeDef *hdmatx; /*!< SmartCard Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< SmartCard Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< Locking object */
+
+ __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global
+ Handle management and also related to Tx operations.
+ This parameter can be a value
+ of @ref HAL_SMARTCARD_StateTypeDef */
+
+ __IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations.
+ This parameter can be a value
+ of @ref HAL_SMARTCARD_StateTypeDef */
+
+ __IO uint32_t ErrorCode; /*!< SmartCard Error code */
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ void (* TxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Tx Complete Callback */
+
+ void (* RxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Rx Complete Callback */
+
+ void (* ErrorCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Error Callback */
+
+ void (* AbortCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Complete Callback */
+
+ void (* AbortTransmitCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Transmit Complete Callback */
+
+ void (* AbortReceiveCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Receive Complete Callback */
+
+ void (* RxFifoFullCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Rx Fifo Full Callback */
+
+ void (* TxFifoEmptyCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Tx Fifo Empty Callback */
+
+ void (* MspInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Msp Init callback */
+
+ void (* MspDeInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Msp DeInit callback */
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+
+} SMARTCARD_HandleTypeDef;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL SMARTCARD Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_SMARTCARD_TX_COMPLETE_CB_ID = 0x00U, /*!< SMARTCARD Tx Complete Callback ID */
+ HAL_SMARTCARD_RX_COMPLETE_CB_ID = 0x01U, /*!< SMARTCARD Rx Complete Callback ID */
+ HAL_SMARTCARD_ERROR_CB_ID = 0x02U, /*!< SMARTCARD Error Callback ID */
+ HAL_SMARTCARD_ABORT_COMPLETE_CB_ID = 0x03U, /*!< SMARTCARD Abort Complete Callback ID */
+ HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x04U, /*!< SMARTCARD Abort Transmit Complete Callback ID */
+ HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID = 0x05U, /*!< SMARTCARD Abort Receive Complete Callback ID */
+ HAL_SMARTCARD_RX_FIFO_FULL_CB_ID = 0x06U, /*!< SMARTCARD Rx Fifo Full Callback ID */
+ HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID = 0x07U, /*!< SMARTCARD Tx Fifo Empty Callback ID */
+
+ HAL_SMARTCARD_MSPINIT_CB_ID = 0x08U, /*!< SMARTCARD MspInit callback ID */
+ HAL_SMARTCARD_MSPDEINIT_CB_ID = 0x09U /*!< SMARTCARD MspDeInit callback ID */
+
+} HAL_SMARTCARD_CallbackIDTypeDef;
+
+/**
+ * @brief HAL SMARTCARD Callback pointer definition
+ */
+typedef void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsmartcard); /*!< pointer to an SMARTCARD callback function */
+
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+
+/**
+ * @brief SMARTCARD clock sources
+ */
+typedef enum
+{
+ SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
+ SMARTCARD_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
+ SMARTCARD_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
+ SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
+ SMARTCARD_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
+ SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10U /*!< undefined clock source */
+} SMARTCARD_ClockSourceTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Constants SMARTCARD Exported Constants
+ * @{
+ */
+
+/** @defgroup SMARTCARD_State_Definition SMARTCARD State Code Definition
+ * @{
+ */
+#define HAL_SMARTCARD_STATE_RESET 0x00000000U /*!< Peripheral is not initialized. Value
+ is allowed for gState and RxState */
+#define HAL_SMARTCARD_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for
+ use. Value is allowed for gState
+ and RxState */
+#define HAL_SMARTCARD_STATE_BUSY 0x00000024U /*!< an internal process is ongoing
+ Value is allowed for gState only */
+#define HAL_SMARTCARD_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing
+ Value is allowed for gState only */
+#define HAL_SMARTCARD_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing
+ Value is allowed for RxState only */
+#define HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception
+ process is ongoing Not to be used for
+ neither gState nor RxState.
+ Value is result of combination (Or)
+ between gState and RxState values */
+#define HAL_SMARTCARD_STATE_TIMEOUT 0x000000A0U /*!< Timeout state
+ Value is allowed for gState only */
+#define HAL_SMARTCARD_STATE_ERROR 0x000000E0U /*!< Error
+ Value is allowed for gState only */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Error_Definition SMARTCARD Error Code Definition
+ * @{
+ */
+#define HAL_SMARTCARD_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_SMARTCARD_ERROR_PE (0x00000001U) /*!< Parity error */
+#define HAL_SMARTCARD_ERROR_NE (0x00000002U) /*!< Noise error */
+#define HAL_SMARTCARD_ERROR_FE (0x00000004U) /*!< frame error */
+#define HAL_SMARTCARD_ERROR_ORE (0x00000008U) /*!< Overrun error */
+#define HAL_SMARTCARD_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
+#define HAL_SMARTCARD_ERROR_RTO (0x00000020U) /*!< Receiver TimeOut error */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
+ * @{
+ */
+#define SMARTCARD_WORDLENGTH_9B USART_CR1_M0 /*!< SMARTCARD frame length */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
+ * @{
+ */
+#define SMARTCARD_STOPBITS_0_5 USART_CR2_STOP_0 /*!< SMARTCARD frame with 0.5 stop bit */
+#define SMARTCARD_STOPBITS_1_5 USART_CR2_STOP /*!< SMARTCARD frame with 1.5 stop bits */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Parity SMARTCARD Parity
+ * @{
+ */
+#define SMARTCARD_PARITY_EVEN USART_CR1_PCE /*!< SMARTCARD frame even parity */
+#define SMARTCARD_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< SMARTCARD frame odd parity */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Mode SMARTCARD Transfer Mode
+ * @{
+ */
+#define SMARTCARD_MODE_RX USART_CR1_RE /*!< SMARTCARD RX mode */
+#define SMARTCARD_MODE_TX USART_CR1_TE /*!< SMARTCARD TX mode */
+#define SMARTCARD_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< SMARTCARD RX and TX mode */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
+ * @{
+ */
+#define SMARTCARD_POLARITY_LOW 0x00000000U /*!< SMARTCARD frame low polarity */
+#define SMARTCARD_POLARITY_HIGH USART_CR2_CPOL /*!< SMARTCARD frame high polarity */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
+ * @{
+ */
+#define SMARTCARD_PHASE_1EDGE 0x00000000U /*!< SMARTCARD frame phase on first clock transition */
+#define SMARTCARD_PHASE_2EDGE USART_CR2_CPHA /*!< SMARTCARD frame phase on second clock transition */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
+ * @{
+ */
+#define SMARTCARD_LASTBIT_DISABLE 0x00000000U /*!< SMARTCARD frame last data bit clock pulse not output to SCLK pin */
+#define SMARTCARD_LASTBIT_ENABLE USART_CR2_LBCL /*!< SMARTCARD frame last data bit clock pulse output to SCLK pin */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD One Bit Sampling Method
+ * @{
+ */
+#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< SMARTCARD frame one-bit sample disabled */
+#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< SMARTCARD frame one-bit sample enabled */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable
+ * @{
+ */
+#define SMARTCARD_NACK_DISABLE 0x00000000U /*!< SMARTCARD NACK transmission disabled */
+#define SMARTCARD_NACK_ENABLE USART_CR3_NACK /*!< SMARTCARD NACK transmission enabled */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable
+ * @{
+ */
+#define SMARTCARD_TIMEOUT_DISABLE 0x00000000U /*!< SMARTCARD receiver timeout disabled */
+#define SMARTCARD_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< SMARTCARD receiver timeout enabled */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_ClockPrescaler SMARTCARD Clock Prescaler
+ * @{
+ */
+#define SMARTCARD_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */
+#define SMARTCARD_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */
+#define SMARTCARD_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */
+#define SMARTCARD_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */
+#define SMARTCARD_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */
+#define SMARTCARD_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */
+#define SMARTCARD_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */
+#define SMARTCARD_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */
+#define SMARTCARD_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */
+#define SMARTCARD_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */
+#define SMARTCARD_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */
+#define SMARTCARD_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Tx_Inv SMARTCARD advanced feature TX pin active level inversion
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_TXINV_DISABLE 0x00000000U /*!< TX pin active level inversion disable */
+#define SMARTCARD_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV /*!< TX pin active level inversion enable */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Rx_Inv SMARTCARD advanced feature RX pin active level inversion
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */
+#define SMARTCARD_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Data_Inv SMARTCARD advanced feature Binary Data inversion
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE 0x00000000U /*!< Binary data inversion disable */
+#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV /*!< Binary data inversion enable */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD advanced feature RX TX pins swap
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_SWAP_DISABLE 0x00000000U /*!< TX/RX pins swap disable */
+#define SMARTCARD_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP /*!< TX/RX pins swap enable */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Overrun_Disable SMARTCARD advanced feature Overrun Disable
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */
+#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD advanced feature DMA Disable on Rx Error
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U /*!< DMA enable on Reception Error */
+#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE /*!< DMA disable on Reception Error */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_MSB_First SMARTCARD advanced feature MSB first
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received first disable */
+#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received first enable */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters
+ * @{
+ */
+#define SMARTCARD_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive data flush request */
+#define SMARTCARD_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush request */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flags mask
+ * @{
+ */
+#define SMARTCARD_IT_MASK 0x001FU /*!< SMARTCARD interruptions flags mask */
+#define SMARTCARD_CR_MASK 0x00E0U /*!< SMARTCARD control register mask */
+#define SMARTCARD_CR_POS 5U /*!< SMARTCARD control register position */
+#define SMARTCARD_ISR_MASK 0x1F00U /*!< SMARTCARD ISR register mask */
+#define SMARTCARD_ISR_POS 8U /*!< SMARTCARD ISR register position */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros
+ * @{
+ */
+
+/** @brief Reset SMARTCARD handle states.
+ * @param __HANDLE__ SMARTCARD handle.
+ * @retval None
+ */
+#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
+#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0U)
+#else
+#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
+ } while(0U)
+#endif /*USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+
+/** @brief Flush the Smartcard Data registers.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) \
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
+ SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
+ } while(0U)
+
+/** @brief Clear the specified SMARTCARD pending flag.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg @ref SMARTCARD_CLEAR_PEF Parity error clear flag
+ * @arg @ref SMARTCARD_CLEAR_FEF Framing error clear flag
+ * @arg @ref SMARTCARD_CLEAR_NEF Noise detected clear flag
+ * @arg @ref SMARTCARD_CLEAR_OREF OverRun error clear flag
+ * @arg @ref SMARTCARD_CLEAR_IDLEF Idle line detected clear flag
+ * @arg @ref SMARTCARD_CLEAR_TCF Transmission complete clear flag
+ * @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag
+ * @arg @ref SMARTCARD_CLEAR_RTOF Receiver timeout clear flag
+ * @arg @ref SMARTCARD_CLEAR_EOBF End of block clear flag
+ * @arg @ref SMARTCARD_CLEAR_TXFECF TXFIFO empty Clear flag
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief Clear the SMARTCARD PE pending flag.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
+
+/** @brief Clear the SMARTCARD FE pending flag.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)
+
+/** @brief Clear the SMARTCARD NE pending flag.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)
+
+/** @brief Clear the SMARTCARD ORE pending flag.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)
+
+/** @brief Clear the SMARTCARD IDLE pending flag.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)
+
+/** @brief Check whether the specified Smartcard flag is set or not.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref SMARTCARD_FLAG_TCBGT Transmission complete before guard time flag (when flag available)
+ * @arg @ref SMARTCARD_FLAG_REACK Receive enable acknowledge flag
+ * @arg @ref SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag
+ * @arg @ref SMARTCARD_FLAG_BUSY Busy flag
+ * @arg @ref SMARTCARD_FLAG_EOBF End of block flag
+ * @arg @ref SMARTCARD_FLAG_RTOF Receiver timeout flag
+ * @arg @ref SMARTCARD_FLAG_TXE Transmit data register empty flag
+ * @arg @ref SMARTCARD_FLAG_TC Transmission complete flag
+ * @arg @ref SMARTCARD_FLAG_RXNE Receive data register not empty flag
+ * @arg @ref SMARTCARD_FLAG_IDLE Idle line detection flag
+ * @arg @ref SMARTCARD_FLAG_ORE Overrun error flag
+ * @arg @ref SMARTCARD_FLAG_NE Noise error flag
+ * @arg @ref SMARTCARD_FLAG_FE Framing error flag
+ * @arg @ref SMARTCARD_FLAG_PE Parity error flag
+ * @arg @ref SMARTCARD_FLAG_TXFNF TXFIFO not full flag
+ * @arg @ref SMARTCARD_FLAG_RXFNE RXFIFO not empty flag
+ * @arg @ref SMARTCARD_FLAG_TXFE TXFIFO Empty flag
+ * @arg @ref SMARTCARD_FLAG_RXFF RXFIFO Full flag
+ * @arg @ref SMARTCARD_FLAG_RXFT SMARTCARD RXFIFO threshold flag
+ * @arg @ref SMARTCARD_FLAG_TXFT SMARTCARD TXFIFO threshold flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Enable the specified SmartCard interrupt.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @param __INTERRUPT__ specifies the SMARTCARD interrupt to enable.
+ * This parameter can be one of the following values:
+ * @arg @ref SMARTCARD_IT_EOB End of block interrupt
+ * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
+ * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
+ * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
+ * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before
+ * guard time interrupt (when interruption available)
+ * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
+ * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
+ * @arg @ref SMARTCARD_IT_PE Parity error interrupt
+ * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
+ * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption
+ * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption
+ * @arg @ref SMARTCARD_IT_RXFF RXFIFO full interruption
+ * @arg @ref SMARTCARD_IT_TXFE TXFIFO empty interruption
+ * @arg @ref SMARTCARD_IT_RXFT RXFIFO threshold reached interruption
+ * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
+ * @retval None
+ */
+#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
+ SMARTCARD_CR_POS) == 1U)?\
+ ((__HANDLE__)->Instance->CR1 |= (1UL <<\
+ ((__INTERRUPT__) & SMARTCARD_IT_MASK))):\
+ ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
+ SMARTCARD_CR_POS) == 2U)?\
+ ((__HANDLE__)->Instance->CR2 |= (1UL <<\
+ ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 |= (1UL <<\
+ ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
+
+/** @brief Disable the specified SmartCard interrupt.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @param __INTERRUPT__ specifies the SMARTCARD interrupt to disable.
+ * This parameter can be one of the following values:
+ * @arg @ref SMARTCARD_IT_EOB End of block interrupt
+ * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
+ * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
+ * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
+ * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard
+ * time interrupt (when interruption available)
+ * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
+ * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
+ * @arg @ref SMARTCARD_IT_PE Parity error interrupt
+ * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
+ * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption
+ * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption
+ * @arg @ref SMARTCARD_IT_RXFF RXFIFO full interruption
+ * @arg @ref SMARTCARD_IT_TXFE TXFIFO empty interruption
+ * @arg @ref SMARTCARD_IT_RXFT RXFIFO threshold reached interruption
+ * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
+ * @retval None
+ */
+#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
+ SMARTCARD_CR_POS) == 1U)?\
+ ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\
+ ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+ ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
+ SMARTCARD_CR_POS) == 2U)?\
+ ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\
+ ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\
+ ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
+
+/** @brief Check whether the specified SmartCard interrupt has occurred or not.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @param __INTERRUPT__ specifies the SMARTCARD interrupt to check.
+ * This parameter can be one of the following values:
+ * @arg @ref SMARTCARD_IT_EOB End of block interrupt
+ * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
+ * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
+ * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
+ * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time
+ * interrupt (when interruption available)
+ * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
+ * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
+ * @arg @ref SMARTCARD_IT_PE Parity error interrupt
+ * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
+ * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption
+ * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption
+ * @arg @ref SMARTCARD_IT_RXFF RXFIFO full interruption
+ * @arg @ref SMARTCARD_IT_TXFE TXFIFO empty interruption
+ * @arg @ref SMARTCARD_IT_RXFT RXFIFO threshold reached interruption
+ * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
+ * @retval The new state of __INTERRUPT__ (SET or RESET).
+ */
+#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) (\
+ (((__HANDLE__)->Instance->ISR & (0x01UL << (((__INTERRUPT__)\
+ & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS)))!= 0U)\
+ ? SET : RESET)
+
+/** @brief Check whether the specified SmartCard interrupt source is enabled or not.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @param __INTERRUPT__ specifies the SMARTCARD interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg @ref SMARTCARD_IT_EOB End of block interrupt
+ * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
+ * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
+ * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
+ * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time
+ * interrupt (when interruption available)
+ * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
+ * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
+ * @arg @ref SMARTCARD_IT_PE Parity error interrupt
+ * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
+ * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption
+ * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption
+ * @arg @ref SMARTCARD_IT_RXFF RXFIFO full interruption
+ * @arg @ref SMARTCARD_IT_TXFE TXFIFO empty interruption
+ * @arg @ref SMARTCARD_IT_RXFT RXFIFO threshold reached interruption
+ * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
+ * @retval The new state of __INTERRUPT__ (SET or RESET).
+ */
+#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
+ SMARTCARD_CR_POS) == 0x01U)?\
+ (__HANDLE__)->Instance->CR1 : \
+ (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
+ SMARTCARD_CR_POS) == 0x02U)?\
+ (__HANDLE__)->Instance->CR2 : \
+ (__HANDLE__)->Instance->CR3)) &\
+ (0x01UL << (((uint16_t)(__INTERRUPT__))\
+ & SMARTCARD_IT_MASK))) != 0U)\
+ ? SET : RESET)
+
+/** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
+ * to clear the corresponding interrupt.
+ * This parameter can be one of the following values:
+ * @arg @ref SMARTCARD_CLEAR_PEF Parity error clear flag
+ * @arg @ref SMARTCARD_CLEAR_FEF Framing error clear flag
+ * @arg @ref SMARTCARD_CLEAR_NEF Noise detected clear flag
+ * @arg @ref SMARTCARD_CLEAR_OREF OverRun error clear flag
+ * @arg @ref SMARTCARD_CLEAR_IDLEF Idle line detection clear flag
+ * @arg @ref SMARTCARD_CLEAR_TXFECF TXFIFO empty Clear Flag
+ * @arg @ref SMARTCARD_CLEAR_TCF Transmission complete clear flag
+ * @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available)
+ * @arg @ref SMARTCARD_CLEAR_RTOF Receiver timeout clear flag
+ * @arg @ref SMARTCARD_CLEAR_EOBF End of block clear flag
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__))
+
+/** @brief Set a specific SMARTCARD request flag.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @param __REQ__ specifies the request flag to set
+ * This parameter can be one of the following values:
+ * @arg @ref SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request
+ * @arg @ref SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request
+ * @retval None
+ */
+#define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
+
+/** @brief Enable the SMARTCARD one bit sample method.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief Disable the SMARTCARD one bit sample method.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
+ &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
+
+/** @brief Enable the USART associated to the SMARTCARD Handle.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+
+/** @brief Disable the USART associated to the SMARTCARD Handle
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+/**
+ * @}
+ */
+
+/* Private macros -------------------------------------------------------------*/
+/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
+ * @{
+ */
+
+/** @brief Report the SMARTCARD clock source.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @param __CLOCKSOURCE__ output variable.
+ * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.
+ */
+#if defined(USART6)
+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK2: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
+ case RCC_USART3CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART3CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART3CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART3CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART6) \
+ { \
+ switch(__HAL_RCC_GET_USART6_SOURCE()) \
+ { \
+ case RCC_USART6CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART6CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART6CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART6CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0U)
+#else
+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK2: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
+ case RCC_USART3CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART3CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART3CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART3CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0U)
+#endif /* USART6 */
+
+/** @brief Check the Baud rate range.
+ * @note The maximum Baud Rate is derived from the maximum clock on U5 (160 MHz)
+ * divided by the oversampling used on the SMARTCARD (i.e. 16).
+ * @param __BAUDRATE__ Baud rate set by the configuration function.
+ * @retval Test result (TRUE or FALSE)
+ */
+#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 10000000U)
+
+/** @brief Check the block length range.
+ * @note The maximum SMARTCARD block length is 0xFF.
+ * @param __LENGTH__ block length.
+ * @retval Test result (TRUE or FALSE)
+ */
+#define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFFU)
+
+/** @brief Check the receiver timeout value.
+ * @note The maximum SMARTCARD receiver timeout value is 0xFFFFFF.
+ * @param __TIMEOUTVALUE__ receiver timeout value.
+ * @retval Test result (TRUE or FALSE)
+ */
+#define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
+
+/** @brief Check the SMARTCARD autoretry counter value.
+ * @note The maximum number of retransmissions is 0x7.
+ * @param __COUNT__ number of retransmissions.
+ * @retval Test result (TRUE or FALSE)
+ */
+#define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7U)
+
+/** @brief Ensure that SMARTCARD frame length is valid.
+ * @param __LENGTH__ SMARTCARD frame length.
+ * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+ */
+#define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
+
+/** @brief Ensure that SMARTCARD frame number of stop bits is valid.
+ * @param __STOPBITS__ SMARTCARD frame number of stop bits.
+ * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
+ */
+#define IS_SMARTCARD_STOPBITS(__STOPBITS__) (((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\
+ ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5))
+
+/** @brief Ensure that SMARTCARD frame parity is valid.
+ * @param __PARITY__ SMARTCARD frame parity.
+ * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+ */
+#define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \
+ ((__PARITY__) == SMARTCARD_PARITY_ODD))
+
+/** @brief Ensure that SMARTCARD communication mode is valid.
+ * @param __MODE__ SMARTCARD communication mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & 0xFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
+
+/** @brief Ensure that SMARTCARD frame polarity is valid.
+ * @param __CPOL__ SMARTCARD frame polarity.
+ * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
+ */
+#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW)\
+ || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
+
+/** @brief Ensure that SMARTCARD frame phase is valid.
+ * @param __CPHA__ SMARTCARD frame phase.
+ * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
+ */
+#define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
+
+/** @brief Ensure that SMARTCARD frame last bit clock pulse setting is valid.
+ * @param __LASTBIT__ SMARTCARD frame last bit clock pulse setting.
+ * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
+ */
+#define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \
+ ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE))
+
+/** @brief Ensure that SMARTCARD frame sampling is valid.
+ * @param __ONEBIT__ SMARTCARD frame sampling.
+ * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
+ */
+#define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \
+ ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE))
+
+/** @brief Ensure that SMARTCARD NACK transmission setting is valid.
+ * @param __NACK__ SMARTCARD NACK transmission setting.
+ * @retval SET (__NACK__ is valid) or RESET (__NACK__ is invalid)
+ */
+#define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \
+ ((__NACK__) == SMARTCARD_NACK_DISABLE))
+
+/** @brief Ensure that SMARTCARD receiver timeout setting is valid.
+ * @param __TIMEOUT__ SMARTCARD receiver timeout setting.
+ * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
+ */
+#define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \
+ ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE))
+
+/** @brief Ensure that SMARTCARD clock Prescaler is valid.
+ * @param __CLOCKPRESCALER__ SMARTCARD clock Prescaler value.
+ * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
+ */
+#define IS_SMARTCARD_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV1) || \
+ ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV2) || \
+ ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV4) || \
+ ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV6) || \
+ ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV8) || \
+ ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV10) || \
+ ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV12) || \
+ ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV16) || \
+ ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV32) || \
+ ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV64) || \
+ ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV128) || \
+ ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV256))
+
+/** @brief Ensure that SMARTCARD advanced features initialization is valid.
+ * @param __INIT__ SMARTCARD advanced features initialization.
+ * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT | \
+ SMARTCARD_ADVFEATURE_TXINVERT_INIT | \
+ SMARTCARD_ADVFEATURE_RXINVERT_INIT | \
+ SMARTCARD_ADVFEATURE_DATAINVERT_INIT | \
+ SMARTCARD_ADVFEATURE_SWAP_INIT | \
+ SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT | \
+ SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \
+ SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
+
+/** @brief Ensure that SMARTCARD frame TX inversion setting is valid.
+ * @param __TXINV__ SMARTCARD frame TX inversion setting.
+ * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \
+ ((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))
+
+/** @brief Ensure that SMARTCARD frame RX inversion setting is valid.
+ * @param __RXINV__ SMARTCARD frame RX inversion setting.
+ * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \
+ ((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))
+
+/** @brief Ensure that SMARTCARD frame data inversion setting is valid.
+ * @param __DATAINV__ SMARTCARD frame data inversion setting.
+ * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \
+ ((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))
+
+/** @brief Ensure that SMARTCARD frame RX/TX pins swap setting is valid.
+ * @param __SWAP__ SMARTCARD frame RX/TX pins swap setting.
+ * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \
+ ((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))
+
+/** @brief Ensure that SMARTCARD frame overrun setting is valid.
+ * @param __OVERRUN__ SMARTCARD frame overrun setting.
+ * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
+ */
+#define IS_SMARTCARD_OVERRUN(__OVERRUN__) (((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \
+ ((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))
+
+/** @brief Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.
+ * @param __DMA__ SMARTCARD DMA enabling or disabling on error setting.
+ * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \
+ ((__DMA__) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))
+
+/** @brief Ensure that SMARTCARD frame MSB first setting is valid.
+ * @param __MSBFIRST__ SMARTCARD frame MSB first setting.
+ * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \
+ ((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))
+
+/** @brief Ensure that SMARTCARD request parameter is valid.
+ * @param __PARAM__ SMARTCARD request parameter.
+ * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+ */
+#define IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \
+ ((__PARAM__) == SMARTCARD_TXDATA_FLUSH_REQUEST))
+
+/**
+ * @}
+ */
+
+/* Include SMARTCARD HAL Extended module */
+#include "stm32u5xx_hal_smartcard_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMARTCARD_Exported_Functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+/** @addtogroup SMARTCARD_Exported_Functions_Group1
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard);
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+/* Callbacks Register/UnRegister functions ***********************************/
+HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
+ HAL_SMARTCARD_CallbackIDTypeDef CallbackID,
+ pSMARTCARD_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
+ HAL_SMARTCARD_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/* IO operation functions *****************************************************/
+/** @addtogroup SMARTCARD_Exported_Functions_Group2
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+
+void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+
+/**
+ * @}
+ */
+
+/* Peripheral State and Error functions ***************************************/
+/** @addtogroup SMARTCARD_Exported_Functions_Group4
+ * @{
+ */
+
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard);
+uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_SMARTCARD_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_smartcard_ex.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_smartcard_ex.h
new file mode 100644
index 00000000..4470cbd5
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_smartcard_ex.h
@@ -0,0 +1,335 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_smartcard_ex.h
+ * @author MCD Application Team
+ * @brief Header file of SMARTCARD HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_SMARTCARD_EX_H
+#define STM32U5xx_HAL_SMARTCARD_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SMARTCARDEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @addtogroup SMARTCARDEx_Exported_Constants SMARTCARD Extended Exported Constants
+ * @{
+ */
+
+/** @defgroup SMARTCARDEx_Transmission_Completion_Indication SMARTCARD Transmission Completion Indication
+ * @{
+ */
+#define SMARTCARD_TCBGT SMARTCARD_IT_TCBGT /*!< SMARTCARD transmission complete before guard time */
+#define SMARTCARD_TC SMARTCARD_IT_TC /*!< SMARTCARD transmission complete (flag raised when guard time has elapsed) */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARDEx_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */
+#define SMARTCARD_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */
+#define SMARTCARD_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */
+#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */
+#define SMARTCARD_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */
+#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */
+#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */
+#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */
+#define SMARTCARD_ADVFEATURE_TXCOMPLETION 0x00000100U /*!< TX completion indication before of after guard time */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARDEx_FIFO_mode SMARTCARD FIFO mode
+ * @brief SMARTCARD FIFO mode
+ * @{
+ */
+#define SMARTCARD_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */
+#define SMARTCARD_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARDEx_TXFIFO_threshold_level SMARTCARD TXFIFO threshold level
+ * @brief SMARTCARD TXFIFO level
+ * @{
+ */
+#define SMARTCARD_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */
+#define SMARTCARD_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */
+#define SMARTCARD_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */
+#define SMARTCARD_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */
+#define SMARTCARD_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */
+#define SMARTCARD_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARDEx_RXFIFO_threshold_level SMARTCARD RXFIFO threshold level
+ * @brief SMARTCARD RXFIFO level
+ * @{
+ */
+#define SMARTCARD_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */
+#define SMARTCARD_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RXFIFO FIFO reaches 1/4 of its depth */
+#define SMARTCARD_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RXFIFO FIFO reaches 1/2 of its depth */
+#define SMARTCARD_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */
+#define SMARTCARD_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RXFIFO FIFO reaches 7/8 of its depth */
+#define SMARTCARD_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARDEx_Flags SMARTCARD Flags
+ * Elements values convention: 0xXXXX
+ * - 0xXXXX : Flag mask in the ISR register
+ * @{
+ */
+#define SMARTCARD_FLAG_TCBGT USART_ISR_TCBGT /*!< SMARTCARD transmission complete before guard time completion */
+#define SMARTCARD_FLAG_REACK USART_ISR_REACK /*!< SMARTCARD receive enable acknowledge flag */
+#define SMARTCARD_FLAG_TEACK USART_ISR_TEACK /*!< SMARTCARD transmit enable acknowledge flag */
+#define SMARTCARD_FLAG_BUSY USART_ISR_BUSY /*!< SMARTCARD busy flag */
+#define SMARTCARD_FLAG_EOBF USART_ISR_EOBF /*!< SMARTCARD end of block flag */
+#define SMARTCARD_FLAG_RTOF USART_ISR_RTOF /*!< SMARTCARD receiver timeout flag */
+#define SMARTCARD_FLAG_TXE USART_ISR_TXE_TXFNF /*!< SMARTCARD transmit data register empty */
+#define SMARTCARD_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< SMARTCARD TXFIFO not full */
+#define SMARTCARD_FLAG_TC USART_ISR_TC /*!< SMARTCARD transmission complete */
+#define SMARTCARD_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< SMARTCARD read data register not empty */
+#define SMARTCARD_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< SMARTCARD RXFIFO not empty */
+#define SMARTCARD_FLAG_IDLE USART_ISR_IDLE /*!< SMARTCARD idle line detection */
+#define SMARTCARD_FLAG_ORE USART_ISR_ORE /*!< SMARTCARD overrun error */
+#define SMARTCARD_FLAG_NE USART_ISR_NE /*!< SMARTCARD noise error */
+#define SMARTCARD_FLAG_FE USART_ISR_FE /*!< SMARTCARD frame error */
+#define SMARTCARD_FLAG_PE USART_ISR_PE /*!< SMARTCARD parity error */
+#define SMARTCARD_FLAG_TXFE USART_ISR_TXFE /*!< SMARTCARD TXFIFO Empty flag */
+#define SMARTCARD_FLAG_RXFF USART_ISR_RXFF /*!< SMARTCARD RXFIFO Full flag */
+#define SMARTCARD_FLAG_RXFT USART_ISR_RXFT /*!< SMARTCARD RXFIFO threshold flag */
+#define SMARTCARD_FLAG_TXFT USART_ISR_TXFT /*!< SMARTCARD TXFIFO threshold flag */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARDEx_Interrupt_definition SMARTCARD Interrupts Definition
+ * Elements values convention: 000ZZZZZ0XXYYYYYb
+ * - YYYYY : Interrupt source position in the XX register (5 bits)
+ * - XX : Interrupt source register (2 bits)
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
+ * - ZZZZZ : Flag position in the ISR register(5 bits)
+ * @{
+ */
+#define SMARTCARD_IT_PE 0x0028U /*!< SMARTCARD parity error interruption */
+#define SMARTCARD_IT_TXE 0x0727U /*!< SMARTCARD transmit data register empty interruption */
+#define SMARTCARD_IT_TXFNF 0x0727U /*!< SMARTCARD TX FIFO not full interruption */
+#define SMARTCARD_IT_TC 0x0626U /*!< SMARTCARD transmission complete interruption */
+#define SMARTCARD_IT_RXNE 0x0525U /*!< SMARTCARD read data register not empty interruption */
+#define SMARTCARD_IT_RXFNE 0x0525U /*!< SMARTCARD RXFIFO not empty interruption */
+#define SMARTCARD_IT_IDLE 0x0424U /*!< SMARTCARD idle line detection interruption */
+
+#define SMARTCARD_IT_ERR 0x0060U /*!< SMARTCARD error interruption */
+#define SMARTCARD_IT_ORE 0x0300U /*!< SMARTCARD overrun error interruption */
+#define SMARTCARD_IT_NE 0x0200U /*!< SMARTCARD noise error interruption */
+#define SMARTCARD_IT_FE 0x0100U /*!< SMARTCARD frame error interruption */
+
+#define SMARTCARD_IT_EOB 0x0C3BU /*!< SMARTCARD end of block interruption */
+#define SMARTCARD_IT_RTO 0x0B3AU /*!< SMARTCARD receiver timeout interruption */
+#define SMARTCARD_IT_TCBGT 0x1978U /*!< SMARTCARD transmission complete before guard time completion interruption */
+
+#define SMARTCARD_IT_RXFF 0x183FU /*!< SMARTCARD RXFIFO full interruption */
+#define SMARTCARD_IT_TXFE 0x173EU /*!< SMARTCARD TXFIFO empty interruption */
+#define SMARTCARD_IT_RXFT 0x1A7CU /*!< SMARTCARD RXFIFO threshold reached interruption */
+#define SMARTCARD_IT_TXFT 0x1B77U /*!< SMARTCARD TXFIFO threshold reached interruption */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARDEx_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags
+ * @{
+ */
+#define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< SMARTCARD parity error clear flag */
+#define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< SMARTCARD framing error clear flag */
+#define SMARTCARD_CLEAR_NEF USART_ICR_NECF /*!< SMARTCARD noise error detected clear flag */
+#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< SMARTCARD overrun error clear flag */
+#define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF /*!< SMARTCARD idle line detected clear flag */
+#define SMARTCARD_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO empty Clear Flag */
+#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< SMARTCARD transmission complete clear flag */
+#define SMARTCARD_CLEAR_TCBGTF USART_ICR_TCBGTCF /*!< SMARTCARD transmission complete before guard time completion clear flag */
+#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< SMARTCARD receiver time out clear flag */
+#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< SMARTCARD end of block clear flag */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Exported macros -----------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SMARTCARDEx_Private_Macros SMARTCARD Extended Private Macros
+ * @{
+ */
+
+/** @brief Set the Transmission Completion flag
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @note If TCBGT (Transmission Complete Before Guard Time) flag is not available or if
+ * AdvancedInit.TxCompletionIndication is not already filled, the latter is forced
+ * to SMARTCARD_TC (transmission completion indication when guard time has elapsed).
+ * @retval None
+ */
+#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__) \
+ do { \
+ if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION)) \
+ { \
+ (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \
+ } \
+ else \
+ { \
+ assert_param(IS_SMARTCARD_TRANSMISSION_COMPLETION((__HANDLE__)->AdvancedInit.TxCompletionIndication)); \
+ } \
+ } while(0U)
+
+/** @brief Return the transmission completion flag.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @note Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag.
+ * When TCBGT flag (Transmission Complete Before Guard Time) is not available, TC flag is
+ * reported.
+ * @retval Transmission completion flag
+ */
+#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) \
+ (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) : (SMARTCARD_FLAG_TCBGT))
+
+
+/** @brief Ensure that SMARTCARD frame transmission completion used flag is valid.
+ * @param __TXCOMPLETE__ SMARTCARD frame transmission completion used flag.
+ * @retval SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid)
+ */
+#define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) (((__TXCOMPLETE__) == SMARTCARD_TCBGT) || \
+ ((__TXCOMPLETE__) == SMARTCARD_TC))
+
+/** @brief Ensure that SMARTCARD FIFO mode is valid.
+ * @param __STATE__ SMARTCARD FIFO mode.
+ * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
+ */
+#define IS_SMARTCARD_FIFOMODE_STATE(__STATE__) (((__STATE__) == SMARTCARD_FIFOMODE_DISABLE ) || \
+ ((__STATE__) == SMARTCARD_FIFOMODE_ENABLE))
+
+/** @brief Ensure that SMARTCARD TXFIFO threshold level is valid.
+ * @param __THRESHOLD__ SMARTCARD TXFIFO threshold level.
+ * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
+ */
+#define IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_8) || \
+ ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_4) || \
+ ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_2) || \
+ ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3_4) || \
+ ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7_8) || \
+ ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_8_8))
+
+/** @brief Ensure that SMARTCARD RXFIFO threshold level is valid.
+ * @param __THRESHOLD__ SMARTCARD RXFIFO threshold level.
+ * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
+ */
+#define IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_8) || \
+ ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_4) || \
+ ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_2) || \
+ ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3_4) || \
+ ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7_8) || \
+ ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_8_8))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMARTCARDEx_Exported_Functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+/* IO operation methods *******************************************************/
+
+/** @addtogroup SMARTCARDEx_Exported_Functions_Group1
+ * @{
+ */
+
+/* Peripheral Control functions ***********************************************/
+void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength);
+void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue);
+HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMARTCARDEx_Exported_Functions_Group2
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+void HAL_SMARTCARDEx_RxFifoFullCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARDEx_TxFifoEmptyCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+
+/**
+ * @}
+ */
+
+/** @addtogroup SMARTCARDEx_Exported_Functions_Group3
+ * @{
+ */
+
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold);
+HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_SMARTCARD_EX_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_smbus.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_smbus.h
new file mode 100644
index 00000000..e231b8f6
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_smbus.h
@@ -0,0 +1,755 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_smbus.h
+ * @author MCD Application Team
+ * @brief Header file of SMBUS HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_SMBUS_H
+#define STM32U5xx_HAL_SMBUS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SMBUS
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SMBUS_Exported_Types SMBUS Exported Types
+ * @{
+ */
+
+/** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition
+ * @brief SMBUS Configuration Structure definition
+ * @{
+ */
+typedef struct
+{
+ uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value.
+ This parameter calculated by referring to SMBUS initialization
+ section in Reference manual */
+ uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not.
+ This parameter can be a value of @ref SMBUS_Analog_Filter */
+
+ uint32_t OwnAddress1; /*!< Specifies the first device own address.
+ This parameter can be a 7-bit address. */
+
+ uint32_t AddressingMode; /*!< Specifies addressing mode selected.
+ This parameter can be a value of @ref SMBUS_addressing_mode */
+
+ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
+ This parameter can be a value of @ref SMBUS_dual_addressing_mode */
+
+ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
+ This parameter can be a 7-bit address. */
+
+ uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
+ This parameter can be a value of @ref SMBUS_own_address2_masks. */
+
+ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
+ This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
+
+ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
+ This parameter can be a value of @ref SMBUS_nostretch_mode */
+
+ uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected.
+ This parameter can be a value of @ref SMBUS_packet_error_check_mode */
+
+ uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected.
+ This parameter can be a value of @ref SMBUS_peripheral_mode */
+
+ uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
+ (Enable bits and different timeout values)
+ This parameter calculated by referring to SMBUS initialization
+ section in Reference manual */
+} SMBUS_InitTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HAL_state_definition HAL state definition
+ * @brief HAL State definition
+ * @{
+ */
+#define HAL_SMBUS_STATE_RESET (0x00000000U) /*!< SMBUS not yet initialized or disabled */
+#define HAL_SMBUS_STATE_READY (0x00000001U) /*!< SMBUS initialized and ready for use */
+#define HAL_SMBUS_STATE_BUSY (0x00000002U) /*!< SMBUS internal process is ongoing */
+#define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */
+#define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */
+#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */
+#define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */
+#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */
+#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */
+#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition
+ * @brief SMBUS Error Code definition
+ * @{
+ */
+#define HAL_SMBUS_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_SMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */
+#define HAL_SMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */
+#define HAL_SMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */
+#define HAL_SMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */
+#define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */
+#define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */
+#define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */
+#define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+#define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+#define HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition
+ * @brief SMBUS handle Structure definition
+ * @{
+ */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+typedef struct __SMBUS_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+{
+ I2C_TypeDef *Instance; /*!< SMBUS registers base address */
+
+ SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */
+
+ uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */
+
+ uint16_t XferSize; /*!< SMBUS transfer size */
+
+ __IO uint16_t XferCount; /*!< SMBUS transfer counter */
+
+ __IO uint32_t XferOptions; /*!< SMBUS transfer options */
+
+ __IO uint32_t PreviousState; /*!< SMBUS communication Previous state */
+
+ HAL_LockTypeDef Lock; /*!< SMBUS locking object */
+
+ __IO uint32_t State; /*!< SMBUS communication state */
+
+ __IO uint32_t ErrorCode; /*!< SMBUS Error code */
+
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Tx Transfer completed callback */
+ void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Rx Transfer completed callback */
+ void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Slave Tx Transfer completed callback */
+ void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Slave Rx Transfer completed callback */
+ void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Listen Complete callback */
+ void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Error callback */
+
+ void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< SMBUS Slave Address Match callback */
+
+ void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Msp Init callback */
+ void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Msp DeInit callback */
+
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+} SMBUS_HandleTypeDef;
+
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL SMBUS Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< SMBUS Master Tx Transfer completed callback ID */
+ HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< SMBUS Master Rx Transfer completed callback ID */
+ HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< SMBUS Slave Tx Transfer completed callback ID */
+ HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< SMBUS Slave Rx Transfer completed callback ID */
+ HAL_SMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< SMBUS Listen Complete callback ID */
+ HAL_SMBUS_ERROR_CB_ID = 0x05U, /*!< SMBUS Error callback ID */
+
+ HAL_SMBUS_MSPINIT_CB_ID = 0x06U, /*!< SMBUS Msp Init callback ID */
+ HAL_SMBUS_MSPDEINIT_CB_ID = 0x07U /*!< SMBUS Msp DeInit callback ID */
+
+} HAL_SMBUS_CallbackIDTypeDef;
+
+/**
+ * @brief HAL SMBUS Callback pointer definition
+ */
+typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus); /*!< pointer to an SMBUS callback function */
+typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an SMBUS Address Match callback function */
+
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants
+ * @{
+ */
+
+/** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
+ * @{
+ */
+#define SMBUS_ANALOGFILTER_ENABLE (0x00000000U)
+#define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_addressing_mode SMBUS addressing mode
+ * @{
+ */
+#define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U)
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode
+ * @{
+ */
+
+#define SMBUS_DUALADDRESS_DISABLE (0x00000000U)
+#define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks
+ * @{
+ */
+
+#define SMBUS_OA2_NOMASK ((uint8_t)0x00U)
+#define SMBUS_OA2_MASK01 ((uint8_t)0x01U)
+#define SMBUS_OA2_MASK02 ((uint8_t)0x02U)
+#define SMBUS_OA2_MASK03 ((uint8_t)0x03U)
+#define SMBUS_OA2_MASK04 ((uint8_t)0x04U)
+#define SMBUS_OA2_MASK05 ((uint8_t)0x05U)
+#define SMBUS_OA2_MASK06 ((uint8_t)0x06U)
+#define SMBUS_OA2_MASK07 ((uint8_t)0x07U)
+/**
+ * @}
+ */
+
+
+/** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode
+ * @{
+ */
+#define SMBUS_GENERALCALL_DISABLE (0x00000000U)
+#define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode
+ * @{
+ */
+#define SMBUS_NOSTRETCH_DISABLE (0x00000000U)
+#define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode
+ * @{
+ */
+#define SMBUS_PEC_DISABLE (0x00000000U)
+#define SMBUS_PEC_ENABLE I2C_CR1_PECEN
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode
+ * @{
+ */
+#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN
+#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U)
+#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition
+ * @{
+ */
+
+#define SMBUS_SOFTEND_MODE (0x00000000U)
+#define SMBUS_RELOAD_MODE I2C_CR2_RELOAD
+#define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND
+#define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition
+ * @{
+ */
+
+#define SMBUS_NO_STARTSTOP (0x00000000U)
+#define SMBUS_GENERATE_NO_START_READ (uint32_t)(0x80000000U | I2C_CR2_RD_WRN)
+#define SMBUS_GENERATE_NO_START_WRITE (uint32_t)(0x80000000U)
+#define SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
+#define SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
+#define SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition
+ * @{
+ */
+
+/* List of XferOptions in usage of :
+ * 1- Restart condition when direction change
+ * 2- No Restart condition in other use cases
+ */
+#define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE
+#define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
+#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
+#define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
+#define SMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(SMBUS_SOFTEND_MODE | SMBUS_SENDPEC_MODE))
+#define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
+#define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
+
+/* List of XferOptions in usage of :
+ * 1- Restart condition in all use cases (direction change or not)
+ */
+#define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)
+#define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)
+#define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)
+#define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition
+ * @brief SMBUS Interrupt definition
+ * Elements values convention: 0xXXXXXXXX
+ * - XXXXXXXX : Interrupt control mask
+ * @{
+ */
+#define SMBUS_IT_ERRI I2C_CR1_ERRIE
+#define SMBUS_IT_TCI I2C_CR1_TCIE
+#define SMBUS_IT_STOPI I2C_CR1_STOPIE
+#define SMBUS_IT_NACKI I2C_CR1_NACKIE
+#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE
+#define SMBUS_IT_RXI I2C_CR1_RXIE
+#define SMBUS_IT_TXI I2C_CR1_TXIE
+#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
+#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
+#define SMBUS_IT_ALERT (SMBUS_IT_ERRI)
+#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_Flag_definition SMBUS Flag definition
+ * @brief Flag definition
+ * Elements values convention: 0xXXXXYYYY
+ * - XXXXXXXX : Flag mask
+ * @{
+ */
+
+#define SMBUS_FLAG_TXE I2C_ISR_TXE
+#define SMBUS_FLAG_TXIS I2C_ISR_TXIS
+#define SMBUS_FLAG_RXNE I2C_ISR_RXNE
+#define SMBUS_FLAG_ADDR I2C_ISR_ADDR
+#define SMBUS_FLAG_AF I2C_ISR_NACKF
+#define SMBUS_FLAG_STOPF I2C_ISR_STOPF
+#define SMBUS_FLAG_TC I2C_ISR_TC
+#define SMBUS_FLAG_TCR I2C_ISR_TCR
+#define SMBUS_FLAG_BERR I2C_ISR_BERR
+#define SMBUS_FLAG_ARLO I2C_ISR_ARLO
+#define SMBUS_FLAG_OVR I2C_ISR_OVR
+#define SMBUS_FLAG_PECERR I2C_ISR_PECERR
+#define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT
+#define SMBUS_FLAG_ALERT I2C_ISR_ALERT
+#define SMBUS_FLAG_BUSY I2C_ISR_BUSY
+#define SMBUS_FLAG_DIR I2C_ISR_DIR
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros ------------------------------------------------------------*/
+/** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros
+ * @{
+ */
+
+/** @brief Reset SMBUS handle state.
+ * @param __HANDLE__ specifies the SMBUS Handle.
+ * @retval None
+ */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
+#endif /*USE_HAL_SMBUS_REGISTER_CALLBACKS*/
+
+/** @brief Enable the specified SMBUS interrupts.
+ * @param __HANDLE__ specifies the SMBUS Handle.
+ * @param __INTERRUPT__ specifies the interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg @ref SMBUS_IT_ERRI Errors interrupt enable
+ * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
+ * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
+ * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
+ * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
+ * @arg @ref SMBUS_IT_RXI RX interrupt enable
+ * @arg @ref SMBUS_IT_TXI TX interrupt enable
+ *
+ * @retval None
+ */
+#define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
+
+/** @brief Disable the specified SMBUS interrupts.
+ * @param __HANDLE__ specifies the SMBUS Handle.
+ * @param __INTERRUPT__ specifies the interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg @ref SMBUS_IT_ERRI Errors interrupt enable
+ * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
+ * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
+ * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
+ * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
+ * @arg @ref SMBUS_IT_RXI RX interrupt enable
+ * @arg @ref SMBUS_IT_TXI TX interrupt enable
+ *
+ * @retval None
+ */
+#define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
+
+/** @brief Check whether the specified SMBUS interrupt source is enabled or not.
+ * @param __HANDLE__ specifies the SMBUS Handle.
+ * @param __INTERRUPT__ specifies the SMBUS interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg @ref SMBUS_IT_ERRI Errors interrupt enable
+ * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
+ * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
+ * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
+ * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
+ * @arg @ref SMBUS_IT_RXI RX interrupt enable
+ * @arg @ref SMBUS_IT_TXI TX interrupt enable
+ *
+ * @retval The new state of __IT__ (SET or RESET).
+ */
+#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \
+ (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Check whether the specified SMBUS flag is set or not.
+ * @param __HANDLE__ specifies the SMBUS Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref SMBUS_FLAG_TXE Transmit data register empty
+ * @arg @ref SMBUS_FLAG_TXIS Transmit interrupt status
+ * @arg @ref SMBUS_FLAG_RXNE Receive data register not empty
+ * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode)
+ * @arg @ref SMBUS_FLAG_AF NACK received flag
+ * @arg @ref SMBUS_FLAG_STOPF STOP detection flag
+ * @arg @ref SMBUS_FLAG_TC Transfer complete (master mode)
+ * @arg @ref SMBUS_FLAG_TCR Transfer complete reload
+ * @arg @ref SMBUS_FLAG_BERR Bus error
+ * @arg @ref SMBUS_FLAG_ARLO Arbitration lost
+ * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun
+ * @arg @ref SMBUS_FLAG_PECERR PEC error in reception
+ * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
+ * @arg @ref SMBUS_FLAG_ALERT SMBus alert
+ * @arg @ref SMBUS_FLAG_BUSY Bus busy
+ * @arg @ref SMBUS_FLAG_DIR Transfer direction (slave mode)
+ *
+ * @retval The new state of __FLAG__ (SET or RESET).
+ */
+#define SMBUS_FLAG_MASK (0x0001FFFFU)
+#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \
+ ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & \
+ SMBUS_FLAG_MASK)) ? SET : RESET)
+
+/** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
+ * @param __HANDLE__ specifies the SMBUS Handle.
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode)
+ * @arg @ref SMBUS_FLAG_AF NACK received flag
+ * @arg @ref SMBUS_FLAG_STOPF STOP detection flag
+ * @arg @ref SMBUS_FLAG_BERR Bus error
+ * @arg @ref SMBUS_FLAG_ARLO Arbitration lost
+ * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun
+ * @arg @ref SMBUS_FLAG_PECERR PEC error in reception
+ * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
+ * @arg @ref SMBUS_FLAG_ALERT SMBus alert
+ *
+ * @retval None
+ */
+#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief Enable the specified SMBUS peripheral.
+ * @param __HANDLE__ specifies the SMBUS Handle.
+ * @retval None
+ */
+#define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+
+/** @brief Disable the specified SMBUS peripheral.
+ * @param __HANDLE__ specifies the SMBUS Handle.
+ * @retval None
+ */
+#define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+
+/** @brief Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
+ * @param __HANDLE__ specifies the SMBUS Handle.
+ * @retval None
+ */
+#define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
+
+/**
+ * @}
+ */
+
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SMBUS_Private_Macro SMBUS Private Macros
+ * @{
+ */
+
+#define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
+ ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
+
+#define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
+
+#define IS_SMBUS_ADDRESSING_MODE(MODE) ((MODE) == SMBUS_ADDRESSINGMODE_7BIT)
+
+#define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
+ ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
+
+#define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \
+ ((MASK) == SMBUS_OA2_MASK01) || \
+ ((MASK) == SMBUS_OA2_MASK02) || \
+ ((MASK) == SMBUS_OA2_MASK03) || \
+ ((MASK) == SMBUS_OA2_MASK04) || \
+ ((MASK) == SMBUS_OA2_MASK05) || \
+ ((MASK) == SMBUS_OA2_MASK06) || \
+ ((MASK) == SMBUS_OA2_MASK07))
+
+#define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \
+ ((CALL) == SMBUS_GENERALCALL_ENABLE))
+
+#define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
+ ((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
+
+#define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \
+ ((PEC) == SMBUS_PEC_ENABLE))
+
+#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \
+ ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
+ ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
+
+#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \
+ ((MODE) == SMBUS_AUTOEND_MODE) || \
+ ((MODE) == SMBUS_SOFTEND_MODE) || \
+ ((MODE) == SMBUS_SENDPEC_MODE) || \
+ ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \
+ ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \
+ ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \
+ ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))
+
+
+#define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \
+ ((REQUEST) == SMBUS_GENERATE_START_READ) || \
+ ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \
+ ((REQUEST) == SMBUS_NO_STARTSTOP))
+
+
+#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \
+ ((REQUEST) == SMBUS_FIRST_FRAME) || \
+ ((REQUEST) == SMBUS_NEXT_FRAME) || \
+ ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
+ ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
+ ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \
+ ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
+ ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
+
+#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \
+ ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \
+ ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \
+ ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
+
+#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | \
+ I2C_CR1_SMBDEN | \
+ I2C_CR1_PECEN)))
+#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | \
+ I2C_CR2_HEAD10R | \
+ I2C_CR2_NBYTES | \
+ I2C_CR2_RELOAD | \
+ I2C_CR2_RD_WRN)))
+
+#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? \
+ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
+ (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
+ (~I2C_CR2_RD_WRN)) : \
+ (uint32_t)((((uint32_t)(__ADDRESS__) & \
+ (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | \
+ (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
+
+#define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
+#define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
+#define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
+#define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
+#define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
+
+#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
+ ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
+#define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
+
+#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
+#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
+
+/**
+ * @}
+ */
+#include "stm32u5xx_hal_smbus_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
+ * @{
+ */
+
+/** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter);
+HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID,
+ pSMBUS_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+/******* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials,
+ uint32_t Timeout);
+
+/******* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
+HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions);
+
+HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
+/**
+ * @}
+ */
+
+/** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+/******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
+void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
+void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
+
+/**
+ * @}
+ */
+
+/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @{
+ */
+
+/* Peripheral State and Errors functions **************************************************/
+uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
+uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
+
+/**
+ * @}
+ */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup SMBUS_Private_Functions SMBUS Private Functions
+ * @{
+ */
+/* Private functions are defined in stm32u5xx_hal_smbus.c file */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32U5xx_HAL_SMBUS_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_smbus_ex.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_smbus_ex.h
new file mode 100644
index 00000000..c8ff32aa
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_smbus_ex.h
@@ -0,0 +1,287 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_smbus_ex.h
+ * @author MCD Application Team
+ * @brief Header file of SMBUS HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_SMBUS_EX_H
+#define STM32U5xx_HAL_SMBUS_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SMBUSEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SMBUS_Exported_Types SMBUS Exported Types
+ * @{
+ */
+
+/** @defgroup SMBUS_Autonomous_Mode_Configuration_Structure_definition SMBUS Autonomous Mode Configuration
+ Structure definition.
+ * @brief SMBUS Autonomous Mode Configuration structure definition
+ * @{
+ */
+typedef struct
+{
+ uint32_t TriggerState; /*!< Specifies the trigger state. This parameter can be a value
+ of @ref SMBUSEx_AutonomousMode_FunctionalState */
+
+ uint32_t TriggerSelection; /*!< Specifies the autonomous mode trigger signal selection. This parameter
+ can be a value of @ref SMBUSEx_AutonomousMode_TriggerSelection */
+
+ uint32_t TriggerPolarity; /*!< Specifies the autonomous mode trigger signal polarity sensitivity. This parameter
+ can be a value of @ref SMBUSEx_AutonomousMode_TriggerPolarity */
+
+} SMBUS_AutonomousModeConfTypeDef;
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SMBUSEx_Exported_Constants SMBUS Extended Exported Constants
+ * @{
+ */
+
+/** @defgroup SMBUSEx_FastModePlus SMBUS Extended Fast Mode Plus
+ * @{
+ */
+#define SMBUS_FASTMODEPLUS_ENABLE 0x00000000U /*!< Enable Fast Mode Plus */
+#define SMBUS_FASTMODEPLUS_DISABLE 0x00000001U /*!< Disable Fast Mode Plus */
+/**
+ * @}
+ */
+
+/** @defgroup SMBUSEx_AutonomousMode_FunctionalState SMBUS Extended Autonomous Mode State
+ * @{
+ */
+#define SMBUS_AUTO_MODE_DISABLE (0x00000000U) /* Autonomous mode disable */
+#define SMBUS_AUTO_MODE_ENABLE I2C_AUTOCR_TRIGEN /* Autonomous mode enable */
+/**
+ * @}
+ */
+
+/** @defgroup SMBUSEx_AutonomousMode_TriggerSelection SMBUS Extended Autonomous Mode Trigger Selection
+ * @{
+ */
+#define SMBUS_TRIG_GRP1 (0x10000000U) /* Trigger Group for I2C1, I2C2 and I2C4 */
+#define SMBUS_TRIG_GRP2 (0x20000000U) /* Trigger Group for I2C3 */
+
+/* HW Trigger signal is GPDMA_CH0_TRG */
+#define SMBUS_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x00000000U))
+/* HW Trigger signal is GPDMA_CH1_TRG */
+#define SMBUS_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is GPDMA_CH2_TRG */
+#define SMBUS_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is GPDMA_CH3_TRG */
+#define SMBUS_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is EXTI5_TRG */
+#define SMBUS_GRP1_EXTI5_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is EXTI9_TRG */
+#define SMBUS_GRP1_EXTI9_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is LPTIM1_CH1_TRG */
+#define SMBUS_GRP1_LPTIM1_CH1_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is LPTIM2_CH1_TRG */
+#define SMBUS_GRP1_LPTIM2_CH1_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is COMP1_TRG */
+#define SMBUS_GRP1_COMP1_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is COMP2_TRG */
+#define SMBUS_GRP1_COMP2_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is RTC_ALRA_TRG */
+#define SMBUS_GRP1_RTC_ALRA_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is RTC_WUT_TRG */
+#define SMBUS_GRP1_RTC_WUT_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos))
+
+/* HW Trigger signal is LPDMA_CH0_TRG */
+#define SMBUS_GRP2_LPDMA_CH0_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x00000000U))
+/* HW Trigger signal is LPDMA_CH1_TRG */
+#define SMBUS_GRP2_LPDMA_CH1_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is LPDMA_CH2_TRG */
+#define SMBUS_GRP2_LPDMA_CH2_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is LPDMA_CH3_TRG */
+#define SMBUS_GRP2_LPDMA_CH3_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is EXTI5_TRG */
+#define SMBUS_GRP2_EXTI5_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is EXTI8_TRG */
+#define SMBUS_GRP2_EXTI8_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is LPTIM1_CH1_TRG */
+#define SMBUS_GRP2_LPTIM1_CH1_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is LPTIM3_CH1_TRG */
+#define SMBUS_GRP2_LPTIM3_CH1_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is COMP1_TRG */
+#define SMBUS_GRP2_COMP1_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is COMP2_TRG */
+#define SMBUS_GRP2_COMP2_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is RTC_ALRA_TRG */
+#define SMBUS_GRP2_RTC_ALRA_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is RTC_WUT_TRG */
+#define SMBUS_GRP2_RTC_WUT_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos))
+/**
+ * @}
+ */
+
+/** @defgroup SMBUSEx_AutonomousMode_TriggerPolarity SMBUS Extended Autonomous Mode Trigger Polarity
+ * @{
+ */
+#define SMBUS_TRIG_POLARITY_RISING (0x00000000U) /* SMBUS HW Trigger signal on rising edge */
+#define SMBUS_TRIG_POLARITY_FALLING I2C_AUTOCR_TRIGPOL /* SMBUS HW Trigger signal on falling edge */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SMBUSEx_Exported_Macros SMBUS Extended Exported Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions
+ * @{
+ */
+
+/** @addtogroup SMBUSEx_Exported_Functions_Group2 SMBUS Extended WakeUp Mode Functions
+ * @{
+ */
+/* Peripheral Control functions ************************************************/
+HAL_StatusTypeDef HAL_SMBUSEx_EnableWakeUp(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUSEx_DisableWakeUp(SMBUS_HandleTypeDef *hsmbus);
+/**
+ * @}
+ */
+
+/** @addtogroup SMBUSEx_Exported_Functions_Group3 SMBUS Extended FastModePlus Functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_SMBUSEx_ConfigFastModePlus(SMBUS_HandleTypeDef *hsmbus, uint32_t FastModePlus);
+/**
+ * @}
+ */
+
+/** @addtogroup SMBUSEx_Exported_Functions_Group4 SMBUS Extended Autonomous Mode Functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_SMBUSEx_SetConfigAutonomousMode(SMBUS_HandleTypeDef *hsmbus,
+ SMBUS_AutonomousModeConfTypeDef *sConfig);
+HAL_StatusTypeDef HAL_SMBUSEx_GetConfigAutonomousMode(SMBUS_HandleTypeDef *hsmbus,
+ SMBUS_AutonomousModeConfTypeDef *sConfig);
+HAL_StatusTypeDef HAL_SMBUSEx_ClearConfigAutonomousMode(SMBUS_HandleTypeDef *hsmbus);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SMBUSEx_Private_Constants SMBUS Extended Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SMBUSEx_Private_Macro SMBUS Extended Private Macros
+ * @{
+ */
+#define IS_SMBUS_FASTMODEPLUS(__CONFIG__) (((__CONFIG__) == (SMBUS_FASTMODEPLUS_ENABLE)) || \
+ ((__CONFIG__) == (SMBUS_FASTMODEPLUS_DISABLE)))
+
+#define IS_SMBUS_AUTO_MODE(__MODE__) (((__MODE__) == SMBUS_AUTO_MODE_DISABLE) || \
+ ((__MODE__) == SMBUS_AUTO_MODE_ENABLE))
+
+#define IS_SMBUS_TRIG_SOURCE(__INSTANCE__, __SOURCE__) (((__INSTANCE__) == I2C3) ? \
+ IS_SMBUS_GRP2_TRIG_SOURCE(__SOURCE__) : \
+ IS_SMBUS_GRP1_TRIG_SOURCE(__SOURCE__))
+
+#define IS_SMBUS_GRP1_TRIG_SOURCE(__SOURCE__) (((__SOURCE__) == SMBUS_GRP1_GPDMA_CH0_TCF_TRG ) || \
+ ((__SOURCE__) == SMBUS_GRP1_GPDMA_CH1_TCF_TRG ) || \
+ ((__SOURCE__) == SMBUS_GRP1_GPDMA_CH2_TCF_TRG ) || \
+ ((__SOURCE__) == SMBUS_GRP1_GPDMA_CH3_TCF_TRG ) || \
+ ((__SOURCE__) == SMBUS_GRP1_EXTI5_TRG ) || \
+ ((__SOURCE__) == SMBUS_GRP1_EXTI9_TRG ) || \
+ ((__SOURCE__) == SMBUS_GRP1_LPTIM1_CH1_TRG ) || \
+ ((__SOURCE__) == SMBUS_GRP1_LPTIM2_CH1_TRG ) || \
+ ((__SOURCE__) == SMBUS_GRP1_COMP1_TRG ) || \
+ ((__SOURCE__) == SMBUS_GRP1_COMP2_TRG ) || \
+ ((__SOURCE__) == SMBUS_GRP1_RTC_ALRA_TRG ) || \
+ ((__SOURCE__) == SMBUS_GRP1_RTC_WUT_TRG ))
+
+#define IS_SMBUS_GRP2_TRIG_SOURCE(__SOURCE__) (((__SOURCE__) == SMBUS_GRP2_LPDMA_CH0_TCF_TRG ) || \
+ ((__SOURCE__) == SMBUS_GRP2_LPDMA_CH1_TCF_TRG ) || \
+ ((__SOURCE__) == SMBUS_GRP2_LPDMA_CH2_TCF_TRG ) || \
+ ((__SOURCE__) == SMBUS_GRP2_LPDMA_CH3_TCF_TRG ) || \
+ ((__SOURCE__) == SMBUS_GRP2_EXTI5_TRG ) || \
+ ((__SOURCE__) == SMBUS_GRP2_EXTI8_TRG ) || \
+ ((__SOURCE__) == SMBUS_GRP2_LPTIM1_CH1_TRG ) || \
+ ((__SOURCE__) == SMBUS_GRP2_LPTIM3_CH1_TRG ) || \
+ ((__SOURCE__) == SMBUS_GRP2_COMP1_TRG ) || \
+ ((__SOURCE__) == SMBUS_GRP2_COMP2_TRG ) || \
+ ((__SOURCE__) == SMBUS_GRP2_RTC_ALRA_TRG ) || \
+ ((__SOURCE__) == SMBUS_GRP2_RTC_WUT_TRG ))
+
+#define IS_SMBUS_AUTO_MODE_TRG_POL(__POLARITY__) (((__POLARITY__) == SMBUS_TRIG_POLARITY_RISING) || \
+ ((__POLARITY__) == SMBUS_TRIG_POLARITY_FALLING))
+/**
+ * @}
+ */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup SMBUSEx_Private_Functions SMBUS Extended Private Functions
+ * @{
+ */
+/* Private functions are defined in stm32u5xx_hal_smbus_ex.c file */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_SMBUS_EX_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_spi.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_spi.h
new file mode 100644
index 00000000..2217e55b
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_spi.h
@@ -0,0 +1,1100 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_spi.h
+ * @author MCD Application Team
+ * @brief Header file of SPI HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_SPI_H
+#define STM32U5xx_HAL_SPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SPI
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SPI_Exported_Types SPI Exported Types
+ * @{
+ */
+
+/**
+ * @brief SPI Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t Mode; /*!< Specifies the SPI operating mode.
+ This parameter can be a value of @ref SPI_Mode */
+
+ uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
+ This parameter can be a value of @ref SPI_Direction */
+
+ uint32_t DataSize; /*!< Specifies the SPI data size.
+ This parameter can be a value of @ref SPI_Data_Size */
+
+ uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
+ This parameter can be a value of @ref SPI_Clock_Polarity */
+
+ uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
+ This parameter can be a value of @ref SPI_Clock_Phase */
+
+ uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
+ hardware (NSS pin) or by software using the SSI bit.
+ This parameter can be a value of
+ @ref SPI_Slave_Select_Management */
+
+ uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
+ used to configure the transmit and receive SCK clock.
+ This parameter can be a value of @ref SPI_BaudRate_Prescaler
+ @note The communication clock is derived from the master
+ clock. The slave clock does not need to be set. */
+
+ uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
+ This parameter can be a value of @ref SPI_MSB_LSB_Transmission */
+
+ uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
+ This parameter can be a value of @ref SPI_TI_Mode */
+
+ uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
+ This parameter can be a value of @ref SPI_CRC_Calculation */
+
+ uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
+ This parameter must be an odd number between
+ Min_Data = 0 and Max_Data = 65535 */
+
+ uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation.
+ This parameter can be a value of @ref SPI_CRC_length */
+
+ uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not .
+ This parameter can be a value of @ref SPI_NSSP_Mode
+ This mode is activated by the SSOM bit in the SPIx_CR2 register
+ and it takes effect only if the SPI interface is configured
+ as Motorola SPI master (FRF=0). */
+
+ uint32_t NSSPolarity; /*!< Specifies which level of SS input/output external signal
+ (present on SS pin) is considered as active one.
+ This parameter can be a value of @ref SPI_NSS_Polarity */
+
+ uint32_t FifoThreshold; /*!< Specifies the FIFO threshold level.
+ This parameter can be a value of @ref SPI_Fifo_Threshold */
+
+ uint32_t TxCRCInitializationPattern; /*!< Specifies the transmitter CRC initialization Pattern used for
+ the CRC calculation. This parameter can be a value of
+ @ref SPI_CRC_Calculation_Initialization_Pattern */
+
+ uint32_t RxCRCInitializationPattern; /*!< Specifies the receiver CRC initialization Pattern used for
+ the CRC calculation. This parameter can be a value of
+ @ref SPI_CRC_Calculation_Initialization_Pattern */
+
+ uint32_t MasterSSIdleness; /*!< Specifies an extra delay, expressed in number of SPI clock cycle
+ periods, inserted additionally between active edge of SS
+ and first data transaction start in master mode.
+ This parameter can be a value of @ref SPI_Master_SS_Idleness */
+
+ uint32_t MasterInterDataIdleness; /*!< Specifies minimum time delay (expressed in SPI clock cycles periods)
+ inserted between two consecutive data frames in master mode.
+ This parameter can be a value of
+ @ref SPI_Master_InterData_Idleness */
+
+ uint32_t MasterReceiverAutoSusp; /*!< Control continuous SPI transfer in master receiver mode
+ and automatic management in order to avoid overrun condition.
+ This parameter can be a value of @ref SPI_Master_RX_AutoSuspend*/
+
+ uint32_t MasterKeepIOState; /*!< Control of Alternate function GPIOs state
+ This parameter can be a value of @ref SPI_Master_Keep_IO_State */
+
+ uint32_t IOSwap; /*!< Invert MISO/MOSI alternate functions
+ This parameter can be a value of @ref SPI_IO_Swap */
+
+ uint32_t ReadyMasterManagement; /*!< Specifies if RDY Signal is managed internally or not.
+ This parameter can be a value of @ref SPI_RDY_Master_Management */
+
+ uint32_t ReadyPolarity; /*!< Specifies which level of RDY Signal input (present on RDY pin)
+ is considered as active one.
+ This parameter can be a value of @ref SPI_RDY_Polarity */
+} SPI_InitTypeDef;
+
+/**
+ * @brief HAL SPI State structure definition
+ */
+typedef enum
+{
+ HAL_SPI_STATE_RESET = 0x00UL, /*!< Peripheral not Initialized */
+ HAL_SPI_STATE_READY = 0x01UL, /*!< Peripheral Initialized and ready for use */
+ HAL_SPI_STATE_BUSY = 0x02UL, /*!< an internal process is ongoing */
+ HAL_SPI_STATE_BUSY_TX = 0x03UL, /*!< Data Transmission process is ongoing */
+ HAL_SPI_STATE_BUSY_RX = 0x04UL, /*!< Data Reception process is ongoing */
+ HAL_SPI_STATE_BUSY_TX_RX = 0x05UL, /*!< Data Transmission and Reception process is ongoing */
+ HAL_SPI_STATE_ERROR = 0x06UL, /*!< SPI error state */
+ HAL_SPI_STATE_ABORT = 0x07UL /*!< SPI abort is ongoing */
+} HAL_SPI_StateTypeDef;
+
+
+/**
+ * @brief SPI handle Structure definition
+ */
+typedef struct __SPI_HandleTypeDef
+{
+ SPI_TypeDef *Instance; /*!< SPI registers base address */
+
+ SPI_InitTypeDef Init; /*!< SPI communication parameters */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
+
+ uint16_t TxXferSize; /*!< SPI Tx Transfer size */
+
+ __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
+
+ uint16_t RxXferSize; /*!< SPI Rx Transfer size */
+
+ __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
+
+ uint32_t CRCSize; /*!< SPI CRC size used for the transfer */
+
+ void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */
+
+ void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */
+
+ DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< Locking object */
+
+ __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */
+
+ __IO uint32_t ErrorCode; /*!< SPI Error code */
+
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+ void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */
+ void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */
+ void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */
+ void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */
+ void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */
+ void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */
+ void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */
+ void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */
+ void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */
+ void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */
+
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+} SPI_HandleTypeDef;
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+/**
+ * @brief HAL SPI Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_SPI_TX_COMPLETE_CB_ID = 0x00UL, /*!< SPI Tx Completed callback ID */
+ HAL_SPI_RX_COMPLETE_CB_ID = 0x01UL, /*!< SPI Rx Completed callback ID */
+ HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02UL, /*!< SPI TxRx Completed callback ID */
+ HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03UL, /*!< SPI Tx Half Completed callback ID */
+ HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04UL, /*!< SPI Rx Half Completed callback ID */
+ HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05UL, /*!< SPI TxRx Half Completed callback ID */
+ HAL_SPI_ERROR_CB_ID = 0x06UL, /*!< SPI Error callback ID */
+ HAL_SPI_ABORT_CB_ID = 0x07UL, /*!< SPI Abort callback ID */
+ HAL_SPI_MSPINIT_CB_ID = 0x08UL, /*!< SPI Msp Init callback ID */
+ HAL_SPI_MSPDEINIT_CB_ID = 0x09UL /*!< SPI Msp DeInit callback ID */
+
+} HAL_SPI_CallbackIDTypeDef;
+
+/**
+ * @brief HAL SPI Callback pointer definition
+ */
+typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */
+
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SPI_Exported_Constants SPI Exported Constants
+ * @{
+ */
+
+/** @defgroup SPI_FIFO_Type SPI FIFO Type
+ * @{
+ */
+#define SPI_LOWEND_FIFO_SIZE 8UL
+#define SPI_HIGHEND_FIFO_SIZE 16UL
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Error_Code SPI Error Codes
+ * @{
+ */
+#define HAL_SPI_ERROR_NONE (0x00000000UL) /*!< No error */
+#define HAL_SPI_ERROR_MODF (0x00000001UL) /*!< MODF error */
+#define HAL_SPI_ERROR_CRC (0x00000002UL) /*!< CRC error */
+#define HAL_SPI_ERROR_OVR (0x00000004UL) /*!< OVR error */
+#define HAL_SPI_ERROR_FRE (0x00000008UL) /*!< FRE error */
+#define HAL_SPI_ERROR_DMA (0x00000010UL) /*!< DMA transfer error */
+#define HAL_SPI_ERROR_FLAG (0x00000020UL) /*!< Error on RXP/TXP/DXP/FTLVL/FRLVL Flag */
+#define HAL_SPI_ERROR_ABORT (0x00000040UL) /*!< Error during SPI Abort procedure */
+#define HAL_SPI_ERROR_UDR (0x00000080UL) /*!< Underrun error */
+#define HAL_SPI_ERROR_TIMEOUT (0x00000100UL) /*!< Timeout error */
+#define HAL_SPI_ERROR_UNKNOW (0x00000200UL) /*!< Unknown error */
+#define HAL_SPI_ERROR_NOT_SUPPORTED (0x00000400UL) /*!< Requested operation not supported */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00001000UL) /*!< Invalid Callback error */
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Mode SPI Mode
+ * @{
+ */
+#define SPI_MODE_SLAVE (0x00000000UL)
+#define SPI_MODE_MASTER SPI_CFG2_MASTER
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Direction SPI Direction Mode
+ * @{
+ */
+#define SPI_DIRECTION_2LINES (0x00000000UL)
+#define SPI_DIRECTION_2LINES_TXONLY SPI_CFG2_COMM_0
+#define SPI_DIRECTION_2LINES_RXONLY SPI_CFG2_COMM_1
+#define SPI_DIRECTION_1LINE SPI_CFG2_COMM
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Data_Size SPI Data Size
+ * @{
+ */
+#define SPI_DATASIZE_4BIT (0x00000003UL)
+#define SPI_DATASIZE_5BIT (0x00000004UL)
+#define SPI_DATASIZE_6BIT (0x00000005UL)
+#define SPI_DATASIZE_7BIT (0x00000006UL)
+#define SPI_DATASIZE_8BIT (0x00000007UL)
+#define SPI_DATASIZE_9BIT (0x00000008UL)
+#define SPI_DATASIZE_10BIT (0x00000009UL)
+#define SPI_DATASIZE_11BIT (0x0000000AUL)
+#define SPI_DATASIZE_12BIT (0x0000000BUL)
+#define SPI_DATASIZE_13BIT (0x0000000CUL)
+#define SPI_DATASIZE_14BIT (0x0000000DUL)
+#define SPI_DATASIZE_15BIT (0x0000000EUL)
+#define SPI_DATASIZE_16BIT (0x0000000FUL)
+#define SPI_DATASIZE_17BIT (0x00000010UL)
+#define SPI_DATASIZE_18BIT (0x00000011UL)
+#define SPI_DATASIZE_19BIT (0x00000012UL)
+#define SPI_DATASIZE_20BIT (0x00000013UL)
+#define SPI_DATASIZE_21BIT (0x00000014UL)
+#define SPI_DATASIZE_22BIT (0x00000015UL)
+#define SPI_DATASIZE_23BIT (0x00000016UL)
+#define SPI_DATASIZE_24BIT (0x00000017UL)
+#define SPI_DATASIZE_25BIT (0x00000018UL)
+#define SPI_DATASIZE_26BIT (0x00000019UL)
+#define SPI_DATASIZE_27BIT (0x0000001AUL)
+#define SPI_DATASIZE_28BIT (0x0000001BUL)
+#define SPI_DATASIZE_29BIT (0x0000001CUL)
+#define SPI_DATASIZE_30BIT (0x0000001DUL)
+#define SPI_DATASIZE_31BIT (0x0000001EUL)
+#define SPI_DATASIZE_32BIT (0x0000001FUL)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
+ * @{
+ */
+#define SPI_POLARITY_LOW (0x00000000UL)
+#define SPI_POLARITY_HIGH SPI_CFG2_CPOL
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Clock_Phase SPI Clock Phase
+ * @{
+ */
+#define SPI_PHASE_1EDGE (0x00000000UL)
+#define SPI_PHASE_2EDGE SPI_CFG2_CPHA
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Slave_Select_Management SPI Slave Select Management
+ * @{
+ */
+#define SPI_NSS_SOFT SPI_CFG2_SSM
+#define SPI_NSS_HARD_INPUT (0x00000000UL)
+#define SPI_NSS_HARD_OUTPUT SPI_CFG2_SSOE
+/**
+ * @}
+ */
+
+/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
+ * @{
+ */
+#define SPI_NSS_PULSE_DISABLE (0x00000000UL)
+#define SPI_NSS_PULSE_ENABLE SPI_CFG2_SSOM
+/**
+ * @}
+ */
+
+/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
+ * @{
+ */
+#define SPI_BAUDRATEPRESCALER_BYPASS (0x80000000UL)
+#define SPI_BAUDRATEPRESCALER_2 (0x00000000UL)
+#define SPI_BAUDRATEPRESCALER_4 (0x10000000UL)
+#define SPI_BAUDRATEPRESCALER_8 (0x20000000UL)
+#define SPI_BAUDRATEPRESCALER_16 (0x30000000UL)
+#define SPI_BAUDRATEPRESCALER_32 (0x40000000UL)
+#define SPI_BAUDRATEPRESCALER_64 (0x50000000UL)
+#define SPI_BAUDRATEPRESCALER_128 (0x60000000UL)
+#define SPI_BAUDRATEPRESCALER_256 (0x70000000UL)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_MSB_LSB_Transmission SPI MSB LSB Transmission
+ * @{
+ */
+#define SPI_FIRSTBIT_MSB (0x00000000UL)
+#define SPI_FIRSTBIT_LSB SPI_CFG2_LSBFRST
+/**
+ * @}
+ */
+
+/** @defgroup SPI_TI_Mode SPI TI Mode
+ * @{
+ */
+#define SPI_TIMODE_DISABLE (0x00000000UL)
+#define SPI_TIMODE_ENABLE SPI_CFG2_SP_0
+/**
+ * @}
+ */
+
+/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
+ * @{
+ */
+#define SPI_CRCCALCULATION_DISABLE (0x00000000UL)
+#define SPI_CRCCALCULATION_ENABLE SPI_CFG1_CRCEN
+/**
+ * @}
+ */
+
+/** @defgroup SPI_CRC_length SPI CRC Length
+ * @{
+ */
+#define SPI_CRC_LENGTH_DATASIZE (0x00000000UL)
+#define SPI_CRC_LENGTH_4BIT (0x00030000UL)
+#define SPI_CRC_LENGTH_5BIT (0x00040000UL)
+#define SPI_CRC_LENGTH_6BIT (0x00050000UL)
+#define SPI_CRC_LENGTH_7BIT (0x00060000UL)
+#define SPI_CRC_LENGTH_8BIT (0x00070000UL)
+#define SPI_CRC_LENGTH_9BIT (0x00080000UL)
+#define SPI_CRC_LENGTH_10BIT (0x00090000UL)
+#define SPI_CRC_LENGTH_11BIT (0x000A0000UL)
+#define SPI_CRC_LENGTH_12BIT (0x000B0000UL)
+#define SPI_CRC_LENGTH_13BIT (0x000C0000UL)
+#define SPI_CRC_LENGTH_14BIT (0x000D0000UL)
+#define SPI_CRC_LENGTH_15BIT (0x000E0000UL)
+#define SPI_CRC_LENGTH_16BIT (0x000F0000UL)
+#define SPI_CRC_LENGTH_17BIT (0x00100000UL)
+#define SPI_CRC_LENGTH_18BIT (0x00110000UL)
+#define SPI_CRC_LENGTH_19BIT (0x00120000UL)
+#define SPI_CRC_LENGTH_20BIT (0x00130000UL)
+#define SPI_CRC_LENGTH_21BIT (0x00140000UL)
+#define SPI_CRC_LENGTH_22BIT (0x00150000UL)
+#define SPI_CRC_LENGTH_23BIT (0x00160000UL)
+#define SPI_CRC_LENGTH_24BIT (0x00170000UL)
+#define SPI_CRC_LENGTH_25BIT (0x00180000UL)
+#define SPI_CRC_LENGTH_26BIT (0x00190000UL)
+#define SPI_CRC_LENGTH_27BIT (0x001A0000UL)
+#define SPI_CRC_LENGTH_28BIT (0x001B0000UL)
+#define SPI_CRC_LENGTH_29BIT (0x001C0000UL)
+#define SPI_CRC_LENGTH_30BIT (0x001D0000UL)
+#define SPI_CRC_LENGTH_31BIT (0x001E0000UL)
+#define SPI_CRC_LENGTH_32BIT (0x001F0000UL)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Fifo_Threshold SPI Fifo Threshold
+ * @{
+ */
+#define SPI_FIFO_THRESHOLD_01DATA (0x00000000UL)
+#define SPI_FIFO_THRESHOLD_02DATA (0x00000020UL)
+#define SPI_FIFO_THRESHOLD_03DATA (0x00000040UL)
+#define SPI_FIFO_THRESHOLD_04DATA (0x00000060UL)
+#define SPI_FIFO_THRESHOLD_05DATA (0x00000080UL)
+#define SPI_FIFO_THRESHOLD_06DATA (0x000000A0UL)
+#define SPI_FIFO_THRESHOLD_07DATA (0x000000C0UL)
+#define SPI_FIFO_THRESHOLD_08DATA (0x000000E0UL)
+#define SPI_FIFO_THRESHOLD_09DATA (0x00000100UL)
+#define SPI_FIFO_THRESHOLD_10DATA (0x00000120UL)
+#define SPI_FIFO_THRESHOLD_11DATA (0x00000140UL)
+#define SPI_FIFO_THRESHOLD_12DATA (0x00000160UL)
+#define SPI_FIFO_THRESHOLD_13DATA (0x00000180UL)
+#define SPI_FIFO_THRESHOLD_14DATA (0x000001A0UL)
+#define SPI_FIFO_THRESHOLD_15DATA (0x000001C0UL)
+#define SPI_FIFO_THRESHOLD_16DATA (0x000001E0UL)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_CRC_Calculation_Initialization_Pattern SPI CRC Calculation Initialization Pattern
+ * @{
+ */
+#define SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN (0x00000000UL)
+#define SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN (0x00000001UL)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_NSS_Polarity SPI NSS Polarity
+ * @{
+ */
+#define SPI_NSS_POLARITY_LOW (0x00000000UL)
+#define SPI_NSS_POLARITY_HIGH SPI_CFG2_SSIOP
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Master_Keep_IO_State Keep IO State
+ * @{
+ */
+#define SPI_MASTER_KEEP_IO_STATE_DISABLE (0x00000000UL)
+#define SPI_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR
+/**
+ * @}
+ */
+
+/** @defgroup SPI_IO_Swap Control SPI IO Swap
+ * @{
+ */
+#define SPI_IO_SWAP_DISABLE (0x00000000UL)
+#define SPI_IO_SWAP_ENABLE SPI_CFG2_IOSWP
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Master_SS_Idleness SPI Master SS Idleness
+ * @{
+ */
+#define SPI_MASTER_SS_IDLENESS_00CYCLE (0x00000000UL)
+#define SPI_MASTER_SS_IDLENESS_01CYCLE (0x00000001UL)
+#define SPI_MASTER_SS_IDLENESS_02CYCLE (0x00000002UL)
+#define SPI_MASTER_SS_IDLENESS_03CYCLE (0x00000003UL)
+#define SPI_MASTER_SS_IDLENESS_04CYCLE (0x00000004UL)
+#define SPI_MASTER_SS_IDLENESS_05CYCLE (0x00000005UL)
+#define SPI_MASTER_SS_IDLENESS_06CYCLE (0x00000006UL)
+#define SPI_MASTER_SS_IDLENESS_07CYCLE (0x00000007UL)
+#define SPI_MASTER_SS_IDLENESS_08CYCLE (0x00000008UL)
+#define SPI_MASTER_SS_IDLENESS_09CYCLE (0x00000009UL)
+#define SPI_MASTER_SS_IDLENESS_10CYCLE (0x0000000AUL)
+#define SPI_MASTER_SS_IDLENESS_11CYCLE (0x0000000BUL)
+#define SPI_MASTER_SS_IDLENESS_12CYCLE (0x0000000CUL)
+#define SPI_MASTER_SS_IDLENESS_13CYCLE (0x0000000DUL)
+#define SPI_MASTER_SS_IDLENESS_14CYCLE (0x0000000EUL)
+#define SPI_MASTER_SS_IDLENESS_15CYCLE (0x0000000FUL)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Master_InterData_Idleness SPI Master Inter-Data Idleness
+ * @{
+ */
+#define SPI_MASTER_INTERDATA_IDLENESS_00CYCLE (0x00000000UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_01CYCLE (0x00000010UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_02CYCLE (0x00000020UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_03CYCLE (0x00000030UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_04CYCLE (0x00000040UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_05CYCLE (0x00000050UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_06CYCLE (0x00000060UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_07CYCLE (0x00000070UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_08CYCLE (0x00000080UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_09CYCLE (0x00000090UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_10CYCLE (0x000000A0UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_11CYCLE (0x000000B0UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_12CYCLE (0x000000C0UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_13CYCLE (0x000000D0UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_14CYCLE (0x000000E0UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_15CYCLE (0x000000F0UL)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Master_RX_AutoSuspend SPI Master Receiver AutoSuspend
+ * @{
+ */
+#define SPI_MASTER_RX_AUTOSUSP_DISABLE (0x00000000UL)
+#define SPI_MASTER_RX_AUTOSUSP_ENABLE SPI_CR1_MASRX
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Underrun_Behaviour SPI Underrun Behavior
+ * @{
+ */
+#define SPI_UNDERRUN_BEHAV_REGISTER_PATTERN (0x00000000UL)
+#define SPI_UNDERRUN_BEHAV_LAST_RECEIVED SPI_CFG1_UDRCFG
+/**
+ * @}
+ */
+
+/** @defgroup SPI_RDY_Master_Management SPI RDY Signal Input Master Management
+ * @{
+ */
+#define SPI_RDY_MASTER_MANAGEMENT_INTERNALLY (0x00000000UL)
+#define SPI_RDY_MASTER_MANAGEMENT_EXTERNALLY SPI_CFG2_RDIMM
+/**
+ * @}
+ */
+
+/** @defgroup SPI_RDY_Polarity SPI RDY Signal Input/Output Polarity
+ * @{
+ */
+#define SPI_RDY_POLARITY_HIGH (0x00000000UL)
+#define SPI_RDY_POLARITY_LOW SPI_CFG2_RDIOP
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
+ * @{
+ */
+#define SPI_IT_RXP SPI_IER_RXPIE
+#define SPI_IT_TXP SPI_IER_TXPIE
+#define SPI_IT_DXP SPI_IER_DXPIE
+#define SPI_IT_EOT SPI_IER_EOTIE
+#define SPI_IT_TXTF SPI_IER_TXTFIE
+#define SPI_IT_UDR SPI_IER_UDRIE
+#define SPI_IT_OVR SPI_IER_OVRIE
+#define SPI_IT_CRCERR SPI_IER_CRCEIE
+#define SPI_IT_FRE SPI_IER_TIFREIE
+#define SPI_IT_MODF SPI_IER_MODFIE
+#define SPI_IT_ERR (SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_CRCERR)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Flags_definition SPI Flags Definition
+ * @{
+ */
+#define SPI_FLAG_RXP SPI_SR_RXP /* SPI status flag : Rx-Packet available flag */
+#define SPI_FLAG_TXP SPI_SR_TXP /* SPI status flag : Tx-Packet space available flag */
+#define SPI_FLAG_DXP SPI_SR_DXP /* SPI status flag : Duplex Packet flag */
+#define SPI_FLAG_EOT SPI_SR_EOT /* SPI status flag : End of transfer flag */
+#define SPI_FLAG_TXTF SPI_SR_TXTF /* SPI status flag : Transmission Transfer Filled flag */
+#define SPI_FLAG_UDR SPI_SR_UDR /* SPI Error flag : Underrun flag */
+#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag : Overrun flag */
+#define SPI_FLAG_CRCERR SPI_SR_CRCE /* SPI Error flag : CRC error flag */
+#define SPI_FLAG_FRE SPI_SR_TIFRE /* SPI Error flag : TI mode frame format error flag */
+#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag : Mode fault flag */
+#define SPI_FLAG_SUSP SPI_SR_SUSP /* SPI status flag : Transfer suspend complete flag */
+#define SPI_FLAG_TXC SPI_SR_TXC /* SPI status flag : TxFIFO transmission complete flag */
+#define SPI_FLAG_FRLVL SPI_SR_RXPLVL /* SPI status flag : Fifo reception level flag */
+#define SPI_FLAG_RXWNE SPI_SR_RXWNE /* SPI status flag : RxFIFO word not empty flag */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
+ * @{
+ */
+#define SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packets available in the RxFIFO */
+#define SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0)
+#define SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1)
+#define SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup SPI_Exported_Macros SPI Exported Macros
+ * @{
+ */
+
+/** @brief Reset SPI handle state.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
+ * @retval None
+ */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_SPI_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+
+/** @brief Enable the specified SPI interrupts.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
+ * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg SPI_IT_RXP : Rx-Packet available interrupt
+ * @arg SPI_IT_TXP : Tx-Packet space available interrupt
+ * @arg SPI_IT_DXP : Duplex Packet interrupt
+ * @arg SPI_IT_EOT : End of transfer interrupt
+ * @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt
+ * @arg SPI_IT_UDR : Underrun interrupt
+ * @arg SPI_IT_OVR : Overrun interrupt
+ * @arg SPI_IT_CRCERR : CRC error interrupt
+ * @arg SPI_IT_FRE : TI mode frame format error interrupt
+ * @arg SPI_IT_MODF : Mode fault interrupt
+ * @arg SPI_IT_ERR : Error interrupt
+ * @retval None
+ */
+#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+
+/** @brief Disable the specified SPI interrupts.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
+ * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg SPI_IT_RXP : Rx-Packet available interrupt
+ * @arg SPI_IT_TXP : Tx-Packet space available interrupt
+ * @arg SPI_IT_DXP : Duplex Packet interrupt
+ * @arg SPI_IT_EOT : End of transfer interrupt
+ * @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt
+ * @arg SPI_IT_UDR : Underrun interrupt
+ * @arg SPI_IT_OVR : Overrun interrupt
+ * @arg SPI_IT_CRCERR : CRC error interrupt
+ * @arg SPI_IT_FRE : TI mode frame format error interrupt
+ * @arg SPI_IT_MODF : Mode fault interrupt
+ * @arg SPI_IT_ERR : Error interrupt
+ * @retval None
+ */
+#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
+
+/** @brief Check whether the specified SPI interrupt source is enabled or not.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
+ * @param __INTERRUPT__: specifies the SPI interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_IT_RXP : Rx-Packet available interrupt
+ * @arg SPI_IT_TXP : Tx-Packet space available interrupt
+ * @arg SPI_IT_DXP : Duplex Packet interrupt
+ * @arg SPI_IT_EOT : End of transfer interrupt
+ * @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt
+ * @arg SPI_IT_UDR : Underrun interrupt
+ * @arg SPI_IT_OVR : Overrun interrupt
+ * @arg SPI_IT_CRCERR : CRC error interrupt
+ * @arg SPI_IT_FRE : TI mode frame format error interrupt
+ * @arg SPI_IT_MODF : Mode fault interrupt
+ * @arg SPI_IT_ERR : Error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & \
+ (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Check whether the specified SPI flag is set or not.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_FLAG_RXP : Rx-Packet available flag
+ * @arg SPI_FLAG_TXP : Tx-Packet space available flag
+ * @arg SPI_FLAG_DXP : Duplex Packet flag
+ * @arg SPI_FLAG_EOT : End of transfer flag
+ * @arg SPI_FLAG_TXTF : Transmission Transfer Filled flag
+ * @arg SPI_FLAG_UDR : Underrun flag
+ * @arg SPI_FLAG_OVR : Overrun flag
+ * @arg SPI_FLAG_CRCERR : CRC error flag
+ * @arg SPI_FLAG_FRE : TI mode frame format error flag
+ * @arg SPI_FLAG_MODF : Mode fault flag
+ * @arg SPI_FLAG_SUSP : Transfer suspend complete flag
+ * @arg SPI_FLAG_TXC : TxFIFO transmission complete flag
+ * @arg SPI_FLAG_FRLVL : Fifo reception level flag
+ * @arg SPI_FLAG_RXWNE : RxFIFO word not empty flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the SPI CRCERR pending flag.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_CRCEC)
+
+/** @brief Clear the SPI MODF pending flag.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , (uint32_t)(SPI_IFCR_MODFC));
+
+/** @brief Clear the SPI OVR pending flag.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC)
+
+/** @brief Clear the SPI FRE pending flag.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC)
+
+/** @brief Clear the SPI UDR pending flag.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC)
+
+/** @brief Clear the SPI EOT pending flag.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_EOTFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_EOTC)
+
+/** @brief Clear the SPI UDR pending flag.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_TXTFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TXTFC)
+
+/** @brief Clear the SPI SUSP pending flag.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_SUSPFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_SUSPC)
+
+/** @brief Enable the SPI peripheral.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * @retval None
+ */
+#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE)
+
+/** @brief Disable the SPI peripheral.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * @retval None
+ */
+#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE)
+/**
+ * @}
+ */
+
+
+/* Include SPI HAL Extension module */
+#include "stm32u5xx_hal_spi_ex.h"
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPI_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+/* Initialization/de-initialization functions ********************************/
+HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
+void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
+void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
+ pSPI_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+/* I/O operation functions ***************************************************/
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size);
+
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size);
+
+
+HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
+
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
+
+void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @{
+ */
+
+/* Peripheral State and Error functions ***************************************/
+HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
+uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SPI_Private_Macros SPI Private Macros
+ * @{
+ */
+
+/** @brief Set the SPI transmit-only mode.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_HDDIR)
+
+/** @brief Set the SPI receive-only mode.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 ,SPI_CR1_HDDIR)
+
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
+ ((MODE) == SPI_MODE_MASTER))
+
+#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
+ ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
+ ((MODE) == SPI_DIRECTION_1LINE) || \
+ ((MODE) == SPI_DIRECTION_2LINES_TXONLY))
+
+#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
+
+#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \
+ ((MODE) == SPI_DIRECTION_1LINE) || \
+ ((MODE) == SPI_DIRECTION_2LINES_TXONLY))
+
+#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \
+ ((MODE) == SPI_DIRECTION_1LINE) || \
+ ((MODE) == SPI_DIRECTION_2LINES_RXONLY))
+
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_32BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_31BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_30BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_29BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_28BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_27BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_26BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_25BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_24BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_23BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_22BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_21BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_20BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_22BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_19BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_18BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_17BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_16BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_15BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_14BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_13BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_12BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_11BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_10BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_9BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_8BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_7BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_6BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_5BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_4BIT))
+
+/**
+ * @brief DataSize for limited instance
+ */
+#define IS_SPI_LIMITED_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_8BIT))
+
+#define IS_SPI_FIFOTHRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_FIFO_THRESHOLD_01DATA) || \
+ ((THRESHOLD) == SPI_FIFO_THRESHOLD_02DATA) || \
+ ((THRESHOLD) == SPI_FIFO_THRESHOLD_03DATA) || \
+ ((THRESHOLD) == SPI_FIFO_THRESHOLD_04DATA) || \
+ ((THRESHOLD) == SPI_FIFO_THRESHOLD_05DATA) || \
+ ((THRESHOLD) == SPI_FIFO_THRESHOLD_06DATA) || \
+ ((THRESHOLD) == SPI_FIFO_THRESHOLD_07DATA) || \
+ ((THRESHOLD) == SPI_FIFO_THRESHOLD_08DATA) || \
+ ((THRESHOLD) == SPI_FIFO_THRESHOLD_09DATA) || \
+ ((THRESHOLD) == SPI_FIFO_THRESHOLD_10DATA) || \
+ ((THRESHOLD) == SPI_FIFO_THRESHOLD_11DATA) || \
+ ((THRESHOLD) == SPI_FIFO_THRESHOLD_12DATA) || \
+ ((THRESHOLD) == SPI_FIFO_THRESHOLD_13DATA) || \
+ ((THRESHOLD) == SPI_FIFO_THRESHOLD_14DATA) || \
+ ((THRESHOLD) == SPI_FIFO_THRESHOLD_15DATA) || \
+ ((THRESHOLD) == SPI_FIFO_THRESHOLD_16DATA))
+
+/**
+ * @brief FifoThreshold for limited instance
+ */
+#define IS_SPI_LIMITED_FIFOTHRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_FIFO_THRESHOLD_01DATA) || \
+ ((THRESHOLD) == SPI_FIFO_THRESHOLD_02DATA) || \
+ ((THRESHOLD) == SPI_FIFO_THRESHOLD_03DATA) || \
+ ((THRESHOLD) == SPI_FIFO_THRESHOLD_04DATA) || \
+ ((THRESHOLD) == SPI_FIFO_THRESHOLD_05DATA) || \
+ ((THRESHOLD) == SPI_FIFO_THRESHOLD_06DATA) || \
+ ((THRESHOLD) == SPI_FIFO_THRESHOLD_07DATA) || \
+ ((THRESHOLD) == SPI_FIFO_THRESHOLD_08DATA))
+
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
+ ((CPOL) == SPI_POLARITY_HIGH))
+
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
+ ((CPHA) == SPI_PHASE_2EDGE))
+
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
+ ((NSS) == SPI_NSS_HARD_INPUT) || \
+ ((NSS) == SPI_NSS_HARD_OUTPUT))
+
+#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \
+ ((NSSP) == SPI_NSS_PULSE_DISABLE))
+
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
+
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
+ ((BIT) == SPI_FIRSTBIT_LSB))
+
+#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
+ ((MODE) == SPI_TIMODE_ENABLE))
+
+#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
+ ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
+
+#define IS_SPI_CRC_INITIALIZATION_PATTERN(PATTERN) (((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN) || \
+ ((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN))
+
+#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) || \
+ ((LENGTH) == SPI_CRC_LENGTH_32BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_31BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_30BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_29BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_28BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_27BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_26BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_25BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_24BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_23BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_22BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_21BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_20BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_19BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_18BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_17BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_16BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_15BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_14BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_13BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_12BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_11BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_10BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_9BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_7BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_6BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_5BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_4BIT))
+
+/**
+ * @brief CRC Length for limited instance
+ */
+#define IS_SPI_LIMITED_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_8BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_16BIT))
+
+
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) > 0x0UL)
+
+
+
+#define IS_SPI_UNDERRUN_BEHAVIOUR(MODE) (((MODE) == SPI_UNDERRUN_BEHAV_REGISTER_PATTERN) || \
+ ((MODE) == SPI_UNDERRUN_BEHAV_LAST_RECEIVED))
+
+#define IS_SPI_RDY_MASTER_MANAGEMENT(MANAGEMENT) (((MANAGEMENT) == SPI_RDY_MASTER_MANAGEMENT_INTERNALLY) || \
+ ((MANAGEMENT) == SPI_RDY_MASTER_MANAGEMENT_EXTERNALLY))
+
+#define IS_SPI_RDY_POLARITY(POLARITY) (((POLARITY) == SPI_RDY_POLARITY_HIGH) || \
+ ((POLARITY) == SPI_RDY_POLARITY_LOW))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_SPI_H */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_spi_ex.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_spi_ex.h
new file mode 100644
index 00000000..c9830aa3
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_spi_ex.h
@@ -0,0 +1,244 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_spi_ex.h
+ * @author MCD Application Team
+ * @brief Header file of SPI HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_SPI_EX_H
+#define STM32U5xx_HAL_SPI_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SPIEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SPIEx_Exported_Types SPIEx Exported Types
+ * @{
+ */
+
+/**
+ * @brief SPI Autonomous Mode Configuration structure definition
+ */
+typedef struct
+{
+ uint32_t TriggerState; /*!< Specifies the trigger state. This parameter can be a value
+ of @ref FunctionalState */
+
+ uint32_t TriggerSelection; /*!< Specifies the autonomous mode trigger signal selection. This parameter
+ can be a value of @ref SPI_AutonomousMode_TriggerSelection */
+
+ uint32_t TriggerPolarity; /*!< Specifies the autonomous mode trigger signal polarity sensitivity. This parameter
+ can be a value of @ref SPI_AutonomousMode_TriggerPolarity */
+
+} SPI_AutonomousModeConfTypeDef;
+
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SPIEx_Exported_Constants SPIEx Exported Constants
+ * @{
+ */
+
+/** @defgroup FunctionalState SPI Autonomous Mode State
+ * @{
+ */
+#define SPI_AUTO_MODE_DISABLE (0x00000000UL)
+#define SPI_AUTO_MODE_ENABLE SPI_AUTOCR_TRIGEN
+/**
+ * @}
+ */
+
+/** @defgroup SPI_AutonomousMode_TriggerSelection Autonomous Mode Trigger Selection
+ * @{
+ */
+#define SPI_TRIG_GRP1 (0x10000000U) /* Trigger Group for SPI1 and SPI2 */
+#define SPI_TRIG_GRP2 (0x20000000U) /* Trigger Group for SPI3 */
+
+/* HW Trigger signal is GPDMA_CH0_TRG */
+#define SPI_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x00000000U))
+/* HW Trigger signal is GPDMA_CH1_TRG */
+#define SPI_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x1U << SPI_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is GPDMA_CH2_TRG */
+#define SPI_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x2U << SPI_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is GPDMA_CH3_TRG */
+#define SPI_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x3U << SPI_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is EXTI4_TRG */
+#define SPI_GRP1_EXTI4_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x4U << SPI_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is EXTI9_TRG */
+#define SPI_GRP1_EXTI9_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x5U << SPI_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is LPTIM1_CH1_TRG */
+#define SPI_GRP1_LPTIM1_CH1_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x6U << SPI_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is LPTIM2_CH1_TRG */
+#define SPI_GRP1_LPTIM2_CH1_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x7U << SPI_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is COMP1_TRG */
+#define SPI_GRP1_COMP1_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x8U << SPI_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is COMP2_TRG */
+#define SPI_GRP1_COMP2_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x9U << SPI_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is RTC_ALRA_TRG */
+#define SPI_GRP1_RTC_ALRA_TRG (uint32_t)(SPI_TRIG_GRP1 | (0xAU << SPI_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is RTC_WUT_TRG */
+#define SPI_GRP1_RTC_WUT_TRG (uint32_t)(SPI_TRIG_GRP1 | (0xBU << SPI_AUTOCR_TRIGSEL_Pos))
+
+/* HW Trigger signal is LPDMA_CH0_TRG */
+#define SPI_GRP2_LPDMA_CH0_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x00000000U))
+/* HW Trigger signal is LPDMA_CH1_TRG */
+#define SPI_GRP2_LPDMA_CH1_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x1U << SPI_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is LPDMA_CH2_TRG */
+#define SPI_GRP2_LPDMA_CH2_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x2U << SPI_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is LPDMA_CH3_TRG */
+#define SPI_GRP2_LPDMA_CH3_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x3U << SPI_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is EXTI4_TRG */
+#define SPI_GRP2_EXTI4_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x4U << SPI_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is EXTI8_TRG */
+#define SPI_GRP2_EXTI8_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x5U << SPI_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is LPTIM1_CH1_TRG */
+#define SPI_GRP2_LPTIM1_CH1_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x6U << SPI_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is LPTIM3_CH1_TRG */
+#define SPI_GRP2_LPTIM3_CH1_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x7U << SPI_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is COMP1_TRG */
+#define SPI_GRP2_COMP1_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x8U << SPI_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is COMP2_TRG */
+#define SPI_GRP2_COMP2_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x9U << SPI_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is RTC_ALRA_TRG */
+#define SPI_GRP2_RTC_ALRA_TRG (uint32_t)(SPI_TRIG_GRP2 | (0xAU << SPI_AUTOCR_TRIGSEL_Pos))
+/* HW Trigger signal is RTC_WUT_TRG */
+#define SPI_GRP2_RTC_WUT_TRG (uint32_t)(SPI_TRIG_GRP2 | (0xBU << SPI_AUTOCR_TRIGSEL_Pos))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_AutonomousMode_TriggerPolarity Autonomous Mode Trigger Polarity
+ * @{
+ */
+#define SPI_TRIG_POLARITY_RISING (0x00000000UL) /* SPI HW Trigger signal on rising edge */
+#define SPI_TRIG_POLARITY_FALLING SPI_AUTOCR_TRIGPOL /* SPI HW Trigger signal on falling edge */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup SPIEx_Exported_Macros SPIEx Extended Exported Macros
+ * @{
+ */
+
+#define IS_SPI_AUTO_MODE(__MODE__) (((__MODE__) == SPI_AUTO_MODE_DISABLE) || \
+ ((__MODE__) == SPI_AUTO_MODE_ENABLE))
+
+#define IS_SPI_TRIG_SOURCE(__INSTANCE__, __SOURCE__) (((__INSTANCE__) == SPI3) ? \
+ IS_SPI_GRP2_TRIG_SOURCE(__SOURCE__) : \
+ IS_SPI_GRP1_TRIG_SOURCE(__SOURCE__))
+
+#define IS_SPI_GRP1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) ||\
+ ((__INSTANCE__) == SPI2))
+
+#define IS_SPI_GRP2_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPI3)
+
+#define IS_SPI_GRP1_TRIG_SOURCE(__SOURCE__) (((__SOURCE__) == SPI_GRP1_GPDMA_CH0_TCF_TRG ) || \
+ ((__SOURCE__) == SPI_GRP1_GPDMA_CH1_TCF_TRG ) || \
+ ((__SOURCE__) == SPI_GRP1_GPDMA_CH2_TCF_TRG ) || \
+ ((__SOURCE__) == SPI_GRP1_GPDMA_CH3_TCF_TRG ) || \
+ ((__SOURCE__) == SPI_GRP1_EXTI4_TRG ) || \
+ ((__SOURCE__) == SPI_GRP1_EXTI9_TRG ) || \
+ ((__SOURCE__) == SPI_GRP1_LPTIM1_CH1_TRG ) || \
+ ((__SOURCE__) == SPI_GRP1_LPTIM2_CH1_TRG ) || \
+ ((__SOURCE__) == SPI_GRP1_COMP1_TRG ) || \
+ ((__SOURCE__) == SPI_GRP1_COMP2_TRG ) || \
+ ((__SOURCE__) == SPI_GRP1_RTC_ALRA_TRG ) || \
+ ((__SOURCE__) == SPI_GRP1_RTC_WUT_TRG ))
+
+#define IS_SPI_GRP2_TRIG_SOURCE(__SOURCE__) (((__SOURCE__) == SPI_GRP2_LPDMA_CH0_TCF_TRG ) || \
+ ((__SOURCE__) == SPI_GRP2_LPDMA_CH1_TCF_TRG ) || \
+ ((__SOURCE__) == SPI_GRP2_LPDMA_CH2_TCF_TRG ) || \
+ ((__SOURCE__) == SPI_GRP2_LPDMA_CH3_TCF_TRG ) || \
+ ((__SOURCE__) == SPI_GRP2_EXTI4_TRG ) || \
+ ((__SOURCE__) == SPI_GRP2_EXTI8_TRG ) || \
+ ((__SOURCE__) == SPI_GRP2_LPTIM1_CH1_TRG ) || \
+ ((__SOURCE__) == SPI_GRP2_LPTIM3_CH1_TRG ) || \
+ ((__SOURCE__) == SPI_GRP2_COMP1_TRG ) || \
+ ((__SOURCE__) == SPI_GRP2_COMP2_TRG ) || \
+ ((__SOURCE__) == SPI_GRP2_RTC_ALRA_TRG ) || \
+ ((__SOURCE__) == SPI_GRP2_RTC_WUT_TRG ))
+
+#define IS_SPI_AUTO_MODE_TRG_POL(__POLARITY__) (((__POLARITY__) == SPI_TRIG_POLARITY_RISING) || \
+ ((__POLARITY__) == SPI_TRIG_POLARITY_FALLING))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPIEx_Exported_Functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+/* IO operation functions *****************************************************/
+/** @addtogroup SPIEx_Exported_Functions_Group1
+ * @{
+ */
+HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPIEx_EnableLockConfiguration(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection,
+ uint32_t UnderrunBehaviour);
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Autonomous_Mode_Functions Autonomous Mode Functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_SPIEx_SetConfigAutonomousMode(SPI_HandleTypeDef *hspi, SPI_AutonomousModeConfTypeDef *sConfig);
+HAL_StatusTypeDef HAL_SPIEx_GetConfigAutonomousMode(SPI_HandleTypeDef *hspi, SPI_AutonomousModeConfTypeDef *sConfig);
+HAL_StatusTypeDef HAL_SPIEx_ClearConfigAutonomousMode(SPI_HandleTypeDef *hspi);
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_SPI_EX_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sram.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sram.h
new file mode 100644
index 00000000..9ffc6f09
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sram.h
@@ -0,0 +1,231 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_sram.h
+ * @author MCD Application Team
+ * @brief Header file of SRAM HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_SRAM_H
+#define STM32U5xx_HAL_SRAM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_ll_fmc.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+/** @addtogroup SRAM
+ * @{
+ */
+
+/* Exported typedef ----------------------------------------------------------*/
+
+/** @defgroup SRAM_Exported_Types SRAM Exported Types
+ * @{
+ */
+/**
+ * @brief HAL SRAM State structures definition
+ */
+typedef enum
+{
+ HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */
+ HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */
+ HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */
+ HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */
+ HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */
+
+} HAL_SRAM_StateTypeDef;
+
+/**
+ * @brief SRAM handle Structure definition
+ */
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+typedef struct __SRAM_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
+{
+ FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
+
+ FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
+
+ FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */
+
+ HAL_LockTypeDef Lock; /*!< SRAM locking object */
+
+ __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */
+
+ DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
+
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+ void (* MspInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp Init callback */
+ void (* MspDeInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp DeInit callback */
+ void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Complete callback */
+ void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Error callback */
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
+} SRAM_HandleTypeDef;
+
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL SRAM Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_SRAM_MSP_INIT_CB_ID = 0x00U, /*!< SRAM MspInit Callback ID */
+ HAL_SRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SRAM MspDeInit Callback ID */
+ HAL_SRAM_DMA_XFER_CPLT_CB_ID = 0x02U, /*!< SRAM DMA Xfer Complete Callback ID */
+ HAL_SRAM_DMA_XFER_ERR_CB_ID = 0x03U /*!< SRAM DMA Xfer Complete Callback ID */
+} HAL_SRAM_CallbackIDTypeDef;
+
+/**
+ * @brief HAL SRAM Callback pointer definition
+ */
+typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram);
+typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma);
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup SRAM_Exported_Macros SRAM Exported Macros
+ * @{
+ */
+
+/** @brief Reset SRAM handle state
+ * @param __HANDLE__ SRAM handle
+ * @retval None
+ */
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_SRAM_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SRAM_Exported_Functions SRAM Exported Functions
+ * @{
+ */
+
+/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions ********************************/
+HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing,
+ FMC_NORSRAM_TimingTypeDef *ExtTiming);
+HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
+void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
+void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
+
+/**
+ * @}
+ */
+
+/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
+ * @{
+ */
+
+/* I/O operation functions ***************************************************/
+HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
+ uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
+ uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
+ uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
+ uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
+ uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
+ uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
+ uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
+ uint32_t BufferSize);
+
+void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
+void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
+
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+/* SRAM callback registering/unregistering */
+HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
+ pSRAM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId);
+HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
+ pSRAM_DmaCallbackTypeDef pCallback);
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SRAM_Exported_Functions_Group3 Control functions
+ * @{
+ */
+
+/* SRAM Control functions ****************************************************/
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
+
+/**
+ * @}
+ */
+
+/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
+
+/* SRAM State functions ******************************************************/
+HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_SRAM_H */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_tim.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_tim.h
new file mode 100644
index 00000000..0c457b2b
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_tim.h
@@ -0,0 +1,2500 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_tim.h
+ * @author MCD Application Team
+ * @brief Header file of TIM HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_TIM_H
+#define STM32U5xx_HAL_TIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup TIM
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIM_Exported_Types TIM Exported Types
+ * @{
+ */
+
+/**
+ * @brief TIM Time base Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF
+ Macro __HAL_TIM_CALC_PSC() can be used to calculate prescaler value */
+
+ uint32_t CounterMode; /*!< Specifies the counter mode.
+ This parameter can be a value of @ref TIM_Counter_Mode */
+
+ uint32_t Period; /*!< Specifies the period value to be loaded into the active
+ Auto-Reload Register at the next update event.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF
+ (or 0xFFEF if dithering is activated)Macros __HAL_TIM_CALC_PERIOD(),
+ __HAL_TIM_CALC_PERIOD_DITHER(),__HAL_TIM_CALC_PERIOD_BY_DELAY(),
+ __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY()can be used to calculate Period value */
+
+ uint32_t ClockDivision; /*!< Specifies the clock division.
+ This parameter can be a value of @ref TIM_ClockDivision */
+
+ uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
+ reaches zero, an update event is generated and counting restarts
+ from the RCR value (N).
+ This means in PWM mode that (N+1) corresponds to:
+ - the number of PWM periods in edge-aligned mode
+ - the number of half PWM period in center-aligned mode
+ GP timers: this parameter must be a number between Min_Data = 0x00 and
+ Max_Data = 0xFF.
+ Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
+ Max_Data = 0xFFFF. */
+
+ uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
+ This parameter can be a value of @ref TIM_AutoReloadPreload */
+} TIM_Base_InitTypeDef;
+
+/**
+ * @brief TIM Output Compare Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t OCMode; /*!< Specifies the TIM mode.
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF
+ (or 0xFFEF if dithering is activated)
+ Macros __HAL_TIM_CALC_PULSE(), __HAL_TIM_CALC_PULSE_DITHER() can be used to calculate
+ Pulse value */
+
+ uint32_t OCPolarity; /*!< Specifies the output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+ @note This parameter is valid only for timer instances supporting break feature. */
+
+ uint32_t OCFastMode; /*!< Specifies the Fast mode state.
+ This parameter can be a value of @ref TIM_Output_Fast_State
+ @note This parameter is valid only in PWM1 and PWM2 mode. */
+
+
+ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+ @note This parameter is valid only for timer instances supporting break feature. */
+
+ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+ @note This parameter is valid only for timer instances supporting break feature. */
+} TIM_OC_InitTypeDef;
+
+/**
+ * @brief TIM One Pulse Mode Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t OCMode; /*!< Specifies the TIM mode.
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF
+ (or 0xFFEF if dithering is activated)
+ Macros __HAL_TIM_CALC_PULSE(), __HAL_TIM_CALC_PULSE_DITHER() can be used to calculate
+ Pulse value */
+
+ uint32_t OCPolarity; /*!< Specifies the output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+ @note This parameter is valid only for timer instances supporting break feature. */
+
+ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+ @note This parameter is valid only for timer instances supporting break feature. */
+
+ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+ @note This parameter is valid only for timer instances supporting break feature. */
+
+ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t ICSelection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint32_t ICFilter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_OnePulse_InitTypeDef;
+
+/**
+ * @brief TIM Input Capture Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t ICSelection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint32_t ICFilter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_IC_InitTypeDef;
+
+/**
+ * @brief TIM Encoder Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Encoder_Mode */
+
+ uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
+
+ uint32_t IC1Selection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint32_t IC1Filter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+ uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
+
+ uint32_t IC2Selection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint32_t IC2Filter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_Encoder_InitTypeDef;
+
+/**
+ * @brief Clock Configuration Handle Structure definition
+ */
+typedef struct
+{
+ uint32_t ClockSource; /*!< TIM clock sources
+ This parameter can be a value of @ref TIM_Clock_Source */
+ uint32_t ClockPolarity; /*!< TIM clock polarity
+ This parameter can be a value of @ref TIM_Clock_Polarity */
+ uint32_t ClockPrescaler; /*!< TIM clock prescaler
+ This parameter can be a value of @ref TIM_Clock_Prescaler */
+ uint32_t ClockFilter; /*!< TIM clock filter
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_ClockConfigTypeDef;
+
+/**
+ * @brief TIM Clear Input Configuration Handle Structure definition
+ */
+typedef struct
+{
+ uint32_t ClearInputState; /*!< TIM clear Input state
+ This parameter can be ENABLE or DISABLE */
+ uint32_t ClearInputSource; /*!< TIM clear Input sources
+ This parameter can be a value of @ref TIM_ClearInput_Source */
+ uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
+ This parameter can be a value of @ref TIM_ClearInput_Polarity */
+ uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
+ This parameter must be 0: When OCRef clear feature is used with ETR source,
+ ETR prescaler must be off */
+ uint32_t ClearInputFilter; /*!< TIM Clear Input filter
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_ClearInputConfigTypeDef;
+
+/**
+ * @brief TIM Master configuration Structure definition
+ * @note Advanced timers provide TRGO2 internal line which is redirected
+ * to the ADC
+ */
+typedef struct
+{
+ uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
+ This parameter can be a value of @ref TIM_Master_Mode_Selection */
+ uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection
+ This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
+ uint32_t MasterSlaveMode; /*!< Master/slave mode selection
+ This parameter can be a value of @ref TIM_Master_Slave_Mode
+ @note When the Master/slave mode is enabled, the effect of
+ an event on the trigger input (TRGI) is delayed to allow a
+ perfect synchronization between the current timer and its
+ slaves (through TRGO). It is not mandatory in case of timer
+ synchronization mode. */
+} TIM_MasterConfigTypeDef;
+
+/**
+ * @brief TIM Slave configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t SlaveMode; /*!< Slave mode selection
+ This parameter can be a value of @ref TIM_Slave_Mode */
+ uint32_t InputTrigger; /*!< Input Trigger source
+ This parameter can be a value of @ref TIM_Trigger_Selection */
+ uint32_t TriggerPolarity; /*!< Input Trigger polarity
+ This parameter can be a value of @ref TIM_Trigger_Polarity */
+ uint32_t TriggerPrescaler; /*!< Input trigger prescaler
+ This parameter can be a value of @ref TIM_Trigger_Prescaler */
+ uint32_t TriggerFilter; /*!< Input trigger filter
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+} TIM_SlaveConfigTypeDef;
+
+/**
+ * @brief TIM Break input(s) and Dead time configuration Structure definition
+ * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
+ * filter and polarity.
+ */
+typedef struct
+{
+ uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
+
+ uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
+
+ uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */
+
+ uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+
+ uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */
+
+ uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */
+
+ uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+ uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.This parameter can be a value of @ref TIM_Break_Input_AF_Mode */
+
+ uint32_t Break2State; /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */
+
+ uint32_t Break2Polarity; /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */
+
+ uint32_t Break2Filter; /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+ uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */
+
+ uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+
+} TIM_BreakDeadTimeConfigTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
+ HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
+ HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
+ HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
+ HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
+} HAL_TIM_StateTypeDef;
+
+/**
+ * @brief TIM Channel States definition
+ */
+typedef enum
+{
+ HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */
+ HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */
+ HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */
+} HAL_TIM_ChannelStateTypeDef;
+
+/**
+ * @brief DMA Burst States definition
+ */
+typedef enum
+{
+ HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */
+ HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */
+ HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */
+} HAL_TIM_DMABurstStateTypeDef;
+
+/**
+ * @brief HAL Active channel structures definition
+ */
+typedef enum
+{
+ HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
+ HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
+ HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
+ HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
+ HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */
+ HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */
+ HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */
+} HAL_TIM_ActiveChannel;
+
+/**
+ * @brief TIM Time Base Handle Structure definition
+ */
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+typedef struct __TIM_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+{
+ TIM_TypeDef *Instance; /*!< Register base address */
+ TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
+ HAL_TIM_ActiveChannel Channel; /*!< Active channel */
+ DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
+ This array is accessed by a @ref DMA_Handle_index */
+ HAL_LockTypeDef Lock; /*!< Locking object */
+ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
+ __IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */
+ __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */
+ __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */
+ void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */
+ void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */
+ void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */
+ void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */
+ void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */
+ void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */
+ void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */
+ void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */
+ void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */
+ void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */
+ void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */
+ void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */
+ void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */
+ void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */
+ void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */
+ void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */
+ void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */
+ void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */
+ void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */
+ void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */
+ void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */
+ void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */
+ void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */
+ void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */
+ void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */
+ void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */
+ void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */
+ void (* EncoderIndexCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Index Callback */
+ void (* DirectionChangeCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Direction Change Callback */
+ void (* IndexErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Index Error Callback */
+ void (* TransitionErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Transition Error Callback */
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+} TIM_HandleTypeDef;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL TIM Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
+ , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
+ , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
+ , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
+ , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
+ , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
+ , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
+ , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
+ , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
+ , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
+ , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
+ , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
+ , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
+ , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
+ , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
+ , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
+ , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
+ , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
+
+ , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
+ , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
+ , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
+ , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
+ , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
+ , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
+ , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
+ , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */
+ , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
+ , HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */
+ , HAL_TIM_ENCODER_INDEX_CB_ID = 0x1CU /*!< TIM Encoder Index Callback ID */
+ , HAL_TIM_DIRECTION_CHANGE_CB_ID = 0x1DU /*!< TIM Direction Change Callback ID */
+ , HAL_TIM_INDEX_ERROR_CB_ID = 0x1EU /*!< TIM Index Error Callback ID */
+ , HAL_TIM_TRANSITION_ERROR_CB_ID = 0x1FU /*!< TIM Transition Error Callback ID */
+} HAL_TIM_CallbackIDTypeDef;
+
+/**
+ * @brief HAL TIM Callback pointer definition
+ */
+typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */
+
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+/* End of exported types -----------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_Exported_Constants TIM Exported Constants
+ * @{
+ */
+
+/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
+ * @{
+ */
+#define TIM_CLEARINPUTSOURCE_NONE 0xFFFFFFFFU /*!< OCREF_CLR is disabled */
+#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */
+#define TIM_CLEARINPUTSOURCE_COMP1 0x00000000U /*!< OCREF_CLR_INT is connected to COMP1 output */
+#define TIM_CLEARINPUTSOURCE_COMP2 TIM1_AF2_OCRSEL_0 /*!< OCREF_CLR_INT is connected to COMP2 output */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
+ * @{
+ */
+#define TIM_DMABASE_CR1 0x00000000U
+#define TIM_DMABASE_CR2 0x00000001U
+#define TIM_DMABASE_SMCR 0x00000002U
+#define TIM_DMABASE_DIER 0x00000003U
+#define TIM_DMABASE_SR 0x00000004U
+#define TIM_DMABASE_EGR 0x00000005U
+#define TIM_DMABASE_CCMR1 0x00000006U
+#define TIM_DMABASE_CCMR2 0x00000007U
+#define TIM_DMABASE_CCER 0x00000008U
+#define TIM_DMABASE_CNT 0x00000009U
+#define TIM_DMABASE_PSC 0x0000000AU
+#define TIM_DMABASE_ARR 0x0000000BU
+#define TIM_DMABASE_RCR 0x0000000CU
+#define TIM_DMABASE_CCR1 0x0000000DU
+#define TIM_DMABASE_CCR2 0x0000000EU
+#define TIM_DMABASE_CCR3 0x0000000FU
+#define TIM_DMABASE_CCR4 0x00000010U
+#define TIM_DMABASE_BDTR 0x00000011U
+#define TIM_DMABASE_CCR5 0x00000012U
+#define TIM_DMABASE_CCR6 0x00000013U
+#define TIM_DMABASE_CCMR3 0x00000014U
+#define TIM_DMABASE_DTR2 0x00000015U
+#define TIM_DMABASE_ECR 0x00000016U
+#define TIM_DMABASE_TISEL 0x00000017U
+#define TIM_DMABASE_AF1 0x00000018U
+#define TIM_DMABASE_AF2 0x00000019U
+#define TIM_DMABASE_OR1 0x0000001AU
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Event_Source TIM Event Source
+ * @{
+ */
+#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
+#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
+#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
+#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
+#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
+#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */
+#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */
+#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */
+#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
+ * @{
+ */
+#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */
+#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */
+#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
+ * @{
+ */
+#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */
+#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
+ * @{
+ */
+#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */
+#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */
+#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */
+#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Counter_Mode TIM Counter Mode
+ * @{
+ */
+#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */
+#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */
+#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */
+#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */
+#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap
+ * @{
+ */
+#define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */
+#define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ClockDivision TIM Clock Division
+ * @{
+ */
+#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */
+#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */
+#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_State TIM Output Compare State
+ * @{
+ */
+#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */
+#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
+ * @{
+ */
+#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */
+#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Fast_State TIM Output Fast State
+ * @{
+ */
+#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */
+#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
+ * @{
+ */
+#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */
+#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
+ * @{
+ */
+#define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */
+#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
+ * @{
+ */
+#define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */
+#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
+ * @{
+ */
+#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */
+#define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
+ * @{
+ */
+#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */
+#define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
+ * @{
+ */
+#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */
+#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */
+#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
+ * @{
+ */
+#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */
+#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
+ * @{
+ */
+#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */
+#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
+ * @{
+ */
+#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */
+#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */
+#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */
+#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
+ * @{
+ */
+#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
+#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
+ * @{
+ */
+#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */
+#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
+#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
+#define TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1) /*!< Encoder mode: Clock plus direction, x2 mode */
+#define TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode: Clock plus direction, x1 mode, TI2FP2 edge sensitivity is set by CC2P */
+#define TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2) /*!< Encoder mode: Directional Clock, x2 mode */
+#define TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Encoder mode: Directional Clock, x1 mode, TI1FP1 and TI2FP2 edge sensitivity is set by CC1P and CC2P */
+#define TIM_ENCODERMODE_X1_TI1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Quadrature encoder mode: x1 mode, counting on TI1FP1 edges only, edge sensitivity is set by CC1P */
+#define TIM_ENCODERMODE_X1_TI2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode: x1 mode, counting on TI2FP2 edges only, edge sensitivity is set by CC1P */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
+ * @{
+ */
+#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */
+#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */
+#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */
+#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */
+#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */
+#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */
+#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */
+#define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */
+#define TIM_IT_IDX TIM_DIER_IDXIE /*!< Index interrupt */
+#define TIM_IT_DIR TIM_DIER_DIRIE /*!< Direction change interrupt */
+#define TIM_IT_IERR TIM_DIER_IERRIE /*!< Index error interrupt */
+#define TIM_IT_TERR TIM_DIER_TERRIE /*!< Transition error interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Commutation_Source TIM Commutation Source
+ * @{
+ */
+#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */
+#define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_sources TIM DMA Sources
+ * @{
+ */
+#define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */
+#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */
+#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */
+#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */
+#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */
+#define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */
+#define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Flag_definition TIM Flag Definition
+ * @{
+ */
+#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */
+#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */
+#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */
+#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */
+#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */
+#define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */
+#define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */
+#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */
+#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */
+#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */
+#define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */
+#define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */
+#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */
+#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */
+#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */
+#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */
+#define TIM_FLAG_IDX TIM_SR_IDXF /*!< Encoder index flag */
+#define TIM_FLAG_DIR TIM_SR_DIRF /*!< Direction change flag */
+#define TIM_FLAG_IERR TIM_SR_IERRF /*!< Index error flag */
+#define TIM_FLAG_TERR TIM_SR_TERRF /*!< Transition error flag */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Channel TIM Channel
+ * @{
+ */
+#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */
+#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */
+#define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */
+#define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */
+#define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */
+#define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */
+#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Clock_Source TIM Clock Source
+ * @{
+ */
+#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */
+#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */
+#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */
+#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */
+#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */
+#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */
+#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
+#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */
+#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */
+#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */
+#define TIM_CLOCKSOURCE_ITR4 TIM_TS_ITR4 /*!< External clock source mode 1 (ITR4) */
+#define TIM_CLOCKSOURCE_ITR5 TIM_TS_ITR5 /*!< External clock source mode 1 (ITR5) */
+#define TIM_CLOCKSOURCE_ITR6 TIM_TS_ITR6 /*!< External clock source mode 1 (ITR6) */
+#define TIM_CLOCKSOURCE_ITR7 TIM_TS_ITR7 /*!< External clock source mode 1 (ITR7) */
+#define TIM_CLOCKSOURCE_ITR8 TIM_TS_ITR8 /*!< External clock source mode 1 (ITR8) */
+#define TIM_CLOCKSOURCE_ITR11 TIM_TS_ITR11 /*!< External clock source mode 1 (ITR11) */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
+ * @{
+ */
+#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
+ * @{
+ */
+#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
+#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
+#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
+ * @{
+ */
+#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
+#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
+ * @{
+ */
+#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
+ * @{
+ */
+#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */
+#define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
+ * @{
+ */
+#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */
+#define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
+/**
+ * @}
+ */
+/** @defgroup TIM_Lock_level TIM Lock level
+ * @{
+ */
+#define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */
+#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
+#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
+#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
+ * @{
+ */
+#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */
+#define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
+ * @{
+ */
+#define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
+#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break_Input_AF_Mode TIM Break Input Alternate Function Mode
+ * @{
+ */
+#define TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */
+#define TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable
+ * @{
+ */
+#define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */
+#define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity
+ * @{
+ */
+#define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
+#define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break2_Input_AF_Mode TIM Break2 Input Alternate Function Mode
+ * @{
+ */
+#define TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */
+#define TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
+ * @{
+ */
+#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
+#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3
+ * @{
+ */
+#define TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
+#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
+#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
+#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
+ * @{
+ */
+#define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */
+#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */
+#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */
+#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */
+#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */
+#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */
+#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */
+#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */
+#define TIM_TRGO_ENCODER_CLK TIM_CR2_MMS_3 /*!< Encoder clock is used as trigger output(TRGO) */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)
+ * @{
+ */
+#define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */
+#define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */
+#define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */
+#define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */
+#define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */
+#define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */
+#define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */
+#define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */
+#define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */
+#define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */
+#define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */
+#define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */
+#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */
+#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */
+#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */
+#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
+ * @{
+ */
+#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */
+#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Slave_Mode TIM Slave mode
+ * @{
+ */
+#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */
+#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */
+#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */
+#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */
+#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */
+#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */
+#define TIM_SLAVEMODE_COMBINED_GATEDRESET (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0) /*!< Combined gated + reset mode */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
+ * @{
+ */
+#define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */
+#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */
+#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */
+#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */
+#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */
+#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */
+#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */
+#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */
+#define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */
+#define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */
+#define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */
+#define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */
+#define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */
+#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */
+#define TIM_OCMODE_PULSE_ON_COMPARE (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1) /*!< Pulse on compare (CH3&CH4 only) */
+#define TIM_OCMODE_DIRECTION_OUTPUT (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0) /*!< Direction output (CH3&CH4 only) */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
+ * @{
+ */
+#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */
+#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */
+#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */
+#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */
+#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */
+#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */
+#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */
+#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */
+#define TIM_TS_ITR4 (TIM_SMCR_TS_3) /*!< Internal Trigger 4 (ITR4) */
+#define TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3) /*!< Internal Trigger 5 (ITR5) */
+#define TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 6 (ITR6) */
+#define TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 7 (ITR7) */
+#define TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 8 (ITR8) */
+#define TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) */
+#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
+ * @{
+ */
+#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
+#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
+#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
+ * @{
+ */
+#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
+#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
+#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
+ * @{
+ */
+#define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */
+#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
+ * @{
+ */
+#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_19TRANSFERS 0x00001200U /*!< The transfer is done to 19 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_20TRANSFERS 0x00001300U /*!< The transfer is done to 20 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_21TRANSFERS 0x00001400U /*!< The transfer is done to 21 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_22TRANSFERS 0x00001500U /*!< The transfer is done to 22 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_23TRANSFERS 0x00001600U /*!< The transfer is done to 23 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_24TRANSFERS 0x00001700U /*!< The transfer is done to 24 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_25TRANSFERS 0x00001800U /*!< The transfer is done to 25 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_26TRANSFERS 0x00001900U /*!< The transfer is done to 26 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Handle_index TIM DMA Handle Index
+ * @{
+ */
+#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */
+#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
+#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
+#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
+#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
+#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */
+#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */
+/**
+ * @}
+ */
+
+/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
+ * @{
+ */
+#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */
+#define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */
+#define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */
+#define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break_System TIM Break System
+ * @{
+ */
+#define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17/20 */
+#define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17/20 Break Input and also the PVDE and PLS bits of the Power Control Interface */
+#define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17/20 */
+#define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17/20 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* End of exported constants -------------------------------------------------*/
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup TIM_Exported_Macros TIM Exported Macros
+ * @{
+ */
+
+/** @brief Reset TIM handle state.
+ * @param __HANDLE__ TIM handle.
+ * @retval None
+ */
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
+ (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
+ (__HANDLE__)->Base_MspInitCallback = NULL; \
+ (__HANDLE__)->Base_MspDeInitCallback = NULL; \
+ (__HANDLE__)->IC_MspInitCallback = NULL; \
+ (__HANDLE__)->IC_MspDeInitCallback = NULL; \
+ (__HANDLE__)->OC_MspInitCallback = NULL; \
+ (__HANDLE__)->OC_MspDeInitCallback = NULL; \
+ (__HANDLE__)->PWM_MspInitCallback = NULL; \
+ (__HANDLE__)->PWM_MspDeInitCallback = NULL; \
+ (__HANDLE__)->OnePulse_MspInitCallback = NULL; \
+ (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
+ (__HANDLE__)->Encoder_MspInitCallback = NULL; \
+ (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
+ (__HANDLE__)->HallSensor_MspInitCallback = NULL; \
+ (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
+ (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
+ } while(0)
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+ * @brief Enable the TIM peripheral.
+ * @param __HANDLE__ TIM handle
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
+
+/**
+ * @brief Enable the TIM main Output.
+ * @param __HANDLE__ TIM handle
+ * @retval None
+ */
+#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
+
+/**
+ * @brief Disable the TIM peripheral.
+ * @param __HANDLE__ TIM handle
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE(__HANDLE__) \
+ do { \
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
+ { \
+ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
+ { \
+ (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
+ } \
+ } \
+ } while(0)
+
+/**
+ * @brief Disable the TIM main Output.
+ * @param __HANDLE__ TIM handle
+ * @retval None
+ * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been
+ * disabled
+ */
+#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
+ do { \
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
+ { \
+ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
+ { \
+ (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
+ } \
+ } \
+ } while(0)
+
+/**
+ * @brief Disable the TIM main Output.
+ * @param __HANDLE__ TIM handle
+ * @retval None
+ * @note The Main Output Enable of a timer instance is disabled unconditionally
+ */
+#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
+
+/** @brief Enable the specified TIM interrupt.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __INTERRUPT__ specifies the TIM interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg TIM_IT_UPDATE: Update interrupt
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
+ * @arg TIM_IT_COM: Commutation interrupt
+ * @arg TIM_IT_TRIGGER: Trigger interrupt
+ * @arg TIM_IT_BREAK: Break interrupt
+ * @arg TIM_IT_IDX: Index interrupt
+ * @arg TIM_IT_DIR: Direction change interrupt
+ * @arg TIM_IT_IERR: Index error interrupt
+ * @arg TIM_IT_TERR: Transition error interrupt
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
+
+/** @brief Disable the specified TIM interrupt.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __INTERRUPT__ specifies the TIM interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg TIM_IT_UPDATE: Update interrupt
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
+ * @arg TIM_IT_COM: Commutation interrupt
+ * @arg TIM_IT_TRIGGER: Trigger interrupt
+ * @arg TIM_IT_BREAK: Break interrupt
+ * @arg TIM_IT_IDX: Index interrupt
+ * @arg TIM_IT_DIR: Direction change interrupt
+ * @arg TIM_IT_IERR: Index error interrupt
+ * @arg TIM_IT_TERR: Transition error interrupt
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
+
+/** @brief Enable the specified DMA request.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __DMA__ specifies the TIM DMA request to enable.
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: Update DMA request
+ * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
+ * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
+ * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
+ * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
+ * @arg TIM_DMA_COM: Commutation DMA request
+ * @arg TIM_DMA_TRIGGER: Trigger DMA request
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
+
+/** @brief Disable the specified DMA request.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __DMA__ specifies the TIM DMA request to disable.
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: Update DMA request
+ * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
+ * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
+ * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
+ * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
+ * @arg TIM_DMA_COM: Commutation DMA request
+ * @arg TIM_DMA_TRIGGER: Trigger DMA request
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
+
+/** @brief Check whether the specified TIM interrupt flag is set or not.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __FLAG__ specifies the TIM interrupt flag to check.
+ * This parameter can be one of the following values:
+ * @arg TIM_FLAG_UPDATE: Update interrupt flag
+ * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+ * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+ * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+ * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+ * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
+ * @arg TIM_FLAG_CC6: Compare 6 interrupt flag
+ * @arg TIM_FLAG_COM: Commutation interrupt flag
+ * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+ * @arg TIM_FLAG_BREAK: Break interrupt flag
+ * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
+ * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
+ * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+ * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+ * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+ * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+ * @arg TIM_FLAG_IDX: Index interrupt flag
+ * @arg TIM_FLAG_DIR: Direction change interrupt flag
+ * @arg TIM_FLAG_IERR: Index error interrupt flag
+ * @arg TIM_FLAG_TERR: Transition error interrupt flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the specified TIM interrupt flag.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __FLAG__ specifies the TIM interrupt flag to clear.
+ * This parameter can be one of the following values:
+ * @arg TIM_FLAG_UPDATE: Update interrupt flag
+ * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+ * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+ * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+ * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+ * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
+ * @arg TIM_FLAG_CC6: Compare 6 interrupt flag
+ * @arg TIM_FLAG_COM: Commutation interrupt flag
+ * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+ * @arg TIM_FLAG_BREAK: Break interrupt flag
+ * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
+ * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
+ * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+ * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+ * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+ * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+ * @arg TIM_FLAG_IDX: Index interrupt flag
+ * @arg TIM_FLAG_DIR: Direction change interrupt flag
+ * @arg TIM_FLAG_IERR: Index error interrupt flag
+ * @arg TIM_FLAG_TERR: Transition error interrupt flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+
+/**
+ * @brief Check whether the specified TIM interrupt source is enabled or not.
+ * @param __HANDLE__ TIM handle
+ * @param __INTERRUPT__ specifies the TIM interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg TIM_IT_UPDATE: Update interrupt
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
+ * @arg TIM_IT_COM: Commutation interrupt
+ * @arg TIM_IT_TRIGGER: Trigger interrupt
+ * @arg TIM_IT_BREAK: Break interrupt
+ * @arg TIM_IT_IDX: Index interrupt
+ * @arg TIM_IT_DIR: Direction change interrupt
+ * @arg TIM_IT_IERR: Index error interrupt
+ * @arg TIM_IT_TERR: Transition error interrupt
+ * @retval The state of TIM_IT (SET or RESET).
+ */
+#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
+ == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Clear the TIM interrupt pending bits.
+ * @param __HANDLE__ TIM handle
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
+ * This parameter can be one of the following values:
+ * @arg TIM_IT_UPDATE: Update interrupt
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
+ * @arg TIM_IT_COM: Commutation interrupt
+ * @arg TIM_IT_TRIGGER: Trigger interrupt
+ * @arg TIM_IT_BREAK: Break interrupt
+ * @arg TIM_IT_IDX: Index interrupt
+ * @arg TIM_IT_DIR: Direction change interrupt
+ * @arg TIM_IT_IERR: Index error interrupt
+ * @arg TIM_IT_TERR: Transition error interrupt
+ * @retval None
+ */
+#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
+
+/**
+ * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
+ * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
+ * in an atomic way.
+ * @param __HANDLE__ TIM handle.
+ * @retval None
+mode.
+ */
+#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP))
+
+/**
+ * @brief Disable update interrupt flag (UIF) remapping.
+ * @param __HANDLE__ TIM handle.
+ * @retval None
+mode.
+ */
+#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP))
+
+/**
+ * @brief Get update interrupt flag (UIF) copy status.
+ * @param __COUNTER__ Counter value.
+ * @retval The state of UIFCPY (TRUE or FALSE).
+mode.
+ */
+#define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY))
+
+/**
+ * @brief Indicates whether or not the TIM Counter is used as downcounter.
+ * @param __HANDLE__ TIM handle.
+ * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
+ * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode
+ * or Encoder mode.
+ */
+#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
+
+/**
+ * @brief Set the TIM Prescaler on runtime.
+ * @param __HANDLE__ TIM handle.
+ * @param __PRESC__ specifies the Prescaler new value.
+ * @retval None
+ */
+#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
+
+/**
+ * @brief Set the TIM Counter Register value on runtime.
+ * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in
+ * case of 32 bits counter TIM instance.
+ * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros.
+ * @param __HANDLE__ TIM handle.
+ * @param __COUNTER__ specifies the Counter register new value.
+ * @retval None
+ */
+#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
+
+/**
+ * @brief Get the TIM Counter Register value on runtime.
+ * @param __HANDLE__ TIM handle.
+ * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
+ */
+#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
+
+/**
+ * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.
+ * @param __HANDLE__ TIM handle.
+ * @param __AUTORELOAD__ specifies the Counter register new value.
+ * @retval None
+ */
+#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
+ do{ \
+ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
+ (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
+ } while(0)
+
+/**
+ * @brief Get the TIM Autoreload Register value on runtime.
+ * @param __HANDLE__ TIM handle.
+ * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
+ */
+#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
+
+/**
+ * @brief Set the TIM Clock Division value on runtime without calling another time any Init function.
+ * @param __HANDLE__ TIM handle.
+ * @param __CKD__ specifies the clock division value.
+ * This parameter can be one of the following value:
+ * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
+ * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
+ * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
+ * @retval None
+ */
+#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
+ do{ \
+ (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
+ (__HANDLE__)->Instance->CR1 |= (__CKD__); \
+ (__HANDLE__)->Init.ClockDivision = (__CKD__); \
+ } while(0)
+
+/**
+ * @brief Get the TIM Clock Division value on runtime.
+ * @param __HANDLE__ TIM handle.
+ * @retval The clock division can be one of the following values:
+ * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
+ * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
+ * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
+ */
+#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
+
+/**
+ * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel()
+ * function.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param __ICPSC__ specifies the Input Capture4 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPSC_DIV1: no prescaler
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+ * @retval None
+ */
+#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
+ do{ \
+ TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
+ TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
+ } while(0)
+
+/**
+ * @brief Get the TIM Input Capture prescaler on runtime.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
+ * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
+ * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
+ * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
+ * @retval The input capture prescaler can be one of the following values:
+ * @arg TIM_ICPSC_DIV1: no prescaler
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+ */
+#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
+ (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
+
+/**
+ * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @param __COMPARE__ specifies the Capture Compare register new value.
+ * @retval None
+ */
+#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
+ ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
+
+/**
+ * @brief Get the TIM Capture Compare Register value on runtime.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channel associated with the capture compare register
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: get capture/compare 1 register value
+ * @arg TIM_CHANNEL_2: get capture/compare 2 register value
+ * @arg TIM_CHANNEL_3: get capture/compare 3 register value
+ * @arg TIM_CHANNEL_4: get capture/compare 4 register value
+ * @arg TIM_CHANNEL_5: get capture/compare 5 register value
+ * @arg TIM_CHANNEL_6: get capture/compare 6 register value
+ * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
+ */
+#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
+ ((__HANDLE__)->Instance->CCR6))
+
+/**
+ * @brief Set the TIM Output compare preload.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
+ ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
+
+/**
+ * @brief Reset the TIM Output compare preload.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\
+ ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE))
+
+/**
+ * @brief Enable fast mode for a given channel.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @note When fast mode is enabled an active edge on the trigger input acts
+ * like a compare match on CCx output. Delay to sample the trigger
+ * input and to activate CCx output is reduced to 3 clock cycles.
+ * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\
+ ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE))
+
+/**
+ * @brief Disable fast mode for a given channel.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @note When fast mode is disabled CCx output behaves normally depending
+ * on counter and CCRx values even when the trigger is ON. The minimum
+ * delay to activate CCx output when an active edge occurs on the
+ * trigger input is 5 clock cycles.
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\
+ ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE))
+
+/**
+ * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
+ * @param __HANDLE__ TIM handle.
+ * @note When the URS bit of the TIMx_CR1 register is set, only counter
+ * overflow/underflow generates an update interrupt or DMA request (if
+ * enabled)
+ * @retval None
+ */
+#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
+
+/**
+ * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
+ * @param __HANDLE__ TIM handle.
+ * @note When the URS bit of the TIMx_CR1 register is reset, any of the
+ * following events generate an update interrupt or DMA request (if
+ * enabled):
+ * _ Counter overflow underflow
+ * _ Setting the UG bit
+ * _ Update generation through the slave mode controller
+ * @retval None
+ */
+#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
+
+/**
+ * @brief Set the TIM Capture x input polarity on runtime.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param __POLARITY__ Polarity for TIx source
+ * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
+ * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
+ * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
+ * @retval None
+ */
+#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
+ do{ \
+ TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
+ TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
+ }while(0)
+
+/**
+ * @}
+ */
+/* End of exported macros ----------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIM_Private_Constants TIM Private Constants
+ * @{
+ */
+/* The counter of a timer instance is disabled only if all the CCx and CCxN
+ channels have been disabled */
+#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
+#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE))
+/**
+ * @}
+ */
+/* End of private constants --------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIM_Private_Macros TIM Private Macros
+ * @{
+ */
+#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \
+ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1) || \
+ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2) || \
+ ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))
+
+#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
+ ((__BASE__) == TIM_DMABASE_CR2) || \
+ ((__BASE__) == TIM_DMABASE_SMCR) || \
+ ((__BASE__) == TIM_DMABASE_DIER) || \
+ ((__BASE__) == TIM_DMABASE_SR) || \
+ ((__BASE__) == TIM_DMABASE_EGR) || \
+ ((__BASE__) == TIM_DMABASE_CCMR1) || \
+ ((__BASE__) == TIM_DMABASE_CCMR2) || \
+ ((__BASE__) == TIM_DMABASE_CCER) || \
+ ((__BASE__) == TIM_DMABASE_CNT) || \
+ ((__BASE__) == TIM_DMABASE_PSC) || \
+ ((__BASE__) == TIM_DMABASE_ARR) || \
+ ((__BASE__) == TIM_DMABASE_RCR) || \
+ ((__BASE__) == TIM_DMABASE_CCR1) || \
+ ((__BASE__) == TIM_DMABASE_CCR2) || \
+ ((__BASE__) == TIM_DMABASE_CCR3) || \
+ ((__BASE__) == TIM_DMABASE_CCR4) || \
+ ((__BASE__) == TIM_DMABASE_BDTR) || \
+ ((__BASE__) == TIM_DMABASE_CCMR3) || \
+ ((__BASE__) == TIM_DMABASE_CCR5) || \
+ ((__BASE__) == TIM_DMABASE_CCR6) || \
+ ((__BASE__) == TIM_DMABASE_AF1) || \
+ ((__BASE__) == TIM_DMABASE_AF2) || \
+ ((__BASE__) == TIM_DMABASE_TISEL) || \
+ ((__BASE__) == TIM_DMABASE_DTR2) || \
+ ((__BASE__) == TIM_DMABASE_ECR) || \
+ ((__BASE__) == TIM_DMABASE_OR1))
+
+#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
+
+#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \
+ ((__MODE__) == TIM_COUNTERMODE_DOWN) || \
+ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \
+ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
+ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
+
+#define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \
+ ((__MODE__) == TIM_UIFREMAP_ENALE))
+
+#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
+ ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
+ ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
+
+#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
+ ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
+
+#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \
+ ((__STATE__) == TIM_OCFAST_ENABLE))
+
+#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
+ ((__POLARITY__) == TIM_OCPOLARITY_LOW))
+
+#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
+ ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
+
+#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \
+ ((__STATE__) == TIM_OCIDLESTATE_RESET))
+
+#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
+ ((__STATE__) == TIM_OCNIDLESTATE_RESET))
+
+#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \
+ ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
+
+#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
+ ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
+ ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
+
+#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
+ ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
+ ((__SELECTION__) == TIM_ICSELECTION_TRC))
+
+#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
+ ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
+ ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
+ ((__PRESCALER__) == TIM_ICPSC_DIV8))
+
+#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
+ ((__MODE__) == TIM_OPMODE_REPETITIVE))
+
+#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \
+ ((__MODE__) == TIM_ENCODERMODE_TI2) || \
+ ((__MODE__) == TIM_ENCODERMODE_TI12) || \
+ ((__MODE__) == TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2) || \
+ ((__MODE__) == TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1) || \
+ ((__MODE__) == TIM_ENCODERMODE_DIRECTIONALCLOCK_X2) || \
+ ((__MODE__) == TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12) || \
+ ((__MODE__) == TIM_ENCODERMODE_X1_TI1) || \
+ ((__MODE__) == TIM_ENCODERMODE_X1_TI2))
+
+#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
+
+#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \
+ ((__CHANNEL__) == TIM_CHANNEL_4) || \
+ ((__CHANNEL__) == TIM_CHANNEL_5) || \
+ ((__CHANNEL__) == TIM_CHANNEL_6) || \
+ ((__CHANNEL__) == TIM_CHANNEL_ALL))
+
+#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
+ ((__CHANNEL__) == TIM_CHANNEL_2))
+
+#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \
+ ((__CHANNEL__) == TIM_CHANNEL_4))
+
+#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))
+
+#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
+ ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
+ ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \
+ ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \
+ ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
+
+#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
+ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
+ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
+ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
+
+#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
+ ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
+
+#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
+ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
+ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
+ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
+
+#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \
+ ((__STATE__) == TIM_OSSR_DISABLE))
+
+#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \
+ ((__STATE__) == TIM_OSSI_DISABLE))
+
+#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
+ ((__LEVEL__) == TIM_LOCKLEVEL_1) || \
+ ((__LEVEL__) == TIM_LOCKLEVEL_2) || \
+ ((__LEVEL__) == TIM_LOCKLEVEL_3))
+
+#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
+
+
+#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
+ ((__STATE__) == TIM_BREAK_DISABLE))
+
+#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
+ ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
+
+#define IS_TIM_BREAK_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK_AFMODE_INPUT) || \
+ ((__AFMODE__) == TIM_BREAK_AFMODE_BIDIRECTIONAL))
+
+
+#define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \
+ ((__STATE__) == TIM_BREAK2_DISABLE))
+
+#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
+ ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
+
+#define IS_TIM_BREAK2_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK2_AFMODE_INPUT) || \
+ ((__AFMODE__) == TIM_BREAK2_AFMODE_BIDIRECTIONAL))
+
+
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
+ ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
+
+#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
+
+#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \
+ ((__SOURCE__) == TIM_TRGO_ENABLE) || \
+ ((__SOURCE__) == TIM_TRGO_UPDATE) || \
+ ((__SOURCE__) == TIM_TRGO_OC1) || \
+ ((__SOURCE__) == TIM_TRGO_OC1REF) || \
+ ((__SOURCE__) == TIM_TRGO_OC2REF) || \
+ ((__SOURCE__) == TIM_TRGO_OC3REF) || \
+ ((__SOURCE__) == TIM_TRGO_OC4REF) || \
+ ((__SOURCE__) == TIM_TRGO_ENCODER_CLK))
+
+#define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \
+ ((__SOURCE__) == TIM_TRGO2_ENABLE) || \
+ ((__SOURCE__) == TIM_TRGO2_UPDATE) || \
+ ((__SOURCE__) == TIM_TRGO2_OC1) || \
+ ((__SOURCE__) == TIM_TRGO2_OC1REF) || \
+ ((__SOURCE__) == TIM_TRGO2_OC2REF) || \
+ ((__SOURCE__) == TIM_TRGO2_OC3REF) || \
+ ((__SOURCE__) == TIM_TRGO2_OC3REF) || \
+ ((__SOURCE__) == TIM_TRGO2_OC4REF) || \
+ ((__SOURCE__) == TIM_TRGO2_OC5REF) || \
+ ((__SOURCE__) == TIM_TRGO2_OC6REF) || \
+ ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \
+ ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \
+ ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \
+ ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
+ ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \
+ ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
+
+#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
+ ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
+
+#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \
+ ((__MODE__) == TIM_SLAVEMODE_RESET) || \
+ ((__MODE__) == TIM_SLAVEMODE_GATED) || \
+ ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \
+ ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \
+ ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER) || \
+ ((__MODE__) == TIM_SLAVEMODE_COMBINED_GATEDRESET))
+
+#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \
+ ((__MODE__) == TIM_OCMODE_PWM2) || \
+ ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \
+ ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \
+ ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \
+ ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
+
+#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \
+ ((__MODE__) == TIM_OCMODE_ACTIVE) || \
+ ((__MODE__) == TIM_OCMODE_INACTIVE) || \
+ ((__MODE__) == TIM_OCMODE_TOGGLE) || \
+ ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \
+ ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \
+ ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
+ ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2) || \
+ ((__MODE__) == TIM_OCMODE_DIRECTION_OUTPUT) || \
+ ((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE))
+
+#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
+ ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_ITR4) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || \
+ ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8) || \
+ ((__SELECTION__) == TIM_TS_ITR11)|| \
+ ((__SELECTION__) == TIM_TS_NONE))
+
+#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \
+ ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
+ ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \
+ ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \
+ ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
+
+#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
+ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
+ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
+ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
+
+#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
+ ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
+
+#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_19TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_20TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_21TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_22TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_23TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_24TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_25TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_26TRANSFERS))
+
+#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
+
+#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
+
+#define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \
+ ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \
+ ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) || \
+ ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
+
+#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \
+ ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
+
+#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
+ ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
+
+#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
+ ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
+
+#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
+ ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
+
+#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
+ ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
+
+#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\
+ (__HANDLE__)->ChannelState[5])
+
+#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\
+ ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__)))
+
+#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
+ (__HANDLE__)->ChannelState[0] = \
+ (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelState[1] = \
+ (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelState[2] = \
+ (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelState[3] = \
+ (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelState[4] = \
+ (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelState[5] = \
+ (__CHANNEL_STATE__); \
+ } while(0)
+
+#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
+ (__HANDLE__)->ChannelNState[3])
+
+#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
+ ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
+
+#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
+ (__HANDLE__)->ChannelNState[0] = \
+ (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelNState[1] = \
+ (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelNState[2] = \
+ (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelNState[3] = \
+ (__CHANNEL_STATE__); \
+ } while(0)
+
+/**
+ * @}
+ */
+/* End of private macros -----------------------------------------------------*/
+
+/* Include TIM HAL Extended module */
+#include "stm32u5xx_hal_tim_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIM_Exported_Functions TIM Exported Functions
+ * @{
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
+ * @brief Time Base functions
+ * @{
+ */
+/* Time Base functions ********************************************************/
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
+ * @brief TIM Output Compare functions
+ * @{
+ */
+/* Timer Output Compare functions *********************************************/
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
+ * @brief TIM PWM functions
+ * @{
+ */
+/* Timer PWM functions ********************************************************/
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
+ * @brief TIM Input Capture functions
+ * @{
+ */
+/* Timer Input Capture functions **********************************************/
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
+ * @brief TIM One Pulse functions
+ * @{
+ */
+/* Timer One Pulse functions **************************************************/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
+ * @brief TIM Encoder functions
+ * @{
+ */
+/* Timer Encoder functions ****************************************************/
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig);
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
+ uint32_t *pData2, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+ * @brief IRQ handler management
+ * @{
+ */
+/* Interrupt Handler functions ***********************************************/
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
+ * @brief Peripheral Control functions
+ * @{
+ */
+/* Control functions *********************************************************/
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
+ uint32_t OutputChannel, uint32_t InputChannel);
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
+ uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
+ uint32_t BurstLength, uint32_t DataLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
+ uint32_t BurstLength, uint32_t DataLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+ * @brief TIM Callbacks functions
+ * @{
+ */
+/* Callback in non blocking modes (Interrupt and DMA) *************************/
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
+ pTIM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
+ * @brief Peripheral State functions
+ * @{
+ */
+/* Peripheral State functions ************************************************/
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
+
+/* Peripheral Channel state functions ************************************************/
+HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim);
+HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private functions----------------------------------------------------------*/
+/** @defgroup TIM_Private_Functions TIM Private Functions
+ * @{
+ */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
+ uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
+
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMAError(DMA_HandleTypeDef *hdma);
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
+HAL_StatusTypeDef TIM_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t src, uint32_t dst,
+ uint32_t length);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+void TIM_ResetCallback(TIM_HandleTypeDef *htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+/* End of private functions --------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_TIM_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_tim_ex.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_tim_ex.h
new file mode 100644
index 00000000..ef7cfd10
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_tim_ex.h
@@ -0,0 +1,1012 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_tim_ex.h
+ * @author MCD Application Team
+ * @brief Header file of TIM HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_TIM_EX_H
+#define STM32U5xx_HAL_TIM_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup TIMEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
+ * @{
+ */
+
+/**
+ * @brief TIM Hall sensor Configuration Structure definition
+ */
+
+typedef struct
+{
+ uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint32_t IC1Filter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+ uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+} TIM_HallSensor_InitTypeDef;
+
+/**
+ * @brief TIM Break/Break2 input configuration
+ */
+typedef struct
+{
+ uint32_t Source; /*!< Specifies the source of the timer break input.
+ This parameter can be a value of @ref TIMEx_Break_Input_Source */
+ uint32_t Enable; /*!< Specifies whether or not the break input source is enabled.
+ This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */
+ uint32_t Polarity; /*!< Specifies the break input source polarity.
+ This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity */
+} TIMEx_BreakInputConfigTypeDef;
+
+/**
+ * @brief TIM Encoder index configuration
+ */
+typedef struct
+{
+ uint32_t Polarity; /*!< TIM Encoder index polarity.This parameter can be a value of @ref TIMEx_Encoder_Index_Polarity */
+
+ uint32_t Prescaler; /*!< TIM Encoder index prescaler.This parameter can be a value of @ref TIMEx_Encoder_Index_Prescaler */
+
+ uint32_t Filter; /*!< TIM Encoder index filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+ uint32_t Blanking; /*!< Specifies whether or not the encoder index event is conditioned by TI3 or TI4 input.This parameter can be a value of @ref TIMEx_Encoder_Index_Blanking */
+
+ FunctionalState FirstIndexEnable; /*!< Specifies whether or not the encoder first index is enabled.This parameter value can be ENABLE or DISABLE. */
+
+ uint32_t Position; /*!< Specifies in which AB input configuration the index event resets the counter.This parameter can be a value of @ref TIMEx_Encoder_Index_Position */
+
+ uint32_t Direction; /*!< Specifies in which counter direction the index event resets the counter.This parameter can be a value of @ref TIMEx_Encoder_Index_Direction */
+
+} TIMEx_EncoderIndexConfigTypeDef;
+
+/**
+ * @}
+ */
+/* End of exported types -----------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
+ * @{
+ */
+
+/** @defgroup TIMEx_Remap TIM Extended Remapping
+ * @{
+ */
+#define TIM_TIM1_ETR_GPIO 0x00000000UL /*!< TIM1_ETR is not connected to I/O */
+#define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM1_ETR is connected to COMP1 output */
+#define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM1_ETR is connected to COMP2 output */
+#define TIM_TIM1_ETR_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to MSIK */
+#define TIM_TIM1_ETR_HSI TIM1_AF1_ETRSEL_2 /*!< TIM1_ETR is connected to HSI */
+#define TIM_TIM1_ETR_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to MSI */
+#define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_3) /*!< TIM1_ETR is connected to ADC1 AWD1 */
+#define TIM_TIM1_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC1 AWD2 */
+#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< TIM1_ETR is connected to ADC1 AWD3 */
+#define TIM_TIM1_ETR_ADC4_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC4 AWD1 */
+#define TIM_TIM1_ETR_ADC4_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< TIM1_ETR is connected to ADC4 AWD2 */
+#define TIM_TIM1_ETR_ADC4_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC4 AWD3 */
+
+#define TIM_TIM2_ETR_GPIO 0x00000000UL /*!< TIM2_ETR is not connected to I/O */
+#define TIM_TIM2_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM2_ETR is connected to COMP1 output */
+#define TIM_TIM2_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM2_ETR is connected to COMP2 output */
+#define TIM_TIM2_ETR_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to MSIK */
+#define TIM_TIM2_ETR_HSI TIM1_AF1_ETRSEL_2 /*!< TIM2_ETR is connected to HSI */
+#define TIM_TIM2_ETR_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to MSIS */
+#define TIM_TIM2_ETR_TIM3_ETR TIM1_AF1_ETRSEL_3 /*!< TIM2_ETR is connected to TIM3 ETR */
+#define TIM_TIM2_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to TIM4 ETR */
+#define TIM_TIM2_ETR_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to TIM5 ETR */
+#define TIM_TIM2_ETR_LSE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to LSE */
+
+#define TIM_TIM3_ETR_GPIO 0x00000000UL /*!< TIM3_ETR is not connected to I/O */
+#define TIM_TIM3_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM3_ETR is connected to COMP1 output */
+#define TIM_TIM3_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM3_ETR is connected to COMP2 output */
+#define TIM_TIM3_ETR_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to MSIK */
+#define TIM_TIM3_ETR_HSI TIM1_AF1_ETRSEL_2 /*!< TIM3_ETR is connected to HSI */
+#define TIM_TIM3_ETR_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to MSIS */
+#define TIM_TIM3_ETR_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< TIM3_ETR is connected to TIM2 ETR */
+#define TIM_TIM3_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to TIM4 ETR */
+#define TIM_TIM3_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to ADC1 AWD1 */
+#define TIM_TIM3_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< TIM3_ETR is connected to ADC1 AWD2 */
+#define TIM_TIM3_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to ADC1 AWD3 */
+
+#define TIM_TIM4_ETR_GPIO 0x00000000UL /*!< TIM4_ETR is not connected to I/O */
+#define TIM_TIM4_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM4_ETR is connected to COMP1 output */
+#define TIM_TIM4_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM4_ETR is connected to COMP2 output */
+#define TIM_TIM4_ETR_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to MSIK */
+#define TIM_TIM4_ETR_HSI TIM1_AF1_ETRSEL_2 /*!< TIM4_ETR is connected to HSI */
+#define TIM_TIM4_ETR_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to MSIS */
+#define TIM_TIM4_ETR_TIM3_ETR TIM1_AF1_ETRSEL_3 /*!< TIM4_ETR is connected to TIM3 ETR */
+#define TIM_TIM4_ETR_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to TIM5 ETR */
+
+#define TIM_TIM5_ETR_GPIO 0x00000000UL /*!< TIM5_ETR is not connected to I/O */
+#define TIM_TIM5_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM5_ETR is connected to COMP1 output */
+#define TIM_TIM5_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM5_ETR is connected to COMP2 output */
+#define TIM_TIM5_ETR_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to MSIK */
+#define TIM_TIM5_ETR_HSI TIM1_AF1_ETRSEL_2 /*!< TIM5_ETR is connected to HSI */
+#define TIM_TIM5_ETR_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to MSIS */
+#define TIM_TIM5_ETR_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< TIM5_ETR is connected to TIM2 ETR */
+#define TIM_TIM5_ETR_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to TIM3 ETR */
+
+#define TIM_TIM8_ETR_GPIO 0x00000000UL /*!< TIM8_ETR is not connected to I/O */
+#define TIM_TIM8_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM8_ETR is connected to COMP1 output */
+#define TIM_TIM8_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM8_ETR is connected to COMP2 output */
+#define TIM_TIM8_ETR_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to MSIK */
+#define TIM_TIM8_ETR_HSI TIM1_AF1_ETRSEL_2 /*!< TIM8_ETR is connected to HSI */
+#define TIM_TIM8_ETR_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to MSIS */
+#define TIM_TIM8_ETR_ADC1_AWD1 TIM1_AF1_ETRSEL_3 /*!< TIM8_ETR is connected to ADC1 AWD1 */
+#define TIM_TIM8_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC1 AWD2 */
+#define TIM_TIM8_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< TIM8_ETR is connected to ADC1 AWD3 */
+#define TIM_TIM8_ETR_ADC4_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC4 AWD1 */
+#define TIM_TIM8_ETR_ADC4_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< TIM8_ETR is connected to ADC4 AWD2 */
+#define TIM_TIM8_ETR_ADC4_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC4 AWD3 */
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Break_Input TIM Extended Break input
+ * @{
+ */
+#define TIM_BREAKINPUT_BRK 0x00000001U /*!< Timer break input */
+#define TIM_BREAKINPUT_BRK2 0x00000002U /*!< Timer break2 input */
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source
+ * @{
+ */
+#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /*!< An external source (GPIO) is connected to the BKIN pin */
+#define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /*!< The COMP1 output is connected to the break input */
+#define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /*!< The COMP2 output is connected to the break input */
+#define TIM_BREAKINPUTSOURCE_MDF1 0x00000008U /*!< The analog watchdog output of the MDF1 peripheral is connected to the break input */
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
+ * @{
+ */
+#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /*!< Break input source is disabled */
+#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /*!< Break input source is enabled */
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity
+ * @{
+ */
+#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /*!< Break input source is active low */
+#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /*!< Break input source is active_high */
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Timer_Input_Selection TIM Extended Timer input selection
+ * @{
+ */
+#define TIM_TIM1_TI1_GPIO 0x00000000UL /*!< TIM1_TI1 is connected to GPIO */
+#define TIM_TIM1_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM1_TI1 is connected to COMP1 OUT */
+#define TIM_TIM1_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM1_TI1 is connected to COMP2 OUT */
+
+#define TIM_TIM2_TI1_GPIO 0x00000000UL /*!< TIM2_TI1 is connected to GPIO */
+#define TIM_TIM2_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM2_TI1 is connected to COMP1 OUT */
+#define TIM_TIM2_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM2_TI1 is connected to COMP2 OUT */
+#define TIM_TIM2_TI2_GPIO 0x00000000UL /*!< TIM2_TI2 is connected to GPIO */
+#define TIM_TIM2_TI2_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM2_TI2 is connected to COMP1 OUT */
+#define TIM_TIM2_TI2_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM2_TI2 is connected to COMP2 OUT */
+#define TIM_TIM2_TI4_GPIO 0x00000000UL /*!< TIM2_TI4 is connected to GPIO */
+#define TIM_TIM2_TI4_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM2_TI4 is connected to COMP1 OUT */
+#define TIM_TIM2_TI4_COMP2 TIM_TISEL_TI4SEL_1 /*!< TIM2_TI4 is connected to COMP2 OUT */
+
+#define TIM_TIM3_TI1_GPIO 0x00000000UL /*!< TIM3_TI1 is connected to GPIO */
+#define TIM_TIM3_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM3_TI1 is connected to COMP1 OUT */
+#define TIM_TIM3_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM3_TI1 is connected to COMP2 OUT */
+#define TIM_TIM3_TI2_GPIO 0x00000000UL /*!< TIM3_TI2 is connected to GPIO */
+#define TIM_TIM3_TI2_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM3_TI2 is connected to COMP1 OUT */
+#define TIM_TIM3_TI2_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM3_TI2 is connected to COMP2 OUT */
+
+#define TIM_TIM4_TI1_GPIO 0x00000000UL /*!< TIM4_TI1 is connected to GPIO */
+#define TIM_TIM4_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM4_TI1 is connected to COMP1 OUT */
+#define TIM_TIM4_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM4_TI1 is connected to COMP2 OUT */
+#define TIM_TIM4_TI2_GPIO 0x00000000UL /*!< TIM4_TI2 is connected to GPIO */
+#define TIM_TIM4_TI2_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM4_TI2 is connected to COMP1 OUT */
+#define TIM_TIM4_TI2_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM4_TI2 is connected to COMP2 OUT */
+
+#define TIM_TIM5_TI1_GPIO 0x00000000UL /*!< TIM5_TI1 is connected to GPIO */
+#define TIM_TIM5_TI1_LSI TIM_TISEL_TI1SEL_0 /*!< TIM5_TI1 is connected to LSI */
+#define TIM_TIM5_TI1_LSE TIM_TISEL_TI1SEL_1 /*!< TIM5_TI1 is connected to LSE */
+#define TIM_TIM5_TI1_RTC_WKUP (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM5_TI1 is connected to RTC Wakeup */
+#define TIM_TIM5_TI1_COMP1 TIM_TISEL_TI1SEL_2 /*!< TIM5_COMP1 is connected to COMP1 OUT */
+#define TIM_TIM5_TI1_COMP2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM5_COMP2 is connected to COMP2 OUT */
+
+#define TIM_TIM5_TI2_GPIO 0x00000000UL /*!< TIM5_TI2 is connected to GPIO */
+#define TIM_TIM5_TI2_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM5_TI2 is connected to COMP1 OUT */
+#define TIM_TIM5_TI2_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM5_TI2 is connected to COMP2 OUT */
+
+#define TIM_TIM8_TI1_GPIO 0x00000000UL /*!< TIM8_TI1 is connected to GPIO */
+#define TIM_TIM8_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM8_TI1 is connected to COMP1 OUT */
+#define TIM_TIM8_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM8_TI1 is connected to COMP2 OUT */
+
+#define TIM_TIM15_TI1_GPIO 0x00000000UL /*!< TIM15_TI1 is connected to GPIO */
+#define TIM_TIM15_TI1_LSE TIM_TISEL_TI1SEL_0 /*!< TIM15_TI1 is connected to LSE */
+#define TIM_TIM15_TI1_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM15_TI1 is connected to COMP1 OUT */
+#define TIM_TIM15_TI1_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM15_TI1 is connected to COMP2 OUT */
+#define TIM_TIM15_TI2_GPIO 0x00000000UL /*!< TIM15_TI2 is connected to GPIO */
+#define TIM_TIM15_TI2_COMP2 TIM_TISEL_TI2SEL_0 /*!< TIM15_TI2 is connected to COMP2 OUT */
+
+#define TIM_TIM16_TI1_GPIO 0x00000000UL /*!< TIM16_TI1 is connected to GPIO */
+#define TIM_TIM16_TI1_MCO TIM_TISEL_TI1SEL_1 /*!< TIM16_TI1 is connected to MCO */
+#define TIM_TIM16_TI1_HSE_DIV32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM16_TI1 is connected to HSE/32 */
+#define TIM_TIM16_TI1_RTC_WKUP TIM_TISEL_TI1SEL_2 /*!< TIM16_TI1 is connected to RTC Wakeup */
+#define TIM_TIM16_TI1_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM16_TI1 is connected to LSE */
+#define TIM_TIM16_TI1_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM16_TI1 is connected to LSI */
+#define TIM_TIM16_TI1_MSIS_1024 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM16_TI1 is connected to MSIS/1024 */
+#define TIM_TIM16_TI1_MSIS_4 TIM_TISEL_TI1SEL_3 /*!< TIM16_TI1 is connected to MSIS/4 */
+#define TIM_TIM16_TI1_HSI_256 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0) /*!< TIM16_TI1 is connected to HSI/256 */
+
+#define TIM_TIM17_TI1_GPIO 0x00000000UL /*!< TIM17_TI1 is connected to GPIO */
+#define TIM_TIM17_TI1_MCO TIM_TISEL_TI1SEL_1 /*!< TIM17_TI1 is connected to MCO */
+#define TIM_TIM17_TI1_HSE_DIV32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM17_TI1 is connected to HSE/32 */
+#define TIM_TIM17_TI1_RTC_WKUP TIM_TISEL_TI1SEL_2 /*!< TIM17_TI1 is connected to RTC Wakeup */
+#define TIM_TIM17_TI1_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM17_TI1 is connected to LSE */
+#define TIM_TIM17_TI1_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM17_TI1 is connected to LSI */
+#define TIM_TIM17_TI1_MSIS_1024 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM17_TI1 is connected to MSIS/1024 */
+#define TIM_TIM17_TI1_MSIS_4 TIM_TISEL_TI1SEL_3 /*!< TIM17_TI1 is connected to MSIS/4 */
+#define TIM_TIM17_TI1_HSI_256 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0) /*!< TIM17_TI1 is connected to HSI/256 */
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_SMS_Preload_Enable TIM Extended Bitfield SMS preload enabling
+ * @{
+ */
+#define TIM_SMS_PRELOAD_SOURCE_UPDATE 0x00000000U /*!< Prelaod of SMS bitfield is disabled */
+#define TIM_SMS_PRELOAD_SOURCE_INDEX TIM_SMCR_SMSPS /*!< Preload of SMS bitfield is enabled */
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Encoder_Index_Blanking TIM Extended Encoder index blanking
+ * @{
+ */
+#define TIM_ENCODERINDEX_BLANKING_DISABLE 0x00000000U /*!< Encoder index blanking is disabled */
+#define TIM_ENCODERINDEX_BLANKING_TI3 TIM_ECR_IBLK_0 /*!< Encoder index blanking is enabled on TI3 */
+#define TIM_ENCODERINDEX_BLANKING_TI4 TIM_ECR_IBLK_1 /*!< Encoder index blanking is enabled on TI4 */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Encoder_Index_Position TIM Extended Encoder index position
+ * @{
+ */
+#define TIM_ENCODERINDEX_POSITION_00 0x00000000U /*!< Encoder index position is AB=00 */
+#define TIM_ENCODERINDEX_POSITION_01 TIM_ECR_IPOS_0 /*!< Encoder index position is AB=01 */
+#define TIM_ENCODERINDEX_POSITION_10 TIM_ECR_IPOS_1 /*!< Encoder index position is AB=10 */
+#define TIM_ENCODERINDEX_POSITION_11 (TIM_ECR_IPOS_1 | TIM_ECR_IPOS_0) /*!< Encoder index position is AB=11 */
+#define TIM_ENCODERINDEX_POSITION_0 0x00000000U /*!< In directional clock mode or clock plus direction mode, index resets the counter when clock is 0 */
+#define TIM_ENCODERINDEX_POSITION_1 TIM_ECR_IPOS_0 /*!< In directional clock mode or clock plus direction mode, index resets the counter when clock is 1 */
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Encoder_Index_Direction TIM Extended Encoder index direction
+ * @{
+ */
+#define TIM_ENCODERINDEX_DIRECTION_UP_DOWN 0x00000000U /*!< Index resets the counter whatever the direction */
+#define TIM_ENCODERINDEX_DIRECTION_UP TIM_ECR_IDIR_0 /*!< Index resets the counter when up-counting only */
+#define TIM_ENCODERINDEX_DIRECTION_DOWN TIM_ECR_IDIR_1 /*!< Index resets the counter when down-counting only */
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Encoder_Index_Polarity TIM Extended Encoder index polarity
+ * @{
+ */
+#define TIM_ENCODERINDEX_POLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
+#define TIM_ENCODERINDEX_POLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Encoder_Index_Prescaler TIM Extended Encodder index prescaler
+ * @{
+ */
+#define TIM_ENCODERINDEX_PRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_ENCODERINDEX_PRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
+#define TIM_ENCODERINDEX_PRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
+#define TIM_ENCODERINDEX_PRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* End of exported constants -------------------------------------------------*/
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
+ * @{
+ */
+
+/**
+ * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
+ * @note ex: @ref __HAL_TIM_CALC_PSC(80000000, 1000000);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __CNTCLK__ counter clock frequency (in Hz)
+ * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __HAL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
+ ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
+
+/**
+ * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
+ * @note ex: @ref __HAL_TIM_CALC_PERIOD(1000000, 0, 10000);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __PSC__ prescaler
+ * @param __FREQ__ output signal frequency (in Hz)
+ * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __HAL_TIM_CALC_PERIOD(__TIMCLK__, __PSC__, __FREQ__) \
+ (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
+
+/**
+ * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
+ * output signal frequency.
+ * @note ex: @ref __HAL_TIM_CALC_PERIOD_DITHER(1000000, 0, 10000);
+ * @note This macro should be used only if dithering is already enabled
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __PSC__ prescaler
+ * @param __FREQ__ output signal frequency (in Hz)
+ * @retval Auto-reload value (between Min_Data=0 and Max_Data=65519)
+ */
+#define __HAL_TIM_CALC_PERIOD_DITHER(__TIMCLK__, __PSC__, __FREQ__) \
+ (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? \
+ (uint32_t)(((uint64_t)(__TIMCLK__)*16/((__FREQ__) * ((__PSC__) + 1U)) - 16U)) : 0U
+
+/**
+ * @brief HELPER macro calculating the compare value required to achieve the required timer output compare
+ * active/inactive delay.
+ * @note ex: @ref __HAL_TIM_CALC_PULSE(1000000, 0, 10);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __PSC__ prescaler
+ * @param __DELAY__ timer output compare active/inactive delay (in us)
+ * @retval Compare value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __HAL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__) \
+ ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
+ / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
+
+/**
+ * @brief HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer
+ * output compare active/inactive delay.
+ * @note ex: @ref __HAL_TIM_CALC_PULSE_DITHER(1000000, 0, 10);
+ * @note This macro should be used only if dithering is already enabled
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __PSC__ prescaler
+ * @param __DELAY__ timer output compare active/inactive delay (in us)
+ * @retval Compare value (between Min_Data=0 and Max_Data=65519)
+ */
+#define __HAL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__) \
+ ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__) * 16U) \
+ / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
+
+/**
+ * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
+ * (when the timer operates in one pulse mode).
+ * @note ex: @ref __HAL_TIM_CALC_PERIOD_BY_DELAY(1000000, 0, 10, 20);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __PSC__ prescaler
+ * @param __DELAY__ timer output compare active/inactive delay (in us)
+ * @param __PULSE__ pulse duration (in us)
+ * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __HAL_TIM_CALC_PERIOD_BY_DELAY(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
+ ((uint32_t)(__HAL_TIM_CALC_PULSE((__TIMCLK__), (__PSC__), (__PULSE__)) \
+ + __HAL_TIM_CALC_PULSE((__TIMCLK__), (__PSC__), (__DELAY__))))
+
+/**
+ * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
+ * pulse duration (when the timer operates in one pulse mode).
+ * @note ex: @ref __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY(1000000, 0, 10, 20);
+ * @note This macro should be used only if dithering is already enabled
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __PSC__ prescaler
+ * @param __DELAY__ timer output compare active/inactive delay (in us)
+ * @param __PULSE__ pulse duration (in us)
+ * @retval Auto-reload value (between Min_Data=0 and Max_Data=65519)
+ */
+#define __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
+ ((uint32_t)(__HAL_TIM_CALC_PULSE_DITHER((__TIMCLK__), (__PSC__), (__PULSE__)) \
+ + __HAL_TIM_CALC_PULSE_DITHER((__TIMCLK__), (__PSC__), (__DELAY__))))
+
+/**
+ * @}
+ */
+/* End of exported macro -----------------------------------------------------*/
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
+ * @{
+ */
+#define IS_TIM_REMAP(__REMAP__) ((((__REMAP__) & 0xFFFC3FFFU) == 0x00000000U))
+#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \
+ ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
+
+#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \
+ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
+ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
+ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_MDF1))
+
+#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \
+ ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
+
+#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \
+ ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
+
+#define IS_TIM_TISEL(__TISEL__) ((((__TISEL__) & 0xF0F0F0F0U) == 0x00000000U))
+
+#define IS_TIM_TISEL_TIX_INSTANCE(INSTANCE, CHANNEL) \
+ (IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) && ((CHANNEL) < TIM_CHANNEL_5))
+
+#define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \
+ ((((INSTANCE) == TIM1) && \
+ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \
+ || \
+ (((INSTANCE) == TIM15) && \
+ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))))
+
+#define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \
+ ((((INSTANCE) == TIM1) && \
+ (((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_TI1F_ED) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || \
+ ((__SELECTION__) == TIM_TS_ETRF) || \
+ ((__SELECTION__) == TIM_TS_ITR4) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || \
+ ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((__SELECTION__) == TIM_TS_ITR0) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_TI1F_ED) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || \
+ ((__SELECTION__) == TIM_TS_ETRF) || \
+ ((__SELECTION__) == TIM_TS_ITR4) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || \
+ ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((__SELECTION__) == TIM_TS_ITR0) || \
+ ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_TI1F_ED) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || \
+ ((__SELECTION__) == TIM_TS_ETRF) || \
+ ((__SELECTION__) == TIM_TS_ITR4) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || \
+ ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((__SELECTION__) == TIM_TS_ITR0) || \
+ ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR4) || \
+ ((__SELECTION__) == TIM_TS_TI1F_ED) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || \
+ ((__SELECTION__) == TIM_TS_ETRF) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || \
+ ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((__SELECTION__) == TIM_TS_ITR0) || \
+ ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_TI1F_ED) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || \
+ ((__SELECTION__) == TIM_TS_ETRF) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || \
+ ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((__SELECTION__) == TIM_TS_ITR0) || \
+ ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_TI1F_ED) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || \
+ ((__SELECTION__) == TIM_TS_ETRF) || \
+ ((__SELECTION__) == TIM_TS_ITR4) || \
+ ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8))) \
+ || \
+ (((INSTANCE) == TIM15) && \
+ (((__SELECTION__) == TIM_TS_ITR0) || \
+ ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_TI1F_ED) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || \
+ ((__SELECTION__) == TIM_TS_ITR4) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8))))
+
+#define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \
+ ((((INSTANCE) == TIM1) && \
+ (((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_ITR4) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || \
+ ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8) || \
+ ((__SELECTION__) == TIM_TS_NONE))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((__SELECTION__) == TIM_TS_ITR0) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_ITR4) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || \
+ ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8) || \
+ ((__SELECTION__) == TIM_TS_ITR11)|| \
+ ((__SELECTION__) == TIM_TS_NONE))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((__SELECTION__) == TIM_TS_ITR0) || \
+ ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_ITR4) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || \
+ ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8) || \
+ ((__SELECTION__) == TIM_TS_NONE))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((__SELECTION__) == TIM_TS_ITR0) || \
+ ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR4) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || \
+ ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8) || \
+ ((__SELECTION__) == TIM_TS_NONE))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((__SELECTION__) == TIM_TS_ITR0) || \
+ ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || \
+ ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8) || \
+ ((__SELECTION__) == TIM_TS_NONE))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((__SELECTION__) == TIM_TS_ITR0) || \
+ ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_ITR4) || \
+ ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8) || \
+ ((__SELECTION__) == TIM_TS_NONE))) \
+ || \
+ (((INSTANCE) == TIM15) && \
+ (((__SELECTION__) == TIM_TS_ITR0) || \
+ ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_ITR4) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8) || \
+ ((__SELECTION__) == TIM_TS_NONE))))
+
+#define IS_TIM_OC_CHANNEL_MODE(__MODE__, __CHANNEL__) \
+ (IS_TIM_OC_MODE(__MODE__) \
+ && ((((__MODE__) == TIM_OCMODE_DIRECTION_OUTPUT) || ((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE)) \
+ ? (((__CHANNEL__) == TIM_CHANNEL_3) || ((__CHANNEL__) == TIM_CHANNEL_4)) : (1==1)) )
+
+#define IS_TIM_PULSEONCOMPARE_CHANNEL(__CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_3) || \
+ ((__CHANNEL__) == TIM_CHANNEL_4))
+
+#define IS_TIM_PULSEONCOMPARE_INSTANCE(INSTANCE) IS_TIM_CC3_INSTANCE(INSTANCE)
+
+#define IS_TIM_PULSEONCOMPARE_WIDTH(__WIDTH__) ((__WIDTH__) <= 0xFFU)
+
+#define IS_TIM_PULSEONCOMPARE_WIDTHPRESCALER(__PRESCALER__) ((__PRESCALER__) <= 0x7U)
+
+#define IS_TIM_SLAVE_PRELOAD_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_SMS_PRELOAD_SOURCE_UPDATE) \
+ || ((__SOURCE__) == TIM_SMS_PRELOAD_SOURCE_INDEX))
+
+#define IS_TIM_ENCODERINDEX_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINDEX_POLARITY_INVERTED) || \
+ ((__POLARITY__) == TIM_ENCODERINDEX_POLARITY_NONINVERTED))
+
+#define IS_TIM_ENCODERINDEX_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV1) || \
+ ((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV2) || \
+ ((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV4) || \
+ ((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV8))
+
+#define IS_TIM_ENCODERINDEX_FILTER(__FILTER__) ((__FILTER__) <= 0xFUL)
+
+#define IS_TIM_ENCODERINDEX_POSITION(__POSITION__) (((__POSITION__) == TIM_ENCODERINDEX_POSITION_00) || \
+ ((__POSITION__) == TIM_ENCODERINDEX_POSITION_01) || \
+ ((__POSITION__) == TIM_ENCODERINDEX_POSITION_10) || \
+ ((__POSITION__) == TIM_ENCODERINDEX_POSITION_11) || \
+ ((__POSITION__) == TIM_ENCODERINDEX_POSITION_0) || \
+ ((__POSITION__) == TIM_ENCODERINDEX_POSITION_1))
+
+#define IS_TIM_ENCODERINDEX_DIRECTION(__DIRECTION__) (((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_UP_DOWN) || \
+ ((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_UP) || \
+ ((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_DOWN))
+
+#define IS_TIM_ENCODERINDEX_BLANKING(__BLANKING__) (((__BLANKING__) == TIM_ENCODERINDEX_BLANKING_DISABLE) || \
+ ((__BLANKING__) == TIM_ENCODERINDEX_BLANKING_TI3) || \
+ ((__BLANKING__) == TIM_ENCODERINDEX_BLANKING_TI4))
+
+/**
+ * @}
+ */
+/* End of private macro ------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
+ * @{
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
+ * @brief Timer Hall Sensor functions
+ * @{
+ */
+/* Timer Hall Sensor functions **********************************************/
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
+
+void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
+ * @brief Timer Complementary Output Compare functions
+ * @{
+ */
+/* Timer Complementary Output Compare functions *****************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
+ * @brief Timer Complementary PWM functions
+ * @{
+ */
+/* Timer Complementary PWM functions ****************************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
+ * @brief Timer Complementary One Pulse functions
+ * @{
+ */
+/* Timer Complementary One Pulse functions **********************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
+ * @brief Peripheral Control functions
+ * @{
+ */
+/* Extended Control functions ************************************************/
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
+ uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
+ uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
+ uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+ TIM_MasterConfigTypeDef *sMasterConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+ TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput,
+ TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
+HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_EnableHSE32(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_DisableHSE32(TIM_HandleTypeDef *htim);
+
+HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput);
+HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput);
+HAL_StatusTypeDef HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_OC_ConfigPulseOnCompare(TIM_HandleTypeDef *htim, uint32_t PulseWidthPrescaler,
+ uint32_t PulseWidth);
+HAL_StatusTypeDef HAL_TIMEx_ConfigSlaveModePreload(TIM_HandleTypeDef *htim, uint32_t Source);
+HAL_StatusTypeDef HAL_TIMEx_EnableSlaveModePreload(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_DisableSlaveModePreload(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_EnableDeadTimePreload(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_DisableDeadTimePreload(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_ConfigDeadTime(TIM_HandleTypeDef *htim, uint32_t Deadtime);
+HAL_StatusTypeDef HAL_TIMEx_ConfigAsymmetricalDeadTime(TIM_HandleTypeDef *htim, uint32_t FallingDeadtime);
+HAL_StatusTypeDef HAL_TIMEx_EnableAsymmetricalDeadTime(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_DisableAsymmetricalDeadTime(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_ConfigEncoderIndex(TIM_HandleTypeDef *htim,
+ TIMEx_EncoderIndexConfigTypeDef *sEncoderIndexConfig);
+HAL_StatusTypeDef HAL_TIMEx_EnableEncoderIndex(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_DisableEncoderIndex(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_EnableEncoderFirstIndex(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
+ * @brief Extended Callbacks functions
+ * @{
+ */
+/* Extended Callback **********************************************************/
+void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
+ * @brief Extended Peripheral State functions
+ * @{
+ */
+/* Extended Peripheral State functions ***************************************/
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private functions----------------------------------------------------------*/
+/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
+ * @{
+ */
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+/* End of private functions --------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32U5xx_HAL_TIM_EX_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_tsc.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_tsc.h
new file mode 100644
index 00000000..be631231
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_tsc.h
@@ -0,0 +1,795 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_tsc.h
+ * @author MCD Application Team
+ * @brief Header file of TSC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_TSC_H
+#define STM32U5xx_HAL_TSC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup TSC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TSC_Exported_Types TSC Exported Types
+ * @{
+ */
+
+/**
+ * @brief TSC state structure definition
+ */
+typedef enum
+{
+ HAL_TSC_STATE_RESET = 0x00UL, /*!< TSC registers have their reset value */
+ HAL_TSC_STATE_READY = 0x01UL, /*!< TSC registers are initialized or acquisition is completed with success */
+ HAL_TSC_STATE_BUSY = 0x02UL, /*!< TSC initialization or acquisition is on-going */
+ HAL_TSC_STATE_ERROR = 0x03UL /*!< Acquisition is completed with max count error */
+} HAL_TSC_StateTypeDef;
+
+/**
+ * @brief TSC group status structure definition
+ */
+typedef enum
+{
+ TSC_GROUP_ONGOING = 0x00UL, /*!< Acquisition on group is on-going or not started */
+ TSC_GROUP_COMPLETED = 0x01UL /*!< Acquisition on group is completed with success (no max count error) */
+} TSC_GroupStatusTypeDef;
+
+/**
+ * @brief TSC init structure definition
+ */
+typedef struct
+{
+ uint32_t CTPulseHighLength; /*!< Charge-transfer high pulse length
+ This parameter can be a value of @ref TSC_CTPulseHL_Config */
+ uint32_t CTPulseLowLength; /*!< Charge-transfer low pulse length
+ This parameter can be a value of @ref TSC_CTPulseLL_Config */
+ FunctionalState SpreadSpectrum; /*!< Spread spectrum activation
+ This parameter can be set to ENABLE or DISABLE. */
+ uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation
+ This parameter must be a number between Min_Data = 0 and Max_Data = 127 */
+ uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler
+ This parameter can be a value of @ref TSC_SpreadSpec_Prescaler */
+ uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler
+ This parameter can be a value of @ref TSC_PulseGenerator_Prescaler */
+ uint32_t MaxCountValue; /*!< Max count value
+ This parameter can be a value of @ref TSC_MaxCount_Value */
+ uint32_t IODefaultMode; /*!< IO default mode
+ This parameter can be a value of @ref TSC_IO_Default_Mode */
+ uint32_t SynchroPinPolarity; /*!< Synchro pin polarity
+ This parameter can be a value of @ref TSC_Synchro_Pin_Polarity */
+ uint32_t AcquisitionMode; /*!< Acquisition mode
+ This parameter can be a value of @ref TSC_Acquisition_Mode */
+ FunctionalState MaxCountInterrupt;/*!< Max count interrupt activation
+ This parameter can be set to ENABLE or DISABLE. */
+ uint32_t ChannelIOs; /*!< Channel IOs mask */
+ uint32_t ShieldIOs; /*!< Shield IOs mask */
+ uint32_t SamplingIOs; /*!< Sampling IOs mask */
+} TSC_InitTypeDef;
+
+/**
+ * @brief TSC IOs configuration structure definition
+ */
+typedef struct
+{
+ uint32_t ChannelIOs; /*!< Channel IOs mask */
+ uint32_t ShieldIOs; /*!< Shield IOs mask */
+ uint32_t SamplingIOs; /*!< Sampling IOs mask */
+} TSC_IOConfigTypeDef;
+
+/**
+ * @brief TSC handle Structure definition
+ */
+#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
+typedef struct __TSC_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
+{
+ TSC_TypeDef *Instance; /*!< Register base address */
+ TSC_InitTypeDef Init; /*!< Initialization parameters */
+ __IO HAL_TSC_StateTypeDef State; /*!< Peripheral state */
+ HAL_LockTypeDef Lock; /*!< Lock feature */
+ __IO uint32_t ErrorCode; /*!< TSC Error code */
+
+#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
+ void (* ConvCpltCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Conversion complete callback */
+ void (* ErrorCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Error callback */
+
+ void (* MspInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp Init callback */
+ void (* MspDeInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp DeInit callback */
+
+#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
+} TSC_HandleTypeDef;
+
+enum
+{
+ TSC_GROUP1_IDX = 0x00UL,
+ TSC_GROUP2_IDX,
+ TSC_GROUP3_IDX,
+ TSC_GROUP4_IDX,
+ TSC_GROUP5_IDX,
+ TSC_GROUP6_IDX,
+ TSC_GROUP7_IDX,
+ TSC_GROUP8_IDX,
+ TSC_NB_OF_GROUPS
+};
+
+#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL TSC Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_TSC_CONV_COMPLETE_CB_ID = 0x00UL, /*!< TSC Conversion completed callback ID */
+ HAL_TSC_ERROR_CB_ID = 0x01UL, /*!< TSC Error callback ID */
+
+ HAL_TSC_MSPINIT_CB_ID = 0x02UL, /*!< TSC Msp Init callback ID */
+ HAL_TSC_MSPDEINIT_CB_ID = 0x03UL /*!< TSC Msp DeInit callback ID */
+
+} HAL_TSC_CallbackIDTypeDef;
+
+/**
+ * @brief HAL TSC Callback pointer definition
+ */
+typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to an TSC callback function */
+
+#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TSC_Exported_Constants TSC Exported Constants
+ * @{
+ */
+
+/** @defgroup TSC_Error_Code_definition TSC Error Code definition
+ * @brief TSC Error Code definition
+ * @{
+ */
+#define HAL_TSC_ERROR_NONE 0x00000000UL /*!< No error */
+#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
+#define HAL_TSC_ERROR_INVALID_CALLBACK 0x00000001UL /*!< Invalid Callback error */
+#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup TSC_CTPulseHL_Config CTPulse High Length
+ * @{
+ */
+#define TSC_CTPH_1CYCLE 0x00000000UL /*!< Charge transfer pulse high during 1 cycle (PGCLK) */
+#define TSC_CTPH_2CYCLES TSC_CR_CTPH_0 /*!< Charge transfer pulse high during 2 cycles (PGCLK) */
+#define TSC_CTPH_3CYCLES TSC_CR_CTPH_1 /*!< Charge transfer pulse high during 3 cycles (PGCLK) */
+#define TSC_CTPH_4CYCLES (TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 4 cycles (PGCLK) */
+#define TSC_CTPH_5CYCLES TSC_CR_CTPH_2 /*!< Charge transfer pulse high during 5 cycles (PGCLK) */
+#define TSC_CTPH_6CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 6 cycles (PGCLK) */
+#define TSC_CTPH_7CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 7 cycles (PGCLK) */
+#define TSC_CTPH_8CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 8 cycles (PGCLK) */
+#define TSC_CTPH_9CYCLES TSC_CR_CTPH_3 /*!< Charge transfer pulse high during 9 cycles (PGCLK) */
+#define TSC_CTPH_10CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 10 cycles (PGCLK) */
+#define TSC_CTPH_11CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 11 cycles (PGCLK) */
+#define TSC_CTPH_12CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 12 cycles (PGCLK) */
+#define TSC_CTPH_13CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2) /*!< Charge transfer pulse high during 13 cycles (PGCLK) */
+#define TSC_CTPH_14CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 14 cycles (PGCLK) */
+#define TSC_CTPH_15CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 15 cycles (PGCLK) */
+#define TSC_CTPH_16CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 16 cycles (PGCLK) */
+/**
+ * @}
+ */
+
+/** @defgroup TSC_CTPulseLL_Config CTPulse Low Length
+ * @{
+ */
+#define TSC_CTPL_1CYCLE 0x00000000UL /*!< Charge transfer pulse low during 1 cycle (PGCLK) */
+#define TSC_CTPL_2CYCLES TSC_CR_CTPL_0 /*!< Charge transfer pulse low during 2 cycles (PGCLK) */
+#define TSC_CTPL_3CYCLES TSC_CR_CTPL_1 /*!< Charge transfer pulse low during 3 cycles (PGCLK) */
+#define TSC_CTPL_4CYCLES (TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 4 cycles (PGCLK) */
+#define TSC_CTPL_5CYCLES TSC_CR_CTPL_2 /*!< Charge transfer pulse low during 5 cycles (PGCLK) */
+#define TSC_CTPL_6CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 6 cycles (PGCLK) */
+#define TSC_CTPL_7CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 7 cycles (PGCLK) */
+#define TSC_CTPL_8CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 8 cycles (PGCLK) */
+#define TSC_CTPL_9CYCLES TSC_CR_CTPL_3 /*!< Charge transfer pulse low during 9 cycles (PGCLK) */
+#define TSC_CTPL_10CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 10 cycles (PGCLK) */
+#define TSC_CTPL_11CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 11 cycles (PGCLK) */
+#define TSC_CTPL_12CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 12 cycles (PGCLK) */
+#define TSC_CTPL_13CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2) /*!< Charge transfer pulse low during 13 cycles (PGCLK) */
+#define TSC_CTPL_14CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 14 cycles (PGCLK) */
+#define TSC_CTPL_15CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 15 cycles (PGCLK) */
+#define TSC_CTPL_16CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 16 cycles (PGCLK) */
+/**
+ * @}
+ */
+
+/** @defgroup TSC_SpreadSpec_Prescaler Spread Spectrum Prescaler
+ * @{
+ */
+#define TSC_SS_PRESC_DIV1 0x00000000UL /*!< Spread Spectrum Prescaler Div1 */
+#define TSC_SS_PRESC_DIV2 TSC_CR_SSPSC /*!< Spread Spectrum Prescaler Div2 */
+/**
+ * @}
+ */
+
+/** @defgroup TSC_PulseGenerator_Prescaler Pulse Generator Prescaler
+ * @{
+ */
+#define TSC_PG_PRESC_DIV1 0x00000000UL /*!< Pulse Generator HCLK Div1 */
+#define TSC_PG_PRESC_DIV2 TSC_CR_PGPSC_0 /*!< Pulse Generator HCLK Div2 */
+#define TSC_PG_PRESC_DIV4 TSC_CR_PGPSC_1 /*!< Pulse Generator HCLK Div4 */
+#define TSC_PG_PRESC_DIV8 (TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div8 */
+#define TSC_PG_PRESC_DIV16 TSC_CR_PGPSC_2 /*!< Pulse Generator HCLK Div16 */
+#define TSC_PG_PRESC_DIV32 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div32 */
+#define TSC_PG_PRESC_DIV64 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1) /*!< Pulse Generator HCLK Div64 */
+#define TSC_PG_PRESC_DIV128 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div128 */
+/**
+ * @}
+ */
+
+/** @defgroup TSC_MaxCount_Value Max Count Value
+ * @{
+ */
+#define TSC_MCV_255 0x00000000UL /*!< 255 maximum number of charge transfer pulses */
+#define TSC_MCV_511 TSC_CR_MCV_0 /*!< 511 maximum number of charge transfer pulses */
+#define TSC_MCV_1023 TSC_CR_MCV_1 /*!< 1023 maximum number of charge transfer pulses */
+#define TSC_MCV_2047 (TSC_CR_MCV_1 | TSC_CR_MCV_0) /*!< 2047 maximum number of charge transfer pulses */
+#define TSC_MCV_4095 TSC_CR_MCV_2 /*!< 4095 maximum number of charge transfer pulses */
+#define TSC_MCV_8191 (TSC_CR_MCV_2 | TSC_CR_MCV_0) /*!< 8191 maximum number of charge transfer pulses */
+#define TSC_MCV_16383 (TSC_CR_MCV_2 | TSC_CR_MCV_1) /*!< 16383 maximum number of charge transfer pulses */
+/**
+ * @}
+ */
+
+/** @defgroup TSC_IO_Default_Mode IO Default Mode
+ * @{
+ */
+#define TSC_IODEF_OUT_PP_LOW 0x00000000UL /*!< I/Os are forced to output push-pull low */
+#define TSC_IODEF_IN_FLOAT TSC_CR_IODEF /*!< I/Os are in input floating */
+/**
+ * @}
+ */
+
+/** @defgroup TSC_Synchro_Pin_Polarity Synchro Pin Polarity
+ * @{
+ */
+#define TSC_SYNC_POLARITY_FALLING 0x00000000UL /*!< Falling edge only */
+#define TSC_SYNC_POLARITY_RISING TSC_CR_SYNCPOL /*!< Rising edge and high level */
+/**
+ * @}
+ */
+
+/** @defgroup TSC_Acquisition_Mode Acquisition Mode
+ * @{
+ */
+#define TSC_ACQ_MODE_NORMAL 0x00000000UL /*!< Normal acquisition mode (acquisition starts as soon as START bit is set) */
+#define TSC_ACQ_MODE_SYNCHRO TSC_CR_AM /*!< Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin) */
+/**
+ * @}
+ */
+
+/** @defgroup TSC_interrupts_definition Interrupts definition
+ * @{
+ */
+#define TSC_IT_EOA TSC_IER_EOAIE /*!< End of acquisition interrupt enable */
+#define TSC_IT_MCE TSC_IER_MCEIE /*!< Max count error interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup TSC_flags_definition Flags definition
+ * @{
+ */
+#define TSC_FLAG_EOA TSC_ISR_EOAF /*!< End of acquisition flag */
+#define TSC_FLAG_MCE TSC_ISR_MCEF /*!< Max count error flag */
+/**
+ * @}
+ */
+
+/** @defgroup TSC_Group_definition Group definition
+ * @{
+ */
+#define TSC_GROUP1 (0x1UL << TSC_GROUP1_IDX)
+#define TSC_GROUP2 (0x1UL << TSC_GROUP2_IDX)
+#define TSC_GROUP3 (0x1UL << TSC_GROUP3_IDX)
+#define TSC_GROUP4 (0x1UL << TSC_GROUP4_IDX)
+#define TSC_GROUP5 (0x1UL << TSC_GROUP5_IDX)
+#define TSC_GROUP6 (0x1UL << TSC_GROUP6_IDX)
+#define TSC_GROUP7 (0x1UL << TSC_GROUP7_IDX)
+#define TSC_GROUP8 (0x1UL << TSC_GROUP8_IDX)
+
+#define TSC_GROUP1_IO1 TSC_IOCCR_G1_IO1 /*!< TSC Group1 IO1 */
+#define TSC_GROUP1_IO2 TSC_IOCCR_G1_IO2 /*!< TSC Group1 IO2 */
+#define TSC_GROUP1_IO3 TSC_IOCCR_G1_IO3 /*!< TSC Group1 IO3 */
+#define TSC_GROUP1_IO4 TSC_IOCCR_G1_IO4 /*!< TSC Group1 IO4 */
+
+#define TSC_GROUP2_IO1 TSC_IOCCR_G2_IO1 /*!< TSC Group2 IO1 */
+#define TSC_GROUP2_IO2 TSC_IOCCR_G2_IO2 /*!< TSC Group2 IO2 */
+#define TSC_GROUP2_IO3 TSC_IOCCR_G2_IO3 /*!< TSC Group2 IO3 */
+#define TSC_GROUP2_IO4 TSC_IOCCR_G2_IO4 /*!< TSC Group2 IO4 */
+
+#define TSC_GROUP3_IO1 TSC_IOCCR_G3_IO1 /*!< TSC Group3 IO1 */
+#define TSC_GROUP3_IO2 TSC_IOCCR_G3_IO2 /*!< TSC Group3 IO2 */
+#define TSC_GROUP3_IO3 TSC_IOCCR_G3_IO3 /*!< TSC Group3 IO3 */
+#define TSC_GROUP3_IO4 TSC_IOCCR_G3_IO4 /*!< TSC Group3 IO4 */
+
+#define TSC_GROUP4_IO1 TSC_IOCCR_G4_IO1 /*!< TSC Group4 IO1 */
+#define TSC_GROUP4_IO2 TSC_IOCCR_G4_IO2 /*!< TSC Group4 IO2 */
+#define TSC_GROUP4_IO3 TSC_IOCCR_G4_IO3 /*!< TSC Group4 IO3 */
+#define TSC_GROUP4_IO4 TSC_IOCCR_G4_IO4 /*!< TSC Group4 IO4 */
+
+#define TSC_GROUP5_IO1 TSC_IOCCR_G5_IO1 /*!< TSC Group5 IO1 */
+#define TSC_GROUP5_IO2 TSC_IOCCR_G5_IO2 /*!< TSC Group5 IO2 */
+#define TSC_GROUP5_IO3 TSC_IOCCR_G5_IO3 /*!< TSC Group5 IO3 */
+#define TSC_GROUP5_IO4 TSC_IOCCR_G5_IO4 /*!< TSC Group5 IO4 */
+
+#define TSC_GROUP6_IO1 TSC_IOCCR_G6_IO1 /*!< TSC Group6 IO1 */
+#define TSC_GROUP6_IO2 TSC_IOCCR_G6_IO2 /*!< TSC Group6 IO2 */
+#define TSC_GROUP6_IO3 TSC_IOCCR_G6_IO3 /*!< TSC Group6 IO3 */
+#define TSC_GROUP6_IO4 TSC_IOCCR_G6_IO4 /*!< TSC Group6 IO4 */
+
+#define TSC_GROUP7_IO1 TSC_IOCCR_G7_IO1 /*!< TSC Group7 IO1 */
+#define TSC_GROUP7_IO2 TSC_IOCCR_G7_IO2 /*!< TSC Group7 IO2 */
+#define TSC_GROUP7_IO3 TSC_IOCCR_G7_IO3 /*!< TSC Group7 IO3 */
+#define TSC_GROUP7_IO4 TSC_IOCCR_G7_IO4 /*!< TSC Group7 IO4 */
+
+#define TSC_GROUP8_IO1 TSC_IOCCR_G8_IO1 /*!< TSC Group8 IO1 */
+#define TSC_GROUP8_IO2 TSC_IOCCR_G8_IO2 /*!< TSC Group8 IO2 */
+#define TSC_GROUP8_IO3 TSC_IOCCR_G8_IO3 /*!< TSC Group8 IO3 */
+#define TSC_GROUP8_IO4 TSC_IOCCR_G8_IO4 /*!< TSC Group8 IO4 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup TSC_Exported_Macros TSC Exported Macros
+ * @{
+ */
+
+/** @brief Reset TSC handle state.
+ * @param __HANDLE__ TSC handle
+ * @retval None
+ */
+#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
+#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_TSC_STATE_RESET;\
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET)
+#endif /* (USE_HAL_TSC_REGISTER_CALLBACKS == 1) */
+
+/**
+ * @brief Enable the TSC peripheral.
+ * @param __HANDLE__ TSC handle
+ * @retval None
+ */
+#define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE)
+
+/**
+ * @brief Disable the TSC peripheral.
+ * @param __HANDLE__ TSC handle
+ * @retval None
+ */
+#define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_TSCE))
+
+/**
+ * @brief Start acquisition.
+ * @param __HANDLE__ TSC handle
+ * @retval None
+ */
+#define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START)
+
+/**
+ * @brief Stop acquisition.
+ * @param __HANDLE__ TSC handle
+ * @retval None
+ */
+#define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_START))
+
+/**
+ * @brief Set IO default mode to output push-pull low.
+ * @param __HANDLE__ TSC handle
+ * @retval None
+ */
+#define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_IODEF))
+
+/**
+ * @brief Set IO default mode to input floating.
+ * @param __HANDLE__ TSC handle
+ * @retval None
+ */
+#define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF)
+
+/**
+ * @brief Set synchronization polarity to falling edge.
+ * @param __HANDLE__ TSC handle
+ * @retval None
+ */
+#define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_SYNCPOL))
+
+/**
+ * @brief Set synchronization polarity to rising edge and high level.
+ * @param __HANDLE__ TSC handle
+ * @retval None
+ */
+#define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL)
+
+/**
+ * @brief Enable TSC interrupt.
+ * @param __HANDLE__ TSC handle
+ * @param __INTERRUPT__ TSC interrupt
+ * @retval None
+ */
+#define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+
+/**
+ * @brief Disable TSC interrupt.
+ * @param __HANDLE__ TSC handle
+ * @param __INTERRUPT__ TSC interrupt
+ * @retval None
+ */
+#define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
+
+/** @brief Check whether the specified TSC interrupt source is enabled or not.
+ * @param __HANDLE__ TSC Handle
+ * @param __INTERRUPT__ TSC interrupt
+ * @retval SET or RESET
+ */
+#define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\
+ & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET :\
+ RESET)
+
+/**
+ * @brief Check whether the specified TSC flag is set or not.
+ * @param __HANDLE__ TSC handle
+ * @param __FLAG__ TSC flag
+ * @retval SET or RESET
+ */
+#define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR\
+ & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+
+/**
+ * @brief Clear the TSC's pending flag.
+ * @param __HANDLE__ TSC handle
+ * @param __FLAG__ TSC flag
+ * @retval None
+ */
+#define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/**
+ * @brief Enable schmitt trigger hysteresis on a group of IOs.
+ * @param __HANDLE__ TSC handle
+ * @param __GX_IOY_MASK__ IOs mask
+ * @retval None
+ */
+#define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__))
+
+/**
+ * @brief Disable schmitt trigger hysteresis on a group of IOs.
+ * @param __HANDLE__ TSC handle
+ * @param __GX_IOY_MASK__ IOs mask
+ * @retval None
+ */
+#define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR\
+ &= (~(__GX_IOY_MASK__)))
+
+/**
+ * @brief Open analog switch on a group of IOs.
+ * @param __HANDLE__ TSC handle
+ * @param __GX_IOY_MASK__ IOs mask
+ * @retval None
+ */
+#define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR\
+ &= (~(__GX_IOY_MASK__)))
+
+/**
+ * @brief Close analog switch on a group of IOs.
+ * @param __HANDLE__ TSC handle
+ * @param __GX_IOY_MASK__ IOs mask
+ * @retval None
+ */
+#define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__))
+
+/**
+ * @brief Enable a group of IOs in channel mode.
+ * @param __HANDLE__ TSC handle
+ * @param __GX_IOY_MASK__ IOs mask
+ * @retval None
+ */
+#define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__))
+
+/**
+ * @brief Disable a group of channel IOs.
+ * @param __HANDLE__ TSC handle
+ * @param __GX_IOY_MASK__ IOs mask
+ * @retval None
+ */
+#define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR\
+ &= (~(__GX_IOY_MASK__)))
+
+/**
+ * @brief Enable a group of IOs in sampling mode.
+ * @param __HANDLE__ TSC handle
+ * @param __GX_IOY_MASK__ IOs mask
+ * @retval None
+ */
+#define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__))
+
+/**
+ * @brief Disable a group of sampling IOs.
+ * @param __HANDLE__ TSC handle
+ * @param __GX_IOY_MASK__ IOs mask
+ * @retval None
+ */
+#define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (~(__GX_IOY_MASK__)))
+
+/**
+ * @brief Enable acquisition groups.
+ * @param __HANDLE__ TSC handle
+ * @param __GX_MASK__ Groups mask
+ * @retval None
+ */
+#define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__))
+
+/**
+ * @brief Disable acquisition groups.
+ * @param __HANDLE__ TSC handle
+ * @param __GX_MASK__ Groups mask
+ * @retval None
+ */
+#define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (~(__GX_MASK__)))
+
+/** @brief Gets acquisition group status.
+ * @param __HANDLE__ TSC Handle
+ * @param __GX_INDEX__ Group index
+ * @retval SET or RESET
+ */
+#define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \
+ ((((__HANDLE__)->Instance->IOGCSR & (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) == \
+ (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING)
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup TSC_Private_Macros TSC Private Macros
+ * @{
+ */
+
+#define IS_TSC_CTPH(__VALUE__) (((__VALUE__) == TSC_CTPH_1CYCLE) || \
+ ((__VALUE__) == TSC_CTPH_2CYCLES) || \
+ ((__VALUE__) == TSC_CTPH_3CYCLES) || \
+ ((__VALUE__) == TSC_CTPH_4CYCLES) || \
+ ((__VALUE__) == TSC_CTPH_5CYCLES) || \
+ ((__VALUE__) == TSC_CTPH_6CYCLES) || \
+ ((__VALUE__) == TSC_CTPH_7CYCLES) || \
+ ((__VALUE__) == TSC_CTPH_8CYCLES) || \
+ ((__VALUE__) == TSC_CTPH_9CYCLES) || \
+ ((__VALUE__) == TSC_CTPH_10CYCLES) || \
+ ((__VALUE__) == TSC_CTPH_11CYCLES) || \
+ ((__VALUE__) == TSC_CTPH_12CYCLES) || \
+ ((__VALUE__) == TSC_CTPH_13CYCLES) || \
+ ((__VALUE__) == TSC_CTPH_14CYCLES) || \
+ ((__VALUE__) == TSC_CTPH_15CYCLES) || \
+ ((__VALUE__) == TSC_CTPH_16CYCLES))
+
+#define IS_TSC_CTPL(__VALUE__) (((__VALUE__) == TSC_CTPL_1CYCLE) || \
+ ((__VALUE__) == TSC_CTPL_2CYCLES) || \
+ ((__VALUE__) == TSC_CTPL_3CYCLES) || \
+ ((__VALUE__) == TSC_CTPL_4CYCLES) || \
+ ((__VALUE__) == TSC_CTPL_5CYCLES) || \
+ ((__VALUE__) == TSC_CTPL_6CYCLES) || \
+ ((__VALUE__) == TSC_CTPL_7CYCLES) || \
+ ((__VALUE__) == TSC_CTPL_8CYCLES) || \
+ ((__VALUE__) == TSC_CTPL_9CYCLES) || \
+ ((__VALUE__) == TSC_CTPL_10CYCLES) || \
+ ((__VALUE__) == TSC_CTPL_11CYCLES) || \
+ ((__VALUE__) == TSC_CTPL_12CYCLES) || \
+ ((__VALUE__) == TSC_CTPL_13CYCLES) || \
+ ((__VALUE__) == TSC_CTPL_14CYCLES) || \
+ ((__VALUE__) == TSC_CTPL_15CYCLES) || \
+ ((__VALUE__) == TSC_CTPL_16CYCLES))
+
+#define IS_TSC_SS(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE)\
+ || ((FunctionalState)(__VALUE__) == ENABLE))
+
+#define IS_TSC_SSD(__VALUE__) (((__VALUE__) == 0UL) || (((__VALUE__) > 0UL) && ((__VALUE__) < 128UL)))
+
+#define IS_TSC_SS_PRESC(__VALUE__) (((__VALUE__) == TSC_SS_PRESC_DIV1) || ((__VALUE__) == TSC_SS_PRESC_DIV2))
+
+#define IS_TSC_PG_PRESC(__VALUE__) (((__VALUE__) == TSC_PG_PRESC_DIV1) || \
+ ((__VALUE__) == TSC_PG_PRESC_DIV2) || \
+ ((__VALUE__) == TSC_PG_PRESC_DIV4) || \
+ ((__VALUE__) == TSC_PG_PRESC_DIV8) || \
+ ((__VALUE__) == TSC_PG_PRESC_DIV16) || \
+ ((__VALUE__) == TSC_PG_PRESC_DIV32) || \
+ ((__VALUE__) == TSC_PG_PRESC_DIV64) || \
+ ((__VALUE__) == TSC_PG_PRESC_DIV128))
+
+#define IS_TSC_PG_PRESC_VS_CTPL(__PGPSC__, __CTPL__) ((((__PGPSC__) == TSC_PG_PRESC_DIV1) && \
+ ((__CTPL__) > TSC_CTPL_2CYCLES)) || \
+ (((__PGPSC__) == TSC_PG_PRESC_DIV2) && \
+ ((__CTPL__) > TSC_CTPL_1CYCLE)) || \
+ (((__PGPSC__) > TSC_PG_PRESC_DIV2) && \
+ (((__CTPL__) == TSC_CTPL_1CYCLE) || \
+ ((__CTPL__) > TSC_CTPL_1CYCLE))))
+
+#define IS_TSC_MCV(__VALUE__) (((__VALUE__) == TSC_MCV_255) || \
+ ((__VALUE__) == TSC_MCV_511) || \
+ ((__VALUE__) == TSC_MCV_1023) || \
+ ((__VALUE__) == TSC_MCV_2047) || \
+ ((__VALUE__) == TSC_MCV_4095) || \
+ ((__VALUE__) == TSC_MCV_8191) || \
+ ((__VALUE__) == TSC_MCV_16383))
+
+#define IS_TSC_IODEF(__VALUE__) (((__VALUE__) == TSC_IODEF_OUT_PP_LOW) || ((__VALUE__) == TSC_IODEF_IN_FLOAT))
+
+#define IS_TSC_SYNC_POL(__VALUE__) (((__VALUE__) == TSC_SYNC_POLARITY_FALLING)\
+ || ((__VALUE__) == TSC_SYNC_POLARITY_RISING))
+
+#define IS_TSC_ACQ_MODE(__VALUE__) (((__VALUE__) == TSC_ACQ_MODE_NORMAL) || ((__VALUE__) == TSC_ACQ_MODE_SYNCHRO))
+
+#define IS_TSC_MCE_IT(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE)\
+ || ((FunctionalState)(__VALUE__) == ENABLE))
+
+#define IS_TSC_GROUP_INDEX(__VALUE__) (((__VALUE__) == 0UL)\
+ || (((__VALUE__) > 0UL) && ((__VALUE__) < (uint32_t)TSC_NB_OF_GROUPS)))
+
+#define IS_TSC_GROUP(__VALUE__) (((__VALUE__) == 0UL) ||\
+ (((__VALUE__) & TSC_GROUP1_IO1) == TSC_GROUP1_IO1) ||\
+ (((__VALUE__) & TSC_GROUP1_IO2) == TSC_GROUP1_IO2) ||\
+ (((__VALUE__) & TSC_GROUP1_IO3) == TSC_GROUP1_IO3) ||\
+ (((__VALUE__) & TSC_GROUP1_IO4) == TSC_GROUP1_IO4) ||\
+ (((__VALUE__) & TSC_GROUP2_IO1) == TSC_GROUP2_IO1) ||\
+ (((__VALUE__) & TSC_GROUP2_IO2) == TSC_GROUP2_IO2) ||\
+ (((__VALUE__) & TSC_GROUP2_IO3) == TSC_GROUP2_IO3) ||\
+ (((__VALUE__) & TSC_GROUP2_IO4) == TSC_GROUP2_IO4) ||\
+ (((__VALUE__) & TSC_GROUP3_IO1) == TSC_GROUP3_IO1) ||\
+ (((__VALUE__) & TSC_GROUP3_IO2) == TSC_GROUP3_IO2) ||\
+ (((__VALUE__) & TSC_GROUP3_IO3) == TSC_GROUP3_IO3) ||\
+ (((__VALUE__) & TSC_GROUP3_IO4) == TSC_GROUP3_IO4) ||\
+ (((__VALUE__) & TSC_GROUP4_IO1) == TSC_GROUP4_IO1) ||\
+ (((__VALUE__) & TSC_GROUP4_IO2) == TSC_GROUP4_IO2) ||\
+ (((__VALUE__) & TSC_GROUP4_IO3) == TSC_GROUP4_IO3) ||\
+ (((__VALUE__) & TSC_GROUP4_IO4) == TSC_GROUP4_IO4) ||\
+ (((__VALUE__) & TSC_GROUP5_IO1) == TSC_GROUP5_IO1) ||\
+ (((__VALUE__) & TSC_GROUP5_IO2) == TSC_GROUP5_IO2) ||\
+ (((__VALUE__) & TSC_GROUP5_IO3) == TSC_GROUP5_IO3) ||\
+ (((__VALUE__) & TSC_GROUP5_IO4) == TSC_GROUP5_IO4) ||\
+ (((__VALUE__) & TSC_GROUP6_IO1) == TSC_GROUP6_IO1) ||\
+ (((__VALUE__) & TSC_GROUP6_IO2) == TSC_GROUP6_IO2) ||\
+ (((__VALUE__) & TSC_GROUP6_IO3) == TSC_GROUP6_IO3) ||\
+ (((__VALUE__) & TSC_GROUP6_IO4) == TSC_GROUP6_IO4) ||\
+ (((__VALUE__) & TSC_GROUP7_IO1) == TSC_GROUP7_IO1) ||\
+ (((__VALUE__) & TSC_GROUP7_IO2) == TSC_GROUP7_IO2) ||\
+ (((__VALUE__) & TSC_GROUP7_IO3) == TSC_GROUP7_IO3) ||\
+ (((__VALUE__) & TSC_GROUP7_IO4) == TSC_GROUP7_IO4) ||\
+ (((__VALUE__) & TSC_GROUP8_IO1) == TSC_GROUP8_IO1) ||\
+ (((__VALUE__) & TSC_GROUP8_IO2) == TSC_GROUP8_IO2) ||\
+ (((__VALUE__) & TSC_GROUP8_IO3) == TSC_GROUP8_IO3) ||\
+ (((__VALUE__) & TSC_GROUP8_IO4) == TSC_GROUP8_IO4))
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TSC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef *htsc);
+HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc);
+void HAL_TSC_MspInit(TSC_HandleTypeDef *htsc);
+void HAL_TSC_MspDeInit(TSC_HandleTypeDef *htsc);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID,
+ pTSC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_TSC_UnRegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @addtogroup TSC_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef *htsc);
+HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef *htsc);
+HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef *htsc);
+HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef *htsc);
+HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef *htsc);
+TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef *htsc, uint32_t gx_index);
+uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef *htsc, uint32_t gx_index);
+/**
+ * @}
+ */
+
+/** @addtogroup TSC_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, TSC_IOConfigTypeDef *config);
+HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef *htsc, FunctionalState choice);
+/**
+ * @}
+ */
+
+/** @addtogroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef *htsc);
+/**
+ * @}
+ */
+
+/** @addtogroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+/******* TSC IRQHandler and Callbacks used in Interrupt mode */
+void HAL_TSC_IRQHandler(TSC_HandleTypeDef *htsc);
+void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef *htsc);
+void HAL_TSC_ErrorCallback(TSC_HandleTypeDef *htsc);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_TSC_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart.h
new file mode 100644
index 00000000..5340081a
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart.h
@@ -0,0 +1,1696 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_uart.h
+ * @author MCD Application Team
+ * @brief Header file of UART HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_UART_H
+#define STM32U5xx_HAL_UART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup UART
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UART_Exported_Types UART Exported Types
+ * @{
+ */
+
+/**
+ * @brief UART Init Structure definition
+ */
+typedef struct
+{
+ uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
+ The baud rate register is computed using the following formula:
+ LPUART:
+ =======
+ Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate)))
+ where lpuart_ker_ck_pres is the UART input clock divided by a prescaler
+ UART:
+ =====
+ - If oversampling is 16 or in LIN mode,
+ Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate)))
+ - If oversampling is 8,
+ Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) /
+ ((huart->Init.BaudRate)))[15:4]
+ Baud Rate Register[3] = 0
+ Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) /
+ ((huart->Init.BaudRate)))[3:0]) >> 1
+ where uart_ker_ck_pres is the UART input clock divided by a prescaler */
+
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref UARTEx_Word_Length. */
+
+ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref UART_Stop_Bits. */
+
+ uint32_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref UART_Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits). */
+
+ uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref UART_Mode. */
+
+ uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled
+ or disabled.
+ This parameter can be a value of @ref UART_Hardware_Flow_Control. */
+
+ uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled,
+ to achieve higher speed (up to f_PCLK/8).
+ This parameter can be a value of @ref UART_Over_Sampling. */
+
+ uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
+ Selecting the single sample method increases the receiver tolerance to clock
+ deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
+
+ uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the UART clock source.
+ This parameter can be a value of @ref UART_ClockPrescaler. */
+
+} UART_InitTypeDef;
+
+/**
+ * @brief UART Advanced Features initialization structure definition
+ */
+typedef struct
+{
+ uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several
+ Advanced Features may be initialized at the same time .
+ This parameter can be a value of
+ @ref UART_Advanced_Features_Initialization_Type. */
+
+ uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted.
+ This parameter can be a value of @ref UART_Tx_Inv. */
+
+ uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted.
+ This parameter can be a value of @ref UART_Rx_Inv. */
+
+ uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic
+ vs negative/inverted logic).
+ This parameter can be a value of @ref UART_Data_Inv. */
+
+ uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped.
+ This parameter can be a value of @ref UART_Rx_Tx_Swap. */
+
+ uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled.
+ This parameter can be a value of @ref UART_Overrun_Disable. */
+
+ uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error.
+ This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */
+
+ uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled.
+ This parameter can be a value of @ref UART_AutoBaudRate_Enable. */
+
+ uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate
+ detection is carried out.
+ This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */
+
+ uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
+ This parameter can be a value of @ref UART_MSB_First. */
+} UART_AdvFeatureInitTypeDef;
+
+/**
+ * @brief HAL UART State definition
+ * @note HAL UART State value is a combination of 2 different substates:
+ * gState and RxState (see @ref UART_State_Definition).
+ * - gState contains UART state information related to global Handle management
+ * and also information related to Tx operations.
+ * gState value coding follow below described bitmap :
+ * b7-b6 Error information
+ * 00 : No Error
+ * 01 : (Not Used)
+ * 10 : Timeout
+ * 11 : Error
+ * b5 Peripheral initialization status
+ * 0 : Reset (Peripheral not initialized)
+ * 1 : Init done (Peripheral initialized. HAL UART Init function already called)
+ * b4-b3 (not used)
+ * xx : Should be set to 00
+ * b2 Intrinsic process state
+ * 0 : Ready
+ * 1 : Busy (Peripheral busy with some configuration or internal operations)
+ * b1 (not used)
+ * x : Should be set to 0
+ * b0 Tx state
+ * 0 : Ready (no Tx operation ongoing)
+ * 1 : Busy (Tx operation ongoing)
+ * - RxState contains information related to Rx operations.
+ * RxState value coding follow below described bitmap :
+ * b7-b6 (not used)
+ * xx : Should be set to 00
+ * b5 Peripheral initialization status
+ * 0 : Reset (Peripheral not initialized)
+ * 1 : Init done (Peripheral initialized)
+ * b4-b2 (not used)
+ * xxx : Should be set to 000
+ * b1 Rx state
+ * 0 : Ready (no Rx operation ongoing)
+ * 1 : Busy (Rx operation ongoing)
+ * b0 (not used)
+ * x : Should be set to 0.
+ */
+typedef uint32_t HAL_UART_StateTypeDef;
+
+/**
+ * @brief HAL UART Reception type definition
+ * @note HAL UART Reception type value aims to identify which type of Reception is ongoing.
+ * It is expected to admit following values :
+ * HAL_UART_RECEPTION_STANDARD = 0x00U,
+ * HAL_UART_RECEPTION_TOIDLE = 0x01U,
+ * HAL_UART_RECEPTION_TORTO = 0x02U,
+ * HAL_UART_RECEPTION_TOCHARMATCH = 0x03U,
+ */
+typedef uint32_t HAL_UART_RxTypeTypeDef;
+
+/**
+ * @brief UART handle Structure definition
+ */
+typedef struct __UART_HandleTypeDef
+{
+ USART_TypeDef *Instance; /*!< UART registers base address */
+
+ UART_InitTypeDef Init; /*!< UART communication parameters */
+
+ UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */
+
+ uint16_t TxXferSize; /*!< UART Tx Transfer size */
+
+ __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */
+
+ uint16_t RxXferSize; /*!< UART Rx Transfer size */
+
+ __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */
+
+ uint16_t Mask; /*!< UART Rx RDR register mask */
+
+ uint32_t FifoMode; /*!< Specifies if the FIFO mode is being used.
+ This parameter can be a value of @ref UARTEx_FIFO_mode. */
+
+ uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */
+
+ uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */
+
+ __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */
+
+ void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
+
+ void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
+
+ DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< Locking object */
+
+ __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management
+ and also related to Tx operations. This parameter
+ can be a value of @ref HAL_UART_StateTypeDef */
+
+ __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. This
+ parameter can be a value of @ref HAL_UART_StateTypeDef */
+
+ __IO uint32_t ErrorCode; /*!< UART Error code */
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */
+ void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */
+ void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */
+ void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */
+ void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */
+ void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */
+ void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */
+ void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */
+ void (* RxFifoFullCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Fifo Full Callback */
+ void (* TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Fifo Empty Callback */
+ void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback */
+
+ void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */
+ void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+} UART_HandleTypeDef;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL UART Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */
+ HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */
+ HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */
+ HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */
+ HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */
+ HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */
+ HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */
+ HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */
+ HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */
+ HAL_UART_RX_FIFO_FULL_CB_ID = 0x09U, /*!< UART Rx Fifo Full Callback ID */
+ HAL_UART_TX_FIFO_EMPTY_CB_ID = 0x0AU, /*!< UART Tx Fifo Empty Callback ID */
+
+ HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */
+ HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */
+
+} HAL_UART_CallbackIDTypeDef;
+
+/**
+ * @brief HAL UART Callback pointer definition
+ */
+typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */
+typedef void (*pUART_RxEventCallbackTypeDef)
+(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */
+
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UART_Exported_Constants UART Exported Constants
+ * @{
+ */
+
+/** @defgroup UART_State_Definition UART State Code Definition
+ * @{
+ */
+#define HAL_UART_STATE_RESET 0x00000000U /*!< Peripheral is not initialized
+ Value is allowed for gState and RxState */
+#define HAL_UART_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use
+ Value is allowed for gState and RxState */
+#define HAL_UART_STATE_BUSY 0x00000024U /*!< an internal process is ongoing
+ Value is allowed for gState only */
+#define HAL_UART_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing
+ Value is allowed for gState only */
+#define HAL_UART_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing
+ Value is allowed for RxState only */
+#define HAL_UART_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing
+ Not to be used for neither gState nor RxState.Value is result
+ of combination (Or) between gState and RxState values */
+#define HAL_UART_STATE_TIMEOUT 0x000000A0U /*!< Timeout state
+ Value is allowed for gState only */
+#define HAL_UART_STATE_ERROR 0x000000E0U /*!< Error
+ Value is allowed for gState only */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Error_Definition UART Error Definition
+ * @{
+ */
+#define HAL_UART_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_UART_ERROR_PE (0x00000001U) /*!< Parity error */
+#define HAL_UART_ERROR_NE (0x00000002U) /*!< Noise error */
+#define HAL_UART_ERROR_FE (0x00000004U) /*!< Frame error */
+#define HAL_UART_ERROR_ORE (0x00000008U) /*!< Overrun error */
+#define HAL_UART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
+#define HAL_UART_ERROR_RTO (0x00000020U) /*!< Receiver Timeout error */
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+#define HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Stop_Bits UART Number of Stop Bits
+ * @{
+ */
+#define UART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< UART frame with 0.5 stop bit */
+#define UART_STOPBITS_1 0x00000000U /*!< UART frame with 1 stop bit */
+#define UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */
+#define UART_STOPBITS_2 USART_CR2_STOP_1 /*!< UART frame with 2 stop bits */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Parity UART Parity
+ * @{
+ */
+#define UART_PARITY_NONE 0x00000000U /*!< No parity */
+#define UART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */
+#define UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
+ * @{
+ */
+#define UART_HWCONTROL_NONE 0x00000000U /*!< No hardware control */
+#define UART_HWCONTROL_RTS USART_CR3_RTSE /*!< Request To Send */
+#define UART_HWCONTROL_CTS USART_CR3_CTSE /*!< Clear To Send */
+#define UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< Request and Clear To Send */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Mode UART Transfer Mode
+ * @{
+ */
+#define UART_MODE_RX USART_CR1_RE /*!< RX mode */
+#define UART_MODE_TX USART_CR1_TE /*!< TX mode */
+#define UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */
+/**
+ * @}
+ */
+
+/** @defgroup UART_State UART State
+ * @{
+ */
+#define UART_STATE_DISABLE 0x00000000U /*!< UART disabled */
+#define UART_STATE_ENABLE USART_CR1_UE /*!< UART enabled */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Over_Sampling UART Over Sampling
+ * @{
+ */
+#define UART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */
+#define UART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */
+/**
+ * @}
+ */
+
+/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method
+ * @{
+ */
+#define UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disable */
+#define UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_ClockPrescaler UART Clock Prescaler
+ * @{
+ */
+#define UART_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */
+#define UART_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */
+#define UART_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */
+#define UART_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */
+#define UART_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */
+#define UART_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */
+#define UART_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */
+#define UART_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */
+#define UART_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */
+#define UART_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */
+#define UART_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */
+#define UART_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */
+/**
+ * @}
+ */
+
+/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode
+ * @{
+ */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection
+ on start bit */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection
+ on falling edge */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection
+ on 0x7F frame detection */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection
+ on 0x55 frame detection */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Receiver_Timeout UART Receiver Timeout
+ * @{
+ */
+#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART Receiver Timeout disable */
+#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART Receiver Timeout enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_LIN UART Local Interconnection Network mode
+ * @{
+ */
+#define UART_LIN_DISABLE 0x00000000U /*!< Local Interconnect Network disable */
+#define UART_LIN_ENABLE USART_CR2_LINEN /*!< Local Interconnect Network enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_LIN_Break_Detection UART LIN Break Detection
+ * @{
+ */
+#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U /*!< LIN 10-bit break detection length */
+#define UART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL /*!< LIN 11-bit break detection length */
+/**
+ * @}
+ */
+
+/** @defgroup UART_DMA_Tx UART DMA Tx
+ * @{
+ */
+#define UART_DMA_TX_DISABLE 0x00000000U /*!< UART DMA TX disabled */
+#define UART_DMA_TX_ENABLE USART_CR3_DMAT /*!< UART DMA TX enabled */
+/**
+ * @}
+ */
+
+/** @defgroup UART_DMA_Rx UART DMA Rx
+ * @{
+ */
+#define UART_DMA_RX_DISABLE 0x00000000U /*!< UART DMA RX disabled */
+#define UART_DMA_RX_ENABLE USART_CR3_DMAR /*!< UART DMA RX enabled */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection
+ * @{
+ */
+#define UART_HALF_DUPLEX_DISABLE 0x00000000U /*!< UART half-duplex disabled */
+#define UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL /*!< UART half-duplex enabled */
+/**
+ * @}
+ */
+
+/** @defgroup UART_WakeUp_Methods UART WakeUp Methods
+ * @{
+ */
+#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U /*!< UART wake-up on idle line */
+#define UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE /*!< UART wake-up on address mark */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Request_Parameters UART Request Parameters
+ * @{
+ */
+#define UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */
+#define UART_SENDBREAK_REQUEST USART_RQR_SBKRQ /*!< Send Break Request */
+#define UART_MUTE_MODE_REQUEST USART_RQR_MMRQ /*!< Mute Mode Request */
+#define UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */
+#define UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type
+ * @{
+ */
+#define UART_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */
+#define UART_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */
+#define UART_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */
+#define UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */
+#define UART_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */
+#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */
+#define UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */
+#define UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U /*!< Auto Baud rate detection initialization */
+#define UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion
+ * @{
+ */
+#define UART_ADVFEATURE_TXINV_DISABLE 0x00000000U /*!< TX pin active level inversion disable */
+#define UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV /*!< TX pin active level inversion enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion
+ * @{
+ */
+#define UART_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */
+#define UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion
+ * @{
+ */
+#define UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U /*!< Binary data inversion disable */
+#define UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV /*!< Binary data inversion enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap
+ * @{
+ */
+#define UART_ADVFEATURE_SWAP_DISABLE 0x00000000U /*!< TX/RX pins swap disable */
+#define UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP /*!< TX/RX pins swap enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable
+ * @{
+ */
+#define UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */
+#define UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable
+ * @{
+ */
+#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U /*!< RX Auto Baud rate detection enable */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN /*!< RX Auto Baud rate detection disable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error
+ * @{
+ */
+#define UART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U /*!< DMA enable on Reception Error */
+#define UART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE /*!< DMA disable on Reception Error */
+/**
+ * @}
+ */
+
+/** @defgroup UART_MSB_First UART Advanced Feature MSB First
+ * @{
+ */
+#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received
+ first disable */
+#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received
+ first enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Stop_Mode_Enable UART Advanced Feature Stop Mode Enable
+ * @{
+ */
+#define UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U /*!< UART stop mode disable */
+#define UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM /*!< UART stop mode enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable
+ * @{
+ */
+#define UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U /*!< UART mute mode disable */
+#define UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME /*!< UART mute mode enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register
+ * @{
+ */
+#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */
+/**
+ * @}
+ */
+
+/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection
+ * @{
+ */
+#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */
+#define UART_WAKEUP_ON_READDATA_NONEMPTY 0x00000001U /*!< UART wake-up on receive data register
+ not empty or RXFIFO is not empty */
+/**
+ * @}
+ */
+
+/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity
+ * @{
+ */
+#define UART_DE_POLARITY_HIGH 0x00000000U /*!< Driver enable signal is active high */
+#define UART_DE_POLARITY_LOW USART_CR3_DEP /*!< Driver enable signal is active low */
+/**
+ * @}
+ */
+
+/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register
+ * @{
+ */
+#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB
+ position in CR1 register */
+/**
+ * @}
+ */
+
+/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register
+ * @{
+ */
+#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB
+ position in CR1 register */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask
+ * @{
+ */
+#define UART_IT_MASK 0x001FU /*!< UART interruptions flags mask */
+/**
+ * @}
+ */
+
+/** @defgroup UART_TimeOut_Value UART polling-based communications time-out value
+ * @{
+ */
+#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU /*!< UART polling-based communications time-out value */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Flags UART Status Flags
+ * Elements values convention: 0xXXXX
+ * - 0xXXXX : Flag mask in the ISR register
+ * @{
+ */
+#define UART_FLAG_TXFT USART_ISR_TXFT /*!< UART TXFIFO threshold flag */
+#define UART_FLAG_RXFT USART_ISR_RXFT /*!< UART RXFIFO threshold flag */
+#define UART_FLAG_RXFF USART_ISR_RXFF /*!< UART RXFIFO Full flag */
+#define UART_FLAG_TXFE USART_ISR_TXFE /*!< UART TXFIFO Empty flag */
+#define UART_FLAG_REACK USART_ISR_REACK /*!< UART receive enable acknowledge flag */
+#define UART_FLAG_TEACK USART_ISR_TEACK /*!< UART transmit enable acknowledge flag */
+#define UART_FLAG_RWU USART_ISR_RWU /*!< UART receiver wake-up from mute mode flag */
+#define UART_FLAG_SBKF USART_ISR_SBKF /*!< UART send break flag */
+#define UART_FLAG_CMF USART_ISR_CMF /*!< UART character match flag */
+#define UART_FLAG_BUSY USART_ISR_BUSY /*!< UART busy flag */
+#define UART_FLAG_ABRF USART_ISR_ABRF /*!< UART auto Baud rate flag */
+#define UART_FLAG_ABRE USART_ISR_ABRE /*!< UART auto Baud rate error */
+#define UART_FLAG_RTOF USART_ISR_RTOF /*!< UART receiver timeout flag */
+#define UART_FLAG_CTS USART_ISR_CTS /*!< UART clear to send flag */
+#define UART_FLAG_CTSIF USART_ISR_CTSIF /*!< UART clear to send interrupt flag */
+#define UART_FLAG_LBDF USART_ISR_LBDF /*!< UART LIN break detection flag */
+#define UART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< UART transmit data register empty */
+#define UART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< UART TXFIFO not full */
+#define UART_FLAG_TC USART_ISR_TC /*!< UART transmission complete */
+#define UART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< UART read data register not empty */
+#define UART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< UART RXFIFO not empty */
+#define UART_FLAG_IDLE USART_ISR_IDLE /*!< UART idle flag */
+#define UART_FLAG_ORE USART_ISR_ORE /*!< UART overrun error */
+#define UART_FLAG_NE USART_ISR_NE /*!< UART noise error */
+#define UART_FLAG_FE USART_ISR_FE /*!< UART frame error */
+#define UART_FLAG_PE USART_ISR_PE /*!< UART parity error */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Interrupt_definition UART Interrupts Definition
+ * Elements values convention: 000ZZZZZ0XXYYYYYb
+ * - YYYYY : Interrupt source position in the XX register (5bits)
+ * - XX : Interrupt source register (2bits)
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
+ * - ZZZZZ : Flag position in the ISR register(5bits)
+ * Elements values convention: 000000000XXYYYYYb
+ * - YYYYY : Interrupt source position in the XX register (5bits)
+ * - XX : Interrupt source register (2bits)
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
+ * Elements values convention: 0000ZZZZ00000000b
+ * - ZZZZ : Flag position in the ISR register(4bits)
+ * @{
+ */
+#define UART_IT_PE 0x0028U /*!< UART parity error interruption */
+#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */
+#define UART_IT_TXFNF 0x0727U /*!< UART TX FIFO not full interruption */
+#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */
+#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */
+#define UART_IT_RXFNE 0x0525U /*!< UART RXFIFO not empty interruption */
+#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */
+#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */
+#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */
+#define UART_IT_CM 0x112EU /*!< UART character match interruption */
+#define UART_IT_RXFF 0x183FU /*!< UART RXFIFO full interruption */
+#define UART_IT_TXFE 0x173EU /*!< UART TXFIFO empty interruption */
+#define UART_IT_RXFT 0x1A7CU /*!< UART RXFIFO threshold reached interruption */
+#define UART_IT_TXFT 0x1B77U /*!< UART TXFIFO threshold reached interruption */
+#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */
+
+#define UART_IT_ERR 0x0060U /*!< UART error interruption */
+
+#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */
+#define UART_IT_NE 0x0200U /*!< UART noise error interruption */
+#define UART_IT_FE 0x0100U /*!< UART frame error interruption */
+/**
+ * @}
+ */
+
+/** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags
+ * @{
+ */
+#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
+#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
+#define UART_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */
+#define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */
+#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
+#define UART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO empty clear flag */
+#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
+#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */
+#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */
+#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */
+#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< UART receiver timeout clear flag */
+/**
+ * @}
+ */
+
+/** @defgroup UART_RECEPTION_TYPE_Values UART Reception type values
+ * @{
+ */
+#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */
+#define HAL_UART_RECEPTION_TOIDLE (0x00000001U) /*!< Reception till completion or IDLE event */
+#define HAL_UART_RECEPTION_TORTO (0x00000002U) /*!< Reception till completion or RTO event */
+#define HAL_UART_RECEPTION_TOCHARMATCH (0x00000003U) /*!< Reception till completion or CM event */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup UART_Exported_Macros UART Exported Macros
+ * @{
+ */
+
+/** @brief Reset UART handle states.
+ * @param __HANDLE__ UART handle.
+ * @retval None
+ */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_UART_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0U)
+#else
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_UART_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
+ } while(0U)
+#endif /*USE_HAL_UART_REGISTER_CALLBACKS */
+
+/** @brief Flush the UART Data registers.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
+ SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
+ } while(0U)
+
+/** @brief Clear the specified UART pending flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag
+ * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag
+ * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag
+ * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag
+ * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag
+ * @arg @ref UART_CLEAR_TXFECF TXFIFO empty clear Flag
+ * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag
+ * @arg @ref UART_CLEAR_RTOF Receiver Timeout clear flag
+ * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag
+ * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag
+ * @arg @ref UART_CLEAR_CMF Character Match Clear Flag
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief Clear the UART PE pending flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
+
+/** @brief Clear the UART FE pending flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
+
+/** @brief Clear the UART NE pending flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
+
+/** @brief Clear the UART ORE pending flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
+
+/** @brief Clear the UART IDLE pending flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
+
+/** @brief Clear the UART TX FIFO empty clear flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_TXFECF(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF)
+
+/** @brief Check whether the specified UART flag is set or not.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_FLAG_TXFT TXFIFO threshold flag
+ * @arg @ref UART_FLAG_RXFT RXFIFO threshold flag
+ * @arg @ref UART_FLAG_RXFF RXFIFO Full flag
+ * @arg @ref UART_FLAG_TXFE TXFIFO Empty flag
+ * @arg @ref UART_FLAG_REACK Receive enable acknowledge flag
+ * @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag
+ * @arg @ref UART_FLAG_RWU Receiver wake up flag (if the UART in mute mode)
+ * @arg @ref UART_FLAG_SBKF Send Break flag
+ * @arg @ref UART_FLAG_CMF Character match flag
+ * @arg @ref UART_FLAG_BUSY Busy flag
+ * @arg @ref UART_FLAG_ABRF Auto Baud rate detection flag
+ * @arg @ref UART_FLAG_ABRE Auto Baud rate detection error flag
+ * @arg @ref UART_FLAG_CTS CTS Change flag
+ * @arg @ref UART_FLAG_LBDF LIN Break detection flag
+ * @arg @ref UART_FLAG_TXE Transmit data register empty flag
+ * @arg @ref UART_FLAG_TXFNF UART TXFIFO not full flag
+ * @arg @ref UART_FLAG_TC Transmission Complete flag
+ * @arg @ref UART_FLAG_RXNE Receive data register not empty flag
+ * @arg @ref UART_FLAG_RXFNE UART RXFIFO not empty flag
+ * @arg @ref UART_FLAG_RTOF Receiver Timeout flag
+ * @arg @ref UART_FLAG_IDLE Idle Line detection flag
+ * @arg @ref UART_FLAG_ORE Overrun Error flag
+ * @arg @ref UART_FLAG_NE Noise Error flag
+ * @arg @ref UART_FLAG_FE Framing Error flag
+ * @arg @ref UART_FLAG_PE Parity Error flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Enable the specified UART interrupt.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __INTERRUPT__ specifies the UART interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_IT_RXFF RXFIFO Full interrupt
+ * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt
+ * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt
+ * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt
+ * @arg @ref UART_IT_CM Character match interrupt
+ * @arg @ref UART_IT_CTS CTS change interrupt
+ * @arg @ref UART_IT_LBD LIN Break detection interrupt
+ * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
+ * @arg @ref UART_IT_TC Transmission complete interrupt
+ * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
+ * @arg @ref UART_IT_RTO Receive Timeout interrupt
+ * @arg @ref UART_IT_IDLE Idle line detection interrupt
+ * @arg @ref UART_IT_PE Parity Error interrupt
+ * @arg @ref UART_IT_ERR Error interrupt (frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (\
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\
+ ((__HANDLE__)->Instance->CR1 |= (1U <<\
+ ((__INTERRUPT__) & UART_IT_MASK))): \
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\
+ ((__HANDLE__)->Instance->CR2 |= (1U <<\
+ ((__INTERRUPT__) & UART_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 |= (1U <<\
+ ((__INTERRUPT__) & UART_IT_MASK))))
+
+/** @brief Disable the specified UART interrupt.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __INTERRUPT__ specifies the UART interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_IT_RXFF RXFIFO Full interrupt
+ * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt
+ * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt
+ * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt
+ * @arg @ref UART_IT_CM Character match interrupt
+ * @arg @ref UART_IT_CTS CTS change interrupt
+ * @arg @ref UART_IT_LBD LIN Break detection interrupt
+ * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
+ * @arg @ref UART_IT_TC Transmission complete interrupt
+ * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
+ * @arg @ref UART_IT_RTO Receive Timeout interrupt
+ * @arg @ref UART_IT_IDLE Idle line detection interrupt
+ * @arg @ref UART_IT_PE Parity Error interrupt
+ * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (\
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\
+ ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\
+ ((__INTERRUPT__) & UART_IT_MASK))): \
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\
+ ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\
+ ((__INTERRUPT__) & UART_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\
+ ((__INTERRUPT__) & UART_IT_MASK))))
+
+/** @brief Check whether the specified UART interrupt has occurred or not.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __INTERRUPT__ specifies the UART interrupt to check.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_IT_RXFF RXFIFO Full interrupt
+ * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt
+ * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt
+ * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt
+ * @arg @ref UART_IT_CM Character match interrupt
+ * @arg @ref UART_IT_CTS CTS change interrupt
+ * @arg @ref UART_IT_LBD LIN Break detection interrupt
+ * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
+ * @arg @ref UART_IT_TC Transmission complete interrupt
+ * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
+ * @arg @ref UART_IT_RTO Receive Timeout interrupt
+ * @arg @ref UART_IT_IDLE Idle line detection interrupt
+ * @arg @ref UART_IT_PE Parity Error interrupt
+ * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
+ * @retval The new state of __INTERRUPT__ (SET or RESET).
+ */
+#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
+ & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET)
+
+/** @brief Check whether the specified UART interrupt source is enabled or not.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __INTERRUPT__ specifies the UART interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_IT_RXFF RXFIFO Full interrupt
+ * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt
+ * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt
+ * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt
+ * @arg @ref UART_IT_CM Character match interrupt
+ * @arg @ref UART_IT_CTS CTS change interrupt
+ * @arg @ref UART_IT_LBD LIN Break detection interrupt
+ * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
+ * @arg @ref UART_IT_TC Transmission complete interrupt
+ * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
+ * @arg @ref UART_IT_RTO Receive Timeout interrupt
+ * @arg @ref UART_IT_IDLE Idle line detection interrupt
+ * @arg @ref UART_IT_PE Parity Error interrupt
+ * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
+ * @retval The new state of __INTERRUPT__ (SET or RESET).
+ */
+#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ?\
+ (__HANDLE__)->Instance->CR1 : \
+ (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ?\
+ (__HANDLE__)->Instance->CR2 : \
+ (__HANDLE__)->Instance->CR3)) & (1U <<\
+ (((uint16_t)(__INTERRUPT__)) &\
+ UART_IT_MASK))) != RESET) ? SET : RESET)
+
+/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
+ * to clear the corresponding interrupt
+ * This parameter can be one of the following values:
+ * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag
+ * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag
+ * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag
+ * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag
+ * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag
+ * @arg @ref UART_CLEAR_RTOF Receiver timeout clear flag
+ * @arg @ref UART_CLEAR_TXFECF TXFIFO empty Clear Flag
+ * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag
+ * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag
+ * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag
+ * @arg @ref UART_CLEAR_CMF Character Match Clear Flag
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+
+/** @brief Set a specific UART request flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __REQ__ specifies the request flag to set
+ * This parameter can be one of the following values:
+ * @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request
+ * @arg @ref UART_SENDBREAK_REQUEST Send Break Request
+ * @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request
+ * @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request
+ * @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request
+ * @retval None
+ */
+#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
+
+/** @brief Enable the UART one bit sample method.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief Disable the UART one bit sample method.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
+
+/** @brief Enable UART.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+
+/** @brief Disable UART.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+/** @brief Enable CTS flow control.
+ * @note This macro allows to enable CTS hardware flow control for a given UART instance,
+ * without need to call HAL_UART_Init() function.
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+ * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )
+ * - macro could only be called when corresponding UART instance is disabled
+ * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
+ * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \
+ do{ \
+ ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
+ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \
+ } while(0U)
+
+/** @brief Disable CTS flow control.
+ * @note This macro allows to disable CTS hardware flow control for a given UART instance,
+ * without need to call HAL_UART_Init() function.
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+ * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )
+ * - macro could only be called when corresponding UART instance is disabled
+ * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
+ * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \
+ do{ \
+ ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
+ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \
+ } while(0U)
+
+/** @brief Enable RTS flow control.
+ * @note This macro allows to enable RTS hardware flow control for a given UART instance,
+ * without need to call HAL_UART_Init() function.
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+ * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )
+ * - macro could only be called when corresponding UART instance is disabled
+ * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
+ * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \
+ do{ \
+ ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
+ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \
+ } while(0U)
+
+/** @brief Disable RTS flow control.
+ * @note This macro allows to disable RTS hardware flow control for a given UART instance,
+ * without need to call HAL_UART_Init() function.
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+ * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )
+ * - macro could only be called when corresponding UART instance is disabled
+ * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
+ * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \
+ do{ \
+ ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
+ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
+ } while(0U)
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup UART_Private_Macros UART Private Macros
+ * @{
+ */
+/** @brief Get UART clok division factor from clock prescaler value.
+ * @param __CLOCKPRESCALER__ UART prescaler value.
+ * @retval UART clock division factor
+ */
+#define UART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \
+ (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) ? 1U : \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) ? 2U : \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) ? 4U : \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) ? 6U : \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) ? 8U : \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) ? 10U : \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) ? 12U : \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) ? 16U : \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) ? 32U : \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) ? 64U : \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U)
+
+/** @brief BRR division operation to set BRR register with LPUART.
+ * @param __PCLK__ LPUART clock.
+ * @param __BAUD__ Baud rate set by the user.
+ * @param __CLOCKPRESCALER__ UART prescaler value.
+ * @retval Division result
+ */
+#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \
+ ((uint32_t)((((((uint64_t)(__PCLK__))/(UARTPrescTable[(__CLOCKPRESCALER__)]))*256U)+ \
+ (uint32_t)((__BAUD__)/2U)) / (__BAUD__)) \
+ )
+
+/** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
+ * @param __PCLK__ UART clock.
+ * @param __BAUD__ Baud rate set by the user.
+ * @param __CLOCKPRESCALER__ UART prescaler value.
+ * @retval Division result
+ */
+#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \
+ (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2U) + ((__BAUD__)/2U)) / (__BAUD__))
+
+/** @brief BRR division operation to set BRR register in 16-bit oversampling mode.
+ * @param __PCLK__ UART clock.
+ * @param __BAUD__ Baud rate set by the user.
+ * @param __CLOCKPRESCALER__ UART prescaler value.
+ * @retval Division result
+ */
+#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \
+ ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)]) + ((__BAUD__)/2U)) / (__BAUD__))
+
+/** @brief Check whether or not UART instance is Low Power UART.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval SET (instance is LPUART) or RESET (instance isn't LPUART)
+ */
+#define UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance))
+
+/** @brief Check UART Baud rate.
+ * @param __BAUDRATE__ Baudrate specified by the user.
+ * The maximum Baud Rate is derived from the maximum clock on U5 (i.e. 160 MHz)
+ * divided by the smallest oversampling used on the USART (i.e. 8)
+ * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)
+ */
+#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 20000000U)
+
+/** @brief Check UART assertion time.
+ * @param __TIME__ 5-bit value assertion time.
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
+
+/** @brief Check UART deassertion time.
+ * @param __TIME__ 5-bit value deassertion time.
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
+
+/**
+ * @brief Ensure that UART frame number of stop bits is valid.
+ * @param __STOPBITS__ UART frame number of stop bits.
+ * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
+ */
+#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \
+ ((__STOPBITS__) == UART_STOPBITS_1) || \
+ ((__STOPBITS__) == UART_STOPBITS_1_5) || \
+ ((__STOPBITS__) == UART_STOPBITS_2))
+
+/**
+ * @brief Ensure that LPUART frame number of stop bits is valid.
+ * @param __STOPBITS__ LPUART frame number of stop bits.
+ * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
+ */
+#define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \
+ ((__STOPBITS__) == UART_STOPBITS_2))
+
+/**
+ * @brief Ensure that UART frame parity is valid.
+ * @param __PARITY__ UART frame parity.
+ * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+ */
+#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \
+ ((__PARITY__) == UART_PARITY_EVEN) || \
+ ((__PARITY__) == UART_PARITY_ODD))
+
+/**
+ * @brief Ensure that UART hardware flow control is valid.
+ * @param __CONTROL__ UART hardware flow control.
+ * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)
+ */
+#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\
+ (((__CONTROL__) == UART_HWCONTROL_NONE) || \
+ ((__CONTROL__) == UART_HWCONTROL_RTS) || \
+ ((__CONTROL__) == UART_HWCONTROL_CTS) || \
+ ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
+
+/**
+ * @brief Ensure that UART communication mode is valid.
+ * @param __MODE__ UART communication mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
+
+/**
+ * @brief Ensure that UART state is valid.
+ * @param __STATE__ UART state.
+ * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
+ */
+#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \
+ ((__STATE__) == UART_STATE_ENABLE))
+
+/**
+ * @brief Ensure that UART oversampling is valid.
+ * @param __SAMPLING__ UART oversampling.
+ * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
+ */
+#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \
+ ((__SAMPLING__) == UART_OVERSAMPLING_8))
+
+/**
+ * @brief Ensure that UART frame sampling is valid.
+ * @param __ONEBIT__ UART frame sampling.
+ * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
+ */
+#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \
+ ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))
+
+/**
+ * @brief Ensure that UART auto Baud rate detection mode is valid.
+ * @param __MODE__ UART auto Baud rate detection mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \
+ ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
+ ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \
+ ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
+
+/**
+ * @brief Ensure that UART receiver timeout setting is valid.
+ * @param __TIMEOUT__ UART receiver timeout setting.
+ * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
+ */
+#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
+ ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
+
+/** @brief Check the receiver timeout value.
+ * @note The maximum UART receiver timeout value is 0xFFFFFF.
+ * @param __TIMEOUTVALUE__ receiver timeout value.
+ * @retval Test result (TRUE or FALSE)
+ */
+#define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
+
+/**
+ * @brief Ensure that UART LIN state is valid.
+ * @param __LIN__ UART LIN state.
+ * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid)
+ */
+#define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || \
+ ((__LIN__) == UART_LIN_ENABLE))
+
+/**
+ * @brief Ensure that UART LIN break detection length is valid.
+ * @param __LENGTH__ UART LIN break detection length.
+ * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+ */
+#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \
+ ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))
+
+/**
+ * @brief Ensure that UART DMA TX state is valid.
+ * @param __DMATX__ UART DMA TX state.
+ * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
+ */
+#define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || \
+ ((__DMATX__) == UART_DMA_TX_ENABLE))
+
+/**
+ * @brief Ensure that UART DMA RX state is valid.
+ * @param __DMARX__ UART DMA RX state.
+ * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
+ */
+#define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \
+ ((__DMARX__) == UART_DMA_RX_ENABLE))
+
+/**
+ * @brief Ensure that UART half-duplex state is valid.
+ * @param __HDSEL__ UART half-duplex state.
+ * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)
+ */
+#define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \
+ ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))
+
+/**
+ * @brief Ensure that UART wake-up method is valid.
+ * @param __WAKEUP__ UART wake-up method .
+ * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)
+ */
+#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \
+ ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))
+
+/**
+ * @brief Ensure that UART request parameter is valid.
+ * @param __PARAM__ UART request parameter.
+ * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+ */
+#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \
+ ((__PARAM__) == UART_SENDBREAK_REQUEST) || \
+ ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \
+ ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \
+ ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))
+
+/**
+ * @brief Ensure that UART advanced features initialization is valid.
+ * @param __INIT__ UART advanced features initialization.
+ * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \
+ UART_ADVFEATURE_TXINVERT_INIT | \
+ UART_ADVFEATURE_RXINVERT_INIT | \
+ UART_ADVFEATURE_DATAINVERT_INIT | \
+ UART_ADVFEATURE_SWAP_INIT | \
+ UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \
+ UART_ADVFEATURE_DMADISABLEONERROR_INIT | \
+ UART_ADVFEATURE_AUTOBAUDRATE_INIT | \
+ UART_ADVFEATURE_MSBFIRST_INIT))
+
+/**
+ * @brief Ensure that UART frame TX inversion setting is valid.
+ * @param __TXINV__ UART frame TX inversion setting.
+ * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \
+ ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))
+
+/**
+ * @brief Ensure that UART frame RX inversion setting is valid.
+ * @param __RXINV__ UART frame RX inversion setting.
+ * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \
+ ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))
+
+/**
+ * @brief Ensure that UART frame data inversion setting is valid.
+ * @param __DATAINV__ UART frame data inversion setting.
+ * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \
+ ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))
+
+/**
+ * @brief Ensure that UART frame RX/TX pins swap setting is valid.
+ * @param __SWAP__ UART frame RX/TX pins swap setting.
+ * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \
+ ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))
+
+/**
+ * @brief Ensure that UART frame overrun setting is valid.
+ * @param __OVERRUN__ UART frame overrun setting.
+ * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
+ */
+#define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
+ ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))
+
+/**
+ * @brief Ensure that UART auto Baud rate state is valid.
+ * @param __AUTOBAUDRATE__ UART auto Baud rate state.
+ * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == \
+ UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
+ ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
+
+/**
+ * @brief Ensure that UART DMA enabling or disabling on error setting is valid.
+ * @param __DMA__ UART DMA enabling or disabling on error setting.
+ * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
+ ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))
+
+/**
+ * @brief Ensure that UART frame MSB first setting is valid.
+ * @param __MSBFIRST__ UART frame MSB first setting.
+ * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
+ ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))
+
+/**
+ * @brief Ensure that UART stop mode state is valid.
+ * @param __STOPMODE__ UART stop mode state.
+ * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
+ ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))
+
+/**
+ * @brief Ensure that UART mute mode state is valid.
+ * @param __MUTE__ UART mute mode state.
+ * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)
+ */
+#define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
+ ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))
+
+/**
+ * @brief Ensure that UART wake-up selection is valid.
+ * @param __WAKE__ UART wake-up selection.
+ * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)
+ */
+#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \
+ ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))
+
+/**
+ * @brief Ensure that UART driver enable polarity is valid.
+ * @param __POLARITY__ UART driver enable polarity.
+ * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)
+ */
+#define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \
+ ((__POLARITY__) == UART_DE_POLARITY_LOW))
+
+/**
+ * @brief Ensure that UART Prescaler is valid.
+ * @param __CLOCKPRESCALER__ UART Prescaler value.
+ * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
+ */
+#define IS_UART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) || \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) || \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) || \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) || \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) || \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) || \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) || \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) || \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) || \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) || \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) || \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256))
+
+/**
+ * @}
+ */
+
+/* Include UART HAL Extended module */
+#include "stm32u5xx_hal_uart_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UART_Exported_Functions UART Exported Functions
+ * @{
+ */
+
+/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart);
+void HAL_UART_MspInit(UART_HandleTypeDef *huart);
+void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
+ pUART_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
+
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
+void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);
+
+void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size);
+
+/**
+ * @}
+ */
+
+/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+
+/* Peripheral Control functions ************************************************/
+void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue);
+HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart);
+
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
+void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
+
+/**
+ * @}
+ */
+
+/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions
+ * @{
+ */
+
+/* Peripheral State and Errors functions **************************************************/
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
+uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions -----------------------------------------------------------*/
+/** @addtogroup UART_Private_Functions UART Private Functions
+ * @{
+ */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
+ uint32_t Tickstart, uint32_t Timeout);
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+
+/**
+ * @}
+ */
+
+/* Private variables -----------------------------------------------------------*/
+/** @defgroup UART_Private_variables UART Private variables
+ * @{
+ */
+/* Prescaler Table used in BRR computation macros.
+ Declared as extern here to allow use of private UART macros, outside of HAL UART functions */
+extern const uint16_t UARTPrescTable[12];
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_UART_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart_ex.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart_ex.h
new file mode 100644
index 00000000..e1c97ff9
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart_ex.h
@@ -0,0 +1,514 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_uart_ex.h
+ * @author MCD Application Team
+ * @brief Header file of UART HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_UART_EX_H
+#define STM32U5xx_HAL_UART_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup UARTEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UARTEx_Exported_Types UARTEx Exported Types
+ * @{
+ */
+
+/**
+ * @brief UART wake up from stop mode parameters
+ */
+typedef struct
+{
+ uint32_t WakeUpEvent; /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF).
+ This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
+ If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
+ be filled up. */
+
+ uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long.
+ This parameter can be a value of @ref UARTEx_WakeUp_Address_Length. */
+
+ uint8_t Address; /*!< UART/USART node address (7-bit long max). */
+} UART_WakeUpTypeDef;
+
+/**
+ * @brief UART Autonomous mode parameters
+ */
+typedef struct
+{
+ uint32_t AutonomousModeState; /*!< Specifies the autonomous mode state.This parameter can be a value of
+ @ref UARTEx_Autonomous_mode.*/
+
+ uint32_t TriggerSelection; /*!< Specifies which trigger will activate the Transmission automatically.
+ This parameter can be a value of @ref UARTEx_Autonomous_Trigger_selection
+ or @ref LPUARTEx_Autonomous_Trigger_selection.*/
+
+ uint32_t TriggerPolarity; /*!< Specifies the autonomous mode trigger signal polarity.
+ This parameter can be a value of @ref UARTEx_Autonomous_Trigger_Polarity */
+
+ uint32_t DataSize; /*!< Specifies the transmitted data size in byte */
+
+ uint32_t IdleFrame; /*!< Specifies whether the IDLE frame transmission is enabled or disabled.
+ This parameter can be a value of @ref UARTEx_Autonomous_IDLE_FRAME. */
+} UART_AutonomousModeConfTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
+ * @{
+ */
+
+/** @defgroup UARTEx_Word_Length UARTEx Word Length
+ * @{
+ */
+#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */
+#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */
+#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */
+/**
+ * @}
+ */
+
+/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length
+ * @{
+ */
+#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */
+#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */
+/**
+ * @}
+ */
+
+/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode
+ * @brief UART FIFO mode
+ * @{
+ */
+#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */
+#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */
+/**
+ * @}
+ */
+
+/** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level
+ * @brief UART TXFIFO threshold level
+ * @{
+ */
+#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TX FIFO reaches 1/8 of its depth */
+#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TX FIFO reaches 1/4 of its depth */
+#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TX FIFO reaches 1/2 of its depth */
+#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TX FIFO reaches 3/4 of its depth */
+#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TX FIFO reaches 7/8 of its depth */
+#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TX FIFO becomes empty */
+/**
+ * @}
+ */
+
+/** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level
+ * @brief UART RXFIFO threshold level
+ * @{
+ */
+#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RX FIFO reaches 1/8 of its depth */
+#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RX FIFO reaches 1/4 of its depth */
+#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RX FIFO reaches 1/2 of its depth */
+#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RX FIFO reaches 3/4 of its depth */
+#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RX FIFO reaches 7/8 of its depth */
+#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RX FIFO becomes full */
+/**
+ * @}
+ */
+
+/** @defgroup UARTEx_Autonomous_mode UARTEx Autonomous Mode
+ * @brief UART Autonomous mode
+ * @{
+ */
+#define UART_AUTONOMOUS_MODE_DISABLE 0x00000000U /*!< Autonomous mode disable */
+#define UART_AUTONOMOUS_MODE_ENABLE USART_AUTOCR_TRIGEN /*!< Autonomous mode enable */
+/**
+ * @}
+ */
+
+/** @defgroup UARTEx_Autonomous_Trigger_Polarity UARTEx Autonomous Trigger Polarity
+ * @brief UART Trigger polarity edge selection
+ * @{
+ */
+#define UART_TRIG_POLARITY_RISING 0x00000000U /*!< UART triggered on rising edge */
+#define UART_TRIG_POLARITY_FALLING USART_AUTOCR_TRIGPOL /*!< UART triggered on falling edge */
+/**
+ * @}
+ */
+
+/** @defgroup UARTEx_Autonomous_IDLE_FRAME UARTEx Autonomous IDLE Frame
+ * @brief UART IDLE frame transmission
+ * @{
+ */
+#define UART_IDLE_FRAME_ENABLE 0x00000000U /*!< IDLE Frame sent after enabling the transmitter */
+#define UART_IDLE_FRAME_DISABLE USART_AUTOCR_IDLEDIS /*!< IDLE Frame not sent after enabling the transmitter */
+/**
+ * @}
+ */
+
+/** @defgroup UARTEx_Autonomous_Trigger_selection UARTEx Autonomous trigger selection
+ * @brief UART Autonomous Trigger selection
+ * @{
+ */
+#define UART_GPDMA1_CH0_TCF_TRG 0U /*!< UART GPDMA1 channel0 Internal Trigger */
+#define UART_GPDMA1_CH1_TCF_TRG 1U /*!< UART GPDMA1 channel1 Internal Trigger */
+#define UART_GPDMA1_CH2_TCF_TRG 2U /*!< UART GPDMA1 channel2 Internal Trigger */
+#define UART_GPDMA1_CH3_TCF_TRG 3U /*!< UART GPDMA1 channel3 Internal Trigger */
+#define UART_EXTI_LINE6_TRG 4U /*!< UART EXTI line 6 Internal Trigger */
+#define UART_EXTI_LINE9_TRG 5U /*!< UART EXTI line 9 Internal Trigger */
+#define UART_LPTIM1_OUT_TRG 6U /*!< UART LPTIM1 out Internal Trigger */
+#define UART_LPTIM2_OUT_TRG 7U /*!< UART LPTIM2 out Internal Trigger */
+#define UART_COMP1_OUT_TRG 8U /*!< UART COMP1 out Internal Trigger */
+#define UART_COMP2_OUT_TRG 9U /*!< UART COMP2 out Internal Trigger */
+#define UART_RTC_ALRA_TRG 10U /*!< UART RTC alarm Internal Trigger */
+#define UART_RTC_WUT_TRG 11U /*!< UART RTC wakeup Internal Trigger */
+/**
+ * @}
+ */
+
+/** @defgroup LPUARTEx_Autonomous_Trigger_selection LPUARTEx Autonomous trigger selection
+ * @brief LPUART Autonomous Trigger selection
+ * @{
+ */
+#define LPUART_LPDMA1_CH0_TCF_TRG 0U /*!< LPUART LPDMA1 channel0 Internal Trigger */
+#define LPUART_LPDMA1_CH1_TCF_TRG 1U /*!< LPUART LPDMA1 channel1 Internal Trigger */
+#define LPUART_LPDMA1_CH2_TCF_TRG 2U /*!< LPUART LPDMA1 channel2 Internal Trigger */
+#define LPUART_LPDMA1_CH3_TCF_TRG 3U /*!< LPUART LPDMA1 channel3 Internal Trigger */
+#define LPUART_EXTI_LINE6_TRG 4U /*!< LPUART EXTI line 6 Internal Trigger */
+#define LPUART_EXTI_LINE8_TRG 5U /*!< LPUART EXTI line 8 Internal Trigger */
+#define LPUART_LPTIM1_OUT_TRG 6U /*!< LPUART LPTIM1 out Internal Trigger */
+#define LPUART_LPTIM3_OUT_TRG 7U /*!< LPUART LPTIM3 out Internal Trigger */
+#define LPUART_COMP1_OUT_TRG 8U /*!< LPUART COMP1 out Internal Trigger */
+#define LPUART_COMP2_OUT_TRG 9U /*!< LPUART COMP2 out Internal Trigger */
+#define LPUART_RTC_ALRA_TRG 10U /*!< LPUART RTC alarm Internal Trigger */
+#define LPUART_RTC_WUT_TRG 11U /*!< LPUART RTC wakeup Internal Trigger */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UARTEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup UARTEx_Exported_Functions_Group1
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
+ uint32_t DeassertionTime);
+
+/**
+ * @}
+ */
+
+/** @addtogroup UARTEx_Exported_Functions_Group2
+ * @{
+ */
+
+void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
+
+void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart);
+void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart);
+
+/**
+ * @}
+ */
+
+/** @addtogroup UARTEx_Exported_Functions_Group3
+ * @{
+ */
+
+/* Peripheral Control functions **********************************************/
+HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
+HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
+
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
+
+HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
+HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
+
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+
+/* Autonomous Mode Control functions **********************************************/
+HAL_StatusTypeDef HAL_UARTEx_SetConfigAutonomousMode(UART_HandleTypeDef *huart,
+ UART_AutonomousModeConfTypeDef *sConfig);
+HAL_StatusTypeDef HAL_UARTEx_GetConfigAutonomousMode(UART_HandleTypeDef *huart,
+ UART_AutonomousModeConfTypeDef *sConfig);
+HAL_StatusTypeDef HAL_UARTEx_ClearConfigAutonomousMode(UART_HandleTypeDef *huart);
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UARTEx_Private_Macros UARTEx Private Macros
+ * @{
+ */
+
+/** @brief Report the UART clock source.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __CLOCKSOURCE__ output variable.
+ * @retval UART clocking source, written in __CLOCKSOURCE__.
+ */
+#if defined(USART6)
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ (__CLOCKSOURCE__) = RCC_PERIPHCLK_USART1; \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ (__CLOCKSOURCE__) = RCC_PERIPHCLK_USART2; \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ (__CLOCKSOURCE__) = RCC_PERIPHCLK_USART3; \
+ } \
+ else if((__HANDLE__)->Instance == UART4) \
+ { \
+ (__CLOCKSOURCE__) = RCC_PERIPHCLK_UART4; \
+ } \
+ else if((__HANDLE__)->Instance == UART5) \
+ { \
+ (__CLOCKSOURCE__) = RCC_PERIPHCLK_UART5; \
+ } \
+ else if((__HANDLE__)->Instance == USART6) \
+ { \
+ (__CLOCKSOURCE__) = RCC_PERIPHCLK_USART6; \
+ } \
+ else if((__HANDLE__)->Instance == LPUART1) \
+ { \
+ (__CLOCKSOURCE__) = RCC_PERIPHCLK_LPUART1; \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = 0U; \
+ } \
+ } while(0U)
+#else
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ (__CLOCKSOURCE__) = RCC_PERIPHCLK_USART1; \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ (__CLOCKSOURCE__) = RCC_PERIPHCLK_USART2; \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ (__CLOCKSOURCE__) = RCC_PERIPHCLK_USART3; \
+ } \
+ else if((__HANDLE__)->Instance == UART4) \
+ { \
+ (__CLOCKSOURCE__) = RCC_PERIPHCLK_UART4; \
+ } \
+ else if((__HANDLE__)->Instance == UART5) \
+ { \
+ (__CLOCKSOURCE__) = RCC_PERIPHCLK_UART5; \
+ } \
+ else if((__HANDLE__)->Instance == LPUART1) \
+ { \
+ (__CLOCKSOURCE__) = RCC_PERIPHCLK_LPUART1; \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = 0U; \
+ } \
+ } while(0U)
+#endif /* USART6 */
+
+/** @brief Report the UART mask to apply to retrieve the received data
+ * according to the word length and to the parity bits activation.
+ * @note If PCE = 1, the parity bit is not included in the data extracted
+ * by the reception API().
+ * This masking operation is not carried out in the case of
+ * DMA transfers.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
+ */
+#define UART_MASK_COMPUTATION(__HANDLE__) \
+ do { \
+ if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x01FFU ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x00FFU ; \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x00FFU ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x007FU ; \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x007FU ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x003FU ; \
+ } \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x0000U; \
+ } \
+ } while(0U)
+
+/**
+ * @brief Ensure that UART frame length is valid.
+ * @param __LENGTH__ UART frame length.
+ * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+ */
+#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
+ ((__LENGTH__) == UART_WORDLENGTH_8B) || \
+ ((__LENGTH__) == UART_WORDLENGTH_9B))
+
+/**
+ * @brief Ensure that UART wake-up address length is valid.
+ * @param __ADDRESS__ UART wake-up address length.
+ * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
+ */
+#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
+ ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
+
+/**
+ * @brief Ensure that UART TXFIFO threshold level is valid.
+ * @param __THRESHOLD__ UART TXFIFO threshold level.
+ * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
+ */
+#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \
+ ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \
+ ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \
+ ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \
+ ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \
+ ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8))
+
+/**
+ * @brief Ensure that UART RXFIFO threshold level is valid.
+ * @param __THRESHOLD__ UART RXFIFO threshold level.
+ * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
+ */
+#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \
+ ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \
+ ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \
+ ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \
+ ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \
+ ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8))
+
+/**
+ * @brief Ensure that UART Trigger polarity state is valid.
+ * @param __POLARITY__ UART Trigger polarity.
+ * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)
+ */
+#define IS_UART_TRIGGER_POLARITY(__POLARITY__) (((__POLARITY__) == UART_TRIG_POLARITY_RISING) ||\
+ ((__POLARITY__) == UART_TRIG_POLARITY_FALLING))
+
+/**
+ * @brief Ensure that UART IDLE Frame Transmit state is valid.
+ * @param __IDLE__ UART IDLE Frame Transmit state.
+ * @retval SET (__IDLE__ is valid) or RESET (__IDLE__ is invalid)
+ */
+#define IS_UART_IDLE_FRAME_TRANSMIT(__IDLE__) (((__IDLE__) == UART_IDLE_FRAME_ENABLE) ||\
+ ((__IDLE__) == UART_IDLE_FRAME_DISABLE))
+
+/**
+ * @brief Ensure that UART Trigger source selection is valid.
+ * @param __SOURCE__ UART Trigger source selection.
+ * @retval SET (__SOURCE__ is valid) or RESET (__SOURCE__ is invalid)
+ */
+#define IS_UART_TRIGGER_SELECTION(__SOURCE__) ((__SOURCE__) <= 11U)
+
+/**
+ * @brief Ensure that LPUART Trigger source selection is valid.
+ * @param __SOURCE__ LPUART Trigger source selection.
+ * @retval SET (__SOURCE__ is valid) or RESET (__SOURCE__ is invalid)
+ */
+#define IS_LPUART_TRIGGER_SELECTION(__SOURCE__) ((__SOURCE__) <= 11U)
+
+/**
+ * @brief Ensure that the number of transferred data is valid.
+ * @param __SOURCE__ UART TX data size.
+ * @retval SET (__SOURCE__ is valid) or RESET (__SOURCE__ is invalid)
+ */
+#define IS_UART_TX_DATA_SIZE(__SOURCE__) ((__SOURCE__) <= 0xFFFFU)
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_UART_EX_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_usart.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_usart.h
new file mode 100644
index 00000000..51b241af
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_usart.h
@@ -0,0 +1,1077 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_usart.h
+ * @author MCD Application Team
+ * @brief Header file of USART HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_USART_H
+#define STM32U5xx_HAL_USART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup USART
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup USART_Exported_Types USART Exported Types
+ * @{
+ */
+
+/**
+ * @brief USART Init Structure definition
+ */
+typedef struct
+{
+ uint32_t BaudRate; /*!< This member configures the Usart communication baud rate.
+ The baud rate is computed using the following formula:
+ Baud Rate Register[15:4] = ((2 * fclk_pres) /
+ ((huart->Init.BaudRate)))[15:4]
+ Baud Rate Register[3] = 0
+ Baud Rate Register[2:0] = (((2 * fclk_pres) /
+ ((huart->Init.BaudRate)))[3:0]) >> 1
+ where fclk_pres is the USART input clock frequency (fclk)
+ divided by a prescaler.
+ @note Oversampling by 8 is systematically applied to
+ achieve high baud rates. */
+
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref USARTEx_Word_Length. */
+
+ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref USART_Stop_Bits. */
+
+ uint32_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref USART_Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits). */
+
+ uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref USART_Mode. */
+
+ uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
+ This parameter can be a value of @ref USART_Clock_Polarity. */
+
+ uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref USART_Clock_Phase. */
+
+ uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+ This parameter can be a value of @ref USART_Last_Bit. */
+
+ uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the USART clock source.
+ This parameter can be a value of @ref USART_ClockPrescaler. */
+} USART_InitTypeDef;
+
+/**
+ * @brief HAL USART State structures definition
+ */
+typedef enum
+{
+ HAL_USART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized */
+ HAL_USART_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
+ HAL_USART_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
+ HAL_USART_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
+ HAL_USART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
+ HAL_USART_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission Reception process is ongoing */
+ HAL_USART_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
+ HAL_USART_STATE_ERROR = 0x04U /*!< Error */
+} HAL_USART_StateTypeDef;
+
+/**
+ * @brief USART clock sources definitions
+ */
+typedef enum
+{
+ USART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
+ USART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
+ USART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
+ USART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
+ USART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
+ USART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */
+} USART_ClockSourceTypeDef;
+
+/**
+ * @brief USART handle Structure definition
+ */
+typedef struct __USART_HandleTypeDef
+{
+ USART_TypeDef *Instance; /*!< USART registers base address */
+
+ USART_InitTypeDef Init; /*!< USART communication parameters */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */
+
+ uint16_t TxXferSize; /*!< USART Tx Transfer size */
+
+ __IO uint16_t TxXferCount; /*!< USART Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /*!< Pointer to USART Rx transfer Buffer */
+
+ uint16_t RxXferSize; /*!< USART Rx Transfer size */
+
+ __IO uint16_t RxXferCount; /*!< USART Rx Transfer Counter */
+
+ uint16_t Mask; /*!< USART Rx RDR register mask */
+
+ uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */
+
+ uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */
+
+ uint32_t SlaveMode; /*!< Enable/Disable UART SPI Slave Mode. This parameter can be a value
+ of @ref USARTEx_Slave_Mode */
+
+ uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used. This parameter can be a value
+ of @ref USARTEx_FIFO_mode. */
+
+ void (*RxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Rx IRQ handler */
+
+ void (*TxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Tx IRQ handler */
+
+ DMA_HandleTypeDef *hdmatx; /*!< USART Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< Locking object */
+
+ __IO HAL_USART_StateTypeDef State; /*!< USART communication state */
+
+ __IO uint32_t ErrorCode; /*!< USART Error code */
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ void (* TxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Half Complete Callback */
+ void (* TxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Complete Callback */
+ void (* RxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Half Complete Callback */
+ void (* RxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Complete Callback */
+ void (* TxRxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Rx Complete Callback */
+ void (* ErrorCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Error Callback */
+ void (* AbortCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Abort Complete Callback */
+ void (* RxFifoFullCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Fifo Full Callback */
+ void (* TxFifoEmptyCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Fifo Empty Callback */
+
+ void (* MspInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp Init callback */
+ void (* MspDeInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp DeInit callback */
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+
+} USART_HandleTypeDef;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL USART Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_USART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< USART Tx Half Complete Callback ID */
+ HAL_USART_TX_COMPLETE_CB_ID = 0x01U, /*!< USART Tx Complete Callback ID */
+ HAL_USART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< USART Rx Half Complete Callback ID */
+ HAL_USART_RX_COMPLETE_CB_ID = 0x03U, /*!< USART Rx Complete Callback ID */
+ HAL_USART_TX_RX_COMPLETE_CB_ID = 0x04U, /*!< USART Tx Rx Complete Callback ID */
+ HAL_USART_ERROR_CB_ID = 0x05U, /*!< USART Error Callback ID */
+ HAL_USART_ABORT_COMPLETE_CB_ID = 0x06U, /*!< USART Abort Complete Callback ID */
+ HAL_USART_RX_FIFO_FULL_CB_ID = 0x07U, /*!< USART Rx Fifo Full Callback ID */
+ HAL_USART_TX_FIFO_EMPTY_CB_ID = 0x08U, /*!< USART Tx Fifo Empty Callback ID */
+
+ HAL_USART_MSPINIT_CB_ID = 0x09U, /*!< USART MspInit callback ID */
+ HAL_USART_MSPDEINIT_CB_ID = 0x0AU /*!< USART MspDeInit callback ID */
+
+} HAL_USART_CallbackIDTypeDef;
+
+/**
+ * @brief HAL USART Callback pointer definition
+ */
+typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< pointer to an USART callback function */
+
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup USART_Exported_Constants USART Exported Constants
+ * @{
+ */
+
+/** @defgroup USART_Error_Definition USART Error Definition
+ * @{
+ */
+#define HAL_USART_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_USART_ERROR_PE (0x00000001U) /*!< Parity error */
+#define HAL_USART_ERROR_NE (0x00000002U) /*!< Noise error */
+#define HAL_USART_ERROR_FE (0x00000004U) /*!< Frame error */
+#define HAL_USART_ERROR_ORE (0x00000008U) /*!< Overrun error */
+#define HAL_USART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
+#define HAL_USART_ERROR_UDR (0x00000020U) /*!< SPI slave underrun error */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+#define HAL_USART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+#define HAL_USART_ERROR_RTO (0x00000080U) /*!< Receiver Timeout error */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Stop_Bits USART Number of Stop Bits
+ * @{
+ */
+#define USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< USART frame with 0.5 stop bit */
+#define USART_STOPBITS_1 0x00000000U /*!< USART frame with 1 stop bit */
+#define USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< USART frame with 1.5 stop bits */
+#define USART_STOPBITS_2 USART_CR2_STOP_1 /*!< USART frame with 2 stop bits */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Parity USART Parity
+ * @{
+ */
+#define USART_PARITY_NONE 0x00000000U /*!< No parity */
+#define USART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */
+#define USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Mode USART Mode
+ * @{
+ */
+#define USART_MODE_RX USART_CR1_RE /*!< RX mode */
+#define USART_MODE_TX USART_CR1_TE /*!< TX mode */
+#define USART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock USART Clock
+ * @{
+ */
+#define USART_CLOCK_DISABLE 0x00000000U /*!< USART clock disable */
+#define USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< USART clock enable */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock_Polarity USART Clock Polarity
+ * @{
+ */
+#define USART_POLARITY_LOW 0x00000000U /*!< Driver enable signal is active high */
+#define USART_POLARITY_HIGH USART_CR2_CPOL /*!< Driver enable signal is active low */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock_Phase USART Clock Phase
+ * @{
+ */
+#define USART_PHASE_1EDGE 0x00000000U /*!< USART frame phase on first clock transition */
+#define USART_PHASE_2EDGE USART_CR2_CPHA /*!< USART frame phase on second clock transition */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Last_Bit USART Last Bit
+ * @{
+ */
+#define USART_LASTBIT_DISABLE 0x00000000U /*!< USART frame last data bit clock pulse not output to SCLK pin */
+#define USART_LASTBIT_ENABLE USART_CR2_LBCL /*!< USART frame last data bit clock pulse output to SCLK pin */
+/**
+ * @}
+ */
+
+/** @defgroup USART_ClockPrescaler USART Clock Prescaler
+ * @{
+ */
+#define USART_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */
+#define USART_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */
+#define USART_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */
+#define USART_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */
+#define USART_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */
+#define USART_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */
+#define USART_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */
+#define USART_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */
+#define USART_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */
+#define USART_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */
+#define USART_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */
+#define USART_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Request_Parameters USART Request Parameters
+ * @{
+ */
+#define USART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */
+#define USART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Flags USART Flags
+ * Elements values convention: 0xXXXX
+ * - 0xXXXX : Flag mask in the ISR register
+ * @{
+ */
+#define USART_FLAG_TXFT USART_ISR_TXFT /*!< USART TXFIFO threshold flag */
+#define USART_FLAG_RXFT USART_ISR_RXFT /*!< USART RXFIFO threshold flag */
+#define USART_FLAG_RXFF USART_ISR_RXFF /*!< USART RXFIFO Full flag */
+#define USART_FLAG_TXFE USART_ISR_TXFE /*!< USART TXFIFO Empty flag */
+#define USART_FLAG_REACK USART_ISR_REACK /*!< USART receive enable acknowledge flag */
+#define USART_FLAG_TEACK USART_ISR_TEACK /*!< USART transmit enable acknowledge flag */
+#define USART_FLAG_BUSY USART_ISR_BUSY /*!< USART busy flag */
+#define USART_FLAG_UDR USART_ISR_UDR /*!< SPI slave underrun error flag */
+#define USART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< USART transmit data register empty */
+#define USART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< USART TXFIFO not full */
+#define USART_FLAG_RTOF USART_ISR_RTOF /*!< USART receiver timeout flag */
+#define USART_FLAG_TC USART_ISR_TC /*!< USART transmission complete */
+#define USART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< USART read data register not empty */
+#define USART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< USART RXFIFO not empty */
+#define USART_FLAG_IDLE USART_ISR_IDLE /*!< USART idle flag */
+#define USART_FLAG_ORE USART_ISR_ORE /*!< USART overrun error */
+#define USART_FLAG_NE USART_ISR_NE /*!< USART noise error */
+#define USART_FLAG_FE USART_ISR_FE /*!< USART frame error */
+#define USART_FLAG_PE USART_ISR_PE /*!< USART parity error */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Interrupt_definition USART Interrupts Definition
+ * Elements values convention: 0000ZZZZ0XXYYYYYb
+ * - YYYYY : Interrupt source position in the XX register (5bits)
+ * - XX : Interrupt source register (2bits)
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
+ * - ZZZZ : Flag position in the ISR register(4bits)
+ * @{
+ */
+
+#define USART_IT_PE 0x0028U /*!< USART parity error interruption */
+#define USART_IT_TXE 0x0727U /*!< USART transmit data register empty interruption */
+#define USART_IT_TXFNF 0x0727U /*!< USART TX FIFO not full interruption */
+#define USART_IT_TC 0x0626U /*!< USART transmission complete interruption */
+#define USART_IT_RXNE 0x0525U /*!< USART read data register not empty interruption */
+#define USART_IT_RXFNE 0x0525U /*!< USART RXFIFO not empty interruption */
+#define USART_IT_IDLE 0x0424U /*!< USART idle interruption */
+#define USART_IT_ERR 0x0060U /*!< USART error interruption */
+#define USART_IT_ORE 0x0300U /*!< USART overrun error interruption */
+#define USART_IT_NE 0x0200U /*!< USART noise error interruption */
+#define USART_IT_FE 0x0100U /*!< USART frame error interruption */
+#define USART_IT_RXFF 0x183FU /*!< USART RXFIFO full interruption */
+#define USART_IT_TXFE 0x173EU /*!< USART TXFIFO empty interruption */
+#define USART_IT_RXFT 0x1A7CU /*!< USART RXFIFO threshold reached interruption */
+#define USART_IT_TXFT 0x1B77U /*!< USART TXFIFO threshold reached interruption */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_IT_CLEAR_Flags USART Interruption Clear Flags
+ * @{
+ */
+#define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
+#define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
+#define USART_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */
+#define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
+#define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
+#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
+#define USART_CLEAR_UDRF USART_ICR_UDRCF /*!< SPI slave underrun error Clear Flag */
+#define USART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO Empty Clear Flag */
+#define USART_CLEAR_RTOF USART_ICR_RTOCF /*!< USART receiver timeout clear flag */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Interruption_Mask USART Interruption Flags Mask
+ * @{
+ */
+#define USART_IT_MASK 0x001FU /*!< USART interruptions flags mask */
+#define USART_CR_MASK 0x00E0U /*!< USART control register mask */
+#define USART_CR_POS 5U /*!< USART control register position */
+#define USART_ISR_MASK 0x1F00U /*!< USART ISR register mask */
+#define USART_ISR_POS 8U /*!< USART ISR register position */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup USART_Exported_Macros USART Exported Macros
+ * @{
+ */
+
+/** @brief Reset USART handle state.
+ * @param __HANDLE__ USART handle.
+ * @retval None
+ */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_USART_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0U)
+#else
+#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+
+/** @brief Check whether the specified USART flag is set or not.
+ * @param __HANDLE__ specifies the USART Handle
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref USART_FLAG_TXFT TXFIFO threshold flag
+ * @arg @ref USART_FLAG_RXFT RXFIFO threshold flag
+ * @arg @ref USART_FLAG_RXFF RXFIFO Full flag
+ * @arg @ref USART_FLAG_TXFE TXFIFO Empty flag
+ * @arg @ref USART_FLAG_REACK Receive enable acknowledge flag
+ * @arg @ref USART_FLAG_TEACK Transmit enable acknowledge flag
+ * @arg @ref USART_FLAG_BUSY Busy flag
+ * @arg @ref USART_FLAG_UDR SPI slave underrun error flag
+ * @arg @ref USART_FLAG_TXE Transmit data register empty flag
+ * @arg @ref USART_FLAG_TXFNF TXFIFO not full flag
+ * @arg @ref USART_FLAG_TC Transmission Complete flag
+ * @arg @ref USART_FLAG_RXNE Receive data register not empty flag
+ * @arg @ref USART_FLAG_RXFNE RXFIFO not empty flag
+ * @arg @ref USART_FLAG_RTOF Receiver Timeout flag
+ * @arg @ref USART_FLAG_IDLE Idle Line detection flag
+ * @arg @ref USART_FLAG_ORE OverRun Error flag
+ * @arg @ref USART_FLAG_NE Noise Error flag
+ * @arg @ref USART_FLAG_FE Framing Error flag
+ * @arg @ref USART_FLAG_PE Parity Error flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the specified USART pending flag.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag
+ * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag
+ * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag
+ * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag
+ * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
+ * @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag
+ * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
+ * @arg @ref USART_CLEAR_RTOF Receiver Timeout clear flag
+ * @arg @ref USART_CLEAR_UDRF SPI slave underrun error Clear Flag
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief Clear the USART PE pending flag.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)
+
+/** @brief Clear the USART FE pending flag.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)
+
+/** @brief Clear the USART NE pending flag.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)
+
+/** @brief Clear the USART ORE pending flag.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)
+
+/** @brief Clear the USART IDLE pending flag.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)
+
+/** @brief Clear the USART TX FIFO empty clear flag.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_TXFECF(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_TXFECF)
+
+/** @brief Clear SPI slave underrun error flag.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_UDRFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_UDRF)
+
+/** @brief Enable the specified USART interrupt.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @param __INTERRUPT__ specifies the USART interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg @ref USART_IT_RXFF RXFIFO Full interrupt
+ * @arg @ref USART_IT_TXFE TXFIFO Empty interrupt
+ * @arg @ref USART_IT_RXFT RXFIFO threshold interrupt
+ * @arg @ref USART_IT_TXFT TXFIFO threshold interrupt
+ * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref USART_IT_TXFNF TX FIFO not full interrupt
+ * @arg @ref USART_IT_TC Transmission complete interrupt
+ * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt
+ * @arg @ref USART_IT_IDLE Idle line detection interrupt
+ * @arg @ref USART_IT_PE Parity Error interrupt
+ * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)\
+ (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\
+ ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\
+ ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))
+
+/** @brief Disable the specified USART interrupt.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @param __INTERRUPT__ specifies the USART interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg @ref USART_IT_RXFF RXFIFO Full interrupt
+ * @arg @ref USART_IT_TXFE TXFIFO Empty interrupt
+ * @arg @ref USART_IT_RXFT RXFIFO threshold interrupt
+ * @arg @ref USART_IT_TXFT TXFIFO threshold interrupt
+ * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref USART_IT_TXFNF TX FIFO not full interrupt
+ * @arg @ref USART_IT_TC Transmission complete interrupt
+ * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt
+ * @arg @ref USART_IT_IDLE Idle line detection interrupt
+ * @arg @ref USART_IT_PE Parity Error interrupt
+ * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)\
+ (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\
+ ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\
+ ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))
+
+/** @brief Check whether the specified USART interrupt has occurred or not.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @param __INTERRUPT__ specifies the USART interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg @ref USART_IT_RXFF RXFIFO Full interrupt
+ * @arg @ref USART_IT_TXFE TXFIFO Empty interrupt
+ * @arg @ref USART_IT_RXFT RXFIFO threshold interrupt
+ * @arg @ref USART_IT_TXFT TXFIFO threshold interrupt
+ * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref USART_IT_TXFNF TX FIFO not full interrupt
+ * @arg @ref USART_IT_TC Transmission complete interrupt
+ * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt
+ * @arg @ref USART_IT_IDLE Idle line detection interrupt
+ * @arg @ref USART_IT_ORE OverRun Error interrupt
+ * @arg @ref USART_IT_NE Noise Error interrupt
+ * @arg @ref USART_IT_FE Framing Error interrupt
+ * @arg @ref USART_IT_PE Parity Error interrupt
+ * @retval The new state of __INTERRUPT__ (SET or RESET).
+ */
+#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
+ & (0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>>\
+ USART_ISR_POS))) != 0U) ? SET : RESET)
+
+/** @brief Check whether the specified USART interrupt source is enabled or not.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @param __INTERRUPT__ specifies the USART interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg @ref USART_IT_RXFF RXFIFO Full interrupt
+ * @arg @ref USART_IT_TXFE TXFIFO Empty interrupt
+ * @arg @ref USART_IT_RXFT RXFIFO threshold interrupt
+ * @arg @ref USART_IT_TXFT TXFIFO threshold interrupt
+ * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref USART_IT_TXFNF TX FIFO not full interrupt
+ * @arg @ref USART_IT_TC Transmission complete interrupt
+ * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt
+ * @arg @ref USART_IT_IDLE Idle line detection interrupt
+ * @arg @ref USART_IT_ORE OverRun Error interrupt
+ * @arg @ref USART_IT_NE Noise Error interrupt
+ * @arg @ref USART_IT_FE Framing Error interrupt
+ * @arg @ref USART_IT_PE Parity Error interrupt
+ * @retval The new state of __INTERRUPT__ (SET or RESET).
+ */
+#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ?\
+ (__HANDLE__)->Instance->CR1 : \
+ (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ?\
+ (__HANDLE__)->Instance->CR2 : \
+ (__HANDLE__)->Instance->CR3)) & (0x01U <<\
+ (((uint16_t)(__INTERRUPT__)) &\
+ USART_IT_MASK))) != 0U) ? SET : RESET)
+
+/** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
+ * to clear the corresponding interrupt.
+ * This parameter can be one of the following values:
+ * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag
+ * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag
+ * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag
+ * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag
+ * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
+ * @arg @ref USART_CLEAR_RTOF Receiver timeout clear flag
+ * @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag
+ * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+
+/** @brief Set a specific USART request flag.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @param __REQ__ specifies the request flag to set.
+ * This parameter can be one of the following values:
+ * @arg @ref USART_RXDATA_FLUSH_REQUEST Receive Data flush Request
+ * @arg @ref USART_TXDATA_FLUSH_REQUEST Transmit data flush Request
+ *
+ * @retval None
+ */
+#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
+
+/** @brief Enable the USART one bit sample method.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief Disable the USART one bit sample method.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
+
+/** @brief Enable USART.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+
+/** @brief Disable USART.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup USART_Private_Macros USART Private Macros
+ * @{
+ */
+
+/** @brief Get USART clock division factor from clock prescaler value.
+ * @param __CLOCKPRESCALER__ USART prescaler value.
+ * @retval USART clock division factor
+ */
+#define USART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \
+ (((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1) ? 1U : \
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2) ? 2U : \
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4) ? 4U : \
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6) ? 6U : \
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8) ? 8U : \
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10) ? 10U : \
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12) ? 12U : \
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) ? 16U : \
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) ? 32U : \
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) ? 64U : \
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : \
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256) ? 256U : 1U)
+
+/** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
+ * @param __PCLK__ USART clock.
+ * @param __BAUD__ Baud rate set by the user.
+ * @param __CLOCKPRESCALER__ USART prescaler value.
+ * @retval Division result
+ */
+#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)\
+ (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U)\
+ + ((__BAUD__)/2U)) / (__BAUD__))
+
+/** @brief Report the USART clock source.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @param __CLOCKSOURCE__ output variable.
+ * @retval the USART clocking source, written in __CLOCKSOURCE__.
+ */
+#if defined(USART6)
+#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK2: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
+ case RCC_USART3CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART3CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART3CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART3CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART6) \
+ { \
+ switch(__HAL_RCC_GET_USART6_SOURCE()) \
+ { \
+ case RCC_USART6CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART6CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART6CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART6CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0U)
+#else
+#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK2: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
+ case RCC_USART3CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART3CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART3CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART3CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0U)
+#endif /* USART6 */
+
+/** @brief Check USART Baud rate.
+ * @param __BAUDRATE__ Baudrate specified by the user.
+ * The maximum Baud Rate is derived from the maximum clock on U5 (i.e. 160 MHz)
+ * divided by the smallest oversampling used on the USART (i.e. 8)
+ * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) */
+#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 20000000U)
+
+/**
+ * @brief Ensure that USART frame number of stop bits is valid.
+ * @param __STOPBITS__ USART frame number of stop bits.
+ * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
+ */
+#define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_0_5) || \
+ ((__STOPBITS__) == USART_STOPBITS_1) || \
+ ((__STOPBITS__) == USART_STOPBITS_1_5) || \
+ ((__STOPBITS__) == USART_STOPBITS_2))
+
+/**
+ * @brief Ensure that USART frame parity is valid.
+ * @param __PARITY__ USART frame parity.
+ * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+ */
+#define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \
+ ((__PARITY__) == USART_PARITY_EVEN) || \
+ ((__PARITY__) == USART_PARITY_ODD))
+
+/**
+ * @brief Ensure that USART communication mode is valid.
+ * @param __MODE__ USART communication mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
+
+/**
+ * @brief Ensure that USART clock state is valid.
+ * @param __CLOCK__ USART clock state.
+ * @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)
+ */
+#define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \
+ ((__CLOCK__) == USART_CLOCK_ENABLE))
+
+/**
+ * @brief Ensure that USART frame polarity is valid.
+ * @param __CPOL__ USART frame polarity.
+ * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
+ */
+#define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
+
+/**
+ * @brief Ensure that USART frame phase is valid.
+ * @param __CPHA__ USART frame phase.
+ * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
+ */
+#define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
+
+/**
+ * @brief Ensure that USART frame last bit clock pulse setting is valid.
+ * @param __LASTBIT__ USART frame last bit clock pulse setting.
+ * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
+ */
+#define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \
+ ((__LASTBIT__) == USART_LASTBIT_ENABLE))
+
+/**
+ * @brief Ensure that USART request parameter is valid.
+ * @param __PARAM__ USART request parameter.
+ * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+ */
+#define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \
+ ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))
+
+/**
+ * @brief Ensure that USART Prescaler is valid.
+ * @param __CLOCKPRESCALER__ USART Prescaler value.
+ * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
+ */
+#define IS_USART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1) || \
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2) || \
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4) || \
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6) || \
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8) || \
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10) || \
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12) || \
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) || \
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) || \
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) || \
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) || \
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256))
+
+/**
+ * @}
+ */
+
+/* Include USART HAL Extended module */
+#include "stm32u5xx_hal_usart_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup USART_Exported_Functions USART Exported Functions
+ * @{
+ */
+
+/** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
+void HAL_USART_MspInit(USART_HandleTypeDef *husart);
+void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID,
+ pUSART_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size);
+HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart);
+
+void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
+void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
+void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart);
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Exported_Functions_Group4 Peripheral State and Error functions
+ * @{
+ */
+
+/* Peripheral State and Error functions ***************************************/
+HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
+uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_USART_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_usart_ex.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_usart_ex.h
new file mode 100644
index 00000000..de0480fb
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_usart_ex.h
@@ -0,0 +1,393 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_usart_ex.h
+ * @author MCD Application Team
+ * @brief Header file of USART HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_USART_EX_H
+#define STM32U5xx_HAL_USART_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup USARTEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup USARTEx_Exported_Types USARTEx Exported Types
+ * @{
+ */
+/**
+ * @brief USART Autonomous mode parameters
+ */
+typedef struct
+{
+ uint32_t AutonomousModeState; /*!< Specifies the autonomous mode state.This parameter can be a value of
+ @ref USARTEx_Autonomous_mode.*/
+
+ uint32_t TriggerSelection; /*!< Specifies which trigger will activate the Transmission automatically.
+ This parameter can be a value of @ref USARTEx_Autonomous_Trigger_selection */
+
+ uint32_t TriggerPolarity; /*!< Specifies the autonomous mode trigger signal polarity.
+ This parameter can be a value of @ref USARTEx_Autonomous_Trigger_Polarity */
+
+ uint32_t DataSize; /*!< Specifies the transmitted data size in byte */
+
+ uint32_t IdleFrame; /*!< Specifies whether the IDLE frame transmission is enabled or disabled.
+ This parameter can be a value of @ref USARTEx_Autonomous_IDLE_FRAME. */
+
+} USART_AutonomousModeConfTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants
+ * @{
+ */
+
+/** @defgroup USARTEx_Word_Length USARTEx Word Length
+ * @{
+ */
+#define USART_WORDLENGTH_7B (USART_CR1_M1) /*!< 7-bit long USART frame */
+#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
+#define USART_WORDLENGTH_9B (USART_CR1_M0) /*!< 9-bit long USART frame */
+/**
+ * @}
+ */
+
+/** @defgroup USARTEx_Slave_Select_management USARTEx Slave Select Management
+ * @{
+ */
+#define USART_NSS_HARD 0x00000000U /*!< SPI slave selection depends on NSS input pin */
+#define USART_NSS_SOFT USART_CR2_DIS_NSS /*!< SPI slave is always selected and NSS input pin is ignored */
+/**
+ * @}
+ */
+
+
+/** @defgroup USARTEx_Slave_Mode USARTEx Synchronous Slave mode enable
+ * @brief USART SLAVE mode
+ * @{
+ */
+#define USART_SLAVEMODE_DISABLE 0x00000000U /*!< USART SPI Slave Mode Enable */
+#define USART_SLAVEMODE_ENABLE USART_CR2_SLVEN /*!< USART SPI Slave Mode Disable */
+/**
+ * @}
+ */
+
+/** @defgroup USARTEx_FIFO_mode USARTEx FIFO mode
+ * @brief USART FIFO mode
+ * @{
+ */
+#define USART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */
+#define USART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */
+/**
+ * @}
+ */
+
+/** @defgroup USARTEx_TXFIFO_threshold_level USARTEx TXFIFO threshold level
+ * @brief USART TXFIFO level
+ * @{
+ */
+#define USART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */
+#define USART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */
+#define USART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */
+#define USART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */
+#define USART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */
+#define USART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */
+/**
+ * @}
+ */
+
+/** @defgroup USARTEx_RXFIFO_threshold_level USARTEx RXFIFO threshold level
+ * @brief USART RXFIFO level
+ * @{
+ */
+#define USART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */
+#define USART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RXFIFO FIFO reaches 1/4 of its depth */
+#define USART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RXFIFO FIFO reaches 1/2 of its depth */
+#define USART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */
+#define USART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RXFIFO FIFO reaches 7/8 of its depth */
+#define USART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full */
+/**
+ * @}
+ */
+
+/** @defgroup USARTEx_Autonomous_mode USARTEx Autonomous Mode
+ * @brief USART Autonomous mode
+ * @{
+ */
+#define USART_AUTONOMOUS_MODE_DISABLE 0x00000000U /*!< Autonomous mode disable */
+#define USART_AUTONOMOUS_MODE_ENABLE USART_AUTOCR_TRIGEN /*!< Autonomous mode enable */
+/**
+ * @}
+ */
+
+/** @defgroup USARTEx_Autonomous_Trigger_Polarity USARTEx Autonomous Trigger Polarity
+ * @brief USART Trigger polarity edge selection
+ * @{
+ */
+#define USART_TRIG_POLARITY_RISING 0x00000000U /*!< USART triggered on rising edge */
+#define USART_TRIG_POLARITY_FALLING USART_AUTOCR_TRIGPOL /*!< USART triggered on falling edge */
+/**
+ * @}
+ */
+
+/** @defgroup USARTEx_Autonomous_IDLE_FRAME USARTEx Autonomous IDLE Frame
+ * @brief USART IDLE frame transmission
+ * @{
+ */
+#define USART_IDLE_FRAME_ENABLE 0x00000000U /*!< IDLE Frame sent after enabling the transmitter */
+#define USART_IDLE_FRAME_DISABLE USART_AUTOCR_IDLEDIS /*!< IDLE Frame not sent after enabling the transmitter */
+/**
+ * @}
+ */
+
+/** @defgroup USARTEx_Autonomous_Trigger_selection USARTEx Autonomous trigger selection
+ * @brief USART Autonomous Trigger selection
+ * @{
+ */
+#define USART_GPDMA1_CH0_TCF_TRG 0U /*!< USART GPDMA1 channel0 Internal Trigger */
+#define USART_GPDMA1_CH1_TCF_TRG 1U /*!< USART GPDMA1 channel1 Internal Trigger */
+#define USART_GPDMA1_CH2_TCF_TRG 2U /*!< USART GPDMA1 channel2 Internal Trigger */
+#define USART_GPDMA1_CH3_TCF_TRG 3U /*!< USART GPDMA1 channel3 Internal Trigger */
+#define USART_EXTI_LINE6_TRG 4U /*!< USART EXTI line 6 Internal Trigger */
+#define USART_EXTI_LINE9_TRG 5U /*!< USART EXTI line 9 Internal Trigger */
+#define USART_LPTIM1_OUT_TRG 6U /*!< USART LPTIM1 out Internal Trigger */
+#define USART_LPTIM2_OUT_TRG 7U /*!< USART LPTIM2 out Internal Trigger */
+#define USART_COMP1_OUT_TRG 8U /*!< USART COMP1 out Internal Trigger */
+#define USART_COMP2_OUT_TRG 9U /*!< USART COMP2 out Internal Trigger */
+#define USART_RTC_ALRA_TRG 10U /*!< USART RTC alarm Internal Trigger */
+#define USART_RTC_WUT_TRG 11U /*!< USART RTC wakeup Internal Trigger */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup USARTEx_Private_Macros USARTEx Private Macros
+ * @{
+ */
+
+/** @brief Compute the USART mask to apply to retrieve the received data
+ * according to the word length and to the parity bits activation.
+ * @note If PCE = 1, the parity bit is not included in the data extracted
+ * by the reception API().
+ * This masking operation is not carried out in the case of
+ * DMA transfers.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field.
+ */
+#define USART_MASK_COMPUTATION(__HANDLE__) \
+ do { \
+ if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x01FFU; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x00FFU; \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x00FFU; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x007FU; \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x007FU; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x003FU; \
+ } \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x0000U; \
+ } \
+ } while(0U)
+
+/**
+ * @brief Ensure that USART frame length is valid.
+ * @param __LENGTH__ USART frame length.
+ * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+ */
+#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \
+ ((__LENGTH__) == USART_WORDLENGTH_8B) || \
+ ((__LENGTH__) == USART_WORDLENGTH_9B))
+
+/**
+ * @brief Ensure that USART Negative Slave Select (NSS) pin management is valid.
+ * @param __NSS__ USART Negative Slave Select pin management.
+ * @retval SET (__NSS__ is valid) or RESET (__NSS__ is invalid)
+ */
+#define IS_USART_NSS(__NSS__) (((__NSS__) == USART_NSS_HARD) || \
+ ((__NSS__) == USART_NSS_SOFT))
+
+/**
+ * @brief Ensure that USART Slave Mode is valid.
+ * @param __STATE__ USART Slave Mode.
+ * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
+ */
+#define IS_USART_SLAVEMODE(__STATE__) (((__STATE__) == USART_SLAVEMODE_DISABLE ) || \
+ ((__STATE__) == USART_SLAVEMODE_ENABLE))
+
+/**
+ * @brief Ensure that USART FIFO mode is valid.
+ * @param __STATE__ USART FIFO mode.
+ * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
+ */
+#define IS_USART_FIFO_MODE_STATE(__STATE__) (((__STATE__) == USART_FIFOMODE_DISABLE ) || \
+ ((__STATE__) == USART_FIFOMODE_ENABLE))
+
+/**
+ * @brief Ensure that USART TXFIFO threshold level is valid.
+ * @param __THRESHOLD__ USART TXFIFO threshold level.
+ * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
+ */
+#define IS_USART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_8) || \
+ ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_4) || \
+ ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_2) || \
+ ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_3_4) || \
+ ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_7_8) || \
+ ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_8_8))
+
+/**
+ * @brief Ensure that USART RXFIFO threshold level is valid.
+ * @param __THRESHOLD__ USART RXFIFO threshold level.
+ * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
+ */
+#define IS_USART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_8) || \
+ ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_4) || \
+ ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_2) || \
+ ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_3_4) || \
+ ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_7_8) || \
+ ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_8_8))
+/**
+ * @brief Ensure that USART Trigger polarity state is valid.
+ * @param __POLARITY__ USART Trigger polarity.
+ * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)
+ */
+#define IS_USART_TRIGGER_POLARITY(__POLARITY__) (((__POLARITY__) == USART_TRIG_POLARITY_RISING) ||\
+ ((__POLARITY__) == USART_TRIG_POLARITY_FALLING))
+
+/**
+ * @brief Ensure that USART IDLE Frame Transmit state is valid.
+ * @param __IDLE__ USART IDLE Frame Transmit state.
+ * @retval SET (__IDLE__ is valid) or RESET (__IDLE__ is invalid)
+ */
+#define IS_USART_IDLE_FRAME_TRANSMIT(__IDLE__) (((__IDLE__) == USART_IDLE_FRAME_ENABLE) ||\
+ ((__IDLE__) == USART_IDLE_FRAME_DISABLE))
+
+/**
+ * @brief Ensure that USART Trigger source selection is valid.
+ * @param __SOURCE__ USART Trigger source selection.
+ * @retval SET (__SOURCE__ is valid) or RESET (__SOURCE__ is invalid)
+ */
+#define IS_USART_TRIGGER_SELECTION(__SOURCE__) ((__SOURCE__) <= 11U)
+
+/**
+ * @brief Ensure that the number of transferred data is valid.
+ * @param __SOURCE__ USART TX data size.
+ * @retval SET (__SOURCE__ is valid) or RESET (__SOURCE__ is invalid)
+ */
+#define IS_USART_TX_DATA_SIZE(__SOURCE__) ((__SOURCE__) <= 0xFFFFU)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup USARTEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup USARTEx_Exported_Functions_Group1
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+void HAL_USARTEx_RxFifoFullCallback(USART_HandleTypeDef *husart);
+void HAL_USARTEx_TxFifoEmptyCallback(USART_HandleTypeDef *husart);
+
+/**
+ * @}
+ */
+
+/** @addtogroup USARTEx_Exported_Functions_Group2
+ * @{
+ */
+
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig);
+HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold);
+HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold);
+HAL_StatusTypeDef HAL_USARTEx_SetConfigAutonomousMode(USART_HandleTypeDef *husart,
+ USART_AutonomousModeConfTypeDef *sConfig);
+HAL_StatusTypeDef HAL_USARTEx_GetConfigAutonomousMode(USART_HandleTypeDef *husart,
+ USART_AutonomousModeConfTypeDef *sConfig);
+HAL_StatusTypeDef HAL_USARTEx_ClearConfigAutonomousMode(USART_HandleTypeDef *husart);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_USART_EX_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_wwdg.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_wwdg.h
new file mode 100644
index 00000000..4efca69d
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_wwdg.h
@@ -0,0 +1,307 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_wwdg.h
+ * @author MCD Application Team
+ * @brief Header file of WWDG HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_WWDG_H
+#define STM32U5xx_HAL_WWDG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup WWDG
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Types WWDG Exported Types
+ * @{
+ */
+
+/**
+ * @brief WWDG Init structure definition
+ */
+typedef struct
+{
+ uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG.
+ This parameter can be a value of @ref WWDG_Prescaler */
+
+ uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter.
+ This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */
+
+ uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value.
+ This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
+
+ uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interrupt is enable or not.
+ This parameter can be a value of @ref WWDG_EWI_Mode */
+
+} WWDG_InitTypeDef;
+
+/**
+ * @brief WWDG handle Structure definition
+ */
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+typedef struct __WWDG_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
+{
+ WWDG_TypeDef *Instance; /*!< Register base address */
+
+ WWDG_InitTypeDef Init; /*!< WWDG required parameters */
+
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+ void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */
+
+ void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
+} WWDG_HandleTypeDef;
+
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL WWDG common Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_WWDG_EWI_CB_ID = 0x00U, /*!< WWDG EWI callback ID */
+ HAL_WWDG_MSPINIT_CB_ID = 0x01U, /*!< WWDG MspInit callback ID */
+} HAL_WWDG_CallbackIDTypeDef;
+
+/**
+ * @brief HAL WWDG Callback pointer definition
+ */
+typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer to a WWDG common callback functions */
+
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Constants WWDG Exported Constants
+ * @{
+ */
+
+/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
+ * @{
+ */
+#define WWDG_IT_EWI WWDG_CFR_EWI /*!< Early wakeup interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Flag_definition WWDG Flag definition
+ * @brief WWDG Flag definition
+ * @{
+ */
+#define WWDG_FLAG_EWIF WWDG_SR_EWIF /*!< Early wakeup interrupt flag */
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Prescaler WWDG Prescaler
+ * @{
+ */
+#define WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */
+#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
+#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
+#define WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/8 */
+#define WWDG_PRESCALER_16 WWDG_CFR_WDGTB_2 /*!< WWDG counter clock = (PCLK1/4096)/16 */
+#define WWDG_PRESCALER_32 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/32 */
+#define WWDG_PRESCALER_64 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/64 */
+#define WWDG_PRESCALER_128 WWDG_CFR_WDGTB /*!< WWDG counter clock = (PCLK1/4096)/128 */
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode
+ * @{
+ */
+#define WWDG_EWI_DISABLE 0x00000000u /*!< EWI Disable */
+#define WWDG_EWI_ENABLE WWDG_CFR_EWI /*!< EWI Enable */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup WWDG_Private_Macros WWDG Private Macros
+ * @{
+ */
+#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
+ ((__PRESCALER__) == WWDG_PRESCALER_2) || \
+ ((__PRESCALER__) == WWDG_PRESCALER_4) || \
+ ((__PRESCALER__) == WWDG_PRESCALER_8) || \
+ ((__PRESCALER__) == WWDG_PRESCALER_16) || \
+ ((__PRESCALER__) == WWDG_PRESCALER_32) || \
+ ((__PRESCALER__) == WWDG_PRESCALER_64) || \
+ ((__PRESCALER__) == WWDG_PRESCALER_128))
+
+#define IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
+
+#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
+
+#define IS_WWDG_EWI_MODE(__MODE__) (((__MODE__) == WWDG_EWI_ENABLE) || \
+ ((__MODE__) == WWDG_EWI_DISABLE))
+/**
+ * @}
+ */
+
+
+/* Exported macros ------------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Macros WWDG Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Enable the WWDG peripheral.
+ * @param __HANDLE__ WWDG handle
+ * @retval None
+ */
+#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
+
+/**
+ * @brief Enable the WWDG early wakeup interrupt.
+ * @param __HANDLE__: WWDG handle
+ * @param __INTERRUPT__ specifies the interrupt to enable.
+ * This parameter can be one of the following values:
+ * @arg WWDG_IT_EWI: Early wakeup interrupt
+ * @note Once enabled this interrupt cannot be disabled except by a system reset.
+ * @retval None
+ */
+#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
+
+/**
+ * @brief Check whether the selected WWDG interrupt has occurred or not.
+ * @param __HANDLE__ WWDG handle
+ * @param __INTERRUPT__ specifies the it to check.
+ * This parameter can be one of the following values:
+ * @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
+ * @retval The new state of WWDG_FLAG (SET or RESET).
+ */
+#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
+
+/** @brief Clear the WWDG interrupt pending bits.
+ * bits to clear the selected interrupt pending bits.
+ * @param __HANDLE__ WWDG handle
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
+ * This parameter can be one of the following values:
+ * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
+ */
+#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified WWDG flag is set or not.
+ * @param __HANDLE__ WWDG handle
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
+ * @retval The new state of WWDG_FLAG (SET or RESET).
+ */
+#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clear the WWDG's pending flags.
+ * @param __HANDLE__ WWDG handle
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be one of the following values:
+ * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
+ * @retval None
+ */
+#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+
+/** @brief Check whether the specified WWDG interrupt source is enabled or not.
+ * @param __HANDLE__ WWDG Handle.
+ * @param __INTERRUPT__ specifies the WWDG interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg WWDG_IT_EWI: Early Wakeup Interrupt
+ * @retval state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR\
+ & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup WWDG_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup WWDG_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
+void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID,
+ pWWDG_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Exported_Functions_Group2
+ * @{
+ */
+/* I/O operation functions ******************************************************/
+HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);
+void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
+void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_WWDG_H */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_adc.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_adc.h
new file mode 100644
index 00000000..2918a1d1
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_adc.h
@@ -0,0 +1,8905 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_adc.h
+ * @author MCD Application Team
+ * @brief Header file of ADC LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_LL_ADC_H
+#define STM32U5xx_LL_ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx.h"
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined (ADC1) || defined (ADC2) || defined (ADC4)
+
+/** @defgroup ADC_LL ADC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup ADC_LL_Private_Constants ADC Private Constants
+ * @{
+ */
+
+/* Internal mask for ADC calibration: */
+/* Internal register offset for ADC calibration factors configuration */
+
+/* To select into literals LL_ADC_CALIB_OFFSET, LL_ADC_CALIB_LINEARITY, ... */
+/* the relevant bits for: */
+/* (concatenation of multiple bits used in different registers) */
+/* - ADC calibration configuration: configuration before calibration start */
+/* - ADC calibration factors: register offset */
+#define ADC_CALIB_FACTOR_OFFSET_REGOFFSET (0x00000000UL) /* Register CALFACT defined as reference register */
+#define ADC_CALIB_FACTOR_LINEARITY_REGOFFSET (0x00000001UL) /* Register CALFACT2 offset vs register CALFACT */
+#define ADC_CALIB_FACTOR_REGOFFSET_MASK (ADC_CALIB_FACTOR_OFFSET_REGOFFSET | ADC_CALIB_FACTOR_LINEARITY_REGOFFSET)
+#define ADC_CALIB_MODE_MASK (ADC_CR_ADCALLIN)
+#define ADC_CALIB_MODE_BINARY_MASK (ADC_CALIB_FACTOR_REGOFFSET_MASK) /* Mask to get binary value of
+ calibration mode: 0 for offset,
+ 1 for linearity */
+
+
+/* Internal mask for ADC group regular sequencer: */
+/* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
+/* - sequencer register offset */
+/* - sequencer rank bits position into the selected register */
+
+/* Internal register offset for ADC group regular sequencer configuration */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_SQR1_REGOFFSET (0x00000000UL)
+#define ADC_SQR2_REGOFFSET (0x00000100UL)
+#define ADC_SQR3_REGOFFSET (0x00000200UL)
+#define ADC_SQR4_REGOFFSET (0x00000300UL)
+
+#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET\
+ | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
+#define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */
+#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
+
+/* Definition of ADC group regular sequencer bits information to be inserted */
+/* into ADC group regular sequencer ranks literals definition. */
+#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_SQR1_SQ1" position in register */
+#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_SQR1_SQ2" position in register */
+#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC_SQR1_SQ3" position in register */
+#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC_SQR1_SQ4" position in register */
+#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_SQR2_SQ5" position in register */
+#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_SQR2_SQ6" position in register */
+#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_SQR2_SQ7" position in register */
+#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC_SQR2_SQ8" position in register */
+#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC_SQR2_SQ9" position in register */
+#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_SQR3_SQ10" position in register */
+#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_SQR3_SQ11" position in register */
+#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_SQR3_SQ12" position in register */
+#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC_SQR3_SQ13" position in register */
+#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC_SQR3_SQ14" position in register */
+#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_SQR4_SQ15" position in register */
+#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_SQR4_SQ16" position in register */
+
+#define ADC4_REG_RANK_1_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC4_CHSELR_SQ1" position in register */
+#define ADC4_REG_RANK_2_SQRX_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC4_CHSELR_SQ2" position in register */
+#define ADC4_REG_RANK_3_SQRX_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC4_CHSELR_SQ3" position in register */
+#define ADC4_REG_RANK_4_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC4_CHSELR_SQ4" position in register */
+#define ADC4_REG_RANK_5_SQRX_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC4_CHSELR_SQ5" position in register */
+#define ADC4_REG_RANK_6_SQRX_BITOFFSET_POS (20UL) /* Equivalent to bitfield "ADC4_CHSELR_SQ6" position in register */
+#define ADC4_REG_RANK_7_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC4_CHSELR_SQ7" position in register */
+#define ADC4_REG_RANK_8_SQRX_BITOFFSET_POS (28UL) /* Equivalent to bitfield "ADC4_CHSELR_SQ8" position in register */
+
+/* Internal mask for ADC group injected sequencer: */
+/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
+/* - data register offset */
+/* - sequencer rank bits position into the selected register */
+
+/* Internal register offset for ADC group injected data register */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_JDR1_REGOFFSET (0x00000000UL)
+#define ADC_JDR2_REGOFFSET (0x00000100UL)
+#define ADC_JDR3_REGOFFSET (0x00000200UL)
+#define ADC_JDR4_REGOFFSET (0x00000300UL)
+
+#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET\
+ | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
+#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
+#define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */
+
+/* Definition of ADC group injected sequencer bits information to be inserted */
+/* into ADC group injected sequencer ranks literals definition. */
+#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ1_Pos)
+#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ2_Pos)
+#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ3_Pos)
+#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ4_Pos)
+
+#define ADC_TR1_HT1_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC4_TR1_HT1" position in register */
+#define ADC4_CHSELR_CHSEL0_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL0" position in register */
+#define ADC4_CHSELR_CHSEL1_BITOFFSET_POS ( 1UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL1" position in register */
+#define ADC4_CHSELR_CHSEL2_BITOFFSET_POS ( 2UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL2" position in register */
+#define ADC4_CHSELR_CHSEL3_BITOFFSET_POS ( 3UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL3" position in register */
+#define ADC4_CHSELR_CHSEL4_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL4" position in register */
+#define ADC4_CHSELR_CHSEL5_BITOFFSET_POS ( 5UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL5" position in register */
+#define ADC4_CHSELR_CHSEL6_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL6" position in register */
+#define ADC4_CHSELR_CHSEL7_BITOFFSET_POS ( 7UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL7" position in register */
+#define ADC4_CHSELR_CHSEL8_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL8" position in register */
+#define ADC4_CHSELR_CHSEL9_BITOFFSET_POS ( 9UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL9" position in register */
+#define ADC4_CHSELR_CHSEL10_BITOFFSET_POS (10UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL10" position in register */
+#define ADC4_CHSELR_CHSEL11_BITOFFSET_POS (11UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL11" position in register */
+#define ADC4_CHSELR_CHSEL12_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL12" position in register */
+#define ADC4_CHSELR_CHSEL13_BITOFFSET_POS (13UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL13" position in register */
+#define ADC4_CHSELR_CHSEL14_BITOFFSET_POS (14UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL14" position in register */
+#define ADC4_CHSELR_CHSEL15_BITOFFSET_POS (15UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL15" position in register */
+#define ADC4_CHSELR_CHSEL16_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL16" position in register */
+#define ADC4_CHSELR_CHSEL17_BITOFFSET_POS (17UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL17" position in register */
+#define ADC4_CHSELR_CHSEL18_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL18" position in register */
+#define ADC4_CHSELR_CHSEL19_BITOFFSET_POS (19UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL19" position in register */
+#define ADC4_CHSELR_CHSEL20_BITOFFSET_POS (20UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL20" position in register */
+#define ADC4_CHSELR_CHSEL21_BITOFFSET_POS (21UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL21" position in register */
+#define ADC4_CHSELR_CHSEL22_BITOFFSET_POS (22UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL22" position in register */
+#define ADC4_CHSELR_CHSEL23_BITOFFSET_POS (23UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL23" position in register */
+#define ADC4_SMPR_SMP1_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC4_SMPR_SMP1" position in register */
+#define ADC4_SMPR_SMP2_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC4_SMPR_SMP2" position in register */
+#define ADC4_SMPR_SMPSEL0_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC4_SMPR_SMPSEL0" position in register */
+
+/* Internal mask for ADC group regular trigger: */
+/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
+/* - regular trigger source */
+/* - regular trigger edge */
+#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting
+ for compatibility with some ADC on other STM32
+ families having this setting set by HW default value) */
+
+/* Mask containing trigger source masks for each of possible */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
+#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTSEL) << (4U * 0UL)) | \
+ ((ADC_CFGR1_EXTSEL) << (4U * 1UL)) | \
+ ((ADC_CFGR1_EXTSEL) << (4U * 2UL)) | \
+ ((ADC_CFGR1_EXTSEL) << (4U * 3UL)) )
+
+#define ADC4_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC4_CFGR1_EXTSEL) << (4U * 0UL)) | \
+ ((ADC4_CFGR1_EXTSEL) << (4U * 1UL)) | \
+ ((ADC4_CFGR1_EXTSEL) << (4U * 2UL)) | \
+ ((ADC4_CFGR1_EXTSEL) << (4U * 3UL)) )
+
+/* Mask containing trigger edge masks for each of possible */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
+#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN) << (4U * 0UL)) | \
+ ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
+ ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
+ ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
+
+/* Definition of ADC group regular trigger bits information. */
+#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_CFGR1_EXTSEL"
+ position in register */
+#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Value equivalent to bitfield "ADC_CFGR1_EXTEN"
+ position in register */
+
+/* Internal mask for ADC group injected trigger: */
+/* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
+/* - injected trigger source */
+/* - injected trigger edge */
+#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for
+ compatibility with some ADC on other STM32 families
+ having this setting set by HW default value) */
+
+/* Mask containing trigger source masks for each of possible */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
+#define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \
+ ((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | \
+ ((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \
+ ((ADC_JSQR_JEXTSEL) << (4U * 3UL)) )
+
+/* Mask containing trigger edge masks for each of possible */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
+#define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \
+ ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
+ ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
+ ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
+
+/* Definition of ADC group injected trigger bits information. */
+#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ( 2UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTSEL"
+ position in register */
+#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTEN"
+ position in register */
+
+/* Internal mask for ADC channel: */
+/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
+/* - channel identifier defined by number */
+/* - channel identifier defined by bitfield */
+/* - channel differentiation between external channels (connected to */
+/* GPIO pins) and internal channels (connected to internal paths) */
+/* - channel sampling time defined by SMPRx register offset */
+/* and SMPx bits positions into SMPRx register */
+#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR1_AWD1CH)
+#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
+#define ADC_CHANNEL_ID_OFFSET_NUMBER_MASK (ADC_OFR1_OFFSET1_CH)
+#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL) /* Value equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK"
+ position in register */
+#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK \
+ | ADC_CHANNEL_ID_INTERNAL_CH_MASK) /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK
+ aligned on register LSB (bit 0) */
+#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >>
+ [Position of bitfield "ADC_CHANNEL_NUMBER_MASK"
+ in register]) */
+
+/* Channel differentiation between external and internal channels */
+#define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
+#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH)
+
+/* Internal register offset for ADC channel sampling time configuration */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_SMPR1_REGOFFSET (0x00000000UL)
+#define ADC_SMPR2_REGOFFSET (0x02000000UL)
+#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
+#define ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in
+ ADC_CHANNEL_SMPRX_REGOFFSET_MASK */
+
+#define ADC4_CHANNEL_ID_BITFIELD_MASK (ADC_CHSELR_CHSEL)
+#define ADC4_SAMPLING_TIME_CH_MASK (ADC4_CHANNEL_ID_BITFIELD_MASK << ADC4_SMPR_SMPSEL0_BITOFFSET_POS)
+#define ADC4_CHANNEL_ID_NUMBER_MASK_SEQ (ADC_CHSELR_SQ1 \
+ << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) /* Value equivalent to
+ ADC_CHANNEL_ID_NUMBER_MASK with
+ reduced range: on this STM32 series,
+ ADC group regular sequencer, if set
+ to mode "fully configurable", can
+ contain channels with a restricted
+ channel number. */
+
+/* Definition of channels ID number information to be inserted into */
+/* channels literals definition. */
+#define ADC_CHANNEL_0_NUMBER (0x00000000UL)
+#define ADC_CHANNEL_1_NUMBER (ADC_CFGR1_AWD1CH_0)
+#define ADC_CHANNEL_2_NUMBER (ADC_CFGR1_AWD1CH_1)
+#define ADC_CHANNEL_3_NUMBER (ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
+#define ADC_CHANNEL_4_NUMBER (ADC_CFGR1_AWD1CH_2)
+#define ADC_CHANNEL_5_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
+#define ADC_CHANNEL_6_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
+#define ADC_CHANNEL_7_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
+#define ADC_CHANNEL_8_NUMBER (ADC_CFGR1_AWD1CH_3)
+#define ADC_CHANNEL_9_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_0)
+#define ADC_CHANNEL_10_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1)
+#define ADC_CHANNEL_11_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
+#define ADC_CHANNEL_12_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2)
+#define ADC_CHANNEL_13_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
+#define ADC_CHANNEL_14_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
+#define ADC_CHANNEL_15_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
+#define ADC_CHANNEL_16_NUMBER (ADC_CFGR1_AWD1CH_4)
+#define ADC_CHANNEL_17_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_0)
+#define ADC_CHANNEL_18_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_1)
+#define ADC_CHANNEL_19_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
+#if defined(ADC4)
+#define ADC_CHANNEL_20_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_2 )
+#define ADC_CHANNEL_21_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
+#define ADC_CHANNEL_22_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
+#define ADC_CHANNEL_23_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
+#endif /* ADC4 */
+/* Definition of channels ID bitfield information to be inserted into */
+/* channels literals definition. */
+#define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
+#define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
+#define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
+#define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
+#define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
+#define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
+#define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
+#define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
+#define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
+#define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
+#define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
+#define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
+#define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
+#define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
+#define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
+#define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
+#define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
+#define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
+#define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
+#define ADC_CHANNEL_19_BITFIELD (ADC_AWD2CR_AWD2CH_19)
+#define ADC_CHANNEL_20_BITFIELD (ADC_AWD2CR_AWD2CH_20)
+#define ADC_CHANNEL_21_BITFIELD (ADC_AWD2CR_AWD2CH_21)
+#define ADC_CHANNEL_22_BITFIELD (ADC_AWD2CR_AWD2CH_22)
+#define ADC_CHANNEL_23_BITFIELD (ADC_AWD2CR_AWD2CH_23)
+
+#define ADC4_CHANNEL_0_BITFIELD (ADC_CHSELR_CHSEL0)
+#define ADC4_CHANNEL_1_BITFIELD (ADC_CHSELR_CHSEL1)
+#define ADC4_CHANNEL_2_BITFIELD (ADC_CHSELR_CHSEL2)
+#define ADC4_CHANNEL_3_BITFIELD (ADC_CHSELR_CHSEL3)
+#define ADC4_CHANNEL_4_BITFIELD (ADC_CHSELR_CHSEL4)
+#define ADC4_CHANNEL_5_BITFIELD (ADC_CHSELR_CHSEL5)
+#define ADC4_CHANNEL_6_BITFIELD (ADC_CHSELR_CHSEL6)
+#define ADC4_CHANNEL_7_BITFIELD (ADC_CHSELR_CHSEL7)
+#define ADC4_CHANNEL_8_BITFIELD (ADC_CHSELR_CHSEL8)
+#define ADC4_CHANNEL_9_BITFIELD (ADC_CHSELR_CHSEL9)
+#define ADC4_CHANNEL_10_BITFIELD (ADC_CHSELR_CHSEL10)
+#define ADC4_CHANNEL_11_BITFIELD (ADC_CHSELR_CHSEL11)
+#define ADC4_CHANNEL_12_BITFIELD (ADC_CHSELR_CHSEL12)
+#define ADC4_CHANNEL_13_BITFIELD (ADC_CHSELR_CHSEL13)
+#define ADC4_CHANNEL_14_BITFIELD (ADC_CHSELR_CHSEL14)
+#define ADC4_CHANNEL_15_BITFIELD (ADC_CHSELR_CHSEL15)
+#define ADC4_CHANNEL_16_BITFIELD (ADC_CHSELR_CHSEL16)
+#define ADC4_CHANNEL_17_BITFIELD (ADC_CHSELR_CHSEL17)
+#define ADC4_CHANNEL_18_BITFIELD (ADC_CHSELR_CHSEL18)
+#define ADC4_CHANNEL_19_BITFIELD (ADC_CHSELR_CHSEL19)
+#define ADC4_CHANNEL_20_BITFIELD (ADC_CHSELR_CHSEL20)
+#define ADC4_CHANNEL_21_BITFIELD (ADC_CHSELR_CHSEL21)
+#define ADC4_CHANNEL_22_BITFIELD (ADC_CHSELR_CHSEL22)
+#define ADC4_CHANNEL_23_BITFIELD (ADC_CHSELR_CHSEL23)
+
+/* Definition of channels sampling time information to be inserted into */
+/* channels literals definition. */
+#define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP0" register */
+#define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP1" register */
+#define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP2" register */
+#define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP3" register */
+#define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP4" register */
+#define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP5" register */
+#define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP6" register */
+#define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP7" register */
+#define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP8" register */
+#define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP9" register */
+#define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP10" register */
+#define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP11" register */
+#define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP12" register */
+#define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP13" register */
+#define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP14" register */
+#define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP15" register */
+#define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP16" register */
+#define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP17" register */
+#define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP18" register */
+#define ADC_CHANNEL_19_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP19" register */
+#define ADC_CHANNEL_20_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP20" register */
+#define ADC_CHANNEL_21_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP21" register */
+#define ADC_CHANNEL_22_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP22" register */
+#define ADC_CHANNEL_23_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP23" register */
+
+/* Internal mask for ADC mode single or differential ended: */
+/* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */
+/* the relevant bits for: */
+/* (concatenation of multiple bits used in different registers) */
+/* - ADC calibration: calibration start, calibration factor get or set */
+/* - ADC channels: set each ADC channel ending mode */
+#define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT2_CALFACT)
+#define ADC_CALFACT2_CALFACT_S (0x0000FFFFUL)
+#define ADC_CALFACT2_CALFACT_D (0xFFFF0000UL)
+#define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
+#define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_I_APB_ADDR_4 \
+ | ADC_CALFACT_I_APB_ADDR_3) /* Bits chosen to perform of shift when single
+ mode is selected, shift value out of
+ channels bits range. */
+#define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000UL) /* Selection of 1 bit to discriminate differential mode:
+ mask of bit */
+#define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16UL) /* Selection of 1 bit to discriminate differential mode:
+ position of bit */
+#define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit
+ ADC_SINGLEDIFF_CALIB_F_BIT_D
+ to position to perform a shift
+ of 4 ranks */
+
+/* Internal mask for ADC analog watchdog: */
+/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
+/* (concatenation of multiple bits used in different analog watchdogs, */
+/* (feature of several watchdogs not available on all STM32 families)). */
+/* - analog watchdog 1: monitored channel defined by number, */
+/* selection of ADC group (ADC groups regular and-or injected). */
+/* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */
+/* selection on groups. */
+
+/* Internal register offset for ADC analog watchdog channel configuration */
+#define ADC_AWD_CR1_REGOFFSET (0x00000000UL)
+#define ADC_AWD_CR2_REGOFFSET (0x01000000UL)
+#define ADC_AWD_CR3_REGOFFSET (0x02000000UL)
+
+/* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
+/* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
+#define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
+#define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
+
+#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
+
+#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR1_AWD1CH | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
+#define ADC_AWD_CHANNEL_MASK (ADC_CHANNEL_ID_NUMBER_MASK)
+#define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
+#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
+
+#define ADC_AWD_CRX_REGOFFSET_POS (24UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK*/
+
+/* Internal register offset for ADC analog watchdog threshold configuration */
+#define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
+#define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
+#define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
+#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
+#define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_TRx_REGOFFSET in
+ ADC_AWD_TRX_REGOFFSET_MASK */
+
+#define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate
+ threshold high: mask of bit */
+#define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate
+ threshold high: position of bit */
+#define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH
+ to position to perform a shift of 4 ranks */
+#define ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS (20UL)
+
+/* Register offset gap between AWD1 and AWD2-AWD3 thresholds registers */
+/* (Set separately as ADC_AWD_TRX_REGOFFSET to spare 32 bits space */
+#define ADC_AWD_TR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
+#define ADC_AWD_TR12_REGOFFSETGAP_VAL (0x00000022UL)
+
+/* Legacy literals */
+#define LL_ADC_AWD1_TR LL_ADC_AWD1
+#define LL_ADC_AWD2_TR LL_ADC_AWD2
+#define LL_ADC_AWD3_TR LL_ADC_AWD3
+
+/* Internal mask for ADC offset: */
+/* Internal register offset for ADC offset number configuration */
+#define ADC_OFR1_REGOFFSET (0x00000000UL)
+#define ADC_OFR2_REGOFFSET (0x00000001UL)
+#define ADC_OFR3_REGOFFSET (0x00000002UL)
+#define ADC_OFR4_REGOFFSET (0x00000003UL)
+#define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET\
+ | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
+
+/* ADC registers bits positions */
+#define ADC_CFGR_RES_BITOFFSET_POS (ADC_CFGR1_RES_Pos)
+#define ADC_CFGR_AWD1SGL_BITOFFSET_POS (ADC_CFGR1_AWD1SGL_Pos)
+#define ADC_CFGR_AWD1EN_BITOFFSET_POS (ADC_CFGR1_AWD1EN_Pos)
+#define ADC_CFGR_JAWD1EN_BITOFFSET_POS (ADC_CFGR1_JAWD1EN_Pos)
+
+/* ADC registers bits groups */
+#define ADC_CR_BITS_PROPERTY_RS ( ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART \
+ | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs":
+ Software can read as well as set this bit.
+ Writing '0' has no effect on the bit value. */
+
+/* ADC internal channels related definitions */
+/* Internal voltage reference VrefInt */
+#define VREFINT_CAL_ADDR ((uint16_t*) (0x0BFA07A5UL)) /* Internal voltage reference, address of parameter
+ VREFINT_CAL: VrefInt ADC raw data acquired at
+ temperature 30 DegC (tolerance: +-5 DegC),
+ Vref+ = 3.0 V (tolerance: +-10 mV). */
+#define VREFINT_CAL_VREF (3000UL) /* Analog voltage reference (Vref+) value with which
+ VrefInt has been calibrated in production
+ (tolerance: +-10 mV) (unit: mV). */
+/* Temperature sensor */
+#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x0BFA0710UL)) /* Internal temperature sensor, address of parameter
+ TS_CAL1: On STM32U5, temperature sensor ADC raw
+ data acquired at temperature 30 DegC
+ (tolerance: +-5 DegC),Vref+ = 3.0 V
+ (tolerance: +-10 mV). */
+#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x0BFA0742UL)) /* Internal temperature sensor, address of parameter
+ TS_CAL2: On STM32U5, temperature sensor ADC raw
+ data acquired at temperature 110 DegC
+ (tolerance: +-5 DegC), Vref+ = 3.0 V
+ (tolerance: +-10 mV). */
+#define TEMPSENSOR_CAL1_TEMP (30L) /* Internal temperature sensor, temperature at which
+ temperature sensor has been calibrated in
+ production for data into TEMPSENSOR_CAL1_ADDR
+ (tolerance: +-5 DegC) (unit: DegC). */
+#define TEMPSENSOR_CAL2_TEMP (130L) /* Internal temperature sensor, temperature at which
+ temperature sensor has been calibrated in
+ production for data into TEMPSENSOR_CAL2_ADDR
+ (tolerance: +-5 DegC) (unit: DegC). */
+#define TEMPSENSOR_CAL_VREFANALOG (3000UL) /* Analog voltage reference (Vref+) voltage with
+ which temperature sensor has been calibrated in
+ production (+-10 mV) (unit: mV). */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup ADC_LL_Private_Macros ADC Private Macros
+ * @{
+ */
+
+/**
+ * @brief Driver macro reserved for internal use: isolate bits with the
+ * selected mask and shift them to the register LSB
+ * (shift mask on register position bit 0).
+ * @param __BITS__ Bits in register 32 bits
+ * @param __MASK__ Mask in register 32 bits
+ * @retval Bits in register 32 bits
+ */
+#define __ADC_MASK_SHIFT(__BITS__, __MASK__) \
+ (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
+
+/**
+ * @brief Driver macro reserved for internal use: set a pointer to
+ * a register from a register basis from which an offset
+ * is applied.
+ * @param __REG__ Register basis from which the offset is applied.
+ * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
+ * @retval Pointer to register address
+ */
+#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
+ ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
+
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief Structure definition of some features of ADC common parameters
+ * and multimode
+ * (all ADC instances belonging to the same ADC common instance).
+ * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
+ * is conditioned to ADC instances state (all ADC instances
+ * sharing the same ADC common instance):
+ * All ADC instances sharing the same ADC common instance must be
+ * disabled.
+ */
+typedef struct
+{
+ uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
+ This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
+ This feature can be modified afterwards using unitary function
+ @ref LL_ADC_SetCommonClock(). */
+
+} LL_ADC_CommonInitTypeDef;
+
+/**
+ * @brief Structure definition of some features of ADC instance.
+ * @note These parameters have an impact on ADC scope: ADC instance.
+ * Affects both group regular and group injected (availability
+ * of ADC group injected depends on STM32 families).
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Instance .
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ */
+typedef struct
+{
+ uint32_t Resolution; /*!< Set ADC resolution.
+ This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
+ This feature can be modified afterwards using unitary function
+ @ref LL_ADC_SetResolution(). */
+
+ uint32_t LeftBitShift; /*!< Configures the left shifting applied to the final result with or without oversampling.
+ This parameter can be a value of @ref ADC_LL_EC_LEFT_BIT_SHIFT. */
+
+ uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
+ This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
+ This feature can be modified afterwards using unitary function
+ @ref LL_ADC_SetDataAlignment(). */
+
+ uint32_t LowPowerMode; /*!< Set ADC low power mode.
+ This parameter can be a value of @ref ADC_LL_EC_LP_MODE
+ This feature can be modified afterwards using unitary function
+ @ref LL_ADC_SetLowPowerMode(). */
+
+} LL_ADC_InitTypeDef;
+
+/**
+ * @brief Structure definition of some features of ADC group regular.
+ * @note These parameters have an impact on ADC scope: ADC group regular.
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ * (functions with prefix "REG").
+ * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ */
+typedef struct
+{
+ uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start)
+ or from external peripheral (timer event, external interrupt line).
+ This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
+ @note On this STM32 series, setting trigger source to external trigger
+ also set trigger polarity to rising edge (default setting for
+ compatibility with some ADC on other STM32 families having this
+ setting set by HW default value).
+ In case of need to modify trigger edge, use function
+ @ref LL_ADC_REG_SetTriggerEdge().
+ This feature can be modified afterwards using unitary function
+ @ref LL_ADC_REG_SetTriggerSource(). */
+
+ uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
+ This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
+ This feature can be modified afterwards using unitary function
+ @ref LL_ADC_REG_SetSequencerLength(). */
+
+ uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided
+ and scan conversions interrupted every selected number of ranks.
+ This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
+ @note This parameter has an effect only if group regular sequencer is
+ enabled (scan length of 2 ranks or more).
+ This feature can be modified afterwards using unitary function
+ @ref LL_ADC_REG_SetSequencerDiscont(). */
+
+ uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular,
+ whether ADC conversions are performed in single mode (one conversion per
+ trigger) or in continuous mode (after the first trigger, following
+ conversions launched successively automatically).
+ This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
+ Note: It is not possible to enable both ADC group regular continuous
+ mode and discontinuous mode.
+ This feature can be modified afterwards using unitary function
+ @ref LL_ADC_REG_SetContinuousMode(). */
+
+ uint32_t DataTransferMode; /*!< Set ADC group regular conversion data transfer mode: no transfer,
+ transfer by DMA (Limited/Unlimited) or MDF.
+ This parameter can be a value of @ref ADC_LL_EC_REG_DATA_TRANSFER_MODE
+ This feature can be modified afterwards using unitary function
+ @ref LL_ADC_REG_SetDataTransferMode(). */
+
+ uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer
+ by DMA, and DMA requests mode.
+ This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
+ This feature can be modified afterwards using unitary function
+ @ref LL_ADC_REG_SetDMATransfer(). */
+
+ uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
+ data preserved or overwritten.
+ This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
+ This feature can be modified afterwards using unitary function
+ @ref LL_ADC_REG_SetOverrun(). */
+
+} LL_ADC_REG_InitTypeDef;
+
+/**
+ * @brief Structure definition of some features of ADC group injected.
+ * @note These parameters have an impact on ADC scope: ADC group injected.
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ * (functions with prefix "INJ").
+ * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ */
+typedef struct
+{
+ uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start)
+ or from external peripheral (timer event, external interrupt line).
+ This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
+ @note On this STM32 series, setting trigger source to external trigger
+ also set trigger polarity to rising edge (default setting for
+ compatibility with some ADC on other STM32 families having this
+ setting set by HW default value).
+ In case of need to modify trigger edge, use function
+ @ref LL_ADC_INJ_SetTriggerEdge().
+ This feature can be modified afterwards using unitary function
+ @ref LL_ADC_INJ_SetTriggerSource(). */
+
+ uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
+ This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
+ This feature can be modified afterwards using unitary function
+ @ref LL_ADC_INJ_SetSequencerLength(). */
+
+ uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided
+ and scan conversions interrupted every selected number of ranks.
+ This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
+ @note This parameter has an effect only if group injected sequencer
+ is enabled (scan length of 2 ranks or more).
+ This feature can be modified afterwards using unitary function
+ @ref LL_ADC_INJ_SetSequencerDiscont(). */
+
+ uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
+ This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
+ Note: This parameter must be set to set to independent trigger if injected
+ trigger source is set to an external trigger.
+ This feature can be modified afterwards using unitary function
+ @ref LL_ADC_INJ_SetTrigAuto(). */
+
+} LL_ADC_INJ_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
+ * @{
+ */
+
+/** @defgroup ADC_LL_EC_FLAG ADC flags
+ * @brief Flags defines which can be used with LL_ADC_ReadReg function
+ * @{
+ */
+#define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
+#define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */
+#define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence conversions */
+#define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */
+#define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */
+#define LL_ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC flag ADC group injected end of unitary conversion */
+#define LL_ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC flag ADC group injected end of sequence conversions */
+#define LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC flag ADC group injected contexts queue overflow */
+#define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */
+#define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */
+#define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */
+#define LL_ADC_FLAG_EOCAL ADC_ISR_EOCAL /*!< ADC flag end of calibration */
+#define LL_ADC_FLAG_LDORDY ADC_ISR_LDORDY /*!< ADC flag Voltage Regulator (LDO) Ready */
+
+#define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST /*!< ADC flag ADC multimode master instance ready */
+#define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV /*!< ADC flag ADC multimode slave instance ready */
+#define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST /*!< ADC flag ADC multimode master group regular end
+ of unitary conversion */
+#define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV /*!< ADC flag ADC multimode slave group regular end
+ of unitary conversion */
+#define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST /*!< ADC flag ADC multimode master group regular end
+ of sequence conversions */
+#define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV /*!< ADC flag ADC multimode slave group regular end
+ of sequence conversions */
+#define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST /*!< ADC flag ADC multimode master group regular overrun */
+#define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV /*!< ADC flag ADC multimode slave group regular overrun */
+#define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST /*!< ADC flag ADC multimode master group regular end
+ of sampling phase */
+#define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV /*!< ADC flag ADC multimode slave group regular end
+ of sampling phase */
+#define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST /*!< ADC flag ADC multimode master group injected end
+ of unitary conversion */
+#define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV /*!< ADC flag ADC multimode slave group injected end
+ of unitary conversion */
+#define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST /*!< ADC flag ADC multimode master group injected end
+ of sequence conversions */
+#define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV /*!< ADC flag ADC multimode slave group injected end
+ of sequence conversions */
+#define LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST /*!< ADC flag ADC multimode master group injected
+ contexts queue overflow */
+#define LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV /*!< ADC flag ADC multimode slave group injected
+ contexts queue overflow */
+#define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST /*!< ADC flag ADC multimode master analog watchdog 1
+ of the ADC master */
+#define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV /*!< ADC flag ADC multimode slave analog watchdog 1
+ of the ADC slave */
+#define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST /*!< ADC flag ADC multimode master analog watchdog 2
+ of the ADC master */
+#define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2
+ of the ADC slave */
+#define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3
+ of the ADC master */
+#define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3
+ of the ADC slave */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
+ * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
+ * @{
+ */
+#define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
+#define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of
+ unitary conversion */
+#define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of
+ sequence conversions */
+#define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */
+#define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of
+ sampling phase */
+#define LL_ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC interruption ADC group injected end of
+ unitary conversion */
+#define LL_ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC interruption ADC group injected end of
+ sequence conversions */
+#define LL_ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC interruption ADC group injected contexts
+ queue overflow */
+#define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */
+#define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */
+#define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */
+#define LL_ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC interruption ADC end of calibration */
+#define LL_ADC_IT_LDORDY ADC_IER_LDORDYIE /*!< ADC interruption ADC Voltage Regulator (LDO) Ready */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
+ * @{
+ */
+/* List of ADC registers intended to be used (most commonly) with */
+/* DMA transfer. */
+/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
+#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register
+ (corresponding to register DR) to be used with ADC
+ configured in independent mode. Without DMA transfer,
+ register accessed by LL function
+ @ref LL_ADC_REG_ReadConversionData32() and
+ other functions @ref LL_ADC_REG_ReadConversionDatax() */
+#if defined(ADC_MULTIMODE_SUPPORT)
+#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001UL) /* ADC group regular conversion data register
+ (corresponding to register CDR) to be used with
+ ADC configured in multimode (available on STM32 devices
+ with several ADC instances). Without DMA transfer,
+ register accessed by LL function
+ @ref LL_ADC_REG_ReadMultiConversionData32() */
+#endif /* ADC_MULTIMODE_SUPPORT */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
+ * @{
+ */
+#define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock
+ without prescaler */
+#define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock
+ with prescaler division
+ by 2 */
+#define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1) /*!< ADC asynchronous clock
+ with prescaler division
+ by 4 */
+#define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock
+ with prescaler division
+ by 6 */
+#define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2) /*!< ADC asynchronous clock
+ with prescaler division
+ by 8 */
+#define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock
+ with prescaler division
+ by 10 */
+#define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock
+ with prescaler division
+ by 12 */
+#define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock
+ with prescaler division
+ by 16 */
+#define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock
+ with prescaler division
+ by 32 */
+#define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock
+ with prescaler division
+ by 64 */
+#define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock
+ with prescaler division
+ by 128 */
+#define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock
+ with prescaler division
+ by 256 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
+ * @{
+ */
+/* Note: Other measurement paths to internal channels may be available */
+/* (connections to other peripherals). */
+/* If they are not listed below, they do not require any specific */
+/* path enable. In this case, Access to measurement path is done */
+/* only by selecting the corresponding ADC internal channel. */
+#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */
+#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
+#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_VSENSEEN) /*!< ADC measurement path to internal channel
+ temperature sensor */
+#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */
+
+#define LL_ADC_PATH_INTERNAL_VCORE (LL_ADC_PATH_INTERNAL_VREFINT \
+ | LL_ADC_CHANNEL_DIFFERENCIATION_VREFINT_VCORE) /*!< ADC measurement path
+to internal channel VCore */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_CALIBRATION_OFFSET_LINEARITY ADC instance - Calibration mode for offset and linearity
+ * @{
+ */
+#define LL_ADC_CALIB_OFFSET (ADC_CALIB_FACTOR_OFFSET_REGOFFSET) /*!< Calibration of ADC offset.
+ Duration of calibration of offset
+ duration: 1280 ADC clock cycles.
+ For devices with differential mode
+ available: Calibration of offset
+ is specific to each of single-ended
+ and differential modes. */
+#define LL_ADC_CALIB_LINEARITY (ADC_CALIB_FACTOR_LINEARITY_REGOFFSET)/*!< Calibration of ADC linearity.
+ Duration of calibration of
+ linearity: 15104 ADC clock cycles.
+ For devices with differential mode
+ available: Calibration of linearity
+ is common to both single-ended and
+ differential modes. */
+#define LL_ADC_CALIB_OFFSET_LINEARITY (ADC_CALIB_FACTOR_LINEARITY_REGOFFSET \
+ | ADC_CR_ADCALLIN) /*!< Calibration of ADC offset and
+ linearity. Duration of calibration
+ of offset and linearity: 16384 ADC
+ clock cycles. For devices with
+ differential mode available:
+ Calibration of offset is specific
+ to each of single-ended and
+ differential modes, calibration of
+ linearity is common to both
+single-ended and differential modes. */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_CALIBRATION_LINEARITY_INDEX ADC indexes for linear calibration
+ * @{
+ */
+#define LL_ADC_CALIB_OFFSET_INDEX (0x00000000UL) /*!< Offset Calibration Index */
+#define LL_ADC_CALIB_LINEARITY_INDEX1 (ADC_CR_CALINDEX0) /*!< Linearity Calibration Index 1*/
+#define LL_ADC_CALIB_LINEARITY_INDEX2 (ADC_CR_CALINDEX1) /*!< Linearity Calibration Index 2*/
+#define LL_ADC_CALIB_LINEARITY_INDEX3 (ADC_CR_CALINDEX1 | ADC_CR_CALINDEX0) /*!< Linearity Calibration Index 3*/
+#define LL_ADC_CALIB_LINEARITY_INDEX4 (ADC_CR_CALINDEX2) /*!< Linearity Calibration Index 4*/
+#define LL_ADC_CALIB_LINEARITY_INDEX5 (ADC_CR_CALINDEX2 | ADC_CR_CALINDEX0) /*!< Linearity Calibration Index 5*/
+#define LL_ADC_CALIB_LINEARITY_INDEX6 (ADC_CR_CALINDEX2 | ADC_CR_CALINDEX1) /*!< Linearity Calibration Index 6*/
+#define LL_ADC_CALIB_LINEARITY_INDEX7 (ADC_CR_CALINDEX2 | ADC_CR_CALINDEX1 \
+ | ADC_CR_CALINDEX0) /*!< Linearity Calibration Index 7*/
+#define LL_ADC_CALIB_INTEROFFSET_INDEX (ADC_CR_CALINDEX3) /*!< Linearity Calibration Index 8*/
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
+ * @{
+ */
+#define LL_ADC_RESOLUTION_14B (0x00000000UL) /*!< ADC resolution 14 bits */
+#define LL_ADC_RESOLUTION_12B ( ADC_CFGR1_RES_0) /*!< ADC resolution 12 bits */
+#define LL_ADC_RESOLUTION_10B (ADC_CFGR1_RES_1 ) /*!< ADC resolution 10 bits */
+#define LL_ADC_RESOLUTION_8B (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0) /*!< ADC resolution 8 bits */
+#define LL_ADC_RESOLUTION_6B (0x0000FFFFUL) /*!< ADC resolution 6 bits, Internal value
+ used to differentiate 8B to 6B resolutions
+ for ADC1 and ADC4 respectively */
+
+/* Internal values only, please do not use */
+#define LL_ADC_RESOLUTION_12B_ADC4 (0x00000000UL) /*!< ADC resolution 12 bits */
+#define LL_ADC_RESOLUTION_10B_ADC4 ( ADC_CFGR1_RES_0) /*!< ADC resolution 10 bits */
+#define LL_ADC_RESOLUTION_8B_ADC4 (ADC_CFGR1_RES_1 ) /*!< ADC resolution 8 bits */
+#define LL_ADC_RESOLUTION_6B_ADC4 (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0) /*!< ADC resolution 6 bits */
+
+/**
+ * @}
+ */
+/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
+ * @{
+ */
+#define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned
+ (alignment on data register LSB bit 0)*/
+#define LL_ADC_DATA_ALIGN_LEFT (ADC4_CFGR1_ALIGN) /*!< ADC conversion data alignment: left aligned
+ (alignment on data register MSB bit 15)*/
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_LEFT_BIT_SHIFT ADC left Shift
+ * @{
+ */
+#define LL_ADC_LEFT_BIT_SHIFT_NONE (0x00000000UL) /*!< ADC no bit shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_1 (ADC_CFGR2_LSHIFT_0) /*!< ADC 1 bit shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_2 (ADC_CFGR2_LSHIFT_1) /*!< ADC 2 bits shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_3 (ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 3 bits shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_4 (ADC_CFGR2_LSHIFT_2) /*!< ADC 4 bits shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_5 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0) /*!< ADC 5 bits shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_6 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1) /*!< ADC 6 bits shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_7 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 7 bits shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_8 (ADC_CFGR2_LSHIFT_3) /*!< ADC 8 bits shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_9 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_0) /*!< ADC 9 bits shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_10 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1) /*!< ADC 10 bits shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_11 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 11 bits shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_12 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2) /*!< ADC 12 bits shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_13 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0) /*!< ADC 13 bits shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_14 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1) /*!< ADC 14 bits shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_15 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 15 bits shift left applied on the final ADC conversion data */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
+ * @{
+ */
+#define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */
+#define LL_ADC_LP_AUTOWAIT (ADC_CFGR1_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_AUTOPOWEROFF_MODE ADC instance - Low power mode auto power-off
+ * @{
+ */
+#define LL_ADC_LP_AUTOPOWEROFF_DISABLE (0x00000000UL) /*!< ADC low power mode auto power-off disabled */
+#define LL_ADC_LP_AUTOPOWEROFF_ENABLE (ADC4_PW_AUTOFF) /*!< ADC low power mode auto power-off enabled: the ADC automatically powers-off after a ADC conversion and automatically wakes up when a new ADC conversion is triggered (with startup time between trigger and start of sampling). See description with function @ref LL_ADC_SetLPModeAutoPowerOff(). It can be combined with mode low power mode auto wait. */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_AUTONOMOUS_DEEP_POWER_DOWN_MODE ADC instance - Autonomous deep power down mode
+ * @{
+ */
+#define LL_ADC_LP_AUTONOMOUS_DPD_DISABLE (0x00000000UL) /*!< ADC deep power down in autonomous mode disabled */
+#define LL_ADC_LP_AUTONOMOUS_DPD_ENABLE (ADC4_PW_DPD) /*!< ADC deep power down in autonomous mode enabled */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset number
+ * @{
+ */
+#define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
+#define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
+#define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
+#define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_OFFSET_SIGNED_SATURATION ADC instance - Offset signed saturation mode
+ * @{
+ */
+#define LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE (0x00000000UL) /*!< ADC offset signed saturation is disabled (among ADC selected offset number 1, 2, 3 or 4) */
+#define LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE (ADC_OFR1_SSAT) /*!< ADC offset signed saturation is enabled (among ADC selected offset number 1, 2, 3 or 4) */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_OFFSET_UNSIGNED_SATURATION ADC instance - Offset unsigned saturation mode
+ * @{
+ */
+#define LL_ADC_OFFSET_UNSIGNED_SATURATION_DISABLE (0x00000000UL) /*!< ADC offset unsigned saturation is disabled (among ADC selected offset number 1, 2, 3 or 4) */
+#define LL_ADC_OFFSET_UNSIGNED_SATURATION_ENABLE (ADC_OFR1_USAT) /*!< ADC offset unsigned saturation is enabled (among ADC selected offset number 1, 2, 3 or 4) */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_OFFSET_SIGN ADC instance - Offset sign
+ * @{
+ */
+#define LL_ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< ADC offset is negative (among ADC selected offset number 1, 2, 3 or 4) */
+#define LL_ADC_OFFSET_SIGN_POSITIVE (ADC_OFR1_OFFSETPOS) /*!< ADC offset is positive (among ADC selected offset number 1, 2, 3 or 4) */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
+ * @{
+ */
+#define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */
+#define LL_ADC_GROUP_INJECTED (0x00000002UL) /*!< ADC group injected (not available on all STM32 devices)*/
+#define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL) /*!< ADC both groups regular and injected */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON ADC instance - Sampling time common to a group of channels
+ * @{
+ */
+#define LL_ADC_SAMPLINGTIME_COMMON_1 (ADC4_SMPR_SMP1_BITOFFSET_POS) /*!< Set sampling time common to a group of channels: sampling time nb 1 */
+#define LL_ADC_SAMPLINGTIME_COMMON_2 (ADC4_SMPR_SMP2_BITOFFSET_POS | ADC4_SAMPLING_TIME_CH_MASK) /*!< Set sampling time common to a group of channels: sampling time nb 2 */
+/* Internal mask for ADC channel sampling time: */
+/* To select into literals LL_ADC_SAMPLINGTIME_x */
+/* the relevant bits for: */
+/* (concatenation of multiple bits used in register SMPR) */
+/* - ADC channels sampling time: setting channel wise, to map each channel */
+/* on one of the common sampling time available. */
+/* - ADC channels common sampling time: set a sampling time into one of the */
+/* common sampling time available. */
+#define ADC4_SAMPLING_TIME_SMP_MASK (ADC4_SMPR_SMP2 | ADC4_SMPR_SMP1)
+#define ADC4_SAMPLING_TIME_SMP_SHIFT_MASK (ADC4_SMPR_SMP2_BITOFFSET_POS | ADC4_SMPR_SMP1_BITOFFSET_POS)
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode
+ * @{
+ */
+#define LL_ADC_TRIGGER_FREQ_HIGH (0x00000000UL) /*!< ADC trigger frequency mode set to high frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */
+#define LL_ADC_TRIGGER_FREQ_LOW (ADC4_CFGR2_LFTRIG) /*!< ADC trigger frequency mode set to low frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
+ * @{
+ */
+#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
+#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
+#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
+#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
+#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
+#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
+#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
+#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
+#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
+#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
+#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
+#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
+#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
+#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
+#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
+#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
+#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
+#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
+#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
+#define LL_ADC_CHANNEL_19 (ADC_CHANNEL_19_NUMBER | ADC_CHANNEL_19_SMP | ADC_CHANNEL_19_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN19 */
+#define LL_ADC_CHANNEL_20 (ADC_CHANNEL_20_NUMBER | ADC_CHANNEL_20_SMP | ADC_CHANNEL_20_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN20 */
+#define LL_ADC_CHANNEL_21 (ADC_CHANNEL_21_NUMBER | ADC_CHANNEL_21_SMP | ADC_CHANNEL_21_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN21 */
+#define LL_ADC_CHANNEL_22 (ADC_CHANNEL_22_NUMBER | ADC_CHANNEL_22_SMP | ADC_CHANNEL_22_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN22 */
+#define LL_ADC_CHANNEL_23 (ADC_CHANNEL_23_NUMBER | ADC_CHANNEL_23_SMP | ADC_CHANNEL_23_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN23 */
+
+#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_0 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. . */
+#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_19 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. */
+#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda. */
+
+#define LL_ADC_CHANNEL_VCORE (LL_ADC_CHANNEL_12 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vcore. On STM32U5, ADC channel available only on ADC instance: ADC4. */
+#define LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32U5, ADC channel available only on ADC instance: ADC4. */
+#define LL_ADC_CHANNEL_VBAT_ADC4 (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda. On STM32U5, ADC channel available only on ADC instance: ADC4. */
+#define LL_ADC_CHANNEL_DAC1CH1_ADC4 (LL_ADC_CHANNEL_21 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC4 */
+#define LL_ADC_CHANNEL_DAC1CH2_ADC4 (LL_ADC_CHANNEL_DAC1CH1_ADC4 | LL_ADC_CHANNEL_DIFFERENCIATION_VREFINT_VCORE) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC4 */
+
+#define LL_ADC_CHANNEL_DIFFERENCIATION_VREFINT_VCORE (0x01000000UL) /*!< Dummy bit for driver internal usage, not used in ADC channel setting registers CHSELR or SQRx */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
+ * @{
+ */
+#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular conversion trigger internal: SW start. */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11 event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 \
+ | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR1_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 \
+ | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 \
+ | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 \
+ | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 \
+ | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_EXTI_LINE15 (ADC_CFGR1_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIM TRG1 event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_LPTIM1_CH1 (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM1 CH1 event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_LPTIM2_CH1 (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 \
+ | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM2 CH1 event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_LPTIM3_CH1 (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM3 CH1 event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_LPTIM4_OUT (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 \
+ | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM4 event OUT. Trigger edge set to rising edge (default setting). */
+
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2_ADC4 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH4_ADC4 (ADC4_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#if defined(TIM2)
+#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO_ADC4 (ADC4_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
+#endif /* TIM2 */
+#if defined(TIM15)
+#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO_ADC4 (ADC4_CFGR1_EXTSEL_1 | ADC4_CFGR1_EXTSEL_0 \
+ | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
+#endif /* TIM5 */
+#if defined(TIM6)
+#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC4 (ADC4_CFGR1_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
+#endif /* TIM6 */
+#if defined(LPTIM1)
+#define LL_ADC_REG_TRIG_EXT_LPTIM1_CH1_ADC4 (ADC4_CFGR1_EXTSEL_2 | ADC4_CFGR1_EXTSEL_0 \
+ | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: LPTIM1 CH1. Trigger edge set to rising edge (default setting). */
+#endif /* LPTIM1 */
+#if defined(LPTIM3)
+#define LL_ADC_REG_TRIG_EXT_LPTIM3_CH2_ADC4 (ADC4_CFGR1_EXTSEL_2 | ADC4_CFGR1_EXTSEL_1 \
+ | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: LPTIM3 CH2. Trigger edge set to rising edge (default setting). */
+#endif /* LPTIM3 */
+#define LL_ADC_REG_TRIG_EXT_EXTI_LINE15_ADC4 (ADC4_CFGR1_EXTSEL_2 | ADC4_CFGR1_EXTSEL_1 \
+ | ADC4_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
+ * @{
+ */
+#define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */
+#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR1_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */
+#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
+ * @{
+ */
+#define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions are performed in single mode: one conversion per trigger */
+#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR1_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_DATA_TRANSFER_MODE ADC group regular - Data transfer mode of ADC conversion data
+ * @{
+ */
+#define LL_ADC_REG_DR_TRANSFER (0x00000000UL) /*!< ADC conversions are transferred to DR rigister */
+#define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversion data are not transferred by DMA but to DR register */
+#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR1_DMNGT_0) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
+#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR1_DMNGT_1 | ADC_CFGR1_DMNGT_0) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
+#define LL_ADC_REG_MDF_TRANSFER (ADC_CFGR1_DMNGT_1 ) /*!< ADC conversion data are transferred to DFSDM */
+/**
+ * @}
+ */
+/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
+ * @{
+ */
+#define LL_ADC_REG_DMA_TRANSFER_NONE_ADC4 (0x00000000UL) /*!< ADC conversions are not transferred by DMA */
+#define LL_ADC_REG_DMA_TRANSFER_LIMITED_ADC4 ( ADC4_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
+#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED_ADC4 (ADC4_CFGR1_DMACFG | ADC4_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
+ * @{
+ */
+#define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun: data preserved */
+#define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR1_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_MODE ADC group regular - Sequencer configuration flexibility
+ * @{
+ */
+#define LL_ADC_REG_SEQ_FIXED (0x00000000UL) /*!< Sequencer configured to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number. Refer to description of function @ref LL_ADC_REG_SetSequencerChannels(). */
+#define LL_ADC_REG_SEQ_CONFIGURABLE (ADC4_CFGR1_CHSELRMOD) /*!< Sequencer configured to fully configurable: sequencer length and each rank affectation to a channel are configurable. Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
+ * @{
+ */
+#define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
+/**
+ * @}
+ */
+/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
+ * @{
+ */
+#define LL_ADC4_REG_SEQ_SCAN_DISABLE (ADC_CHSELR_SQ2) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
+#define LL_ADC4_REG_SEQ_SCAN_ENABLE_2RANKS (ADC_CHSELR_SQ3) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
+#define LL_ADC4_REG_SEQ_SCAN_ENABLE_3RANKS (ADC_CHSELR_SQ4) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
+#define LL_ADC4_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_CHSELR_SQ5) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
+#define LL_ADC4_REG_SEQ_SCAN_ENABLE_5RANKS (ADC_CHSELR_SQ6) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
+#define LL_ADC4_REG_SEQ_SCAN_ENABLE_6RANKS (ADC_CHSELR_SQ7) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
+#define LL_ADC4_REG_SEQ_SCAN_ENABLE_7RANKS (ADC_CHSELR_SQ8) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
+#define LL_ADC4_REG_SEQ_SCAN_ENABLE_8RANKS (0x00000000UL) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
+ * @{
+ */
+#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer discontinuous mode disable */
+#define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
+#define LL_ADC_REG_SEQ_DISCONT_2RANKS (ADC_CFGR1_DISCNUM_0 | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_3RANKS (ADC_CFGR1_DISCNUM_1 | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_4RANKS (ADC_CFGR1_DISCNUM_1 | ADC_CFGR1_DISCNUM_0 | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR1_DISCNUM_2 | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR1_DISCNUM_2 | ADC_CFGR1_DISCNUM_0 | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR1_DISCNUM_2 | ADC_CFGR1_DISCNUM_1 | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR1_DISCNUM_2 | ADC_CFGR1_DISCNUM_1 | ADC_CFGR1_DISCNUM_0 \
+ | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_DIRECTION ADC group regular - Sequencer scan direction
+ * @{
+ */
+#define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD (0x00000000UL) /*!< On this STM32 series, parameter relevant only is sequencer set to mode not fully configurable, refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan direction forward: from lowest channel number to highest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer). On some other STM32 families, this setting is not available and the default scan direction is forward. */
+#define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD (ADC4_CFGR1_SCANDIR) /*!< On this STM32 series, parameter relevant only is sequencer set to mode not fully configurable, refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan direction backward: from highest channel number to lowest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer) */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
+ * @{
+ */
+#define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
+#define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
+#define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
+#define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
+#define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
+#define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
+#define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
+#define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
+#define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */
+#define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
+#define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
+#define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
+#define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
+#define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
+#define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
+#define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
+
+#define LL_ADC_REG_RANK_1_ADC4 (ADC4_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
+#define LL_ADC_REG_RANK_2_ADC4 (ADC4_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
+#define LL_ADC_REG_RANK_3_ADC4 (ADC4_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
+#define LL_ADC_REG_RANK_4_ADC4 (ADC4_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
+#define LL_ADC_REG_RANK_5_ADC4 (ADC4_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
+#define LL_ADC_REG_RANK_6_ADC4 (ADC4_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
+#define LL_ADC_REG_RANK_7_ADC4 (ADC4_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
+#define LL_ADC_REG_RANK_8_ADC4 (ADC4_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
+ * @{
+ */
+#define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group injected conversion trigger internal: SW start. */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 \
+ | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 \
+ | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 \
+ | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 \
+ | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 \
+ | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 \
+ | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_LPTIM3_CH1 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM3 OUT event. 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_LPTIM4_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 \
+ | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM3 OUT event. 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
+ * @{
+ */
+#define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */
+#define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */
+#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
+ * @{
+ */
+#define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL) /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
+#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_SAMPLING_MODE ADC group regular - Sampling mode
+ * @{
+ */
+#define LL_ADC_REG_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration is defined using @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME. */
+#define LL_ADC_REG_SAMPLING_MODE_BULB (ADC_CFGR2_BULB) /*!< ADC conversions sampling phase starts immediately after end of conversion, and stops upon trigger event.
+ Note: First conversion is using minimal
+ sampling time (see @ref
+ ADC_LL_EC_CHANNEL_SAMPLINGTIME). */
+#define LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED (ADC_CFGR2_SMPTRIG)/*!< ADC conversions sampling phase is controlled by trigger events:
+ Trigger rising edge = start sampling
+ Trigger falling edge = stop sampling and
+ start conversion. */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
+ * @{
+ */
+#define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
+ * @{
+ */
+#define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group injected sequencer discontinuous mode disable */
+#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR1_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
+ * @{
+ */
+#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */
+#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */
+#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */
+#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
+ * @{
+ */
+#define LL_ADC_SAMPLINGTIME_5CYCLE (0x00000000UL) /*!< Sampling time 5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_6CYCLES ( ADC_SMPR2_SMP10_0) /*!< Sampling time 6 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_12CYCLES ( ADC_SMPR2_SMP10_1 ) /*!< Sampling time 12 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_20CYCLES ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 20 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_36CYCLES (ADC_SMPR2_SMP10_2 ) /*!< Sampling time 36 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_68CYCLES (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0) /*!< Sampling time 68 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_391CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 ) /*!< Sampling time 391.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_814CYCLES (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 814 ADC clock cycles */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
+ * @{
+ */
+#define LL_ADC4_SAMPLINGTIME_1CYCLE_5 (0x00000000UL) /*!< Sampling time 1.5 ADC clock cycle */
+#define LL_ADC4_SAMPLINGTIME_3CYCLES_5 (ADC4_SMPR_SMP1_0) /*!< Sampling time 3.5 ADC clock cycles */
+#define LL_ADC4_SAMPLINGTIME_7CYCLES_5 (ADC4_SMPR_SMP1_1) /*!< Sampling time 7.5 ADC clock cycles */
+#define LL_ADC4_SAMPLINGTIME_12CYCLES_5 (ADC4_SMPR_SMP1_1 | ADC4_SMPR_SMP1_0) /*!< Sampling time 12.5 ADC clock cycles */
+#define LL_ADC4_SAMPLINGTIME_19CYCLES_5 (ADC4_SMPR_SMP1_2) /*!< Sampling time 19.5 ADC clock cycles */
+#define LL_ADC4_SAMPLINGTIME_39CYCLES_5 (ADC4_SMPR_SMP1_2 | ADC4_SMPR_SMP1_0) /*!< Sampling time 39.5 ADC clock cycles */
+#define LL_ADC4_SAMPLINGTIME_79CYCLES_5 (ADC4_SMPR_SMP1_2 | ADC4_SMPR_SMP1_1) /*!< Sampling time 79.5 ADC clock cycles */
+#define LL_ADC4_SAMPLINGTIME_160CYCLES_5 (ADC4_SMPR_SMP1_2 | ADC4_SMPR_SMP1_1 | ADC4_SMPR_SMP1_0) /*!< Sampling time 160.5 ADC clock cycles */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
+ * @{
+ */
+#define LL_ADC_SINGLE_ENDED (0x0000FFFFUL) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
+#define LL_ADC_DIFFERENTIAL_ENDED (0xFFFF0000UL) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
+#define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
+ * @{
+ */
+#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
+#define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
+#define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
+ * @{
+ */
+#define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring disabled */
+#define LL_ADC_AWD_ALL_CHANNELS_REG ((0x000FFFFFUL) | ADC_CFGR1_AWD1EN) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
+#define LL_ADC_AWD_ALL_CHANNELS_INJ ((0x000FFFFFUL) | ADC_CFGR1_JAWD1EN) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
+#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ((0x000FFFFFUL) | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_19_REG ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_19_INJ ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_19_REG_INJ ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_20_REG ((LL_ADC_CHANNEL_20 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_20_INJ ((LL_ADC_CHANNEL_20 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_20_REG_INJ ((LL_ADC_CHANNEL_20 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_21_REG ((LL_ADC_CHANNEL_21 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_21_INJ ((LL_ADC_CHANNEL_21 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_21_REG_INJ ((LL_ADC_CHANNEL_21 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_22_REG ((LL_ADC_CHANNEL_22 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_22_INJ ((LL_ADC_CHANNEL_22 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_22_REG_INJ ((LL_ADC_CHANNEL_22 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_23_REG ((LL_ADC_CHANNEL_23 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_23_INJ ((LL_ADC_CHANNEL_23 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_23_REG_INJ ((LL_ADC_CHANNEL_23 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_NUMBER_MASK) \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
+#define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_NUMBER_MASK) \
+ | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
+#define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_NUMBER_MASK) \
+ | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_NUMBER_MASK) \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
+#define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_NUMBER_MASK) \
+ | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
+#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_NUMBER_MASK) \
+ | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_NUMBER_MASK) \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, converted by group regular only */
+#define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_NUMBER_MASK) \
+ | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, converted by group injected only */
+#define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_NUMBER_MASK) \
+ | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda */
+#define LL_ADC_AWD_CH_VCORE_REG ((LL_ADC_CHANNEL_VCORE & ADC_CHANNEL_ID_NUMBER_MASK) \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
+#define LL_ADC_AWD_CH_VCORE_INJ ((LL_ADC_CHANNEL_VCORE & ADC_CHANNEL_ID_NUMBER_MASK) \
+ | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
+#define LL_ADC_AWD_CH_VCORE_REG_INJ ((LL_ADC_CHANNEL_VCORE & ADC_CHANNEL_ID_NUMBER_MASK) \
+ | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
+
+#define LL_ADC_AWD_CH_DAC1CH1_ADC4_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC4 & ADC_CHANNEL_ID_NUMBER_MASK) \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC4, converted by group regular only */
+#define LL_ADC_AWD_CH_DAC1CH2_ADC4_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC4 & ADC_CHANNEL_ID_NUMBER_MASK) \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 2, channel specific to ADC4, converted by group regular only */
+#define LL_ADC_AWD_CH_TEMPSENSOR_ADC4_REG ((LL_ADC_CHANNEL_TEMPSENSOR_ADC4 & ADC_CHANNEL_ID_NUMBER_MASK) \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to emperature sensor, channel specific to ADC4, converted by group regular only */
+#define LL_ADC_AWD_CH_VBAT_ADC4_REG ((LL_ADC_CHANNEL_VBAT_ADC4 & ADC_CHANNEL_ID_NUMBER_MASK) \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, channel specific to ADC4, converted by group regular only */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
+ * @{
+ */
+#define LL_ADC_AWD_THRESHOLD_HIGH (0x1UL) /*!< ADC analog watchdog threshold high */
+#define LL_ADC_AWD_THRESHOLD_LOW (0x0UL) /*!< ADC analog watchdog threshold low */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_AWD_FILTERING_CONFIG Analog watchdog - filtering config
+ * @{
+ */
+#define LL_ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog wathdog no filtering, one out-of-window sample is needed to raise flag or interrupt */
+#define LL_ADC_AWD_FILTERING_2SAMPLES ( ADC_HTR_AWDFILT_0) /*!< ADC analog wathdog 2 consecutives out-of-window samples are needed to raise flag or interrupt */
+#define LL_ADC_AWD_FILTERING_3SAMPLES ( ADC_HTR_AWDFILT_1 ) /*!< ADC analog wathdog 3 consecutives out-of-window samples are needed to raise flag or interrupt */
+#define LL_ADC_AWD_FILTERING_4SAMPLES ( ADC_HTR_AWDFILT_1 | ADC_HTR_AWDFILT_0) /*!< ADC analog wathdog 4 consecutives out-of-window samples are needed to raise flag or interrupt */
+#define LL_ADC_AWD_FILTERING_5SAMPLES (ADC_HTR_AWDFILT_2 ) /*!< ADC analog wathdog 5 consecutives out-of-window samples are needed to raise flag or interrupt */
+#define LL_ADC_AWD_FILTERING_6SAMPLES (ADC_HTR_AWDFILT_2 | ADC_HTR_AWDFILT_0) /*!< ADC analog wathdog 6 consecutives out-of-window samples are needed to raise flag or interrupt */
+#define LL_ADC_AWD_FILTERING_7SAMPLES (ADC_HTR_AWDFILT_2 | ADC_HTR_AWDFILT_1 ) /*!< ADC analog wathdog 7 consecutives out-of-window samples are needed to raise flag or interrupt */
+#define LL_ADC_AWD_FILTERING_8SAMPLES (ADC_HTR_AWDFILT_2 | ADC_HTR_AWDFILT_1 | ADC_HTR_AWDFILT_0) /*!< ADC analog wathdog 8 consecutives out-of-window samples are needed to raise flag or interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope
+ * @{
+ */
+#define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */
+#define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards. */
+#define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
+#define LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE ) /*!< ADC oversampling on conversions of ADC group injected. */
+#define LL_ADC_OVS_GRP_INJ_REG_RESUMED ( ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
+ * @{
+ */
+#define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
+#define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
+/**
+ * @}
+ */
+/** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio
+ * @{
+ */
+#define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_4 ( ADC4_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_8 ( ADC4_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_16 ( ADC4_CFGR2_OVSR_1 | ADC4_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_32 (ADC4_CFGR2_OVSR_2 ) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_64 (ADC4_CFGR2_OVSR_2 | ADC4_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_128 (ADC4_CFGR2_OVSR_2 | ADC4_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_256 (ADC4_CFGR2_OVSR_2 | ADC4_CFGR2_OVSR_1 | ADC4_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data shift
+ * @{
+ */
+#define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_9 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 9 (sum of the ADC conversions data is divided by 512 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_10 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 10 (sum of the ADC conversions data is divided by 1024 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_11 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 11 (sum of the ADC conversions data is divided by 2048 to result as the ADC oversampling conversion data) */
+/**
+ * @}
+ */
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
+ * @{
+ */
+#define LL_ADC_MULTI_INDEPENDENT (0x00000000UL) /*!< ADC dual mode disabled (ADC independent mode) */
+#define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: group regular simultaneous */
+#define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved */
+#define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */
+#define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
+#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
+#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
+#define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
+ * @{
+ */
+#define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000UL) /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */
+#define LL_ADC_MULTI_REG_DMA_RES_32_10B (ADC_CCR_DAMDF_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master). Setting for ADC resolution of 32 (16x2) down to 10 bits */
+#define LL_ADC_MULTI_REG_DMA_RES_8B (ADC_CCR_DAMDF_1 | ADC_CCR_DAMDF_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master). Setting for ADC resolution of 8 bits */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
+ * @{
+ */
+#define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5 (0x00000000UL) /*!< ADC multimode delay between two sampling phases: 1.5 ADC clock cycle for all resolution */
+#define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5 ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2.5 ADC clock cycles for all resolution */
+#define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5 ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 3.5 ADC clock cycles for all resolution */
+#define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5 ( ADC_CCR_DELAY_1|ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4.5 ADC clock cycles for 16, 14, 12 or 10 bits resolution */
+#define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS ( ADC_CCR_DELAY_2|ADC_CCR_DELAY_1|ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4.5 ADC clock cycles for 8 bits resolution */
+#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5 ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 5.5 ADC clock cycles for 16, 14, 12 bits resolution */
+#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS ( ADC_CCR_DELAY_2|ADC_CCR_DELAY_1|ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 5.5 ADC clock cycles for 10 bits resolution */
+#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles for 10 or 8 bits resolution */
+#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5 ( ADC_CCR_DELAY_2 |ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6.5 ADC clock cycles for 16 or 14 bits resolution */
+#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS ( ADC_CCR_DELAY_2|ADC_CCR_DELAY_1|ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6.5 ADC clock cycles for 12 bits resolution */
+#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5 ( ADC_CCR_DELAY_2|ADC_CCR_DELAY_1|ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 7.5 ADC clock cycles for 16 bits resolution */
+#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles for 12 bits resolution */
+#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles for 16 or 14 bits resolution */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
+ * @{
+ */
+#define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */
+#define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */
+#define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
+/**
+ * @}
+ */
+
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
+ * @note Only ADC peripheral HW delays are defined in ADC LL driver driver,
+ * not timeout values.
+ * For details on delays values, refer to descriptions in source code
+ * above each literal definition.
+ * @{
+ */
+
+/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
+/* not timeout values. */
+/* Timeout values for ADC operations are dependent to device clock */
+/* configuration (system clock versus ADC clock), */
+/* and therefore must be defined in user application. */
+/* Indications for estimation of ADC timeout delays, for this */
+/* STM32 series: */
+/* - ADC calibration time: maximum delay is 16384/fADC. */
+/* (refer to device datasheet, parameter "tCAL") */
+/* - ADC enable time: maximum delay is 1 conversion cycle. */
+/* (refer to device datasheet, parameter "tSTAB") */
+/* - ADC disable time: maximum delay should be a few ADC clock cycles */
+/* - ADC stop conversion time: maximum delay should be a few ADC clock */
+/* cycles */
+/* - ADC conversion time: duration depending on ADC clock and ADC */
+/* configuration. */
+/* (refer to device reference manual, section "Timing") */
+
+/* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
+/* Delay set to maximum value (refer to device datasheet, */
+/* parameter "tADCVREG_STUP"). */
+/* Unit: us */
+#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */
+
+/* Delay for internal voltage reference stabilization time. */
+/* Delay set to maximum value (refer to device datasheet, */
+/* parameter "ts_vrefint"). */
+/* Unit: us */
+#define LL_ADC_DELAY_VREFINT_STAB_US (5UL) /*!< Delay for internal voltage reference stabilization time */
+
+/* Delay for temperature sensor stabilization time. */
+/* Literal set to maximum value (refer to device datasheet, */
+/* parameter "tSTART_RUN"). */
+/* Unit: us */
+#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 26UL) /*!< Delay for temperature sensor stabilization time */
+
+/* Delay required between ADC end of calibration and ADC enable. */
+/* Note: On this STM32 series, a minimum number of ADC clock cycles */
+/* are required between ADC end of calibration and ADC enable. */
+/* Wait time can be computed in user application by waiting for the */
+/* equivalent number of CPU cycles, by taking into account */
+/* ratio of CPU clock versus ADC clock prescalers. */
+/* Unit: ADC clock cycles. */
+#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration and ADC enable */
+
+/* Fixed timeout value for ADC linearity word bit set/clear delay. */
+/* Values defined to be higher than worst cases: low clock frequency, */
+/* maximum prescalers. */
+/* Ex of profile low frequency : f_ADC at 4,577 Khz (minimum value */
+/* according to Data sheet), linearity set/clear bit delay MAX = 6 / f_ADC + 3 cycles AHB */
+/* 6 / 4577 = 1,311ms */
+/* At maximum CPU speed (400 MHz), this means */
+/* 3.58 * 400 MHz = 524400 CPU cycles */
+#define ADC_LINEARITY_BIT_TOGGLE_TIMEOUT (524400UL) /*!< ADC linearity set/clear bit delay */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
+ * @{
+ */
+
+/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in ADC register
+ * @param __INSTANCE__ ADC Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in ADC register
+ * @param __INSTANCE__ ADC Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
+ * @{
+ */
+
+/**
+ * @brief Helper macro to get ADC channel number in decimal format
+ * from literals LL_ADC_CHANNEL_x.
+ * @note Example:
+ * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
+ * will return decimal number "4".
+ * @note The input can be a value from functions where a channel
+ * number is returned, either defined with number
+ * or with bitfield (only one bit must be set).
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0 (3)
+ * @arg @ref LL_ADC_CHANNEL_1 (3)
+ * @arg @ref LL_ADC_CHANNEL_2 (3)
+ * @arg @ref LL_ADC_CHANNEL_3 (3)
+ * @arg @ref LL_ADC_CHANNEL_4 (3)
+ * @arg @ref LL_ADC_CHANNEL_5 (3)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_19
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_VCORE (2)
+ *
+ * (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.
+ * (2) On STM32U5, parameter available only on ADC instance: ADC4.
+ * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).
+ * @retval Value between Min_Data=0 and Max_Data=18
+ */
+#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
+ ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) \
+ ? ( ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ) \
+ : ( (uint32_t)POSITION_VAL((__CHANNEL__)) ) \
+ )
+
+/**
+ * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
+ * from number in decimal format.
+ * @note Example:
+ * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
+ * will return a data equivalent to "LL_ADC_CHANNEL_4".
+ * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0 (3)
+ * @arg @ref LL_ADC_CHANNEL_1 (3)
+ * @arg @ref LL_ADC_CHANNEL_2 (3)
+ * @arg @ref LL_ADC_CHANNEL_3 (3)
+ * @arg @ref LL_ADC_CHANNEL_4 (3)
+ * @arg @ref LL_ADC_CHANNEL_5 (3)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_19
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_VCORE (2)
+ *
+ * (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.
+ * (2) On STM32U5, parameter available only on ADC instance: ADC4.
+ * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).
+ * (1, 2) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ */
+#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
+ (((__DECIMAL_NB__) <= 9UL) \
+ ? (((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
+ (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
+ (ADC_SMPR1_REGOFFSET)) \
+ : (((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
+ (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
+ (ADC_SMPR2_REGOFFSET)) \
+ )
+
+/**
+ * @brief Helper macro to convert ADC1 resolution to ADC4 resolution bit values.
+ * @note Example 1:
+ * __LL_ADC_RESOLUTION_ADC1_TO_ADC4(LL_ADC_RESOLUTION_6B)
+ * will return a data equivalent to "(ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0)".
+ * @note Example 2:
+ * __LL_ADC_RESOLUTION_ADC1_TO_ADC4(LL_ADC_RESOLUTION_10B)
+ * will return a data equivalent to "(ADC_CFGR1_RES_0)".
+ * @param __RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @retval Returned value can be one of the following values:
+ * @arg 0x00000000UL (value correspodning to ADC4 12 bits)
+ * @arg ADC_CFGR1_RES_0 = 0x00000004UL (value correspodning to ADC4 10 bits)
+ * @arg ADC_CFGR1_RES_1 = 0x00000008UL (value corresponding to ADC4 8 bits)
+ * @arg ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0 = 0x0000000CUL (value corresponding to ADC4 6 bits)
+ */
+
+#define __LL_ADC_RESOLUTION_ADC1_TO_ADC4(__RESOLUTION__) \
+ (((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
+ ? ((LL_ADC_RESOLUTION_8B)) \
+ : ((((__RESOLUTION__)-1UL) & ADC_CFGR1_RES_Msk)) \
+ )
+
+/**
+ * @brief Helper macro to convert ADC4 resolution bit values to ADC1 resolution.
+ * @note Example 1:
+ * __LL_ADC_RESOLUTION_ADC4_TO_ADC1((ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0))
+ * will return a data equivalent to "LL_ADC_RESOLUTION_6B".
+ * @note Example 2:
+ * __LL_ADC_RESOLUTION_ADC1_TO_ADC4((ADC_CFGR1_RES_0))
+ * will return a data equivalent to "LL_ADC_RESOLUTION_10B".
+ * @param __RESOLUTION__ This parameter can be one of the following values:
+ * @arg 0x00000000UL (value correspodning to ADC4 12 bits)
+ * @arg ADC_CFGR1_RES_0 = 0x00000004UL (value correspodning to ADC4 10 bits)
+ * @arg ADC_CFGR1_RES_1 = 0x00000008UL (value corresponding to ADC4 8 bits)
+ * @arg ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0 = 0x0000000CUL (value corresponding to ADC4 6 bits)
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ */
+
+#define __LL_ADC_RESOLUTION_ADC4_TO_ADC1(__RESOLUTION__) \
+ (((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
+ ? ((LL_ADC_RESOLUTION_6B)) \
+ : ((((((__RESOLUTION__) >> ADC_CFGR1_RES_Pos) + 1UL) << ADC_CFGR1_RES_Pos) & ADC_CFGR1_RES_Msk)) \
+ )
+/**
+ * @brief Helper macro to determine whether the selected channel
+ * corresponds to literal definitions of driver.
+ * @note The different literal definitions of ADC channels are:
+ * - ADC internal channel:
+ * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
+ * - ADC external channel (channel connected to a GPIO pin):
+ * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
+ * @note The channel parameter must be a value defined from literal
+ * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+ * LL_ADC_CHANNEL_TEMPSENSOR, ...),
+ * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
+ * must not be a value from functions where a channel number is
+ * returned from ADC registers,
+ * because internal and external channels share the same channel
+ * number in ADC registers. The differentiation is made only with
+ * parameters definitions of driver.
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0 (3)
+ * @arg @ref LL_ADC_CHANNEL_1 (3)
+ * @arg @ref LL_ADC_CHANNEL_2 (3)
+ * @arg @ref LL_ADC_CHANNEL_3 (3)
+ * @arg @ref LL_ADC_CHANNEL_4 (3)
+ * @arg @ref LL_ADC_CHANNEL_5 (3)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_19
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_VCORE (2)
+ *
+ * (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.
+ * (2) On STM32U5, parameter available only on ADC instance: ADC4.
+ * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).
+ * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel
+ * (channel connected to a GPIO pin).
+ * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
+ */
+#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
+ (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
+
+/**
+ * @brief Helper macro to convert a channel defined from parameter
+ * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+ * LL_ADC_CHANNEL_TEMPSENSOR, ...),
+ * to its equivalent parameter definition of a ADC external channel
+ * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
+ * @note The channel parameter can be, additionally to a value
+ * defined from parameter definition of a ADC internal channel
+ * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
+ * a value defined from parameter definition of
+ * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
+ * or a value from functions where a channel number is returned
+ * from ADC registers.
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0 (3)
+ * @arg @ref LL_ADC_CHANNEL_1 (3)
+ * @arg @ref LL_ADC_CHANNEL_2 (3)
+ * @arg @ref LL_ADC_CHANNEL_3 (3)
+ * @arg @ref LL_ADC_CHANNEL_4 (3)
+ * @arg @ref LL_ADC_CHANNEL_5 (3)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_19
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_VCORE (2)
+ *
+ * (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.
+ * (2) On STM32U5, parameter available only on ADC instance: ADC4.
+ * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_19
+ */
+#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
+ ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
+
+/**
+ * @brief Helper macro to determine whether the internal channel
+ * selected is available on the ADC instance selected.
+ * @note The channel parameter must be a value defined from parameter
+ * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+ * LL_ADC_CHANNEL_TEMPSENSOR, ...),
+ * must not be a value defined from parameter definition of
+ * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
+ * or a value from functions where a channel number is
+ * returned from ADC registers,
+ * because internal and external channels share the same channel
+ * number in ADC registers. The differentiation is made only with
+ * parameters definitions of driver.
+ * @param __ADC_INSTANCE__ ADC instance
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_VCORE (2)
+ *
+ * (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.
+ * (2) On STM32U5, parameter available only on ADC instance: ADC4.
+ * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
+ * Value "1" if the internal channel selected is available on the ADC instance selected.
+ */
+#if defined(ADC2)
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
+ ((((__ADC_INSTANCE__) == ADC4) &&( ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC4) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC4) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC4) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT_ADC4) ) \
+ ) \
+ || \
+ (((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2) \
+ &&(((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) ) \
+ ) \
+ )
+#else
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
+ ((((__ADC_INSTANCE__) == ADC4) \
+ &&(((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC4) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC4) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC4) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT_ADC4) ) \
+ ) \
+ || \
+ (((__ADC_INSTANCE__) == ADC1) \
+ &&(((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) ) \
+ ) \
+ )
+#endif /* ADC2 */
+/**
+ * @brief Helper macro to define ADC analog watchdog parameter:
+ * define a single channel to monitor with analog watchdog
+ * from sequencer channel and groups definition.
+ * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
+ * Example:
+ * LL_ADC_SetAnalogWDMonitChannels(
+ * ADC1, LL_ADC_AWD1,
+ * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0 (3)
+ * @arg @ref LL_ADC_CHANNEL_1 (3)
+ * @arg @ref LL_ADC_CHANNEL_2 (3)
+ * @arg @ref LL_ADC_CHANNEL_3 (3)
+ * @arg @ref LL_ADC_CHANNEL_4 (3)
+ * @arg @ref LL_ADC_CHANNEL_5 (3)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_19
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_VCORE (2)
+ *
+ * (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.
+ * (2) On STM32U5, parameter available only on ADC instance: ADC4.
+ * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).
+ * (1, 2) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ * @param __GROUP__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_GROUP_REGULAR
+ * @arg @ref LL_ADC_GROUP_INJECTED
+ * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_AWD_DISABLE
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC4_REG (0)(2)
+ * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC4_REG (0)(2)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC4_REG (2)
+ * @arg @ref LL_ADC_AWD_CH_VBAT_ADC4_REG (2)
+ * @arg @ref LL_ADC_AWD_CH_VCORE_REG (2)
+ *
+ * (0) On STM32U5, parameter available only on analog watchdog number: AWD1.
+ * (1) On STM32U5, parameter available only on ADC instance: ADC1/2.
+ * (2) On STM32U5, parameter available only on ADC instance: ADC4.
+ */
+#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
+ (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
+ ? (((__CHANNEL__) & ADC_AWD_CHANNEL_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) \
+ : \
+ ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
+ ? (((__CHANNEL__) & ADC_AWD_CHANNEL_MASK) | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) \
+ : \
+ (((__CHANNEL__) & ADC_AWD_CHANNEL_MASK) | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) \
+ )
+
+/**
+ * @brief Helper macro to set the value of ADC analog watchdog threshold high
+ * or low in function of ADC resolution, when ADC resolution is
+ * different of 14 bits in case of ADC1 and 12 bits in case of ADC4.
+ * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds().
+ * Example, with a ADC resolution of 8 bits, to set the value of
+ * analog watchdog threshold high (on 8 bits):
+ * LL_ADC_SetAnalogWDThresholds
+ * (< ADCx param >,
+ * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, )
+ * );
+ * @param __ADC_INSTANCE__ ADC instance
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_14B (1)
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B (2)
+ * @param __AWD_THRESHOLD__ Value between Min_Data=0x000000 and Max_Data=0x1FFFFFF, In case of ADC1 insatnce
+ * __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF, In case of ADC4 insatnce
+ * @retval In case of ADC1 insatnce, Value between Min_Data=0x000000 and Max_Data=0x1FFFFFF
+ * In case of ADC4 insatnce, Value between Min_Data=0x000 and Max_Data=0xFFF
+ *
+ * (1): Only for ADC1 instance
+ * (2): Only for ADC4 insatnce
+ */
+#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_INSTANCE__, __ADC_RESOLUTION__, __AWD_THRESHOLD__) \
+ (((__ADC_INSTANCE__) == ADC1) \
+ ? ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U ))) \
+ : \
+ ((__AWD_THRESHOLD__) << ((__LL_ADC_RESOLUTION_ADC1_TO_ADC4(__ADC_RESOLUTION__)) \
+ >> (ADC_CFGR_RES_BITOFFSET_POS - 1U ))) \
+ )
+
+/**
+ * @brief Helper macro to get the value of ADC analog watchdog threshold high
+ * or low in function of ADC resolution, when ADC resolution is
+ * different of 14 bits in case of ADC1 and 12 bits in case of ADC4.
+ * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
+ * Example, with a ADC resolution of 8 bits, to get the value of
+ * analog watchdog threshold high (on 8 bits):
+ * < threshold_value_8_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
+ * (LL_ADC_RESOLUTION_8B,
+ * LL_ADC_GetAnalogWDThresholds(, LL_ADC_AWD_THRESHOLD_HIGH)
+ * );
+ * @param __ADC_INSTANCE__ ADC instance
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_14B (1)
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B (2)
+ * @param __AWD_THRESHOLD__ Value between Min_Data=0x000000 and Max_Data=0x1FFFFFF, In case of ADC1 insatnce
+ * __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF, In case of ADC4 insatnce
+ * @retval In case of ADC1 insatnce, Value between Min_Data=0x000000 and Max_Data=0x1FFFFFF
+ * In case of ADC4 insatnce, Value between Min_Data=0x000 and Max_Data=0xFFF
+ *
+ * (1): Only for ADC1 instance
+ * (2): Only for ADC4 insatnce
+ */
+#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_INSTANCE__, __ADC_RESOLUTION__, __AWD_THRESHOLD__) \
+ (((__ADC_INSTANCE__) == ADC1) \
+ ? ((__AWD_THRESHOLD__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U ))) \
+ : \
+ ((__AWD_THRESHOLD__) >> ((__LL_ADC_RESOLUTION_ADC1_TO_ADC4(__ADC_RESOLUTION__)) \
+ >> (ADC_CFGR_RES_BITOFFSET_POS - 1U ))) \
+ )
+
+/**
+ * @brief Helper macro to set the ADC calibration value with both single ended
+ * and differential modes calibration factors concatenated.
+ * @note To be used with function @ref LL_ADC_SetCalibrationOffsetFactor().
+ * Example, to set calibration factors single ended to 0x55
+ * and differential ended to 0x2A:
+ * LL_ADC_SetCalibrationOffsetFactor(
+ * ADC1,
+ * __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
+ * @param __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F
+ * @param __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F
+ * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+ */
+#define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \
+ (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_SINGLEDIFF_CALIB_F_BIT_D_POS) | (__CALIB_FACTOR_SINGLE_ENDED__))
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Helper macro to get the ADC multimode conversion data of ADC master
+ * or ADC slave from raw value with both ADC conversion data concatenated.
+ * @note This macro is intended to be used when multimode transfer by DMA
+ * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
+ * In this case the transferred data need to processed with this macro
+ * to separate the conversion data of ADC master and ADC slave.
+ * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_MASTER
+ * @arg @ref LL_ADC_MULTI_SLAVE
+ * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
+ (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @brief Helper macro to select, from a ADC instance, to which ADC instance
+ * it has a dependence in multimode (ADC master of the corresponding
+ * ADC common instance).
+ * @note In case of device with multimode available and a mix of
+ * ADC instances compliant and not compliant with multimode feature,
+ * ADC instances not compliant with multimode feature are
+ * considered as master instances (do not depend to
+ * any other ADC instance).
+ * @param __ADCx__ ADC instance
+ * @retval __ADCx__ ADC instance master of the corresponding ADC common instance
+ */
+#if defined(ADC2)
+#define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
+ (((__ADCx__) == ADC2) ? (ADC1) : (__ADCx__))
+#else
+#define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) (__ADCx__)
+#endif /* ADC2 */
+/**
+ * @brief Helper macro to select the ADC common instance
+ * to which is belonging the selected ADC instance.
+ * @note ADC common register instance can be used for:
+ * - Set parameters common to several ADC instances
+ * - Multimode (for devices with several ADC instances)
+ * Refer to functions having argument "ADCxy_COMMON" as parameter.
+ * @param __ADCx__ ADC instance
+ * @retval ADC common register instance
+ */
+#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
+ (((__ADCx__) == ADC1) ? (ADC12_COMMON) : (ADC4_COMMON))
+
+/**
+ * @brief Helper macro to check if all ADC instances sharing the same
+ * ADC common instance are disabled.
+ * @note This check is required by functions with setting conditioned to
+ * ADC state:
+ * All ADC instances of the ADC common group must be disabled.
+ * Refer to functions having argument "ADCxy_COMMON" as parameter.
+ * @note On devices with only 1 ADC common instance, parameter of this macro
+ * is useless and can be ignored (parameter kept for compatibility
+ * with devices featuring several ADC common instances).
+ * @param __ADCXY_COMMON__ ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Value "0" if all ADC instances sharing the same ADC common instance
+ * are disabled.
+ * Value "1" if at least one ADC instance sharing the same ADC common instance
+ * is enabled.
+ */
+#if defined(ADC2)
+#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
+ (((__ADCXY_COMMON__) == ADC12_COMMON) ? (LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2)) : (LL_ADC_IsEnabled(ADC4)))
+#else
+#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
+ (((__ADCXY_COMMON__) == ADC12_COMMON) ? (LL_ADC_IsEnabled(ADC1)) : (LL_ADC_IsEnabled(ADC4)))
+#endif /* ADC2 */
+
+/**
+ * @brief Helper macro to define the ADC conversion data full-scale digital
+ * value corresponding to the selected ADC resolution.
+ * @note ADC conversion data full-scale corresponds to voltage range
+ * determined by analog voltage references Vref+ and Vref-
+ * (refer to reference manual).
+ * @param __ADC_INSTANCE__ ADC instance
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_14B
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)
+ */
+#define __LL_ADC_DIGITAL_SCALE(__ADC_INSTANCE__, __ADC_RESOLUTION__) \
+ (((__ADC_INSTANCE__) == ADC1) \
+ ?((0x3FFFUL) >> (((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) & 0x6UL)) \
+ : \
+ ((0xFFFUL) >> ((__LL_ADC_RESOLUTION_ADC1_TO_ADC4(__ADC_RESOLUTION__) \
+ >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) & 0x6UL)) \
+ )
+
+/**
+ * @brief Helper macro to convert the ADC conversion data from
+ * a resolution to another resolution.
+ * @param __ADC_INSTANCE__ ADC instance
+ * @param __DATA__ ADC conversion data to be converted
+ * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
+ * This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_14B (1)
+ * @arg @ref LL_ADC_RESOLUTION_12B (2)
+ * @arg @ref LL_ADC_RESOLUTION_10B (2)
+ * @arg @ref LL_ADC_RESOLUTION_8B (2)
+ * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
+ * This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_14B (1)
+ * @arg @ref LL_ADC_RESOLUTION_12B (2)
+ * @arg @ref LL_ADC_RESOLUTION_10B (2)
+ * @arg @ref LL_ADC_RESOLUTION_8B (2)
+ * (1): Specific to ADC1 instance
+ * (2): Common to all instances but different bits positions
+ * @retval ADC conversion data to the requested resolution
+ */
+#define __LL_ADC_CONVERT_DATA_RESOLUTION(__ADC_INSTANCE__, __DATA__,\
+ __ADC_RESOLUTION_CURRENT__,\
+ __ADC_RESOLUTION_TARGET__) \
+(((__ADC_INSTANCE__) == ADC1) \
+ ?((__DATA__) \
+ << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
+ >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
+ : \
+ ((__DATA__) \
+ << ((__LL_ADC_RESOLUTION_ADC1_TO_ADC4(__ADC_RESOLUTION_CURRENT__)) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
+ >> ((__LL_ADC_RESOLUTION_ADC1_TO_ADC4(__ADC_RESOLUTION_TARGET__)) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
+)
+
+/**
+ * @brief Helper macro to calculate the voltage (unit: mVolt)
+ * corresponding to a ADC conversion data (unit: digital value).
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+ * @param __ADC_DATA__ ADC conversion data (resolution 16 bits)
+ * (unit: digital value).
+ * @param __ADC_INSTANCE__ ADC instance
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_14B (1)
+ * @arg @ref LL_ADC_RESOLUTION_12B (3)
+ * @arg @ref LL_ADC_RESOLUTION_10B (3)
+ * @arg @ref LL_ADC_RESOLUTION_8B (3)
+ * @arg @ref LL_ADC_RESOLUTION_6B (2)
+ * (1): Specific to ADC1 instance
+ * (2): Specific to ADC4 instance
+ * (3): Common to all instances but different bits positions
+ * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+ */
+#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__ADC_INSTANCE__, __VREFANALOG_VOLTAGE__,\
+ __ADC_DATA__, \
+ __ADC_RESOLUTION__) \
+((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
+ / __LL_ADC_DIGITAL_SCALE(__ADC_INSTANCE__, __ADC_RESOLUTION__) \
+)
+
+/**
+ * @brief Helper macro to calculate analog reference voltage (Vref+)
+ * (unit: mVolt) from ADC conversion data of internal voltage
+ * reference VrefInt.
+ * @note Computation is using VrefInt calibration value
+ * stored in system memory for each device during production.
+ * @note This voltage depends on user board environment: voltage level
+ * connected to pin Vref+.
+ * On devices with small package, the pin Vref+ is not present
+ * and internally bonded to pin Vdda.
+ * @note On this STM32 series, calibration data of internal voltage reference
+ * VrefInt corresponds to a resolution of 16 bits,
+ * this is the recommended ADC resolution to convert voltage of
+ * internal voltage reference VrefInt.
+ * Otherwise, this macro performs the processing to scale
+ * ADC conversion data to 14 bits.
+ * @param __ADC_INSTANCE__ ADC instance
+ * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 16 bits)
+ * of internal voltage reference VrefInt (unit: digital value).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_14B (1)
+ * @arg @ref LL_ADC_RESOLUTION_12B (3)
+ * @arg @ref LL_ADC_RESOLUTION_10B (3)
+ * @arg @ref LL_ADC_RESOLUTION_8B (3)
+ * @arg @ref LL_ADC_RESOLUTION_6B (2)
+ * (1): Specific to ADC1 instance
+ * (2): Specific to ADC4 instance
+ * (3): Common to all instances but different bits positions
+ * @retval Analog reference voltage (unit: mV)
+ */
+#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__ADC_INSTANCE__, __VREFINT_ADC_DATA__, \
+ __ADC_RESOLUTION__) \
+(((__ADC_INSTANCE__) == ADC1) \
+ ?((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
+ / __LL_ADC_CONVERT_DATA_RESOLUTION((__ADC_INSTANCE__), (__VREFINT_ADC_DATA__),\
+ (__ADC_RESOLUTION__), \
+ LL_ADC_RESOLUTION_14B) \
+ : \
+ ((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
+ / __LL_ADC_CONVERT_DATA_RESOLUTION((__ADC_INSTANCE__), (__VREFINT_ADC_DATA__),\
+ (__ADC_RESOLUTION__), \
+ LL_ADC_RESOLUTION_12B) \
+)
+
+/**
+ * @brief Helper macro to calculate the temperature (unit: degree Celsius)
+ * from ADC conversion data of internal temperature sensor.
+ * @note Computation is using temperature sensor calibration values
+ * stored in system memory for each device during production.
+ * @note Calculation formula:
+ * Temperature = ((TS_ADC_DATA - TS_CAL1)
+ * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
+ * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
+ * with TS_ADC_DATA = temperature sensor raw data measured by ADC
+ * Avg_Slope = (TS_CAL2 - TS_CAL1)
+ * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
+ * TS_CAL1 = equivalent TS_ADC_DATA at temperature
+ * TEMP_DEGC_CAL1 (calibrated in factory)
+ * TS_CAL2 = equivalent TS_ADC_DATA at temperature
+ * TEMP_DEGC_CAL2 (calibrated in factory)
+ * Caution: Calculation relevancy under reserve that calibration
+ * parameters are correct (address and data).
+ * To calculate temperature using temperature sensor
+ * datasheet typical values (generic values less, therefore
+ * less accurate than calibrated values),
+ * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
+ * @note As calculation input, the analog reference voltage (Vref+) must be
+ * defined as it impacts the ADC LSB equivalent voltage.
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @note On this STM32 series, calibration data of temperature sensor
+ * corresponds to a resolution of 14 bits,
+ * this is the recommended ADC resolution to convert voltage of
+ * temperature sensor.
+ * Otherwise, this macro performs the processing to scale
+ * ADC conversion data to 14 bits.
+ * @param __ADC_INSTANCE__ ADC instance
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+ * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
+ * temperature sensor (unit: digital value).
+ * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
+ * sensor voltage has been measured.
+ * This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_14B (1)
+ * @arg @ref LL_ADC_RESOLUTION_12B (3)
+ * @arg @ref LL_ADC_RESOLUTION_10B (3)
+ * @arg @ref LL_ADC_RESOLUTION_8B (3)
+ * @arg @ref LL_ADC_RESOLUTION_6B (2)
+ * (1): Specific to ADC1 instance
+ * (2): Specific to ADC4 instance
+ * (3): Common to all instances but different bits positions
+ * @retval Temperature (unit: degree Celsius)
+ */
+#define __LL_ADC_CALC_TEMPERATURE(__ADC_INSTANCE__, __VREFANALOG_VOLTAGE__, \
+ __TEMPSENSOR_ADC_DATA__, \
+ __ADC_RESOLUTION__) \
+(((__ADC_INSTANCE__) == ADC1) \
+ ?(((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__ADC_INSTANCE__), (__TEMPSENSOR_ADC_DATA__), \
+ (__ADC_RESOLUTION__), \
+ LL_ADC_RESOLUTION_14B) \
+ * (__VREFANALOG_VOLTAGE__)) \
+ / TEMPSENSOR_CAL_VREFANALOG) \
+ - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
+ ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
+ ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
+ ) + TEMPSENSOR_CAL1_TEMP \
+ ) \
+ : \
+ (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__ADC_INSTANCE__), (__TEMPSENSOR_ADC_DATA__), \
+ (__ADC_RESOLUTION__), \
+ LL_ADC_RESOLUTION_12B) \
+ * (__VREFANALOG_VOLTAGE__)) \
+ / TEMPSENSOR_CAL_VREFANALOG) \
+ - (int32_t) (*TEMPSENSOR_CAL1_ADDR >> 2 )) \
+ ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
+ ) / (int32_t)((int32_t)(*TEMPSENSOR_CAL2_ADDR >> 2 ) - (int32_t)(*TEMPSENSOR_CAL1_ADDR >> 2) ) \
+ ) + TEMPSENSOR_CAL1_TEMP \
+ ) \
+)
+
+/**
+ * @brief Helper macro to calculate the temperature (unit: degree Celsius)
+ * from ADC conversion data of internal temperature sensor.
+ * @note Computation is using temperature sensor typical values
+ * (refer to device datasheet).
+ * @note Calculation formula:
+ * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
+ * / Avg_Slope + CALx_TEMP
+ * with TS_ADC_DATA = temperature sensor raw data measured by ADC
+ * (unit: digital value)
+ * Avg_Slope = temperature sensor slope
+ * (unit: uV/Degree Celsius)
+ * TS_TYP_CALx_VOLT = temperature sensor digital value at
+ * temperature CALx_TEMP (unit: mV)
+ * Caution: Calculation relevancy under reserve the temperature sensor
+ * of the current device has characteristics in line with
+ * datasheet typical values.
+ * If temperature sensor calibration values are available on
+ * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
+ * temperature calculation will be more accurate using
+ * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
+ * @note As calculation input, the analog reference voltage (Vref+) must be
+ * defined as it impacts the ADC LSB equivalent voltage.
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @note ADC measurement data must correspond to a resolution of 14 bits
+ * (full scale digital value 4095). If not the case, the data must be
+ * preliminarily rescaled to an equivalent resolution of 14 bits.
+ * @param __ADC_INSTANCE__ ADC instance
+ * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value
+ * (unit: uV/DegCelsius).
+ * On STM32U5, refer to device datasheet parameter "Avg_Slope".
+ * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value
+ * (at temperature and Vref+ defined in parameters below) (unit: mV).
+ * On STM32U5, refer to device datasheet parameter "V30"
+ * (corresponding to TS_CAL1).
+ * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage
+ * see parameter above) is corresponding (unit: mV)
+ * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
+ * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
+ * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
+ * This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_14B (1)
+ * @arg @ref LL_ADC_RESOLUTION_12B (3)
+ * @arg @ref LL_ADC_RESOLUTION_10B (3)
+ * @arg @ref LL_ADC_RESOLUTION_8B (3)
+ * @arg @ref LL_ADC_RESOLUTION_6B (2)
+ * (1): Specific to ADC1 instance
+ * (2): Specific to ADC4 instance
+ * (3): Common to all instances but different bits positions
+ * @retval Temperature (unit: degree Celsius)
+ */
+#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__ADC_INSTANCE__, __TEMPSENSOR_TYP_AVGSLOPE__, \
+ __TEMPSENSOR_TYP_CALX_V__, \
+ __TEMPSENSOR_CALX_TEMP__, \
+ __VREFANALOG_VOLTAGE__, \
+ __TEMPSENSOR_ADC_DATA__, \
+ __ADC_RESOLUTION__) \
+((( ((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
+ / __LL_ADC_DIGITAL_SCALE(__ADC_INSTANCE__, __ADC_RESOLUTION__)) \
+ * 1000UL) \
+ - \
+ (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
+ * 1000UL) \
+ ) \
+ ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \
+ ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \
+)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
+ * @{
+ */
+
+/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
+ * @{
+ */
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Function to help to configure DMA transfer from ADC: retrieve the
+ * ADC register address from ADC instance and a list of ADC registers
+ * intended to be used (most commonly) with DMA transfer.
+ * @note These ADC registers are data registers:
+ * when ADC conversion data is available in ADC data registers,
+ * ADC generates a DMA transfer request.
+ * @note This macro is intended to be used with LL DMA driver, refer to
+ * function "LL_DMA_ConfigAddresses()".
+ * Example:
+ * LL_DMA_ConfigAddresses(DMA1,
+ * LL_DMA_CHANNEL_1,
+ * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
+ * (uint32_t)&< array or variable >,
+ * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
+ * @note For devices with several ADC: in multimode, some devices
+ * use a different data register outside of ADC instance scope
+ * (common data register). This macro manages this register difference,
+ * only ADC instance has to be set as parameter.
+ * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr
+ * CDR RDATA_MST LL_ADC_DMA_GetRegAddr
+ * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
+ * @param ADCx ADC instance
+ * @param RegisterValue This parameter can be one of the following values:
+ * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
+ * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
+ *
+ * (1) Available on devices with several ADC instances.
+ * @retval ADC register address
+ */
+__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t RegisterValue)
+{
+ uint32_t data_reg_addr;
+
+ if (RegisterValue == LL_ADC_DMA_REG_REGULAR_DATA)
+ {
+ /* Retrieve address of register DR */
+ data_reg_addr = (uint32_t) &(ADCx->DR);
+ }
+ else /* (RegisterValue == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
+ {
+ /* Retrieve address of register CDR */
+ data_reg_addr = (uint32_t) &((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
+ }
+
+ return data_reg_addr;
+}
+#else
+/**
+ * @brief Function to help to configure DMA transfer from ADC: retrieve the
+ * ADC register address from ADC instance and a list of ADC registers
+ * intended to be used (most commonly) with DMA transfer.
+ * @note These ADC registers are data registers:
+ * when ADC conversion data is available in ADC data registers,
+ * ADC generates a DMA transfer request.
+ * @note This macro is intended to be used with LL DMA driver, refer to
+ * function "LL_DMA_ConfigAddresses()".
+ * Example:
+ * LL_DMA_ConfigAddresses(DMA1,
+ * LL_DMA_CHANNEL_1,
+ * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
+ * (uint32_t)&< array or variable >,
+ * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
+ * @note For devices with several ADC: in multimode, some devices
+ * use a different data register outside of ADC instance scope
+ * (common data register). This macro manages this register difference,
+ * only ADC instance has to be set as parameter.
+ * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr
+ * @param ADCx ADC instance
+ * @param RegisterValue This parameter can be one of the following values:
+ * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
+ * @retval ADC register address
+ */
+__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t RegisterValue)
+{
+ /* Prevent unused argument(s) compilation warning */
+ (void)(RegisterValue);
+
+ /* Retrieve address of register DR */
+ return (uint32_t) &(ADCx->DR);
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope:
+ * common to several ADC instances
+ * @{
+ */
+
+/**
+ * @brief Set parameter common to several ADC: Clock source and prescaler.
+ * @note On this STM32 series, if ADC group injected is used, some
+ * clock ratio constraints between ADC clock and AHB clock
+ * must be respected.
+ * Refer to reference manual.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * All ADC instances of the ADC common group must be disabled.
+ * This check can be done with function @ref LL_ADC_IsEnabled() for each
+ * ADC instance or by using helper macro helper macro
+ * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+ * @rmtoll CCR CKMODE LL_ADC_SetCommonClock
+ * CCR PRESC LL_ADC_SetCommonClock
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param CommonClock This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
+{
+ MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_PRESC, CommonClock);
+}
+
+/**
+ * @brief Get parameter common to several ADC: Clock source and prescaler.
+ * @rmtoll CCR CKMODE LL_ADC_GetCommonClock
+ * CCR PRESC LL_ADC_GetCommonClock
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_PRESC));
+}
+
+/**
+ * @brief Set parameter common to several ADC: measurement path to
+ * internal channels (VrefInt, temperature sensor, ...).
+ * Add paths to the current configuration.
+ * @note One or several values can be selected.
+ * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+ * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+ * @note Stabilization time of measurement path to internal channel:
+ * After enabling internal paths, before starting ADC conversion,
+ * a delay is required for internal voltage reference and
+ * temperature sensor stabilization time.
+ * Refer to device datasheet.
+ * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
+ * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US,
+ * @note ADC internal channel sampling time constraint:
+ * For ADC conversion of internal channels,
+ * a sampling time minimum value is required.
+ * Refer to device datasheet.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * All ADC instances of the ADC common group must be disabled.
+ * This check can be done with function @ref LL_ADC_IsEnabled() for each
+ * ADC instance or by using helper macro helper macro
+ * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+ * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd
+ * CCR VSENSESEL LL_ADC_SetCommonPathInternalChAdd
+ * CCR VBATEN LL_ADC_SetCommonPathInternalChAdd
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param PathInternal This parameter can be a combination of the following values:
+ * @arg @ref LL_ADC_PATH_INTERNAL_NONE
+ * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+ * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+ * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
+{
+ SET_BIT(ADCxy_COMMON->CCR, PathInternal);
+}
+
+/**
+ * @brief Set parameter common to several ADC: measurement path to
+ * internal channels (VrefInt, temperature sensor, ...).
+ * Remove paths to the current configuration.
+ * @note One or several values can be selected.
+ * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+ * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * All ADC instances of the ADC common group must be disabled.
+ * This check can be done with function @ref LL_ADC_IsEnabled() for each
+ * ADC instance or by using helper macro helper macro
+ * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+ * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem
+ * CCR VSENSESEL LL_ADC_SetCommonPathInternalChRem
+ * CCR VBATEN LL_ADC_SetCommonPathInternalChRem
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param PathInternal This parameter can be a combination of the following values:
+ * @arg @ref LL_ADC_PATH_INTERNAL_NONE
+ * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+ * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+ * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
+{
+ CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
+}
+
+/**
+ * @brief Set parameter common to several ADC: measurement path to internal
+ * channels (VrefInt, temperature sensor, ...).
+ * @note One or several values can be selected.
+ * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+ * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+ * @note Stabilization time of measurement path to internal channel:
+ * After enabling internal paths, before starting ADC conversion,
+ * a delay is required for internal voltage reference and
+ * temperature sensor stabilization time.
+ * Refer to device datasheet.
+ * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
+ * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
+ * @note ADC internal channel sampling time constraint:
+ * For ADC conversion of internal channels,
+ * a sampling time minimum value is required.
+ * Refer to device datasheet.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * All ADC instances of the ADC common group must be disabled.
+ * This check can be done with function @ref LL_ADC_IsEnabled() for each
+ * ADC instance or by using helper macro helper macro
+ * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+ * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh
+ * CCR VSENSESEL LL_ADC_SetCommonPathInternalCh
+ * CCR VBATEN LL_ADC_SetCommonPathInternalCh
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param PathInternal This parameter can be a combination of the following values:
+ * @arg @ref LL_ADC_PATH_INTERNAL_NONE
+ * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+ * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+ * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
+{
+ MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSEEN | ADC_CCR_VBATEN, PathInternal);
+}
+
+/**
+ * @brief Get parameter common to several ADC: measurement path to internal
+ * channels (VrefInt, temperature sensor, ...).
+ * @note One or several values can be selected.
+ * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+ * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+ * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh
+ * CCR VSENSESEL LL_ADC_GetCommonPathInternalCh
+ * CCR VBATEN LL_ADC_GetCommonPathInternalCh
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Returned value can be a combination of the following values:
+ * @arg @ref LL_ADC_PATH_INTERNAL_NONE
+ * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+ * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+ * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSEEN | ADC_CCR_VBATEN));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
+ * @{
+ */
+
+/**
+ * @brief Set ADC calibration factor in the mode single-ended
+ * or differential (for devices with differential mode available).
+ * @note This function is intended to set calibration parameters
+ * without having to perform a new calibration using
+ * @ref LL_ADC_StartCalibration().
+ * @note For devices with differential mode available:
+ * Calibration of offset is specific to each of
+ * single-ended and differential modes
+ * (calibration factor must be specified for each of these
+ * differential modes, if used afterwards and if the application
+ * requires their calibration).
+ * Calibration of linearity is common to both
+ * single-ended and differential modes
+ * (calibration factor can be specified only once).
+ * @note In case of setting calibration factors of both modes single ended
+ * and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
+ * both calibration factors must be concatenated.
+ * To perform this processing, use helper macro
+ * @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be enabled, without calibration on going, without conversion
+ * on going on group regular.
+ * @param ADCx ADC instance
+ * @param SingleDiff This parameter can be one of the following values:
+ * @arg @ref LL_ADC_SINGLE_ENDED
+ * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+ * @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
+ * @param CalibrationFactor Value between Min_Data=0x0000 and Max_Data=0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff,
+ uint32_t CalibrationFactor)
+{
+ if (ADCx == ADC1)
+ {
+ CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_LATCH_COEF | ADC_CALFACT_CAPTURE_COEF);
+ MODIFY_REG(ADCx->CR, ADC_CR_ADCALLIN, (0UL << ADC_CR_CALINDEX0_Pos)); /* CalibIndex == 0*/
+ MODIFY_REG(ADCx->CALFACT2,
+ SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
+ CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) \
+ >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) \
+ & ~(SingleDiff & ADC_CALFACT2_CALFACT_S)));
+ SET_BIT(ADCx->CALFACT, ADC_CALFACT_LATCH_COEF);
+ CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CAPTURE_COEF);
+ }
+ else
+ {
+ MODIFY_REG(ADCx->CALFACT, ADC4_CALFACT_CALFACT, CalibrationFactor);
+ }
+}
+
+/**
+ * @brief Get ADC calibration factor in the mode single-ended
+ * or differential (for devices with differential mode available).
+ * @note Calibration factors are set by hardware after performing
+ * a calibration run using function @ref LL_ADC_StartCalibration().
+ * @note For devices with differential mode available:
+ * Calibration of offset is specific to each of
+ * single-ended and differential modes
+ * Calibration of linearity is common to both
+ * single-ended and differential modes
+ * @param ADCx ADC instance
+ * @param SingleDiff This parameter can be one of the following values:
+ * @arg @ref LL_ADC_SINGLE_ENDED
+ * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+ * @retval Value between Min_Data=0x0000 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)
+{
+ /* Retrieve bits with position in register depending on parameter */
+ /* "SingleDiff". */
+ /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */
+ /* containing other bits reserved for other purpose. */
+ if (ADCx == ADC1)
+ {
+ uint32_t temp_CalibOffset;
+ MODIFY_REG(ADCx->CALFACT, ADC_CALFACT_LATCH_COEF, ADC_CALFACT_CAPTURE_COEF);
+ MODIFY_REG(ADCx->CR, ADC_CR_ADCALLIN, (0UL << ADC_CR_CALINDEX0_Pos)); /* CalibIndex == 0*/
+ temp_CalibOffset = (READ_BIT(ADCx->CALFACT2, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) \
+ >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
+ CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CAPTURE_COEF);
+ return temp_CalibOffset;
+ }
+ else
+ {
+ return (uint32_t)(READ_BIT(ADCx->CALFACT, ADC4_CALFACT_CALFACT));
+ }
+}
+
+/**
+ * @brief Set ADC Linear calibration factor in the mode single-ended.
+ * @note This function is intended to set linear calibration parameters
+ * without having to perform a new calibration using
+ * @ref LL_ADC_StartCalibration().
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be enabled, without calibration on going, without conversion
+ * on going on group regular.
+ * @rmtoll CALFACT2 LINCALFACT LL_ADC_SetCalibrationLinearFactor
+ * CALFACT2 LINCALFACT LL_ADC_SetCalibrationLinearFactor
+ * @param ADCx ADC instance
+ * @param LinearityWord This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX1
+ * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX2
+ * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX3
+ * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX4
+ * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX5
+ * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX6
+ * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX7
+ * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x3FFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32_t LinearityWord,
+ uint32_t CalibrationFactor)
+{
+ /* Before using this!
+ Make sure ADEN = 1, ADSTART = 0 and JADSTART = 0 (ADC enabled and no conversion is ongoing).
+ --> This should be checked by application.
+ */
+ CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_LATCH_COEF | ADC_CALFACT_CAPTURE_COEF);
+ MODIFY_REG(ADCx->CR, (ADC_CR_CALINDEX3 | ADC_CR_CALINDEX2 | ADC_CR_CALINDEX1 | ADC_CR_CALINDEX0),
+ LinearityWord); /* LinearityWord == CalibIndex (1 to 8 for linearity reading)*/
+ MODIFY_REG(ADCx->CALFACT2, ADC_CALFACT2_CALFACT, CalibrationFactor);
+ SET_BIT(ADCx->CALFACT, ADC_CALFACT_LATCH_COEF);
+ CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CAPTURE_COEF);
+}
+
+/**
+ * @brief Get ADC Linear calibration factor in the mode single-ended.
+ * @note Calibration factors are set by hardware after performing
+ * a calibration run using function @ref LL_ADC_StartCalibration().
+ * @rmtoll CALFACT2 LINCALFACT LL_ADC_GetCalibrationLinearFactor
+ * CALFACT2 LINCALFACT LL_ADC_GetCalibrationLinearFactor
+ * @param ADCx ADC instance
+ * @param LinearityWord This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX1
+ * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX2
+ * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX3
+ * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX4
+ * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX5
+ * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX6
+ * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX7
+ * @retval Value between Min_Data=0x00 and Max_Data=0x3FFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32_t LinearityWord)
+{
+ uint32_t temp_calib_linearity;
+ SET_BIT(ADCx->CALFACT, ADC_CALFACT_CAPTURE_COEF);
+ CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_LATCH_COEF);
+ MODIFY_REG(ADCx->CR, (ADC_CR_CALINDEX3 | ADC_CR_CALINDEX2 | ADC_CR_CALINDEX1 | ADC_CR_CALINDEX0),
+ LinearityWord); /* LinearityWord == CalibIndex (1 to 8 for linearity reading)*/
+ temp_calib_linearity = (uint32_t)(READ_BIT(ADCx->CALFACT2, ADC_CALFACT2_CALFACT_Msk));
+ CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CAPTURE_COEF);
+ return temp_calib_linearity;
+}
+/**
+ * @brief Set ADC resolution.
+ * Refer to reference manual for alignments formats
+ * dependencies to ADC resolutions.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @note if ADC4 instance __LL_ADC_RESOLUTION_ADC1_TO_ADC4() is used to
+ * convert ADC1 to ADC4 resolution
+ * @rmtoll CFGR RES LL_ADC_SetResolution
+ * @param ADCx ADC instance
+ * @param Resolution This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_14B (1)
+ * @arg @ref LL_ADC_RESOLUTION_12B (3)
+ * @arg @ref LL_ADC_RESOLUTION_10B (3)
+ * @arg @ref LL_ADC_RESOLUTION_8B (3)
+ * @arg @ref LL_ADC_RESOLUTION_6B (2)
+ * (1): Specific to ADC1 instance
+ * (2): Specific to ADC4 instance
+ * (3): Common to all instances but different bits positions
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
+{
+ if (ADCx == ADC1)
+ {
+ MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, Resolution);
+ }
+ else /* ADCx == ADC4 */
+ {
+ MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, __LL_ADC_RESOLUTION_ADC1_TO_ADC4(Resolution));
+ }
+}
+
+/**
+ * @brief Get ADC resolution.
+ * Refer to reference manual for alignments formats
+ * dependencies to ADC resolutions.
+ * @rmtoll CFGR RES LL_ADC_GetResolution
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_14B (1)
+ * @arg @ref LL_ADC_RESOLUTION_12B (3)
+ * @arg @ref LL_ADC_RESOLUTION_10B (3)
+ * @arg @ref LL_ADC_RESOLUTION_8B (3)
+ * @arg @ref LL_ADC_RESOLUTION_6B (2)
+ * (1): Specific to ADC1 instance
+ * (2): Specific to ADC4 instance
+ * (3): Common to all instances but different bits positions
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
+{
+ if (ADCx == ADC1)
+ {
+ return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES));
+ }
+ else /* ADCx == ADC4 */
+ {
+ uint32_t temp_Resolution;
+ temp_Resolution = (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES));
+ if (temp_Resolution == (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0))
+ {
+ return LL_ADC_RESOLUTION_6B;
+ }
+ else
+ {
+ return __LL_ADC_RESOLUTION_ADC4_TO_ADC1(temp_Resolution);
+ }
+ }
+}
+
+/**
+ * @brief Set ADC conversion data alignment.
+ * @note Refer to reference manual for alignments formats
+ * dependencies to ADC resolutions.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll CFGR1 ALIGN LL_ADC_SetDataAlignment
+ * @param ADCx ADC instance
+ * @param DataAlignment This parameter can be one of the following values:
+ * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
+ * @arg @ref LL_ADC_DATA_ALIGN_LEFT
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
+{
+ MODIFY_REG(ADCx->CFGR1, ADC4_CFGR1_ALIGN, DataAlignment);
+}
+
+/**
+ * @brief Get ADC conversion data alignment.
+ * @note Refer to reference manual for alignments formats
+ * dependencies to ADC resolutions.
+ * @rmtoll CFGR1 ALIGN LL_ADC_GetDataAlignment
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
+ * @arg @ref LL_ADC_DATA_ALIGN_LEFT
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC4_CFGR1_ALIGN));
+}
+
+/**
+ * @brief Set ADC low power mode.
+ * @note Description of ADC low power modes:
+ * - ADC low power mode "auto wait": Dynamic low power mode,
+ * ADC conversions occurrences are limited to the minimum necessary
+ * in order to reduce power consumption.
+ * New ADC conversion starts only when the previous
+ * unitary conversion data (for ADC group regular)
+ * or previous sequence conversions data (for ADC group injected)
+ * has been retrieved by user software.
+ * In the meantime, ADC remains idle: does not performs any
+ * other conversion.
+ * This mode allows to automatically adapt the ADC conversions
+ * triggers to the speed of the software that reads the data.
+ * Moreover, this avoids risk of overrun for low frequency
+ * applications.
+ * How to use this low power mode:
+ * - It is not recommended to use with interruption or DMA
+ * since these modes have to clear immediately the EOC flag
+ * (by CPU to free the IRQ pending event or by DMA).
+ * Auto wait will work but fort a very short time, discarding
+ * its intended benefit (except specific case of high load of CPU
+ * or DMA transfers which can justify usage of auto wait).
+ * - Do use with polling: 1. Start conversion,
+ * 2. Later on, when conversion data is needed: poll for end of
+ * conversion to ensure that conversion is completed and
+ * retrieve ADC conversion data. This will trig another
+ * ADC conversion start.
+ * - ADC low power mode "auto power-off" (feature available on
+ * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
+ * the ADC automatically powers-off after a conversion and
+ * automatically wakes up when a new conversion is triggered
+ * (with startup time between trigger and start of sampling).
+ * This feature can be combined with low power mode "auto wait".
+ * @note With ADC low power mode "auto wait", the ADC conversion data read
+ * is corresponding to previous ADC conversion start, independently
+ * of delay during which ADC was idle.
+ * Therefore, the ADC conversion data may be outdated: does not
+ * correspond to the current voltage level on the selected
+ * ADC channel.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR AUTDLY LL_ADC_SetLowPowerMode
+ * @param ADCx ADC instance
+ * @param LowPowerMode This parameter can be one of the following values:
+ * @arg @ref LL_ADC_LP_MODE_NONE
+ * @arg @ref LL_ADC_LP_AUTOWAIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
+{
+ if (ADCx != ADC4) /* ADC1 or ADC2 */
+ {
+ MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_AUTDLY, LowPowerMode);
+ }
+ else
+ {
+ MODIFY_REG(ADCx->CFGR1, ADC4_CFGR1_WAIT, LowPowerMode);
+ MODIFY_REG(ADCx->PW, ADC4_PW_AUTOFF, LowPowerMode);
+ }
+}
+
+/**
+ * @brief Get ADC low power mode:
+ * @note Description of ADC low power modes:
+ * - ADC low power mode "auto wait": Dynamic low power mode,
+ * ADC conversions occurrences are limited to the minimum necessary
+ * in order to reduce power consumption.
+ * New ADC conversion starts only when the previous
+ * unitary conversion data (for ADC group regular)
+ * or previous sequence conversions data (for ADC group injected)
+ * has been retrieved by user software.
+ * In the meantime, ADC remains idle: does not performs any
+ * other conversion.
+ * This mode allows to automatically adapt the ADC conversions
+ * triggers to the speed of the software that reads the data.
+ * Moreover, this avoids risk of overrun for low frequency
+ * applications.
+ * How to use this low power mode:
+ * - It is not recommended to use with interruption or DMA
+ * since these modes have to clear immediately the EOC flag
+ * (by CPU to free the IRQ pending event or by DMA).
+ * Auto wait will work but fort a very short time, discarding
+ * its intended benefit (except specific case of high load of CPU
+ * or DMA transfers which can justify usage of auto wait).
+ * - Do use with polling: 1. Start conversion,
+ * 2. Later on, when conversion data is needed: poll for end of
+ * conversion to ensure that conversion is completed and
+ * retrieve ADC conversion data. This will trig another
+ * ADC conversion start.
+ * - ADC low power mode "auto power-off" (feature available on
+ * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
+ * the ADC automatically powers-off after a conversion and
+ * automatically wakes up when a new conversion is triggered
+ * (with startup time between trigger and start of sampling).
+ * This feature can be combined with low power mode "auto wait".
+ * @note With ADC low power mode "auto wait", the ADC conversion data read
+ * is corresponding to previous ADC conversion start, independently
+ * of delay during which ADC was idle.
+ * Therefore, the ADC conversion data may be outdated: does not
+ * correspond to the current voltage level on the selected
+ * ADC channel.
+ * @rmtoll CFGR AUTDLY LL_ADC_GetLowPowerMode
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_LP_MODE_NONE
+ * @arg @ref LL_ADC_LP_AUTOWAIT
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
+{
+ if (ADCx != ADC4) /* ADC1 or ADC2 */
+ {
+ return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_AUTDLY));
+ }
+ else
+ {
+ return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC4_CFGR1_WAIT));
+ }
+
+}
+
+/**
+ * @brief Set ADC selected offset number 1, 2, 3 or 4.
+ * @note This function set the 2 items of offset configuration:
+ * - ADC channel to which the offset programmed will be applied
+ * (independently of channel mapped on ADC group regular
+ * or group injected)
+ * - Offset level (offset to be subtracted from the raw
+ * converted data).
+ * @note Caution: Offset format is dependent to ADC resolution:
+ * offset has to be left-aligned on bit 11, the LSB (right bits)
+ * are set to 0.
+ * @note This function enables the offset, by default. It can be forced
+ * to disable state using function LL_ADC_SetOffsetState().
+ * @note If a channel is mapped on several offsets numbers, only the offset
+ * with the lowest value is considered for the subtraction.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @note On STM32U5, some fast channels are available: fast analog inputs
+ * coming from GPIO pads (ADC_IN0..5).
+ * @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset
+ * OFR1 OFFSET1 LL_ADC_SetOffset
+ * OFR1 OFFSET1_EN LL_ADC_SetOffset
+ * OFR2 OFFSET2_CH LL_ADC_SetOffset
+ * OFR2 OFFSET2 LL_ADC_SetOffset
+ * OFR2 OFFSET2_EN LL_ADC_SetOffset
+ * OFR3 OFFSET3_CH LL_ADC_SetOffset
+ * OFR3 OFFSET3 LL_ADC_SetOffset
+ * OFR3 OFFSET3_EN LL_ADC_SetOffset
+ * OFR4 OFFSET4_CH LL_ADC_SetOffset
+ * OFR4 OFFSET4 LL_ADC_SetOffset
+ * OFR4 OFFSET4_EN LL_ADC_SetOffset
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0 (3)
+ * @arg @ref LL_ADC_CHANNEL_1 (3)
+ * @arg @ref LL_ADC_CHANNEL_2 (3)
+ * @arg @ref LL_ADC_CHANNEL_3 (3)
+ * @arg @ref LL_ADC_CHANNEL_4 (3)
+ * @arg @ref LL_ADC_CHANNEL_5 (3)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_19
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
+ *
+ * (1) On STM32U5, parameter available only on ADC instance: ADC1/2.
+ * (2) On STM32U5, parameter available only on ADC instance: ADC4.
+ * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).
+ * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0x1FFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
+{
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+ MODIFY_REG(*preg,
+ ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
+ ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) << 1UL) | OffsetLevel);
+}
+
+/**
+ * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
+ * Channel to which the offset programmed will be applied
+ * (independently of channel mapped on ADC group regular
+ * or group injected)
+ * @note Usage of the returned channel number:
+ * - To reinject this channel into another function LL_ADC_xxx:
+ * the returned channel number is only partly formatted on definition
+ * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+ * with parts of literals LL_ADC_CHANNEL_x or using
+ * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Then the selected literal LL_ADC_CHANNEL_x can be used
+ * as parameter for another function.
+ * - To get the channel number in decimal format:
+ * process the returned value with the helper macro
+ * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * @note On STM32U5, some fast channels are available: fast analog inputs
+ * coming from GPIO pads (ADC_IN0..5).
+ * @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel
+ * OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel
+ * OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel
+ * OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0 (3)
+ * @arg @ref LL_ADC_CHANNEL_1 (3)
+ * @arg @ref LL_ADC_CHANNEL_2 (3)
+ * @arg @ref LL_ADC_CHANNEL_3 (3)
+ * @arg @ref LL_ADC_CHANNEL_4 (3)
+ * @arg @ref LL_ADC_CHANNEL_5 (3)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_19
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
+ *
+ * (1) On STM32U5, parameter available only on ADC instance: ADC1/2.
+ * (2) On STM32U5, parameter available only on ADC instance: ADC4.
+ * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).
+ * (1, 2) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)
+{
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+ return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
+}
+
+/**
+ * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
+ * Offset level (offset to be subtracted from the raw
+ * converted data).
+ * @note Caution: Offset format is dependent to ADC resolution:
+ * offset has to be left-aligned on bit 11, the LSB (right bits)
+ * are set to 0.
+ * @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel
+ * OFR2 OFFSET2 LL_ADC_GetOffsetLevel
+ * OFR3 OFFSET3 LL_ADC_GetOffsetLevel
+ * OFR4 OFFSET4 LL_ADC_GetOffsetLevel
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @retval Value between Min_Data=0x000 and Max_Data=0x1FFFFFF
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)
+{
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+ return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
+}
+
+/**
+ * @brief Set for the ADC selected offset number 1, 2, 3 or 4:
+ * choose offset sign.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll OFR1 OFFSETPOS LL_ADC_SetOffsetSign
+ * OFR2 OFFSETPOS LL_ADC_SetOffsetSign
+ * OFR3 OFFSETPOS LL_ADC_SetOffsetSign
+ * OFR4 OFFSETPOS LL_ADC_SetOffsetSign
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @param OffsetSign This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
+ * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign)
+{
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+ MODIFY_REG(*preg, ADC_OFR1_OFFSETPOS, OffsetSign);
+}
+
+/**
+ * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
+ * offset sign if positive or negative.
+ * @rmtoll OFR1 OFFSETPOS LL_ADC_GetOffsetSign
+ * OFR2 OFFSETPOS LL_ADC_GetOffsetSign
+ * OFR3 OFFSETPOS LL_ADC_GetOffsetSign
+ * OFR4 OFFSETPOS LL_ADC_GetOffsetSign
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
+ * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety)
+{
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+ return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSETPOS);
+}
+
+/**
+ * @brief Set Signed saturation for the ADC selected offset number 1, 2, 3 or 4:
+ * signed offset saturation if enabled or disabled.
+ * @rmtoll OFR1 SSAT LL_ADC_SetOffsetSignedSaturation
+ * OFR2 SSAT LL_ADC_SetOffsetSignedSaturation
+ * OFR3 SSAT LL_ADC_SetOffsetSignedSaturation
+ * OFR4 SSAT LL_ADC_SetOffsetSignedSaturation
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @param OffsetSignedSaturation This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE
+ * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE
+ * @retval Returned None
+ */
+__STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety,
+ uint32_t OffsetSignedSaturation)
+{
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+ MODIFY_REG(*preg, ADC_OFR1_SSAT, OffsetSignedSaturation);
+}
+
+/**
+ * @brief Get Signed saturation for the ADC selected offset number 1, 2, 3 or 4:
+ * signed offset saturation if enabled or disabled.
+ * @rmtoll OFR1 SSAT LL_ADC_GetOffsetSignedSaturation
+ * OFR2 SSAT LL_ADC_GetOffsetSignedSaturation
+ * OFR3 SSAT LL_ADC_GetOffsetSignedSaturation
+ * OFR4 SSAT LL_ADC_GetOffsetSignedSaturation
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE
+ * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety)
+{
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+ return (uint32_t) READ_BIT(*preg, ADC_OFR1_SSAT);
+}
+
+/**
+ * @brief Set Unsigned saturation for the ADC selected offset number 1, 2, 3 or 4:
+ * signed offset saturation if enabled or disabled.
+ * @rmtoll OFR1 USAT LL_ADC_SetOffsetUnsignedSaturation
+ * OFR2 USAT LL_ADC_SetOffsetUnsignedSaturation
+ * OFR3 USAT LL_ADC_SetOffsetUnsignedSaturation
+ * OFR4 USAT LL_ADC_SetOffsetUnsignedSaturation
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @param OffsetUnsignedSaturation This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_UNSIGNED_SATURATION_ENABLE
+ * @arg @ref LL_ADC_OFFSET_UNSIGNED_SATURATION_DISABLE
+ * @retval Returned None
+ */
+__STATIC_INLINE void LL_ADC_SetOffsetUnsignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety,
+ uint32_t OffsetUnsignedSaturation)
+{
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+ MODIFY_REG(*preg, ADC_OFR1_USAT, OffsetUnsignedSaturation);
+}
+
+/**
+ * @brief Get Unsigned saturation for the ADC selected offset number 1, 2, 3 or 4:
+ * signed offset saturation if enabled or disabled.
+ * @rmtoll OFR1 USAT LL_ADC_GetOffsetUnsignedSaturation
+ * OFR2 USAT LL_ADC_GetOffsetUnsignedSaturation
+ * OFR3 USAT LL_ADC_GetOffsetUnsignedSaturation
+ * OFR4 USAT LL_ADC_GetOffsetUnsignedSaturation
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_UNSIGNED_SATURATION_ENABLE
+ * @arg @ref LL_ADC_OFFSET_UNSIGNED_SATURATION_DISABLE
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetUnsignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety)
+{
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+ return (uint32_t) READ_BIT(*preg, ADC_OFR1_USAT);
+}
+
+/**
+ * @brief Set ADC gain compensation.
+ * @note This function set the gain compensation coefficient
+ * that is applied to raw converted data using the formula:
+ * DATA = DATA(raw) * (gain compensation coef) / 4096
+ * @note This function enables the gain compensation if given
+ * coefficient is above 0, otherwise it disables it.
+ * @note Gain compensation when enabled is applied to all channels.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll GCOMP GCOMPCOEFF LL_ADC_SetGainCompensation
+ * CFGR2 GCOMP LL_ADC_SetGainCompensation
+ * @param ADCx ADC instance
+ * @param GainCompensation This parameter can be:
+ * 0 Gain compensation will be disabled and value set to 0
+ * 1 -> 16393 Gain compensation will be enabled with specified value
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetGainCompensation(ADC_TypeDef *ADCx, uint32_t GainCompensation)
+{
+ MODIFY_REG(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF, GainCompensation);
+ MODIFY_REG(ADCx->GCOMP, ADC_GCOMP_GCOMP, ((GainCompensation == 0UL) ? 0UL : 1UL) << ADC_GCOMP_GCOMP_Pos);
+}
+
+/**
+ * @brief Get the ADC gain compensation value
+ * @rmtoll GCOMP GCOMPCOEFF LL_ADC_GetGainCompensation
+ * CFGR2 GCOMP LL_ADC_GetGainCompensation
+ * @param ADCx ADC instance
+ * @retval Returned value can be:
+ * 0 Gain compensation is disabled
+ * 1 -> 16393 Gain compensation is enabled with returned value
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetGainCompensation(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->GCOMP, ADC_GCOMP_GCOMP) == ADC_GCOMP_GCOMP) \
+ ? READ_BIT(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF) : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @brief Set sampling time common to a group of channels.
+ * @note Unit: ADC clock cycles.
+ * @note On this STM32 series, sampling time scope is on ADC instance:
+ * Sampling time common to all channels.
+ * (on some other STM32 families, sampling time is channel wise)
+ * @note In case of internal channel (VrefInt, TempSensor, ...) to be
+ * converted:
+ * sampling time constraints must be respected (sampling time can be
+ * adjusted in function of ADC clock frequency and sampling time
+ * setting).
+ * Refer to device datasheet for timings values (parameters TS_vrefint,
+ * TS_temp, ...).
+ * @note Conversion time is the addition of sampling time and processing time.
+ * On this STM32 series, ADC processing time is:
+ * - 12.5 ADC clock cycles at ADC resolution 12 bits
+ * - 10.5 ADC clock cycles at ADC resolution 10 bits
+ * - 8.5 ADC clock cycles at ADC resolution 8 bits
+ * - 6.5 ADC clock cycles at ADC resolution 6 bits
+ * @note In case of ADC conversion of internal channel (VrefInt,
+ * temperature sensor, ...), a sampling time minimum value
+ * is required.
+ * Refer to device datasheet.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @note Applicable only on ADC4 instance
+ * @rmtoll SMPR SMP1 LL_ADC_SetSamplingTimeCommonChannels
+ * @rmtoll SMPR SMP2 LL_ADC_SetSamplingTimeCommonChannels
+ * @param ADCx ADC instance
+ * @param SamplingTimeY This parameter can be one of the following values:
+ * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
+ * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
+ * @param SamplingTime This parameter can be one of the following values:
+ * @arg @ref LL_ADC4_SAMPLINGTIME_1CYCLE_5
+ * @arg @ref LL_ADC4_SAMPLINGTIME_3CYCLES_5
+ * @arg @ref LL_ADC4_SAMPLINGTIME_7CYCLES_5
+ * @arg @ref LL_ADC4_SAMPLINGTIME_12CYCLES_5
+ * @arg @ref LL_ADC4_SAMPLINGTIME_19CYCLES_5
+ * @arg @ref LL_ADC4_SAMPLINGTIME_39CYCLES_5
+ * @arg @ref LL_ADC4_SAMPLINGTIME_79CYCLES_5
+ * @arg @ref LL_ADC4_SAMPLINGTIME_160CYCLES_5
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY,
+ uint32_t SamplingTime)
+{
+ MODIFY_REG(ADCx->SMPR1,
+ ADC4_SMPR_SMP1 << (SamplingTimeY & ADC4_SAMPLING_TIME_SMP_SHIFT_MASK),
+ SamplingTime << (SamplingTimeY & ADC4_SAMPLING_TIME_SMP_SHIFT_MASK));
+}
+
+/**
+ * @brief Get sampling time common to a group of channels.
+ * @note Unit: ADC clock cycles.
+ * @note On this STM32 series, sampling time scope is on ADC instance:
+ * Sampling time common to all channels.
+ * (on some other STM32 families, sampling time is channel wise)
+ * @note Conversion time is the addition of sampling time and processing time.
+ * Refer to reference manual for ADC processing time of
+ * this STM32 series.
+ * @rmtoll SMPR SMP1 LL_ADC_GetSamplingTimeCommonChannels
+ * @rmtoll SMPR SMP2 LL_ADC_GetSamplingTimeCommonChannels
+ * @param ADCx ADC instance (ADC4 for this device)
+ * @param SamplingTimeY This parameter can be one of the following values:
+ * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
+ * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC4_SAMPLINGTIME_1CYCLE_5
+ * @arg @ref LL_ADC4_SAMPLINGTIME_3CYCLES_5
+ * @arg @ref LL_ADC4_SAMPLINGTIME_7CYCLES_5
+ * @arg @ref LL_ADC4_SAMPLINGTIME_12CYCLES_5
+ * @arg @ref LL_ADC4_SAMPLINGTIME_19CYCLES_5
+ * @arg @ref LL_ADC4_SAMPLINGTIME_39CYCLES_5
+ * @arg @ref LL_ADC4_SAMPLINGTIME_79CYCLES_5
+ * @arg @ref LL_ADC4_SAMPLINGTIME_160CYCLES_5
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY)
+{
+ return (uint32_t)((READ_BIT(ADCx->SMPR1, ADC4_SMPR_SMP1 << (SamplingTimeY & ADC4_SAMPLING_TIME_SMP_SHIFT_MASK)))
+ >> (SamplingTimeY & ADC4_SAMPLING_TIME_SMP_SHIFT_MASK));
+}
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
+ * @{
+ */
+
+/**
+ * @brief Set ADC group regular conversion trigger source:
+ * internal (SW start) or from external peripheral (timer event,
+ * external interrupt line).
+ * @note On this STM32 series, setting trigger source to external trigger
+ * also set trigger polarity to rising edge
+ * (default setting for compatibility with some ADC on other
+ * STM32 families having this setting set by HW default value).
+ * In case of need to modify trigger edge, use
+ * function @ref LL_ADC_REG_SetTriggerEdge().
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll CFGR EXTSEL LL_ADC_REG_SetTriggerSource
+ * CFGR EXTEN LL_ADC_REG_SetTriggerSource
+ * @param ADCx ADC instance
+ * @param TriggerSource This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
+ * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
+ * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_CH1
+ * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_CH1
+ * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM3_CH1
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
+{
+ if (ADCx == ADC1)
+ {
+ MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL, TriggerSource);
+ }
+ else /* ADCx == ADC4 */
+ {
+ MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC4_CFGR1_EXTSEL, TriggerSource);
+ }
+}
+
+/**
+ * @brief Get ADC group regular conversion trigger source:
+ * internal (SW start) or from external peripheral (timer event,
+ * external interrupt line).
+ * @note To determine whether group regular trigger source is
+ * internal (SW start) or external, without detail
+ * of which peripheral is selected as external trigger,
+ * (equivalent to
+ * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
+ * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CFGR EXTSEL LL_ADC_REG_GetTriggerSource
+ * CFGR EXTEN LL_ADC_REG_GetTriggerSource
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
+ * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
+ * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_CH1
+ * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_CH1
+ * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM3_CH1
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
+{
+ if (ADCx == ADC1)
+ {
+ __IO uint32_t trigger_source = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN);
+
+ /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
+ /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */
+ uint32_t shift_exten = ((trigger_source & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
+
+ /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */
+ /* to match with triggers literals definition. */
+ return ((trigger_source
+ & (ADC_REG_TRIG_SOURCE_MASK >> shift_exten) & ADC_CFGR1_EXTSEL)
+ | ((ADC_REG_TRIG_EDGE_MASK >> shift_exten) & ADC_CFGR1_EXTEN)
+ );
+ }
+ else /* ADCx == ADC4 */
+ {
+ __IO uint32_t trigger_source = READ_BIT(ADCx->CFGR1, ADC4_CFGR1_EXTSEL | ADC_CFGR1_EXTEN);
+
+ /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
+ /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */
+ uint32_t shift_exten = ((trigger_source & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
+
+ /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */
+ /* to match with triggers literals definition. */
+ return ((trigger_source
+ & (ADC_REG_TRIG_SOURCE_MASK >> shift_exten) & ADC4_CFGR1_EXTSEL)
+ | ((ADC_REG_TRIG_EDGE_MASK >> shift_exten) & ADC_CFGR1_EXTEN)
+ );
+ }
+}
+
+/**
+ * @brief Get ADC group regular conversion trigger source internal (SW start)
+ * or external.
+ * @note In case of group regular trigger source set to external trigger,
+ * to determine which peripheral is selected as external trigger,
+ * use function @ref LL_ADC_REG_GetTriggerSource().
+ * @rmtoll CFGR EXTEN LL_ADC_REG_IsTriggerSourceSWStart
+ * @param ADCx ADC instance
+ * @retval Value "0" if trigger source external trigger
+ * Value "1" if trigger source SW start.
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set ADC group regular conversion trigger polarity.
+ * @note Applicable only for trigger source set to external trigger.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll CFGR EXTEN LL_ADC_REG_SetTriggerEdge
+ * @param ADCx ADC instance
+ * @param ExternalTriggerEdge This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
+ * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
+ * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
+{
+ MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN, ExternalTriggerEdge);
+}
+
+/**
+ * @brief Get ADC group regular conversion trigger polarity.
+ * @note Applicable only for trigger source set to external trigger.
+ * @rmtoll CFGR EXTEN LL_ADC_REG_GetTriggerEdge
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
+ * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
+ * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN));
+}
+
+/**
+ * @brief Set ADC trigger frequency mode.
+ * @note ADC trigger frequency mode must be set to low frequency when
+ * a duration is exceeded before ADC conversion start trigger event
+ * (between ADC enable and ADC conversion start trigger event
+ * or between two ADC conversion start trigger event).
+ * Duration value: Refer to device datasheet, parameter "tIdle".
+ * @note When ADC trigger frequency mode is set to low frequency,
+ * some rearm cycles are inserted before performing ADC conversion
+ * start, inducing a delay of 2 ADC clock cycles.
+ * @note Usage of ADC trigger frequency mode with ADC low power mode:
+ * - Low power mode auto wait: Only the first ADC conversion
+ * start trigger inserts the rearm delay.
+ * - Low power mode auto power-off: ADC trigger frequency mode
+ * is discarded.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll CFGR2 LFTRIG LL_ADC_SetTriggerFrequencyMode
+ * @param ADCx ADC instance
+ * @param TriggerFrequencyMode This parameter can be one of the following values:
+ * @arg @ref LL_ADC_TRIGGER_FREQ_HIGH
+ * @arg @ref LL_ADC_TRIGGER_FREQ_LOW
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetTriggerFrequencyMode(ADC_TypeDef *ADCx, uint32_t TriggerFrequencyMode)
+{
+ if (ADCx == ADC1)
+ {
+ MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LFTRIG, (TriggerFrequencyMode >> 2U));
+ }
+ else /* ADCx == ADC4 */
+ {
+ MODIFY_REG(ADCx->CFGR2, ADC4_CFGR2_LFTRIG, TriggerFrequencyMode);
+ }
+}
+
+/**
+ * @brief Get ADC trigger frequency mode.
+ * @rmtoll CFGR2 LFTRIG LL_ADC_GetTriggerFrequencyMode
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_TRIGGER_FREQ_HIGH
+ * @arg @ref LL_ADC_TRIGGER_FREQ_LOW
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetTriggerFrequencyMode(ADC_TypeDef *ADCx)
+{
+ if (ADCx == ADC1)
+ {
+ return (uint32_t)((READ_BIT(ADCx->CFGR2, ADC_CFGR2_LFTRIG)) << 2U);
+ }
+ else /* ADCx == ADC4 */
+ {
+ return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC4_CFGR2_LFTRIG));
+ }
+}
+
+/**
+ * @brief Set ADC sampling mode.
+ * @note This function set the ADC conversion sampling mode
+ * @note This mode applies to regular group only.
+ * @note Set sampling mode is applied to all conversion of regular group.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll CFGR2 BULB LL_ADC_REG_SetSamplingMode
+ * CFGR2 SMPTRIG LL_ADC_REG_SetSamplingMode
+ * @param ADCx ADC instance
+ * @param SamplingMode This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
+ * @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
+ * @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetSamplingMode(ADC_TypeDef *ADCx, uint32_t SamplingMode)
+{
+ MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, SamplingMode);
+}
+
+/**
+ * @brief Get the ADC sampling mode
+ * @rmtoll CFGR2 BULB LL_ADC_REG_GetSamplingMode
+ * CFGR2 SMPTRIG LL_ADC_REG_GetSamplingMode
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
+ * @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
+ * @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSamplingMode(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG));
+}
+
+/**
+ * @brief Start ADC sampling phase for sampling time trigger mode
+ * @note This function is relevant only when
+ * - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set
+ * using @ref LL_ADC_REG_SetSamplingMode
+ * - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be enabled without conversion on going on group regular,
+ * without conversion stop command on going on group regular,
+ * without ADC disable command on going.
+ * @rmtoll CFGR2 SWTRIG LL_ADC_REG_StartSamplingPhase
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_StartSamplingPhase(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG);
+}
+
+/**
+ * @brief Stop ADC sampling phase for sampling time trigger mode and start conversion
+ * @note This function is relevant only when
+ * - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set
+ * using @ref LL_ADC_REG_SetSamplingMode
+ * - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source
+ * - @ref LL_ADC_REG_StartSamplingPhase has been called to start
+ * the sampling phase
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be enabled without conversion on going on group regular,
+ * without conversion stop command on going on group regular,
+ * without ADC disable command on going.
+ * @rmtoll CFGR2 SWTRIG LL_ADC_REG_StopSamplingPhase
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_StopSamplingPhase(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG);
+}
+
+/**
+ * @brief Set ADC group regular sequencer configuration flexibility.
+ * @note On this STM32 series, ADC group regular sequencer both modes
+ * "fully configurable" or "not fully configurable" are
+ * available:
+ * - sequencer configured to fully configurable:
+ * sequencer length and each rank
+ * affectation to a channel are configurable.
+ * Refer to description of function
+ * @ref LL_ADC_REG_SetSequencerLength().
+ * - sequencer configured to not fully configurable:
+ * sequencer length and each rank affectation to a channel
+ * are fixed by channel HW number.
+ * Refer to description of function
+ * @ref LL_ADC_REG_SetSequencerChannels().
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll CFGR CHSELRMOD LL_ADC_REG_SetSequencerConfigurable
+ * @param ADCx ADC instance
+ * @param Configurability This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_FIXED
+ * @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE
+ * @retval None
+ * @note On this STM32U5 series, this is applicable on ADC4 only.
+ */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerConfigurable(ADC_TypeDef *ADCx, uint32_t Configurability)
+{
+ MODIFY_REG(ADCx->CFGR1, ADC4_CFGR1_CHSELRMOD, Configurability);
+}
+
+/**
+ * @brief Get ADC group regular sequencer configuration flexibility.
+ * @note On this STM32 series, ADC group regular sequencer both modes
+ * "fully configurable" or "not fully configurable" are
+ * available:
+ * - sequencer configured to fully configurable:
+ * sequencer length and each rank
+ * affectation to a channel are configurable.
+ * Refer to description of function
+ * @ref LL_ADC_REG_SetSequencerLength().
+ * - sequencer configured to not fully configurable:
+ * sequencer length and each rank affectation to a channel
+ * are fixed by channel HW number.
+ * Refer to description of function
+ * @ref LL_ADC_REG_SetSequencerChannels().
+ * @rmtoll CFGR CHSELRMOD LL_ADC_REG_SetSequencerConfigurable
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_FIXED
+ * @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE
+ * @note On this STM32U5 series, this is applicable on ADC4 only.
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerConfigurable(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC4_CFGR1_CHSELRMOD));
+}
+
+/**
+ * @brief Set ADC group regular sequencer length and scan direction.
+ * @note Description of ADC group regular sequencer features:
+ * - For devices with sequencer fully configurable
+ * (function "LL_ADC_REG_SetSequencerRanks()" available):
+ * sequencer length and each rank affectation to a channel
+ * are configurable.
+ * This function performs configuration of:
+ * - Sequence length: Number of ranks in the scan sequence.
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from rank 1 to rank n).
+ * Sequencer ranks are selected using
+ * function "LL_ADC_REG_SetSequencerRanks()".
+ * - For devices with sequencer not fully configurable
+ * (function "LL_ADC_REG_SetSequencerChannels()" available):
+ * sequencer length and each rank affectation to a channel
+ * are defined by channel number.
+ * This function performs configuration of:
+ * - Sequence length: Number of ranks in the scan sequence is
+ * defined by number of channels set in the sequence,
+ * rank of each channel is fixed by channel HW number.
+ * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from lowest channel number to
+ * highest channel number).
+ * Sequencer ranks are selected using
+ * function "LL_ADC_REG_SetSequencerChannels()".
+ * @note Sequencer disabled is equivalent to sequencer of 1 rank:
+ * ADC conversion on only 1 channel.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
+ * @param ADCx ADC instance
+ * @param SequencerNbRanks This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
+{
+ if (ADCx != ADC4) /* ADC1 or ADC2 */
+ {
+ MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
+ }
+ else
+ {
+ SET_BIT(ADCx->CHSELR, SequencerNbRanks);
+ }
+}
+
+/**
+ * @brief Get ADC group regular sequencer length and scan direction.
+ * @note Description of ADC group regular sequencer features:
+ * - For devices with sequencer fully configurable
+ * (function "LL_ADC_REG_SetSequencerRanks()" available):
+ * sequencer length and each rank affectation to a channel
+ * are configurable.
+ * This function retrieves:
+ * - Sequence length: Number of ranks in the scan sequence.
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from rank 1 to rank n).
+ * Sequencer ranks are selected using
+ * function "LL_ADC_REG_SetSequencerRanks()".
+ * - For devices with sequencer not fully configurable
+ * (function "LL_ADC_REG_SetSequencerChannels()" available):
+ * sequencer length and each rank affectation to a channel
+ * are defined by channel number.
+ * This function retrieves:
+ * - Sequence length: Number of ranks in the scan sequence is
+ * defined by number of channels set in the sequence,
+ * rank of each channel is fixed by channel HW number.
+ * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from lowest channel number to
+ * highest channel number).
+ * Sequencer ranks are selected using
+ * function "LL_ADC_REG_SetSequencerChannels()".
+ * @note Sequencer disabled is equivalent to sequencer of 1 rank:
+ * ADC conversion on only 1 channel.
+ * @rmtoll SQR1 L LL_ADC_REG_GetSequencerLength
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
+{
+ if (ADCx != ADC4) /* ADC1 or ADC2 */
+ {
+ return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
+ }
+ else
+ {
+ uint32_t channels_ranks = READ_BIT(ADCx->CHSELR, ADC_CHSELR_SQ_ALL);
+ uint32_t sequencer_length = LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS;
+ uint32_t rank_index;
+ uint32_t rank_shifted;
+
+ /* Parse register for end of sequence identifier */
+ /* Note: Value "0xF0UL" corresponds to bitfield of sequencer 2nd rank
+ (ADC_CHSELR_SQ2), value "4" to length of end of sequence
+ identifier (0xF)*/
+ for (rank_index = 0UL; rank_index <= (28U - 4U); rank_index += 4U)
+ {
+ rank_shifted = (uint32_t)(0xF0UL << rank_index);
+ if ((channels_ranks & rank_shifted) == rank_shifted)
+ {
+ sequencer_length = rank_shifted;
+ break;
+ }
+ }
+
+ return sequencer_length;
+ }
+}
+
+/**
+ * @brief Set ADC group regular sequencer discontinuous mode:
+ * sequence subdivided and scan conversions interrupted every selected
+ * number of ranks.
+ * @note It is not possible to enable both ADC group regular
+ * continuous mode and sequencer discontinuous mode.
+ * @note It is not possible to enable both ADC auto-injected mode
+ * and ADC group regular sequencer discontinuous mode.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll CFGR DISCEN LL_ADC_REG_SetSequencerDiscont
+ * CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont
+ * @param ADCx ADC instance
+ * @param SeqDiscont This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
+{
+ MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DISCEN | ADC_CFGR1_DISCNUM, SeqDiscont);
+}
+
+/**
+ * @brief Get ADC group regular sequencer discontinuous mode:
+ * sequence subdivided and scan conversions interrupted every selected
+ * number of ranks.
+ * @rmtoll CFGR DISCEN LL_ADC_REG_GetSequencerDiscont
+ * CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN | ADC_CFGR1_DISCNUM));
+}
+
+/**
+ * @brief Set ADC group regular sequence: channel on the selected
+ * scan sequence rank.
+ * @note This function performs configuration of:
+ * - Channels ordering into each rank of scan sequence:
+ * whatever channel can be placed into whatever rank.
+ * @note On this STM32 series, ADC group regular sequencer is
+ * fully configurable: sequencer length and each rank
+ * affectation to a channel are configurable.
+ * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note On this STM32 series, to measure internal channels (VrefInt,
+ * TempSensor, ...), measurement paths to internal channels must be
+ * enabled separately.
+ * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll SQR1 SQ1 LL_ADC_REG_SetSequencerRanks
+ * SQR1 SQ2 LL_ADC_REG_SetSequencerRanks
+ * SQR1 SQ3 LL_ADC_REG_SetSequencerRanks
+ * SQR1 SQ4 LL_ADC_REG_SetSequencerRanks
+ * SQR2 SQ5 LL_ADC_REG_SetSequencerRanks
+ * SQR2 SQ6 LL_ADC_REG_SetSequencerRanks
+ * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks
+ * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks
+ * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks
+ * SQR3 SQ10 LL_ADC_REG_SetSequencerRanks
+ * SQR3 SQ11 LL_ADC_REG_SetSequencerRanks
+ * SQR3 SQ12 LL_ADC_REG_SetSequencerRanks
+ * SQR3 SQ13 LL_ADC_REG_SetSequencerRanks
+ * SQR3 SQ14 LL_ADC_REG_SetSequencerRanks
+ * SQR4 SQ15 LL_ADC_REG_SetSequencerRanks
+ * SQR4 SQ16 LL_ADC_REG_SetSequencerRanks
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_RANK_1
+ * @arg @ref LL_ADC_REG_RANK_2
+ * @arg @ref LL_ADC_REG_RANK_3
+ * @arg @ref LL_ADC_REG_RANK_4
+ * @arg @ref LL_ADC_REG_RANK_5
+ * @arg @ref LL_ADC_REG_RANK_6
+ * @arg @ref LL_ADC_REG_RANK_7
+ * @arg @ref LL_ADC_REG_RANK_8
+ * @arg @ref LL_ADC_REG_RANK_9
+ * @arg @ref LL_ADC_REG_RANK_10
+ * @arg @ref LL_ADC_REG_RANK_11
+ * @arg @ref LL_ADC_REG_RANK_12
+ * @arg @ref LL_ADC_REG_RANK_13
+ * @arg @ref LL_ADC_REG_RANK_14
+ * @arg @ref LL_ADC_REG_RANK_15
+ * @arg @ref LL_ADC_REG_RANK_16
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0 (3)
+ * @arg @ref LL_ADC_CHANNEL_1 (3)
+ * @arg @ref LL_ADC_CHANNEL_2 (3)
+ * @arg @ref LL_ADC_CHANNEL_3 (3)
+ * @arg @ref LL_ADC_CHANNEL_4 (3)
+ * @arg @ref LL_ADC_CHANNEL_5 (3)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_19
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
+ *
+ * (1) On STM32U5, parameter available only on ADC instance: ADC1/2.
+ * (2) On STM32U5, parameter available only on ADC instance: ADC4.
+ * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
+{
+ /* Set bits with content of parameter "Channel" with bits position */
+ /* in register and register position depending on parameter "Rank". */
+ /* Parameters "Rank" and "Channel" are used with masks because containing */
+ /* other bits reserved for other purpose. */
+ if (ADCx != ADC4) /* ADC1 or ADC2 */
+ {
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) \
+ >> ADC_SQRX_REGOFFSET_POS));
+
+ MODIFY_REG(*preg,
+ ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
+ ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
+ << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
+ }
+ else
+ {
+ MODIFY_REG(ADCx->CHSELR,
+ ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
+ (__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)));
+ }
+}
+
+/**
+ * @brief Get ADC group regular sequence: channel on the selected
+ * scan sequence rank.
+ * @note On this STM32 series, ADC group regular sequencer is
+ * fully configurable: sequencer length and each rank
+ * affectation to a channel are configurable.
+ * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note Usage of the returned channel number:
+ * - To reinject this channel into another function LL_ADC_xxx:
+ * the returned channel number is only partly formatted on definition
+ * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+ * with parts of literals LL_ADC_CHANNEL_x or using
+ * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Then the selected literal LL_ADC_CHANNEL_x can be used
+ * as parameter for another function.
+ * - To get the channel number in decimal format:
+ * process the returned value with the helper macro
+ * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * @rmtoll SQR1 SQ1 LL_ADC_REG_GetSequencerRanks
+ * SQR1 SQ2 LL_ADC_REG_GetSequencerRanks
+ * SQR1 SQ3 LL_ADC_REG_GetSequencerRanks
+ * SQR1 SQ4 LL_ADC_REG_GetSequencerRanks
+ * SQR2 SQ5 LL_ADC_REG_GetSequencerRanks
+ * SQR2 SQ6 LL_ADC_REG_GetSequencerRanks
+ * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks
+ * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks
+ * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks
+ * SQR3 SQ10 LL_ADC_REG_GetSequencerRanks
+ * SQR3 SQ11 LL_ADC_REG_GetSequencerRanks
+ * SQR3 SQ12 LL_ADC_REG_GetSequencerRanks
+ * SQR3 SQ13 LL_ADC_REG_GetSequencerRanks
+ * SQR3 SQ14 LL_ADC_REG_GetSequencerRanks
+ * SQR4 SQ15 LL_ADC_REG_GetSequencerRanks
+ * SQR4 SQ16 LL_ADC_REG_GetSequencerRanks
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_RANK_1
+ * @arg @ref LL_ADC_REG_RANK_2
+ * @arg @ref LL_ADC_REG_RANK_3
+ * @arg @ref LL_ADC_REG_RANK_4
+ * @arg @ref LL_ADC_REG_RANK_5
+ * @arg @ref LL_ADC_REG_RANK_6
+ * @arg @ref LL_ADC_REG_RANK_7
+ * @arg @ref LL_ADC_REG_RANK_8
+ * @arg @ref LL_ADC_REG_RANK_9
+ * @arg @ref LL_ADC_REG_RANK_10
+ * @arg @ref LL_ADC_REG_RANK_11
+ * @arg @ref LL_ADC_REG_RANK_12
+ * @arg @ref LL_ADC_REG_RANK_13
+ * @arg @ref LL_ADC_REG_RANK_14
+ * @arg @ref LL_ADC_REG_RANK_15
+ * @arg @ref LL_ADC_REG_RANK_16
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0 (3)
+ * @arg @ref LL_ADC_CHANNEL_1 (3)
+ * @arg @ref LL_ADC_CHANNEL_2 (3)
+ * @arg @ref LL_ADC_CHANNEL_3 (3)
+ * @arg @ref LL_ADC_CHANNEL_4 (3)
+ * @arg @ref LL_ADC_CHANNEL_5 (3)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_19
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
+ *
+ * (1) On STM32U5, parameter available only on ADC instance: ADC1/2.
+ * (2) On STM32U5, parameter available only on ADC instance: ADC4.
+ * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).
+ * (1, 2) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ if (ADCx != ADC4) /* ADC1 or ADC2 */
+ {
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) \
+ >> ADC_SQRX_REGOFFSET_POS));
+
+ return (uint32_t)((READ_BIT(*preg,
+ ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
+ >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
+ );
+ }
+ else
+ {
+ return (uint32_t)((READ_BIT(ADCx->CHSELR,
+ ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
+ >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
+ ) << (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+ );
+ }
+}
+
+/**
+ * @brief Set ADC group regular sequencer scan direction.
+ * @note On this STM32 series, parameter relevant only is sequencer is set
+ * to mode not fully configurable,
+ * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
+ * @note On some other STM32 families, this setting is not available and
+ * the default scan direction is forward.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll CFGR1 SCANDIR LL_ADC_REG_SetSequencerScanDirection
+ * @param ADCx ADC instance
+ * @param ScanDirection This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef *ADCx, uint32_t ScanDirection)
+{
+ MODIFY_REG(ADCx->CFGR1, ADC4_CFGR1_SCANDIR, ScanDirection);
+}
+
+/**
+ * @brief Get ADC group regular sequencer scan direction.
+ * @note On this STM32 series, parameter relevant only is sequencer is set
+ * to mode not fully configurable,
+ * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
+ * @note On some other STM32 families, this setting is not available and
+ * the default scan direction is forward.
+ * @rmtoll CFGR1 SCANDIR LL_ADC_REG_GetSequencerScanDirection
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC4_CFGR1_SCANDIR));
+}
+
+/**
+ * @brief Set ADC group regular sequence: channel on rank corresponding to
+ * channel number.
+ * @note This function performs:
+ * - Channels ordering into each rank of scan sequence:
+ * rank of each channel is fixed by channel HW number
+ * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+ * - Set channels selected by overwriting the current sequencer
+ * configuration.
+ * @note On this STM32 series, ADC group regular sequencer both modes
+ * "fully configurable" or "not fully configurable"
+ * are available, they can be chosen using
+ * function @ref LL_ADC_REG_SetSequencerConfigurable().
+ * This function can be used with setting "not fully configurable".
+ * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
+ * and @ref LL_ADC_REG_SetSequencerLength().
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note On this STM32 series, to measure internal channels (VrefInt,
+ * TempSensor, ...), measurement paths to internal channels must be
+ * enabled separately.
+ * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @note One or several values can be selected.
+ * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
+ * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChannels
+ * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChannels
+ * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChannels
+ * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChannels
+ * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChannels
+ * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChannels
+ * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChannels
+ * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChannels
+ * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChannels
+ * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChannels
+ * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChannels
+ * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChannels
+ * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChannels
+ * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChannels
+ * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChannels
+ * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChannels
+ * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChannels
+ * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChannels
+ * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChannels
+ * @param ADCx ADC instance
+ * @param Channel This parameter can be a combination of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15 (1)
+ * @arg @ref LL_ADC_CHANNEL_16 (1)
+ * @arg @ref LL_ADC_CHANNEL_17 (1)
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
+ * @arg @ref LL_ADC_CHANNEL_VBAT
+ *
+ * (1) On STM32U5, parameter can be set in ADC group sequencer
+ * only if sequencer is set in mode "not fully configurable",
+ * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerChannels(ADC_TypeDef *ADCx, uint32_t Channel)
+{
+ /* Parameter "Channel" is used with masks because containing */
+ /* other bits reserved for other purpose. */
+ WRITE_REG(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
+}
+
+/**
+ * @brief Add channel to ADC group regular sequence: channel on rank corresponding to
+ * channel number.
+ * @note This function performs:
+ * - Channels ordering into each rank of scan sequence:
+ * rank of each channel is fixed by channel HW number
+ * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+ * - Set channels selected by adding them to the current sequencer
+ * configuration.
+ * @note On this STM32 series, ADC group regular sequencer both modes
+ * "fully configurable" or "not fully configurable"
+ * are available, they can be chosen using
+ * function @ref LL_ADC_REG_SetSequencerConfigurable().
+ * This function can be used with setting "not fully configurable".
+ * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
+ * and @ref LL_ADC_REG_SetSequencerLength().
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note On this STM32 series, to measure internal channels (VrefInt,
+ * TempSensor, ...), measurement paths to internal channels must be
+ * enabled separately.
+ * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @note One or several values can be selected.
+ * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
+ * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChAdd
+ * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChAdd
+ * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChAdd
+ * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChAdd
+ * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChAdd
+ * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChAdd
+ * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChAdd
+ * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChAdd
+ * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChAdd
+ * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChAdd
+ * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChAdd
+ * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChAdd
+ * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChAdd
+ * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChAdd
+ * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChAdd
+ * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChAdd
+ * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChAdd
+ * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChAdd
+ * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChAdd
+ * @param ADCx ADC instance
+ * @param Channel This parameter can be a combination of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15 (1)
+ * @arg @ref LL_ADC_CHANNEL_16 (1)
+ * @arg @ref LL_ADC_CHANNEL_17 (1)
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
+ * @arg @ref LL_ADC_CHANNEL_VBAT
+ *
+ * (1) On STM32U5, parameter can be set in ADC group sequencer
+ * only if sequencer is set in mode "not fully configurable",
+ * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef *ADCx, uint32_t Channel)
+{
+ /* Parameter "Channel" is used with masks because containing */
+ /* other bits reserved for other purpose. */
+ SET_BIT(ADCx->CHSELR, (1UL << ((__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) & ADC_CHSELR_CHSEL) & 0x1FUL)));
+}
+
+/**
+ * @brief Remove channel to ADC group regular sequence: channel on rank corresponding to
+ * channel number.
+ * @note This function performs:
+ * - Channels ordering into each rank of scan sequence:
+ * rank of each channel is fixed by channel HW number
+ * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+ * - Set channels selected by removing them to the current sequencer
+ * configuration.
+ * @note On this STM32 series, ADC group regular sequencer both modes
+ * "fully configurable" or "not fully configurable"
+ * are available, they can be chosen using
+ * function @ref LL_ADC_REG_SetSequencerConfigurable().
+ * This function can be used with setting "not fully configurable".
+ * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
+ * and @ref LL_ADC_REG_SetSequencerLength().
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note On this STM32 series, to measure internal channels (VrefInt,
+ * TempSensor, ...), measurement paths to internal channels must be
+ * enabled separately.
+ * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @note One or several values can be selected.
+ * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
+ * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChRem
+ * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChRem
+ * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChRem
+ * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChRem
+ * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChRem
+ * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChRem
+ * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChRem
+ * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChRem
+ * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChRem
+ * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChRem
+ * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChRem
+ * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChRem
+ * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChRem
+ * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChRem
+ * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChRem
+ * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChRem
+ * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChRem
+ * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChRem
+ * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChRem
+ * @param ADCx ADC instance
+ * @param Channel This parameter can be a combination of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15 (1)
+ * @arg @ref LL_ADC_CHANNEL_16 (1)
+ * @arg @ref LL_ADC_CHANNEL_17 (1)
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
+ * @arg @ref LL_ADC_CHANNEL_VBAT
+ *
+ * (1) On STM32U5, parameter can be set in ADC group sequencer
+ * only if sequencer is set in mode "not fully configurable",
+ * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Channel)
+{
+ /* Parameter "Channel" is used with masks because containing */
+ /* other bits reserved for other purpose. */
+ CLEAR_BIT(ADCx->CHSELR, (1UL << ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)));
+}
+
+/**
+ * @brief Get ADC group regular sequence: channel on rank corresponding to
+ * channel number.
+ * @note This function performs:
+ * - Channels order reading into each rank of scan sequence:
+ * rank of each channel is fixed by channel HW number
+ * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+ * @note On this STM32 series, ADC group regular sequencer both modes
+ * "fully configurable" or "not fully configurable"
+ * are available, they can be chosen using
+ * function @ref LL_ADC_REG_SetSequencerConfigurable().
+ * This function can be used with setting "not fully configurable".
+ * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
+ * and @ref LL_ADC_REG_SetSequencerLength().
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note On this STM32 series, to measure internal channels (VrefInt,
+ * TempSensor, ...), measurement paths to internal channels must be
+ * enabled separately.
+ * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @note One or several values can be retrieved.
+ * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
+ * @rmtoll CHSELR CHSEL0 LL_ADC_REG_GetSequencerChannels
+ * CHSELR CHSEL1 LL_ADC_REG_GetSequencerChannels
+ * CHSELR CHSEL2 LL_ADC_REG_GetSequencerChannels
+ * CHSELR CHSEL3 LL_ADC_REG_GetSequencerChannels
+ * CHSELR CHSEL4 LL_ADC_REG_GetSequencerChannels
+ * CHSELR CHSEL5 LL_ADC_REG_GetSequencerChannels
+ * CHSELR CHSEL6 LL_ADC_REG_GetSequencerChannels
+ * CHSELR CHSEL7 LL_ADC_REG_GetSequencerChannels
+ * CHSELR CHSEL8 LL_ADC_REG_GetSequencerChannels
+ * CHSELR CHSEL9 LL_ADC_REG_GetSequencerChannels
+ * CHSELR CHSEL10 LL_ADC_REG_GetSequencerChannels
+ * CHSELR CHSEL11 LL_ADC_REG_GetSequencerChannels
+ * CHSELR CHSEL12 LL_ADC_REG_GetSequencerChannels
+ * CHSELR CHSEL13 LL_ADC_REG_GetSequencerChannels
+ * CHSELR CHSEL14 LL_ADC_REG_GetSequencerChannels
+ * CHSELR CHSEL15 LL_ADC_REG_GetSequencerChannels
+ * CHSELR CHSEL16 LL_ADC_REG_GetSequencerChannels
+ * CHSELR CHSEL17 LL_ADC_REG_GetSequencerChannels
+ * CHSELR CHSEL18 LL_ADC_REG_GetSequencerChannels
+ * @param ADCx ADC instance
+ * @retval Returned value can be a combination of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15 (1)
+ * @arg @ref LL_ADC_CHANNEL_16 (1)
+ * @arg @ref LL_ADC_CHANNEL_17 (1)
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
+ * @arg @ref LL_ADC_CHANNEL_VBAT
+ *
+ * (1) On STM32U5, parameter can be set in ADC group sequencer
+ * only if sequencer is set in mode "not fully configurable",
+ * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(ADC_TypeDef *ADCx)
+{
+ uint32_t channels_bitfield = READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL);
+
+ return ((((channels_bitfield & ADC_CHSELR_CHSEL0) >> ADC4_CHSELR_CHSEL0_BITOFFSET_POS) * LL_ADC_CHANNEL_0)
+ | (((channels_bitfield & ADC_CHSELR_CHSEL1) >> ADC4_CHSELR_CHSEL1_BITOFFSET_POS) * LL_ADC_CHANNEL_1)
+ | (((channels_bitfield & ADC_CHSELR_CHSEL2) >> ADC4_CHSELR_CHSEL2_BITOFFSET_POS) * LL_ADC_CHANNEL_2)
+ | (((channels_bitfield & ADC_CHSELR_CHSEL3) >> ADC4_CHSELR_CHSEL3_BITOFFSET_POS) * LL_ADC_CHANNEL_3)
+ | (((channels_bitfield & ADC_CHSELR_CHSEL4) >> ADC4_CHSELR_CHSEL4_BITOFFSET_POS) * LL_ADC_CHANNEL_4)
+ | (((channels_bitfield & ADC_CHSELR_CHSEL5) >> ADC4_CHSELR_CHSEL5_BITOFFSET_POS) * LL_ADC_CHANNEL_5)
+ | (((channels_bitfield & ADC_CHSELR_CHSEL6) >> ADC4_CHSELR_CHSEL6_BITOFFSET_POS) * LL_ADC_CHANNEL_6)
+ | (((channels_bitfield & ADC_CHSELR_CHSEL7) >> ADC4_CHSELR_CHSEL7_BITOFFSET_POS) * LL_ADC_CHANNEL_7)
+ | (((channels_bitfield & ADC_CHSELR_CHSEL8) >> ADC4_CHSELR_CHSEL8_BITOFFSET_POS) * LL_ADC_CHANNEL_8)
+ | (((channels_bitfield & ADC_CHSELR_CHSEL9) >> ADC4_CHSELR_CHSEL9_BITOFFSET_POS) * LL_ADC_CHANNEL_9)
+ | (((channels_bitfield & ADC_CHSELR_CHSEL10) >> ADC4_CHSELR_CHSEL10_BITOFFSET_POS) * LL_ADC_CHANNEL_10)
+ | (((channels_bitfield & ADC_CHSELR_CHSEL11) >> ADC4_CHSELR_CHSEL11_BITOFFSET_POS) * LL_ADC_CHANNEL_11)
+ | (((channels_bitfield & ADC_CHSELR_CHSEL12) >> ADC4_CHSELR_CHSEL12_BITOFFSET_POS) * LL_ADC_CHANNEL_12)
+ | (((channels_bitfield & ADC_CHSELR_CHSEL13) >> ADC4_CHSELR_CHSEL13_BITOFFSET_POS) * LL_ADC_CHANNEL_13)
+ | (((channels_bitfield & ADC_CHSELR_CHSEL14) >> ADC4_CHSELR_CHSEL14_BITOFFSET_POS) * LL_ADC_CHANNEL_14)
+ | (((channels_bitfield & ADC_CHSELR_CHSEL15) >> ADC4_CHSELR_CHSEL15_BITOFFSET_POS) * LL_ADC_CHANNEL_15)
+ | (((channels_bitfield & ADC_CHSELR_CHSEL16) >> ADC4_CHSELR_CHSEL16_BITOFFSET_POS) * LL_ADC_CHANNEL_16)
+ | (((channels_bitfield & ADC_CHSELR_CHSEL17) >> ADC4_CHSELR_CHSEL17_BITOFFSET_POS) * LL_ADC_CHANNEL_17)
+ | (((channels_bitfield & ADC_CHSELR_CHSEL18) >> ADC4_CHSELR_CHSEL18_BITOFFSET_POS) * LL_ADC_CHANNEL_18)
+ | (((channels_bitfield & ADC_CHSELR_CHSEL19) >> ADC4_CHSELR_CHSEL19_BITOFFSET_POS) * LL_ADC_CHANNEL_19)
+ | (((channels_bitfield & ADC_CHSELR_CHSEL20) >> ADC4_CHSELR_CHSEL20_BITOFFSET_POS) * LL_ADC_CHANNEL_20)
+ | (((channels_bitfield & ADC_CHSELR_CHSEL21) >> ADC4_CHSELR_CHSEL21_BITOFFSET_POS) * LL_ADC_CHANNEL_21)
+ | (((channels_bitfield & ADC_CHSELR_CHSEL22) >> ADC4_CHSELR_CHSEL22_BITOFFSET_POS) * LL_ADC_CHANNEL_22)
+ | (((channels_bitfield & ADC_CHSELR_CHSEL23) >> ADC4_CHSELR_CHSEL23_BITOFFSET_POS) * LL_ADC_CHANNEL_23)
+
+ );
+}
+
+/**
+ * @brief Set ADC Channel Preselection to LL_ADC_CHANNEL_x, x = 0 to 19.
+ * @note This function set the the value for the channel preselection register
+ * corresponding to ADC channel to be selected.
+ * @note Caution: This is not valid for ADC4.
+ * @param ADCx ADC instance.
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_19
+ * @arg @ref LL_ADC_CHANNEL_VREFINT
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
+ * @arg @ref LL_ADC_CHANNEL_VBAT
+ *
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetChannelPreselection(ADC_TypeDef *ADCx, uint32_t Channel)
+{
+ __IO uint32_t channel_preselectione = READ_REG(ADCx->PCSEL);
+ WRITE_REG(ADCx->PCSEL,
+ channel_preselectione | (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)Channel) & 0x1FUL)));
+}
+
+/**
+ * @brief Get ADC Channel Preselection register value.
+ * @note This function set the the value for the channel preselection register
+ * corresponding to ADC channel to be selected.
+ * @note Caution: This is not valid for ADC4.
+ * @param ADCx ADC instance.
+ *
+ * @retval Returned decimal value that can correspend to one or multiple channels:
+ * @rmtoll PCSEL PCSEL0 LL_ADC_CHANNEL_0
+ * PCSEL PCSEL1 LL_ADC_CHANNEL_1
+ * PCSEL PCSEL2 LL_ADC_CHANNEL_2
+ * PCSEL PCSEL3 LL_ADC_CHANNEL_3
+ * PCSEL PCSEL4 LL_ADC_CHANNEL_4
+ * PCSEL PCSEL5 LL_ADC_CHANNEL_5
+ * PCSEL PCSEL6 LL_ADC_CHANNEL_6
+ * PCSEL PCSEL7 LL_ADC_CHANNEL_7
+ * PCSEL PCSEL8 LL_ADC_CHANNEL_8
+ * PCSEL PCSEL9 LL_ADC_CHANNEL_9
+ * PCSEL PCSEL10 LL_ADC_CHANNEL_10
+ * PCSEL PCSEL11 LL_ADC_CHANNEL_11
+ * PCSEL PCSEL12 LL_ADC_CHANNEL_12
+ * PCSEL PCSEL13 LL_ADC_CHANNEL_13
+ * PCSEL PCSEL14 LL_ADC_CHANNEL_14
+ * PCSEL PCSEL15 LL_ADC_CHANNEL_15
+ * PCSEL PCSEL16 LL_ADC_CHANNEL_16
+ * PCSEL PCSEL17 LL_ADC_CHANNEL_17
+ * PCSEL PCSEL18 LL_ADC_CHANNEL_18
+ * PCSEL PCSEL19 LL_ADC_CHANNEL_19
+ *
+ * @note User helper macro @ref __LL_ADC_DECIMAL_NB_TO_CHANNEL().
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetChannelPreselection(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->PCSEL, ADC_PCSEL_PCSEL));
+}
+
+/**
+ * @brief Set ADC low power mode.
+ * @note Description of ADC low power mode:
+ * - ADC low power mode "auto power-off":
+ * the ADC automatically powers-off after a conversion and
+ * automatically wakes up when a new conversion is triggered
+ * (with startup time between trigger and start of sampling).
+ * This feature can be combined with low power mode "auto wait".
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled.
+ * @rmtoll PWRR AUTOFF LL_ADC_SetLPModeAutoPowerOff
+ * @param ADCx ADC instance
+ * @param LowPowerMode This parameter can be one of the following values:
+ * @arg @ref LL_ADC_LP_AUTOPOWEROFF_DISABLE
+ * @arg @ref LL_ADC_LP_AUTOPOWEROFF_ENABLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetLPModeAutoPowerOff(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
+{
+ MODIFY_REG(ADCx->PW, ADC4_PW_AUTOFF, LowPowerMode);
+}
+
+/**
+ * @brief Get ADC low power mode.
+ * @note Description of ADC low power mode:
+ * - ADC low power mode "auto power-off":
+ * the ADC automatically powers-off after a conversion and
+ * automatically wakes up when a new conversion is triggered
+ * (with startup time between trigger and start of sampling).
+ * This feature can be combined with low power mode "auto wait".
+ * @rmtoll PW AUTOFF LL_ADC_GetLPModeAutoPowerOff
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_LP_AUTOPOWEROFF_DISABLE
+ * @arg @ref LL_ADC_LP_AUTOPOWEROFF_ENABLE
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetLPModeAutoPowerOff(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->PW, ADC4_PW_AUTOFF));
+}
+
+/**
+ * @brief Set ADC low power mode: deep power down in autonomous mode
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled.
+ * @rmtoll PWRR DPD LL_ADC_SetLPModeAutonomousDPD
+ * @param ADCx ADC instance
+ * @param LowPowerMode This parameter can be one of the following values:
+ * @arg @ref LL_ADC_LP_AUTONOMOUS_DPD_DISABLE
+ * @arg @ref LL_ADC_LP_AUTONOMOUS_DPD_ENABLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetLPModeAutonomousDPD(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
+{
+ MODIFY_REG(ADCx->PW, ADC4_PW_DPD, LowPowerMode);
+}
+
+/**
+ * @brief Get ADC low power mode: deep power down in autonomous mode
+ * @rmtoll PWRR DPD LL_ADC_GetLPModeAutonomousDPD
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_LP_AUTONOMOUS_DPD_DISABLE
+ * @arg @ref LL_ADC_LP_AUTONOMOUS_DPD_ENABLE
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetLPModeAutonomousDPD(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->PW, ADC4_PW_DPD));
+}
+
+/**
+ * @brief Set ADC continuous conversion mode on ADC group regular.
+ * @note Description of ADC continuous conversion mode:
+ * - single mode: one conversion per trigger
+ * - continuous mode: after the first trigger, following
+ * conversions launched successively automatically.
+ * @note It is not possible to enable both ADC group regular
+ * continuous mode and sequencer discontinuous mode.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll CFGR CONT LL_ADC_REG_SetContinuousMode
+ * @param ADCx ADC instance
+ * @param Continuous This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_CONV_SINGLE
+ * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
+{
+ MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CONT, Continuous);
+}
+
+/**
+ * @brief Get ADC continuous conversion mode on ADC group regular.
+ * @note Description of ADC continuous conversion mode:
+ * - single mode: one conversion per trigger
+ * - continuous mode: after the first trigger, following
+ * conversions launched successively automatically.
+ * @rmtoll CFGR CONT LL_ADC_REG_GetContinuousMode
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_CONV_SINGLE
+ * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT));
+}
+/**
+ * @brief Set ADC data transfer mode
+ * @note Conversion data can be either:
+ * - Available in Data Register
+ * - Transferred by DMA in one shot mode
+ * - Transferred by DMA in circular mode
+ * - Transferred to MDF data register
+ * @rmtoll CFGR DMNGT LL_ADC_REG_SetDataTransferMode
+ * @param ADCx ADC instance
+ * @param DataTransferMode Select Data Management configuration
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetDataTransferMode(ADC_TypeDef *ADCx, uint32_t DataTransferMode)
+{
+ MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DMNGT, DataTransferMode);
+}
+
+/**
+ * @brief Get ADC data transfer mode
+ * @note Conversion data can be either:
+ * - Available in Data Register
+ * - Transferred by DMA in one shot mode
+ * - Transferred by DMA in circular mode
+ * - Transferred to DFSDM data register
+ * @rmtoll CFGR DMNGT LL_ADC_REG_GetDataTransferMode
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_DR_TRANSFER
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
+ * @arg @ref LL_ADC_REG_MDF_TRANSFER
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetDataTransferMode(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMNGT));
+}
+
+/**
+ * @brief Set ADC group regular conversion data transfer: no transfer or
+ * transfer by DMA, and DMA requests mode.
+ * @note If transfer by DMA selected, specifies the DMA requests
+ * mode:
+ * - Limited mode (One shot mode): DMA transfer requests are stopped
+ * when number of DMA data transfers (number of
+ * ADC conversions) is reached.
+ * This ADC mode is intended to be used with DMA mode non-circular.
+ * - Unlimited mode: DMA transfer requests are unlimited,
+ * whatever number of DMA data transfers (number of
+ * ADC conversions).
+ * This ADC mode is intended to be used with DMA mode circular.
+ * @note If ADC DMA requests mode is set to unlimited and DMA is set to
+ * mode non-circular:
+ * when DMA transfers size will be reached, DMA will stop transfers of
+ * ADC conversions data ADC will raise an overrun error
+ * (overrun flag and interruption if enabled).
+ * @note To configure DMA source address (peripheral address),
+ * use function @ref LL_ADC_DMA_GetRegAddr().
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll CFGR1 DMAEN LL_ADC_REG_SetDMATransfer
+ * CFGR1 DMACFG LL_ADC_REG_SetDMATransfer
+ * @param ADCx ADC instance
+ * @param DMATransfer This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
+{
+ MODIFY_REG(ADCx->CFGR1, ADC4_CFGR1_DMAEN | ADC4_CFGR1_DMACFG, DMATransfer);
+}
+
+/**
+ * @brief Get ADC group regular conversion data transfer: no transfer or
+ * transfer by DMA, and DMA requests mode.
+ * @note If transfer by DMA selected, specifies the DMA requests
+ * mode:
+ * - Limited mode (One shot mode): DMA transfer requests are stopped
+ * when number of DMA data transfers (number of
+ * ADC conversions) is reached.
+ * This ADC mode is intended to be used with DMA mode non-circular.
+ * - Unlimited mode: DMA transfer requests are unlimited,
+ * whatever number of DMA data transfers (number of
+ * ADC conversions).
+ * This ADC mode is intended to be used with DMA mode circular.
+ * @note If ADC DMA requests mode is set to unlimited and DMA is set to
+ * mode non-circular:
+ * when DMA transfers size will be reached, DMA will stop transfers of
+ * ADC conversions data ADC will raise an overrun error
+ * (overrun flag and interruption if enabled).
+ * @note To configure DMA source address (peripheral address),
+ * use function @ref LL_ADC_DMA_GetRegAddr().
+ * @rmtoll CFGR1 DMAEN LL_ADC_REG_GetDMATransfer
+ * CFGR1 DMACFG LL_ADC_REG_GetDMATransfer
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC4_CFGR1_DMAEN | ADC4_CFGR1_DMACFG));
+}
+
+/**
+ * @brief Set ADC group regular behavior in case of overrun:
+ * data preserved or overwritten.
+ * @note Compatibility with devices without feature overrun:
+ * other devices without this feature have a behavior
+ * equivalent to data overwritten.
+ * The default setting of overrun is data preserved.
+ * Therefore, for compatibility with all devices, parameter
+ * overrun should be set to data overwritten.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll CFGR OVRMOD LL_ADC_REG_SetOverrun
+ * @param ADCx ADC instance
+ * @param Overrun This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
+ * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
+{
+ MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_OVRMOD, Overrun);
+}
+
+/**
+ * @brief Get ADC group regular behavior in case of overrun:
+ * data preserved or overwritten.
+ * @rmtoll CFGR OVRMOD LL_ADC_REG_GetOverrun
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
+ * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
+ * @{
+ */
+
+/**
+ * @brief Set ADC group injected conversion trigger source:
+ * internal (SW start) or from external peripheral (timer event,
+ * external interrupt line).
+ * @note On this STM32 series, setting trigger source to external trigger
+ * also set trigger polarity to rising edge
+ * (default setting for compatibility with some ADC on other
+ * STM32 families having this setting set by HW default value).
+ * In case of need to modify trigger edge, use
+ * function @ref LL_ADC_INJ_SetTriggerEdge().
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must not be disabled. Can be enabled with or without conversion
+ * on going on either groups regular or injected.
+ * @rmtoll JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource
+ * JSQR JEXTEN LL_ADC_INJ_SetTriggerSource
+ * @param ADCx ADC instance
+ * @param TriggerSource This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_CH1
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
+{
+ MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
+}
+
+/**
+ * @brief Get ADC group injected conversion trigger source:
+ * internal (SW start) or from external peripheral (timer event,
+ * external interrupt line).
+ * @note To determine whether group injected trigger source is
+ * internal (SW start) or external, without detail
+ * of which peripheral is selected as external trigger,
+ * (equivalent to
+ * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
+ * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource
+ * JSQR JEXTEN LL_ADC_INJ_GetTriggerSource
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_CH1
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
+{
+ __IO uint32_t trigger_source = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
+
+ /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
+ /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */
+ uint32_t shift_jexten = ((trigger_source & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
+
+ /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */
+ /* to match with triggers literals definition. */
+ return ((trigger_source
+ & (ADC_INJ_TRIG_SOURCE_MASK >> shift_jexten) & ADC_JSQR_JEXTSEL)
+ | ((ADC_INJ_TRIG_EDGE_MASK >> shift_jexten) & ADC_JSQR_JEXTEN)
+ );
+}
+
+/**
+ * @brief Get ADC group injected conversion trigger source internal (SW start)
+ or external
+ * @note In case of group injected trigger source set to external trigger,
+ * to determine which peripheral is selected as external trigger,
+ * use function @ref LL_ADC_INJ_GetTriggerSource.
+ * @rmtoll JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
+ * @param ADCx ADC instance
+ * @retval Value "0" if trigger source external trigger
+ * Value "1" if trigger source SW start.
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set ADC group injected conversion trigger polarity.
+ * Applicable only for trigger source set to external trigger.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must not be disabled. Can be enabled with or without conversion
+ * on going on either groups regular or injected.
+ * @rmtoll JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge
+ * @param ADCx ADC instance
+ * @param ExternalTriggerEdge This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
+{
+ MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
+}
+
+/**
+ * @brief Get ADC group injected conversion trigger polarity.
+ * Applicable only for trigger source set to external trigger.
+ * @rmtoll JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
+}
+
+/**
+ * @brief Set ADC group injected sequencer length and scan direction.
+ * @note This function performs configuration of:
+ * - Sequence length: Number of ranks in the scan sequence.
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from rank 1 to rank n).
+ * @note Sequencer disabled is equivalent to sequencer of 1 rank:
+ * ADC conversion on only 1 channel.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must not be disabled. Can be enabled with or without conversion
+ * on going on either groups regular or injected.
+ * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
+ * @param ADCx ADC instance
+ * @param SequencerNbRanks This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
+{
+ MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
+}
+
+/**
+ * @brief Get ADC group injected sequencer length and scan direction.
+ * @note This function retrieves:
+ * - Sequence length: Number of ranks in the scan sequence.
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from rank 1 to rank n).
+ * @note Sequencer disabled is equivalent to sequencer of 1 rank:
+ * ADC conversion on only 1 channel.
+ * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
+}
+
+/**
+ * @brief Set ADC group injected sequencer discontinuous mode:
+ * sequence subdivided and scan conversions interrupted every selected
+ * number of ranks.
+ * @note It is not possible to enable both ADC group injected
+ * auto-injected mode and sequencer discontinuous mode.
+ * @rmtoll CFGR JDISCEN LL_ADC_INJ_SetSequencerDiscont
+ * @param ADCx ADC instance
+ * @param SeqDiscont This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
+{
+ MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_JDISCEN, SeqDiscont);
+}
+
+/**
+ * @brief Get ADC group injected sequencer discontinuous mode:
+ * sequence subdivided and scan conversions interrupted every selected
+ * number of ranks.
+ * @rmtoll CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_JDISCEN));
+}
+
+/**
+ * @brief Set ADC group injected sequence: channel on the selected
+ * sequence rank.
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note On this STM32 series, to measure internal channels (VrefInt,
+ * TempSensor, ...), measurement paths to internal channels must be
+ * enabled separately.
+ * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+ * @note On STM32U5, some fast channels are available: fast analog inputs
+ * coming from GPIO pads (ADC_IN0..5).
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must not be disabled. Can be enabled with or without conversion
+ * on going on either groups regular or injected.
+ * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks
+ * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks
+ * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks
+ * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0 (3)
+ * @arg @ref LL_ADC_CHANNEL_1 (3)
+ * @arg @ref LL_ADC_CHANNEL_2 (3)
+ * @arg @ref LL_ADC_CHANNEL_3 (3)
+ * @arg @ref LL_ADC_CHANNEL_4 (3)
+ * @arg @ref LL_ADC_CHANNEL_5 (3)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_19
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
+ *
+ * (1) On STM32U5, parameter available only on ADC instance: ADC1/2.
+ * (2) On STM32U5, parameter available only on ADC instance: ADC4.
+ * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
+{
+ /* Set bits with content of parameter "Channel" with bits position */
+ /* in register depending on parameter "Rank". */
+ /* Parameters "Rank" and "Channel" are used with masks because containing */
+ /* other bits reserved for other purpose. */
+ MODIFY_REG(ADCx->JSQR,
+ (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
+ ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
+ << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
+}
+
+/**
+ * @brief Get ADC group injected sequence: channel on the selected
+ * sequence rank.
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note Usage of the returned channel number:
+ * - To reinject this channel into another function LL_ADC_xxx:
+ * the returned channel number is only partly formatted on definition
+ * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+ * with parts of literals LL_ADC_CHANNEL_x or using
+ * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Then the selected literal LL_ADC_CHANNEL_x can be used
+ * as parameter for another function.
+ * - To get the channel number in decimal format:
+ * process the returned value with the helper macro
+ * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * @rmtoll JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks
+ * JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks
+ * JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks
+ * JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0 (3)
+ * @arg @ref LL_ADC_CHANNEL_1 (3)
+ * @arg @ref LL_ADC_CHANNEL_2 (3)
+ * @arg @ref LL_ADC_CHANNEL_3 (3)
+ * @arg @ref LL_ADC_CHANNEL_4 (3)
+ * @arg @ref LL_ADC_CHANNEL_5 (3)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_19
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
+ *
+ * (1) On STM32U5, parameter available only on ADC instance: ADC1/2.
+ * (2) On STM32U5, parameter available only on ADC instance: ADC4.
+ * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).
+ * (1, 2) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ return (uint32_t)((READ_BIT(ADCx->JSQR,
+ (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
+ << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
+ >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
+ );
+}
+
+/**
+ * @brief Set ADC group injected conversion trigger:
+ * independent or from ADC group regular.
+ * @note This mode can be used to extend number of data registers
+ * updated after one ADC conversion trigger and with data
+ * permanently kept (not erased by successive conversions of scan of
+ * ADC sequencer ranks), up to 5 data registers:
+ * 1 data register on ADC group regular, 4 data registers
+ * on ADC group injected.
+ * @note If ADC group injected injected trigger source is set to an
+ * external trigger, this feature must be must be set to
+ * independent trigger.
+ * ADC group injected automatic trigger is compliant only with
+ * group injected trigger source set to SW start, without any
+ * further action on ADC group injected conversion start or stop:
+ * in this case, ADC group injected is controlled only
+ * from ADC group regular.
+ * @note It is not possible to enable both ADC group injected
+ * auto-injected mode and sequencer discontinuous mode.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR JAUTO LL_ADC_INJ_SetTrigAuto
+ * @param ADCx ADC instance
+ * @param TrigAuto This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
+ * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
+{
+ MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_JAUTO, TrigAuto);
+}
+
+/**
+ * @brief Get ADC group injected conversion trigger:
+ * independent or from ADC group regular.
+ * @rmtoll CFGR JAUTO LL_ADC_INJ_GetTrigAuto
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
+ * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_JAUTO));
+}
+
+/**
+ * @brief Set one context on ADC group injected that will be checked in
+ * contexts queue.
+ * @note A context is a setting of group injected sequencer:
+ * - group injected trigger
+ * - sequencer length
+ * - sequencer ranks
+ * This function is intended to be used when contexts queue is enabled,
+ * because the sequence must be fully configured in one time
+ * (functions to set separately injected trigger and sequencer channels
+ * cannot be used):
+ * @note In the contexts queue, only the active context can be read.
+ * The parameters of this function can be read using functions:
+ * @arg @ref LL_ADC_INJ_GetTriggerSource()
+ * @arg @ref LL_ADC_INJ_GetTriggerEdge()
+ * @arg @ref LL_ADC_INJ_GetSequencerRanks()
+ * @note On this STM32 series, to measure internal channels (VrefInt,
+ * TempSensor, ...), measurement paths to internal channels must be
+ * enabled separately.
+ * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+ * @note On STM32U5, some fast channels are available: fast analog inputs
+ * coming from GPIO pads (ADC_IN0..5).
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must not be disabled. Can be enabled with or without conversion
+ * on going on either groups regular or injected.
+ * @rmtoll JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext
+ * JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext
+ * JSQR JL LL_ADC_INJ_ConfigQueueContext
+ * JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext
+ * JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext
+ * JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext
+ * JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext
+ * @param ADCx ADC instance
+ * @param TriggerSource This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_CH1
+ * @param ExternalTriggerEdge This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
+ *
+ * Note: This parameter is discarded in case of SW start:
+ * parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
+ * @param SequencerNbRanks This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+ * @param Rank1_Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0 (3)
+ * @arg @ref LL_ADC_CHANNEL_1 (3)
+ * @arg @ref LL_ADC_CHANNEL_2 (3)
+ * @arg @ref LL_ADC_CHANNEL_3 (3)
+ * @arg @ref LL_ADC_CHANNEL_4 (3)
+ * @arg @ref LL_ADC_CHANNEL_5 (3)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_19
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
+ *
+ * (1) On STM32U5, parameter available only on ADC instance: ADC1/2.
+ * (2) On STM32U5, parameter available only on ADC instance: ADC4.
+ * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).
+ * @param Rank2_Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0 (3)
+ * @arg @ref LL_ADC_CHANNEL_1 (3)
+ * @arg @ref LL_ADC_CHANNEL_2 (3)
+ * @arg @ref LL_ADC_CHANNEL_3 (3)
+ * @arg @ref LL_ADC_CHANNEL_4 (3)
+ * @arg @ref LL_ADC_CHANNEL_5 (3)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_19
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
+ *
+ * (1) On STM32U5, parameter available only on ADC instance: ADC1/2.
+ * (2) On STM32U5, parameter available only on ADC instance: ADC4.
+ * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).
+ * @param Rank3_Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0 (3)
+ * @arg @ref LL_ADC_CHANNEL_1 (3)
+ * @arg @ref LL_ADC_CHANNEL_2 (3)
+ * @arg @ref LL_ADC_CHANNEL_3 (3)
+ * @arg @ref LL_ADC_CHANNEL_4 (3)
+ * @arg @ref LL_ADC_CHANNEL_5 (3)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_19
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
+ *
+ * (1) On STM32U5, parameter available only on ADC instance: ADC1/2.
+ * (2) On STM32U5, parameter available only on ADC instance: ADC4.
+ * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).
+ * @param Rank4_Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0 (3)
+ * @arg @ref LL_ADC_CHANNEL_1 (3)
+ * @arg @ref LL_ADC_CHANNEL_2 (3)
+ * @arg @ref LL_ADC_CHANNEL_3 (3)
+ * @arg @ref LL_ADC_CHANNEL_4 (3)
+ * @arg @ref LL_ADC_CHANNEL_5 (3)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_19
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
+ *
+ * (1) On STM32U5, parameter available only on ADC instance: ADC1/2.
+ * (2) On STM32U5, parameter available only on ADC instance: ADC4.
+ * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
+ uint32_t TriggerSource,
+ uint32_t ExternalTriggerEdge,
+ uint32_t SequencerNbRanks,
+ uint32_t Rank1_Channel,
+ uint32_t Rank2_Channel,
+ uint32_t Rank3_Channel,
+ uint32_t Rank4_Channel)
+{
+ /* Set bits with content of parameter "Rankx_Channel" with bits position */
+ /* in register depending on literal "LL_ADC_INJ_RANK_x". */
+ /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */
+ /* because containing other bits reserved for other purpose. */
+ /* If parameter "TriggerSource" is set to SW start, then parameter */
+ /* "ExternalTriggerEdge" is discarded. */
+ /* "TriggerSource" is define dwith default edge (rising): */
+ /* So we need to discard the default edge else the edge will not as expected*/
+ uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
+ MODIFY_REG(ADCx->JSQR,
+ ADC_JSQR_JEXTSEL |
+ ADC_JSQR_JEXTEN |
+ ADC_JSQR_JSQ4 |
+ ADC_JSQR_JSQ3 |
+ ADC_JSQR_JSQ2 |
+ ADC_JSQR_JSQ1 |
+ ADC_JSQR_JL,
+ (TriggerSource & ADC_JSQR_JEXTSEL) |
+ (ExternalTriggerEdge * (is_trigger_not_sw)) |
+ (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
+ << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |
+ (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
+ << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |
+ (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
+ << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) |
+ (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
+ << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) |
+ SequencerNbRanks
+ );
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
+ * @{
+ */
+
+/**
+ * @brief Set sampling time of the selected ADC channel
+ * Unit: ADC clock cycles.
+ * @note On this device, sampling time is on channel scope: independently
+ * of channel mapped on ADC group regular or injected.
+ * @note In case of internal channel (VrefInt, TempSensor, ...) to be
+ * converted:
+ * sampling time constraints must be respected (sampling time can be
+ * adjusted in function of ADC clock frequency and sampling time
+ * setting).
+ * Refer to device datasheet for timings values (parameters TS_vrefint,
+ * TS_temp, ...).
+ * @note Conversion time is the addition of sampling time and processing time.
+ * On this STM32 series, ADC processing time is:
+ * - 12.5 ADC clock cycles at ADC resolution 12 bits
+ * - 10.5 ADC clock cycles at ADC resolution 10 bits
+ * - 8.5 ADC clock cycles at ADC resolution 8 bits
+ * - 6.5 ADC clock cycles at ADC resolution 6 bits
+ * @note In case of ADC conversion of internal channel (VrefInt,
+ * temperature sensor, ...), a sampling time minimum value
+ * is required.
+ * Refer to device datasheet.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime
+ * SMPR1 SMP1 LL_ADC_SetChannelSamplingTime
+ * SMPR1 SMP2 LL_ADC_SetChannelSamplingTime
+ * SMPR1 SMP3 LL_ADC_SetChannelSamplingTime
+ * SMPR1 SMP4 LL_ADC_SetChannelSamplingTime
+ * SMPR1 SMP5 LL_ADC_SetChannelSamplingTime
+ * SMPR1 SMP6 LL_ADC_SetChannelSamplingTime
+ * SMPR1 SMP7 LL_ADC_SetChannelSamplingTime
+ * SMPR1 SMP8 LL_ADC_SetChannelSamplingTime
+ * SMPR1 SMP9 LL_ADC_SetChannelSamplingTime
+ * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime
+ * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime
+ * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime
+ * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime
+ * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime
+ * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime
+ * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime
+ * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime
+ * SMPR2 SMP18 LL_ADC_SetChannelSamplingTime
+ * @param ADCx ADC instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0 (3)
+ * @arg @ref LL_ADC_CHANNEL_1 (3)
+ * @arg @ref LL_ADC_CHANNEL_2 (3)
+ * @arg @ref LL_ADC_CHANNEL_3 (3)
+ * @arg @ref LL_ADC_CHANNEL_4 (3)
+ * @arg @ref LL_ADC_CHANNEL_5 (3)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_19
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
+ *
+ * (1) On STM32U5, parameter available only on ADC instance: ADC1/2.
+ * (2) On STM32U5, parameter available only on ADC instance: ADC4.
+ * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).
+ * @param SamplingTime This parameter can be one of the following values, In case of ADC1 instance:
+ * @arg @ref LL_ADC_SAMPLINGTIME_5CYCLE
+ * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES
+ * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES
+ * @arg @ref LL_ADC_SAMPLINGTIME_20CYCLES
+ * @arg @ref LL_ADC_SAMPLINGTIME_36CYCLES
+ * @arg @ref LL_ADC_SAMPLINGTIME_68CYCLES
+ * @arg @ref LL_ADC_SAMPLINGTIME_391CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_814CYCLES
+ * @param SamplingTime This parameter can be one of the following values, In case of ADC4 instance:
+ * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
+ * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
+{
+ if (ADCx != ADC4) /* ADC1 or ADC2 */
+ {
+ /* Set bits with content of parameter "SamplingTime" with bits position */
+ /* in register and register position depending on parameter "Channel". */
+ /* Parameter "Channel" is used with masks because containing */
+ /* other bits reserved for other purpose. */
+ uint32_t shift_value = ((__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) - (10UL * ((Channel \
+ & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) \
+ >> ADC_SMPRX_REGOFFSET_POS))) * 3UL);
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) \
+ >> ADC_SMPRX_REGOFFSET_POS));
+
+ MODIFY_REG(*preg, ADC_SMPR1_SMP0 << shift_value, SamplingTime << shift_value);
+
+ }
+ else
+ {
+ /* Parameter "Channel" is used with masks because containing */
+ /* other bits reserved for other purpose. It needs to be converted to decimal */
+ /* to select the bit position */
+ MODIFY_REG(ADCx->SMPR1,
+ ADC4_SAMPLING_TIME_CH_MASK,
+ ((1UL << __LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel)) << ADC4_SMPR_SMPSEL0_BITOFFSET_POS) \
+ & (SamplingTime & ADC4_SAMPLING_TIME_CH_MASK)
+ );
+ }
+}
+
+/**
+ * @brief Get sampling time of the selected ADC channel
+ * Unit: ADC clock cycles.
+ * @note On this device, sampling time is on channel scope: independently
+ * of channel mapped on ADC group regular or injected.
+ * @note Conversion time is the addition of sampling time and processing time.
+ * On this STM32 series, ADC processing time is:
+ * - 12.5 ADC clock cycles at ADC resolution 12 bits
+ * - 10.5 ADC clock cycles at ADC resolution 10 bits
+ * - 8.5 ADC clock cycles at ADC resolution 8 bits
+ * - 6.5 ADC clock cycles at ADC resolution 6 bits
+ * @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime
+ * SMPR1 SMP1 LL_ADC_GetChannelSamplingTime
+ * SMPR1 SMP2 LL_ADC_GetChannelSamplingTime
+ * SMPR1 SMP3 LL_ADC_GetChannelSamplingTime
+ * SMPR1 SMP4 LL_ADC_GetChannelSamplingTime
+ * SMPR1 SMP5 LL_ADC_GetChannelSamplingTime
+ * SMPR1 SMP6 LL_ADC_GetChannelSamplingTime
+ * SMPR1 SMP7 LL_ADC_GetChannelSamplingTime
+ * SMPR1 SMP8 LL_ADC_GetChannelSamplingTime
+ * SMPR1 SMP9 LL_ADC_GetChannelSamplingTime
+ * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime
+ * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime
+ * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime
+ * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime
+ * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime
+ * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime
+ * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime
+ * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime
+ * SMPR2 SMP18 LL_ADC_GetChannelSamplingTime
+ * @param ADCx ADC instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0 (3)
+ * @arg @ref LL_ADC_CHANNEL_1 (3)
+ * @arg @ref LL_ADC_CHANNEL_2 (3)
+ * @arg @ref LL_ADC_CHANNEL_3 (3)
+ * @arg @ref LL_ADC_CHANNEL_4 (3)
+ * @arg @ref LL_ADC_CHANNEL_5 (3)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_19
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
+ * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
+ *
+ * (1) On STM32U5, parameter available only on ADC instance: ADC1/2.
+ * (2) On STM32U5, parameter available only on ADC instance: ADC4.
+ * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).
+ * @retval In case of ADC1 insatnace, Returned value can be one of the following values:
+ * @arg @ref LL_ADC_SAMPLINGTIME_5CYCLE
+ * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES
+ * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES
+ * @arg @ref LL_ADC_SAMPLINGTIME_20CYCLES
+ * @arg @ref LL_ADC_SAMPLINGTIME_36CYCLES
+ * @arg @ref LL_ADC_SAMPLINGTIME_68CYCLES
+ * @arg @ref LL_ADC_SAMPLINGTIME_391CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_814CYCLES
+ * @retval In case of ADC4 insatnce, Returned value can be one of the following values:
+ * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
+ * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
+{
+ if (ADCx != ADC4) /* (ADCx == ADC1) || (ADCx == ADC2) */
+ {
+ uint32_t shift_value = ((__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) - (10UL * ((Channel \
+ & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) \
+ >> ADC_SMPRX_REGOFFSET_POS))) * 3UL);
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) \
+ >> ADC_SMPRX_REGOFFSET_POS));
+
+ return (uint32_t)(READ_BIT(*preg, ADC_SMPR1_SMP0 << shift_value) >> shift_value);
+ }
+ else /* ADCx == ADC4 */
+ {
+ uint32_t smpr = READ_REG(ADCx->SMPR1);
+
+ /* Retrieve sampling time bit corresponding to the selected channel */
+ /* and shift it to position 0. */
+ uint32_t smp_channel_posbit0 = ((smpr & ADC4_SAMPLING_TIME_CH_MASK)
+ >> ((((Channel & ADC_CHANNEL_ID_NUMBER_MASK) \
+ >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
+ + ADC4_SMPR_SMPSEL0_BITOFFSET_POS)
+ & 0x1FUL));
+
+ /* Select sampling time bitfield depending on sampling time bit value 0 or 1. */
+ return ((~(smp_channel_posbit0) * LL_ADC_SAMPLINGTIME_COMMON_1)
+ | (smp_channel_posbit0 * LL_ADC_SAMPLINGTIME_COMMON_2));
+ }
+}
+
+/**
+ * @brief Set mode single-ended or differential input of the selected
+ * ADC channel.
+ * @note Channel ending is on channel scope: independently of channel mapped
+ * on ADC group regular or injected.
+ * In differential mode: Differential measurement is carried out
+ * between the selected channel 'i' (positive input) and
+ * channel 'i+1' (negative input). Only channel 'i' has to be
+ * configured, channel 'i+1' is configured automatically.
+ * @note Refer to Reference Manual to ensure the selected channel is
+ * available in differential mode.
+ * For example, internal channels (VrefInt, TempSensor, ...) are
+ * not available in differential mode.
+ * @note When configuring a channel 'i' in differential mode,
+ * the channel 'i+1' is not usable separately.
+ * @note On STM32U5, some channels are internally fixed to single-ended inputs
+ * configuration:
+ * - ADC1: Channels 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17
+ * - ADC2: Channels 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17
+ * - ADC4: None
+ * @note For ADC channels configured in differential mode, both inputs
+ * should be biased at (Vref+)/2 +/-200mV.
+ * (Vref+ is the analog voltage reference)
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be ADC disabled.
+ * @note One or several values can be selected.
+ * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
+ * @rmtoll DIFSEL DIFSEL LL_ADC_SetChannelSingleDiff
+ * @param ADCx ADC instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_19
+ * @param SingleDiff This parameter can be a combination of the following values:
+ * @arg @ref LL_ADC_SINGLE_ENDED
+ * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
+{
+ /* Bits of channels in single or differential mode are set only for */
+ /* differential mode (for single mode, mask of bits allowed to be set is */
+ /* shifted out of range of bits of channels in single or differential mode. */
+ MODIFY_REG(ADCx->DIFSEL,
+ Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
+ (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff \
+ & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
+}
+
+/**
+ * @brief Get mode single-ended or differential input of the selected
+ * ADC channel.
+ * @note When configuring a channel 'i' in differential mode,
+ * the channel 'i+1' is not usable separately.
+ * Therefore, to ensure a channel is configured in single-ended mode,
+ * the configuration of channel itself and the channel 'i-1' must be
+ * read back (to ensure that the selected channel channel has not been
+ * configured in differential mode by the previous channel).
+ * @note Refer to Reference Manual to ensure the selected channel is
+ * available in differential mode.
+ * For example, internal channels (VrefInt, TempSensor, ...) are
+ * not available in differential mode.
+ * @note When configuring a channel 'i' in differential mode,
+ * the channel 'i+1' is not usable separately.
+ * @note On STM32U5, some channels are internally fixed to single-ended inputs
+ * configuration:
+ * - ADC1: Channels 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17
+ * - ADC2: Channels 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17
+ * - ADC4: None
+ * @note One or several values can be selected. In this case, the value
+ * returned is null if all channels are in single ended-mode.
+ * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
+ * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSingleDiff
+ * @param ADCx ADC instance
+ * @param Channel This parameter can be a combination of the following values:
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_19
+ * @retval 0: channel in single-ended mode, else: channel in differential mode
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel)
+{
+ return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
+ * @{
+ */
+
+/**
+ * @brief Set ADC analog watchdog monitored channels:
+ * a single channel, multiple channels or all channels,
+ * on ADC groups regular and-or injected.
+ * @note Once monitored channels are selected, analog watchdog
+ * is enabled.
+ * @note In case of need to define a single channel to monitor
+ * with analog watchdog from sequencer channel definition,
+ * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
+ * @note On this STM32 series, there are 2 kinds of analog watchdog
+ * instance:
+ * - AWD standard (instance AWD1):
+ * - channels monitored: can monitor 1 channel or all channels.
+ * - groups monitored: ADC groups regular and-or injected.
+ * - resolution: resolution is not limited (corresponds to
+ * ADC resolution configured).
+ * - AWD flexible (instances AWD2, AWD3):
+ * - channels monitored: flexible on channels monitored, selection is
+ * channel wise, from from 1 to all channels.
+ * Specificity of this analog watchdog: Multiple channels can
+ * be selected. For example:
+ * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+ * - groups monitored: not selection possible (monitoring on both
+ * groups regular and injected).
+ * Channels selected are monitored on groups regular and injected:
+ * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+ * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+ * - resolution: resolution is limited to 8 bits: if ADC resolution is
+ * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
+ * the 2 LSB are ignored.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels
+ * CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels
+ * CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels
+ * CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels
+ * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels
+ * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
+ * @param ADCx ADC instance
+ * @param AWDy This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD1
+ * @arg @ref LL_ADC_AWD2
+ * @arg @ref LL_ADC_AWD3
+ * @param AWDChannelGroup This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD_DISABLE
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC4_REG (0)(2)
+ * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC4_REG (0)(2)
+ *
+ * (0) On STM32U5, parameter available only on analog watchdog number: AWD1.
+ * (1) On STM32U5, parameter available only on ADC instance: ADC1/2.
+ * (2) On STM32U5, parameter available only on ADC instance: ADC4.
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
+{
+ /* Set bits with content of parameter "AWDChannelGroup" with bits position */
+ /* in register and register position depending on parameter "AWDy". */
+ /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
+ /* containing other bits reserved for other purpose. */
+
+ __IO uint32_t *preg;
+ uint32_t channel_monitored;
+
+ if (AWDy == LL_ADC_AWD1)
+ {
+ /* Set pointer to register of selected analog watchdog */
+ preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, 0UL);
+
+ /* Compute channel monitored as number */
+ channel_monitored = (AWDChannelGroup & ADC_AWD_CR1_CHANNEL_MASK);
+ }
+ else
+ {
+ /* Set pointer to register of selected analog watchdog */
+ preg = __ADC_PTR_REG_OFFSET(ADCx->AWD2CR, ((AWDy & ADC_AWD_CR3_REGOFFSET)) >> (ADC_AWD_CRX_REGOFFSET_POS + 1UL));
+
+ /* Compute channel monitored as bitfield */
+ channel_monitored = (1UL << ((AWDChannelGroup & ADC_CHANNEL_ID_NUMBER_MASK) \
+ >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS));
+ /* Case of all channels monitored */
+ channel_monitored |= ((1UL - ((AWDChannelGroup & ADC_CFGR1_AWD1SGL) >> ADC_CFGR1_AWD1SGL_Pos)) * 0x00FFFFFFUL);
+ /* Case of no channel monitored */
+ channel_monitored *= ((((AWDChannelGroup & (ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN)) == 0UL) ? 0UL : 1UL));
+ }
+
+ MODIFY_REG(*preg, (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK), channel_monitored);
+}
+
+/**
+ * @brief Get ADC analog watchdog monitored channel.
+ * @note Usage of the returned channel number:
+ * - To reinject this channel into another function LL_ADC_xxx:
+ * the returned channel number is only partly formatted on definition
+ * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+ * with parts of literals LL_ADC_CHANNEL_x or using
+ * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Then the selected literal LL_ADC_CHANNEL_x can be used
+ * as parameter for another function.
+ * - To get the channel number in decimal format:
+ * process the returned value with the helper macro
+ * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Applicable only when the analog watchdog is set to monitor
+ * one channel.
+ * @note On this STM32 series, there are 2 kinds of analog watchdog
+ * instance:
+ * - AWD standard (instance AWD1):
+ * - channels monitored: can monitor 1 channel or all channels.
+ * - groups monitored: ADC groups regular and-or injected.
+ * - resolution: resolution is not limited (corresponds to
+ * ADC resolution configured).
+ * - AWD flexible (instances AWD2, AWD3):
+ * - channels monitored: flexible on channels monitored, selection is
+ * channel wise, from from 1 to all channels.
+ * Specificity of this analog watchdog: Multiple channels can
+ * be selected. For example:
+ * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+ * - groups monitored: not selection possible (monitoring on both
+ * groups regular and injected).
+ * Channels selected are monitored on groups regular and injected:
+ * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+ * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+ * - resolution: resolution is limited to 8 bits: if ADC resolution is
+ * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
+ * the 2 LSB are ignored.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels
+ * CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels
+ * CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels
+ * CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels
+ * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels
+ * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
+ * @param ADCx ADC instance
+ * @param AWDy This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD1
+ * @arg @ref LL_ADC_AWD2 (1)
+ * @arg @ref LL_ADC_AWD3 (1)
+ *
+ * (1) On this AWD number, monitored channel can be retrieved
+ * if only 1 channel is programmed (or none or all channels).
+ * This function cannot retrieve monitored channel if
+ * multiple channels are programmed simultaneously
+ * by bitfield.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_AWD_DISABLE
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ
+ *
+ * (0) On STM32U5, parameter available only on analog watchdog number: AWD1.
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
+{
+ const __IO uint32_t *preg;
+
+ if (AWDy == LL_ADC_AWD1)
+ {
+ /* Set pointer to register of selected analog watchdog */
+ preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, 0UL);
+ }
+ else
+ {
+ /* Set pointer to register of selected analog watchdog */
+ preg = __ADC_PTR_REG_OFFSET(ADCx->AWD2CR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK)) \
+ >> (ADC_AWD_CRX_REGOFFSET_POS + 1UL));
+ }
+
+ uint32_t analog_wd_monit_channels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
+
+ /* If "analog_wd_monit_channels" == 0, then the selected AWD is disabled */
+ /* (parameter value LL_ADC_AWD_DISABLE). */
+ /* Else, the selected AWD is enabled and is monitoring a group of channels */
+ /* or a single channel. */
+ if (analog_wd_monit_channels != 0UL)
+ {
+ if (AWDy == LL_ADC_AWD1)
+ {
+ if ((analog_wd_monit_channels & ADC_CFGR1_AWD1SGL) == 0UL)
+ {
+ /* AWD monitoring a group of channels */
+ analog_wd_monit_channels = ((analog_wd_monit_channels | (0x000FFFFFUL)) & (~(ADC_CFGR1_AWD1CH)));
+ }
+ else
+ {
+ /* AWD monitoring a single channel */
+ analog_wd_monit_channels = analog_wd_monit_channels;
+ }
+ }
+ else
+ {
+ if (ADCx == ADC1)
+ {
+ if ((analog_wd_monit_channels & 0x000FFFFFUL) == 0x000FFFFFUL)
+ {
+ /* AWD monitoring a group of channels */
+ analog_wd_monit_channels = (0x000FFFFFUL | ((ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN)));
+ }
+ else
+ {
+ /* AWD monitoring a single channel */
+ /* AWD monitoring a group of channels */
+ analog_wd_monit_channels = ((ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
+ | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(analog_wd_monit_channels) \
+ << ADC_CFGR1_AWD1CH_Pos));
+ }
+ }
+ else
+ {
+ if ((analog_wd_monit_channels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
+ {
+ /* AWD monitoring a group of channels */
+ analog_wd_monit_channels = (0x000FFFFFUL | (ADC_CFGR1_AWD1EN));
+ }
+ else
+ {
+ /* AWD monitoring a single channel */
+ /* AWD monitoring a group of channels */
+ analog_wd_monit_channels = ((ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
+ | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(analog_wd_monit_channels) \
+ << ADC_CFGR1_AWD1CH_Pos));
+ }
+ }
+ }
+ }
+
+ return analog_wd_monit_channels;
+}
+
+/**
+ * @brief Set ADC analog watchdog threshold value of threshold
+ * high or low.
+ * @note In case of ADC resolution different of 12 bits,
+ * analog watchdog thresholds data require a specific shift.
+ * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
+ * @note On this STM32 series, there are 2 kinds of analog watchdog
+ * instance:
+ * - AWD standard (instance AWD1):
+ * - channels monitored: can monitor 1 channel or all channels.
+ * - groups monitored: ADC groups regular and-or injected.
+ * - resolution: resolution is not limited (corresponds to
+ * ADC resolution configured).
+ * - AWD flexible (instances AWD2, AWD3):
+ * - channels monitored: flexible on channels monitored, selection is
+ * channel wise, from from 1 to all channels.
+ * Specificity of this analog watchdog: Multiple channels can
+ * be selected. For example:
+ * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+ * - groups monitored: not selection possible (monitoring on both
+ * groups regular and injected).
+ * Channels selected are monitored on groups regular and injected:
+ * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+ * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+ * - resolution: resolution is limited to 8 bits: if ADC resolution is
+ * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
+ * the 2 LSB are ignored.
+ * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
+ * impacted: the comparison of analog watchdog thresholds is done
+ * on oversampling intermediate computation (after ratio, before shift
+ * application): intermediate register bitfield [32:7]
+ * (26 most significant bits).
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either ADC groups regular or injected.
+ * @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds
+ * TR2 HT2 LL_ADC_SetAnalogWDThresholds
+ * TR3 HT3 LL_ADC_SetAnalogWDThresholds
+ * TR1 LT1 LL_ADC_SetAnalogWDThresholds
+ * TR2 LT2 LL_ADC_SetAnalogWDThresholds
+ * TR3 LT3 LL_ADC_SetAnalogWDThresholds
+ * @param ADCx ADC instance
+ * @param AWDy This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD1
+ * @arg @ref LL_ADC_AWD2
+ * @arg @ref LL_ADC_AWD3
+ * @param AWDThresholdsHighLow This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+ * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+ * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,
+ uint32_t AWDThresholdValue)
+{
+ __IO uint32_t *preg;
+ /* Set bits with content of parameter "AWDThresholdValue" with bits */
+ /* position in register and register position depending on parameters */
+ /* "AWDThresholdsHighLow" and "AWDy". */
+ /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
+ /* containing other bits reserved for other purpose. */
+ if (ADCx == ADC1)
+ {
+ if (AWDy == LL_ADC_AWD1)
+ {
+ preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (AWDThresholdsHighLow));
+ }
+ else
+ {
+ preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) \
+ >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
+ + (AWDThresholdsHighLow));
+ }
+
+ MODIFY_REG(*preg, ADC_LTR_LT, AWDThresholdValue);
+ }
+ else /* ADCx == ADC4 */
+ {
+ if (AWDy == LL_ADC_AWD1)
+ {
+ preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, 0UL);
+ }
+ else
+ {
+ preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) >> (ADC_AWD_TRX_REGOFFSET_POS))\
+ + ((ADC_AWD_CR3_REGOFFSET & AWDy) >> (ADC_AWD_CRX_REGOFFSET_POS + 1UL)));
+ }
+
+ MODIFY_REG(*preg,
+ ADC_AWD1TR_LT1 << (AWDThresholdsHighLow * ADC_AWD1TR_HT1_Pos),
+ AWDThresholdValue << (((AWDThresholdsHighLow << ADC_AWD1TR_HT1_Pos) & ADC_AWD_TRX_BIT_HIGH_MASK) \
+ >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
+
+ }
+}
+
+/**
+ * @brief Get ADC analog watchdog threshold value of threshold high,
+ * threshold low or raw data with ADC thresholds high and low
+ * concatenated.
+ * @note In case of ADC resolution different of 12 bits,
+ * analog watchdog thresholds data require a specific shift.
+ * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
+ * @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds
+ * TR2 HT2 LL_ADC_GetAnalogWDThresholds
+ * TR3 HT3 LL_ADC_GetAnalogWDThresholds
+ * TR1 LT1 LL_ADC_GetAnalogWDThresholds
+ * TR2 LT2 LL_ADC_GetAnalogWDThresholds
+ * TR3 LT3 LL_ADC_GetAnalogWDThresholds
+ * @param ADCx ADC instance
+ * @param AWDy This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD1
+ * @arg @ref LL_ADC_AWD2
+ * @arg @ref LL_ADC_AWD3
+ * @param AWDThresholdsHighLow This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+ * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+ * @retval In case of ADC1 instance, Value between Min_Data=0x000 and Max_Data=0x1FFFFFF
+ * @retval In case of ADC1 instance, Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
+{
+ const __IO uint32_t *preg;
+ if (ADCx == ADC1)
+ {
+ if (AWDy == LL_ADC_AWD1)
+ {
+ preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (AWDThresholdsHighLow));
+ }
+ else
+ {
+ preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
+ + (AWDThresholdsHighLow));
+ }
+
+ return (uint32_t)(READ_BIT(*preg, ADC_LTR_LT));
+ }
+ else
+ {
+ if (AWDy == LL_ADC_AWD1)
+ {
+ preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, 0UL);
+
+ }
+ else
+ {
+ preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) >> (ADC_AWD_TRX_REGOFFSET_POS))\
+ + ((ADC_AWD_CR3_REGOFFSET & AWDy) >> (ADC_AWD_CRX_REGOFFSET_POS + 1UL)));
+ }
+
+ return (uint32_t)(READ_BIT(*preg,
+ (ADC_AWD1TR_LT1 << (AWDThresholdsHighLow * ADC_AWD1TR_HT1_Pos)))
+ >> (((AWDThresholdsHighLow << ADC_AWD1TR_HT1_Pos) & ADC_AWD_TRX_BIT_HIGH_MASK) \
+ >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)
+ );
+ }
+}
+
+/**
+ * @brief Set ADC analog watchdog thresholds value of both thresholds
+ * high and low.
+ * @note If value of only one threshold high or low must be set,
+ * use function @ref LL_ADC_SetAnalogWDThresholds().
+ * @note In case of ADC resolution different of 12 bits,
+ * analog watchdog thresholds data require a specific shift.
+ * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
+ * @note On this STM32 series, there are 2 kinds of analog watchdog
+ * instance:
+ * - AWD standard (instance AWD1):
+ * - channels monitored: can monitor 1 channel or all channels.
+ * - groups monitored: ADC group regular.
+ * - resolution: resolution is not limited (corresponds to
+ * ADC resolution configured).
+ * - AWD flexible (instances AWD2, AWD3):
+ * - channels monitored: flexible on channels monitored, selection is
+ * channel wise, from from 1 to all channels.
+ * Specificity of this analog watchdog: Multiple channels can
+ * be selected. For example:
+ * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+ * - groups monitored: not selection possible (monitoring on both
+ * groups regular and injected).
+ * Channels selected are monitored on groups regular and injected:
+ * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+ * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+ * - resolution: resolution is not limited (corresponds to
+ * ADC resolution configured).
+ * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
+ * impacted: the comparison of analog watchdog thresholds is done on
+ * oversampling final computation (after ratio and shift application):
+ * ADC data register bitfield [15:4] (12 most significant bits).
+ * Examples:
+ * - Oversampling ratio and shift selected to have ADC conversion data
+ * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...):
+ * ADC analog watchdog thresholds must be divided by 16.
+ * - Oversampling ratio and shift selected to have ADC conversion data
+ * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...):
+ * ADC analog watchdog thresholds must be divided by 4.
+ * - Oversampling ratio and shift selected to have ADC conversion data
+ * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...):
+ * ADC analog watchdog thresholds match directly to ADC data register.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds
+ * TR2 HT2 LL_ADC_ConfigAnalogWDThresholds
+ * TR3 HT3 LL_ADC_ConfigAnalogWDThresholds
+ * TR1 LT1 LL_ADC_ConfigAnalogWDThresholds
+ * TR2 LT2 LL_ADC_ConfigAnalogWDThresholds
+ * TR3 LT3 LL_ADC_ConfigAnalogWDThresholds
+ * @param ADCx ADC instance
+ * @param AWDy This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD1
+ * @arg @ref LL_ADC_AWD2
+ * @arg @ref LL_ADC_AWD3
+ * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue,
+ uint32_t AWDThresholdLowValue)
+{
+ __IO uint32_t *preg;
+ __IO uint32_t *preg2;
+ /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */
+ /* position in register and register position depending on parameter */
+ /* "AWDy". */
+ /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
+ /* containing other bits reserved for other purpose. */
+ if (ADCx != ADC4) /* ADC1 or ADC2 */
+ {
+ if (AWDy == LL_ADC_AWD1)
+ {
+ preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (LL_ADC_AWD_THRESHOLD_LOW));
+ preg2 = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (LL_ADC_AWD_THRESHOLD_HIGH));
+ }
+ else
+ {
+ preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) \
+ >> (ADC_AWD_TRX_REGOFFSET_POS - 1UL)))
+ + (LL_ADC_AWD_THRESHOLD_LOW));
+ preg2 = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) \
+ >> (ADC_AWD_TRX_REGOFFSET_POS - 1UL)))
+ + (LL_ADC_AWD_THRESHOLD_HIGH));
+ }
+
+ MODIFY_REG(*preg, ADC_LTR_LT, AWDThresholdLowValue);
+ MODIFY_REG(*preg2, ADC_HTR_HT, AWDThresholdHighValue);
+ }
+ else
+ {
+ if (AWDy == LL_ADC_AWD1)
+ {
+ preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, 0UL);
+ }
+ else
+ {
+ preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) >> (ADC_AWD_TRX_REGOFFSET_POS)) \
+ + ((ADC_AWD_CR3_REGOFFSET & AWDy) >> (ADC_AWD_CRX_REGOFFSET_POS + 1UL)));
+ }
+
+ MODIFY_REG(*preg,
+ ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1,
+ (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
+ }
+}
+
+/**
+ * @brief Set ADC analog watchdog filtering configuration
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @note On this STM32 series, this feature is only available on first
+ * analog watchdog (AWD1)
+ * @rmtoll TR1 AWDFILT LL_ADC_SetAWDFilteringConfiguration
+ * @param ADCx ADC instance
+ * @param AWDy This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD1
+ * @param FilteringConfig This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD_FILTERING_NONE
+ * @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
+ * @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
+ * @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
+ * @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
+ * @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
+ * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
+ * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t FilteringConfig)
+{
+ /* Prevent unused argument(s) compilation warning */
+ (void)(AWDy);
+ MODIFY_REG(ADCx->HTR1, ADC_HTR_AWDFILT, FilteringConfig);
+}
+
+/**
+ * @brief Get ADC analog watchdog filtering configuration
+ * @note On this STM32 series, this feature is only available on first
+ * analog watchdog (AWD1)
+ * @rmtoll TR1 AWDFILT LL_ADC_GetAWDFilteringConfiguration
+ * @param ADCx ADC instance
+ * @param AWDy This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD1
+ * @retval Returned value can be:
+ * @arg @ref LL_ADC_AWD_FILTERING_NONE
+ * @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
+ * @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
+ * @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
+ * @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
+ * @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
+ * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
+ * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy)
+{
+ /* Prevent unused argument(s) compilation warning */
+ (void)(AWDy);
+ return (uint32_t)(READ_BIT(ADCx->HTR1, ADC_HTR_AWDFILT));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
+ * @{
+ */
+
+/**
+ * @brief Set ADC oversampling scope: ADC groups regular and-or injected
+ * (availability of ADC group injected depends on STM32 families).
+ * @note If both groups regular and injected are selected,
+ * specify behavior of ADC group injected interrupting
+ * group regular: when ADC group injected is triggered,
+ * the oversampling on ADC group regular is either
+ * temporary stopped and continued, or resumed from start
+ * (oversampler buffer reset).
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR2 ROVSE LL_ADC_SetOverSamplingScope
+ * CFGR2 JOVSE LL_ADC_SetOverSamplingScope
+ * CFGR2 ROVSM LL_ADC_SetOverSamplingScope
+ * @param ADCx ADC instance
+ * @param OvsScope This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OVS_DISABLE
+ * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
+ * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
+ * @arg @ref LL_ADC_OVS_GRP_INJECTED
+ * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
+{
+ if (ADCx == ADC1)
+ {
+ MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);
+ }
+ else
+ {
+ MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE, OvsScope);
+ }
+}
+
+/**
+ * @brief Get ADC oversampling scope: ADC groups regular and-or injected
+ * (availability of ADC group injected depends on STM32 families).
+ * @note If both groups regular and injected are selected,
+ * specify behavior of ADC group injected interrupting
+ * group regular: when ADC group injected is triggered,
+ * the oversampling on ADC group regular is either
+ * temporary stopped and continued, or resumed from start
+ * (oversampler buffer reset).
+ * @rmtoll CFGR2 ROVSE LL_ADC_GetOverSamplingScope
+ * CFGR2 JOVSE LL_ADC_GetOverSamplingScope
+ * CFGR2 ROVSM LL_ADC_GetOverSamplingScope
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_OVS_DISABLE
+ * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
+ * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
+ * @arg @ref LL_ADC_OVS_GRP_INJECTED
+ * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx)
+{
+ if (ADCx == ADC1)
+ {
+ return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
+ }
+ else
+ {
+ return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE));
+ }
+}
+
+/**
+ * @brief Set ADC oversampling discontinuous mode (triggered mode)
+ * on the selected ADC group.
+ * @note Number of oversampled conversions are done either in:
+ * - continuous mode (all conversions of oversampling ratio
+ * are done from 1 trigger)
+ * - discontinuous mode (each conversion of oversampling ratio
+ * needs a trigger)
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @note On this STM32 series, oversampling discontinuous mode
+ * (triggered mode) can be used only when oversampling is
+ * set on group regular only and in resumed mode.
+ * @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont
+ * @param ADCx ADC instance
+ * @param OverSamplingDiscont This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OVS_REG_CONT
+ * @arg @ref LL_ADC_OVS_REG_DISCONT
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
+{
+ MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
+}
+
+/**
+ * @brief Get ADC oversampling discontinuous mode (triggered mode)
+ * on the selected ADC group.
+ * @note Number of oversampled conversions are done either in:
+ * - continuous mode (all conversions of oversampling ratio
+ * are done from 1 trigger)
+ * - discontinuous mode (each conversion of oversampling ratio
+ * needs a trigger)
+ * @rmtoll CFGR2 TROVS LL_ADC_GetOverSamplingDiscont
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_OVS_REG_CONT
+ * @arg @ref LL_ADC_OVS_REG_DISCONT
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
+}
+
+/**
+ * @brief Set ADC oversampling
+ * (impacting both ADC groups regular and injected)
+ * @note This function set the 2 items of oversampling configuration:
+ * - ratio
+ * - shift
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift
+ * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift
+ * @param ADCx ADC instance
+ * @param Ratio This parameter can be in the range from 1 to 1024 in case of ADC1 instance.
+ * @param Ratio This parameter can be one of the following values, in case of ADC4 :
+ * @arg @ref LL_ADC_OVS_RATIO_2
+ * @arg @ref LL_ADC_OVS_RATIO_4
+ * @arg @ref LL_ADC_OVS_RATIO_8
+ * @arg @ref LL_ADC_OVS_RATIO_16
+ * @arg @ref LL_ADC_OVS_RATIO_32
+ * @arg @ref LL_ADC_OVS_RATIO_64
+ * @arg @ref LL_ADC_OVS_RATIO_128
+ * @arg @ref LL_ADC_OVS_RATIO_256
+ * @param Shift This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OVS_SHIFT_NONE
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_9 (1)
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_10 (1)
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_11 (1)
+ *
+ * (1): Only for ADC1 instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
+{
+ if (ADCx == ADC1)
+ {
+ MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | (((Ratio - 1UL) << ADC_CFGR2_OVSR_Pos))));
+ }
+ else /* ADCx == ADC4 */
+ {
+ MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC4_CFGR2_OVSR), (Shift | Ratio));
+ }
+}
+
+/**
+ * @brief Get ADC oversampling ratio
+ * (impacting both ADC groups regular and injected)
+ * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio
+ * @param ADCx ADC instance
+ * @retval Ratio This parameter can be in the from 1 to 1024.
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)
+{
+ if (ADCx == ADC1)
+ {
+ return (((uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)) + (1UL << ADC_CFGR2_OVSR_Pos)) >> ADC_CFGR2_OVSR_Pos);
+ }
+ else /* ADCx == ADC4 */
+ {
+ return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC4_CFGR2_OVSR));
+ }
+}
+
+/**
+ * @brief Get ADC oversampling shift
+ * (impacting both ADC groups regular and injected)
+ * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift
+ * @param ADCx ADC instance
+ * @retval Shift This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OVS_SHIFT_NONE
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_9 (1)
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_10 (1)
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_11 (1)
+ *
+ * (1): Only for ADC1 instance.
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
+}
+
+
+/**
+ * @}
+ */
+/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
+ * @{
+ */
+
+/**
+ * @brief Put ADC instance in deep power down state.
+ * @note In case of ADC calibration necessary: When ADC is in deep-power-down
+ * state, the internal analog calibration is lost. After exiting from
+ * deep power down, calibration must be relaunched or calibration factor
+ * (preliminarily saved) must be set back into calibration register.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be ADC disabled.
+ * @rmtoll CR DEEPPWD LL_ADC_EnableDeepPowerDown
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)
+{
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_DEEPPWD);
+}
+
+/**
+ * @brief Disable ADC deep power down mode.
+ * @note In case of ADC calibration necessary: When ADC is in deep-power-down
+ * state, the internal analog calibration is lost. After exiting from
+ * deep power down, calibration must be relaunched or calibration factor
+ * (preliminarily saved) must be set back into calibration register.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be ADC disabled.
+ * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
+{
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
+}
+
+/**
+ * @brief Get the selected ADC instance deep power down state.
+ * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled
+ * @param ADCx ADC instance
+ * @retval 0: deep power down is disabled, 1: deep power down is enabled.
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable ADC instance internal voltage regulator.
+ * @note On this STM32 series, after ADC internal voltage regulator enable,
+ * a delay for ADC internal voltage regulator stabilization
+ * is required before performing a ADC calibration or ADC enable.
+ * Refer to device datasheet, parameter tADCVREG_STUP.
+ * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be ADC disabled.
+ * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
+{
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADVREGEN);
+}
+
+/**
+ * @brief Disable ADC internal voltage regulator.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be ADC disabled.
+ * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
+}
+
+/**
+ * @brief Get the selected ADC instance internal voltage regulator state.
+ * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
+ * @param ADCx ADC instance
+ * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable the selected ADC instance.
+ * @note On this STM32 series, after ADC enable, a delay for
+ * ADC internal analog stabilization is required before performing a
+ * ADC conversion start.
+ * Refer to device datasheet, parameter tSTAB.
+ * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+ * is enabled and when conversion clock is active.
+ * (not only core clock: this ADC has a dual clock domain)
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be ADC disabled and ADC internal voltage regulator enabled.
+ * @rmtoll CR ADEN LL_ADC_Enable
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
+{
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADEN);
+}
+
+/**
+ * @brief Disable the selected ADC instance.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be not disabled. Must be enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CR ADDIS LL_ADC_Disable
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
+{
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADDIS);
+}
+
+/**
+ * @brief Get the selected ADC instance enable state.
+ * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+ * is enabled and when conversion clock is active.
+ * (not only core clock: this ADC has a dual clock domain)
+ * @rmtoll CR ADEN LL_ADC_IsEnabled
+ * @param ADCx ADC instance
+ * @retval 0: ADC is disabled, 1: ADC is enabled.
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get the selected ADC instance disable state.
+ * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
+ * @param ADCx ADC instance
+ * @retval 0: no ADC disable command on going.
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Start ADC calibration in the mode single-ended
+ * or differential (for devices with differential mode available).
+ * @note On this STM32 series, a minimum number of ADC clock cycles
+ * are required between ADC end of calibration and ADC enable.
+ * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
+ * @note Calibration duration:
+ * - Calibration of offset: 520 ADC clock cycles
+ * - Calibration of linearity: 131072 ADC clock cycles
+ * @note For devices with differential mode available:
+ * Calibration of offset is specific to each of
+ * single-ended and differential modes
+ * (calibration run must be performed for each of these
+ * differential modes, if used afterwards and if the application
+ * requires their calibration).
+ * Calibration of linearity is common to both
+ * single-ended and differential modes
+ * (calibration run can be performed only once).
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be ADC disabled.
+ * @rmtoll CR ADCAL LL_ADC_StartCalibration
+ * CR ADCALDIF LL_ADC_StartCalibration
+ * CR ADCALLIN LL_ADC_StartCalibration
+ * @param ADCx ADC instance
+ * @param CalibrationMode This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CALIB_OFFSET
+ * @arg @ref LL_ADC_CALIB_OFFSET_LINEARITY
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t CalibrationMode)
+{
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ if (ADCx != ADC4) /* ADC1 or ADC2 */
+ {
+ MODIFY_REG(ADCx->CR,
+ ADC_CR_ADCALLIN | ADC_CR_BITS_PROPERTY_RS,
+ ADC_CR_ADCAL | (CalibrationMode & ADC_CALIB_MODE_MASK));
+ }
+ else
+ {
+ MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADCAL);
+ }
+}
+
+/**
+ * @brief Get ADC calibration state.
+ * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
+ * @param ADCx ADC instance
+ * @retval 0: calibration complete, 1: calibration in progress.
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
+ * @{
+ */
+
+/**
+ * @brief Start ADC group regular conversion.
+ * @note On this STM32 series, this function is relevant for both
+ * internal trigger (SW start) and external trigger:
+ * - If ADC trigger has been set to software start, ADC conversion
+ * starts immediately.
+ * - If ADC trigger has been set to external trigger, ADC conversion
+ * will start at next trigger event (on the selected trigger edge)
+ * following the ADC start conversion command.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be enabled without conversion on going on group regular,
+ * without conversion stop command on going on group regular,
+ * without ADC disable command on going.
+ * @rmtoll CR ADSTART LL_ADC_REG_StartConversion
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
+{
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADSTART);
+}
+
+/**
+ * @brief Stop ADC group regular conversion.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be enabled with conversion on going on group regular,
+ * without ADC disable command on going.
+ * @rmtoll CR ADSTP LL_ADC_REG_StopConversion
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
+{
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR,
+ ADC_CR_BITS_PROPERTY_RS,
+ ADC_CR_ADSTP);
+}
+
+/**
+ * @brief Get ADC group regular conversion state.
+ * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
+ * @param ADCx ADC instance
+ * @retval 0: no conversion is on going on ADC group regular.
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get ADC group regular command of conversion stop state
+ * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
+ * @param ADCx ADC instance
+ * @retval 0: no command of conversion stop is on going on ADC group regular.
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * all ADC configurations: all ADC resolutions and
+ * all oversampling increased data width (for devices
+ * with feature oversampling).
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
+ * @param ADCx ADC instance
+ * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * ADC resolution 16 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_REG_ReadConversionData32.
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData16
+ * @param ADCx ADC instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData16(ADC_TypeDef *ADCx)
+{
+ return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * ADC resolution 14 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_REG_ReadConversionData32.
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData14
+ * @param ADCx ADC instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x3FF
+ */
+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData14(ADC_TypeDef *ADCx)
+{
+ return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * ADC resolution 12 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_REG_ReadConversionData32.
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
+ * @param ADCx ADC instance
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
+{
+ return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * ADC resolution 10 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_REG_ReadConversionData32.
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
+ * @param ADCx ADC instance
+ * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
+ */
+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
+{
+ return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * ADC resolution 8 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_REG_ReadConversionData32.
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
+ * @param ADCx ADC instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
+{
+ return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Get ADC multimode conversion data of ADC master, ADC slave
+ * or raw data with ADC master and slave concatenated.
+ * @note If raw data with ADC master and slave concatenated is retrieved,
+ * a macro is available to get the conversion data of
+ * ADC master or ADC slave: see helper macro
+ * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
+ * (however this macro is mainly intended for multimode
+ * transfer by DMA, because this function can do the same
+ * by getting multimode conversion data of ADC master or ADC slave
+ * separately).
+ * @rmtoll CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32
+ * CDR RDATA_SLV LL_ADC_REG_ReadMultiConversionData32
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param ConversionData This parameter can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_MASTER
+ * @arg @ref LL_ADC_MULTI_SLAVE
+ * @arg @ref LL_ADC_MULTI_MASTER_SLAVE
+ * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
+{
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR, ConversionData) >> (POSITION_VAL(ConversionData) & 0x1FUL));
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
+ * @{
+ */
+
+/**
+ * @brief Start ADC group injected conversion.
+ * @note On this STM32 series, this function is relevant for both
+ * internal trigger (SW start) and external trigger:
+ * - If ADC trigger has been set to software start, ADC conversion
+ * starts immediately.
+ * - If ADC trigger has been set to external trigger, ADC conversion
+ * will start at next trigger event (on the selected trigger edge)
+ * following the ADC start conversion command.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be enabled without conversion on going on group injected,
+ * without conversion stop command on going on group injected,
+ * without ADC disable command on going.
+ * @rmtoll CR JADSTART LL_ADC_INJ_StartConversion
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
+{
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_JADSTART);
+}
+
+/**
+ * @brief Stop ADC group injected conversion.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be enabled with conversion on going on group injected,
+ * without ADC disable command on going.
+ * @rmtoll CR JADSTP LL_ADC_INJ_StopConversion
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
+{
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_JADSTP);
+}
+
+/**
+ * @brief Get ADC group injected conversion state.
+ * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing
+ * @param ADCx ADC instance
+ * @retval 0: no conversion is on going on ADC group injected.
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get ADC group injected command of conversion stop state
+ * @rmtoll CR JADSTP LL_ADC_INJ_IsStopConversionOngoing
+ * @param ADCx ADC instance
+ * @retval 0: no command of conversion stop is on going on ADC group injected.
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * all ADC configurations: all ADC resolutions and
+ * all oversampling increased data width (for devices
+ * with feature oversampling).
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData32
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData32
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) \
+ >> ADC_JDRX_REGOFFSET_POS));
+
+ return (uint32_t)(READ_BIT(*preg, ADC_JDR1_JDATA));
+}
+
+/**
+ * @brief Get ADC group injected conversion data, range fit for
+ * ADC resolution 16 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData16
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData16
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData16
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData16
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData16(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) \
+ >> ADC_JDRX_REGOFFSET_POS));
+
+ return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA));
+}
+
+/**
+ * @brief Get ADC group injected conversion data, range fit for
+ * ADC resolution 14 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData14
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData14
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData14
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData14
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x000 and Max_Data=0x3FFF
+ */
+__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData14(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) \
+ >> ADC_JDRX_REGOFFSET_POS));
+
+ return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA));
+}
+
+/**
+ * @brief Get ADC group injected conversion data, range fit for
+ * ADC resolution 12 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData12
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData12
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) \
+ >> ADC_JDRX_REGOFFSET_POS));
+
+ return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA));
+}
+
+/**
+ * @brief Get ADC group injected conversion data, range fit for
+ * ADC resolution 10 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData10
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData10
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData10
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
+ */
+__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) \
+ >> ADC_JDRX_REGOFFSET_POS));
+
+ return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA));
+}
+
+/**
+ * @brief Get ADC group injected conversion data, range fit for
+ * ADC resolution 8 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData8
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData8
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData8
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) \
+ >> ADC_JDRX_REGOFFSET_POS));
+
+ return (uint8_t)(READ_BIT(*preg, ADC_JDR1_JDATA));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
+ * @{
+ */
+
+/**
+ * @brief Get flag ADC ready.
+ * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+ * is enabled and when conversion clock is active.
+ * (not only core clock: this ADC has a dual clock domain)
+ * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag ADC group regular end of unitary conversion.
+ * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag ADC group regular end of sequence conversions.
+ * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag ADC group regular overrun.
+ * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag ADC group regular end of sampling phase.
+ * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag ADC group injected end of unitary conversion.
+ * @rmtoll ISR JEOC LL_ADC_IsActiveFlag_JEOC
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag ADC group injected end of sequence conversions.
+ * @rmtoll ISR JEOS LL_ADC_IsActiveFlag_JEOS
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag ADC group injected contexts queue overflow.
+ * @rmtoll ISR JQOVF LL_ADC_IsActiveFlag_JQOVF
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag ADC analog watchdog 1 flag
+ * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag ADC analog watchdog 2.
+ * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag ADC analog watchdog 3.
+ * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear flag ADC ready.
+ * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+ * is enabled and when conversion clock is active.
+ * (not only core clock: this ADC has a dual clock domain)
+ * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
+}
+
+/**
+ * @brief Clear flag ADC group regular end of unitary conversion.
+ * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
+}
+
+/**
+ * @brief Clear flag ADC group regular end of sequence conversions.
+ * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
+}
+
+/**
+ * @brief Clear flag ADC group regular overrun.
+ * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
+}
+
+/**
+ * @brief Clear flag ADC group regular end of sampling phase.
+ * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
+}
+
+/**
+ * @brief Clear flag ADC group injected end of unitary conversion.
+ * @rmtoll ISR JEOC LL_ADC_ClearFlag_JEOC
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);
+}
+
+/**
+ * @brief Clear flag ADC group injected end of sequence conversions.
+ * @rmtoll ISR JEOS LL_ADC_ClearFlag_JEOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);
+}
+
+/**
+ * @brief Clear flag ADC group injected contexts queue overflow.
+ * @rmtoll ISR JQOVF LL_ADC_ClearFlag_JQOVF
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);
+}
+
+/**
+ * @brief Clear flag ADC analog watchdog 1.
+ * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
+}
+
+/**
+ * @brief Clear flag ADC analog watchdog 2.
+ * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
+}
+
+/**
+ * @brief Clear flag ADC analog watchdog 3.
+ * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_IT_Management ADC IT management
+ * @{
+ */
+
+/**
+ * @brief Enable ADC ready.
+ * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
+}
+
+/**
+ * @brief Enable interruption ADC group regular end of unitary conversion.
+ * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
+}
+
+/**
+ * @brief Enable interruption ADC group regular end of sequence conversions.
+ * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
+}
+
+/**
+ * @brief Enable ADC group regular interruption overrun.
+ * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
+}
+
+/**
+ * @brief Enable interruption ADC group regular end of sampling.
+ * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
+}
+
+/**
+ * @brief Enable interruption ADC group injected end of unitary conversion.
+ * @rmtoll IER JEOCIE LL_ADC_EnableIT_JEOC
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);
+}
+
+/**
+ * @brief Enable interruption ADC group injected end of sequence conversions.
+ * @rmtoll IER JEOSIE LL_ADC_EnableIT_JEOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);
+}
+
+/**
+ * @brief Enable interruption ADC group injected context queue overflow.
+ * @rmtoll IER JQOVFIE LL_ADC_EnableIT_JQOVF
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
+}
+
+/**
+ * @brief Enable interruption ADC analog watchdog 1.
+ * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
+}
+
+/**
+ * @brief Enable interruption ADC analog watchdog 2.
+ * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
+}
+
+/**
+ * @brief Enable interruption ADC analog watchdog 3.
+ * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
+}
+
+/**
+ * @brief Enable interruption ADC end of calibration.
+ * @rmtoll IER EOCALIE LL_ADC_EnableIT_EOCAL
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_EOCAL(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_EOCAL);
+}
+
+/**
+ * @brief Disable interruption ADC ready.
+ * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
+}
+
+/**
+ * @brief Disable interruption ADC group regular end of unitary conversion.
+ * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
+}
+
+/**
+ * @brief Disable interruption ADC group regular end of sequence conversions.
+ * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
+}
+
+/**
+ * @brief Disable interruption ADC group regular overrun.
+ * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
+}
+
+/**
+ * @brief Disable interruption ADC group regular end of sampling.
+ * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
+}
+
+/**
+ * @brief Disable interruption ADC group regular end of unitary conversion.
+ * @rmtoll IER JEOCIE LL_ADC_DisableIT_JEOC
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);
+}
+
+/**
+ * @brief Disable interruption ADC group injected end of sequence conversions.
+ * @rmtoll IER JEOSIE LL_ADC_DisableIT_JEOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);
+}
+
+/**
+ * @brief Disable interruption ADC group injected context queue overflow.
+ * @rmtoll IER JQOVFIE LL_ADC_DisableIT_JQOVF
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
+}
+
+/**
+ * @brief Disable interruption ADC analog watchdog 1.
+ * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
+}
+
+/**
+ * @brief Disable interruption ADC analog watchdog 2.
+ * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
+}
+
+/**
+ * @brief Disable interruption ADC analog watchdog 3.
+ * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
+}
+
+/**
+ * @brief Disable interruption ADC end of calibration.
+ * @rmtoll IER EOCALIE LL_ADC_DisableIT_EOCAL
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_EOCAL(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOCAL);
+}
+
+/**
+ * @brief Get state of interruption ADC ready
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get state of interruption ADC group regular end of unitary conversion
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get state of interruption ADC group regular end of sequence conversions
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get state of interruption ADC group regular overrun
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get state of interruption ADC group regular end of sampling
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get state of interruption ADC group injected end of unitary conversion
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER JEOCIE LL_ADC_IsEnabledIT_JEOC
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get state of interruption ADC group injected end of sequence conversions
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER JEOSIE LL_ADC_IsEnabledIT_JEOS
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get state of interruption ADC group injected context queue overflow interrupt state
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER JQOVFIE LL_ADC_IsEnabledIT_JQOVF
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get state of interruption ADC analog watchdog 1
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get state of interruption Get ADC analog watchdog 2
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get state of interruption Get ADC analog watchdog 3
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get state of interruption ADC end of calibration
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER EOCALIE LL_ADC_IsEnabledIT_EOCAL
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOCAL) == (LL_ADC_IT_EOCAL)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization of some features of ADC common parameters and multimode */
+ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *pADCxyCOMMON);
+ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *pADCxyCOMMON, LL_ADC_CommonInitTypeDef *pADC_CommonInit);
+void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInit);
+
+/* De-initialization of ADC instance, ADC group regular and ADC group injected */
+/* (availability of ADC group injected depends on STM32 families) */
+ErrorStatus LL_ADC_DeInit(ADC_TypeDef *pADCx);
+
+/* Initialization of some features of ADC instance */
+ErrorStatus LL_ADC_Init(ADC_TypeDef *pADCx, LL_ADC_InitTypeDef *pADC_InitStruct);
+void LL_ADC_StructInit(ADC_TypeDef *pADCx, LL_ADC_InitTypeDef *pADC_InitStruct);
+
+/* Initialization of some features of ADC instance and ADC group regular */
+ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *pADCx, LL_ADC_REG_InitTypeDef *pADC_RegInitStruct);
+void LL_ADC_REG_StructInit(ADC_TypeDef *pADCx, LL_ADC_REG_InitTypeDef *pADC_RegInitStruct);
+
+/* Initialization of some features of ADC instance and ADC group injected */
+ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *pADCx, LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct);
+void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* ADC1 || ADC2 || ADC3 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_LL_ADC_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_bus.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_bus.h
new file mode 100644
index 00000000..873bc460
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_bus.h
@@ -0,0 +1,2579 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_bus.h
+ * @author MCD Application Team
+ * @brief Header file of BUS LL module.
+
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ##### RCC Limitations #####
+ ==============================================================================
+ [..]
+ A delay between an RCC peripheral clock enable and the effective peripheral
+ enabling should be taken into account in order to manage the peripheral read/write
+ from/to registers.
+ (+) This delay depends on the peripheral mapping.
+ (++) AHB , APB peripherals, 1 dummy read is necessary
+
+ [..]
+ Workarounds:
+ (#) For AHB , APB peripherals, a dummy read to the peripheral register has been
+ inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_LL_BUS_H
+#define STM32U5xx_LL_BUS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx.h"
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined(RCC)
+
+/** @defgroup BUS_LL BUS
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
+ * @{
+ */
+
+/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
+ * @{
+ */
+#define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
+#define LL_AHB1_GRP1_PERIPH_GPDMA1 RCC_AHB1ENR_GPDMA1EN
+#define LL_AHB1_GRP1_PERIPH_CORDIC RCC_AHB1ENR_CORDICEN
+#define LL_AHB1_GRP1_PERIPH_FMAC RCC_AHB1ENR_FMACEN
+#define LL_AHB1_GRP1_PERIPH_MDF1 RCC_AHB1ENR_MDF1EN
+#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN
+#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
+#define LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN
+#define LL_AHB1_GRP1_PERIPH_RAMCFG RCC_AHB1ENR_RAMCFGEN
+#define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN
+#define LL_AHB1_GRP1_PERIPH_GTZC1 RCC_AHB1ENR_GTZC1EN
+#define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN
+#define LL_AHB1_GRP1_PERIPH_DCACHE1 RCC_AHB1ENR_DCACHE1EN
+#define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1ENR_SRAM1EN
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
+ * @{
+ */
+#define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
+#define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR1_GPIOAEN
+#define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR1_GPIOBEN
+#define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR1_GPIOCEN
+#define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR1_GPIODEN
+#define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR1_GPIOEEN
+#define LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR1_GPIOFEN
+#define LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR1_GPIOGEN
+#define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR1_GPIOHEN
+#define LL_AHB2_GRP1_PERIPH_GPIOI RCC_AHB2ENR1_GPIOIEN
+#define LL_AHB2_GRP1_PERIPH_ADC1 RCC_AHB2ENR1_ADC1EN
+#define LL_AHB2_GRP1_PERIPH_DCMI_PSSI RCC_AHB2ENR1_DCMI_PSSIEN
+#define LL_AHB2_GRP1_PERIPH_USBFS RCC_AHB2ENR1_OTGEN
+#if defined(AES)
+#define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR1_AESEN
+#endif /* AES */
+#if defined(HASH)
+#define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR1_HASHEN
+#endif /* HASH */
+#define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR1_RNGEN
+#define LL_AHB2_GRP1_PERIPH_PKA RCC_AHB2ENR1_PKAEN
+#if defined(SAES)
+#define LL_AHB2_GRP1_PERIPH_SAES RCC_AHB2ENR1_SAESEN
+#endif /* SAES */
+#define LL_AHB2_GRP1_PERIPH_OCTOSPIM RCC_AHB2ENR1_OCTOSPIMEN
+#define LL_AHB2_GRP1_PERIPH_OTFDEC1 RCC_AHB2ENR1_OTFDEC1EN
+#define LL_AHB2_GRP1_PERIPH_OTFDEC2 RCC_AHB2ENR1_OTFDEC2EN
+#define LL_AHB2_GRP1_PERIPH_SDMMC1 RCC_AHB2ENR1_SDMMC1EN
+#define LL_AHB2_GRP1_PERIPH_SDMMC2 RCC_AHB2ENR1_SDMMC2EN
+#define LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2ENR1_SRAM2EN
+#define LL_AHB2_GRP1_PERIPH_SRAM3 RCC_AHB2ENR1_SRAM3EN
+
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
+ * @{
+ */
+#define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU
+#define LL_AHB3_GRP1_PERIPH_LPGPIO1 RCC_AHB3ENR_LPGPIO1EN
+#define LL_AHB3_GRP1_PERIPH_PWR RCC_AHB3ENR_PWREN
+#define LL_AHB3_GRP1_PERIPH_ADC4 RCC_AHB3ENR_ADC4EN
+#define LL_AHB3_GRP1_PERIPH_DAC1 RCC_AHB3ENR_DAC1EN
+#define LL_AHB3_GRP1_PERIPH_LPDMA1 RCC_AHB3ENR_LPDMA1EN
+#define LL_AHB3_GRP1_PERIPH_ADF1 RCC_AHB3ENR_ADF1EN
+#define LL_AHB3_GRP1_PERIPH_GTZC2 RCC_AHB3ENR_GTZC2EN
+#define LL_AHB3_GRP1_PERIPH_SRAM4 RCC_AHB3SMENR_SRAM4SMEN
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EC_AHB2_GRP2_PERIPH AHB2 GRP2 PERIPH
+ * @{
+ */
+#define LL_AHB2_GRP2_PERIPH_ALL 0xFFFFFFFFU
+#define LL_AHB2_GRP2_PERIPH_FSMC RCC_AHB2ENR2_FSMCEN
+#define LL_AHB2_GRP2_PERIPH_OCTOSPI1 RCC_AHB2ENR2_OCTOSPI1EN
+#define LL_AHB2_GRP2_PERIPH_OCTOSPI2 RCC_AHB2ENR2_OCTOSPI2EN
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
+ * @{
+ */
+#define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
+#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN
+#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN
+#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR1_TIM4EN
+#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN
+#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR1_TIM6EN
+#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR1_TIM7EN
+#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN
+#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN
+#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN
+#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR1_USART3EN
+#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR1_UART4EN
+#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR1_UART5EN
+#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN
+#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN
+#define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR1_CRSEN
+/**
+ * @}
+ */
+
+
+/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
+ * @{
+ */
+#define LL_APB1_GRP2_PERIPH_ALL 0xFFFFFFFFU
+#define LL_APB1_GRP2_PERIPH_I2C4 RCC_APB1ENR2_I2C4EN
+#define LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1ENR2_LPTIM2EN
+#define LL_APB1_GRP2_PERIPH_FDCAN1 RCC_APB1ENR2_FDCAN1EN
+#define LL_APB1_GRP2_PERIPH_UCPD1 RCC_APB1ENR2_UCPD1EN
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
+ * @{
+ */
+#define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
+#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
+#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
+#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
+#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
+#define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
+#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
+#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
+#define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
+#define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EC_APB3_GRP1_PERIPH APB3 GRP1 PERIPH
+ * @{
+ */
+#define LL_APB3_GRP1_PERIPH_ALL 0xFFFFFFFFU
+#define LL_APB3_GRP1_PERIPH_SYSCFG RCC_APB3ENR_SYSCFGEN
+#define LL_APB3_GRP1_PERIPH_SPI3 RCC_APB3ENR_SPI3EN
+#define LL_APB3_GRP1_PERIPH_LPUART1 RCC_APB3ENR_LPUART1EN
+#define LL_APB3_GRP1_PERIPH_I2C3 RCC_APB3ENR_I2C3EN
+#define LL_APB3_GRP1_PERIPH_LPTIM1 RCC_APB3ENR_LPTIM1EN
+#define LL_APB3_GRP1_PERIPH_LPTIM3 RCC_APB3ENR_LPTIM3EN
+#define LL_APB3_GRP1_PERIPH_LPTIM4 RCC_APB3ENR_LPTIM4EN
+#define LL_APB3_GRP1_PERIPH_OPAMP RCC_APB3ENR_OPAMPEN
+#define LL_APB3_GRP1_PERIPH_COMP RCC_APB3ENR_COMPEN
+#define LL_APB3_GRP1_PERIPH_VREF RCC_APB3ENR_VREFEN
+#define LL_APB3_GRP1_PERIPH_RTCAPB RCC_APB3ENR_RTCAPBEN
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EC_SRDAMR_GRP1_PERIPH SRDAMR GRP1 PERIPH
+ * @{
+ */
+#define LL_SRDAMR_GRP1_PERIPH_ALL 0xFFFFFFFFU
+#define LL_SRDAMR_GRP1_PERIPH_SPI3AMEN RCC_SRDAMR_SPI3AMEN
+#define LL_SRDAMR_GRP1_PERIPH_LPUART1AMEN RCC_SRDAMR_LPUART1AMEN
+#define LL_SRDAMR_GRP1_PERIPH_I2C3AMEN RCC_SRDAMR_I2C3AMEN
+#define LL_SRDAMR_GRP1_PERIPH_LPTIM1AMEN RCC_SRDAMR_LPTIM1AMEN
+#define LL_SRDAMR_GRP1_PERIPH_LPTIM3AMEN RCC_SRDAMR_LPTIM3AMEN
+#define LL_SRDAMR_GRP1_PERIPH_LPTIM4AMEN RCC_SRDAMR_LPTIM4AMEN
+#define LL_SRDAMR_GRP1_PERIPH_OPAMPAMEN RCC_SRDAMR_OPAMPAMEN
+#define LL_SRDAMR_GRP1_PERIPH_COMPAMEN RCC_SRDAMR_COMPAMEN
+#define LL_SRDAMR_GRP1_PERIPH_VREFAMEN RCC_SRDAMR_VREFAMEN
+#define LL_SRDAMR_GRP1_PERIPH_RTCAPBAMEN RCC_SRDAMR_RTCAPBAMEN
+#define LL_SRDAMR_GRP1_PERIPH_ADC4AMEN RCC_SRDAMR_ADC4AMEN
+#define LL_SRDAMR_GRP1_PERIPH_LPGPIO1AMEN RCC_SRDAMR_LPGPIO1AMEN
+#define LL_SRDAMR_GRP1_PERIPH_DAC1AMEN RCC_SRDAMR_DAC1AMEN
+#define LL_SRDAMR_GRP1_PERIPH_LPDMA1AMEN RCC_SRDAMR_LPDMA1AMEN
+#define LL_SRDAMR_GRP1_PERIPH_ADF1AMEN RCC_SRDAMR_ADF1AMEN
+#define LL_SRDAMR_GRP1_PERIPH_SRAM4AMEN RCC_SRDAMR_SRAM4AMEN
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
+ * @{
+ */
+
+/** @defgroup BUS_LL_EF_AHB1 AHB1
+ * @{
+ */
+/**
+ * @brief Enable AHB1 peripherals clock.
+ * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR CORDICEN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR FMACEN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR MDF1EN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR RAMCFGEN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR GTZC1EN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR DCACHE1EN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR SRAM1EN LL_AHB1_GRP1_EnableClock\n
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->AHB1ENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if AHB1 peripheral clock is enabled or not
+ * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR CORDICEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR FMACEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR MDF1EN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR RAMCFGEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR GTZC1EN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR DCACHEEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR SRAM1EN LL_AHB1_GRP1_IsEnabledClock\n
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
+ * @retval State of Periphs (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+ return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Disable AHB1 peripherals clock.
+ * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR CORDICEN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR FMACEN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR MDF1EN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR RAMCFGEN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR GTZC1EN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR DCACHEEN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR SRAM1EN LL_AHB1_GRP1_IsEnabledClock\n
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->AHB1ENR, Periphs);
+}
+
+/**
+ * @brief Force AHB1 peripherals reset.
+ * @rmtoll AHB1RSTR GPDMA1RSTR LL_AHB1_GRP1_ForceReset\n
+ * AHB1RSTR CORDICRSTR LL_AHB1_GRP1_ForceReset\n
+ * AHB1RSTR FMACRSTR LL_AHB1_GRP1_ForceReset\n
+ * AHB1RSTR MDF1RSTR LL_AHB1_GRP1_ForceReset\n
+ * AHB1RSTR CRCRSTR LL_AHB1_GRP1_ForceReset\n
+ * AHB1RSTR TSCRSTR LL_AHB1_GRP1_ForceReset\n
+ * AHB1RSTR RAMCFGRSTR LL_AHB1_GRP1_ForceReset\n
+ * AHB1RSTR DMA2DRSTR LL_AHB1_GRP1_ForceReset\n
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
+{
+ SET_BIT(RCC->AHB1RSTR, Periphs);
+}
+
+/**
+ * @brief Release AHB1 peripherals reset.
+ * @rmtoll AHB1RSTR GPDMA1RSTR LL_AHB1_GRP1_ReleaseReset\n
+ * AHB1RSTR CORDICRSTR LL_AHB1_GRP1_ReleaseReset\n
+ * AHB1RSTR FMACRSTR LL_AHB1_GRP1_ReleaseReset\n
+ * AHB1RSTR MDF1RSTR LL_AHB1_GRP1_ReleaseReset\n
+ * AHB1RSTR CRCRSTR LL_AHB1_GRP1_ReleaseReset\n
+ * AHB1RSTR TSCRSTR LL_AHB1_GRP1_ReleaseReset\n
+ * AHB1RSTR RAMCFGRSTR LL_AHB1_GRP1_ReleaseReset\n
+ * AHB1RSTR DMA2DRSTR LL_AHB1_GRP1_ReleaseReset\n
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->AHB1RSTR, Periphs);
+}
+
+/**
+ * @brief Enable AHB1 peripheral clocks in Sleep and Stop modes
+ * @rmtoll AHB1SMENR GPDMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
+ * AHB1SMENR CORDICSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
+ * AHB1SMENR FMACSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
+ * AHB1SMENR MDF1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
+ * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
+ * AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
+ * AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
+ * AHB1SMENR RAMCFGSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
+ * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
+ * AHB1SMENR GTZC1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
+ * AHB1SMENR BKPSRAMSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
+ * AHB1SMENR DCACHESMEN LL_AHB1_GRP1_EnableClockStopSleep\n
+ * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->AHB1SMENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if AHB1 peripheral clocks in Sleep and Stop modes is enabled or not
+ * @rmtoll AHB1SMENR GPDMA1SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
+ * AHB1SMENR CORDICSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
+ * AHB1SMENR FMACSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
+ * AHB1SMENR MDF1SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
+ * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
+ * AHB1SMENR CRCSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
+ * AHB1SMENR TSCSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
+ * AHB1SMENR RAMCFGSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
+ * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
+ * AHB1SMENR GTZC1SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
+ * AHB1SMENR BKPSRAMSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
+ * AHB1SMENR DCACHESMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
+ * @retval State of Periphs (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)
+{
+ return ((READ_BIT(RCC->AHB1SMENR, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Disable AHB1 peripheral clocks in Sleep and Stop modes
+ * @rmtoll AHB1SMENR GPDMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
+ * AHB1SMENR CORDICSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
+ * AHB1SMENR FMACSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
+ * AHB1SMENR MDF1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
+ * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
+ * AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
+ * AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
+ * AHB1SMENR RAMCFGSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
+ * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
+ * AHB1SMENR GTZC1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
+ * AHB1SMENR BKPSRAMSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
+ * AHB1SMENR DCACHESMEN LL_AHB1_GRP1_DisableClockStopSleep\n
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->AHB1SMENR, Periphs);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EF_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
+ * @{
+ */
+/**
+ * @brief Enable AHB2 peripherals clock.
+ * @rmtoll AHB2ENR1 GPIOAEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR1 GPIOBEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR1 GPIOCEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR1 GPIODEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR1 GPIOEEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR1 GPIOFEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR1 GPIOGEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR1 GPIOHEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR1 GPIOIEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR1 ADC1EN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR1 DCMI_PSSIEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR1 OTGEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR1 AESEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR1 HASHEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR1 RNGEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR1 PKAEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR1 SAESEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR1 OCTOSPIMEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR1 OTFDEC1EN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR1 OTFDEC2EN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR1 SDMMC1EN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR1 SDMMC2EN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR1 SRAM2EN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR1 SRAM3EN LL_AHB2_GRP1_EnableClock\n
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ADC1
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI
+ * @arg @ref LL_AHB2_GRP1_PERIPH_USBFS
+ * @arg @ref LL_AHB2_GRP1_PERIPH_AES
+ * @arg @ref LL_AHB2_GRP1_PERIPH_HASH
+ * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ * @arg @ref LL_AHB2_GRP1_PERIPH_PKA
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SAES
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->AHB2ENR1, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->AHB2ENR1, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if AHB2 peripheral clock is enabled or not
+ * @rmtoll AHB2ENR1 GPIOAEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR1 GPIOBEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR1 GPIOCEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR1 GPIODEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR1 GPIOEEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR1 GPIOFEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR1 GPIOGEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR1 GPIOHEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR1 GPIOIEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR1 ADC1EN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR1 DCMI_PSSIEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR1 OTGFSEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR1 AESEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR1 HASHEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR1 RNGEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR1 PKAEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR1 SAESEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR1 OCTOSPIMEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR1 OTFDEC1EN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR1 OTFDEC2EN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR1 SDMMC1EN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR1 SDMMC2EN LL_AHB2_GRP1_IsEnabledClock\n
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ADC1
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI
+ * @arg @ref LL_AHB2_GRP1_PERIPH_USBFS
+ * @arg @ref LL_AHB2_GRP1_PERIPH_AES
+ * @arg @ref LL_AHB2_GRP1_PERIPH_HASH
+ * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ * @arg @ref LL_AHB2_GRP1_PERIPH_PKA
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SAES
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3
+ * @retval State of Periphs (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+ return ((READ_BIT(RCC->AHB2ENR1, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Disable AHB2 peripherals clock.
+ * @rmtoll AHB2ENR1 GPIOAEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR1 GPIOBEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR1 GPIOCEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR1 GPIODEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR1 GPIOEEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR1 GPIOFEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR1 GPIOGEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR1 GPIOHEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR1 GPIOIEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR1 ADC1EN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR1 DCMI_PSSIEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR1 OTGEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR1 AESEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR1 HASHEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR1 RNGEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR1 PKAEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR1 SAESEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR1 OSPIMEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR1 OTFDEC1EN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR1 OTFDEC2EN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR1 SDMMC1EN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR1 SDMMC2EN LL_AHB2_GRP1_DisableClock\n
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ADC1
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI
+ * @arg @ref LL_AHB2_GRP1_PERIPH_USBFS
+ * @arg @ref LL_AHB2_GRP1_PERIPH_AES
+ * @arg @ref LL_AHB2_GRP1_PERIPH_HASH
+ * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ * @arg @ref LL_AHB2_GRP1_PERIPH_PKA
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SAES
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->AHB2ENR1, Periphs);
+}
+
+/**
+ * @brief Force AHB2 peripherals reset.
+ * @rmtoll AHB2RSTR1 GPIOARST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR1 GPIOBRST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR1 GPIOCRST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR1 GPIODRST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR1 GPIOERST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR1 GPIOFRST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR1 GPIOGRST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR1 GPIOHRST LL_AHB2_GRP1_ForceResetn
+ * AHB2RSTR1 GPIOIRST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR1 ADC1RST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR1 DCMI_PSSIRST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR1 OTGRST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR1 AESRST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR1 HASHRST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR1 RNGRST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR1 PKARST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR1 SAESRST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR1 OCTOSPIMRST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR1 OTFDEC1RST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR1 OTFDEC2RST LL_AHB2_GRP1_ForceReset\n
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ADC1
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI
+ * @arg @ref LL_AHB2_GRP1_PERIPH_USBFS
+ * @arg @ref LL_AHB2_GRP1_PERIPH_AES
+ * @arg @ref LL_AHB2_GRP1_PERIPH_HASH
+ * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ * @arg @ref LL_AHB2_GRP1_PERIPH_PKA
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SAES
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
+{
+ SET_BIT(RCC->AHB2RSTR1, Periphs);
+}
+
+/**
+ * @brief Release AHB2 peripherals reset.
+ * @rmtoll AHB2RSTR1 GPIOARST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR1 GPIOBRST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR1 GPIOCRST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR1 GPIODRST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR1 GPIOERST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR1 GPIOFRST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR1 GPIOGRST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR1 GPIOHRST LL_AHB2_GRP1_ReleaseResetn
+ * AHB2RSTR1 GPIOIRST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR1 ADC1RST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR1 DCMI_PSSIRST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR1 OTGRST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR1 AESRST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR1 HASHRST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR1 RNGRST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR1 PKARST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR1 SAESRST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR1 OCTOSPIMRST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR1 OTFDEC1RST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR1 OTFDEC2RST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR1 SDMMC1RST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR1 SDMMC2RST LL_AHB2_GRP1_ReleaseReset\n
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ADC1
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI
+ * @arg @ref LL_AHB2_GRP1_PERIPH_USBFS
+ * @arg @ref LL_AHB2_GRP1_PERIPH_AES
+ * @arg @ref LL_AHB2_GRP1_PERIPH_HASH
+ * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ * @arg @ref LL_AHB2_GRP1_PERIPH_PKA
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SAES
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->AHB2RSTR1, Periphs);
+}
+
+/**
+ * @brief Enable AHB2 peripheral clocks in Sleep and Stop modes
+ * @rmtoll AHB2SMENR1 GPIOASMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR1 GPIOBSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR1 GPIOCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR1 GPIODSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR1 GPIOESMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR1 GPIOFSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR1 GPIOGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR1 GPIOHSMEN LL_AHB2_GRP1_EnableClockStopSleepn
+ * AHB2SMENR1 GPIOISMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR1 ADC1SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR1 DCMI_PSSISMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR1 OTGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR1 AESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR1 HASHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR1 RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR1 PKASMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR1 SAESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR1 OSPIMSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR1 OTFDEC1SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR1 OTFDEC2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR1 SDMMC1SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR1 SDMMC2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR1 SRAM3SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR1 SRAM4SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ADC1
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI
+ * @arg @ref LL_AHB2_GRP1_PERIPH_USBFS
+ * @arg @ref LL_AHB2_GRP1_PERIPH_AES
+ * @arg @ref LL_AHB2_GRP1_PERIPH_HASH
+ * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ * @arg @ref LL_AHB2_GRP1_PERIPH_PKA
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SAES
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->AHB2SMENR1, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->AHB2SMENR1, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if AHB2 peripheral clocks in Sleep and Stop modes is enabled or not
+ * @rmtoll AHB2SMENR1 GPIOASMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
+ * AHB2SMENR1 GPIOBSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
+ * AHB2SMENR1 GPIOCSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
+ * AHB2SMENR1 GPIODSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
+ * AHB2SMENR1 GPIOESMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
+ * AHB2SMENR1 GPIOFSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
+ * AHB2SMENR1 GPIOGSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
+ * AHB2SMENR1 GPIOHSMEN LL_AHB2_GRP1_IsEnabledClockStopSleepn
+ * AHB2SMENR1 GPIOISMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
+ * AHB2SMENR1 ADC1SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
+ * AHB2SMENR1 DCMI_PSSISMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
+ * AHB2SMENR1 OTGSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
+ * AHB2SMENR1 AESSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
+ * AHB2SMENR1 HASHSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
+ * AHB2SMENR1 RNGSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
+ * AHB2SMENR1 PKASMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
+ * AHB2SMENR1 SAESSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
+ * AHB2SMENR1 OSPIMSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
+ * AHB2SMENR1 OTFDEC1SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
+ * AHB2SMENR1 OTFDEC2SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
+ * AHB2SMENR1 SDMMC1SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
+ * AHB2SMENR1 SDMMC2SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
+ * AHB2SMENR1 SRAM3SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
+ * AHB2SMENR1 SRAM4SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ADC1
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI
+ * @arg @ref LL_AHB2_GRP1_PERIPH_USBFS
+ * @arg @ref LL_AHB2_GRP1_PERIPH_AES
+ * @arg @ref LL_AHB2_GRP1_PERIPH_HASH
+ * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ * @arg @ref LL_AHB2_GRP1_PERIPH_PKA
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SAES
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3
+ * @retval State of Periphs (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)
+{
+ return ((READ_BIT(RCC->AHB2SMENR1, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Disable AHB2 peripheral clocks in Sleep and Stop modes
+ * @rmtoll AHB2SMENR1 GPIOASMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR1 GPIOBSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR1 GPIOCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR1 GPIODSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR1 GPIOESMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR1 GPIOFSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR1 GPIOGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR1 GPIOHSMEN LL_AHB2_GRP1_DisableClockStopSleepn
+ * AHB2SMENR1 GPIOISMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR1 ADC1SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR1 DCMI_PSSISMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR1 OTGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR1 AESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR1 HASHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR1 RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR1 PKASMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR1 SAESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR1 OSPIMSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR1 OTFDEC1SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR1 OTFDEC2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR1 SDMMC1SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR1 SDMMC2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR1 SRAM3SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR1 SRAM4SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ADC1
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI
+ * @arg @ref LL_AHB2_GRP1_PERIPH_USBFS
+ * @arg @ref LL_AHB2_GRP1_PERIPH_AES
+ * @arg @ref LL_AHB2_GRP1_PERIPH_HASH
+ * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ * @arg @ref LL_AHB2_GRP1_PERIPH_PKA
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SAES
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->AHB2SMENR1, Periphs);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EF_AHB3 AHB3
+ * @{
+ */
+/**
+ * @brief Enable AHB3 peripherals clock.
+ * @rmtoll AHB3ENR LPGPIO1EN LL_AHB3_GRP1_EnableClock\n
+ * AHB3ENR PWREN LL_AHB3_GRP1_EnableClock\n
+ * AHB3ENR ADC4EN LL_AHB3_GRP1_EnableClock\n
+ * AHB3ENR DAC1EN LL_AHB3_GRP1_EnableClock\n
+ * AHB3ENR LPDMA1EN LL_AHB3_GRP1_EnableClock\n
+ * AHB3ENR ADF1EN LL_AHB3_GRP1_EnableClock\n
+ * AHB3ENR GTZC2EN LL_AHB3_GRP1_EnableClock\n
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1
+ * @arg @ref LL_AHB3_GRP1_PERIPH_PWR
+ * @arg @ref LL_AHB3_GRP1_PERIPH_ADC4
+ * @arg @ref LL_AHB3_GRP1_PERIPH_DAC1
+ * @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1
+ * @arg @ref LL_AHB3_GRP1_PERIPH_ADF1
+ * @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->AHB3ENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if AHB3 peripheral clock is enabled or not
+ * @rmtoll AHB3ENR LPGPIO1EN LL_AHB3_GRP1_IsEnabledClock\n
+ * AHB3ENR PWREN LL_AHB3_GRP1_IsEnabledClock\n
+ * AHB3ENR ADC4EN LL_AHB3_GRP1_IsEnabledClock\n
+ * AHB3ENR DAC1EN LL_AHB3_GRP1_IsEnabledClock\n
+ * AHB3ENR LPDMA1EN LL_AHB3_GRP1_IsEnabledClock\n
+ * AHB3ENR ADF1EN LL_AHB3_GRP1_IsEnabledClock\n
+ * AHB3ENR GTZC2EN LL_AHB3_GRP1_IsEnabledClock\n
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1
+ * @arg @ref LL_AHB3_GRP1_PERIPH_PWR
+ * @arg @ref LL_AHB3_GRP1_PERIPH_ADC4
+ * @arg @ref LL_AHB3_GRP1_PERIPH_DAC1
+ * @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1
+ * @arg @ref LL_AHB3_GRP1_PERIPH_ADF1
+ * @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2
+ * @retval State of Periphs (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+ return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Disable AHB3 peripherals clock.
+ * @rmtoll AHB3ENR LPGPIO1EN LL_AHB3_GRP1_DisableClock\n
+ * AHB3ENR PWREN LL_AHB3_GRP1_DisableClock\n
+ * AHB3ENR ADC4EN LL_AHB3_GRP1_DisableClock\n
+ * AHB3ENR DAC1EN LL_AHB3_GRP1_DisableClock\n
+ * AHB3ENR LPDMA1EN LL_AHB3_GRP1_DisableClock\n
+ * AHB3ENR ADF1EN LL_AHB3_GRP1_DisableClock\n
+ * AHB3ENR GTZC2EN LL_AHB3_GRP1_DisableClock\n
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1
+ * @arg @ref LL_AHB3_GRP1_PERIPH_PWR
+ * @arg @ref LL_AHB3_GRP1_PERIPH_ADC4
+ * @arg @ref LL_AHB3_GRP1_PERIPH_DAC1
+ * @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1
+ * @arg @ref LL_AHB3_GRP1_PERIPH_ADF1
+ * @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->AHB3ENR, Periphs);
+}
+
+/**
+ * @brief Force AHB3 peripherals reset.
+ * @rmtoll AHB3RSTR LPGPIO1RST LL_AHB3_GRP1_ForceReset\n
+ * AHB3RSTR PWRRST LL_AHB3_GRP1_ForceReset\n
+ * AHB3RSTR ADC4RST LL_AHB3_GRP1_ForceReset\n
+ * AHB3RSTR DAC1RST LL_AHB3_GRP1_ForceReset\n
+ * AHB3RSTR LPDMA1RST LL_AHB3_GRP1_ForceReset\n
+ * AHB3RSTR ADF1RST LL_AHB3_GRP1_ForceReset\n
+ * AHB3RSTR GTZC2RST LL_AHB3_GRP1_ForceReset\n
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1
+ * @arg @ref LL_AHB3_GRP1_PERIPH_PWR
+ * @arg @ref LL_AHB3_GRP1_PERIPH_ADC4
+ * @arg @ref LL_AHB3_GRP1_PERIPH_DAC1
+ * @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1
+ * @arg @ref LL_AHB3_GRP1_PERIPH_ADF1
+ * @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
+{
+ SET_BIT(RCC->AHB3RSTR, Periphs);
+}
+
+/**
+ * @brief Release AHB3 peripherals reset.
+ * @rmtoll AHB3RSTR LPGPIO1RST LL_AHB3_GRP1_ReleaseReset\n
+ * AHB3RSTR PWRRST LL_AHB3_GRP1_ReleaseReset\n
+ * AHB3RSTR ADC4RST LL_AHB3_GRP1_ReleaseReset\n
+ * AHB3RSTR DAC1RST LL_AHB3_GRP1_ReleaseReset\n
+ * AHB3RSTR LPDMA1RST LL_AHB3_GRP1_ReleaseReset\n
+ * AHB3RSTR ADF1RST LL_AHB3_GRP1_ReleaseReset\n
+ * AHB3RSTR GTZC2RST LL_AHB3_GRP1_ReleaseReset\n
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1
+ * @arg @ref LL_AHB3_GRP1_PERIPH_PWR
+ * @arg @ref LL_AHB3_GRP1_PERIPH_ADC4
+ * @arg @ref LL_AHB3_GRP1_PERIPH_DAC1
+ * @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1
+ * @arg @ref LL_AHB3_GRP1_PERIPH_ADF1
+ * @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->AHB3RSTR, Periphs);
+}
+
+/**
+ * @brief Enable AHB3 peripheral clocks in Sleep and Stop modes
+ * @rmtoll AHB3SMENR LPGPIO1SMEN LL_AHB3_GRP1_EnableClockStopSleep\n
+ * AHB3SMENR PWRSMEN LL_AHB3_GRP1_EnableClockStopSleep\n
+ * AHB3SMENR ADC4SMEN LL_AHB3_GRP1_EnableClockStopSleep\n
+ * AHB3SMENR DAC1SMEN LL_AHB3_GRP1_EnableClockStopSleep\n
+ * AHB3SMENR LPDMA1SMEN LL_AHB3_GRP1_EnableClockStopSleep\n
+ * AHB3SMENR ADF1SMEN LL_AHB3_GRP1_EnableClockStopSleep\n
+ * AHB3SMENR GTZC2SMEN LL_AHB3_GRP1_EnableClockStopSleep\n
+ * AHB3SMENR SRAM4SMEN LL_AHB3_GRP1_EnableClockStopSleep\n
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1
+ * @arg @ref LL_AHB3_GRP1_PERIPH_PWR
+ * @arg @ref LL_AHB3_GRP1_PERIPH_ADC4
+ * @arg @ref LL_AHB3_GRP1_PERIPH_DAC1
+ * @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1
+ * @arg @ref LL_AHB3_GRP1_PERIPH_ADF1
+ * @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2
+ * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM4
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->AHB3SMENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->AHB3SMENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if AHB3 peripheral clocks in Sleep and Stop modes is enabled or not
+ * @rmtoll AHB3SMENR LPGPIO1SMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n
+ * AHB3SMENR PWRSMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n
+ * AHB3SMENR ADC4SMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n
+ * AHB3SMENR DAC1SMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n
+ * AHB3SMENR LPDMA1SMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n
+ * AHB3SMENR ADF1SMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n
+ * AHB3SMENR GTZC2SMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n
+ * AHB3SMENR SRAM4SMEN LL_AHB3_GRP1_IsEnabledClockStopSleep
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1
+ * @arg @ref LL_AHB3_GRP1_PERIPH_PWR
+ * @arg @ref LL_AHB3_GRP1_PERIPH_ADC4
+ * @arg @ref LL_AHB3_GRP1_PERIPH_DAC1
+ * @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1
+ * @arg @ref LL_AHB3_GRP1_PERIPH_ADF1
+ * @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2
+ * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM4
+ * @retval State of Periphs (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)
+{
+ return ((READ_BIT(RCC->AHB3SMENR, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Disable AHB3 peripheral clocks in Sleep and Stop modes
+ * @rmtoll AHB3SMENR LPGPIO1SMEN LL_AHB3_GRP1_DisableClockStopSleep\n
+ * AHB3SMENR PWRSMEN LL_AHB3_GRP1_DisableClockStopSleep\n
+ * AHB3SMENR ADC4SMEN LL_AHB3_GRP1_DisableClockStopSleep\n
+ * AHB3SMENR DAC1SMEN LL_AHB3_GRP1_DisableClockStopSleep\n
+ * AHB3SMENR LPDMA1SMEN LL_AHB3_GRP1_DisableClockStopSleep\n
+ * AHB3SMENR ADF1SMEN LL_AHB3_GRP1_DisableClockStopSleep\n
+ * AHB3SMENR GTZC2SMEN LL_AHB3_GRP1_DisableClockStopSleep\n
+ * AHB3SMENR SRAM4SMEN LL_AHB3_GRP1_EnableClockStopSleep
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1
+ * @arg @ref LL_AHB3_GRP1_PERIPH_PWR
+ * @arg @ref LL_AHB3_GRP1_PERIPH_ADC4
+ * @arg @ref LL_AHB3_GRP1_PERIPH_DAC1
+ * @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1
+ * @arg @ref LL_AHB3_GRP1_PERIPH_ADF1
+ * @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2
+ * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM4
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->AHB3SMENR, Periphs);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EF_AHB2_GRP2_PERIPH AHB2 GRP2 PERIPH
+ * @{
+ */
+/**
+ * @brief Enable AHB2 peripherals clock.
+ * @rmtoll AHB2ENR2 FSMCEN LL_AHB2_GRP2_EnableClock\n
+ * AHB2ENR2 OCTOSPI1EN LL_AHB2_GRP2_EnableClock\n
+ * AHB2ENR2 OCTOSPI2EN LL_AHB2_GRP2_EnableClock\n
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB2_GRP2_PERIPH_ALL
+ * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC
+ * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1
+ * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB2_GRP2_EnableClock(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->AHB2ENR2, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->AHB2ENR2, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if AHB4 peripheral clock is enabled or not
+ * @rmtoll AHB2ENR2 FSMCEN LL_AHB2_GRP2_IsEnabledClock\n
+ * AHB2ENR2 OCTOSPI1EN LL_AHB2_GRP2_IsEnabledClock\n
+ * AHB2ENR2 OCTOSPI2EN LL_AHB2_GRP2_IsEnabledClock\n
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB2_GRP2_PERIPH_ALL
+ * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC
+ * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1
+ * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2
+ * @retval None
+ * @retval State of Periphs (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_AHB2_GRP2_IsEnabledClock(uint32_t Periphs)
+{
+ return ((READ_BIT(RCC->AHB2ENR2, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Disable AHB4 peripherals clock.
+ * @rmtoll AHB2ENR2 FSMCEN LL_AHB2_GRP2_DisableClock\n
+ * AHB2ENR2 OCTOSPI1EN LL_AHB2_GRP2_DisableClock\n
+ * AHB2ENR2 OCTOSPI2EN LL_AHB2_GRP2_DisableClock\n
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB2_GRP2_PERIPH_ALL
+ * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC
+ * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1
+ * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB2_GRP2_DisableClock(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->AHB2ENR2, Periphs);
+}
+
+/**
+ * @brief Force AHB4 peripherals reset.
+ * @rmtoll AHB2RSTR2 FSMCRST LL_AHB2_GRP2_ForceReset\n
+ * AHB2RSTR2 OCTOSPI1RST LL_AHB2_GRP2_ForceReset\n
+ * AHB2RSTR2 OCTOSPI2RST LL_AHB2_GRP2_ForceReset\n
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB2_GRP2_PERIPH_ALL
+ * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC
+ * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1
+ * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB2_GRP2_ForceReset(uint32_t Periphs)
+{
+ SET_BIT(RCC->AHB2RSTR2, Periphs);
+}
+
+/**
+ * @brief Release AHB4 peripherals reset.
+ * @rmtoll AHB2RSTR2 FSMCRST LL_AHB2_GRP2_ReleaseReset\n
+ * AHB2RSTR2 OCTOSPI1RST LL_AHB2_GRP2_ReleaseReset\n
+ * AHB2RSTR2 OCTOSPI2RST LL_AHB2_GRP2_ReleaseReset\n
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB2_GRP2_PERIPH_ALL
+ * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC
+ * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1
+ * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB2_GRP2_ReleaseReset(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->AHB2RSTR2, Periphs);
+}
+
+/**
+ * @brief Enable AHB4 peripheral clocks in Sleep and Stop modes
+ * @rmtoll AHB2SMENR2 FSMCSMEN LL_AHB2_GRP2_EnableClockStopSleep\n
+ * AHB2SMENR2 OCTOSPI1SMEN LL_AHB2_GRP2_EnableClockStopSleep\n
+ * AHB2SMENR2 OCTOSPI2SMEN LL_AHB2_GRP2_EnableClockStopSleep\n
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB2_GRP2_PERIPH_ALL
+ * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC
+ * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1
+ * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB2_GRP2_EnableClockStopSleep(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->AHB2SMENR2, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->AHB2SMENR2, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if AHB4 peripheral clocks in Sleep and Stop modes is enabled or not
+ * @rmtoll AHB2SMENR2 FSMCSMEN LL_AHB2_GRP2_IsEnabledClockStopSleep\n
+ * AHB2SMENR2 OCTOSPI1SMEN LL_AHB2_GRP2_IsEnabledClockStopSleep\n
+ * AHB2SMENR2 OCTOSPI2SMEN LL_AHB2_GRP2_IsEnabledClockStopSleep\n
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB2_GRP2_PERIPH_ALL
+ * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC
+ * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1
+ * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2
+ * @retval State of Periphs (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_AHB2_GRP2_IsEnabledClockStopSleep(uint32_t Periphs)
+{
+ return ((READ_BIT(RCC->AHB2SMENR2, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Disable AHB4 peripheral clocks in Sleep and Stop modes
+ * @rmtoll AHB2SMENR2 FSMCSMEN LL_AHB2_GRP2_DisableClockStopSleep\n
+ * AHB2SMENR2 OCTOSPI1SMEN LL_AHB2_GRP2_DisableClockStopSleep\n
+ * AHB2SMENR2 OCTOSPI2SMEN LL_AHB2_GRP2_DisableClockStopSleep\n
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB2_GRP2_PERIPH_ALL
+ * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC
+ * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1
+ * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB2_GRP2_DisableClockStopSleep(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->AHB2SMENR2, Periphs);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EF_APB1 APB1
+ * @{
+ */
+
+/**
+ * @brief Enable APB1 peripherals clock.
+ * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 TIM3EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 TIM4EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 TIM5EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 TIM6EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 TIM7EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 SPI2EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 USART3EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 UART4EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 UART5EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 I2C2EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 CRSEN LL_APB1_GRP1_EnableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+ * @arg @ref LL_APB1_GRP1_PERIPH_CRS
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->APB1ENR1, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Enable APB1 peripherals clock.
+ * @rmtoll APB1ENR2 I2C4EN LL_APB1_GRP2_EnableClock\n
+ * APB1ENR2 LPTIM2EN LL_APB1_GRP2_EnableClock\n
+ * APB1ENR2 FDCAN1EN LL_APB1_GRP2_EnableClock\n
+ * APB1ENR2 UCPD1EN LL_APB1_GRP2_EnableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP2_PERIPH_ALL
+ * @arg @ref LL_APB1_GRP2_PERIPH_I2C4
+ * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
+ * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1
+ * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->APB1ENR2, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->APB1ENR2, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if APB1 peripheral clock is enabled or not
+ * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 TIM4EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 TIM5EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 USART3EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 UART4EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 UART5EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 CRSEN LL_APB1_GRP1_IsEnabledClock\n
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+ * @arg @ref LL_APB1_GRP1_PERIPH_CRS
+ * @retval State of Periphs (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+ return ((READ_BIT(RCC->APB1ENR1, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if APB1 peripheral clock is enabled or not
+ * @rmtoll APB1ENR2 I2C4EN LL_APB1_GRP2_IsEnabledClock\n
+ * APB1ENR2 LPTIM2EN LL_APB1_GRP2_IsEnabledClock\n
+ * APB1ENR2 FDCAN1EN LL_APB1_GRP2_IsEnabledClock\n
+ * APB1ENR2 UCPD1EN LL_APB1_GRP2_IsEnabledClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP2_PERIPH_ALL
+ * @arg @ref LL_APB1_GRP2_PERIPH_I2C4
+ * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
+ * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1
+ * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
+ * @retval State of Periphs (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
+{
+ return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Disable APB1 peripherals clock.
+ * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 TIM3EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 TIM4EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 TIM5EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 TIM6EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 TIM7EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 WWDGEN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 SPI2EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 USART2EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 USART3EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 UART4EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 UART5EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 I2C2EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 CRSEN LL_APB1_GRP1_DisableClock\n
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+ * @arg @ref LL_APB1_GRP1_PERIPH_CRS
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB1ENR1, Periphs);
+}
+
+/**
+ * @brief Disable APB1 peripherals clock.
+ * @rmtoll APB1ENR2 I2C4EN LL_APB1_GRP2_DisableClock\n
+ * APB1ENR2 LPTIM2EN LL_APB1_GRP2_DisableClock\n
+ * APB1ENR2 FDCAN1EN LL_APB1_GRP2_DisableClock\n
+ * APB1ENR2 UCPD1EN LL_APB1_GRP2_DisableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP2_PERIPH_ALL
+ * @arg @ref LL_APB1_GRP2_PERIPH_I2C4
+ * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
+ * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1
+ * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB1ENR2, Periphs);
+}
+
+/**
+ * @brief Force APB1 peripherals reset.
+ * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 TIM4RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 TIM5RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 TIM6RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 TIM7RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 USART2RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 USART3RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 UART4RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 UART5RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 I2C2RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 CRSRST LL_APB1_GRP1_ForceReset\n
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+ * @arg @ref LL_APB1_GRP1_PERIPH_CRS
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
+{
+ SET_BIT(RCC->APB1RSTR1, Periphs);
+}
+
+/**
+ * @brief Force APB1 peripherals reset.
+ * @rmtoll APB1RSTR2 I2C4RST LL_APB1_GRP2_DisableClock\n
+ * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_DisableClock\n
+ * APB1RSTR2 FDCAN1RST LL_APB1_GRP2_DisableClock\n
+ * APB1RSTR2 UCPDRST LL_APB1_GRP2_DisableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP2_PERIPH_ALL
+ * @arg @ref LL_APB1_GRP2_PERIPH_I2C4
+ * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
+ * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1
+ * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
+{
+ SET_BIT(RCC->APB1RSTR2, Periphs);
+}
+
+/**
+ * @brief Release APB1 peripherals reset.
+ * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 TIM4RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 TIM5RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 TIM6RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 TIM7RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 USART2RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 USART3RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 UART4RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 UART5RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 CRSRST LL_APB1_GRP1_ReleaseReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+ * @arg @ref LL_APB1_GRP1_PERIPH_CRS
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB1RSTR1, Periphs);
+}
+
+/**
+ * @brief Release APB1 peripherals reset.
+ * @rmtoll APB1RSTR2 I2C4RST LL_APB1_GRP2_ReleaseReset\n
+ * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ReleaseReset\n
+ * APB1RSTR2 FDCAN1RST LL_APB1_GRP2_ReleaseReset\n
+ * APB1RSTR2 UCPD1RST LL_APB1_GRP2_ReleaseReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP2_PERIPH_ALL
+ * @arg @ref LL_APB1_GRP2_PERIPH_I2C4
+ * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
+ * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1
+ * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB1RSTR2, Periphs);
+}
+
+/**
+ * @brief Enable APB1 peripheral clocks in Sleep and Stop modes
+ * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 USART3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 UART4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 UART5SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 CRSSMEN LL_APB1_GRP1_EnableClockStopSleep
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+ * @arg @ref LL_APB1_GRP1_PERIPH_CRS
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->APB1SMENR1, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->APB1SMENR1, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if APB1 peripheral clocks in Sleep and Stop modes is enabled or not
+ * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
+ * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
+ * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
+ * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
+ * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
+ * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
+ * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
+ * APB1SMENR1 USART2SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
+ * APB1SMENR1 USART3SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
+ * APB1SMENR1 UART4SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
+ * APB1SMENR1 UART5SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
+ * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
+ * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
+ * APB1SMENR1 CRSSMEN LL_APB1_GRP1_IsEnabledClockStopSleep
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+ * @arg @ref LL_APB1_GRP1_PERIPH_CRS
+ * @retval State of Periphs (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)
+{
+ return ((READ_BIT(RCC->APB1SMENR1, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Disable APB1 peripheral clocks in Sleep and Stop modes
+ * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 USART3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 UART4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 UART5SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 CRSSMEN LL_APB1_GRP1_DisableClockStopSleep
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+ * @arg @ref LL_APB1_GRP1_PERIPH_CRS
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB1SMENR1, Periphs);
+}
+
+/**
+ * @brief Enable APB1 peripheral clocks in Sleep and Stop modes
+ * @rmtoll APB1SMENR2 I2C4SMEN LL_APB1_GRP2_EnableClockStopSleep\n
+ * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_EnableClockStopSleep\n
+ * APB1SMENR2 FDCAN1SMEN LL_APB1_GRP2_EnableClockStopSleep\n
+ * APB1SMENR2 UCPD1SMEN LL_APB1_GRP2_EnableClockStopSleep
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP2_PERIPH_ALL
+ * @arg @ref LL_APB1_GRP2_PERIPH_I2C4
+ * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
+ * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1
+ * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->APB1SMENR2, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->APB1SMENR2, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if APB1 peripheral clocks in Sleep and Stop modes is enabled or not
+ * @rmtoll APB1SMENR2 I2C4SMEN LL_APB1_GRP2_IsEnabledClockStopSleep\n
+ * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_IsEnabledClockStopSleep\n
+ * APB1SMENR2 FDCAN1SMEN LL_APB1_GRP2_IsEnabledClockStopSleep\n
+ * APB1SMENR2 UCPD1SMEN LL_APB1_GRP2_IsEnabledClockStopSleep
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP2_PERIPH_ALL
+ * @arg @ref LL_APB1_GRP2_PERIPH_I2C4
+ * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
+ * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1
+ * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
+ * @retval State of Periphs (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClockStopSleep(uint32_t Periphs)
+{
+ return ((READ_BIT(RCC->APB1SMENR2, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Disable APB1 peripheral clocks in Sleep and Stop modes
+ * @rmtoll APB1SMENR2 I2C4SMEN LL_APB1_GRP2_DisableClockStopSleep\n
+ * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_DisableClockStopSleep\n
+ * APB1SMENR2 FDCAN1SMEN LL_APB1_GRP2_DisableClockStopSleep\n
+ * APB1SMENR2 UCPD1SMEN LL_APB1_GRP2_DisableClockStopSleep
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP2_PERIPH_ALL
+ * @arg @ref LL_APB1_GRP2_PERIPH_I2C4
+ * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
+ * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1
+ * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB1SMENR2, Periphs);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EF_APB2 APB2
+ * @{
+ */
+
+/**
+ * @brief Enable APB2 peripherals clock.
+ * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->APB2ENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if APB2 peripheral clock is enabled or not
+ * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+ * @retval State of Periphs (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+ return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Disable APB2 peripherals clock.
+ * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB2ENR, Periphs);
+}
+
+/**
+ * @brief Force APB2 peripherals reset.
+ * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
+{
+ SET_BIT(RCC->APB2RSTR, Periphs);
+}
+
+/**
+ * @brief Release APB2 peripherals reset.
+ * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB2RSTR, Periphs);
+}
+
+/**
+ * @brief Enable APB2 peripheral clocks in Sleep and Stop modes
+ * @rmtoll APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
+ * APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
+ * APB2SMENR TIM8SMEN LL_APB2_GRP1_EnableClockStopSleep\n
+ * APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
+ * APB2SMENR TIM15SMEN LL_APB2_GRP1_EnableClockStopSleep\n
+ * APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockStopSleep\n
+ * APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep\n
+ * APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
+ * APB2SMENR SAI2SMEN LL_APB2_GRP1_EnableClockStopSleep
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->APB2SMENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->APB2SMENR, Periphs);
+ (void)tmpreg;
+}
+
+
+/**
+ * @brief Check if APB2 peripheral clocks in Sleep and Stop modes is enabled or not
+ * @rmtoll APB2SMENR TIM1SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
+ * APB2SMENR SPI1SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
+ * APB2SMENR TIM8SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
+ * APB2SMENR USART1SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
+ * APB2SMENR TIM15SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
+ * APB2SMENR TIM16SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
+ * APB2SMENR TIM17SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
+ * APB2SMENR SAI1SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
+ * APB2SMENR SAI2SMEN LL_APB2_GRP1_IsEnabledClockStopSleep
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+ * @retval State of Periphs (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)
+{
+ return ((READ_BIT(RCC->APB2SMENR, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Disable APB2 peripheral clocks in Sleep and Stop modes
+ * @rmtoll APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
+ * APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
+ * APB2SMENR TIM8SMEN LL_APB2_GRP1_DisableClockStopSleep\n
+ * APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
+ * APB2SMENR TIM15SMEN LL_APB2_GRP1_DisableClockStopSleep\n
+ * APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockStopSleep\n
+ * APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep\n
+ * APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
+ * APB2SMENR SAI2SMEN LL_APB2_GRP1_DisableClockStopSleep
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB2SMENR, Periphs);
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup BUS_LL_EF_APB3 APB3
+ * @{
+ */
+
+/**
+ * @brief Enable APB3 peripherals clock.
+ * @rmtoll APB3ENR SYSCFGEN LL_APB3_GRP1_EnableClock\n
+ * APB3ENR SPI3EN LL_APB3_GRP1_EnableClock\n
+ * APB3ENR LPUART1EN LL_APB3_GRP1_EnableClock\n
+ * APB3ENR I2C3EN LL_APB3_GRP1_EnableClock\n
+ * APB3ENR LPTIM1EN LL_APB3_GRP1_EnableClock\n
+ * APB3ENR LPTIM3EN LL_APB3_GRP1_EnableClock\n
+ * APB3ENR LPTIM4EN LL_APB3_GRP1_EnableClock\n
+ * APB3ENR OPAMPEN LL_APB3_GRP1_EnableClock\n
+ * APB3ENR COMPEN LL_APB3_GRP1_EnableClock\n
+ * APB3ENR VREFEN LL_APB3_GRP1_EnableClock\n
+ * APB3ENR RTCAPBEN LL_APB3_GRP1_EnableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB3_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG
+ * @arg @ref LL_APB3_GRP1_PERIPH_SPI3
+ * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1
+ * @arg @ref LL_APB3_GRP1_PERIPH_I2C3
+ * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1
+ * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
+ * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
+ * @arg @ref LL_APB3_GRP1_PERIPH_OPAMP
+ * @arg @ref LL_APB3_GRP1_PERIPH_COMP
+ * @arg @ref LL_APB3_GRP1_PERIPH_VREF
+ * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB3_GRP1_EnableClock(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->APB3ENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->APB3ENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if APB3 peripheral clock is enabled or not
+ * @rmtoll APB3ENR SYSCFGEN LL_APB3_GRP1_IsEnabledClock\n
+ * APB3ENR SPI3EN LL_APB3_GRP1_IsEnabledClock\n
+ * APB3ENR LPUART1EN LL_APB3_GRP1_IsEnabledClock\n
+ * APB3ENR I2C3EN LL_APB3_GRP1_IsEnabledClock\n
+ * APB3ENR LPTIM1EN LL_APB3_GRP1_IsEnabledClock\n
+ * APB3ENR LPTIM3EN LL_APB3_GRP1_IsEnabledClock\n
+ * APB3ENR LPTIM4EN LL_APB3_GRP1_IsEnabledClock\n
+ * APB3ENR OPAMPEN LL_APB3_GRP1_IsEnabledClock\n
+ * APB3ENR COMPEN LL_APB3_GRP1_IsEnabledClock\n
+ * APB3ENR VREFEN LL_APB3_GRP1_IsEnabledClock\n
+ * APB3ENR RTCAPBEN LL_APB3_GRP1_IsEnabledClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB3_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG
+ * @arg @ref LL_APB3_GRP1_PERIPH_SPI3
+ * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1
+ * @arg @ref LL_APB3_GRP1_PERIPH_I2C3
+ * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1
+ * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
+ * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
+ * @arg @ref LL_APB3_GRP1_PERIPH_OPAMP
+ * @arg @ref LL_APB3_GRP1_PERIPH_COMP
+ * @arg @ref LL_APB3_GRP1_PERIPH_VREF
+ * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB
+ * @retval State of Periphs (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+ return ((READ_BIT(RCC->APB3ENR, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Disable APB2 peripherals clock.
+ * @rmtoll APB3ENR SYSCFGEN LL_APB3_GRP1_DisableClock\n
+ * APB3ENR SPI3EN LL_APB3_GRP1_DisableClock\n
+ * APB3ENR LPUART1EN LL_APB3_GRP1_DisableClock\n
+ * APB3ENR I2C3EN LL_APB3_GRP1_DisableClock\n
+ * APB3ENR LPTIM1EN LL_APB3_GRP1_DisableClock\n
+ * APB3ENR LPTIM3EN LL_APB3_GRP1_DisableClock\n
+ * APB3ENR LPTIM4EN LL_APB3_GRP1_DisableClock\n
+ * APB3ENR OPAMPEN LL_APB3_GRP1_DisableClock\n
+ * APB3ENR COMPEN LL_APB3_GRP1_DisableClock\n
+ * APB3ENR VREFEN LL_APB3_GRP1_DisableClock\n
+ * APB3ENR RTCAPBEN LL_APB3_GRP1_DisableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB3_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG
+ * @arg @ref LL_APB3_GRP1_PERIPH_SPI3
+ * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1
+ * @arg @ref LL_APB3_GRP1_PERIPH_I2C3
+ * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1
+ * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
+ * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
+ * @arg @ref LL_APB3_GRP1_PERIPH_OPAMP
+ * @arg @ref LL_APB3_GRP1_PERIPH_COMP
+ * @arg @ref LL_APB3_GRP1_PERIPH_VREF
+ * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB3_GRP1_DisableClock(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB3ENR, Periphs);
+}
+
+/**
+ * @brief Force APB3 peripherals reset.
+ * @rmtoll APB3RSTR SYSCFGRST LL_APB3_GRP1_ForceReset\n
+ * APB3RSTR SPI3RST LL_APB3_GRP1_ForceReset\n
+ * APB3RSTR LPUART1RST LL_APB3_GRP1_ForceReset\n
+ * APB3RSTR I2C3RST LL_APB3_GRP1_ForceReset\n
+ * APB3RSTR LPTIM1RST LL_APB3_GRP1_ForceReset\n
+ * APB3RSTR LPTIM3RST LL_APB3_GRP1_ForceReset\n
+ * APB3RSTR LPTIM4RST LL_APB3_GRP1_ForceReset\n
+ * APB3RSTR OPAMPRST LL_APB3_GRP1_ForceReset\n
+ * APB3RSTR COMPRST LL_APB3_GRP1_ForceReset\n
+ * APB3RSTR VREFRST LL_APB3_GRP1_ForceReset\n
+ * APB3RSTR RTCAPBRST LL_APB3_GRP1_ForceReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB3_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG
+ * @arg @ref LL_APB3_GRP1_PERIPH_SPI3
+ * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1
+ * @arg @ref LL_APB3_GRP1_PERIPH_I2C3
+ * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1
+ * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
+ * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
+ * @arg @ref LL_APB3_GRP1_PERIPH_OPAMP
+ * @arg @ref LL_APB3_GRP1_PERIPH_COMP
+ * @arg @ref LL_APB3_GRP1_PERIPH_VREF
+ * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB3_GRP1_ForceReset(uint32_t Periphs)
+{
+ SET_BIT(RCC->APB3RSTR, Periphs);
+}
+
+/**
+ * @brief Release APB3 peripherals reset.
+ * @rmtoll APB3RSTR SYSCFGRST LL_APB3_GRP1_ReleaseReset\n
+ * APB3RSTR SPI3RST LL_APB3_GRP1_ReleaseReset\n
+ * APB3RSTR LPUART1RST LL_APB3_GRP1_ReleaseReset\n
+ * APB3RSTR I2C3RST LL_APB3_GRP1_ReleaseReset\n
+ * APB3RSTR LPTIM1RST LL_APB3_GRP1_ReleaseReset\n
+ * APB3RSTR LPTIM3RST LL_APB3_GRP1_ReleaseReset\n
+ * APB3RSTR LPTIM4RST LL_APB3_GRP1_ReleaseReset\n
+ * APB3RSTR OPAMPRST LL_APB3_GRP1_ReleaseReset\n
+ * APB3RSTR COMPRST LL_APB3_GRP1_ReleaseReset\n
+ * APB3RSTR VREFRST LL_APB3_GRP1_ReleaseReset\n
+ * APB3RSTR RTCAPBRST LL_APB3_GRP1_ReleaseReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB3_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG
+ * @arg @ref LL_APB3_GRP1_PERIPH_SPI3
+ * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1
+ * @arg @ref LL_APB3_GRP1_PERIPH_I2C3
+ * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1
+ * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
+ * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
+ * @arg @ref LL_APB3_GRP1_PERIPH_OPAMP
+ * @arg @ref LL_APB3_GRP1_PERIPH_COMP
+ * @arg @ref LL_APB3_GRP1_PERIPH_VREF
+ * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB3_GRP1_ReleaseReset(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB3RSTR, Periphs);
+}
+
+/**
+ * @brief Enable APB3 peripheral clocks in Sleep and Stop modes
+ * @rmtoll APB3SMENR SYSCFGSMEN LL_APB3_GRP1_EnableClockStopSleep\n
+ * APB3SMENR SPI3SMEN LL_APB3_GRP1_EnableClockStopSleep\n
+ * APB3SMENR LPUART1SMEN LL_APB3_GRP1_EnableClockStopSleep\n
+ * APB3SMENR I2C3SMEN LL_APB3_GRP1_EnableClockStopSleep\n
+ * APB3SMENR LPTIM1SMEN LL_APB3_GRP1_EnableClockStopSleep\n
+ * APB3SMENR LPTIM3SMEN LL_APB3_GRP1_EnableClockStopSleep\n
+ * APB3SMENR LPTIM4SMEN LL_APB3_GRP1_EnableClockStopSleep\n
+ * APB3SMENR OPAMPSMEN LL_APB3_GRP1_EnableClockStopSleep\n
+ * APB3SMENR COMPSMEN LL_APB3_GRP1_EnableClockStopSleep\n
+ * APB3SMENR VREFSMEN LL_APB3_GRP1_EnableClockStopSleep\n
+ * APB3SMENR RTCAPBSMEN LL_APB3_GRP1_EnableClockStopSleep
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB3_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG
+ * @arg @ref LL_APB3_GRP1_PERIPH_SPI3
+ * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1
+ * @arg @ref LL_APB3_GRP1_PERIPH_I2C3
+ * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1
+ * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
+ * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
+ * @arg @ref LL_APB3_GRP1_PERIPH_OPAMP
+ * @arg @ref LL_APB3_GRP1_PERIPH_COMP
+ * @arg @ref LL_APB3_GRP1_PERIPH_VREF
+ * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB3_GRP1_EnableClockStopSleep(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->APB3SMENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->APB3SMENR, Periphs);
+ (void)tmpreg;
+}
+
+
+/**
+ * @brief Check if APB3 peripheral clocks in Sleep and Stop modes is enabled or not
+ * @rmtoll APB3SMENR SYSCFGSMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n
+ * APB3SMENR SPI3SMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n
+ * APB3SMENR LPUART1SMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n
+ * APB3SMENR I2C3SMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n
+ * APB3SMENR LPTIM1SMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n
+ * APB3SMENR LPTIM3SMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n
+ * APB3SMENR LPTIM4SMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n
+ * APB3SMENR OPAMPSMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n
+ * APB3SMENR COMPSMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n
+ * APB3SMENR VREFSMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n
+ * APB3SMENR RTCAPBSMEN LL_APB3_GRP1_IsEnabledClockStopSleep
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB3_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG
+ * @arg @ref LL_APB3_GRP1_PERIPH_SPI3
+ * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1
+ * @arg @ref LL_APB3_GRP1_PERIPH_I2C3
+ * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1
+ * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
+ * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
+ * @arg @ref LL_APB3_GRP1_PERIPH_OPAMP
+ * @arg @ref LL_APB3_GRP1_PERIPH_COMP
+ * @arg @ref LL_APB3_GRP1_PERIPH_VREF
+ * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB
+ * @retval State of Periphs (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)
+{
+ return ((READ_BIT(RCC->APB3SMENR, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Disable APB3 peripheral clocks in Sleep and Stop modes
+ * @rmtoll APB3SMENR SYSCFGSMEN LL_APB3_GRP1_DisableClockStopSleep\n
+ * APB3SMENR SPI3SMEN LL_APB3_GRP1_DisableClockStopSleep\n
+ * APB3SMENR LPUART1SMEN LL_APB3_GRP1_DisableClockStopSleep\n
+ * APB3SMENR I2C3SMEN LL_APB3_GRP1_DisableClockStopSleep\n
+ * APB3SMENR LPTIM1SMEN LL_APB3_GRP1_DisableClockStopSleep\n
+ * APB3SMENR LPTIM3SMEN LL_APB3_GRP1_DisableClockStopSleep\n
+ * APB3SMENR LPTIM4SMEN LL_APB3_GRP1_DisableClockStopSleep\n
+ * APB3SMENR OPAMPSMEN LL_APB3_GRP1_DisableClockStopSleep\n
+ * APB3SMENR COMPSMEN LL_APB3_GRP1_DisableClockStopSleep\n
+ * APB3SMENR VREFSMEN LL_APB3_GRP1_DisableClockStopSleep\n
+ * APB3SMENR RTCAPBSMEN LL_APB3_GRP1_DisableClockStopSleep
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB3_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG
+ * @arg @ref LL_APB3_GRP1_PERIPH_SPI3
+ * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1
+ * @arg @ref LL_APB3_GRP1_PERIPH_I2C3
+ * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1
+ * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
+ * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
+ * @arg @ref LL_APB3_GRP1_PERIPH_OPAMP
+ * @arg @ref LL_APB3_GRP1_PERIPH_COMP
+ * @arg @ref LL_APB3_GRP1_PERIPH_VREF
+ * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB3_GRP1_DisableClockStopSleep(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB3SMENR, Periphs);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EF_S2DAMR S2DAMR
+ * @{
+ */
+
+/**
+ * @brief Enable SRDAMR peripheral clocks in autonomous mode
+ * @rmtoll S2DAMR SPI3AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
+ * S2DAMR LPUART1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
+ * S2DAMR I2C3AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
+ * S2DAMR LPTIM1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
+ * S2DAMR LPTIM3AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
+ * S2DAMR LPTIM4AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
+ * S2DAMR OPAMPAMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
+ * S2DAMR COMPAMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
+ * S2DAMR VREFAMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
+ * S2DAMR VREFRST LL_SRDAMR_GRP1_EnableAutonomousClock\n
+ * S2DAMR RTCAPBAMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
+ * S2DAMR ADC4AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
+ * S2DAMR LPGPIO1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
+ * S2DAMR DAC1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
+ * S2DAMR LPDMA1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
+ * S2DAMR ADF1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
+ * S2DAMR SRAM4AMEN LL_SRDAMR_GRP1_EnableAutonomousClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_ALL
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_SPI3AMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPUART1AMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_I2C3AMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM1AMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM3AMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM4AMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_OPAMPAMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_COMPAMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_VREFAMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_RTCAPBAMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_ADC4AMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPGPIO1AMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_DAC1AMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPDMA1AMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_ADF1AMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_SRAM4AMEN
+ * @retval None
+ */
+__STATIC_INLINE void LL_SRDAMR_GRP1_EnableAutonomousClock(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->SRDAMR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->SRDAMR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if S2DAMR peripheral clock is enabled or not
+ * @rmtoll S2DAMR SPI3AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
+ * S2DAMR LPUART1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
+ * S2DAMR I2C3AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
+ * S2DAMR LPTIM1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
+ * S2DAMR LPTIM3AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
+ * S2DAMR LPTIM4AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
+ * S2DAMR OPAMPAMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
+ * S2DAMR COMPAMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
+ * S2DAMR VREFAMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
+ * S2DAMR VREFRST LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
+ * S2DAMR RTCAPBAMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
+ * S2DAMR ADC4AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
+ * S2DAMR LPGPIO1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
+ * S2DAMR DAC1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
+ * S2DAMR LPDMA1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
+ * S2DAMR ADF1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
+ * S2DAMR SRAM4AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_ALL
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_SPI3AMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPUART1AMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_I2C3AMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM1AMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM3AMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM4AMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_OPAMPAMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_COMPAMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_VREFAMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_RTCAPBAMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_ADC4AMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPGPIO1AMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_DAC1AMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPDMA1AMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_ADF1AMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_SRAM4AMEN
+ * @retval State of Periphs (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SRDAMR_GRP1_IsEnabledAutonomousClock(uint32_t Periphs)
+{
+ return ((READ_BIT(RCC->SRDAMR, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Disable S2DAMR peripheral clocks in Sleep and Stop modes
+ * @rmtoll S2DAMR SPI3AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
+ * S2DAMR LPUART1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
+ * S2DAMR I2C3AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
+ * S2DAMR LPTIM1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
+ * S2DAMR LPTIM3AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
+ * S2DAMR LPTIM4AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
+ * S2DAMR OPAMPAMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
+ * S2DAMR COMPAMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
+ * S2DAMR VREFAMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
+ * S2DAMR VREFRST LL_SRDAMR_GRP1_DisableAutonomousClock\n
+ * S2DAMR RTCAPBAMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
+ * S2DAMR ADC4AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
+ * S2DAMR LPGPIO1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
+ * S2DAMR DAC1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
+ * S2DAMR LPDMA1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
+ * S2DAMR ADF1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
+ * S2DAMR SRAM4AMEN LL_SRDAMR_GRP1_DisableAutonomousClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_ALL
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_SPI3AMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPUART1AMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_I2C3AMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM1AMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM3AMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM4AMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_OPAMPAMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_COMPAMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_VREFAMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_RTCAPBAMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_ADC4AMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPGPIO1AMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_DAC1AMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPDMA1AMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_ADF1AMEN
+ * @arg @ref LL_SRDAMR_GRP1_PERIPH_SRAM4AMEN
+ * @retval None
+ */
+__STATIC_INLINE void LL_SRDAMR_GRP1_DisableAutonomousClock(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->SRDAMR, Periphs);
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* defined(RCC) */
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_LL_BUS_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_comp.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_comp.h
new file mode 100644
index 00000000..b5b200e7
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_comp.h
@@ -0,0 +1,872 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_comp.h
+ * @author MCD Application Team
+ * @brief Header file of COMP LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_LL_COMP_H
+#define STM32U5xx_LL_COMP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx.h"
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined (COMP1) || defined (COMP2)
+
+/** @defgroup COMP_LL COMP
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup COMP_LL_Private_Constants COMP Private Constants
+ * @{
+ */
+
+/* Internal mask for pair of comparators instances window mode: */
+/* To select into literals LL_COMP_WINDOWMODE_COMPx_INPUT_PLUS_COMMON */
+/* the relevant bits for: */
+/* (concatenation of multiple bits used in different registers) */
+/* - Comparator instance selected as master for window mode : register offset */
+/* - Window mode enable or disable: bit value */
+#define LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK (0x00000000UL) /* Register of COMP instance odd (COMP1_CSR, ...)
+ defined as reference register */
+#define LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK (0x00000001UL) /* Register of COMP instance even (COMP2_CSR, ...)
+ offset vs register of COMP instance odd */
+#define LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK (LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK\
+ | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK)
+#define LL_COMP_WINDOWMODE_COMPX_SETTING_MASK (COMP_CSR_WINMODE)
+#define LL_COMP_WINDOWOUTPUT_COMPX_SETTING_MASK (COMP_CSR_WINOUT)
+#define LL_COMP_WINDOWOUTPUT_BOTH_SETTING_MASK (COMP_CSR_WINOUT << 1UL)
+#define LL_COMP_WINDOWOUTPUT_BOTH_POS_VS_WINDOW (1UL)
+
+/* COMP registers bits positions */
+#define LL_COMP_WINDOWMODE_BITOFFSET_POS (11UL) /* Value equivalent to POSITION_VAL(COMP_CSR_WINMODE) */
+#define LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS (30UL) /* Value equivalent to POSITION_VAL(COMP_CSR_VALUE) */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup COMP_LL_Private_Macros COMP Private Macros
+ * @{
+ */
+
+/**
+ * @brief Driver macro reserved for internal use: set a pointer to
+ * a register from a register basis from which an offset
+ * is applied.
+ * @param __REG__ Register basis from which the offset is applied.
+ * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
+ * @retval Pointer to register address
+ */
+#define __COMP_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
+ ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
+
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup COMP_LL_ES_INIT COMP Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief Structure definition of some features of COMP instance.
+ */
+typedef struct
+{
+ uint32_t PowerMode; /*!< Set comparator operating mode to adjust power and speed.
+ This parameter can be a value of @ref COMP_LL_EC_POWERMODE
+ This feature can be modified afterwards using
+ unitary function @ref LL_COMP_SetPowerMode(). */
+
+ uint32_t InputPlus; /*!< Set comparator input plus (non-inverting input).
+ This parameter can be a value of @ref COMP_LL_EC_INPUT_PLUS
+ This feature can be modified afterwards using
+ unitary function @ref LL_COMP_SetInputPlus(). */
+
+ uint32_t InputMinus; /*!< Set comparator input minus (inverting input).
+ This parameter can be a value of @ref COMP_LL_EC_INPUT_MINUS
+ This feature can be modified afterwards using
+ unitary function @ref LL_COMP_SetInputMinus(). */
+
+ uint32_t InputHysteresis; /*!< Set comparator hysteresis mode of the input minus.
+ This parameter can be a value of @ref COMP_LL_EC_INPUT_HYSTERESIS
+ This feature can be modified afterwards using
+ unitary function @ref LL_COMP_SetInputHysteresis(). */
+
+ uint32_t OutputPolarity; /*!< Set comparator output polarity.
+ This parameter can be a value of @ref COMP_LL_EC_OUTPUT_POLARITY
+ This feature can be modified afterwards using
+ unitary function @ref LL_COMP_SetOutputPolarity(). */
+
+ uint32_t OutputBlankingSource; /*!< Set comparator blanking source.
+ This parameter can be a value of @ref COMP_LL_EC_OUTPUT_BLANKING_SOURCE
+ This feature can be modified afterwards using
+ unitary function @ref LL_COMP_SetOutputBlankingSource(). */
+
+} LL_COMP_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup COMP_LL_Exported_Constants COMP Exported Constants
+ * @{
+ */
+
+/** @defgroup COMP_LL_EC_COMMON_WINDOWMODE Comparator common modes - Window mode
+ * @{
+ */
+#define LL_COMP_WINDOWMODE_DISABLE (0x00000000UL) /*!< Window mode disable: Comparators 1 and 2 are independent */
+#define LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK) /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */
+#define LL_COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON (COMP_CSR_WINMODE | LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK) /*!< Window mode enable: if used from COMP1 or COMP2 instance, comparators instances pair COMP1 and COMP2 have their input plus connected together, the common input is COMP2 input plus (COMP1 input plus is no more accessible) */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_COMMON_WINDOWOUTPUT Comparator common modes - Window output
+ * @{
+ */
+#define LL_COMP_WINDOWOUTPUT_EACH_COMP (0x00000000UL) /*!< Window output default mode: Comparators output are indicating each their own state. To know window mode state: each comparator output must be read, if "((COMPx exclusive or COMPy) == 1)" then monitored signal is within comparators window. The same way, if both comparators output are high, then monitored signal is below window. */
+#define LL_COMP_WINDOWOUTPUT_COMP1 (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK) /*!< Window output synthetized on COMP1 output: COMP1 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). */
+#define LL_COMP_WINDOWOUTPUT_COMP2 (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK) /*!< Window output synthetized on COMP2 output: COMP2 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). */
+#define LL_COMP_WINDOWOUTPUT_BOTH (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK | LL_COMP_WINDOWOUTPUT_BOTH_SETTING_MASK) /*!< Window output synthetized on both comparators output of pair of comparator selected (COMP1 and COMP2): both comparators outputs are no more indicating their own state, but global window mode state (logical high means monitored signal is within comparators window). This is a specific configuration (technically possible but not relevant from application point of view: 2 comparators output used for the same signal level), standard configuration for window mode is one of the settings above. */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_POWERMODE Comparator modes - Power mode
+ * @{
+ */
+#define LL_COMP_POWERMODE_HIGHSPEED (0x00000000UL) /*!< COMP power mode to high speed */
+#define LL_COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0) /*!< COMP power mode to medium speed */
+#define LL_COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_PWRMODE_1 | COMP_CSR_PWRMODE_0) /*!< COMP power mode to ultra-low power */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_INPUT_PLUS Comparator inputs - Input plus (input non-inverting) selection
+ * @{
+ */
+#define LL_COMP_INPUT_PLUS_IO1 (0x00000000UL) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2) */
+#define LL_COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0) /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2) */
+#define LL_COMP_INPUT_PLUS_IO3 (COMP_CSR_INPSEL_1) /*!< Comparator input plus connected to IO3 (pin PA2 for COMP1) */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_INPUT_MINUS Comparator inputs - Input minus (input inverting) selection
+ * @{
+ */
+#define LL_COMP_INPUT_MINUS_1_4VREFINT (0x00000000UL ) /*!< Comparator input minus connected to 1/4 VrefInt */
+#define LL_COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to 1/2 VrefInt */
+#define LL_COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to 3/4 VrefInt */
+#define LL_COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to VrefInt */
+#define LL_COMP_INPUT_MINUS_DAC1_CH1 (COMP_CSR_INMSEL_2 ) /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) */
+#define LL_COMP_INPUT_MINUS_DAC1_CH2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */
+#define LL_COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB3 for COMP2) */
+#define LL_COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PB7 for COMP2) */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_INPUT_HYSTERESIS Comparator input - Hysteresis
+ * @{
+ */
+#define LL_COMP_HYSTERESIS_NONE (0x00000000UL) /*!< No hysteresis */
+#define LL_COMP_HYSTERESIS_LOW ( COMP_CSR_HYST_0) /*!< Hysteresis level low */
+#define LL_COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1 ) /*!< Hysteresis level medium */
+#define LL_COMP_HYSTERESIS_HIGH (COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level high */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_OUTPUT_POLARITY Comparator output - Output polarity
+ * @{
+ */
+#define LL_COMP_OUTPUTPOL_NONINVERTED (0x00000000UL) /*!< COMP output polarity is not inverted: comparator output is high when the plus (non-inverting) input is at a higher voltage than the minus (inverting) input */
+#define LL_COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY) /*!< COMP output polarity is inverted: comparator output is low when the plus (non-inverting) input is at a lower voltage than the minus (inverting) input */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_OUTPUT_BLANKING_SOURCE Comparator output - Blanking source
+ * @{
+ */
+#define LL_COMP_BLANKINGSRC_NONE ( 0x00000000UL) /*!__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in COMP register
+ * @param __INSTANCE__ comparator instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EM_HELPER_MACRO COMP helper macro
+ * @{
+ */
+
+/**
+ * @brief Helper macro to select the COMP common instance
+ * to which is belonging the selected COMP instance.
+ * @note COMP common register instance can be used to
+ * set parameters common to several COMP instances.
+ * Refer to functions having argument "COMPxy_COMMON" as parameter.
+ * @param __COMPx__ COMP instance
+ * @retval COMP common instance or value "0" if there is no COMP common instance.
+ */
+#define __LL_COMP_COMMON_INSTANCE(__COMPx__) (COMP12_COMMON)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup COMP_LL_Exported_Functions COMP Exported Functions
+ * @{
+ */
+
+/** @defgroup COMP_LL_EF_Configuration_comparator_common Configuration
+ * of COMP hierarchical scope: common to several COMP instances
+ * @{
+ */
+
+/**
+ * @brief Set window mode of a pair of comparators instances
+ * (2 consecutive COMP instances COMP and COMP).
+ * @rmtoll CSR WINMODE LL_COMP_SetCommonWindowMode
+ * @param COMPxy_COMMON Comparator common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
+ * @param WindowMode This parameter can be one of the following values:
+ * @arg @ref LL_COMP_WINDOWMODE_DISABLE
+ * @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (1)
+ * @arg @ref LL_COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON (1)
+ *
+ * (1) Parameter available on all STM32U5 devices, must be used with comparator common instance COMP12_COMMON
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode)
+{
+ /* Note: On this STM32 series, window mode can be set from any instance */
+ /* of the pair of comparator instances. */
+
+ __IO uint32_t *preg = __COMP_PTR_REG_OFFSET(COMPxy_COMMON->CSR_ODD,
+ (WindowMode & LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK));
+
+ /* Clear the potential previous setting of window mode */
+ __IO uint32_t *preg_clear = __COMP_PTR_REG_OFFSET(COMPxy_COMMON->CSR_ODD,
+ (~(WindowMode & LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK) & 0x1UL)
+ );
+ CLEAR_BIT(*preg_clear, COMP_CSR_WINMODE);
+
+ /* Set window mode */
+ MODIFY_REG(*preg, COMP_CSR_WINMODE, (WindowMode & LL_COMP_WINDOWMODE_COMPX_SETTING_MASK));
+}
+
+/**
+ * @brief Get window mode of a pair of comparators instances
+ * (2 consecutive COMP instances COMP and COMP).
+ * @rmtoll CSR WINMODE LL_COMP_GetCommonWindowMode
+ * @param COMPxy_COMMON Comparator common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_WINDOWMODE_DISABLE
+ * @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (1)
+ * @arg @ref LL_COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON (1)
+ *
+ * (1) Parameter available on all STM32U5 devices, must be used with comparator common instance COMP12_COMMON
+ */
+__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON)
+{
+ /* Note: On this STM32 series, window mode can be set from any instance */
+ /* of the pair of comparator instances. */
+
+ const uint32_t window_mode_comp_odd = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_ODD, COMP_CSR_WINMODE);
+ const uint32_t window_mode_comp_even = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_EVEN, COMP_CSR_WINMODE);
+
+ return (uint32_t)(window_mode_comp_odd
+ | window_mode_comp_even
+ | ((window_mode_comp_even >> LL_COMP_WINDOWMODE_BITOFFSET_POS)
+ * LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK)
+ );
+}
+
+/**
+ * @brief Set window output of a pair of comparators instances
+ * (2 consecutive COMP instances COMP and COMP).
+ * @rmtoll CSR WINOUT LL_COMP_SetCommonWindowOutput
+ * @param COMPxy_COMMON Comparator common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
+ * @param WindowOutput This parameter can be one of the following values:
+ * @arg @ref LL_COMP_WINDOWOUTPUT_EACH_COMP
+ * @arg @ref LL_COMP_WINDOWOUTPUT_COMP1 (1)
+ * @arg @ref LL_COMP_WINDOWOUTPUT_COMP2 (1)
+ * @arg @ref LL_COMP_WINDOWOUTPUT_BOTH
+ *
+ * (1) Parameter available on all STM32U5 devices, must be used with comparator common instance COMP12_COMMON
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_SetCommonWindowOutput(COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowOutput)
+{
+ __IO uint32_t *preg = __COMP_PTR_REG_OFFSET(COMPxy_COMMON->CSR_ODD,
+ (WindowOutput & LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK));
+
+ /* Clear the potential previous setting of window output on the relevant comparator instance */
+ /* (clear bit of window output unless specific case of setting of comparator both output selected) */
+ __IO uint32_t *preg_clear = __COMP_PTR_REG_OFFSET(COMPxy_COMMON->CSR_ODD,
+ (~(WindowOutput & LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK) & 0x1UL)
+ );
+ MODIFY_REG(*preg_clear,
+ COMP_CSR_WINOUT,
+ ((WindowOutput & LL_COMP_WINDOWOUTPUT_BOTH_SETTING_MASK) >> LL_COMP_WINDOWOUTPUT_BOTH_POS_VS_WINDOW)
+ );
+
+ /* Set window output */
+ MODIFY_REG(*preg,
+ COMP_CSR_WINOUT,
+ (WindowOutput & LL_COMP_WINDOWOUTPUT_COMPX_SETTING_MASK)
+ );
+}
+
+/**
+ * @brief Get window output of a pair of comparators instances
+ * (2 consecutive COMP instances COMP and COMP).
+ * @rmtoll CSR WINMODE LL_COMP_GetCommonWindowOutput
+ * @param COMPxy_COMMON Comparator common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_WINDOWOUTPUT_EACH_COMP
+ * @arg @ref LL_COMP_WINDOWOUTPUT_COMP1 (1)
+ * @arg @ref LL_COMP_WINDOWOUTPUT_COMP2 (1)
+ * @arg @ref LL_COMP_WINDOWOUTPUT_BOTH
+ *
+ * (1) Parameter available on all STM32U5 devices, must be used with comparator common instance COMP12_COMMON
+ */
+__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowOutput(COMP_Common_TypeDef *COMPxy_COMMON)
+{
+ const uint32_t window_output_comp_odd = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_ODD, COMP_CSR_WINOUT);
+ const uint32_t window_output_comp_even = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_EVEN, COMP_CSR_WINOUT);
+
+ /* Construct value corresponding to LL_COMP_WINDOWOUTPUT_xxx */
+ return (uint32_t)(window_output_comp_odd
+ | window_output_comp_even
+ | ((window_output_comp_even >> COMP_CSR_WINOUT_Pos) * LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK)
+ | (window_output_comp_odd + window_output_comp_even));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EF_Configuration_comparator_modes Configuration of comparator modes
+ * @{
+ */
+
+/**
+ * @brief Set comparator instance operating mode to adjust power and speed.
+ * @rmtoll CSR PWRMODE LL_COMP_SetPowerMode
+ * @param COMPx Comparator instance
+ * @param PowerMode This parameter can be one of the following values:
+ * @arg @ref LL_COMP_POWERMODE_HIGHSPEED
+ * @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED
+ * @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_SetPowerMode(COMP_TypeDef *COMPx, uint32_t PowerMode)
+{
+ MODIFY_REG(COMPx->CSR, COMP_CSR_PWRMODE, PowerMode);
+}
+
+/**
+ * @brief Get comparator instance operating mode to adjust power and speed.
+ * @rmtoll CSR PWRMODE LL_COMP_GetPowerMode
+ * @param COMPx Comparator instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_POWERMODE_HIGHSPEED
+ * @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED
+ * @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER
+ */
+__STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx)
+{
+ return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_PWRMODE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EF_Configuration_comparator_inputs Configuration of comparator inputs
+ * @{
+ */
+
+/**
+ * @brief Set comparator inputs minus (inverting) and plus (non-inverting).
+ * @note In case of comparator input selected to be connected to IO:
+ * GPIO pins are specific to each comparator instance.
+ * Refer to description of parameters or to reference manual.
+ * @note On this STM32 series, a voltage scaler is used
+ * when COMP input is based on VrefInt (VrefInt or subdivision
+ * of VrefInt):
+ * Voltage scaler requires a delay for voltage stabilization.
+ * Refer to device datasheet, parameter "tSTART_SCALER".
+ * @rmtoll CSR INMSEL LL_COMP_ConfigInputs\n
+ * CSR INPSEL LL_COMP_ConfigInputs\n
+ * @param COMPx Comparator instance
+ * @param InputMinus This parameter can be one of the following values:
+ * @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2
+ * @arg @ref LL_COMP_INPUT_MINUS_IO1
+ * @arg @ref LL_COMP_INPUT_MINUS_IO2
+ * @param InputPlus This parameter can be one of the following values:
+ * @arg @ref LL_COMP_INPUT_PLUS_IO1
+ * @arg @ref LL_COMP_INPUT_PLUS_IO2
+ * @arg @ref LL_COMP_INPUT_PLUS_IO3
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_ConfigInputs(COMP_TypeDef *COMPx, uint32_t InputMinus, uint32_t InputPlus)
+{
+ MODIFY_REG(COMPx->CSR, COMP_CSR_INMSEL | COMP_CSR_INPSEL, InputMinus | InputPlus);
+}
+
+/**
+ * @brief Set comparator input plus (non-inverting).
+ * @note In case of comparator input selected to be connected to IO:
+ * GPIO pins are specific to each comparator instance.
+ * Refer to description of parameters or to reference manual.
+ * @rmtoll CSR INPSEL LL_COMP_SetInputPlus
+ * @param COMPx Comparator instance
+ * @param InputPlus This parameter can be one of the following values:
+ * @arg @ref LL_COMP_INPUT_PLUS_IO1
+ * @arg @ref LL_COMP_INPUT_PLUS_IO2
+ * @arg @ref LL_COMP_INPUT_PLUS_IO3
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlus)
+{
+ MODIFY_REG(COMPx->CSR, COMP_CSR_INPSEL, InputPlus);
+}
+
+/**
+ * @brief Get comparator input plus (non-inverting).
+ * @note In case of comparator input selected to be connected to IO:
+ * GPIO pins are specific to each comparator instance.
+ * Refer to description of parameters or to reference manual.
+ * @rmtoll CSR INPSEL LL_COMP_GetInputPlus
+ * @param COMPx Comparator instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_INPUT_PLUS_IO1
+ * @arg @ref LL_COMP_INPUT_PLUS_IO2
+ * @arg @ref LL_COMP_INPUT_PLUS_IO3
+ */
+__STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx)
+{
+ return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INPSEL));
+}
+
+/**
+ * @brief Set comparator input minus (inverting).
+ * @note In case of comparator input selected to be connected to IO:
+ * GPIO pins are specific to each comparator instance.
+ * Refer to description of parameters or to reference manual.
+ * @note On this STM32 series, a voltage scaler is used
+ * when COMP input is based on VrefInt (VrefInt or subdivision
+ * of VrefInt):
+ * Voltage scaler requires a delay for voltage stabilization.
+ * Refer to device datasheet, parameter "tSTART_SCALER".
+ * @rmtoll CSR INMSEL LL_COMP_SetInputMinus
+ * @param COMPx Comparator instance
+ * @param InputMinus This parameter can be one of the following values:
+ * @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2
+ * @arg @ref LL_COMP_INPUT_MINUS_IO1
+ * @arg @ref LL_COMP_INPUT_MINUS_IO2
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *COMPx, uint32_t InputMinus)
+{
+ MODIFY_REG(COMPx->CSR, COMP_CSR_INMSEL, InputMinus);
+}
+
+/**
+ * @brief Get comparator input minus (inverting).
+ * @note In case of comparator input selected to be connected to IO:
+ * GPIO pins are specific to each comparator instance.
+ * Refer to description of parameters or to reference manual.
+ * @rmtoll CSR INMSEL LL_COMP_GetInputMinus
+ * @param COMPx Comparator instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2
+ * @arg @ref LL_COMP_INPUT_MINUS_IO1
+ * @arg @ref LL_COMP_INPUT_MINUS_IO2
+ */
+__STATIC_INLINE uint32_t LL_COMP_GetInputMinus(COMP_TypeDef *COMPx)
+{
+ return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INMSEL));
+}
+
+/**
+ * @brief Set comparator instance hysteresis mode of the input minus (inverting input).
+ * @rmtoll CSR HYST LL_COMP_SetInputHysteresis
+ * @param COMPx Comparator instance
+ * @param InputHysteresis This parameter can be one of the following values:
+ * @arg @ref LL_COMP_HYSTERESIS_NONE
+ * @arg @ref LL_COMP_HYSTERESIS_LOW
+ * @arg @ref LL_COMP_HYSTERESIS_MEDIUM
+ * @arg @ref LL_COMP_HYSTERESIS_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_SetInputHysteresis(COMP_TypeDef *COMPx, uint32_t InputHysteresis)
+{
+ MODIFY_REG(COMPx->CSR, COMP_CSR_HYST, InputHysteresis);
+}
+
+/**
+ * @brief Get comparator instance hysteresis mode of the minus (inverting) input.
+ * @rmtoll CSR HYST LL_COMP_GetInputHysteresis
+ * @param COMPx Comparator instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_HYSTERESIS_NONE
+ * @arg @ref LL_COMP_HYSTERESIS_LOW
+ * @arg @ref LL_COMP_HYSTERESIS_MEDIUM
+ * @arg @ref LL_COMP_HYSTERESIS_HIGH
+ */
+__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(COMP_TypeDef *COMPx)
+{
+ return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_HYST));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EF_Configuration_comparator_output Configuration of comparator output
+ * @{
+ */
+
+/**
+ * @brief Set comparator instance output polarity.
+ * @rmtoll CSR POLARITY LL_COMP_SetOutputPolarity
+ * @param COMPx Comparator instance
+ * @param OutputPolarity This parameter can be one of the following values:
+ * @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
+ * @arg @ref LL_COMP_OUTPUTPOL_INVERTED
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_SetOutputPolarity(COMP_TypeDef *COMPx, uint32_t OutputPolarity)
+{
+ MODIFY_REG(COMPx->CSR, COMP_CSR_POLARITY, OutputPolarity);
+}
+
+/**
+ * @brief Get comparator instance output polarity.
+ * @rmtoll CSR POLARITY LL_COMP_GetOutputPolarity
+ * @param COMPx Comparator instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
+ * @arg @ref LL_COMP_OUTPUTPOL_INVERTED
+ */
+__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(COMP_TypeDef *COMPx)
+{
+ return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_POLARITY));
+}
+
+/**
+ * @brief Set comparator instance blanking source.
+ * @note Blanking source may be specific to each comparator instance.
+ * Refer to description of parameters or to reference manual.
+ * @note Availability of parameters of blanking source from timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CSR BLANKSEL LL_COMP_SetOutputBlankingSource
+ * @param COMPx Comparator instance
+ * @param BlankingSource This parameter can be one of the following values:
+ * @arg @ref LL_COMP_BLANKINGSRC_NONE
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC4
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_SetOutputBlankingSource(COMP_TypeDef *COMPx, uint32_t BlankingSource)
+{
+ MODIFY_REG(COMPx->CSR, COMP_CSR_BLANKSEL, BlankingSource);
+}
+
+/**
+ * @brief Get comparator instance blanking source.
+ * @note Availability of parameters of blanking source from timer
+ * depends on timers availability on the selected device.
+ * @note Blanking source may be specific to each comparator instance.
+ * Refer to description of parameters or to reference manual.
+ * @rmtoll CSR BLANKSEL LL_COMP_GetOutputBlankingSource
+ * @param COMPx Comparator instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_BLANKINGSRC_NONE
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC4
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1
+ */
+__STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(COMP_TypeDef *COMPx)
+{
+ return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_BLANKSEL));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EF_Operation Operation on comparator instance
+ * @{
+ */
+
+/**
+ * @brief Enable comparator instance.
+ * @note After enable from off state, comparator requires a delay
+ * to reach reach propagation delay specification.
+ * Refer to device datasheet, parameter "tSTART".
+ * @rmtoll CSR EN LL_COMP_Enable
+ * @param COMPx Comparator instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_Enable(COMP_TypeDef *COMPx)
+{
+ SET_BIT(COMPx->CSR, COMP_CSR_EN);
+}
+
+/**
+ * @brief Disable comparator instance.
+ * @rmtoll CSR EN LL_COMP_Disable
+ * @param COMPx Comparator instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_Disable(COMP_TypeDef *COMPx)
+{
+ CLEAR_BIT(COMPx->CSR, COMP_CSR_EN);
+}
+
+/**
+ * @brief Get comparator enable state
+ * (0: COMP is disabled, 1: COMP is enabled)
+ * @rmtoll CSR EN LL_COMP_IsEnabled
+ * @param COMPx Comparator instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_COMP_IsEnabled(COMP_TypeDef *COMPx)
+{
+ return ((READ_BIT(COMPx->CSR, COMP_CSR_EN) == (COMP_CSR_EN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Lock comparator instance.
+ * @note Once locked, comparator configuration can be accessed in read-only.
+ * @note The only way to unlock the comparator is a device hardware reset.
+ * @rmtoll CSR LOCK LL_COMP_Lock
+ * @param COMPx Comparator instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_Lock(COMP_TypeDef *COMPx)
+{
+ SET_BIT(COMPx->CSR, COMP_CSR_LOCK);
+}
+
+/**
+ * @brief Get comparator lock state
+ * (0: COMP is unlocked, 1: COMP is locked).
+ * @note Once locked, comparator configuration can be accessed in read-only.
+ * @note The only way to unlock the comparator is a device hardware reset.
+ * @rmtoll CSR LOCK LL_COMP_IsLocked
+ * @param COMPx Comparator instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx)
+{
+ return ((READ_BIT(COMPx->CSR, COMP_CSR_LOCK) == (COMP_CSR_LOCK)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Read comparator instance output level.
+ * @note The comparator output level depends on the selected polarity
+ * (Refer to function @ref LL_COMP_SetOutputPolarity()).
+ * If the comparator polarity is not inverted:
+ * - Comparator output is low when the input plus
+ * is at a lower voltage than the input minus
+ * - Comparator output is high when the input plus
+ * is at a higher voltage than the input minus
+ * If the comparator polarity is inverted:
+ * - Comparator output is high when the input plus
+ * is at a lower voltage than the input minus
+ * - Comparator output is low when the input plus
+ * is at a higher voltage than the input minus
+ * @rmtoll CSR VALUE LL_COMP_ReadOutputLevel
+ * @param COMPx Comparator instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_OUTPUT_LEVEL_LOW
+ * @arg @ref LL_COMP_OUTPUT_LEVEL_HIGH
+ */
+__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(COMP_TypeDef *COMPx)
+{
+ return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_VALUE)
+ >> LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup COMP_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx);
+ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct);
+void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* COMP1 || COMP2 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_LL_COMP_H */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_cordic.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_cordic.h
new file mode 100644
index 00000000..4f6037ab
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_cordic.h
@@ -0,0 +1,783 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_cordic.h
+ * @author MCD Application Team
+ * @brief Header file of CORDIC LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_LL_CORDIC_H
+#define STM32U5xx_LL_CORDIC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx.h"
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined(CORDIC)
+
+/** @defgroup CORDIC_LL CORDIC
+ * @{
+ */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CORDIC_LL_Exported_Constants CORDIC Exported Constants
+ * @{
+ */
+
+/** @defgroup CORDIC_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_CORDIC_ReadReg function.
+ * @{
+ */
+#define LL_CORDIC_FLAG_RRDY CORDIC_CSR_RRDY
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_CORDIC_ReadReg and LL_CORDIC_WriteReg functions.
+ * @{
+ */
+#define LL_CORDIC_IT_IEN CORDIC_CSR_IEN /*!< Result Ready interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_LL_EC_FUNCTION FUNCTION
+ * @{
+ */
+#define LL_CORDIC_FUNCTION_COSINE (0x00000000U) /*!< Cosine */
+#define LL_CORDIC_FUNCTION_SINE ((uint32_t)(CORDIC_CSR_FUNC_0)) /*!< Sine */
+#define LL_CORDIC_FUNCTION_PHASE ((uint32_t)(CORDIC_CSR_FUNC_1)) /*!< Phase */
+#define LL_CORDIC_FUNCTION_MODULUS ((uint32_t)(CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0)) /*!< Modulus */
+#define LL_CORDIC_FUNCTION_ARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2)) /*!< Arctangent */
+#define LL_CORDIC_FUNCTION_HCOSINE ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_0)) /*!< Hyperbolic Cosine */
+#define LL_CORDIC_FUNCTION_HSINE ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1)) /*!< Hyperbolic Sine */
+#define LL_CORDIC_FUNCTION_HARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))/*!< Hyperbolic Arctangent */
+#define LL_CORDIC_FUNCTION_NATURALLOG ((uint32_t)(CORDIC_CSR_FUNC_3)) /*!< Natural Logarithm */
+#define LL_CORDIC_FUNCTION_SQUAREROOT ((uint32_t)(CORDIC_CSR_FUNC_3 | CORDIC_CSR_FUNC_0)) /*!< Square Root */
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_LL_EC_PRECISION PRECISION
+ * @{
+ */
+#define LL_CORDIC_PRECISION_1CYCLE ((uint32_t)(CORDIC_CSR_PRECISION_0))
+#define LL_CORDIC_PRECISION_2CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_1))
+#define LL_CORDIC_PRECISION_3CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
+#define LL_CORDIC_PRECISION_4CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2))
+#define LL_CORDIC_PRECISION_5CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))
+#define LL_CORDIC_PRECISION_6CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))
+#define LL_CORDIC_PRECISION_7CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2\
+ | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
+#define LL_CORDIC_PRECISION_8CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3))
+#define LL_CORDIC_PRECISION_9CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_0))
+#define LL_CORDIC_PRECISION_10CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1))
+#define LL_CORDIC_PRECISION_11CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
+ | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
+#define LL_CORDIC_PRECISION_12CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2))
+#define LL_CORDIC_PRECISION_13CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
+ | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))
+#define LL_CORDIC_PRECISION_14CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
+ | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))
+#define LL_CORDIC_PRECISION_15CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
+ | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1\
+ | CORDIC_CSR_PRECISION_0))
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_LL_EC_SCALE SCALE
+ * @{
+ */
+#define LL_CORDIC_SCALE_0 (0x00000000U)
+#define LL_CORDIC_SCALE_1 ((uint32_t)(CORDIC_CSR_SCALE_0))
+#define LL_CORDIC_SCALE_2 ((uint32_t)(CORDIC_CSR_SCALE_1))
+#define LL_CORDIC_SCALE_3 ((uint32_t)(CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0))
+#define LL_CORDIC_SCALE_4 ((uint32_t)(CORDIC_CSR_SCALE_2))
+#define LL_CORDIC_SCALE_5 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_0))
+#define LL_CORDIC_SCALE_6 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1))
+#define LL_CORDIC_SCALE_7 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0))
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_LL_EC_NBWRITE NBWRITE
+ * @{
+ */
+#define LL_CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one
+ 32-bit data input (Q1.31 format), or two
+ 16-bit data input (Q1.15 format) packed
+ in one 32 bits Data */
+#define LL_CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bits data input
+ (Q1.31 format) */
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_LL_EC_NBREAD NBREAD
+ * @{
+ */
+#define LL_CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one
+ 32-bit data output (Q1.31 format), or two
+ 16-bit data output (Q1.15 format) packed
+ in one 32 bits Data */
+#define LL_CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output
+ (Q1.31 format) */
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_LL_EC_INSIZE INSIZE
+ * @{
+ */
+#define LL_CORDIC_INSIZE_32BITS (0x00000000U) /*!< 32 bits input data size (Q1.31 format) */
+#define LL_CORDIC_INSIZE_16BITS CORDIC_CSR_ARGSIZE /*!< 16 bits input data size (Q1.15 format) */
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_LL_EC_OUTSIZE OUTSIZE
+ * @{
+ */
+#define LL_CORDIC_OUTSIZE_32BITS (0x00000000U) /*!< 32 bits output data size (Q1.31 format) */
+#define LL_CORDIC_OUTSIZE_16BITS CORDIC_CSR_RESSIZE /*!< 16 bits output data size (Q1.15 format) */
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_LL_EC_DMA_REG_DATA DMA register data
+ * @{
+ */
+#define LL_CORDIC_DMA_REG_DATA_IN (0x00000000U) /*!< Get address of input data register */
+#define LL_CORDIC_DMA_REG_DATA_OUT (0x00000001U) /*!< Get address of output data register */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CORDIC_LL_Exported_Macros CORDIC Exported Macros
+ * @{
+ */
+
+/** @defgroup CORDIC_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in CORDIC register.
+ * @param __INSTANCE__ CORDIC Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_CORDIC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in CORDIC register.
+ * @param __INSTANCE__ CORDIC Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_CORDIC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup CORDIC_LL_Exported_Functions CORDIC Exported Functions
+ * @{
+ */
+
+/** @defgroup CORDIC_LL_EF_Configuration CORDIC Configuration functions
+ * @{
+ */
+
+/**
+ * @brief Configure the CORDIC processing.
+ * @note This function set all parameters of CORDIC processing.
+ * These parameters can also be set individually using
+ * dedicated functions:
+ * - @ref LL_CORDIC_SetFunction()
+ * - @ref LL_CORDIC_SetPrecision()
+ * - @ref LL_CORDIC_SetScale()
+ * - @ref LL_CORDIC_SetNbWrite()
+ * - @ref LL_CORDIC_SetNbRead()
+ * - @ref LL_CORDIC_SetInSize()
+ * - @ref LL_CORDIC_SetOutSize()
+ * @rmtoll CSR FUNC LL_CORDIC_Configure\n
+ * CSR PRECISION LL_CORDIC_Configure\n
+ * CSR SCALE LL_CORDIC_Configure\n
+ * CSR NARGS LL_CORDIC_Configure\n
+ * CSR NRES LL_CORDIC_Configure\n
+ * CSR ARGSIZE LL_CORDIC_Configure\n
+ * CSR RESIZE LL_CORDIC_Configure
+ * @param CORDICx CORDIC instance
+ * @param Function parameter can be one of the following values:
+ * @arg @ref LL_CORDIC_FUNCTION_COSINE
+ * @arg @ref LL_CORDIC_FUNCTION_SINE
+ * @arg @ref LL_CORDIC_FUNCTION_PHASE
+ * @arg @ref LL_CORDIC_FUNCTION_MODULUS
+ * @arg @ref LL_CORDIC_FUNCTION_ARCTANGENT
+ * @arg @ref LL_CORDIC_FUNCTION_HCOSINE
+ * @arg @ref LL_CORDIC_FUNCTION_HSINE
+ * @arg @ref LL_CORDIC_FUNCTION_HARCTANGENT
+ * @arg @ref LL_CORDIC_FUNCTION_NATURALLOG
+ * @arg @ref LL_CORDIC_FUNCTION_SQUAREROOT
+ * @param Precision parameter can be one of the following values:
+ * @arg @ref LL_CORDIC_PRECISION_1CYCLE
+ * @arg @ref LL_CORDIC_PRECISION_2CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_3CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_4CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_5CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_6CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_7CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_8CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_9CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_10CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_11CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_12CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_13CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_14CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_15CYCLES
+ * @param Scale parameter can be one of the following values:
+ * @arg @ref LL_CORDIC_SCALE_0
+ * @arg @ref LL_CORDIC_SCALE_1
+ * @arg @ref LL_CORDIC_SCALE_2
+ * @arg @ref LL_CORDIC_SCALE_3
+ * @arg @ref LL_CORDIC_SCALE_4
+ * @arg @ref LL_CORDIC_SCALE_5
+ * @arg @ref LL_CORDIC_SCALE_6
+ * @arg @ref LL_CORDIC_SCALE_7
+ * @param NbWrite parameter can be one of the following values:
+ * @arg @ref LL_CORDIC_NBWRITE_1
+ * @arg @ref LL_CORDIC_NBWRITE_2
+ * @param NbRead parameter can be one of the following values:
+ * @arg @ref LL_CORDIC_NBREAD_1
+ * @arg @ref LL_CORDIC_NBREAD_2
+ * @param InSize parameter can be one of the following values:
+ * @arg @ref LL_CORDIC_INSIZE_32BITS
+ * @arg @ref LL_CORDIC_INSIZE_16BITS
+ * @param OutSize parameter can be one of the following values:
+ * @arg @ref LL_CORDIC_OUTSIZE_32BITS
+ * @arg @ref LL_CORDIC_OUTSIZE_16BITS
+ * @retval None
+ */
+__STATIC_INLINE void LL_CORDIC_Config(CORDIC_TypeDef *CORDICx, uint32_t Function, uint32_t Precision, uint32_t Scale,
+ uint32_t NbWrite, uint32_t NbRead, uint32_t InSize, uint32_t OutSize)
+{
+ MODIFY_REG(CORDICx->CSR,
+ CORDIC_CSR_FUNC | CORDIC_CSR_PRECISION | CORDIC_CSR_SCALE |
+ CORDIC_CSR_NARGS | CORDIC_CSR_NRES | CORDIC_CSR_ARGSIZE | CORDIC_CSR_RESSIZE,
+ Function | Precision | Scale |
+ NbWrite | NbRead | InSize | OutSize);
+}
+
+/**
+ * @brief Configure function.
+ * @rmtoll CSR FUNC LL_CORDIC_SetFunction
+ * @param CORDICx CORDIC Instance
+ * @param Function parameter can be one of the following values:
+ * @arg @ref LL_CORDIC_FUNCTION_COSINE
+ * @arg @ref LL_CORDIC_FUNCTION_SINE
+ * @arg @ref LL_CORDIC_FUNCTION_PHASE
+ * @arg @ref LL_CORDIC_FUNCTION_MODULUS
+ * @arg @ref LL_CORDIC_FUNCTION_ARCTANGENT
+ * @arg @ref LL_CORDIC_FUNCTION_HCOSINE
+ * @arg @ref LL_CORDIC_FUNCTION_HSINE
+ * @arg @ref LL_CORDIC_FUNCTION_HARCTANGENT
+ * @arg @ref LL_CORDIC_FUNCTION_NATURALLOG
+ * @arg @ref LL_CORDIC_FUNCTION_SQUAREROOT
+ * @retval None
+ */
+__STATIC_INLINE void LL_CORDIC_SetFunction(CORDIC_TypeDef *CORDICx, uint32_t Function)
+{
+ MODIFY_REG(CORDICx->CSR, CORDIC_CSR_FUNC, Function);
+}
+
+/**
+ * @brief Return function.
+ * @rmtoll CSR FUNC LL_CORDIC_GetFunction
+ * @param CORDICx CORDIC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_CORDIC_FUNCTION_COSINE
+ * @arg @ref LL_CORDIC_FUNCTION_SINE
+ * @arg @ref LL_CORDIC_FUNCTION_PHASE
+ * @arg @ref LL_CORDIC_FUNCTION_MODULUS
+ * @arg @ref LL_CORDIC_FUNCTION_ARCTANGENT
+ * @arg @ref LL_CORDIC_FUNCTION_HCOSINE
+ * @arg @ref LL_CORDIC_FUNCTION_HSINE
+ * @arg @ref LL_CORDIC_FUNCTION_HARCTANGENT
+ * @arg @ref LL_CORDIC_FUNCTION_NATURALLOG
+ * @arg @ref LL_CORDIC_FUNCTION_SQUAREROOT
+ */
+__STATIC_INLINE uint32_t LL_CORDIC_GetFunction(CORDIC_TypeDef *CORDICx)
+{
+ return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_FUNC));
+}
+
+/**
+ * @brief Configure precision in cycles number.
+ * @rmtoll CSR PRECISION LL_CORDIC_SetPrecision
+ * @param CORDICx CORDIC Instance
+ * @param Precision parameter can be one of the following values:
+ * @arg @ref LL_CORDIC_PRECISION_1CYCLE
+ * @arg @ref LL_CORDIC_PRECISION_2CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_3CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_4CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_5CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_6CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_7CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_8CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_9CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_10CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_11CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_12CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_13CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_14CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_15CYCLES
+ * @retval None
+ */
+__STATIC_INLINE void LL_CORDIC_SetPrecision(CORDIC_TypeDef *CORDICx, uint32_t Precision)
+{
+ MODIFY_REG(CORDICx->CSR, CORDIC_CSR_PRECISION, Precision);
+}
+
+/**
+ * @brief Return precision in cycles number.
+ * @rmtoll CSR PRECISION LL_CORDIC_GetPrecision
+ * @param CORDICx CORDIC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_CORDIC_PRECISION_1CYCLE
+ * @arg @ref LL_CORDIC_PRECISION_2CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_3CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_4CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_5CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_6CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_7CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_8CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_9CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_10CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_11CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_12CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_13CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_14CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_15CYCLES
+ */
+__STATIC_INLINE uint32_t LL_CORDIC_GetPrecision(CORDIC_TypeDef *CORDICx)
+{
+ return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_PRECISION));
+}
+
+/**
+ * @brief Configure scaling factor.
+ * @rmtoll CSR SCALE LL_CORDIC_SetScale
+ * @param CORDICx CORDIC Instance
+ * @param Scale parameter can be one of the following values:
+ * @arg @ref LL_CORDIC_SCALE_0
+ * @arg @ref LL_CORDIC_SCALE_1
+ * @arg @ref LL_CORDIC_SCALE_2
+ * @arg @ref LL_CORDIC_SCALE_3
+ * @arg @ref LL_CORDIC_SCALE_4
+ * @arg @ref LL_CORDIC_SCALE_5
+ * @arg @ref LL_CORDIC_SCALE_6
+ * @arg @ref LL_CORDIC_SCALE_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_CORDIC_SetScale(CORDIC_TypeDef *CORDICx, uint32_t Scale)
+{
+ MODIFY_REG(CORDICx->CSR, CORDIC_CSR_SCALE, Scale);
+}
+
+/**
+ * @brief Return scaling factor.
+ * @rmtoll CSR SCALE LL_CORDIC_GetScale
+ * @param CORDICx CORDIC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_CORDIC_SCALE_0
+ * @arg @ref LL_CORDIC_SCALE_1
+ * @arg @ref LL_CORDIC_SCALE_2
+ * @arg @ref LL_CORDIC_SCALE_3
+ * @arg @ref LL_CORDIC_SCALE_4
+ * @arg @ref LL_CORDIC_SCALE_5
+ * @arg @ref LL_CORDIC_SCALE_6
+ * @arg @ref LL_CORDIC_SCALE_7
+ */
+__STATIC_INLINE uint32_t LL_CORDIC_GetScale(CORDIC_TypeDef *CORDICx)
+{
+ return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_SCALE));
+}
+
+/**
+ * @brief Configure number of 32-bit write expected for one calculation.
+ * @rmtoll CSR NARGS LL_CORDIC_SetNbWrite
+ * @param CORDICx CORDIC Instance
+ * @param NbWrite parameter can be one of the following values:
+ * @arg @ref LL_CORDIC_NBWRITE_1
+ * @arg @ref LL_CORDIC_NBWRITE_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_CORDIC_SetNbWrite(CORDIC_TypeDef *CORDICx, uint32_t NbWrite)
+{
+ MODIFY_REG(CORDICx->CSR, CORDIC_CSR_NARGS, NbWrite);
+}
+
+/**
+ * @brief Return number of 32-bit write expected for one calculation.
+ * @rmtoll CSR NARGS LL_CORDIC_GetNbWrite
+ * @param CORDICx CORDIC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_CORDIC_NBWRITE_1
+ * @arg @ref LL_CORDIC_NBWRITE_2
+ */
+__STATIC_INLINE uint32_t LL_CORDIC_GetNbWrite(CORDIC_TypeDef *CORDICx)
+{
+ return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_NARGS));
+}
+
+/**
+ * @brief Configure number of 32-bit read expected after one calculation.
+ * @rmtoll CSR NRES LL_CORDIC_SetNbRead
+ * @param CORDICx CORDIC Instance
+ * @param NbRead parameter can be one of the following values:
+ * @arg @ref LL_CORDIC_NBREAD_1
+ * @arg @ref LL_CORDIC_NBREAD_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_CORDIC_SetNbRead(CORDIC_TypeDef *CORDICx, uint32_t NbRead)
+{
+ MODIFY_REG(CORDICx->CSR, CORDIC_CSR_NRES, NbRead);
+}
+
+/**
+ * @brief Return number of 32-bit read expected after one calculation.
+ * @rmtoll CSR NRES LL_CORDIC_GetNbRead
+ * @param CORDICx CORDIC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_CORDIC_NBREAD_1
+ * @arg @ref LL_CORDIC_NBREAD_2
+ */
+__STATIC_INLINE uint32_t LL_CORDIC_GetNbRead(CORDIC_TypeDef *CORDICx)
+{
+ return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_NRES));
+}
+
+/**
+ * @brief Configure width of input data.
+ * @rmtoll CSR ARGSIZE LL_CORDIC_SetInSize
+ * @param CORDICx CORDIC Instance
+ * @param InSize parameter can be one of the following values:
+ * @arg @ref LL_CORDIC_INSIZE_32BITS
+ * @arg @ref LL_CORDIC_INSIZE_16BITS
+ * @retval None
+ */
+__STATIC_INLINE void LL_CORDIC_SetInSize(CORDIC_TypeDef *CORDICx, uint32_t InSize)
+{
+ MODIFY_REG(CORDICx->CSR, CORDIC_CSR_ARGSIZE, InSize);
+}
+
+/**
+ * @brief Return width of input data.
+ * @rmtoll CSR ARGSIZE LL_CORDIC_GetInSize
+ * @param CORDICx CORDIC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_CORDIC_INSIZE_32BITS
+ * @arg @ref LL_CORDIC_INSIZE_16BITS
+ */
+__STATIC_INLINE uint32_t LL_CORDIC_GetInSize(CORDIC_TypeDef *CORDICx)
+{
+ return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_ARGSIZE));
+}
+
+/**
+ * @brief Configure width of output data.
+ * @rmtoll CSR RESIZE LL_CORDIC_SetOutSize
+ * @param CORDICx CORDIC Instance
+ * @param OutSize parameter can be one of the following values:
+ * @arg @ref LL_CORDIC_OUTSIZE_32BITS
+ * @arg @ref LL_CORDIC_OUTSIZE_16BITS
+ * @retval None
+ */
+__STATIC_INLINE void LL_CORDIC_SetOutSize(CORDIC_TypeDef *CORDICx, uint32_t OutSize)
+{
+ MODIFY_REG(CORDICx->CSR, CORDIC_CSR_RESSIZE, OutSize);
+}
+
+/**
+ * @brief Return width of output data.
+ * @rmtoll CSR RESIZE LL_CORDIC_GetOutSize
+ * @param CORDICx CORDIC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_CORDIC_OUTSIZE_32BITS
+ * @arg @ref LL_CORDIC_OUTSIZE_16BITS
+ */
+__STATIC_INLINE uint32_t LL_CORDIC_GetOutSize(CORDIC_TypeDef *CORDICx)
+{
+ return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_RESSIZE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable CORDIC result ready interrupt
+ * @rmtoll CSR IEN LL_CORDIC_EnableIT
+ * @param CORDICx CORDIC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_CORDIC_EnableIT(CORDIC_TypeDef *CORDICx)
+{
+ SET_BIT(CORDICx->CSR, CORDIC_CSR_IEN);
+}
+
+/**
+ * @brief Disable CORDIC result ready interrupt
+ * @rmtoll CSR IEN LL_CORDIC_DisableIT
+ * @param CORDICx CORDIC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_CORDIC_DisableIT(CORDIC_TypeDef *CORDICx)
+{
+ CLEAR_BIT(CORDICx->CSR, CORDIC_CSR_IEN);
+}
+
+/**
+ * @brief Check CORDIC result ready interrupt state.
+ * @rmtoll CSR IEN LL_CORDIC_IsEnabledIT
+ * @param CORDICx CORDIC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledIT(CORDIC_TypeDef *CORDICx)
+{
+ return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_IEN) == (CORDIC_CSR_IEN)) ? 1U : 0U);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_LL_EF_DMA_Management DMA_Management
+ * @{
+ */
+
+/**
+ * @brief Enable CORDIC DMA read channel request.
+ * @rmtoll CSR DMAREN LL_CORDIC_EnableDMAReq_RD
+ * @param CORDICx CORDIC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_CORDIC_EnableDMAReq_RD(CORDIC_TypeDef *CORDICx)
+{
+ SET_BIT(CORDICx->CSR, CORDIC_CSR_DMAREN);
+}
+
+/**
+ * @brief Disable CORDIC DMA read channel request.
+ * @rmtoll CSR DMAREN LL_CORDIC_DisableDMAReq_RD
+ * @param CORDICx CORDIC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_CORDIC_DisableDMAReq_RD(CORDIC_TypeDef *CORDICx)
+{
+ CLEAR_BIT(CORDICx->CSR, CORDIC_CSR_DMAREN);
+}
+
+/**
+ * @brief Check CORDIC DMA read channel request state.
+ * @rmtoll CSR DMAREN LL_CORDIC_IsEnabledDMAReq_RD
+ * @param CORDICx CORDIC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledDMAReq_RD(CORDIC_TypeDef *CORDICx)
+{
+ return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_DMAREN) == (CORDIC_CSR_DMAREN)) ? 1U : 0U);
+}
+
+/**
+ * @brief Enable CORDIC DMA write channel request.
+ * @rmtoll CSR DMAWEN LL_CORDIC_EnableDMAReq_WR
+ * @param CORDICx CORDIC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_CORDIC_EnableDMAReq_WR(CORDIC_TypeDef *CORDICx)
+{
+ SET_BIT(CORDICx->CSR, CORDIC_CSR_DMAWEN);
+}
+
+/**
+ * @brief Disable CORDIC DMA write channel request.
+ * @rmtoll CSR DMAWEN LL_CORDIC_DisableDMAReq_WR
+ * @param CORDICx CORDIC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_CORDIC_DisableDMAReq_WR(CORDIC_TypeDef *CORDICx)
+{
+ CLEAR_BIT(CORDICx->CSR, CORDIC_CSR_DMAWEN);
+}
+
+/**
+ * @brief Check CORDIC DMA write channel request state.
+ * @rmtoll CSR DMAWEN LL_CORDIC_IsEnabledDMAReq_WR
+ * @param CORDICx CORDIC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledDMAReq_WR(CORDIC_TypeDef *CORDICx)
+{
+ return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_DMAWEN) == (CORDIC_CSR_DMAWEN)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get the CORDIC data register address used for DMA transfer.
+ * @rmtoll RDATA RES LL_CORDIC_DMA_GetRegAddr\n
+ * @rmtoll WDATA ARG LL_CORDIC_DMA_GetRegAddr
+ * @param CORDICx CORDIC Instance
+ * @param Direction parameter can be one of the following values:
+ * @arg @ref LL_CORDIC_DMA_REG_DATA_IN
+ * @arg @ref LL_CORDIC_DMA_REG_DATA_OUT
+ * @retval Address of data register
+ */
+__STATIC_INLINE uint32_t LL_CORDIC_DMA_GetRegAddr(CORDIC_TypeDef *CORDICx, uint32_t Direction)
+{
+ uint32_t data_reg_addr;
+
+ if (Direction == LL_CORDIC_DMA_REG_DATA_OUT)
+ {
+ /* return address of RDATA register */
+ data_reg_addr = (uint32_t) &(CORDICx->RDATA);
+ }
+ else
+ {
+ /* return address of WDATA register */
+ data_reg_addr = (uint32_t) &(CORDICx->WDATA);
+ }
+
+ return data_reg_addr;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Check CORDIC result ready flag state.
+ * @rmtoll CSR RRDY LL_CORDIC_IsActiveFlag_RRDY
+ * @param CORDICx CORDIC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CORDIC_IsActiveFlag_RRDY(CORDIC_TypeDef *CORDICx)
+{
+ return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_RRDY) == (CORDIC_CSR_RRDY)) ? 1U : 0U);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_LL_EF_Data_Management Data_Management
+ * @{
+ */
+
+/**
+ * @brief Write 32-bit input data for the CORDIC processing.
+ * @rmtoll WDATA ARG LL_CORDIC_WriteData
+ * @param CORDICx CORDIC Instance
+ * @param InData 0 .. 0xFFFFFFFF : 32-bit value to be provided as input data for CORDIC processing.
+ * @retval None
+ */
+__STATIC_INLINE void LL_CORDIC_WriteData(CORDIC_TypeDef *CORDICx, uint32_t InData)
+{
+ WRITE_REG(CORDICx->WDATA, InData);
+}
+
+/**
+ * @brief Return 32-bit output data of CORDIC processing.
+ * @rmtoll RDATA RES LL_CORDIC_ReadData
+ * @param CORDICx CORDIC Instance
+ * @retval 32-bit output data of CORDIC processing.
+ */
+__STATIC_INLINE uint32_t LL_CORDIC_ReadData(CORDIC_TypeDef *CORDICx)
+{
+ return (uint32_t)(READ_REG(CORDICx->RDATA));
+}
+
+/**
+ * @}
+ */
+
+
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup CORDIC_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+ErrorStatus LL_CORDIC_DeInit(CORDIC_TypeDef *CORDICx);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(CORDIC) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_LL_CORDIC_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_cortex.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_cortex.h
new file mode 100644
index 00000000..51797948
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_cortex.h
@@ -0,0 +1,1270 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_cortex.h
+ * @author MCD Application Team
+ * @brief Header file of CORTEX LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The LL CORTEX driver contains a set of generic APIs that can be
+ used by user:
+ (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
+ functions
+ (+) Low power mode configuration (SCB register of Cortex-MCU)
+ (+) API to access to MCU info (CPUID register)
+ (+) API to enable fault handler (SHCSR accesses)
+ (+) API to enable and disable the MPU secure and non-secure
+ (+) API to configure the region of MPU secure and non-secure
+ (+) API to configure the attributes region of MPU secure and non-secure
+
+ @endverbatim
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_LL_CORTEX_H
+#define STM32U5xx_LL_CORTEX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx.h"
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup CORTEX_LL CORTEX
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Exported_Constants CORTEX LL Exported Constants
+ * @{
+ */
+
+/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
+ * @{
+ */
+#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick
+ clock source */
+#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick
+ clock source */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
+ * @{
+ */
+#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
+#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
+#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
+#define LL_HANDLER_FAULT_SECURE SCB_SHCSR_SECUREFAULTENA_Msk /*!< Secure fault */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_MPU_HFNMI_PRIVDEF_Control CORTEX LL MPU HFNMI and PRIVILEGED Access control
+ * @{
+ */
+#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0U
+#define LL_MPU_CTRL_HARDFAULT_NMI 2U
+#define LL_MPU_CTRL_PRIVILEGED_DEFAULT 4U
+#define LL_MPU_CTRL_HFNMI_PRIVDEF 6U
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_MPU_Attributes CORTEX LL MPU Attributes
+ * @{
+ */
+#define LL_MPU_DEVICE_nGnRnE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */
+#define LL_MPU_DEVICE_nGnRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */
+#define LL_MPU_DEVICE_nGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */
+#define LL_MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */
+
+#define LL_MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */
+#define LL_MPU_NOT_CACHEABLE 0x4U /* Normal memory, non-cacheable. */
+#define LL_MPU_WRITE_BACK 0x4U /* Normal memory, write-back. */
+
+#define LL_MPU_TRANSIENT 0x0U /* Normal memory, transient. */
+#define LL_MPU_NON_TRANSIENT 0x8U /* Normal memory, non-transient. */
+
+#define LL_MPU_NO_ALLOCATE 0x0U /* Normal memory, no allocate. */
+#define LL_MPU_W_ALLOCATE 0x1U /* Normal memory, write allocate. */
+#define LL_MPU_R_ALLOCATE 0x2U /* Normal memory, read allocate. */
+#define LL_MPU_RW_ALLOCATE 0x3U /* Normal memory, read/write allocate. */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_MPU_Region_Enable CORTEX LL MPU Region Enable
+ * @{
+ */
+#define LL_MPU_REGION_ENABLE 1U
+#define LL_MPU_REGION_DISABLE 0U
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_MPU_Instruction_Access CORTEX LL MPU Instruction Access
+ * @{
+ */
+#define LL_MPU_INSTRUCTION_ACCESS_ENABLE (0U << MPU_RBAR_XN_Pos)
+#define LL_MPU_INSTRUCTION_ACCESS_DISABLE (1U << MPU_RBAR_XN_Pos)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_MPU_Access_Shareable CORTEX LL MPU Instruction Access Shareable
+ * @{
+ */
+#define LL_MPU_ACCESS_NOT_SHAREABLE (0U << MPU_RBAR_SH_Pos)
+#define LL_MPU_ACCESS_OUTER_SHAREABLE (1U << MPU_RBAR_SH_Pos)
+#define LL_MPU_ACCESS_INNER_SHAREABLE (3U << MPU_RBAR_SH_Pos)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_MPU_Region_Permission_Attributes CORTEX LL MPU Region Permission Attributes
+ * @{
+ */
+#define LL_MPU_REGION_PRIV_RW (0U << MPU_RBAR_AP_Pos)
+#define LL_MPU_REGION_ALL_RW (1U << MPU_RBAR_AP_Pos)
+#define LL_MPU_REGION_PRIV_RO (2U << MPU_RBAR_AP_Pos)
+#define LL_MPU_REGION_ALL_RO (3U << MPU_RBAR_AP_Pos)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_MPU_Region_Index CORTEX LL MPU Region Index
+ * @{
+ */
+#define LL_MPU_REGION_NUMBER0 0U
+#define LL_MPU_REGION_NUMBER1 1U
+#define LL_MPU_REGION_NUMBER2 2U
+#define LL_MPU_REGION_NUMBER3 3U
+#define LL_MPU_REGION_NUMBER4 4U
+#define LL_MPU_REGION_NUMBER5 5U
+#define LL_MPU_REGION_NUMBER6 6U
+#define LL_MPU_REGION_NUMBER7 7U
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_MPU_Attributes_Index CORTEX LL MPU Memory Attributes Index
+ * @{
+ */
+#define LL_MPU_ATTRIBUTES_NUMBER0 0U
+#define LL_MPU_ATTRIBUTES_NUMBER1 1U
+#define LL_MPU_ATTRIBUTES_NUMBER2 2U
+#define LL_MPU_ATTRIBUTES_NUMBER3 3U
+#define LL_MPU_ATTRIBUTES_NUMBER4 4U
+#define LL_MPU_ATTRIBUTES_NUMBER5 5U
+#define LL_MPU_ATTRIBUTES_NUMBER6 6U
+#define LL_MPU_ATTRIBUTES_NUMBER7 7U
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Exported_Functions CORTEX LL Exported Functions
+ * @{
+ */
+
+/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
+ * @brief CORTEX SYSTICK LL module driver
+ * @{
+ */
+
+/**
+ * @brief This function checks if the Systick counter flag is active or not.
+ * @note It can be used in timeout function on application side.
+ * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
+{
+ return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configures the SysTick clock source
+ * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
+ * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
+{
+ if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
+ {
+ SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+ }
+ else
+ {
+ CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+ }
+}
+
+/**
+ * @brief Get the SysTick clock source
+ * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
+ * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
+ */
+__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
+{
+ return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+}
+
+/**
+ * @brief Enable SysTick exception request
+ * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
+{
+ SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+ * @brief Disable SysTick exception request
+ * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
+{
+ CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+ * @brief Checks if the SYSTICK interrupt is enabled or disabled.
+ * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
+{
+ return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE CORTEX LL LOW POWER MODE
+ * @{
+ */
+
+/**
+ * @brief Processor uses sleep as its low power mode
+ * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_EnableSleep(void)
+{
+ /* Clear SLEEPDEEP bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+/**
+ * @brief Processor uses deep sleep as its low power mode
+ * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
+{
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+/**
+ * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
+ * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
+ * empty main application.
+ * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
+{
+ /* Set SLEEPONEXIT bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+ * @brief Do not sleep when returning to Thread mode.
+ * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
+{
+ /* Clear SLEEPONEXIT bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+ * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
+ * processor.
+ * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
+{
+ /* Set SEVEONPEND bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+ * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
+ * excluded
+ * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
+{
+ /* Clear SEVEONPEND bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EF_HANDLER CORTEX LL HANDLER
+ * @{
+ */
+
+/**
+ * @brief Enable a fault in System handler control register (SHCSR)
+ * @rmtoll SCB_SHCSR USGFAULTENA LL_HANDLER_EnableFault\n
+ * SCB_SHCSR BUSFAULTENA LL_HANDLER_EnableFault\n
+ * SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault\n
+ * SCB_SHCSR SECUREFAULTENA LL_HANDLER_EnableFault
+ * @param Fault This parameter can be a combination of the following values:
+ * @arg @ref LL_HANDLER_FAULT_USG
+ * @arg @ref LL_HANDLER_FAULT_BUS
+ * @arg @ref LL_HANDLER_FAULT_MEM
+ * @arg @ref LL_HANDLER_FAULT_SECURE (*)
+ *
+ * (*) value applicable in secure when the system implements the security.
+ * @retval None
+ */
+__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
+{
+ /* Enable the system handler fault */
+ SET_BIT(SCB->SHCSR, Fault);
+}
+
+/**
+ * @brief Disable a fault in System handler control register (SHCSR)
+ * @rmtoll SCB_SHCSR USGFAULTENA LL_HANDLER_DisableFault\n
+ * SCB_SHCSR BUSFAULTENA LL_HANDLER_DisableFault\n
+ * SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault\n
+ * SCB_SHCSR SECUREFAULTENA LL_HANDLER_DisableFault
+ * @param Fault This parameter can be a combination of the following values:
+ * @arg @ref LL_HANDLER_FAULT_USG
+ * @arg @ref LL_HANDLER_FAULT_BUS
+ * @arg @ref LL_HANDLER_FAULT_MEM
+ * @arg @ref LL_HANDLER_FAULT_SECURE (*)
+ *
+ * (*) value applicable in secure when the system implements the security.
+ * @retval None
+ */
+__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
+{
+ /* Disable the system handler fault */
+ CLEAR_BIT(SCB->SHCSR, Fault);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EF_MCU_INFO CORTEX LL MCU INFO
+ * @{
+ */
+
+/**
+ * @brief Get Implementer code
+ * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
+ * @retval Value should be equal to 0x41 for ARM
+ */
+__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
+{
+ return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
+}
+
+/**
+ * @brief Get Variant number (The r value in the rnpn product revision identifier)
+ * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
+ * @retval Value between 0 and 255 (0x0: revision 0)
+ */
+__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
+{
+ return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
+}
+
+/**
+ * @brief Get Constant number
+ * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
+ * @retval Value should be equal to 0xF for Cortex-M33 devices
+ */
+__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
+{
+ return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
+}
+
+/**
+ * @brief Get Part number
+ * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
+ * @retval Value should be equal to 0xD21 for Cortex-M33
+ */
+__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
+{
+ return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
+}
+
+/**
+ * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
+ * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
+ * @retval Value between 0 and 255 (0x1: patch 1)
+ */
+__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
+{
+ return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EF_MPU CORTEX LL MPU
+ * @{
+ */
+
+/**
+ * @brief Enable MPU with input options
+ * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
+ * @param MPU_Control This parameter can be one of the following values:
+ * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
+ * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
+ * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
+ * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_Enable(uint32_t MPU_Control)
+{
+ /* Enable the MPU*/
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control;
+
+ /* Ensure MPU settings take effects */
+ __DSB();
+
+ /* Sequence instruction fetches using update settings */
+ __ISB();
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ * @brief Enable non-secure MPU with input options
+ * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
+ * @param MPU_Control This parameter can be one of the following values:
+ * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
+ * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
+ * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
+ * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_Enable_NS(uint32_t MPU_Control)
+{
+ /* Enable the MPU*/
+ MPU_NS->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control;
+
+ /* Ensure MPU settings take effects */
+ __DSB();
+
+ /* Sequence instruction fetches using update settings */
+ __ISB();
+}
+#endif /* __ARM_FEATURE_CMSE */
+
+/**
+ * @brief Disable MPU
+ * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_Disable(void)
+{
+ /* Make sure outstanding transfers are done */
+ __DMB();
+ /* Disable MPU*/
+ WRITE_REG(MPU->CTRL, 0U);
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ * @brief Disable the non-secure MPU
+ * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable_NS
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_Disable_NS(void)
+{
+ /* Make sure outstanding transfers are done */
+ __DMB();
+ /* Disable MPU*/
+ WRITE_REG(MPU_NS->CTRL, 0U);
+}
+#endif /* __ARM_FEATURE_CMSE */
+
+
+/**
+ * @brief Check if MPU is enabled or not
+ * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
+{
+ return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ * @brief Check if non-secure MPU is enabled or not
+ * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled_NS
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_MPU_IsEnabled_NS(void)
+{
+ return ((READ_BIT(MPU_NS->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
+}
+#endif /* __ARM_FEATURE_CMSE */
+
+/**
+ * @brief Enable a MPU region
+ * @rmtoll MPU_RLAR ENABLE LL_MPU_EnableRegion
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @note cortex-M33 supports 8 secure and 8 non secure regions.
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
+{
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+
+ /* Enable the MPU region */
+ SET_BIT(MPU->RLAR, MPU_RLAR_EN_Msk);
+}
+
+/**
+ * @brief Check if MPU region is enabled or not
+ * @rmtoll MPU_RNR ENABLE LL_MPU_IsEnabledRegion
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @note cortex-M33 supports 8 secure and 8 non secure regions.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_MPU_IsEnabled_Region(uint32_t Region)
+{
+ return ((READ_BIT(MPU->RNR, Region) == (Region)) ? 1UL : 0UL);
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ * @brief Enable a non-secure MPU region
+ * @rmtoll MPU_RLAR ENABLE LL_MPU_EnableRegion_NS
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @note cortex-M33 supports 8 secure and 8 non secure regions.
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_EnableRegion_NS(uint32_t Region)
+{
+ /* Set Region number */
+ WRITE_REG(MPU_NS->RNR, Region);
+
+ /* Enable the MPU region */
+ SET_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk);
+}
+
+/**
+ * @brief Check if non-secure MPU region is enabled or not
+ * @rmtoll MPU_RNR ENABLE LL_MPU_IsEnableRegion_NS
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @note cortex-M33 supports 8 secure and 8 non secure regions.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_MPU_IsEnabled_Region_NS(uint32_t Region)
+{
+ return ((READ_BIT(MPU_NS->RNR, Region) == (Region)) ? 1UL : 0UL);
+}
+#endif /* __ARM_FEATURE_CMSE */
+
+/**
+ * @brief Disable a MPU region
+ * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
+ * MPU_RLAR ENABLE LL_MPU_DisableRegion
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @note cortex-M33 supports 8 secure and 8 non secure regions.
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
+{
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+
+ /* Disable the MPU region */
+ CLEAR_BIT(MPU->RLAR, MPU_RLAR_EN_Msk);
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ * @brief Disable a non-secure MPU region
+ * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion_NS\n
+ * MPU_RLAR ENABLE LL_MPU_DisableRegion_NS\n
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @note cortex-M33 supports 8 secure and 8 non secure regions.
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_DisableRegion_NS(uint32_t Region)
+{
+ /* Set Region number */
+ WRITE_REG(MPU_NS->RNR, Region);
+
+ /* Disable the MPU region */
+ CLEAR_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk);
+}
+#endif /* __ARM_FEATURE_CMSE */
+
+/**
+ * @brief Configure and enable a MPU region
+ * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
+ * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
+ * MPU_RLAR ADDR LL_MPU_ConfigRegion\n
+ * MPU_RBAR XN LL_MPU_ConfigRegion\n
+ * MPU_RBAR AP LL_MPU_ConfigRegion\n
+ * MPU_RBAR SH LL_MPU_ConfigRegion\n
+ * MPU_RLAR EN LL_MPU_ConfigRegion\n
+ * MPU_RLAR AttrIndx LL_MPU_ConfigRegion\n
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @param Attributes This parameter can be a combination of the following values:
+ * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
+ * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
+ * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
+ * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
+ * or @ref LL_MPU_REGION_ALL_RO
+ * @param AttrIndx This parameter can be one of the following values:
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
+ * @param BaseAddress Value of region base address
+ * @param LimitAddress Value of region limit address
+ * @note cortex-M33 supports 8 secure and 8 non secure regions.
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx, uint32_t BaseAddress,
+ uint32_t LimitAddress)
+{
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+
+ /* Set base address */
+ MPU->RBAR |= Attributes;
+ /* Set base address */
+ MPU->RBAR |= (BaseAddress & 0xFFFFFFE0U);
+
+ /* Set limit address */
+ MPU->RLAR |= (LimitAddress & 0xFFFFFFE0U);
+ /* Configure MPU */
+ MPU->RLAR |= (MPU_RLAR_EN_Msk | AttrIndx);
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ * @brief Configure and enable a non-secure MPU region
+ * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion_NS\n
+ * MPU_RBAR ADDR LL_MPU_ConfigRegion_NS\n
+ * MPU_RLAR ADDR LL_MPU_ConfigRegion_NS\n
+ * MPU_RBAR XN LL_MPU_ConfigRegion_NS\n
+ * MPU_RBAR AP LL_MPU_ConfigRegion_NS\n
+ * MPU_RBAR SH LL_MPU_ConfigRegion_NS\n
+ * MPU_RLAR EN LL_MPU_ConfigRegion_NS\n
+ * MPU_RLAR AttrIndx LL_MPU_ConfigRegion_NS\n
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @param Attributes This parameter can be a combination of the following values:
+ * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
+ * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
+ * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
+ * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
+ * or @ref LL_MPU_REGION_ALL_RO
+ * @param AttrIndx This parameter can be one of the following values:
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
+ * @param BaseAddress Value of region base address
+ * @param LimitAddress Value of region limit address
+ * @note cortex-M33 supports 8 secure and 8 non secure regions.
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_ConfigRegion_NS(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx,
+ uint32_t BaseAddress, uint32_t LimitAddress)
+{
+ /* Set Region number */
+ WRITE_REG(MPU_NS->RNR, Region);
+
+ /* Set base address */
+ MPU_NS->RBAR |= Attributes;
+
+ /* Set base address */
+ MPU_NS->RBAR |= (BaseAddress & 0xFFFFFFE0U);
+
+ /* Set limit address */
+ MPU_NS->RLAR |= (LimitAddress & 0xFFFFFFE0U);
+ /* Configure MPU */
+ MPU_NS->RLAR |= (MPU_RLAR_EN_Msk | AttrIndx);
+}
+#endif /* __ARM_FEATURE_CMSE */
+
+/**
+ * @brief Configure a MPU region address range
+ * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegionAddress\n
+ * MPU_RBAR ADDR LL_MPU_ConfigRegionAddress\n
+ * MPU_RLAR ADDR LL_MPU_ConfigRegionAddress\n
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @param BaseAddress Value of region base address
+ * @param LimitAddress Value of region limit address
+ * @note cortex-M33 supports 8 secure and 8 non secure regions.
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_ConfigRegionAddress(uint32_t Region, uint32_t BaseAddress, uint32_t LimitAddress)
+{
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+ /* Set base address */
+ MPU->RBAR |= (BaseAddress & 0xFFFFFFE0U) ;
+
+ /* Set limit address */
+ MPU->RLAR |= (LimitAddress & 0xFFFFFFE0U);
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ * @brief Configure a non-secure MPU region address range
+ * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegionAddress_NS\n
+ * MPU_RBAR ADDR LL_MPU_ConfigRegionAddress_NS\n
+ * MPU_RLAR ADDR LL_MPU_ConfigRegionAddress_NS\n
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @param BaseAddress Value of region base address
+ * @param LimitAddress Value of region limit address
+ * @note cortex-M33 supports 8 secure and 8 non secure regions.
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_ConfigRegionAddress_NS(uint32_t Region, uint32_t BaseAddress, uint32_t LimitAddress)
+{
+ /* Set Region number */
+ WRITE_REG(MPU_NS->RNR, Region);
+ /* Set base address */
+ MPU_NS->RBAR |= (BaseAddress & 0xFFFFFFE0U);
+
+ /* Set limit address */
+ MPU_NS->RLAR |= (LimitAddress & 0xFFFFFFE0U);
+}
+#endif /* __ARM_FEATURE_CMSE */
+
+/**
+ * @brief Configure a MPU attributes index
+ * @rmtoll MPU_MAIR0 Attribute LL_MPU_ConfigAttributes\n
+ * MPU_MAIR1 Attribute LL_MPU_ConfigAttributes\n
+ * @param AttIndex This parameter can be one of the following values:
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
+ * @param Attributes This parameter can be a combination of @ref CORTEX_LL_MPU_Attributes
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_ConfigAttributes(uint32_t AttIndex, uint32_t Attributes)
+{
+ if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4)
+ {
+ /* Program MPU_MAIR0 */
+ WRITE_REG(MPU->MAIR0, (Attributes << (AttIndex * 8U)));
+ }
+ else
+ {
+ /* Program MPU_MAIR1 */
+ WRITE_REG(MPU->MAIR1, (Attributes << ((AttIndex - 4U) * 8U)));
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ * @brief Configure a non-secure MPU attributes index
+ * @rmtoll MPU_MAIR0 Attribute LL_MPU_ConfigAttributes_NS\n
+ * MPU_MAIR1 Attribute LL_MPU_ConfigAttributes_NS\n
+ * @param AttIndex This parameter can be one of the following values:
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
+ * @param Attributes This parameter can be a combination of @ref CORTEX_LL_MPU_Attributes
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_ConfigAttributes_NS(uint32_t AttIndex, uint32_t Attributes)
+{
+ if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4)
+ {
+ /* Program MPU_MAIR0 */
+ WRITE_REG(MPU_NS->MAIR0, (Attributes << (AttIndex * 8U)));
+ }
+ else
+ {
+ /* Program MPU_MAIR1 */
+ WRITE_REG(MPU_NS->MAIR1, (Attributes << ((AttIndex - 4U) * 8U)));
+ }
+}
+#endif /* __ARM_FEATURE_CMSE */
+
+/**
+ * @brief Configure a MPU region limit address
+ * @rmtoll MPU_RNR REGION LL_MPU_SetRegionLimitAddress\n
+ * MPU_RLAR ADDR LL_MPU_SetRegionLimitAddress\n
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @param LimitAddress Value of region limit address
+ * @note cortex-M33 supports 8 secure and 8 non secure regions.
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_SetRegionLimitAddress(uint32_t Region, uint32_t LimitAddress)
+{
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+ /* Set limit address */
+ MPU->RLAR |= (LimitAddress & 0xFFFFFFE0U);
+}
+
+/**
+ * @brief Get a MPU region limit address
+ * @rmtoll MPU_RNR REGION LL_MPU_GetRegionLimitAddress\n
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress(uint32_t Region)
+{
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+ return (READ_REG(MPU->RLAR & MPU_RLAR_LIMIT_Msk));
+}
+
+/**
+ * @brief Configure a MPU region base address
+ * @rmtoll MPU_RNR REGION LL_MPU_SetRegionBaseAddress\n
+ * MPU_RBAR ADDR LL_MPU_SetRegionBaseAddress\n
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @param BaseAddress Value of region base address
+ * @note cortex-M33 supports 8 secure and 8 non secure regions.
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_SetRegionBaseAddress(uint32_t Region, uint32_t BaseAddress)
+{
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+ /* Set base address */
+ MPU->RBAR |= (BaseAddress & 0xFFFFFFE0U);
+}
+
+/**
+ * @brief Get a MPU region base address
+ * @rmtoll MPU_RNR REGION LL_MPU_GetRegionBaseAddress\n
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress(uint32_t Region)
+{
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+ return (READ_REG(MPU->RBAR & MPU_RBAR_BASE_Msk));
+}
+
+/**
+ * @brief Configure a MPU region access attributes and enable a region
+ * @rmtoll MPU_RNR REGION LL_MPU_SetRegionAccess\n
+ * MPU_RBAR XN LL_MPU_SetRegionAccess\n
+ * MPU_RBAR AP LL_MPU_SetRegionAccess\n
+ * MPU_RBAR SH LL_MPU_SetRegionAccess\n
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @param Attributes This parameter can be a combination of the following values:
+ * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
+ * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
+ * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
+ * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
+ * or @ref LL_MPU_REGION_ALL_RO
+ * @note cortex-M33 supports 8 secure and 8 non secure regions.
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_SetRegionAccess(uint32_t Region, uint32_t Attributes)
+{
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+ /* Set base address */
+ MPU->RBAR |= Attributes;
+}
+
+/**
+ * @brief Get a MPU region access attributes
+ * @rmtoll MPU_RNR REGION LL_MPU_GetRegionAccess\n
+ * MPU_RBAR XN LL_MPU_GetRegionAccess\n
+ * MPU_RBAR AP LL_MPU_GetRegionAccess\n
+ * MPU_RBAR SH LL_MPU_GetRegionAccess\n
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_MPU_GetRegionAccess(uint32_t Region)
+{
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+ return (READ_REG(MPU->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk)));
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ * @brief Configure a non-secure MPU region limit address
+ * @rmtoll MPU_RNR REGION LL_MPU_SetRegionLimitAddress_NS\n
+ * MPU_RLAR ADDR LL_MPU_SetRegionLimitAddress_NS\n
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @param LimitAddress Value of region limit address
+ * @note cortex-M33 supports 8 secure and 8 non secure regions.
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_SetRegionLimitAddress_NS(uint32_t Region, uint32_t LimitAddress)
+{
+ /* Set Region number */
+ WRITE_REG(MPU_NS->RNR, Region);
+ /* Set limit address */
+ MPU_NS->RLAR |= (LimitAddress & 0xFFFFFFE0U);
+}
+
+/**
+ * @brief Get a non-secure MPU region limit address
+ * @rmtoll MPU_RNR REGION LL_MPU_GetRegionLimitAddress_NS\n
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress_NS(uint32_t Region)
+{
+ /* Set Region number */
+ WRITE_REG(MPU_NS->RNR, Region);
+ return (READ_REG(MPU_NS->RLAR & MPU_RLAR_LIMIT_Msk));
+}
+
+/**
+ * @brief Configure a non-secure MPU region base address
+ * @rmtoll MPU_RNR REGION LL_MPU_SetRegionBaseAddress_NS\n
+ * MPU_RBAR ADDR LL_MPU_SetRegionBaseAddress_NS\n
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @param BaseAddress Value of region base address
+ * @note cortex-M33 supports 8 secure and 8 non secure regions.
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_SetRegionBaseAddress_NS(uint32_t Region, uint32_t BaseAddress)
+{
+ /* Set Region number */
+ WRITE_REG(MPU_NS->RNR, Region);
+ /* Set base address */
+ MPU_NS->RBAR |= (BaseAddress & 0xFFFFFFE0U);
+}
+
+/**
+ * @brief Get a non-secure MPU region base address
+ * @rmtoll MPU_RNR REGION LL_MPU_GetRegionBaseAddress_NS\n
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress_NS(uint32_t Region)
+{
+ /* Set Region number */
+ WRITE_REG(MPU_NS->RNR, Region);
+ return (READ_REG(MPU_NS->RBAR & MPU_RBAR_BASE_Msk));
+}
+
+/**
+ * @brief Configure a non-secure MPU region access attributes and enable a region
+ * @rmtoll MPU_RNR REGION LL_MPU_SetRegionAccess_NS\n
+ * MPU_RBAR XN LL_MPU_SetRegionAccess_NS\n
+ * MPU_RBAR AP LL_MPU_SetRegionAccess_NS\n
+ * MPU_RBAR SH LL_MPU_SetRegionAccess_NS\n
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @param Attributes This parameter can be a combination of the following values:
+ * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
+ * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
+ * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
+ * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
+ * or @ref LL_MPU_REGION_ALL_RO
+ * @note cortex-M33 supports 8 secure and 8 non secure regions.
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_SetRegionAccess_NS(uint32_t Region, uint32_t Attributes)
+{
+ /* Set Region number */
+ WRITE_REG(MPU_NS->RNR, Region);
+ /* Set base address Attributes */
+ MPU_NS->RBAR |= Attributes;
+}
+
+/**
+ * @brief Get a non-secure MPU region access attributes
+ * @rmtoll MPU_RNR REGION LL_MPU_GetRegionAccess_NS\n
+ * MPU_RBAR XN LL_MPU_GetRegionAccess_NS\n
+ * MPU_RBAR AP LL_MPU_GetRegionAccess_NS\n
+ * MPU_RBAR SH LL_MPU_GetRegionAccess_NS\n
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_MPU_GetRegionAccess_NS(uint32_t Region)
+{
+ /* Set Region number */
+ WRITE_REG(MPU_NS->RNR, Region);
+ return (READ_REG(MPU_NS->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk)));
+}
+#endif /* __ARM_FEATURE_CMSE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_LL_CORTEX_H */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_crc.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_crc.h
new file mode 100644
index 00000000..95fb5b36
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_crc.h
@@ -0,0 +1,461 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_crc.h
+ * @author MCD Application Team
+ * @brief Header file of CRC LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_LL_CRC_H
+#define STM32U5xx_LL_CRC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx.h"
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined(CRC)
+
+/** @defgroup CRC_LL CRC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRC_LL_Exported_Constants CRC Exported Constants
+ * @{
+ */
+
+/** @defgroup CRC_LL_EC_POLYLENGTH Polynomial length
+ * @{
+ */
+#define LL_CRC_POLYLENGTH_32B 0x00000000U /*!< 32 bits Polynomial size */
+#define LL_CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< 16 bits Polynomial size */
+#define LL_CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< 8 bits Polynomial size */
+#define LL_CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0) /*!< 7 bits Polynomial size */
+/**
+ * @}
+ */
+
+/** @defgroup CRC_LL_EC_INDATA_REVERSE Input Data Reverse
+ * @{
+ */
+#define LL_CRC_INDATA_REVERSE_NONE 0x00000000U /*!< Input Data bit order not affected */
+#define LL_CRC_INDATA_REVERSE_BYTE CRC_CR_REV_IN_0 /*!< Input Data bit reversal done by byte */
+#define LL_CRC_INDATA_REVERSE_HALFWORD CRC_CR_REV_IN_1 /*!< Input Data bit reversal done by half-word */
+#define LL_CRC_INDATA_REVERSE_WORD (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0) /*!< Input Data bit reversal done by word */
+/**
+ * @}
+ */
+
+/** @defgroup CRC_LL_EC_OUTDATA_REVERSE Output Data Reverse
+ * @{
+ */
+#define LL_CRC_OUTDATA_REVERSE_NONE 0x00000000U /*!< Output Data bit order not affected */
+#define LL_CRC_OUTDATA_REVERSE_BIT CRC_CR_REV_OUT /*!< Output Data bit reversal done by bit */
+/**
+ * @}
+ */
+
+/** @defgroup CRC_LL_EC_Default_Polynomial_Value Default CRC generating polynomial value
+ * @brief Normal representation of this polynomial value is
+ * X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 .
+ * @{
+ */
+#define LL_CRC_DEFAULT_CRC32_POLY 0x04C11DB7U /*!< Default CRC generating polynomial value */
+/**
+ * @}
+ */
+
+/** @defgroup CRC_LL_EC_Default_InitValue Default CRC computation initialization value
+ * @{
+ */
+#define LL_CRC_DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Default CRC computation initialization value */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros
+ * @{
+ */
+
+/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in CRC register
+ * @param __INSTANCE__ CRC Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__)
+
+/**
+ * @brief Read a value in CRC register
+ * @param __INSTANCE__ CRC Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions
+ * @{
+ */
+
+/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions
+ * @{
+ */
+
+/**
+ * @brief Reset the CRC calculation unit.
+ * @note If Programmable Initial CRC value feature
+ * is available, also set the Data Register to the value stored in the
+ * CRC_INIT register, otherwise, reset Data Register to its default value.
+ * @rmtoll CR RESET LL_CRC_ResetCRCCalculationUnit
+ * @param CRCx CRC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx)
+{
+ SET_BIT(CRCx->CR, CRC_CR_RESET);
+}
+
+/**
+ * @brief Configure size of the polynomial.
+ * @rmtoll CR POLYSIZE LL_CRC_SetPolynomialSize
+ * @param CRCx CRC Instance
+ * @param PolySize This parameter can be one of the following values:
+ * @arg @ref LL_CRC_POLYLENGTH_32B
+ * @arg @ref LL_CRC_POLYLENGTH_16B
+ * @arg @ref LL_CRC_POLYLENGTH_8B
+ * @arg @ref LL_CRC_POLYLENGTH_7B
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRC_SetPolynomialSize(CRC_TypeDef *CRCx, uint32_t PolySize)
+{
+ MODIFY_REG(CRCx->CR, CRC_CR_POLYSIZE, PolySize);
+}
+
+/**
+ * @brief Return size of the polynomial.
+ * @rmtoll CR POLYSIZE LL_CRC_GetPolynomialSize
+ * @param CRCx CRC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_CRC_POLYLENGTH_32B
+ * @arg @ref LL_CRC_POLYLENGTH_16B
+ * @arg @ref LL_CRC_POLYLENGTH_8B
+ * @arg @ref LL_CRC_POLYLENGTH_7B
+ */
+__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(CRC_TypeDef *CRCx)
+{
+ return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE));
+}
+
+/**
+ * @brief Configure the reversal of the bit order of the input data
+ * @rmtoll CR REV_IN LL_CRC_SetInputDataReverseMode
+ * @param CRCx CRC Instance
+ * @param ReverseMode This parameter can be one of the following values:
+ * @arg @ref LL_CRC_INDATA_REVERSE_NONE
+ * @arg @ref LL_CRC_INDATA_REVERSE_BYTE
+ * @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
+ * @arg @ref LL_CRC_INDATA_REVERSE_WORD
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
+{
+ MODIFY_REG(CRCx->CR, CRC_CR_REV_IN, ReverseMode);
+}
+
+/**
+ * @brief Return type of reversal for input data bit order
+ * @rmtoll CR REV_IN LL_CRC_GetInputDataReverseMode
+ * @param CRCx CRC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_CRC_INDATA_REVERSE_NONE
+ * @arg @ref LL_CRC_INDATA_REVERSE_BYTE
+ * @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
+ * @arg @ref LL_CRC_INDATA_REVERSE_WORD
+ */
+__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(CRC_TypeDef *CRCx)
+{
+ return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN));
+}
+
+/**
+ * @brief Configure the reversal of the bit order of the Output data
+ * @rmtoll CR REV_OUT LL_CRC_SetOutputDataReverseMode
+ * @param CRCx CRC Instance
+ * @param ReverseMode This parameter can be one of the following values:
+ * @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
+ * @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
+{
+ MODIFY_REG(CRCx->CR, CRC_CR_REV_OUT, ReverseMode);
+}
+
+/**
+ * @brief Configure the reversal of the bit order of the Output data
+ * @rmtoll CR REV_OUT LL_CRC_GetOutputDataReverseMode
+ * @param CRCx CRC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
+ * @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
+ */
+__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(CRC_TypeDef *CRCx)
+{
+ return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT));
+}
+
+/**
+ * @brief Initialize the Programmable initial CRC value.
+ * @note If the CRC size is less than 32 bits, the least significant bits
+ * are used to write the correct value
+ * @note LL_CRC_DEFAULT_CRC_INITVALUE could be used as value for InitCrc parameter.
+ * @rmtoll INIT INIT LL_CRC_SetInitialData
+ * @param CRCx CRC Instance
+ * @param InitCrc Value to be programmed in Programmable initial CRC value register
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRC_SetInitialData(CRC_TypeDef *CRCx, uint32_t InitCrc)
+{
+ WRITE_REG(CRCx->INIT, InitCrc);
+}
+
+/**
+ * @brief Return current Initial CRC value.
+ * @note If the CRC size is less than 32 bits, the least significant bits
+ * are used to read the correct value
+ * @rmtoll INIT INIT LL_CRC_GetInitialData
+ * @param CRCx CRC Instance
+ * @retval Value programmed in Programmable initial CRC value register
+ */
+__STATIC_INLINE uint32_t LL_CRC_GetInitialData(CRC_TypeDef *CRCx)
+{
+ return (uint32_t)(READ_REG(CRCx->INIT));
+}
+
+/**
+ * @brief Initialize the Programmable polynomial value
+ * (coefficients of the polynomial to be used for CRC calculation).
+ * @note LL_CRC_DEFAULT_CRC32_POLY could be used as value for PolynomCoef parameter.
+ * @note Please check Reference Manual and existing Errata Sheets,
+ * regarding possible limitations for Polynomial values usage.
+ * For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
+ * @rmtoll POL POL LL_CRC_SetPolynomialCoef
+ * @param CRCx CRC Instance
+ * @param PolynomCoef Value to be programmed in Programmable Polynomial value register
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRC_SetPolynomialCoef(CRC_TypeDef *CRCx, uint32_t PolynomCoef)
+{
+ WRITE_REG(CRCx->POL, PolynomCoef);
+}
+
+/**
+ * @brief Return current Programmable polynomial value
+ * @note Please check Reference Manual and existing Errata Sheets,
+ * regarding possible limitations for Polynomial values usage.
+ * For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
+ * @rmtoll POL POL LL_CRC_GetPolynomialCoef
+ * @param CRCx CRC Instance
+ * @retval Value programmed in Programmable Polynomial value register
+ */
+__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(CRC_TypeDef *CRCx)
+{
+ return (uint32_t)(READ_REG(CRCx->POL));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_LL_EF_Data_Management Data_Management
+ * @{
+ */
+
+/**
+ * @brief Write given 32-bit data to the CRC calculator
+ * @rmtoll DR DR LL_CRC_FeedData32
+ * @param CRCx CRC Instance
+ * @param InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData)
+{
+ WRITE_REG(CRCx->DR, InData);
+}
+
+/**
+ * @brief Write given 16-bit data to the CRC calculator
+ * @rmtoll DR DR LL_CRC_FeedData16
+ * @param CRCx CRC Instance
+ * @param InData 16 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData)
+{
+ __IO uint16_t *pReg;
+
+ pReg = (__IO uint16_t *)(__IO void *)(&CRCx->DR); /* Derogation MisraC2012 R.11.5 */
+ *pReg = InData;
+}
+
+/**
+ * @brief Write given 8-bit data to the CRC calculator
+ * @rmtoll DR DR LL_CRC_FeedData8
+ * @param CRCx CRC Instance
+ * @param InData 8 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRC_FeedData8(CRC_TypeDef *CRCx, uint8_t InData)
+{
+ *(uint8_t __IO *)(&CRCx->DR) = (uint8_t) InData;
+}
+
+/**
+ * @brief Return current CRC calculation result. 32 bits value is returned.
+ * @rmtoll DR DR LL_CRC_ReadData32
+ * @param CRCx CRC Instance
+ * @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
+ */
+__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
+{
+ return (uint32_t)(READ_REG(CRCx->DR));
+}
+
+/**
+ * @brief Return current CRC calculation result. 16 bits value is returned.
+ * @note This function is expected to be used in a 16 bits CRC polynomial size context.
+ * @rmtoll DR DR LL_CRC_ReadData16
+ * @param CRCx CRC Instance
+ * @retval Current CRC calculation result as stored in CRC_DR register (16 bits).
+ */
+__STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx)
+{
+ return (uint16_t)READ_REG(CRCx->DR);
+}
+
+/**
+ * @brief Return current CRC calculation result. 8 bits value is returned.
+ * @note This function is expected to be used in a 8 bits CRC polynomial size context.
+ * @rmtoll DR DR LL_CRC_ReadData8
+ * @param CRCx CRC Instance
+ * @retval Current CRC calculation result as stored in CRC_DR register (8 bits).
+ */
+__STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx)
+{
+ return (uint8_t)READ_REG(CRCx->DR);
+}
+
+/**
+ * @brief Return current CRC calculation result. 7 bits value is returned.
+ * @note This function is expected to be used in a 7 bits CRC polynomial size context.
+ * @rmtoll DR DR LL_CRC_ReadData7
+ * @param CRCx CRC Instance
+ * @retval Current CRC calculation result as stored in CRC_DR register (7 bits).
+ */
+__STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx)
+{
+ return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU);
+}
+
+/**
+ * @brief Return data stored in the Independent Data(IDR) register.
+ * @note This register can be used as a temporary storage location for one 32-bit long data.
+ * @rmtoll IDR IDR LL_CRC_Read_IDR
+ * @param CRCx CRC Instance
+ * @retval Value stored in CRC_IDR register (General-purpose 32-bit data register).
+ */
+__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
+{
+ return (uint32_t)(READ_REG(CRCx->IDR));
+}
+
+/**
+ * @brief Store data in the Independent Data(IDR) register.
+ * @note This register can be used as a temporary storage location for one 32-bit long data.
+ * @rmtoll IDR IDR LL_CRC_Write_IDR
+ * @param CRCx CRC Instance
+ * @param InData value to be stored in CRC_IDR register (32-bit) between Min_Data=0 and Max_Data=0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
+{
+ *((uint32_t __IO *)(&CRCx->IDR)) = (uint32_t) InData;
+}
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(CRC) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_LL_CRC_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_crs.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_crs.h
new file mode 100644
index 00000000..163d6f1c
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_crs.h
@@ -0,0 +1,796 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_crs.h
+ * @author MCD Application Team
+ * @brief Header file of CRS LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_LL_CRS_H
+#define STM32U5xx_LL_CRS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx.h"
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined(CRS)
+
+/** @defgroup CRS_LL CRS
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CRS_LL_Private_Constants CRS Private Constants
+ * @{
+ */
+
+/* Defines used for the bit position in the register and perform offsets*/
+#define CRS_POSITION_TRIM (CRS_CR_TRIM_Pos) /* bit position in CR reg */
+#define CRS_POSITION_FECAP (CRS_ISR_FECAP_Pos) /* bit position in ISR reg */
+#define CRS_POSITION_FELIM (CRS_CFGR_FELIM_Pos) /* bit position in CFGR reg */
+
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
+ * @{
+ */
+
+/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_CRS_ReadReg function
+ * @{
+ */
+#define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF
+#define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF
+#define LL_CRS_ISR_ERRF CRS_ISR_ERRF
+#define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF
+#define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR
+#define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS
+#define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF
+/**
+ * @}
+ */
+
+/** @defgroup CRS_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions
+ * @{
+ */
+#define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE
+#define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE
+#define LL_CRS_CR_ERRIE CRS_CR_ERRIE
+#define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE
+/**
+ * @}
+ */
+
+/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
+ * @{
+ */
+#define LL_CRS_SYNC_DIV_1 0x00000000U /*!< Synchro Signal not divided (default) */
+#define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
+#define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
+#define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
+#define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
+#define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
+#define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
+#define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
+/**
+ * @}
+ */
+
+/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
+ * @{
+ */
+#define LL_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */
+#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
+#define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
+/**
+ * @}
+ */
+
+/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
+ * @{
+ */
+#define LL_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */
+#define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
+/**
+ * @}
+ */
+
+/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
+ * @{
+ */
+#define LL_CRS_FREQ_ERROR_DIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */
+#define LL_CRS_FREQ_ERROR_DIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */
+/**
+ * @}
+ */
+
+/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
+ * @{
+ */
+/**
+ * @brief Reset value of the RELOAD field
+ * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
+ * and a synchronization signal frequency of 1 kHz (SOF signal from USB)
+ */
+#define LL_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU
+
+/**
+ * @brief Reset value of Frequency error limit.
+ */
+#define LL_CRS_ERRORLIMIT_DEFAULT 0x00000022U
+
+/**
+ * @brief Reset value of the HSI48 Calibration field
+ * @note The default value is 64, which corresponds to the middle of the trimming interval.
+ * The trimming step is specified in the product datasheet.
+ * A higher TRIM value corresponds to a higher output frequency.
+ */
+#define LL_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
+ * @{
+ */
+
+/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in CRS register
+ * @param __INSTANCE__ CRS Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in CRS register
+ * @param __INSTANCE__ CRS Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
+ * @{
+ */
+
+/**
+ * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
+ * @note The RELOAD value should be selected according to the ratio between
+ * the target frequency and the frequency of the synchronization source after
+ * prescaling. It is then decreased by one in order to reach the expected
+ * synchronization on the zero value. The formula is the following:
+ * RELOAD = (fTARGET / fSYNC) -1
+ * @param __FTARGET__ Target frequency (value in Hz)
+ * @param __FSYNC__ Synchronization signal frequency (value in Hz)
+ * @retval Reload value (in Hz)
+ */
+#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
+ * @{
+ */
+
+/** @defgroup CRS_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Enable Frequency error counter
+ * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
+ * @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
+{
+ SET_BIT(CRS->CR, CRS_CR_CEN);
+}
+
+/**
+ * @brief Disable Frequency error counter
+ * @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
+{
+ CLEAR_BIT(CRS->CR, CRS_CR_CEN);
+}
+
+/**
+ * @brief Check if Frequency error counter is enabled or not
+ * @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
+{
+ return ((READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable Automatic trimming counter
+ * @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
+{
+ SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
+}
+
+/**
+ * @brief Disable Automatic trimming counter
+ * @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
+{
+ CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
+}
+
+/**
+ * @brief Check if Automatic trimming is enabled or not
+ * @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
+{
+ return ((READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set HSI48 oscillator smooth trimming
+ * @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
+ * @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming
+ * @param Value a number between Min_Data = 0 and Max_Data = 63
+ * @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
+{
+ MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_POSITION_TRIM);
+}
+
+/**
+ * @brief Get HSI48 oscillator smooth trimming
+ * @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming
+ * @retval a number between Min_Data = 0 and Max_Data = 63
+ */
+__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
+{
+ return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_POSITION_TRIM);
+}
+
+/**
+ * @brief Set counter reload value
+ * @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter
+ * @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF
+ * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
+ * Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
+{
+ MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
+}
+
+/**
+ * @brief Get counter reload value
+ * @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter
+ * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
+{
+ return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
+}
+
+/**
+ * @brief Set frequency error limit
+ * @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit
+ * @param Value a number between Min_Data = 0 and Max_Data = 255
+ * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
+{
+ MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_POSITION_FELIM);
+}
+
+/**
+ * @brief Get frequency error limit
+ * @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit
+ * @retval A number between Min_Data = 0 and Max_Data = 255
+ */
+__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
+{
+ return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_POSITION_FELIM);
+}
+
+/**
+ * @brief Set division factor for SYNC signal
+ * @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider
+ * @param Divider This parameter can be one of the following values:
+ * @arg @ref LL_CRS_SYNC_DIV_1
+ * @arg @ref LL_CRS_SYNC_DIV_2
+ * @arg @ref LL_CRS_SYNC_DIV_4
+ * @arg @ref LL_CRS_SYNC_DIV_8
+ * @arg @ref LL_CRS_SYNC_DIV_16
+ * @arg @ref LL_CRS_SYNC_DIV_32
+ * @arg @ref LL_CRS_SYNC_DIV_64
+ * @arg @ref LL_CRS_SYNC_DIV_128
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
+{
+ MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
+}
+
+/**
+ * @brief Get division factor for SYNC signal
+ * @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_CRS_SYNC_DIV_1
+ * @arg @ref LL_CRS_SYNC_DIV_2
+ * @arg @ref LL_CRS_SYNC_DIV_4
+ * @arg @ref LL_CRS_SYNC_DIV_8
+ * @arg @ref LL_CRS_SYNC_DIV_16
+ * @arg @ref LL_CRS_SYNC_DIV_32
+ * @arg @ref LL_CRS_SYNC_DIV_64
+ * @arg @ref LL_CRS_SYNC_DIV_128
+ */
+__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
+{
+ return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
+}
+
+/**
+ * @brief Set SYNC signal source
+ * @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_CRS_SYNC_SOURCE_GPIO
+ * @arg @ref LL_CRS_SYNC_SOURCE_LSE
+ * @arg @ref LL_CRS_SYNC_SOURCE_USB
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
+{
+ MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
+}
+
+/**
+ * @brief Get SYNC signal source
+ * @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_CRS_SYNC_SOURCE_GPIO
+ * @arg @ref LL_CRS_SYNC_SOURCE_LSE
+ * @arg @ref LL_CRS_SYNC_SOURCE_USB
+ */
+__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
+{
+ return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
+}
+
+/**
+ * @brief Set input polarity for the SYNC signal source
+ * @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_CRS_SYNC_POLARITY_RISING
+ * @arg @ref LL_CRS_SYNC_POLARITY_FALLING
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
+{
+ MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
+}
+
+/**
+ * @brief Get input polarity for the SYNC signal source
+ * @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_CRS_SYNC_POLARITY_RISING
+ * @arg @ref LL_CRS_SYNC_POLARITY_FALLING
+ */
+__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
+{
+ return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
+}
+
+/**
+ * @brief Configure CRS for the synchronization
+ * @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n
+ * CFGR RELOAD LL_CRS_ConfigSynchronization\n
+ * CFGR FELIM LL_CRS_ConfigSynchronization\n
+ * CFGR SYNCDIV LL_CRS_ConfigSynchronization\n
+ * CFGR SYNCSRC LL_CRS_ConfigSynchronization\n
+ * CFGR SYNCPOL LL_CRS_ConfigSynchronization
+ * @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
+ * @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
+ * @param ReloadValue a number between Min_Data = 0 and Max_Data = 255
+ * @param Settings This parameter can be a combination of the following values:
+ * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4
+ * or @ref LL_CRS_SYNC_DIV_8 or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32
+ * or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
+ * @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
+ * @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue,
+ uint32_t ReloadValue, uint32_t Settings)
+{
+ MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue);
+ MODIFY_REG(CRS->CFGR,
+ CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
+ ReloadValue | (ErrorLimitValue << CRS_POSITION_FELIM) | Settings);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRS_LL_EF_CRS_Management CRS_Management
+ * @{
+ */
+
+/**
+ * @brief Generate software SYNC event
+ * @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
+{
+ SET_BIT(CRS->CR, CRS_CR_SWSYNC);
+}
+
+/**
+ * @brief Get the frequency error direction latched in the time of the last
+ * SYNC event
+ * @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
+ * @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
+ */
+__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
+{
+ return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
+}
+
+/**
+ * @brief Get the frequency error counter value latched in the time of the last SYNC event
+ * @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture
+ * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
+{
+ return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_POSITION_FECAP);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Check if SYNC event OK signal occurred or not
+ * @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
+{
+ return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if SYNC warning signal occurred or not
+ * @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
+{
+ return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Synchronization or trimming error signal occurred or not
+ * @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
+{
+ return ((READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Expected SYNC signal occurred or not
+ * @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
+{
+ return ((READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if SYNC error signal occurred or not
+ * @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
+{
+ return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if SYNC missed error signal occurred or not
+ * @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
+{
+ return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Trimming overflow or underflow occurred or not
+ * @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
+{
+ return ((READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the SYNC event OK flag
+ * @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
+{
+ WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
+}
+
+/**
+ * @brief Clear the SYNC warning flag
+ * @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
+{
+ WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
+}
+
+/**
+ * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
+ * the ERR flag
+ * @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
+{
+ WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
+}
+
+/**
+ * @brief Clear Expected SYNC flag
+ * @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
+{
+ WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRS_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable SYNC event OK interrupt
+ * @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
+{
+ SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
+}
+
+/**
+ * @brief Disable SYNC event OK interrupt
+ * @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
+{
+ CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
+}
+
+/**
+ * @brief Check if SYNC event OK interrupt is enabled or not
+ * @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
+{
+ return ((READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable SYNC warning interrupt
+ * @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
+{
+ SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
+}
+
+/**
+ * @brief Disable SYNC warning interrupt
+ * @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
+{
+ CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
+}
+
+/**
+ * @brief Check if SYNC warning interrupt is enabled or not
+ * @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
+{
+ return ((READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable Synchronization or trimming error interrupt
+ * @rmtoll CR ERRIE LL_CRS_EnableIT_ERR
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
+{
+ SET_BIT(CRS->CR, CRS_CR_ERRIE);
+}
+
+/**
+ * @brief Disable Synchronization or trimming error interrupt
+ * @rmtoll CR ERRIE LL_CRS_DisableIT_ERR
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
+{
+ CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
+}
+
+/**
+ * @brief Check if Synchronization or trimming error interrupt is enabled or not
+ * @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
+{
+ return ((READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable Expected SYNC interrupt
+ * @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
+{
+ SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
+}
+
+/**
+ * @brief Disable Expected SYNC interrupt
+ * @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
+{
+ CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
+}
+
+/**
+ * @brief Check if Expected SYNC interrupt is enabled or not
+ * @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
+{
+ return ((READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_CRS_DeInit(void);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(CRS) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_LL_CRS_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dac.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dac.h
new file mode 100644
index 00000000..7b0fee28
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dac.h
@@ -0,0 +1,2062 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_dac.h
+ * @author MCD Application Team
+ * @brief Header file of DAC LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_LL_DAC_H
+#define STM32U5xx_LL_DAC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx.h"
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined(DAC1)
+
+/** @defgroup DAC_LL DAC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DAC_LL_Private_Constants DAC Private Constants
+ * @{
+ */
+
+/* Internal masks for DAC channels definition */
+/* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
+/* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */
+/* - channel bits position into register SWTRIG */
+/* - channel register offset of data holding register DHRx */
+/* - channel register offset of data output register DORx */
+/* - channel register offset of sample-and-hold sample time register SHSRx */
+#define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers
+ CR, MCR, CCR, SHHR, SHRR of channel 1 */
+#define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers
+ CR, MCR, CCR, SHHR, SHRR of channel 2 */
+#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
+
+#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
+#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
+#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
+
+#define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */
+#define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus
+ DHR12Rx channel 1 (shifted left of 20 bits) */
+#define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus
+ DHR12Rx channel 1 (shifted left of 24 bits) */
+
+#define DAC_REG_DHR12R2_REGOFFSET 0x30000000UL /* Register offset of DHR12Rx channel 2 versus
+ DHR12Rx channel 1 (shifted left of 28 bits) */
+#define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus
+ DHR12Rx channel 1 (shifted left of 20 bits) */
+#define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus
+ DHR12Rx channel 1 (shifted left of 24 bits) */
+
+#define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL
+#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
+#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL
+#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\
+ | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
+
+#define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */
+
+#define DAC_REG_DOR2_REGOFFSET 0x00000020UL /* Register offset of DORx channel 1 versus
+ DORx channel 2 (shifted left of 5 bits) */
+#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
+
+#define DAC_REG_SHSR1_REGOFFSET 0x00000000UL /* Register SHSRx channel 1 taken as reference */
+#define DAC_REG_SHSR2_REGOFFSET 0x00000040UL /* Register offset of SHSRx channel 1 versus
+ SHSRx channel 2 (shifted left of 6 bits) */
+#define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)
+
+
+#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx,
+ DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
+#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted
+ to position 0 */
+#define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted
+ to position 0 */
+
+#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DHR12Rx
+ channel 1 or 2 versus DHR12Rx channel 1
+ (shifted left of 28 bits) */
+#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx
+ channel 1 or 2 versus DHR12Rx channel 1
+ (shifted left of 20 bits) */
+#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx
+ channel 1 or 2 versus DHR12Rx channel 1
+ (shifted left of 24 bits) */
+#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5UL /* Position of bits register offset of DORx
+ channel 1 or 2 versus DORx channel 1
+ (shifted left of 5 bits) */
+#define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6UL /* Position of bits register offset of SHSRx
+ channel 1 or 2 versus SHSRx channel 1
+ (shifted left of 6 bits) */
+
+/* DAC registers bits positions */
+#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
+#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos
+#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
+
+/* Miscellaneous data */
+#define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12
+ bits (voltage range determined by analog voltage
+ references Vref+ and Vref-, refer to reference manual) */
+
+/**
+ * @}
+ */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DAC_LL_Private_Macros DAC Private Macros
+ * @{
+ */
+
+/**
+ * @brief Driver macro reserved for internal use: set a pointer to
+ * a register from a register basis from which an offset
+ * is applied.
+ * @param __REG__ Register basis from which the offset is applied.
+ * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
+ * @retval Pointer to register address
+ */
+#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
+ ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
+
+/**
+ * @}
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief Structure definition of some features of DAC instance.
+ */
+typedef struct
+{
+ uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel:
+ internal (SW start) or from external peripheral
+ (timer event, external interrupt line).
+ This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_DAC_SetTriggerSource(). */
+
+ uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
+ This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_DAC_SetWaveAutoGeneration(). */
+
+ uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
+ If waveform automatic generation mode is set to noise, this parameter
+ can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
+ If waveform automatic generation mode is set to triangle,
+ this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
+ @note If waveform automatic generation mode is disabled,
+ this parameter is discarded.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_DAC_SetWaveNoiseLFSR(),
+ @ref LL_DAC_SetWaveTriangleAmplitude()
+ depending on the wave automatic generation selected. */
+
+ uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
+ This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_DAC_SetOutputBuffer(). */
+
+ uint32_t OutputConnection; /*!< Set the output connection for the selected DAC channel.
+ This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_DAC_SetOutputConnection(). */
+
+ uint32_t OutputMode; /*!< Set the output mode normal or sample-and-hold for the selected DAC
+ channel. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_DAC_SetOutputMode(). */
+} LL_DAC_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
+ * @{
+ */
+
+/** @defgroup DAC_LL_EC_GET_FLAG DAC flags
+ * @brief Flags defines which can be used with LL_DAC_ReadReg function
+ * @{
+ */
+/* DAC channel 1 flags */
+#define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
+#define LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1) /*!< DAC channel 1 flag offset calibration status */
+#define LL_DAC_FLAG_BWST1 (DAC_SR_BWST1) /*!< DAC channel 1 flag busy writing sample time */
+#define LL_DAC_FLAG_DAC1RDY (DAC_SR_DAC1RDY) /*!< DAC channel 1 flag ready */
+#define LL_DAC_FLAG_DORSTAT1 (DAC_SR_DORSTAT1) /*!< DAC channel 1 flag output register */
+
+/* DAC channel 2 flags */
+#define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
+#define LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2) /*!< DAC channel 2 flag offset calibration status */
+#define LL_DAC_FLAG_BWST2 (DAC_SR_BWST2) /*!< DAC channel 2 flag busy writing sample time */
+#define LL_DAC_FLAG_DAC2RDY (DAC_SR_DAC2RDY) /*!< DAC channel 2 flag ready */
+#define LL_DAC_FLAG_DORSTAT2 (DAC_SR_DORSTAT2) /*!< DAC channel 2 flag output register */
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_IT DAC interruptions
+ * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
+ * @{
+ */
+#define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
+
+#define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_CHANNEL DAC channels
+ * @{
+ */
+#define LL_DAC_CHANNEL_1 (DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
+#define LL_DAC_CHANNEL_2 (DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_HIGH_FREQUENCY_MODE DAC high frequency interface mode
+ * @brief High frequency interface mode defines that can be used
+ * with LL_DAC_SetHighFrequencyMode and LL_DAC_GetHighFrequencyMode
+ * @{
+ */
+#define LL_DAC_HIGH_FREQ_MODE_DISABLE 0x00000000UL /*!< High frequency interface mode disabled */
+#define LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ (DAC_MCR_HFSEL_0) /*!< High frequency interface mode compatible to AHB>80MHz enabled */
+#define LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ (DAC_MCR_HFSEL_1) /*!< High frequency interface mode compatible to AHB>160MHz enabled */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_OPERATING_MODE DAC operating mode
+ * @{
+ */
+#define LL_DAC_MODE_NORMAL_OPERATION 0x00000000UL /*!< DAC channel in mode normal operation */
+#define LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1) /*!< DAC channel in mode calibration */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
+ * @{
+ */
+#define LL_DAC_TRIG_SOFTWARE 0x00000000U /*!< DAC channel conversion trigger internal (SW start) */
+#define LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM1 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM4_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM4 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: TIM5 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM8 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM15_TRGO (DAC_CR_TSEL1_3 ) /*!< DAC channel conversion trigger from external peripheral: TIM15 TRGO. */
+#define LL_DAC_TRIG_EXT_LPTIM1_CH1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: LPTIM1 CH1. */
+#define LL_DAC_TRIG_EXT_LPTIM3_CH1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: LPTIM3 CH1. */
+#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */
+
+#define LL_DAC_TRIG_EXT_LPTIM1_OUT LL_DAC_TRIG_EXT_LPTIM1_CH1 /*!< Keep old definition for compatibility */
+#define LL_DAC_TRIG_EXT_LPTIM3_OUT LL_DAC_TRIG_EXT_LPTIM3_CH1 /*!< Keep old definition for compatibility */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
+ * @{
+ */
+#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL /*!< DAC channel wave auto generation mode disabled. */
+#define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
+#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
+ * @{
+ */
+#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
+ * @{
+ */
+#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_OUTPUT_MODE DAC channel output mode
+ * @{
+ */
+#define LL_DAC_OUTPUT_MODE_NORMAL 0x00000000UL /*!< The selected DAC channel output is on mode normal. */
+#define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2) /*!< The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function @ref LL_DAC_ConfigOutput() or @ref LL_DAC_SetOutputMode(). */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
+ * @{
+ */
+#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
+#define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_OUTPUT_CONNECTION DAC channel output connection
+ * @{
+ */
+#define LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000UL /*!< The selected DAC channel output is connected to external pin */
+#define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0) /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 series, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_SIGNED_FORMAT DAC channel signed format
+ * @{
+ */
+#define LL_DAC_SIGNED_FORMAT_DISABLE 0x00000000UL /*!< The selected DAC channel data format is not signed */
+#define LL_DAC_SIGNED_FORMAT_ENABLE (DAC_MCR_SINFORMAT1) /*!< The selected DAC channel data format is signed */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
+ * @{
+ */
+#define LL_DAC_RESOLUTION_12B 0x00000000UL /*!< DAC channel resolution 12 bits */
+#define LL_DAC_RESOLUTION_8B 0x00000002UL /*!< DAC channel resolution 8 bits */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
+ * @{
+ */
+/* List of DAC registers intended to be used (most commonly) with */
+/* DMA transfer. */
+/* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
+#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
+#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
+#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
+ * @note Only DAC peripheral HW delays are defined in DAC LL driver driver,
+ * not timeout values.
+ * For details on delays values, refer to descriptions in source code
+ * above each literal definition.
+ * @{
+ */
+
+/* Delay for DAC channel voltage settling time from DAC channel startup */
+/* (transition from disable to enable). */
+/* Note: DAC channel startup time depends on board application environment: */
+/* impedance connected to DAC channel output. */
+/* The delay below is specified under conditions: */
+/* - voltage maximum transition (lowest to highest value) */
+/* - until voltage reaches final value +-1LSB */
+/* - DAC channel output buffer enabled */
+/* - load impedance of 5kOhm (min), 50pF (max) */
+/* Literal set to maximum value (refer to device datasheet, */
+/* parameter "tWAKEUP"). */
+/* Unit: us */
+#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
+
+/* Delay for DAC channel voltage settling time. */
+/* Note: DAC channel startup time depends on board application environment: */
+/* impedance connected to DAC channel output. */
+/* The delay below is specified under conditions: */
+/* - voltage maximum transition (lowest to highest value) */
+/* - until voltage reaches final value +-1LSB */
+/* - DAC channel output buffer enabled */
+/* - load impedance of 5kOhm min, 50pF max */
+/* Literal set to maximum value (refer to device datasheet, */
+/* parameter "tSETTLING"). */
+/* Unit: us */
+#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 3UL /*!< Delay for DAC channel voltage settling time */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
+ * @{
+ */
+
+/** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in DAC register
+ * @param __INSTANCE__ DAC Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in DAC register
+ * @param __INSTANCE__ DAC Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
+ * @{
+ */
+
+/**
+ * @brief Helper macro to get DAC channel number in decimal format
+ * from literals LL_DAC_CHANNEL_x.
+ * Example:
+ * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
+ * will return decimal number "1".
+ * @note The input can be a value from functions where a channel
+ * number is returned.
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval 1...2
+ */
+#define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
+ ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
+
+/**
+ * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
+ * from number in decimal format.
+ * Example:
+ * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
+ * will return a data equivalent to "LL_DAC_CHANNEL_1".
+ * @note If the input parameter does not correspond to a DAC channel,
+ * this macro returns value '0'.
+ * @param __DECIMAL_NB__ 1...2
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ */
+#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)\
+ (((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1 ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL)))
+
+/**
+ * @brief Helper macro to define the DAC conversion data full-scale digital
+ * value corresponding to the selected DAC resolution.
+ * @note DAC conversion data full-scale corresponds to voltage range
+ * determined by analog voltage references Vref+ and Vref-
+ * (refer to reference manual).
+ * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_DAC_RESOLUTION_12B
+ * @arg @ref LL_DAC_RESOLUTION_8B
+ * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+ */
+#define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
+ ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
+
+/**
+ * @brief Helper macro to calculate the DAC conversion data (unit: digital
+ * value) corresponding to a voltage (unit: mVolt).
+ * @note This helper macro is intended to provide input data in voltage
+ * rather than digital value,
+ * to be used with LL DAC functions such as
+ * @ref LL_DAC_ConvertData12RightAligned().
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+ * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
+ * (unit: mVolt).
+ * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_DAC_RESOLUTION_12B
+ * @arg @ref LL_DAC_RESOLUTION_8B
+ * @retval DAC conversion data (unit: digital value)
+ */
+#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
+ __DAC_VOLTAGE__,\
+ __DAC_RESOLUTION__) \
+((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
+ / (__VREFANALOG_VOLTAGE__) \
+)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
+ * @{
+ */
+/** @defgroup DAC_LL_EF_Channel_Configuration Configuration of DAC instance
+ * @{
+ */
+/**
+ * @brief Set the high frequency interface mode for the selected DAC instance
+ * @rmtoll MCR HFSEL LL_DAC_SetHighFrequencyMode
+ * @param DACx DAC instance
+ * @param HighFreqMode This parameter can be one of the following values:
+ * @arg @ref LL_DAC_HIGH_FREQ_MODE_DISABLE
+ * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ
+ * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_SetHighFrequencyMode(DAC_TypeDef *DACx, uint32_t HighFreqMode)
+{
+ MODIFY_REG(DACx->MCR, DAC_MCR_HFSEL, HighFreqMode);
+}
+
+/**
+ * @brief Get the high frequency interface mode for the selected DAC instance
+ * @rmtoll MCR HFSEL LL_DAC_GetHighFrequencyMode
+ * @param DACx DAC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DAC_HIGH_FREQ_MODE_DISABLE
+ * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ
+ * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ
+ */
+__STATIC_INLINE uint32_t LL_DAC_GetHighFrequencyMode(DAC_TypeDef *DACx)
+{
+ return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_HFSEL));
+}
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
+ * @{
+ */
+
+/**
+ * @brief Set the operating mode for the selected DAC channel:
+ * calibration or normal operating mode.
+ * @rmtoll CR CEN1 LL_DAC_SetMode\n
+ * CR CEN2 LL_DAC_SetMode
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @param ChannelMode This parameter can be one of the following values:
+ * @arg @ref LL_DAC_MODE_NORMAL_OPERATION
+ * @arg @ref LL_DAC_MODE_CALIBRATION
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode)
+{
+ MODIFY_REG(DACx->CR,
+ DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+ ChannelMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get the operating mode for the selected DAC channel:
+ * calibration or normal operating mode.
+ * @rmtoll CR CEN1 LL_DAC_GetMode\n
+ * CR CEN2 LL_DAC_GetMode
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DAC_MODE_NORMAL_OPERATION
+ * @arg @ref LL_DAC_MODE_CALIBRATION
+ */
+__STATIC_INLINE uint32_t LL_DAC_GetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+}
+
+/**
+ * @brief Set the offset trimming value for the selected DAC channel.
+ * Trimming has an impact when output buffer is enabled
+ * and is intended to replace factory calibration default values.
+ * @rmtoll CCR OTRIM1 LL_DAC_SetTrimmingValue\n
+ * CCR OTRIM2 LL_DAC_SetTrimmingValue
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @param TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue)
+{
+ MODIFY_REG(DACx->CCR,
+ DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+ TrimmingValue << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get the offset trimming value for the selected DAC channel.
+ * Trimming has an impact when output buffer is enabled
+ * and is intended to replace factory calibration default values.
+ * @rmtoll CCR OTRIM1 LL_DAC_GetTrimmingValue\n
+ * CCR OTRIM2 LL_DAC_GetTrimmingValue
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
+ */
+__STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+}
+
+/**
+ * @brief Set the conversion trigger source for the selected DAC channel.
+ * @note For conversion trigger source to be effective, DAC trigger
+ * must be enabled using function @ref LL_DAC_EnableTrigger().
+ * @note To set conversion trigger source, DAC channel must be disabled.
+ * Otherwise, the setting is discarded.
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
+ * CR TSEL2 LL_DAC_SetTriggerSource
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @param TriggerSource This parameter can be one of the following values:
+ * @arg @ref LL_DAC_TRIG_SOFTWARE
+ * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_CH1
+ * @arg @ref LL_DAC_TRIG_EXT_LPTIM3_CH1
+ * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
+{
+ MODIFY_REG(DACx->CR,
+ DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+ TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get the conversion trigger source for the selected DAC channel.
+ * @note For conversion trigger source to be effective, DAC trigger
+ * must be enabled using function @ref LL_DAC_EnableTrigger().
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
+ * CR TSEL2 LL_DAC_GetTriggerSource
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DAC_TRIG_SOFTWARE
+ * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_CH1
+ * @arg @ref LL_DAC_TRIG_EXT_LPTIM3_CH1
+ * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
+ */
+__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+}
+
+/**
+ * @brief Set the waveform automatic generation mode
+ * for the selected DAC channel.
+ * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
+ * CR WAVE2 LL_DAC_SetWaveAutoGeneration
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @param WaveAutoGeneration This parameter can be one of the following values:
+ * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
+ * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
+ * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
+{
+ MODIFY_REG(DACx->CR,
+ DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+ WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get the waveform automatic generation mode
+ * for the selected DAC channel.
+ * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
+ * CR WAVE2 LL_DAC_GetWaveAutoGeneration
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
+ * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
+ * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
+ */
+__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+}
+
+/**
+ * @brief Set the noise waveform generation for the selected DAC channel:
+ * Noise mode and parameters LFSR (linear feedback shift register).
+ * @note For wave generation to be effective, DAC channel
+ * wave generation mode must be enabled using
+ * function @ref LL_DAC_SetWaveAutoGeneration().
+ * @note This setting can be set when the selected DAC channel is disabled
+ * (otherwise, the setting operation is ignored).
+ * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
+ * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @param NoiseLFSRMask This parameter can be one of the following values:
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
+{
+ MODIFY_REG(DACx->CR,
+ DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+ NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get the noise waveform generation for the selected DAC channel:
+ * Noise mode and parameters LFSR (linear feedback shift register).
+ * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
+ * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
+ */
+__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+}
+
+/**
+ * @brief Set the triangle waveform generation for the selected DAC channel:
+ * triangle mode and amplitude.
+ * @note For wave generation to be effective, DAC channel
+ * wave generation mode must be enabled using
+ * function @ref LL_DAC_SetWaveAutoGeneration().
+ * @note This setting can be set when the selected DAC channel is disabled
+ * (otherwise, the setting operation is ignored).
+ * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
+ * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @param TriangleAmplitude This parameter can be one of the following values:
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel,
+ uint32_t TriangleAmplitude)
+{
+ MODIFY_REG(DACx->CR,
+ DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+ TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get the triangle waveform generation for the selected DAC channel:
+ * triangle mode and amplitude.
+ * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
+ * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
+ */
+__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+}
+
+/**
+ * @brief Set the output for the selected DAC channel.
+ * @note This function set several features:
+ * - mode normal or sample-and-hold
+ * - buffer
+ * - connection to GPIO or internal path.
+ * These features can also be set individually using
+ * dedicated functions:
+ * - @ref LL_DAC_SetOutputBuffer()
+ * - @ref LL_DAC_SetOutputMode()
+ * - @ref LL_DAC_SetOutputConnection()
+ * @note On this STM32 series, output connection depends on output mode
+ * (normal or sample and hold) and output buffer state.
+ * - if output connection is set to internal path and output buffer
+ * is enabled (whatever output mode):
+ * output connection is also connected to GPIO pin
+ * (both connections to GPIO pin and internal path).
+ * - if output connection is set to GPIO pin, output buffer
+ * is disabled, output mode set to sample and hold:
+ * output connection is also connected to internal path
+ * (both connections to GPIO pin and internal path).
+ * @note Mode sample-and-hold requires an external capacitor
+ * to be connected between DAC channel output and ground.
+ * Capacitor value depends on load on DAC channel output and
+ * sample-and-hold timings configured.
+ * As indication, capacitor typical value is 100nF
+ * (refer to device datasheet, parameter "CSH").
+ * @rmtoll CR MODE1 LL_DAC_ConfigOutput\n
+ * CR MODE2 LL_DAC_ConfigOutput
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @param OutputMode This parameter can be one of the following values:
+ * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
+ * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
+ * @param OutputBuffer This parameter can be one of the following values:
+ * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
+ * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
+ * @param OutputConnection This parameter can be one of the following values:
+ * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
+ * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode,
+ uint32_t OutputBuffer, uint32_t OutputConnection)
+{
+ MODIFY_REG(DACx->MCR,
+ (DAC_MCR_MODE1_2 | DAC_MCR_MODE1_1 | DAC_MCR_MODE1_0) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+ (OutputMode | OutputBuffer | OutputConnection) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Set the output mode normal or sample-and-hold
+ * for the selected DAC channel.
+ * @note Mode sample-and-hold requires an external capacitor
+ * to be connected between DAC channel output and ground.
+ * Capacitor value depends on load on DAC channel output and
+ * sample-and-hold timings configured.
+ * As indication, capacitor typical value is 100nF
+ * (refer to device datasheet, parameter "CSH").
+ * @rmtoll CR MODE1 LL_DAC_SetOutputMode\n
+ * CR MODE2 LL_DAC_SetOutputMode
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @param OutputMode This parameter can be one of the following values:
+ * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
+ * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode)
+{
+ MODIFY_REG(DACx->MCR,
+ (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+ OutputMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get the output mode normal or sample-and-hold for the selected DAC channel.
+ * @rmtoll CR MODE1 LL_DAC_GetOutputMode\n
+ * CR MODE2 LL_DAC_GetOutputMode
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
+ * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
+ */
+__STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+}
+
+/**
+ * @brief Set the output buffer for the selected DAC channel.
+ * @note On this STM32 series, when buffer is enabled, its offset can be
+ * trimmed: factory calibration default values can be
+ * replaced by user trimming values, using function
+ * @ref LL_DAC_SetTrimmingValue().
+ * @rmtoll CR MODE1 LL_DAC_SetOutputBuffer\n
+ * CR MODE2 LL_DAC_SetOutputBuffer
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @param OutputBuffer This parameter can be one of the following values:
+ * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
+ * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
+{
+ MODIFY_REG(DACx->MCR,
+ (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+ OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get the output buffer state for the selected DAC channel.
+ * @rmtoll CR MODE1 LL_DAC_GetOutputBuffer\n
+ * CR MODE2 LL_DAC_GetOutputBuffer
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
+ * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
+ */
+__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+}
+
+/**
+ * @brief Set the output connection for the selected DAC channel.
+ * @note On this STM32 series, output connection depends on output mode (normal or
+ * sample and hold) and output buffer state.
+ * - if output connection is set to internal path and output buffer
+ * is enabled (whatever output mode):
+ * output connection is also connected to GPIO pin
+ * (both connections to GPIO pin and internal path).
+ * - if output connection is set to GPIO pin, output buffer
+ * is disabled, output mode set to sample and hold:
+ * output connection is also connected to internal path
+ * (both connections to GPIO pin and internal path).
+ * @rmtoll CR MODE1 LL_DAC_SetOutputConnection\n
+ * CR MODE2 LL_DAC_SetOutputConnection
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @param OutputConnection This parameter can be one of the following values:
+ * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
+ * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection)
+{
+ MODIFY_REG(DACx->MCR,
+ (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+ OutputConnection << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get the output connection for the selected DAC channel.
+ * @note On this STM32 series, output connection depends on output mode (normal or
+ * sample and hold) and output buffer state.
+ * - if output connection is set to internal path and output buffer
+ * is enabled (whatever output mode):
+ * output connection is also connected to GPIO pin
+ * (both connections to GPIO pin and internal path).
+ * - if output connection is set to GPIO pin, output buffer
+ * is disabled, output mode set to sample and hold:
+ * output connection is also connected to internal path
+ * (both connections to GPIO pin and internal path).
+ * @rmtoll CR MODE1 LL_DAC_GetOutputConnection\n
+ * CR MODE2 LL_DAC_GetOutputConnection
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
+ * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
+ */
+__STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+}
+
+/**
+ * @brief Set the sample-and-hold timing for the selected DAC channel:
+ * sample time
+ * @note Sample time must be set when DAC channel is disabled
+ * or during DAC operation when DAC channel flag BWSTx is reset,
+ * otherwise the setting is ignored.
+ * Check BWSTx flag state using function "LL_DAC_IsActiveFlag_BWSTx()".
+ * @rmtoll SHSR1 TSAMPLE1 LL_DAC_SetSampleAndHoldSampleTime\n
+ * SHSR2 TSAMPLE2 LL_DAC_SetSampleAndHoldSampleTime
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @param SampleTime Value between Min_Data=0x000 and Max_Data=0x3FF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
+{
+ __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
+ & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
+
+ MODIFY_REG(*preg, DAC_SHSR1_TSAMPLE1, SampleTime);
+}
+
+/**
+ * @brief Get the sample-and-hold timing for the selected DAC channel:
+ * sample time
+ * @rmtoll SHSR1 TSAMPLE1 LL_DAC_GetSampleAndHoldSampleTime\n
+ * SHSR2 TSAMPLE2 LL_DAC_GetSampleAndHoldSampleTime
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
+ */
+__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
+ & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
+
+ return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1);
+}
+
+/**
+ * @brief Set the sample-and-hold timing for the selected DAC channel:
+ * hold time
+ * @rmtoll SHHR THOLD1 LL_DAC_SetSampleAndHoldHoldTime\n
+ * SHHR THOLD2 LL_DAC_SetSampleAndHoldHoldTime
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @param HoldTime Value between Min_Data=0x000 and Max_Data=0x3FF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime)
+{
+ MODIFY_REG(DACx->SHHR,
+ DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+ HoldTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get the sample-and-hold timing for the selected DAC channel:
+ * hold time
+ * @rmtoll SHHR THOLD1 LL_DAC_GetSampleAndHoldHoldTime\n
+ * SHHR THOLD2 LL_DAC_GetSampleAndHoldHoldTime
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
+ */
+__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+}
+
+/**
+ * @brief Set the sample-and-hold timing for the selected DAC channel:
+ * refresh time
+ * @rmtoll SHRR TREFRESH1 LL_DAC_SetSampleAndHoldRefreshTime\n
+ * SHRR TREFRESH2 LL_DAC_SetSampleAndHoldRefreshTime
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @param RefreshTime Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime)
+{
+ MODIFY_REG(DACx->SHRR,
+ DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+ RefreshTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get the sample-and-hold timing for the selected DAC channel:
+ * refresh time
+ * @rmtoll SHRR TREFRESH1 LL_DAC_GetSampleAndHoldRefreshTime\n
+ * SHRR TREFRESH2 LL_DAC_GetSampleAndHoldRefreshTime
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+}
+
+/**
+ * @brief Set the signed format for the selected DAC channel.
+ * @note On this STM32 series, signed format can be used to inject
+ * Q1.15, Q1.11, Q1.7 signed format data to DAC.
+ * Ex when using 12bits data format (Q1.11 is used):
+ * 0x800 will output 0v level
+ * 0xFFF will output mid-scale level
+ * 0x000 will output mid-scale level
+ * 0x7FF will output full-scale level
+ * @rmtoll MCR SINFORMAT1 LL_DAC_SetSignedFormat\n
+ * MCR SINFORMAT2 LL_DAC_SetSignedFormat
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @param SignedFormat This parameter can be one of the following values:
+ * @arg @ref LL_DAC_SIGNED_FORMAT_ENABLE
+ * @arg @ref LL_DAC_SIGNED_FORMAT_DISABLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_SetSignedFormat(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SignedFormat)
+{
+ MODIFY_REG(DACx->MCR,
+ DAC_MCR_SINFORMAT1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+ SignedFormat << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get the signed format state for the selected DAC channel.
+ * @rmtoll MCR SINFORMAT1 LL_DAC_GetSignedFormat\n
+ * MCR SINFORMAT2 LL_DAC_GetSignedFormat
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DAC_SIGNED_FORMAT_ENABLE
+ * @arg @ref LL_DAC_SIGNED_FORMAT_DISABLE
+ */
+__STATIC_INLINE uint32_t LL_DAC_GetSignedFormat(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_SINFORMAT1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EF_DMA_Management DMA Management
+ * @{
+ */
+
+/**
+ * @brief Enable DAC DMA transfer request of the selected channel.
+ * @note To configure DMA source address (peripheral address),
+ * use function @ref LL_DAC_DMA_GetRegAddr().
+ * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
+ * CR DMAEN2 LL_DAC_EnableDMAReq
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ SET_BIT(DACx->CR,
+ DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Disable DAC DMA transfer request of the selected channel.
+ * @note To configure DMA source address (peripheral address),
+ * use function @ref LL_DAC_DMA_GetRegAddr().
+ * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
+ * CR DMAEN2 LL_DAC_DisableDMAReq
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ CLEAR_BIT(DACx->CR,
+ DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get DAC DMA transfer request state of the selected channel.
+ * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
+ * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
+ * CR DMAEN2 LL_DAC_IsDMAReqEnabled
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return ((READ_BIT(DACx->CR,
+ DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable DAC DMA Double data mode of the selected channel.
+ * @rmtoll MCR DMADOUBLE1 LL_DAC_EnableDMADoubleDataMode\n
+ * MCR DMADOUBLE2 LL_DAC_EnableDMADoubleDataMode
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_EnableDMADoubleDataMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ SET_BIT(DACx->MCR,
+ DAC_MCR_DMADOUBLE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Disable DAC DMA Double data mode of the selected channel.
+ * @rmtoll MCR DMADOUBLE1 LL_DAC_DisableDMADoubleDataMode\n
+ * MCR DMADOUBLE2 LL_DAC_DisableDMADoubleDataMode
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_DisableDMADoubleDataMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ CLEAR_BIT(DACx->MCR,
+ DAC_MCR_DMADOUBLE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get DAC DMA double data mode state of the selected channel.
+ * (0: DAC DMA double data mode is disabled, 1: DAC DMA double data mode is enabled)
+ * @rmtoll MCR DMADOUBLE1 LL_DAC_IsDMADoubleDataModeEnabled\n
+ * MCR DMADOUBLE2 LL_DAC_IsDMADoubleDataModeEnabled
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsDMADoubleDataModeEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return ((READ_BIT(DACx->MCR,
+ DAC_MCR_DMADOUBLE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ == (DAC_MCR_DMADOUBLE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Function to help to configure DMA transfer to DAC: retrieve the
+ * DAC register address from DAC instance and a list of DAC registers
+ * intended to be used (most commonly) with DMA transfer.
+ * @note These DAC registers are data holding registers:
+ * when DAC conversion is requested, DAC generates a DMA transfer
+ * request to have data available in DAC data holding registers.
+ * @note This macro is intended to be used with LL DMA driver, refer to
+ * function "LL_DMA_ConfigAddresses()".
+ * Example:
+ * LL_DMA_ConfigAddresses(DMA1,
+ * LL_DMA_CHANNEL_1,
+ * (uint32_t)&< array or variable >,
+ * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1,
+ * LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
+ * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
+ * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
+ * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
+ * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
+ * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
+ * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
+ * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @param Register This parameter can be one of the following values:
+ * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
+ * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
+ * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
+ * @retval DAC register address
+ */
+__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
+{
+ /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
+ /* DAC channel selected. */
+ return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL))
+ & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
+}
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EF_Operation Operation on DAC channels
+ * @{
+ */
+
+/**
+ * @brief Enable DAC selected channel.
+ * @rmtoll CR EN1 LL_DAC_Enable\n
+ * CR EN2 LL_DAC_Enable
+ * @note After enable from off state, DAC channel requires a delay
+ * for output voltage to reach accuracy +/- 1 LSB.
+ * Refer to device datasheet, parameter "tWAKEUP".
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ SET_BIT(DACx->CR,
+ DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Disable DAC selected channel.
+ * @rmtoll CR EN1 LL_DAC_Disable\n
+ * CR EN2 LL_DAC_Disable
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ CLEAR_BIT(DACx->CR,
+ DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get DAC enable state of the selected channel.
+ * (0: DAC channel is disabled, 1: DAC channel is enabled)
+ * @rmtoll CR EN1 LL_DAC_IsEnabled\n
+ * CR EN2 LL_DAC_IsEnabled
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return ((READ_BIT(DACx->CR,
+ DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get DAC ready for conversion state of the selected channel.
+ * (0: DAC channel is not ready, 1: DAC channel is ready)
+ * @rmtoll SR DAC1RDY LL_DAC_IsReady\n
+ * SR DAC2RDY LL_DAC_IsReady
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsReady(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return ((READ_BIT(DACx->SR,
+ DAC_SR_DAC1RDY << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ == (DAC_SR_DAC1RDY << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable DAC trigger of the selected channel.
+ * @note - If DAC trigger is disabled, DAC conversion is performed
+ * automatically once the data holding register is updated,
+ * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
+ * @ref LL_DAC_ConvertData12RightAligned(), ...
+ * - If DAC trigger is enabled, DAC conversion is performed
+ * only when a hardware of software trigger event is occurring.
+ * Select trigger source using
+ * function @ref LL_DAC_SetTriggerSource().
+ * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
+ * CR TEN2 LL_DAC_EnableTrigger
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ SET_BIT(DACx->CR,
+ DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Disable DAC trigger of the selected channel.
+ * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
+ * CR TEN2 LL_DAC_DisableTrigger
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ CLEAR_BIT(DACx->CR,
+ DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get DAC trigger state of the selected channel.
+ * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
+ * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
+ * CR TEN2 LL_DAC_IsTriggerEnabled
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return ((READ_BIT(DACx->CR,
+ DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Trig DAC conversion by software for the selected DAC channel.
+ * @note Preliminarily, DAC trigger must be set to software trigger
+ * using function
+ * @ref LL_DAC_Init()
+ * @ref LL_DAC_SetTriggerSource()
+ * with parameter "LL_DAC_TRIGGER_SOFTWARE".
+ * and DAC trigger must be enabled using
+ * function @ref LL_DAC_EnableTrigger().
+ * @note For devices featuring DAC with 2 channels: this function
+ * can perform a SW start of both DAC channels simultaneously.
+ * Two channels can be selected as parameter.
+ * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
+ * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
+ * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can a combination of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ SET_BIT(DACx->SWTRIGR,
+ (DAC_Channel & DAC_SWTR_CHX_MASK));
+}
+
+/**
+ * @brief Set the data to be loaded in the data holding register
+ * in format 12 bits left alignment (LSB aligned on bit 0),
+ * for the selected DAC channel.
+ * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
+ * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
+{
+ __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS)
+ & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
+
+ MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data);
+}
+
+/**
+ * @brief Set the data to be loaded in the data holding register
+ * in format 12 bits left alignment (MSB aligned on bit 15),
+ * for the selected DAC channel.
+ * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
+ * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
+{
+ __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS)
+ & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
+
+ MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data);
+}
+
+/**
+ * @brief Set the data to be loaded in the data holding register
+ * in format 8 bits left alignment (LSB aligned on bit 0),
+ * for the selected DAC channel.
+ * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
+ * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
+{
+ __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS)
+ & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
+
+ MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data);
+}
+
+
+/**
+ * @brief Set the data to be loaded in the data holding register
+ * in format 12 bits left alignment (LSB aligned on bit 0),
+ * for both DAC channels.
+ * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
+ * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
+ * @param DACx DAC instance
+ * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
+ uint32_t DataChannel2)
+{
+ MODIFY_REG(DACx->DHR12RD,
+ (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
+ ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
+}
+
+/**
+ * @brief Set the data to be loaded in the data holding register
+ * in format 12 bits left alignment (MSB aligned on bit 15),
+ * for both DAC channels.
+ * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
+ * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
+ * @param DACx DAC instance
+ * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
+ uint32_t DataChannel2)
+{
+ /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
+ /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
+ /* the 4 LSB must be taken into account for the shift value. */
+ MODIFY_REG(DACx->DHR12LD,
+ (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
+ ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
+}
+
+/**
+ * @brief Set the data to be loaded in the data holding register
+ * in format 8 bits left alignment (LSB aligned on bit 0),
+ * for both DAC channels.
+ * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
+ * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
+ * @param DACx DAC instance
+ * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
+ * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
+ uint32_t DataChannel2)
+{
+ MODIFY_REG(DACx->DHR8RD,
+ (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
+ ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
+}
+
+
+/**
+ * @brief Retrieve output data currently generated for the selected DAC channel.
+ * @note Whatever alignment and resolution settings
+ * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
+ * @ref LL_DAC_ConvertData12RightAligned(), ...),
+ * output data format is 12 bits right aligned (LSB aligned on bit 0).
+ * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
+ * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
+ & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
+
+ return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
+ * @{
+ */
+/**
+ * @brief Get DAC calibration offset flag for DAC channel 1
+ * @rmtoll SR CAL_FLAG1 LL_DAC_IsActiveFlag_CAL1
+ * @param DACx DAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx)
+{
+ return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL);
+}
+
+
+/**
+ * @brief Get DAC calibration offset flag for DAC channel 2
+ * @rmtoll SR CAL_FLAG2 LL_DAC_IsActiveFlag_CAL2
+ * @param DACx DAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx)
+{
+ return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)) ? 1UL : 0UL);
+}
+
+
+/**
+ * @brief Get DAC busy writing sample time flag for DAC channel 1
+ * @rmtoll SR BWST1 LL_DAC_IsActiveFlag_BWST1
+ * @param DACx DAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx)
+{
+ return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get DAC busy writing sample time flag for DAC channel 2
+ * @rmtoll SR BWST2 LL_DAC_IsActiveFlag_BWST2
+ * @param DACx DAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx)
+{
+ return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)) ? 1UL : 0UL);
+}
+
+
+/**
+ * @brief Get DAC ready status flag for DAC channel 1
+ * @rmtoll SR DAC1RDY LL_DAC_IsActiveFlag_DAC1RDY
+ * @param DACx DAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DAC1RDY(DAC_TypeDef *DACx)
+{
+ return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DAC1RDY) == (LL_DAC_FLAG_DAC1RDY)) ? 1UL : 0UL);
+}
+
+
+/**
+ * @brief Get DAC ready status flag for DAC channel 2
+ * @rmtoll SR DAC2RDY LL_DAC_IsActiveFlag_DAC2RDY
+ * @param DACx DAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DAC2RDY(DAC_TypeDef *DACx)
+{
+ return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DAC2RDY) == (LL_DAC_FLAG_DAC2RDY)) ? 1UL : 0UL);
+}
+
+
+/**
+ * @brief Get DAC output register status flag for DAC channel 1
+ * @rmtoll SR DORSTAT1 LL_DAC_IsActiveFlag_DORSTAT1
+ * @param DACx DAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DORSTAT1(DAC_TypeDef *DACx)
+{
+ return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DORSTAT1) == (LL_DAC_FLAG_DORSTAT1)) ? 1UL : 0UL);
+}
+
+
+/**
+ * @brief Get DAC output register status flag for DAC channel 2
+ * @rmtoll SR DORSTAT2 LL_DAC_IsActiveFlag_DORSTAT2
+ * @param DACx DAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DORSTAT2(DAC_TypeDef *DACx)
+{
+ return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DORSTAT2) == (LL_DAC_FLAG_DORSTAT2)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get DAC underrun flag for DAC channel 1
+ * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
+ * @param DACx DAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
+{
+ return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
+}
+
+
+/**
+ * @brief Get DAC underrun flag for DAC channel 2
+ * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
+ * @param DACx DAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
+{
+ return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
+}
+
+
+/**
+ * @brief Clear DAC underrun flag for DAC channel 1
+ * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
+ * @param DACx DAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
+{
+ WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
+}
+
+
+/**
+ * @brief Clear DAC underrun flag for DAC channel 2
+ * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
+ * @param DACx DAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
+{
+ WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EF_IT_Management IT management
+ * @{
+ */
+
+/**
+ * @brief Enable DMA underrun interrupt for DAC channel 1
+ * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
+ * @param DACx DAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
+{
+ SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
+}
+
+
+/**
+ * @brief Enable DMA underrun interrupt for DAC channel 2
+ * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
+ * @param DACx DAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
+{
+ SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
+}
+
+
+/**
+ * @brief Disable DMA underrun interrupt for DAC channel 1
+ * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
+ * @param DACx DAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
+{
+ CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
+}
+
+
+/**
+ * @brief Disable DMA underrun interrupt for DAC channel 2
+ * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
+ * @param DACx DAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
+{
+ CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
+}
+
+
+/**
+ * @brief Get DMA underrun interrupt for DAC channel 1
+ * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
+ * @param DACx DAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
+{
+ return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
+}
+
+
+/**
+ * @brief Get DMA underrun interrupt for DAC channel 2
+ * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
+ * @param DACx DAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
+{
+ return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
+}
+
+
+/**
+ * @brief Enable DAC autonomous mode.
+ * @rmtoll AUTOCR AUTOMODE LL_DAC_EnableAutonomousMode
+ * @param DACx DAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_EnableAutonomousMode(DAC_TypeDef *DACx)
+{
+ SET_BIT(DACx->AUTOCR, DAC_AUTOCR_AUTOMODE);
+}
+
+/**
+ * @brief Disable DAC autonomous mode.
+ * @rmtoll AUTOCR AUTOMODE LL_DAC_DisableAutonomousMode
+ * @param DACx DAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_DisableAutonomousMode(DAC_TypeDef *DACx)
+{
+ CLEAR_BIT(DACx->AUTOCR, DAC_AUTOCR_AUTOMODE);
+}
+
+/**
+ * @brief Get DAC autonomous mode state.
+ * (0: DAC autonomous mode is disabled, 1: DAC autonomous mode is enabled)
+ * @param DACx DAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsAutonomousModeEnabled(DAC_TypeDef *DACx)
+{
+ return ((READ_BIT(DACx->AUTOCR, DAC_AUTOCR_AUTOMODE) == (DAC_AUTOCR_AUTOMODE)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx);
+ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct);
+void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* DAC1 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_LL_DAC_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dcache.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dcache.h
new file mode 100644
index 00000000..911e0f5d
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dcache.h
@@ -0,0 +1,655 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_dcache.h
+ * @author MCD Application Team
+ * @brief Header file of DCACHE LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion ------------------------------------*/
+#ifndef STM32U5xx_LL_DCACHE_H
+#define STM32U5xx_LL_DCACHE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes -----------------------------------------------------------------*/
+#include "stm32u5xx.h"
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined (DCACHE1)
+
+/** @defgroup DCACHE_LL DCACHE
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup DCACHE_Private_Constants DCACHE Private Constants
+ * @{
+ */
+#define LL_DCACHE_COMMAND_NO_OPERATION (0x00000000)
+#define LL_DCACHE_COMMAND_CLEAN_BY_ADDR DCACHE_CR_CACHECMD_0
+#define LL_DCACHE_COMMAND_INVALIDATE_BY_ADDR DCACHE_CR_CACHECMD_1
+#define LL_DCACHE_COMMAND_CLEAN_INVALIDATE_BY_ADDR (DCACHE_CR_CACHECMD_0|DCACHE_CR_CACHECMD_1)
+/**
+ * @}
+ */
+
+/** @defgroup DCACHE_Read_Burst_Type Remapped Output burst type
+ * @{
+ */
+#define LL_DCACHE_READ_BURST_WRAP 0U /*!< WRAP */
+#define LL_DCACHE_READ_BURST_INCR DCACHE_CR_HBURST /*!< INCR */
+/**
+ * @}
+ */
+
+/** @defgroup DCACHE_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_DCACHE_ReadReg function
+ * @{
+ */
+#define LL_DCACHE_SR_ERRF DCACHE_SR_ERRF /*!< Cache error flag */
+#define LL_DCACHE_SR_BUSYF DCACHE_SR_BUSYF /*!< Busy flag */
+#define LL_DCACHE_SR_CMDENDF DCACHE_SR_CMDENDF /*!< Command end flag */
+#define LL_DCACHE_SR_BSYENDF DCACHE_SR_BSYENDF /*!< Full invalidate busy end flag */
+#define LL_DCACHE_SR_BUSYCMDF DCACHE_SR_BUSYCMDF /*!< Command busy flag */
+/**
+ * @}
+ */
+
+/** @defgroup DCACHE_LL_EC_CLEAR_FLAG Clear Flags Defines
+ * @brief Flags defines which can be used with LL_DCACHE_WriteReg function
+ * @{
+ */
+#define LL_DCACHE_FCR_CERRF DCACHE_FCR_CERRF /*!< Cache error flag */
+#define LL_DCACHE_FCR_CBSYENDF DCACHE_FCR_CBSYENDF /*!< Full invalidate busy end flag */
+#define LL_DCACHE_FCR_CCMDENDF DCACHE_FCR_CCMDENDF /*!< Command end flag*/
+/**
+ * @}
+ */
+
+/** @defgroup DCACHE_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_DCACHE_ReadReg and LL_DCACHE_WriteReg functions
+ * @{
+ */
+#define LL_DCACHE_IER_BSYENDIE DCACHE_IER_BSYENDIE /*!< Busy end interrupt */
+#define LL_DCACHE_IER_ERRIE DCACHE_IER_ERRIE /*!< Cache error interrupt */
+#define LL_DCACHE_IER_CMDENDIE DCACHE_IER_CMDENDIE /*!< Command end interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup DCACHE_Monitor_Type Monitor type
+ * @{
+ */
+#define LL_DCACHE_MONITOR_READ_HIT DCACHE_CR_RHITMEN /*!< Read Hit monitoring */
+#define LL_DCACHE_MONITOR_READ_MISS DCACHE_CR_RMISSMEN /*!< Read Miss monitoring */
+#define LL_DCACHE_MONITOR_WRITE_HIT DCACHE_CR_WHITMEN /*!< Write Hit monitoring */
+#define LL_DCACHE_MONITOR_WRITE_MISS DCACHE_CR_WMISSMEN /*!< Write Miss monitoring */
+#define LL_DCACHE_MONITOR_ALL (DCACHE_CR_RHITMEN | DCACHE_CR_RMISSMEN \
+ | DCACHE_CR_WHITMEN | DCACHE_CR_WMISSMEN)
+/**
+ * @}
+ */
+
+/* Exported macros --------------------------------------------------------*/
+/** @defgroup DCACHE_LL_Exported_Macros DCACHE Exported Macros
+ * @{
+ */
+
+/** @defgroup DCACHE_LL_EM_WRITE_READ Common write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in DCACHE register
+ * @param __INSTANCE__ DCACHE Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_DCACHE_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in DCACHE register
+ * @param __INSTANCE__ DCACHE Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_DCACHE_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DCACHE_LL_Exported_Functions DCACHE Exported Functions
+ * @{
+ */
+
+/** @defgroup DCACHE_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Enable the selected DCACHE instance.
+ * @rmtoll CR EN LL_DCACHE_Enable
+ * @param DCACHEx DCACHE instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DCACHE_Enable(DCACHE_TypeDef *DCACHEx)
+{
+ SET_BIT(DCACHEx->CR, DCACHE_CR_EN);
+}
+
+/**
+ * @brief Disable the selected DCACHE instance.
+ * @rmtoll CR EN LL_DCACHE_Disable
+ * @param DCACHEx DCACHE instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DCACHE_Disable(DCACHE_TypeDef *DCACHEx)
+{
+ CLEAR_BIT(DCACHEx->CR, DCACHE_CR_EN);
+}
+
+/**
+ * @brief Get the selected DCACHE instance enable state.
+ * @rmtoll CR EN LL_DCACHE_IsEnabled
+ * @param DCACHEx DCACHE instance
+ * @retval 0: DCACHE is disabled, 1: DCACHE is enabled.
+ */
+__STATIC_INLINE uint32_t LL_DCACHE_IsEnabled(DCACHE_TypeDef *DCACHEx)
+{
+ return ((READ_BIT(DCACHEx->CR, DCACHE_CR_EN) == (DCACHE_CR_EN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set the dcache instance start command address.
+ * @rmtoll CR CMDRSADDRR LL_DCACHE_SetStartAddress
+ * @param addr dcache command start address(Clean, Invalidate or Clean and Invalidate).
+ * @param DCACHEx DCACHE instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DCACHE_SetStartAddress(DCACHE_TypeDef *DCACHEx, uint32_t addr)
+{
+ WRITE_REG(DCACHEx->CMDRSADDRR, addr);
+}
+
+/**
+ * @brief Get the dcache command start address.
+ * @rmtoll CR CMDRSADDRR LL_DCACHE_GetStartAddress
+ * @param DCACHEx DCACHE instance
+ * @retval Start address of dcache command
+ */
+__STATIC_INLINE uint32_t LL_DCACHE_GetStartAddress(DCACHE_TypeDef *DCACHEx)
+{
+ return (uint32_t)(READ_REG(DCACHEx->CMDRSADDRR));
+}
+
+/**
+ * @brief Set the dcache instance End command address.
+ * @rmtoll CR CMDREADDRR LL_DCACHE_SetEndAddress
+ * @param DCACHEx DCACHE instance
+ * @param addr dcache command end address(Clean, Invalidate or Clean and Invalidate).
+ * @retval None
+ */
+__STATIC_INLINE void LL_DCACHE_SetEndAddress(DCACHE_TypeDef *DCACHEx, uint32_t addr)
+{
+ WRITE_REG(DCACHEx->CMDREADDRR, addr);
+}
+
+/**
+ * @brief Get the dcache command End address.
+ * @rmtoll CR CMDREADDRR LL_DCACHE_GetEndAddress
+ * @param DCACHEx DCACHE instance
+ * @retval End address of dcache command
+ */
+__STATIC_INLINE uint32_t LL_DCACHE_GetEndAddress(DCACHE_TypeDef *DCACHEx)
+{
+ return (uint32_t)(READ_REG(DCACHEx->CMDREADDRR));
+}
+
+/**
+ * @brief Set Dcache command.
+ * @rmtoll CR CACHECMD LL_DCACHE_SetCommand
+ * @param DCACHEx DCACHE instance
+ * @param Command command to be applied for the dcache
+ * LL_DCACHE_COMMAND_INVALIDATE_BY_ADDR, LL_DCACHE_COMMAND_CLEAN_BY_ADDR,
+ * LL_DCACHE_COMMAND_CLEAN_INVALIDATE_BY_ADDR,LL_DCACHE_COMMAND_NO_OPERATION
+ * @retval None
+ */
+__STATIC_INLINE void LL_DCACHE_SetCommand(DCACHE_TypeDef *DCACHEx, uint32_t Command)
+{
+ /* Set dcache command */
+ MODIFY_REG(DCACHEx->CR, DCACHE_CR_CACHECMD, Command);
+}
+
+/**
+ * @brief Set Dcache command.
+ * @rmtoll CR CACHECMD LL_DCACHE_GetCommand
+ * @param DCACHEx DCACHE instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DCACHE_COMMAND_NO_OPERATION
+ * @arg @ref LL_DCACHE_COMMAND_CLEAN_BY_ADDR
+ * @arg @ref LL_DCACHE_COMMAND_INVALIDATE_BY_ADDR
+ * @arg @ref LL_DCACHE_COMMAND_CLEAN_INVALIDATE_BY_ADDR
+ */
+__STATIC_INLINE uint32_t LL_DCACHE_GetCommand(DCACHE_TypeDef *DCACHEx)
+{
+ /*Get Dcache Command */
+ return (uint32_t)(READ_BIT(DCACHEx->CR, DCACHE_CR_CACHECMD));
+}
+
+/**
+ * @brief Launch Dcache Command.
+ * @rmtoll CR CACHECMD LL_DCACHE_StartCommand
+ * @param DCACHEx DCACHE instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DCACHE_StartCommand(DCACHE_TypeDef *DCACHEx)
+{
+ SET_BIT(DCACHEx->CR, DCACHE_CR_STARTCMD);
+}
+
+/**
+ * @brief Set requested read burst type.
+ * @rmtoll CR HBURST LL_DCACHE_SetReadBurstType
+ * @param DCACHEx DCACHE instance
+ * @param ReadBurstType Burst type to be applied for Data Cache
+ * LL_DCACHE_READ_BURST_WRAP, LL_DCACHE_READ_BURST_INCR.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DCACHE_SetReadBurstType(DCACHE_TypeDef *DCACHEx, uint32_t ReadBurstType)
+{
+ MODIFY_REG(DCACHEx->CR, DCACHE_CR_HBURST, ReadBurstType);
+}
+
+/**
+ * @brief Get requested read burst type.
+ * @rmtoll CR HBURST LL_DCACHE_GetReadBurstType
+ * @param DCACHEx DCACHE instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DCACHE_READ_BURST_WRAP
+ * @arg @ref LL_DCACHE_READ_BURST_INCR
+ */
+__STATIC_INLINE uint32_t LL_DCACHE_GetReadBurstType(DCACHE_TypeDef *DCACHEx)
+{
+ return (uint32_t)(READ_BIT(DCACHEx->CR, DCACHE_CR_HBURST));
+}
+
+/**
+ * @brief Invalidate the Data cache.
+ * @rmtoll CR CACHEINV LL_DCACHE_Invalidate
+ * @param DCACHEx DCACHE instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DCACHE_Invalidate(DCACHE_TypeDef *DCACHEx)
+{
+ SET_BIT(DCACHEx->CR, DCACHE_CR_CACHEINV);
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup DCACHE_LL_EF_Monitor Monitor
+ * @{
+ */
+
+/**
+ * @brief Enable the hit/miss monitor(s).
+ * @rmtoll CR (RMISSMEN/RHITMEN/WMISSMEN/WHITMEN) LL_DCACHE_EnableMonitors
+ * @param DCACHEx DCACHE instance
+ * @param Monitors This parameter can be one or a combination of the following values:
+ * @arg LL_DCACHE_MONITOR_READ_HIT
+ * @arg LL_DCACHE_MONITOR_READ_MISS
+ * @arg LL_DCACHE_MONITOR_WRITE_HIT
+ * @arg LL_DCACHE_MONITOR_WRITE_MISS
+ * @arg LL_DCACHE_MONITOR_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_DCACHE_EnableMonitors(DCACHE_TypeDef *DCACHEx, uint32_t Monitors)
+{
+ SET_BIT(DCACHEx->CR, Monitors);
+}
+
+/**
+ * @brief Disable the hit/miss monitor(s).
+ * @rmtoll CR (RMISSMEN/RHITMEN/WMISSMEN/WHITMEN) LL_DCACHE_DisableMonitors
+ * @param DCACHEx DCACHE instance
+ * @param Monitors This parameter can be one or a combination of the following values:
+ * @arg LL_DCACHE_MONITOR_READ_HIT
+ * @arg LL_DCACHE_MONITOR_READ_MISS
+ * @arg LL_DCACHE_MONITOR_WRITE_HIT
+ * @arg LL_DCACHE_MONITOR_WRITE_MISS
+ * @arg LL_DCACHE_MONITOR_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_DCACHE_DisableMonitors(DCACHE_TypeDef *DCACHEx, uint32_t Monitors)
+{
+ CLEAR_BIT(DCACHEx->CR, Monitors);
+}
+
+/**
+ * @brief Return the hit/miss monitor(s) enable state.
+ * @rmtoll CR (RMISSMEN/RHITMEN/WMISSMEN/WHITMEN) LL_DCACHE_IsEnabledMonitors
+ * @param DCACHEx DCACHE instance
+ * @param Monitors This parameter can be one or a combination of the following values:
+ * @arg LL_DCACHE_MONITOR_READ_HIT
+ * @arg LL_DCACHE_MONITOR_READ_MISS
+ * @arg LL_DCACHE_MONITOR_WRITE_HIT
+ * @arg LL_DCACHE_MONITOR_WRITE_MISS
+ * @arg LL_DCACHE_MONITOR_ALL
+ * @retval State of parameter value (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DCACHE_IsEnabledMonitors(DCACHE_TypeDef *DCACHEx, uint32_t Monitors)
+{
+ return (((READ_BIT(DCACHEx->CR, (DCACHE_CR_WMISSMEN | DCACHE_CR_WHITMEN | DCACHE_CR_RMISSMEN | DCACHE_CR_RHITMEN))\
+ & Monitors) == (Monitors)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Reset the Data Cache performance monitoring.
+ * @rmtoll CR (RHITMRST/RMISSMRST/WHITMRST/WMISSMRST) LL_DCACHE_ResetMonitors
+ * @param DCACHEx DCACHE instance
+ * @param Monitors Monitoring type
+ * This parameter can be a combination of the following values:
+ * @arg LL_DCACHE_MONITOR_READ_HIT
+ * @arg LL_DCACHE_MONITOR_READ_MISS
+ * @arg LL_DCACHE_MONITOR_WRITE_HIT
+ * @arg LL_DCACHE_MONITOR_WRITE_MISS
+ * @arg LL_DCACHE_MONITOR_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_DCACHE_ResetMonitors(DCACHE_TypeDef *DCACHEx, uint32_t Monitors)
+{
+ /* Reset */
+ SET_BIT(DCACHEx->CR, (Monitors << 2U));
+
+ /* Release reset */
+ CLEAR_BIT(DCACHEx->CR, (Monitors << 2U));
+}
+
+/**
+ * @brief Get the Read Hit monitor Value
+ * @rmtoll RHMONR LL_DCACHE_Monitor_GetReadHitValue
+ * @param DCACHEx DCACHE instance
+ * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetReadHitValue(DCACHE_TypeDef *DCACHEx)
+{
+ return DCACHEx->RHMONR;
+}
+
+/**
+ * @brief Get the Read Miss monitor Value
+ * @rmtoll RMMONR LL_DCACHE_Monitor_GetReadMissValue
+ * @param DCACHEx DCACHE instance
+ * @retval Value between Min_Data=0 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetReadMissValue(DCACHE_TypeDef *DCACHEx)
+{
+ return DCACHEx->RMMONR;
+}
+
+/**
+ * @brief Get the Write Hit monitor Value
+ * @rmtoll WHMONR LL_DCACHE_Monitor_GetWriteHitValue
+ * @param DCACHEx DCACHE instance
+ * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetWriteHitValue(DCACHE_TypeDef *DCACHEx)
+{
+ return DCACHEx->WHMONR;
+}
+
+/**
+ * @brief Get the Write Miss monitor Value
+ * @rmtoll WMMONR LL_DCACHE_Monitor_GetWriteMissValue
+ * @param DCACHEx DCACHE instance
+ * @retval Value between Min_Data=0 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetWriteMissValue(DCACHE_TypeDef *DCACHEx)
+{
+ return DCACHEx->WMMONR;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DCACHE_LL_EF_IT_Management IT-Management
+ * @{
+ */
+
+/**
+ * @brief Enable BusyEnd interrupt.
+ * @rmtoll IER BSYENDIE LL_DCACHE_EnableIT_BSYEND
+ * @param DCACHEx DCACHE instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DCACHE_EnableIT_BSYEND(DCACHE_TypeDef *DCACHEx)
+{
+ SET_BIT(DCACHEx->IER, DCACHE_IER_BSYENDIE);
+}
+
+/**
+ * @brief Disable BusyEnd interrupt.
+ * @rmtoll IER BSYENDIE LL_DCACHE_DisableIT_BSYEND
+ * @param DCACHEx DCACHE instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DCACHE_DisableIT_BSYEND(DCACHE_TypeDef *DCACHEx)
+{
+ CLEAR_BIT(DCACHEx->IER, DCACHE_IER_BSYENDIE);
+}
+
+/**
+ * @brief Indicates whether the Busyend interrupt is enabled.
+ * @rmtoll IER BSYENDIE LL_DCACHE_IsEnabledIT_BSYEND
+ * @param DCACHEx DCACHE instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DCACHE_IsEnabledIT_BSYEND(DCACHE_TypeDef *DCACHEx)
+{
+ return ((READ_BIT(DCACHEx->IER, DCACHE_IER_BSYENDIE) == (DCACHE_IER_BSYENDIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable Error interrupt.
+ * @rmtoll IER ERRIE LL_DCACHE_EnableIT_ERR
+ * @param DCACHEx DCACHE instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DCACHE_EnableIT_ERR(DCACHE_TypeDef *DCACHEx)
+{
+ SET_BIT(DCACHEx->IER, DCACHE_IER_ERRIE);
+}
+
+/**
+ * @brief Disable Error interrupt.
+ * @rmtoll IER ERRIE LL_DCACHE_DisableIT_ERR
+ * @param DCACHEx DCACHE instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DCACHE_DisableIT_ERR(DCACHE_TypeDef *DCACHEx)
+{
+ CLEAR_BIT(DCACHEx->IER, DCACHE_IER_ERRIE);
+}
+
+/**
+ * @brief Indicates whether the Error interrupt is enabled.
+ * @rmtoll IER ERRIE LL_DCACHE_IsEnabledIT_ERR
+ * @param DCACHEx DCACHE instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DCACHE_IsEnabledIT_ERR(DCACHE_TypeDef *DCACHEx)
+{
+ return ((READ_BIT(DCACHEx->IER, DCACHE_IER_ERRIE) == (DCACHE_IER_ERRIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable command end interrupt.
+ * @rmtoll IER CMDENDIE LL_DCACHE_EnableIT_CMDEND
+ * @param DCACHEx DCACHE instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DCACHE_EnableIT_CMDEND(DCACHE_TypeDef *DCACHEx)
+{
+ SET_BIT(DCACHEx->IER, DCACHE_IER_CMDENDIE);
+}
+
+/**
+ * @brief Disable command end interrupt.
+ * @rmtoll IER CMDENDIE LL_DCACHE_DisableIT_CMDEND
+ * @param DCACHEx DCACHE instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DCACHE_DisableIT_CMDEND(DCACHE_TypeDef *DCACHEx)
+{
+ CLEAR_BIT(DCACHEx->IER, DCACHE_IER_CMDENDIE);
+}
+
+/**
+ * @brief Indicates whether the command end interrupt is enabled.
+ * @rmtoll IER CMDENDIE LL_DCACHE_IsEnabledIT_CMDEND
+ * @param DCACHEx DCACHE instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DCACHE_IsEnabledIT_CMDEND(DCACHE_TypeDef *DCACHEx)
+{
+ return ((READ_BIT(DCACHEx->IER, DCACHE_IER_CMDENDIE) == (DCACHE_IER_CMDENDIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear full invalidate busy end flag.
+ * @rmtoll FCR CBSYENDF LL_DCACHE_ClearFlag_BSYEND
+ * @param DCACHEx DCACHE instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DCACHE_ClearFlag_BSYEND(DCACHE_TypeDef *DCACHEx)
+{
+ WRITE_REG(DCACHEx->FCR, DCACHE_FCR_CBSYENDF);
+}
+
+/**
+ * @brief Clear cache error flag.
+ * @rmtoll FCR CERRF LL_DCACHE_ClearFlag_ERR
+ * @param DCACHEx DCACHE instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DCACHE_ClearFlag_ERR(DCACHE_TypeDef *DCACHEx)
+{
+ WRITE_REG(DCACHEx->FCR, DCACHE_FCR_CERRF);
+}
+
+/**
+ * @brief Clear command end flag.
+ * @rmtoll FCR CCMDENDF LL_DCACHE_ClearFlag_CMDEND
+ * @param DCACHEx DCACHE instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DCACHE_ClearFlag_CMDEND(DCACHE_TypeDef *DCACHEx)
+{
+ WRITE_REG(DCACHEx->FCR, DCACHE_FCR_CCMDENDF);
+}
+
+/**
+ * @brief Get flag Dcache BUSY.
+ * @rmtoll SR BUSYF LL_DCACHE_IsActiveFlag_BUSY
+ * @param DCACHEx DCACHE instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DCACHE_IsActiveFlag_BUSY(DCACHE_TypeDef *DCACHEx)
+{
+ return ((READ_BIT(DCACHEx->SR, DCACHE_SR_BUSYF) == (DCACHE_SR_BUSYF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag Dcache Busyend.
+ * @rmtoll SR BSYENDF LL_DCACHE_IsActiveFlag_BSYEND
+ * @param DCACHEx DCACHE instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DCACHE_IsActiveFlag_BSYEND(DCACHE_TypeDef *DCACHEx)
+{
+ return ((READ_BIT(DCACHEx->SR, DCACHE_SR_BSYENDF) == (DCACHE_SR_BSYENDF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag Dcache Error.
+ * @rmtoll SR ERRF LL_DCACHE_IsActiveFlag_ERR
+ * @param DCACHEx DCACHE instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DCACHE_IsActiveFlag_ERR(DCACHE_TypeDef *DCACHEx)
+{
+ return ((READ_BIT(DCACHEx->SR, DCACHE_SR_ERRF) == (DCACHE_SR_ERRF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag Dcache Busy command.
+ * @rmtoll SR BUSYCMDF LL_DCACHE_IsActiveFlag_BUSYCMD
+ * @param DCACHEx DCACHE instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DCACHE_IsActiveFlag_BUSYCMD(DCACHE_TypeDef *DCACHEx)
+{
+ return ((READ_BIT(DCACHEx->SR, DCACHE_SR_BUSYCMDF) == (DCACHE_SR_BUSYCMDF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag Dcache command end.
+ * @rmtoll SR CMDENDF LL_DCACHE_IsActiveFlag_CMDEND
+ * @param DCACHEx DCACHE instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DCACHE_IsActiveFlag_CMDEND(DCACHE_TypeDef *DCACHEx)
+{
+ return ((READ_BIT(DCACHEx->SR, DCACHE_SR_CMDENDF) == (DCACHE_SR_CMDENDF)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(DCACHE1) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_LL_DCACHE_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dlyb.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dlyb.h
new file mode 100644
index 00000000..1c9494e0
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dlyb.h
@@ -0,0 +1,150 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_dlyb.h
+ * @author MCD Application Team
+ * @brief Header file of DelayBlock module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_LL_DLYB_H
+#define STM32U5xx_LL_DLYB_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_QSPI_MODULE_ENABLED)|| defined(HAL_OSPI_MODULE_ENABLED)
+
+/** @addtogroup DLYB
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DLYB_LL_Exported_Types DLYB Exported Types
+ * @{
+ */
+
+/**
+ * @brief DLYB Configuration Structure definition
+ */
+
+typedef struct
+{
+ uint32_t Units; /*!< Specifies the Delay of a unit delay cell.
+ This parameter can be a value between 0 and DLYB_MAX_UNIT */
+
+ uint32_t PhaseSel; /*!< Specifies the Phase for the output clock.
+ This parameter can be a value between 0 and DLYB_MAX_SELECT */
+} LL_DLYB_CfgTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DLYB_Exported_Constants DLYB Exported Constants
+ * @{
+ */
+
+#define DLYB_MAX_UNIT ((uint32_t)0x00000080U) /*!< Max UNIT value (128) */
+#define DLYB_MAX_SELECT ((uint32_t)0x0000000CU) /*!< Max SELECT value (12) */
+
+/** @defgroup DLYB_LL_Flags DLYB Flags
+ * @{
+ */
+
+#define DLYB_FLAG_LNGF DLYB_CFGR_LNGF
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup DLYB_LL_Exported_Functions DLYB Exported Functions
+ * @{
+ */
+
+/** @defgroup DLYB_LL_Configuration Configuration functions
+ * @{
+ */
+
+/**
+ * @brief DLYB Enable
+ * @param DLYBx DLYB Instance
+ * @retval None
+ */
+
+__STATIC_INLINE void LL_DLYB_Enable(DLYB_TypeDef *DLYBx)
+{
+ SET_BIT(DLYBx->CR, DLYB_CR_DEN);
+}
+
+/** @brief Disable the DLYB.
+ * @param DLYBx DLYB Instance.
+ * @retval None
+ */
+
+__STATIC_INLINE void LL_DLYB_Disable(DLYB_TypeDef *DLYBx)
+{
+ CLEAR_BIT(DLYBx->CR, DLYB_CR_DEN);
+}
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup DLYB_Control_Functions DLYB Control functions
+ * @{
+ */
+
+void LL_DLYB_SetDelay(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg);
+void LL_DLYB_GetDelay(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg);
+uint32_t LL_DLYB_GetClockPeriod(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_SD_MODULE_ENABLED || HAL_QSPI_MODULE_ENABLED || HAL_OSPI_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_LL_DLYB_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dma.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dma.h
new file mode 100644
index 00000000..27a996e0
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dma.h
@@ -0,0 +1,6809 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_dma.h
+ * @author MCD Application Team
+ * @brief Header file of DMA LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### LL DMA driver acronyms #####
+ ==============================================================================
+ [..] Acronyms table :
+ =========================================
+ || Acronym || ||
+ =========================================
+ || SRC || Source ||
+ || DEST || Destination ||
+ || ADDR || Address ||
+ || ADDRS || Addresses ||
+ || INC || Increment / Incremented ||
+ || DEC || Decrement / Decremented ||
+ || BLK || Block ||
+ || RPT || Repeat / Repeated ||
+ || TRIG || Trigger ||
+ =========================================
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_LL_DMA_H
+#define STM32U5xx_LL_DMA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx.h"
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if (defined (GPDMA1) || defined (LPDMA1))
+
+/** @defgroup DMA_LL DMA
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/** @defgroup DMA_LL_Private_Variables DMA Private Variables
+ * @{
+ */
+#define DMA_CHANNEL0_OFFSET (0x00000050UL)
+#define DMA_CHANNEL1_OFFSET (0x000000D0UL)
+#define DMA_CHANNEL2_OFFSET (0x00000150UL)
+#define DMA_CHANNEL3_OFFSET (0x000001D0UL)
+#define DMA_CHANNEL4_OFFSET (0x00000250UL)
+#define DMA_CHANNEL5_OFFSET (0x000002D0UL)
+#define DMA_CHANNEL6_OFFSET (0x00000350UL)
+#define DMA_CHANNEL7_OFFSET (0x000003D0UL)
+#define DMA_CHANNEL8_OFFSET (0x00000450UL)
+#define DMA_CHANNEL9_OFFSET (0x000004D0UL)
+#define DMA_CHANNEL10_OFFSET (0x00000550UL)
+#define DMA_CHANNEL11_OFFSET (0x000005D0UL)
+#define DMA_CHANNEL12_OFFSET (0x00000650UL)
+#define DMA_CHANNEL13_OFFSET (0x000006D0UL)
+#define DMA_CHANNEL14_OFFSET (0x00000750UL)
+#define DMA_CHANNEL15_OFFSET (0x000007D0UL)
+
+/* Array used to get the DMA Channel register offset versus Channel index LL_DMA_CHANNEL_x */
+static const uint32_t LL_DMA_CH_OFFSET_TAB[] =
+{
+ DMA_CHANNEL0_OFFSET, DMA_CHANNEL1_OFFSET, DMA_CHANNEL2_OFFSET, DMA_CHANNEL3_OFFSET,
+ DMA_CHANNEL4_OFFSET, DMA_CHANNEL5_OFFSET, DMA_CHANNEL6_OFFSET, DMA_CHANNEL7_OFFSET,
+ DMA_CHANNEL8_OFFSET, DMA_CHANNEL9_OFFSET, DMA_CHANNEL10_OFFSET, DMA_CHANNEL11_OFFSET,
+ DMA_CHANNEL12_OFFSET, DMA_CHANNEL13_OFFSET, DMA_CHANNEL14_OFFSET, DMA_CHANNEL15_OFFSET,
+};
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+
+#if defined (USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief LL DMA init structure definition.
+ */
+typedef struct
+{
+ uint32_t SrcAddress; /*!< This field specify the data transfer source address.
+ Programming this field is mandatory for all available DMA channels.
+ This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
+ This feature can be modified afterwards using unitary function
+ @ref LL_DMA_SetSrcAddress(). */
+
+ uint32_t DestAddress; /*!< This field specify the data transfer destination address.
+ Programming this field is mandatory for all available DMA channels.
+ This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
+ This feature can be modified afterwards using unitary function
+ @ref LL_DMA_SetDestAddress(). */
+
+ uint32_t Direction; /*!< This field specify the data transfer direction.
+ Programming this field is mandatory for all available DMA channels.
+ This parameter can be a value of @ref DMA_LL_EC_TRANSFER_DIRECTION.
+ This feature can be modified afterwards using unitary function
+ @ref LL_DMA_SetDataTransferDirection(). */
+
+ uint32_t BlkHWRequest; /*!< This field specify the hardware request unity.
+ Programming this field is mandatory for all available DMA channels.
+ This parameter can be a value of @ref DMA_LL_EC_BLKHW_REQUEST.
+ This feature can be modified afterwards using unitary function
+ @ref LL_DMA_SetBlkHWRequest(). */
+
+ uint32_t DataAlignment; /*!< This field specify the transfer data alignment.
+ Programming this field is mandatory for all available DMA channels.
+ This parameter can be a value of @ref DMA_LL_EC_DATA_ALIGNMENT.
+ This feature can be modified afterwards using unitary function
+ @ref LL_DMA_SetDataAlignment(). */
+
+ uint32_t SrcBurstLength; /*!< This field specify the source burst length of transfer in bytes.
+ Programming this field is not mandatory for LPDMA channels.
+ This parameter must be a value between Min_Data = 1 and Max_Data = 64.
+ This feature can be modified afterwards using unitary function
+ @ref LL_DMA_SetSrcBurstLength(). */
+
+ uint32_t DestBurstLength; /*!< This field specify the destination burst length of transfer in bytes.
+ Programming this field is not mandatory for LPDMA channels.
+ This parameter must be a value between Min_Data = 1 and Max_Data = 64.
+ This feature can be modified afterwards using unitary function
+ @ref LL_DMA_SetDestBurstLength(). */
+
+ uint32_t SrcDataWidth; /*!< This field specify the source data width.
+ Programming this field is mandatory for all available DMA channels.
+ This parameter can be a value of @ref DMA_LL_EC_SOURCE_DATA_WIDTH.
+ This feature can be modified afterwards using unitary function
+ @ref LL_DMA_SetSrcDataWidth(). */
+
+ uint32_t DestDataWidth; /*!< This field specify the destination data width.
+ Programming this field is mandatory for all available DMA channels.
+ This parameter can be a value of @ref DMA_LL_EC_DESTINATION_DATA_WIDTH.
+ This feature can be modified afterwards using unitary function
+ @ref LL_DMA_SetDestDataWidth(). */
+
+ uint32_t SrcIncMode; /*!< This field specify the source burst increment mode.
+ Programming this field is mandatory for all available DMA channels.
+ This parameter can be a value of @ref DMA_LL_EC_SOURCE_INCREMENT_MODE.
+ This feature can be modified afterwards using unitary function
+ @ref LL_DMA_SetSrcIncMode(). */
+
+ uint32_t DestIncMode; /*!< This field specify the destination burst increment mode.
+ Programming this field is mandatory for all available DMA channels.
+ This parameter can be a value of @ref DMA_LL_EC_DESTINATION_INCREMENT_MODE.
+ This feature can be modified afterwards using unitary function
+ @ref LL_DMA_SetDestIncMode(). */
+
+ uint32_t Priority; /*!< This field specify the channel priority level.
+ Programming this field is mandatory for all available DMA channels.
+ This parameter can be a value of @ref DMA_LL_EC_PRIORITY_LEVEL.
+ This feature can be modified afterwards using unitary function
+ @ref LL_DMA_SetChannelPriorityLevel(). */
+
+ uint32_t BlkDataLength; /*!< This field specify the length of a block transfer in bytes.
+ Programming this field is mandatory for all available DMA channels.
+ This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF.
+ This feature can be modified afterwards using unitary function
+ @ref LL_DMA_SetBlkDataLength(). */
+
+ uint32_t BlkRptCount; /*!< This field specify the number of repetitions of the current block.
+ Programming this field is mandatory only for 2D addressing channels.
+ This parameter can be a value between 1 and 2048 Min_Data = 0
+ and Max_Data = 0x000007FF.
+ This feature can be modified afterwards using unitary function
+ @ref LL_DMA_SetBlkRptCount(). */
+
+ uint32_t TriggerMode; /*!< This field specify the trigger mode.
+ Programming this field is mandatory for all available DMA channels.
+ This parameter can be a value of @ref DMA_LL_EC_TRIGGER_MODE.
+ This feature can be modified afterwards using unitary function
+ @ref LL_DMA_SetTriggerMode(). */
+
+ uint32_t TriggerPolarity; /*!< This field specify the trigger event polarity.
+ Programming this field is mandatory for all available DMA channels.
+ This parameter can be a value of @ref DMA_LL_EC_TRIGGER_POLARITY.
+ This feature can be modified afterwards using unitary function
+ @ref LL_DMA_SetTriggerPolarity(). */
+
+ uint32_t TriggerSelection; /*!< This field specify the trigger event selection.
+ Programming this field is mandatory for all available DMA channels.
+ This parameter can be a value of @ref DMA_LL_EC_TRIGGER_SELECTION.
+ This feature can be modified afterwards using unitary function
+ @ref LL_DMA_SetHWTrigger(). */
+
+ uint32_t Request; /*!< This field specify the peripheral request selection.
+ Programming this field is mandatory for all available DMA channels.
+ This parameter can be a value of @ref DMA_LL_EC_REQUEST_SELECTION.
+ This feature can be modified afterwards using unitary function
+ @ref LL_DMA_SetPeriphRequest(). */
+
+ uint32_t TransferEventMode; /*!< This field specify the transfer event mode.
+ Programming this field is mandatory for all available DMA channels.
+ This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE.
+ This feature can be modified afterwards using unitary function
+ @ref LL_DMA_SetTransferEventMode(). */
+
+ uint32_t DestHWordExchange; /*!< This field specify the destination half word exchange.
+ Programming this field is not mandatory for LPDMA channels.
+ This parameter can be a value of @ref DMA_LL_EC_DEST_HALFWORD_EXCHANGE.
+ This feature can be modified afterwards using unitary function
+ @ref LL_DMA_SetDestHWordExchange(). */
+
+ uint32_t DestByteExchange; /*!< This field specify the destination byte exchange.
+ Programming this field is not mandatory for LPDMA channels.
+ This parameter can be a value of @ref DMA_LL_EC_DEST_BYTE_EXCHANGE.
+ This feature can be modified afterwards using unitary function
+ @ref LL_DMA_SetDestByteExchange(). */
+
+ uint32_t SrcByteExchange; /*!< This field specify the source byte exchange.
+ Programming this field is not mandatory for LPDMA channels.
+ This parameter can be a value of @ref DMA_LL_EC_SRC_BYTE_EXCHANGE.
+ This feature can be modified afterwards using unitary function
+ @ref LL_DMA_SetSrcByteExchange(). */
+
+ uint32_t SrcAllocatedPort; /*!< This field specify the source allocated port.
+ Programming this field is not mandatory for LPDMA channels.
+ This parameter can be a value of @ref DMA_LL_EC_SOURCE_ALLOCATED_PORT.
+ This feature can be modified afterwards using unitary function
+ @ref LL_DMA_SetSrcAllocatedPort(). */
+
+ uint32_t DestAllocatedPort; /*!< This field specify the destination allocated port.
+ Programming this field is not mandatory for LPDMA channels.
+ This parameter can be a value of @ref DMA_LL_EC_DESTINATION_ALLOCATED_PORT.
+ This feature can be modified afterwards using unitary function
+ @ref LL_DMA_SetDestAllocatedPort(). */
+
+ uint32_t LinkAllocatedPort; /*!< This field specify the linked-list allocated port.
+ Programming this field is not mandatory for LPDMA channels.
+ This parameter can be a value of @ref DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT.
+ This feature can be modified afterwards using unitary function
+ @ref LL_DMA_SetLinkAllocatedPort(). */
+
+ uint32_t LinkStepMode; /*!< This field specify the link step mode.
+ Programming this field is mandatory for all available DMA channels.
+ This parameter can be a value of @ref DMA_LL_EC_LINK_STEP_MODE.
+ This feature can be modified afterwards using unitary function
+ @ref LL_DMA_SetLinkStepMode(). */
+
+ uint32_t SrcAddrUpdateMode; /*!< This field specify the source address update mode.
+ Programming this field is mandatory only for 2D addressing channels.
+ This parameter can be a value of @ref DMA_LL_EC_SRC_ADDR_UPDATE_MODE.
+ This feature can be modified afterwards using unitary function
+ @ref LL_DMA_SetSrcAddrUpdate(). */
+
+ uint32_t DestAddrUpdateMode; /*!< This field specify the destination address update mode.
+ Programming this field is mandatory only for 2D addressing channels.
+ This parameter can be a value of @ref DMA_LL_EC_DEST_ADDR_UPDATE_MODE.
+ This feature can be modified afterwards using unitary function
+ @ref LL_DMA_SetDestAddrUpdate(). */
+
+ uint32_t SrcAddrOffset; /*!< This field specifies the source address offset.
+ Programming this field is mandatory only for 2D addressing channels.
+ This parameter can be a value Between 0 to 0x00001FFF.
+ This feature can be modified afterwards using unitary function
+ @ref LL_DMA_SetSrcAddrUpdateValue(). */
+
+ uint32_t DestAddrOffset; /*!< This field specifies the destination address offset.
+ Programming this field is mandatory only for 2D addressing channels.
+ This parameter can be a value Between 0 to 0x00001FFF.
+ This feature can be modified afterwards using unitary function
+ @ref LL_DMA_SetDestAddrUpdateValue(). */
+
+ uint32_t BlkRptSrcAddrUpdateMode; /*!< This field specifies the block repeat source address update mode.
+ Programming this field is mandatory only for 2D addressing channels.
+ This parameter can be a value of @ref DMA_LL_EC_BLK_RPT_SRC_ADDR_UPDATE_MODE.
+ This feature can be modified afterwards using unitary function
+ @ref LL_DMA_SetBlkRptSrcAddrUpdate(). */
+
+ uint32_t BlkRptDestAddrUpdateMode; /*!< This field specifies the block repeat destination address update mode.
+ Programming this field is mandatory only for 2D addressing channels.
+ This parameter can be a value of @ref DMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE.
+ This feature can be modified afterwards using unitary function
+ @ref LL_DMA_SetBlkRptDestAddrUpdate(). */
+
+ uint32_t BlkRptSrcAddrOffset; /*!< This field specifies the block repeat source address offset.
+ Programming this field is mandatory only for 2D addressing channels.
+ This parameter can be a value Between 0 to 0x0000FFFF.
+ This feature can be modified afterwards using unitary function
+ @ref LL_DMA_SetBlkRptSrcAddrUpdateValue(). */
+
+ uint32_t BlkRptDestAddrOffset; /*!< This field specifies the block repeat destination address offset.
+ Programming this field is mandatory only for 2D addressing channels.
+ This parameter can be a value Between 0 to 0x0000FFFF.
+ This feature can be modified afterwards using unitary function
+ @ref LL_DMA_SetBlkRptDestAddrUpdateValue(). */
+
+ uint32_t LinkedListBaseAddr; /*!< This field specify the linked list base address.
+ Programming this field is mandatory for all available DMA channels.
+ This parameter can be a value Between 0 to 0xFFFF0000 (where the 4 first
+ bytes are always forced to 0).
+ This feature can be modified afterwards using unitary function
+ @ref LL_DMA_SetLinkedListBaseAddr(). */
+
+ uint32_t LinkedListAddrOffset; /*!< Specifies the linked list address offset.
+ Programming this field is mandatory for all available DMA channels.
+ This parameter can be a value Between 0 to 0x0000FFFC.
+ This feature can be modified afterwards using unitary function
+ @ref LL_DMA_SetLinkedListAddrOffset(). */
+} LL_DMA_InitTypeDef;
+
+
+/**
+ * @brief LL DMA init linked list structure definition.
+ */
+typedef struct
+{
+ uint32_t Priority; /*!< This field specify the channel priority level.
+ Programming this field is mandatory for all available DMA channels.
+ This parameter can be a value of @ref DMA_LL_EC_PRIORITY_LEVEL.
+ This feature can be modified afterwards using unitary function
+ @ref LL_DMA_SetChannelPriorityLevel(). */
+
+ uint32_t LinkStepMode; /*!< This field specify the link step mode.
+ Programming this field is mandatory for all available DMA channels.
+ This parameter can be a value of @ref DMA_LL_EC_LINK_STEP_MODE.
+ This feature can be modified afterwards using unitary function
+ @ref LL_DMA_SetLinkStepMode(). */
+
+ uint32_t LinkAllocatedPort; /*!< This field specify the linked-list allocated port.
+ Programming this field is not mandatory for LPDMA channels.
+ This parameter can be a value of @ref DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT.
+ This feature can be modified afterwards using unitary function
+ @ref LL_DMA_SetLinkAllocatedPort(). */
+
+ uint32_t TransferEventMode; /*!< This field specify the transfer event mode.
+ Programming this field is mandatory for all available DMA channels.
+ This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE.
+ This feature can be modified afterwards using unitary function
+ @ref LL_DMA_SetTransferEventMode(). */
+} LL_DMA_InitLinkedListTypeDef;
+
+
+/**
+ * @brief LL DMA node init structure definition.
+ */
+typedef struct
+{
+ /* CTR1 register fields ******************************************************
+ If any CTR1 fields need to be updated comparing to previous node, it is
+ mandatory to update the new value in CTR1 register fields and enable update
+ CTR1 register in UpdateRegisters fields if it is not enabled in the
+ previous node.
+
+ If the node to be created is for LPDMA channels, there is no need to fill
+ the following fields for CTR1 register :
+ - DestAllocatedPort.
+ - DestHWordExchange.
+ - DestByteExchange.
+ - DestBurstLength.
+ - SrcAllocatedPort.
+ - SrcByteExchange.
+ - SrcBurstLength.
+ */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ uint32_t DestSecure; /*!< This field specify the destination secure.
+ This parameter can be a value of @ref DMA_LL_EC_DESTINATION_SECURITY_ATTRIBUTE. */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+ uint32_t DestAllocatedPort; /*!< This field specify the destination allocated port.
+ This parameter can be a value of @ref DMA_LL_EC_DESTINATION_ALLOCATED_PORT. */
+
+ uint32_t DestHWordExchange; /*!< This field specify the destination half word exchange.
+ This parameter can be a value of @ref DMA_LL_EC_DEST_HALFWORD_EXCHANGE. */
+
+ uint32_t DestByteExchange; /*!< This field specify the destination byte exchange.
+ This parameter can be a value of @ref DMA_LL_EC_DEST_BYTE_EXCHANGE. */
+
+ uint32_t DestBurstLength; /*!< This field specify the destination burst length of transfer in bytes.
+ This parameter must be a value between Min_Data = 1 and Max_Data = 64. */
+
+ uint32_t DestIncMode; /*!< This field specify the destination increment mode.
+ This parameter can be a value of @ref DMA_LL_EC_DESTINATION_INCREMENT_MODE. */
+
+ uint32_t DestDataWidth; /*!< This field specify the destination data width.
+ This parameter can be a value of @ref DMA_LL_EC_DESTINATION_DATA_WIDTH. */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ uint32_t SrcSecure; /*!< This field specify the source secure.
+ This parameter can be a value of @ref DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE. */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+ uint32_t SrcAllocatedPort; /*!< This field specify the source allocated port.
+ This parameter can be a value of @ref DMA_LL_EC_SOURCE_ALLOCATED_PORT. */
+
+ uint32_t SrcByteExchange; /*!< This field specify the source byte exchange.
+ This parameter can be a value of @ref DMA_LL_EC_SRC_BYTE_EXCHANGE. */
+
+ uint32_t DataAlignment; /*!< This field specify the transfer data alignment.
+ This parameter can be a value of @ref DMA_LL_EC_DATA_ALIGNMENT. */
+
+ uint32_t SrcBurstLength; /*!< This field specify the source burst length of transfer in bytes.
+ This parameter must be a value between Min_Data = 1 and Max_Data = 64. */
+
+ uint32_t SrcIncMode; /*!< This field specify the source increment mode.
+ This parameter can be a value of @ref DMA_LL_EC_SOURCE_INCREMENT_MODE. */
+
+ uint32_t SrcDataWidth; /*!< This field specify the source data width.
+ This parameter can be a value of @ref DMA_LL_EC_SOURCE_DATA_WIDTH. */
+
+
+ /* CTR2 register fields ******************************************************
+ If any CTR2 fields need to be updated comparing to previous node, it is
+ mandatory to update the new value in CTR2 register fields and enable update
+ CTR2 register in UpdateRegisters fields if it is not enabled in the
+ previous node.
+
+ For all node created, filling all fields is mandatory.
+ */
+ uint32_t TransferEventMode; /*!< This field specify the transfer event mode.
+ This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE. */
+
+ uint32_t TriggerPolarity; /*!< This field specify the trigger event polarity.
+ This parameter can be a value of @ref DMA_LL_EC_TRIGGER_POLARITY. */
+
+ uint32_t TriggerSelection; /*!< This field specify the trigger event selection.
+ This parameter can be a value of @ref DMA_LL_EC_TRIGGER_SELECTION. */
+
+ uint32_t TriggerMode; /*!< This field specify the trigger mode.
+ This parameter can be a value of @ref DMA_LL_EC_TRIGGER_MODE. */
+
+ uint32_t BlkHWRequest; /*!< This field specify the hardware request unity.
+ This parameter can be a value of @ref DMA_LL_EC_BLKHW_REQUEST. */
+
+ uint32_t Direction; /*!< This field specify the transfer direction.
+ This parameter can be a value of @ref DMA_LL_EC_TRANSFER_DIRECTION. */
+
+ uint32_t Request; /*!< This field specify the peripheral request selection.
+ This parameter can be a value of @ref DMA_LL_EC_REQUEST_SELECTION. */
+
+
+ /* CBR1 register fields ******************************************************
+ If any CBR1 fields need to be updated comparing to previous node, it is
+ mandatory to update the new value in CBR1 register fields and enable update
+ CBR1 register in UpdateRegisters fields if it is not enabled in the
+ previous node.
+
+ If the node to be created is not for 2D addressing channels, there is no
+ need to fill the following fields for CBR1 register :
+ - BlkReptDestAddrUpdate.
+ - BlkRptSrcAddrUpdate.
+ - DestAddrUpdate.
+ - SrcAddrUpdate.
+ - BlkRptCount.
+ */
+ uint32_t BlkRptDestAddrUpdateMode; /*!< This field specifies the block repeat destination address update mode.
+ This parameter can be a value of
+ @ref DMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE. */
+
+ uint32_t BlkRptSrcAddrUpdateMode; /*!< This field specifies the block repeat source address update mode.
+ This parameter can be a value of
+ @ref DMA_LL_EC_BLK_RPT_SRC_ADDR_UPDATE_MODE. */
+
+ uint32_t DestAddrUpdateMode; /*!< This field specify the Destination address update mode.
+ This parameter can be a value of @ref DMA_LL_EC_DEST_ADDR_UPDATE_MODE. */
+
+ uint32_t SrcAddrUpdateMode; /*!< This field specify the Source address update mode.
+ This parameter can be a value of @ref DMA_LL_EC_SRC_ADDR_UPDATE_MODE. */
+
+ uint32_t BlkRptCount; /*!< This field specify the number of repetitions of the current block.
+ This parameter can be a value between 1 and 2048 Min_Data = 0
+ and Max_Data = 0x000007FF. */
+
+ uint32_t BlkDataLength; /*!< This field specify the length of a block transfer in bytes.
+ This parameter must be a value between Min_Data = 0
+ and Max_Data = 0x0000FFFF. */
+
+
+ /* CSAR register fields ******************************************************
+ If any CSAR fields need to be updated comparing to previous node, it is
+ mandatory to update the new value in CSAR register fields and enable update
+ CSAR register in UpdateRegisters fields if it is not enabled in the
+ previous node.
+
+ For all node created, filling all fields is mandatory.
+ */
+ uint32_t SrcAddress; /*!< This field specify the transfer source address.
+ This parameter must be a value between Min_Data = 0
+ and Max_Data = 0xFFFFFFFF. */
+
+
+ /* CDAR register fields ******************************************************
+ If any CDAR fields need to be updated comparing to previous node, it is
+ mandatory to update the new value in CDAR register fields and enable update
+ CDAR register in UpdateRegisters fields if it is not enabled in the
+ previous node.
+
+ For all node created, filling all fields is mandatory.
+ */
+ uint32_t DestAddress; /*!< This field specify the transfer destination address.
+ This parameter must be a value between Min_Data = 0
+ and Max_Data = 0xFFFFFFFF. */
+
+
+ /* CTR3 register fields ******************************************************
+ If any CTR3 fields need to be updated comparing to previous node, it is
+ mandatory to update the new value in CTR3 register fields and enable update
+ CTR3 register in UpdateRegisters fields if it is not enabled in the
+ previous node.
+
+ This register is used only for 2D addressing channels.
+ If used channel is linear addressing, this register will be overwritten by
+ CLLR register in memory.
+ When this register is enabled on UpdateRegisters and the selected channel
+ is linear addressing, LL APIs will discard this register update in memory.
+ */
+ uint32_t DestAddrOffset; /*!< This field specifies the destination address offset.
+ This parameter can be a value Between 0 to 0x00001FFF. */
+
+ uint32_t SrcAddrOffset; /*!< This field specifies the source address offset.
+ This parameter can be a value Between 0 to 0x00001FFF. */
+
+
+ /* CBR2 register fields ******************************************************
+ If any CBR2 fields need to be updated comparing to previous node, it is
+ mandatory to update the new value in CBR2 register fields and enable update
+ CBR2 register in UpdateRegisters fields if it is not enabled in the
+ previous node.
+
+ This register is used only for 2D addressing channels.
+ If used channel is linear addressing, this register will be discarded in
+ memory. When this register is enabled on UpdateRegisters and the selected
+ channel is linear addressing, LL APIs will discard this register update in
+ memory.
+ */
+ uint32_t BlkRptDestAddrOffset; /*!< This field specifies the block repeat destination address offset.
+ This parameter can be a value Between 0 to 0x0000FFFF. */
+
+ uint32_t BlkRptSrcAddrOffset; /*!< This field specifies the block repeat source address offset.
+ This parameter can be a value Between 0 to 0x0000FFFF. */
+
+
+ /* CLLR register fields ******************************************************
+ If any CLLR fields need to be updated comparing to previous node, it is
+ mandatory to update the new value in CLLR register fields and enable update
+ CLLR register in UpdateRegisters fields if it is not enabled in the
+ previous node.
+
+ If used channel is linear addressing, there is no need to enable/disable
+ CTR3 and CBR2 register in UpdateRegisters fields as they will be discarded
+ by LL APIs.
+ */
+ uint32_t UpdateRegisters; /*!< Specifies the linked list register update.
+ This parameter can be a value of @ref DMA_LL_EC_LINKEDLIST_REGISTER_UPDATE. */
+
+ /* DMA Node type field *******************************************************
+ This parameter defines node types as node size and node content varies
+ between channels.
+ Thanks to this fields, linked list queue could be created independently
+ from channel selection. So, one queue could be executed by all DMA channels.
+ */
+ uint32_t NodeType; /*!< Specifies the node type to be created.
+ This parameter can be a value of @ref DMA_LL_EC_LINKEDLIST_NODE_TYPE. */
+} LL_DMA_InitNodeTypeDef;
+
+/**
+ * @brief LL DMA linked list node structure definition.
+ * @note For 2D addressing channels, the maximum node size is :
+ * (4 Bytes * 8 registers = 32 Bytes).
+ * For GPDMA linear addressing channels, the maximum node size is :
+ * (4 Bytes * 6 registers = 24 Bytes).
+ * For LPDMA linear addressing channels, the maximum node size is :
+ * (4 Bytes * 6 registers = 24 Bytes).
+ */
+typedef struct
+{
+ __IO uint32_t LinkRegisters[8];
+
+} LL_DMA_LinkNodeTypeDef;
+/**
+ * @}
+ */
+
+#endif /* defined (USE_FULL_LL_DRIVER) */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
+ * @{
+ */
+
+/** @defgroup DMA_LL_EC_CHANNEL Channel
+ * @{
+ */
+#define LL_DMA_CHANNEL_0 (0x00U)
+#define LL_DMA_CHANNEL_1 (0x01U)
+#define LL_DMA_CHANNEL_2 (0x02U)
+#define LL_DMA_CHANNEL_3 (0x03U)
+#define LL_DMA_CHANNEL_4 (0x04U)
+#define LL_DMA_CHANNEL_5 (0x05U)
+#define LL_DMA_CHANNEL_6 (0x06U)
+#define LL_DMA_CHANNEL_7 (0x07U)
+#define LL_DMA_CHANNEL_8 (0x08U)
+#define LL_DMA_CHANNEL_9 (0x09U)
+#define LL_DMA_CHANNEL_10 (0x0AU)
+#define LL_DMA_CHANNEL_11 (0x0BU)
+#define LL_DMA_CHANNEL_12 (0x0CU)
+#define LL_DMA_CHANNEL_13 (0x0DU)
+#define LL_DMA_CHANNEL_14 (0x0EU)
+#define LL_DMA_CHANNEL_15 (0x0FU)
+#if defined (USE_FULL_LL_DRIVER)
+#define LL_DMA_CHANNEL_ALL (0x10U)
+#endif /* defined (USE_FULL_LL_DRIVER) */
+/**
+ * @}
+ */
+
+#if defined (USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_EC_CLLR_OFFSET CLLR offset
+ * @{
+ */
+#define LL_DMA_CLLR_OFFSET0 (0x00U)
+#define LL_DMA_CLLR_OFFSET1 (0x01U)
+#define LL_DMA_CLLR_OFFSET2 (0x02U)
+#define LL_DMA_CLLR_OFFSET3 (0x03U)
+#define LL_DMA_CLLR_OFFSET4 (0x04U)
+#define LL_DMA_CLLR_OFFSET5 (0x05U)
+#define LL_DMA_CLLR_OFFSET6 (0x06U)
+#define LL_DMA_CLLR_OFFSET7 (0x07U)
+/**
+ * @}
+ */
+#endif /* defined (USE_FULL_LL_DRIVER) */
+
+/** @defgroup DMA_LL_EC_PRIORITY_LEVEL Priority Level
+ * @{
+ */
+#define LL_DMA_LOW_PRIORITY_LOW_WEIGHT 0x00000000U /*!< Priority level : Low Priority, Low Weight */
+#define LL_DMA_LOW_PRIORITY_MID_WEIGHT DMA_CCR_PRIO_0 /*!< Priority level : Low Priority, Mid Weight */
+#define LL_DMA_LOW_PRIORITY_HIGH_WEIGHT DMA_CCR_PRIO_1 /*!< Priority level : Low Priority, High Weight */
+#define LL_DMA_HIGH_PRIORITY DMA_CCR_PRIO /*!< Priority level : High Priority */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT Linked List Allocated Port
+ * @{
+ */
+#define LL_DMA_LINK_ALLOCATED_PORT0 0x00000000U /*!< Linked List Allocated Port 0 */
+#define LL_DMA_LINK_ALLOCATED_PORT1 DMA_CCR_LAP /*!< Linked List Allocated Port 1 */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_LINK_STEP_MODE Link Step Mode
+ * @{
+ */
+#define LL_DMA_LSM_FULL_EXECUTION 0x00000000U /*!< Channel execute the full linked list */
+#define LL_DMA_LSM_1LINK_EXECUTION DMA_CCR_LSM /*!< Channel execute one node of the linked list */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_DEST_HALFWORD_EXCHANGE Destination Half-Word Exchange
+ * @{
+ */
+#define LL_DMA_DEST_HALFWORD_PRESERVE 0x00000000U /*!< No destinatiion Half-Word exchange when destination data width
+ is word */
+#define LL_DMA_DEST_HALFWORD_EXCHANGE DMA_CTR1_DHX /*!< Destinatiion Half-Word exchange when destination data width
+ is word */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_DEST_BYTE_EXCHANGE Destination Byte Exchange
+ * @{
+ */
+#define LL_DMA_DEST_BYTE_PRESERVE 0x00000000U /*!< No destination Byte exchange when destination data width > Byte */
+#define LL_DMA_DEST_BYTE_EXCHANGE DMA_CTR1_DBX /*!< Destination Byte exchange when destination data width > Byte */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_SRC_BYTE_EXCHANGE Source Byte Exchange
+ * @{
+ */
+#define LL_DMA_SRC_BYTE_PRESERVE 0x00000000U /*!< No source Byte exchange when source data width is word */
+#define LL_DMA_SRC_BYTE_EXCHANGE DMA_CTR1_SBX /*!< Source Byte exchange when source data width is word */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_SOURCE_ALLOCATED_PORT Source Allocated Port
+ * @{
+ */
+#define LL_DMA_SRC_ALLOCATED_PORT0 0x00000000U /*!< Source Allocated Port 0 */
+#define LL_DMA_SRC_ALLOCATED_PORT1 DMA_CTR1_SAP /*!< Source Allocated Port 1 */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_DESTINATION_ALLOCATED_PORT Destination Allocated Port
+ * @{
+ */
+#define LL_DMA_DEST_ALLOCATED_PORT0 0x00000000U /*!< Destination Allocated Port 0 */
+#define LL_DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP /*!< Destination Allocated Port 1 */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_DESTINATION_INCREMENT_MODE Destination Increment Mode
+ * @{
+ */
+#define LL_DMA_DEST_FIXED 0x00000000U /*!< Destination fixed single/burst */
+#define LL_DMA_DEST_INCREMENT DMA_CTR1_DINC /*!< Destination incremented single/burst */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_DESTINATION_DATA_WIDTH Destination Data Width
+ * @{
+ */
+#define LL_DMA_DEST_DATAWIDTH_BYTE 0x00000000U /*!< Destination Data Width : Byte */
+#define LL_DMA_DEST_DATAWIDTH_HALFWORD DMA_CTR1_DDW_LOG2_0 /*!< Destination Data Width : HalfWord */
+#define LL_DMA_DEST_DATAWIDTH_WORD DMA_CTR1_DDW_LOG2_1 /*!< Destination Data Width : Word */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_DATA_ALIGNMENT Data Alignment
+ * @{
+ */
+#define LL_DMA_DATA_ALIGN_ZEROPADD 0x00000000U /*!< If src data width < dest data width :
+ => Right Aligned padded with 0 up to destination
+ data width.
+ If src data width > dest data width :
+ => Right Aligned Left Truncated down to destination
+ data width. */
+#define LL_DMA_DATA_ALIGN_SIGNEXTPADD DMA_CTR1_PAM_0 /*!< If src data width < dest data width :
+ => Right Aligned padded with sign extended up to destination
+ data width.
+ If src data width > dest data width :
+ => Left Aligned Right Truncated down to the destination
+ data width */
+#define LL_DMA_DATA_PACK_UNPACK DMA_CTR1_PAM_1 /*!< If src data width < dest data width :
+ => Packed at the destination data width (Not Available
+ for LPDMA)
+ If src data width > dest data width :
+ => Unpacked at the destination data width (Not Available
+ for LPDMA) */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_SOURCE_INCREMENT_MODE Source Increment Mode
+ * @{
+ */
+#define LL_DMA_SRC_FIXED 0x00000000U /*!< Source fixed single/burst */
+#define LL_DMA_SRC_INCREMENT DMA_CTR1_SINC /*!< Source incremented single/burst */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_SOURCE_DATA_WIDTH Source Data Width
+ * @{
+ */
+#define LL_DMA_SRC_DATAWIDTH_BYTE 0x00000000U /*!< Source Data Width : Byte */
+#define LL_DMA_SRC_DATAWIDTH_HALFWORD DMA_CTR1_SDW_LOG2_0 /*!< Source Data Width : HalfWord */
+#define LL_DMA_SRC_DATAWIDTH_WORD DMA_CTR1_SDW_LOG2_1 /*!< Source Data Width : Word */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_BLKHW_REQUEST Block Hardware Request
+ * @{
+ */
+#define LL_DMA_HWREQUEST_SINGLEBURST 0x00000000U /*!< Hardware request is driven by a peripheral with a hardware
+ request/acknowledge protocol at a burst level */
+#define LL_DMA_HWREQUEST_BLK DMA_CTR2_BREQ /*!< Hardware request is driven by a peripheral with a hardware
+ request/acknowledge protocol at a block level */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_TRANSFER_EVENT_MODE Transfer Event Mode
+ * @{
+ */
+#define LL_DMA_TCEM_BLK_TRANSFER 0x00000000U /*!< The TC (and the HT) event is generated at the
+ (respectively half) end of each block */
+#define LL_DMA_TCEM_RPT_BLK_TRANSFER DMA_CTR2_TCEM_0 /*!< The TC (and the HT) event is generated at the
+ (respectively half) end of the repeated block */
+#define LL_DMA_TCEM_EACH_LLITEM_TRANSFER DMA_CTR2_TCEM_1 /*!< The TC (and the HT) event is generated at the
+ (respectively half) end of each linked-list item */
+#define LL_DMA_TCEM_LAST_LLITEM_TRANSFER DMA_CTR2_TCEM /*!< The TC (and the HT) event is generated at the
+ (respectively half) end of the last linked-list item */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_TRIGGER_POLARITY Trigger Polarity
+ * @{
+ */
+#define LL_DMA_TRIG_POLARITY_MASKED 0x00000000U /*!< No trigger of the selected DMA request.
+ Masked trigger event */
+#define LL_DMA_TRIG_POLARITY_RISING DMA_CTR2_TRIGPOL_0 /*!< Trigger of the selected DMA request on the rising
+ edge of the selected trigger event input */
+#define LL_DMA_TRIG_POLARITY_FALLING DMA_CTR2_TRIGPOL_1 /*!< Trigger of the selected DMA request on the falling
+ edge of the selected trigger event input */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_TRIGGER_MODE Transfer Trigger Mode
+ * @{
+ */
+#define LL_DMA_TRIGM_BLK_TRANSFER 0x00000000U /*!< A block transfer is conditioned by (at least)
+ one hit trigger */
+#define LL_DMA_TRIGM_RPT_BLK_TRANSFER DMA_CTR2_TRIGM_0 /*!< A repeated block transfer is conditioned by (at least)
+ one hit trigger */
+#define LL_DMA_TRIGM_LLI_LINK_TRANSFER DMA_CTR2_TRIGM_1 /*!< A LLI link transfer is conditioned by (at least)
+ one hit trigger */
+#define LL_DMA_TRIGM_SINGLBURST_TRANSFER DMA_CTR2_TRIGM /*!< A Single/Burst transfer is conditioned by (at least)
+ one hit trigger */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_TRANSFER_DIRECTION Transfer Direction
+ * @{
+ */
+#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction */
+#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
+#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CTR2_DREQ /*!< Memory to peripheral direction */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_BLK_RPT_SRC_ADDR_UPDATE_MODE Block Repeat Source Address Update Mode
+ * @{
+ */
+#define LL_DMA_BLKRPT_SRC_ADDR_INCREMENT 0x00000000U /*!< Source address pointer is incremented after each block
+ transfer by source update value */
+#define LL_DMA_BLKRPT_SRC_ADDR_DECREMENT DMA_CBR1_BRSDEC /*!< Source address pointer is decremented after each block
+ transfer by source update value */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE Block Repeat Destination Address Update Mode
+ * @{
+ */
+#define LL_DMA_BLKRPT_DEST_ADDR_INCREMENT 0x00000000U /*!< Destination address is incremented after each block
+ transfer by destination update value */
+#define LL_DMA_BLKRPT_DEST_ADDR_DECREMENT DMA_CBR1_BRDDEC /*!< Destination address is decremented after each block
+ transfer by destination update value */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_SRC_ADDR_UPDATE_MODE Burst Source Address Update Mode
+ * @{
+ */
+#define LL_DMA_BURST_SRC_ADDR_INCREMENT 0x00000000U /*!< Source address pointer is incremented after each burst
+ transfer by source update value */
+#define LL_DMA_BURST_SRC_ADDR_DECREMENT DMA_CBR1_SDEC /*!< Source address pointer is decremented after each burst
+ transfer by source update value */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_DEST_ADDR_UPDATE_MODE Burst Destination Address Update Mode
+ * @{
+ */
+#define LL_DMA_BURST_DEST_ADDR_INCREMENT 0x00000000U /*!< Destination address pointer is incremented after each
+ burst transfer by destination update value */
+#define LL_DMA_BURST_DEST_ADDR_DECREMENT DMA_CBR1_DDEC /*!< Destination address pointer is decremented after each
+ burst transfer by destination update value */
+/**
+ * @}
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/** @defgroup DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE Source Security Attribute
+ * @{
+ */
+#define LL_DMA_CHANNEL_NSEC 0x00000000U /*!< NSecure channel */
+#define LL_DMA_CHANNEL_SEC 0x00000001U /*!< Secure channel */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE Source Security Attribute
+ * @{
+ */
+#define LL_DMA_CHANNEL_SRC_NSEC 0x00000000U /*!< NSecure transfer from the source */
+#define LL_DMA_CHANNEL_SRC_SEC DMA_CTR1_SSEC /*!< Secure transfer from the source */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_DESTINATION_SECURITY_ATTRIBUTE Destination Security Attribute
+ * @{
+ */
+#define LL_DMA_CHANNEL_DEST_NSEC 0x00000000U /*!< NSecure transfer from the destination */
+#define LL_DMA_CHANNEL_DEST_SEC DMA_CTR1_DSEC /*!< Secure transfer from the destination */
+/**
+ * @}
+ */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/** @defgroup DMA_LL_EC_LINKEDLIST_NODE_TYPE Linked list node type
+ * @{
+ */
+#define LL_DMA_LPDMA_LINEAR_NODE 0x00U /*!< LPDMA node : linear addressing node */
+#define LL_DMA_GPDMA_LINEAR_NODE 0x01U /*!< GPDMA node : linear addressing node */
+#define LL_DMA_GPDMA_2D_NODE 0x02U /*!< GPDMA node : 2 dimension addressing node */
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_LINKEDLIST_REGISTER_UPDATE Linked list register update
+ * @{
+ */
+#define LL_DMA_UPDATE_CTR1 DMA_CLLR_UT1 /*!< Update CTR1 register from memory :
+ available for all DMA channels */
+#define LL_DMA_UPDATE_CTR2 DMA_CLLR_UT2 /*!< Update CTR2 register from memory :
+ available for all DMA channels */
+#define LL_DMA_UPDATE_CBR1 DMA_CLLR_UB1 /*!< Update CBR1 register from memory :
+ available for all DMA channels */
+#define LL_DMA_UPDATE_CSAR DMA_CLLR_USA /*!< Update CSAR register from memory :
+ available for all DMA channels */
+#define LL_DMA_UPDATE_CDAR DMA_CLLR_UDA /*!< Update CDAR register from memory :
+ available for all DMA channels */
+#define LL_DMA_UPDATE_CTR3 DMA_CLLR_UT3 /*!< Update CTR3 register from memory :
+ available only for 2D addressing DMA channels */
+#define LL_DMA_UPDATE_CBR2 DMA_CLLR_UB2 /*!< Update CBR2 register from memory :
+ available only for 2D addressing DMA channels */
+#define LL_DMA_UPDATE_CLLR DMA_CLLR_ULL /*!< Update CLLR register from memory :
+ available for all DMA channels */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_REQUEST_SELECTION Request Selection
+ * @{
+ */
+/* GPDMA1 Hardware Requests */
+#define LL_GPDMA1_REQUEST_ADC1 0U /*!< GPDMA1 HW Request is ADC1 */
+#define LL_GPDMA1_REQUEST_ADC4 1U /*!< GPDMA1 HW Request is ADC4 */
+#define LL_GPDMA1_REQUEST_DAC1_CH1 2U /*!< GPDMA1 HW Request is DAC1_CH1 */
+#define LL_GPDMA1_REQUEST_DAC1_CH2 3U /*!< GPDMA1 HW Request is DAC1_CH2 */
+#define LL_GPDMA1_REQUEST_TIM6_UP 4U /*!< GPDMA1 HW Request is TIM6_UP */
+#define LL_GPDMA1_REQUEST_TIM7_UP 5U /*!< GPDMA1 HW Request is TIM7_UP */
+#define LL_GPDMA1_REQUEST_SPI1_RX 6U /*!< GPDMA1 HW Request is SPI1_RX */
+#define LL_GPDMA1_REQUEST_SPI1_TX 7U /*!< GPDMA1 HW Request is SPI1_TX */
+#define LL_GPDMA1_REQUEST_SPI2_RX 8U /*!< GPDMA1 HW Request is SPI2_RX */
+#define LL_GPDMA1_REQUEST_SPI2_TX 9U /*!< GPDMA1 HW Request is SPI2_TX */
+#define LL_GPDMA1_REQUEST_SPI3_RX 10U /*!< GPDMA1 HW Request is SPI3_RX */
+#define LL_GPDMA1_REQUEST_SPI3_TX 11U /*!< GPDMA1 HW Request is SPI3_TX */
+#define LL_GPDMA1_REQUEST_I2C1_RX 12U /*!< GPDMA1 HW Request is I2C1_RX */
+#define LL_GPDMA1_REQUEST_I2C1_TX 13U /*!< GPDMA1 HW Request is I2C1_TX */
+#define LL_GPDMA1_REQUEST_I2C1_EVC 14U /*!< GPDMA1 HW Request is I2C1_EVC */
+#define LL_GPDMA1_REQUEST_I2C2_RX 15U /*!< GPDMA1 HW Request is I2C2_RX */
+#define LL_GPDMA1_REQUEST_I2C2_TX 16U /*!< GPDMA1 HW Request is I2C2_TX */
+#define LL_GPDMA1_REQUEST_I2C2_EVC 17U /*!< GPDMA1 HW Request is I2C2_EVC */
+#define LL_GPDMA1_REQUEST_I2C3_RX 18U /*!< GPDMA1 HW Request is I2C3_RX */
+#define LL_GPDMA1_REQUEST_I2C3_TX 19U /*!< GPDMA1 HW Request is I2C3_TX */
+#define LL_GPDMA1_REQUEST_I2C3_EVC 20U /*!< GPDMA1 HW Request is I2C3_EVC */
+#define LL_GPDMA1_REQUEST_I2C4_RX 21U /*!< GPDMA1 HW Request is I2C4_RX */
+#define LL_GPDMA1_REQUEST_I2C4_TX 22U /*!< GPDMA1 HW Request is I2C4_TX */
+#define LL_GPDMA1_REQUEST_I2C4_EVC 23U /*!< GPDMA1 HW Request is I2C4_EVC */
+#define LL_GPDMA1_REQUEST_USART1_RX 24U /*!< GPDMA1 HW Request is USART1_RX */
+#define LL_GPDMA1_REQUEST_USART1_TX 25U /*!< GPDMA1 HW Request is USART1_TX */
+#define LL_GPDMA1_REQUEST_USART2_RX 26U /*!< GPDMA1 HW Request is USART2_RX */
+#define LL_GPDMA1_REQUEST_USART2_TX 27U /*!< GPDMA1 HW Request is USART2_TX */
+#define LL_GPDMA1_REQUEST_USART3_RX 28U /*!< GPDMA1 HW Request is USART3_RX */
+#define LL_GPDMA1_REQUEST_USART3_TX 29U /*!< GPDMA1 HW Request is USART3_TX */
+#define LL_GPDMA1_REQUEST_UART4_RX 30U /*!< GPDMA1 HW Request is UART4_RX */
+#define LL_GPDMA1_REQUEST_UART4_TX 31U /*!< GPDMA1 HW Request is UART4_TX */
+#define LL_GPDMA1_REQUEST_UART5_RX 32U /*!< GPDMA1 HW Request is UART5_RX */
+#define LL_GPDMA1_REQUEST_UART5_TX 33U /*!< GPDMA1 HW Request is UART5_TX */
+#define LL_GPDMA1_REQUEST_LPUART1_RX 34U /*!< GPDMA1 HW Request is LPUART1_RX */
+#define LL_GPDMA1_REQUEST_LPUART1_TX 35U /*!< GPDMA1 HW Request is LPUART1_TX */
+#define LL_GPDMA1_REQUEST_SAI1_A 36U /*!< GPDMA1 HW Request is SAI1_A */
+#define LL_GPDMA1_REQUEST_SAI1_B 37U /*!< GPDMA1 HW Request is SAI1_B */
+#define LL_GPDMA1_REQUEST_SAI2_A 38U /*!< GPDMA1 HW Request is SAI2_A */
+#define LL_GPDMA1_REQUEST_SAI2_B 39U /*!< GPDMA1 HW Request is SAI2_B */
+#define LL_GPDMA1_REQUEST_OCTOSPI1 40U /*!< GPDMA1 HW Request is OCTOSPI1 */
+#define LL_GPDMA1_REQUEST_OCTOSPI2 41U /*!< GPDMA1 HW Request is OCTOSPI2 */
+#define LL_GPDMA1_REQUEST_TIM1_CH1 42U /*!< GPDMA1 HW Request is TIM1_CH1 */
+#define LL_GPDMA1_REQUEST_TIM1_CH2 43U /*!< GPDMA1 HW Request is TIM1_CH2 */
+#define LL_GPDMA1_REQUEST_TIM1_CH3 44U /*!< GPDMA1 HW Request is TIM1_CH3 */
+#define LL_GPDMA1_REQUEST_TIM1_CH4 45U /*!< GPDMA1 HW Request is TIM1_CH4 */
+#define LL_GPDMA1_REQUEST_TIM1_UP 46U /*!< GPDMA1 HW Request is TIM1_UP */
+#define LL_GPDMA1_REQUEST_TIM1_TRIG 47U /*!< GPDMA1 HW Request is TIM1_TRIG */
+#define LL_GPDMA1_REQUEST_TIM1_COM 48U /*!< GPDMA1 HW Request is TIM1_COM */
+#define LL_GPDMA1_REQUEST_TIM8_CH1 49U /*!< GPDMA1 HW Request is TIM8_CH1 */
+#define LL_GPDMA1_REQUEST_TIM8_CH2 50U /*!< GPDMA1 HW Request is TIM8_CH2 */
+#define LL_GPDMA1_REQUEST_TIM8_CH3 51U /*!< GPDMA1 HW Request is TIM8_CH3 */
+#define LL_GPDMA1_REQUEST_TIM8_CH4 52U /*!< GPDMA1 HW Request is TIM8_CH4 */
+#define LL_GPDMA1_REQUEST_TIM8_UP 53U /*!< GPDMA1 HW Request is TIM8_UP */
+#define LL_GPDMA1_REQUEST_TIM8_TRIG 54U /*!< GPDMA1 HW Request is TIM8_TRIG */
+#define LL_GPDMA1_REQUEST_TIM8_COM 55U /*!< GPDMA1 HW Request is TIM8_COM */
+#define LL_GPDMA1_REQUEST_TIM2_CH1 56U /*!< GPDMA1 HW Request is TIM2_CH1 */
+#define LL_GPDMA1_REQUEST_TIM2_CH2 57U /*!< GPDMA1 HW Request is TIM2_CH2 */
+#define LL_GPDMA1_REQUEST_TIM2_CH3 58U /*!< GPDMA1 HW Request is TIM2_CH3 */
+#define LL_GPDMA1_REQUEST_TIM2_CH4 59U /*!< GPDMA1 HW Request is TIM2_CH4 */
+#define LL_GPDMA1_REQUEST_TIM2_UP 60U /*!< GPDMA1 HW Request is TIM2_UP */
+#define LL_GPDMA1_REQUEST_TIM3_CH1 61U /*!< GPDMA1 HW Request is TIM3_CH1 */
+#define LL_GPDMA1_REQUEST_TIM3_CH2 62U /*!< GPDMA1 HW Request is TIM3_CH2 */
+#define LL_GPDMA1_REQUEST_TIM3_CH3 63U /*!< GPDMA1 HW Request is TIM3_CH3 */
+#define LL_GPDMA1_REQUEST_TIM3_CH4 64U /*!< GPDMA1 HW Request is TIM3_CH4 */
+#define LL_GPDMA1_REQUEST_TIM3_UP 65U /*!< GPDMA1 HW Request is TIM3_UP */
+#define LL_GPDMA1_REQUEST_TIM3_TRIG 66U /*!< GPDMA1 HW Request is TIM3_TRIG */
+#define LL_GPDMA1_REQUEST_TIM4_CH1 67U /*!< GPDMA1 HW Request is TIM4_CH1 */
+#define LL_GPDMA1_REQUEST_TIM4_CH2 68U /*!< GPDMA1 HW Request is TIM4_CH2 */
+#define LL_GPDMA1_REQUEST_TIM4_CH3 69U /*!< GPDMA1 HW Request is TIM4_CH3 */
+#define LL_GPDMA1_REQUEST_TIM4_CH4 70U /*!< GPDMA1 HW Request is TIM4_CH4 */
+#define LL_GPDMA1_REQUEST_TIM4_UP 71U /*!< GPDMA1 HW Request is TIM4_UP */
+#define LL_GPDMA1_REQUEST_TIM5_CH1 72U /*!< GPDMA1 HW Request is TIM5_CH1 */
+#define LL_GPDMA1_REQUEST_TIM5_CH2 73U /*!< GPDMA1 HW Request is TIM5_CH2 */
+#define LL_GPDMA1_REQUEST_TIM5_CH3 74U /*!< GPDMA1 HW Request is TIM5_CH3 */
+#define LL_GPDMA1_REQUEST_TIM5_CH4 75U /*!< GPDMA1 HW Request is TIM5_CH4 */
+#define LL_GPDMA1_REQUEST_TIM5_UP 76U /*!< GPDMA1 HW Request is TIM5_UP */
+#define LL_GPDMA1_REQUEST_TIM5_TRIG 77U /*!< GPDMA1 HW Request is TIM5_TRIG */
+#define LL_GPDMA1_REQUEST_TIM15_CH1 78U /*!< GPDMA1 HW Request is TIM15_CH1 */
+#define LL_GPDMA1_REQUEST_TIM15_UP 79U /*!< GPDMA1 HW Request is TIM15_UP */
+#define LL_GPDMA1_REQUEST_TIM15_TRIG 80U /*!< GPDMA1 HW Request is TIM15_TRIG */
+#define LL_GPDMA1_REQUEST_TIM15_COM 81U /*!< GPDMA1 HW Request is TIM15_COM */
+#define LL_GPDMA1_REQUEST_TIM16_CH1 82U /*!< GPDMA1 HW Request is TIM16_CH1 */
+#define LL_GPDMA1_REQUEST_TIM16_UP 83U /*!< GPDMA1 HW Request is TIM16_UP */
+#define LL_GPDMA1_REQUEST_TIM17_CH1 84U /*!< GPDMA1 HW Request is TIM17_CH1 */
+#define LL_GPDMA1_REQUEST_TIM17_UP 85U /*!< GPDMA1 HW Request is TIM17_UP */
+#define LL_GPDMA1_REQUEST_DCMI 86U /*!< GPDMA1 HW Request is DCMI */
+#define LL_GPDMA1_REQUEST_AES_IN 87U /*!< GPDMA1 HW Request is AES_IN */
+#define LL_GPDMA1_REQUEST_AES_OUT 88U /*!< GPDMA1 HW Request is AES_OUT */
+#define LL_GPDMA1_REQUEST_HASH_IN 89U /*!< GPDMA1 HW Request is HASH_IN */
+#define LL_GPDMA1_REQUEST_UCPD1_TX 90U /*!< GPDMA1 HW Request is UCPD1_TX */
+#define LL_GPDMA1_REQUEST_UCPD1_RX 91U /*!< GPDMA1 HW Request is UCPD1_RX */
+#define LL_GPDMA1_REQUEST_MDF1_FLT0 92U /*!< GPDMA1 HW Request is MDF1_FLT0 */
+#define LL_GPDMA1_REQUEST_MDF1_FLT1 93U /*!< GPDMA1 HW Request is MDF1_FLT1 */
+#define LL_GPDMA1_REQUEST_MDF1_FLT2 94U /*!< GPDMA1 HW Request is MDF1_FLT2 */
+#define LL_GPDMA1_REQUEST_MDF1_FLT3 95U /*!< GPDMA1 HW Request is MDF1_FLT3 */
+#define LL_GPDMA1_REQUEST_MDF1_FLT4 96U /*!< GPDMA1 HW Request is MDF1_FLT4 */
+#define LL_GPDMA1_REQUEST_MDF1_FLT5 97U /*!< GPDMA1 HW Request is MDF1_FLT5 */
+#define LL_GPDMA1_REQUEST_ADF1_FLT0 98U /*!< GPDMA1 HW Request is ADF1_FLT0 */
+#define LL_GPDMA1_REQUEST_FMAC_READ 99U /*!< GPDMA1 HW Request is FMAC_READ */
+#define LL_GPDMA1_REQUEST_FMAC_WRITE 100U /*!< GPDMA1 HW Request is FMAC_WRITE */
+#define LL_GPDMA1_REQUEST_CORDIC_READ 101U /*!< GPDMA1 HW Request is CORDIC_READ */
+#define LL_GPDMA1_REQUEST_CORDIC_WRITE 102U /*!< GPDMA1 HW Request is CORDIC_WRITE */
+#define LL_GPDMA1_REQUEST_SAES_IN 103U /*!< GPDMA1 HW Request is SAES_IN */
+#define LL_GPDMA1_REQUEST_SAES_OUT 104U /*!< GPDMA1 HW Request is SAES_OUT */
+#define LL_GPDMA1_REQUEST_LPTIM1_IC1 105U /*!< GPDMA1 HW Request is LPTIM1_IC1 */
+#define LL_GPDMA1_REQUEST_LPTIM1_IC2 106U /*!< GPDMA1 HW Request is LPTIM1_IC2 */
+#define LL_GPDMA1_REQUEST_LPTIM1_UE 107U /*!< GPDMA1 HW Request is LPTIM1_UE */
+#define LL_GPDMA1_REQUEST_LPTIM2_IC1 108U /*!< GPDMA1 HW Request is LPTIM2_IC1 */
+#define LL_GPDMA1_REQUEST_LPTIM2_IC2 109U /*!< GPDMA1 HW Request is LPTIM2_IC2 */
+#define LL_GPDMA1_REQUEST_LPTIM2_UE 110U /*!< GPDMA1 HW Request is LPTIM2_UE */
+#define LL_GPDMA1_REQUEST_LPTIM3_IC1 111U /*!< GPDMA1 HW Request is LPTIM3_IC1 */
+#define LL_GPDMA1_REQUEST_LPTIM3_IC2 112U /*!< GPDMA1 HW Request is LPTIM3_IC2 */
+#define LL_GPDMA1_REQUEST_LPTIM3_UE 113U /*!< GPDMA1 HW Request is LPTIM3_UE */
+
+/* LPDMA1 Hardware Requests */
+#define LL_LPDMA1_REQUEST_LPUART1_RX 0U /*!< LPDMA1 HW Request is LPUART1_RX */
+#define LL_LPDMA1_REQUEST_LPUART1_TX 1U /*!< LPDMA1 HW Request is LPUART1_TX */
+#define LL_LPDMA1_REQUEST_SPI3_RX 2U /*!< LPDMA1 HW Request is SPI3_RX */
+#define LL_LPDMA1_REQUEST_SPI3_TX 3U /*!< LPDMA1 HW Request is SPI3_TX */
+#define LL_LPDMA1_REQUEST_I2C3_RX 4U /*!< LPDMA1 HW Request is I2C3_RX */
+#define LL_LPDMA1_REQUEST_I2C3_TX 5U /*!< LPDMA1 HW Request is I2C3_TX */
+#define LL_LPDMA1_REQUEST_I2C3_EVC 6U /*!< LPDMA1 HW Request is I2C3_EVC */
+#define LL_LPDMA1_REQUEST_ADC4 7U /*!< LPDMA1 HW Request is ADC4 */
+#define LL_LPDMA1_REQUEST_DAC1_CH1 8U /*!< LPDMA1 HW Request is DAC1_CH1 */
+#define LL_LPDMA1_REQUEST_DAC1_CH2 9U /*!< LPDMA1 HW Request is DAC1_CH2 */
+#define LL_LPDMA1_REQUEST_ADF1_FLT0 10U /*!< LPDMA1 HW Request is ADF1_FLT0 */
+#define LL_LPDMA1_REQUEST_LPTIM1_IC1 11U /*!< LPDMA1 HW Request is LPTIM1_IC1 */
+#define LL_LPDMA1_REQUEST_LPTIM1_IC2 12U /*!< LPDMA1 HW Request is LPTIM1_IC2 */
+#define LL_LPDMA1_REQUEST_LPTIM1_UE 13U /*!< LPDMA1 HW Request is LPTIM1_UE */
+#define LL_LPDMA1_REQUEST_LPTIM3_IC1 14U /*!< LPDMA1 HW Request is LPTIM3_IC1 */
+#define LL_LPDMA1_REQUEST_LPTIM3_IC2 15U /*!< LPDMA1 HW Request is LPTIM3_IC2 */
+#define LL_LPDMA1_REQUEST_LPTIM3_UE 16U /*!< LPDMA1 HW Request is LPTIM3_UE */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_TRIGGER_SELECTION Trigger Selection
+ * @{
+ */
+/* GPDMA1 Hardware Triggers */
+#define LL_GPDMA1_TRIGGER_EXTI_LINE0 0U /*!< GPDMA1 HW Trigger is EXTI_LINE0 */
+#define LL_GPDMA1_TRIGGER_EXTI_LINE1 1U /*!< GPDMA1 HW Trigger is EXTI_LINE1 */
+#define LL_GPDMA1_TRIGGER_EXTI_LINE2 2U /*!< GPDMA1 HW Trigger is EXTI_LINE2 */
+#define LL_GPDMA1_TRIGGER_EXTI_LINE3 3U /*!< GPDMA1 HW Trigger is EXTI_LINE3 */
+#define LL_GPDMA1_TRIGGER_EXTI_LINE4 4U /*!< GPDMA1 HW Trigger is EXTI_LINE4 */
+#define LL_GPDMA1_TRIGGER_EXTI_LINE5 5U /*!< GPDMA1 HW Trigger is EXTI_LINE5 */
+#define LL_GPDMA1_TRIGGER_EXTI_LINE6 6U /*!< GPDMA1 HW Trigger is EXTI_LINE6 */
+#define LL_GPDMA1_TRIGGER_EXTI_LINE7 7U /*!< GPDMA1 HW Trigger is EXTI_LINE7 */
+#define LL_GPDMA1_TRIGGER_TAMP_TRG1 8U /*!< GPDMA1 HW Trigger is TAMP_TRG1 */
+#define LL_GPDMA1_TRIGGER_TAMP_TRG2 9U /*!< GPDMA1 HW Trigger is TAMP_TRG2 */
+#define LL_GPDMA1_TRIGGER_TAMP_TRG3 10U /*!< GPDMA1 HW Trigger is TAMP_TRG3 */
+#define LL_GPDMA1_TRIGGER_LPTIM1_CH1 11U /*!< GPDMA1 HW Trigger is LPTIM1_CH1 */
+#define LL_GPDMA1_TRIGGER_LPTIM1_CH2 12U /*!< GPDMA1 HW Trigger is LPTIM1_CH2 */
+#define LL_GPDMA1_TRIGGER_LPTIM2_CH1 13U /*!< GPDMA1 HW Trigger is LPTIM2_CH1 */
+#define LL_GPDMA1_TRIGGER_LPTIM2_CH2 14U /*!< GPDMA1 HW Trigger is LPTIM2_CH2 */
+#define LL_GPDMA1_TRIGGER_LPTIM4_OUT 15U /*!< GPDMA1 HW Trigger is LPTIM4_OUT */
+#define LL_GPDMA1_TRIGGER_COMP1_OUT 16U /*!< GPDMA1 HW Trigger is COMP1_OUT */
+#define LL_GPDMA1_TRIGGER_COMP2_OUT 17U /*!< GPDMA1 HW Trigger is COMP2_OUT */
+#define LL_GPDMA1_TRIGGER_RTC_ALRA_TRG 18U /*!< GPDMA1 HW Trigger is RTC_ALRA_TRG */
+#define LL_GPDMA1_TRIGGER_RTC_ALRB_TRG 19U /*!< GPDMA1 HW Trigger is RTC_ALRB_TRG */
+#define LL_GPDMA1_TRIGGER_RTC_WUT_TRG 20U /*!< GPDMA1 HW Trigger is RTC_WUT_TRG */
+#define LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF 22U /*!< GPDMA1 HW Trigger is GPDMA1_CH0_TCF */
+#define LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF 23U /*!< GPDMA1 HW Trigger is GPDMA1_CH1_TCF */
+#define LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF 24U /*!< GPDMA1 HW Trigger is GPDMA1_CH2_TCF */
+#define LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF 25U /*!< GPDMA1 HW Trigger is GPDMA1_CH3_TCF */
+#define LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF 26U /*!< GPDMA1 HW Trigger is GPDMA1_CH4_TCF */
+#define LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF 27U /*!< GPDMA1 HW Trigger is GPDMA1_CH5_TCF */
+#define LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF 28U /*!< GPDMA1 HW Trigger is GPDMA1_CH6_TCF */
+#define LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF 29U /*!< GPDMA1 HW Trigger is GPDMA1_CH7_TCF */
+#define LL_GPDMA1_TRIGGER_GPDMA1_CH8_TCF 30U /*!< GPDMA1 HW Trigger is GPDMA1_CH8_TCF */
+#define LL_GPDMA1_TRIGGER_GPDMA1_CH9_TCF 31U /*!< GPDMA1 HW Trigger is GPDMA1_CH9_TCF */
+#define LL_GPDMA1_TRIGGER_GPDMA1_CH10_TCF 32U /*!< GPDMA1 HW Trigger is GPDMA1_CH10_TCF */
+#define LL_GPDMA1_TRIGGER_GPDMA1_CH11_TCF 33U /*!< GPDMA1 HW Trigger is GPDMA1_CH11_TCF */
+#define LL_GPDMA1_TRIGGER_GPDMA1_CH12_TCF 34U /*!< GPDMA1 HW Trigger is GPDMA1_CH12_TCF */
+#define LL_GPDMA1_TRIGGER_GPDMA1_CH13_TCF 35U /*!< GPDMA1 HW Trigger is GPDMA1_CH13_TCF */
+#define LL_GPDMA1_TRIGGER_GPDMA1_CH14_TCF 36U /*!< GPDMA1 HW Trigger is GPDMA1_CH14_TCF */
+#define LL_GPDMA1_TRIGGER_GPDMA1_CH15_TCF 37U /*!< GPDMA1 HW Trigger is GPDMA1_CH15_TCF */
+#define LL_GPDMA1_TRIGGER_LPDMA1_CH0_TCF 38U /*!< GPDMA1 HW Trigger is LPDMA1_CH0_TCF */
+#define LL_GPDMA1_TRIGGER_LPDMA1_CH1_TCF 39U /*!< GPDMA1 HW Trigger is LPDMA1_CH1_TCF */
+#define LL_GPDMA1_TRIGGER_LPDMA1_CH2_TCF 40U /*!< GPDMA1 HW Trigger is LPDMA1_CH2_TCF */
+#define LL_GPDMA1_TRIGGER_LPDMA1_CH3_TCF 41U /*!< GPDMA1 HW Trigger is LPDMA1_CH3_TCF */
+#define LL_GPDMA1_TRIGGER_TIM2_TRGO 42U /*!< GPDMA1 HW Trigger is TIM2_TRGO */
+#define LL_GPDMA1_TRIGGER_TIM15_TRGO 43U /*!< GPDMA1 HW Trigger is TIM15_TRGO */
+#define LL_GPDMA1_TRIGGER_ADC4_AWD1 57U /*!< GPDMA1 HW Trigger is ADC4_AWD1 */
+#define LL_GPDMA1_TRIGGER_ADC1_AWD1 58U /*!< GPDMA1 HW Trigger is ADC1_AWD1 */
+
+/* LPDMA1 triggers */
+#define LL_LPDMA1_TRIGGER_EXTI_LINE0 0U /*!< LPDMA1 HW Trigger is EXTI_LINE0 */
+#define LL_LPDMA1_TRIGGER_EXTI_LINE1 1U /*!< LPDMA1 HW Trigger is EXTI_LINE1 */
+#define LL_LPDMA1_TRIGGER_EXTI_LINE2 2U /*!< LPDMA1 HW Trigger is EXTI_LINE2 */
+#define LL_LPDMA1_TRIGGER_EXTI_LINE3 3U /*!< LPDMA1 HW Trigger is EXTI_LINE3 */
+#define LL_LPDMA1_TRIGGER_EXTI_LINE4 4U /*!< LPDMA1 HW Trigger is EXTI_LINE4 */
+#define LL_LPDMA1_TRIGGER_TAMP_TRG1 5U /*!< LPDMA1 HW Trigger is TAMP_TRG1 */
+#define LL_LPDMA1_TRIGGER_TAMP_TRG2 6U /*!< LPDMA1 HW Trigger is TAMP_TRG2 */
+#define LL_LPDMA1_TRIGGER_TAMP_TRG3 7U /*!< LPDMA1 HW Trigger is TAMP_TRG3 */
+#define LL_LPDMA1_TRIGGER_LPTIM1_CH1 8U /*!< LPDMA1 HW Trigger is LPTIM1_CH1 */
+#define LL_LPDMA1_TRIGGER_LPTIM1_CH2 9U /*!< LPDMA1 HW Trigger is LPTIM1_CH2 */
+#define LL_LPDMA1_TRIGGER_LPTIM3_CH1 10U /*!< LPDMA1 HW Trigger is LPTIM3_CH1 */
+#define LL_LPDMA1_TRIGGER_LPTIM4_OUT 11U /*!< LPDMA1 HW Trigger is LPTIM4_OUT */
+#define LL_LPDMA1_TRIGGER_COMP1_OUT 12U /*!< LPDMA1 HW Trigger is COMP1_OUT */
+#define LL_LPDMA1_TRIGGER_COMP2_OUT 13U /*!< LPDMA1 HW Trigger is COMP2_OUT */
+#define LL_LPDMA1_TRIGGER_RTC_ALRA_TRG 14U /*!< LPDMA1 HW Trigger is RTC_ALRA_TRG */
+#define LL_LPDMA1_TRIGGER_RTC_ALRB_TRG 15U /*!< LPDMA1 HW Trigger is RTC_ALRB_TRG */
+#define LL_LPDMA1_TRIGGER_RTC_WUT_TRG 16U /*!< LPDMA1 HW Trigger is RTC_WUT_TRG */
+#define LL_LPDMA1_TRIGGER_LPDMA1_CH0_TCF 18U /*!< LPDMA1 HW Trigger is LPDMA1_CH0_TCF */
+#define LL_LPDMA1_TRIGGER_LPDMA1_CH1_TCF 19U /*!< LPDMA1 HW Trigger is LPDMA1_CH1_TCF */
+#define LL_LPDMA1_TRIGGER_LPDMA1_CH2_TCF 20U /*!< LPDMA1 HW Trigger is LPDMA1_CH2_TCF */
+#define LL_LPDMA1_TRIGGER_LPDMA1_CH3_TCF 21U /*!< LPDMA1 HW Trigger is LPDMA1_CH3_TCF */
+#define LL_LPDMA1_TRIGGER_GPDMA1_CH0_TCF 22U /*!< LPDMA1 HW Trigger is GPDMA1_CH0_TCF */
+#define LL_LPDMA1_TRIGGER_GPDMA1_CH1_TCF 23U /*!< LPDMA1 HW Trigger is GPDMA1_CH1_TCF */
+#define LL_LPDMA1_TRIGGER_GPDMA1_CH4_TCF 24U /*!< LPDMA1 HW Trigger is GPDMA1_CH4_TCF */
+#define LL_LPDMA1_TRIGGER_GPDMA1_CH5_TCF 25U /*!< LPDMA1 HW Trigger is GPDMA1_CH5_TCF */
+#define LL_LPDMA1_TRIGGER_GPDMA1_CH6_TCF 26U /*!< LPDMA1 HW Trigger is GPDMA1_CH6_TCF */
+#define LL_LPDMA1_TRIGGER_GPDMA1_CH7_TCF 27U /*!< LPDMA1 HW Trigger is GPDMA1_CH7_TCF */
+#define LL_LPDMA1_TRIGGER_GPDMA1_CH12_TCF 28U /*!< LPDMA1 HW Trigger is GPDMA1_CH12_TCF */
+#define LL_LPDMA1_TRIGGER_GPDMA1_CH13_TCF 29U /*!< LPDMA1 HW Trigger is GPDMA1_CH13_TCF */
+#define LL_LPDMA1_TRIGGER_TIM2_TRGO 30U /*!< LPDMA1 HW Trigger is TIM2_TRGO */
+#define LL_LPDMA1_TRIGGER_TIM15_TRGO 31U /*!< LPDMA1 HW Trigger is TIM15_TRGO */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
+ * @{
+ */
+
+/** @defgroup DMA_LL_EM_COMMON_WRITE_READ_REGISTERS Common Write and Read Registers macros
+ * @{
+ */
+/**
+ * @brief Write a value in DMA register.
+ * @param __INSTANCE__ DMA Instance.
+ * @param __REG__ Register to be written.
+ * @param __VALUE__ Value to be written in the register.
+ * @retval None.
+ */
+#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in DMA register.
+ * @param __INSTANCE__ DMA Instance.
+ * @param __REG__ Register to be read.
+ * @retval Register value.
+ */
+#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
+ * @{
+ */
+/**
+ * @brief Convert DMAx_Channely into DMAx.
+ * @param __CHANNEL_INSTANCE__ DMAx_Channely.
+ * @retval DMAx.
+ */
+#define LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
+ (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)GPDMA1_Channel15)) ? LPDMA1 : GPDMA1)
+
+/**
+ * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y.
+ * @param __CHANNEL_INSTANCE__ DMAx_Channely.
+ * @retval LL_DMA_CHANNEL_y.
+ */
+#define LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
+ (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel0)) ? LL_DMA_CHANNEL_0 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)LPDMA1_Channel0)) ? LL_DMA_CHANNEL_0 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)LPDMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)LPDMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)LPDMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel7)) ? LL_DMA_CHANNEL_7 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel8)) ? LL_DMA_CHANNEL_8 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel9)) ? LL_DMA_CHANNEL_9 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel10)) ? LL_DMA_CHANNEL_10 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel11)) ? LL_DMA_CHANNEL_11 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel12)) ? LL_DMA_CHANNEL_12 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel13)) ? LL_DMA_CHANNEL_13 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel14)) ? LL_DMA_CHANNEL_14 : \
+ LL_DMA_CHANNEL_15)
+
+/**
+ * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely.
+ * @param __DMA_INSTANCE__ DMAx.
+ * @param __CHANNEL__ LL_DMA_CHANNEL_y.
+ * @retval DMAx_Channely.
+ */
+#define LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
+ ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_0))) \
+ ? GPDMA1_Channel0 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)LPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_0))) \
+ ? LPDMA1_Channel0 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) \
+ ? GPDMA1_Channel1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)LPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) \
+ ? LPDMA1_Channel1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) \
+ ? GPDMA1_Channel2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)LPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) \
+ ? LPDMA1_Channel2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) \
+ ? GPDMA1_Channel3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)LPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) \
+ ? LPDMA1_Channel3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) \
+ ? GPDMA1_Channel4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) \
+ ? GPDMA1_Channel5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) \
+ ? GPDMA1_Channel6 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) \
+ ? GPDMA1_Channel7 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_8))) \
+ ? GPDMA1_Channel8 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_9))) \
+ ? GPDMA1_Channel9 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_10)))\
+ ? GPDMA1_Channel10 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_11)))\
+ ? GPDMA1_Channel11 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_12)))\
+ ? GPDMA1_Channel12 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_13)))\
+ ? GPDMA1_Channel13 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_14)))\
+ ? GPDMA1_Channel14 : GPDMA1_Channel15)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
+ * @{
+ */
+
+/** @defgroup DMA_LL_EF_Configuration Configuration
+ * @{
+ */
+/**
+ * @brief Enable channel.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CCR EN LL_DMA_EnableChannel
+ * @param DMAx DMAx Instance.
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN);
+}
+
+/**
+ * @brief Disable channel.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CCR EN LL_DMA_DisableChannel
+ * @param DMAx DMAx Instance.
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR,
+ (DMA_CCR_SUSP | DMA_CCR_RESET));
+}
+
+/**
+ * @brief Check if channel is enabled or disabled.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CCR EN LL_DMA_IsEnabledChannel
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN)
+ == (DMA_CCR_EN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Reset channel.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CCR RESET LL_DMA_ResetChannel
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_ResetChannel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_RESET);
+}
+
+/**
+ * @brief Suspend channel.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CCR SUSP LL_DMA_SuspendChannel
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_SuspendChannel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP);
+}
+
+/**
+ * @brief Resume channel.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CCR SUSP LL_DMA_ResumeChannel
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_ResumeChannel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP);
+}
+
+/**
+ * @brief Check if channel is suspended.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CCR SUSP LL_DMA_IsSuspendedChannel
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsSuspendedChannel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP)
+ == (DMA_CCR_SUSP)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set linked-list base address.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CLBAR LBA LL_DMA_SetLinkedListBaseAddr
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param LinkedListBaseAddr Between 0 to 0xFFFF0000 (where the 4 LSB bytes
+ * are always 0)
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_SetLinkedListBaseAddr(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t LinkedListBaseAddr)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLBAR, DMA_CLBAR_LBA,
+ (LinkedListBaseAddr & DMA_CLBAR_LBA));
+}
+
+/**
+ * @brief Get linked-list base address.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CLBAR LBA LL_DMA_GetLinkedListBaseAddr
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval Value between 0 to 0xFFFF0000 (where the 4 LSB bytes are always 0)
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetLinkedListBaseAddr(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLBAR, DMA_CLBAR_LBA));
+}
+
+/**
+ * @brief Configure all parameters linked to channel control.
+ * @note This API is used for all available DMA channels.
+ * For LPDMA channels, LAP field programming is discarded.
+ * @rmtoll CCR PRIO LL_DMA_ConfigControl\n
+ * CCR LAP LL_DMA_ConfigControl\n
+ * CCR LSM LL_DMA_ConfigControl
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param Configuration This parameter must be a combination of all the following values:
+ * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT or @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT or
+ * @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT or @ref LL_DMA_HIGH_PRIORITY
+ * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0 or @ref LL_DMA_LINK_ALLOCATED_PORT1
+ * @arg @ref LL_DMA_LSM_FULL_EXECUTION or @ref LL_DMA_LSM_1LINK_EXECUTION
+ *@retval None.
+ */
+__STATIC_INLINE void LL_DMA_ConfigControl(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR,
+ (DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM), Configuration);
+}
+
+/**
+ * @brief Set priority level.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CCR PRIO LL_DMA_SetChannelPriorityLevel
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param Priority This parameter can be one of the following values:
+ * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT
+ * @arg @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT
+ * @arg @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT
+ * @arg @ref LL_DMA_HIGH_PRIORITY
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIO, Priority);
+}
+
+/**
+ * @brief Get Channel priority level.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CCR PRIO LL_DMA_GetChannelPriorityLevel
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT
+ * @arg @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT
+ * @arg @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT
+ * @arg @ref LL_DMA_HIGH_PRIORITY
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIO));
+}
+
+/**
+ * @brief Set linked-list allocated port.
+ * @note This API is not used for LPDMA channels.
+ * @rmtoll CCR LAP LL_DMA_SetLinkAllocatedPort
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param LinkAllocatedPort This parameter can be one of the following values:
+ * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0
+ * @arg @ref LL_DMA_LINK_ALLOCATED_PORT1
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_SetLinkAllocatedPort(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t LinkAllocatedPort)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR,
+ DMA_CCR_LAP, LinkAllocatedPort);
+}
+
+/**
+ * @brief Get linked-list allocated port.
+ * @note This API is not used for LPDMA channels.
+ * @rmtoll CCR LAP LL_DMA_GetLinkAllocatedPort
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0
+ * @arg @ref LL_DMA_LINK_ALLOCATED_PORT1
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetLinkAllocatedPort(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LAP));
+}
+
+/**
+ * @brief Set link step mode.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CCR LSM LL_DMA_SetLinkStepMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param LinkStepMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA_LSM_FULL_EXECUTION
+ * @arg @ref LL_DMA_LSM_1LINK_EXECUTION
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_SetLinkStepMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t LinkStepMode)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LSM, LinkStepMode);
+}
+
+/**
+ * @brief Get Link step mode.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CCR LSM LL_DMA_GetLinkStepMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_LSM_FULL_EXECUTION
+ * @arg @ref LL_DMA_LSM_1LINK_EXECUTION
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetLinkStepMode(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LSM));
+}
+
+/**
+ * @brief Configure data transfer.
+ * @note This API is used for all available DMA channels.
+ * For LPDMA channels DAP, DHX, DBX, SAP, SBX fields programming is
+ * discarded.
+ * @rmtoll CTR1 DAP LL_DMA_ConfigTransfer\n
+ * CTR1 DHX LL_DMA_ConfigTransfer\n
+ * CTR1 DBX LL_DMA_ConfigTransfer\n
+ * CTR1 DINC LL_DMA_ConfigTransfer\n
+ * CTR1 SAP LL_DMA_ConfigTransfer\n
+ * CTR1 SBX LL_DMA_ConfigTransfer\n
+ * CTR1 PAM LL_DMA_ConfigTransfer\n
+ * CTR1 SINC LL_DMA_ConfigTransfer
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param Configuration This parameter must be a combination of all the following values:
+ * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0 or @ref LL_DMA_DEST_ALLOCATED_PORT1
+ * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE or @ref LL_DMA_DEST_HALFWORD_EXCHANGE
+ * @arg @ref LL_DMA_DEST_BYTE_PRESERVE or @ref LL_DMA_DEST_BYTE_EXCHANGE
+ * @arg @ref LL_DMA_SRC_BYTE_PRESERVE or @ref LL_DMA_SRC_BYTE_EXCHANGE
+ * @arg @ref LL_DMA_DEST_FIXED or @ref LL_DMA_DEST_INCREMENT
+ * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE or @ref LL_DMA_DEST_DATAWIDTH_HALFWORD or
+ * @ref LL_DMA_DEST_DATAWIDTH_WORD
+ * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0 or @ref LL_DMA_SRC_ALLOCATED_PORT1
+ * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD or @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD or
+ * @ref LL_DMA_DATA_PACK_UNPACK
+ * @arg @ref LL_DMA_SRC_FIXED or @ref LL_DMA_SRC_INCREMENT
+ * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE or @ref LL_DMA_SRC_DATAWIDTH_HALFWORD or
+ * @ref LL_DMA_SRC_DATAWIDTH_WORD
+ *@retval None.
+ */
+__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
+ DMA_CTR1_DAP | DMA_CTR1_DHX | DMA_CTR1_DBX | DMA_CTR1_SBX | DMA_CTR1_DINC | DMA_CTR1_SINC | \
+ DMA_CTR1_SAP | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, Configuration);
+}
+
+/**
+ * @brief Configure source and destination burst length.
+ * @note This API is not used for LPDMA channels.
+ * @rmtoll CTR1 DBL_1 LL_DMA_SetDestBurstLength\n
+ * @rmtoll CTR1 SBL_1 LL_DMA_SetDestBurstLength
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param SrcBurstLength Between 1 to 64
+ * @param DestBurstLength Between 1 to 64
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_ConfigBurstLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcBurstLength,
+ uint32_t DestBurstLength)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
+ (DMA_CTR1_SBL_1 | DMA_CTR1_DBL_1), (((SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1) | \
+ (((DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1));
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ * @brief Configure all secure parameters linked to DMA channel.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll SECCFGR SEC LL_DMA_ConfigChannelSecure\n
+ * @rmtoll CTR1 SSEC LL_DMA_ConfigChannelSecure\n
+ * @rmtoll CTR1 DSEC LL_DMA_ConfigChannelSecure
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param Configuration This parameter must be a combination of all the following values:
+ * @arg @ref LL_DMA_CHANNEL_NSEC or @ref LL_DMA_CHANNEL_SEC
+ * @arg @ref LL_DMA_CHANNEL_SRC_NSEC or @ref LL_DMA_CHANNEL_SRC_SEC
+ * @arg @ref LL_DMA_CHANNEL_DEST_NSEC or @ref LL_DMA_CHANNEL_DEST_SEC
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_ConfigChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << Channel), ((Configuration & LL_DMA_CHANNEL_SEC) << Channel));
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
+ (DMA_CTR1_DSEC | DMA_CTR1_DSEC), (Configuration & (~LL_DMA_CHANNEL_SEC)));
+}
+
+/**
+ * @brief Enable security attribute of the DMA transfer to the destination.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CTR1 DSEC LL_DMA_EnableChannelDestSecure
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_EnableChannelDestSecure(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC);
+}
+
+/**
+ * @brief Disable security attribute of the DMA transfer to the destination.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CTR1 DSEC LL_DMA_DisableChannelDestSecure
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_DisableChannelDestSecure(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC);
+}
+
+/**
+ * @brief Check security attribute of the DMA transfer to the destination.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CTR1 DSEC LL_DMA_IsEnabledChannelDestSecure
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelDestSecure(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC)
+ == (DMA_CTR1_DSEC)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable security attribute of the DMA transfer from the source.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CTR1 SSEC LL_DMA_EnableChannelSrcSecure
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_EnableChannelSrcSecure(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC);
+}
+
+/**
+ * @brief Disable security attribute of the DMA transfer from the source.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CTR1 SSEC LL_DMA_DisableChannelSrcSecure
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_DisableChannelSrcSecure(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC);
+}
+
+/**
+ * @brief Check security attribute of the DMA transfer from the source.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CTR1 SSEC LL_DMA_IsEnabledChannelSrcSecure
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSrcSecure(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC)
+ == (DMA_CTR1_SSEC)) ? 1UL : 0UL);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/**
+ * @brief Set destination allocated port.
+ * @note This API is not used for LPDMA channels.
+ * @rmtoll CTR1 DAP LL_DMA_SetDestAllocatedPort
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param DestAllocatedPort This parameter can be one of the following values:
+ * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0
+ * @arg @ref LL_DMA_DEST_ALLOCATED_PORT1
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_SetDestAllocatedPort(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAllocatedPort)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DAP,
+ DestAllocatedPort);
+}
+
+/**
+ * @brief Get destination allocated port.
+ * @note This API is not used for LPDMA channels.
+ * @rmtoll CTR1 DAP LL_DMA_GetDestAllocatedPort
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0
+ * @arg @ref LL_DMA_DEST_ALLOCATED_PORT1
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetDestAllocatedPort(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DAP));
+}
+
+/**
+ * @brief Set destination half-word exchange.
+ * @note This API is not used for LPDMA channels.
+ * @rmtoll CTR1 DHX LL_DMA_SetDestHWordExchange
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param DestHWordExchange This parameter can be one of the following values:
+ * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE
+ * @arg @ref LL_DMA_DEST_HALFWORD_EXCHANGE
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_SetDestHWordExchange(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestHWordExchange)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DHX,
+ DestHWordExchange);
+}
+
+/**
+ * @brief Get destination half-word exchange.
+ * @note This API is not used for LPDMA channels.
+ * @rmtoll CTR1 DHX LL_DMA_GetDestHWordExchange
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE
+ * @arg @ref LL_DMA_DEST_HALFWORD_EXCHANGE
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetDestHWordExchange(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DHX));
+}
+
+/**
+ * @brief Set destination byte exchange.
+ * @note This API is not used for LPDMA channels.
+ * @rmtoll CTR1 DBX LL_DMA_SetDestByteExchange
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param DestByteExchange This parameter can be one of the following values:
+ * @arg @ref LL_DMA_DEST_BYTE_PRESERVE
+ * @arg @ref LL_DMA_DEST_BYTE_EXCHANGE
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_SetDestByteExchange(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestByteExchange)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBX,
+ DestByteExchange);
+}
+
+/**
+ * @brief Get destination byte exchange.
+ * @note This API is not used for LPDMA channels.
+ * @rmtoll CTR1 DBX LL_DMA_GetDestByteExchange
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_DEST_BYTE_PRESERVE
+ * @arg @ref LL_DMA_DEST_BYTE_EXCHANGE
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetDestByteExchange(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBX));
+}
+
+/**
+ * @brief Set source byte exchange.
+ * @note This API is not used for LPDMA channels.
+ * @rmtoll CTR1 SBX LL_DMA_SetSrcByteExchange
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param SrcByteExchange This parameter can be one of the following values:
+ * @arg @ref LL_DMA_SRC_BYTE_PRESERVE
+ * @arg @ref LL_DMA_SRC_BYTE_EXCHANGE
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_SetSrcByteExchange(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcByteExchange)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBX,
+ SrcByteExchange);
+}
+
+/**
+ * @brief Get source byte exchange.
+ * @note This API is not used for LPDMA channels.
+ * @rmtoll CTR1 SBX LL_DMA_GetSrcByteExchange
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_SRC_BYTE_PRESERVE
+ * @arg @ref LL_DMA_SRC_BYTE_EXCHANGE
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetSrcByteExchange(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBX));
+}
+
+/**
+ * @brief Set destination burst length.
+ * @note This API is not used for LPDMA channels.
+ * @rmtoll CTR1 DBL_1 LL_DMA_SetDestBurstLength
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param DestBurstLength Between 1 to 64
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_SetDestBurstLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestBurstLength)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBL_1,
+ ((DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1);
+}
+
+/**
+ * @brief Get destination burst length.
+ * @note This API is not used for LPDMA channels.
+ * @rmtoll CTR1 DBL_1 LL_DMA_GetDestBurstLength
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval Between 1 to 64.
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetDestBurstLength(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
+ DMA_CTR1_DBL_1) >> DMA_CTR1_DBL_1_Pos) + 1U);
+}
+
+/**
+ * @brief Set destination increment mode.
+ * @note This API is not used for LPDMA channels.
+ * @rmtoll CTR1 DINC LL_DMA_SetDestIncMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param DestInc This parameter can be one of the following values:
+ * @arg @ref LL_DMA_DEST_FIXED
+ * @arg @ref LL_DMA_DEST_INCREMENT
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_SetDestIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestInc)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DINC, DestInc);
+}
+
+/**
+ * @brief Get destination increment mode.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CTR1 DINC LL_DMA_GetDestinationIncMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_DEST_FIXED
+ * @arg @ref LL_DMA_DEST_INCREMENT
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetDestIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DINC));
+}
+
+/**
+ * @brief Set destination data width.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CTR1 DDW_LOG2 LL_DMA_SetDestDataWidth
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param DestDataWidth This parameter can be one of the following values:
+ * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE
+ * @arg @ref LL_DMA_DEST_DATAWIDTH_HALFWORD
+ * @arg @ref LL_DMA_DEST_DATAWIDTH_WORD
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_SetDestDataWidth(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestDataWidth)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2,
+ DestDataWidth);
+}
+
+/**
+ * @brief Get destination data width.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CTR1 DDW_LOG2 LL_DMA_GetDestDataWidth
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE
+ * @arg @ref LL_DMA_DEST_DATAWIDTH_HALFWORD
+ * @arg @ref LL_DMA_DEST_DATAWIDTH_WORD
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetDestDataWidth(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2));
+}
+
+/**
+ * @brief Set source allocated port.
+ * @note This API is not used for LPDMA channels.
+ * @rmtoll CTR1 SAP LL_DMA_SetSrcAllocatedPort
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param SrcAllocatedPort This parameter can be one of the following values:
+ * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0
+ * @arg @ref LL_DMA_SRC_ALLOCATED_PORT1
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_SetSrcAllocatedPort(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAllocatedPort)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SAP,
+ SrcAllocatedPort);
+}
+
+/**
+ * @brief Get source allocated port.
+ * @note This API is not used for LPDMA channels.
+ * @rmtoll CTR1 SAP LL_DMA_GetSrcAllocatedPort
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0
+ * @arg @ref LL_DMA_SRC_ALLOCATED_PORT1
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetSrcAllocatedPort(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SAP));
+}
+
+/**
+ * @brief Set data alignment mode.
+ * @note This API is used for all available DMA channels.
+ * For LPDMA channels, PAM field is reduced to one bit.
+ * @rmtoll CTR1 PAM LL_DMA_SetDataAlignment
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param DataAlignment This parameter can be one of the following values:
+ * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD
+ * @arg @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD
+ * @arg @ref LL_DMA_DATA_PACK_UNPACK (This value is not allowed for LPDMA channels)
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_SetDataAlignment(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DataAlignment)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM,
+ DataAlignment);
+}
+
+/**
+ * @brief Get data alignment mode.
+ * @note This API is used for all available DMA channels.
+ * For LPDMA channels, PAM field is reduced to one bit.
+ * @rmtoll CTR1 PAM LL_DMA_GetDataAlignment
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD
+ * @arg @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD
+ * @arg @ref LL_DMA_DATA_PACK_UNPACK (This value is not allowed for LPDMA channels)
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetDataAlignment(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM));
+}
+
+/**
+ * @brief Set source burst length.
+ * @note This API is not used for LPDMA channels.
+ * @rmtoll CTR1 SBL_1 LL_DMA_SetSrcBurstLength
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param SrcBurstLength Between 1 to 64
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_SetSrcBurstLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcBurstLength)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBL_1,
+ ((SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1);
+}
+
+/**
+ * @brief Get source burst length.
+ * @note This API is not used for LPDMA channels.
+ * @rmtoll CTR1 SBL_1 LL_DMA_GetSrcBurstLength
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval Between 1 to 64
+ * @retval None.
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetSrcBurstLength(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
+ DMA_CTR1_SBL_1) >> DMA_CTR1_SBL_1_Pos) + 1U);
+}
+
+/**
+ * @brief Set source increment mode.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CTR1 SINC LL_DMA_SetSrcIncMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param SrcInc This parameter can be one of the following values:
+ * @arg @ref LL_DMA_SRC_FIXED
+ * @arg @ref LL_DMA_SRC_INCREMENT
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_SetSrcIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcInc)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SINC, SrcInc);
+}
+
+/**
+ * @brief Get source increment mode.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CTR1 SINC LL_DMA_GetSrcIncMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_SRC_FIXED
+ * @arg @ref LL_DMA_SRC_INCREMENT
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetSrcIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SINC));
+}
+
+/**
+ * @brief Set source data width.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CTR1 SDW_LOG2 LL_DMA_SetSrcDataWidth
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param SrcDataWidth This parameter can be one of the following values:
+ * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE
+ * @arg @ref LL_DMA_SRC_DATAWIDTH_HALFWORD
+ * @arg @ref LL_DMA_SRC_DATAWIDTH_WORD
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_SetSrcDataWidth(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcDataWidth)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2,
+ SrcDataWidth);
+}
+
+/**
+ * @brief Get Source Data width.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CTR1 SDW_LOG2 LL_DMA_GetSrcDataWidth
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE
+ * @arg @ref LL_DMA_SRC_DATAWIDTH_HALFWORD
+ * @arg @ref LL_DMA_SRC_DATAWIDTH_WORD
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetSrcDataWidth(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2));
+}
+
+/**
+ * @brief Configure channel transfer.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CTR2 TCEM LL_DMA_ConfigChannelTransfer\n
+ * CTR2 TRIGPOL LL_DMA_ConfigChannelTransfer\n
+ * CTR2 TRIGM LL_DMA_ConfigChannelTransfer\n
+ * CTR2 BREQ LL_DMA_ConfigChannelTransfer\n
+ * CTR2 DREQ LL_DMA_ConfigChannelTransfer\n
+ * CTR2 SWREQ LL_DMA_ConfigChannelTransfer
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param Configuration This parameter must be a combination of all the following values:
+ * @arg @ref LL_DMA_TCEM_BLK_TRANSFER or @ref LL_DMA_TCEM_RPT_BLK_TRANSFER or
+ * @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER or @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER
+ * @arg @ref LL_DMA_TRIG_POLARITY_MASKED or @ref LL_DMA_HWREQUEST_BLK
+ * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST or @ref LL_DMA_TRIG_POLARITY_RISING or
+ * @ref LL_DMA_TRIG_POLARITY_FALLING
+ * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER or @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER or
+ * @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER or @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER
+ * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or
+ * @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+ *@retval None.
+ */
+__STATIC_INLINE void LL_DMA_ConfigChannelTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
+ (DMA_CTR2_TCEM | DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGM | DMA_CTR2_DREQ | DMA_CTR2_SWREQ | DMA_CTR2_BREQ),
+ Configuration);
+}
+
+/**
+ * @brief Set transfer event mode.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CTR2 TCEM LL_DMA_SetTransferEventMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param TransferEventMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA_TCEM_BLK_TRANSFER
+ * @arg @ref LL_DMA_TCEM_RPT_BLK_TRANSFER
+ * @arg @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER
+ * @arg @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_SetTransferEventMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TransferEventMode)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TCEM,
+ TransferEventMode);
+}
+
+/**
+ * @brief Get transfer event mode.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CTR2 TCEM LL_DMA_GetTransferEventMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_TCEM_BLK_TRANSFER
+ * @arg @ref LL_DMA_TCEM_RPT_BLK_TRANSFER
+ * @arg @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER
+ * @arg @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetTransferEventMode(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TCEM));
+}
+
+/**
+ * @brief Set trigger polarity.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CTR2 TRIGPOL LL_DMA_SetTriggerPolarity
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param TriggerPolarity This parameter can be one of the following values:
+ * @arg @ref LL_DMA_TRIG_POLARITY_MASKED
+ * @arg @ref LL_DMA_TRIG_POLARITY_RISING
+ * @arg @ref LL_DMA_TRIG_POLARITY_FALLING
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_SetTriggerPolarity(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TriggerPolarity)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGPOL,
+ TriggerPolarity);
+}
+
+/**
+ * @brief Get trigger polarity.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CTR2 TRIGPOL LL_DMA_GetTriggerPolarity
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_TRIG_POLARITY_MASKED
+ * @arg @ref LL_DMA_TRIG_POLARITY_RISING
+ * @arg @ref LL_DMA_TRIG_POLARITY_FALLING
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetTriggerPolarity(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGPOL));
+}
+
+/**
+ * @brief Set trigger Mode.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CTR2 TRIGM LL_DMA_SetTriggerMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param TriggerMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER
+ * @arg @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER (This value is allowed only for 2D addressing channels)
+ * @arg @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER
+ * @arg @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_SetTriggerMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TriggerMode)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGM,
+ TriggerMode);
+}
+
+/**
+ * @brief Get trigger Mode.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CTR2 TRIGM LL_DMA_GetTriggerMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER
+ * @arg @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER (This value is allowed only for 2D addressing channels)
+ * @arg @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER
+ * @arg @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetTriggerMode(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGM));
+}
+
+/**
+ * @brief Set destination hardware and software transfer request.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CTR2 DREQ LL_DMA_SetDataTransferDirection\n
+ * @rmtoll CTR2 SWREQ LL_DMA_SetDataTransferDirection
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param Direction This parameter can be one of the following values:
+ * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH (This value is not allowed for LPDMA channels)
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY (This value is not allowed for LPDMA channels)
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
+ DMA_CTR2_DREQ | DMA_CTR2_SWREQ, Direction);
+}
+
+/**
+ * @brief Get destination hardware and software transfer request.
+ * @note This API is used for all available DMA channels.
+ * For LPDMA channels, DREQ fields programming is discarded.
+ * @rmtoll CTR2 DREQ LL_DMA_GetDataTransferDirection\n
+ * @rmtoll CTR2 SWREQ LL_DMA_GetDataTransferDirection
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH (This value is not allowed for LPDMA channels)
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY (This value is not allowed for LPDMA channels)
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
+ DMA_CTR2_DREQ | DMA_CTR2_SWREQ));
+}
+
+/**
+ * @brief Set block hardware request.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CTR2 BREQ LL_DMA_SetBlkHWRequest\n
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param BlkHWRequest This parameter can be one of the following values:
+ * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST
+ * @arg @ref LL_DMA_HWREQUEST_BLK
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_SetBlkHWRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkHWRequest)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_BREQ,
+ BlkHWRequest);
+}
+
+/**
+ * @brief Get block hardware request.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CTR2 BREQ LL_DMA_GetBlkHWRequest\n
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST
+ * @arg @ref LL_DMA_HWREQUEST_BLK
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetBlkHWRequest(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_BREQ));
+}
+
+/**
+ * @brief Set hardware request.
+ * @note This API is used for all available DMA channels.
+ * For LPDMA channels, REQSEL fields is reduced to 5 bits.
+ * @rmtoll CTR2 REQSEL LL_DMA_SetPeriphRequest
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param Request This parameter can be one of the following values:
+ * @arg @ref LL_GPDMA1_REQUEST_ADC1
+ * @arg @ref LL_GPDMA1_REQUEST_ADC4
+ * @arg @ref LL_GPDMA1_REQUEST_DAC1_CH1
+ * @arg @ref LL_GPDMA1_REQUEST_DAC1_CH2
+ * @arg @ref LL_GPDMA1_REQUEST_TIM6_UP
+ * @arg @ref LL_GPDMA1_REQUEST_TIM7_UP
+ * @arg @ref LL_GPDMA1_REQUEST_SPI1_RX
+ * @arg @ref LL_GPDMA1_REQUEST_SPI1_TX
+ * @arg @ref LL_GPDMA1_REQUEST_SPI2_RX
+ * @arg @ref LL_GPDMA1_REQUEST_SPI2_TX
+ * @arg @ref LL_GPDMA1_REQUEST_SPI3_RX
+ * @arg @ref LL_GPDMA1_REQUEST_SPI3_TX
+ * @arg @ref LL_GPDMA1_REQUEST_I2C1_RX
+ * @arg @ref LL_GPDMA1_REQUEST_I2C1_TX
+ * @arg @ref LL_GPDMA1_REQUEST_I2C1_EVC
+ * @arg @ref LL_GPDMA1_REQUEST_I2C2_RX
+ * @arg @ref LL_GPDMA1_REQUEST_I2C2_TX
+ * @arg @ref LL_GPDMA1_REQUEST_I2C2_EVC
+ * @arg @ref LL_GPDMA1_REQUEST_I2C3_RX
+ * @arg @ref LL_GPDMA1_REQUEST_I2C3_TX
+ * @arg @ref LL_GPDMA1_REQUEST_I2C3_EVC
+ * @arg @ref LL_GPDMA1_REQUEST_I2C4_RX
+ * @arg @ref LL_GPDMA1_REQUEST_I2C4_TX
+ * @arg @ref LL_GPDMA1_REQUEST_I2C4_EVC
+ * @arg @ref LL_GPDMA1_REQUEST_USART1_RX
+ * @arg @ref LL_GPDMA1_REQUEST_USART1_TX
+ * @arg @ref LL_GPDMA1_REQUEST_USART2_RX
+ * @arg @ref LL_GPDMA1_REQUEST_USART2_TX
+ * @arg @ref LL_GPDMA1_REQUEST_USART3_RX
+ * @arg @ref LL_GPDMA1_REQUEST_USART3_TX
+ * @arg @ref LL_GPDMA1_REQUEST_UART4_RX
+ * @arg @ref LL_GPDMA1_REQUEST_UART4_TX
+ * @arg @ref LL_GPDMA1_REQUEST_UART5_RX
+ * @arg @ref LL_GPDMA1_REQUEST_UART5_TX
+ * @arg @ref LL_GPDMA1_REQUEST_LPUART1_RX
+ * @arg @ref LL_GPDMA1_REQUEST_LPUART1_TX
+ * @arg @ref LL_GPDMA1_REQUEST_SAI1_A
+ * @arg @ref LL_GPDMA1_REQUEST_SAI1_B
+ * @arg @ref LL_GPDMA1_REQUEST_SAI2_A
+ * @arg @ref LL_GPDMA1_REQUEST_SAI2_B
+ * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI1
+ * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI2
+ * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH1
+ * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH2
+ * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH3
+ * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH4
+ * @arg @ref LL_GPDMA1_REQUEST_TIM1_UP
+ * @arg @ref LL_GPDMA1_REQUEST_TIM1_TRIG
+ * @arg @ref LL_GPDMA1_REQUEST_TIM1_COM
+ * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH1
+ * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH2
+ * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH3
+ * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH4
+ * @arg @ref LL_GPDMA1_REQUEST_TIM8_UP
+ * @arg @ref LL_GPDMA1_REQUEST_TIM8_TRIG
+ * @arg @ref LL_GPDMA1_REQUEST_TIM8_COM
+ * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH1
+ * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH2
+ * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH3
+ * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH4
+ * @arg @ref LL_GPDMA1_REQUEST_TIM2_UP
+ * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH1
+ * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH2
+ * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH3
+ * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH4
+ * @arg @ref LL_GPDMA1_REQUEST_TIM3_UP
+ * @arg @ref LL_GPDMA1_REQUEST_TIM3_TRIG
+ * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH1
+ * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH2
+ * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH3
+ * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH4
+ * @arg @ref LL_GPDMA1_REQUEST_TIM4_UP
+ * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH1
+ * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH2
+ * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH3
+ * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH4
+ * @arg @ref LL_GPDMA1_REQUEST_TIM5_UP
+ * @arg @ref LL_GPDMA1_REQUEST_TIM5_TRIG
+ * @arg @ref LL_GPDMA1_REQUEST_TIM15_CH1
+ * @arg @ref LL_GPDMA1_REQUEST_TIM15_UP
+ * @arg @ref LL_GPDMA1_REQUEST_TIM15_TRIG
+ * @arg @ref LL_GPDMA1_REQUEST_TIM15_COM
+ * @arg @ref LL_GPDMA1_REQUEST_TIM16_CH1
+ * @arg @ref LL_GPDMA1_REQUEST_TIM16_UP
+ * @arg @ref LL_GPDMA1_REQUEST_TIM17_CH1
+ * @arg @ref LL_GPDMA1_REQUEST_TIM17_UP
+ * @arg @ref LL_GPDMA1_REQUEST_DCMI
+ * @arg @ref LL_GPDMA1_REQUEST_AES_IN
+ * @arg @ref LL_GPDMA1_REQUEST_AES_OUT
+ * @arg @ref LL_GPDMA1_REQUEST_HASH_IN
+ * @arg @ref LL_GPDMA1_REQUEST_UCPD1_TX
+ * @arg @ref LL_GPDMA1_REQUEST_UCPD1_RX
+ * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT0
+ * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT1
+ * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT2
+ * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT3
+ * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT4
+ * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT5
+ * @arg @ref LL_GPDMA1_REQUEST_ADF1_FLT0
+ * @arg @ref LL_GPDMA1_REQUEST_FMAC_READ
+ * @arg @ref LL_GPDMA1_REQUEST_FMAC_WRITE
+ * @arg @ref LL_GPDMA1_REQUEST_CORDIC_READ
+ * @arg @ref LL_GPDMA1_REQUEST_CORDIC_WRITE
+ * @arg @ref LL_GPDMA1_REQUEST_SAES_IN
+ * @arg @ref LL_GPDMA1_REQUEST_SAES_OUT
+ * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC1
+ * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC2
+ * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_UE
+ * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC1
+ * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC2
+ * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_UE
+ * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC1
+ * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC2
+ * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_UE
+ *
+ * @arg @ref LL_LPDMA1_REQUEST_LPUART1_RX
+ * @arg @ref LL_LPDMA1_REQUEST_LPUART1_TX
+ * @arg @ref LL_LPDMA1_REQUEST_SPI3_RX
+ * @arg @ref LL_LPDMA1_REQUEST_SPI3_TX
+ * @arg @ref LL_LPDMA1_REQUEST_I2C3_RX
+ * @arg @ref LL_LPDMA1_REQUEST_I2C3_TX
+ * @arg @ref LL_LPDMA1_REQUEST_I2C3_EVC
+ * @arg @ref LL_LPDMA1_REQUEST_ADC4
+ * @arg @ref LL_LPDMA1_REQUEST_DAC1_CH1
+ * @arg @ref LL_LPDMA1_REQUEST_DAC1_CH2
+ * @arg @ref LL_LPDMA1_REQUEST_ADF1_FLT0
+ * @arg @ref LL_LPDMA1_REQUEST_LPTIM1_IC1
+ * @arg @ref LL_LPDMA1_REQUEST_LPTIM1_IC2
+ * @arg @ref LL_LPDMA1_REQUEST_LPTIM1_UE
+ * @arg @ref LL_LPDMA1_REQUEST_LPTIM3_IC1
+ * @arg @ref LL_LPDMA1_REQUEST_LPTIM3_IC2
+ * @arg @ref LL_LPDMA1_REQUEST_LPTIM3_UE
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_REQSEL, Request);
+}
+
+/**
+ * @brief Get hardware request.
+ * @note This API is used for all available DMA channels.
+ * For LPDMA channels, REQSEL fields is reduced to 5 bits.
+ * @rmtoll CTR2 REQSEL LL_DMA_GetPeriphRequest
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPDMA1_REQUEST_ADC1
+ * @arg @ref LL_GPDMA1_REQUEST_ADC4
+ * @arg @ref LL_GPDMA1_REQUEST_DAC1_CH1
+ * @arg @ref LL_GPDMA1_REQUEST_DAC1_CH2
+ * @arg @ref LL_GPDMA1_REQUEST_TIM6_UP
+ * @arg @ref LL_GPDMA1_REQUEST_TIM7_UP
+ * @arg @ref LL_GPDMA1_REQUEST_SPI1_RX
+ * @arg @ref LL_GPDMA1_REQUEST_SPI1_TX
+ * @arg @ref LL_GPDMA1_REQUEST_SPI2_RX
+ * @arg @ref LL_GPDMA1_REQUEST_SPI2_TX
+ * @arg @ref LL_GPDMA1_REQUEST_SPI3_RX
+ * @arg @ref LL_GPDMA1_REQUEST_SPI3_TX
+ * @arg @ref LL_GPDMA1_REQUEST_I2C1_RX
+ * @arg @ref LL_GPDMA1_REQUEST_I2C1_TX
+ * @arg @ref LL_GPDMA1_REQUEST_I2C1_EVC
+ * @arg @ref LL_GPDMA1_REQUEST_I2C2_RX
+ * @arg @ref LL_GPDMA1_REQUEST_I2C2_TX
+ * @arg @ref LL_GPDMA1_REQUEST_I2C2_EVC
+ * @arg @ref LL_GPDMA1_REQUEST_I2C3_RX
+ * @arg @ref LL_GPDMA1_REQUEST_I2C3_TX
+ * @arg @ref LL_GPDMA1_REQUEST_I2C3_EVC
+ * @arg @ref LL_GPDMA1_REQUEST_I2C4_RX
+ * @arg @ref LL_GPDMA1_REQUEST_I2C4_TX
+ * @arg @ref LL_GPDMA1_REQUEST_I2C4_EVC
+ * @arg @ref LL_GPDMA1_REQUEST_USART1_RX
+ * @arg @ref LL_GPDMA1_REQUEST_USART1_TX
+ * @arg @ref LL_GPDMA1_REQUEST_USART2_RX
+ * @arg @ref LL_GPDMA1_REQUEST_USART2_TX
+ * @arg @ref LL_GPDMA1_REQUEST_USART3_RX
+ * @arg @ref LL_GPDMA1_REQUEST_USART3_TX
+ * @arg @ref LL_GPDMA1_REQUEST_UART4_RX
+ * @arg @ref LL_GPDMA1_REQUEST_UART4_TX
+ * @arg @ref LL_GPDMA1_REQUEST_UART5_RX
+ * @arg @ref LL_GPDMA1_REQUEST_UART5_TX
+ * @arg @ref LL_GPDMA1_REQUEST_LPUART1_RX
+ * @arg @ref LL_GPDMA1_REQUEST_LPUART1_TX
+ * @arg @ref LL_GPDMA1_REQUEST_SAI1_A
+ * @arg @ref LL_GPDMA1_REQUEST_SAI1_B
+ * @arg @ref LL_GPDMA1_REQUEST_SAI2_A
+ * @arg @ref LL_GPDMA1_REQUEST_SAI2_B
+ * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI1
+ * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI2
+ * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH1
+ * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH2
+ * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH3
+ * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH4
+ * @arg @ref LL_GPDMA1_REQUEST_TIM1_UP
+ * @arg @ref LL_GPDMA1_REQUEST_TIM1_TRIG
+ * @arg @ref LL_GPDMA1_REQUEST_TIM1_COM
+ * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH1
+ * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH2
+ * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH3
+ * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH4
+ * @arg @ref LL_GPDMA1_REQUEST_TIM8_UP
+ * @arg @ref LL_GPDMA1_REQUEST_TIM8_TRIG
+ * @arg @ref LL_GPDMA1_REQUEST_TIM8_COM
+ * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH1
+ * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH2
+ * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH3
+ * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH4
+ * @arg @ref LL_GPDMA1_REQUEST_TIM2_UP
+ * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH1
+ * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH2
+ * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH3
+ * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH4
+ * @arg @ref LL_GPDMA1_REQUEST_TIM3_UP
+ * @arg @ref LL_GPDMA1_REQUEST_TIM3_TRIG
+ * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH1
+ * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH2
+ * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH3
+ * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH4
+ * @arg @ref LL_GPDMA1_REQUEST_TIM4_UP
+ * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH1
+ * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH2
+ * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH3
+ * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH4
+ * @arg @ref LL_GPDMA1_REQUEST_TIM5_UP
+ * @arg @ref LL_GPDMA1_REQUEST_TIM5_TRIG
+ * @arg @ref LL_GPDMA1_REQUEST_TIM15_CH1
+ * @arg @ref LL_GPDMA1_REQUEST_TIM15_UP
+ * @arg @ref LL_GPDMA1_REQUEST_TIM15_TRIG
+ * @arg @ref LL_GPDMA1_REQUEST_TIM15_COM
+ * @arg @ref LL_GPDMA1_REQUEST_TIM16_CH1
+ * @arg @ref LL_GPDMA1_REQUEST_TIM16_UP
+ * @arg @ref LL_GPDMA1_REQUEST_TIM17_CH1
+ * @arg @ref LL_GPDMA1_REQUEST_TIM17_UP
+ * @arg @ref LL_GPDMA1_REQUEST_DCMI
+ * @arg @ref LL_GPDMA1_REQUEST_AES_IN
+ * @arg @ref LL_GPDMA1_REQUEST_AES_OUT
+ * @arg @ref LL_GPDMA1_REQUEST_HASH_IN
+ * @arg @ref LL_GPDMA1_REQUEST_UCPD1_TX
+ * @arg @ref LL_GPDMA1_REQUEST_UCPD1_RX
+ * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT0
+ * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT1
+ * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT2
+ * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT3
+ * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT4
+ * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT5
+ * @arg @ref LL_GPDMA1_REQUEST_ADF1_FLT0
+ * @arg @ref LL_GPDMA1_REQUEST_FMAC_READ
+ * @arg @ref LL_GPDMA1_REQUEST_FMAC_WRITE
+ * @arg @ref LL_GPDMA1_REQUEST_CORDIC_READ
+ * @arg @ref LL_GPDMA1_REQUEST_CORDIC_WRITE
+ * @arg @ref LL_GPDMA1_REQUEST_SAES_IN
+ * @arg @ref LL_GPDMA1_REQUEST_SAES_OUT
+ * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC1
+ * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC2
+ * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_UE
+ * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC1
+ * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC2
+ * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_UE
+ * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC1
+ * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC2
+ * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_UE
+ *
+ * @arg @ref LL_LPDMA1_REQUEST_LPUART1_RX
+ * @arg @ref LL_LPDMA1_REQUEST_LPUART1_TX
+ * @arg @ref LL_LPDMA1_REQUEST_SPI3_RX
+ * @arg @ref LL_LPDMA1_REQUEST_SPI3_TX
+ * @arg @ref LL_LPDMA1_REQUEST_I2C3_RX
+ * @arg @ref LL_LPDMA1_REQUEST_I2C3_TX
+ * @arg @ref LL_LPDMA1_REQUEST_I2C3_EVC
+ * @arg @ref LL_LPDMA1_REQUEST_ADC4
+ * @arg @ref LL_LPDMA1_REQUEST_DAC1_CH1
+ * @arg @ref LL_LPDMA1_REQUEST_DAC1_CH2
+ * @arg @ref LL_LPDMA1_REQUEST_ADF1_FLT0
+ * @arg @ref LL_LPDMA1_REQUEST_LPTIM1_IC1
+ * @arg @ref LL_LPDMA1_REQUEST_LPTIM1_IC2
+ * @arg @ref LL_LPDMA1_REQUEST_LPTIM1_UE
+ * @arg @ref LL_LPDMA1_REQUEST_LPTIM3_IC1
+ * @arg @ref LL_LPDMA1_REQUEST_LPTIM3_IC2
+ * @arg @ref LL_LPDMA1_REQUEST_LPTIM3_UE
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_REQSEL));
+}
+
+/**
+ * @brief Set hardware trigger.
+ * @note This API is used for all available DMA channels.
+ * For LPDMA channels, TRIGSEL fields is reduced to 5 bits.
+ * @rmtoll CTR2 TRIGSEL LL_DMA_SetHWTrigger
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param Trigger This parameter can be one of the following values:
+ * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE0
+ * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE1
+ * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE2
+ * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE3
+ * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG1
+ * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG2
+ * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG3
+ * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH1
+ * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH2
+ * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH1
+ * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH2
+ * @arg @ref LL_GPDMA1_TRIGGER_LPTIM4_OUT
+ * @arg @ref LL_GPDMA1_TRIGGER_COMP1_OUT
+ * @arg @ref LL_GPDMA1_TRIGGER_COMP2_OUT
+ * @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRA_TRG
+ * @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRB_TRG
+ * @arg @ref LL_GPDMA1_TRIGGER_RTC_WUT_TRG
+ * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF
+ * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF
+ * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF
+ * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF
+ * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF
+ * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF
+ * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF
+ * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF
+ * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH8_TCF
+ * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH9_TCF
+ * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH10_TCF
+ * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH11_TCF
+ * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH12_TCF
+ * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH13_TCF
+ * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH14_TCF
+ * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH15_TCF
+ * @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH0_TCF
+ * @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH1_TCF
+ * @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH2_TCF
+ * @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH3_TCF
+ * @arg @ref LL_GPDMA1_TRIGGER_TIM2_TRGO
+ * @arg @ref LL_GPDMA1_TRIGGER_TIM15_TRGO
+ *
+ * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE0
+ * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE1
+ * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE2
+ * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE3
+ * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE4
+ * @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG1
+ * @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG2
+ * @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG3
+ * @arg @ref LL_LPDMA1_TRIGGER_LPTIM1_CH1
+ * @arg @ref LL_LPDMA1_TRIGGER_LPTIM1_CH2
+ * @arg @ref LL_LPDMA1_TRIGGER_LPTIM3_CH1
+ * @arg @ref LL_LPDMA1_TRIGGER_LPTIM4_OUT
+ * @arg @ref LL_LPDMA1_TRIGGER_COMP1_OUT
+ * @arg @ref LL_LPDMA1_TRIGGER_COMP2_OUT
+ * @arg @ref LL_LPDMA1_TRIGGER_RTC_ALRA_TRG
+ * @arg @ref LL_LPDMA1_TRIGGER_RTC_ALRB_TRG
+ * @arg @ref LL_LPDMA1_TRIGGER_RTC_WUT_TRG
+ * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH0_TCF
+ * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH1_TCF
+ * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH2_TCF
+ * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH3_TCF
+ * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH0_TCF
+ * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH1_TCF
+ * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH4_TCF
+ * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH5_TCF
+ * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH6_TCF
+ * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH7_TCF
+ * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH12_TCF
+ * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH13_TCF
+ * @arg @ref LL_LPDMA1_TRIGGER_TIM2_TRGO
+ * @arg @ref LL_LPDMA1_TRIGGER_TIM15_TRGO
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_SetHWTrigger(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Trigger)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGSEL,
+ (Trigger << DMA_CTR2_TRIGSEL_Pos) & DMA_CTR2_TRIGSEL);
+}
+
+/**
+ * @brief Get hardware triggers.
+ * @note This API is used for all available DMA channels.
+ * For LPDMA channels, TRIGSEL fields is reduced to 5 bits.
+ * @rmtoll CTR2 TRIGSEL LL_DMA_GetHWTrigger
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE0
+ * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE1
+ * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE2
+ * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE3
+ * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG1
+ * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG2
+ * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG3
+ * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH1
+ * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH2
+ * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH1
+ * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH2
+ * @arg @ref LL_GPDMA1_TRIGGER_LPTIM4_OUT
+ * @arg @ref LL_GPDMA1_TRIGGER_COMP1_OUT
+ * @arg @ref LL_GPDMA1_TRIGGER_COMP2_OUT
+ * @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRA_TRG
+ * @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRB_TRG
+ * @arg @ref LL_GPDMA1_TRIGGER_RTC_WUT_TRG
+ * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF
+ * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF
+ * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF
+ * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF
+ * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF
+ * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF
+ * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF
+ * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF
+ * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH8_TCF
+ * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH9_TCF
+ * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH10_TCF
+ * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH11_TCF
+ * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH12_TCF
+ * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH13_TCF
+ * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH14_TCF
+ * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH15_TCF
+ * @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH0_TCF
+ * @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH1_TCF
+ * @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH2_TCF
+ * @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH3_TCF
+ * @arg @ref LL_GPDMA1_TRIGGER_TIM2_TRGO
+ * @arg @ref LL_GPDMA1_TRIGGER_TIM15_TRGO
+ *
+ * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE0
+ * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE1
+ * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE2
+ * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE3
+ * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE4
+ * @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG1
+ * @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG2
+ * @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG3
+ * @arg @ref LL_LPDMA1_TRIGGER_LPTIM1_CH1
+ * @arg @ref LL_LPDMA1_TRIGGER_LPTIM1_CH2
+ * @arg @ref LL_LPDMA1_TRIGGER_LPTIM3_CH1
+ * @arg @ref LL_LPDMA1_TRIGGER_LPTIM4_OUT
+ * @arg @ref LL_LPDMA1_TRIGGER_COMP1_OUT
+ * @arg @ref LL_LPDMA1_TRIGGER_COMP2_OUT
+ * @arg @ref LL_LPDMA1_TRIGGER_RTC_ALRA_TRG
+ * @arg @ref LL_LPDMA1_TRIGGER_RTC_ALRB_TRG
+ * @arg @ref LL_LPDMA1_TRIGGER_RTC_WUT_TRG
+ * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH0_TCF
+ * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH1_TCF
+ * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH2_TCF
+ * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH3_TCF
+ * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH0_TCF
+ * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH1_TCF
+ * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH4_TCF
+ * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH5_TCF
+ * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH6_TCF
+ * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH7_TCF
+ * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH12_TCF
+ * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH13_TCF
+ * @arg @ref LL_LPDMA1_TRIGGER_TIM2_TRGO
+ * @arg @ref LL_LPDMA1_TRIGGER_TIM15_TRGO
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetHWTrigger(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
+ DMA_CTR2_TRIGSEL) >> DMA_CTR2_TRIGSEL_Pos);
+}
+
+/**
+ * @brief Configure addresses update.
+ * @note This API is used only for 2D addressing channels.
+ * @rmtoll CBR1 BRDDEC LL_DMA_ConfigBlkRptAddrUpdate\n
+ * CBR1 BRSDEC LL_DMA_ConfigBlkRptAddrUpdate\n
+ * CBR1 DDEC LL_DMA_ConfigBlkRptAddrUpdate\n
+ * CBR1 SDEC LL_DMA_ConfigBlkRptAddrUpdate
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param Configuration This parameter must be a combination of all the following values:
+ * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_INCREMENT or @ref LL_DMA_BLKRPT_DEST_ADDR_DECREMENT
+ * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_INCREMENT or @ref LL_DMA_BLKRPT_SRC_ADDR_DECREMENT
+ * @arg @ref LL_DMA_BURST_DEST_ADDR_INCREMENT or @ref LL_DMA_BURST_DEST_ADDR_DECREMENT
+ * @arg @ref LL_DMA_BURST_SRC_ADDR_INCREMENT or @ref LL_DMA_BURST_SRC_ADDR_DECREMENT
+ *@retval None.
+ */
+__STATIC_INLINE void LL_DMA_ConfigBlkRptAddrUpdate(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1,
+ DMA_CBR1_BRDDEC | DMA_CBR1_BRSDEC | DMA_CBR1_DDEC | DMA_CBR1_SDEC, Configuration);
+}
+
+/**
+ * @brief Configure DMA Block number of data and repeat Count.
+ * @note This API is used only for 2D addressing channels.
+ * @rmtoll CBR1 BNDT LL_DMA_ConfigBlkCounters\n
+ * CBR1 BRC LL_DMA_ConfigBlkCounters
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param BlkDataLength Between 0 to 0x0000FFFF
+ * @param BlkRptCount Between 0 to 0x00000EFF
+ *@retval None.
+ */
+__STATIC_INLINE void LL_DMA_ConfigBlkCounters(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkDataLength,
+ uint32_t BlkRptCount)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1,
+ (DMA_CBR1_BNDT | DMA_CBR1_BRC), (BlkDataLength | (BlkRptCount << DMA_CBR1_BRC_Pos)));
+}
+
+/**
+ * @brief Set block repeat destination address update.
+ * @note This API is used only for 2D addressing channels.
+ * @rmtoll CBR1 BRDDEC LL_DMA_SetBlkRptDestAddrUpdate
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param BlkRptDestAddrUpdate This parameter can be one of the following values:
+ * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_INCREMENT
+ * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_DECREMENT
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_SetBlkRptDestAddrUpdate(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkRptDestAddrUpdate)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRDDEC,
+ BlkRptDestAddrUpdate);
+}
+
+/**
+ * @brief Get block repeat destination address update.
+ * @note This API is used only for 2D addressing channels.
+ * @rmtoll CBR1 BRDDEC LL_DMA_GetBlkRptDestAddrUpdate
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_INCREMENT
+ * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_DECREMENT
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetBlkRptDestAddrUpdate(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRDDEC));
+}
+
+/**
+ * @brief Set block repeat source address update.
+ * @note This API is used only for 2D addressing channels.
+ * @rmtoll CBR1 BRSDEC LL_DMA_SetBlkRptSrcAddrUpdate
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param BlkRptSrcAddrUpdate This parameter can be one of the following values:
+ * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_INCREMENT
+ * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_DECREMENT
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_SetBlkRptSrcAddrUpdate(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkRptSrcAddrUpdate)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRSDEC,
+ BlkRptSrcAddrUpdate);
+}
+
+/**
+ * @brief Get block repeat source address update.
+ * @note This API is used only for 2D addressing channels.
+ * @rmtoll CBR1 BRSDEC LL_DMA_GetBlkRptSrcAddrUpdate
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_INCREMENT
+ * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_DECREMENT
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetBlkRptSrcAddrUpdate(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRSDEC));
+}
+
+/**
+ * @brief Set destination address update.
+ * @note This API is used only for 2D addressing channels.
+ * @rmtoll CBR1 DDEC LL_DMA_SetDestAddrUpdate
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param DestAddrUpdate This parameter can be one of the following values:
+ * @arg @ref LL_DMA_BURST_DEST_ADDR_INCREMENT
+ * @arg @ref LL_DMA_BURST_DEST_ADDR_DECREMENT
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_SetDestAddrUpdate(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddrUpdate)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_DDEC,
+ DestAddrUpdate);
+}
+
+/**
+ * @brief Get destination address update.
+ * @note This API is used only for 2D addressing channels.
+ * @rmtoll CBR1 DDEC LL_DMA_GetDestAddrUpdate
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_BURST_DEST_ADDR_INCREMENT
+ * @arg @ref LL_DMA_BURST_DEST_ADDR_DECREMENT
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetDestAddrUpdate(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_DDEC));
+}
+
+/**
+ * @brief Set source address update.
+ * @note This API is used only for 2D addressing channels.
+ * @rmtoll CBR1 SDEC LL_DMA_SetSrcAddrUpdate
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param SrcAddrUpdate This parameter can be one of the following values:
+ * @arg @ref LL_DMA_BURST_SRC_ADDR_INCREMENT
+ * @arg @ref LL_DMA_BURST_SRC_ADDR_DECREMENT
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_SetSrcAddrUpdate(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrUpdate)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_SDEC,
+ SrcAddrUpdate);
+}
+
+/**
+ * @brief Get source address update.
+ * @note This API is used only for 2D addressing channels.
+ * @rmtoll CBR1 SDEC LL_DMA_GetSrcAddrUpdate
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_BURST_SRC_ADDR_INCREMENT
+ * @arg @ref LL_DMA_BURST_SRC_ADDR_DECREMENT
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetSrcAddrUpdate(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_SDEC));
+}
+
+/**
+ * @brief Set block repeat count.
+ * @note This API is used only for 2D addressing channels.
+ * @rmtoll CBR1 BRC LL_DMA_SetBlkRptCount
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param BlkRptCount Between 0 to 0x00000EFF
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_SetBlkRptCount(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkRptCount)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRC,
+ (BlkRptCount << DMA_CBR1_BRC_Pos) & DMA_CBR1_BRC);
+}
+
+/**
+ * @brief Get block repeat count.
+ * @note This API is used only for 2D addressing channels.
+ * @rmtoll CBR1 BRC LL_DMA_GetBlkRptCount
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval Between 0 to 0x00000EFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetBlkRptCount(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1,
+ DMA_CBR1_BRC) >> DMA_CBR1_BRC_Pos);
+}
+
+/**
+ * @brief Set block data length in bytes to transfer.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CBR1 BNDT LL_DMA_SetBlkDataLength
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param BlkDataLength Between 0 to 0x0000FFFF
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_SetBlkDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkDataLength)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BNDT,
+ BlkDataLength);
+}
+
+/**
+ * @brief Get block data length in bytes to transfer.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CBR1 BNDT LL_DMA_GetBlkDataLength
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval Between 0 to 0x0000FFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetBlkDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BNDT));
+}
+
+/**
+ * @brief Configure the source and destination addresses.
+ * @note This API is used for all available DMA channels.
+ * @note This API must not be called when the DMA Channel is enabled.
+ * @rmtoll CSAR SA LL_DMA_ConfigAddresses\n
+ * CDAR DA LL_DMA_ConfigAddresses
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param SrcAddress Between 0 to 0xFFFFFFFF
+ * @param DestAddress Between 0 to 0xFFFFFFFF
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t
+ DestAddress)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress);
+ WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR, DestAddress);
+}
+
+/**
+ * @brief Set source address.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CSAR SA LL_DMA_SetSrcAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param SrcAddress Between 0 to 0xFFFFFFFF
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_SetSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress);
+}
+
+/**
+ * @brief Get source address.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CSAR SA LL_DMA_GetSrcAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval Between 0 to 0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR));
+}
+
+/**
+ * @brief Set destination address.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CDAR DA LL_DMA_SetDestAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param DestAddress Between 0 to 0xFFFFFFFF
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_SetDestAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddress)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR, DestAddress);
+}
+
+/**
+ * @brief Get destination address.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CDAR DA LL_DMA_GetDestAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval Between 0 to 0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetDestAddress(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR));
+}
+
+/**
+ * @brief Configure source and destination addresses offset.
+ * @note This API is used only for 2D addressing channels.
+ * @note This API must not be called when the DMA Channel is enabled.
+ * @rmtoll CTR3 DAO LL_DMA_ConfigAddrUpdateValue\n
+ * CTR3 SAO LL_DMA_ConfigAddrUpdateValue
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param DestAddrOffset Between 0 to 0x00001FFF
+ * @param SrcAddrOffset Between 0 to 0x00001FFF
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_ConfigAddrUpdateValue(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrOffset,
+ uint32_t DestAddrOffset)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3,
+ (SrcAddrOffset & DMA_CTR3_SAO) | ((DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO));
+}
+
+/**
+ * @brief Set destination address offset.
+ * @note This API is used only for 2D addressing channels.
+ * @rmtoll CTR3 DAO LL_DMA_SetDestAddrUpdateValue
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param DestAddrOffset Between 0 to 0x00001FFF
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_SetDestAddrUpdateValue(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddrOffset)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_DAO,
+ ((DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO));
+}
+
+/**
+ * @brief Get destination address offset.
+ * @note This API is used only for 2D addressing channels.
+ * @rmtoll CDAR DAO LL_DMA_GetDestAddrUpdateValue
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval Between 0 to 0x00001FFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetDestAddrUpdateValue(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3,
+ DMA_CTR3_DAO) >> DMA_CTR3_DAO_Pos);
+}
+
+/**
+ * @brief Set source address offset.
+ * @note This API is used only for 2D addressing channels.
+ * @rmtoll CTR3 SAO LL_DMA_SetSrcAddrUpdateValue
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param SrcAddrOffset Between 0 to 0x00001FFF
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_SetSrcAddrUpdateValue(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrOffset)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_SAO,
+ SrcAddrOffset & DMA_CTR3_SAO);
+}
+
+/**
+ * @brief Get source address offset.
+ * @note This API is used only for 2D addressing channels.
+ * @rmtoll CTR3 SAO LL_DMA_GetSrcAddressUpdateValue
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval Between 0 to 0x00001FFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetSrcAddrUpdateValue(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_SAO));
+}
+
+/**
+ * @brief Configure the block repeated source and destination addresses offset.
+ * @note This API is used only for 2D addressing channels.
+ * @note This API must not be called when the DMA Channel is enabled.
+ * @rmtoll CBR2 BRDAO LL_DMA_ConfigBlkRptAddrUpdateValue\n
+ * CBR2 BRSAO LL_DMA_ConfigBlkRptAddrUpdateValue
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param BlkRptDestAddrOffset Between 0 to 0x0000FFFF
+ * @param BlkRptSrcAddrOffset Between 0 to 0x0000FFFF
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_ConfigBlkRptAddrUpdateValue(DMA_TypeDef *DMAx, uint32_t Channel,
+ uint32_t BlkRptSrcAddrOffset, uint32_t BlkRptDestAddrOffset)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2,
+ ((BlkRptDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO) | (BlkRptSrcAddrOffset & DMA_CBR2_BRSAO));
+}
+
+/**
+ * @brief Set block repeated destination address offset.
+ * @note This API is used only for 2D addressing channels.
+ * @rmtoll CBR2 BRDAO LL_DMA_SetBlkRptDestAddrUpdateValue
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param BlkRptDestAddrOffset Between 0 to 0x0000FFFF
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_SetBlkRptDestAddrUpdateValue(DMA_TypeDef *DMAx, uint32_t Channel,
+ uint32_t BlkRptDestAddrOffset)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRDAO,
+ ((BlkRptDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO));
+}
+
+/**
+ * @brief Get block repeated destination address offset.
+ * @note This API is used only for 2D addressing channels.
+ * @rmtoll CBR2 BRDAO LL_DMA_GetBlkRptDestAddrUpdateValue
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval Between 0 to 0x0000FFFF.
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetBlkRptDestAddrUpdateValue(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2,
+ DMA_CBR2_BRDAO) >> DMA_CBR2_BRDAO_Pos);
+}
+
+/**
+ * @brief Set block repeated source address offset.
+ * @note This API is used only for 2D addressing channels.
+ * @rmtoll CBR2 BRSAO LL_DMA_SetBlkRptSrcAddrUpdateValue
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param BlkRptSrcAddrOffset Between 0 to 0x0000FFFF
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_SetBlkRptSrcAddrUpdateValue(DMA_TypeDef *DMAx, uint32_t Channel,
+ uint32_t BlkRptSrcAddrOffset)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRSAO,
+ BlkRptSrcAddrOffset);
+}
+
+/**
+ * @brief Get block repeated source address offset.
+ * @note This API is used only for 2D addressing channels.
+ * @rmtoll CBR2 BRSAO LL_DMA_GetBlkRptSrcAddrUpdateValue
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval Between 0 to 0x0000FFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetBlkRptSrcAddrUpdateValue(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRSAO));
+}
+
+/**
+ * @brief Configure registers update and node address offset during the link transfer.
+ * @note This API is used for all available DMA channels.
+ * For linear addressing channels, UT3 and UB2 fields are discarded.
+ * @rmtoll CLLR UT1 LL_DMA_ConfigRegistersUpdate\n
+ * @rmtoll CLLR UT2 LL_DMA_ConfigRegistersUpdate\n
+ * @rmtoll CLLR UB1 LL_DMA_ConfigRegistersUpdate\n
+ * @rmtoll CLLR USA LL_DMA_ConfigRegistersUpdate\n
+ * @rmtoll CLLR UDA LL_DMA_ConfigRegistersUpdate\n
+ * @rmtoll CLLR UT3 LL_DMA_ConfigRegistersUpdate\n
+ * @rmtoll CLLR UB2 LL_DMA_ConfigRegistersUpdate\n
+ * @rmtoll CLLR ULL LL_DMA_ConfigRegistersUpdate
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param RegistersUpdate This parameter must be a combination of all the following values:
+ * @arg @ref LL_DMA_UPDATE_CTR1
+ * @arg @ref LL_DMA_UPDATE_CTR2
+ * @arg @ref LL_DMA_UPDATE_CBR1
+ * @arg @ref LL_DMA_UPDATE_CSAR
+ * @arg @ref LL_DMA_UPDATE_CDAR
+ * @arg @ref LL_DMA_UPDATE_CTR3 (This value is allowed only for 2D addressing channels)
+ * @arg @ref LL_DMA_UPDATE_CBR2 (This value is allowed only for 2D addressing channels)
+ * @arg @ref LL_DMA_UPDATE_CLLR
+ * @param LinkedListAddrOffset Between 0 to 0x0000FFFC
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_ConfigLinkUpdate(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t RegistersUpdate,
+ uint32_t LinkedListAddrOffset)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR,
+ (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | \
+ DMA_CLLR_UB2 | DMA_CLLR_ULL | DMA_CLLR_LA), (RegistersUpdate | (LinkedListAddrOffset & DMA_CLLR_LA)));
+}
+
+/**
+ * @brief Enable CTR1 update during the link transfer.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CLLR UT1 LL_DMA_EnableCTR1Update
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_EnableCTR1Update(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1);
+}
+
+/**
+ * @brief Disable CTR1 update during the link transfer.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CLLR UT1 LL_DMA_DisableCTR1Update
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_DisableCTR1Update(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1);
+}
+
+/**
+ * @brief Check if CTR1 update during the link transfer is enabled.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CLLR UT1 LL_DMA_IsEnabledCTR1Update
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR1Update(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1)
+ == (DMA_CLLR_UT1)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable CTR2 update during the link transfer.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CLLR UT2 LL_DMA_EnableCTR2Update
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_EnableCTR2Update(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2);
+}
+
+/**
+ * @brief Disable CTR2 update during the link transfer.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CLLR UT2 LL_DMA_DisableCTR2Update
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_DisableCTR2Update(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2);
+}
+
+/**
+ * @brief Check if CTR2 update during the link transfer is enabled.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CLLR UT2 LL_DMA_IsEnabledCTR2Update
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR2Update(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2)
+ == (DMA_CLLR_UT2)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable CBR1 update during the link transfer.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CLLR UB1 LL_DMA_EnableCBR1Update
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_EnableCBR1Update(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1);
+}
+
+/**
+ * @brief Disable CBR1 update during the link transfer.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CLLR UB1 LL_DMA_DisableCBR1Update
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_DisableCBR1Update(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1);
+}
+
+/**
+ * @brief Check if CBR1 update during the link transfer is enabled.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CLLR UB1 LL_DMA_IsEnabledCBR1Update
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledCBR1Update(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1)
+ == (DMA_CLLR_UB1)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable CSAR update during the link transfer.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CLLR USA LL_DMA_EnableCSARUpdate
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_EnableCSARUpdate(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA);
+}
+
+/**
+ * @brief Disable CSAR update during the link transfer.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CLLR USA LL_DMA_DisableCSARUpdate
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_DisableCSARUpdate(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA);
+}
+
+/**
+ * @brief Check if CSAR update during the link transfer is enabled.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CLLR USA LL_DMA_IsEnabledCSARUpdate
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledCSARUpdate(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA)
+ == (DMA_CLLR_USA)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable CDAR update during the link transfer.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CLLR UDA LL_DMA_EnableCDARUpdate
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_EnableCDARUpdate(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA);
+}
+
+/**
+ * @brief Disable CDAR update during the link transfer.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CLLR UDA LL_DMA_DisableCDARUpdate
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_DisableCDARUpdate(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA);
+}
+
+/**
+ * @brief Check if CDAR update during the link transfer is enabled.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CLLR UDA LL_DMA_IsEnabledCDARUpdate
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledCDARUpdate(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA)
+ == (DMA_CLLR_UDA)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable CTR3 update during the link transfer.
+ * @note This API is used only for 2D addressing channels.
+ * @rmtoll CLLR UT3 LL_DMA_EnableCTR3Update
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_EnableCTR3Update(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3);
+}
+
+/**
+ * @brief Disable CTR3 update during the link transfer.
+ * @note This API is used only for 2D addressing channels.
+ * @rmtoll CLLR UT3 LL_DMA_DisableCTR3Update
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_DisableCTR3Update(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3);
+}
+
+/**
+ * @brief Check if CTR3 update during the link transfer is enabled.
+ * @note This API is used only for 2D addressing channels.
+ * @rmtoll CLLR UT3 LL_DMA_IsEnabledCTR3Update
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR3Update(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3)
+ == (DMA_CLLR_UT3)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable CBR2 update during the link transfer.
+ * @note This API is used only for 2D addressing channels.
+ * @rmtoll CLLR UB2 LL_DMA_EnableCBR2Update
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_EnableCBR2Update(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2);
+}
+
+/**
+ * @brief Disable CBR2 update during the link transfer.
+ * @note This API is used only for 2D addressing channels.
+ * @rmtoll CLLR UB2 LL_DMA_DisableCBR2Update
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_DisableCBR2Update(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2);
+}
+
+/**
+ * @brief Check if CBR2 update during the link transfer is enabled.
+ * @note This API is used only for 2D addressing channels.
+ * @rmtoll CLLR UB2 LL_DMA_IsEnabledCBR2Update
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledCBR2Update(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2)
+ == (DMA_CLLR_UB2)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable CLLR update during the link transfer.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CLLR ULL LL_DMA_EnableCLLRUpdate
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_EnableCLLRUpdate(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL);
+}
+
+/**
+ * @brief Disable CLLR update during the link transfer.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CLLR ULL LL_DMA_DisableCLLRUpdate
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_DisableCLLRUpdate(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL);
+}
+
+/**
+ * @brief Check if CLLR update during the link transfer is enabled.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CLLR ULL LL_DMA_IsEnabledCLLRUpdate
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledCLLRUpdate(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL)
+ == (DMA_CLLR_ULL)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set linked list address offset.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CLLR LA LL_DMA_SetLinkedListAddrOffset
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param LinkedListAddrOffset Between 0 to 0x0000FFFC
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_SetLinkedListAddrOffset(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t LinkedListAddrOffset)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_LA,
+ (LinkedListAddrOffset & DMA_CLLR_LA));
+}
+
+/**
+ * @brief Get linked list address offset.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CLLR LA LL_DMA_GetLinkedListAddrOffset
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval Between 0 to 0x0000FFFC.
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetLinkedListAddrOffset(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR,
+ DMA_CLLR_LA) >> DMA_CLLR_LA_Pos);
+}
+
+/**
+ * @brief Get FIFO level.
+ * @note This API is not used for LPDMA channels.
+ * @rmtoll CSR FIFOL LL_DMA_GetFIFOLevel
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval Between 0 to 0x000000FF.
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetFIFOLevel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR,
+ DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos);
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ * @brief Enable the DMA channel secure attribute.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll SECCFGR SECx LL_DMA_EnableChannelSecure
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_EnableChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ SET_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU)));
+}
+
+/**
+ * @brief Disable the DMA channel secure attribute.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll SECCFGR SECx LL_DMA_DisableChannelSecure
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_DisableChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ CLEAR_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU)));
+}
+
+/**
+ * @brief Check if DMA channel secure is enabled.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll SECCFGR SECx LL_DMA_IsEnabledChannelSecure
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return ((READ_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU)))
+ == (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/**
+ * @brief Enable the DMA channel privilege attribute.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll PRIVCFGR PRIVx LL_DMA_EnableChannelPrivilege
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_EnableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ SET_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU)));
+}
+
+/**
+ * @brief Disable the DMA channel privilege attribute.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll PRIVCFGR PRIVx LL_DMA_DisableChannelPrivilege
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_DisableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ CLEAR_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU)));
+}
+
+/**
+ * @brief Check if DMA Channel privilege is enabled.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll PRIVCFGR PRIVx LL_DMA_IsEnabledChannelPrivileged
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return ((READ_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU)))
+ == (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ * @brief Enable the DMA channel lock attributes.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll RCFGLOCKR LOCKx LL_DMA_EnableChannelLockAttribute
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_EnableChannelLockAttribute(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ SET_BIT(DMAx->RCFGLOCKR, (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU)));
+}
+
+/**
+ * @brief Check if DMA channel attributes are locked.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll SECCFGR LOCKx LL_DMA_IsEnabledChannelLockAttribute
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelLockAttribute(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return ((READ_BIT(DMAx->RCFGLOCKR, (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU)))
+ == (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EF_FLAG_Management Flag Management
+ * @{
+ */
+
+/**
+ * @brief Clear trigger overrun flag.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CFCR TOF LL_DMA_ClearFlag_TO
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TO(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_TOF);
+}
+
+/**
+ * @brief Clear suspension flag.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CFCR SUSPF LL_DMA_ClearFlag_SUSP
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_SUSP(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_SUSPF);
+}
+
+/**
+ * @brief Clear user setting error flag.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CFCR USEF LL_DMA_ClearFlag_USE
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_USE(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_USEF);
+}
+
+/**
+ * @brief Clear link transfer error flag.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CFCR ULEF LL_DMA_ClearFlag_ULE
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_ULE(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_ULEF);
+}
+
+/**
+ * @brief Clear data transfer error flag.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CFCR DTEF LL_DMA_ClearFlag_DTE
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_DTE(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_DTEF);
+}
+
+/**
+ * @brief Clear half transfer flag.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CFCR HTF LL_DMA_ClearFlag_HT
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_HTF);
+}
+
+/**
+ * @brief Clear transfer complete flag.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CFCR TCF LL_DMA_ClearFlag_TC
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_TCF);
+}
+
+/**
+ * @brief Get trigger overrun flag.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CSR TOF LL_DMA_IsActiveFlag_TO
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TO(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_TOF)
+ == (DMA_CSR_TOF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get suspension flag.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CSR SUSPF LL_DMA_IsActiveFlag_SUSP
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_SUSP(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_SUSPF)
+ == (DMA_CSR_SUSPF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get user setting error flag.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CSR USEF LL_DMA_IsActiveFlag_USE
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_USE(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_USEF)
+ == (DMA_CSR_USEF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get user setting error flag.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CSR ULEF LL_DMA_IsActiveFlag_ULE
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_ULE(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_ULEF)
+ == (DMA_CSR_ULEF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get data transfer error flag.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CSR DTEF LL_DMA_IsActiveFlag_DTE
+ * @param DMAx DMAx Instance
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DTE(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_DTEF)
+ == (DMA_CSR_DTEF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get half transfer flag.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CSR HTF LL_DMA_IsActiveFlag_HT
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_HTF)
+ == (DMA_CSR_HTF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get transfer complete flag.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CSR TCF LL_DMA_IsActiveFlag_TC
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_TCF)
+ == (DMA_CSR_TCF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get idle flag.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CSR IDLEF LL_DMA_IsActiveFlag_IDLE
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_IDLE(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_IDLEF)
+ == (DMA_CSR_IDLEF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if nsecure masked interrupt is active.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll MISR MISx LL_DMA_IsEnableIT_MIS
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_MIS(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return ((READ_BIT(DMAx->MISR, (DMA_MISR_MIS0 << (Channel & 0x0FU)))
+ == (DMA_MISR_MIS0 << (Channel & 0x0FU))) ? 1UL : 0UL);
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ * @brief Check if secure masked interrupt is active.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll SMISR MISx LL_DMA_IsEnableIT_SMIS
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_SMIS(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return ((READ_BIT(DMAx->SMISR, (DMA_SMISR_MIS0 << (Channel & 0x0000000FU)))
+ == (DMA_SMISR_MIS0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EF_IT_Management Interrupt Management
+ * @{
+ */
+
+/**
+ * @brief Enable trigger overrun interrupt.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CCR TOIE LL_DMA_EnableIT_TO
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_EnableIT_TO(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE);
+}
+
+/**
+ * @brief Enable suspension interrupt.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CCR SUSPIE LL_DMA_EnableIT_SUSP
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_EnableIT_SUSP(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE);
+}
+
+/**
+ * @brief Enable user setting error interrupt.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CCR USEIE LL_DMA_EnableIT_USE
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_EnableIT_USE(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE);
+}
+
+/**
+ * @brief Enable update link transfer error interrupt.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CCR ULEIE LL_DMA_EnableIT_ULE
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_EnableIT_ULE(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE);
+}
+
+/**
+ * @brief Enable data transfer error interrupt.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CCR DTEIE LL_DMA_EnableIT_DTE
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_EnableIT_DTE(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE);
+}
+
+/**
+ * @brief Enable half transfer complete interrupt.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE);
+}
+
+/**
+ * @brief Enable transfer complete interrupt.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
+}
+
+/**
+ * @brief Disable trigger overrun interrupt.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CCR TOIE LL_DMA_DisableIT_TO
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_DisableIT_TO(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE);
+}
+
+/**
+ * @brief Disable suspension interrupt.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CCR SUSPIE LL_DMA_DisableIT_SUSP
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_DisableIT_SUSP(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE);
+}
+
+/**
+ * @brief Disable user setting error interrupt.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CCR USEIE LL_DMA_DisableIT_USE
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_DisableIT_USE(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE);
+}
+
+/**
+ * @brief Disable update link transfer error interrupt.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CCR ULEIE LL_DMA_DisableIT_ULE
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_DisableIT_ULE(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE);
+}
+
+/**
+ * @brief Disable data transfer error interrupt.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CCR DTEIE LL_DMA_DisableIT_DTE
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_DisableIT_DTE(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE);
+}
+
+/**
+ * @brief Disable half transfer complete interrupt.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE);
+}
+
+/**
+ * @brief Disable transfer complete interrupt.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
+}
+
+/**
+ * @brief Check if trigger overrun interrupt is enabled.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CCR TOIE LL_DMA_IsEnabledIT_TO
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TO(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE)
+ == DMA_CCR_TOIE) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if suspension interrupt is enabled.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CCR SUSPIE LL_DMA_IsEnabledIT_SUSP
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_SUSP(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE)
+ == DMA_CCR_SUSPIE) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if user setting error interrupt is enabled.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CCR USEIE LL_DMA_IsEnabledIT_USE
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_USE(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE)
+ == DMA_CCR_USEIE) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if update link transfer error interrupt is enabled.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CCR ULEIE LL_DMA_IsEnabledIT_ULE
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_ULE(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE)
+ == DMA_CCR_ULEIE) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if data transfer error interrupt is enabled.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CCR DTEIE LL_DMA_IsEnabledIT_DTE
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DTE(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE)
+ == DMA_CCR_DTEIE) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if half transfer complete interrupt is enabled.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE)
+ == DMA_CCR_HTIE) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if transfer complete interrupt is enabled.
+ * @note This API is used for all available DMA channels.
+ * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE)
+ == DMA_CCR_TCIE) ? 1UL : 0UL);
+}
+/**
+ * @}
+ */
+
+#if defined (USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
+uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
+
+void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
+void LL_DMA_ListStructInit(LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct);
+void LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct);
+
+uint32_t LL_DMA_List_Init(DMA_TypeDef *DMAx, uint32_t Channel,
+ LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct);
+uint32_t LL_DMA_List_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
+
+uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DMA_LinkNodeTypeDef *pNode);
+void LL_DMA_ConnectLinkNode(LL_DMA_LinkNodeTypeDef *pPrevLinkNode, uint32_t PrevNodeCLLRIdx,
+ LL_DMA_LinkNodeTypeDef *pNewLinkNode, uint32_t NewNodeCLLRIdx);
+void LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32_t LinkNodeCLLRIdx);
+/**
+ * @}
+ */
+#endif /* defined (USE_FULL_LL_DRIVER) */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* (defined (GPDMA1) || defined (LPDMA1)) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* STM32U5xx_LL_DMA_H */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dma2d.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dma2d.h
new file mode 100644
index 00000000..abf5aad2
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dma2d.h
@@ -0,0 +1,2188 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_dma2d.h
+ * @author MCD Application Team
+ * @brief Header file of DMA2D LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_LL_DMA2D_H
+#define STM32U5xx_LL_DMA2D_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx.h"
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined (DMA2D)
+
+/** @defgroup DMA2D_LL DMA2D
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA2D_LL_Private_Macros DMA2D Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA2D_LL_ES_Init_Struct DMA2D Exported Init structures
+ * @{
+ */
+
+/**
+ * @brief LL DMA2D Init Structure Definition
+ */
+typedef struct
+{
+ uint32_t Mode; /*!< Specifies the DMA2D transfer mode.
+ - This parameter can be one value of @ref DMA2D_LL_EC_MODE.
+
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetMode(). */
+
+ uint32_t ColorMode; /*!< Specifies the color format of the output image.
+ - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
+
+ This parameter can be modified afterwards using,
+ unitary function @ref LL_DMA2D_SetOutputColorMode(). */
+
+ uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ function @ref LL_DMA2D_ConfigOutputColor(). */
+
+ uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+ This parameter can be modified afterwards
+ using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ function @ref LL_DMA2D_ConfigOutputColor(). */
+
+ uint32_t OutputRed; /*!< Specifies the Red value of the output image.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+ This parameter can be modified afterwards
+ using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ function @ref LL_DMA2D_ConfigOutputColor(). */
+
+ uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+ - This parameter is not considered if RGB888 or RGB565 color mode is selected.
+
+ This parameter can be modified afterwards using,
+ unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ function @ref LL_DMA2D_ConfigOutputColor(). */
+
+ uint32_t OutputMemoryAddress; /*!< Specifies the memory address.
+ - This parameter must be a number between:
+ Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
+
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */
+
+ uint32_t OutputSwapMode; /*!< Specifies the output swap mode color format of the output image.
+ - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_SWAP_MODE.
+
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetOutputSwapMode(). */
+
+ uint32_t LineOffsetMode; /*!< Specifies the output line offset mode.
+ - This parameter can be one value of @ref DMA2D_LL_EC_LINE_OFFSET_MODE.
+
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetLineOffsetMode(). */
+
+ uint32_t LineOffset; /*!< Specifies the output line offset value.
+ - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
+
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetLineOffset(). */
+
+ uint32_t NbrOfLines; /*!< Specifies the number of lines of the area to be transferred.
+ - This parameter must be a number between:
+ Min_Data = 0x0000 and Max_Data = 0xFFFF.
+
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetNbrOfLines(). */
+
+ uint32_t NbrOfPixelsPerLines; /*!< Specifies the number of pixels per lines of the area to be transferred.
+ - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
+
+ This parameter can be modified afterwards using,
+ unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */
+
+ uint32_t AlphaInversionMode; /*!< Specifies the output alpha inversion mode.
+ - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION.
+
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetOutputAlphaInvMode(). */
+
+ uint32_t RBSwapMode; /*!< Specifies the output Red Blue swap mode.
+ - This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP.
+
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetOutputRBSwapMode(). */
+
+} LL_DMA2D_InitTypeDef;
+
+/**
+ * @brief LL DMA2D Layer Configuration Structure Definition
+ */
+typedef struct
+{
+ uint32_t MemoryAddress; /*!< Specifies the foreground or background memory address.
+ - This parameter must be a number between:
+ Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
+
+ This parameter can be modified afterwards using unitary functions
+ - @ref LL_DMA2D_FGND_SetMemAddr() for foreground layer,
+ - @ref LL_DMA2D_BGND_SetMemAddr() for background layer. */
+
+ uint32_t LineOffset; /*!< Specifies the foreground or background line offset value.
+ - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
+
+ This parameter can be modified afterwards using unitary functions
+ - @ref LL_DMA2D_FGND_SetLineOffset() for foreground layer,
+ - @ref LL_DMA2D_BGND_SetLineOffset() for background layer. */
+
+ uint32_t ColorMode; /*!< Specifies the foreground or background color mode.
+ - This parameter can be one value of @ref DMA2D_LL_EC_INPUT_COLOR_MODE.
+
+ This parameter can be modified afterwards using unitary functions
+ - @ref LL_DMA2D_FGND_SetColorMode() for foreground layer,
+ - @ref LL_DMA2D_BGND_SetColorMode() for background layer. */
+
+ uint32_t CLUTColorMode; /*!< Specifies the foreground or background CLUT color mode.
+ - This parameter can be one value of @ref DMA2D_LL_EC_CLUT_COLOR_MODE.
+
+ This parameter can be modified afterwards using unitary functions
+ - @ref LL_DMA2D_FGND_SetCLUTColorMode() for foreground layer,
+ - @ref LL_DMA2D_BGND_SetCLUTColorMode() for background layer. */
+
+ uint32_t CLUTSize; /*!< Specifies the foreground or background CLUT size.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+ This parameter can be modified afterwards using unitary functions
+ - @ref LL_DMA2D_FGND_SetCLUTSize() for foreground layer,
+ - @ref LL_DMA2D_BGND_SetCLUTSize() for background layer. */
+
+ uint32_t AlphaMode; /*!< Specifies the foreground or background alpha mode.
+ - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_MODE.
+
+ This parameter can be modified afterwards using unitary functions
+ - @ref LL_DMA2D_FGND_SetAlphaMode() for foreground layer,
+ - @ref LL_DMA2D_BGND_SetAlphaMode() for background layer. */
+
+ uint32_t Alpha; /*!< Specifies the foreground or background Alpha value.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+ This parameter can be modified afterwards using unitary functions
+ - @ref LL_DMA2D_FGND_SetAlpha() for foreground layer,
+ - @ref LL_DMA2D_BGND_SetAlpha() for background layer. */
+
+ uint32_t Blue; /*!< Specifies the foreground or background Blue color value.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+ This parameter can be modified afterwards using unitary functions
+ - @ref LL_DMA2D_FGND_SetBlueColor() for foreground layer,
+ - @ref LL_DMA2D_BGND_SetBlueColor() for background layer. */
+
+ uint32_t Green; /*!< Specifies the foreground or background Green color value.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+ This parameter can be modified afterwards using unitary functions
+ - @ref LL_DMA2D_FGND_SetGreenColor() for foreground layer,
+ - @ref LL_DMA2D_BGND_SetGreenColor() for background layer. */
+
+ uint32_t Red; /*!< Specifies the foreground or background Red color value.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+ This parameter can be modified afterwards using unitary functions
+ - @ref LL_DMA2D_FGND_SetRedColor() for foreground layer,
+ - @ref LL_DMA2D_BGND_SetRedColor() for background layer. */
+
+ uint32_t CLUTMemoryAddress; /*!< Specifies the foreground or background CLUT memory address.
+ - This parameter must be a number between:
+ Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
+
+ This parameter can be modified afterwards using unitary functions
+ - @ref LL_DMA2D_FGND_SetCLUTMemAddr() for foreground layer,
+ - @ref LL_DMA2D_BGND_SetCLUTMemAddr() for background layer. */
+
+ uint32_t AlphaInversionMode; /*!< Specifies the foreground or background alpha inversion mode.
+ - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION.
+
+ This parameter can be modified afterwards using unitary functions
+ - @ref LL_DMA2D_FGND_SetAlphaInvMode() for foreground layer,
+ - @ref LL_DMA2D_BGND_SetAlphaInvMode() for background layer. */
+
+ uint32_t RBSwapMode; /*!< Specifies the foreground or background Red Blue swap mode.
+ This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP .
+
+ This parameter can be modified afterwards using unitary functions
+ - @ref LL_DMA2D_FGND_SetRBSwapMode() for foreground layer,
+ - @ref LL_DMA2D_BGND_SetRBSwapMode() for background layer. */
+
+
+} LL_DMA2D_LayerCfgTypeDef;
+
+/**
+ * @brief LL DMA2D Output Color Structure Definition
+ */
+typedef struct
+{
+ uint32_t ColorMode; /*!< Specifies the color format of the output image.
+ - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
+
+ This parameter can be modified afterwards using
+ unitary function @ref LL_DMA2D_SetOutputColorMode(). */
+
+ uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+ This parameter can be modified afterwards using,
+ unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ function @ref LL_DMA2D_ConfigOutputColor(). */
+
+ uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between
+ Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ function @ref LL_DMA2D_ConfigOutputColor(). */
+
+ uint32_t OutputRed; /*!< Specifies the Red value of the output image.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ function @ref LL_DMA2D_ConfigOutputColor(). */
+
+ uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+ - This parameter is not considered if RGB888 or RGB565 color mode is selected.
+
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ function @ref LL_DMA2D_ConfigOutputColor(). */
+
+} LL_DMA2D_ColorTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMA2D_LL_Exported_Constants DMA2D Exported Constants
+ * @{
+ */
+
+/** @defgroup DMA2D_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_DMA2D_ReadReg function
+ * @{
+ */
+#define LL_DMA2D_FLAG_CEIF DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */
+#define LL_DMA2D_FLAG_CTCIF DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */
+#define LL_DMA2D_FLAG_CAEIF DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */
+#define LL_DMA2D_FLAG_TWIF DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */
+#define LL_DMA2D_FLAG_TCIF DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */
+#define LL_DMA2D_FLAG_TEIF DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_DMA2D_ReadReg and LL_DMA2D_WriteReg functions
+ * @{
+ */
+#define LL_DMA2D_IT_CEIE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */
+#define LL_DMA2D_IT_CTCIE DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */
+#define LL_DMA2D_IT_CAEIE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */
+#define LL_DMA2D_IT_TWIE DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */
+#define LL_DMA2D_IT_TCIE DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */
+#define LL_DMA2D_IT_TEIE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_LL_EC_MODE Mode
+ * @{
+ */
+#define LL_DMA2D_MODE_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */
+#define LL_DMA2D_MODE_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */
+#define LL_DMA2D_MODE_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */
+#define LL_DMA2D_MODE_R2M (DMA2D_CR_MODE_0|DMA2D_CR_MODE_1) /*!< DMA2D register to memory transfer mode */
+#define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG DMA2D_CR_MODE_2 /*!< DMA2D memory to memory with blending transfer mode and fixed color foreground */
+#define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG (DMA2D_CR_MODE_0|DMA2D_CR_MODE_2) /*!< DMA2D memory to memory with blending transfer mode and fixed color background */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_LL_EC_OUTPUT_COLOR_MODE Output Color Mode
+ * @{
+ */
+#define LL_DMA2D_OUTPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
+#define LL_DMA2D_OUTPUT_MODE_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 */
+#define LL_DMA2D_OUTPUT_MODE_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 */
+#define LL_DMA2D_OUTPUT_MODE_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 */
+#define LL_DMA2D_OUTPUT_MODE_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_LL_EC_INPUT_COLOR_MODE Input Color Mode
+ * @{
+ */
+#define LL_DMA2D_INPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
+#define LL_DMA2D_INPUT_MODE_RGB888 DMA2D_FGPFCCR_CM_0 /*!< RGB888 */
+#define LL_DMA2D_INPUT_MODE_RGB565 DMA2D_FGPFCCR_CM_1 /*!< RGB565 */
+#define LL_DMA2D_INPUT_MODE_ARGB1555 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1) /*!< ARGB1555 */
+#define LL_DMA2D_INPUT_MODE_ARGB4444 DMA2D_FGPFCCR_CM_2 /*!< ARGB4444 */
+#define LL_DMA2D_INPUT_MODE_L8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_2) /*!< L8 */
+#define LL_DMA2D_INPUT_MODE_AL44 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL44 */
+#define LL_DMA2D_INPUT_MODE_AL88 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL88 */
+#define LL_DMA2D_INPUT_MODE_L4 DMA2D_FGPFCCR_CM_3 /*!< L4 */
+#define LL_DMA2D_INPUT_MODE_A8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_3) /*!< A8 */
+#define LL_DMA2D_INPUT_MODE_A4 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3) /*!< A4 */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_LL_EC_ALPHA_MODE Alpha Mode
+ * @{
+ */
+#define LL_DMA2D_ALPHA_MODE_NO_MODIF 0x00000000U /*!< No modification of the alpha channel value */
+#define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0 /*!< Replace original alpha channel value by
+ programmed alpha value */
+#define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1 /*!< Replace original alpha channel value by
+ programmed alpha value with,
+ original alpha channel value */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_LL_EC_OUTPUT_SWAP_MODE Swap Mode
+ * @{
+ */
+#define LL_DMA2D_SWAP_MODE_REGULAR 0x00000000U /*!< Regular order */
+#define LL_DMA2D_SWAP_MODE_TWO_BY_TWO DMA2D_OPFCCR_SB /*!< Bytes swapped two by two */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_LL_EC_RED_BLUE_SWAP Red Blue Swap
+ * @{
+ */
+#define LL_DMA2D_RB_MODE_REGULAR 0x00000000U /*!< RGB or ARGB */
+#define LL_DMA2D_RB_MODE_SWAP DMA2D_FGPFCCR_RBS /*!< BGR or ABGR */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_LL_EC_ALPHA_INVERSION Alpha Inversion
+ * @{
+ */
+#define LL_DMA2D_ALPHA_REGULAR 0x00000000U /*!< Regular alpha */
+#define LL_DMA2D_ALPHA_INVERTED DMA2D_FGPFCCR_AI /*!< Inverted alpha */
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA2D_LL_EC_LINE_OFFSET_MODE Line Offset Mode
+ * @{
+ */
+#define LL_DMA2D_LINE_OFFSET_PIXELS 0x00000000U /*!< Line offsets are expressed in pixels */
+#define LL_DMA2D_LINE_OFFSET_BYTES DMA2D_CR_LOM /*!< Line offsets are expressed in bytes */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_LL_EC_CLUT_COLOR_MODE CLUT Color Mode
+ * @{
+ */
+#define LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
+#define LL_DMA2D_CLUT_COLOR_MODE_RGB888 DMA2D_FGPFCCR_CCM /*!< RGB888 */
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMA2D_LL_Exported_Macros DMA2D Exported Macros
+ * @{
+ */
+
+/** @defgroup DMA2D_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in DMA2D register.
+ * @param __INSTANCE__ DMA2D Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in DMA2D register.
+ * @param __INSTANCE__ DMA2D Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DMA2D_LL_Exported_Functions DMA2D Exported Functions
+ * @{
+ */
+
+/** @defgroup DMA2D_LL_EF_Configuration Configuration Functions
+ * @{
+ */
+
+/**
+ * @brief Start a DMA2D transfer.
+ * @rmtoll CR START LL_DMA2D_Start
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx)
+{
+ SET_BIT(DMA2Dx->CR, DMA2D_CR_START);
+}
+
+/**
+ * @brief Indicate if a DMA2D transfer is ongoing.
+ * @rmtoll CR START LL_DMA2D_IsTransferOngoing
+ * @param DMA2Dx DMA2D Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef *DMA2Dx)
+{
+ return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Suspend DMA2D transfer.
+ * @note This API can be used to suspend automatic foreground or background CLUT loading.
+ * @rmtoll CR SUSP LL_DMA2D_Suspend
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_Suspend(DMA2D_TypeDef *DMA2Dx)
+{
+ MODIFY_REG(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP);
+}
+
+/**
+ * @brief Resume DMA2D transfer.
+ * @note This API can be used to resume automatic foreground or background CLUT loading.
+ * @rmtoll CR SUSP LL_DMA2D_Resume
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx)
+{
+ CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START);
+}
+
+/**
+ * @brief Indicate if DMA2D transfer is suspended.
+ * @note This API can be used to indicate whether or not automatic foreground or
+ * background CLUT loading is suspended.
+ * @rmtoll CR SUSP LL_DMA2D_IsSuspended
+ * @param DMA2Dx DMA2D Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(DMA2D_TypeDef *DMA2Dx)
+{
+ return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Abort DMA2D transfer.
+ * @note This API can be used to abort automatic foreground or background CLUT loading.
+ * @rmtoll CR ABORT LL_DMA2D_Abort
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx)
+{
+ MODIFY_REG(DMA2Dx->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT);
+}
+
+/**
+ * @brief Indicate if DMA2D transfer is aborted.
+ * @note This API can be used to indicate whether or not automatic foreground or
+ * background CLUT loading is aborted.
+ * @rmtoll CR ABORT LL_DMA2D_IsAborted
+ * @param DMA2Dx DMA2D Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx)
+{
+ return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set DMA2D mode.
+ * @rmtoll CR MODE LL_DMA2D_SetMode
+ * @param DMA2Dx DMA2D Instance
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_DMA2D_MODE_M2M
+ * @arg @ref LL_DMA2D_MODE_M2M_PFC
+ * @arg @ref LL_DMA2D_MODE_M2M_BLEND
+ * @arg @ref LL_DMA2D_MODE_R2M
+ * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG
+ * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode)
+{
+ MODIFY_REG(DMA2Dx->CR, DMA2D_CR_MODE, Mode);
+}
+
+/**
+ * @brief Return DMA2D mode
+ * @rmtoll CR MODE LL_DMA2D_GetMode
+ * @param DMA2Dx DMA2D Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA2D_MODE_M2M
+ * @arg @ref LL_DMA2D_MODE_M2M_PFC
+ * @arg @ref LL_DMA2D_MODE_M2M_BLEND
+ * @arg @ref LL_DMA2D_MODE_R2M
+ * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG
+ * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_GetMode(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_MODE));
+}
+
+/**
+ * @brief Set DMA2D output color mode.
+ * @rmtoll OPFCCR CM LL_DMA2D_SetOutputColorMode
+ * @param DMA2Dx DMA2D Instance
+ * @param ColorMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
+{
+ MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM, ColorMode);
+}
+
+/**
+ * @brief Return DMA2D output color mode.
+ * @rmtoll OPFCCR CM LL_DMA2D_GetOutputColorMode
+ * @param DMA2Dx DMA2D Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM));
+}
+
+/**
+ * @brief Set DMA2D output Red Blue swap mode.
+ * @rmtoll OPFCCR RBS LL_DMA2D_SetOutputRBSwapMode
+ * @param DMA2Dx DMA2D Instance
+ * @param RBSwapMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA2D_RB_MODE_REGULAR
+ * @arg @ref LL_DMA2D_RB_MODE_SWAP
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_SetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
+{
+ MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS, RBSwapMode);
+}
+
+/**
+ * @brief Return DMA2D output Red Blue swap mode.
+ * @rmtoll OPFCCR RBS LL_DMA2D_GetOutputRBSwapMode
+ * @param DMA2Dx DMA2D Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA2D_RB_MODE_REGULAR
+ * @arg @ref LL_DMA2D_RB_MODE_SWAP
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_GetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS));
+}
+
+/**
+ * @brief Set DMA2D output alpha inversion mode.
+ * @rmtoll OPFCCR AI LL_DMA2D_SetOutputAlphaInvMode
+ * @param DMA2Dx DMA2D Instance
+ * @param AlphaInversionMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA2D_ALPHA_REGULAR
+ * @arg @ref LL_DMA2D_ALPHA_INVERTED
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_SetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
+{
+ MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI, AlphaInversionMode);
+}
+
+/**
+ * @brief Return DMA2D output alpha inversion mode.
+ * @rmtoll OPFCCR AI LL_DMA2D_GetOutputAlphaInvMode
+ * @param DMA2Dx DMA2D Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA2D_ALPHA_REGULAR
+ * @arg @ref LL_DMA2D_ALPHA_INVERTED
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI));
+}
+
+
+/**
+ * @brief Set DMA2D output swap mode.
+ * @rmtoll OPFCCR SB LL_DMA2D_SetOutputSwapMode
+ * @param DMA2Dx DMA2D Instance
+ * @param OutputSwapMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA2D_SWAP_MODE_REGULAR
+ * @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_SetOutputSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t OutputSwapMode)
+{
+ MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB, OutputSwapMode);
+}
+
+/**
+ * @brief Return DMA2D output swap mode.
+ * @rmtoll OPFCCR SB LL_DMA2D_GetOutputSwapMode
+ * @param DMA2Dx DMA2D Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA2D_SWAP_MODE_REGULAR
+ * @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_GetOutputSwapMode(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB));
+}
+
+/**
+ * @brief Set DMA2D line offset mode.
+ * @rmtoll CR LOM LL_DMA2D_SetLineOffsetMode
+ * @param DMA2Dx DMA2D Instance
+ * @param LineOffsetMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS
+ * @arg @ref LL_DMA2D_LINE_OFFSET_BYTES
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_SetLineOffsetMode(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffsetMode)
+{
+ MODIFY_REG(DMA2Dx->CR, DMA2D_CR_LOM, LineOffsetMode);
+}
+
+/**
+ * @brief Return DMA2D line offset mode.
+ * @rmtoll CR LOM LL_DMA2D_GetLineOffsetMode
+ * @param DMA2Dx DMA2D Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS
+ * @arg @ref LL_DMA2D_LINE_OFFSET_BYTES
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffsetMode(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_LOM));
+}
+
+/**
+ * @brief Set DMA2D line offset, expressed on 14 bits ([13:0] bits).
+ * @rmtoll OOR LO LL_DMA2D_SetLineOffset
+ * @param DMA2Dx DMA2D Instance
+ * @param LineOffset Value between Min_Data=0 and Max_Data=0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
+{
+ MODIFY_REG(DMA2Dx->OOR, DMA2D_OOR_LO, LineOffset);
+}
+
+/**
+ * @brief Return DMA2D line offset, expressed on 14 bits ([13:0] bits).
+ * @rmtoll OOR LO LL_DMA2D_GetLineOffset
+ * @param DMA2Dx DMA2D Instance
+ * @retval Line offset value between Min_Data=0 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->OOR, DMA2D_OOR_LO));
+}
+
+/**
+ * @brief Set DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits).
+ * @rmtoll NLR PL LL_DMA2D_SetNbrOfPixelsPerLines
+ * @param DMA2Dx DMA2D Instance
+ * @param NbrOfPixelsPerLines Value between Min_Data=0 and Max_Data=0x3FFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfPixelsPerLines)
+{
+ MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_PL, (NbrOfPixelsPerLines << DMA2D_NLR_PL_Pos));
+}
+
+/**
+ * @brief Return DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits)
+ * @rmtoll NLR PL LL_DMA2D_GetNbrOfPixelsPerLines
+ * @param DMA2Dx DMA2D Instance
+ * @retval Number of pixels per lines value between Min_Data=0 and Max_Data=0x3FFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_PL) >> DMA2D_NLR_PL_Pos);
+}
+
+/**
+ * @brief Set DMA2D number of lines, expressed on 16 bits ([15:0] bits).
+ * @rmtoll NLR NL LL_DMA2D_SetNbrOfLines
+ * @param DMA2Dx DMA2D Instance
+ * @param NbrOfLines Value between Min_Data=0 and Max_Data=0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines)
+{
+ MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_NL, NbrOfLines);
+}
+
+/**
+ * @brief Return DMA2D number of lines, expressed on 16 bits ([15:0] bits).
+ * @rmtoll NLR NL LL_DMA2D_GetNbrOfLines
+ * @param DMA2Dx DMA2D Instance
+ * @retval Number of lines value between Min_Data=0 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_NL));
+}
+
+/**
+ * @brief Set DMA2D output memory address, expressed on 32 bits ([31:0] bits).
+ * @rmtoll OMAR MA LL_DMA2D_SetOutputMemAddr
+ * @param DMA2Dx DMA2D Instance
+ * @param OutputMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t OutputMemoryAddress)
+{
+ LL_DMA2D_WriteReg(DMA2Dx, OMAR, OutputMemoryAddress);
+}
+
+/**
+ * @brief Get DMA2D output memory address, expressed on 32 bits ([31:0] bits).
+ * @rmtoll OMAR MA LL_DMA2D_GetOutputMemAddr
+ * @param DMA2Dx DMA2D Instance
+ * @retval Output memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, OMAR));
+}
+
+/**
+ * @brief Set DMA2D output color, expressed on 32 bits ([31:0] bits).
+ * @note Output color format depends on output color mode, ARGB8888, RGB888,
+ * RGB565, ARGB1555 or ARGB4444.
+ * @note LL_DMA2D_ConfigOutputColor() API may be used instead if colors values formatting
+ * with respect to color mode is not done by the user code.
+ * @rmtoll OCOLR BLUE LL_DMA2D_SetOutputColor\n
+ * OCOLR GREEN LL_DMA2D_SetOutputColor\n
+ * OCOLR RED LL_DMA2D_SetOutputColor\n
+ * OCOLR ALPHA LL_DMA2D_SetOutputColor
+ * @param DMA2Dx DMA2D Instance
+ * @param OutputColor Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t OutputColor)
+{
+ MODIFY_REG(DMA2Dx->OCOLR, (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1), \
+ OutputColor);
+}
+
+/**
+ * @brief Get DMA2D output color, expressed on 32 bits ([31:0] bits).
+ * @note Alpha channel and red, green, blue color values must be retrieved from the returned
+ * value based on the output color mode (ARGB8888, RGB888, RGB565, ARGB1555 or ARGB4444)
+ * as set by @ref LL_DMA2D_SetOutputColorMode.
+ * @rmtoll OCOLR BLUE LL_DMA2D_GetOutputColor\n
+ * OCOLR GREEN LL_DMA2D_GetOutputColor\n
+ * OCOLR RED LL_DMA2D_GetOutputColor\n
+ * OCOLR ALPHA LL_DMA2D_GetOutputColor
+ * @param DMA2Dx DMA2D Instance
+ * @retval Output color value between Min_Data=0 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->OCOLR, \
+ (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1)));
+}
+
+/**
+ * @brief Set DMA2D line watermark, expressed on 16 bits ([15:0] bits).
+ * @rmtoll LWR LW LL_DMA2D_SetLineWatermark
+ * @param DMA2Dx DMA2D Instance
+ * @param LineWatermark Value between Min_Data=0 and Max_Data=0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_SetLineWatermark(DMA2D_TypeDef *DMA2Dx, uint32_t LineWatermark)
+{
+ MODIFY_REG(DMA2Dx->LWR, DMA2D_LWR_LW, LineWatermark);
+}
+
+/**
+ * @brief Return DMA2D line watermark, expressed on 16 bits ([15:0] bits).
+ * @rmtoll LWR LW LL_DMA2D_GetLineWatermark
+ * @param DMA2Dx DMA2D Instance
+ * @retval Line watermark value between Min_Data=0 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->LWR, DMA2D_LWR_LW));
+}
+
+/**
+ * @brief Set DMA2D dead time, expressed on 8 bits ([7:0] bits).
+ * @rmtoll AMTCR DT LL_DMA2D_SetDeadTime
+ * @param DMA2Dx DMA2D Instance
+ * @param DeadTime Value between Min_Data=0 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_SetDeadTime(DMA2D_TypeDef *DMA2Dx, uint32_t DeadTime)
+{
+ MODIFY_REG(DMA2Dx->AMTCR, DMA2D_AMTCR_DT, (DeadTime << DMA2D_AMTCR_DT_Pos));
+}
+
+/**
+ * @brief Return DMA2D dead time, expressed on 8 bits ([7:0] bits).
+ * @rmtoll AMTCR DT LL_DMA2D_GetDeadTime
+ * @param DMA2Dx DMA2D Instance
+ * @retval Dead time value between Min_Data=0 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_DT) >> DMA2D_AMTCR_DT_Pos);
+}
+
+/**
+ * @brief Enable DMA2D dead time functionality.
+ * @rmtoll AMTCR EN LL_DMA2D_EnableDeadTime
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_EnableDeadTime(DMA2D_TypeDef *DMA2Dx)
+{
+ SET_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
+}
+
+/**
+ * @brief Disable DMA2D dead time functionality.
+ * @rmtoll AMTCR EN LL_DMA2D_DisableDeadTime
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx)
+{
+ CLEAR_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
+}
+
+/**
+ * @brief Indicate if DMA2D dead time functionality is enabled.
+ * @rmtoll AMTCR EN LL_DMA2D_IsEnabledDeadTime
+ * @param DMA2Dx DMA2D Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef *DMA2Dx)
+{
+ return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL);
+}
+
+/** @defgroup DMA2D_LL_EF_FGND_Configuration Foreground Configuration Functions
+ * @{
+ */
+
+/**
+ * @brief Set DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
+ * @rmtoll FGMAR MA LL_DMA2D_FGND_SetMemAddr
+ * @param DMA2Dx DMA2D Instance
+ * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
+{
+ LL_DMA2D_WriteReg(DMA2Dx, FGMAR, MemoryAddress);
+}
+
+/**
+ * @brief Get DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
+ * @rmtoll FGMAR MA LL_DMA2D_FGND_GetMemAddr
+ * @param DMA2Dx DMA2D Instance
+ * @retval Foreground memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGMAR));
+}
+
+/**
+ * @brief Enable DMA2D foreground CLUT loading.
+ * @rmtoll FGPFCCR START LL_DMA2D_FGND_EnableCLUTLoad
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
+{
+ SET_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START);
+}
+
+/**
+ * @brief Indicate if DMA2D foreground CLUT loading is enabled.
+ * @rmtoll FGPFCCR START LL_DMA2D_FGND_IsEnabledCLUTLoad
+ * @param DMA2Dx DMA2D Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
+{
+ return ((READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set DMA2D foreground color mode.
+ * @rmtoll FGPFCCR CM LL_DMA2D_FGND_SetColorMode
+ * @param DMA2Dx DMA2D Instance
+ * @param ColorMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
+ * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
+ * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
+ * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
+ * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
+ * @arg @ref LL_DMA2D_INPUT_MODE_L8
+ * @arg @ref LL_DMA2D_INPUT_MODE_AL44
+ * @arg @ref LL_DMA2D_INPUT_MODE_AL88
+ * @arg @ref LL_DMA2D_INPUT_MODE_L4
+ * @arg @ref LL_DMA2D_INPUT_MODE_A8
+ * @arg @ref LL_DMA2D_INPUT_MODE_A4
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
+{
+ MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM, ColorMode);
+}
+
+/**
+ * @brief Return DMA2D foreground color mode.
+ * @rmtoll FGPFCCR CM LL_DMA2D_FGND_GetColorMode
+ * @param DMA2Dx DMA2D Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
+ * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
+ * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
+ * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
+ * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
+ * @arg @ref LL_DMA2D_INPUT_MODE_L8
+ * @arg @ref LL_DMA2D_INPUT_MODE_AL44
+ * @arg @ref LL_DMA2D_INPUT_MODE_AL88
+ * @arg @ref LL_DMA2D_INPUT_MODE_L4
+ * @arg @ref LL_DMA2D_INPUT_MODE_A8
+ * @arg @ref LL_DMA2D_INPUT_MODE_A4
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM));
+}
+
+/**
+ * @brief Set DMA2D foreground alpha mode.
+ * @rmtoll FGPFCCR AM LL_DMA2D_FGND_SetAlphaMode
+ * @param DMA2Dx DMA2D Instance
+ * @param AphaMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
+ * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
+ * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
+{
+ MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM, AphaMode);
+}
+
+/**
+ * @brief Return DMA2D foreground alpha mode.
+ * @rmtoll FGPFCCR AM LL_DMA2D_FGND_GetAlphaMode
+ * @param DMA2Dx DMA2D Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
+ * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
+ * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM));
+}
+
+/**
+ * @brief Set DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
+ * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_SetAlpha
+ * @param DMA2Dx DMA2D Instance
+ * @param Alpha Value between Min_Data=0 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
+{
+ MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA, (Alpha << DMA2D_FGPFCCR_ALPHA_Pos));
+}
+
+/**
+ * @brief Return DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
+ * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_GetAlpha
+ * @param DMA2Dx DMA2D Instance
+ * @retval Alpha value between Min_Data=0 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA) >> DMA2D_FGPFCCR_ALPHA_Pos);
+}
+
+/**
+ * @brief Set DMA2D foreground Red Blue swap mode.
+ * @rmtoll FGPFCCR RBS LL_DMA2D_FGND_SetRBSwapMode
+ * @param DMA2Dx DMA2D Instance
+ * @param RBSwapMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA2D_RB_MODE_REGULAR
+ * @arg @ref LL_DMA2D_RB_MODE_SWAP
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_FGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
+{
+ MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS, RBSwapMode);
+}
+
+/**
+ * @brief Return DMA2D foreground Red Blue swap mode.
+ * @rmtoll FGPFCCR RBS LL_DMA2D_FGND_GetRBSwapMode
+ * @param DMA2Dx DMA2D Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA2D_RB_MODE_REGULAR
+ * @arg @ref LL_DMA2D_RB_MODE_SWAP
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS));
+}
+
+/**
+ * @brief Set DMA2D foreground alpha inversion mode.
+ * @rmtoll FGPFCCR AI LL_DMA2D_FGND_SetAlphaInvMode
+ * @param DMA2Dx DMA2D Instance
+ * @param AlphaInversionMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA2D_ALPHA_REGULAR
+ * @arg @ref LL_DMA2D_ALPHA_INVERTED
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_FGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
+{
+ MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI, AlphaInversionMode);
+}
+
+/**
+ * @brief Return DMA2D foreground alpha inversion mode.
+ * @rmtoll FGPFCCR AI LL_DMA2D_FGND_GetAlphaInvMode
+ * @param DMA2Dx DMA2D Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA2D_ALPHA_REGULAR
+ * @arg @ref LL_DMA2D_ALPHA_INVERTED
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI));
+}
+
+/**
+ * @brief Set DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
+ * @rmtoll FGOR LO LL_DMA2D_FGND_SetLineOffset
+ * @param DMA2Dx DMA2D Instance
+ * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
+{
+ MODIFY_REG(DMA2Dx->FGOR, DMA2D_FGOR_LO, LineOffset);
+}
+
+/**
+ * @brief Return DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
+ * @rmtoll FGOR LO LL_DMA2D_FGND_GetLineOffset
+ * @param DMA2Dx DMA2D Instance
+ * @retval Foreground line offset value between Min_Data=0 and Max_Data=0x3FF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->FGOR, DMA2D_FGOR_LO));
+}
+
+/**
+ * @brief Set DMA2D foreground color values, expressed on 24 bits ([23:0] bits).
+ * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetColor
+ * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetColor
+ * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetColor
+ * @param DMA2Dx DMA2D Instance
+ * @param Red Value between Min_Data=0 and Max_Data=0xFF
+ * @param Green Value between Min_Data=0 and Max_Data=0xFF
+ * @param Blue Value between Min_Data=0 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_FGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
+{
+ MODIFY_REG(DMA2Dx->FGCOLR, (DMA2D_FGCOLR_RED | DMA2D_FGCOLR_GREEN | DMA2D_FGCOLR_BLUE), \
+ ((Red << DMA2D_FGCOLR_RED_Pos) | (Green << DMA2D_FGCOLR_GREEN_Pos) | Blue));
+}
+
+/**
+ * @brief Set DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
+ * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetRedColor
+ * @param DMA2Dx DMA2D Instance
+ * @param Red Value between Min_Data=0 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
+{
+ MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED, (Red << DMA2D_FGCOLR_RED_Pos));
+}
+
+/**
+ * @brief Return DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
+ * @rmtoll FGCOLR RED LL_DMA2D_FGND_GetRedColor
+ * @param DMA2Dx DMA2D Instance
+ * @retval Red color value between Min_Data=0 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED) >> DMA2D_FGCOLR_RED_Pos);
+}
+
+/**
+ * @brief Set DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
+ * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetGreenColor
+ * @param DMA2Dx DMA2D Instance
+ * @param Green Value between Min_Data=0 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
+{
+ MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN, (Green << DMA2D_FGCOLR_GREEN_Pos));
+}
+
+/**
+ * @brief Return DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
+ * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_GetGreenColor
+ * @param DMA2Dx DMA2D Instance
+ * @retval Green color value between Min_Data=0 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN) >> DMA2D_FGCOLR_GREEN_Pos);
+}
+
+/**
+ * @brief Set DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
+ * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetBlueColor
+ * @param DMA2Dx DMA2D Instance
+ * @param Blue Value between Min_Data=0 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
+{
+ MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE, Blue);
+}
+
+/**
+ * @brief Return DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
+ * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_GetBlueColor
+ * @param DMA2Dx DMA2D Instance
+ * @retval Blue color value between Min_Data=0 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE));
+}
+
+/**
+ * @brief Set DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
+ * @rmtoll FGCMAR MA LL_DMA2D_FGND_SetCLUTMemAddr
+ * @param DMA2Dx DMA2D Instance
+ * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
+{
+ LL_DMA2D_WriteReg(DMA2Dx, FGCMAR, CLUTMemoryAddress);
+}
+
+/**
+ * @brief Get DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
+ * @rmtoll FGCMAR MA LL_DMA2D_FGND_GetCLUTMemAddr
+ * @param DMA2Dx DMA2D Instance
+ * @retval Foreground CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGCMAR));
+}
+
+/**
+ * @brief Set DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
+ * @rmtoll FGPFCCR CS LL_DMA2D_FGND_SetCLUTSize
+ * @param DMA2Dx DMA2D Instance
+ * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
+{
+ MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS, (CLUTSize << DMA2D_FGPFCCR_CS_Pos));
+}
+
+/**
+ * @brief Get DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
+ * @rmtoll FGPFCCR CS LL_DMA2D_FGND_GetCLUTSize
+ * @param DMA2Dx DMA2D Instance
+ * @retval Foreground CLUT size value between Min_Data=0 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS) >> DMA2D_FGPFCCR_CS_Pos);
+}
+
+/**
+ * @brief Set DMA2D foreground CLUT color mode.
+ * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_SetCLUTColorMode
+ * @param DMA2Dx DMA2D Instance
+ * @param CLUTColorMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
+ * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
+{
+ MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM, CLUTColorMode);
+}
+
+/**
+ * @brief Return DMA2D foreground CLUT color mode.
+ * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_GetCLUTColorMode
+ * @param DMA2Dx DMA2D Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
+ * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_LL_EF_BGND_Configuration Background Configuration Functions
+ * @{
+ */
+
+/**
+ * @brief Set DMA2D background memory address, expressed on 32 bits ([31:0] bits).
+ * @rmtoll BGMAR MA LL_DMA2D_BGND_SetMemAddr
+ * @param DMA2Dx DMA2D Instance
+ * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
+{
+ LL_DMA2D_WriteReg(DMA2Dx, BGMAR, MemoryAddress);
+}
+
+/**
+ * @brief Get DMA2D background memory address, expressed on 32 bits ([31:0] bits).
+ * @rmtoll BGMAR MA LL_DMA2D_BGND_GetMemAddr
+ * @param DMA2Dx DMA2D Instance
+ * @retval Background memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGMAR));
+}
+
+/**
+ * @brief Enable DMA2D background CLUT loading.
+ * @rmtoll BGPFCCR START LL_DMA2D_BGND_EnableCLUTLoad
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
+{
+ SET_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START);
+}
+
+/**
+ * @brief Indicate if DMA2D background CLUT loading is enabled.
+ * @rmtoll BGPFCCR START LL_DMA2D_BGND_IsEnabledCLUTLoad
+ * @param DMA2Dx DMA2D Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
+{
+ return ((READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set DMA2D background color mode.
+ * @rmtoll BGPFCCR CM LL_DMA2D_BGND_SetColorMode
+ * @param DMA2Dx DMA2D Instance
+ * @param ColorMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
+ * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
+ * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
+ * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
+ * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
+ * @arg @ref LL_DMA2D_INPUT_MODE_L8
+ * @arg @ref LL_DMA2D_INPUT_MODE_AL44
+ * @arg @ref LL_DMA2D_INPUT_MODE_AL88
+ * @arg @ref LL_DMA2D_INPUT_MODE_L4
+ * @arg @ref LL_DMA2D_INPUT_MODE_A8
+ * @arg @ref LL_DMA2D_INPUT_MODE_A4
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
+{
+ MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM, ColorMode);
+}
+
+/**
+ * @brief Return DMA2D background color mode.
+ * @rmtoll BGPFCCR CM LL_DMA2D_BGND_GetColorMode
+ * @param DMA2Dx DMA2D Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
+ * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
+ * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
+ * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
+ * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
+ * @arg @ref LL_DMA2D_INPUT_MODE_L8
+ * @arg @ref LL_DMA2D_INPUT_MODE_AL44
+ * @arg @ref LL_DMA2D_INPUT_MODE_AL88
+ * @arg @ref LL_DMA2D_INPUT_MODE_L4
+ * @arg @ref LL_DMA2D_INPUT_MODE_A8
+ * @arg @ref LL_DMA2D_INPUT_MODE_A4
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM));
+}
+
+/**
+ * @brief Set DMA2D background alpha mode.
+ * @rmtoll BGPFCCR AM LL_DMA2D_BGND_SetAlphaMode
+ * @param DMA2Dx DMA2D Instance
+ * @param AphaMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
+ * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
+ * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
+{
+ MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM, AphaMode);
+}
+
+/**
+ * @brief Return DMA2D background alpha mode.
+ * @rmtoll BGPFCCR AM LL_DMA2D_BGND_GetAlphaMode
+ * @param DMA2Dx DMA2D Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
+ * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
+ * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM));
+}
+
+/**
+ * @brief Set DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
+ * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_SetAlpha
+ * @param DMA2Dx DMA2D Instance
+ * @param Alpha Value between Min_Data=0 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
+{
+ MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA, (Alpha << DMA2D_BGPFCCR_ALPHA_Pos));
+}
+
+/**
+ * @brief Return DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
+ * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_GetAlpha
+ * @param DMA2Dx DMA2D Instance
+ * @retval Alpha value between Min_Data=0 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA) >> DMA2D_BGPFCCR_ALPHA_Pos);
+}
+
+/**
+ * @brief Set DMA2D background Red Blue swap mode.
+ * @rmtoll BGPFCCR RBS LL_DMA2D_BGND_SetRBSwapMode
+ * @param DMA2Dx DMA2D Instance
+ * @param RBSwapMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA2D_RB_MODE_REGULAR
+ * @arg @ref LL_DMA2D_RB_MODE_SWAP
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_BGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
+{
+ MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS, RBSwapMode);
+}
+
+/**
+ * @brief Return DMA2D background Red Blue swap mode.
+ * @rmtoll BGPFCCR RBS LL_DMA2D_BGND_GetRBSwapMode
+ * @param DMA2Dx DMA2D Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA2D_RB_MODE_REGULAR
+ * @arg @ref LL_DMA2D_RB_MODE_SWAP
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS));
+}
+
+/**
+ * @brief Set DMA2D background alpha inversion mode.
+ * @rmtoll BGPFCCR AI LL_DMA2D_BGND_SetAlphaInvMode
+ * @param DMA2Dx DMA2D Instance
+ * @param AlphaInversionMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA2D_ALPHA_REGULAR
+ * @arg @ref LL_DMA2D_ALPHA_INVERTED
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_BGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
+{
+ MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI, AlphaInversionMode);
+}
+
+/**
+ * @brief Return DMA2D background alpha inversion mode.
+ * @rmtoll BGPFCCR AI LL_DMA2D_BGND_GetAlphaInvMode
+ * @param DMA2Dx DMA2D Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA2D_ALPHA_REGULAR
+ * @arg @ref LL_DMA2D_ALPHA_INVERTED
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI));
+}
+
+/**
+ * @brief Set DMA2D background line offset, expressed on 14 bits ([13:0] bits).
+ * @rmtoll BGOR LO LL_DMA2D_BGND_SetLineOffset
+ * @param DMA2Dx DMA2D Instance
+ * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
+{
+ MODIFY_REG(DMA2Dx->BGOR, DMA2D_BGOR_LO, LineOffset);
+}
+
+/**
+ * @brief Return DMA2D background line offset, expressed on 14 bits ([13:0] bits).
+ * @rmtoll BGOR LO LL_DMA2D_BGND_GetLineOffset
+ * @param DMA2Dx DMA2D Instance
+ * @retval Background line offset value between Min_Data=0 and Max_Data=0x3FF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->BGOR, DMA2D_BGOR_LO));
+}
+
+/**
+ * @brief Set DMA2D background color values, expressed on 24 bits ([23:0] bits).
+ * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetColor
+ * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetColor
+ * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetColor
+ * @param DMA2Dx DMA2D Instance
+ * @param Red Value between Min_Data=0 and Max_Data=0xFF
+ * @param Green Value between Min_Data=0 and Max_Data=0xFF
+ * @param Blue Value between Min_Data=0 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_BGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
+{
+ MODIFY_REG(DMA2Dx->BGCOLR, (DMA2D_BGCOLR_RED | DMA2D_BGCOLR_GREEN | DMA2D_BGCOLR_BLUE), \
+ ((Red << DMA2D_BGCOLR_RED_Pos) | (Green << DMA2D_BGCOLR_GREEN_Pos) | Blue));
+}
+
+/**
+ * @brief Set DMA2D background red color value, expressed on 8 bits ([7:0] bits).
+ * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetRedColor
+ * @param DMA2Dx DMA2D Instance
+ * @param Red Value between Min_Data=0 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
+{
+ MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED, (Red << DMA2D_BGCOLR_RED_Pos));
+}
+
+/**
+ * @brief Return DMA2D background red color value, expressed on 8 bits ([7:0] bits).
+ * @rmtoll BGCOLR RED LL_DMA2D_BGND_GetRedColor
+ * @param DMA2Dx DMA2D Instance
+ * @retval Red color value between Min_Data=0 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED) >> DMA2D_BGCOLR_RED_Pos);
+}
+
+/**
+ * @brief Set DMA2D background green color value, expressed on 8 bits ([7:0] bits).
+ * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetGreenColor
+ * @param DMA2Dx DMA2D Instance
+ * @param Green Value between Min_Data=0 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
+{
+ MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN, (Green << DMA2D_BGCOLR_GREEN_Pos));
+}
+
+/**
+ * @brief Return DMA2D background green color value, expressed on 8 bits ([7:0] bits).
+ * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_GetGreenColor
+ * @param DMA2Dx DMA2D Instance
+ * @retval Green color value between Min_Data=0 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN) >> DMA2D_BGCOLR_GREEN_Pos);
+}
+
+/**
+ * @brief Set DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
+ * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetBlueColor
+ * @param DMA2Dx DMA2D Instance
+ * @param Blue Value between Min_Data=0 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
+{
+ MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE, Blue);
+}
+
+/**
+ * @brief Return DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
+ * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_GetBlueColor
+ * @param DMA2Dx DMA2D Instance
+ * @retval Blue color value between Min_Data=0 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE));
+}
+
+/**
+ * @brief Set DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
+ * @rmtoll BGCMAR MA LL_DMA2D_BGND_SetCLUTMemAddr
+ * @param DMA2Dx DMA2D Instance
+ * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
+{
+ LL_DMA2D_WriteReg(DMA2Dx, BGCMAR, CLUTMemoryAddress);
+}
+
+/**
+ * @brief Get DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
+ * @rmtoll BGCMAR MA LL_DMA2D_BGND_GetCLUTMemAddr
+ * @param DMA2Dx DMA2D Instance
+ * @retval Background CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGCMAR));
+}
+
+/**
+ * @brief Set DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
+ * @rmtoll BGPFCCR CS LL_DMA2D_BGND_SetCLUTSize
+ * @param DMA2Dx DMA2D Instance
+ * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
+{
+ MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS, (CLUTSize << DMA2D_BGPFCCR_CS_Pos));
+}
+
+/**
+ * @brief Get DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
+ * @rmtoll BGPFCCR CS LL_DMA2D_BGND_GetCLUTSize
+ * @param DMA2Dx DMA2D Instance
+ * @retval Background CLUT size value between Min_Data=0 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS) >> DMA2D_BGPFCCR_CS_Pos);
+}
+
+/**
+ * @brief Set DMA2D background CLUT color mode.
+ * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_SetCLUTColorMode
+ * @param DMA2Dx DMA2D Instance
+ * @param CLUTColorMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
+ * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
+{
+ MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM, CLUTColorMode);
+}
+
+/**
+ * @brief Return DMA2D background CLUT color mode.
+ * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_GetCLUTColorMode
+ * @param DMA2Dx DMA2D Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
+ * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM));
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA2D_LL_EF_FLAG_MANAGEMENT Flag Management
+ * @{
+ */
+
+/**
+ * @brief Check if the DMA2D Configuration Error Interrupt Flag is set or not
+ * @rmtoll ISR CEIF LL_DMA2D_IsActiveFlag_CE
+ * @param DMA2Dx DMA2D Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx)
+{
+ return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the DMA2D CLUT Transfer Complete Interrupt Flag is set or not
+ * @rmtoll ISR CTCIF LL_DMA2D_IsActiveFlag_CTC
+ * @param DMA2Dx DMA2D Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx)
+{
+ return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the DMA2D CLUT Access Error Interrupt Flag is set or not
+ * @rmtoll ISR CAEIF LL_DMA2D_IsActiveFlag_CAE
+ * @param DMA2Dx DMA2D Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx)
+{
+ return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the DMA2D Transfer Watermark Interrupt Flag is set or not
+ * @rmtoll ISR TWIF LL_DMA2D_IsActiveFlag_TW
+ * @param DMA2Dx DMA2D Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx)
+{
+ return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the DMA2D Transfer Complete Interrupt Flag is set or not
+ * @rmtoll ISR TCIF LL_DMA2D_IsActiveFlag_TC
+ * @param DMA2Dx DMA2D Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx)
+{
+ return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the DMA2D Transfer Error Interrupt Flag is set or not
+ * @rmtoll ISR TEIF LL_DMA2D_IsActiveFlag_TE
+ * @param DMA2Dx DMA2D Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef *DMA2Dx)
+{
+ return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear DMA2D Configuration Error Interrupt Flag
+ * @rmtoll IFCR CCEIF LL_DMA2D_ClearFlag_CE
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_ClearFlag_CE(DMA2D_TypeDef *DMA2Dx)
+{
+ WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCEIF);
+}
+
+/**
+ * @brief Clear DMA2D CLUT Transfer Complete Interrupt Flag
+ * @rmtoll IFCR CCTCIF LL_DMA2D_ClearFlag_CTC
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_ClearFlag_CTC(DMA2D_TypeDef *DMA2Dx)
+{
+ WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCTCIF);
+}
+
+/**
+ * @brief Clear DMA2D CLUT Access Error Interrupt Flag
+ * @rmtoll IFCR CAECIF LL_DMA2D_ClearFlag_CAE
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_ClearFlag_CAE(DMA2D_TypeDef *DMA2Dx)
+{
+ WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CAECIF);
+}
+
+/**
+ * @brief Clear DMA2D Transfer Watermark Interrupt Flag
+ * @rmtoll IFCR CTWIF LL_DMA2D_ClearFlag_TW
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_ClearFlag_TW(DMA2D_TypeDef *DMA2Dx)
+{
+ WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTWIF);
+}
+
+/**
+ * @brief Clear DMA2D Transfer Complete Interrupt Flag
+ * @rmtoll IFCR CTCIF LL_DMA2D_ClearFlag_TC
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_ClearFlag_TC(DMA2D_TypeDef *DMA2Dx)
+{
+ WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTCIF);
+}
+
+/**
+ * @brief Clear DMA2D Transfer Error Interrupt Flag
+ * @rmtoll IFCR CTEIF LL_DMA2D_ClearFlag_TE
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_ClearFlag_TE(DMA2D_TypeDef *DMA2Dx)
+{
+ WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTEIF);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_LL_EF_IT_MANAGEMENT Interruption Management
+ * @{
+ */
+
+/**
+ * @brief Enable Configuration Error Interrupt
+ * @rmtoll CR CEIE LL_DMA2D_EnableIT_CE
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_EnableIT_CE(DMA2D_TypeDef *DMA2Dx)
+{
+ SET_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
+}
+
+/**
+ * @brief Enable CLUT Transfer Complete Interrupt
+ * @rmtoll CR CTCIE LL_DMA2D_EnableIT_CTC
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_EnableIT_CTC(DMA2D_TypeDef *DMA2Dx)
+{
+ SET_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
+}
+
+/**
+ * @brief Enable CLUT Access Error Interrupt
+ * @rmtoll CR CAEIE LL_DMA2D_EnableIT_CAE
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_EnableIT_CAE(DMA2D_TypeDef *DMA2Dx)
+{
+ SET_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
+}
+
+/**
+ * @brief Enable Transfer Watermark Interrupt
+ * @rmtoll CR TWIE LL_DMA2D_EnableIT_TW
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_EnableIT_TW(DMA2D_TypeDef *DMA2Dx)
+{
+ SET_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
+}
+
+/**
+ * @brief Enable Transfer Complete Interrupt
+ * @rmtoll CR TCIE LL_DMA2D_EnableIT_TC
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_EnableIT_TC(DMA2D_TypeDef *DMA2Dx)
+{
+ SET_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
+}
+
+/**
+ * @brief Enable Transfer Error Interrupt
+ * @rmtoll CR TEIE LL_DMA2D_EnableIT_TE
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_EnableIT_TE(DMA2D_TypeDef *DMA2Dx)
+{
+ SET_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
+}
+
+/**
+ * @brief Disable Configuration Error Interrupt
+ * @rmtoll CR CEIE LL_DMA2D_DisableIT_CE
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_DisableIT_CE(DMA2D_TypeDef *DMA2Dx)
+{
+ CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
+}
+
+/**
+ * @brief Disable CLUT Transfer Complete Interrupt
+ * @rmtoll CR CTCIE LL_DMA2D_DisableIT_CTC
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_DisableIT_CTC(DMA2D_TypeDef *DMA2Dx)
+{
+ CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
+}
+
+/**
+ * @brief Disable CLUT Access Error Interrupt
+ * @rmtoll CR CAEIE LL_DMA2D_DisableIT_CAE
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_DisableIT_CAE(DMA2D_TypeDef *DMA2Dx)
+{
+ CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
+}
+
+/**
+ * @brief Disable Transfer Watermark Interrupt
+ * @rmtoll CR TWIE LL_DMA2D_DisableIT_TW
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_DisableIT_TW(DMA2D_TypeDef *DMA2Dx)
+{
+ CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
+}
+
+/**
+ * @brief Disable Transfer Complete Interrupt
+ * @rmtoll CR TCIE LL_DMA2D_DisableIT_TC
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_DisableIT_TC(DMA2D_TypeDef *DMA2Dx)
+{
+ CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
+}
+
+/**
+ * @brief Disable Transfer Error Interrupt
+ * @rmtoll CR TEIE LL_DMA2D_DisableIT_TE
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx)
+{
+ CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
+}
+
+/**
+ * @brief Check if the DMA2D Configuration Error interrupt source is enabled or disabled.
+ * @rmtoll CR CEIE LL_DMA2D_IsEnabledIT_CE
+ * @param DMA2Dx DMA2D Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx)
+{
+ return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the DMA2D CLUT Transfer Complete interrupt source is enabled or disabled.
+ * @rmtoll CR CTCIE LL_DMA2D_IsEnabledIT_CTC
+ * @param DMA2Dx DMA2D Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx)
+{
+ return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the DMA2D CLUT Access Error interrupt source is enabled or disabled.
+ * @rmtoll CR CAEIE LL_DMA2D_IsEnabledIT_CAE
+ * @param DMA2Dx DMA2D Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx)
+{
+ return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the DMA2D Transfer Watermark interrupt source is enabled or disabled.
+ * @rmtoll CR TWIE LL_DMA2D_IsEnabledIT_TW
+ * @param DMA2Dx DMA2D Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx)
+{
+ return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the DMA2D Transfer Complete interrupt source is enabled or disabled.
+ * @rmtoll CR TCIE LL_DMA2D_IsEnabledIT_TC
+ * @param DMA2Dx DMA2D Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx)
+{
+ return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the DMA2D Transfer Error interrupt source is enabled or disabled.
+ * @rmtoll CR TEIE LL_DMA2D_IsEnabledIT_TE
+ * @param DMA2Dx DMA2D Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx)
+{
+ return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE)) ? 1UL : 0UL);
+}
+
+
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA2D_LL_EF_Init_Functions Initialization and De-initialization Functions
+ * @{
+ */
+
+ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx);
+ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
+void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
+void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx);
+void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg);
+void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct);
+uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
+uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
+uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
+uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
+void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (DMA2D) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_LL_DMA2D_H */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_exti.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_exti.h
new file mode 100644
index 00000000..7101af13
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_exti.h
@@ -0,0 +1,1387 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_exti.h
+ * @author MCD Application Team
+ * @brief Header file of EXTI LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_LL_EXTI_H
+#define STM32U5xx_LL_EXTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx.h"
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined (EXTI)
+
+/** @defgroup EXTI_LL EXTI
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+#define LL_EXTI_REGISTER_PINPOS_SHFT 16U /*!< Define used to shift pin position in EXTICR register */
+
+/* Private Macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
+ * @{
+ */
+typedef struct
+{
+
+ uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
+ This parameter can be any combination of @ref EXTI_LL_EC_LINE */
+
+ FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines.
+ This parameter can be set either to ENABLE or DISABLE */
+
+ uint8_t Mode; /*!< Specifies the mode for the EXTI lines.
+ This parameter can be a value of @ref EXTI_LL_EC_MODE. */
+
+ uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
+ This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
+} LL_EXTI_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
+ * @{
+ */
+
+/** @defgroup EXTI_LL_EC_LINE LINE
+ * @{
+ */
+#define LL_EXTI_LINE_0 EXTI_IMR1_IM0 /*!< Extended line 0 */
+#define LL_EXTI_LINE_1 EXTI_IMR1_IM1 /*!< Extended line 1 */
+#define LL_EXTI_LINE_2 EXTI_IMR1_IM2 /*!< Extended line 2 */
+#define LL_EXTI_LINE_3 EXTI_IMR1_IM3 /*!< Extended line 3 */
+#define LL_EXTI_LINE_4 EXTI_IMR1_IM4 /*!< Extended line 4 */
+#define LL_EXTI_LINE_5 EXTI_IMR1_IM5 /*!< Extended line 5 */
+#define LL_EXTI_LINE_6 EXTI_IMR1_IM6 /*!< Extended line 6 */
+#define LL_EXTI_LINE_7 EXTI_IMR1_IM7 /*!< Extended line 7 */
+#define LL_EXTI_LINE_8 EXTI_IMR1_IM8 /*!< Extended line 8 */
+#define LL_EXTI_LINE_9 EXTI_IMR1_IM9 /*!< Extended line 9 */
+#define LL_EXTI_LINE_10 EXTI_IMR1_IM10 /*!< Extended line 10 */
+#define LL_EXTI_LINE_11 EXTI_IMR1_IM11 /*!< Extended line 11 */
+#define LL_EXTI_LINE_12 EXTI_IMR1_IM12 /*!< Extended line 12 */
+#define LL_EXTI_LINE_13 EXTI_IMR1_IM13 /*!< Extended line 13 */
+#define LL_EXTI_LINE_14 EXTI_IMR1_IM14 /*!< Extended line 14 */
+#define LL_EXTI_LINE_15 EXTI_IMR1_IM15 /*!< Extended line 15 */
+#define LL_EXTI_LINE_16 EXTI_IMR1_IM16 /*!< Extended line 16 */
+#define LL_EXTI_LINE_17 EXTI_IMR1_IM17 /*!< Extended line 17 */
+#define LL_EXTI_LINE_18 EXTI_IMR1_IM18 /*!< Extended line 18 */
+#define LL_EXTI_LINE_19 EXTI_IMR1_IM19 /*!< Extended line 19 */
+#define LL_EXTI_LINE_20 EXTI_IMR1_IM20 /*!< Extended line 20 */
+#define LL_EXTI_LINE_21 EXTI_IMR1_IM21 /*!< Extended line 21 */
+#define LL_EXTI_LINE_22 EXTI_IMR1_IM22 /*!< Extended line 22 */
+#define LL_EXTI_LINE_ALL_0_31 0x007FFFFFU /*!< ALL Extended line */
+
+#if defined(USE_FULL_LL_DRIVER)
+#define LL_EXTI_LINE_NONE 0x00000000U /*!< None Extended line */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/** @defgroup SYSTEM_LL_EC_EXTI_PORT EXTI EXTI PORT
+ * @{
+ */
+#define LL_EXTI_EXTI_PORTA 0U /*!< EXTI PORT A */
+#define LL_EXTI_EXTI_PORTB EXTI_EXTICR1_EXTI0_0 /*!< EXTI PORT B */
+#define LL_EXTI_EXTI_PORTC EXTI_EXTICR1_EXTI0_1 /*!< EXTI PORT C */
+#define LL_EXTI_EXTI_PORTD (EXTI_EXTICR1_EXTI0_1|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT D */
+#define LL_EXTI_EXTI_PORTE EXTI_EXTICR1_EXTI0_2 /*!< EXTI PORT E */
+#define LL_EXTI_EXTI_PORTF (EXTI_EXTICR1_EXTI0_2|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT F */
+#define LL_EXTI_EXTI_PORTG (EXTI_EXTICR1_EXTI0_2|EXTI_EXTICR1_EXTI0_1) /*!< EXTI PORT G */
+#define LL_EXTI_EXTI_PORTH (EXTI_EXTICR1_EXTI0_2|EXTI_EXTICR1_EXTI0_1|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT H */
+#define LL_EXTI_EXTI_PORTI EXTI_EXTICR1_EXTI0_3 /*!< EXTI PORT I */
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_EXTI_LINE EXTI EXTI LINE
+ * @{
+ */
+#define LL_EXTI_EXTI_LINE0 ((0U << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */
+#define LL_EXTI_EXTI_LINE1 ((8U << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */
+#define LL_EXTI_EXTI_LINE2 ((16U << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_16 | EXTICR[0] */
+#define LL_EXTI_EXTI_LINE3 ((24U << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_24 | EXTICR[0] */
+#define LL_EXTI_EXTI_LINE4 ((0U << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */
+#define LL_EXTI_EXTI_LINE5 ((8U << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */
+#define LL_EXTI_EXTI_LINE6 ((16U << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_16 | EXTICR[1] */
+#define LL_EXTI_EXTI_LINE7 ((24U << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_24 | EXTICR[1] */
+#define LL_EXTI_EXTI_LINE8 ((0U << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */
+#define LL_EXTI_EXTI_LINE9 ((8U << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */
+#define LL_EXTI_EXTI_LINE10 ((16U << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_16 | EXTICR[2] */
+#define LL_EXTI_EXTI_LINE11 ((24U << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_24 | EXTICR[2] */
+#define LL_EXTI_EXTI_LINE12 ((0U << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */
+#define LL_EXTI_EXTI_LINE13 ((8U << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */
+#define LL_EXTI_EXTI_LINE14 ((16U << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_16 | EXTICR[3] */
+#define LL_EXTI_EXTI_LINE15 ((24U << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_24 | EXTICR[3] */
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup EXTI_LL_EC_MODE Mode
+ * @{
+ */
+#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */
+#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */
+#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
+ * @{
+ */
+#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */
+#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */
+#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */
+#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */
+
+/**
+ * @}
+ */
+
+
+#endif /*USE_FULL_LL_DRIVER*/
+
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
+ * @{
+ */
+
+/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in EXTI register
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in EXTI register
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
+ * @{
+ */
+/** @defgroup EXTI_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31
+ * @note The reset value for the direct or internal lines (see RM)
+ * is set to 1 in order to enable the interrupt by default.
+ * Bits are set automatically at Power on.
+ * @rmtoll IMR1 IMx LL_EXTI_EnableIT_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->IMR1, ExtiLine);
+}
+
+/**
+ * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31
+ * @note The reset value for the direct or internal lines (see RM)
+ * is set to 1 in order to enable the interrupt by default.
+ * Bits are set automatically at Power on.
+ * @rmtoll IMR1 IMx LL_EXTI_DisableIT_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->IMR1, ExtiLine);
+}
+
+/**
+ * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
+ * @note The reset value for the direct or internal lines (see RM)
+ * is set to 1 in order to enable the interrupt by default.
+ * Bits are set automatically at Power on.
+ * @rmtoll IMR1 IMx LL_EXTI_IsEnabledIT_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
+{
+ return ((READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Event_Management Event_Management
+ * @{
+ */
+
+/**
+ * @brief Enable ExtiLine Event request for Lines in range 0 to 31
+ * @rmtoll EMR1 EMx LL_EXTI_EnableEvent_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->EMR1, ExtiLine);
+
+}
+
+/**
+ * @brief Disable ExtiLine Event request for Lines in range 0 to 31
+ * @rmtoll EMR1 EMx LL_EXTI_DisableEvent_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->EMR1, ExtiLine);
+}
+
+/**
+ * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
+ * @rmtoll EMR1 EMx LL_EXTI_IsEnabledEvent_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
+{
+ return ((READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
+ * @{
+ */
+
+/**
+ * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a rising edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_RTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for
+ * the same interrupt line. In this case, both generate a trigger
+ * condition.
+ * @rmtoll RTSR1 RTx LL_EXTI_EnableRisingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->RTSR1, ExtiLine);
+}
+
+/**
+ * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a rising edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_RTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for
+ * the same interrupt line. In this case, both generate a trigger
+ * condition.
+ * @rmtoll RTSR1 RTx LL_EXTI_DisableRisingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->RTSR1, ExtiLine);
+
+}
+
+/**
+ * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31
+ * @rmtoll RTSR1 RTx LL_EXTI_IsEnabledRisingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
+{
+ return ((READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
+ * @{
+ */
+
+/**
+ * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a falling edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_FTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for
+ * the same interrupt line. In this case, both generate a trigger
+ * condition.
+ * @rmtoll FTSR1 FTx LL_EXTI_EnableFallingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->FTSR1, ExtiLine);
+}
+
+/**
+ * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a Falling edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_FTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for the same interrupt line.
+ * In this case, both generate a trigger condition.
+ * @rmtoll FTSR1 FTx LL_EXTI_DisableFallingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->FTSR1, ExtiLine);
+}
+
+/**
+ * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31
+ * @rmtoll FTSR1 FTx LL_EXTI_IsEnabledFallingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
+{
+ return ((READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
+ * @{
+ */
+
+/**
+ * @brief Generate a software Interrupt Event for Lines in range 0 to 31
+ * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to
+ * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR
+ * resulting in an interrupt request generation.
+ * This bit is cleared by clearing the corresponding bit in the EXTI_PR
+ * register (by writing a 1 into the bit)
+ * @rmtoll SWIER1 SWIx LL_EXTI_GenerateSWI_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->SWIER1, ExtiLine);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
+ * @{
+ */
+
+/**
+ * @brief Check if the ExtLine Falling Flag is set or not for Lines in range 0 to 31
+ * @note This bit is set when the falling edge event arrives on the interrupt
+ * line. This bit is cleared by writing a 1 to the bit.
+ * @rmtoll FPR1 FPIFx LL_EXTI_IsActiveFallingFlag_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsActiveFallingFlag_0_31(uint32_t ExtiLine)
+{
+ return ((READ_BIT(EXTI->FPR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Read ExtLine Combination Falling Flag for Lines in range 0 to 31
+ * @note This bit is set when the falling edge event arrives on the interrupt
+ * line. This bit is cleared by writing a 1 to the bit.
+ * @rmtoll FPR1 FPIFx LL_EXTI_ReadFallingFlag_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval @note This bit is set when the selected edge event arrives on the interrupt
+ */
+__STATIC_INLINE uint32_t LL_EXTI_ReadFallingFlag_0_31(uint32_t ExtiLine)
+{
+ return (uint32_t)(READ_BIT(EXTI->FPR1, ExtiLine));
+}
+
+/**
+ * @brief Clear ExtLine Falling Flags for Lines in range 0 to 31
+ * @note This bit is set when the falling edge event arrives on the interrupt
+ * line. This bit is cleared by writing a 1 to the bit.
+ * @rmtoll FPR1 FPIFx LL_EXTI_ClearFallingFlag_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_ClearFallingFlag_0_31(uint32_t ExtiLine)
+{
+ WRITE_REG(EXTI->FPR1, ExtiLine);
+}
+
+/**
+ * @brief Check if the ExtLine Rising Flag is set or not for Lines in range 0 to 31
+ * @note This bit is set when the Rising edge event arrives on the interrupt
+ * line. This bit is cleared by writing a 1 to the bit.
+ * @rmtoll RPR1 RPIFx LL_EXTI_IsActiveRisingFlag_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsActiveRisingFlag_0_31(uint32_t ExtiLine)
+{
+ return ((READ_BIT(EXTI->RPR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Read ExtLine Combination Rising Flag for Lines in range 0 to 31
+ * @note This bit is set when the Rising edge event arrives on the interrupt
+ * line. This bit is cleared by writing a 1 to the bit.
+ * @rmtoll RPR1 RPIFx LL_EXTI_ReadRisingFlag_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval @note This bit is set when the selected edge event arrives on the interrupt
+ */
+__STATIC_INLINE uint32_t LL_EXTI_ReadRisingFlag_0_31(uint32_t ExtiLine)
+{
+ return (uint32_t)(READ_BIT(EXTI->RPR1, ExtiLine));
+}
+
+/**
+ * @brief Clear ExtLine Rising Flags for Lines in range 0 to 31
+ * @note This bit is set when the Rising edge event arrives on the interrupt
+ * line. This bit is cleared by writing a 1 to the bit.
+ * @rmtoll RPR1 RPIFx LL_EXTI_ClearRisingFlag_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_ClearRisingFlag_0_31(uint32_t ExtiLine)
+{
+ WRITE_REG(EXTI->RPR1, ExtiLine);
+}
+
+/**
+ * @}
+ */
+/** @defgroup EXTI_LL_EF_Config EF configuration functions
+ * @{
+ */
+
+/**
+ * @brief Configure source input for the EXTI external interrupt.
+ * @rmtoll EXTI_EXTICR1 EXTI0 LL_EXTI_SetEXTISource\n
+ * EXTI_EXTICR1 EXTI1 LL_EXTI_SetEXTISource\n
+ * EXTI_EXTICR1 EXTI2 LL_EXTI_SetEXTISource\n
+ * EXTI_EXTICR1 EXTI3 LL_EXTI_SetEXTISource\n
+ * EXTI_EXTICR2 EXTI4 LL_EXTI_SetEXTISource\n
+ * EXTI_EXTICR2 EXTI5 LL_EXTI_SetEXTISource\n
+ * EXTI_EXTICR2 EXTI6 LL_EXTI_SetEXTISource\n
+ * EXTI_EXTICR2 EXTI7 LL_EXTI_SetEXTISource\n
+ * EXTI_EXTICR3 EXTI8 LL_EXTI_SetEXTISource\n
+ * EXTI_EXTICR3 EXTI9 LL_EXTI_SetEXTISource\n
+ * EXTI_EXTICR3 EXTI10 LL_EXTI_SetEXTISource\n
+ * EXTI_EXTICR3 EXTI11 LL_EXTI_SetEXTISource\n
+ * EXTI_EXTICR4 EXTI12 LL_EXTI_SetEXTISource\n
+ * EXTI_EXTICR4 EXTI13 LL_EXTI_SetEXTISource\n
+ * EXTI_EXTICR4 EXTI14 LL_EXTI_SetEXTISource\n
+ * EXTI_EXTICR4 EXTI15 LL_EXTI_SetEXTISource
+ * @param Port This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_EXTI_PORTA
+ * @arg @ref LL_EXTI_EXTI_PORTB
+ * @arg @ref LL_EXTI_EXTI_PORTC
+ * @arg @ref LL_EXTI_EXTI_PORTD
+ * @arg @ref LL_EXTI_EXTI_PORTE
+ * @arg @ref LL_EXTI_EXTI_PORTF
+ * @arg @ref LL_EXTI_EXTI_PORTG
+ * @arg @ref LL_EXTI_EXTI_PORTH
+ * @arg @ref LL_EXTI_EXTI_PORTI
+ *
+ * (*) value not defined in all devices
+ * @param Line This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_EXTI_LINE0
+ * @arg @ref LL_EXTI_EXTI_LINE1
+ * @arg @ref LL_EXTI_EXTI_LINE2
+ * @arg @ref LL_EXTI_EXTI_LINE3
+ * @arg @ref LL_EXTI_EXTI_LINE4
+ * @arg @ref LL_EXTI_EXTI_LINE5
+ * @arg @ref LL_EXTI_EXTI_LINE6
+ * @arg @ref LL_EXTI_EXTI_LINE7
+ * @arg @ref LL_EXTI_EXTI_LINE8
+ * @arg @ref LL_EXTI_EXTI_LINE9
+ * @arg @ref LL_EXTI_EXTI_LINE10
+ * @arg @ref LL_EXTI_EXTI_LINE11
+ * @arg @ref LL_EXTI_EXTI_LINE12
+ * @arg @ref LL_EXTI_EXTI_LINE13
+ * @arg @ref LL_EXTI_EXTI_LINE14
+ * @arg @ref LL_EXTI_EXTI_LINE15
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_SetEXTISource(uint32_t Port, uint32_t Line)
+{
+ MODIFY_REG(EXTI->EXTICR[Line & 0x03U], EXTI_EXTICR1_EXTI0 << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT), \
+ Port << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT));
+}
+
+/**
+ * @brief Get the configured defined for specific EXTI Line
+ * @rmtoll EXTI_EXTICR1 EXTI0 LL_EXTI_GetEXTISource\n
+ * EXTI_EXTICR1 EXTI1 LL_EXTI_GetEXTISource\n
+ * EXTI_EXTICR1 EXTI2 LL_EXTI_GetEXTISource\n
+ * EXTI_EXTICR1 EXTI3 LL_EXTI_GetEXTISource\n
+ * EXTI_EXTICR2 EXTI4 LL_EXTI_GetEXTISource\n
+ * EXTI_EXTICR2 EXTI5 LL_EXTI_GetEXTISource\n
+ * EXTI_EXTICR2 EXTI6 LL_EXTI_GetEXTISource\n
+ * EXTI_EXTICR2 EXTI7 LL_EXTI_GetEXTISource\n
+ * EXTI_EXTICR3 EXTI8 LL_EXTI_GetEXTISource\n
+ * EXTI_EXTICR3 EXTI9 LL_EXTI_GetEXTISource\n
+ * EXTI_EXTICR3 EXTI10 LL_EXTI_GetEXTISource\n
+ * EXTI_EXTICR3 EXTI11 LL_EXTI_GetEXTISource\n
+ * EXTI_EXTICR4 EXTI12 LL_EXTI_GetEXTISource\n
+ * EXTI_EXTICR4 EXTI13 LL_EXTI_GetEXTISource\n
+ * EXTI_EXTICR4 EXTI14 LL_EXTI_GetEXTISource\n
+ * EXTI_EXTICR4 EXTI15 LL_EXTI_GetEXTISource
+ * @param Line This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_EXTI_LINE0
+ * @arg @ref LL_EXTI_EXTI_LINE1
+ * @arg @ref LL_EXTI_EXTI_LINE2
+ * @arg @ref LL_EXTI_EXTI_LINE3
+ * @arg @ref LL_EXTI_EXTI_LINE4
+ * @arg @ref LL_EXTI_EXTI_LINE5
+ * @arg @ref LL_EXTI_EXTI_LINE6
+ * @arg @ref LL_EXTI_EXTI_LINE7
+ * @arg @ref LL_EXTI_EXTI_LINE8
+ * @arg @ref LL_EXTI_EXTI_LINE9
+ * @arg @ref LL_EXTI_EXTI_LINE10
+ * @arg @ref LL_EXTI_EXTI_LINE11
+ * @arg @ref LL_EXTI_EXTI_LINE12
+ * @arg @ref LL_EXTI_EXTI_LINE13
+ * @arg @ref LL_EXTI_EXTI_LINE14
+ * @arg @ref LL_EXTI_EXTI_LINE15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_EXTI_EXTI_PORTA
+ * @arg @ref LL_EXTI_EXTI_PORTB
+ * @arg @ref LL_EXTI_EXTI_PORTC
+ * @arg @ref LL_EXTI_EXTI_PORTD
+ * @arg @ref LL_EXTI_EXTI_PORTE
+ * @arg @ref LL_EXTI_EXTI_PORTF
+ * @arg @ref LL_EXTI_EXTI_PORTG
+ * @arg @ref LL_EXTI_EXTI_PORTH
+ * @arg @ref LL_EXTI_EXTI_PORTI
+ */
+__STATIC_INLINE uint32_t LL_EXTI_GetEXTISource(uint32_t Line)
+{
+ return (uint32_t)(READ_BIT(EXTI->EXTICR[Line & 0x03U],
+ (EXTI_EXTICR1_EXTI0 << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT))) >>
+ (Line >> LL_EXTI_REGISTER_PINPOS_SHFT));
+}
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Secure_Management Secure_Management
+ * @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ * @brief Enable ExtiLine Secure attribute for Lines in range 0 to 31
+ * @rmtoll SECCFGR1 SECx LL_EXTI_EnableSecure_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableSecure_0_31(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->SECCFGR1, ExtiLine);
+}
+
+/**
+ * @brief Disable ExtiLine Secure attribute for Lines in range 0 to 31
+ * @rmtoll SECCFGR1 SECx LL_EXTI_DisableSecure_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableSecure_0_31(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->SECCFGR1, ExtiLine);
+}
+
+#endif /* __ARM_FEATURE_CMSE */
+
+/**
+ * @brief Indicate if ExtiLine Secure attribute is enabled for Lines in range 0 to 31
+ * @rmtoll SECCFGR1 SECx LL_EXTI_IsEnabledSecure_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledSecure_0_31(uint32_t ExtiLine)
+{
+ return ((READ_BIT(EXTI->SECCFGR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Privilege_Management Privilege_Management
+ * @{
+ */
+
+/**
+ * @brief Enable ExtiLine Privilege attribute for Lines in range 0 to 31
+ * @rmtoll PRIVCFGR1 PRIVx LL_EXTI_EnablePrivilege_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnablePrivilege_0_31(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->PRIVCFGR1, ExtiLine);
+}
+
+/**
+ * @brief Disable ExtiLine Privilege attribute for Lines in range 0 to 31
+ * @rmtoll PRIVCFGR1 PRIVx LL_EXTI_DisablePrivilege_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisablePrivilege_0_31(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->PRIVCFGR1, ExtiLine);
+}
+
+/**
+ * @brief Indicate if ExtiLine Privilege attribute is enabled for Lines in range 0 to 31
+ * @rmtoll PRIVCFGR1 PRIVx LL_EXTI_IsEnabledPrivilege_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledPrivilege_0_31(uint32_t ExtiLine)
+{
+ return ((READ_BIT(EXTI->PRIVCFGR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
+ErrorStatus LL_EXTI_DeInit(void);
+void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
+
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* EXTI */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_LL_EXTI_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_fmac.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_fmac.h
new file mode 100644
index 00000000..5e5d8684
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_fmac.h
@@ -0,0 +1,1063 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_fmac.h
+ * @author MCD Application Team
+ * @brief Header file of FMAC LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_LL_FMAC_H
+#define STM32U5xx_LL_FMAC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx.h"
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined(FMAC)
+
+/** @defgroup FMAC_LL FMAC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FMAC_LL_Exported_Constants FMAC Exported Constants
+ * @{
+ */
+
+/** @defgroup FMAC_LL_EC_GET_FLAG Get Flag Defines
+ * @brief Flag defines which can be used with LL_FMAC_ReadReg function
+ * @{
+ */
+#define LL_FMAC_SR_SAT FMAC_SR_SAT /*!< Saturation Error Flag (this helps in debugging a filter) */
+#define LL_FMAC_SR_UNFL FMAC_SR_UNFL /*!< Underflow Error Flag */
+#define LL_FMAC_SR_OVFL FMAC_SR_OVFL /*!< Overflow Error Flag */
+#define LL_FMAC_SR_X1FULL FMAC_SR_X1FULL /*!< X1 Buffer Full Flag */
+#define LL_FMAC_SR_YEMPTY FMAC_SR_YEMPTY /*!< Y Buffer Empty Flag */
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_FMAC_ReadReg and LL_FMAC_WriteReg functions
+ * @{
+ */
+#define LL_FMAC_CR_SATIEN FMAC_CR_SATIEN /*!< Saturation Error Interrupt Enable (this helps in debugging a filter) */
+#define LL_FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN /*!< Underflow Error Interrupt Enable */
+#define LL_FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN /*!< Overflow Error Interrupt Enable */
+#define LL_FMAC_CR_WIEN FMAC_CR_WIEN /*!< Write Interrupt Enable */
+#define LL_FMAC_CR_RIEN FMAC_CR_RIEN /*!< Read Interrupt Enable */
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_LL_EC_WM FMAC watermarks
+ * @brief Watermark defines that can be used for buffer full (input) or buffer empty (output)
+ * @{
+ */
+#define LL_FMAC_WM_0_THRESHOLD_1 0x00000000U /*!< Buffer full/empty flag set if there is less than 1 free/unread space. */
+#define LL_FMAC_WM_1_THRESHOLD_2 0x01000000U /*!< Buffer full/empty flag set if there are less than 2 free/unread spaces. */
+#define LL_FMAC_WM_2_THRESHOLD_4 0x02000000U /*!< Buffer full/empty flag set if there are less than 4 free/unread spaces. */
+#define LL_FMAC_WM_3_THRESHOLD_8 0x03000000U /*!< Buffer full/empty flag set if there are less than 8 free/empty spaces. */
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_LL_EC_FUNC FMAC functions
+ * @{
+ */
+#define LL_FMAC_FUNC_LOAD_X1 (FMAC_PARAM_FUNC_0) /*!< Load X1 buffer */
+#define LL_FMAC_FUNC_LOAD_X2 (FMAC_PARAM_FUNC_1) /*!< Load X2 buffer */
+#define LL_FMAC_FUNC_LOAD_Y (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0) /*!< Load Y buffer */
+#define LL_FMAC_FUNC_CONVO_FIR (FMAC_PARAM_FUNC_3) /*!< Convolution (FIR filter) */
+#define LL_FMAC_FUNC_IIR_DIRECT_FORM_1 (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0) /*!< IIR filter (direct form 1) */
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_LL_EC_PROCESSING FMAC processing
+ * @{
+ */
+#define LL_FMAC_PROCESSING_STOP 0x00U /*!< Stop FMAC Processing */
+#define LL_FMAC_PROCESSING_START 0x01U /*!< Start FMAC Processing */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* External variables --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup FMAC_LL_Exported_Macros FMAC Exported Macros
+ * @{
+ */
+
+/** @defgroup FMAC_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in FMAC register
+ * @param __INSTANCE__ FMAC Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_FMAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in FMAC register
+ * @param __INSTANCE__ FMAC Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_FMAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup FMAC_LL_Exported_Functions FMAC Exported Functions
+ * @{
+ */
+
+/** @defgroup FMAC_LL_EF_Configuration FMAC Configuration functions
+ * @{
+ */
+
+/**
+ * @brief Configure X1 full watermark.
+ * @rmtoll X1BUFCFG FULL_WM LL_FMAC_SetX1FullWatermark
+ * @param FMACx FMAC instance
+ * @param Watermark This parameter can be one of the following values:
+ * @arg @ref LL_FMAC_WM_0_THRESHOLD_1
+ * @arg @ref LL_FMAC_WM_1_THRESHOLD_2
+ * @arg @ref LL_FMAC_WM_2_THRESHOLD_4
+ * @arg @ref LL_FMAC_WM_3_THRESHOLD_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_SetX1FullWatermark(FMAC_TypeDef *FMACx, uint32_t Watermark)
+{
+ MODIFY_REG(FMACx->X1BUFCFG, FMAC_X1BUFCFG_FULL_WM, Watermark);
+}
+
+/**
+ * @brief Return X1 full watermark.
+ * @rmtoll X1BUFCFG FULL_WM LL_FMAC_GetX1FullWatermark
+ * @param FMACx FMAC instance
+ * @retval uint32_t Returned value can be one of the following values:
+ * @arg @ref LL_FMAC_WM_0_THRESHOLD_1
+ * @arg @ref LL_FMAC_WM_1_THRESHOLD_2
+ * @arg @ref LL_FMAC_WM_2_THRESHOLD_4
+ * @arg @ref LL_FMAC_WM_3_THRESHOLD_8
+ */
+__STATIC_INLINE uint32_t LL_FMAC_GetX1FullWatermark(FMAC_TypeDef *FMACx)
+{
+ return (uint32_t)(READ_BIT(FMACx->X1BUFCFG, FMAC_X1BUFCFG_FULL_WM));
+}
+
+/**
+ * @brief Configure X1 buffer size.
+ * @rmtoll X1BUFCFG X1_BUF_SIZE LL_FMAC_SetX1BufferSize
+ * @param FMACx FMAC instance
+ * @param BufferSize Number of 16-bit words allocated to the input buffer (including the optional "headroom").
+ * This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_SetX1BufferSize(FMAC_TypeDef *FMACx, uint8_t BufferSize)
+{
+ MODIFY_REG(FMACx->X1BUFCFG, FMAC_X1BUFCFG_X1_BUF_SIZE, ((uint32_t)BufferSize) << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos);
+}
+
+/**
+ * @brief Return X1 buffer size.
+ * @rmtoll X1BUFCFG X1_BUF_SIZE LL_FMAC_GetX1BufferSize
+ * @param FMACx FMAC instance
+ * @retval uint8_t Number of 16-bit words allocated to the input buffer
+ * (including the optional "headroom") (value between Min_Data=0x01 and Max_Data=0xFF).
+ */
+__STATIC_INLINE uint8_t LL_FMAC_GetX1BufferSize(FMAC_TypeDef *FMACx)
+{
+ return (uint8_t)(READ_BIT(FMACx->X1BUFCFG, FMAC_X1BUFCFG_X1_BUF_SIZE) >> FMAC_X1BUFCFG_X1_BUF_SIZE_Pos);
+}
+
+/**
+ * @brief Configure X1 base.
+ * @rmtoll X1BUFCFG X1_BASE LL_FMAC_SetX1Base
+ * @param FMACx FMAC instance
+ * @param Base Base address of the input buffer (X1) within the internal memory.
+ * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_SetX1Base(FMAC_TypeDef *FMACx, uint8_t Base)
+{
+ MODIFY_REG(FMACx->X1BUFCFG, FMAC_X1BUFCFG_X1_BASE, ((uint32_t)Base) << FMAC_X1BUFCFG_X1_BASE_Pos);
+}
+
+/**
+ * @brief Return X1 base.
+ * @rmtoll X1BUFCFG X1_BASE LL_FMAC_GetX1Base
+ * @param FMACx FMAC instance
+ * @retval uint8_t Base address of the input buffer (X1) within the internal memory
+ * (value between Min_Data=0x00 and Max_Data=0xFF).
+ */
+__STATIC_INLINE uint8_t LL_FMAC_GetX1Base(FMAC_TypeDef *FMACx)
+{
+ return (uint8_t)(READ_BIT(FMACx->X1BUFCFG, FMAC_X1BUFCFG_X1_BASE) >> FMAC_X1BUFCFG_X1_BASE_Pos);
+}
+
+/**
+ * @brief Configure X2 buffer size.
+ * @rmtoll X2BUFCFG X2_BUF_SIZE LL_FMAC_SetX2BufferSize
+ * @param FMACx FMAC instance
+ * @param BufferSize Number of 16-bit words allocated to the coefficient buffer.
+ * This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_SetX2BufferSize(FMAC_TypeDef *FMACx, uint8_t BufferSize)
+{
+ MODIFY_REG(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BUF_SIZE, ((uint32_t)BufferSize) << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos);
+}
+
+/**
+ * @brief Return X2 buffer size.
+ * @rmtoll X2BUFCFG X2_BUF_SIZE LL_FMAC_GetX2BufferSize
+ * @param FMACx FMAC instance
+ * @retval uint8_t Number of 16-bit words allocated to the coefficient buffer
+ * (value between Min_Data=0x01 and Max_Data=0xFF).
+ */
+__STATIC_INLINE uint8_t LL_FMAC_GetX2BufferSize(FMAC_TypeDef *FMACx)
+{
+ return (uint8_t)(READ_BIT(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BUF_SIZE) >> FMAC_X2BUFCFG_X2_BUF_SIZE_Pos);
+}
+
+/**
+ * @brief Configure X2 base.
+ * @rmtoll X2BUFCFG X2_BASE LL_FMAC_SetX2Base
+ * @param FMACx FMAC instance
+ * @param Base Base address of the coefficient buffer (X2) within the internal memory.
+ * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_SetX2Base(FMAC_TypeDef *FMACx, uint8_t Base)
+{
+ MODIFY_REG(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BASE, ((uint32_t)Base) << FMAC_X2BUFCFG_X2_BASE_Pos);
+}
+
+/**
+ * @brief Return X2 base.
+ * @rmtoll X2BUFCFG X2_BASE LL_FMAC_GetX2Base
+ * @param FMACx FMAC instance
+ * @retval uint8_t Base address of the coefficient buffer (X2) within the internal memory
+ * (value between Min_Data=0x00 and Max_Data=0xFF).
+ */
+__STATIC_INLINE uint8_t LL_FMAC_GetX2Base(FMAC_TypeDef *FMACx)
+{
+ return (uint8_t)(READ_BIT(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BASE) >> FMAC_X2BUFCFG_X2_BASE_Pos);
+}
+
+/**
+ * @brief Configure Y empty watermark.
+ * @rmtoll YBUFCFG EMPTY_WM LL_FMAC_SetYEmptyWatermark
+ * @param FMACx FMAC instance
+ * @param Watermark This parameter can be one of the following values:
+ * @arg @ref LL_FMAC_WM_0_THRESHOLD_1
+ * @arg @ref LL_FMAC_WM_1_THRESHOLD_2
+ * @arg @ref LL_FMAC_WM_2_THRESHOLD_4
+ * @arg @ref LL_FMAC_WM_3_THRESHOLD_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_SetYEmptyWatermark(FMAC_TypeDef *FMACx, uint32_t Watermark)
+{
+ MODIFY_REG(FMACx->YBUFCFG, FMAC_YBUFCFG_EMPTY_WM, Watermark);
+}
+
+/**
+ * @brief Return Y empty watermark.
+ * @rmtoll YBUFCFG EMPTY_WM LL_FMAC_GetYEmptyWatermark
+ * @param FMACx FMAC instance
+ * @retval uint32_t Returned value can be one of the following values:
+ * @arg @ref LL_FMAC_WM_0_THRESHOLD_1
+ * @arg @ref LL_FMAC_WM_1_THRESHOLD_2
+ * @arg @ref LL_FMAC_WM_2_THRESHOLD_4
+ * @arg @ref LL_FMAC_WM_3_THRESHOLD_8
+ */
+__STATIC_INLINE uint32_t LL_FMAC_GetYEmptyWatermark(FMAC_TypeDef *FMACx)
+{
+ return (uint32_t)(READ_BIT(FMACx->YBUFCFG, FMAC_YBUFCFG_EMPTY_WM));
+}
+
+/**
+ * @brief Configure Y buffer size.
+ * @rmtoll YBUFCFG Y_BUF_SIZE LL_FMAC_SetYBufferSize
+ * @param FMACx FMAC instance
+ * @param BufferSize Number of 16-bit words allocated to the output buffer (including the optional "headroom").
+ * This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_SetYBufferSize(FMAC_TypeDef *FMACx, uint8_t BufferSize)
+{
+ MODIFY_REG(FMACx->YBUFCFG, FMAC_YBUFCFG_Y_BUF_SIZE, ((uint32_t)BufferSize) << FMAC_YBUFCFG_Y_BUF_SIZE_Pos);
+}
+
+/**
+ * @brief Return Y buffer size.
+ * @rmtoll YBUFCFG Y_BUF_SIZE LL_FMAC_GetYBufferSize
+ * @param FMACx FMAC instance
+ * @retval uint8_t Number of 16-bit words allocated to the output buffer
+ * (including the optional "headroom" - value between Min_Data=0x01 and Max_Data=0xFF).
+ */
+__STATIC_INLINE uint8_t LL_FMAC_GetYBufferSize(FMAC_TypeDef *FMACx)
+{
+ return (uint8_t)(READ_BIT(FMACx->YBUFCFG, FMAC_YBUFCFG_Y_BUF_SIZE) >> FMAC_YBUFCFG_Y_BUF_SIZE_Pos);
+}
+
+/**
+ * @brief Configure Y base.
+ * @rmtoll YBUFCFG Y_BASE LL_FMAC_SetYBase
+ * @param FMACx FMAC instance
+ * @param Base Base address of the output buffer (Y) within the internal memory.
+ * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_SetYBase(FMAC_TypeDef *FMACx, uint8_t Base)
+{
+ MODIFY_REG(FMACx->YBUFCFG, FMAC_YBUFCFG_Y_BASE, ((uint32_t)Base) << FMAC_YBUFCFG_Y_BASE_Pos);
+}
+
+/**
+ * @brief Return Y base.
+ * @rmtoll YBUFCFG Y_BASE LL_FMAC_GetYBase
+ * @param FMACx FMAC instance
+ * @retval uint8_t Base address of the output buffer (Y) within the internal memory
+ * (value between Min_Data=0x00 and Max_Data=0xFF).
+ */
+__STATIC_INLINE uint8_t LL_FMAC_GetYBase(FMAC_TypeDef *FMACx)
+{
+ return (uint8_t)(READ_BIT(FMACx->YBUFCFG, FMAC_YBUFCFG_Y_BASE) >> FMAC_YBUFCFG_Y_BASE_Pos);
+}
+
+/**
+ * @brief Start FMAC processing.
+ * @rmtoll PARAM START LL_FMAC_EnableStart
+ * @param FMACx FMAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_EnableStart(FMAC_TypeDef *FMACx)
+{
+ SET_BIT(FMACx->PARAM, FMAC_PARAM_START);
+}
+
+/**
+ * @brief Stop FMAC processing.
+ * @rmtoll PARAM START LL_FMAC_DisableStart
+ * @param FMACx FMAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_DisableStart(FMAC_TypeDef *FMACx)
+{
+ CLEAR_BIT(FMACx->PARAM, FMAC_PARAM_START);
+}
+
+/**
+ * @brief Check the state of FMAC processing.
+ * @rmtoll PARAM START LL_FMAC_IsEnabledStart
+ * @param FMACx FMAC instance
+ * @retval uint32_t State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMAC_IsEnabledStart(FMAC_TypeDef *FMACx)
+{
+ return ((READ_BIT(FMACx->PARAM, FMAC_PARAM_START) == (FMAC_PARAM_START)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure function.
+ * @rmtoll PARAM FUNC LL_FMAC_SetFunction
+ * @param FMACx FMAC instance
+ * @param Function This parameter can be one of the following values:
+ * @arg @ref LL_FMAC_FUNC_LOAD_X1
+ * @arg @ref LL_FMAC_FUNC_LOAD_X2
+ * @arg @ref LL_FMAC_FUNC_LOAD_Y
+ * @arg @ref LL_FMAC_FUNC_CONVO_FIR
+ * @arg @ref LL_FMAC_FUNC_IIR_DIRECT_FORM_1
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_SetFunction(FMAC_TypeDef *FMACx, uint32_t Function)
+{
+ MODIFY_REG(FMACx->PARAM, FMAC_PARAM_FUNC, Function);
+}
+
+/**
+ * @brief Return function.
+ * @rmtoll PARAM FUNC LL_FMAC_GetFunction
+ * @param FMACx FMAC instance
+ * @retval uint32_t Returned value can be one of the following values:
+ * @arg @ref LL_FMAC_FUNC_LOAD_X1
+ * @arg @ref LL_FMAC_FUNC_LOAD_X2
+ * @arg @ref LL_FMAC_FUNC_LOAD_Y
+ * @arg @ref LL_FMAC_FUNC_CONVO_FIR
+ * @arg @ref LL_FMAC_FUNC_IIR_DIRECT_FORM_1
+ */
+__STATIC_INLINE uint32_t LL_FMAC_GetFunction(FMAC_TypeDef *FMACx)
+{
+ return (uint32_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_FUNC));
+}
+
+/**
+ * @brief Configure input parameter R.
+ * @rmtoll PARAM R LL_FMAC_SetParamR
+ * @param FMACx FMAC instance
+ * @param Param Parameter R (gain, etc.).
+ * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_SetParamR(FMAC_TypeDef *FMACx, uint8_t Param)
+{
+ MODIFY_REG(FMACx->PARAM, FMAC_PARAM_R, ((uint32_t)Param) << FMAC_PARAM_R_Pos);
+}
+
+/**
+ * @brief Return input parameter R.
+ * @rmtoll PARAM R LL_FMAC_GetParamR
+ * @param FMACx FMAC instance
+ * @retval uint8_t Parameter R (gain, etc.) (value between Min_Data=0x00 and Max_Data=0xFF).
+ */
+__STATIC_INLINE uint8_t LL_FMAC_GetParamR(FMAC_TypeDef *FMACx)
+{
+ return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_R) >> FMAC_PARAM_R_Pos);
+}
+
+/**
+ * @brief Configure input parameter Q.
+ * @rmtoll PARAM Q LL_FMAC_SetParamQ
+ * @param FMACx FMAC instance
+ * @param Param Parameter Q (vector length, etc.).
+ * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_SetParamQ(FMAC_TypeDef *FMACx, uint8_t Param)
+{
+ MODIFY_REG(FMACx->PARAM, FMAC_PARAM_Q, ((uint32_t)Param) << FMAC_PARAM_Q_Pos);
+}
+
+/**
+ * @brief Return input parameter Q.
+ * @rmtoll PARAM Q LL_FMAC_GetParamQ
+ * @param FMACx FMAC instance
+ * @retval uint8_t Parameter Q (vector length, etc.) (value between Min_Data=0x00 and Max_Data=0xFF).
+ */
+__STATIC_INLINE uint8_t LL_FMAC_GetParamQ(FMAC_TypeDef *FMACx)
+{
+ return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_Q) >> FMAC_PARAM_Q_Pos);
+}
+
+/**
+ * @brief Configure input parameter P.
+ * @rmtoll PARAM P LL_FMAC_SetParamP
+ * @param FMACx FMAC instance
+ * @param Param Parameter P (vector length, number of filter taps, etc.).
+ * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_SetParamP(FMAC_TypeDef *FMACx, uint8_t Param)
+{
+ MODIFY_REG(FMACx->PARAM, FMAC_PARAM_P, ((uint32_t)Param));
+}
+
+/**
+ * @brief Return input parameter P.
+ * @rmtoll PARAM P LL_FMAC_GetParamP
+ * @param FMACx FMAC instance
+ * @retval uint8_t Parameter P (vector length, number of filter taps, etc.)
+ * (value between Min_Data=0x00 and Max_Data=0xFF).
+ */
+__STATIC_INLINE uint8_t LL_FMAC_GetParamP(FMAC_TypeDef *FMACx)
+{
+ return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_P));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_LL_EF_Reset_Management Reset_Management
+ * @{
+ */
+
+/**
+ * @brief Start the FMAC reset.
+ * @rmtoll CR RESET LL_FMAC_EnableReset
+ * @param FMACx FMAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_EnableReset(FMAC_TypeDef *FMACx)
+{
+ SET_BIT(FMACx->CR, FMAC_CR_RESET);
+}
+
+/**
+ * @brief Check the state of the FMAC reset.
+ * @rmtoll CR RESET LL_FMAC_IsEnabledReset
+ * @param FMACx FMAC instance
+ * @retval uint32_t State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMAC_IsEnabledReset(FMAC_TypeDef *FMACx)
+{
+ return ((READ_BIT(FMACx->CR, FMAC_CR_RESET) == (FMAC_CR_RESET)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_LL_EF_Configuration FMAC Configuration functions
+ * @{
+ */
+
+/**
+ * @brief Enable Clipping.
+ * @rmtoll CR CLIPEN LL_FMAC_EnableClipping
+ * @param FMACx FMAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_EnableClipping(FMAC_TypeDef *FMACx)
+{
+ SET_BIT(FMACx->CR, FMAC_CR_CLIPEN);
+}
+
+/**
+ * @brief Disable Clipping.
+ * @rmtoll CR CLIPEN LL_FMAC_DisableClipping
+ * @param FMACx FMAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_DisableClipping(FMAC_TypeDef *FMACx)
+{
+ CLEAR_BIT(FMACx->CR, FMAC_CR_CLIPEN);
+}
+
+/**
+ * @brief Check Clipping State.
+ * @rmtoll CR CLIPEN LL_FMAC_IsEnabledClipping
+ * @param FMACx FMAC instance
+ * @retval uint32_t State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMAC_IsEnabledClipping(FMAC_TypeDef *FMACx)
+{
+ return ((READ_BIT(FMACx->CR, FMAC_CR_CLIPEN) == (FMAC_CR_CLIPEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_LL_EF_DMA_Management DMA_Management
+ * @{
+ */
+
+/**
+ * @brief Enable FMAC DMA write channel request.
+ * @rmtoll CR DMAWEN LL_FMAC_EnableDMAReq_WRITE
+ * @param FMACx FMAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_EnableDMAReq_WRITE(FMAC_TypeDef *FMACx)
+{
+ SET_BIT(FMACx->CR, FMAC_CR_DMAWEN);
+}
+
+/**
+ * @brief Disable FMAC DMA write channel request.
+ * @rmtoll CR DMAWEN LL_FMAC_DisableDMAReq_WRITE
+ * @param FMACx FMAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_DisableDMAReq_WRITE(FMAC_TypeDef *FMACx)
+{
+ CLEAR_BIT(FMACx->CR, FMAC_CR_DMAWEN);
+}
+
+/**
+ * @brief Check FMAC DMA write channel request state.
+ * @rmtoll CR DMAWEN LL_FMAC_IsEnabledDMAReq_WRITE
+ * @param FMACx FMAC instance
+ * @retval uint32_t State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMAC_IsEnabledDMAReq_WRITE(FMAC_TypeDef *FMACx)
+{
+ return ((READ_BIT(FMACx->CR, FMAC_CR_DMAWEN) == (FMAC_CR_DMAWEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable FMAC DMA read channel request.
+ * @rmtoll CR DMAREN LL_FMAC_EnableDMAReq_READ
+ * @param FMACx FMAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_EnableDMAReq_READ(FMAC_TypeDef *FMACx)
+{
+ SET_BIT(FMACx->CR, FMAC_CR_DMAREN);
+}
+
+/**
+ * @brief Disable FMAC DMA read channel request.
+ * @rmtoll CR DMAREN LL_FMAC_DisableDMAReq_READ
+ * @param FMACx FMAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_DisableDMAReq_READ(FMAC_TypeDef *FMACx)
+{
+ CLEAR_BIT(FMACx->CR, FMAC_CR_DMAREN);
+}
+
+/**
+ * @brief Check FMAC DMA read channel request state.
+ * @rmtoll CR DMAREN LL_FMAC_IsEnabledDMAReq_READ
+ * @param FMACx FMAC instance
+ * @retval uint32_t State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMAC_IsEnabledDMAReq_READ(FMAC_TypeDef *FMACx)
+{
+ return ((READ_BIT(FMACx->CR, FMAC_CR_DMAREN) == (FMAC_CR_DMAREN)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable FMAC saturation error interrupt.
+ * @rmtoll CR SATIEN LL_FMAC_EnableIT_SAT
+ * @param FMACx FMAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_EnableIT_SAT(FMAC_TypeDef *FMACx)
+{
+ SET_BIT(FMACx->CR, FMAC_CR_SATIEN);
+}
+
+/**
+ * @brief Disable FMAC saturation error interrupt.
+ * @rmtoll CR SATIEN LL_FMAC_DisableIT_SAT
+ * @param FMACx FMAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_DisableIT_SAT(FMAC_TypeDef *FMACx)
+{
+ CLEAR_BIT(FMACx->CR, FMAC_CR_SATIEN);
+}
+
+/**
+ * @brief Check FMAC saturation error interrupt state.
+ * @rmtoll CR SATIEN LL_FMAC_IsEnabledIT_SAT
+ * @param FMACx FMAC instance
+ * @retval uint32_t State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_SAT(FMAC_TypeDef *FMACx)
+{
+ return ((READ_BIT(FMACx->CR, FMAC_CR_SATIEN) == (FMAC_CR_SATIEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable FMAC underflow error interrupt.
+ * @rmtoll CR UNFLIEN LL_FMAC_EnableIT_UNFL
+ * @param FMACx FMAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_EnableIT_UNFL(FMAC_TypeDef *FMACx)
+{
+ SET_BIT(FMACx->CR, FMAC_CR_UNFLIEN);
+}
+
+/**
+ * @brief Disable FMAC underflow error interrupt.
+ * @rmtoll CR UNFLIEN LL_FMAC_DisableIT_UNFL
+ * @param FMACx FMAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_DisableIT_UNFL(FMAC_TypeDef *FMACx)
+{
+ CLEAR_BIT(FMACx->CR, FMAC_CR_UNFLIEN);
+}
+
+/**
+ * @brief Check FMAC underflow error interrupt state.
+ * @rmtoll CR UNFLIEN LL_FMAC_IsEnabledIT_UNFL
+ * @param FMACx FMAC instance
+ * @retval uint32_t State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_UNFL(FMAC_TypeDef *FMACx)
+{
+ return ((READ_BIT(FMACx->CR, FMAC_CR_UNFLIEN) == (FMAC_CR_UNFLIEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable FMAC overflow error interrupt.
+ * @rmtoll CR OVFLIEN LL_FMAC_EnableIT_OVFL
+ * @param FMACx FMAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_EnableIT_OVFL(FMAC_TypeDef *FMACx)
+{
+ SET_BIT(FMACx->CR, FMAC_CR_OVFLIEN);
+}
+
+/**
+ * @brief Disable FMAC overflow error interrupt.
+ * @rmtoll CR OVFLIEN LL_FMAC_DisableIT_OVFL
+ * @param FMACx FMAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_DisableIT_OVFL(FMAC_TypeDef *FMACx)
+{
+ CLEAR_BIT(FMACx->CR, FMAC_CR_OVFLIEN);
+}
+
+/**
+ * @brief Check FMAC overflow error interrupt state.
+ * @rmtoll CR OVFLIEN LL_FMAC_IsEnabledIT_OVFL
+ * @param FMACx FMAC instance
+ * @retval uint32_t State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_OVFL(FMAC_TypeDef *FMACx)
+{
+ return ((READ_BIT(FMACx->CR, FMAC_CR_OVFLIEN) == (FMAC_CR_OVFLIEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable FMAC write interrupt.
+ * @rmtoll CR WIEN LL_FMAC_EnableIT_WR
+ * @param FMACx FMAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_EnableIT_WR(FMAC_TypeDef *FMACx)
+{
+ SET_BIT(FMACx->CR, FMAC_CR_WIEN);
+}
+
+/**
+ * @brief Disable FMAC write interrupt.
+ * @rmtoll CR WIEN LL_FMAC_DisableIT_WR
+ * @param FMACx FMAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_DisableIT_WR(FMAC_TypeDef *FMACx)
+{
+ CLEAR_BIT(FMACx->CR, FMAC_CR_WIEN);
+}
+
+/**
+ * @brief Check FMAC write interrupt state.
+ * @rmtoll CR WIEN LL_FMAC_IsEnabledIT_WR
+ * @param FMACx FMAC instance
+ * @retval uint32_t State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_WR(FMAC_TypeDef *FMACx)
+{
+ return ((READ_BIT(FMACx->CR, FMAC_CR_WIEN) == (FMAC_CR_WIEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable FMAC read interrupt.
+ * @rmtoll CR RIEN LL_FMAC_EnableIT_RD
+ * @param FMACx FMAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_EnableIT_RD(FMAC_TypeDef *FMACx)
+{
+ SET_BIT(FMACx->CR, FMAC_CR_RIEN);
+}
+
+/**
+ * @brief Disable FMAC read interrupt.
+ * @rmtoll CR RIEN LL_FMAC_DisableIT_RD
+ * @param FMACx FMAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_DisableIT_RD(FMAC_TypeDef *FMACx)
+{
+ CLEAR_BIT(FMACx->CR, FMAC_CR_RIEN);
+}
+
+/**
+ * @brief Check FMAC read interrupt state.
+ * @rmtoll CR RIEN LL_FMAC_IsEnabledIT_RD
+ * @param FMACx FMAC instance
+ * @retval uint32_t State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_RD(FMAC_TypeDef *FMACx)
+{
+ return ((READ_BIT(FMACx->CR, FMAC_CR_RIEN) == (FMAC_CR_RIEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Check FMAC saturation error flag state.
+ * @rmtoll SR SAT LL_FMAC_IsActiveFlag_SAT
+ * @param FMACx FMAC instance
+ * @retval uint32_t State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_SAT(FMAC_TypeDef *FMACx)
+{
+ return ((READ_BIT(FMACx->SR, FMAC_SR_SAT) == (FMAC_SR_SAT)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check FMAC underflow error flag state.
+ * @rmtoll SR UNFL LL_FMAC_IsActiveFlag_UNFL
+ * @param FMACx FMAC instance
+ * @retval uint32_t State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_UNFL(FMAC_TypeDef *FMACx)
+{
+ return ((READ_BIT(FMACx->SR, FMAC_SR_UNFL) == (FMAC_SR_UNFL)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check FMAC overflow error flag state.
+ * @rmtoll SR OVFL LL_FMAC_IsActiveFlag_OVFL
+ * @param FMACx FMAC instance
+ * @retval uint32_t State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_OVFL(FMAC_TypeDef *FMACx)
+{
+ return ((READ_BIT(FMACx->SR, FMAC_SR_OVFL) == (FMAC_SR_OVFL)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check FMAC X1 buffer full flag state.
+ * @rmtoll SR X1FULL LL_FMAC_IsActiveFlag_X1FULL
+ * @param FMACx FMAC instance
+ * @retval uint32_t State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_X1FULL(FMAC_TypeDef *FMACx)
+{
+ return ((READ_BIT(FMACx->SR, FMAC_SR_X1FULL) == (FMAC_SR_X1FULL)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check FMAC Y buffer empty flag state.
+ * @rmtoll SR YEMPTY LL_FMAC_IsActiveFlag_YEMPTY
+ * @param FMACx FMAC instance
+ * @retval uint32_t State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_YEMPTY(FMAC_TypeDef *FMACx)
+{
+ return ((READ_BIT(FMACx->SR, FMAC_SR_YEMPTY) == (FMAC_SR_YEMPTY)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_LL_EF_Data_Management Data_Management
+ * @{
+ */
+
+/**
+ * @brief Write 16-bit input data for the FMAC processing.
+ * @rmtoll WDATA WDATA LL_FMAC_WriteData
+ * @param FMACx FMAC instance
+ * @param InData 16-bit value to be provided as input data for FMAC processing.
+ * This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_WriteData(FMAC_TypeDef *FMACx, uint16_t InData)
+{
+ WRITE_REG(FMACx->WDATA, InData);
+}
+
+/**
+ * @brief Return 16-bit output data of FMAC processing.
+ * @rmtoll RDATA RDATA LL_FMAC_ReadData
+ * @param FMACx FMAC instance
+ * @retval uint16_t 16-bit output data of FMAC processing (value between Min_Data=0x0000 and Max_Data=0xFFFF).
+ */
+__STATIC_INLINE uint16_t LL_FMAC_ReadData(FMAC_TypeDef *FMACx)
+{
+ return (uint16_t)(READ_REG(FMACx->RDATA));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_LL_EF_Configuration FMAC Configuration functions
+ * @{
+ */
+
+/**
+ * @brief Configure memory for X1 buffer.
+ * @rmtoll X1BUFCFG FULL_WM LL_FMAC_ConfigX1\n
+ * X1BUFCFG X1_BASE LL_FMAC_ConfigX1\n
+ * X1BUFCFG X1_BUF_SIZE LL_FMAC_ConfigX1
+ * @param FMACx FMAC instance
+ * @param Watermark This parameter can be one of the following values:
+ * @arg @ref LL_FMAC_WM_0_THRESHOLD_1
+ * @arg @ref LL_FMAC_WM_1_THRESHOLD_2
+ * @arg @ref LL_FMAC_WM_2_THRESHOLD_4
+ * @arg @ref LL_FMAC_WM_3_THRESHOLD_8
+ * @param Base Base address of the input buffer (X1) within the internal memory.
+ * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
+ * @param BufferSize Number of 16-bit words allocated to the input buffer (including the optional "headroom").
+ * This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_ConfigX1(FMAC_TypeDef *FMACx, uint32_t Watermark, uint8_t Base, uint8_t BufferSize)
+{
+ MODIFY_REG(FMACx->X1BUFCFG, FMAC_X1BUFCFG_FULL_WM | FMAC_X1BUFCFG_X1_BASE | FMAC_X1BUFCFG_X1_BUF_SIZE,
+ Watermark | (((uint32_t)Base) << FMAC_X1BUFCFG_X1_BASE_Pos) |
+ (((uint32_t)BufferSize) << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos));
+}
+
+/**
+ * @brief Configure memory for X2 buffer.
+ * @rmtoll X2BUFCFG X2_BASE LL_FMAC_ConfigX2\n
+ * X2BUFCFG X2_BUF_SIZE LL_FMAC_ConfigX2
+ * @param FMACx FMAC instance
+ * @param Base Base address of the coefficient buffer (X2) within the internal memory.
+ * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
+ * @param BufferSize Number of 16-bit words allocated to the coefficient buffer.
+ * This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_ConfigX2(FMAC_TypeDef *FMACx, uint8_t Base, uint8_t BufferSize)
+{
+ MODIFY_REG(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BASE | FMAC_X2BUFCFG_X2_BUF_SIZE,
+ (((uint32_t)Base) << FMAC_X2BUFCFG_X2_BASE_Pos) |
+ (((uint32_t)BufferSize) << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos));
+}
+
+/**
+ * @brief Configure memory for Y buffer.
+ * @rmtoll YBUFCFG EMPTY_WM LL_FMAC_ConfigY\n
+ * YBUFCFG Y_BASE LL_FMAC_ConfigY\n
+ * YBUFCFG Y_BUF_SIZE LL_FMAC_ConfigY
+ * @param FMACx FMAC instance
+ * @param Watermark This parameter can be one of the following values:
+ * @arg @ref LL_FMAC_WM_0_THRESHOLD_1
+ * @arg @ref LL_FMAC_WM_1_THRESHOLD_2
+ * @arg @ref LL_FMAC_WM_2_THRESHOLD_4
+ * @arg @ref LL_FMAC_WM_3_THRESHOLD_8
+ * @param Base Base address of the output buffer (Y) within the internal memory.
+ * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
+ * @param BufferSize Number of 16-bit words allocated to the output buffer (including the optional "headroom").
+ * This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_ConfigY(FMAC_TypeDef *FMACx, uint32_t Watermark, uint8_t Base, uint8_t BufferSize)
+{
+ MODIFY_REG(FMACx->YBUFCFG, FMAC_YBUFCFG_EMPTY_WM | FMAC_YBUFCFG_Y_BASE | FMAC_YBUFCFG_Y_BUF_SIZE,
+ Watermark | (((uint32_t)Base) << FMAC_YBUFCFG_Y_BASE_Pos) |
+ (((uint32_t)BufferSize) << FMAC_YBUFCFG_Y_BUF_SIZE_Pos));
+}
+
+/**
+ * @brief Configure the FMAC processing.
+ * @rmtoll PARAM START LL_FMAC_ConfigFunc\n
+ * PARAM FUNC LL_FMAC_ConfigFunc\n
+ * PARAM P LL_FMAC_ConfigFunc\n
+ * PARAM Q LL_FMAC_ConfigFunc\n
+ * PARAM R LL_FMAC_ConfigFunc
+ * @param FMACx FMAC instance
+ * @param Start This parameter can be one of the following values:
+ * @arg @ref LL_FMAC_PROCESSING_STOP
+ * @arg @ref LL_FMAC_PROCESSING_START
+ * @param Function This parameter can be one of the following values:
+ * @arg @ref LL_FMAC_FUNC_LOAD_X1
+ * @arg @ref LL_FMAC_FUNC_LOAD_X2
+ * @arg @ref LL_FMAC_FUNC_LOAD_Y
+ * @arg @ref LL_FMAC_FUNC_CONVO_FIR
+ * @arg @ref LL_FMAC_FUNC_IIR_DIRECT_FORM_1
+ * @param ParamP Parameter P (vector length, number of filter taps, etc.).
+ * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
+ * @param ParamQ Parameter Q (vector length, etc.).
+ * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
+ * @param ParamR Parameter R (gain, etc.).
+ * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_ConfigFunc(FMAC_TypeDef *FMACx, uint8_t Start, uint32_t Function, uint8_t ParamP,
+ uint8_t ParamQ, uint8_t ParamR)
+{
+ MODIFY_REG(FMACx->PARAM, FMAC_PARAM_START | FMAC_PARAM_FUNC | FMAC_PARAM_P | FMAC_PARAM_Q | FMAC_PARAM_R,
+ (((uint32_t)Start) << FMAC_PARAM_START_Pos) | Function | (((uint32_t)ParamP) << FMAC_PARAM_P_Pos) |
+ (((uint32_t)ParamQ) << FMAC_PARAM_Q_Pos) | (((uint32_t)ParamR) << FMAC_PARAM_R_Pos));
+}
+
+/**
+ * @}
+ */
+
+
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup FMAC_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+ErrorStatus LL_FMAC_Init(FMAC_TypeDef *FMACx);
+ErrorStatus LL_FMAC_DeInit(FMAC_TypeDef *FMACx);
+
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(FMAC) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_LL_FMAC_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_fmc.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_fmc.h
new file mode 100644
index 00000000..5054924d
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_fmc.h
@@ -0,0 +1,831 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_fmc.h
+ * @author MCD Application Team
+ * @brief Header file of FMC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_LL_FMC_H
+#define STM32U5xx_LL_FMC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FMC_LL
+ * @{
+ */
+
+/** @addtogroup FMC_LL_Private_Macros
+ * @{
+ */
+
+#define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \
+ ((__BANK__) == FMC_NORSRAM_BANK2) || \
+ ((__BANK__) == FMC_NORSRAM_BANK3) || \
+ ((__BANK__) == FMC_NORSRAM_BANK4))
+#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
+ ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
+#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
+ ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
+ ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
+#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
+ ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
+ ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
+#define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \
+ ((__SIZE__) == FMC_PAGE_SIZE_128) || \
+ ((__SIZE__) == FMC_PAGE_SIZE_256) || \
+ ((__SIZE__) == FMC_PAGE_SIZE_512) || \
+ ((__SIZE__) == FMC_PAGE_SIZE_1024))
+#define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \
+ ((__FIFO__) == FMC_WRITE_FIFO_ENABLE))
+#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
+ ((__MODE__) == FMC_ACCESS_MODE_B) || \
+ ((__MODE__) == FMC_ACCESS_MODE_C) || \
+ ((__MODE__) == FMC_ACCESS_MODE_D))
+#define IS_FMC_NBL_SETUPTIME(__NBL__) (((__NBL__) == FMC_NBL_SETUPTIME_0) || \
+ ((__NBL__) == FMC_NBL_SETUPTIME_1) || \
+ ((__NBL__) == FMC_NBL_SETUPTIME_2) || \
+ ((__NBL__) == FMC_NBL_SETUPTIME_3))
+#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
+ ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
+#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
+ ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
+#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
+ ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
+#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
+ ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
+#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
+ ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
+#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
+ ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
+#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
+ ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
+#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
+#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
+ ((__BURST__) == FMC_WRITE_BURST_ENABLE))
+#define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
+ ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
+#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
+#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
+#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
+#define IS_FMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U)
+#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
+#define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U))
+#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
+#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
+#define IS_FMC_MAX_CHIP_SELECT_PULSE_TIME(__TIME__) (((__TIME__) >= 1U) && ((__TIME__) <= 65535U))
+
+
+#define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3)
+#define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \
+ ((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE))
+#define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \
+ ((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16))
+#define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \
+ ((__STATE__) == FMC_NAND_ECC_ENABLE))
+
+#define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
+ ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
+ ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
+ ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
+ ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
+ ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
+#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U)
+#define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U)
+#define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U)
+#define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U)
+#define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U)
+#define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U)
+#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
+
+
+/**
+ * @}
+ */
+
+/* Exported typedef ----------------------------------------------------------*/
+
+/** @defgroup FMC_LL_Exported_typedef FMC Low Layer Exported Types
+ * @{
+ */
+
+#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
+#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
+#define FMC_NAND_TypeDef FMC_Bank3_TypeDef
+
+#define FMC_NORSRAM_DEVICE FMC_Bank1_R
+#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E_R
+#define FMC_NAND_DEVICE FMC_Bank3_R
+
+/**
+ * @brief FMC NORSRAM Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
+ This parameter can be a value of @ref FMC_NORSRAM_Bank */
+
+ uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
+ multiplexed on the data bus or not.
+ This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
+
+ uint32_t MemoryType; /*!< Specifies the type of external memory attached to
+ the corresponding memory device.
+ This parameter can be a value of @ref FMC_Memory_Type */
+
+ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
+ This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
+
+ uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
+ valid only with synchronous burst Flash memories.
+ This parameter can be a value of @ref FMC_Burst_Access_Mode */
+
+ uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
+ the Flash memory in burst mode.
+ This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
+
+ uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
+ clock cycle before the wait state or during the wait state,
+ valid only when accessing memories in burst mode.
+ This parameter can be a value of @ref FMC_Wait_Timing */
+
+ uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
+ This parameter can be a value of @ref FMC_Write_Operation */
+
+ uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
+ signal, valid for Flash memory access in burst mode.
+ This parameter can be a value of @ref FMC_Wait_Signal */
+
+ uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
+ This parameter can be a value of @ref FMC_Extended_Mode */
+
+ uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
+ valid only with asynchronous Flash memories.
+ This parameter can be a value of @ref FMC_AsynchronousWait */
+
+ uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
+ This parameter can be a value of @ref FMC_Write_Burst */
+
+ uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
+ This parameter is only enabled through the FMC_BCR1 register,
+ and don't care through FMC_BCR2..4 registers.
+ This parameter can be a value of @ref FMC_Continous_Clock */
+
+ uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
+ This parameter is only enabled through the FMC_BCR1 register,
+ and don't care through FMC_BCR2..4 registers.
+ This parameter can be a value of @ref FMC_Write_FIFO */
+
+ uint32_t PageSize; /*!< Specifies the memory page size.
+ This parameter can be a value of @ref FMC_Page_Size */
+
+ uint32_t NBLSetupTime; /*!< Specifies the NBL setup timing clock cycle number
+ This parameter can be a value of @ref FMC_Byte_Lane */
+
+ FunctionalState MaxChipSelectPulse; /*!< Enables or disables the maximum chip select pulse management in this
+ NSBank for PSRAM refresh.
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t MaxChipSelectPulseTime; /*!< Specifies the maximum chip select pulse time in FMC_CLK cycles for
+ synchronous accesses and in HCLK cycles for asynchronous accesses,
+ valid only if MaxChipSelectPulse is ENABLE.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 65535.
+ @note: This parameter is common to all NSBank. */
+} FMC_NORSRAM_InitTypeDef;
+
+/**
+ * @brief FMC NORSRAM Timing parameters structure definition
+ */
+typedef struct
+{
+ uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the address setup time.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 15.
+ @note This parameter is not used with synchronous NOR Flash memories. */
+
+ uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the address hold time.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 15.
+ @note This parameter is not used with synchronous NOR Flash memories. */
+
+ uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the data setup time.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 255.
+ @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
+ NOR Flash memories. */
+
+ uint32_t DataHoldTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the data hold time.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 3.
+ @note This parameter is used for used in asynchronous accesses. */
+
+ uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
+ the duration of the bus turnaround.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 15.
+ @note This parameter is only used for multiplexed NOR Flash memories. */
+
+ uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
+ HCLK cycles. This parameter can be a value between Min_Data = 2 and
+ Max_Data = 16.
+ @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
+ accesses. */
+
+ uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
+ to the memory before getting the first data.
+ The parameter value depends on the memory type as shown below:
+ - It must be set to 0 in case of a CRAM
+ - It is don't care in asynchronous NOR, SRAM or ROM accesses
+ - It may assume a value between Min_Data = 2 and Max_Data = 17
+ in NOR Flash memories with synchronous burst mode enable */
+
+ uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
+ This parameter can be a value of @ref FMC_Access_Mode */
+} FMC_NORSRAM_TimingTypeDef;
+
+/**
+ * @brief FMC NAND Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
+ This parameter can be a value of @ref FMC_NAND_Bank */
+
+ uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
+ This parameter can be any value of @ref FMC_Wait_feature */
+
+ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
+ This parameter can be any value of @ref FMC_NAND_Data_Width */
+
+ uint32_t EccComputation; /*!< Enables or disables the ECC computation.
+ This parameter can be any value of @ref FMC_ECC */
+
+ uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
+ This parameter can be any value of @ref FMC_ECC_Page_Size */
+
+ uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between CLE low and RE low.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between ALE low and RE low.
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+} FMC_NAND_InitTypeDef;
+
+/**
+ * @brief FMC NAND Timing parameters structure definition
+ */
+typedef struct
+{
+ uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
+ the command assertion for NAND-Flash read or write access
+ to common/Attribute or I/O memory space (depending on
+ the memory space timing to be configured).
+ This parameter can be a value between Min_Data = 0 and Max_Data = 254 */
+
+ uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
+ command for NAND-Flash read or write access to
+ common/Attribute or I/O memory space (depending on the
+ memory space timing to be configured).
+ This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
+
+ uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
+ (and data for write access) after the command de-assertion
+ for NAND-Flash read or write access to common/Attribute
+ or I/O memory space (depending on the memory space timing
+ to be configured).
+ This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
+
+ uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
+ data bus is kept in HiZ after the start of a NAND-Flash
+ write access to common/Attribute or I/O memory space (depending
+ on the memory space timing to be configured).
+ This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
+} FMC_NAND_PCC_TimingTypeDef;
+
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants
+ * @{
+ */
+
+/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
+ * @{
+ */
+
+/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
+ * @{
+ */
+#define FMC_NORSRAM_BANK1 (0x00000000U)
+#define FMC_NORSRAM_BANK2 (0x00000002U)
+#define FMC_NORSRAM_BANK3 (0x00000004U)
+#define FMC_NORSRAM_BANK4 (0x00000006U)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
+ * @{
+ */
+#define FMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U)
+#define FMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Memory_Type FMC Memory Type
+ * @{
+ */
+#define FMC_MEMORY_TYPE_SRAM (0x00000000U)
+#define FMC_MEMORY_TYPE_PSRAM (0x00000004U)
+#define FMC_MEMORY_TYPE_NOR (0x00000008U)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
+ * @{
+ */
+#define FMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U)
+#define FMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U)
+#define FMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
+ * @{
+ */
+#define FMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U)
+#define FMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
+ * @{
+ */
+#define FMC_BURST_ACCESS_MODE_DISABLE (0x00000000U)
+#define FMC_BURST_ACCESS_MODE_ENABLE (0x00000100U)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
+ * @{
+ */
+#define FMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U)
+#define FMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Wait_Timing FMC Wait Timing
+ * @{
+ */
+#define FMC_WAIT_TIMING_BEFORE_WS (0x00000000U)
+#define FMC_WAIT_TIMING_DURING_WS (0x00000800U)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Write_Operation FMC Write Operation
+ * @{
+ */
+#define FMC_WRITE_OPERATION_DISABLE (0x00000000U)
+#define FMC_WRITE_OPERATION_ENABLE (0x00001000U)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Wait_Signal FMC Wait Signal
+ * @{
+ */
+#define FMC_WAIT_SIGNAL_DISABLE (0x00000000U)
+#define FMC_WAIT_SIGNAL_ENABLE (0x00002000U)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Extended_Mode FMC Extended Mode
+ * @{
+ */
+#define FMC_EXTENDED_MODE_DISABLE (0x00000000U)
+#define FMC_EXTENDED_MODE_ENABLE (0x00004000U)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
+ * @{
+ */
+#define FMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U)
+#define FMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Page_Size FMC Page Size
+ * @{
+ */
+#define FMC_PAGE_SIZE_NONE (0x00000000U)
+#define FMC_PAGE_SIZE_128 FMC_BCRx_CPSIZE_0
+#define FMC_PAGE_SIZE_256 FMC_BCRx_CPSIZE_1
+#define FMC_PAGE_SIZE_512 (FMC_BCRx_CPSIZE_0\
+ | FMC_BCRx_CPSIZE_1)
+#define FMC_PAGE_SIZE_1024 FMC_BCRx_CPSIZE_2
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Write_Burst FMC Write Burst
+ * @{
+ */
+#define FMC_WRITE_BURST_DISABLE (0x00000000U)
+#define FMC_WRITE_BURST_ENABLE (0x00080000U)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Continous_Clock FMC Continuous Clock
+ * @{
+ */
+#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U)
+#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Write_FIFO FMC Write FIFO
+ * @{
+ */
+#define FMC_WRITE_FIFO_DISABLE FMC_BCR1_WFDIS
+#define FMC_WRITE_FIFO_ENABLE (0x00000000U)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Access_Mode FMC Access Mode
+ * @{
+ */
+#define FMC_ACCESS_MODE_A (0x00000000U)
+#define FMC_ACCESS_MODE_B (0x10000000U)
+#define FMC_ACCESS_MODE_C (0x20000000U)
+#define FMC_ACCESS_MODE_D (0x30000000U)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Byte_Lane FMC Byte Lane(NBL) Setup
+ * @{
+ */
+#define FMC_NBL_SETUPTIME_0 (0x00000000U)
+#define FMC_NBL_SETUPTIME_1 (0x00400000U)
+#define FMC_NBL_SETUPTIME_2 (0x00800000U)
+#define FMC_NBL_SETUPTIME_3 (0x00C00000U)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
+ * @{
+ */
+/** @defgroup FMC_NAND_Bank FMC NAND Bank
+ * @{
+ */
+#define FMC_NAND_BANK3 (0x00000100U)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Wait_feature FMC Wait feature
+ * @{
+ */
+#define FMC_NAND_WAIT_FEATURE_DISABLE (0x00000000U)
+#define FMC_NAND_WAIT_FEATURE_ENABLE (0x00000002U)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
+ * @{
+ */
+#define FMC_PCR_MEMORY_TYPE_NAND (0x00000008U)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
+ * @{
+ */
+#define FMC_NAND_MEM_BUS_WIDTH_8 (0x00000000U)
+#define FMC_NAND_MEM_BUS_WIDTH_16 (0x00000010U)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_ECC FMC ECC
+ * @{
+ */
+#define FMC_NAND_ECC_DISABLE (0x00000000U)
+#define FMC_NAND_ECC_ENABLE (0x00000040U)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
+ * @{
+ */
+#define FMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U)
+#define FMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U)
+#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U)
+#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U)
+#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U)
+#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition
+ * @{
+ */
+#define FMC_IT_RISING_EDGE (0x00000008U)
+#define FMC_IT_LEVEL (0x00000010U)
+#define FMC_IT_FALLING_EDGE (0x00000020U)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition
+ * @{
+ */
+#define FMC_FLAG_RISING_EDGE (0x00000001U)
+#define FMC_FLAG_LEVEL (0x00000002U)
+#define FMC_FLAG_FALLING_EDGE (0x00000004U)
+#define FMC_FLAG_FEMPT (0x00000040U)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros
+ * @{
+ */
+/**
+ * @brief Enable the FMC Peripheral.
+ * @retval None
+ */
+#define __FMC_ENABLE() (FMC_Bank1_R->BTCR[0] |= FMC_BCR1_FMCEN)
+
+/**
+ * @brief Disable the FMC Peripheral.
+ * @retval None
+ */
+#define __FMC_DISABLE() (FMC_Bank1_R->BTCR[0] &= ~FMC_BCR1_FMCEN)
+/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
+ * @brief macros to handle NOR device enable/disable and read/write operations
+ * @{
+ */
+
+/**
+ * @brief Enable the NORSRAM device access.
+ * @param __INSTANCE__ FMC_NORSRAM Instance
+ * @param __BANK__ FMC_NORSRAM Bank
+ * @retval None
+ */
+#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
+ |= FMC_BCRx_MBKEN)
+
+/**
+ * @brief Disable the NORSRAM device access.
+ * @param __INSTANCE__ FMC_NORSRAM Instance
+ * @param __BANK__ FMC_NORSRAM Bank
+ * @retval None
+ */
+#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
+ &= ~FMC_BCRx_MBKEN)
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
+ * @brief macros to handle NAND device enable/disable
+ * @{
+ */
+
+/**
+ * @brief Enable the NAND device access.
+ * @param __INSTANCE__ FMC_NAND Instance
+ * @retval None
+ */
+#define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN)
+
+/**
+ * @brief Disable the NAND device access.
+ * @param __INSTANCE__ FMC_NAND Instance
+ * @param __BANK__ FMC_NAND Bank
+ * @retval None
+ */
+#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN)
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_LL_NAND_Interrupt FMC NAND Interrupt
+ * @brief macros to handle NAND interrupts
+ * @{
+ */
+
+/**
+ * @brief Enable the NAND device interrupt.
+ * @param __INSTANCE__ FMC_NAND instance
+ * @param __INTERRUPT__ FMC_NAND interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FMC_IT_LEVEL: Interrupt level.
+ * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @retval None
+ */
+#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the NAND device interrupt.
+ * @param __INSTANCE__ FMC_NAND Instance
+ * @param __INTERRUPT__ FMC_NAND interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FMC_IT_LEVEL: Interrupt level.
+ * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @retval None
+ */
+#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Get flag status of the NAND device.
+ * @param __INSTANCE__ FMC_NAND Instance
+ * @param __BANK__ FMC_NAND Bank
+ * @param __FLAG__ FMC_NAND flag
+ * This parameter can be any combination of the following values:
+ * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FMC_FLAG_FEMPT: FIFO empty flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clear flag status of the NAND device.
+ * @param __INSTANCE__ FMC_NAND Instance
+ * @param __FLAG__ FMC_NAND flag
+ * This parameter can be any combination of the following values:
+ * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FMC_FLAG_FEMPT: FIFO empty flag.
+ * @retval None
+ */
+#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
+ * @{
+ */
+
+/** @defgroup FMC_LL_NORSRAM NOR SRAM
+ * @{
+ */
+/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
+ FMC_NORSRAM_InitTypeDef *Init);
+HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
+ FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
+ FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
+ uint32_t ExtendedMode);
+HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
+ FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
+/**
+ * @}
+ */
+
+/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
+ * @{
+ */
+HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/** @defgroup FMC_LL_NAND NAND
+ * @{
+ */
+/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
+HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
+ FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
+ FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
+/**
+ * @}
+ */
+
+/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
+ * @{
+ */
+HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
+ uint32_t Timeout);
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_LL_FMC_H */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_gpio.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_gpio.h
new file mode 100644
index 00000000..d19a9861
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_gpio.h
@@ -0,0 +1,1178 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_gpio.h
+ * @author MCD Application Team
+ * @brief Header file of GPIO LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_LL_GPIO_H
+#define STM32U5xx_LL_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx.h"
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || \
+ defined (GPIOG) || defined (GPIOH) || defined (GPIOI)
+
+/** @defgroup GPIO_LL GPIO
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
+ * @{
+ */
+
+/**
+ * @brief LL GPIO Init Structure definition
+ */
+typedef struct
+{
+ uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
+ This parameter can be any value of @ref GPIO_LL_EC_PIN */
+
+ uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref GPIO_LL_EC_MODE.
+
+ GPIO HW configuration can be modified afterwards using unitary function
+ @ref LL_GPIO_SetPinMode().*/
+
+ uint32_t Speed; /*!< Specifies the speed for the selected pins.
+ This parameter can be a value of @ref GPIO_LL_EC_SPEED.
+
+ GPIO HW configuration can be modified afterwards using unitary function
+ @ref LL_GPIO_SetPinSpeed().*/
+
+ uint32_t OutputType; /*!< Specifies the operating output type for the selected pins.
+ This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
+
+ GPIO HW configuration can be modified afterwards using unitary function
+ @ref LL_GPIO_SetPinOutputType().*/
+
+ uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
+ This parameter can be a value of @ref GPIO_LL_EC_PULL.
+
+ GPIO HW configuration can be modified afterwards using unitary function
+ @ref LL_GPIO_SetPinPull().*/
+
+ uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins.
+ This parameter can be a value of @ref GPIO_LL_EC_AF.
+
+ GPIO HW configuration can be modified afterwards using unitary function
+ @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/
+} LL_GPIO_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
+ * @{
+ */
+
+/** @defgroup GPIO_LL_EC_PIN PIN
+ * @{
+ */
+#define LL_GPIO_PIN_0 GPIO_BSRR_BS0 /*!< Select pin 0 */
+#define LL_GPIO_PIN_1 GPIO_BSRR_BS1 /*!< Select pin 1 */
+#define LL_GPIO_PIN_2 GPIO_BSRR_BS2 /*!< Select pin 2 */
+#define LL_GPIO_PIN_3 GPIO_BSRR_BS3 /*!< Select pin 3 */
+#define LL_GPIO_PIN_4 GPIO_BSRR_BS4 /*!< Select pin 4 */
+#define LL_GPIO_PIN_5 GPIO_BSRR_BS5 /*!< Select pin 5 */
+#define LL_GPIO_PIN_6 GPIO_BSRR_BS6 /*!< Select pin 6 */
+#define LL_GPIO_PIN_7 GPIO_BSRR_BS7 /*!< Select pin 7 */
+#define LL_GPIO_PIN_8 GPIO_BSRR_BS8 /*!< Select pin 8 */
+#define LL_GPIO_PIN_9 GPIO_BSRR_BS9 /*!< Select pin 9 */
+#define LL_GPIO_PIN_10 GPIO_BSRR_BS10 /*!< Select pin 10 */
+#define LL_GPIO_PIN_11 GPIO_BSRR_BS11 /*!< Select pin 11 */
+#define LL_GPIO_PIN_12 GPIO_BSRR_BS12 /*!< Select pin 12 */
+#define LL_GPIO_PIN_13 GPIO_BSRR_BS13 /*!< Select pin 13 */
+#define LL_GPIO_PIN_14 GPIO_BSRR_BS14 /*!< Select pin 14 */
+#define LL_GPIO_PIN_15 GPIO_BSRR_BS15 /*!< Select pin 15 */
+#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS0 | GPIO_BSRR_BS1 | GPIO_BSRR_BS2 | \
+ GPIO_BSRR_BS3 | GPIO_BSRR_BS4 | GPIO_BSRR_BS5 | \
+ GPIO_BSRR_BS6 | GPIO_BSRR_BS7 | GPIO_BSRR_BS8 | \
+ GPIO_BSRR_BS9 | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \
+ GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \
+ GPIO_BSRR_BS15) /*!< Select all pins */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EC_MODE Mode
+ * @{
+ */
+#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */
+#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0 /*!< Select output mode */
+#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODE0_1 /*!< Select alternate function mode */
+#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0 /*!< Select analog mode */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EC_OUTPUT Output Type
+ * @{
+ */
+#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */
+#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT0 /*!< Select open-drain as output type */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EC_SPEED Output Speed
+ * @{
+ */
+#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */
+#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEED0_0 /*!< Select I/O medium output speed */
+#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEED0_1 /*!< Select I/O fast output speed */
+#define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDR_OSPEED0 /*!< Select I/O high output speed */
+/**
+ * @}
+ */
+#define LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW
+#define LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM
+#define LL_GPIO_SPEED_FAST LL_GPIO_SPEED_FREQ_HIGH
+#define LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_VERY_HIGH
+
+/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
+ * @{
+ */
+#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */
+#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */
+#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EC_AF Alternate Function
+ * @{
+ */
+#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */
+#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */
+#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */
+#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */
+#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */
+#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */
+#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */
+#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */
+#define LL_GPIO_AF_8 (0x0000008U) /*!< Select alternate function 8 */
+#define LL_GPIO_AF_9 (0x0000009U) /*!< Select alternate function 9 */
+#define LL_GPIO_AF_10 (0x000000AU) /*!< Select alternate function 10 */
+#define LL_GPIO_AF_11 (0x000000BU) /*!< Select alternate function 11 */
+#define LL_GPIO_AF_12 (0x000000CU) /*!< Select alternate function 12 */
+#define LL_GPIO_AF_13 (0x000000DU) /*!< Select alternate function 13 */
+#define LL_GPIO_AF_14 (0x000000EU) /*!< Select alternate function 14 */
+#define LL_GPIO_AF_15 (0x000000FU) /*!< Select alternate function 15 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
+ * @{
+ */
+
+/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in GPIO register
+ * @param __INSTANCE__ GPIO Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in GPIO register
+ * @param __INSTANCE__ GPIO Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
+ * @{
+ */
+
+/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
+ * @{
+ */
+
+/**
+ * @brief Configure gpio mode for a dedicated pin on dedicated port.
+ * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll MODER MODEy LL_GPIO_SetPinMode
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_MODE_INPUT
+ * @arg @ref LL_GPIO_MODE_OUTPUT
+ * @arg @ref LL_GPIO_MODE_ALTERNATE
+ * @arg @ref LL_GPIO_MODE_ANALOG
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
+{
+ MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));
+}
+
+/**
+ * @brief Return gpio mode for a dedicated pin on dedicated port.
+ * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll MODER MODEy LL_GPIO_GetPinMode
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_MODE_INPUT
+ * @arg @ref LL_GPIO_MODE_OUTPUT
+ * @arg @ref LL_GPIO_MODE_ALTERNATE
+ * @arg @ref LL_GPIO_MODE_ANALOG
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+ return (uint32_t)(READ_BIT(GPIOx->MODER,
+ (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
+}
+
+/**
+ * @brief Configure gpio output type for several pins on dedicated port.
+ * @note Output type as to be set when gpio pin is in output or
+ * alternate modes. Possible type are Push-pull or Open-drain.
+ * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @param OutputType This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_OUTPUT_PUSHPULL
+ * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
+{
+ MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
+}
+
+/**
+ * @brief Return gpio output type for several pins on dedicated port.
+ * @note Output type as to be set when gpio pin is in output or
+ * alternate modes. Possible type are Push-pull or Open-drain.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_OUTPUT_PUSHPULL
+ * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+ return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin));
+}
+
+/**
+ * @brief Configure gpio speed for a dedicated pin on dedicated port.
+ * @note I/O speed can be Low, Medium, Fast or High speed.
+ * @note Warning: only one pin can be passed as parameter.
+ * @note Refer to datasheet for frequency specifications and the power
+ * supply and load conditions for each speed.
+ * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @param Speed This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_SPEED_FREQ_LOW
+ * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
+ * @arg @ref LL_GPIO_SPEED_FREQ_HIGH
+ * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
+{
+ MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * 2U)),
+ (Speed << (POSITION_VAL(Pin) * 2U)));
+}
+
+/**
+ * @brief Return gpio speed for a dedicated pin on dedicated port.
+ * @note I/O speed can be Low, Medium, Fast or High speed.
+ * @note Warning: only one pin can be passed as parameter.
+ * @note Refer to datasheet for frequency specifications and the power
+ * supply and load conditions for each speed.
+ * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_SPEED_FREQ_LOW
+ * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
+ * @arg @ref LL_GPIO_SPEED_FREQ_HIGH
+ * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+ return (uint32_t)(READ_BIT(GPIOx->OSPEEDR,
+ (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
+}
+
+/**
+ * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @param Pull This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PULL_NO
+ * @arg @ref LL_GPIO_PULL_UP
+ * @arg @ref LL_GPIO_PULL_DOWN
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
+{
+ MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U)));
+}
+
+/**
+ * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_PULL_NO
+ * @arg @ref LL_GPIO_PULL_UP
+ * @arg @ref LL_GPIO_PULL_DOWN
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+ return (uint32_t)(READ_BIT(GPIOx->PUPDR,
+ (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
+}
+
+/**
+ * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
+ * @note Possible values are from AF0 to AF15 depending on target.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @param Alternate This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_AF_0
+ * @arg @ref LL_GPIO_AF_1
+ * @arg @ref LL_GPIO_AF_2
+ * @arg @ref LL_GPIO_AF_3
+ * @arg @ref LL_GPIO_AF_4
+ * @arg @ref LL_GPIO_AF_5
+ * @arg @ref LL_GPIO_AF_6
+ * @arg @ref LL_GPIO_AF_7
+ * @arg @ref LL_GPIO_AF_8
+ * @arg @ref LL_GPIO_AF_9
+ * @arg @ref LL_GPIO_AF_10
+ * @arg @ref LL_GPIO_AF_11
+ * @arg @ref LL_GPIO_AF_12
+ * @arg @ref LL_GPIO_AF_13
+ * @arg @ref LL_GPIO_AF_14
+ * @arg @ref LL_GPIO_AF_15
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
+{
+ MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U)),
+ (Alternate << (POSITION_VAL(Pin) * 4U)));
+}
+
+/**
+ * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
+ * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_AF_0
+ * @arg @ref LL_GPIO_AF_1
+ * @arg @ref LL_GPIO_AF_2
+ * @arg @ref LL_GPIO_AF_3
+ * @arg @ref LL_GPIO_AF_4
+ * @arg @ref LL_GPIO_AF_5
+ * @arg @ref LL_GPIO_AF_6
+ * @arg @ref LL_GPIO_AF_7
+ * @arg @ref LL_GPIO_AF_8
+ * @arg @ref LL_GPIO_AF_9
+ * @arg @ref LL_GPIO_AF_10
+ * @arg @ref LL_GPIO_AF_11
+ * @arg @ref LL_GPIO_AF_12
+ * @arg @ref LL_GPIO_AF_13
+ * @arg @ref LL_GPIO_AF_14
+ * @arg @ref LL_GPIO_AF_15
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+ return (uint32_t)(READ_BIT(GPIOx->AFR[0],
+ (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
+}
+
+/**
+ * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
+ * @note Possible values are from AF0 to AF15 depending on target.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @param Alternate This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_AF_0
+ * @arg @ref LL_GPIO_AF_1
+ * @arg @ref LL_GPIO_AF_2
+ * @arg @ref LL_GPIO_AF_3
+ * @arg @ref LL_GPIO_AF_4
+ * @arg @ref LL_GPIO_AF_5
+ * @arg @ref LL_GPIO_AF_6
+ * @arg @ref LL_GPIO_AF_7
+ * @arg @ref LL_GPIO_AF_8
+ * @arg @ref LL_GPIO_AF_9
+ * @arg @ref LL_GPIO_AF_10
+ * @arg @ref LL_GPIO_AF_11
+ * @arg @ref LL_GPIO_AF_12
+ * @arg @ref LL_GPIO_AF_13
+ * @arg @ref LL_GPIO_AF_14
+ * @arg @ref LL_GPIO_AF_15
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
+{
+ MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U)),
+ (Alternate << (POSITION_VAL(Pin >> 8U) * 4U)));
+}
+
+/**
+ * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
+ * @note Possible values are from AF0 to AF15 depending on target.
+ * @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_AF_0
+ * @arg @ref LL_GPIO_AF_1
+ * @arg @ref LL_GPIO_AF_2
+ * @arg @ref LL_GPIO_AF_3
+ * @arg @ref LL_GPIO_AF_4
+ * @arg @ref LL_GPIO_AF_5
+ * @arg @ref LL_GPIO_AF_6
+ * @arg @ref LL_GPIO_AF_7
+ * @arg @ref LL_GPIO_AF_8
+ * @arg @ref LL_GPIO_AF_9
+ * @arg @ref LL_GPIO_AF_10
+ * @arg @ref LL_GPIO_AF_11
+ * @arg @ref LL_GPIO_AF_12
+ * @arg @ref LL_GPIO_AF_13
+ * @arg @ref LL_GPIO_AF_14
+ * @arg @ref LL_GPIO_AF_15
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+ return (uint32_t)(READ_BIT(GPIOx->AFR[1],
+ (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U));
+}
+
+/**
+ * @brief Lock configuration of several pins for a dedicated port.
+ * @note When the lock sequence has been applied on a port bit, the
+ * value of this port bit can no longer be modified until the
+ * next reset.
+ * @note Each lock bit freezes a specific configuration register
+ * (control and alternate function registers).
+ * @rmtoll LCKR LCKK LL_GPIO_LockPin
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ __IO uint32_t temp;
+ WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
+ WRITE_REG(GPIOx->LCKR, PinMask);
+ WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
+ /* Read LCKK register. This read is mandatory to complete key lock sequence */
+ temp = READ_REG(GPIOx->LCKR);
+ (void) temp;
+}
+
+/**
+ * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
+ * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0.
+ * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked
+ * @param GPIOx GPIO Port
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
+{
+ return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EF_Data_Access Data Access
+ * @{
+ */
+
+/**
+ * @brief Return full input data register value for a dedicated port.
+ * @rmtoll IDR IDy LL_GPIO_ReadInputPort
+ * @param GPIOx GPIO Port
+ * @retval Input data register value of port
+ */
+__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
+{
+ return (uint32_t)(READ_REG(GPIOx->IDR));
+}
+
+/**
+ * @brief Return if input data level for several pins of dedicated port is high or low.
+ * @rmtoll IDR IDy LL_GPIO_IsInputPinSet
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Write output data register for the port.
+ * @rmtoll ODR ODy LL_GPIO_WriteOutputPort
+ * @param GPIOx GPIO Port
+ * @param PortValue Level value for each pin of the port
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
+{
+ WRITE_REG(GPIOx->ODR, PortValue);
+}
+
+/**
+ * @brief Return full output data register value for a dedicated port.
+ * @rmtoll ODR ODy LL_GPIO_ReadOutputPort
+ * @param GPIOx GPIO Port
+ * @retval Output data register value of port
+ */
+__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
+{
+ return (uint32_t)(READ_REG(GPIOx->ODR));
+}
+
+/**
+ * @brief Return if input data level for several pins of dedicated port is high or low.
+ * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set several pins to high level on dedicated gpio port.
+ * @rmtoll BSRR BSy LL_GPIO_SetOutputPin
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ WRITE_REG(GPIOx->BSRR, PinMask);
+}
+
+/**
+ * @brief Set several pins to low level on dedicated gpio port.
+ * @rmtoll BRR BRy LL_GPIO_ResetOutputPin
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ WRITE_REG(GPIOx->BRR, PinMask);
+}
+
+/**
+ * @brief Toggle data value for several pin of dedicated port.
+ * @rmtoll ODR ODy LL_GPIO_TogglePin
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ uint32_t odr = READ_REG(GPIOx->ODR);
+ WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask));
+}
+
+/**
+ * @brief Enable speed optimization for several pin of dedicated port.
+ * @note Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding
+ * datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must
+ * be kept at reset value.
+ * @note It must be used only if the I/O supply voltage is below 2.7 V.
+ * @rmtoll HSLVR HSLVy LL_GPIO_EnableHighSPeedLowVoltage
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_EnableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ SET_BIT(GPIOx->HSLVR, PinMask);
+}
+
+
+/**
+ * @brief Disable speed optimization for several pin of dedicated port.
+ * @note Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding
+ * datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must
+ * be kept at reset value.
+ * @note It must be used only if the I/O supply voltage is below 2.7 V.
+ * @rmtoll HSLVR HSLVy LL_GPIO_DisableHighSPeedLowVoltage
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_DisableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ CLEAR_BIT(GPIOx->HSLVR, PinMask);
+}
+
+/**
+ * @brief Return if speed optimization for several pin of dedicated port is enabled or not.
+ * @note Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding
+ * datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must
+ * be kept at reset value.
+ * @note It must be used only if the I/O supply voltage is below 2.7 V.
+ * @rmtoll HSLVR HSLVy LL_GPIO_IsEnabledHighSPeedLowVoltage
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_IsEnabledHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ return ((READ_BIT(GPIOx->HSLVR, PinMask) == (PinMask)) ? 1UL : 0UL);
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ * @brief Enable secure write only access for several pin of dedicated port.
+ * @rmtoll SECCFGR SECy LL_GPIO_EnablePinSecure
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_EnablePinSecure(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ SET_BIT(GPIOx->SECCFGR, PinMask);
+}
+
+
+/**
+ * @brief Disable secure write only access for several pin of dedicated port.
+ * @rmtoll SECCFGR SECy LL_GPIO_DisablePinSecure
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_DisablePinSecure(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ CLEAR_BIT(GPIOx->SECCFGR, PinMask);
+}
+
+#endif /* __ARM_FEATURE_CMSE */
+
+/**
+ * @brief Return if secure write only access for several pin of dedicated port is enabled or not.
+ * @rmtoll SECCFGR SECy LL_GPIO_IsEnabledPinSecure
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_IsEnabledPinSecure(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ return ((READ_BIT(GPIOx->SECCFGR, PinMask) == (PinMask)) ? 1UL : 0UL);
+}
+
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
+ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
+void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || \
+ defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) */
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_LL_GPIO_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_i2c.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_i2c.h
new file mode 100644
index 00000000..d90701e8
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_i2c.h
@@ -0,0 +1,2518 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_i2c.h
+ * @author MCD Application Team
+ * @brief Header file of I2C LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_LL_I2C_H
+#define STM32U5xx_LL_I2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx.h"
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4)
+
+/** @defgroup I2C_LL I2C
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2C_LL_Private_Constants I2C Private Constants
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2C_LL_Private_Macros I2C Private Macros
+ * @{
+ */
+#define IS_LL_I2C_GRP1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) ||\
+ ((__INSTANCE__) == I2C2) ||\
+ ((__INSTANCE__) == I2C4))
+
+#define IS_LL_I2C_GRP2_INSTANCE(__INSTANCE__) ((__INSTANCE__) == I2C3)
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
+ * @{
+ */
+typedef struct
+{
+ uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
+ This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_I2C_SetMode(). */
+
+ uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
+ This parameter must be set by referring to the STM32CubeMX Tool and
+ the helper macro @ref __LL_I2C_CONVERT_TIMINGS()
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_I2C_SetTiming(). */
+
+ uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
+ This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION
+
+ This feature can be modified afterwards using unitary functions
+ @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
+
+ uint32_t DigitalFilter; /*!< Configures the digital noise filter.
+ This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_I2C_SetDigitalFilter(). */
+
+ uint32_t OwnAddress1; /*!< Specifies the device own address 1.
+ This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_I2C_SetOwnAddress1(). */
+
+ uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive
+ match code or next received byte.
+ This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_I2C_AcknowledgeNextData(). */
+
+ uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
+ This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_I2C_SetOwnAddress1(). */
+} LL_I2C_InitTypeDef;
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
+ * @{
+ */
+
+/** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
+ * @brief Flags defines which can be used with LL_I2C_WriteReg function
+ * @{
+ */
+#define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF /*!< Address Matched flag */
+#define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF /*!< Not Acknowledge flag */
+#define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF /*!< Stop detection flag */
+#define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF /*!< Bus error flag */
+#define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF /*!< Arbitration Lost flag */
+#define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF /*!< Overrun/Underrun flag */
+#define LL_I2C_ICR_PECCF I2C_ICR_PECCF /*!< PEC error flag */
+#define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF /*!< Timeout detection flag */
+#define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF /*!< Alert flag */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_I2C_ReadReg function
+ * @{
+ */
+#define LL_I2C_ISR_TXE I2C_ISR_TXE /*!< Transmit data register empty */
+#define LL_I2C_ISR_TXIS I2C_ISR_TXIS /*!< Transmit interrupt status */
+#define LL_I2C_ISR_RXNE I2C_ISR_RXNE /*!< Receive data register not empty */
+#define LL_I2C_ISR_ADDR I2C_ISR_ADDR /*!< Address matched (slave mode) */
+#define LL_I2C_ISR_NACKF I2C_ISR_NACKF /*!< Not Acknowledge received flag */
+#define LL_I2C_ISR_STOPF I2C_ISR_STOPF /*!< Stop detection flag */
+#define LL_I2C_ISR_TC I2C_ISR_TC /*!< Transfer Complete (master mode) */
+#define LL_I2C_ISR_TCR I2C_ISR_TCR /*!< Transfer Complete Reload */
+#define LL_I2C_ISR_BERR I2C_ISR_BERR /*!< Bus error */
+#define LL_I2C_ISR_ARLO I2C_ISR_ARLO /*!< Arbitration lost */
+#define LL_I2C_ISR_OVR I2C_ISR_OVR /*!< Overrun/Underrun (slave mode) */
+#define LL_I2C_ISR_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */
+#define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */
+#define LL_I2C_ISR_ALERT I2C_ISR_ALERT /*!< SMBus alert (SMBus mode) */
+#define LL_I2C_ISR_BUSY I2C_ISR_BUSY /*!< Bus busy */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
+ * @{
+ */
+#define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable */
+#define LL_I2C_CR1_RXIE I2C_CR1_RXIE /*!< RX Interrupt enable */
+#define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE /*!< Address match Interrupt enable (slave only) */
+#define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE /*!< Not acknowledge received Interrupt enable */
+#define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE /*!< STOP detection Interrupt enable */
+#define LL_I2C_CR1_TCIE I2C_CR1_TCIE /*!< Transfer Complete interrupt enable */
+#define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
+ * @{
+ */
+#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */
+#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */
+#define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode
+ (Default address not acknowledge) */
+#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
+ * @{
+ */
+#define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */
+#define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /*!< Analog filter is disabled. */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
+ * @{
+ */
+#define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /*!< Master operates in 7-bit addressing mode. */
+#define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /*!< Master operates in 10-bit addressing mode.*/
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
+ * @{
+ */
+#define LL_I2C_OWNADDRESS1_7BIT 0x00000000U /*!< Own address 1 is a 7-bit address. */
+#define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /*!< Own address 1 is a 10-bit address.*/
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
+ * @{
+ */
+#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */
+#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done.
+ All Address2 are acknowledged. */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
+ * @{
+ */
+#define LL_I2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */
+#define LL_I2C_NACK I2C_CR2_NACK /*!< NACK is sent after current received byte.*/
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
+ * @{
+ */
+#define LL_I2C_ADDRSLAVE_7BIT 0x00000000U /*!< Slave Address in 7-bit. */
+#define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /*!< Slave Address in 10-bit.*/
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
+ * @{
+ */
+#define LL_I2C_REQUEST_WRITE 0x00000000U /*!< Master request a write transfer. */
+#define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /*!< Master request a read transfer. */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_MODE Transfer End Mode
+ * @{
+ */
+/*!< Enable I2C Reload mode. */
+#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD
+/*!< Enable I2C Automatic end mode with no HW PEC comparison. */
+#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND
+/*!< Enable I2C Software end mode with no HW PEC comparison. */
+#define LL_I2C_MODE_SOFTEND 0x00000000U
+/*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
+#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD
+/*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
+#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND
+/*!< Enable SMBUS Software end mode with HW PEC comparison. */
+#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND
+/*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
+#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)
+/*!< Enable SMBUS Software end mode with HW PEC comparison. */
+#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
+ * @{
+ */
+/*!< Don't Generate Stop and Start condition. */
+#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U
+/*!< Generate Stop condition (Size should be set to 0). */
+#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
+/*!< Generate Start for read request. */
+#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
+/*!< Generate Start for write request. */
+#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
+/*!< Generate Restart for read request, slave 7Bit address. */
+#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
+/*!< Generate Restart for write request, slave 7Bit address. */
+#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
+/*!< Generate Restart for read request, slave 10Bit address. */
+#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R)
+/*!< Generate Restart for write request, slave 10Bit address.*/
+#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
+ * @{
+ */
+#define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, slave enters receiver mode. */
+#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master, slave enters transmitter mode.*/
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
+ * @{
+ */
+#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
+#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
+ * @{
+ */
+#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect SCL low level
+ timeout. */
+#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect both SCL and SDA
+ high level timeout.*/
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
+ * @{
+ */
+#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */
+#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) enable bit */
+#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | \
+ I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB enable bits */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_AUTOCR_TRIGSEL Autonomous Trigger selection
+ * @brief I2C Autonomous Trigger selection
+ * @{
+ */
+#define LL_I2C_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1, I2C2 and I2C4 */
+#define LL_I2C_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3 */
+
+/*!< HW Trigger signal is GPDMA_CH0_TRG */
+#define LL_I2C_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x00000000U))
+/*!< HW Trigger signal is GPDMA_CH1_TRG */
+#define LL_I2C_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is GPDMA_CH2_TRG */
+#define LL_I2C_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is GPDMA_CH3_TRG */
+#define LL_I2C_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is EXTI5_TRG */
+#define LL_I2C_GRP1_EXTI5_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is EXTI9_TRG */
+#define LL_I2C_GRP1_EXTI9_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is LPTIM1_CH1_TRG */
+#define LL_I2C_GRP1_LPTIM1_CH1_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is LPTIM2_CH1_TRG */
+#define LL_I2C_GRP1_LPTIM2_CH1_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is COMP1_TRG */
+#define LL_I2C_GRP1_COMP1_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is COMP2_TRG */
+#define LL_I2C_GRP1_COMP2_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is RTC_ALRA_TRG */
+#define LL_I2C_GRP1_RTC_ALRA_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is RTC_WUT_TRG */
+#define LL_I2C_GRP1_RTC_WUT_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos))
+
+/*!< HW Trigger signal is LPDMA_CH0_TRG */
+#define LL_I2C_GRP2_LPDMA_CH0_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x00000000U))
+/*!< HW Trigger signal is LPDMA_CH1_TRG */
+#define LL_I2C_GRP2_LPDMA_CH1_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is LPDMA_CH2_TRG */
+#define LL_I2C_GRP2_LPDMA_CH2_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is LPDMA_CH3_TRG */
+#define LL_I2C_GRP2_LPDMA_CH3_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is EXTI5_TRG */
+#define LL_I2C_GRP2_EXTI5_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is EXTI8_TRG */
+#define LL_I2C_GRP2_EXTI8_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is LPTIM1_CH1_TRG */
+#define LL_I2C_GRP2_LPTIM1_CH1_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is LPTIM3_CH1_TRG */
+#define LL_I2C_GRP2_LPTIM3_CH1_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is COMP1_TRG */
+#define LL_I2C_GRP2_COMP1_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is COMP2_TRG */
+#define LL_I2C_GRP2_COMP2_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is RTC_ALRA_TRG */
+#define LL_I2C_GRP2_RTC_ALRA_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is RTC_WUT_TRG */
+#define LL_I2C_GRP2_RTC_WUT_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_AUTOCR_TRIGPOL Autonomous Trigger Polarity
+ * @brief I2C Autonomous Trigger Polarity
+ * @{
+ */
+#define LL_I2C_TRIG_POLARITY_RISING 0x00000000U /*!< I2C triggered on rising edge */
+#define LL_I2C_TRIG_POLARITY_FALLING I2C_AUTOCR_TRIGPOL /*!< I2C triggered on falling edge */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
+ * @{
+ */
+
+/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in I2C register
+ * @param __INSTANCE__ I2C Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in I2C register
+ * @param __INSTANCE__ I2C Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
+ * @{
+ */
+/**
+ * @brief Configure the SDA setup, hold time and the SCL high, low period.
+ * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
+ * @param __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
+ (tscldel = (SCLDEL+1)xtpresc)
+ * @param __HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
+ (tsdadel = SDADELxtpresc)
+ * @param __SCL_H_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
+ (tsclh = (SCLH+1)xtpresc)
+ * @param __SCL_L_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
+ (tscll = (SCLL+1)xtpresc)
+ * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+ */
+#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCL_H_PERIOD__, __SCL_L_PERIOD__) \
+ ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \
+ (((uint32_t)(__SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \
+ (((uint32_t)(__HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \
+ (((uint32_t)(__SCL_H_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \
+ (((uint32_t)(__SCL_L_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
+ * @{
+ */
+
+/** @defgroup I2C_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Enable I2C peripheral (PE = 1).
+ * @rmtoll CR1 PE LL_I2C_Enable
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_PE);
+}
+
+/**
+ * @brief Disable I2C peripheral (PE = 0).
+ * @note When PE = 0, the I2C SCL and SDA lines are released.
+ * Internal state machines and status bits are put back to their reset value.
+ * When cleared, PE must be kept low for at least 3 APB clock cycles.
+ * @rmtoll CR1 PE LL_I2C_Disable
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
+}
+
+/**
+ * @brief Check if the I2C peripheral is enabled or disabled.
+ * @rmtoll CR1 PE LL_I2C_IsEnabled
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
+{
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure Noise Filters (Analog and Digital).
+ * @note If the analog filter is also enabled, the digital filter is added to analog filter.
+ * The filters can only be programmed when the I2C is disabled (PE = 0).
+ * @rmtoll CR1 ANFOFF LL_I2C_ConfigFilters\n
+ * CR1 DNF LL_I2C_ConfigFilters
+ * @param I2Cx I2C Instance.
+ * @param AnalogFilter This parameter can be one of the following values:
+ * @arg @ref LL_I2C_ANALOGFILTER_ENABLE
+ * @arg @ref LL_I2C_ANALOGFILTER_DISABLE
+ * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
+ and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
+ * This parameter is used to configure the digital noise filter on SDA and SCL input.
+ * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
+{
+ MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos));
+}
+
+/**
+ * @brief Configure Digital Noise Filter.
+ * @note If the analog filter is also enabled, the digital filter is added to analog filter.
+ * This filter can only be programmed when the I2C is disabled (PE = 0).
+ * @rmtoll CR1 DNF LL_I2C_SetDigitalFilter
+ * @param I2Cx I2C Instance.
+ * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
+ and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
+ * This parameter is used to configure the digital noise filter on SDA and SCL input.
+ * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
+{
+ MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos);
+}
+
+/**
+ * @brief Get the current Digital Noise Filter configuration.
+ * @rmtoll CR1 DNF LL_I2C_GetDigitalFilter
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x0 and Max_Data=0xF
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
+}
+
+/**
+ * @brief Enable Analog Noise Filter.
+ * @note This filter can only be programmed when the I2C is disabled (PE = 0).
+ * @rmtoll CR1 ANFOFF LL_I2C_EnableAnalogFilter
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
+}
+
+/**
+ * @brief Disable Analog Noise Filter.
+ * @note This filter can only be programmed when the I2C is disabled (PE = 0).
+ * @rmtoll CR1 ANFOFF LL_I2C_DisableAnalogFilter
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
+}
+
+/**
+ * @brief Check if Analog Noise Filter is enabled or disabled.
+ * @rmtoll CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
+{
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable DMA transmission requests.
+ * @rmtoll CR1 TXDMAEN LL_I2C_EnableDMAReq_TX
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
+}
+
+/**
+ * @brief Disable DMA transmission requests.
+ * @rmtoll CR1 TXDMAEN LL_I2C_DisableDMAReq_TX
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
+}
+
+/**
+ * @brief Check if DMA transmission requests are enabled or disabled.
+ * @rmtoll CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
+{
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable DMA reception requests.
+ * @rmtoll CR1 RXDMAEN LL_I2C_EnableDMAReq_RX
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
+}
+
+/**
+ * @brief Disable DMA reception requests.
+ * @rmtoll CR1 RXDMAEN LL_I2C_DisableDMAReq_RX
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
+}
+
+/**
+ * @brief Check if DMA reception requests are enabled or disabled.
+ * @rmtoll CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
+{
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get the data register address used for DMA transfer
+ * @rmtoll TXDR TXDATA LL_I2C_DMA_GetRegAddr\n
+ * RXDR RXDATA LL_I2C_DMA_GetRegAddr
+ * @param I2Cx I2C Instance
+ * @param Direction This parameter can be one of the following values:
+ * @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
+ * @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
+ * @retval Address of data register
+ */
+__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
+{
+ uint32_t data_reg_addr;
+
+ if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
+ {
+ /* return address of TXDR register */
+ data_reg_addr = (uint32_t) &(I2Cx->TXDR);
+ }
+ else
+ {
+ /* return address of RXDR register */
+ data_reg_addr = (uint32_t) &(I2Cx->RXDR);
+ }
+
+ return data_reg_addr;
+}
+
+/**
+ * @brief Enable Clock stretching.
+ * @note This bit can only be programmed when the I2C is disabled (PE = 0).
+ * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
+}
+
+/**
+ * @brief Disable Clock stretching.
+ * @note This bit can only be programmed when the I2C is disabled (PE = 0).
+ * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
+}
+
+/**
+ * @brief Check if Clock stretching is enabled or disabled.
+ * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
+{
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable hardware byte control in slave mode.
+ * @rmtoll CR1 SBC LL_I2C_EnableSlaveByteControl
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
+}
+
+/**
+ * @brief Disable hardware byte control in slave mode.
+ * @rmtoll CR1 SBC LL_I2C_DisableSlaveByteControl
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
+}
+
+/**
+ * @brief Check if hardware byte control in slave mode is enabled or disabled.
+ * @rmtoll CR1 SBC LL_I2C_IsEnabledSlaveByteControl
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
+{
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable Wakeup from STOP.
+ * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
+ * WakeUpFromStop feature is supported by the I2Cx Instance.
+ * @note This bit can only be programmed when Digital Filter is disabled.
+ * @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
+}
+
+/**
+ * @brief Disable Wakeup from STOP.
+ * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
+ * WakeUpFromStop feature is supported by the I2Cx Instance.
+ * @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
+}
+
+/**
+ * @brief Check if Wakeup from STOP is enabled or disabled.
+ * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
+ * WakeUpFromStop feature is supported by the I2Cx Instance.
+ * @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx)
+{
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable General Call.
+ * @note When enabled the Address 0x00 is ACKed.
+ * @rmtoll CR1 GCEN LL_I2C_EnableGeneralCall
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
+}
+
+/**
+ * @brief Disable General Call.
+ * @note When disabled the Address 0x00 is NACKed.
+ * @rmtoll CR1 GCEN LL_I2C_DisableGeneralCall
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
+}
+
+/**
+ * @brief Check if General Call is enabled or disabled.
+ * @rmtoll CR1 GCEN LL_I2C_IsEnabledGeneralCall
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
+{
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable I2C Fast Mode Plus (FMP = 1).
+ * @note 20mA I/O drive enable
+ * @rmtoll CR1 FMP LL_I2C_EnableFastModePlus
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableFastModePlus(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_FMP);
+}
+
+/**
+ * @brief Disable I2C Fast Mode Plus (FMP = 0).
+ * @note 20mA I/O drive disable
+ * @rmtoll CR1 FMP LL_I2C_DisableFastModePlus
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableFastModePlus(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_FMP);
+}
+
+/**
+ * @brief Check if the I2C Fast Mode Plus is enabled or disabled.
+ * @rmtoll CR1 FMP LL_I2C_IsEnabledFastModePlus
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledFastModePlus(I2C_TypeDef *I2Cx)
+{
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_FMP) == (I2C_CR1_FMP)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure the Master to operate in 7-bit or 10-bit addressing mode.
+ * @note Changing this bit is not allowed, when the START bit is set.
+ * @rmtoll CR2 ADD10 LL_I2C_SetMasterAddressingMode
+ * @param I2Cx I2C Instance.
+ * @param AddressingMode This parameter can be one of the following values:
+ * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
+ * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
+{
+ MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
+}
+
+/**
+ * @brief Get the Master addressing mode.
+ * @rmtoll CR2 ADD10 LL_I2C_GetMasterAddressingMode
+ * @param I2Cx I2C Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
+ * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
+}
+
+/**
+ * @brief Set the Own Address1.
+ * @rmtoll OAR1 OA1 LL_I2C_SetOwnAddress1\n
+ * OAR1 OA1MODE LL_I2C_SetOwnAddress1
+ * @param I2Cx I2C Instance.
+ * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
+ * @param OwnAddrSize This parameter can be one of the following values:
+ * @arg @ref LL_I2C_OWNADDRESS1_7BIT
+ * @arg @ref LL_I2C_OWNADDRESS1_10BIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
+{
+ MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
+}
+
+/**
+ * @brief Enable acknowledge on Own Address1 match address.
+ * @rmtoll OAR1 OA1EN LL_I2C_EnableOwnAddress1
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
+}
+
+/**
+ * @brief Disable acknowledge on Own Address1 match address.
+ * @rmtoll OAR1 OA1EN LL_I2C_DisableOwnAddress1
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
+}
+
+/**
+ * @brief Check if Own Address1 acknowledge is enabled or disabled.
+ * @rmtoll OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
+{
+ return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set the 7bits Own Address2.
+ * @note This action has no effect if own address2 is enabled.
+ * @rmtoll OAR2 OA2 LL_I2C_SetOwnAddress2\n
+ * OAR2 OA2MSK LL_I2C_SetOwnAddress2
+ * @param I2Cx I2C Instance.
+ * @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
+ * @param OwnAddrMask This parameter can be one of the following values:
+ * @arg @ref LL_I2C_OWNADDRESS2_NOMASK
+ * @arg @ref LL_I2C_OWNADDRESS2_MASK01
+ * @arg @ref LL_I2C_OWNADDRESS2_MASK02
+ * @arg @ref LL_I2C_OWNADDRESS2_MASK03
+ * @arg @ref LL_I2C_OWNADDRESS2_MASK04
+ * @arg @ref LL_I2C_OWNADDRESS2_MASK05
+ * @arg @ref LL_I2C_OWNADDRESS2_MASK06
+ * @arg @ref LL_I2C_OWNADDRESS2_MASK07
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
+{
+ MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
+}
+
+/**
+ * @brief Enable acknowledge on Own Address2 match address.
+ * @rmtoll OAR2 OA2EN LL_I2C_EnableOwnAddress2
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
+}
+
+/**
+ * @brief Disable acknowledge on Own Address2 match address.
+ * @rmtoll OAR2 OA2EN LL_I2C_DisableOwnAddress2
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
+}
+
+/**
+ * @brief Check if Own Address1 acknowledge is enabled or disabled.
+ * @rmtoll OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
+{
+ return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure the SDA setup, hold time and the SCL high, low period.
+ * @note This bit can only be programmed when the I2C is disabled (PE = 0).
+ * @rmtoll TIMINGR TIMINGR LL_I2C_SetTiming
+ * @param I2Cx I2C Instance.
+ * @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
+ * @note This parameter is computed with the STM32CubeMX Tool.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
+{
+ WRITE_REG(I2Cx->TIMINGR, Timing);
+}
+
+/**
+ * @brief Get the Timing Prescaler setting.
+ * @rmtoll TIMINGR PRESC LL_I2C_GetTimingPrescaler
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x0 and Max_Data=0xF
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
+}
+
+/**
+ * @brief Get the SCL low period setting.
+ * @rmtoll TIMINGR SCLL LL_I2C_GetClockLowPeriod
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
+}
+
+/**
+ * @brief Get the SCL high period setting.
+ * @rmtoll TIMINGR SCLH LL_I2C_GetClockHighPeriod
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
+}
+
+/**
+ * @brief Get the SDA hold time.
+ * @rmtoll TIMINGR SDADEL LL_I2C_GetDataHoldTime
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x0 and Max_Data=0xF
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
+}
+
+/**
+ * @brief Get the SDA setup time.
+ * @rmtoll TIMINGR SCLDEL LL_I2C_GetDataSetupTime
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x0 and Max_Data=0xF
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
+}
+
+/**
+ * @brief Configure peripheral mode.
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll CR1 SMBHEN LL_I2C_SetMode\n
+ * CR1 SMBDEN LL_I2C_SetMode
+ * @param I2Cx I2C Instance.
+ * @param PeripheralMode This parameter can be one of the following values:
+ * @arg @ref LL_I2C_MODE_I2C
+ * @arg @ref LL_I2C_MODE_SMBUS_HOST
+ * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
+ * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
+{
+ MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode);
+}
+
+/**
+ * @brief Get peripheral mode.
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll CR1 SMBHEN LL_I2C_GetMode\n
+ * CR1 SMBDEN LL_I2C_GetMode
+ * @param I2Cx I2C Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2C_MODE_I2C
+ * @arg @ref LL_I2C_MODE_SMBUS_HOST
+ * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
+ * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
+}
+
+/**
+ * @brief Enable SMBus alert (Host or Device mode)
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note SMBus Device mode:
+ * - SMBus Alert pin is drived low and
+ * Alert Response Address Header acknowledge is enabled.
+ * SMBus Host mode:
+ * - SMBus Alert pin management is supported.
+ * @rmtoll CR1 ALERTEN LL_I2C_EnableSMBusAlert
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
+}
+
+/**
+ * @brief Disable SMBus alert (Host or Device mode)
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note SMBus Device mode:
+ * - SMBus Alert pin is not drived (can be used as a standard GPIO) and
+ * Alert Response Address Header acknowledge is disabled.
+ * SMBus Host mode:
+ * - SMBus Alert pin management is not supported.
+ * @rmtoll CR1 ALERTEN LL_I2C_DisableSMBusAlert
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
+}
+
+/**
+ * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
+{
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable SMBus Packet Error Calculation (PEC).
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
+}
+
+/**
+ * @brief Disable SMBus Packet Error Calculation (PEC).
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
+}
+
+/**
+ * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
+{
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure the SMBus Clock Timeout.
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
+ * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n
+ * TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout\n
+ * TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout
+ * @param I2Cx I2C Instance.
+ * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
+ * @param TimeoutAMode This parameter can be one of the following values:
+ * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
+ * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
+ * @param TimeoutB
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
+ uint32_t TimeoutB)
+{
+ MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB,
+ TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos));
+}
+
+/**
+ * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note These bits can only be programmed when TimeoutA is disabled.
+ * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA
+ * @param I2Cx I2C Instance.
+ * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
+{
+ WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
+}
+
+/**
+ * @brief Get the SMBus Clock TimeoutA setting.
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
+}
+
+/**
+ * @brief Set the SMBus Clock TimeoutA mode.
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note This bit can only be programmed when TimeoutA is disabled.
+ * @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode
+ * @param I2Cx I2C Instance.
+ * @param TimeoutAMode This parameter can be one of the following values:
+ * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
+ * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
+{
+ WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
+}
+
+/**
+ * @brief Get the SMBus Clock TimeoutA mode.
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode
+ * @param I2Cx I2C Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
+ * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
+}
+
+/**
+ * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note These bits can only be programmed when TimeoutB is disabled.
+ * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB
+ * @param I2Cx I2C Instance.
+ * @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
+{
+ WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos);
+}
+
+/**
+ * @brief Get the SMBus Extended Cumulative Clock TimeoutB setting.
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
+}
+
+/**
+ * @brief Enable the SMBus Clock Timeout.
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n
+ * TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout
+ * @param I2Cx I2C Instance.
+ * @param ClockTimeout This parameter can be one of the following values:
+ * @arg @ref LL_I2C_SMBUS_TIMEOUTA
+ * @arg @ref LL_I2C_SMBUS_TIMEOUTB
+ * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
+{
+ SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
+}
+
+/**
+ * @brief Disable the SMBus Clock Timeout.
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n
+ * TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout
+ * @param I2Cx I2C Instance.
+ * @param ClockTimeout This parameter can be one of the following values:
+ * @arg @ref LL_I2C_SMBUS_TIMEOUTA
+ * @arg @ref LL_I2C_SMBUS_TIMEOUTB
+ * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
+{
+ CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
+}
+
+/**
+ * @brief Check if the SMBus Clock Timeout is enabled or disabled.
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n
+ * TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout
+ * @param I2Cx I2C Instance.
+ * @param ClockTimeout This parameter can be one of the following values:
+ * @arg @ref LL_I2C_SMBUS_TIMEOUTA
+ * @arg @ref LL_I2C_SMBUS_TIMEOUTB
+ * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
+{
+ return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable TXIS interrupt.
+ * @rmtoll CR1 TXIE LL_I2C_EnableIT_TX
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
+}
+
+/**
+ * @brief Disable TXIS interrupt.
+ * @rmtoll CR1 TXIE LL_I2C_DisableIT_TX
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
+}
+
+/**
+ * @brief Check if the TXIS Interrupt is enabled or disabled.
+ * @rmtoll CR1 TXIE LL_I2C_IsEnabledIT_TX
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
+{
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable RXNE interrupt.
+ * @rmtoll CR1 RXIE LL_I2C_EnableIT_RX
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
+}
+
+/**
+ * @brief Disable RXNE interrupt.
+ * @rmtoll CR1 RXIE LL_I2C_DisableIT_RX
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
+}
+
+/**
+ * @brief Check if the RXNE Interrupt is enabled or disabled.
+ * @rmtoll CR1 RXIE LL_I2C_IsEnabledIT_RX
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
+{
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable Address match interrupt (slave mode only).
+ * @rmtoll CR1 ADDRIE LL_I2C_EnableIT_ADDR
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
+}
+
+/**
+ * @brief Disable Address match interrupt (slave mode only).
+ * @rmtoll CR1 ADDRIE LL_I2C_DisableIT_ADDR
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
+}
+
+/**
+ * @brief Check if Address match interrupt is enabled or disabled.
+ * @rmtoll CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
+{
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable Not acknowledge received interrupt.
+ * @rmtoll CR1 NACKIE LL_I2C_EnableIT_NACK
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
+}
+
+/**
+ * @brief Disable Not acknowledge received interrupt.
+ * @rmtoll CR1 NACKIE LL_I2C_DisableIT_NACK
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
+}
+
+/**
+ * @brief Check if Not acknowledge received interrupt is enabled or disabled.
+ * @rmtoll CR1 NACKIE LL_I2C_IsEnabledIT_NACK
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
+{
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable STOP detection interrupt.
+ * @rmtoll CR1 STOPIE LL_I2C_EnableIT_STOP
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
+}
+
+/**
+ * @brief Disable STOP detection interrupt.
+ * @rmtoll CR1 STOPIE LL_I2C_DisableIT_STOP
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
+}
+
+/**
+ * @brief Check if STOP detection interrupt is enabled or disabled.
+ * @rmtoll CR1 STOPIE LL_I2C_IsEnabledIT_STOP
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
+{
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable Transfer Complete interrupt.
+ * @note Any of these events will generate interrupt :
+ * Transfer Complete (TC)
+ * Transfer Complete Reload (TCR)
+ * @rmtoll CR1 TCIE LL_I2C_EnableIT_TC
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
+}
+
+/**
+ * @brief Disable Transfer Complete interrupt.
+ * @note Any of these events will generate interrupt :
+ * Transfer Complete (TC)
+ * Transfer Complete Reload (TCR)
+ * @rmtoll CR1 TCIE LL_I2C_DisableIT_TC
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
+}
+
+/**
+ * @brief Check if Transfer Complete interrupt is enabled or disabled.
+ * @rmtoll CR1 TCIE LL_I2C_IsEnabledIT_TC
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
+{
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable Error interrupts.
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note Any of these errors will generate interrupt :
+ * Arbitration Loss (ARLO)
+ * Bus Error detection (BERR)
+ * Overrun/Underrun (OVR)
+ * SMBus Timeout detection (TIMEOUT)
+ * SMBus PEC error detection (PECERR)
+ * SMBus Alert pin event detection (ALERT)
+ * @rmtoll CR1 ERRIE LL_I2C_EnableIT_ERR
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
+}
+
+/**
+ * @brief Disable Error interrupts.
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note Any of these errors will generate interrupt :
+ * Arbitration Loss (ARLO)
+ * Bus Error detection (BERR)
+ * Overrun/Underrun (OVR)
+ * SMBus Timeout detection (TIMEOUT)
+ * SMBus PEC error detection (PECERR)
+ * SMBus Alert pin event detection (ALERT)
+ * @rmtoll CR1 ERRIE LL_I2C_DisableIT_ERR
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
+}
+
+/**
+ * @brief Check if Error interrupts are enabled or disabled.
+ * @rmtoll CR1 ERRIE LL_I2C_IsEnabledIT_ERR
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
+{
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EF_FLAG_management FLAG_management
+ * @{
+ */
+
+/**
+ * @brief Indicate the status of Transmit data register empty flag.
+ * @note RESET: When next data is written in Transmit data register.
+ * SET: When Transmit data register is empty.
+ * @rmtoll ISR TXE LL_I2C_IsActiveFlag_TXE
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
+{
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Transmit interrupt flag.
+ * @note RESET: When next data is written in Transmit data register.
+ * SET: When Transmit data register is empty.
+ * @rmtoll ISR TXIS LL_I2C_IsActiveFlag_TXIS
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
+{
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Receive data register not empty flag.
+ * @note RESET: When Receive data register is read.
+ * SET: When the received data is copied in Receive data register.
+ * @rmtoll ISR RXNE LL_I2C_IsActiveFlag_RXNE
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
+{
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Address matched flag (slave mode).
+ * @note RESET: Clear default value.
+ * SET: When the received slave address matched with one of the enabled slave address.
+ * @rmtoll ISR ADDR LL_I2C_IsActiveFlag_ADDR
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
+{
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Not Acknowledge received flag.
+ * @note RESET: Clear default value.
+ * SET: When a NACK is received after a byte transmission.
+ * @rmtoll ISR NACKF LL_I2C_IsActiveFlag_NACK
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
+{
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Stop detection flag.
+ * @note RESET: Clear default value.
+ * SET: When a Stop condition is detected.
+ * @rmtoll ISR STOPF LL_I2C_IsActiveFlag_STOP
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
+{
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Transfer complete flag (master mode).
+ * @note RESET: Clear default value.
+ * SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
+ * @rmtoll ISR TC LL_I2C_IsActiveFlag_TC
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
+{
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Transfer complete flag (master mode).
+ * @note RESET: Clear default value.
+ * SET: When RELOAD=1 and NBYTES date have been transferred.
+ * @rmtoll ISR TCR LL_I2C_IsActiveFlag_TCR
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
+{
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Bus error flag.
+ * @note RESET: Clear default value.
+ * SET: When a misplaced Start or Stop condition is detected.
+ * @rmtoll ISR BERR LL_I2C_IsActiveFlag_BERR
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
+{
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Arbitration lost flag.
+ * @note RESET: Clear default value.
+ * SET: When arbitration lost.
+ * @rmtoll ISR ARLO LL_I2C_IsActiveFlag_ARLO
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
+{
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Overrun/Underrun flag (slave mode).
+ * @note RESET: Clear default value.
+ * SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
+ * @rmtoll ISR OVR LL_I2C_IsActiveFlag_OVR
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
+{
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of SMBus PEC error flag in reception.
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note RESET: Clear default value.
+ * SET: When the received PEC does not match with the PEC register content.
+ * @rmtoll ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
+{
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of SMBus Timeout detection flag.
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note RESET: Clear default value.
+ * SET: When a timeout or extended clock timeout occurs.
+ * @rmtoll ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
+{
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of SMBus alert flag.
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note RESET: Clear default value.
+ * SET: When SMBus host configuration, SMBus alert enabled and
+ * a falling edge event occurs on SMBA pin.
+ * @rmtoll ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
+{
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Bus Busy flag.
+ * @note RESET: Clear default value.
+ * SET: When a Start condition is detected.
+ * @rmtoll ISR BUSY LL_I2C_IsActiveFlag_BUSY
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
+{
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear Address Matched flag.
+ * @rmtoll ICR ADDRCF LL_I2C_ClearFlag_ADDR
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
+}
+
+/**
+ * @brief Clear Not Acknowledge flag.
+ * @rmtoll ICR NACKCF LL_I2C_ClearFlag_NACK
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
+}
+
+/**
+ * @brief Clear Stop detection flag.
+ * @rmtoll ICR STOPCF LL_I2C_ClearFlag_STOP
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
+}
+
+/**
+ * @brief Clear Transmit data register empty flag (TXE).
+ * @note This bit can be clear by software in order to flush the transmit data register (TXDR).
+ * @rmtoll ISR TXE LL_I2C_ClearFlag_TXE
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
+{
+ WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
+}
+
+/**
+ * @brief Clear Bus error flag.
+ * @rmtoll ICR BERRCF LL_I2C_ClearFlag_BERR
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
+}
+
+/**
+ * @brief Clear Arbitration lost flag.
+ * @rmtoll ICR ARLOCF LL_I2C_ClearFlag_ARLO
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
+}
+
+/**
+ * @brief Clear Overrun/Underrun flag.
+ * @rmtoll ICR OVRCF LL_I2C_ClearFlag_OVR
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
+}
+
+/**
+ * @brief Clear SMBus PEC error flag.
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
+}
+
+/**
+ * @brief Clear SMBus Timeout detection flag.
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
+}
+
+/**
+ * @brief Clear SMBus Alert flag.
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EF_Data_Management Data_Management
+ * @{
+ */
+
+/**
+ * @brief Enable automatic STOP condition generation (master mode).
+ * @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
+ * This bit has no effect in slave mode or when RELOAD bit is set.
+ * @rmtoll CR2 AUTOEND LL_I2C_EnableAutoEndMode
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
+}
+
+/**
+ * @brief Disable automatic STOP condition generation (master mode).
+ * @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
+ * @rmtoll CR2 AUTOEND LL_I2C_DisableAutoEndMode
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
+}
+
+/**
+ * @brief Check if automatic STOP condition is enabled or disabled.
+ * @rmtoll CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
+{
+ return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable reload mode (master mode).
+ * @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
+ * @rmtoll CR2 RELOAD LL_I2C_EnableReloadMode
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
+}
+
+/**
+ * @brief Disable reload mode (master mode).
+ * @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
+ * @rmtoll CR2 RELOAD LL_I2C_DisableReloadMode
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
+}
+
+/**
+ * @brief Check if reload mode is enabled or disabled.
+ * @rmtoll CR2 RELOAD LL_I2C_IsEnabledReloadMode
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
+{
+ return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure the number of bytes for transfer.
+ * @note Changing these bits when START bit is set is not allowed.
+ * @rmtoll CR2 NBYTES LL_I2C_SetTransferSize
+ * @param I2Cx I2C Instance.
+ * @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
+{
+ MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos);
+}
+
+/**
+ * @brief Get the number of bytes configured for transfer.
+ * @rmtoll CR2 NBYTES LL_I2C_GetTransferSize
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x0 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
+}
+
+/**
+ * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code
+ or next received byte.
+ * @note Usage in Slave mode only.
+ * @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData
+ * @param I2Cx I2C Instance.
+ * @param TypeAcknowledge This parameter can be one of the following values:
+ * @arg @ref LL_I2C_ACK
+ * @arg @ref LL_I2C_NACK
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
+{
+ MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
+}
+
+/**
+ * @brief Generate a START or RESTART condition
+ * @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
+ * This action has no effect when RELOAD is set.
+ * @rmtoll CR2 START LL_I2C_GenerateStartCondition
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR2, I2C_CR2_START);
+}
+
+/**
+ * @brief Generate a STOP condition after the current byte transfer (master mode).
+ * @rmtoll CR2 STOP LL_I2C_GenerateStopCondition
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
+}
+
+/**
+ * @brief Enable automatic RESTART Read request condition for 10bit address header (master mode).
+ * @note The master sends the complete 10bit slave address read sequence :
+ * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address
+ in Read direction.
+ * @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
+}
+
+/**
+ * @brief Disable automatic RESTART Read request condition for 10bit address header (master mode).
+ * @note The master only sends the first 7 bits of 10bit address in Read direction.
+ * @rmtoll CR2 HEAD10R LL_I2C_DisableAuto10BitRead
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
+}
+
+/**
+ * @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
+ * @rmtoll CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
+{
+ return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure the transfer direction (master mode).
+ * @note Changing these bits when START bit is set is not allowed.
+ * @rmtoll CR2 RD_WRN LL_I2C_SetTransferRequest
+ * @param I2Cx I2C Instance.
+ * @param TransferRequest This parameter can be one of the following values:
+ * @arg @ref LL_I2C_REQUEST_WRITE
+ * @arg @ref LL_I2C_REQUEST_READ
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
+{
+ MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
+}
+
+/**
+ * @brief Get the transfer direction requested (master mode).
+ * @rmtoll CR2 RD_WRN LL_I2C_GetTransferRequest
+ * @param I2Cx I2C Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2C_REQUEST_WRITE
+ * @arg @ref LL_I2C_REQUEST_READ
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
+}
+
+/**
+ * @brief Configure the slave address for transfer (master mode).
+ * @note Changing these bits when START bit is set is not allowed.
+ * @rmtoll CR2 SADD LL_I2C_SetSlaveAddr
+ * @param I2Cx I2C Instance.
+ * @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
+{
+ MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
+}
+
+/**
+ * @brief Get the slave address programmed for transfer.
+ * @rmtoll CR2 SADD LL_I2C_GetSlaveAddr
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x0 and Max_Data=0x3F
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
+}
+
+/**
+ * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
+ * @rmtoll CR2 SADD LL_I2C_HandleTransfer\n
+ * CR2 ADD10 LL_I2C_HandleTransfer\n
+ * CR2 RD_WRN LL_I2C_HandleTransfer\n
+ * CR2 START LL_I2C_HandleTransfer\n
+ * CR2 STOP LL_I2C_HandleTransfer\n
+ * CR2 RELOAD LL_I2C_HandleTransfer\n
+ * CR2 NBYTES LL_I2C_HandleTransfer\n
+ * CR2 AUTOEND LL_I2C_HandleTransfer\n
+ * CR2 HEAD10R LL_I2C_HandleTransfer
+ * @param I2Cx I2C Instance.
+ * @param SlaveAddr Specifies the slave address to be programmed.
+ * @param SlaveAddrSize This parameter can be one of the following values:
+ * @arg @ref LL_I2C_ADDRSLAVE_7BIT
+ * @arg @ref LL_I2C_ADDRSLAVE_10BIT
+ * @param TransferSize Specifies the number of bytes to be programmed.
+ * This parameter must be a value between Min_Data=0 and Max_Data=255.
+ * @param EndMode This parameter can be one of the following values:
+ * @arg @ref LL_I2C_MODE_RELOAD
+ * @arg @ref LL_I2C_MODE_AUTOEND
+ * @arg @ref LL_I2C_MODE_SOFTEND
+ * @arg @ref LL_I2C_MODE_SMBUS_RELOAD
+ * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
+ * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
+ * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
+ * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
+ * @param Request This parameter can be one of the following values:
+ * @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
+ * @arg @ref LL_I2C_GENERATE_STOP
+ * @arg @ref LL_I2C_GENERATE_START_READ
+ * @arg @ref LL_I2C_GENERATE_START_WRITE
+ * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
+ * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
+ * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
+ * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
+ uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
+{
+ MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 |
+ (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) |
+ I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
+ SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request);
+}
+
+/**
+ * @brief Indicate the value of transfer direction (slave mode).
+ * @note RESET: Write transfer, Slave enters in receiver mode.
+ * SET: Read transfer, Slave enters in transmitter mode.
+ * @rmtoll ISR DIR LL_I2C_GetTransferDirection
+ * @param I2Cx I2C Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2C_DIRECTION_WRITE
+ * @arg @ref LL_I2C_DIRECTION_READ
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
+}
+
+/**
+ * @brief Return the slave matched address.
+ * @rmtoll ISR ADDCODE LL_I2C_GetAddressMatchCode
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x00 and Max_Data=0x3F
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
+}
+
+/**
+ * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition
+ or an Address Matched is received.
+ * This bit has no effect when RELOAD bit is set.
+ * This bit has no effect in device mode when SBC bit is not set.
+ * @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
+}
+
+/**
+ * @brief Check if the SMBus Packet Error byte internal comparison is requested or not.
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
+{
+ return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get the SMBus Packet Error byte calculated.
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll PECR PEC LL_I2C_GetSMBusPEC
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
+}
+
+/**
+ * @brief Read Receive Data register.
+ * @rmtoll RXDR RXDATA LL_I2C_ReceiveData8
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
+{
+ return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
+}
+
+/**
+ * @brief Write in Transmit Data Register .
+ * @rmtoll TXDR TXDATA LL_I2C_TransmitData8
+ * @param I2Cx I2C Instance.
+ * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
+{
+ WRITE_REG(I2Cx->TXDR, Data);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EF_AutonomousMode Configuration functions related to Autonomous mode feature
+ * @{
+ */
+
+/**
+ * @brief Enable Selected Trigger
+ * @rmtoll AUTOCR TRIGEN LL_I2C_Enable_SelectedTrigger
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_Enable_SelectedTrigger(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->AUTOCR, I2C_AUTOCR_TRIGEN);
+}
+
+/**
+ * @brief Disable Selected Trigger
+ * @rmtoll AUTOCR TRIGEN LL_I2C_Disable_SelectedTrigger
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_Disable_SelectedTrigger(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->AUTOCR, I2C_AUTOCR_TRIGEN);
+}
+
+/**
+ * @brief Indicate if selected Trigger is disabled or enabled
+ * @rmtoll AUTOCR TRIGEN LL_I2C_IsEnabled_SelectedTrigger
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabled_SelectedTrigger(I2C_TypeDef *I2Cx)
+{
+ return ((READ_BIT(I2Cx->AUTOCR, I2C_AUTOCR_TRIGEN) == (I2C_AUTOCR_TRIGEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set the trigger polarity
+ * @rmtoll AUTOCR TRIGPOL LL_I2C_SetTriggerPolarity
+ * @param I2Cx I2C Instance.
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_I2C_TRIG_POLARITY_RISING
+ * @arg @ref LL_I2C_TRIG_POLARITY_FALLING
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetTriggerPolarity(I2C_TypeDef *I2Cx, uint32_t Polarity)
+{
+ MODIFY_REG(I2Cx->AUTOCR, I2C_AUTOCR_TRIGPOL, Polarity);
+}
+
+/**
+ * @brief Get the trigger polarity
+ * @rmtoll AUTOCR TRIGPOL LL_I2C_GetTriggerPolarity
+ * @param I2Cx I2C Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2C_TRIG_POLARITY_RISING
+ * @arg @ref LL_I2C_TRIG_POLARITY_FALLING
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetTriggerPolarity(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->AUTOCR, I2C_AUTOCR_TRIGPOL));
+}
+
+/**
+ * @brief Set the selected trigger
+ * @rmtoll AUTOCR TRIGSEL LL_I2C_SetSelectedTrigger
+ * @param I2Cx I2C Instance.
+ * @param Trigger This parameter can be one of the following values:
+ * @arg @ref LL_I2C_GRP1_GPDMA_CH0_TCF_TRG
+ * @arg @ref LL_I2C_GRP1_GPDMA_CH1_TCF_TRG
+ * @arg @ref LL_I2C_GRP1_GPDMA_CH2_TCF_TRG
+ * @arg @ref LL_I2C_GRP1_GPDMA_CH3_TCF_TRG
+ * @arg @ref LL_I2C_GRP1_EXTI5_TRG
+ * @arg @ref LL_I2C_GRP1_EXTI9_TRG
+ * @arg @ref LL_I2C_GRP1_LPTIM1_CH1_TRG
+ * @arg @ref LL_I2C_GRP1_LPTIM2_CH1_TRG
+ * @arg @ref LL_I2C_GRP1_COMP1_TRG
+ * @arg @ref LL_I2C_GRP1_COMP2_TRG
+ * @arg @ref LL_I2C_GRP1_RTC_ALRA_TRG
+ * @arg @ref LL_I2C_GRP1_RTC_WUT_TRG
+ * @arg @ref LL_I2C_GRP2_LPDMA_CH0_TCF_TRG
+ * @arg @ref LL_I2C_GRP2_LPDMA_CH1_TCF_TRG
+ * @arg @ref LL_I2C_GRP2_LPDMA_CH2_TCF_TRG
+ * @arg @ref LL_I2C_GRP2_LPDMA_CH3_TCF_TRG
+ * @arg @ref LL_I2C_GRP2_EXTI5_TRG
+ * @arg @ref LL_I2C_GRP2_EXTI8_TRG
+ * @arg @ref LL_I2C_GRP2_LPTIM1_CH1_TRG
+ * @arg @ref LL_I2C_GRP2_LPTIM3_CH1_TRG
+ * @arg @ref LL_I2C_GRP2_COMP1_TRG
+ * @arg @ref LL_I2C_GRP2_COMP2_TRG
+ * @arg @ref LL_I2C_GRP2_RTC_ALRA_TRG
+ * @arg @ref LL_I2C_GRP2_RTC_WUT_TRG
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetSelectedTrigger(I2C_TypeDef *I2Cx, uint32_t Trigger)
+{
+ MODIFY_REG(I2Cx->AUTOCR, I2C_AUTOCR_TRIGSEL, (Trigger & I2C_AUTOCR_TRIGSEL_Msk));
+}
+
+/**
+ * @brief Get the selected trigger
+ * @rmtoll AUTOCR TRIGSEL LL_I2C_GetSelectedTrigger
+ * @param I2Cx I2C Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2C_GRP1_GPDMA_CH0_TCF_TRG
+ * @arg @ref LL_I2C_GRP1_GPDMA_CH1_TCF_TRG
+ * @arg @ref LL_I2C_GRP1_GPDMA_CH2_TCF_TRG
+ * @arg @ref LL_I2C_GRP1_GPDMA_CH3_TCF_TRG
+ * @arg @ref LL_I2C_GRP1_EXTI5_TRG
+ * @arg @ref LL_I2C_GRP1_EXTI9_TRG
+ * @arg @ref LL_I2C_GRP1_LPTIM1_CH1_TRG
+ * @arg @ref LL_I2C_GRP1_LPTIM2_CH1_TRG
+ * @arg @ref LL_I2C_GRP1_COMP1_TRG
+ * @arg @ref LL_I2C_GRP1_COMP2_TRG
+ * @arg @ref LL_I2C_GRP1_RTC_ALRA_TRG
+ * @arg @ref LL_I2C_GRP1_RTC_WUT_TRG
+ * @arg @ref LL_I2C_GRP2_LPDMA_CH0_TCF_TRG
+ * @arg @ref LL_I2C_GRP2_LPDMA_CH1_TCF_TRG
+ * @arg @ref LL_I2C_GRP2_LPDMA_CH2_TCF_TRG
+ * @arg @ref LL_I2C_GRP2_LPDMA_CH3_TCF_TRG
+ * @arg @ref LL_I2C_GRP2_EXTI5_TRG
+ * @arg @ref LL_I2C_GRP2_EXTI8_TRG
+ * @arg @ref LL_I2C_GRP2_LPTIM1_CH1_TRG
+ * @arg @ref LL_I2C_GRP2_LPTIM3_CH1_TRG
+ * @arg @ref LL_I2C_GRP2_COMP1_TRG
+ * @arg @ref LL_I2C_GRP2_COMP2_TRG
+ * @arg @ref LL_I2C_GRP2_RTC_ALRA_TRG
+ * @arg @ref LL_I2C_GRP2_RTC_WUT_TRG
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetSelectedTrigger(I2C_TypeDef *I2Cx)
+{
+ if (IS_LL_I2C_GRP2_INSTANCE(I2Cx))
+ {
+ return (uint32_t)((READ_BIT(I2Cx->AUTOCR, I2C_AUTOCR_TRIGSEL) | LL_I2C_TRIG_GRP2));
+ }
+ else
+ {
+ return (uint32_t)((READ_BIT(I2Cx->AUTOCR, I2C_AUTOCR_TRIGSEL) | LL_I2C_TRIG_GRP1));
+ }
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
+ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx);
+void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
+
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* I2C1 || I2C2 || I2C3 || I2C4 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_LL_I2C_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_icache.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_icache.h
new file mode 100644
index 00000000..9e5322b8
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_icache.h
@@ -0,0 +1,778 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_icache.h
+ * @author MCD Application Team
+ * @brief Header file of ICACHE LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion ------------------------------------*/
+#ifndef STM32U5xx_LL_ICACHE_H
+#define STM32U5xx_LL_ICACHE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes -----------------------------------------------------------------*/
+#include "stm32u5xx.h"
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined(ICACHE)
+
+/** @defgroup ICACHE_LL ICACHE
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ICACHE_LL_REGION_CONFIG ICACHE Exported Configuration structure
+ * @{
+ */
+
+/**
+ * @brief LL ICACHE region configuration structure definition
+ */
+typedef struct
+{
+ uint32_t BaseAddress; /*!< Configures the C-AHB base address to be remapped */
+
+ uint32_t RemapAddress; /*!< Configures the remap address to be remapped */
+
+ uint32_t Size; /*!< Configures the region size.
+ This parameter can be a value of @ref ICACHE_LL_EC_Region_Size */
+
+ uint32_t TrafficRoute; /*!< Selects the traffic route.
+ This parameter can be a value of @ref ICACHE_LL_EC_Traffic_Route */
+
+ uint32_t OutputBurstType; /*!< Selects the output burst type.
+ This parameter can be a value of @ref ICACHE_LL_EC_Output_Burst_Type */
+} LL_ICACHE_RegionTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants -------------------------------------------------------*/
+/** @defgroup ICACHE_LL_Exported_Constants ICACHE Exported Constants
+ * @{
+ */
+
+/** @defgroup ICACHE_LL_EC_WaysSelection Ways selection
+ * @{
+ */
+#define LL_ICACHE_1WAY 0U /*!< 1-way cache (direct mapped cache) */
+#define LL_ICACHE_2WAYS ICACHE_CR_WAYSEL /*!< 2-ways set associative cache (default) */
+/**
+ * @}
+ */
+
+/** @defgroup ICACHE_LL_EC_Monitor_Type Monitor type
+ * @{
+ */
+#define LL_ICACHE_MONITOR_HIT ICACHE_CR_HITMEN /*!< Hit monitor counter */
+#define LL_ICACHE_MONITOR_MISS ICACHE_CR_MISSMEN /*!< Miss monitor counter */
+#define LL_ICACHE_MONITOR_ALL (ICACHE_CR_HITMEN | ICACHE_CR_MISSMEN) /*!< All monitors counters */
+/**
+ * @}
+ */
+
+/** @defgroup ICACHE_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_ICACHE_ReadReg function
+ * @{
+ */
+#define LL_ICACHE_SR_BUSYF ICACHE_SR_BUSYF /*!< Busy flag */
+#define LL_ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF /*!< Busy end flag */
+#define LL_ICACHE_SR_ERRF ICACHE_SR_ERRF /*!< Cache error flag */
+/**
+ * @}
+ */
+
+/** @defgroup ICACHE_LL_EC_CLEAR_FLAG Clear Flags Defines
+ * @brief Flags defines which can be used with LL_ICACHE_WriteReg function
+ * @{
+ */
+#define LL_ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF /*!< Busy end flag */
+#define LL_ICACHE_FCR_CERRF ICACHE_FCR_CERRF /*!< Cache error flag */
+/**
+ * @}
+ */
+
+/** @defgroup ICACHE_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_ICACHE_ReadReg and LL_ICACHE_WriteReg functions
+ * @{
+ */
+#define LL_ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE /*!< Busy end interrupt */
+#define LL_ICACHE_IER_ERRIE ICACHE_IER_ERRIE /*!< Cache error interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup ICACHE_LL_EC_Region Remapped Region number
+ * @{
+ */
+#define LL_ICACHE_REGION_0 0U /*!< Region 0 */
+#define LL_ICACHE_REGION_1 1U /*!< Region 1 */
+#define LL_ICACHE_REGION_2 2U /*!< Region 2 */
+#define LL_ICACHE_REGION_3 3U /*!< Region 3 */
+/**
+ * @}
+ */
+
+/** @defgroup ICACHE_LL_EC_Region_Size Remapped Region size
+ * @{
+ */
+#define LL_ICACHE_REGIONSIZE_2MB 1U /*!< Region size 2MB */
+#define LL_ICACHE_REGIONSIZE_4MB 2U /*!< Region size 4MB */
+#define LL_ICACHE_REGIONSIZE_8MB 3U /*!< Region size 8MB */
+#define LL_ICACHE_REGIONSIZE_16MB 4U /*!< Region size 16MB */
+#define LL_ICACHE_REGIONSIZE_32MB 5U /*!< Region size 32MB */
+#define LL_ICACHE_REGIONSIZE_64MB 6U /*!< Region size 64MB */
+#define LL_ICACHE_REGIONSIZE_128MB 7U /*!< Region size 128MB */
+/**
+ * @}
+ */
+
+/** @defgroup ICACHE_LL_EC_Traffic_Route Remapped Traffic route
+ * @{
+ */
+#define LL_ICACHE_MASTER1_PORT 0U /*!< Master1 port */
+#define LL_ICACHE_MASTER2_PORT ICACHE_CRRx_MSTSEL /*!< Master2 port */
+/**
+ * @}
+ */
+
+/** @defgroup ICACHE_LL_EC_Output_Burst_Type Remapped Output burst type
+ * @{
+ */
+#define LL_ICACHE_OUTPUT_BURST_WRAP 0U /*!< WRAP */
+#define LL_ICACHE_OUTPUT_BURST_INCR ICACHE_CRRx_HBURST /*!< INCR */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros ----------------------------------------------------------*/
+/** @defgroup ICACHE_LL_Exported_Macros ICACHE Exported Macros
+ * @{
+ */
+
+/** @defgroup ICACHE_LL_EM_WRITE_READ Common write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in ICACHE register
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_ICACHE_WriteReg(__REG__, __VALUE__) WRITE_REG(ICACHE->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in ICACHE register
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_ICACHE_ReadReg(__REG__) READ_REG(ICACHE->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup ICACHE_LL_Exported_Functions ICACHE Exported Functions
+ * @{
+ */
+
+/** @defgroup ICACHE_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Enable the ICACHE.
+ * @rmtoll CR EN LL_ICACHE_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_ICACHE_Enable(void)
+{
+ SET_BIT(ICACHE->CR, ICACHE_CR_EN);
+}
+
+/**
+ * @brief Disable the ICACHE.
+ * @rmtoll CR EN LL_ICACHE_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_ICACHE_Disable(void)
+{
+ CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN);
+}
+
+/**
+ * @brief Return if ICACHE is enabled or not.
+ * @rmtoll CR EN LL_ICACHE_IsEnabled
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ICACHE_IsEnabled(void)
+{
+ return ((READ_BIT(ICACHE->CR, ICACHE_CR_EN) == (ICACHE_CR_EN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Select the ICACHE operating mode.
+ * @rmtoll CR WAYSEL LL_ICACHE_SetMode
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_ICACHE_1WAY
+ * @arg @ref LL_ICACHE_2WAYS
+ * @retval None
+ */
+__STATIC_INLINE void LL_ICACHE_SetMode(uint32_t Mode)
+{
+ MODIFY_REG(ICACHE->CR, ICACHE_CR_WAYSEL, Mode);
+}
+
+/**
+ * @brief Get the selected ICACHE operating mode.
+ * @rmtoll CR WAYSEL LL_ICACHE_GetMode
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ICACHE_1WAY
+ * @arg @ref LL_ICACHE_2WAYS
+ */
+__STATIC_INLINE uint32_t LL_ICACHE_GetMode(void)
+{
+ return (READ_BIT(ICACHE->CR, ICACHE_CR_WAYSEL));
+}
+
+/**
+ * @brief Invalidate the ICACHE.
+ * @note Until the BSYEND flag is set, the cache is bypassed.
+ * @rmtoll CR CACHEINV LL_ICACHE_Invalidate
+ * @retval None
+ */
+__STATIC_INLINE void LL_ICACHE_Invalidate(void)
+{
+ SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ICACHE_LL_EF_Monitors Monitors
+ * @{
+ */
+
+/**
+ * @brief Enable the hit/miss monitor(s).
+ * @rmtoll CR HITMEN LL_ICACHE_EnableMonitors
+ * @rmtoll CR MISSMEN LL_ICACHE_EnableMonitors
+ * @param Monitors This parameter can be one or a combination of the following values:
+ * @arg @ref LL_ICACHE_MONITOR_HIT
+ * @arg @ref LL_ICACHE_MONITOR_MISS
+ * @arg @ref LL_ICACHE_MONITOR_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_ICACHE_EnableMonitors(uint32_t Monitors)
+{
+ SET_BIT(ICACHE->CR, Monitors);
+}
+
+/**
+ * @brief Disable the hit/miss monitor(s).
+ * @rmtoll CR HITMEN LL_ICACHE_DisableMonitors
+ * @rmtoll CR MISSMEN LL_ICACHE_DisableMonitors
+ * @param Monitors This parameter can be one or a combination of the following values:
+ * @arg @ref LL_ICACHE_MONITOR_HIT
+ * @arg @ref LL_ICACHE_MONITOR_MISS
+ * @arg @ref LL_ICACHE_MONITOR_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_ICACHE_DisableMonitors(uint32_t Monitors)
+{
+ CLEAR_BIT(ICACHE->CR, Monitors);
+}
+
+/**
+ * @brief Check if the monitor(s) is(are) enabled or disabled.
+ * @rmtoll CR HITMEN LL_ICACHE_IsEnabledMonitors
+ * @rmtoll CR MISSMEN LL_ICACHE_IsEnabledMonitors
+ * @param Monitors This parameter can be one or a combination of the following values:
+ * @arg @ref LL_ICACHE_MONITOR_HIT
+ * @arg @ref LL_ICACHE_MONITOR_MISS
+ * @arg @ref LL_ICACHE_MONITOR_ALL
+ * @retval State of parameter value (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledMonitors(uint32_t Monitors)
+{
+ return ((READ_BIT(ICACHE->CR, Monitors) == (Monitors)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Reset the hit/miss monitor(s).
+ * @rmtoll CR HITMRST LL_ICACHE_ResetMonitors
+ * @rmtoll CR MISSMRST LL_ICACHE_ResetMonitors
+ * @param Monitors This parameter can be one or a combination of the following values:
+ * @arg @ref LL_ICACHE_MONITOR_HIT
+ * @arg @ref LL_ICACHE_MONITOR_MISS
+ * @arg @ref LL_ICACHE_MONITOR_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_ICACHE_ResetMonitors(uint32_t Monitors)
+{
+ /* Reset */
+ SET_BIT(ICACHE->CR, (Monitors << 2U));
+ /* Release reset */
+ CLEAR_BIT(ICACHE->CR, (Monitors << 2U));
+}
+
+/**
+ * @brief Get the Hit monitor.
+ * @note Upon reaching the 32-bit maximum value, hit monitor does not wrap.
+ * @rmtoll HMONR HITMON LL_ICACHE_GetHitMonitor
+ * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_ICACHE_GetHitMonitor(void)
+{
+ return (ICACHE->HMONR);
+}
+
+/**
+ * @brief Get the Miss monitor.
+ * @note Upon reaching the 16-bit maximum value, miss monitor does not wrap.
+ * @rmtoll MMONR MISSMON LL_ICACHE_GetMissMonitor
+ * @retval Value between Min_Data=0 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_ICACHE_GetMissMonitor(void)
+{
+ return (ICACHE->MMONR);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ICACHE_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable BSYEND interrupt.
+ * @rmtoll IER BSYENDIE LL_ICACHE_EnableIT_BSYEND
+ * @retval None
+ */
+__STATIC_INLINE void LL_ICACHE_EnableIT_BSYEND(void)
+{
+ SET_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);
+}
+
+/**
+ * @brief Disable BSYEND interrupt.
+ * @rmtoll IER BSYENDIE LL_ICACHE_DisableIT_BSYEND
+ * @retval None
+ */
+__STATIC_INLINE void LL_ICACHE_DisableIT_BSYEND(void)
+{
+ CLEAR_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);
+}
+
+/**
+ * @brief Check if the BSYEND Interrupt is enabled or disabled.
+ * @rmtoll IER BSYENDIE LL_ICACHE_IsEnabledIT_BSYEND
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT_BSYEND(void)
+{
+ return ((READ_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE) == (ICACHE_IER_BSYENDIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable ERR interrupt.
+ * @rmtoll IER ERRIE LL_ICACHE_EnableIT_ERR
+ * @retval None
+ */
+__STATIC_INLINE void LL_ICACHE_EnableIT_ERR(void)
+{
+ SET_BIT(ICACHE->IER, ICACHE_IER_ERRIE);
+}
+
+/**
+ * @brief Disable ERR interrupt.
+ * @rmtoll IER ERRIE LL_ICACHE_DisableIT_ERR
+ * @retval None
+ */
+__STATIC_INLINE void LL_ICACHE_DisableIT_ERR(void)
+{
+ CLEAR_BIT(ICACHE->IER, ICACHE_IER_ERRIE);
+}
+
+/**
+ * @brief Check if the ERR Interrupt is enabled or disabled.
+ * @rmtoll IER ERRIE LL_ICACHE_IsEnabledIT_ERR
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT_ERR(void)
+{
+ return ((READ_BIT(ICACHE->IER, ICACHE_IER_ERRIE) == (ICACHE_IER_ERRIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ICACHE_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Indicate the status of an ongoing operation flag.
+ * @rmtoll SR BUSYF LL_ICACHE_IsActiveFlag_BUSY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_BUSY(void)
+{
+ return ((READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) == (ICACHE_SR_BUSYF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of an operation end flag.
+ * @rmtoll SR BSYEND LL_ICACHE_IsActiveFlag_BSYEND
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_BSYEND(void)
+{
+ return ((READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == (ICACHE_SR_BSYENDF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of an error flag.
+ * @rmtoll SR ERRF LL_ICACHE_IsActiveFlag_ERR
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_ERR(void)
+{
+ return ((READ_BIT(ICACHE->SR, ICACHE_SR_ERRF) == (ICACHE_SR_ERRF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear busy end of operation flag.
+ * @rmtoll FCR CBSYENDF LL_ICACHE_ClearFlag_BSYEND
+ * @retval None
+ */
+__STATIC_INLINE void LL_ICACHE_ClearFlag_BSYEND(void)
+{
+ WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
+}
+
+/**
+ * @brief Clear error flag.
+ * @rmtoll FCR ERRF LL_ICACHE_ClearFlag_ERR
+ * @retval None
+ */
+__STATIC_INLINE void LL_ICACHE_ClearFlag_ERR(void)
+{
+ WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ICACHE_LL_EF_REGION_Management REGION_Management
+ * @{
+ */
+
+/**
+ * @brief Enable the remapped memory region.
+ * @note The region must have been already configured.
+ * @rmtoll CRRx REN LL_ICACHE_EnableRegion
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_ICACHE_REGION_0
+ * @arg @ref LL_ICACHE_REGION_1
+ * @arg @ref LL_ICACHE_REGION_2
+ * @arg @ref LL_ICACHE_REGION_3
+ * @retval None
+ */
+__STATIC_INLINE void LL_ICACHE_EnableRegion(uint32_t Region)
+{
+ SET_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
+ ICACHE_CRRx_REN);
+}
+
+/**
+ * @brief Disable the remapped memory region.
+ * @rmtoll CRRx REN LL_ICACHE_DisableRegion
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_ICACHE_REGION_0
+ * @arg @ref LL_ICACHE_REGION_1
+ * @arg @ref LL_ICACHE_REGION_2
+ * @arg @ref LL_ICACHE_REGION_3
+ * @retval None
+ */
+__STATIC_INLINE void LL_ICACHE_DisableRegion(uint32_t Region)
+{
+ CLEAR_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
+ ICACHE_CRRx_REN);
+}
+
+/**
+ * @brief Return if remapped memory region is enabled or not.
+ * @rmtoll CRRx REN LL_ICACHE_IsEnabledRegion
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_ICACHE_REGION_0
+ * @arg @ref LL_ICACHE_REGION_1
+ * @arg @ref LL_ICACHE_REGION_2
+ * @arg @ref LL_ICACHE_REGION_3
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledRegion(uint32_t Region)
+{
+ return ((READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
+ ICACHE_CRRx_REN) == (ICACHE_CRRx_REN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Select the memory remapped region base address.
+ * @rmtoll CRRx BASEADDR LL_ICACHE_SetRegionBaseAddress
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_ICACHE_REGION_0
+ * @arg @ref LL_ICACHE_REGION_1
+ * @arg @ref LL_ICACHE_REGION_2
+ * @arg @ref LL_ICACHE_REGION_3
+ * @param Address Alias address in the Code region
+ * @retval None
+ */
+__STATIC_INLINE void LL_ICACHE_SetRegionBaseAddress(uint32_t Region, uint32_t Address)
+{
+ MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
+ ICACHE_CRRx_BASEADDR, (((Address & 0x1FFFFFFFU) >> 21U) & ICACHE_CRRx_BASEADDR));
+}
+
+/**
+ * @brief Get the memory remapped region base address.
+ * @note The base address is the alias in the Code region.
+ * @rmtoll CRRx BASEADDR LL_ICACHE_GetRegionBaseAddress
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_ICACHE_REGION_0
+ * @arg @ref LL_ICACHE_REGION_1
+ * @arg @ref LL_ICACHE_REGION_2
+ * @arg @ref LL_ICACHE_REGION_3
+ * @retval Address Alias address in the Code region
+ */
+__STATIC_INLINE uint32_t LL_ICACHE_GetRegionBaseAddress(uint32_t Region)
+{
+ return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
+ ICACHE_CRRx_BASEADDR));
+}
+
+/**
+ * @brief Select the memory remapped region remap address.
+ * @rmtoll CRRx REMAPADDR LL_ICACHE_SetRegionRemapAddress
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_ICACHE_REGION_0
+ * @arg @ref LL_ICACHE_REGION_1
+ * @arg @ref LL_ICACHE_REGION_2
+ * @arg @ref LL_ICACHE_REGION_3
+ * @param Address External memory address
+ * @retval None
+ */
+__STATIC_INLINE void LL_ICACHE_SetRegionRemapAddress(uint32_t Region, uint32_t Address)
+{
+ MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
+ ICACHE_CRRx_REMAPADDR, ((Address >> 21U) << ICACHE_CRRx_REMAPADDR_Pos));
+}
+
+/**
+ * @brief Get the memory remapped region base address.
+ * @rmtoll CRRx REMAPADDR LL_ICACHE_GetRegionRemapAddress
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_ICACHE_REGION_0
+ * @arg @ref LL_ICACHE_REGION_1
+ * @arg @ref LL_ICACHE_REGION_2
+ * @arg @ref LL_ICACHE_REGION_3
+ * @retval Address External memory address
+ */
+__STATIC_INLINE uint32_t LL_ICACHE_GetRegionRemapAddress(uint32_t Region)
+{
+ return ((READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
+ ICACHE_CRRx_REMAPADDR) >> ICACHE_CRRx_REMAPADDR_Pos) << 21U);
+}
+
+/**
+ * @brief Select the memory remapped region size.
+ * @rmtoll CRRx RSIZE LL_ICACHE_SetRegionSize
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_ICACHE_REGION_0
+ * @arg @ref LL_ICACHE_REGION_1
+ * @arg @ref LL_ICACHE_REGION_2
+ * @arg @ref LL_ICACHE_REGION_3
+ * @param Size This parameter can be one of the following values:
+ * @arg @ref LL_ICACHE_REGIONSIZE_2MB
+ * @arg @ref LL_ICACHE_REGIONSIZE_4MB
+ * @arg @ref LL_ICACHE_REGIONSIZE_8MB
+ * @arg @ref LL_ICACHE_REGIONSIZE_16MB
+ * @arg @ref LL_ICACHE_REGIONSIZE_32MB
+ * @arg @ref LL_ICACHE_REGIONSIZE_64MB
+ * @arg @ref LL_ICACHE_REGIONSIZE_128MB
+ * @retval None
+ */
+__STATIC_INLINE void LL_ICACHE_SetRegionSize(uint32_t Region, uint32_t Size)
+{
+ MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
+ ICACHE_CRRx_RSIZE, (Size << ICACHE_CRRx_RSIZE_Pos));
+}
+
+/**
+ * @brief Get the selected the memory remapped region size.
+ * @rmtoll CRRx RSIZE LL_ICACHE_GetRegionSize
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_ICACHE_REGION_0
+ * @arg @ref LL_ICACHE_REGION_1
+ * @arg @ref LL_ICACHE_REGION_2
+ * @arg @ref LL_ICACHE_REGION_3
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ICACHE_REGIONSIZE_2MB
+ * @arg @ref LL_ICACHE_REGIONSIZE_4MB
+ * @arg @ref LL_ICACHE_REGIONSIZE_8MB
+ * @arg @ref LL_ICACHE_REGIONSIZE_16MB
+ * @arg @ref LL_ICACHE_REGIONSIZE_32MB
+ * @arg @ref LL_ICACHE_REGIONSIZE_64MB
+ * @arg @ref LL_ICACHE_REGIONSIZE_128MB
+ */
+__STATIC_INLINE uint32_t LL_ICACHE_GetRegionSize(uint32_t Region)
+{
+ return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
+ ICACHE_CRRx_RSIZE) >> ICACHE_CRRx_RSIZE_Pos);
+}
+
+/**
+ * @brief Select the memory remapped region output burst type.
+ * @rmtoll CRRx HBURST LL_ICACHE_SetRegionOutputBurstType
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_ICACHE_REGION_0
+ * @arg @ref LL_ICACHE_REGION_1
+ * @arg @ref LL_ICACHE_REGION_2
+ * @arg @ref LL_ICACHE_REGION_3
+ * @param Type This parameter can be one of the following values:
+ * @arg @ref LL_ICACHE_OUTPUT_BURST_WRAP
+ * @arg @ref LL_ICACHE_OUTPUT_BURST_INCR
+ * @retval None
+ */
+__STATIC_INLINE void LL_ICACHE_SetRegionOutputBurstType(uint32_t Region, uint32_t Type)
+{
+ MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
+ ICACHE_CRRx_HBURST, Type);
+}
+
+/**
+ * @brief Get the selected the memory remapped region output burst type.
+ * @rmtoll CRRx HBURST LL_ICACHE_GetRegionOutputBurstType
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_ICACHE_REGION_0
+ * @arg @ref LL_ICACHE_REGION_1
+ * @arg @ref LL_ICACHE_REGION_2
+ * @arg @ref LL_ICACHE_REGION_3
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ICACHE_OUTPUT_BURST_WRAP
+ * @arg @ref LL_ICACHE_OUTPUT_BURST_INCR
+ */
+__STATIC_INLINE uint32_t LL_ICACHE_GetRegionOutputBurstType(uint32_t Region)
+{
+ return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
+ ICACHE_CRRx_HBURST));
+}
+
+/**
+ * @brief Select the memory remapped region cache master port.
+ * @rmtoll CRRx MSTSEL LL_ICACHE_SetRegionMasterPort
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_ICACHE_REGION_0
+ * @arg @ref LL_ICACHE_REGION_1
+ * @arg @ref LL_ICACHE_REGION_2
+ * @arg @ref LL_ICACHE_REGION_3
+ * @param Port This parameter can be one of the following values:
+ * @arg @ref LL_ICACHE_MASTER1_PORT
+ * @arg @ref LL_ICACHE_MASTER2_PORT
+ * @retval None
+ */
+__STATIC_INLINE void LL_ICACHE_SetRegionMasterPort(uint32_t Region, uint32_t Port)
+{
+ MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
+ ICACHE_CRRx_MSTSEL, Port);
+}
+
+/**
+ * @brief Get the selected the memory remapped region cache master port.
+ * @rmtoll CRRx MSTSEL LL_ICACHE_GetRegionMasterPort
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_ICACHE_REGION_0
+ * @arg @ref LL_ICACHE_REGION_1
+ * @arg @ref LL_ICACHE_REGION_2
+ * @arg @ref LL_ICACHE_REGION_3
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ICACHE_MASTER1_PORT
+ * @arg @ref LL_ICACHE_MASTER2_PORT
+ */
+__STATIC_INLINE uint32_t LL_ICACHE_GetRegionMasterPort(uint32_t Region)
+{
+ return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
+ ICACHE_CRRx_MSTSEL));
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup ICACHE_LL_EF_REGION_Init Region Initialization functions
+ * @{
+ */
+
+void LL_ICACHE_ConfigRegion(uint32_t Region, const LL_ICACHE_RegionTypeDef *const pICACHE_RegionStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* ICACHE */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_LL_ICACHE_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_iwdg.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_iwdg.h
new file mode 100644
index 00000000..d0be0932
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_iwdg.h
@@ -0,0 +1,442 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_iwdg.h
+ * @author MCD Application Team
+ * @brief Header file of IWDG LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_LL_IWDG_H
+#define STM32U5xx_LL_IWDG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx.h"
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined(IWDG)
+
+/** @defgroup IWDG_LL IWDG
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
+ * @{
+ */
+#define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */
+#define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */
+#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */
+#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants
+ * @{
+ */
+
+/** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_IWDG_ReadReg function
+ * @{
+ */
+#define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */
+#define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */
+#define LL_IWDG_SR_WVU IWDG_SR_WVU /*!< Watchdog counter window value update */
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider
+ * @{
+ */
+#define LL_IWDG_PRESCALER_4 0x00000000U /*!< Divider by 4 */
+#define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0) /*!< Divider by 8 */
+#define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1) /*!< Divider by 16 */
+#define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 32 */
+#define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2) /*!< Divider by 64 */
+#define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< Divider by 128 */
+#define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< Divider by 256 */
+#define LL_IWDG_PRESCALER_512 (IWDG_PR_PR_2 | IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 512 */
+#define LL_IWDG_PRESCALER_1024 IWDG_PR_PR_3 /*!< Divider by 1024 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros
+ * @{
+ */
+
+/** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in IWDG register
+ * @param __INSTANCE__ IWDG Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in IWDG register
+ * @param __INSTANCE__ IWDG Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions
+ * @{
+ */
+/** @defgroup IWDG_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Start the Independent Watchdog
+ * @note Except if the hardware watchdog option is selected
+ * @rmtoll KR KEY LL_IWDG_Enable
+ * @param IWDGx IWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
+{
+ WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE);
+}
+
+/**
+ * @brief Reloads IWDG counter with value defined in the reload register
+ * @rmtoll KR KEY LL_IWDG_ReloadCounter
+ * @param IWDGx IWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
+{
+ WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD);
+}
+
+/**
+ * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
+ * @rmtoll KR KEY LL_IWDG_EnableWriteAccess
+ * @param IWDGx IWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
+{
+ WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
+}
+
+/**
+ * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
+ * @rmtoll KR KEY LL_IWDG_DisableWriteAccess
+ * @param IWDGx IWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)
+{
+ WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
+}
+
+/**
+ * @brief Select the prescaler of the IWDG
+ * @rmtoll PR PR LL_IWDG_SetPrescaler
+ * @param IWDGx IWDG Instance
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_IWDG_PRESCALER_4
+ * @arg @ref LL_IWDG_PRESCALER_8
+ * @arg @ref LL_IWDG_PRESCALER_16
+ * @arg @ref LL_IWDG_PRESCALER_32
+ * @arg @ref LL_IWDG_PRESCALER_64
+ * @arg @ref LL_IWDG_PRESCALER_128
+ * @arg @ref LL_IWDG_PRESCALER_256
+ * @arg @ref LL_IWDG_PRESCALER_512
+ * @arg @ref LL_IWDG_PRESCALER_1024
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler)
+{
+ WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler);
+}
+
+/**
+ * @brief Get the selected prescaler of the IWDG
+ * @rmtoll PR PR LL_IWDG_GetPrescaler
+ * @param IWDGx IWDG Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_IWDG_PRESCALER_4
+ * @arg @ref LL_IWDG_PRESCALER_8
+ * @arg @ref LL_IWDG_PRESCALER_16
+ * @arg @ref LL_IWDG_PRESCALER_32
+ * @arg @ref LL_IWDG_PRESCALER_64
+ * @arg @ref LL_IWDG_PRESCALER_128
+ * @arg @ref LL_IWDG_PRESCALER_256
+ * @arg @ref LL_IWDG_PRESCALER_512
+ * @arg @ref LL_IWDG_PRESCALER_1024
+ */
+__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx)
+{
+ return (READ_REG(IWDGx->PR));
+}
+
+/**
+ * @brief Specify the IWDG down-counter reload value
+ * @rmtoll RLR RL LL_IWDG_SetReloadCounter
+ * @param IWDGx IWDG Instance
+ * @param Counter Value between Min_Data=0 and Max_Data=0x0FFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter)
+{
+ WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter);
+}
+
+/**
+ * @brief Get the specified IWDG down-counter reload value
+ * @rmtoll RLR RL LL_IWDG_GetReloadCounter
+ * @param IWDGx IWDG Instance
+ * @retval Value between Min_Data=0 and Max_Data=0x0FFF
+ */
+__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
+{
+ return (READ_REG(IWDGx->RLR));
+}
+
+/**
+ * @brief Specify high limit of the window value to be compared to the down-counter.
+ * @rmtoll WINR WIN LL_IWDG_SetWindow
+ * @param IWDGx IWDG Instance
+ * @param Window Value between Min_Data=0 and Max_Data=0x0FFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window)
+{
+ WRITE_REG(IWDGx->WINR, IWDG_WINR_WIN & Window);
+}
+
+/**
+ * @brief Get the high limit of the window value specified.
+ * @rmtoll WINR WIN LL_IWDG_GetWindow
+ * @param IWDGx IWDG Instance
+ * @retval Value between Min_Data=0 and Max_Data=0x0FFF
+ */
+__STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx)
+{
+ return (READ_REG(IWDGx->WINR));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Specify comparator value that will be used to trig Early Wakeup interrupt
+ * @rmtoll EWCR EWIT LL_IWDG_SetEwiTime
+ * @param IWDGx IWDG Instance
+ * @param Time Value between Min_Data=0 and Max_Data=0x0FFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_SetEwiTime(IWDG_TypeDef *IWDGx, uint32_t Time)
+{
+ MODIFY_REG(IWDGx->EWCR, IWDG_EWCR_EWIT, Time);
+}
+
+/**
+ * @brief Get the Early Wakeup interrupt comparator value
+ * @rmtoll EWCR EWIT LL_IWDG_GetEwiTime
+ * @param IWDGx IWDG Instance
+ * @retval Value between Min_Data=0 and Max_Data=0x0FFF
+ */
+__STATIC_INLINE uint32_t LL_IWDG_GetEwiTime(IWDG_TypeDef *IWDGx)
+{
+ return (READ_BIT(IWDGx->EWCR, IWDG_EWCR_EWIT));
+}
+
+/**
+ * @brief Enable Early wakeup interrupt
+ * @rmtoll EWCR EWIE LL_IWDG_EnableIT_EWI
+ * @param IWDGx IWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_EnableIT_EWI(IWDG_TypeDef *IWDGx)
+{
+ SET_BIT(IWDGx->EWCR, IWDG_EWCR_EWIE);
+}
+
+/**
+ * @brief Disable Early wakeup interrupt
+ * @rmtoll EWCR EWIE LL_IWDG_DisableIT_EWI
+ * @param IWDGx IWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_DisableIT_EWI(IWDG_TypeDef *IWDGx)
+{
+ CLEAR_BIT(IWDGx->EWCR, IWDG_EWCR_EWIE);
+}
+
+/**
+ * @brief Indicates whether Early wakeup interrupt is enable
+ * @rmtoll EWCR EWIE LL_IWDG_IsEnableIT_EWI
+ * @param IWDGx IWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_IWDG_IsEnableIT_EWI(IWDG_TypeDef *IWDGx)
+{
+ return ((READ_BIT(IWDGx->EWCR, IWDG_EWCR_EWIE) == (IWDG_EWCR_EWIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Check if flag Prescaler Value Update is set or not
+ * @rmtoll SR PVU LL_IWDG_IsActiveFlag_PVU
+ * @param IWDGx IWDG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
+{
+ return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if flag Reload Value Update is set or not
+ * @rmtoll SR RVU LL_IWDG_IsActiveFlag_RVU
+ * @param IWDGx IWDG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
+{
+ return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if flag Window Value Update is set or not
+ * @rmtoll SR WVU LL_IWDG_IsActiveFlag_WVU
+ * @param IWDGx IWDG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx)
+{
+ return ((READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if flag EWI Value Update is set or not
+ * @rmtoll SR EVU LL_IWDG_IsActiveFlag_EWU
+ * @param IWDGx IWDG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_EWU(IWDG_TypeDef *IWDGx)
+{
+ return ((READ_BIT(IWDGx->SR, IWDG_SR_EWU) == (IWDG_SR_EWU)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if all flags Prescaler, Reload, Window & Early Interrupt Value Update are reset or not
+ * @rmtoll SR PVU LL_IWDG_IsReady\n
+ * SR RVU LL_IWDG_IsReady\n
+ * SR WVU LL_IWDG_IsReady\n
+ * SR EWU LL_IWDG_IsReady
+ * @param IWDGx IWDG Instance
+ * @retval State of bits (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
+{
+ return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU | IWDG_SR_EWU) == 0U) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Early Wakeup interrupt flag is set or not
+ * @rmtoll SR EWIF LL_IWDG_IsActiveFlag_EWIF
+ * @param IWDGx IWDG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_EWIF(IWDG_TypeDef *IWDGx)
+{
+ return ((READ_BIT(IWDGx->SR, IWDG_SR_EWIF) == (IWDG_SR_EWIF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the Early Wakeup interrupt flag
+ * @rmtoll EWCR EWIC LL_IWDG_ClearFlag_EWIF
+ * @param IWDGx IWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_ClearFlag_EWIF(IWDG_TypeDef *IWDGx)
+{
+ SET_BIT(IWDGx->EWCR, IWDG_EWCR_EWIC);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* IWDG */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_LL_IWDG_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lpgpio.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lpgpio.h
new file mode 100644
index 00000000..dc886319
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lpgpio.h
@@ -0,0 +1,456 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_lpgpio.h
+ * @author MCD Application Team
+ * @brief Header file of LPGPIO LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_LL_LPGPIO_H
+#define STM32U5xx_LL_LPGPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx.h"
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined (LPGPIO1)
+
+/** @defgroup LPGPIO_LL LPGPIO
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPGPIO_LL_Private_Macros LPGPIO Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPGPIO_LL_ES_INIT LPGPIO Exported Init structures
+ * @{
+ */
+
+/**
+ * @brief LL LPGPIO Init Structure definition
+ */
+typedef struct
+{
+ uint32_t Pin; /*!< Specifies the LPGPIO pins to be configured.
+ This parameter can be any value of @ref LPGPIO_LL_EC_PIN */
+
+ uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref LPGPIO_LL_EC_MODE.*/
+
+} LL_LPGPIO_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup LPGPIO_LL_Exported_Constants LPGPIO Exported Constants
+ * @{
+ */
+
+/** @defgroup LPGPIO_LL_EC_PIN PIN
+ * @{
+ */
+#define LL_LPGPIO_PIN_0 LPGPIO_BSRR_BS0 /*!< Select pin 0 */
+#define LL_LPGPIO_PIN_1 LPGPIO_BSRR_BS1 /*!< Select pin 1 */
+#define LL_LPGPIO_PIN_2 LPGPIO_BSRR_BS2 /*!< Select pin 2 */
+#define LL_LPGPIO_PIN_3 LPGPIO_BSRR_BS3 /*!< Select pin 3 */
+#define LL_LPGPIO_PIN_4 LPGPIO_BSRR_BS4 /*!< Select pin 4 */
+#define LL_LPGPIO_PIN_5 LPGPIO_BSRR_BS5 /*!< Select pin 5 */
+#define LL_LPGPIO_PIN_6 LPGPIO_BSRR_BS6 /*!< Select pin 6 */
+#define LL_LPGPIO_PIN_7 LPGPIO_BSRR_BS7 /*!< Select pin 7 */
+#define LL_LPGPIO_PIN_8 LPGPIO_BSRR_BS8 /*!< Select pin 8 */
+#define LL_LPGPIO_PIN_9 LPGPIO_BSRR_BS9 /*!< Select pin 9 */
+#define LL_LPGPIO_PIN_10 LPGPIO_BSRR_BS10 /*!< Select pin 10 */
+#define LL_LPGPIO_PIN_11 LPGPIO_BSRR_BS11 /*!< Select pin 11 */
+#define LL_LPGPIO_PIN_12 LPGPIO_BSRR_BS12 /*!< Select pin 12 */
+#define LL_LPGPIO_PIN_13 LPGPIO_BSRR_BS13 /*!< Select pin 13 */
+#define LL_LPGPIO_PIN_14 LPGPIO_BSRR_BS14 /*!< Select pin 14 */
+#define LL_LPGPIO_PIN_15 LPGPIO_BSRR_BS15 /*!< Select pin 15 */
+#define LL_LPGPIO_PIN_ALL (LPGPIO_BSRR_BS0 | LPGPIO_BSRR_BS1 | LPGPIO_BSRR_BS2 | \
+ LPGPIO_BSRR_BS3 | LPGPIO_BSRR_BS4 | LPGPIO_BSRR_BS5 | \
+ LPGPIO_BSRR_BS6 | LPGPIO_BSRR_BS7 | LPGPIO_BSRR_BS8 | \
+ LPGPIO_BSRR_BS9 | LPGPIO_BSRR_BS10 | LPGPIO_BSRR_BS11 | \
+ LPGPIO_BSRR_BS12 | LPGPIO_BSRR_BS13 | LPGPIO_BSRR_BS14 | \
+ LPGPIO_BSRR_BS15) /*!< Select all pins */
+/**
+ * @}
+ */
+
+/** @defgroup LPGPIO_LL_EC_MODE Mode
+ * @{
+ */
+#define LL_LPGPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */
+#define LL_LPGPIO_MODE_OUTPUT LPGPIO_MODER_MOD0 /*!< Select output mode */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup LPGPIO_LL_Exported_Macros LPGPIO Exported Macros
+ * @{
+ */
+
+/** @defgroup LPGPIO_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in LPGPIO register
+ * @param __INSTANCE__ LPGPIO Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_LPGPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in LPGPIO register
+ * @param __INSTANCE__ LPGPIO Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_LPGPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup LPGPIO_LL_Exported_Functions LPGPIO Exported Functions
+ * @{
+ */
+
+/** @defgroup LPGPIO_LL_EF_Port_Configuration Port Configuration
+ * @{
+ */
+
+/**
+ * @brief Configure lpgpio mode for a dedicated pin on dedicated port.
+ * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll MODER MODEy LL_LPGPIO_SetPinMode
+ * @param LPGPIOx LPGPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_LPGPIO_PIN_0
+ * @arg @ref LL_LPGPIO_PIN_1
+ * @arg @ref LL_LPGPIO_PIN_2
+ * @arg @ref LL_LPGPIO_PIN_3
+ * @arg @ref LL_LPGPIO_PIN_4
+ * @arg @ref LL_LPGPIO_PIN_5
+ * @arg @ref LL_LPGPIO_PIN_6
+ * @arg @ref LL_LPGPIO_PIN_7
+ * @arg @ref LL_LPGPIO_PIN_8
+ * @arg @ref LL_LPGPIO_PIN_9
+ * @arg @ref LL_LPGPIO_PIN_10
+ * @arg @ref LL_LPGPIO_PIN_11
+ * @arg @ref LL_LPGPIO_PIN_12
+ * @arg @ref LL_LPGPIO_PIN_13
+ * @arg @ref LL_LPGPIO_PIN_14
+ * @arg @ref LL_LPGPIO_PIN_15
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_LPGPIO_MODE_INPUT
+ * @arg @ref LL_LPGPIO_MODE_OUTPUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPGPIO_SetPinMode(GPIO_TypeDef *LPGPIOx, uint32_t Pin, uint32_t Mode)
+{
+ MODIFY_REG(LPGPIOx->MODER, (LPGPIO_MODER_MOD0 << (POSITION_VAL(Pin))), (Mode << (POSITION_VAL(Pin))));
+}
+
+/**
+ * @brief Return lpgpio mode for a dedicated pin on dedicated port.
+ * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll MODER MODEy LL_LPGPIO_GetPinMode
+ * @param LPGPIOx LPGPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_LPGPIO_PIN_0
+ * @arg @ref LL_LPGPIO_PIN_1
+ * @arg @ref LL_LPGPIO_PIN_2
+ * @arg @ref LL_LPGPIO_PIN_3
+ * @arg @ref LL_LPGPIO_PIN_4
+ * @arg @ref LL_LPGPIO_PIN_5
+ * @arg @ref LL_LPGPIO_PIN_6
+ * @arg @ref LL_LPGPIO_PIN_7
+ * @arg @ref LL_LPGPIO_PIN_8
+ * @arg @ref LL_LPGPIO_PIN_9
+ * @arg @ref LL_LPGPIO_PIN_10
+ * @arg @ref LL_LPGPIO_PIN_11
+ * @arg @ref LL_LPGPIO_PIN_12
+ * @arg @ref LL_LPGPIO_PIN_13
+ * @arg @ref LL_LPGPIO_PIN_14
+ * @arg @ref LL_LPGPIO_PIN_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPGPIO_MODE_INPUT
+ * @arg @ref LL_LPGPIO_MODE_OUTPUT
+ */
+__STATIC_INLINE uint32_t LL_LPGPIO_GetPinMode(GPIO_TypeDef *LPGPIOx, uint32_t Pin)
+{
+ return (uint32_t)(READ_BIT(LPGPIOx->MODER,
+ (LPGPIO_MODER_MOD0 << (POSITION_VAL(Pin)))) >> (POSITION_VAL(Pin)));
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup LPGPIO_LL_EF_Data_Access Data Access
+ * @{
+ */
+
+/**
+ * @brief Return full input data register value for a dedicated port.
+ * @rmtoll IDR IDy LL_LPGPIO_ReadInputPort
+ * @param LPGPIOx LPGPIO Port
+ * @retval Input data register value of port
+ */
+__STATIC_INLINE uint32_t LL_LPGPIO_ReadInputPort(GPIO_TypeDef *LPGPIOx)
+{
+ return (uint32_t)(READ_REG(LPGPIOx->IDR));
+}
+
+/**
+ * @brief Return if input data level for several pins of dedicated port is high or low.
+ * @rmtoll IDR IDy LL_LPGPIO_IsInputPinSet
+ * @param LPGPIOx LPGPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_LPGPIO_PIN_0
+ * @arg @ref LL_LPGPIO_PIN_1
+ * @arg @ref LL_LPGPIO_PIN_2
+ * @arg @ref LL_LPGPIO_PIN_3
+ * @arg @ref LL_LPGPIO_PIN_4
+ * @arg @ref LL_LPGPIO_PIN_5
+ * @arg @ref LL_LPGPIO_PIN_6
+ * @arg @ref LL_LPGPIO_PIN_7
+ * @arg @ref LL_LPGPIO_PIN_8
+ * @arg @ref LL_LPGPIO_PIN_9
+ * @arg @ref LL_LPGPIO_PIN_10
+ * @arg @ref LL_LPGPIO_PIN_11
+ * @arg @ref LL_LPGPIO_PIN_12
+ * @arg @ref LL_LPGPIO_PIN_13
+ * @arg @ref LL_LPGPIO_PIN_14
+ * @arg @ref LL_LPGPIO_PIN_15
+ * @arg @ref LL_LPGPIO_PIN_ALL
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPGPIO_IsInputPinSet(GPIO_TypeDef *LPGPIOx, uint32_t PinMask)
+{
+ return ((READ_BIT(LPGPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Write output data register for the port.
+ * @rmtoll ODR ODy LL_LPGPIO_WriteOutputPort
+ * @param LPGPIOx LPGPIO Port
+ * @param PortValue Level value for each pin of the port
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPGPIO_WriteOutputPort(GPIO_TypeDef *LPGPIOx, uint32_t PortValue)
+{
+ WRITE_REG(LPGPIOx->ODR, PortValue);
+}
+
+/**
+ * @brief Return full output data register value for a dedicated port.
+ * @rmtoll ODR ODy LL_LPGPIO_ReadOutputPort
+ * @param LPGPIOx LPGPIO Port
+ * @retval Output data register value of port
+ */
+__STATIC_INLINE uint32_t LL_LPGPIO_ReadOutputPort(GPIO_TypeDef *LPGPIOx)
+{
+ return (uint32_t)(READ_REG(LPGPIOx->ODR));
+}
+
+/**
+ * @brief Return if input data level for several pins of dedicated port is high or low.
+ * @rmtoll ODR ODy LL_LPGPIO_IsOutputPinSet
+ * @param LPGPIOx LPGPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_LPGPIO_PIN_0
+ * @arg @ref LL_LPGPIO_PIN_1
+ * @arg @ref LL_LPGPIO_PIN_2
+ * @arg @ref LL_LPGPIO_PIN_3
+ * @arg @ref LL_LPGPIO_PIN_4
+ * @arg @ref LL_LPGPIO_PIN_5
+ * @arg @ref LL_LPGPIO_PIN_6
+ * @arg @ref LL_LPGPIO_PIN_7
+ * @arg @ref LL_LPGPIO_PIN_8
+ * @arg @ref LL_LPGPIO_PIN_9
+ * @arg @ref LL_LPGPIO_PIN_10
+ * @arg @ref LL_LPGPIO_PIN_11
+ * @arg @ref LL_LPGPIO_PIN_12
+ * @arg @ref LL_LPGPIO_PIN_13
+ * @arg @ref LL_LPGPIO_PIN_14
+ * @arg @ref LL_LPGPIO_PIN_15
+ * @arg @ref LL_LPGPIO_PIN_ALL
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPGPIO_IsOutputPinSet(GPIO_TypeDef *LPGPIOx, uint32_t PinMask)
+{
+ return ((READ_BIT(LPGPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set several pins to high level on dedicated gpio port.
+ * @rmtoll BSRR BSy LL_LPGPIO_SetOutputPin
+ * @param LPGPIOx LPGPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_LPGPIO_PIN_0
+ * @arg @ref LL_LPGPIO_PIN_1
+ * @arg @ref LL_LPGPIO_PIN_2
+ * @arg @ref LL_LPGPIO_PIN_3
+ * @arg @ref LL_LPGPIO_PIN_4
+ * @arg @ref LL_LPGPIO_PIN_5
+ * @arg @ref LL_LPGPIO_PIN_6
+ * @arg @ref LL_LPGPIO_PIN_7
+ * @arg @ref LL_LPGPIO_PIN_8
+ * @arg @ref LL_LPGPIO_PIN_9
+ * @arg @ref LL_LPGPIO_PIN_10
+ * @arg @ref LL_LPGPIO_PIN_11
+ * @arg @ref LL_LPGPIO_PIN_12
+ * @arg @ref LL_LPGPIO_PIN_13
+ * @arg @ref LL_LPGPIO_PIN_14
+ * @arg @ref LL_LPGPIO_PIN_15
+ * @arg @ref LL_LPGPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPGPIO_SetOutputPin(GPIO_TypeDef *LPGPIOx, uint32_t PinMask)
+{
+ WRITE_REG(LPGPIOx->BSRR, PinMask);
+}
+
+/**
+ * @brief Set several pins to low level on dedicated gpio port.
+ * @rmtoll BRR BRy LL_LPGPIO_ResetOutputPin
+ * @param LPGPIOx LPGPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_LPGPIO_PIN_0
+ * @arg @ref LL_LPGPIO_PIN_1
+ * @arg @ref LL_LPGPIO_PIN_2
+ * @arg @ref LL_LPGPIO_PIN_3
+ * @arg @ref LL_LPGPIO_PIN_4
+ * @arg @ref LL_LPGPIO_PIN_5
+ * @arg @ref LL_LPGPIO_PIN_6
+ * @arg @ref LL_LPGPIO_PIN_7
+ * @arg @ref LL_LPGPIO_PIN_8
+ * @arg @ref LL_LPGPIO_PIN_9
+ * @arg @ref LL_LPGPIO_PIN_10
+ * @arg @ref LL_LPGPIO_PIN_11
+ * @arg @ref LL_LPGPIO_PIN_12
+ * @arg @ref LL_LPGPIO_PIN_13
+ * @arg @ref LL_LPGPIO_PIN_14
+ * @arg @ref LL_LPGPIO_PIN_15
+ * @arg @ref LL_LPGPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPGPIO_ResetOutputPin(GPIO_TypeDef *LPGPIOx, uint32_t PinMask)
+{
+ WRITE_REG(LPGPIOx->BRR, PinMask);
+}
+
+/**
+ * @brief Toggle data value for several pin of dedicated port.
+ * @rmtoll ODR ODy LL_LPGPIO_TogglePin
+ * @param LPGPIOx LPGPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_LPGPIO_PIN_0
+ * @arg @ref LL_LPGPIO_PIN_1
+ * @arg @ref LL_LPGPIO_PIN_2
+ * @arg @ref LL_LPGPIO_PIN_3
+ * @arg @ref LL_LPGPIO_PIN_4
+ * @arg @ref LL_LPGPIO_PIN_5
+ * @arg @ref LL_LPGPIO_PIN_6
+ * @arg @ref LL_LPGPIO_PIN_7
+ * @arg @ref LL_LPGPIO_PIN_8
+ * @arg @ref LL_LPGPIO_PIN_9
+ * @arg @ref LL_LPGPIO_PIN_10
+ * @arg @ref LL_LPGPIO_PIN_11
+ * @arg @ref LL_LPGPIO_PIN_12
+ * @arg @ref LL_LPGPIO_PIN_13
+ * @arg @ref LL_LPGPIO_PIN_14
+ * @arg @ref LL_LPGPIO_PIN_15
+ * @arg @ref LL_LPGPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPGPIO_TogglePin(GPIO_TypeDef *LPGPIOx, uint32_t PinMask)
+{
+ WRITE_REG(LPGPIOx->ODR, READ_REG(LPGPIOx->ODR) ^ PinMask);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_LPGPIO_DeInit(GPIO_TypeDef *LPGPIOx);
+ErrorStatus LL_LPGPIO_Init(GPIO_TypeDef *LPGPIOx, const LL_LPGPIO_InitTypeDef *const LPGPIO_InitStruct);
+void LL_LPGPIO_StructInit(LL_LPGPIO_InitTypeDef *LPGPIO_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+#endif /* defined (LPGPIO1) */
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_LL_LPGPIO_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lptim.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lptim.h
new file mode 100644
index 00000000..81946fb4
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lptim.h
@@ -0,0 +1,2392 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_lptim.h
+ * @author MCD Application Team
+ * @brief Header file of LPTIM LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_LL_LPTIM_H
+#define STM32U5xx_LL_LPTIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx.h"
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3) || defined (LPTIM4)
+
+/** @defgroup LPTIM_LL LPTIM
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup LPTIM_LL_Private_variables LPTIM Private variables
+ * @{
+ */
+
+static const uint8_t LL_LPTIM_SHIFT_TAB_CCxP[] =
+{
+ 0U, /* CC1P */
+ 16U /* CC2P */
+};
+
+static const uint8_t LL_LPTIM_SHIFT_TAB_ICxF[] =
+{
+ 0U, /* IC1F */
+ 16U /* IC2F */
+};
+
+static const uint8_t LL_LPTIM_SHIFT_TAB_ICxPSC[] =
+{
+ 0U, /* IC1PSC */
+ 16U /* IC2PSC */
+};
+
+static const uint8_t LL_LPTIM_SHIFT_TAB_CCxSEL[] =
+{
+ 0U, /* CC1SEL */
+ 16U /* CC2SEL */
+};
+
+static const uint8_t LL_LPTIM_SHIFT_TAB_CCxE[] =
+{
+ LPTIM_CCMR1_CC1E_Pos, /* CC1E */
+ LPTIM_CCMR1_CC2E_Pos /* CC2E */
+};
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief LPTIM Init structure definition
+ */
+typedef struct
+{
+ uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance.
+ This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_LPTIM_SetClockSource().*/
+
+ uint32_t Prescaler; /*!< Specifies the prescaler division ratio.
+ This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
+
+ This feature can be modified afterwards using using unitary
+ function @ref LL_LPTIM_SetPrescaler().*/
+
+ uint32_t Waveform; /*!< Specifies the waveform shape.
+ This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_LPTIM_SetWaveform().*/
+} LL_LPTIM_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants
+ * @{
+ */
+
+/** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_LPTIM_ReadReg function
+ * @{
+ */
+#define LL_LPTIM_ISR_CMP1OK LPTIM_ISR_CMP1OK /*!< Compare register 1 update OK */
+#define LL_LPTIM_ISR_CMP2OK LPTIM_ISR_CMP2OK /*!< Compare register 2 update OK */
+#define LL_LPTIM_ISR_CC1IF LPTIM_ISR_CC1IF /*!< Capture/Compare 1 interrupt flag */
+#define LL_LPTIM_ISR_CC2IF LPTIM_ISR_CC2IF /*!< Capture/Compare 2 interrupt flag */
+#define LL_LPTIM_ISR_CC1OF LPTIM_ISR_CC1OF /*!< Capture/Compare 1 over-capture flag */
+#define LL_LPTIM_ISR_CC2OF LPTIM_ISR_CC2OF /*!< Capture/Compare 2 over-capture flag */
+#define LL_LPTIM_ISR_DIEROK LPTIM_ISR_DIEROK /*!< Interrupt enable register update OK */
+#define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */
+#define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */
+#define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */
+#define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */
+#define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */
+#define LL_LPTIM_ISR_UE LPTIM_ISR_UE /*!< Update event */
+#define LL_LPTIM_ISR_REPOK LPTIM_ISR_REPOK /*!< Repetition register update OK */
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions
+ * @{
+ */
+#define LL_LPTIM_DIER_CMP1OKIE LPTIM_DIER_CMP1OKIE /*!< Compare register 1 update OK */
+#define LL_LPTIM_DIER_CMP2OKIE LPTIM_DIER_CMP2OKIE /*!< Compare register 2 update OK */
+#define LL_LPTIM_DIER_CC1IFIE LPTIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt flag */
+#define LL_LPTIM_DIER_CC2IFIE LPTIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt flag */
+#define LL_LPTIM_DIER_CC1OFIE LPTIM_DIER_CC1OIE /*!< Capture/Compare 1 over-capture flag */
+#define LL_LPTIM_DIER_CC2OFIE LPTIM_DIER_CC2OIE /*!< Capture/Compare 2 over-capture flag */
+#define LL_LPTIM_DIER_ARRMIE LPTIM_DIER_ARRMIE /*!< Autoreload match */
+#define LL_LPTIM_DIER_EXTTRIGIE LPTIM_DIER_EXTTRIGIE /*!< External trigger edge event */
+#define LL_LPTIM_DIER_ARROKIE LPTIM_DIER_ARROKIE /*!< Autoreload register update OK */
+#define LL_LPTIM_DIER_UPIE LPTIM_DIER_UPIE /*!< Counter direction change down to up */
+#define LL_LPTIM_DIER_DOWNIE LPTIM_DIER_DOWNIE /*!< Counter direction change up to down */
+#define LL_LPTIM_DIER_UEIE LPTIM_DIER_UEIE /*!< Update event */
+#define LL_LPTIM_DIER_REPOKIE LPTIM_DIER_REPOKIE /*!< Repetition register update OK */
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
+ * @{
+ */
+#define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in LPTIM register
+ * @param __INSTANCE__ LPTIM Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
+ * @{
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
+ * @{
+ */
+
+ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx);
+void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
+ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
+ * @{
+ */
+
+/**
+ * @brief Enable the LPTIM instance
+ * @note After setting the ENABLE bit, a delay of two counter clock is needed
+ * before the LPTIM instance is actually enabled.
+ * @rmtoll CR ENABLE LL_LPTIM_Enable
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
+}
+
+/**
+ * @brief Disable the LPTIM instance
+ * @rmtoll CR ENABLE LL_LPTIM_Disable
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
+}
+
+/**
+ * @brief Indicates whether the LPTIM instance is enabled.
+ * @rmtoll CR ENABLE LL_LPTIM_IsEnabled
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));
+}
+
+/**
+ * @brief Starts the LPTIM counter in the desired mode.
+ * @note LPTIM instance must be enabled before starting the counter.
+ * @note It is possible to change on the fly from One Shot mode to
+ * Continuous mode.
+ * @rmtoll CR CNTSTRT LL_LPTIM_StartCounter\n
+ * CR SNGSTRT LL_LPTIM_StartCounter
+ * @param LPTIMx Low-Power Timer instance
+ * @param OperatingMode This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS
+ * @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
+{
+ MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode);
+}
+
+/**
+ * @brief Enable reset after read.
+ * @note After calling this function any read access to LPTIM_CNT
+ * register will asynchronously reset the LPTIM_CNT register content.
+ * @rmtoll CR RSTARE LL_LPTIM_EnableResetAfterRead
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
+}
+
+/**
+ * @brief Disable reset after read.
+ * @rmtoll CR RSTARE LL_LPTIM_DisableResetAfterRead
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
+}
+
+/**
+ * @brief Indicate whether the reset after read feature is enabled.
+ * @rmtoll CR RSTARE LL_LPTIM_IsEnabledResetAfterRead
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(LPTIM_TypeDef *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL));
+}
+
+/**
+ * @brief Reset of the LPTIM_CNT counter register (synchronous).
+ * @note Due to the synchronous nature of this reset, it only takes
+ * place after a synchronization delay of 3 LPTIM core clock cycles
+ * (LPTIM core clock may be different from APB clock).
+ * @note COUNTRST is automatically cleared by hardware
+ * @rmtoll CR COUNTRST LL_LPTIM_ResetCounter\n
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_ResetCounter(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->CR, LPTIM_CR_COUNTRST);
+}
+
+/**
+ * @brief Set the LPTIM registers update mode (enable/disable register preload)
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @rmtoll CFGR PRELOAD LL_LPTIM_SetUpdateMode
+ * @param LPTIMx Low-Power Timer instance
+ * @param UpdateMode This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
+ * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
+{
+ MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode);
+}
+
+/**
+ * @brief Get the LPTIM registers update mode
+ * @rmtoll CFGR PRELOAD LL_LPTIM_GetUpdateMode
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
+ * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
+}
+
+/**
+ * @brief Set the auto reload value
+ * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
+ * @note After a write to the LPTIMx_ARR register a new write operation to the
+ * same register can only be performed when the previous write operation
+ * is completed. Any successive write before the ARROK flag is set, will
+ * lead to unpredictable results.
+ * @note autoreload value be strictly greater than the compare value.
+ * @rmtoll ARR ARR LL_LPTIM_SetAutoReload
+ * @param LPTIMx Low-Power Timer instance
+ * @param AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
+{
+ MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload);
+}
+
+/**
+ * @brief Get actual auto reload value
+ * @rmtoll ARR ARR LL_LPTIM_GetAutoReload
+ * @param LPTIMx Low-Power Timer instance
+ * @retval AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
+}
+
+/**
+ * @brief Set the repetition value
+ * @note The LPTIMx_RCR register content must only be modified when the LPTIM is enabled
+ * @rmtoll RCR REP LL_LPTIM_SetRepetition
+ * @param LPTIMx Low-Power Timer instance
+ * @param Repetition Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_SetRepetition(LPTIM_TypeDef *LPTIMx, uint32_t Repetition)
+{
+ MODIFY_REG(LPTIMx->RCR, LPTIM_RCR_REP, Repetition);
+}
+
+/**
+ * @brief Get the repetition value
+ * @rmtoll RCR REP LL_LPTIM_GetRepetition
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Repetition Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_GetRepetition(LPTIM_TypeDef *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->RCR, LPTIM_RCR_REP));
+}
+
+/**
+ * @brief Enable capture/compare channel.
+ * @rmtoll CCMR1 CC1E LL_LPTIM_CC_EnableChannel\n
+ * CCMR1 CC2E LL_LPTIM_CC_EnableChannel
+ * @param LPTIMx LPTimer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_CHANNEL_CH1
+ * @arg @ref LL_LPTIM_CHANNEL_CH2
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_CC_EnableChannel(LPTIM_TypeDef *LPTIMx, uint32_t Channel)
+{
+ SET_BIT(LPTIMx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]);
+}
+
+/**
+ * @brief Disable capture/compare channel.
+ * @rmtoll CCMR1 CC1E LL_LPTIM_CC_DisableChannel\n
+ * CCMR1 CC2E LL_LPTIM_CC_DisableChannel
+ * @param LPTIMx LPTimer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_CHANNEL_CH1
+ * @arg @ref LL_LPTIM_CHANNEL_CH2
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_CC_DisableChannel(LPTIM_TypeDef *LPTIMx, uint32_t Channel)
+{
+ CLEAR_BIT(LPTIMx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]);
+}
+
+/**
+ * @brief Indicate whether channel is enabled.
+ * @rmtoll CCMR1 CC1E LL_LPTIM_CC_IsEnabledChannel\n
+ * CCMR1 CC2E LL_LPTIM_CC_IsEnabledChannel
+ * @param LPTIMx LPTimer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_CHANNEL_CH1
+ * @arg @ref LL_LPTIM_CHANNEL_CH2
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_CC_IsEnabledChannel(LPTIM_TypeDef *LPTIMx, uint32_t Channel)
+{
+ return ((READ_BIT(LPTIMx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]) == \
+ (0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel])) ? 1UL : 0UL);
+
+}
+
+/**
+ * @brief Set the compare value
+ * @note After a write to the LPTIMx_CCR1 register a new write operation to the
+ * same register can only be performed when the previous write operation
+ * is completed. Any successive write before the CMP1OK flag is set, will
+ * lead to unpredictable results.
+ * @rmtoll CCR1 CCR1 LL_LPTIM_SetCompareCH1
+ * @param LPTIMx Low-Power Timer instance
+ * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_SetCompareCH1(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
+{
+ MODIFY_REG(LPTIMx->CCR1, LPTIM_CCR1_CCR1, CompareValue);
+}
+
+/**
+ * @brief Get actual compare value
+ * @rmtoll CCR1 CCR1 LL_LPTIM_GetCompareCH1
+ * @param LPTIMx Low-Power Timer instance
+ * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_GetCompareCH1(LPTIM_TypeDef *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CCR1, LPTIM_CCR1_CCR1));
+}
+
+/**
+ * @brief Set the compare value
+ * @note After a write to the LPTIMx_CCR2 register a new write operation to the
+ * same register can only be performed when the previous write operation
+ * is completed. Any successive write before the CMP2OK flag is set, will
+ * lead to unpredictable results.
+ * @rmtoll CCR2 CCR2 LL_LPTIM_SetCompareCH2
+ * @param LPTIMx Low-Power Timer instance
+ * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_SetCompareCH2(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
+{
+ MODIFY_REG(LPTIMx->CCR2, LPTIM_CCR2_CCR2, CompareValue);
+}
+
+/**
+ * @brief Get actual compare value
+ * @rmtoll CCR2 CCR2 LL_LPTIM_GetCompareCH2
+ * @param LPTIMx Low-Power Timer instance
+ * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_GetCompareCH2(LPTIM_TypeDef *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CCR2, LPTIM_CCR2_CCR2));
+}
+
+/**
+ * @brief Get actual counter value
+ * @note When the LPTIM instance is running with an asynchronous clock, reading
+ * the LPTIMx_CNT register may return unreliable values. So in this case
+ * it is necessary to perform two consecutive read accesses and verify
+ * that the two returned values are identical.
+ * @rmtoll CNT CNT LL_LPTIM_GetCounter
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Counter value
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(LPTIM_TypeDef *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
+}
+
+/**
+ * @brief Set the counter mode (selection of the LPTIM counter clock source).
+ * @note The counter mode can be set only when the LPTIM instance is disabled.
+ * @rmtoll CFGR COUNTMODE LL_LPTIM_SetCounterMode
+ * @param LPTIMx Low-Power Timer instance
+ * @param CounterMode This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
+ * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
+{
+ MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode);
+}
+
+/**
+ * @brief Get the counter mode
+ * @rmtoll CFGR COUNTMODE LL_LPTIM_GetCounterMode
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
+ * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(LPTIM_TypeDef *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
+}
+
+/**
+ * @brief Set waveform shape
+ * @rmtoll CFGR WAVE LL_LPTIM_SetWaveform
+ * @param LPTIMx Low-Power Timer instance
+ * @param Waveform This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
+ * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
+{
+ MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform);
+}
+
+/**
+ * @brief Get actual waveform shape
+ * @rmtoll CFGR WAVE LL_LPTIM_GetWaveform
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
+ * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(LPTIM_TypeDef *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
+}
+
+/**
+ * @brief Set the polarity of an output channel.
+ * @rmtoll CCMR1 CC1P LL_LPTIM_OC_SetPolarity\n
+ * @rmtoll CCMR1 CC2P LL_LPTIM_OC_SetPolarity\n
+ * @param LPTIMx Low-Power Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_CHANNEL_CH1
+ * @arg @ref LL_LPTIM_CHANNEL_CH2
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
+ * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_OC_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Polarity)
+{
+ if (LPTIMx == LPTIM4)
+ {
+ MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, ((Polarity >> LPTIM_CCMR1_CC1P_Pos) << LPTIM_CFGR_WAVPOL_Pos));
+ }
+ else
+ {
+ MODIFY_REG(LPTIMx->CCMR1, (LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel]),
+ (Polarity << LL_LPTIM_SHIFT_TAB_CCxP[Channel]));
+ }
+}
+
+/**
+ * @brief Get the polarity of an output channel.
+ * @rmtoll CCMR1 CC1P LL_LPTIM_OC_GetPolarity\n
+ * @rmtoll CCMR1 CC2P LL_LPTIM_OC_GetPolarity\n
+ * @param LPTIMx Low-Power Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_CHANNEL_CH1
+ * @arg @ref LL_LPTIM_CHANNEL_CH2
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
+ * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_OC_GetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Channel)
+{
+ if (LPTIMx == LPTIM4)
+ {
+ return (uint32_t)((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL) >> LPTIM_CFGR_WAVPOL_Pos) << LPTIM_CCMR1_CC1P_Pos);
+ }
+ else
+ {
+ return (uint32_t)(READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel]) >> \
+ LL_LPTIM_SHIFT_TAB_CCxP[Channel]);
+ }
+}
+
+/**
+ * @brief Set actual prescaler division ratio.
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @note When the LPTIM is configured to be clocked by an internal clock source
+ * and the LPTIM counter is configured to be updated by active edges
+ * detected on the LPTIM external Input1, the internal clock provided to
+ * the LPTIM must be not be prescaled.
+ * @rmtoll CFGR PRESC LL_LPTIM_SetPrescaler
+ * @param LPTIMx Low-Power Timer instance
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_PRESCALER_DIV1
+ * @arg @ref LL_LPTIM_PRESCALER_DIV2
+ * @arg @ref LL_LPTIM_PRESCALER_DIV4
+ * @arg @ref LL_LPTIM_PRESCALER_DIV8
+ * @arg @ref LL_LPTIM_PRESCALER_DIV16
+ * @arg @ref LL_LPTIM_PRESCALER_DIV32
+ * @arg @ref LL_LPTIM_PRESCALER_DIV64
+ * @arg @ref LL_LPTIM_PRESCALER_DIV128
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
+{
+ MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler);
+}
+
+/**
+ * @brief Get actual prescaler division ratio.
+ * @rmtoll CFGR PRESC LL_LPTIM_GetPrescaler
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPTIM_PRESCALER_DIV1
+ * @arg @ref LL_LPTIM_PRESCALER_DIV2
+ * @arg @ref LL_LPTIM_PRESCALER_DIV4
+ * @arg @ref LL_LPTIM_PRESCALER_DIV8
+ * @arg @ref LL_LPTIM_PRESCALER_DIV16
+ * @arg @ref LL_LPTIM_PRESCALER_DIV32
+ * @arg @ref LL_LPTIM_PRESCALER_DIV64
+ * @arg @ref LL_LPTIM_PRESCALER_DIV128
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
+}
+
+/**
+ * @brief Set LPTIM input 1 source (default GPIO).
+ * @rmtoll CFGR2 IN1SEL LL_LPTIM_SetInput1Src
+ * @param LPTIMx Low-Power Timer instance
+ * @param Src This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_INPUT1_SRC_GPIO
+ * @arg @ref LL_LPTIM_INPUT1_SRC_COMP1
+ * @arg @ref LL_LPTIM_INPUT1_SRC_COMP2 (*)
+ * (*) Value not defined for all devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
+{
+ MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN1SEL, Src);
+}
+
+/**
+ * @brief Set LPTIM input 2 source (default GPIO).
+ * @rmtoll CFGR2 IN2SEL LL_LPTIM_SetInput2Src
+ * @param LPTIMx Low-Power Timer instance
+ * @param Src This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_INPUT2_SRC_GPIO
+ * @arg @ref LL_LPTIM_INPUT2_SRC_COMP2
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
+{
+ MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN2SEL, Src);
+}
+
+/**
+ * @brief Set LPTIM input source (default GPIO).
+ * @rmtoll CFGR2 IC1SEL LL_LPTIM_SetRemap
+ * @rmtoll CFGR2 IC2SEL LL_LPTIM_SetRemap
+ * @param LPTIMx Low-Power Timer instance
+ * @param Src This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_GPIO
+ * @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_COMP1
+ * @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_COMP2
+ * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_GPIO
+ * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_LSI
+ * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_LSE
+ * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_GPIO
+ * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_HSI
+ * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_MSIS_1024
+ * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_MSIS_4
+ * @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_GPIO
+ * @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_COMP1
+ * @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_COMP2
+ * @arg @ref LL_LPTIM_LPTIM3_IC1_RMP_GPIO
+ * @arg @ref LL_LPTIM_LPTIM3_IC1_RMP_COMP1
+ * @arg @ref LL_LPTIM_LPTIM3_IC1_RMP_COMP2
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_SetRemap(LPTIM_TypeDef *LPTIMx, uint32_t Src)
+{
+ MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IC1SEL | LPTIM_CFGR2_IC2SEL, Src);
+}
+
+/**
+ * @brief Set the polarity of IC channel 1.
+ * @rmtoll CCMR1 CC1P LL_LPTIM_IC_SetPolarity\n
+ * @rmtoll CCMR1 CC2P LL_LPTIM_IC_SetPolarity\n
+ * @param LPTIMx Low-Power Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_CHANNEL_CH1
+ * @arg @ref LL_LPTIM_CHANNEL_CH2
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_ICPOLARITY_RISING
+ * @arg @ref LL_LPTIM_ICPOLARITY_FALLING
+ * @arg @ref LL_LPTIM_ICPOLARITY_RISING_FALLING
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_IC_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Polarity)
+{
+ MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel],
+ Polarity << LL_LPTIM_SHIFT_TAB_CCxP[Channel]);
+}
+
+/**
+ * @brief Get the polarity of IC channels.
+ * @rmtoll CCMR1 CC1P LL_LPTIM_IC_GetPolarity\n
+ * @rmtoll CCMR1 CC2P LL_LPTIM_IC_GetPolarity\n
+ * @param LPTIMx Low-Power Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_CHANNEL_CH1
+ * @arg @ref LL_LPTIM_CHANNEL_CH2
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPTIM_ICPOLARITY_RISING
+ * @arg @ref LL_LPTIM_ICPOLARITY_FALLING
+ * @arg @ref LL_LPTIM_ICPOLARITY_RISING_FALLING
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IC_GetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Channel)
+{
+ return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel])) >> \
+ LL_LPTIM_SHIFT_TAB_CCxP[Channel]);
+
+}
+
+/**
+ * @brief Set the filter of IC channels.
+ * @rmtoll CCMR1 IC1F LL_LPTIM_IC_SetFilter\n
+ * @rmtoll CCMR1 IC2F LL_LPTIM_IC_SetFilter\n
+ * @param LPTIMx Low-Power Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_CHANNEL_CH1
+ * @arg @ref LL_LPTIM_CHANNEL_CH2
+ * @param Filter This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1
+ * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2
+ * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4
+ * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_IC_SetFilter(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Filter)
+{
+ MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_IC1F << LL_LPTIM_SHIFT_TAB_ICxF[Channel],
+ Filter << LL_LPTIM_SHIFT_TAB_ICxF[Channel]);
+}
+
+/**
+ * @brief Get the filter of IC channels.
+ * @rmtoll CCMR1 IC1F LL_LPTIM_IC_GetFilter\n
+ * @rmtoll CCMR1 IC2F LL_LPTIM_IC_GetFilter\n
+ * @param LPTIMx Low-Power Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_CHANNEL_CH1
+ * @arg @ref LL_LPTIM_CHANNEL_CH2
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1
+ * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2
+ * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4
+ * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IC_GetFilter(LPTIM_TypeDef *LPTIMx, uint32_t Channel)
+{
+ return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_IC1F << LL_LPTIM_SHIFT_TAB_ICxF[Channel])) >> \
+ LL_LPTIM_SHIFT_TAB_ICxF[Channel]);
+}
+
+/**
+ * @brief Set the prescaler of IC channels.
+ * @rmtoll CCMR1 IC1PSC LL_LPTIM_IC_SetPrescaler\n
+ * @rmtoll CCMR1 IC2PSC LL_LPTIM_IC_SetPrescaler\n
+ * @param LPTIMx Low-Power Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_CHANNEL_CH1
+ * @arg @ref LL_LPTIM_CHANNEL_CH2
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_ICPSC_DIV1
+ * @arg @ref LL_LPTIM_ICPSC_DIV2
+ * @arg @ref LL_LPTIM_ICPSC_DIV4
+ * @arg @ref LL_LPTIM_ICPSC_DIV8
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_IC_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Prescaler)
+{
+ MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_IC1PSC << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel],
+ Prescaler << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel]);
+}
+
+/**
+ * @brief Get the prescaler of IC channels.
+ * @rmtoll CCMR1 IC1PSC LL_LPTIM_IC_GetPrescaler\n
+ * @rmtoll CCMR1 IC2PSC LL_LPTIM_IC_GetPrescaler\n
+ * @param LPTIMx Low-Power Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_CHANNEL_CH1
+ * @arg @ref LL_LPTIM_CHANNEL_CH2
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPTIM_ICPSC_DIV1
+ * @arg @ref LL_LPTIM_ICPSC_DIV2
+ * @arg @ref LL_LPTIM_ICPSC_DIV4
+ * @arg @ref LL_LPTIM_ICPSC_DIV8
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IC_GetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Channel)
+{
+ return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_IC1PSC << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel])) >> \
+ LL_LPTIM_SHIFT_TAB_ICxPSC[Channel]);
+}
+
+/**
+ * @brief Set the Channel Mode.
+ * @rmtoll CCMR1 CC1SEL LL_LPTIM_CC_SetChannelMode\n
+ * CCMR1 CC2SEL LL_LPTIM_CC_SetChannelMode
+ * @param LPTIMx Low-Power Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_CHANNEL_CH1
+ * @arg @ref LL_LPTIM_CHANNEL_CH2
+ * @param CCMode This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_CCMODE_OUTPUT_PWM
+ * @arg @ref LL_LPTIM_CCMODE_INPUTCAPTURE
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_CC_SetChannelMode(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t CCMode)
+{
+ SET_BIT(LPTIMx->CCMR1, CCMode << LL_LPTIM_SHIFT_TAB_CCxSEL[Channel]);
+}
+
+/**
+ * @brief Get the Channel Mode.
+ * @rmtoll CCMR1 CC1SEL LL_LPTIM_CC_GetChannelMode\n
+ * CCMR1 CC2SEL LL_LPTIM_CC_GetChannelMode
+ * @param LPTIMx Low-Power Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_CHANNEL_CH1
+ * @arg @ref LL_LPTIM_CHANNEL_CH2
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPTIM_CCMODE_OUTPUT_PWM
+ * @arg @ref LL_LPTIM_CCMODE_INPUTCAPTURE
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_CC_GetChannelMode(LPTIM_TypeDef *LPTIMx, uint32_t Channel)
+{
+ return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_CC1SEL << LL_LPTIM_SHIFT_TAB_CCxSEL[Channel])) >> \
+ LL_LPTIM_SHIFT_TAB_CCxSEL[Channel]);
+}
+
+/**
+ * @brief Get captured value for input channel 1.
+ * @rmtoll CCR1 CCR1 LL_LPTIM_IC_GetCaptureCH1
+ * @param LPTIMx Low-Power Timer instance
+ * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IC_GetCaptureCH1(LPTIM_TypeDef *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CCR1, LPTIM_CCR1_CCR1));
+}
+
+/**
+ * @brief Get captured value for input channel 2.
+ * @rmtoll CCR2 CCR2 LL_LPTIM_IC_GetCaptureCH2
+ * @param LPTIMx Low-Power Timer instance
+ * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IC_GetCaptureCH2(LPTIM_TypeDef *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CCR2, LPTIM_CCR2_CCR2));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration
+ * @{
+ */
+
+/**
+ * @brief Enable the timeout function
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @note The first trigger event will start the timer, any successive trigger
+ * event will reset the counter and the timer will restart.
+ * @note The timeout value corresponds to the compare value; if no trigger
+ * occurs within the expected time frame, the MCU is waked-up by the
+ * compare match event.
+ * @rmtoll CFGR TIMOUT LL_LPTIM_EnableTimeout
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
+}
+
+/**
+ * @brief Disable the timeout function
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @note A trigger event arriving when the timer is already started will be
+ * ignored.
+ * @rmtoll CFGR TIMOUT LL_LPTIM_DisableTimeout
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
+}
+
+/**
+ * @brief Indicate whether the timeout function is enabled.
+ * @rmtoll CFGR TIMOUT LL_LPTIM_IsEnabledTimeout
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL));
+}
+
+/**
+ * @brief Start the LPTIM counter
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @rmtoll CFGR TRIGEN LL_LPTIM_TrigSw
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN);
+}
+
+/**
+ * @brief Configure the external trigger used as a trigger event for the LPTIM.
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @note An internal clock source must be present when a digital filter is
+ * required for the trigger.
+ * @rmtoll CFGR TRIGSEL LL_LPTIM_ConfigTrigger\n
+ * CFGR TRGFLT LL_LPTIM_ConfigTrigger\n
+ * CFGR TRIGEN LL_LPTIM_ConfigTrigger
+ * @param LPTIMx Low-Power Timer instance
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
+ * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
+ * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
+ * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
+ * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
+ * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
+ * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
+ * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
+ * @arg @ref LL_LPTIM_TRIG_SOURCE_LPDMA_CH0_TCF
+ * @arg @ref LL_LPTIM_TRIG_SOURCE_LPDMA_CH1_TCF
+ * @arg @ref LL_LPTIM_TRIG_SOURCE_LPDMA_CH2_TCF
+ * @arg @ref LL_LPTIM_TRIG_SOURCE_GPDMA_CH0_TCF
+ * @arg @ref LL_LPTIM_TRIG_SOURCE_GPDMA_CH4_TCF
+ * @param Filter This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
+ * @arg @ref LL_LPTIM_TRIG_FILTER_2
+ * @arg @ref LL_LPTIM_TRIG_FILTER_4
+ * @arg @ref LL_LPTIM_TRIG_FILTER_8
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
+ * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
+ * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
+{
+ MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity);
+}
+
+/**
+ * @brief Get actual external trigger source.
+ * @rmtoll CFGR TRIGSEL LL_LPTIM_GetTriggerSource
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
+ * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
+ * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
+ * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
+ * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
+ * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
+ * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
+ * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
+ * @arg @ref LL_LPTIM_TRIG_SOURCE_LPDMA_CH0_TCF
+ * @arg @ref LL_LPTIM_TRIG_SOURCE_LPDMA_CH1_TCF
+ * @arg @ref LL_LPTIM_TRIG_SOURCE_LPDMA_CH2_TCF
+ * @arg @ref LL_LPTIM_TRIG_SOURCE_GPDMA_CH0_TCF
+ * @arg @ref LL_LPTIM_TRIG_SOURCE_GPDMA_CH4_TCF
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
+}
+
+/**
+ * @brief Get actual external trigger filter.
+ * @rmtoll CFGR TRGFLT LL_LPTIM_GetTriggerFilter
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
+ * @arg @ref LL_LPTIM_TRIG_FILTER_2
+ * @arg @ref LL_LPTIM_TRIG_FILTER_4
+ * @arg @ref LL_LPTIM_TRIG_FILTER_8
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
+}
+
+/**
+ * @brief Get actual external trigger polarity.
+ * @rmtoll CFGR TRIGEN LL_LPTIM_GetTriggerPolarity
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
+ * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
+ * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(LPTIM_TypeDef *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration
+ * @{
+ */
+
+/**
+ * @brief Set the source of the clock used by the LPTIM instance.
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @rmtoll CFGR CKSEL LL_LPTIM_SetClockSource
+ * @param LPTIMx Low-Power Timer instance
+ * @param ClockSource This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
+ * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
+{
+ MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource);
+}
+
+/**
+ * @brief Get actual LPTIM instance clock source.
+ * @rmtoll CFGR CKSEL LL_LPTIM_GetClockSource
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
+ * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(LPTIM_TypeDef *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
+}
+
+/**
+ * @brief Configure the active edge or edges used by the counter when
+ the LPTIM is clocked by an external clock source.
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @note When both external clock signal edges are considered active ones,
+ * the LPTIM must also be clocked by an internal clock source with a
+ * frequency equal to at least four times the external clock frequency.
+ * @note An internal clock source must be present when a digital filter is
+ * required for external clock.
+ * @rmtoll CFGR CKFLT LL_LPTIM_ConfigClock\n
+ * CFGR CKPOL LL_LPTIM_ConfigClock
+ * @param LPTIMx Low-Power Timer instance
+ * @param ClockFilter This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_CLK_FILTER_NONE
+ * @arg @ref LL_LPTIM_CLK_FILTER_2
+ * @arg @ref LL_LPTIM_CLK_FILTER_4
+ * @arg @ref LL_LPTIM_CLK_FILTER_8
+ * @param ClockPolarity This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
+ * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
+ * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
+{
+ MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity);
+}
+
+/**
+ * @brief Get actual clock polarity
+ * @rmtoll CFGR CKPOL LL_LPTIM_GetClockPolarity
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
+ * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
+ * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
+}
+
+/**
+ * @brief Get actual clock digital filter
+ * @rmtoll CFGR CKFLT LL_LPTIM_GetClockFilter
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPTIM_CLK_FILTER_NONE
+ * @arg @ref LL_LPTIM_CLK_FILTER_2
+ * @arg @ref LL_LPTIM_CLK_FILTER_4
+ * @arg @ref LL_LPTIM_CLK_FILTER_8
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(LPTIM_TypeDef *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode
+ * @{
+ */
+
+/**
+ * @brief Configure the encoder mode.
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @rmtoll CFGR CKPOL LL_LPTIM_SetEncoderMode
+ * @param LPTIMx Low-Power Timer instance
+ * @param EncoderMode This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
+ * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
+ * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
+{
+ MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode);
+}
+
+/**
+ * @brief Get actual encoder mode.
+ * @rmtoll CFGR CKPOL LL_LPTIM_GetEncoderMode
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
+ * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
+ * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(LPTIM_TypeDef *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
+}
+
+/**
+ * @brief Enable the encoder mode
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @note In this mode the LPTIM instance must be clocked by an internal clock
+ * source. Also, the prescaler division ratio must be equal to 1.
+ * @note LPTIM instance must be configured in continuous mode prior enabling
+ * the encoder mode.
+ * @rmtoll CFGR ENC LL_LPTIM_EnableEncoderMode
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
+}
+
+/**
+ * @brief Disable the encoder mode
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @rmtoll CFGR ENC LL_LPTIM_DisableEncoderMode
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
+}
+
+/**
+ * @brief Indicates whether the LPTIM operates in encoder mode.
+ * @rmtoll CFGR ENC LL_LPTIM_IsEnabledEncoderMode
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management
+ * @{
+ */
+
+/**
+ * @brief Clear the compare match flag for channel 1 (CC1CF)
+ * @rmtoll ICR CC1CF LL_LPTIM_ClearFLAG_CC1
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_ClearFLAG_CC1(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC1CF);
+}
+
+/**
+ * @brief Inform application whether a capture/compare interrupt has occurred for channel 1.
+ * @rmtoll ISR CC1IF LL_LPTIM_IsActiveFlag_CC1
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC1(LPTIM_TypeDef *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC1IF) == LPTIM_ISR_CC1IF) ? 1UL : 0UL));
+}
+
+/**
+ * @brief Clear the compare match flag for channel 2 (CC2CF)
+ * @rmtoll ICR CC2CF LL_LPTIM_ClearFLAG_CC2
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_ClearFLAG_CC2(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC2CF);
+}
+
+/**
+ * @brief Inform application whether a capture/compare interrupt has occurred for channel 2.
+ * @rmtoll ISR CC2IF LL_LPTIM_IsActiveFlag_CC2
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC2(LPTIM_TypeDef *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC2IF) == LPTIM_ISR_CC2IF) ? 1UL : 0UL));
+}
+
+/**
+ * @brief Clear the Capture/Compare 1 over-capture flag for channel 1 (CC1OCF)
+ * @rmtoll ICR CC1OCF LL_LPTIM_ClearFLAG_CC1O
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_ClearFLAG_CC1O(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC1OCF);
+}
+
+/**
+ * @brief Inform application whether a Capture/Compare 1 over-capture has occurred for channel 1.
+ * @rmtoll ISR CC1OF LL_LPTIM_IsActiveFlag_CC1O
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC1O(LPTIM_TypeDef *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC1OF) == LPTIM_ISR_CC1OF) ? 1UL : 0UL));
+}
+
+/**
+ * @brief Clear the Capture/Compare 2 over-capture flag for channel 2 (CC2OCF)
+ * @rmtoll ICR CC2OCF LL_LPTIM_ClearFLAG_CC2O
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_ClearFLAG_CC2O(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC2OCF);
+}
+
+/**
+ * @brief Inform application whether a Capture/Compare 2 over-capture has occurred for channel 2.
+ * @rmtoll ISR CC2OF LL_LPTIM_IsActiveFlag_CC2O
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC2O(LPTIM_TypeDef *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC2OF) == LPTIM_ISR_CC2OF) ? 1UL : 0UL));
+}
+/**
+ * @brief Clear the autoreload match flag (ARRMCF)
+ * @rmtoll ICR ARRMCF LL_LPTIM_ClearFLAG_ARRM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
+}
+
+/**
+ * @brief Inform application whether a autoreload match interrupt has occurred.
+ * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL));
+}
+
+/**
+ * @brief Clear the external trigger valid edge flag(EXTTRIGCF).
+ * @rmtoll ICR EXTTRIGCF LL_LPTIM_ClearFlag_EXTTRIG
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF);
+}
+
+/**
+ * @brief Inform application whether a valid edge on the selected external trigger input has occurred.
+ * @rmtoll ISR EXTTRIG LL_LPTIM_IsActiveFlag_EXTTRIG
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL));
+}
+
+/**
+ * @brief Clear the compare register update interrupt flag (CMP1OKCF).
+ * @rmtoll ICR CMP1OKCF LL_LPTIM_ClearFlag_CMP1OK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_ClearFlag_CMP1OK(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMP1OKCF);
+}
+
+/**
+ * @brief Informs application whether the APB bus write operation to the LPTIMx_CCR1 register has been successfully
+ completed. If so, a new one can be initiated.
+ * @rmtoll ISR CMP1OK LL_LPTIM_IsActiveFlag_CMP1OK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMP1OK(LPTIM_TypeDef *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMP1OK) == LPTIM_ISR_CMP1OK) ? 1UL : 0UL));
+}
+
+/**
+ * @brief Clear the compare register update interrupt flag (CMP2OKCF).
+ * @rmtoll ICR CMP2OKCF LL_LPTIM_ClearFlag_CMP2OK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_ClearFlag_CMP2OK(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMP2OKCF);
+}
+
+/**
+ * @brief Informs application whether the APB bus write operation to the LPTIMx_CCR2 register has been successfully
+ completed. If so, a new one can be initiated.
+ * @rmtoll ISR CMP2OK LL_LPTIM_IsActiveFlag_CMP2OK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMP2OK(LPTIM_TypeDef *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMP2OK) == LPTIM_ISR_CMP2OK) ? 1UL : 0UL));
+}
+
+/**
+ * @brief Clear the interrupt register update interrupt flag (DIEROKCF).
+ * @rmtoll ICR DIEROKCF LL_LPTIM_ClearFlag_DIEROK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_ClearFlag_DIEROK(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->ICR, LPTIM_ICR_DIEROKCF);
+}
+
+/**
+ * @brief Informs application whether the APB bus write operation to the LPTIMx_DIER register has been successfully
+ completed. If so, a new one can be initiated.
+ * @rmtoll ISR DIEROK LL_LPTIM_IsActiveFlag_DIEROK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DIEROK(LPTIM_TypeDef *LPTIMx)
+{
+ return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DIEROK) == (LPTIM_ISR_DIEROK)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the autoreload register update interrupt flag (ARROKCF).
+ * @rmtoll ICR ARROKCF LL_LPTIM_ClearFlag_ARROK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF);
+}
+
+/**
+ * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully
+ completed. If so, a new one can be initiated.
+ * @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL));
+}
+
+/**
+ * @brief Clear the counter direction change to up interrupt flag (UPCF).
+ * @rmtoll ICR UPCF LL_LPTIM_ClearFlag_UP
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF);
+}
+
+/**
+ * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance
+ operates in encoder mode).
+ * @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL));
+}
+
+/**
+ * @brief Clear the counter direction change to down interrupt flag (DOWNCF).
+ * @rmtoll ICR DOWNCF LL_LPTIM_ClearFlag_DOWN
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF);
+}
+
+/**
+ * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance
+ operates in encoder mode).
+ * @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL));
+}
+
+/**
+ * @brief Clear the repetition register update interrupt flag (REPOKCF).
+ * @rmtoll ICR REPOKCF LL_LPTIM_ClearFlag_REPOK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_ClearFlag_REPOK(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->ICR, LPTIM_ICR_REPOKCF);
+}
+
+/**
+ * @brief Informs application whether the APB bus write operation to the LPTIMx_RCR register has been successfully
+ completed; If so, a new one can be initiated.
+ * @rmtoll ISR REPOK LL_LPTIM_IsActiveFlag_REPOK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_REPOK(LPTIM_TypeDef *LPTIMx)
+{
+ return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_REPOK) == (LPTIM_ISR_REPOK)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the update event flag (UECF).
+ * @rmtoll ICR UECF LL_LPTIM_ClearFlag_UE
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_ClearFlag_UE(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->ICR, LPTIM_ICR_UECF);
+}
+
+/**
+ * @brief Informs application whether the LPTIMx update event has occurred.
+ * @rmtoll ISR UE LL_LPTIM_IsActiveFlag_UE
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UE(LPTIM_TypeDef *LPTIMx)
+{
+ return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UE) == (LPTIM_ISR_UE)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management
+ * @{
+ */
+/**
+ * @brief Enable capture/compare 1 interrupt (CC1IE).
+ * @rmtoll DIER CC1IE LL_LPTIM_EnableIT_CC1
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_EnableIT_CC1(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE);
+}
+
+/**
+ * @brief Disable capture/compare 1 interrupt (CC1IE).
+ * @rmtoll DIER CC1IE LL_LPTIM_DisableIT_CC1
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_DisableIT_CC1(LPTIM_TypeDef *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
+ * @rmtoll DIER CC1IE LL_LPTIM_IsEnabledIT_CC1
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC1(LPTIM_TypeDef *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE) == LPTIM_DIER_CC1IE) ? 1UL : 0UL));
+}
+
+/**
+ * @brief Enable capture/compare 1 interrupt (CC2IE).
+ * @rmtoll DIER CC2IE LL_LPTIM_EnableIT_CC2
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_EnableIT_CC2(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE);
+}
+
+/**
+ * @brief Disable capture/compare 2 interrupt (CC2IE).
+ * @rmtoll DIER CC2IE LL_LPTIM_DisableIT_CC2
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_DisableIT_CC2(LPTIM_TypeDef *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
+ * @rmtoll DIER CC2IE LL_LPTIM_IsEnabledIT_CC2
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC2(LPTIM_TypeDef *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE) == LPTIM_DIER_CC2IE) ? 1UL : 0UL));
+}
+
+/**
+ * @brief Enable capture/compare 1 over-capture interrupt (CC1OIE).
+ * @rmtoll DIER CC1OIE LL_LPTIM_EnableIT_CC1O
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_EnableIT_CC1O(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE);
+}
+
+/**
+ * @brief Disable capture/compare 1 over-capture interrup (CC1OIE).
+ * @rmtoll DIER CC1OIE LL_LPTIM_DisableIT_CC1O
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_DisableIT_CC1O(LPTIM_TypeDef *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 1 over-capture interrup (CC1OIE) is enabled.
+ * @rmtoll DIER CC1OIE LL_LPTIM_IsEnabledIT_CC1O
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC1O(LPTIM_TypeDef *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE) == LPTIM_DIER_CC1OIE) ? 1UL : 0UL));
+}
+
+/**
+ * @brief Enable capture/compare 1 over-capture interrupt (CC2OIE).
+ * @rmtoll DIER CC2OIE LL_LPTIM_EnableIT_CC2O
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_EnableIT_CC2O(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE);
+}
+
+/**
+ * @brief Disable capture/compare 1 over-capture interrup (CC2OIE).
+ * @rmtoll DIER CC2OIE LL_LPTIM_DisableIT_CC2O
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_DisableIT_CC2O(LPTIM_TypeDef *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 2 over-capture interrup (CC2OIE) is enabled.
+ * @rmtoll DIER CC2OIE LL_LPTIM_IsEnabledIT_CC2O
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC2O(LPTIM_TypeDef *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE) == LPTIM_DIER_CC2OIE) ? 1UL : 0UL));
+}
+
+/**
+ * @brief Enable autoreload match interrupt (ARRMIE).
+ * @rmtoll DIER ARRMIE LL_LPTIM_EnableIT_ARRM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE);
+}
+
+/**
+ * @brief Disable autoreload match interrupt (ARRMIE).
+ * @rmtoll DIER ARRMIE LL_LPTIM_DisableIT_ARRM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE);
+}
+
+/**
+ * @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
+ * @rmtoll DIER ARRMIE LL_LPTIM_IsEnabledIT_ARRM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE) == LPTIM_DIER_ARRMIE) ? 1UL : 0UL));
+}
+
+/**
+ * @brief Enable external trigger valid edge interrupt (EXTTRIGIE).
+ * @rmtoll DIER EXTTRIGIE LL_LPTIM_EnableIT_EXTTRIG
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE);
+}
+
+/**
+ * @brief Disable external trigger valid edge interrupt (EXTTRIGIE).
+ * @rmtoll DIER EXTTRIGIE LL_LPTIM_DisableIT_EXTTRIG
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE);
+}
+
+/**
+ * @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
+ * @rmtoll DIER EXTTRIGIE LL_LPTIM_IsEnabledIT_EXTTRIG
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE) == LPTIM_DIER_EXTTRIGIE) ? 1UL : 0UL));
+}
+
+/**
+ * @brief Enable compare register write completed interrupt (CMP1OKIE).
+ * @rmtoll IER CMP1OKIE LL_LPTIM_EnableIT_CMP1OK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_EnableIT_CMP1OK(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE);
+}
+
+/**
+ * @brief Disable compare register write completed interrupt (CMP1OKIE).
+ * @rmtoll IER CMPO1KIE LL_LPTIM_DisableIT_CMP1OK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_DisableIT_CMP1OK(LPTIM_TypeDef *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE);
+}
+
+/**
+ * @brief Indicates whether the compare register write completed interrupt (CMP1OKIE) is enabled.
+ * @rmtoll IER CMP1OKIE LL_LPTIM_IsEnabledIT_CMP1OK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMP1OK(LPTIM_TypeDef *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE) == LPTIM_DIER_CMP1OKIE) ? 1UL : 0UL));
+}
+
+/**
+ * @brief Enable compare register write completed interrupt (CMP2OKIE).
+ * @rmtoll IER CMP2OKIE LL_LPTIM_EnableIT_CMP2OK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_EnableIT_CMP2OK(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE);
+}
+
+/**
+ * @brief Disable compare register write completed interrupt (CMP2OKIE).
+ * @rmtoll IER CMP2OKIE LL_LPTIM_DisableIT_CMP2OK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_DisableIT_CMP2OK(LPTIM_TypeDef *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE);
+}
+
+/**
+ * @brief Indicates whether the compare register write completed interrupt (CMP2OKIE) is enabled.
+ * @rmtoll IER CMP2OKIE LL_LPTIM_IsEnabledIT_CMP2OK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMP2OK(LPTIM_TypeDef *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE) == LPTIM_DIER_CMP2OKIE) ? 1UL : 0UL));
+}
+
+/**
+ * @brief Enable autoreload register write completed interrupt (ARROKIE).
+ * @rmtoll DIER ARROKIE LL_LPTIM_EnableIT_ARROK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE);
+}
+
+/**
+ * @brief Disable autoreload register write completed interrupt (ARROKIE).
+ * @rmtoll DIER ARROKIE LL_LPTIM_DisableIT_ARROK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE);
+}
+
+/**
+ * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
+ * @rmtoll DIER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit(1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE) == LPTIM_DIER_ARROKIE) ? 1UL : 0UL));
+}
+
+/**
+ * @brief Enable direction change to up interrupt (UPIE).
+ * @rmtoll DIER UPIE LL_LPTIM_EnableIT_UP
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE);
+}
+
+/**
+ * @brief Disable direction change to up interrupt (UPIE).
+ * @rmtoll DIER UPIE LL_LPTIM_DisableIT_UP
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE);
+}
+
+/**
+ * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
+ * @rmtoll DIER UPIE LL_LPTIM_IsEnabledIT_UP
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit(1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE) == LPTIM_DIER_UPIE) ? 1UL : 0UL));
+}
+
+/**
+ * @brief Enable direction change to down interrupt (DOWNIE).
+ * @rmtoll DIER DOWNIE LL_LPTIM_EnableIT_DOWN
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE);
+}
+
+/**
+ * @brief Disable direction change to down interrupt (DOWNIE).
+ * @rmtoll DIER DOWNIE LL_LPTIM_DisableIT_DOWN
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE);
+}
+
+/**
+ * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
+ * @rmtoll DIER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit(1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx)
+{
+ return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE) == LPTIM_DIER_DOWNIE) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable repetition register update successfully completed interrupt (REPOKIE).
+ * @rmtoll DIER REPOKIE LL_LPTIM_EnableIT_REPOK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_EnableIT_REPOK(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE);
+}
+
+/**
+ * @brief Disable repetition register update successfully completed interrupt (REPOKIE).
+ * @rmtoll DIER REPOKIE LL_LPTIM_DisableIT_REPOK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_DisableIT_REPOK(LPTIM_TypeDef *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE);
+}
+
+/**
+ * @brief Indicates whether the repetition register update successfully completed interrupt (REPOKIE) is enabled.
+ * @rmtoll DIER REPOKIE LL_LPTIM_IsEnabledIT_REPOK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit(1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_REPOK(LPTIM_TypeDef *LPTIMx)
+{
+ return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE) == (LPTIM_DIER_REPOKIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable update event interrupt (UEIE).
+ * @rmtoll DIER UEIE LL_LPTIM_EnableIT_UE
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_EnableIT_UE(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE);
+}
+
+/**
+ * @brief Disable update event interrupt (UEIE).
+ * @rmtoll DIER UEIE LL_LPTIM_DisableIT_UE
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_DisableIT_UE(LPTIM_TypeDef *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE);
+}
+
+/**
+ * @brief Indicates whether the update event interrupt (UEIE) is enabled.
+ * @rmtoll DIER UEIE LL_LPTIM_IsEnabledIT_UE
+ * @param LPTIMx Low-Power Timer instance
+ *@ retval State of bit(1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UE(LPTIM_TypeDef *LPTIMx)
+{
+ return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE) == (LPTIM_DIER_UEIE)) ? 1UL : 0UL);
+}
+/**
+ * @}
+ */
+
+
+/** @defgroup TIM_LL_EF_DMA_Management DMA Management
+ * @{
+ */
+/**
+ * @brief Enable update DMA request.
+ * @rmtoll DIER UEDE LL_LPTIM_EnableDMAReq_UPDATE
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_EnableDMAReq_UPDATE(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE);
+}
+
+/**
+ * @brief Disable update DMA request.
+ * @rmtoll DIER UEDE LL_LPTIM_DisableDMAReq_UPDATE
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_DisableDMAReq_UPDATE(LPTIM_TypeDef *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE);
+}
+
+/**
+ * @brief Indicates whether the update DMA request is enabled.
+ * @rmtoll DIER UEDE LL_LPTIM_IsEnabledDMAReq_UPDATE
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_UPDATE(LPTIM_TypeDef *LPTIMx)
+{
+ return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE) == (LPTIM_DIER_UEDE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable capture/compare 1 DMA request (CC1DE).
+ * @rmtoll DIER CC1DE LL_LPTIM_EnableDMAReq_CC1
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_EnableDMAReq_CC1(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE);
+}
+
+/**
+ * @brief Disable capture/compare 1 DMA request (CC1DE).
+ * @rmtoll DIER CC1DE LL_LPTIM_DisableDMAReq_CC1
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_DisableDMAReq_CC1(LPTIM_TypeDef *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
+ * @rmtoll DIER CC1DE LL_LPTIM_IsEnabledDMAReq_CC1
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_CC1(LPTIM_TypeDef *LPTIMx)
+{
+ return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE) == (LPTIM_DIER_CC1DE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable capture/compare 2 DMA request (CC2DE).
+ * @rmtoll DIER CC2DE LL_LPTIM_EnableDMAReq_CC2
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_EnableDMAReq_CC2(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE);
+}
+
+/**
+ * @brief Disable capture/compare 2 DMA request (CC2DE).
+ * @rmtoll DIER CC2DE LL_LPTIM_DisableDMAReq_CC2
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_DisableDMAReq_CC2(LPTIM_TypeDef *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
+ * @rmtoll DIER CC2DE LL_LPTIM_IsEnabledDMAReq_CC2
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_CC2(LPTIM_TypeDef *LPTIMx)
+{
+ return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE) == (LPTIM_DIER_CC2DE)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* LPTIM1 || LPTIM2 || LPTIM3 || LPTIM4 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_LL_LPTIM_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lpuart.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lpuart.h
new file mode 100644
index 00000000..a1df60e8
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lpuart.h
@@ -0,0 +1,2764 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_lpuart.h
+ * @author MCD Application Team
+ * @brief Header file of LPUART LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_LL_LPUART_H
+#define STM32U5xx_LL_LPUART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx.h"
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined (LPUART1)
+
+/** @defgroup LPUART_LL LPUART
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup LPUART_LL_Private_Variables LPUART Private Variables
+ * @{
+ */
+/* Array used to get the LPUART prescaler division decimal values versus @ref LPUART_LL_EC_PRESCALER values */
+static const uint16_t LPUART_PRESCALER_TAB[] =
+{
+ (uint16_t)1,
+ (uint16_t)2,
+ (uint16_t)4,
+ (uint16_t)6,
+ (uint16_t)8,
+ (uint16_t)10,
+ (uint16_t)12,
+ (uint16_t)16,
+ (uint16_t)32,
+ (uint16_t)64,
+ (uint16_t)128,
+ (uint16_t)256
+};
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup LPUART_LL_Private_Constants LPUART Private Constants
+ * @{
+ */
+/* Defines used in Baud Rate related macros and corresponding register setting computation */
+#define LPUART_LPUARTDIV_FREQ_MUL 256U
+#define LPUART_BRR_MASK 0x000FFFFFU
+#define LPUART_BRR_MIN_VALUE 0x00000300U
+/**
+ * @}
+ */
+
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPUART_LL_Private_Macros LPUART Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures
+ * @{
+ */
+
+/**
+ * @brief LL LPUART Init Structure definition
+ */
+typedef struct
+{
+ uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate.
+ This parameter can be a value of @ref LPUART_LL_EC_PRESCALER.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_LPUART_SetPrescaler().*/
+
+ uint32_t BaudRate; /*!< This field defines expected LPUART communication baud rate.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_LPUART_SetBaudRate().*/
+
+ uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_LPUART_SetDataWidth().*/
+
+ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref LPUART_LL_EC_STOPBITS.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_LPUART_SetStopBitsLength().*/
+
+ uint32_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref LPUART_LL_EC_PARITY.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_LPUART_SetParity().*/
+
+ uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref LPUART_LL_EC_DIRECTION.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_LPUART_SetTransferDirection().*/
+
+ uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
+ This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_LPUART_SetHWFlowCtrl().*/
+
+} LL_LPUART_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants
+ * @{
+ */
+
+/** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines
+ * @brief Flags defines which can be used with LL_LPUART_WriteReg function
+ * @{
+ */
+#define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */
+#define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */
+#define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected clear flag */
+#define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */
+#define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */
+#define LL_LPUART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty clear flag */
+#define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */
+#define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */
+#define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_LPUART_ReadReg function
+ * @{
+ */
+#define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */
+#define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */
+#define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */
+#define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */
+#define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */
+#define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */
+#define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */
+#define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/
+#define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */
+#define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */
+#define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */
+#define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */
+#define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */
+#define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */
+#define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */
+#define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */
+#define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */
+#define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */
+#define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */
+#define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions
+ * @{
+ */
+#define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */
+#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty
+ interrupt enable */
+#define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */
+#define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO
+ not full interrupt enable */
+#define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */
+#define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */
+#define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */
+#define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */
+#define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */
+#define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */
+#define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */
+#define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold
+ * @{
+ */
+#define LL_LPUART_FIFOTHRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */
+#define LL_LPUART_FIFOTHRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */
+#define LL_LPUART_FIFOTHRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */
+#define LL_LPUART_FIFOTHRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */
+#define LL_LPUART_FIFOTHRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */
+#define LL_LPUART_FIFOTHRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EC_DIRECTION Direction
+ * @{
+ */
+#define LL_LPUART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */
+#define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */
+#define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */
+#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EC_PARITY Parity Control
+ * @{
+ */
+#define LL_LPUART_PARITY_NONE 0x00000000U /*!< Parity control disabled */
+#define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */
+#define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EC_WAKEUP Wakeup
+ * @{
+ */
+#define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */
+#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth
+ * @{
+ */
+#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
+#define LL_LPUART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
+#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler
+ * @{
+ */
+#define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */
+#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */
+#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */
+#define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 |\
+ USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */
+#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */
+#define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 |\
+ USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */
+#define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 |\
+ USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */
+#define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 |\
+ USART_PRESC_PRESCALER_1 |\
+ USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */
+#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */
+#define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 |\
+ USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */
+#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 |\
+ USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */
+#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 |\
+ USART_PRESC_PRESCALER_1 |\
+ USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EC_STOPBITS Stop Bits
+ * @{
+ */
+#define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */
+#define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap
+ * @{
+ */
+#define LL_LPUART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */
+#define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
+ * @{
+ */
+#define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */
+#define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
+ * @{
+ */
+#define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */
+#define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion
+ * @{
+ */
+#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received
+ in positive/direct logic. (1=H, 0=L) */
+#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received
+ in negative/inverse logic. (1=L, 0=H).
+ The parity bit is also inverted. */
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EC_BITORDER Bit Order
+ * @{
+ */
+#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first,
+ following the start bit */
+#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first,
+ following the start bit */
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection
+ * @{
+ */
+#define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */
+#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control
+ * @{
+ */
+#define LL_LPUART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */
+#define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested
+ when there is space in the receive buffer */
+#define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted
+ when the nCTS input is asserted (tied to 0)*/
+#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity
+ * @{
+ */
+#define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */
+#define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data
+ * @{
+ */
+#define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
+#define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EC_AUTOCR_TRIGSEL Autonomous Trigger selection
+ * @brief LPUART Autonomous Trigger selection
+ * @{
+ */
+#define LL_LPUART_LPDMA1_CH0_TCF_TRG 0U /*!< LPUART LPDMA1 channel0 Internal Trigger */
+#define LL_LPUART_LPDMA1_CH1_TCF_TRG 1U /*!< LPUART LPDMA1 channel1 Internal Trigger */
+#define LL_LPUART_LPDMA1_CH2_TCF_TRG 2U /*!< LPUART LPDMA1 channel2 Internal Trigger */
+#define LL_LPUART_LPDMA1_CH3_TCF_TRG 3U /*!< LPUART LPDMA1 channel3 Internal Trigger */
+#define LL_LPUART_EXTI_LINE6_TRG 4U /*!< LPUART EXTI line 6 Internal Trigger */
+#define LL_LPUART_EXTI_LINE8_TRG 5U /*!< LPUART EXTI line 8 Internal Trigger */
+#define LL_LPUART_LPTIM1_OUT_TRG 6U /*!< LPUART LPTIM1 out Internal Trigger */
+#define LL_LPUART_LPTIM3_OUT_TRG 7U /*!< LPUART LPTIM3 out Internal Trigger */
+#define LL_LPUART_COMP1_OUT_TRG 8U /*!< LPUART COMP1 out Internal Trigger */
+#define LL_LPUART_COMP2_OUT_TRG 9U /*!< LPUART COMP2 out Internal Trigger */
+#define LL_LPUART_RTC_ALRA_TRG 10U /*!< LPUART RTC alarm Internal Trigger */
+#define LL_LPUART_RTC_WUT_TRG 11U /*!< LPUART RTC wakeup Internal Trigger */
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EC_AUTOCR_TRIGPOL Autonomous Trigger Polarity
+ * @brief LPUART Autonomous Trigger Polarity
+ * @{
+ */
+#define LL_LPUART_TRIG_POLARITY_RISING 0x00000000U /*!< LPUART triggered on rising edge */
+#define LL_LPUART_TRIG_POLARITY_FALLING USART_AUTOCR_TRIGPOL /*!< LPUART triggered on falling edge */
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros
+ * @{
+ */
+
+/** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in LPUART register
+ * @param __INSTANCE__ LPUART Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in LPUART register
+ * @param __INSTANCE__ LPUART Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros
+ * @{
+ */
+
+/**
+ * @brief Compute LPUARTDIV value according to Peripheral Clock and
+ * expected Baud Rate (20-bit value of LPUARTDIV is returned)
+ * @param __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance
+ * @param __PRESCALER__ This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_PRESCALER_DIV1
+ * @arg @ref LL_LPUART_PRESCALER_DIV2
+ * @arg @ref LL_LPUART_PRESCALER_DIV4
+ * @arg @ref LL_LPUART_PRESCALER_DIV6
+ * @arg @ref LL_LPUART_PRESCALER_DIV8
+ * @arg @ref LL_LPUART_PRESCALER_DIV10
+ * @arg @ref LL_LPUART_PRESCALER_DIV12
+ * @arg @ref LL_LPUART_PRESCALER_DIV16
+ * @arg @ref LL_LPUART_PRESCALER_DIV32
+ * @arg @ref LL_LPUART_PRESCALER_DIV64
+ * @arg @ref LL_LPUART_PRESCALER_DIV128
+ * @arg @ref LL_LPUART_PRESCALER_DIV256
+ * @param __BAUDRATE__ Baud Rate value to achieve
+ * @retval LPUARTDIV value to be used for BRR register filling
+ */
+#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)\
+ ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)]))\
+ * LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions
+ * @{
+ */
+
+/** @defgroup LPUART_LL_EF_Configuration Configuration functions
+ * @{
+ */
+
+/**
+ * @brief LPUART Enable
+ * @rmtoll CR1 UE LL_LPUART_Enable
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx)
+{
+ SET_BIT(LPUARTx->CR1, USART_CR1_UE);
+}
+
+/**
+ * @brief LPUART Disable
+ * @note When LPUART is disabled, LPUART prescalers and outputs are stopped immediately,
+ * and current operations are discarded. The configuration of the LPUART is kept, but all the status
+ * flags, in the LPUARTx_ISR are set to their default values.
+ * @note In order to go into low-power mode without generating errors on the line,
+ * the TE bit must be reset before and the software must wait
+ * for the TC bit in the LPUART_ISR to be set before resetting the UE bit.
+ * The DMA requests are also reset when UE = 0 so the DMA channel must
+ * be disabled before resetting the UE bit.
+ * @rmtoll CR1 UE LL_LPUART_Disable
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx)
+{
+ CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE);
+}
+
+/**
+ * @brief Indicate if LPUART is enabled
+ * @rmtoll CR1 UE LL_LPUART_IsEnabled
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief FIFO Mode Enable
+ * @rmtoll CR1 FIFOEN LL_LPUART_EnableFIFO
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx)
+{
+ SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
+}
+
+/**
+ * @brief FIFO Mode Disable
+ * @rmtoll CR1 FIFOEN LL_LPUART_DisableFIFO
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx)
+{
+ CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
+}
+
+/**
+ * @brief Indicate if FIFO Mode is enabled
+ * @rmtoll CR1 FIFOEN LL_LPUART_IsEnabledFIFO
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure TX FIFO Threshold
+ * @rmtoll CR3 TXFTCFG LL_LPUART_SetTXFIFOThreshold
+ * @param LPUARTx LPUART Instance
+ * @param Threshold This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
+{
+ ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
+}
+
+/**
+ * @brief Return TX FIFO Threshold Configuration
+ * @rmtoll CR3 TXFTCFG LL_LPUART_GetTXFIFOThreshold
+ * @param LPUARTx LPUART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+ */
+__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(USART_TypeDef *LPUARTx)
+{
+ return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
+}
+
+/**
+ * @brief Configure RX FIFO Threshold
+ * @rmtoll CR3 RXFTCFG LL_LPUART_SetRXFIFOThreshold
+ * @param LPUARTx LPUART Instance
+ * @param Threshold This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
+{
+ ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
+}
+
+/**
+ * @brief Return RX FIFO Threshold Configuration
+ * @rmtoll CR3 RXFTCFG LL_LPUART_GetRXFIFOThreshold
+ * @param LPUARTx LPUART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+ */
+__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(USART_TypeDef *LPUARTx)
+{
+ return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
+}
+
+/**
+ * @brief Configure TX and RX FIFOs Threshold
+ * @rmtoll CR3 TXFTCFG LL_LPUART_ConfigFIFOsThreshold\n
+ * CR3 RXFTCFG LL_LPUART_ConfigFIFOsThreshold
+ * @param LPUARTx LPUART Instance
+ * @param TXThreshold This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+ * @param RXThreshold This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold)
+{
+ ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \
+ (RXThreshold << USART_CR3_RXFTCFG_Pos));
+}
+
+/**
+ * @brief LPUART enabled in STOP Mode
+ * @note When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that
+ * LPUART clock selection is HSI or LSE in RCC.
+ * @rmtoll CR1 UESM LL_LPUART_EnableInStopMode
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx)
+{
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+ * @brief LPUART disabled in STOP Mode
+ * @note When this function is disabled, LPUART is not able to wake up the MCU from Stop mode
+ * @rmtoll CR1 UESM LL_LPUART_DisableInStopMode
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx)
+{
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+ * @brief Indicate if LPUART is enabled in STOP Mode
+ * (able to wake up MCU from Stop mode or not)
+ * @rmtoll CR1 UESM LL_LPUART_IsEnabledInStopMode
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit)
+ * @rmtoll CR1 RE LL_LPUART_EnableDirectionRx
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx)
+{
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RE);
+}
+
+/**
+ * @brief Receiver Disable
+ * @rmtoll CR1 RE LL_LPUART_DisableDirectionRx
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx)
+{
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
+}
+
+/**
+ * @brief Transmitter Enable
+ * @rmtoll CR1 TE LL_LPUART_EnableDirectionTx
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx)
+{
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TE);
+}
+
+/**
+ * @brief Transmitter Disable
+ * @rmtoll CR1 TE LL_LPUART_DisableDirectionTx
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx)
+{
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
+}
+
+/**
+ * @brief Configure simultaneously enabled/disabled states
+ * of Transmitter and Receiver
+ * @rmtoll CR1 RE LL_LPUART_SetTransferDirection\n
+ * CR1 TE LL_LPUART_SetTransferDirection
+ * @param LPUARTx LPUART Instance
+ * @param TransferDirection This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_DIRECTION_NONE
+ * @arg @ref LL_LPUART_DIRECTION_RX
+ * @arg @ref LL_LPUART_DIRECTION_TX
+ * @arg @ref LL_LPUART_DIRECTION_TX_RX
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection)
+{
+ ATOMIC_MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
+}
+
+/**
+ * @brief Return enabled/disabled states of Transmitter and Receiver
+ * @rmtoll CR1 RE LL_LPUART_GetTransferDirection\n
+ * CR1 TE LL_LPUART_GetTransferDirection
+ * @param LPUARTx LPUART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPUART_DIRECTION_NONE
+ * @arg @ref LL_LPUART_DIRECTION_RX
+ * @arg @ref LL_LPUART_DIRECTION_TX
+ * @arg @ref LL_LPUART_DIRECTION_TX_RX
+ */
+__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(USART_TypeDef *LPUARTx)
+{
+ return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE));
+}
+
+/**
+ * @brief Configure Parity (enabled/disabled and parity mode if enabled)
+ * @note This function selects if hardware parity control (generation and detection) is enabled or disabled.
+ * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
+ * (depending on data width) and parity is checked on the received data.
+ * @rmtoll CR1 PS LL_LPUART_SetParity\n
+ * CR1 PCE LL_LPUART_SetParity
+ * @param LPUARTx LPUART Instance
+ * @param Parity This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_PARITY_NONE
+ * @arg @ref LL_LPUART_PARITY_EVEN
+ * @arg @ref LL_LPUART_PARITY_ODD
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity)
+{
+ MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
+}
+
+/**
+ * @brief Return Parity configuration (enabled/disabled and parity mode if enabled)
+ * @rmtoll CR1 PS LL_LPUART_GetParity\n
+ * CR1 PCE LL_LPUART_GetParity
+ * @param LPUARTx LPUART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPUART_PARITY_NONE
+ * @arg @ref LL_LPUART_PARITY_EVEN
+ * @arg @ref LL_LPUART_PARITY_ODD
+ */
+__STATIC_INLINE uint32_t LL_LPUART_GetParity(USART_TypeDef *LPUARTx)
+{
+ return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
+}
+
+/**
+ * @brief Set Receiver Wake Up method from Mute mode.
+ * @rmtoll CR1 WAKE LL_LPUART_SetWakeUpMethod
+ * @param LPUARTx LPUART Instance
+ * @param Method This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_WAKEUP_IDLELINE
+ * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method)
+{
+ MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method);
+}
+
+/**
+ * @brief Return Receiver Wake Up method from Mute mode
+ * @rmtoll CR1 WAKE LL_LPUART_GetWakeUpMethod
+ * @param LPUARTx LPUART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPUART_WAKEUP_IDLELINE
+ * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
+ */
+__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(USART_TypeDef *LPUARTx)
+{
+ return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE));
+}
+
+/**
+ * @brief Set Word length (nb of data bits, excluding start and stop bits)
+ * @rmtoll CR1 M LL_LPUART_SetDataWidth
+ * @param LPUARTx LPUART Instance
+ * @param DataWidth This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_DATAWIDTH_7B
+ * @arg @ref LL_LPUART_DATAWIDTH_8B
+ * @arg @ref LL_LPUART_DATAWIDTH_9B
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth)
+{
+ MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth);
+}
+
+/**
+ * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits)
+ * @rmtoll CR1 M LL_LPUART_GetDataWidth
+ * @param LPUARTx LPUART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPUART_DATAWIDTH_7B
+ * @arg @ref LL_LPUART_DATAWIDTH_8B
+ * @arg @ref LL_LPUART_DATAWIDTH_9B
+ */
+__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(USART_TypeDef *LPUARTx)
+{
+ return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M));
+}
+
+/**
+ * @brief Allow switch between Mute Mode and Active mode
+ * @rmtoll CR1 MME LL_LPUART_EnableMuteMode
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx)
+{
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_MME);
+}
+
+/**
+ * @brief Prevent Mute Mode use. Set Receiver in active mode permanently.
+ * @rmtoll CR1 MME LL_LPUART_DisableMuteMode
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx)
+{
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
+}
+
+/**
+ * @brief Indicate if switch between Mute Mode and Active mode is allowed
+ * @rmtoll CR1 MME LL_LPUART_IsEnabledMuteMode
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure Clock source prescaler for baudrate generator and oversampling
+ * @rmtoll PRESC PRESCALER LL_LPUART_SetPrescaler
+ * @param LPUARTx LPUART Instance
+ * @param PrescalerValue This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_PRESCALER_DIV1
+ * @arg @ref LL_LPUART_PRESCALER_DIV2
+ * @arg @ref LL_LPUART_PRESCALER_DIV4
+ * @arg @ref LL_LPUART_PRESCALER_DIV6
+ * @arg @ref LL_LPUART_PRESCALER_DIV8
+ * @arg @ref LL_LPUART_PRESCALER_DIV10
+ * @arg @ref LL_LPUART_PRESCALER_DIV12
+ * @arg @ref LL_LPUART_PRESCALER_DIV16
+ * @arg @ref LL_LPUART_PRESCALER_DIV32
+ * @arg @ref LL_LPUART_PRESCALER_DIV64
+ * @arg @ref LL_LPUART_PRESCALER_DIV128
+ * @arg @ref LL_LPUART_PRESCALER_DIV256
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue)
+{
+ MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
+}
+
+/**
+ * @brief Retrieve the Clock source prescaler for baudrate generator and oversampling
+ * @rmtoll PRESC PRESCALER LL_LPUART_GetPrescaler
+ * @param LPUARTx LPUART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPUART_PRESCALER_DIV1
+ * @arg @ref LL_LPUART_PRESCALER_DIV2
+ * @arg @ref LL_LPUART_PRESCALER_DIV4
+ * @arg @ref LL_LPUART_PRESCALER_DIV6
+ * @arg @ref LL_LPUART_PRESCALER_DIV8
+ * @arg @ref LL_LPUART_PRESCALER_DIV10
+ * @arg @ref LL_LPUART_PRESCALER_DIV12
+ * @arg @ref LL_LPUART_PRESCALER_DIV16
+ * @arg @ref LL_LPUART_PRESCALER_DIV32
+ * @arg @ref LL_LPUART_PRESCALER_DIV64
+ * @arg @ref LL_LPUART_PRESCALER_DIV128
+ * @arg @ref LL_LPUART_PRESCALER_DIV256
+ */
+__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(USART_TypeDef *LPUARTx)
+{
+ return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER));
+}
+
+/**
+ * @brief Set the length of the stop bits
+ * @rmtoll CR2 STOP LL_LPUART_SetStopBitsLength
+ * @param LPUARTx LPUART Instance
+ * @param StopBits This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_STOPBITS_1
+ * @arg @ref LL_LPUART_STOPBITS_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits)
+{
+ MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+ * @brief Retrieve the length of the stop bits
+ * @rmtoll CR2 STOP LL_LPUART_GetStopBitsLength
+ * @param LPUARTx LPUART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPUART_STOPBITS_1
+ * @arg @ref LL_LPUART_STOPBITS_2
+ */
+__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(USART_TypeDef *LPUARTx)
+{
+ return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP));
+}
+
+/**
+ * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits)
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Data Width configuration using @ref LL_LPUART_SetDataWidth() function
+ * - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function
+ * - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function
+ * @rmtoll CR1 PS LL_LPUART_ConfigCharacter\n
+ * CR1 PCE LL_LPUART_ConfigCharacter\n
+ * CR1 M LL_LPUART_ConfigCharacter\n
+ * CR2 STOP LL_LPUART_ConfigCharacter
+ * @param LPUARTx LPUART Instance
+ * @param DataWidth This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_DATAWIDTH_7B
+ * @arg @ref LL_LPUART_DATAWIDTH_8B
+ * @arg @ref LL_LPUART_DATAWIDTH_9B
+ * @param Parity This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_PARITY_NONE
+ * @arg @ref LL_LPUART_PARITY_EVEN
+ * @arg @ref LL_LPUART_PARITY_ODD
+ * @param StopBits This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_STOPBITS_1
+ * @arg @ref LL_LPUART_STOPBITS_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity,
+ uint32_t StopBits)
+{
+ MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
+ MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+ * @brief Configure TX/RX pins swapping setting.
+ * @rmtoll CR2 SWAP LL_LPUART_SetTXRXSwap
+ * @param LPUARTx LPUART Instance
+ * @param SwapConfig This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_TXRX_STANDARD
+ * @arg @ref LL_LPUART_TXRX_SWAPPED
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig)
+{
+ MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig);
+}
+
+/**
+ * @brief Retrieve TX/RX pins swapping configuration.
+ * @rmtoll CR2 SWAP LL_LPUART_GetTXRXSwap
+ * @param LPUARTx LPUART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPUART_TXRX_STANDARD
+ * @arg @ref LL_LPUART_TXRX_SWAPPED
+ */
+__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(USART_TypeDef *LPUARTx)
+{
+ return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP));
+}
+
+/**
+ * @brief Configure RX pin active level logic
+ * @rmtoll CR2 RXINV LL_LPUART_SetRXPinLevel
+ * @param LPUARTx LPUART Instance
+ * @param PinInvMethod This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
+ * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
+{
+ MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod);
+}
+
+/**
+ * @brief Retrieve RX pin active level logic configuration
+ * @rmtoll CR2 RXINV LL_LPUART_GetRXPinLevel
+ * @param LPUARTx LPUART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
+ * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
+ */
+__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(USART_TypeDef *LPUARTx)
+{
+ return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV));
+}
+
+/**
+ * @brief Configure TX pin active level logic
+ * @rmtoll CR2 TXINV LL_LPUART_SetTXPinLevel
+ * @param LPUARTx LPUART Instance
+ * @param PinInvMethod This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
+ * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
+{
+ MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod);
+}
+
+/**
+ * @brief Retrieve TX pin active level logic configuration
+ * @rmtoll CR2 TXINV LL_LPUART_GetTXPinLevel
+ * @param LPUARTx LPUART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
+ * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
+ */
+__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(USART_TypeDef *LPUARTx)
+{
+ return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV));
+}
+
+/**
+ * @brief Configure Binary data logic.
+ *
+ * @note Allow to define how Logical data from the data register are send/received :
+ * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
+ * @rmtoll CR2 DATAINV LL_LPUART_SetBinaryDataLogic
+ * @param LPUARTx LPUART Instance
+ * @param DataLogic This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
+ * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic)
+{
+ MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic);
+}
+
+/**
+ * @brief Retrieve Binary data configuration
+ * @rmtoll CR2 DATAINV LL_LPUART_GetBinaryDataLogic
+ * @param LPUARTx LPUART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
+ * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
+ */
+__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(USART_TypeDef *LPUARTx)
+{
+ return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV));
+}
+
+/**
+ * @brief Configure transfer bit order (either Less or Most Significant Bit First)
+ * @note MSB First means data is transmitted/received with the MSB first, following the start bit.
+ * LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+ * @rmtoll CR2 MSBFIRST LL_LPUART_SetTransferBitOrder
+ * @param LPUARTx LPUART Instance
+ * @param BitOrder This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_BITORDER_LSBFIRST
+ * @arg @ref LL_LPUART_BITORDER_MSBFIRST
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder)
+{
+ MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
+}
+
+/**
+ * @brief Return transfer bit order (either Less or Most Significant Bit First)
+ * @note MSB First means data is transmitted/received with the MSB first, following the start bit.
+ * LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+ * @rmtoll CR2 MSBFIRST LL_LPUART_GetTransferBitOrder
+ * @param LPUARTx LPUART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPUART_BITORDER_LSBFIRST
+ * @arg @ref LL_LPUART_BITORDER_MSBFIRST
+ */
+__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(USART_TypeDef *LPUARTx)
+{
+ return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST));
+}
+
+/**
+ * @brief Set Address of the LPUART node.
+ * @note This is used in multiprocessor communication during Mute mode or Stop mode,
+ * for wake up with address mark detection.
+ * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7.
+ * (b7-b4 should be set to 0)
+ * 8bits address node is used when 7-bit Address Detection is selected in ADDM7.
+ * (This is used in multiprocessor communication during Mute mode or Stop mode,
+ * for wake up with 7-bit address mark detection.
+ * The MSB of the character sent by the transmitter should be equal to 1.
+ * It may also be used for character detection during normal reception,
+ * Mute mode inactive (for example, end of block detection in ModBus protocol).
+ * In this case, the whole received character (8-bit) is compared to the ADD[7:0]
+ * value and CMF flag is set on match)
+ * @rmtoll CR2 ADD LL_LPUART_ConfigNodeAddress\n
+ * CR2 ADDM7 LL_LPUART_ConfigNodeAddress
+ * @param LPUARTx LPUART Instance
+ * @param AddressLen This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_ADDRESS_DETECT_4B
+ * @arg @ref LL_LPUART_ADDRESS_DETECT_7B
+ * @param NodeAddress 4 or 7 bit Address of the LPUART node.
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
+{
+ MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
+ (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
+}
+
+/**
+ * @brief Return 8 bit Address of the LPUART node as set in ADD field of CR2.
+ * @note If 4-bit Address Detection is selected in ADDM7,
+ * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
+ * If 7-bit Address Detection is selected in ADDM7,
+ * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
+ * @rmtoll CR2 ADD LL_LPUART_GetNodeAddress
+ * @param LPUARTx LPUART Instance
+ * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)
+ */
+__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(USART_TypeDef *LPUARTx)
+{
+ return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
+}
+
+/**
+ * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
+ * @rmtoll CR2 ADDM7 LL_LPUART_GetNodeAddressLen
+ * @param LPUARTx LPUART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPUART_ADDRESS_DETECT_4B
+ * @arg @ref LL_LPUART_ADDRESS_DETECT_7B
+ */
+__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(USART_TypeDef *LPUARTx)
+{
+ return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7));
+}
+
+/**
+ * @brief Enable RTS HW Flow Control
+ * @rmtoll CR3 RTSE LL_LPUART_EnableRTSHWFlowCtrl
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
+{
+ SET_BIT(LPUARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+ * @brief Disable RTS HW Flow Control
+ * @rmtoll CR3 RTSE LL_LPUART_DisableRTSHWFlowCtrl
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
+{
+ CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+ * @brief Enable CTS HW Flow Control
+ * @rmtoll CR3 CTSE LL_LPUART_EnableCTSHWFlowCtrl
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
+{
+ SET_BIT(LPUARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+ * @brief Disable CTS HW Flow Control
+ * @rmtoll CR3 CTSE LL_LPUART_DisableCTSHWFlowCtrl
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
+{
+ CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+ * @brief Configure HW Flow Control mode (both CTS and RTS)
+ * @rmtoll CR3 RTSE LL_LPUART_SetHWFlowCtrl\n
+ * CR3 CTSE LL_LPUART_SetHWFlowCtrl
+ * @param LPUARTx LPUART Instance
+ * @param HardwareFlowControl This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_HWCONTROL_NONE
+ * @arg @ref LL_LPUART_HWCONTROL_RTS
+ * @arg @ref LL_LPUART_HWCONTROL_CTS
+ * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
+{
+ MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
+}
+
+/**
+ * @brief Return HW Flow Control configuration (both CTS and RTS)
+ * @rmtoll CR3 RTSE LL_LPUART_GetHWFlowCtrl\n
+ * CR3 CTSE LL_LPUART_GetHWFlowCtrl
+ * @param LPUARTx LPUART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPUART_HWCONTROL_NONE
+ * @arg @ref LL_LPUART_HWCONTROL_RTS
+ * @arg @ref LL_LPUART_HWCONTROL_CTS
+ * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
+ */
+__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(USART_TypeDef *LPUARTx)
+{
+ return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
+}
+
+/**
+ * @brief Enable Overrun detection
+ * @rmtoll CR3 OVRDIS LL_LPUART_EnableOverrunDetect
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx)
+{
+ CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+ * @brief Disable Overrun detection
+ * @rmtoll CR3 OVRDIS LL_LPUART_DisableOverrunDetect
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx)
+{
+ SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+ * @brief Indicate if Overrun detection is enabled
+ * @rmtoll CR3 OVRDIS LL_LPUART_IsEnabledOverrunDetect
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure LPUART BRR register for achieving expected Baud Rate value.
+ *
+ * @note Compute and set LPUARTDIV value in BRR Register (full BRR content)
+ * according to used Peripheral Clock and expected Baud Rate values
+ * @note Peripheral clock and Baud Rate values provided as function parameters should be valid
+ * (Baud rate value != 0).
+ * @note Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit,
+ * a care should be taken when generating high baud rates using high PeriphClk
+ * values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate].
+ * @rmtoll BRR BRR LL_LPUART_SetBaudRate
+ * @param LPUARTx LPUART Instance
+ * @param PeriphClk Peripheral Clock
+ * @param PrescalerValue This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_PRESCALER_DIV1
+ * @arg @ref LL_LPUART_PRESCALER_DIV2
+ * @arg @ref LL_LPUART_PRESCALER_DIV4
+ * @arg @ref LL_LPUART_PRESCALER_DIV6
+ * @arg @ref LL_LPUART_PRESCALER_DIV8
+ * @arg @ref LL_LPUART_PRESCALER_DIV10
+ * @arg @ref LL_LPUART_PRESCALER_DIV12
+ * @arg @ref LL_LPUART_PRESCALER_DIV16
+ * @arg @ref LL_LPUART_PRESCALER_DIV32
+ * @arg @ref LL_LPUART_PRESCALER_DIV64
+ * @arg @ref LL_LPUART_PRESCALER_DIV128
+ * @arg @ref LL_LPUART_PRESCALER_DIV256
+ * @param BaudRate Baud Rate
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
+ uint32_t BaudRate)
+{
+ if (BaudRate != 0U)
+ {
+ LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate);
+ }
+}
+
+/**
+ * @brief Return current Baud Rate value, according to LPUARTDIV present in BRR register
+ * (full BRR content), and to used Peripheral Clock values
+ * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
+ * @rmtoll BRR BRR LL_LPUART_GetBaudRate
+ * @param LPUARTx LPUART Instance
+ * @param PeriphClk Peripheral Clock
+ * @param PrescalerValue This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_PRESCALER_DIV1
+ * @arg @ref LL_LPUART_PRESCALER_DIV2
+ * @arg @ref LL_LPUART_PRESCALER_DIV4
+ * @arg @ref LL_LPUART_PRESCALER_DIV6
+ * @arg @ref LL_LPUART_PRESCALER_DIV8
+ * @arg @ref LL_LPUART_PRESCALER_DIV10
+ * @arg @ref LL_LPUART_PRESCALER_DIV12
+ * @arg @ref LL_LPUART_PRESCALER_DIV16
+ * @arg @ref LL_LPUART_PRESCALER_DIV32
+ * @arg @ref LL_LPUART_PRESCALER_DIV64
+ * @arg @ref LL_LPUART_PRESCALER_DIV128
+ * @arg @ref LL_LPUART_PRESCALER_DIV256
+ * @retval Baud Rate
+ */
+__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue)
+{
+ uint32_t lpuartdiv;
+ uint32_t brrresult;
+ uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue]));
+
+ lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;
+
+ if (lpuartdiv >= LPUART_BRR_MIN_VALUE)
+ {
+ brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);
+ }
+ else
+ {
+ brrresult = 0x0UL;
+ }
+
+ return (brrresult);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
+ * @{
+ */
+
+/**
+ * @brief Enable Single Wire Half-Duplex mode
+ * @rmtoll CR3 HDSEL LL_LPUART_EnableHalfDuplex
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx)
+{
+ SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+ * @brief Disable Single Wire Half-Duplex mode
+ * @rmtoll CR3 HDSEL LL_LPUART_DisableHalfDuplex
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx)
+{
+ CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+ * @brief Indicate if Single Wire Half-Duplex mode is enabled
+ * @rmtoll CR3 HDSEL LL_LPUART_IsEnabledHalfDuplex
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
+ * @{
+ */
+
+/**
+ * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+ * @rmtoll CR1 DEDT LL_LPUART_SetDEDeassertionTime
+ * @param LPUARTx LPUART Instance
+ * @param Time Value between Min_Data=0 and Max_Data=31
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
+{
+ MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
+}
+
+/**
+ * @brief Return DEDT (Driver Enable De-Assertion Time)
+ * @rmtoll CR1 DEDT LL_LPUART_GetDEDeassertionTime
+ * @param LPUARTx LPUART Instance
+ * @retval Time value expressed on 5 bits ([4:0] bits) : c
+ */
+__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(USART_TypeDef *LPUARTx)
+{
+ return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
+}
+
+/**
+ * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+ * @rmtoll CR1 DEAT LL_LPUART_SetDEAssertionTime
+ * @param LPUARTx LPUART Instance
+ * @param Time Value between Min_Data=0 and Max_Data=31
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
+{
+ MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
+}
+
+/**
+ * @brief Return DEAT (Driver Enable Assertion Time)
+ * @rmtoll CR1 DEAT LL_LPUART_GetDEAssertionTime
+ * @param LPUARTx LPUART Instance
+ * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31
+ */
+__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(USART_TypeDef *LPUARTx)
+{
+ return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
+}
+
+/**
+ * @brief Enable Driver Enable (DE) Mode
+ * @rmtoll CR3 DEM LL_LPUART_EnableDEMode
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx)
+{
+ SET_BIT(LPUARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+ * @brief Disable Driver Enable (DE) Mode
+ * @rmtoll CR3 DEM LL_LPUART_DisableDEMode
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx)
+{
+ CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+ * @brief Indicate if Driver Enable (DE) Mode is enabled
+ * @rmtoll CR3 DEM LL_LPUART_IsEnabledDEMode
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Select Driver Enable Polarity
+ * @rmtoll CR3 DEP LL_LPUART_SetDESignalPolarity
+ * @param LPUARTx LPUART Instance
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_DE_POLARITY_HIGH
+ * @arg @ref LL_LPUART_DE_POLARITY_LOW
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)
+{
+ MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity);
+}
+
+/**
+ * @brief Return Driver Enable Polarity
+ * @rmtoll CR3 DEP LL_LPUART_GetDESignalPolarity
+ * @param LPUARTx LPUART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPUART_DE_POLARITY_HIGH
+ * @arg @ref LL_LPUART_DE_POLARITY_LOW
+ */
+__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(USART_TypeDef *LPUARTx)
+{
+ return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Check if the LPUART Parity Error Flag is set or not
+ * @rmtoll ISR PE LL_LPUART_IsActiveFlag_PE
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART Framing Error Flag is set or not
+ * @rmtoll ISR FE LL_LPUART_IsActiveFlag_FE
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART Noise error detected Flag is set or not
+ * @rmtoll ISR NE LL_LPUART_IsActiveFlag_NE
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART OverRun Error Flag is set or not
+ * @rmtoll ISR ORE LL_LPUART_IsActiveFlag_ORE
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART IDLE line detected Flag is set or not
+ * @rmtoll ISR IDLE LL_LPUART_IsActiveFlag_IDLE
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
+}
+
+/* Legacy define */
+#define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE
+
+/**
+ * @brief Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not
+ * @rmtoll ISR RXNE_RXFNE LL_LPUART_IsActiveFlag_RXNE_RXFNE
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART Transmission Complete Flag is set or not
+ * @rmtoll ISR TC LL_LPUART_IsActiveFlag_TC
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
+}
+
+/* Legacy define */
+#define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF
+
+/**
+ * @brief Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not
+ * @rmtoll ISR TXE_TXFNF LL_LPUART_IsActiveFlag_TXE_TXFNF
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART CTS interrupt Flag is set or not
+ * @rmtoll ISR CTSIF LL_LPUART_IsActiveFlag_nCTS
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART CTS Flag is set or not
+ * @rmtoll ISR CTS LL_LPUART_IsActiveFlag_CTS
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART Busy Flag is set or not
+ * @rmtoll ISR BUSY LL_LPUART_IsActiveFlag_BUSY
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART Character Match Flag is set or not
+ * @rmtoll ISR CMF LL_LPUART_IsActiveFlag_CM
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART Send Break Flag is set or not
+ * @rmtoll ISR SBKF LL_LPUART_IsActiveFlag_SBK
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART Receive Wake Up from mute mode Flag is set or not
+ * @rmtoll ISR RWU LL_LPUART_IsActiveFlag_RWU
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART Transmit Enable Acknowledge Flag is set or not
+ * @rmtoll ISR TEACK LL_LPUART_IsActiveFlag_TEACK
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART Receive Enable Acknowledge Flag is set or not
+ * @rmtoll ISR REACK LL_LPUART_IsActiveFlag_REACK
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART TX FIFO Empty Flag is set or not
+ * @rmtoll ISR TXFE LL_LPUART_IsActiveFlag_TXFE
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART RX FIFO Full Flag is set or not
+ * @rmtoll ISR RXFF LL_LPUART_IsActiveFlag_RXFF
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART TX FIFO Threshold Flag is set or not
+ * @rmtoll ISR TXFT LL_LPUART_IsActiveFlag_TXFT
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART RX FIFO Threshold Flag is set or not
+ * @rmtoll ISR RXFT LL_LPUART_IsActiveFlag_RXFT
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear Parity Error Flag
+ * @rmtoll ICR PECF LL_LPUART_ClearFlag_PE
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx)
+{
+ WRITE_REG(LPUARTx->ICR, USART_ICR_PECF);
+}
+
+/**
+ * @brief Clear Framing Error Flag
+ * @rmtoll ICR FECF LL_LPUART_ClearFlag_FE
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx)
+{
+ WRITE_REG(LPUARTx->ICR, USART_ICR_FECF);
+}
+
+/**
+ * @brief Clear Noise detected Flag
+ * @rmtoll ICR NECF LL_LPUART_ClearFlag_NE
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx)
+{
+ WRITE_REG(LPUARTx->ICR, USART_ICR_NECF);
+}
+
+/**
+ * @brief Clear OverRun Error Flag
+ * @rmtoll ICR ORECF LL_LPUART_ClearFlag_ORE
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx)
+{
+ WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF);
+}
+
+/**
+ * @brief Clear IDLE line detected Flag
+ * @rmtoll ICR IDLECF LL_LPUART_ClearFlag_IDLE
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx)
+{
+ WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF);
+}
+
+/**
+ * @brief Clear TX FIFO Empty Flag
+ * @rmtoll ICR TXFECF LL_LPUART_ClearFlag_TXFE
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_ClearFlag_TXFE(USART_TypeDef *LPUARTx)
+{
+ WRITE_REG(LPUARTx->ICR, USART_ICR_TXFECF);
+}
+
+/**
+ * @brief Clear Transmission Complete Flag
+ * @rmtoll ICR TCCF LL_LPUART_ClearFlag_TC
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx)
+{
+ WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF);
+}
+
+/**
+ * @brief Clear CTS Interrupt Flag
+ * @rmtoll ICR CTSCF LL_LPUART_ClearFlag_nCTS
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx)
+{
+ WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF);
+}
+
+/**
+ * @brief Clear Character Match Flag
+ * @rmtoll ICR CMCF LL_LPUART_ClearFlag_CM
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx)
+{
+ WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable IDLE Interrupt
+ * @rmtoll CR1 IDLEIE LL_LPUART_EnableIT_IDLE
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)
+{
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
+}
+
+/* Legacy define */
+#define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE
+
+/**
+ * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt
+ * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_EnableIT_RXNE_RXFNE
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
+{
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+}
+
+/**
+ * @brief Enable Transmission Complete Interrupt
+ * @rmtoll CR1 TCIE LL_LPUART_EnableIT_TC
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)
+{
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
+}
+
+/* Legacy define */
+#define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF
+
+/**
+ * @brief Enable TX Empty and TX FIFO Not Full Interrupt
+ * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_EnableIT_TXE_TXFNF
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
+{
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+}
+
+/**
+ * @brief Enable Parity Error Interrupt
+ * @rmtoll CR1 PEIE LL_LPUART_EnableIT_PE
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx)
+{
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+ * @brief Enable Character Match Interrupt
+ * @rmtoll CR1 CMIE LL_LPUART_EnableIT_CM
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)
+{
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+ * @brief Enable TX FIFO Empty Interrupt
+ * @rmtoll CR1 TXFEIE LL_LPUART_EnableIT_TXFE
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx)
+{
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
+}
+
+/**
+ * @brief Enable RX FIFO Full Interrupt
+ * @rmtoll CR1 RXFFIE LL_LPUART_EnableIT_RXFF
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx)
+{
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
+}
+
+/**
+ * @brief Enable Error Interrupt
+ * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+ * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
+ * - 0: Interrupt is inhibited
+ * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
+ * @rmtoll CR3 EIE LL_LPUART_EnableIT_ERROR
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx)
+{
+ ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+ * @brief Enable CTS Interrupt
+ * @rmtoll CR3 CTSIE LL_LPUART_EnableIT_CTS
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx)
+{
+ ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+ * @brief Enable TX FIFO Threshold Interrupt
+ * @rmtoll CR3 TXFTIE LL_LPUART_EnableIT_TXFT
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx)
+{
+ ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
+}
+
+/**
+ * @brief Enable RX FIFO Threshold Interrupt
+ * @rmtoll CR3 RXFTIE LL_LPUART_EnableIT_RXFT
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx)
+{
+ ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
+}
+
+/**
+ * @brief Disable IDLE Interrupt
+ * @rmtoll CR1 IDLEIE LL_LPUART_DisableIT_IDLE
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)
+{
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
+}
+
+/* Legacy define */
+#define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE
+
+/**
+ * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt
+ * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_DisableIT_RXNE_RXFNE
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
+{
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+}
+
+/**
+ * @brief Disable Transmission Complete Interrupt
+ * @rmtoll CR1 TCIE LL_LPUART_DisableIT_TC
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)
+{
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
+}
+
+/* Legacy define */
+#define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF
+
+/**
+ * @brief Disable TX Empty and TX FIFO Not Full Interrupt
+ * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_DisableIT_TXE_TXFNF
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
+{
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+}
+
+/**
+ * @brief Disable Parity Error Interrupt
+ * @rmtoll CR1 PEIE LL_LPUART_DisableIT_PE
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx)
+{
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+ * @brief Disable Character Match Interrupt
+ * @rmtoll CR1 CMIE LL_LPUART_DisableIT_CM
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)
+{
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+ * @brief Disable TX FIFO Empty Interrupt
+ * @rmtoll CR1 TXFEIE LL_LPUART_DisableIT_TXFE
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx)
+{
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
+}
+
+/**
+ * @brief Disable RX FIFO Full Interrupt
+ * @rmtoll CR1 RXFFIE LL_LPUART_DisableIT_RXFF
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx)
+{
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
+}
+
+/**
+ * @brief Disable Error Interrupt
+ * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+ * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
+ * - 0: Interrupt is inhibited
+ * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
+ * @rmtoll CR3 EIE LL_LPUART_DisableIT_ERROR
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx)
+{
+ ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+ * @brief Disable CTS Interrupt
+ * @rmtoll CR3 CTSIE LL_LPUART_DisableIT_CTS
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx)
+{
+ ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+ * @brief Disable TX FIFO Threshold Interrupt
+ * @rmtoll CR3 TXFTIE LL_LPUART_DisableIT_TXFT
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx)
+{
+ ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
+}
+
+/**
+ * @brief Disable RX FIFO Threshold Interrupt
+ * @rmtoll CR3 RXFTIE LL_LPUART_DisableIT_RXFT
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx)
+{
+ ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
+}
+
+/**
+ * @brief Check if the LPUART IDLE Interrupt source is enabled or disabled.
+ * @rmtoll CR1 IDLEIE LL_LPUART_IsEnabledIT_IDLE
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
+}
+
+/* Legacy define */
+#define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE
+
+/**
+ * @brief Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled.
+ * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_IsEnabledIT_RXNE_RXFNE
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
+ * @rmtoll CR1 TCIE LL_LPUART_IsEnabledIT_TC
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
+}
+
+/* Legacy define */
+#define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF
+
+/**
+ * @brief Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled
+ * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_IsEnabledIT_TXE_TXFNF
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART Parity Error Interrupt is enabled or disabled.
+ * @rmtoll CR1 PEIE LL_LPUART_IsEnabledIT_PE
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART Character Match Interrupt is enabled or disabled.
+ * @rmtoll CR1 CMIE LL_LPUART_IsEnabledIT_CM
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled
+ * @rmtoll CR1 TXFEIE LL_LPUART_IsEnabledIT_TXFE
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART RX FIFO Full Interrupt is enabled or disabled
+ * @rmtoll CR1 RXFFIE LL_LPUART_IsEnabledIT_RXFF
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART Error Interrupt is enabled or disabled.
+ * @rmtoll CR3 EIE LL_LPUART_IsEnabledIT_ERROR
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART CTS Interrupt is enabled or disabled.
+ * @rmtoll CR3 CTSIE LL_LPUART_IsEnabledIT_CTS
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled
+ * @rmtoll CR3 TXFTIE LL_LPUART_IsEnabledIT_TXFT
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled
+ * @rmtoll CR3 RXFTIE LL_LPUART_IsEnabledIT_RXFT
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EF_DMA_Management DMA_Management
+ * @{
+ */
+
+/**
+ * @brief Enable DMA Mode for reception
+ * @rmtoll CR3 DMAR LL_LPUART_EnableDMAReq_RX
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx)
+{
+ ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+ * @brief Disable DMA Mode for reception
+ * @rmtoll CR3 DMAR LL_LPUART_DisableDMAReq_RX
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx)
+{
+ ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+ * @brief Check if DMA Mode is enabled for reception
+ * @rmtoll CR3 DMAR LL_LPUART_IsEnabledDMAReq_RX
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable DMA Mode for transmission
+ * @rmtoll CR3 DMAT LL_LPUART_EnableDMAReq_TX
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx)
+{
+ ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+ * @brief Disable DMA Mode for transmission
+ * @rmtoll CR3 DMAT LL_LPUART_DisableDMAReq_TX
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx)
+{
+ ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+ * @brief Check if DMA Mode is enabled for transmission
+ * @rmtoll CR3 DMAT LL_LPUART_IsEnabledDMAReq_TX
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable DMA Disabling on Reception Error
+ * @rmtoll CR3 DDRE LL_LPUART_EnableDMADeactOnRxErr
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
+{
+ SET_BIT(LPUARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+ * @brief Disable DMA Disabling on Reception Error
+ * @rmtoll CR3 DDRE LL_LPUART_DisableDMADeactOnRxErr
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
+{
+ CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+ * @brief Indicate if DMA Disabling on Reception Error is disabled
+ * @rmtoll CR3 DDRE LL_LPUART_IsEnabledDMADeactOnRxErr
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get the LPUART data register address used for DMA transfer
+ * @rmtoll RDR RDR LL_LPUART_DMA_GetRegAddr\n
+ * @rmtoll TDR TDR LL_LPUART_DMA_GetRegAddr
+ * @param LPUARTx LPUART Instance
+ * @param Direction This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT
+ * @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE
+ * @retval Address of data register
+ */
+__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32_t Direction)
+{
+ uint32_t data_reg_addr;
+
+ if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT)
+ {
+ /* return address of TDR register */
+ data_reg_addr = (uint32_t) &(LPUARTx->TDR);
+ }
+ else
+ {
+ /* return address of RDR register */
+ data_reg_addr = (uint32_t) &(LPUARTx->RDR);
+ }
+
+ return data_reg_addr;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EF_Data_Management Data_Management
+ * @{
+ */
+
+/**
+ * @brief Read Receiver Data register (Receive Data value, 8 bits)
+ * @rmtoll RDR RDR LL_LPUART_ReceiveData8
+ * @param LPUARTx LPUART Instance
+ * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx)
+{
+ return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU);
+}
+
+/**
+ * @brief Read Receiver Data register (Receive Data value, 9 bits)
+ * @rmtoll RDR RDR LL_LPUART_ReceiveData9
+ * @param LPUARTx LPUART Instance
+ * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF
+ */
+__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(USART_TypeDef *LPUARTx)
+{
+ return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
+}
+
+/**
+ * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits)
+ * @rmtoll TDR TDR LL_LPUART_TransmitData8
+ * @param LPUARTx LPUART Instance
+ * @param Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value)
+{
+ LPUARTx->TDR = Value;
+}
+
+/**
+ * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits)
+ * @rmtoll TDR TDR LL_LPUART_TransmitData9
+ * @param LPUARTx LPUART Instance
+ * @param Value between Min_Data=0x00 and Max_Data=0x1FF
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value)
+{
+ LPUARTx->TDR = Value & 0x1FFUL;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EF_Execution Execution
+ * @{
+ */
+
+/**
+ * @brief Request Break sending
+ * @rmtoll RQR SBKRQ LL_LPUART_RequestBreakSending
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx)
+{
+ SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
+}
+
+/**
+ * @brief Put LPUART in mute mode and set the RWU flag
+ * @rmtoll RQR MMRQ LL_LPUART_RequestEnterMuteMode
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx)
+{
+ SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ);
+}
+
+/**
+ * @brief Request a Receive Data and FIFO flush
+ * @note Allows to discard the received data without reading them, and avoid an overrun
+ * condition.
+ * @rmtoll RQR RXFRQ LL_LPUART_RequestRxDataFlush
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx)
+{
+ SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EF_AutonomousMode Configuration functions related to Autonomous mode feature
+ * @{
+ */
+
+/**
+ * @brief Enable Selected Trigger
+ * @rmtoll AUTOCR TRIGEN LL_LPUART_Enable_SelectedTrigger
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_Enable_SelectedTrigger(USART_TypeDef *LPUARTx)
+{
+ SET_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TRIGEN);
+}
+
+/**
+ * @brief Disable Selected Trigger
+ * @rmtoll AUTOCR TRIGEN LL_LPUART_Disable_SelectedTrigger
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_Disable_SelectedTrigger(USART_TypeDef *LPUARTx)
+{
+ CLEAR_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TRIGEN);
+}
+
+/**
+ * @brief Indicate if selected Trigger is disabled or enabled
+ * @rmtoll AUTOCR TRIGEN LL_LPUART_IsEnabled_SelectedTrigger
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabled_SelectedTrigger(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TRIGEN) == (USART_AUTOCR_TRIGEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable Autonomous Send Idle Frame feature
+ * @rmtoll AUTOCR IDLEDIS LL_LPUART_Enable_AutonomousSendIdleFrame
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_Enable_AutonomousSendIdleFrame(USART_TypeDef *LPUARTx)
+{
+ CLEAR_BIT(LPUARTx->AUTOCR, USART_AUTOCR_IDLEDIS);
+}
+
+/**
+ * @brief Disable Autonomous Send Idle Frame feature
+ * @rmtoll AUTOCR IDLEDIS LL_LPUART_Disable_AutonomousSendIdleFrame
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_Disable_AutonomousSendIdleFrame(USART_TypeDef *LPUARTx)
+{
+ SET_BIT(LPUARTx->AUTOCR, USART_AUTOCR_IDLEDIS);
+}
+
+/**
+ * @brief Indicate if Autonomous send Idle Frame feature is disabled or enabled
+ * @rmtoll AUTOCR IDLEDIS LL_LPUART_IsEnabled_AutonomousSendIdleFrame
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabled_AutonomousSendIdleFrame(USART_TypeDef *LPUARTx)
+{
+ return ((READ_BIT(LPUARTx->AUTOCR, USART_AUTOCR_IDLEDIS) == (USART_AUTOCR_IDLEDIS)) ? 0UL : 1UL);
+}
+
+/**
+ * @brief Configure the Number of transferred data in bytes
+ * @rmtoll AUTOCR TDN LL_LPUART_SetNbTxData
+ * @param LPUARTx LPUART Instance
+ * @param Nbdata This parameter can be a value between 0 and 0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetNbTxData(USART_TypeDef *LPUARTx, uint32_t Nbdata)
+{
+ MODIFY_REG(LPUARTx->AUTOCR, USART_AUTOCR_TDN, (uint16_t)Nbdata);
+}
+
+/**
+ * @brief Retrieve the Number of transferred data in bytes
+ * @rmtoll AUTOCR TDN LL_LPUART_GetNbTxData
+ * @param LPUARTx LPUART Instance
+ * @retval Returned value can be a value between 0 and 0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_LPUART_GetNbTxData(USART_TypeDef *LPUARTx)
+{
+ return (uint32_t)(READ_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TDN));
+}
+
+/**
+ * @brief Set the trigger polarity
+ * @rmtoll AUTOCR TRIGPOL LL_LPUART_SetTriggerPolarity
+ * @param LPUARTx LPUART Instance
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_TRIG_POLARITY_RISING
+ * @arg @ref LL_LPUART_TRIG_POLARITY_FALLING
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetTriggerPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)
+{
+ MODIFY_REG(LPUARTx->AUTOCR, USART_AUTOCR_TRIGPOL, Polarity);
+}
+
+/**
+ * @brief Get the trigger polarity
+ * @rmtoll AUTOCR TRIGPOL LL_LPUART_GetTriggerPolarity
+ * @param LPUARTx LPUART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPUART_TRIG_POLARITY_RISING
+ * @arg @ref LL_LPUART_TRIG_POLARITY_FALLING
+ */
+__STATIC_INLINE uint32_t LL_LPUART_GetTriggerPolarity(USART_TypeDef *LPUARTx)
+{
+ return (uint32_t)(READ_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TRIGPOL));
+}
+
+/**
+ * @brief Set the selected trigger
+ * @rmtoll AUTOCR TRIGSEL LL_LPUART_SetSelectedTrigger
+ * @param LPUARTx LPUART Instance
+ * @param Trigger This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_LPDMA1_CH0_TCF_TRG
+ * @arg @ref LL_LPUART_LPDMA1_CH1_TCF_TRG
+ * @arg @ref LL_LPUART_LPDMA1_CH2_TCF_TRG
+ * @arg @ref LL_LPUART_LPDMA1_CH3_TCF_TRG
+ * @arg @ref LL_LPUART_EXTI_LINE6_TRG
+ * @arg @ref LL_LPUART_EXTI_LINE8_TRG
+ * @arg @ref LL_LPUART_LPTIM1_OUT_TRG
+ * @arg @ref LL_LPUART_LPTIM3_OUT_TRG
+ * @arg @ref LL_LPUART_COMP1_OUT_TRG
+ * @arg @ref LL_LPUART_COMP2_OUT_TRG
+ * @arg @ref LL_LPUART_RTC_ALRA_TRG
+ * @arg @ref LL_LPUART_RTC_WUT_TRG
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetSelectedTrigger(USART_TypeDef *LPUARTx, uint32_t Trigger)
+{
+ MODIFY_REG(LPUARTx->AUTOCR, USART_AUTOCR_TRIGSEL, (Trigger << USART_AUTOCR_TRIGSEL_Pos));
+}
+
+/**
+ * @brief Get the selected trigger
+ * @rmtoll AUTOCR TRIGSEL LL_LPUART_GetSelectedTrigger
+ * @param LPUARTx LPUART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPUART_LPDMA1_CH0_TCF_TRG
+ * @arg @ref LL_LPUART_LPDMA1_CH1_TCF_TRG
+ * @arg @ref LL_LPUART_LPDMA1_CH2_TCF_TRG
+ * @arg @ref LL_LPUART_LPDMA1_CH3_TCF_TRG
+ * @arg @ref LL_LPUART_EXTI_LINE6_TRG
+ * @arg @ref LL_LPUART_EXTI_LINE8_TRG
+ * @arg @ref LL_LPUART_LPTIM1_OUT_TRG
+ * @arg @ref LL_LPUART_LPTIM3_OUT_TRG
+ * @arg @ref LL_LPUART_COMP1_OUT_TRG
+ * @arg @ref LL_LPUART_COMP2_OUT_TRG
+ * @arg @ref LL_LPUART_RTC_ALRA_TRG
+ * @arg @ref LL_LPUART_RTC_WUT_TRG
+ */
+__STATIC_INLINE uint32_t LL_LPUART_GetSelectedTrigger(USART_TypeDef *LPUARTx)
+{
+ return (uint32_t)((READ_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TRIGSEL) >> USART_AUTOCR_TRIGSEL_Pos));
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx);
+ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct);
+void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* LPUART1 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_LL_LPUART_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_opamp.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_opamp.h
new file mode 100644
index 00000000..dd389780
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_opamp.h
@@ -0,0 +1,840 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_opamp.h
+ * @author MCD Application Team
+ * @brief Header file of OPAMP LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_LL_OPAMP_H
+#define STM32U5xx_LL_OPAMP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx.h"
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined (OPAMP1) || defined (OPAMP2)
+
+/** @defgroup OPAMP_LL OPAMP
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup OPAMP_LL_Private_Constants OPAMP Private Constants
+ * @{
+ */
+
+/* Internal mask for OPAMP power mode: */
+/* To select into literal LL_OPAMP_POWERMODE_x the relevant bits for: */
+/* - OPAMP power mode into control register */
+/* - OPAMP trimming register offset */
+
+/* Internal register offset for OPAMP trimming configuration */
+#define OPAMP_POWERMODE_OTR_REGOFFSET 0x00000000U
+#define OPAMP_POWERMODE_LPOTR_REGOFFSET 0x00000002U
+#define OPAMP_POWERMODE_OTR_REGOFFSET_MASK (OPAMP_POWERMODE_OTR_REGOFFSET | OPAMP_POWERMODE_LPOTR_REGOFFSET)
+
+/* Mask for OPAMP power mode into control register */
+#define OPAMP_POWERMODE_CSR_BIT_MASK (OPAMP_CSR_OPALPM | OPAMP_CSR_HSM)
+
+/* Internal mask for OPAMP trimming of transistors differential pair NMOS */
+/* or PMOS. */
+/* To select into literal LL_OPAMP_TRIMMING_x the relevant bits for: */
+/* - OPAMP trimming selection of transistors differential pair */
+/* - OPAMP trimming values of transistors differential pair */
+#define OPAMP_TRIMMING_SELECT_MASK (OPAMP_CSR_CALSEL)
+#define OPAMP_TRIMMING_VALUE_MASK (OPAMP_OTR_TRIMOFFSETP | OPAMP_OTR_TRIMOFFSETN)
+
+/**
+ * @}
+ */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup OPAMP_LL_Private_Macros OPAMP Private Macros
+ * @{
+ */
+
+/**
+ * @brief Driver macro reserved for internal use: set a pointer to
+ * a register from a register basis from which an offset
+ * is applied.
+ * @param __REG__ Register basis from which the offset is applied.
+ * @param __REG_OFFSET__ Offset to be applied (unit: number of registers).
+ * @retval Register address
+ */
+#define __OPAMP_PTR_REG_OFFSET(__REG__, __REG_OFFSET__) \
+ ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFSET__) << 1U))))
+/**
+ * @}
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup OPAMP_LL_ES_INIT OPAMP Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief Structure definition of some features of OPAMP instance.
+ */
+typedef struct
+{
+ uint32_t PowerMode; /*!< Set the power mode Normal or Low-Power and the speed mode Normal or High.
+ This parameter can be a value of @ref OPAMP_LL_EC_POWERMODE
+ This feature can be modified afterwards using
+ unitary function @ref LL_OPAMP_SetPowerMode(). */
+
+ uint32_t FunctionalMode; /*!< Set OPAMP functional mode by setting internal connections:
+ OPAMP operation in standalone, follower, ...
+ This parameter can be a value of @ref OPAMP_LL_EC_FUNCTIONAL_MODE
+ @note If OPAMP is configured in mode PGA, the gain can be configured
+ using function @ref LL_OPAMP_SetPGAGain().
+ This feature can be modified afterwards using unitary
+ function @ref LL_OPAMP_SetFunctionalMode(). */
+
+ uint32_t InputNonInverting; /*!< Set OPAMP input non-inverting connection.
+ This parameter can be a value of @ref OPAMP_LL_EC_INPUT_NONINVERTING
+ This feature can be modified afterwards using
+ unitary function @ref LL_OPAMP_SetInputNonInverting(). */
+
+ uint32_t InputInverting; /*!< Set OPAMP inverting input connection.
+ This parameter can be a value of @ref OPAMP_LL_EC_INPUT_INVERTING
+ @note OPAMP inverting input is used with OPAMP in mode
+ standalone or PGA with external capacitors for filtering circuit.
+ Otherwise (OPAMP in mode follower), OPAMP inverting input is not used
+ (not connected to GPIO pin), this parameter is discarded.
+ This feature can be modified afterwards using
+ unitary function @ref LL_OPAMP_SetInputInverting(). */
+
+} LL_OPAMP_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup OPAMP_LL_Exported_Constants OPAMP Exported Constants
+ * @{
+ */
+
+/** @defgroup OPAMP_LL_EC_POWERSUPPLY_RANGE OPAMP power supply range
+ * @{
+ */
+#define LL_OPAMP_POWERSUPPLY_RANGE_LOW 0x00000000U /*!< Power supply range low */
+#define LL_OPAMP_POWERSUPPLY_RANGE_HIGH (OPAMP_CSR_OPARANGE) /*!< Power supply range high - recommended for performance purpose */
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EC_POWERMODE OPAMP power mode
+ * @{
+ */
+#define LL_OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED 0x00000000U /*!< OPAMP power mode normal speed normal */
+#define LL_OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED OPAMP_CSR_HSM /*!< OPAMP power mode normal speed high */
+#define LL_OPAMP_POWERMODE_LOWPOWER_NORMALSPEED OPAMP_CSR_OPALPM /*!< OPAMP power mode low-power speed normal */
+#define LL_OPAMP_POWERMODE_LOWPOWER_HIGHSPEED (OPAMP_CSR_OPALPM | OPAMP_CSR_HSM) /*!< OPAMP power mode low-power speed high */
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EC_MODE OPAMP mode calibration or functional.
+ * @{
+ */
+#define LL_OPAMP_MODE_FUNCTIONAL 0x00000000U /*!< OPAMP functional mode */
+#define LL_OPAMP_MODE_CALIBRATION (OPAMP_CSR_CALON) /*!< OPAMP calibration mode */
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EC_FUNCTIONAL_MODE OPAMP functional mode
+ * @{
+ */
+#define LL_OPAMP_MODE_STANDALONE 0x00000000U /*!< OPAMP functional mode, OPAMP operation in standalone */
+#define LL_OPAMP_MODE_FOLLOWER (OPAMP_CSR_OPAMODE_1 | OPAMP_CSR_OPAMODE_0) /*!< OPAMP functional mode, OPAMP operation in follower */
+#define LL_OPAMP_MODE_PGA (OPAMP_CSR_OPAMODE_1) /*!< OPAMP functional mode, OPAMP operation in PGA */
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EC_MODE_PGA_GAIN OPAMP PGA gain (relevant when OPAMP is in functional mode PGA)
+ * @{
+ */
+#define LL_OPAMP_PGA_GAIN_2 0x00000000U /*!< OPAMP PGA gain 2 */
+#define LL_OPAMP_PGA_GAIN_4 (OPAMP_CSR_PGA_GAIN_0) /*!< OPAMP PGA gain 4 */
+#define LL_OPAMP_PGA_GAIN_8 (OPAMP_CSR_PGA_GAIN_1) /*!< OPAMP PGA gain 8 */
+#define LL_OPAMP_PGA_GAIN_16 (OPAMP_CSR_PGA_GAIN_1 | OPAMP_CSR_PGA_GAIN_0) /*!< OPAMP PGA gain 16 */
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EC_INPUT_NONINVERTING OPAMP input non-inverting
+ * @{
+ */
+#define LL_OPAMP_INPUT_NONINVERT_IO0 0x00000000U /*!< OPAMP non inverting input connected to GPIO pin (pin PA0 for OPAMP1, pin PA6 for OPAMP2) */
+#define LL_OPAMP_INPUT_NONINV_DAC1_CH1 (OPAMP_CSR_VP_SEL) /*!< OPAMP non inverting input connected to DAC1 channel output(channel1 for OPAMP1, channel2 for OPAMP2) */
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EC_INPUT_INVERTING OPAMP input inverting
+ * @{
+ */
+#define LL_OPAMP_INPUT_INVERT_IO0 0x00000000U /*!< OPAMP inverting input connected to GPIO pin (valid also in PGA mode for filtering). Note: OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin). */
+#define LL_OPAMP_INPUT_INVERT_IO1 (OPAMP_CSR_VM_SEL_0) /*!< OPAMP inverting input (low leakage input) connected to GPIO pin (available only on package BGA132). Note: OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin). */
+#define LL_OPAMP_INPUT_INVERT_CONNECT_NO (OPAMP_CSR_VM_SEL_1) /*!< OPAMP inverting input not externally connected (intended for OPAMP in mode follower or PGA without external capacitors for filtering) */
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EC_INPUT_LEGACY OPAMP inputs legacy literals name
+ * @{
+ */
+#define LL_OPAMP_NONINVERTINGINPUT_IO0 LL_OPAMP_INPUT_NONINVERT_IO0
+#define LL_OPAMP_NONINVERTINGINPUT_DAC_CH LL_OPAMP_INPUT_NONINV_DAC1_CH1
+
+#define LL_OPAMP_INVERTINGINPUT_IO0 LL_OPAMP_INPUT_INVERT_IO0
+#define LL_OPAMP_INVERTINGINPUT_IO1 LL_OPAMP_INPUT_INVERT_IO1
+#define LL_OPAMP_INVERTINGINPUT_CONNECT_NO LL_OPAMP_INPUT_INVERT_CONNECT_NO
+
+#define LL_OPAMP_INPUT_NONINVERT_DAC1_CH1 LL_OPAMP_INPUT_NONINV_DAC1_CH1
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EC_TRIMMING_MODE OPAMP trimming mode
+ * @{
+ */
+#define LL_OPAMP_TRIMMING_FACTORY 0x00000000U /*!< OPAMP trimming factors set to factory values */
+#define LL_OPAMP_TRIMMING_USER (OPAMP_CSR_USERTRIM) /*!< OPAMP trimming factors set to user values */
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EC_TRIMMING_TRANSISTORS_DIFF_PAIR OPAMP trimming of transistors differential pair NMOS or PMOS
+ * @{
+ */
+#define LL_OPAMP_TRIMMING_NMOS (OPAMP_OTR_TRIMOFFSETN) /*!< OPAMP trimming of transistors differential pair NMOS */
+#define LL_OPAMP_TRIMMING_PMOS (OPAMP_OTR_TRIMOFFSETP | OPAMP_CSR_CALSEL) /*!< OPAMP trimming of transistors differential pair PMOS */
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EC_HW_DELAYS Definitions of OPAMP hardware constraints delays
+ * @note Only OPAMP IP HW delays are defined in OPAMP LL driver driver,
+ * not timeout values.
+ * For details on delays values, refer to descriptions in source code
+ * above each literal definition.
+ * @{
+ */
+
+/* Delay for OPAMP startup time (transition from state disable to enable). */
+/* Note: OPAMP startup time depends on board application environment: */
+/* impedance connected to OPAMP output. */
+/* The delay below is specified under conditions: */
+/* - OPAMP in mode low power */
+/* - OPAMP in functional mode follower */
+/* - load impedance of 4kOhm (min), 50pF (max) */
+/* Literal set to maximum value (refer to device datasheet, */
+/* parameter "tWAKEUP"). */
+/* Unit: us */
+#define LL_OPAMP_DELAY_STARTUP_US ((uint32_t) 30U) /*!< Delay for OPAMP startup time */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup OPAMP_LL_Exported_Macros OPAMP Exported Macros
+ * @{
+ */
+/** @defgroup OPAMP_LL_EM_WRITE_READ Common write and read registers macro
+ * @{
+ */
+/**
+ * @brief Write a value in OPAMP register
+ * @param __INSTANCE__ OPAMP Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_OPAMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in OPAMP register
+ * @param __INSTANCE__ OPAMP Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_OPAMP_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup OPAMP_LL_Exported_Functions OPAMP Exported Functions
+ * @{
+ */
+
+/** @defgroup OPAMP_LL_EF_Configuration_opamp_common Configuration of OPAMP hierarchical scope: common OPAMP instances
+ * @{
+ */
+
+/**
+ * @brief Set OPAMP power range.
+ * @note The OPAMP power range applies to several OPAMP instances
+ * (if several OPAMP instances available on the selected device).
+ * It is mandatory to set already the power range to high for performance purpose.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * OPAMP state:
+ * All OPAMP instances of the OPAMP common group must be disabled.
+ * This check can be done with function @ref LL_OPAMP_IsEnabled() for each
+ * OPAMP instance.
+ * @note LL_OPAMP_POWERSUPPLY_RANGE_HIGH parameter is highly recommended for performance purpose.
+ * @rmtoll CSR OPARANGE LL_OPAMP_SetCommonPowerRange
+ * @param OPAMPxy_COMMON OPAMP common instance
+ * @param PowerRange This parameter can be one of the following values:
+ * @arg @ref LL_OPAMP_POWERSUPPLY_RANGE_LOW
+ * @arg @ref LL_OPAMP_POWERSUPPLY_RANGE_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_SetCommonPowerRange(OPAMP_Common_TypeDef *OPAMPxy_COMMON, uint32_t PowerRange)
+{
+ /* Prevent unused parameter warning */
+ (void)(*OPAMPxy_COMMON);
+
+ MODIFY_REG(OPAMP1->CSR, OPAMP_CSR_OPARANGE, PowerRange);
+}
+
+/**
+ * @brief Get OPAMP power range.
+ * @note The OPAMP power range applies to several OPAMP instances
+ * (if several OPAMP instances available on the selected device).
+ * @rmtoll CSR OPARANGE LL_OPAMP_GetCommonPowerRange
+ * @param OPAMPxy_COMMON OPAMP common instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_OPAMP_POWERSUPPLY_RANGE_LOW
+ * @arg @ref LL_OPAMP_POWERSUPPLY_RANGE_HIGH
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_GetCommonPowerRange(OPAMP_Common_TypeDef *OPAMPxy_COMMON)
+{
+ /* Prevent unused parameter warning */
+ (void)(*OPAMPxy_COMMON);
+
+ return (uint32_t)(READ_BIT(OPAMP1->CSR, OPAMP_CSR_OPARANGE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EF_CONFIGURATION_OPAMP_INSTANCE Configuration of OPAMP hierarchical scope: OPAMP instance
+ * @{
+ */
+
+/**
+ * @brief Set OPAMP power mode.
+ * @note The OPAMP must be disabled to change this configuration.
+ * @rmtoll CSR OPALPM LL_OPAMP_SetPowerMode
+ * @param OPAMPx OPAMP instance
+ * @param PowerMode This parameter can be one of the following values:
+ * @arg @ref LL_OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED
+ * @arg @ref LL_OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED
+ * @arg @ref LL_OPAMP_POWERMODE_LOWPOWER_NORMALSPEED
+ * @arg @ref LL_OPAMP_POWERMODE_LOWPOWER_HIGHSPEED
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_SetPowerMode(OPAMP_TypeDef *OPAMPx, uint32_t PowerMode)
+{
+ MODIFY_REG(OPAMPx->CSR, OPAMP_POWERMODE_CSR_BIT_MASK, PowerMode);
+}
+
+/**
+ * @brief Get OPAMP power mode.
+ * @rmtoll CSR OPALPM & HSM LL_OPAMP_GetPowerMode
+ * @param OPAMPx OPAMP instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED
+ * @arg @ref LL_OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED
+ * @arg @ref LL_OPAMP_POWERMODE_LOWPOWER_NORMALSPEED
+ * @arg @ref LL_OPAMP_POWERMODE_LOWPOWER_HIGHSPEED
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_GetPowerMode(OPAMP_TypeDef *OPAMPx)
+{
+ uint32_t power_mode = (READ_BIT(OPAMPx->CSR, OPAMP_POWERMODE_CSR_BIT_MASK));
+
+ return (uint32_t)(power_mode);
+}
+
+/**
+ * @brief Set OPAMP mode calibration or functional.
+ * @note OPAMP mode corresponds to functional or calibration mode:
+ * - functional mode: OPAMP operation in standalone, follower, ...
+ * Set functional mode using function
+ * @ref LL_OPAMP_SetFunctionalMode().
+ * - calibration mode: offset calibration of the selected
+ * transistors differential pair NMOS or PMOS.
+ * @note On this STM32 series, during calibration, OPAMP functional
+ * mode must be set to standalone or follower mode
+ * (in order to open internal connections to resistors
+ * of PGA mode).
+ * Refer to function @ref LL_OPAMP_SetFunctionalMode().
+ * @rmtoll CSR CALON LL_OPAMP_SetMode
+ * @param OPAMPx OPAMP instance
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_OPAMP_MODE_FUNCTIONAL
+ * @arg @ref LL_OPAMP_MODE_CALIBRATION
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_SetMode(OPAMP_TypeDef *OPAMPx, uint32_t Mode)
+{
+ MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_CALON, Mode);
+}
+
+/**
+ * @brief Get OPAMP mode calibration or functional.
+ * @note OPAMP mode corresponds to functional or calibration mode:
+ * - functional mode: OPAMP operation in standalone, follower, ...
+ * Set functional mode using function
+ * @ref LL_OPAMP_SetFunctionalMode().
+ * - calibration mode: offset calibration of the selected
+ * transistors differential pair NMOS or PMOS.
+ * @rmtoll CSR CALON LL_OPAMP_GetMode
+ * @param OPAMPx OPAMP instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_OPAMP_MODE_FUNCTIONAL
+ * @arg @ref LL_OPAMP_MODE_CALIBRATION
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_GetMode(OPAMP_TypeDef *OPAMPx)
+{
+ return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALON));
+}
+
+/**
+ * @brief Set OPAMP functional mode by setting internal connections.
+ * OPAMP operation in standalone, follower, ...
+ * @note This function reset bit of calibration mode to ensure
+ * to be in functional mode, in order to have OPAMP parameters
+ * (inputs selection, ...) set with the corresponding OPAMP mode
+ * to be effective.
+ * @rmtoll CSR OPAMODE LL_OPAMP_SetFunctionalMode
+ * @param OPAMPx OPAMP instance
+ * @param FunctionalMode This parameter can be one of the following values:
+ * @arg @ref LL_OPAMP_MODE_STANDALONE
+ * @arg @ref LL_OPAMP_MODE_FOLLOWER
+ * @arg @ref LL_OPAMP_MODE_PGA
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_SetFunctionalMode(OPAMP_TypeDef *OPAMPx, uint32_t FunctionalMode)
+{
+ /* Note: Bit OPAMP_CSR_CALON reset to ensure to be in functional mode */
+ MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_OPAMODE | OPAMP_CSR_CALON, FunctionalMode);
+}
+
+/**
+ * @brief Get OPAMP functional mode from setting of internal connections.
+ * OPAMP operation in standalone, follower, ...
+ * @rmtoll CSR OPAMODE LL_OPAMP_GetFunctionalMode
+ * @param OPAMPx OPAMP instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_OPAMP_MODE_STANDALONE
+ * @arg @ref LL_OPAMP_MODE_FOLLOWER
+ * @arg @ref LL_OPAMP_MODE_PGA
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_GetFunctionalMode(OPAMP_TypeDef *OPAMPx)
+{
+ return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMODE));
+}
+
+/**
+ * @brief Set OPAMP PGA gain.
+ * @note Preliminarily, OPAMP must be set in mode PGA
+ * using function @ref LL_OPAMP_SetFunctionalMode().
+ * @rmtoll CSR PGGAIN LL_OPAMP_SetPGAGain
+ * @param OPAMPx OPAMP instance
+ * @param PGAGain This parameter can be one of the following values:
+ * @arg @ref LL_OPAMP_PGA_GAIN_2
+ * @arg @ref LL_OPAMP_PGA_GAIN_4
+ * @arg @ref LL_OPAMP_PGA_GAIN_8
+ * @arg @ref LL_OPAMP_PGA_GAIN_16
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_SetPGAGain(OPAMP_TypeDef *OPAMPx, uint32_t PGAGain)
+{
+ MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_PGA_GAIN, PGAGain);
+}
+
+/**
+ * @brief Get OPAMP PGA gain.
+ * @note Preliminarily, OPAMP must be set in mode PGA
+ * using function @ref LL_OPAMP_SetFunctionalMode().
+ * @rmtoll CSR PGGAIN LL_OPAMP_GetPGAGain
+ * @param OPAMPx OPAMP instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_OPAMP_PGA_GAIN_2
+ * @arg @ref LL_OPAMP_PGA_GAIN_4
+ * @arg @ref LL_OPAMP_PGA_GAIN_8
+ * @arg @ref LL_OPAMP_PGA_GAIN_16
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_GetPGAGain(OPAMP_TypeDef *OPAMPx)
+{
+ return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_PGA_GAIN));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EF_CONFIGURATION_INPUTS Configuration of OPAMP inputs
+ * @{
+ */
+
+/**
+ * @brief Set OPAMP non-inverting input connection.
+ * @rmtoll CSR VPSEL LL_OPAMP_SetInputNonInverting
+ * @param OPAMPx OPAMP instance
+ * @param InputNonInverting This parameter can be one of the following values:
+ * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0
+ * @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH1
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_SetInputNonInverting(OPAMP_TypeDef *OPAMPx, uint32_t InputNonInverting)
+{
+ MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_VP_SEL, InputNonInverting);
+}
+
+/**
+ * @brief Get OPAMP non-inverting input connection.
+ * @rmtoll CSR VPSEL LL_OPAMP_GetInputNonInverting
+ * @param OPAMPx OPAMP instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0
+ * @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH1
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInverting(OPAMP_TypeDef *OPAMPx)
+{
+ return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_VP_SEL));
+}
+
+/**
+ * @brief Set OPAMP inverting input connection.
+ * @note OPAMP inverting input is used with OPAMP in mode standalone
+ * or PGA with external capacitors for filtering circuit.
+ * Otherwise (OPAMP in mode follower), OPAMP inverting input
+ * is not used (not connected to GPIO pin).
+ * @rmtoll CSR VMSEL LL_OPAMP_SetInputInverting
+ * @param OPAMPx OPAMP instance
+ * @param InputInverting This parameter can be one of the following values:
+ * @arg @ref LL_OPAMP_INPUT_INVERT_IO0
+ * @arg @ref LL_OPAMP_INPUT_INVERT_IO1
+ * @arg @ref LL_OPAMP_INPUT_INVERT_CONNECT_NO
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_SetInputInverting(OPAMP_TypeDef *OPAMPx, uint32_t InputInverting)
+{
+ MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_VM_SEL, InputInverting);
+}
+
+/**
+ * @brief Get OPAMP inverting input connection.
+ * @rmtoll CSR VMSEL LL_OPAMP_GetInputInverting
+ * @param OPAMPx OPAMP instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_OPAMP_INPUT_INVERT_IO0
+ * @arg @ref LL_OPAMP_INPUT_INVERT_IO1
+ * @arg @ref LL_OPAMP_INPUT_INVERT_CONNECT_NO
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_GetInputInverting(OPAMP_TypeDef *OPAMPx)
+{
+ return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_VM_SEL));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EF_Configuration_Legacy_Functions Configuration of OPAMP, legacy functions name
+ * @{
+ */
+/* Old functions name kept for legacy purpose, to be replaced by the */
+/* current functions name. */
+__STATIC_INLINE void LL_OPAMP_SetNonInvertingInput(OPAMP_TypeDef *OPAMPx, uint32_t NonInvertingInput)
+{
+ LL_OPAMP_SetInputNonInverting(OPAMPx, NonInvertingInput);
+}
+
+__STATIC_INLINE void LL_OPAMP_SetInvertingInput(OPAMP_TypeDef *OPAMPx, uint32_t InvertingInput)
+{
+ LL_OPAMP_SetInputInverting(OPAMPx, InvertingInput);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EF_OPAMP_TRIMMING Configuration and operation of OPAMP trimming
+ * @{
+ */
+
+/**
+ * @brief Set OPAMP trimming mode.
+ * @rmtoll CSR USERTRIM LL_OPAMP_SetTrimmingMode
+ * @param OPAMPx OPAMP instance
+ * @param TrimmingMode This parameter can be one of the following values:
+ * @arg @ref LL_OPAMP_TRIMMING_FACTORY
+ * @arg @ref LL_OPAMP_TRIMMING_USER
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_SetTrimmingMode(OPAMP_TypeDef *OPAMPx, uint32_t TrimmingMode)
+{
+ MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_USERTRIM, TrimmingMode);
+}
+
+/**
+ * @brief Get OPAMP trimming mode.
+ * @rmtoll CSR USERTRIM LL_OPAMP_GetTrimmingMode
+ * @param OPAMPx OPAMP instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_OPAMP_TRIMMING_FACTORY
+ * @arg @ref LL_OPAMP_TRIMMING_USER
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingMode(OPAMP_TypeDef *OPAMPx)
+{
+ return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_USERTRIM));
+}
+
+/**
+ * @brief Set OPAMP offset to calibrate the selected transistors
+ * differential pair NMOS or PMOS.
+ * @note Preliminarily, OPAMP must be set in mode calibration
+ * using function @ref LL_OPAMP_SetMode().
+ * @rmtoll CSR CALSEL LL_OPAMP_SetCalibrationSelection
+ * @param OPAMPx OPAMP instance
+ * @param TransistorsDiffPair This parameter can be one of the following values:
+ * @arg @ref LL_OPAMP_TRIMMING_NMOS
+ * @arg @ref LL_OPAMP_TRIMMING_PMOS
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_SetCalibrationSelection(OPAMP_TypeDef *OPAMPx, uint32_t TransistorsDiffPair)
+{
+ /* Parameter used with mask "OPAMP_TRIMMING_SELECT_MASK" because */
+ /* containing other bits reserved for other purpose. */
+ MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_CALSEL, (TransistorsDiffPair & OPAMP_TRIMMING_SELECT_MASK));
+}
+
+/**
+ * @brief Get OPAMP offset to calibrate the selected transistors
+ * differential pair NMOS or PMOS.
+ * @note Preliminarily, OPAMP must be set in mode calibration
+ * using function @ref LL_OPAMP_SetMode().
+ * @rmtoll CSR CALSEL LL_OPAMP_GetCalibrationSelection
+ * @param OPAMPx OPAMP instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_OPAMP_TRIMMING_NMOS
+ * @arg @ref LL_OPAMP_TRIMMING_PMOS
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(OPAMP_TypeDef *OPAMPx)
+{
+ uint32_t CalibrationSelection = (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALSEL));
+
+ return (CalibrationSelection |
+ (((CalibrationSelection & OPAMP_CSR_CALSEL) == 0UL) ? OPAMP_OTR_TRIMOFFSETN : OPAMP_OTR_TRIMOFFSETP));
+}
+
+/**
+ * @brief Get OPAMP calibration result of toggling output.
+ * @note This functions returns:
+ * 0 if OPAMP calibration output is reset
+ * 1 if OPAMP calibration output is set
+ * @rmtoll CSR CALOUT LL_OPAMP_IsCalibrationOutputSet
+ * @param OPAMPx OPAMP instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_IsCalibrationOutputSet(OPAMP_TypeDef *OPAMPx)
+{
+ return ((READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALOUT) == OPAMP_CSR_CALOUT) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set OPAMP trimming factor for the selected transistors
+ * differential pair NMOS or PMOS, corresponding to the selected
+ * power mode.
+ * @rmtoll OTR TRIMOFFSETN LL_OPAMP_SetTrimmingValue
+ * OTR TRIMOFFSETP LL_OPAMP_SetTrimmingValue
+ * LPOTR TRIMLPOFFSETN LL_OPAMP_SetTrimmingValue
+ * LPOTR TRIMLPOFFSETP LL_OPAMP_SetTrimmingValue
+ * @param OPAMPx OPAMP instance
+ * @param PowerMode This parameter can be one of the following values:
+ * @arg @ref LL_OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED
+ * @arg @ref LL_OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED
+ * @arg @ref LL_OPAMP_POWERMODE_LOWPOWER_NORMALSPEED
+ * @arg @ref LL_OPAMP_POWERMODE_LOWPOWER_HIGHSPEED
+ * @param TransistorsDiffPair This parameter can be one of the following values:
+ * @arg @ref LL_OPAMP_TRIMMING_NMOS
+ * @arg @ref LL_OPAMP_TRIMMING_PMOS
+ * @param TrimmingValue 0x00...0x1F
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_SetTrimmingValue(OPAMP_TypeDef *OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair,
+ uint32_t TrimmingValue)
+{
+ uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMPx->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK));
+
+ /* Set bits with position in register depending on parameter */
+ /* "TransistorsDiffPair". */
+ /* Parameter used with mask "OPAMP_TRIMMING_VALUE_MASK" because */
+ /* containing other bits reserved for other purpose. */
+ MODIFY_REG(*preg,
+ (TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK),
+ TrimmingValue << (
+ (TransistorsDiffPair == LL_OPAMP_TRIMMING_NMOS) ? OPAMP_OTR_TRIMOFFSETN_Pos : OPAMP_OTR_TRIMOFFSETP_Pos)
+ );
+}
+
+/**
+ * @brief Get OPAMP trimming factor for the selected transistors
+ * differential pair NMOS or PMOS, corresponding to the selected
+ * power mode.
+ * @rmtoll OTR TRIMOFFSETN LL_OPAMP_GetTrimmingValue
+ * OTR TRIMOFFSETP LL_OPAMP_GetTrimmingValue
+ * LPOTR TRIMLPOFFSETN LL_OPAMP_GetTrimmingValue
+ * LPOTR TRIMLPOFFSETP LL_OPAMP_GetTrimmingValue
+ * @param OPAMPx OPAMP instance
+ * @param PowerMode This parameter can be one of the following values:
+ * @arg @ref LL_OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED
+ * @arg @ref LL_OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED
+ * @arg @ref LL_OPAMP_POWERMODE_LOWPOWER_NORMALSPEED
+ * @arg @ref LL_OPAMP_POWERMODE_LOWPOWER_HIGHSPEED
+ * @param TransistorsDiffPair This parameter can be one of the following values:
+ * @arg @ref LL_OPAMP_TRIMMING_NMOS
+ * @arg @ref LL_OPAMP_TRIMMING_PMOS
+ * @retval 0x0...0x1F
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingValue(OPAMP_TypeDef *OPAMPx, uint32_t PowerMode,
+ uint32_t TransistorsDiffPair)
+{
+ const uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMPx->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK));
+
+ /* Retrieve bits with position in register depending on parameter */
+ /* "TransistorsDiffPair". */
+ /* Parameter used with mask "OPAMP_TRIMMING_VALUE_MASK" because */
+ /* containing other bits reserved for other purpose. */
+ return (uint32_t)(
+ READ_BIT(*preg, (TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK)) >>
+ (
+ (TransistorsDiffPair == LL_OPAMP_TRIMMING_NMOS) ? OPAMP_OTR_TRIMOFFSETN_Pos : OPAMP_OTR_TRIMOFFSETP_Pos));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EF_OPERATION Operation on OPAMP instance
+ * @{
+ */
+/**
+ * @brief Enable OPAMP instance.
+ * @note After enable from off state, OPAMP requires a delay
+ * to fulfill wake up time specification.
+ * Refer to device datasheet, parameter "tWAKEUP".
+ * @rmtoll CSR OPAMPXEN LL_OPAMP_Enable
+ * @param OPAMPx OPAMP instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_Enable(OPAMP_TypeDef *OPAMPx)
+{
+ SET_BIT(OPAMPx->CSR, OPAMP_CSR_OPAEN);
+}
+
+/**
+ * @brief Disable OPAMP instance.
+ * @rmtoll CSR OPAMPXEN LL_OPAMP_Disable
+ * @param OPAMPx OPAMP instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_Disable(OPAMP_TypeDef *OPAMPx)
+{
+ CLEAR_BIT(OPAMPx->CSR, OPAMP_CSR_OPAEN);
+}
+
+/**
+ * @brief Get OPAMP instance enable state
+ * (0: OPAMP is disabled, 1: OPAMP is enabled)
+ * @rmtoll CSR OPAMPXEN LL_OPAMP_IsEnabled
+ * @param OPAMPx OPAMP instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_IsEnabled(OPAMP_TypeDef *OPAMPx)
+{
+ return ((READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPAEN) == (OPAMP_CSR_OPAEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup OPAMP_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_OPAMP_DeInit(OPAMP_TypeDef *OPAMPx);
+ErrorStatus LL_OPAMP_Init(OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_InitStruct);
+void LL_OPAMP_StructInit(LL_OPAMP_InitTypeDef *OPAMP_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* OPAMP1 || OPAMP2 */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_LL_OPAMP_H */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_pka.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_pka.h
new file mode 100644
index 00000000..a6fe9b64
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_pka.h
@@ -0,0 +1,602 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_pka.h
+ * @author MCD Application Team
+ * @brief Header file of PKA LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_LL_PKA_H
+#define STM32U5xx_LL_PKA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx.h"
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined(PKA)
+
+/** @defgroup PKA_LL PKA
+ * @{
+ */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup PKA_LL_ES_INIT PKA Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief PKA Init structures definition
+ */
+typedef struct
+{
+ uint32_t Mode; /*!< Specifies the PKA operation mode.
+ This parameter can be a value of @ref PKA_LL_EC_MODE.
+
+ This feature can be modified afterwards using unitary function @ref LL_PKA_SetMode(). */
+} LL_PKA_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PKA_LL_Exported_Constants PKA Exported Constants
+ * @{
+ */
+
+/** @defgroup PKA_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_PKA_ReadReg function
+ * @{
+ */
+#define LL_PKA_SR_ADDRERRF PKA_SR_ADDRERRF
+#define LL_PKA_SR_RAMERRF PKA_SR_RAMERRF
+#define LL_PKA_SR_PROCENDF PKA_SR_PROCENDF
+#define LL_PKA_SR_BUSY PKA_SR_BUSY
+#define LL_PKA_SR_INITOK PKA_SR_INITOK
+#define LL_PKA_SR_OPERRF PKA_SR_OPERRF
+/**
+ * @}
+ */
+
+/** @defgroup PKA_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_PKA_ReadReg and LL_PKA_WriteReg functions
+ * @{
+ */
+#define LL_PKA_CR_ADDRERRIE PKA_CR_ADDRERRIE
+#define LL_PKA_CR_RAMERRIE PKA_CR_RAMERRIE
+#define LL_PKA_CR_PROCENDIE PKA_CR_PROCENDIE
+#define LL_PKA_CLRFR_PROCENDFC PKA_CLRFR_PROCENDFC
+#define LL_PKA_CLRFR_RAMERRFC PKA_CLRFR_RAMERRFC
+#define LL_PKA_CLRFR_ADDRERRFC PKA_CLRFR_ADDRERRFC
+#define LL_PKA_CR_OPERRIE PKA_CR_OPERRIE
+#define LL_PKA_CLRFR_OPERRFC PKA_CLRFR_OPERRFC
+/**
+ * @}
+ */
+
+/** @defgroup PKA_LL_EC_MODE Operation Mode
+ * @brief List of opearation mode.
+ * @{
+ */
+#define LL_PKA_MODE_MODULAR_EXP ((uint32_t)0x00000000U) /*!< modular exponentiation */
+#define LL_PKA_MODE_MONTGOMERY_PARAM ((uint32_t)0x00000001U) /*!< Compute Montgomery parameter only */
+#define LL_PKA_MODE_MODULAR_EXP_FAST ((uint32_t)0x00000002U) /*!< modular exponentiation fast mode */
+#define LL_PKA_MODE_MODULAR_EXP_PROTECT ((uint32_t)0x00000003U) /*!< modular exponentiation protect mode */
+#define LL_PKA_MODE_ECC_MUL ((uint32_t)0x00000020U) /*!< compute ECC kP operation */
+#define LL_PKA_MODE_ECC_COMPLETE_ADD ((uint32_t)0x00000023U) /*!< ECC complete addition */
+#define LL_PKA_MODE_ECDSA_SIGNATURE ((uint32_t)0x00000024U) /*!< ECDSA signature */
+#define LL_PKA_MODE_ECDSA_VERIFICATION ((uint32_t)0x00000026U) /*!< ECDSA verification */
+#define LL_PKA_MODE_POINT_CHECK ((uint32_t)0x00000028U) /*!< Point check */
+#define LL_PKA_MODE_RSA_CRT_EXP ((uint32_t)0x00000007U) /*!< RSA CRT exponentiation */
+#define LL_PKA_MODE_MODULAR_INV ((uint32_t)0x00000008U) /*!< Modular inversion */
+#define LL_PKA_MODE_ARITHMETIC_ADD ((uint32_t)0x00000009U) /*!< Arithmetic addition */
+#define LL_PKA_MODE_ARITHMETIC_SUB ((uint32_t)0x0000000AU) /*!< Arithmetic subtraction */
+#define LL_PKA_MODE_ARITHMETIC_MUL ((uint32_t)0x0000000BU) /*!< Arithmetic multiplication */
+#define LL_PKA_MODE_COMPARISON ((uint32_t)0x0000000CU) /*!< Comparison */
+#define LL_PKA_MODE_MODULAR_REDUC ((uint32_t)0x0000000DU) /*!< Modular reduction */
+#define LL_PKA_MODE_MODULAR_ADD ((uint32_t)0x0000000EU) /*!< Modular addition */
+#define LL_PKA_MODE_MODULAR_SUB ((uint32_t)0x0000000FU) /*!< Modular subtraction */
+#define LL_PKA_MODE_MONTGOMERY_MUL ((uint32_t)0x00000010U) /*!< Montgomery multiplication */
+#define LL_PKA_MODE_DOUBLE_BASE_LADDER ((uint32_t)0x00000027U) /*!< Double base ladder */
+#define LL_PKA_MODE_ECC_PROJECTIVE_AFF ((uint32_t)0x0000002FU) /*!< ECC projective to affine */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PKA_LL_Exported_Macros PKA Exported Macros
+ * @{
+ */
+
+/** @defgroup PKA_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in PKA register
+ * @param __INSTANCE__ PKA Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_PKA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in PKA register
+ * @param __INSTANCE__ PKA Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_PKA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup PKA_LL_Exported_Functions PKA Exported Functions
+ * @{
+ */
+
+/** @defgroup PKA_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Configure PKA peripheral.
+ * @brief Set PKA operating mode.
+ * @rmtoll CR MODE LL_PKA_Config
+ * @param PKAx PKA Instance.
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM
+ * @arg @ref LL_PKA_MODE_MODULAR_EXP
+ * @arg @ref LL_PKA_MODE_ECDSA_SIGNATURE
+ * @arg @ref LL_PKA_MODE_ECDSA_VERIFICATION
+ * @arg @ref LL_PKA_MODE_POINT_CHECK
+ * @arg @ref LL_PKA_MODE_RSA_CRT_EXP
+ * @arg @ref LL_PKA_MODE_MODULAR_INV
+ * @arg @ref LL_PKA_MODE_ARITHMETIC_ADD
+ * @arg @ref LL_PKA_MODE_ARITHMETIC_SUB
+ * @arg @ref LL_PKA_MODE_ARITHMETIC_MUL
+ * @arg @ref LL_PKA_MODE_COMPARISON
+ * @arg @ref LL_PKA_MODE_MODULAR_REDUC
+ * @arg @ref LL_PKA_MODE_MODULAR_ADD
+ * @arg @ref LL_PKA_MODE_MODULAR_SUB
+ * @arg @ref LL_PKA_MODE_MONTGOMERY_MUL
+ * @arg @ref LL_PKA_MODE_MODULAR_EXP_PROTECT
+ * @arg @ref LL_PKA_MODE_DOUBLE_BASE_LADDER
+ * @arg @ref LL_PKA_MODE_ECC_PROJECTIVE_AFF
+ * @arg @ref LL_PKA_MODE_ECC_COMPLETE_ADD
+ * @arg @ref LL_PKA_MODE_ECC_MUL
+ * @arg @ref LL_PKA_MODE_MODULAR_EXP_FAST
+ */
+__STATIC_INLINE void LL_PKA_Config(PKA_TypeDef *PKAx, uint32_t Mode)
+{
+ MODIFY_REG(PKAx->CR, (PKA_CR_MODE), (Mode << PKA_CR_MODE_Pos));
+}
+
+/**
+ * @brief Enable PKA peripheral.
+ * @rmtoll CR EN LL_PKA_Enable
+ * @param PKAx PKA Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_PKA_Enable(PKA_TypeDef *PKAx)
+{
+ SET_BIT(PKAx->CR, PKA_CR_EN);
+}
+
+/**
+ * @brief Disable PKA peripheral.
+ * @rmtoll CR EN LL_PKA_Disable
+ * @param PKAx PKA Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_PKA_Disable(PKA_TypeDef *PKAx)
+{
+ CLEAR_BIT(PKAx->CR, PKA_CR_EN);
+}
+
+/**
+ * @brief Check if the PKA peripheral is enabled or disabled.
+ * @rmtoll CR EN LL_PKA_IsEnabled
+ * @param PKAx PKA Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PKA_IsEnabled(PKA_TypeDef *PKAx)
+{
+ return ((READ_BIT(PKAx->CR, PKA_CR_EN) == (PKA_CR_EN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set PKA operating mode.
+ * @rmtoll CR MODE LL_PKA_SetMode
+ * @param PKAx PKA Instance.
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM
+ * @arg @ref LL_PKA_MODE_MODULAR_EXP
+ * @arg @ref LL_PKA_MODE_ECDSA_SIGNATURE
+ * @arg @ref LL_PKA_MODE_ECDSA_VERIFICATION
+ * @arg @ref LL_PKA_MODE_POINT_CHECK
+ * @arg @ref LL_PKA_MODE_RSA_CRT_EXP
+ * @arg @ref LL_PKA_MODE_MODULAR_INV
+ * @arg @ref LL_PKA_MODE_ARITHMETIC_ADD
+ * @arg @ref LL_PKA_MODE_ARITHMETIC_SUB
+ * @arg @ref LL_PKA_MODE_ARITHMETIC_MUL
+ * @arg @ref LL_PKA_MODE_COMPARISON
+ * @arg @ref LL_PKA_MODE_MODULAR_REDUC
+ * @arg @ref LL_PKA_MODE_MODULAR_ADD
+ * @arg @ref LL_PKA_MODE_MODULAR_SUB
+ * @arg @ref LL_PKA_MODE_MONTGOMERY_MUL
+ * @arg @ref LL_PKA_MODE_MODULAR_EXP_PROTECT
+ * @arg @ref LL_PKA_MODE_DOUBLE_BASE_LADDER
+ * @arg @ref LL_PKA_MODE_ECC_PROJECTIVE_AFF
+ * @arg @ref LL_PKA_MODE_ECC_COMPLETE_ADD
+ * @arg @ref LL_PKA_MODE_ECC_MUL
+ * @arg @ref LL_PKA_MODE_MODULAR_EXP_FAST
+ * @retval None
+ */
+__STATIC_INLINE void LL_PKA_SetMode(PKA_TypeDef *PKAx, uint32_t Mode)
+{
+ MODIFY_REG(PKAx->CR, PKA_CR_MODE, Mode << PKA_CR_MODE_Pos);
+}
+
+/**
+ * @brief Get PKA operating mode.
+ * @rmtoll CR MODE LL_PKA_GetMode
+ * @param PKAx PKA Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM
+ * @arg @ref LL_PKA_MODE_MODULAR_EXP
+ * @arg @ref LL_PKA_MODE_ECDSA_SIGNATURE
+ * @arg @ref LL_PKA_MODE_ECDSA_VERIFICATION
+ * @arg @ref LL_PKA_MODE_POINT_CHECK
+ * @arg @ref LL_PKA_MODE_RSA_CRT_EXP
+ * @arg @ref LL_PKA_MODE_MODULAR_INV
+ * @arg @ref LL_PKA_MODE_ARITHMETIC_ADD
+ * @arg @ref LL_PKA_MODE_ARITHMETIC_SUB
+ * @arg @ref LL_PKA_MODE_ARITHMETIC_MUL
+ * @arg @ref LL_PKA_MODE_COMPARISON
+ * @arg @ref LL_PKA_MODE_MODULAR_REDUC
+ * @arg @ref LL_PKA_MODE_MODULAR_ADD
+ * @arg @ref LL_PKA_MODE_MODULAR_SUB
+ * @arg @ref LL_PKA_MODE_MONTGOMERY_MUL
+ * @arg @ref LL_PKA_MODE_MODULAR_EXP_PROTECT
+ * @arg @ref LL_PKA_MODE_DOUBLE_BASE_LADDER
+ * @arg @ref LL_PKA_MODE_ECC_PROJECTIVE_AFF
+ * @arg @ref LL_PKA_MODE_ECC_COMPLETE_ADD
+ * @arg @ref LL_PKA_MODE_ECC_MUL
+ * @arg @ref LL_PKA_MODE_MODULAR_EXP_FAST
+ */
+__STATIC_INLINE uint32_t LL_PKA_GetMode(PKA_TypeDef *PKAx)
+{
+ return (uint32_t)(READ_BIT(PKAx->CR, PKA_CR_MODE) >> PKA_CR_MODE_Pos);
+}
+
+/**
+ * @brief Start the operation selected using LL_PKA_SetMode.
+ * @rmtoll CR START LL_PKA_Start
+ * @param PKAx PKA Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_PKA_Start(PKA_TypeDef *PKAx)
+{
+ SET_BIT(PKAx->CR, PKA_CR_START);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup PKA_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable address error interrupt.
+ * @rmtoll CR ADDRERRIE LL_PKA_EnableIT_ADDRERR
+ * @param PKAx PKA Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_PKA_EnableIT_ADDRERR(PKA_TypeDef *PKAx)
+{
+ SET_BIT(PKAx->CR, PKA_CR_ADDRERRIE);
+}
+
+/**
+ * @brief Enable RAM error interrupt.
+ * @rmtoll CR RAMERRIE LL_PKA_EnableIT_RAMERR
+ * @param PKAx PKA Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_PKA_EnableIT_RAMERR(PKA_TypeDef *PKAx)
+{
+ SET_BIT(PKAx->CR, PKA_CR_RAMERRIE);
+}
+
+/**
+ * @brief Enable OPERATION error interrupt.
+ * @rmtoll CR OPERRIE LL_PKA_EnableIT_OPERR
+ * @param PKAx PKA Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_PKA_EnableIT_OPERR(PKA_TypeDef *PKAx)
+{
+ SET_BIT(PKAx->CR, PKA_CR_OPERRIE);
+}
+
+/**
+ * @brief Enable end of operation interrupt.
+ * @rmtoll CR PROCENDIE LL_PKA_EnableIT_PROCEND
+ * @param PKAx PKA Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_PKA_EnableIT_PROCEND(PKA_TypeDef *PKAx)
+{
+ SET_BIT(PKAx->CR, PKA_CR_PROCENDIE);
+}
+
+/**
+ * @brief Disable address error interrupt.
+ * @rmtoll CR ADDRERRIE LL_PKA_DisableIT_ADDERR
+ * @param PKAx PKA Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_PKA_DisableIT_ADDERR(PKA_TypeDef *PKAx)
+{
+ CLEAR_BIT(PKAx->CR, PKA_CR_ADDRERRIE);
+}
+
+/**
+ * @brief Disable RAM error interrupt.
+ * @rmtoll CR RAMERRIE LL_PKA_DisableIT_RAMERR
+ * @param PKAx PKA Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_PKA_DisableIT_RAMERR(PKA_TypeDef *PKAx)
+{
+ CLEAR_BIT(PKAx->CR, PKA_CR_RAMERRIE);
+}
+
+/**
+ * @brief Disable End of operation interrupt.
+ * @rmtoll CR PROCENDIE LL_PKA_DisableIT_PROCEND
+ * @param PKAx PKA Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_PKA_DisableIT_PROCEND(PKA_TypeDef *PKAx)
+{
+ CLEAR_BIT(PKAx->CR, PKA_CR_PROCENDIE);
+}
+
+/**
+ * @brief Disable OPERATION error interrupt.
+ * @rmtoll CR OPERRIE LL_PKA_EnableIT_OPERR
+ * @param PKAx PKA Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_PKA_DisableIT_OPERR(PKA_TypeDef *PKAx)
+{
+ CLEAR_BIT(PKAx->CR, PKA_CR_OPERRIE);
+}
+
+/**
+ * @brief Check if address error interrupt is enabled.
+ * @rmtoll CR ADDRERRIE LL_PKA_IsEnabledIT_ADDRERR
+ * @param PKAx PKA Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_ADDRERR(PKA_TypeDef *PKAx)
+{
+ return ((READ_BIT(PKAx->CR, PKA_CR_ADDRERRIE) == (PKA_CR_ADDRERRIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if RAM error interrupt is enabled.
+ * @rmtoll CR RAMERRIE LL_PKA_IsEnabledIT_RAMERR
+ * @param PKAx PKA Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_RAMERR(PKA_TypeDef *PKAx)
+{
+ return ((READ_BIT(PKAx->CR, PKA_CR_RAMERRIE) == (PKA_CR_RAMERRIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if OPERATION error interrupt is enabled.
+ * @rmtoll CR OPERRIE LL_PKA_IsEnabledIT_OPERR
+ * @param PKAx PKA Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_OPERR(PKA_TypeDef *PKAx)
+{
+ return ((READ_BIT(PKAx->CR, PKA_CR_OPERRIE) == (PKA_CR_OPERRIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if end of operation interrupt is enabled.
+ * @rmtoll CR PROCENDIE LL_PKA_IsEnabledIT_PROCEND
+ * @param PKAx PKA Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_PROCEND(PKA_TypeDef *PKAx)
+{
+ return ((READ_BIT(PKAx->CR, PKA_CR_PROCENDIE) == (PKA_CR_PROCENDIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup PKA_LL_EF_FLAG_Management PKA flag management
+ * @{
+ */
+
+/**
+ * @brief Get PKA address error flag.
+ * @rmtoll SR ADDRERRF LL_PKA_IsActiveFlag_ADDRERR
+ * @param PKAx PKA Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_ADDRERR(PKA_TypeDef *PKAx)
+{
+ return ((READ_BIT(PKAx->SR, PKA_SR_ADDRERRF) == (PKA_SR_ADDRERRF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get PKA RAM error flag.
+ * @rmtoll SR RAMERRF LL_PKA_IsActiveFlag_RAMERR
+ * @param PKAx PKA Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_RAMERR(PKA_TypeDef *PKAx)
+{
+ return ((READ_BIT(PKAx->SR, PKA_SR_RAMERRF) == (PKA_SR_RAMERRF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get PKA OPERATION error flag.
+ * @rmtoll SR OPERRF LL_PKA_IsActiveFlag_OPERR
+ * @param PKAx PKA Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_OPERR(PKA_TypeDef *PKAx)
+{
+ return ((READ_BIT(PKAx->SR, PKA_SR_OPERRF) == (PKA_SR_OPERRF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get PKA end of operation flag.
+ * @rmtoll SR PROCENDF LL_PKA_IsActiveFlag_PROCEND
+ * @param PKAx PKA Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_PROCEND(PKA_TypeDef *PKAx)
+{
+ return ((READ_BIT(PKAx->SR, PKA_SR_PROCENDF) == (PKA_SR_PROCENDF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get PKA busy flag.
+ * @rmtoll SR BUSY LL_PKA_IsActiveFlag_BUSY
+ * @param PKAx PKA Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_BUSY(PKA_TypeDef *PKAx)
+{
+ return ((READ_BIT(PKAx->SR, PKA_SR_BUSY) == (PKA_SR_BUSY)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear PKA address error flag.
+ * @rmtoll CLRFR ADDRERRFC LL_PKA_ClearFlag_ADDERR
+ * @param PKAx PKA Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_PKA_ClearFlag_ADDERR(PKA_TypeDef *PKAx)
+{
+ SET_BIT(PKAx->CLRFR, PKA_CLRFR_ADDRERRFC);
+}
+
+/**
+ * @brief Clear PKA RAM error flag.
+ * @rmtoll CLRFR RAMERRFC LL_PKA_ClearFlag_RAMERR
+ * @param PKAx PKA Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_PKA_ClearFlag_RAMERR(PKA_TypeDef *PKAx)
+{
+ SET_BIT(PKAx->CLRFR, PKA_CLRFR_RAMERRFC);
+}
+
+/**
+ * @brief Clear PKA OPERATION error flag.
+ * @rmtoll CLRFR OPERRFC LL_PKA_ClearFlag_OPERR
+ * @param PKAx PKA Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_PKA_ClearFlag_OPERR(PKA_TypeDef *PKAx)
+{
+ SET_BIT(PKAx->CLRFR, PKA_CLRFR_OPERRFC);
+}
+
+/**
+ * @brief Clear PKA end of operation flag.
+ * @rmtoll CLRFR PROCENDFC LL_PKA_ClearFlag_PROCEND
+ * @param PKAx PKA Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_PKA_ClearFlag_PROCEND(PKA_TypeDef *PKAx)
+{
+ SET_BIT(PKAx->CLRFR, PKA_CLRFR_PROCENDFC);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup PKA_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_PKA_DeInit(PKA_TypeDef *PKAx);
+ErrorStatus LL_PKA_Init(PKA_TypeDef *PKAx, LL_PKA_InitTypeDef *PKA_InitStruct);
+void LL_PKA_StructInit(LL_PKA_InitTypeDef *PKA_InitStruct);
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(PKA) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_LL_PKA_H */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_pwr.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_pwr.h
new file mode 100644
index 00000000..6bac5703
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_pwr.h
@@ -0,0 +1,2631 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_pwr.h
+ * @author MCD Application Team
+ * @brief Header file of PWR LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_LL_PWR_H
+#define STM32U5xx_LL_PWR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx.h"
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined (PWR)
+
+/** @defgroup PWR_LL PWR
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
+ * @{
+ */
+
+/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
+ * @brief Flags defines which can be used with LL_PWR_WriteReg function
+ * @{
+ */
+#define LL_PWR_SR_CSSF PWR_SR_CSSF /*!< Clear Stop and Standby flags */
+#define LL_PWR_WUSCR_CWUF1 PWR_WUSCR_CWUF1 /*!< Clear Wakeup flag 1 */
+#define LL_PWR_WUSCR_CWUF2 PWR_WUSCR_CWUF2 /*!< Clear Wakeup flag 2 */
+#define LL_PWR_WUSCR_CWUF3 PWR_WUSCR_CWUF3 /*!< Clear Wakeup flag 3 */
+#define LL_PWR_WUSCR_CWUF4 PWR_WUSCR_CWUF4 /*!< Clear Wakeup flag 4 */
+#define LL_PWR_WUSCR_CWUF5 PWR_WUSCR_CWUF5 /*!< Clear Wakeup flag 5 */
+#define LL_PWR_WUSCR_CWUF6 PWR_WUSCR_CWUF6 /*!< Clear Wakeup flag 6 */
+#define LL_PWR_WUSCR_CWUF7 PWR_WUSCR_CWUF7 /*!< Clear Wakeup flag 7 */
+#define LL_PWR_WUSCR_CWUF8 PWR_WUSCR_CWUF8 /*!< Clear Wakeup flag 8 */
+#define LL_PWR_WUSCR_CWUF_ALL PWR_WUSCR_CWUF /*!< Clear all Wakeup flags */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_PWR_ReadReg function
+ * @{
+ */
+#define LL_PWR_FLAG_VOSRDY PWR_VOSR_VOSRDY /*!< Voltage scaling ready flag */
+#define LL_PWR_FLAG_BOOSTRDY PWR_VOSR_BOOSTRDY /*!< EPOD booster ready flag */
+#define LL_PWR_FLAG_STOPF PWR_SR_STOPF /*!< Stop flag */
+#define LL_PWR_FLAG_SBF PWR_SR_SBF /*!< Standby flag */
+#define LL_PWR_FLAG_VDDA2RDY PWR_SVMSR_VDDA2RDY /*!< VDDA ready flag (versus 1.8 V threshold) */
+#define LL_PWR_FLAG_VDDA1RDY PWR_SVMSR_VDDA1RDY /*!< VDDA ready flag (versus 1.6 V threshold) */
+#define LL_PWR_FLAG_VDDIO2RDY PWR_SVMSR_VDDIO2RDY /*!< VDDIO2 ready flag */
+#define LL_PWR_FLAG_VDDUSBRDY PWR_SVMSR_VDDUSBRDY /*!< VDDUSB ready flag */
+#define LL_PWR_FLAG_ACTVOSRDY PWR_SVMSR_ACTVOSRDY /*!< Currently applied VOS ready flag */
+#define LL_PWR_FLAG_PVDO PWR_SR2_PVDO /*!< VDD voltage detector output flag */
+#define LL_PWR_FLAG_REGS PWR_SVMSR_REGS /*!< Regulator selection flag */
+#define LL_PWR_FLAG_TEMPH PWR_BDSR_TEMPH /*!< Temperature level flag (versus high threshold) */
+#define LL_PWR_FLAG_TEMPL PWR_BDSR_TEMPL /*!< Temperature level flag (versus low threshold) */
+#define LL_PWR_FLAG_VBATH PWR_BDSR_VBATH /*!< Backup domain voltage level flag (versus high threshold) */
+
+#define LL_PWR_WAKEUP_FLAG1 PWR_WUSR_WUF1 /*!< Wakeup flag 1 */
+#define LL_PWR_WAKEUP_FLAG2 PWR_WUSR_WUF2 /*!< Wakeup flag 2 */
+#define LL_PWR_WAKEUP_FLAG3 PWR_WUSR_WUF3 /*!< Wakeup flag 3 */
+#define LL_PWR_WAKEUP_FLAG4 PWR_WUSR_WUF4 /*!< Wakeup flag 4 */
+#define LL_PWR_WAKEUP_FLAG5 PWR_WUSR_WUF5 /*!< Wakeup flag 5 */
+#define LL_PWR_WAKEUP_FLAG6 PWR_WUSR_WUF6 /*!< Wakeup flag 6 */
+#define LL_PWR_WAKEUP_FLAG7 PWR_WUSR_WUF7 /*!< Wakeup flag 7 */
+#define LL_PWR_WAKEUP_FLAG8 PWR_WUSR_WUF8 /*!< Wakeup flag 8 */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_LOW_POWER_MODE_SELCTION Low Power Mode Selection
+ * @{
+ */
+#define LL_PWR_STOP0_MODE (0U) /*!< Stop 0 mode */
+#define LL_PWR_STOP1_MODE PWR_CR1_LPMS_0 /*!< Stop 1 mode */
+#define LL_PWR_STOP2_MODE PWR_CR1_LPMS_1 /*!< Stop 2 mode */
+#define LL_PWR_STOP3_MODE (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1) /*!< Stop 3 mode */
+#define LL_PWR_STANDBY_MODE PWR_CR1_LPMS_2 /*!< Standby mode */
+#define LL_PWR_SHUTDOWN_MODE (PWR_CR1_LPMS_2 | PWR_CR1_LPMS_1) /*!< Shutdown mode */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_SRAM2_SB_CONTENTS_RETENTION PWR SRAM2 Content Retention in Standby Mode
+ * @note For some products of the U5 family (please see the Reference Manual),
+ * the SRAM2 content is preserved based on the same defines in Stop 3 mode.
+ * @{
+ */
+#define LL_PWR_SRAM2_SB_NO_RETENTION 0U /*!< SRAM2 no retention in Stop 3 and Standby mode */
+#define LL_PWR_SRAM2_SB_PAGE1_RETENTION PWR_CR1_RRSB1 /*!< SRAM2 page 1 (8 KB) retention in Stop 3 and Standby mode */
+#define LL_PWR_SRAM2_SB_PAGE2_RETENTION PWR_CR1_RRSB2 /*!< SRAM2 page 2 (54 KB) retention in Stop 3 and Standby mode */
+#define LL_PWR_SRAM2_SB_FULL_RETENTION (PWR_CR1_RRSB1 | PWR_CR1_RRSB2) /*!< SRAM2 all pages retention in Stop 3 and Standby mode */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_SRAM1_STOP_CONTENTS_RETENTION PWR SRAM1 Content Retention in Stop Mode
+ * @{
+ */
+#define LL_PWR_SRAM1_STOP_NO_RETENTION 0U /*!< SRAM1 no retention in Stop mode (Stop 0, 1, 2, 3) */
+#define LL_PWR_SRAM1_STOP_PAGE1_RETENTION (PWR_CR2_SRAM1PDS1) /*!< SRAM1 page 1 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
+#define LL_PWR_SRAM1_STOP_PAGE2_RETENTION (PWR_CR2_SRAM1PDS2) /*!< SRAM1 page 2 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
+#define LL_PWR_SRAM1_STOP_PAGE3_RETENTION (PWR_CR2_SRAM1PDS3) /*!< SRAM1 page 3 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
+#define LL_PWR_SRAM1_STOP_1_3_RETENTION (PWR_CR2_SRAM1PDS1 | PWR_CR2_SRAM1PDS2 | \
+ PWR_CR2_SRAM1PDS3) /*!< SRAM1 pages (1 to 3) retention in Stop mode (Stop 0, 1, 2, 3) */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_SRAM2_STOP_CONTENTS_RETENTION PWR SRAM2 Content Retention in Stop Mode
+ * @{
+ */
+#define LL_PWR_SRAM2_STOP_NO_RETENTION 0U /*!< SRAM2 no retention in Stop mode (Stop 0, 1, 2) */
+#define LL_PWR_SRAM2_STOP_PAGE1_RETENTION (PWR_CR2_SRAM2PDS1) /*!< SRAM2 page 1 (8 KB) retention in Stop mode (Stop 0, 1, 2) */
+#define LL_PWR_SRAM2_STOP_PAGE2_RETENTION (PWR_CR2_SRAM2PDS2) /*!< SRAM2 page 2 (54 KB) retention in Stop mode (Stop 0, 1, 2) */
+#define LL_PWR_SRAM2_STOP_FULL_RETENTION (PWR_CR2_SRAM2PDS1 | PWR_CR2_SRAM2PDS2) /*!< SRAM2 all pages retention in Stop mode (Stop 0, 1, 2) */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_SRAM3_STOP_CONTENTS_RETENTION PWR SRAM3 Content Retention in Stop Mode
+ * @{
+ */
+#define LL_PWR_SRAM3_STOP_NO_RETENTION 0U /*!< SRAM3 no retention in Stop mode (Stop 0, 1, 2, 3) */
+#define LL_PWR_SRAM3_STOP_PAGE1_RETENTION (PWR_CR2_SRAM3PDS1) /*!< SRAM3 page 1 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
+#define LL_PWR_SRAM3_STOP_PAGE2_RETENTION (PWR_CR2_SRAM3PDS2) /*!< SRAM3 page 2 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
+#define LL_PWR_SRAM3_STOP_PAGE3_RETENTION (PWR_CR2_SRAM3PDS3) /*!< SRAM3 page 3 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
+#define LL_PWR_SRAM3_STOP_PAGE4_RETENTION (PWR_CR2_SRAM3PDS4) /*!< SRAM3 page 4 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
+#define LL_PWR_SRAM3_STOP_PAGE5_RETENTION (PWR_CR2_SRAM3PDS5) /*!< SRAM3 page 5 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
+#define LL_PWR_SRAM3_STOP_PAGE6_RETENTION (PWR_CR2_SRAM3PDS6) /*!< SRAM3 page 6 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
+#define LL_PWR_SRAM3_STOP_PAGE7_RETENTION (PWR_CR2_SRAM3PDS7) /*!< SRAM3 page 7 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
+#define LL_PWR_SRAM3_STOP_PAGE8_RETENTION (PWR_CR2_SRAM3PDS8) /*!< SRAM3 page 8 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
+#define LL_PWR_SRAM3_STOP_1_8_RETENTION (PWR_CR2_SRAM3PDS1 | PWR_CR2_SRAM3PDS2 | PWR_CR2_SRAM3PDS3 | \
+ PWR_CR2_SRAM3PDS4 | PWR_CR2_SRAM3PDS5 | PWR_CR2_SRAM3PDS6 | \
+ PWR_CR2_SRAM3PDS7 | PWR_CR2_SRAM3PDS8) /*!< SRAM3 pages (1 to 8) retention in Stop modes (Stop 0, 1, 2, 3) */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_SRAM4_STOP_CONTENTS_RETENTION PWR SRAM4 Content Retention in Stop Mode
+ * @{
+ */
+#define LL_PWR_SRAM4_STOP_NO_RETENTION 0U /*!< SRAM4 no retention in Stop mode (Stop 0, 1, 2) */
+#define LL_PWR_SRAM4_STOP_FULL_RETENTION PWR_CR2_SRAM4PDS /*!< SRAM4 retention in Stop mode (Stop 0, 1, 2) */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_ICACHERAM_STOP_CONTENTS_RETENTION PWR ICACHE Content Retention in Stop Mode
+ * @{
+ */
+#define LL_PWR_ICACHERAM_STOP_NO_RETENTION 0U /*!< ICACHE SRAM no retention in Stop mode (Stop 0, 1, 2) */
+#define LL_PWR_ICACHERAM_STOP_FULL_RETENTION PWR_CR2_ICRAMPDS /*!< ICACHE SRAM retention in Stop mode (Stop 0, 1, 2) */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_DCACHE1RAM_STOP_CONTENTS_RETENTION PWR DCACHE1 Content Retention in Stop Mode
+ * @{
+ */
+#define LL_PWR_DCACHE1RAM_STOP_NO_RETENTION 0U /*!< DCACHE1 SRAM no retention in Stop mode (Stop 0, 1, 2) */
+#define LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION PWR_CR2_DC1RAMPDS /*!< DCACHE1 SRAM retention in Stop mode (Stop 0, 1, 2) */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_DMA2DRAM_STOP_CONTENTS_RETENTION PWR DMA2DRAM Content Retention in Stop Mode
+ * @{
+ */
+#define LL_PWR_DMA2DRAM_STOP_NO_RETENTION 0U /*!< DMA2D SRAM no retention in Stop mode (Stop 0, 1, 2) */
+#define LL_PWR_DMA2DRAM_STOP_FULL_RETENTION PWR_CR2_DMA2DRAMPDS /*!< DMA2D SRAM retention in Stop mode (Stop 0, 1, 2) */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_PERIPHRAM_STOP_CONTENTS_RETENTION PWR PERIPHRAM Content Retention in Stop Mode
+ * @{
+ */
+#define LL_PWR_PERIPHRAM_STOP_NO_RETENTION 0U /*!< FMAC, FDCAN and USB SRAM no retention in Stop mode (Stop 0, 1, 2) */
+#define LL_PWR_PERIPHRAM_STOP_FULL_RETENTION PWR_CR2_PRAMPDS /*!< FMAC, FDCAN and USB SRAM retention in Stop mode (Stop 0, 1, 2) */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_PKARAM_STOP_CONTENTS_RETENTION PWR PKARAM Content Retention in Stop Mode
+ * @{
+ */
+#define LL_PWR_PKARAM_STOP_NO_RETENTION 0U /*!< PKA32 SRAM no retention in Stop mode (Stop 0, 1, 2) */
+#define LL_PWR_PKARAM_STOP_FULL_RETENTION PWR_CR2_PKARAMPDS /*!< PKA32 SRAM retention in Stop mode (Stop 0, 1, 2) */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_SRAM1_RUN_CONTENTS_RETENTION PWR SRAM1 Content Retention in Run Mode
+ * @{
+ */
+#define LL_PWR_SRAM1_RUN_NO_RETENTION 0U /*!< SRAM1 no retention in Run mode */
+#define LL_PWR_SRAM1_RUN_FULL_RETENTION PWR_CR1_SRAM1PD /*!< SRAM1 retention in Run mode */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_SRAM2_RUN_CONTENTS_RETENTION PWR SRAM2 Content Retention in Run Mode
+ * @{
+ */
+#define LL_PWR_SRAM2_RUN_NO_RETENTION 0U /*!< SRAM2 no retention in Run mode */
+#define LL_PWR_SRAM2_RUN_FULL_RETENTION PWR_CR1_SRAM2PD /*!< SRAM2 retention in Run mode */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_SRAM3_RUN_CONTENTS_RETENTION PWR SRAM3 Content Retention in Run Mode
+ * @{
+ */
+#define LL_PWR_SRAM3_RUN_NO_RETENTION 0U /*!< SRAM3 no retention in Run mode */
+#define LL_PWR_SRAM3_RUN_FULL_RETENTION PWR_CR1_SRAM3PD /*!< SRAM3 retention in Run mode */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_SRAM4_RUN_CONTENTS_RETENTION PWR SRAM4 Content Retention in Run Mode
+ * @{
+ */
+#define LL_PWR_SRAM4_RUN_NO_RETENTION 0U /*!< SRAM4 no retention in Run mode */
+#define LL_PWR_SRAM4_RUN_FULL_RETENTION PWR_CR1_SRAM4PD /*!< SRAM4 retention in Run mode */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_SRD_MODE PWR Smart Run Domain Mode
+ * @{
+ */
+#define LL_PWR_SRD_STOP_MODE 0U /*!< SmartRun domain AHB3 and APB3 clocks disabled by default in Stop mode (Stop 0, 1, 2) */
+#define LL_PWR_SRD_RUN_MODE PWR_CR2_SRDRUN /*!< SmartRun domain AHB3 and APB3 clocks kept enabled in Stop mode (Stop 0, 1, 2) */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_REGULATOR_SUPPLY_SELECTION PWR Regulator Supply Selection
+ * @{
+ */
+#define LL_PWR_LDO_SUPPLY 0U /*!< LDO regulator supply */
+#define LL_PWR_SMPS_SUPPLY PWR_CR3_REGSEL /*!< SMPS regulator supply */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_VOLTAGE_SCALING_RANGE_SELECTION PWR Voltage scaling range selection
+ * @{
+ */
+#define LL_PWR_REGU_VOLTAGE_SCALE1 PWR_VOSR_VOS /*!< Voltage scaling range 1 */
+#define LL_PWR_REGU_VOLTAGE_SCALE2 PWR_VOSR_VOS_1 /*!< Voltage scaling range 2 */
+#define LL_PWR_REGU_VOLTAGE_SCALE3 PWR_VOSR_VOS_0 /*!< Voltage scaling range 3 */
+#define LL_PWR_REGU_VOLTAGE_SCALE4 0x00000000U /*!< Voltage scaling range 4 */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_PVD_LEVEL_SELECTION PWR Power Voltage Detector Level Selection
+ * @{
+ */
+#define LL_PWR_PVDLEVEL_0 0U /*!< Voltage threshold detected by PVD 2.0 V */
+#define LL_PWR_PVDLEVEL_1 PWR_SVMCR_PVDLS_0 /*!< Voltage threshold detected by PVD 2.2 V */
+#define LL_PWR_PVDLEVEL_2 PWR_SVMCR_PVDLS_1 /*!< Voltage threshold detected by PVD 2.4 V */
+#define LL_PWR_PVDLEVEL_3 (PWR_SVMCR_PVDLS_0 | PWR_SVMCR_PVDLS_1) /*!< Voltage threshold detected by PVD 2.5 V */
+#define LL_PWR_PVDLEVEL_4 PWR_SVMCR_PVDLS_2 /*!< Voltage threshold detected by PVD 2.6 V */
+#define LL_PWR_PVDLEVEL_5 (PWR_SVMCR_PVDLS_0 | PWR_SVMCR_PVDLS_2) /*!< Voltage threshold detected by PVD 2.8 V */
+#define LL_PWR_PVDLEVEL_6 (PWR_SVMCR_PVDLS_1 | PWR_SVMCR_PVDLS_2) /*!< Voltage threshold detected by PVD 2.9 V */
+#define LL_PWR_PVDLEVEL_7 PWR_SVMCR_PVDLS /*!< External input analog voltage on PVD_IN
+ pin, compared to internal VREFINT level */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_WAKEUP_PIN PWR Wake Up Pin
+ * @{
+ */
+#define LL_PWR_WAKEUP_PIN1 PWR_WUCR1_WUPEN1 /*!< Wakeup pin 1 enable */
+#define LL_PWR_WAKEUP_PIN2 PWR_WUCR1_WUPEN2 /*!< Wakeup pin 2 enable */
+#define LL_PWR_WAKEUP_PIN3 PWR_WUCR1_WUPEN3 /*!< Wakeup pin 3 enable */
+#define LL_PWR_WAKEUP_PIN4 PWR_WUCR1_WUPEN4 /*!< Wakeup pin 4 enable */
+#define LL_PWR_WAKEUP_PIN5 PWR_WUCR1_WUPEN5 /*!< Wakeup pin 5 enable */
+#define LL_PWR_WAKEUP_PIN6 PWR_WUCR1_WUPEN6 /*!< Wakeup pin 6 enable */
+#define LL_PWR_WAKEUP_PIN7 PWR_WUCR1_WUPEN7 /*!< Wakeup pin 7 enable */
+#define LL_PWR_WAKEUP_PIN8 PWR_WUCR1_WUPEN8 /*!< Wakeup pin 8 enable */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_WAKEUP_PIN_SELECTION PWR Wakeup Pin Selection
+ * @{
+ */
+#define LL_PWR_WAKEUP_PIN_SELECTION_0 0UL /*!< Wakeup pin selection 0 */
+#define LL_PWR_WAKEUP_PIN_SELECTION_1 PWR_WUCR3_WUSEL1_0 /*!< Wakeup pin selection 1 */
+#define LL_PWR_WAKEUP_PIN_SELECTION_2 PWR_WUCR3_WUSEL1_1 /*!< Wakeup pin selection 2 */
+#define LL_PWR_WAKEUP_PIN_SELECTION_3 PWR_WUCR3_WUSEL1 /*!< Wakeup pin selection 3 */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_CHARGING_RESISTOR_SELECTION PWR VBAT Charging Resistor Selection
+ * @{
+ */
+#define LL_PWR_BATT_CHARG_RESISTOR_5K 0U /*!< Charge the battery through a 5 kO resistor */
+#define LL_PWR_BATT_CHARG_RESISTOR_1_5K PWR_BDCR2_VBRS /*!< Charge the battery through a 1.5 kO resistor */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_GPIO_PORT_SELECTION PWR GPIO Port Selection
+ * @{
+ */
+#define LL_PWR_GPIO_PORTA (&(PWR->PUCRA)) /*!< GPIO port A */
+#define LL_PWR_GPIO_PORTB (&(PWR->PUCRB)) /*!< GPIO port B */
+#define LL_PWR_GPIO_PORTC (&(PWR->PUCRC)) /*!< GPIO port C */
+#define LL_PWR_GPIO_PORTD (&(PWR->PUCRD)) /*!< GPIO port D */
+#define LL_PWR_GPIO_PORTE (&(PWR->PUCRE)) /*!< GPIO port E */
+#define LL_PWR_GPIO_PORTF (&(PWR->PUCRF)) /*!< GPIO port F */
+#define LL_PWR_GPIO_PORTG (&(PWR->PUCRG)) /*!< GPIO port G */
+#define LL_PWR_GPIO_PORTH (&(PWR->PUCRH)) /*!< GPIO port H */
+#define LL_PWR_GPIO_PORTI (&(PWR->PUCRI)) /*!< GPIO port I */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_GPIO_PIN_MASK PWR GPIO Pin Mask
+ * @{
+ */
+#define LL_PWR_GPIO_PIN_0 (0x0001U) /*!< GPIO port I/O pin 0 */
+#define LL_PWR_GPIO_PIN_1 (0x0002U) /*!< GPIO port I/O pin 1 */
+#define LL_PWR_GPIO_PIN_2 (0x0004U) /*!< GPIO port I/O pin 2 */
+#define LL_PWR_GPIO_PIN_3 (0x0008U) /*!< GPIO port I/O pin 3 */
+#define LL_PWR_GPIO_PIN_4 (0x0010U) /*!< GPIO port I/O pin 4 */
+#define LL_PWR_GPIO_PIN_5 (0x0020U) /*!< GPIO port I/O pin 5 */
+#define LL_PWR_GPIO_PIN_6 (0x0040U) /*!< GPIO port I/O pin 6 */
+#define LL_PWR_GPIO_PIN_7 (0x0080U) /*!< GPIO port I/O pin 7 */
+#define LL_PWR_GPIO_PIN_8 (0x0100U) /*!< GPIO port I/O pin 8 */
+#define LL_PWR_GPIO_PIN_9 (0x0200U) /*!< GPIO port I/O pin 9 */
+#define LL_PWR_GPIO_PIN_10 (0x0400U) /*!< GPIO port I/O pin 10 */
+#define LL_PWR_GPIO_PIN_11 (0x0800U) /*!< GPIO port I/O pin 11 */
+#define LL_PWR_GPIO_PIN_12 (0x1000U) /*!< GPIO port I/O pin 12 */
+#define LL_PWR_GPIO_PIN_13 (0x2000U) /*!< GPIO port I/O pin 13 */
+#define LL_PWR_GPIO_PIN_14 (0x4000U) /*!< GPIO port I/O pin 14 */
+#define LL_PWR_GPIO_PIN_15 (0x8000U) /*!< GPIO port I/O pin 15 */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_ITEMS_SECURE_ATTRIBUTE PWR Items Secure Attribute
+ * @{
+ */
+#define LL_PWR_WAKEUP_PIN1_NSEC 0U /*!< Wake up pin 1 nsecure mode */
+#define LL_PWR_WAKEUP_PIN1_SEC PWR_SECCFGR_WUP1SEC /*!< Wake up pin 1 secure mode */
+#define LL_PWR_WAKEUP_PIN2_NSEC 0U /*!< Wake up pin 2 nsecure mode */
+#define LL_PWR_WAKEUP_PIN2_SEC PWR_SECCFGR_WUP2SEC /*!< Wake up pin 2 secure mode */
+#define LL_PWR_WAKEUP_PIN3_NSEC 0U /*!< Wake up pin 3 nsecure mode */
+#define LL_PWR_WAKEUP_PIN3_SEC PWR_SECCFGR_WUP3SEC /*!< Wake up pin 3 secure mode */
+#define LL_PWR_WAKEUP_PIN4_NSEC 0U /*!< Wake up pin 4 nsecure mode */
+#define LL_PWR_WAKEUP_PIN4_SEC PWR_SECCFGR_WUP4SEC /*!< Wake up pin 4 secure mode */
+#define LL_PWR_WAKEUP_PIN5_NSEC 0U /*!< Wake up pin 5 nsecure mode */
+#define LL_PWR_WAKEUP_PIN5_SEC PWR_SECCFGR_WUP5SEC /*!< Wake up pin 5 secure mode */
+#define LL_PWR_WAKEUP_PIN6_NSEC 0U /*!< Wake up pin 6 nsecure mode */
+#define LL_PWR_WAKEUP_PIN6_SEC PWR_SECCFGR_WUP6SEC /*!< Wake up pin 6 secure mode */
+#define LL_PWR_WAKEUP_PIN7_NSEC 0U /*!< Wake up pin 7 nsecure mode */
+#define LL_PWR_WAKEUP_PIN7_SEC PWR_SECCFGR_WUP7SEC /*!< Wake up pin 7 secure mode */
+#define LL_PWR_WAKEUP_PIN8_NSEC 0U /*!< Wake up pin 8 nsecure mode */
+#define LL_PWR_WAKEUP_PIN8_SEC PWR_SECCFGR_WUP8SEC /*!< Wake up pin 8 secure mode */
+
+#define LL_PWR_LPM_NSEC 0U /*!< Low-power modes nsecure mode */
+#define LL_PWR_LPM_SEC PWR_SECCFGR_WUP8SEC /*!< Low-power modes secure mode */
+#define LL_PWR_VDM_NSEC 0U /*!< Voltage detection and monitoring nsecure mode */
+#define LL_PWR_VDM_SEC PWR_SECCFGR_WUP8SEC /*!< Voltage detection and monitoring secure mode */
+#define LL_PWR_VB_NSEC 0U /*!< Backup domain nsecure mode */
+#define LL_PWR_VB_SEC PWR_SECCFGR_WUP8SEC /*!< Backup domain secure mode */
+#define LL_PWR_APC_NSEC 0U /*!< Pull-up/pull-down nsecure mode */
+#define LL_PWR_APC_SEC PWR_SECCFGR_WUP8SEC /*!< Pull-up/pull-down secure mode */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
+ * @{
+ */
+
+/** @defgroup PWR_LL_EM_WRITE_READ Common Write and Read Registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in PWR register.
+ * @param __REG__ Register to be written.
+ * @param __VALUE__ Value to be written in the register.
+ * @retval None.
+ */
+#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in PWR register.
+ * @param __REG__ Register to be read.
+ * @retval Register value.
+ */
+#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
+ * @{
+ */
+
+/** @defgroup PWR_LL_EF_CONFIGURATION PWR Configuration
+ * @{
+ */
+
+/**
+ * @brief Set system power mode.
+ * @rmtoll CR1 LPMS LL_PWR_SetPowerMode
+ * @param Mode : This parameter can be one of the following values:
+ * @arg @ref LL_PWR_STOP0_MODE
+ * @arg @ref LL_PWR_STOP1_MODE
+ * @arg @ref LL_PWR_STOP2_MODE
+ * @arg @ref LL_PWR_STOP3_MODE
+ * @arg @ref LL_PWR_STANDBY_MODE
+ * @arg @ref LL_PWR_SHUTDOWN_MODE
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t Mode)
+{
+ MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, Mode);
+}
+
+/**
+ * @brief Get system power mode.
+ * @rmtoll CR1 LPMS LL_PWR_GetPowerMode
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_STOP0_MODE
+ * @arg @ref LL_PWR_STOP1_MODE
+ * @arg @ref LL_PWR_STOP2_MODE
+ * @arg @ref LL_PWR_STOP3_MODE
+ * @arg @ref LL_PWR_STANDBY_MODE
+ * @arg @ref LL_PWR_SHUTDOWN_MODE
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
+{
+ return (READ_BIT(PWR->CR1, PWR_CR1_LPMS));
+}
+
+/**
+ * @brief Set the SRAM2 page(s) retention in Standby mode.
+ * @rmtoll CR1 RRSB1 LL_PWR_SetSRAM2SBRetention\n
+ * @rmtoll CR1 RRSB2 LL_PWR_SetSRAM2SBRetention
+ * @param SRAM2PageRetention : This parameter can be one of the following values:
+ * @arg @ref LL_PWR_SRAM2_SB_NO_RETENTION
+ * @arg @ref LL_PWR_SRAM2_SB_PAGE1_RETENTION
+ * @arg @ref LL_PWR_SRAM2_SB_PAGE2_RETENTION
+ * @arg @ref LL_PWR_SRAM2_SB_FULL_RETENTION
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetSRAM2SBRetention(uint32_t SRAM2PageRetention)
+{
+ MODIFY_REG(PWR->CR1, LL_PWR_SRAM2_SB_FULL_RETENTION, SRAM2PageRetention);
+}
+
+/**
+ * @brief Get the SRAM2 page(s) retention in Standby mode.
+ * @rmtoll CR1 RRSB1 LL_PWR_GetSRAM2SBRetention\n
+ * @rmtoll CR1 RRSB2 LL_PWR_GetSRAM2SBRetention
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_SRAM2_SB_NO_RETENTION
+ * @arg @ref LL_PWR_SRAM2_SB_PAGE1_RETENTION
+ * @arg @ref LL_PWR_SRAM2_SB_PAGE2_RETENTION
+ * @arg @ref LL_PWR_SRAM2_SB_FULL_RETENTION
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetSRAM2SBRetention(void)
+{
+ return (READ_BIT(PWR->CR1, (PWR_CR1_RRSB1 | PWR_CR1_RRSB2)));
+}
+
+/**
+ * @brief Enable BOR ultra low power mode.
+ * @rmtoll CR1 UPLMEN LL_PWR_EnableUltraLowPowerMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableUltraLowPowerMode(void)
+{
+ SET_BIT(PWR->CR1, PWR_CR1_ULPMEN);
+}
+
+/**
+ * @brief Disable BOR ultra low-power mode.
+ * @rmtoll CR1 UPLMEN LL_PWR_DisableUltraLowPowerMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableUltraLowPowerMode(void)
+{
+ CLEAR_BIT(PWR->CR1, PWR_CR1_ULPMEN);
+}
+
+/**
+ * @brief Check if BOR ultra low power mode is enabled.
+ * @rmtoll CR1 UPLMEN LL_PWR_IsEnabledUltraLowPowerMode
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledUltraLowPowerMode(void)
+{
+ return ((READ_BIT(PWR->CR1, PWR_CR1_ULPMEN) == (PWR_CR1_ULPMEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set the SRAM1 retention in Run mode.
+ * @rmtoll CR1 SRAM1PD LL_PWR_SetSRAM1RunRetention\n
+ * @param SRAM1Retention : This parameter can be one of the following values:
+ * @arg @ref LL_PWR_SRAM1_RUN_NO_RETENTION
+ * @arg @ref LL_PWR_SRAM1_RUN_FULL_RETENTION
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetSRAM1RunRetention(uint32_t SRAM1Retention)
+{
+ MODIFY_REG(PWR->CR1, LL_PWR_SRAM1_RUN_FULL_RETENTION, ((~SRAM1Retention) & LL_PWR_SRAM1_RUN_FULL_RETENTION));
+}
+
+/**
+ * @brief Get the SRAM1 retention in Run mode.
+ * @rmtoll CR1 SRAM1PD LL_PWR_GetSRAM1RunRetention\n
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_SRAM1_RUN_NO_RETENTION
+ * @arg @ref LL_PWR_SRAM1_RUN_FULL_RETENTION
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetSRAM1RunRetention(void)
+{
+ return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM1_RUN_FULL_RETENTION))) & LL_PWR_SRAM1_RUN_FULL_RETENTION);
+}
+
+/**
+ * @brief Set the SRAM2 retention in Run mode.
+ * @rmtoll CR1 SRAM2PD LL_PWR_SetSRAM2RunRetention\n
+ * @param SRAM2Retention : This parameter can be one of the following values:
+ * @arg @ref LL_PWR_SRAM2_RUN_NO_RETENTION
+ * @arg @ref LL_PWR_SRAM2_RUN_FULL_RETENTION
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetSRAM2RunRetention(uint32_t SRAM2Retention)
+{
+ MODIFY_REG(PWR->CR1, LL_PWR_SRAM2_RUN_FULL_RETENTION, ((~SRAM2Retention) & LL_PWR_SRAM2_RUN_FULL_RETENTION));
+}
+
+/**
+ * @brief Get the SRAM2 retention in Run mode.
+ * @rmtoll CR1 SRAM2PD LL_PWR_GetSRAM2RunRetention\n
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_SRAM2_RUN_NO_RETENTION
+ * @arg @ref LL_PWR_SRAM2_RUN_FULL_RETENTION
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetSRAM2RunRetention(void)
+{
+ return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM2_RUN_FULL_RETENTION))) & LL_PWR_SRAM2_RUN_FULL_RETENTION);
+}
+
+/**
+ * @brief Set the SRAM3 retention in Run mode.
+ * @rmtoll CR1 SRAM3PD LL_PWR_SetSRAM3RunRetention\n
+ * @param SRAM3Retention : This parameter can be one of the following values:
+ * @arg @ref LL_PWR_SRAM3_RUN_NO_RETENTION
+ * @arg @ref LL_PWR_SRAM3_RUN_FULL_RETENTION
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetSRAM3RunRetention(uint32_t SRAM3Retention)
+{
+ MODIFY_REG(PWR->CR1, LL_PWR_SRAM3_RUN_FULL_RETENTION, ((~SRAM3Retention) & LL_PWR_SRAM3_RUN_FULL_RETENTION));
+}
+
+/**
+ * @brief Get the SRAM3 retention in Run mode.
+ * @rmtoll CR1 SRAM3PD LL_PWR_GetSRAM3RunRetention\n
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_SRAM3_RUN_NO_RETENTION
+ * @arg @ref LL_PWR_SRAM3_RUN_FULL_RETENTION
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetSRAM3RunRetention(void)
+{
+ return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM3_RUN_FULL_RETENTION))) & LL_PWR_SRAM3_RUN_FULL_RETENTION);
+}
+
+/**
+ * @brief Set the SRAM4 retention in Run mode.
+ * @rmtoll CR1 SRAM4PD LL_PWR_SetSRAM4RunRetention\n
+ * @param SRAM4Retention : This parameter can be one of the following values:
+ * @arg @ref LL_PWR_SRAM4_RUN_NO_RETENTION
+ * @arg @ref LL_PWR_SRAM4_RUN_FULL_RETENTION
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetSRAM4RunRetention(uint32_t SRAM4Retention)
+{
+ MODIFY_REG(PWR->CR1, LL_PWR_SRAM4_RUN_FULL_RETENTION, ((~SRAM4Retention) & LL_PWR_SRAM4_RUN_FULL_RETENTION));
+}
+
+/**
+ * @brief Get the SRAM4 retention in Run mode.
+ * @rmtoll CR1 SRAM4PD LL_PWR_GetSRAM4RunRetention\n
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_SRAM4_RUN_NO_RETENTION
+ * @arg @ref LL_PWR_SRAM4_RUN_FULL_RETENTION
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetSRAM4RunRetention(void)
+{
+ return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM4_RUN_FULL_RETENTION))) & LL_PWR_SRAM4_RUN_FULL_RETENTION);
+}
+
+/**
+ * @brief Set the SRAM1 page(s) (From page 1 to page 3) retention in Stop mode.
+ * @rmtoll CR2 SRAM1PDS1 LL_PWR_SetSRAM1StopRetention_1_3\n
+ * @rmtoll CR2 SRAM1PDS2 LL_PWR_SetSRAM1StopRetention_1_3\n
+ * @rmtoll CR2 SRAM1PDS3 LL_PWR_SetSRAM1StopRetention_1_3
+ * @param SRAM1PageRetention : This parameter can be one of the following values:
+ * @arg @ref LL_PWR_SRAM1_STOP_NO_RETENTION
+ * @arg @ref LL_PWR_SRAM1_STOP_1_3_RETENTION
+ * Or can be a combination of the following values:
+ * @arg @ref LL_PWR_SRAM1_STOP_PAGE1_RETENTION
+ * @arg @ref LL_PWR_SRAM1_STOP_PAGE2_RETENTION
+ * @arg @ref LL_PWR_SRAM1_STOP_PAGE3_RETENTION
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetSRAM1StopRetention_1_3(uint32_t SRAM1PageRetention)
+{
+ MODIFY_REG(PWR->CR2, LL_PWR_SRAM1_STOP_1_3_RETENTION, ((~SRAM1PageRetention) & LL_PWR_SRAM1_STOP_1_3_RETENTION));
+}
+
+/**
+ * @brief Get the SRAM1 page(s) (From page 1 to page 3) retention in Stop mode.
+ * @rmtoll CR2 SRAM1PDS1 LL_PWR_GetSRAM1StopRetention_1_3\n
+ * @rmtoll CR2 SRAM1PDS2 LL_PWR_GetSRAM1StopRetention_1_3\n
+ * @rmtoll CR2 SRAM1PDS3 LL_PWR_GetSRAM1StopRetention_1_3
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_SRAM1_STOP_NO_RETENTION
+ * @arg @ref LL_PWR_SRAM1_STOP_1_3_RETENTION
+ * Or a combination of the following values:
+ * @arg @ref LL_PWR_SRAM1_STOP_PAGE1_RETENTION
+ * @arg @ref LL_PWR_SRAM1_STOP_PAGE2_RETENTION
+ * @arg @ref LL_PWR_SRAM1_STOP_PAGE3_RETENTION
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetSRAM1StopRetention_1_3(void)
+{
+ return ((~(READ_BIT(PWR->CR2, LL_PWR_SRAM1_STOP_1_3_RETENTION))) & LL_PWR_SRAM1_STOP_1_3_RETENTION);
+}
+
+/**
+ * @brief Set the SRAM2 page(s) retention in Stop mode.
+ * @rmtoll CR2 SRAM2PDS1 LL_PWR_SetSRAM2StopRetention\n
+ * @rmtoll CR2 SRAM2PDS2 LL_PWR_SetSRAM2StopRetention
+ * @param SRAM2PageRetention : This parameter can be one of the following values:
+ * @arg @ref LL_PWR_SRAM2_STOP_NO_RETENTION
+ * @arg @ref LL_PWR_SRAM2_STOP_PAGE1_RETENTION
+ * @arg @ref LL_PWR_SRAM2_STOP_PAGE2_RETENTION
+ * @arg @ref LL_PWR_SRAM2_STOP_FULL_RETENTION
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetSRAM2StopRetention(uint32_t SRAM2PageRetention)
+{
+ MODIFY_REG(PWR->CR2, LL_PWR_SRAM2_STOP_FULL_RETENTION, ((~SRAM2PageRetention) & LL_PWR_SRAM2_STOP_FULL_RETENTION));
+}
+
+/**
+ * @brief Get the SRAM2 page(s) retention in Stop mode.
+ * @rmtoll CR2 SRAM2PDS1 LL_PWR_GetSRAM2StopRetention\n
+ * @rmtoll CR2 SRAM2PDS2 LL_PWR_GetSRAM2StopRetention
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_SRAM2_STOP_NO_RETENTION
+ * @arg @ref LL_PWR_SRAM2_STOP_PAGE1_RETENTION
+ * @arg @ref LL_PWR_SRAM2_STOP_PAGE2_RETENTION
+ * @arg @ref LL_PWR_SRAM2_STOP_FULL_RETENTION
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetSRAM2StopRetention(void)
+{
+ return ((~(READ_BIT(PWR->CR2, LL_PWR_SRAM2_STOP_FULL_RETENTION))) & LL_PWR_SRAM2_STOP_FULL_RETENTION);
+}
+
+/**
+ * @brief Set the SRAM3 page(s) (From page 1 to page 8) retention in Stop mode.
+ * @rmtoll CR2 SRAM3PDS1 LL_PWR_SetSRAM3StopRetention_1_8\n
+ * @rmtoll CR2 SRAM3PDS2 LL_PWR_SetSRAM3StopRetention_1_8\n
+ * @rmtoll CR2 SRAM3PDS3 LL_PWR_SetSRAM3StopRetention_1_8\n
+ * @rmtoll CR2 SRAM3PDS4 LL_PWR_SetSRAM3StopRetention_1_8\n
+ * @rmtoll CR2 SRAM3PDS5 LL_PWR_SetSRAM3StopRetention_1_8\n
+ * @rmtoll CR2 SRAM3PDS6 LL_PWR_SetSRAM3StopRetention_1_8\n
+ * @rmtoll CR2 SRAM3PDS7 LL_PWR_SetSRAM3StopRetention_1_8\n
+ * @rmtoll CR2 SRAM3PDS8 LL_PWR_SetSRAM3StopRetention_1_8
+ * @param SRAM3PageRetention : This parameter can be one of the following values:
+ * @arg @ref LL_PWR_SRAM3_STOP_NO_RETENTION
+ * @arg @ref LL_PWR_SRAM3_STOP_1_8_RETENTION
+ * Or can be a combination of the following values:
+ * @arg @ref LL_PWR_SRAM3_STOP_PAGE1_RETENTION
+ * @arg @ref LL_PWR_SRAM3_STOP_PAGE2_RETENTION
+ * @arg @ref LL_PWR_SRAM3_STOP_PAGE3_RETENTION
+ * @arg @ref LL_PWR_SRAM3_STOP_PAGE4_RETENTION
+ * @arg @ref LL_PWR_SRAM3_STOP_PAGE5_RETENTION
+ * @arg @ref LL_PWR_SRAM3_STOP_PAGE6_RETENTION
+ * @arg @ref LL_PWR_SRAM3_STOP_PAGE7_RETENTION
+ * @arg @ref LL_PWR_SRAM3_STOP_PAGE8_RETENTION
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetSRAM3StopRetention_1_8(uint32_t SRAM3PageRetention)
+{
+ MODIFY_REG(PWR->CR2, LL_PWR_SRAM3_STOP_1_8_RETENTION, ((~SRAM3PageRetention) & LL_PWR_SRAM3_STOP_1_8_RETENTION));
+}
+
+/**
+ * @brief Get the SRAM3 page(s) (From page 1 to page 8) retention in Stop mode.
+ * @rmtoll CR2 SRAM3PDS1 LL_PWR_GetSRAM3StopRetention_1_8\n
+ * @rmtoll CR2 SRAM3PDS2 LL_PWR_GetSRAM3StopRetention_1_8\n
+ * @rmtoll CR2 SRAM3PDS3 LL_PWR_GetSRAM3StopRetention_1_8\n
+ * @rmtoll CR2 SRAM3PDS4 LL_PWR_GetSRAM3StopRetention_1_8\n
+ * @rmtoll CR2 SRAM3PDS5 LL_PWR_GetSRAM3StopRetention_1_8\n
+ * @rmtoll CR2 SRAM3PDS6 LL_PWR_GetSRAM3StopRetention_1_8\n
+ * @rmtoll CR2 SRAM3PDS7 LL_PWR_GetSRAM3StopRetention_1_8\n
+ * @rmtoll CR2 SRAM3PDS8 LL_PWR_GetSRAM3StopRetention_1_8
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_SRAM3_STOP_NO_RETENTION
+ * @arg @ref LL_PWR_SRAM3_STOP_1_8_RETENTION
+ * Or can be a combination of the following values:
+ * @arg @ref LL_PWR_SRAM3_STOP_PAGE1_RETENTION
+ * @arg @ref LL_PWR_SRAM3_STOP_PAGE2_RETENTION
+ * @arg @ref LL_PWR_SRAM3_STOP_PAGE3_RETENTION
+ * @arg @ref LL_PWR_SRAM3_STOP_PAGE4_RETENTION
+ * @arg @ref LL_PWR_SRAM3_STOP_PAGE5_RETENTION
+ * @arg @ref LL_PWR_SRAM3_STOP_PAGE6_RETENTION
+ * @arg @ref LL_PWR_SRAM3_STOP_PAGE7_RETENTION
+ * @arg @ref LL_PWR_SRAM3_STOP_PAGE8_RETENTION
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetSRAM3StopRetention_1_8(void)
+{
+ return ((~(READ_BIT(PWR->CR2, LL_PWR_SRAM3_STOP_1_8_RETENTION))) & LL_PWR_SRAM3_STOP_1_8_RETENTION);
+}
+
+/**
+ * @brief Set the SRAM4 page retention in Stop mode.
+ * @rmtoll CR2 SRAM4PDS LL_PWR_SetSRAM4StopRetention\n
+ * @param SRAM4PageRetention : This parameter can be one of the following values:
+ * @arg @ref LL_PWR_SRAM4_STOP_NO_RETENTION
+ * @arg @ref LL_PWR_SRAM4_STOP_FULL_RETENTION
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetSRAM4StopRetention(uint32_t SRAM4PageRetention)
+{
+ MODIFY_REG(PWR->CR2, LL_PWR_SRAM4_STOP_FULL_RETENTION, ((~SRAM4PageRetention) & LL_PWR_SRAM4_STOP_FULL_RETENTION));
+}
+
+/**
+ * @brief Get the SRAM4 page retention in Stop mode.
+ * @rmtoll CR2 SRAM4PDS LL_PWR_GetSRAM4StopRetention
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_SRAM4_STOP_NO_RETENTION
+ * @arg @ref LL_PWR_SRAM4_STOP_FULL_RETENTION
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetSRAM4StopRetention(void)
+{
+ return ((~(READ_BIT(PWR->CR2, LL_PWR_SRAM4_STOP_FULL_RETENTION))) & LL_PWR_SRAM4_STOP_FULL_RETENTION);
+}
+
+/**
+ * @brief Set the ICACHE SRAM page retention in Stop mode.
+ * @rmtoll CR2 ICRAMPDS LL_PWR_SetICacheRAMStopRetention\n
+ * @param ICachePageRetention : This parameter can be one of the following values:
+ * @arg @ref LL_PWR_ICACHERAM_STOP_NO_RETENTION
+ * @arg @ref LL_PWR_ICACHERAM_STOP_FULL_RETENTION
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetICacheRAMStopRetention(uint32_t ICachePageRetention)
+{
+ MODIFY_REG(PWR->CR2, LL_PWR_ICACHERAM_STOP_FULL_RETENTION,
+ ((~ICachePageRetention) & LL_PWR_ICACHERAM_STOP_FULL_RETENTION));
+}
+
+/**
+ * @brief Get the ICACHE SRAM page retention in Stop mode.
+ * @rmtoll CR2 ICRAMPDS LL_PWR_GetICacheRAMStopRetention
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_ICACHERAM_STOP_NO_RETENTION
+ * @arg @ref LL_PWR_ICACHERAM_STOP_FULL_RETENTION
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetICacheRAMStopRetention(void)
+{
+ return ((~(READ_BIT(PWR->CR2, LL_PWR_ICACHERAM_STOP_FULL_RETENTION))) & LL_PWR_ICACHERAM_STOP_FULL_RETENTION);
+}
+
+/**
+ * @brief Set the DCACHE1 SRAM page retention in Stop mode.
+ * @rmtoll CR2 DC1RAMPDS LL_PWR_SetDCache1RAMStopRetention\n
+ * @param DCache1PageRetention : This parameter can be one of the following values:
+ * @arg @ref LL_PWR_DCACHE1RAM_STOP_NO_RETENTION
+ * @arg @ref LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetDCache1RAMStopRetention(uint32_t DCache1PageRetention)
+{
+ MODIFY_REG(PWR->CR2, LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION,
+ ((~DCache1PageRetention) & LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION));
+}
+
+/**
+ * @brief Get the DCACHE1 SRAM page retention in Stop mode.
+ * @rmtoll CR2 DC1RAMPDS LL_PWR_GetDCache1RAMStopRetention
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_DCACHE1RAM_STOP_NO_RETENTION
+ * @arg @ref LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetDCache1RAMStopRetention(void)
+{
+ return ((~(READ_BIT(PWR->CR2, LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION))) & LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION);
+}
+
+/**
+ * @brief Set the DMA2D SRAM page retention in Stop mode.
+ * @rmtoll CR2 DMA2DRAMPDS LL_PWR_SetDMA2DRAMStopRetention\n
+ * @param DMA2DRAMPageRetention : This parameter can be one of the following values:
+ * @arg @ref LL_PWR_DMA2DRAM_STOP_NO_RETENTION
+ * @arg @ref LL_PWR_DMA2DRAM_STOP_FULL_RETENTION
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetDMA2DRAMStopRetention(uint32_t DMA2DRAMPageRetention)
+{
+ MODIFY_REG(PWR->CR2, LL_PWR_DMA2DRAM_STOP_FULL_RETENTION,
+ ((~DMA2DRAMPageRetention) & LL_PWR_DMA2DRAM_STOP_FULL_RETENTION));
+}
+
+/**
+ * @brief Get the DMA2D SRAM page retention in Stop mode.
+ * @rmtoll CR2 DMA2DRAMPDS LL_PWR_GetDMA2DRAMStopRetention
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_DMA2DRAM_STOP_NO_RETENTION
+ * @arg @ref LL_PWR_DMA2DRAM_STOP_FULL_RETENTION
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetDMA2DRAMStopRetention(void)
+{
+ return ((~(READ_BIT(PWR->CR2, LL_PWR_DMA2DRAM_STOP_FULL_RETENTION))) & LL_PWR_DMA2DRAM_STOP_FULL_RETENTION);
+}
+
+/**
+ * @brief Set the FMAC, FDCAN and USB SRAMs pages retention in Stop mode.
+ * @rmtoll CR2 PRAMPDS LL_PWR_SetPeriphRAMStopRetention\n
+ * @param PriphRAMPageRetention : This parameter can be one of the following values:
+ * @arg @ref LL_PWR_PERIPHRAM_STOP_NO_RETENTION
+ * @arg @ref LL_PWR_PERIPHRAM_STOP_FULL_RETENTION
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetPeriphRAMStopRetention(uint32_t PriphRAMPageRetention)
+{
+ MODIFY_REG(PWR->CR2, LL_PWR_PERIPHRAM_STOP_FULL_RETENTION,
+ ((~PriphRAMPageRetention) & LL_PWR_PERIPHRAM_STOP_FULL_RETENTION));
+}
+
+/**
+ * @brief Get the FMAC, FDCAN and USB SRAMs pages retention in Stop mode.
+ * @rmtoll CR2 PRAMPDS LL_PWR_GetPeriphRAMStopRetention
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_PERIPHRAM_STOP_NO_RETENTION
+ * @arg @ref LL_PWR_PERIPHRAM_STOP_FULL_RETENTION
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetPeriphRAMStopRetention(void)
+{
+ return ((~(READ_BIT(PWR->CR2, LL_PWR_PERIPHRAM_STOP_FULL_RETENTION))) & LL_PWR_PERIPHRAM_STOP_FULL_RETENTION);
+}
+
+/**
+ * @brief Set the PKA32 SRAM page retention in Stop mode.
+ * @rmtoll CR2 PKARAMPDS LL_PWR_SetPKARAMStopRetention
+ * @param PKARAMPageRetention : This parameter can be one of the following values:
+ * @arg @ref LL_PWR_PKARAM_STOP_NO_RETENTION
+ * @arg @ref LL_PWR_PKARAM_STOP_FULL_RETENTION
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetPKARAMStopRetention(uint32_t PKARAMPageRetention)
+{
+ MODIFY_REG(PWR->CR2, LL_PWR_PKARAM_STOP_FULL_RETENTION, ((~PKARAMPageRetention) & LL_PWR_PKARAM_STOP_FULL_RETENTION));
+}
+
+/**
+ * @brief Get the PKA32 SRAM page retention in Stop mode.
+ * @rmtoll CR2 PKARAMPDS LL_PWR_GetPKARAMStopRetention
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_PKARAM_STOP_NO_RETENTION
+ * @arg @ref LL_PWR_PKARAM_STOP_FULL_RETENTION
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetPKARAMStopRetention(void)
+{
+ return ((~(READ_BIT(PWR->CR2, LL_PWR_PKARAM_STOP_FULL_RETENTION))) & LL_PWR_PKARAM_STOP_FULL_RETENTION);
+}
+
+/**
+ * @brief Enable the flash memory fast wakeup from Stop mode (Stop 0, 1).
+ * @rmtoll CR2 FLASHFWU LL_PWR_EnableFlashFastWakeUp
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableFlashFastWakeUp(void)
+{
+ SET_BIT(PWR->CR2, PWR_CR2_FLASHFWU);
+}
+
+/**
+ * @brief Disable the flash memory fast wakeup from Stop mode (Stop 0, 1).
+ * @rmtoll CR2 FLASHFWU LL_PWR_DisableFlashFastWakeUp
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableFlashFastWakeUp(void)
+{
+ CLEAR_BIT(PWR->CR2, PWR_CR2_FLASHFWU);
+}
+
+/**
+ * @brief Check if the flash memory fast wakeup from Stop mode (Stop 0, 1)
+ * is enabled.
+ * @rmtoll CR2 FLASHFWU LL_PWR_IsEnabledFlashSRAM_StopModes
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashFastWakeUp(void)
+{
+ return ((READ_BIT(PWR->CR2, PWR_CR2_FLASHFWU) == (PWR_CR2_FLASHFWU)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable the SRAM4 memory fast wakeup from Stop mode (Stop 0, 1, 2).
+ * @rmtoll CR2 SRAM4FWU LL_PWR_EnableSRAM4FastWakeUp
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableSRAM4FastWakeUp(void)
+{
+ SET_BIT(PWR->CR2, PWR_CR2_SRAM4FWU);
+}
+
+/**
+ * @brief Disable the SRAM4 memory fast wakeup from Stop mode (Stop 0, 1, 2).
+ * @rmtoll CR2 SRAM4FWU LL_PWR_DisableSRAM4FastWakeUp
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableSRAM4FastWakeUp(void)
+{
+ CLEAR_BIT(PWR->CR2, PWR_CR2_SRAM4FWU);
+}
+
+/**
+ * @brief Check if the SRAM4 memory fast wakeup from Stop mode (Stop 0, 1, 2).
+ * is enabled.
+ * @rmtoll CR2 SRAM4FWU LL_PWR_IsEnabledSRAM4FastWakeUp
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM4FastWakeUp(void)
+{
+ return ((READ_BIT(PWR->CR2, PWR_CR2_SRAM4FWU) == (PWR_CR2_SRAM4FWU)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set the smart run domain mode.
+ * @rmtoll CR2 SRDRUN LL_PWR_SetSmartRunDomainMode
+ * @param SRDMode : This parameter can be one of the following values:
+ * @arg @ref LL_PWR_SRD_RUN_MODE
+ * @arg @ref LL_PWR_SRD_STOP_MODE
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetSmartRunDomainMode(uint32_t SRDMode)
+{
+ MODIFY_REG(PWR->CR2, PWR_CR2_SRDRUN, SRDMode);
+}
+
+/**
+ * @brief Get the smart run domain mode.
+ * @rmtoll CR2 SRDRUN LL_PWR_GetSmartRunDomainMode
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_SRD_RUN_MODE
+ * @arg @ref LL_PWR_SRD_STOP_MODE
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetSmartRunDomainMode(void)
+{
+ return (READ_BIT(PWR->CR2, PWR_CR2_SRDRUN));
+}
+
+/**
+ * @brief Set the VCore regulator supply.
+ * @rmtoll CR3 REGSEL LL_PWR_SetRegulatorSupply
+ * @param RegulatorSupply : This parameter can be one of the following values:
+ * @arg @ref LL_PWR_LDO_SUPPLY
+ * @arg @ref LL_PWR_SMPS_SUPPLY
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetRegulatorSupply(uint32_t RegulatorSupply)
+{
+ MODIFY_REG(PWR->CR3, PWR_CR3_REGSEL, RegulatorSupply);
+}
+
+/**
+ * @brief Get the VCore regulator supply.
+ * @rmtoll CR3 REGSEL LL_PWR_GetRegulatorSupply
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_LDO_SUPPLY
+ * @arg @ref LL_PWR_SMPS_SUPPLY
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetRegulatorSupply(void)
+{
+ return (READ_BIT(PWR->CR3, PWR_CR3_REGSEL));
+}
+
+/**
+ * @brief Enable the fast soft start for selected regulator.
+ * @rmtoll CR3 FSTEN LL_PWR_EnableFastSoftStart
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableFastSoftStart(void)
+{
+ SET_BIT(PWR->CR3, PWR_CR3_FSTEN);
+}
+
+/**
+ * @brief Disable the fast soft start for selected regulator.
+ * @rmtoll CR3 FSTEN LL_PWR_DisableFastSoftStart
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableFastSoftStart(void)
+{
+ CLEAR_BIT(PWR->CR3, PWR_CR3_FSTEN);
+}
+
+/**
+ * @brief Check if the fast soft start for selected regulator is enabled.
+ * @rmtoll CR3 FSTEN LL_PWR_IsEnabledFastSoftStart
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledFastSoftStart(void)
+{
+ return ((READ_BIT(PWR->CR3, PWR_CR3_FSTEN) == (PWR_CR3_FSTEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set the regulator supply output voltage.
+ * @rmtoll VOSR VOS LL_PWR_SetRegulVoltageScaling
+ * @param VoltageScaling This parameter can be one of the following values:
+ * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
+ * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
+ * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
+ * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE4
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
+{
+ MODIFY_REG(PWR->VOSR, PWR_VOSR_VOS, VoltageScaling);
+}
+
+/**
+ * @brief Get the regulator supply output voltage.
+ * @rmtoll VOSR VOS LL_PWR_GetRegulVoltageScaling
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
+ * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
+ * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
+ * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE4
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
+{
+ return (uint32_t)(READ_BIT(PWR->VOSR, PWR_VOSR_VOS));
+}
+
+/**
+ * @brief Enable the EPOD (Embedded Power Distribution) booster.
+ * @rmtoll VOSR BOOSTEN LL_PWR_EnableEPODBooster
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableEPODBooster(void)
+{
+ SET_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN);
+}
+
+/**
+ * @brief Disable the EPOD (Embedded Power Distribution) booster.
+ * @rmtoll VOSR BOOSTEN LL_PWR_DisableEPODBooster
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableEPODBooster(void)
+{
+ CLEAR_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN);
+}
+
+/**
+ * @brief Check if the EPOD (Embedded Power Distribution) booster is enabled.
+ * @rmtoll VOSR BOOSTEN LL_PWR_IsEnabledEPODBooster
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledEPODBooster(void)
+{
+ return ((READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN) == (PWR_VOSR_BOOSTEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set the Power voltage detector level.
+ * @rmtoll SVMCR PVDLS LL_PWR_SetPVDLevel
+ * @param PVDLevel This parameter can be one of the following values:
+ * @arg @ref LL_PWR_PVDLEVEL_0
+ * @arg @ref LL_PWR_PVDLEVEL_1
+ * @arg @ref LL_PWR_PVDLEVEL_2
+ * @arg @ref LL_PWR_PVDLEVEL_3
+ * @arg @ref LL_PWR_PVDLEVEL_4
+ * @arg @ref LL_PWR_PVDLEVEL_5
+ * @arg @ref LL_PWR_PVDLEVEL_6
+ * @arg @ref LL_PWR_PVDLEVEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
+{
+ MODIFY_REG(PWR->SVMCR, PWR_SVMCR_PVDLS, PVDLevel);
+}
+
+/**
+ * @brief Get the Power voltage detector level.
+ * @rmtoll SVMCR PVDLS LL_PWR_GetPVDLevel
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_PVDLEVEL_0
+ * @arg @ref LL_PWR_PVDLEVEL_1
+ * @arg @ref LL_PWR_PVDLEVEL_2
+ * @arg @ref LL_PWR_PVDLEVEL_3
+ * @arg @ref LL_PWR_PVDLEVEL_4
+ * @arg @ref LL_PWR_PVDLEVEL_5
+ * @arg @ref LL_PWR_PVDLEVEL_6
+ * @arg @ref LL_PWR_PVDLEVEL_7
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
+{
+ return (READ_BIT(PWR->SVMCR, PWR_SVMCR_PVDLS));
+}
+
+/**
+ * @brief Enable the power voltage detector.
+ * @rmtoll SVMCR PVDE LL_PWR_EnablePVD
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnablePVD(void)
+{
+ SET_BIT(PWR->SVMCR, PWR_SVMCR_PVDE);
+}
+
+/**
+ * @brief Disable the power voltage detector.
+ * @rmtoll SVMCR PVDE LL_PWR_DisablePVD
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisablePVD(void)
+{
+ CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_PVDE);
+}
+
+/**
+ * @brief Check if the power voltage detector is enabled.
+ * @rmtoll SVMCR PVDE LL_PWR_IsEnabledPVD
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
+{
+ return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_PVDE) == (PWR_SVMCR_PVDE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable the independent USB supply.
+ * @rmtoll SVMCR USV LL_PWR_EnableVDDUSB
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableVDDUSB(void)
+{
+ SET_BIT(PWR->SVMCR, PWR_SVMCR_USV);
+}
+
+/**
+ * @brief Disable the independent USB supply.
+ * @rmtoll SVMCR USV LL_PWR_DisableVDDUSB
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableVDDUSB(void)
+{
+ CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_USV);
+}
+
+/**
+ * @brief Check if the independent USB supply is enabled.
+ * @rmtoll SVMCR USV LL_PWR_IsEnabledVDDUSB
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledVDDUSB(void)
+{
+ return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_USV) == (PWR_SVMCR_USV)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable the independent I/Os supply.
+ * @rmtoll SVMCR IO2SV LL_PWR_EnableVDDIO2
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableVDDIO2(void)
+{
+ SET_BIT(PWR->SVMCR, PWR_SVMCR_IO2SV);
+}
+
+/**
+ * @brief Disable the independent I/Os supply.
+ * @rmtoll SVMCR IO2SV LL_PWR_DisableVDDIO2
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableVDDIO2(void)
+{
+ CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_IO2SV);
+}
+
+/**
+ * @brief Check if the independent I/Os supply is enabled.
+ * @rmtoll SVMCR IO2SV LL_PWR_IsEnabledVDDIO2
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledVDDIO2(void)
+{
+ return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_IO2SV) == (PWR_SVMCR_IO2SV)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable the independent analog supply.
+ * @rmtoll SVMCR ASV LL_PWR_EnableVDDA
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableVDDA(void)
+{
+ SET_BIT(PWR->SVMCR, PWR_SVMCR_ASV);
+}
+
+/**
+ * @brief Disable the independent analog supply.
+ * @rmtoll SVMCR ASV LL_PWR_DisableVDDA
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableVDDA(void)
+{
+ CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_ASV);
+}
+
+/**
+ * @brief Check if the independent analog supply is enabled.
+ * @rmtoll SVMCR ASV LL_PWR_IsEnabledVDDA
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledVDDA(void)
+{
+ return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_ASV) == (PWR_SVMCR_ASV)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable the independent USB supply monitor.
+ * @rmtoll SVMCR UVMEN LL_PWR_EnableVDDUSBMonitor
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableVDDUSBMonitor(void)
+{
+ SET_BIT(PWR->SVMCR, PWR_SVMCR_UVMEN);
+}
+
+/**
+ * @brief Disable the independent USB supply monitor.
+ * @rmtoll SVMCR UVMEN LL_PWR_DisableVDDUSBMonitor
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableVDDUSBMonitor(void)
+{
+ CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_UVMEN);
+}
+
+/**
+ * @brief Check if the independent USB supply monitor is enabled.
+ * @rmtoll SVMCR UVMEN LL_PWR_IsEnabledVDDUSBMonitor
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledVDDUSBMonitor(void)
+{
+ return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_UVMEN) == (PWR_SVMCR_UVMEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable the independent I/Os supply monitor.
+ * @rmtoll SVMCR IO2VMEN LL_PWR_EnableVDDIO2Monitor
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableVDDIO2Monitor(void)
+{
+ SET_BIT(PWR->SVMCR, PWR_SVMCR_IO2VMEN);
+}
+
+/**
+ * @brief Disable the independent I/Os supply monitor.
+ * @rmtoll SVMCR IO2VMEN LL_PWR_DisableVDDIO2Monitor
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableVDDIO2Monitor(void)
+{
+ CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_IO2VMEN);
+}
+
+/**
+ * @brief Check if the independent I/Os supply monitor is enabled.
+ * @rmtoll SVMCR IO2VMEN LL_PWR_IsEnabledVDDIO2Monitor
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledVDDIO2Monitor(void)
+{
+ return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_IO2VMEN) == (PWR_SVMCR_IO2VMEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable the independent analog supply monitor 1.
+ * @rmtoll SVMCR AVM1EN LL_PWR_EnableVDDAMonitor1
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableVDDAMonitor1(void)
+{
+ SET_BIT(PWR->SVMCR, PWR_SVMCR_AVM1EN);
+}
+
+/**
+ * @brief Disable the independent analog supply monitor 1.
+ * @rmtoll SVMCR AVM1EN LL_PWR_DisableVDDAMonitor1
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableVDDAMonitor1(void)
+{
+ CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_AVM1EN);
+}
+
+/**
+ * @brief Check if the independent analog supply monitor 1 is enabled.
+ * @rmtoll SVMCR AVM1EN LL_PWR_IsEnabledVDDAMonitor1
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledVDDAMonitor1(void)
+{
+ return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_AVM1EN) == (PWR_SVMCR_AVM1EN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable the independent analog supply monitor 2.
+ * @rmtoll SVMCR AVM2EN LL_PWR_EnableVDDAMonitor2
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableVDDAMonitor2(void)
+{
+ SET_BIT(PWR->SVMCR, PWR_SVMCR_AVM2EN);
+}
+
+/**
+ * @brief Disable the independent analog supply monitor 2.
+ * @rmtoll SVMCR AVM2EN LL_PWR_DisableVDDAMonitor2
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableVDDAMonitor2(void)
+{
+ CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_AVM2EN);
+}
+
+/**
+ * @brief Check if the independent analog supply monitor 2 is enabled.
+ * @rmtoll SVMCR AVM2EN LL_PWR_IsEnabledVDDAMonitor2
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledVDDAMonitor2(void)
+{
+ return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_AVM2EN) == (PWR_SVMCR_AVM2EN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable the wake up pin_x.
+ * @rmtoll WUCR1 WUPENx LL_PWR_EnableWakeUpPin
+ * @param WakeUpPin This parameter can be a combination of the following values:
+ * @arg @ref LL_PWR_WAKEUP_PIN1
+ * @arg @ref LL_PWR_WAKEUP_PIN2
+ * @arg @ref LL_PWR_WAKEUP_PIN3
+ * @arg @ref LL_PWR_WAKEUP_PIN4
+ * @arg @ref LL_PWR_WAKEUP_PIN5
+ * @arg @ref LL_PWR_WAKEUP_PIN6
+ * @arg @ref LL_PWR_WAKEUP_PIN7
+ * @arg @ref LL_PWR_WAKEUP_PIN8
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
+{
+ SET_BIT(PWR->WUCR1, WakeUpPin);
+}
+
+/**
+ * @brief Disable the wake up pin_x.
+ * @rmtoll WUCR1 WUPENx LL_PWR_DisableWakeUpPin
+ * @param WakeUpPin This parameter can be a combination of the following values:
+ * @arg @ref LL_PWR_WAKEUP_PIN1
+ * @arg @ref LL_PWR_WAKEUP_PIN2
+ * @arg @ref LL_PWR_WAKEUP_PIN3
+ * @arg @ref LL_PWR_WAKEUP_PIN4
+ * @arg @ref LL_PWR_WAKEUP_PIN5
+ * @arg @ref LL_PWR_WAKEUP_PIN6
+ * @arg @ref LL_PWR_WAKEUP_PIN7
+ * @arg @ref LL_PWR_WAKEUP_PIN8
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
+{
+ CLEAR_BIT(PWR->WUCR1, WakeUpPin);
+}
+
+/**
+ * @brief Check if the wake up pin_x is enabled.
+ * @rmtoll WUCR1 WUPENx LL_PWR_IsEnableWakeUpPin
+ * @param WakeUpPin This parameter can be one of the following values:
+ * @arg @ref LL_PWR_WAKEUP_PIN1
+ * @arg @ref LL_PWR_WAKEUP_PIN2
+ * @arg @ref LL_PWR_WAKEUP_PIN3
+ * @arg @ref LL_PWR_WAKEUP_PIN4
+ * @arg @ref LL_PWR_WAKEUP_PIN5
+ * @arg @ref LL_PWR_WAKEUP_PIN6
+ * @arg @ref LL_PWR_WAKEUP_PIN7
+ * @arg @ref LL_PWR_WAKEUP_PIN8
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
+{
+ return ((READ_BIT(PWR->WUCR1, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set the wake up pin polarity low for the event detection.
+ * @rmtoll WUCR2 WUPPx LL_PWR_SetWakeUpPinPolarityLow
+ * @param WakeUpPin This parameter can be a combination of the following values:
+ * @arg @ref LL_PWR_WAKEUP_PIN1
+ * @arg @ref LL_PWR_WAKEUP_PIN2
+ * @arg @ref LL_PWR_WAKEUP_PIN3
+ * @arg @ref LL_PWR_WAKEUP_PIN4
+ * @arg @ref LL_PWR_WAKEUP_PIN5
+ * @arg @ref LL_PWR_WAKEUP_PIN6
+ * @arg @ref LL_PWR_WAKEUP_PIN7
+ * @arg @ref LL_PWR_WAKEUP_PIN8
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
+{
+ SET_BIT(PWR->WUCR2, WakeUpPin);
+}
+
+/**
+ * @brief Set the wake up pin polarity high for the event detection.
+ * @rmtoll WUCR2 WUPPx LL_PWR_SetWakeUpPinPolarityHigh
+ * @param WakeUpPin This parameter can be a combination of the following values:
+ * @arg @ref LL_PWR_WAKEUP_PIN1
+ * @arg @ref LL_PWR_WAKEUP_PIN2
+ * @arg @ref LL_PWR_WAKEUP_PIN3
+ * @arg @ref LL_PWR_WAKEUP_PIN4
+ * @arg @ref LL_PWR_WAKEUP_PIN5
+ * @arg @ref LL_PWR_WAKEUP_PIN6
+ * @arg @ref LL_PWR_WAKEUP_PIN7
+ * @arg @ref LL_PWR_WAKEUP_PIN8
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
+{
+ CLEAR_BIT(PWR->WUCR2, WakeUpPin);
+}
+
+/**
+ * @brief Get the wake up pin polarity for the event detection.
+ * @rmtoll WUCR2 WUPPx LL_PWR_GetWakeUpPinPolarity
+ * @param WakeUpPin This parameter can be one of the following values:
+ * @arg @ref LL_PWR_WAKEUP_PIN1
+ * @arg @ref LL_PWR_WAKEUP_PIN2
+ * @arg @ref LL_PWR_WAKEUP_PIN3
+ * @arg @ref LL_PWR_WAKEUP_PIN4
+ * @arg @ref LL_PWR_WAKEUP_PIN5
+ * @arg @ref LL_PWR_WAKEUP_PIN6
+ * @arg @ref LL_PWR_WAKEUP_PIN7
+ * @arg @ref LL_PWR_WAKEUP_PIN8
+ * @retval State of bit (1 : polarity or 0 : polarity high).
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPolarity(uint32_t WakeUpPin)
+{
+ return ((READ_BIT(PWR->WUCR2, WakeUpPin) == WakeUpPin) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set the wakeup pin_x selection 0.
+ * @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal0Selection
+ * @param WakeUpPin This parameter can be one of the following values:
+ * @arg @ref LL_PWR_WAKEUP_PIN1
+ * @arg @ref LL_PWR_WAKEUP_PIN2
+ * @arg @ref LL_PWR_WAKEUP_PIN3
+ * @arg @ref LL_PWR_WAKEUP_PIN4
+ * @arg @ref LL_PWR_WAKEUP_PIN5
+ * @arg @ref LL_PWR_WAKEUP_PIN6
+ * @arg @ref LL_PWR_WAKEUP_PIN7
+ * @arg @ref LL_PWR_WAKEUP_PIN8
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetWakeUpPinSignal0Selection(uint32_t WakeUpPin)
+{
+ MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)),
+ (LL_PWR_WAKEUP_PIN_SELECTION_0 << (POSITION_VAL(WakeUpPin) * 2U)));
+}
+
+/**
+ * @brief Set the wakeup pin_x selection 1.
+ * @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal1Selection
+ * @param WakeUpPin This parameter can be one of the following values:
+ * @arg @ref LL_PWR_WAKEUP_PIN1
+ * @arg @ref LL_PWR_WAKEUP_PIN2
+ * @arg @ref LL_PWR_WAKEUP_PIN3
+ * @arg @ref LL_PWR_WAKEUP_PIN4
+ * @arg @ref LL_PWR_WAKEUP_PIN5
+ * @arg @ref LL_PWR_WAKEUP_PIN6
+ * @arg @ref LL_PWR_WAKEUP_PIN7
+ * @arg @ref LL_PWR_WAKEUP_PIN8
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetWakeUpPinSignal1Selection(uint32_t WakeUpPin)
+{
+ MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)),
+ (LL_PWR_WAKEUP_PIN_SELECTION_1 << (POSITION_VAL(WakeUpPin) * 2U)));
+}
+
+/**
+ * @brief Set the wakeup pin_x selection 2.
+ * @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal2Selection
+ * @param WakeUpPin This parameter can be one of the following values:
+ * @arg @ref LL_PWR_WAKEUP_PIN1
+ * @arg @ref LL_PWR_WAKEUP_PIN2
+ * @arg @ref LL_PWR_WAKEUP_PIN3
+ * @arg @ref LL_PWR_WAKEUP_PIN4
+ * @arg @ref LL_PWR_WAKEUP_PIN5
+ * @arg @ref LL_PWR_WAKEUP_PIN6
+ * @arg @ref LL_PWR_WAKEUP_PIN7
+ * @arg @ref LL_PWR_WAKEUP_PIN8
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetWakeUpPinSignal2Selection(uint32_t WakeUpPin)
+{
+ MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)),
+ (LL_PWR_WAKEUP_PIN_SELECTION_2 << (POSITION_VAL(WakeUpPin) * 2U)));
+}
+
+/**
+ * @brief Set the wakeup pin_x selection 3.
+ * @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal3Selection
+ * @param WakeUpPin This parameter can be one of the following values:
+ * @arg @ref LL_PWR_WAKEUP_PIN1
+ * @arg @ref LL_PWR_WAKEUP_PIN2
+ * @arg @ref LL_PWR_WAKEUP_PIN3
+ * @arg @ref LL_PWR_WAKEUP_PIN4
+ * @arg @ref LL_PWR_WAKEUP_PIN5
+ * @arg @ref LL_PWR_WAKEUP_PIN6
+ * @arg @ref LL_PWR_WAKEUP_PIN7
+ * @arg @ref LL_PWR_WAKEUP_PIN8
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetWakeUpPinSignal3Selection(uint32_t WakeUpPin)
+{
+ MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)),
+ (LL_PWR_WAKEUP_PIN_SELECTION_3 << (POSITION_VAL(WakeUpPin) * 2U)));
+}
+
+/**
+ * @brief Get the wakeup pin_x selection.
+ * @rmtoll WUCR3 WUSELx LL_PWR_GetWakeUpPinSignalSelection
+ * @param WakeUpPin This parameter can be one of the following values:
+ * @arg @ref LL_PWR_WAKEUP_PIN1
+ * @arg @ref LL_PWR_WAKEUP_PIN2
+ * @arg @ref LL_PWR_WAKEUP_PIN3
+ * @arg @ref LL_PWR_WAKEUP_PIN4
+ * @arg @ref LL_PWR_WAKEUP_PIN5
+ * @arg @ref LL_PWR_WAKEUP_PIN6
+ * @arg @ref LL_PWR_WAKEUP_PIN7
+ * @arg @ref LL_PWR_WAKEUP_PIN8
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinSignalSelection(uint32_t WakeUpPin)
+{
+ return (READ_BIT(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U))));
+}
+
+/**
+ * @brief Enable backup regulator.
+ * @rmtoll BDCR1 BREN LL_PWR_EnableBkUpRegulator
+ * @note When this bit is set, the backup RAM content is kept in Standby and
+ * VBAT modes. If BREN is reset, the backup RAM can still be used in
+ * Run, Sleep and Stop modes. However, its content is lost in Standby,
+ * Shutdown and VBAT modes. This bit can be written only when the
+ * regulator is LDO, which must be configured before switching to SMPS.
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)
+{
+ SET_BIT(PWR->BDCR1, PWR_BDCR1_BREN);
+}
+
+/**
+ * @brief Disable backup regulator
+ * @rmtoll BDCR1 BREN LL_PWR_DisableBkUpRegulator
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)
+{
+ CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_BREN);
+}
+
+/**
+ * @brief Check if the backup regulator is enabled
+ * @rmtoll BDCR1 BREN LL_PWR_IsEnabledBkUpRegulator
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)
+{
+ return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_BREN) == (PWR_BDCR1_BREN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable the backup domain voltage and temperature monitoring.
+ * @rmtoll BDCR1 MONEN LL_PWR_EnableMonitoring
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableMonitoring(void)
+{
+ SET_BIT(PWR->BDCR1, PWR_BDCR1_MONEN);
+}
+
+/**
+ * @brief Disable the backup domain voltage and temperature monitoring.
+ * @rmtoll BDCR1 MONEN LL_PWR_DisableMonitoring
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableMonitoring(void)
+{
+ CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_MONEN);
+}
+
+/**
+ * @brief Check if the backup domain voltage and temperature monitoring is
+ * enabled.
+ * @rmtoll BDCR1 MONEN LL_PWR_IsEnabledMonitoring
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledMonitoring(void)
+{
+ return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_MONEN) == (PWR_BDCR1_MONEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable battery charging.
+ * @rmtoll BDCR2 VBE LL_PWR_EnableBatteryCharging
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
+{
+ SET_BIT(PWR->BDCR2, PWR_BDCR2_VBE);
+}
+
+/**
+ * @brief Disable battery charging.
+ * @rmtoll BDCR2 VBE LL_PWR_DisableBatteryCharging
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
+{
+ CLEAR_BIT(PWR->BDCR2, PWR_BDCR2_VBE);
+}
+
+/**
+ * @brief Check if battery charging is enabled.
+ * @rmtoll BDCR2 VBE LL_PWR_IsEnabledBatteryCharging
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
+{
+ return ((READ_BIT(PWR->BDCR2, PWR_BDCR2_VBE) == (PWR_BDCR2_VBE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set the Battery charge resistor impedance
+ * @rmtoll BDCR2 VBRS LL_PWR_SetBattChargResistor
+ * @param Resistor This parameter can be one of the following values:
+ * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
+ * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_1_5K
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
+{
+ MODIFY_REG(PWR->BDCR2, PWR_BDCR2_VBRS, Resistor);
+}
+
+/**
+ * @brief Get the Battery charge resistor impedance
+ * @rmtoll BDCR2 VBRS LL_PWR_GetBattChargResistor
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
+ * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_1_5K
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
+{
+ return (uint32_t)(READ_BIT(PWR->BDCR2, PWR_BDCR2_VBRS));
+}
+
+/**
+ * @brief Enable access to the backup domain.
+ * @rmtoll DBPR DBP LL_PWR_EnableBkUpAccess
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
+{
+ SET_BIT(PWR->DBPR, PWR_DBPR_DBP);
+}
+
+/**
+ * @brief Disable access to the backup domain.
+ * @rmtoll DBPR DBP LL_PWR_DisableBkUpAccess
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
+{
+ CLEAR_BIT(PWR->DBPR, PWR_DBPR_DBP);
+}
+
+/**
+ * @brief Check if the access to backup domain is enabled.
+ * @rmtoll DBPR DBP LL_PWR_IsEnabledBkUpAccess
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
+{
+ return ((READ_BIT(PWR->DBPR, PWR_DBPR_DBP) == (PWR_DBPR_DBP)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable the USB Type-C and Power Delivery memorization in Standby mode.
+ * @note This function must be called just before entering Standby mode.
+ * @rmtoll UCPDR UCPD_STDBY LL_PWR_EnableUCPDStandbyMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableUCPDStandbyMode(void)
+{
+ SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STDBY);
+}
+
+/**
+ * @brief Disable the USB Type-C and Power Delivery memorization in Standby mode.
+ * @note This function must be called after exiting Standby mode and before any
+ * UCPD configuration update.
+ * @rmtoll UCPDR UCPD_STDBY LL_PWR_DisableUCPDStandbyMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableUCPDStandbyMode(void)
+{
+ CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STDBY);
+}
+
+/**
+ * @brief Check the USB Type-C and Power Delivery Standby mode memorization state.
+ * @rmtoll UCPDR UCPD_STDBY LL_PWR_IsEnabledUCPDStandbyMode
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDStandbyMode(void)
+{
+ return ((READ_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STDBY) == (PWR_UCPDR_UCPD_STDBY)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable the USB Type-C and power delivery dead battery pull-down behavior
+ * on UCPD CC1 and CC2 pins.
+ * @note After exiting reset, the USB Type-C dead battery behavior is enabled,
+ * which may have a pull-down effect on CC1 and CC2 pins. It is recommended
+ * to disable it in all cases, either to stop this pull-down or to hand over
+ * control to the UCPD (which should therefore be initialized before doing the disable).
+ * @rmtoll UCPDR UCPD_DBDIS LL_PWR_EnableUCPDDeadBattery
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableUCPDDeadBattery(void)
+{
+ CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS);
+}
+
+/**
+ * @brief Disable the USB Type-C and power delivery dead battery pull-down behavior
+ * on UCPD CC1 and CC2 pins.
+ * @note After exiting reset, the USB Type-C dead battery behavior is enabled,
+ * which may have a pull-down effect on CC1 and CC2 pins. It is recommended
+ * to disable it in all cases, either to stop this pull-down or to hand over
+ * control to the UCPD (which should therefore be initialized before doing the disable).
+ * @rmtoll UCPDR UCPD_DBDIS LL_PWR_DisableUCPDDeadBattery
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableUCPDDeadBattery(void)
+{
+ SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS);
+}
+
+/**
+ * @brief Check the USB Type-C and power delivery dead battery pull-down behavior
+ * on UCPD CC1 and CC2 pins.
+ * @note After exiting reset, the USB Type-C dead battery behavior is enabled,
+ * which may have a pull-down effect on CC1 and CC2 pins. It is recommended
+ * to disable it in all cases, either to stop this pull-down or to hand over
+ * control to the UCPD (which should therefore be initialized before doing the disable).
+ * @rmtoll UCPDR UCPD_DBDIS LL_PWR_IsEnabledUCPDDeadBattery
+ * @retval State of feature (1 : enabled; 0 : disabled).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDDeadBattery(void)
+{
+ return ((READ_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS) == (PWR_UCPDR_UCPD_DBDIS)) ? 0UL : 1UL);
+}
+
+/**
+ * @brief Enable the pull-up and pull-down configuration.
+ * @rmtoll APCR APC LL_PWR_EnablePUPDConfig
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnablePUPDConfig(void)
+{
+ SET_BIT(PWR->APCR, PWR_APCR_APC);
+}
+
+/**
+ * @brief Disable the pull-up and pull-down configuration.
+ * @rmtoll APCR APC LL_PWR_DisablePUPDConfig
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisablePUPDConfig(void)
+{
+ CLEAR_BIT(PWR->APCR, PWR_APCR_APC);
+}
+
+/**
+ * @brief Check if the pull-up and pull-down configuration is enabled.
+ * @rmtoll APCR APC LL_PWR_IsEnabledPUPDConfig
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDConfig(void)
+{
+ return ((READ_BIT(PWR->APCR, PWR_APCR_APC) == (PWR_APCR_APC)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable GPIO pull-up in Standby and Shutdown modes
+ * @rmtoll PUCRx PUx LL_PWR_EnableGPIOPullUp
+ * @param GPIOPort This parameter can be one of the following values:
+ * @arg @ref LL_PWR_GPIO_PORTA
+ * @arg @ref LL_PWR_GPIO_PORTB
+ * @arg @ref LL_PWR_GPIO_PORTC
+ * @arg @ref LL_PWR_GPIO_PORTD
+ * @arg @ref LL_PWR_GPIO_PORTE
+ * @arg @ref LL_PWR_GPIO_PORTF
+ * @arg @ref LL_PWR_GPIO_PORTG
+ * @arg @ref LL_PWR_GPIO_PORTH
+ * @arg @ref LL_PWR_GPIO_PORTI
+ * @param GPIOPin This parameter can be a combination of the following values:
+ * @arg @ref LL_PWR_GPIO_PIN_0
+ * @arg @ref LL_PWR_GPIO_PIN_1
+ * @arg @ref LL_PWR_GPIO_PIN_2
+ * @arg @ref LL_PWR_GPIO_PIN_3
+ * @arg @ref LL_PWR_GPIO_PIN_4
+ * @arg @ref LL_PWR_GPIO_PIN_5
+ * @arg @ref LL_PWR_GPIO_PIN_6
+ * @arg @ref LL_PWR_GPIO_PIN_7
+ * @arg @ref LL_PWR_GPIO_PIN_8
+ * @arg @ref LL_PWR_GPIO_PIN_9
+ * @arg @ref LL_PWR_GPIO_PIN_10
+ * @arg @ref LL_PWR_GPIO_PIN_11
+ * @arg @ref LL_PWR_GPIO_PIN_12
+ * @arg @ref LL_PWR_GPIO_PIN_13
+ * @arg @ref LL_PWR_GPIO_PIN_14
+ * @arg @ref LL_PWR_GPIO_PIN_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIOPort, uint32_t GPIOPin)
+{
+ SET_BIT(*((uint32_t *)GPIOPort), GPIOPin);
+}
+
+/**
+ * @brief Disable GPIO pull-up in Standby and Shutdown modes
+ * @rmtoll PUCRx PUx LL_PWR_DisableGPIOPullUp
+ * @param GPIOPort This parameter can be one of the following values:
+ * @arg @ref LL_PWR_GPIO_PORTA
+ * @arg @ref LL_PWR_GPIO_PORTB
+ * @arg @ref LL_PWR_GPIO_PORTC
+ * @arg @ref LL_PWR_GPIO_PORTD
+ * @arg @ref LL_PWR_GPIO_PORTE
+ * @arg @ref LL_PWR_GPIO_PORTF
+ * @arg @ref LL_PWR_GPIO_PORTG
+ * @arg @ref LL_PWR_GPIO_PORTH
+ * @arg @ref LL_PWR_GPIO_PORTI
+ * @param GPIOPin This parameter can be a combination of the following values:
+ * @arg @ref LL_PWR_GPIO_PIN_0
+ * @arg @ref LL_PWR_GPIO_PIN_1
+ * @arg @ref LL_PWR_GPIO_PIN_2
+ * @arg @ref LL_PWR_GPIO_PIN_3
+ * @arg @ref LL_PWR_GPIO_PIN_4
+ * @arg @ref LL_PWR_GPIO_PIN_5
+ * @arg @ref LL_PWR_GPIO_PIN_6
+ * @arg @ref LL_PWR_GPIO_PIN_7
+ * @arg @ref LL_PWR_GPIO_PIN_8
+ * @arg @ref LL_PWR_GPIO_PIN_9
+ * @arg @ref LL_PWR_GPIO_PIN_10
+ * @arg @ref LL_PWR_GPIO_PIN_11
+ * @arg @ref LL_PWR_GPIO_PIN_12
+ * @arg @ref LL_PWR_GPIO_PIN_13
+ * @arg @ref LL_PWR_GPIO_PIN_14
+ * @arg @ref LL_PWR_GPIO_PIN_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIOPort, uint32_t GPIOPin)
+{
+ CLEAR_BIT(*((uint32_t *)GPIOPort), GPIOPin);
+}
+
+/**
+ * @brief Check if GPIO pull-up in Standby and Shutdown modes is enabled
+ * @rmtoll PUCRx PUx LL_PWR_IsEnabledGPIOPullUp
+ * @param GPIOPort This parameter can be one of the following values:
+ * @arg @ref LL_PWR_GPIO_PORTA
+ * @arg @ref LL_PWR_GPIO_PORTB
+ * @arg @ref LL_PWR_GPIO_PORTC
+ * @arg @ref LL_PWR_GPIO_PORTD
+ * @arg @ref LL_PWR_GPIO_PORTE
+ * @arg @ref LL_PWR_GPIO_PORTF
+ * @arg @ref LL_PWR_GPIO_PORTG
+ * @arg @ref LL_PWR_GPIO_PORTH
+ * @arg @ref LL_PWR_GPIO_PORTI
+ * @param GPIOPin This parameter can be one of the following values:
+ * @arg @ref LL_PWR_GPIO_PIN_0
+ * @arg @ref LL_PWR_GPIO_PIN_1
+ * @arg @ref LL_PWR_GPIO_PIN_2
+ * @arg @ref LL_PWR_GPIO_PIN_3
+ * @arg @ref LL_PWR_GPIO_PIN_4
+ * @arg @ref LL_PWR_GPIO_PIN_5
+ * @arg @ref LL_PWR_GPIO_PIN_6
+ * @arg @ref LL_PWR_GPIO_PIN_7
+ * @arg @ref LL_PWR_GPIO_PIN_8
+ * @arg @ref LL_PWR_GPIO_PIN_9
+ * @arg @ref LL_PWR_GPIO_PIN_10
+ * @arg @ref LL_PWR_GPIO_PIN_11
+ * @arg @ref LL_PWR_GPIO_PIN_12
+ * @arg @ref LL_PWR_GPIO_PIN_13
+ * @arg @ref LL_PWR_GPIO_PIN_14
+ * @arg @ref LL_PWR_GPIO_PIN_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIOPort, uint32_t GPIOPin)
+{
+ return ((READ_BIT(*((uint32_t *)(GPIOPort)), GPIOPin) == (GPIOPin)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable GPIO pull-down in Standby and Shutdown modes.
+ * @rmtoll PDCRx PDx LL_PWR_EnableGPIOPullDown
+ * @param GPIOPort This parameter can be one of the following values:
+ * @arg @ref LL_PWR_GPIO_PORTA
+ * @arg @ref LL_PWR_GPIO_PORTB
+ * @arg @ref LL_PWR_GPIO_PORTC
+ * @arg @ref LL_PWR_GPIO_PORTD
+ * @arg @ref LL_PWR_GPIO_PORTE
+ * @arg @ref LL_PWR_GPIO_PORTF
+ * @arg @ref LL_PWR_GPIO_PORTG
+ * @arg @ref LL_PWR_GPIO_PORTH
+ * @arg @ref LL_PWR_GPIO_PORTI
+ * @param GPIOPin This parameter can be a combination of the following values:
+ * @arg @ref LL_PWR_GPIO_PIN_0
+ * @arg @ref LL_PWR_GPIO_PIN_1
+ * @arg @ref LL_PWR_GPIO_PIN_2
+ * @arg @ref LL_PWR_GPIO_PIN_3
+ * @arg @ref LL_PWR_GPIO_PIN_4
+ * @arg @ref LL_PWR_GPIO_PIN_5
+ * @arg @ref LL_PWR_GPIO_PIN_6
+ * @arg @ref LL_PWR_GPIO_PIN_7
+ * @arg @ref LL_PWR_GPIO_PIN_8
+ * @arg @ref LL_PWR_GPIO_PIN_9
+ * @arg @ref LL_PWR_GPIO_PIN_10
+ * @arg @ref LL_PWR_GPIO_PIN_11
+ * @arg @ref LL_PWR_GPIO_PIN_12
+ * @arg @ref LL_PWR_GPIO_PIN_13
+ * @arg @ref LL_PWR_GPIO_PIN_14
+ * @arg @ref LL_PWR_GPIO_PIN_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIOPort, uint32_t GPIOPin)
+{
+ SET_BIT(*((__IO uint32_t *)(GPIOPort + 4U)), GPIOPin);
+}
+
+/**
+ * @brief Disable GPIO pull-down in Standby and Shutdown modes.
+ * @rmtoll PDCRx PDx LL_PWR_DisableGPIOPullDown
+ * @param GPIOPort This parameter can be one of the following values:
+ * @arg @ref LL_PWR_GPIO_PORTA
+ * @arg @ref LL_PWR_GPIO_PORTB
+ * @arg @ref LL_PWR_GPIO_PORTC
+ * @arg @ref LL_PWR_GPIO_PORTD
+ * @arg @ref LL_PWR_GPIO_PORTE
+ * @arg @ref LL_PWR_GPIO_PORTF
+ * @arg @ref LL_PWR_GPIO_PORTG
+ * @arg @ref LL_PWR_GPIO_PORTH
+ * @arg @ref LL_PWR_GPIO_PORTI
+ * @param GPIOPin This parameter can be a combination of the following values:
+ * @arg @ref LL_PWR_GPIO_PIN_0
+ * @arg @ref LL_PWR_GPIO_PIN_1
+ * @arg @ref LL_PWR_GPIO_PIN_2
+ * @arg @ref LL_PWR_GPIO_PIN_3
+ * @arg @ref LL_PWR_GPIO_PIN_4
+ * @arg @ref LL_PWR_GPIO_PIN_5
+ * @arg @ref LL_PWR_GPIO_PIN_6
+ * @arg @ref LL_PWR_GPIO_PIN_7
+ * @arg @ref LL_PWR_GPIO_PIN_8
+ * @arg @ref LL_PWR_GPIO_PIN_9
+ * @arg @ref LL_PWR_GPIO_PIN_10
+ * @arg @ref LL_PWR_GPIO_PIN_11
+ * @arg @ref LL_PWR_GPIO_PIN_12
+ * @arg @ref LL_PWR_GPIO_PIN_13
+ * @arg @ref LL_PWR_GPIO_PIN_14
+ * @arg @ref LL_PWR_GPIO_PIN_15
+ * @retval None.
+ */
+__STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIOPort, uint32_t GPIOPin)
+{
+ CLEAR_BIT(*((__IO uint32_t *)(GPIOPort + 4U)), GPIOPin);
+}
+
+/**
+ * @brief Check if GPIO pull-down in Standby and Shutdown modes is enabled
+ * @rmtoll PDCRx PDx LL_PWR_IsEnabledGPIOPullUp
+ * @param GPIOPort This parameter can be one of the following values:
+ * @arg @ref LL_PWR_GPIO_PORTA
+ * @arg @ref LL_PWR_GPIO_PORTB
+ * @arg @ref LL_PWR_GPIO_PORTC
+ * @arg @ref LL_PWR_GPIO_PORTD
+ * @arg @ref LL_PWR_GPIO_PORTE
+ * @arg @ref LL_PWR_GPIO_PORTF
+ * @arg @ref LL_PWR_GPIO_PORTG
+ * @arg @ref LL_PWR_GPIO_PORTH
+ * @arg @ref LL_PWR_GPIO_PORTI
+ * @param GPIOPin This parameter can be one of the following values:
+ * @arg @ref LL_PWR_GPIO_PIN_0
+ * @arg @ref LL_PWR_GPIO_PIN_1
+ * @arg @ref LL_PWR_GPIO_PIN_2
+ * @arg @ref LL_PWR_GPIO_PIN_3
+ * @arg @ref LL_PWR_GPIO_PIN_4
+ * @arg @ref LL_PWR_GPIO_PIN_5
+ * @arg @ref LL_PWR_GPIO_PIN_6
+ * @arg @ref LL_PWR_GPIO_PIN_7
+ * @arg @ref LL_PWR_GPIO_PIN_8
+ * @arg @ref LL_PWR_GPIO_PIN_9
+ * @arg @ref LL_PWR_GPIO_PIN_10
+ * @arg @ref LL_PWR_GPIO_PIN_11
+ * @arg @ref LL_PWR_GPIO_PIN_12
+ * @arg @ref LL_PWR_GPIO_PIN_13
+ * @arg @ref LL_PWR_GPIO_PIN_14
+ * @arg @ref LL_PWR_GPIO_PIN_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIOPort, uint32_t GPIOPin)
+{
+ return ((READ_BIT(*((__IO uint32_t *)(GPIOPort + 4U)), GPIOPin) == (GPIOPin)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get currently voltage scaling applied to VCORE.
+ * @rmtoll SVMSR ACTVOS[1:0] LL_PWR_GetRegulCurrentVOS
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
+ * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
+ * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
+ * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE4
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetRegulCurrentVOS(void)
+{
+ return (READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOS));
+}
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EF_FLAG_MANAGEMENT PWR FLAG Management
+ * @{
+ */
+
+/**
+ * @brief Indicate whether the EPOD (Embedded Power Distribution) booster is
+ * ready OR not.
+ * @rmtoll VOSR BOOSTRDY LL_PWR_IsActiveFlag_BOOST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BOOST(void)
+{
+ return ((READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTRDY) == (PWR_VOSR_BOOSTRDY)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate whether the regulator voltage output is above voltage
+ * scaling range or not.
+ * @rmtoll VOSR VOSRDY LL_PWR_IsActiveFlag_VOS
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
+{
+ return ((READ_BIT(PWR->VOSR, PWR_VOSR_VOSRDY) == (PWR_VOSR_VOSRDY)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate whether the system was in standby mode or not.
+ * @rmtoll SR SBF LL_PWR_IsActiveFlag_SB
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
+{
+ return ((READ_BIT(PWR->SR, PWR_SR_SBF) == (PWR_SR_SBF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate whether the system was in stop mode or not.
+ * @rmtoll SR STOPF LL_PWR_IsActiveFlag_STOP
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_STOP(void)
+{
+ return ((READ_BIT(PWR->SR, PWR_SR_STOPF) == (PWR_SR_STOPF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate whether the regulator supply is LDO or SMPS.
+ * @rmtoll SVMSR REGS LL_PWR_IsActiveFlag_REGULATOR
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGULATOR(void)
+{
+ return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_REGS) == (PWR_SVMSR_REGS)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate whether the VDD voltage is below the threshold or not.
+ * @rmtoll SVMSR PVDO LL_PWR_IsActiveFlag_PVDO
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
+{
+ return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_PVDO) == (PWR_SVMSR_PVDO)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate whether the regulator voltage output is equal to current
+ * used voltage scaling range or not.
+ * @rmtoll SVMSR ACTVOSRDY LL_PWR_IsActiveFlag_ACTVOS
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ACTVOS(void)
+{
+ return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY) == (PWR_SVMSR_ACTVOSRDY)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate whether the VDDUSB is below the threshold of monitor or not.
+ * @rmtoll SVMSR VDDUSBRDY LL_PWR_IsActiveFlag_VDDUSB
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDUSB(void)
+{
+ return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDUSBRDY) == (PWR_SVMSR_VDDUSBRDY)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate whether the VDDIO2 is below the threshold of monitor or not.
+ * @rmtoll SVMSR VDDIO2RDY LL_PWR_IsActiveFlag_VDDIO2
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDIO2(void)
+{
+ return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDIO2RDY) == (PWR_SVMSR_VDDIO2RDY)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate whether the VDDA1 is below the threshold of monitor 1 or
+ * not.
+ * @rmtoll SVMSR VDDA1RDY LL_PWR_IsActiveFlag_VDDA1
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDA1(void)
+{
+ return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDA1RDY) == (PWR_SVMSR_VDDA1RDY)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate whether the VDDA2 is below the threshold of monitor 2 or
+ * not.
+ * @rmtoll SVMSR VDDA2RDY LL_PWR_IsActiveFlag_VDDA2
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDA2(void)
+{
+ return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDA2RDY) == (PWR_SVMSR_VDDA2RDY)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate whether the VBAT level is below high threshold or not.
+ * @rmtoll BDSR VBATH LL_PWR_IsActiveFlag_VBATH
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATH(void)
+{
+ return ((READ_BIT(PWR->BDSR, PWR_BDSR_VBATH) == (PWR_BDSR_VBATH)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate whether the CPU temperature level is above low threshold or
+ * not.
+ * @rmtoll BDSR TEMPL LL_PWR_IsActiveFlag_TEMPL
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPL(void)
+{
+ return ((READ_BIT(PWR->BDSR, PWR_BDSR_TEMPL) == (PWR_BDSR_TEMPL)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate whether the CPU temperature level is below high threshold
+ * or not.
+ * @rmtoll BDSR TEMPH LL_PWR_IsActiveFlag_TEMPH
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPH(void)
+{
+ return ((READ_BIT(PWR->BDSR, PWR_BDSR_TEMPH) == (PWR_BDSR_TEMPH)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate whether a wakeup event is detected on wake up pin 1.
+ * @rmtoll WUSR WUF1 LL_PWR_IsActiveFlag_WU1
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
+{
+ return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) == (PWR_WUSR_WUF1)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate whether a wakeup event is detected on wake up pin 2.
+ * @rmtoll WUSR WUF2 LL_PWR_IsActiveFlag_WU2
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
+{
+ return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) == (PWR_WUSR_WUF2)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate whether a wakeup event is detected on wake up pin 3.
+ * @rmtoll WUSR WUF3 LL_PWR_IsActiveFlag_WU3
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
+{
+ return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) == (PWR_WUSR_WUF3)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate whether a wakeup event is detected on wake up pin 4.
+ * @rmtoll WUSR WUF4 LL_PWR_IsActiveFlag_WU4
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
+{
+ return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) == (PWR_WUSR_WUF4)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate whether a wakeup event is detected on wake up pin 5.
+ * @rmtoll WUSR WUF5 LL_PWR_IsActiveFlag_WU5
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
+{
+ return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) == (PWR_WUSR_WUF5)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate whether a wakeup event is detected on wake up pin 6.
+ * @rmtoll WUSR WUF6 LL_PWR_IsActiveFlag_WU6
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void)
+{
+ return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) == (PWR_WUSR_WUF6)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate whether a wakeup event is detected on wake up pin 7.
+ * @rmtoll WUSR WUF7 LL_PWR_IsActiveFlag_WU7
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU7(void)
+{
+ return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) == (PWR_WUSR_WUF7)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate whether a wakeup event is detected on wake up pin 8.
+ * @rmtoll WUSR WUF8 LL_PWR_IsActiveFlag_WU8
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU8(void)
+{
+ return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == (PWR_WUSR_WUF8)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear stop flag.
+ * @rmtoll SR CSSF LL_PWR_ClearFlag_STOP
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_ClearFlag_STOP(void)
+{
+ WRITE_REG(PWR->SR, PWR_SR_CSSF);
+}
+
+/**
+ * @brief Clear standby flag.
+ * @rmtoll SR CSSF LL_PWR_ClearFlag_SB
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
+{
+ WRITE_REG(PWR->SR, PWR_SR_CSSF);
+}
+
+/**
+ * @brief Clear wake up flag 1.
+ * @rmtoll WUSCR CWUF1 LL_PWR_ClearFlag_WU1
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
+{
+ WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF1);
+}
+
+/**
+ * @brief Clear wake up flag 2.
+ * @rmtoll WUSCR CWUF2 LL_PWR_ClearFlag_WU2
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
+{
+ WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF2);
+}
+
+/**
+ * @brief Clear wake up flag 3.
+ * @rmtoll WUSCR CWUF3 LL_PWR_ClearFlag_WU3
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
+{
+ WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF3);
+}
+
+/**
+ * @brief Clear wake up flag 4.
+ * @rmtoll WUSCR CWUF4 LL_PWR_ClearFlag_WU4
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
+{
+ WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF4);
+}
+
+/**
+ * @brief Clear wake up flag 5.
+ * @rmtoll WUSCR CWUF5 LL_PWR_ClearFlag_WU5
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
+{
+ WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF5);
+}
+
+/**
+ * @brief Clear wake up flag 6.
+ * @rmtoll WUSCR CWUF6 LL_PWR_ClearFlag_WU6
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU6(void)
+{
+ WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF6);
+}
+
+/**
+ * @brief Clear wake up flag 7.
+ * @rmtoll WUSCR CWUF7 LL_PWR_ClearFlag_WU7
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU7(void)
+{
+ WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF7);
+}
+
+/**
+ * @brief Clear wake up flag 8.
+ * @rmtoll WUSCR CWUF8 LL_PWR_ClearFlag_WU8
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU8(void)
+{
+ WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF8);
+}
+
+/**
+ * @brief Clear all wake up flags.
+ * @rmtoll WUSCR CWUF LL_PWR_ClearFlag_WU
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
+{
+ WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF);
+}
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EF_ATTRIBUTE_MANAGEMENT PWR Attribute Management
+ * @{
+ */
+
+/**
+ * @brief Enable privileged mode for nsecure items.
+ * @rmtoll PRIVCFGR NSPRIV LL_PWR_EnableNSecurePrivilege
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableNSecurePrivilege(void)
+{
+ SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV);
+}
+
+/**
+ * @brief Disable privileged mode for nsecure items.
+ * @rmtoll PRIVCFGR NSPRIV LL_PWR_DisableNSecurePrivilege
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableNSecurePrivilege(void)
+{
+ CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV);
+}
+
+/**
+ * @brief Check if privileged mode for nsecure items is enabled.
+ * @rmtoll PRIVCFGR NSPRIV LL_PWR_IsEnabledNSecurePrivilege
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledNSecurePrivilege(void)
+{
+ return ((READ_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV) == PWR_PRIVCFGR_NSPRIV) ? 1UL : 0UL);
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ * @brief Enable privileged mode for secure items.
+ * @rmtoll PRIVCFGR SPRIV LL_PWR_EnableSecurePrivilege
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableSecurePrivilege(void)
+{
+ SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV);
+}
+
+/**
+ * @brief Disable privileged mode for secure items.
+ * @rmtoll PRIVCFGR SPRIV LL_PWR_DisableSecurePrivilege
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableSecurePrivilege(void)
+{
+ CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/**
+ * @brief Check if privileged mode for secure items is enabled.
+ * @rmtoll PRIVCFGR SPRIV LL_PWR_IsEnabledSecurePrivilege
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledSecurePrivilege(void)
+{
+ return ((READ_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV) == PWR_PRIVCFGR_SPRIV) ? 1UL : 0UL);
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ * @brief Configure secure attribute mode.
+ * @note This API can be executed only by CPU in secure mode.
+ * @rmtoll SECCFGR WUP1SEC LL_PWR_ConfigSecure\n
+ * SECCFGR WUP2SEC LL_PWR_ConfigSecure\n
+ * SECCFGR WUP3SEC LL_PWR_ConfigSecure\n
+ * SECCFGR WUP4SEC LL_PWR_ConfigSecure\n
+ * SECCFGR WUP5SEC LL_PWR_ConfigSecure\n
+ * SECCFGR WUP6SEC LL_PWR_ConfigSecure\n
+ * SECCFGR WUP7SEC LL_PWR_ConfigSecure\n
+ * SECCFGR WUP8SEC LL_PWR_ConfigSecure\n
+ * SECCFGR LPMSEC LL_PWR_ConfigSecure\n
+ * SECCFGR VDMSEC LL_PWR_ConfigSecure\n
+ * SECCFGR VBSEC LL_PWR_ConfigSecure\n
+ * SECCFGR APCSEC LL_PWR_ConfigSecure
+ * @param SecureConfig This parameter can be the full combination
+ * of the following values:
+ * @arg @ref LL_PWR_WAKEUP_PIN1_NSEC or LL_PWR_WAKEUP_PIN1_SEC
+ * @arg @ref LL_PWR_WAKEUP_PIN2_NSEC or LL_PWR_WAKEUP_PIN2_SEC
+ * @arg @ref LL_PWR_WAKEUP_PIN3_NSEC or LL_PWR_WAKEUP_PIN3_SEC
+ * @arg @ref LL_PWR_WAKEUP_PIN4_NSEC or LL_PWR_WAKEUP_PIN4_SEC
+ * @arg @ref LL_PWR_WAKEUP_PIN5_NSEC or LL_PWR_WAKEUP_PIN5_SEC
+ * @arg @ref LL_PWR_WAKEUP_PIN6_NSEC or LL_PWR_WAKEUP_PIN6_SEC
+ * @arg @ref LL_PWR_WAKEUP_PIN7_NSEC or LL_PWR_WAKEUP_PIN7_SEC
+ * @arg @ref LL_PWR_WAKEUP_PIN8_NSEC or LL_PWR_WAKEUP_PIN8_SEC
+ * @arg @ref LL_PWR_LPM_NSEC or LL_PWR_LPM_SEC
+ * @arg @ref LL_PWR_VDM_NSEC or LL_PWR_VDM_SEC
+ * @arg @ref LL_PWR_VB_NSEC or LL_PWR_VB_SEC
+ * @arg @ref LL_PWR_APC_NSEC or LL_PWR_APC_SEC
+ * @retval None.
+ */
+__STATIC_INLINE void LL_PWR_ConfigSecure(uint32_t SecureConfig)
+{
+ WRITE_REG(PWR->SECCFGR, SecureConfig);
+}
+
+/**
+ * @brief Get secure attribute configuration.
+ * @note This API can be executed only by CPU in secure mode.
+ * @rmtoll SECCFGR WUP1SEC LL_PWR_GetConfigSecure\n
+ * SECCFGR WUP2SEC LL_PWR_GetConfigSecure\n
+ * SECCFGR WUP3SEC LL_PWR_GetConfigSecure\n
+ * SECCFGR WUP4SEC LL_PWR_GetConfigSecure\n
+ * SECCFGR WUP5SEC LL_PWR_GetConfigSecure\n
+ * SECCFGR WUP6SEC LL_PWR_GetConfigSecure\n
+ * SECCFGR WUP7SEC LL_PWR_GetConfigSecure\n
+ * SECCFGR WUP8SEC LL_PWR_GetConfigSecure\n
+ * SECCFGR LPMSEC LL_PWR_GetConfigSecure\n
+ * SECCFGR VDMSEC LL_PWR_GetConfigSecure\n
+ * SECCFGR VBSEC LL_PWR_GetConfigSecure\n
+ * SECCFGR APCSEC LL_PWR_GetConfigSecure
+ * @retval Returned value is the combination of the following values:
+ * @arg @ref LL_PWR_WAKEUP_PIN1_NSEC or LL_PWR_WAKEUP_PIN1_SEC
+ * @arg @ref LL_PWR_WAKEUP_PIN2_NSEC or LL_PWR_WAKEUP_PIN2_SEC
+ * @arg @ref LL_PWR_WAKEUP_PIN3_NSEC or LL_PWR_WAKEUP_PIN3_SEC
+ * @arg @ref LL_PWR_WAKEUP_PIN4_NSEC or LL_PWR_WAKEUP_PIN4_SEC
+ * @arg @ref LL_PWR_WAKEUP_PIN5_NSEC or LL_PWR_WAKEUP_PIN5_SEC
+ * @arg @ref LL_PWR_WAKEUP_PIN6_NSEC or LL_PWR_WAKEUP_PIN6_SEC
+ * @arg @ref LL_PWR_WAKEUP_PIN7_NSEC or LL_PWR_WAKEUP_PIN7_SEC
+ * @arg @ref LL_PWR_WAKEUP_PIN8_NSEC or LL_PWR_WAKEUP_PIN8_SEC
+ * @arg @ref LL_PWR_LPM_NSEC or LL_PWR_LPM_SEC
+ * @arg @ref LL_PWR_VDM_NSEC or LL_PWR_VDM_SEC
+ * @arg @ref LL_PWR_VB_NSEC or LL_PWR_VB_SEC
+ * @arg @ref LL_PWR_APC_NSEC or LL_PWR_APC_SEC
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetConfigSecure(void)
+{
+ return (READ_REG(PWR->SECCFGR));
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/**
+ * @}
+ */
+
+#if defined (USE_FULL_LL_DRIVER)
+/** @defgroup PWR_LL_EF_Init De-initialization function
+ * @{
+ */
+ErrorStatus LL_PWR_DeInit(void);
+/**
+ * @}
+ */
+#endif /* defined (USE_FULL_LL_DRIVER) */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (PWR) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* STM32U5xx_LL_PWR_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rcc.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rcc.h
new file mode 100644
index 00000000..40b6e23a
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rcc.h
@@ -0,0 +1,5399 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_rcc.h
+ * @author MCD Application Team
+ * @brief Header file of RCC LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_LL_RCC_H
+#define STM32U5xx_LL_RCC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx.h"
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined(RCC)
+
+/** @defgroup RCC_LL RCC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RCC_LL_Private_Constants RCC Private Constants
+ * @{
+ */
+/* Defines used to perform offsets*/
+/* Offset used to access to RCC_CCIPR1 and RCC_CCIPR2 registers */
+#define RCC_OFFSET_CCIPR1 0U
+#define RCC_OFFSET_CCIPR3 0x08U
+
+/* Defines used for security configuration extension */
+#define RCC_SECURE_MASK 0x1FFFU
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_Exported_Types RCC Exported Types
+ * @{
+ */
+
+/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
+ * @{
+ */
+
+/**
+ * @brief RCC Clocks Frequency Structure
+ */
+typedef struct
+{
+ uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
+ uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
+ uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
+ uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
+ uint32_t PCLK3_Frequency; /*!< PCLK3 clock frequency */
+} LL_RCC_ClocksTypeDef;
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
+ * @{
+ */
+
+/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
+ * @brief Defines used to adapt values of different oscillators
+ * @note These values could be modified in the user environment according to
+ * HW set-up.
+ * @{
+ */
+#if !defined (HSE_VALUE)
+#define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSI_VALUE)
+#define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */
+#endif /* HSI_VALUE */
+
+#if !defined (LSE_VALUE)
+#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined (LSI_VALUE)
+#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
+#endif /* LSI_VALUE */
+
+#if !defined (HSI48_VALUE)
+#define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */
+#endif /* HSI48_VALUE */
+
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+#define EXTERNAL_SAI1_CLOCK_VALUE 48000U /*!< Value of the SAI1_EXTCLK external oscillator in Hz */
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+#if !defined (EXTERNAL_SAI2_CLOCK_VALUE)
+#define EXTERNAL_SAI2_CLOCK_VALUE 48000U /*!< Value of the SAI2_EXTCLK external oscillator in Hz */
+#endif /* EXTERNAL_SAI2_CLOCK_VALUE */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_LSIPRE LSI prescaler
+ * @{
+ */
+#define LL_RCC_LSI_DIV_1 0x00000000U /*!< LSI divided by 1 */
+#define LL_RCC_LSI_DIV_128 RCC_BDCR_LSIPREDIV /*!< LSI divided by 128 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
+ * @{
+ */
+#define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */
+#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */
+#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium high driving capability */
+#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_MSI_OSCILLATOR MSI clock Trimming
+ * @{
+ */
+#define LL_RCC_MSI_OSCILLATOR_0 0x00000000U /*!< MSI clock trimming for ranges 0 to 3 */
+#define LL_RCC_MSI_OSCILLATOR_1 0x00000005U /*!< MSI clock trimming for ranges 4 to 7 */
+#define LL_RCC_MSI_OSCILLATOR_2 0x0000000AU /*!< MSI clock trimming for ranges 8 to 11 */
+#define LL_RCC_MSI_OSCILLATOR_3 0x0000000FU /*!< MSI clock trimming for ranges 12 to 15 */
+/**
+ * @}
+ */
+
+
+/** @defgroup RCC_LL_EC_MSISRANGE MSIS Clock Range
+ * @{
+ */
+#define LL_RCC_MSISRANGE_0 0x00000000U /*!< MSIS = 48 MHz */
+#define LL_RCC_MSISRANGE_1 RCC_ICSCR1_MSISRANGE_0 /*!< MSIS = 24 MHz */
+#define LL_RCC_MSISRANGE_2 RCC_ICSCR1_MSISRANGE_1 /*!< MSIS = 16 MHz */
+#define LL_RCC_MSISRANGE_3 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1) /*!< MSIS = 12 MHz */
+#define LL_RCC_MSISRANGE_4 RCC_ICSCR1_MSISRANGE_2 /*!< MSIS = 4 MHz */
+#define LL_RCC_MSISRANGE_5 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_2) /*!< MSIS = 2 MHz */
+#define LL_RCC_MSISRANGE_6 (RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_2) /*!< MSIS = 1.5 MHz */
+#define LL_RCC_MSISRANGE_7 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_2) /*!< MSIS = 1 MHz */
+#define LL_RCC_MSISRANGE_8 RCC_ICSCR1_MSISRANGE_3 /*!< MSIS = 3.072 MHz */
+#define LL_RCC_MSISRANGE_9 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_3) /*!< MSIS = 1.536 MHz */
+#define LL_RCC_MSISRANGE_10 (RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_3) /*!< MSIS = 1.024 MHz */
+#define LL_RCC_MSISRANGE_11 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_3) /*!< MSIS = 768 KHz */
+#define LL_RCC_MSISRANGE_12 (RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_3) /*!< MSIS = 400 KHz */
+#define LL_RCC_MSISRANGE_13 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_3) /*!< MSIS = 200 KHz */
+#define LL_RCC_MSISRANGE_14 (RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_3) /*!< MSIS = 150 KHz */
+#define LL_RCC_MSISRANGE_15 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1| RCC_ICSCR1_MSISRANGE_2 | \
+ RCC_ICSCR1_MSISRANGE_3) /*!< MSIS = 100 KHz */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_MSIKRANGE MSIK Clock Range
+ * @{
+ */
+#define LL_RCC_MSIKRANGE_0 0x00000000U /*!< MSIK = 48 MHz */
+#define LL_RCC_MSIKRANGE_1 RCC_ICSCR1_MSIKRANGE_0 /*!< MSIK = 24 MHz */
+#define LL_RCC_MSIKRANGE_2 RCC_ICSCR1_MSIKRANGE_1 /*!< MSIK = 16 MHz */
+#define LL_RCC_MSIKRANGE_3 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1) /*!< MSIK = 12 MHz */
+#define LL_RCC_MSIKRANGE_4 RCC_ICSCR1_MSIKRANGE_2 /*!< MSIK = 4 MHz */
+#define LL_RCC_MSIKRANGE_5 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIK = 2 MHz */
+#define LL_RCC_MSIKRANGE_6 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIK = 1.5 MHz */
+#define LL_RCC_MSIKRANGE_7 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIK = 1 MHz */
+#define LL_RCC_MSIKRANGE_8 RCC_ICSCR1_MSIKRANGE_3 /*!< MSIK = 3.072 MHz */
+#define LL_RCC_MSIKRANGE_9 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 1.536 MHz */
+#define LL_RCC_MSIKRANGE_10 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 1.024 MHz */
+#define LL_RCC_MSIKRANGE_11 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 768 KHz */
+#define LL_RCC_MSIKRANGE_12 (RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 400 KHz */
+#define LL_RCC_MSIKRANGE_13 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 200 KHz */
+#define LL_RCC_MSIKRANGE_14 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 150 KHz */
+#define LL_RCC_MSIKRANGE_15 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2 | \
+ RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 100 KHz */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_MSISSRANGE MSIS range after Standby mode
+ * @{
+ */
+#define LL_RCC_MSISSRANGE_4 RCC_CSR_MSISSRANGE_2 /*!< MSIS = 4 MHz */
+#define LL_RCC_MSISSRANGE_5 (RCC_CSR_MSISSRANGE_2 | RCC_CSR_MSISSRANGE_0) /*!< MSIS = 2 MHz */
+#define LL_RCC_MSISSRANGE_6 (RCC_CSR_MSISSRANGE_2 | RCC_CSR_MSISSRANGE_1) /*!< MSIS = 1.5 MHz */
+#define LL_RCC_MSISSRANGE_7 (RCC_CSR_MSISSRANGE_0 | RCC_CSR_MSISSRANGE_2 | RCC_CSR_MSISSRANGE_1) /*!< MSIS = 1 MHz */
+#define LL_RCC_MSISSRANGE_8 RCC_CSR_MSISSRANGE_3 /*!< MSIS = 3.072 MHz*/
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_MSIKSRANGE MSIK range after Standby mode
+ * @{
+ */
+#define LL_RCC_MSIKSRANGE_4 RCC_CSR_MSISSRANGE_2 /*!< MSIK = 4 MHz */
+#define LL_RCC_MSIKSRANGE_5 (RCC_CSR_MSIKSRANGE_2 | RCC_CSR_MSIKSRANGE_0) /*!< MSIK = 2 MHz */
+#define LL_RCC_MSIKSRANGE_6 (RCC_CSR_MSIKSRANGE_2 | RCC_CSR_MSIKSRANGE_1) /*!< MSIK = 1.5 MHz */
+#define LL_RCC_MSIKSRANGE_7 (RCC_CSR_MSIKSRANGE_2 | RCC_CSR_MSIKSRANGE_1 | RCC_CSR_MSIKSRANGE_0) /*!< MSIK = 1 MHz */
+#define LL_RCC_MSIKSRANGE_8 RCC_CSR_MSIKSRANGE_3 /*!< MSIK = 3.072 MHz*/
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_MSIPLLMODE MSIS/MSIK Pll Mode
+ * @{
+ */
+#define LL_RCC_PLLMODE_MSIS RCC_CR_MSIPLLSEL /*!< MSIS selection for Pll Mode */
+#define LL_RCC_PLLMODE_MSIK 0U /*!< MSIK selection for Pll Mode */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_MSIBIASMODE MSI BIAS Mode
+ * @{
+ */
+#define LL_RCC_MSIBIASMODE_SAMPLING RCC_ICSCR1_MSIBIAS /*!< Sampling mode selection for MSI*/
+#define LL_RCC_MSIBIASMODE_CONTINUOUS 0U /*!< Continuous mode selection for MSI*/
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_HSEEXT EXTERNAL HSE Mode
+ * @{
+ */
+#define LL_RCC_HSE_ANALOG_MODE 0U /*!< HSE clock used as ANALOG clock source */
+#define LL_RCC_HSE_DIGITAL_MODE RCC_CR_HSEEXT /*!< HSE clock used as DIGITAL clock source */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection
+ * @{
+ */
+#define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock */
+#define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock */
+/**
+ * @}
+ */
+
+
+/** @defgroup RCC_LL_EC_PLL1MBOOST_DIV EPOD prescaler
+ * @{
+ */
+#define LL_RCC_PLL1MBOOST_DIV_1 0x00000000U /*!< PLL1CLK not divided */
+#define LL_RCC_PLL1MBOOST_DIV_2 RCC_PLL1CFGR_PLL1MBOOST_0 /*!< PLL1CLK divided by 2 */
+#define LL_RCC_PLL1MBOOST_DIV_4 RCC_PLL1CFGR_PLL1MBOOST_1 /*!< PLL1CLK divided by 4 */
+#define LL_RCC_PLL1MBOOST_DIV_6 (RCC_PLL1CFGR_PLL1MBOOST_1 | RCC_PLL1CFGR_PLL1MBOOST_0) /*!< PLL1CLK divided by 6 */
+#define LL_RCC_PLL1MBOOST_DIV_8 RCC_PLL1CFGR_PLL1MBOOST_2 /*!< PLL1CLK divided by 8 */
+#define LL_RCC_PLL1MBOOST_DIV_10 (RCC_PLL1CFGR_PLL1MBOOST_2 | RCC_PLL1CFGR_PLL1MBOOST_0) /*!< PLL1CLK divided by 10 */
+#define LL_RCC_PLL1MBOOST_DIV_12 (RCC_PLL1CFGR_PLL1MBOOST_2 | RCC_PLL1CFGR_PLL1MBOOST_1) /*!< PLL1CLK divided by 12 */
+#define LL_RCC_PLL1MBOOST_DIV_14 (RCC_PLL1CFGR_PLL1MBOOST_2 | RCC_PLL1CFGR_PLL1MBOOST_1 | \
+ RCC_PLL1CFGR_PLL1MBOOST_0) /*!< PLL1CLK divided by 14 */
+#define LL_RCC_PLL1MBOOST_DIV_16 RCC_PLL1CFGR_PLL1MBOOST_3 /*!< PLL1CLK divided by 16 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
+ * @{
+ */
+#define LL_RCC_SYS_CLKSOURCE_MSIS 0x00000000U /*!< MSIS selection as system clock */
+#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR1_SW_0 /*!< HSI oscillator selection as system clock */
+#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR1_SW_1 /*!< HSE selection as system clock */
+#define LL_RCC_SYS_CLKSOURCE_PLL1 (RCC_CFGR1_SW_1 | RCC_CFGR1_SW_0) /*!< PLL selection as system clock */
+/**
+ * @}
+ */
+
+
+/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
+ * @{
+ */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_MSIS 0x00000000U /*!< MSIS used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR1_SWS_0 /*!< HSI used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR1_SWS_1 /*!< HSE used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL1 (RCC_CFGR1_SWS_1 | RCC_CFGR1_SWS_0) /*!< PLL1 used as system clock */
+/**
+ * @}
+ */
+
+
+/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
+ * @{
+ */
+#define LL_RCC_SYSCLK_DIV_1 0x00000000U /*!< SYSCLK not divided */
+#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR2_HPRE_3 /*!< SYSCLK divided by 2 */
+#define LL_RCC_SYSCLK_DIV_4 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_0) /*!< SYSCLK divided by 4 */
+#define LL_RCC_SYSCLK_DIV_8 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_1) /*!< SYSCLK divided by 8 */
+#define LL_RCC_SYSCLK_DIV_16 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_0) /*!< SYSCLK divided by 16 */
+#define LL_RCC_SYSCLK_DIV_64 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_2) /*!< SYSCLK divided by 64 */
+#define LL_RCC_SYSCLK_DIV_128 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_0) /*!< SYSCLK divided by 128 */
+#define LL_RCC_SYSCLK_DIV_256 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_1) /*!< SYSCLK divided by 256 */
+#define LL_RCC_SYSCLK_DIV_512 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_1 | \
+ RCC_CFGR2_HPRE_0)/*!< SYSCLK divided by 512 */
+/**
+ * @}
+ */
+
+
+/** @defgroup RCC_LL_EC_SYSTICK_CLKSOURCE SYSTICK clock source selection
+ * @{
+ */
+#define LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8 0x00000000U /*!< HCLKDIV8 clock used as SYSTICK clock source */
+#define LL_RCC_SYSTICK_CLKSOURCE_LSI RCC_CCIPR1_SYSTICKSEL_0 /*!< LSI clock used as SYSTICK clock source */
+#define LL_RCC_SYSTICK_CLKSOURCE_LSE RCC_CCIPR1_SYSTICKSEL_1 /*!< LSE clock used as SYSTICK clock source */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
+ * @{
+ */
+#define LL_RCC_APB1_DIV_1 0x00000000U /*!< HCLK not divided */
+#define LL_RCC_APB1_DIV_2 RCC_CFGR2_PPRE1_2 /*!< HCLK divided by 2 */
+#define LL_RCC_APB1_DIV_4 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_0) /*!< HCLK divided by 4 */
+#define LL_RCC_APB1_DIV_8 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_1) /*!< HCLK divided by 8 */
+#define LL_RCC_APB1_DIV_16 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_0) /*!< HCLK divided by 16 */
+/**
+ * @}
+ */
+
+
+/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
+ * @{
+ */
+#define LL_RCC_APB2_DIV_1 0x00000000U /*!< HCLK not divided */
+#define LL_RCC_APB2_DIV_2 RCC_CFGR2_PPRE2_2 /*!< HCLK divided by 2 */
+#define LL_RCC_APB2_DIV_4 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_0) /*!< HCLK divided by 4 */
+#define LL_RCC_APB2_DIV_8 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_1) /*!< HCLK divided by 8 */
+#define LL_RCC_APB2_DIV_16 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_1 | RCC_CFGR2_PPRE2_0) /*!< HCLK divided by 16 */
+/**
+ * @}
+ */
+
+
+/** @defgroup RCC_LL_EC_APB3_DIV APB high-speed prescaler (APB3)
+ * @{
+ */
+#define LL_RCC_APB3_DIV_1 0x00000000U /*!< HCLK not divided */
+#define LL_RCC_APB3_DIV_2 RCC_CFGR3_PPRE3_2 /*!< HCLK divided by 2 */
+#define LL_RCC_APB3_DIV_4 (RCC_CFGR3_PPRE3_2 | RCC_CFGR3_PPRE3_0) /*!< HCLK divided by 4 */
+#define LL_RCC_APB3_DIV_8 (RCC_CFGR3_PPRE3_2 | RCC_CFGR3_PPRE3_1) /*!< HCLK divided by 8 */
+#define LL_RCC_APB3_DIV_16 (RCC_CFGR3_PPRE3_2 | RCC_CFGR3_PPRE3_1 | RCC_CFGR3_PPRE3_0) /*!< HCLK divided by 16 */
+/**
+ * @}
+ */
+
+
+/** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK Wakeup from Stop and CSS backup clock selection
+ * @{
+ */
+#define LL_RCC_STOP_WAKEUPCLOCK_MSIS 0x00000000U /*!< MSIS selection after wake-up from STOP */
+#define LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR1_STOPWUCK /*!< HSI selection after wake-up from STOP */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
+ * @{
+ */
+#define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO output disabled, no clock on MCO */
+#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR1_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_MSIS RCC_CFGR1_MCOSEL_1 /*!< MSIS selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR1_MCOSEL_0 | RCC_CFGR1_MCOSEL_1) /*!< HSI selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR1_MCOSEL_2 /*!< HSE selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR1_MCOSEL_0 | RCC_CFGR1_MCOSEL_2) /*!< Main PLL selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR1_MCOSEL_1 | RCC_CFGR1_MCOSEL_2) /*!< LSI selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR1_MCOSEL_0 | RCC_CFGR1_MCOSEL_1| RCC_CFGR1_MCOSEL_2)/*!< LSE selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR1_MCOSEL_3 /*!< HSI48 selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_MSIK (RCC_CFGR1_MCOSEL_0 | RCC_CFGR1_MCOSEL_3) /*!< MSIK selection as MCO1 source */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
+ * @{
+ */
+#define LL_RCC_MCO1_DIV_1 0x00000000U /*!< MCO not divided */
+#define LL_RCC_MCO1_DIV_2 RCC_CFGR1_MCOPRE_0 /*!< MCO divided by 2 */
+#define LL_RCC_MCO1_DIV_4 RCC_CFGR1_MCOPRE_1 /*!< MCO divided by 4 */
+#define LL_RCC_MCO1_DIV_8 (RCC_CFGR1_MCOPRE_1 | RCC_CFGR1_MCOPRE_0) /*!< MCO divided by 8 */
+#define LL_RCC_MCO1_DIV_16 RCC_CFGR1_MCOPRE_2 /*!< MCO divided by 16 */
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
+ * @{
+ */
+#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
+#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
+ * @{
+ */
+#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_USART_CLKSOURCE Peripheral USARTx clock source selection
+ * @{
+ */
+#define LL_RCC_USART1_CLKSOURCE_PCLK2 (RCC_CCIPR1_USART1SEL << 16U) /*!< PCLK2 clock used as USART1 clock source */
+#define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR1_USART1SEL << 16U) | RCC_CCIPR1_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */
+#define LL_RCC_USART1_CLKSOURCE_HSI ((RCC_CCIPR1_USART1SEL << 16U) | RCC_CCIPR1_USART1SEL_1) /*!< HSI clock used as USART1 clock source */
+#define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR1_USART1SEL << 16U) | RCC_CCIPR1_USART1SEL) /*!< LSE clock used as USART1 clock source */
+#define LL_RCC_USART2_CLKSOURCE_PCLK1 (RCC_CCIPR1_USART2SEL << 16U) /*!< PCLK1 clock used as USART2 clock source */
+#define LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_CCIPR1_USART2SEL << 16U) | RCC_CCIPR1_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */
+#define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR1_USART2SEL << 16U) | RCC_CCIPR1_USART2SEL_1) /*!< HSI clock used as USART2 clock source */
+#define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR1_USART2SEL << 16U) | RCC_CCIPR1_USART2SEL) /*!< LSE clock used as USART2 clock source */
+#define LL_RCC_USART3_CLKSOURCE_PCLK1 (RCC_CCIPR1_USART3SEL << 16U) /*!< PCLK3 clock used as USART3 clock source */
+#define LL_RCC_USART3_CLKSOURCE_SYSCLK ((RCC_CCIPR1_USART3SEL << 16U) | RCC_CCIPR1_USART3SEL_0) /*!< SYSCLK clock used as USART3 clock source */
+#define LL_RCC_USART3_CLKSOURCE_HSI ((RCC_CCIPR1_USART3SEL << 16U) | RCC_CCIPR1_USART3SEL_1) /*!< HSI clock used as USART3 clock source */
+#define LL_RCC_USART3_CLKSOURCE_LSE ((RCC_CCIPR1_USART3SEL << 16U) | RCC_CCIPR1_USART3SEL) /*!< LSE clock used as USART3 clock source */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_UART_CLKSOURCE Peripheral UARTx clock source selection
+ * @{
+ */
+#define LL_RCC_UART4_CLKSOURCE_PCLK1 (RCC_CCIPR1_UART4SEL << 16U) /*!< PCLK1 clock used as UART4 clock source */
+#define LL_RCC_UART4_CLKSOURCE_SYSCLK ((RCC_CCIPR1_UART4SEL << 16U) | RCC_CCIPR1_UART4SEL_0) /*!< SYSCLK clock used as UART4 clock source */
+#define LL_RCC_UART4_CLKSOURCE_HSI ((RCC_CCIPR1_UART4SEL << 16U) | RCC_CCIPR1_UART4SEL_1) /*!< HSI clock used as UART4 clock source */
+#define LL_RCC_UART4_CLKSOURCE_LSE ((RCC_CCIPR1_UART4SEL << 16U) | RCC_CCIPR1_UART4SEL) /*!< LSE clock used as UART4 clock source */
+#define LL_RCC_UART5_CLKSOURCE_PCLK1 (RCC_CCIPR1_UART5SEL << 16U) /*!< PCLK1 clock used as UART5 clock source */
+#define LL_RCC_UART5_CLKSOURCE_SYSCLK ((RCC_CCIPR1_UART5SEL << 16U) | RCC_CCIPR1_UART5SEL_0) /*!< SYSCLK clock used as UART5 clock source */
+#define LL_RCC_UART5_CLKSOURCE_HSI ((RCC_CCIPR1_UART5SEL << 16U) | RCC_CCIPR1_UART5SEL_1) /*!< HSI clock used as UART5 clock source */
+#define LL_RCC_UART5_CLKSOURCE_LSE ((RCC_CCIPR1_UART5SEL << 16U) | RCC_CCIPR1_UART5SEL) /*!< LSE clock used as UART5 clock source */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_LPUART_CLKSOURCE Peripheral LPUARTx clock source selection
+ * @{
+ */
+#define LL_RCC_LPUART1_CLKSOURCE_PCLK3 0x00000000U /*!< PCLK3 clock used as LPUART1 clock source */
+#define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR3_LPUART1SEL_0 /*!< SYSCLK clock used as LPUART1 clock source */
+#define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR3_LPUART1SEL_1 /*!< HSI clock used as LPUART1 clock source */
+#define LL_RCC_LPUART1_CLKSOURCE_LSE (RCC_CCIPR3_LPUART1SEL_0 | RCC_CCIPR3_LPUART1SEL_1) /*!< LSE clock used as LPUART1 clock source */
+#define LL_RCC_LPUART1_CLKSOURCE_MSIK RCC_CCIPR3_LPUART1SEL_2 /*!< MSIK clock used as LPUART1 clock source */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_I2C_CLKSOURCE Peripheral I2Cx clock source selection
+ * @{
+ */
+#define LL_RCC_I2C1_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C1 clock source */
+#define LL_RCC_I2C1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | \
+ (RCC_CCIPR1_I2C1SEL_0 >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< SYSCLK clock used as I2C1 clock source */
+#define LL_RCC_I2C1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | \
+ (RCC_CCIPR1_I2C1SEL_1 >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< HSI clock used as I2C1 clock source */
+#define LL_RCC_I2C1_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | \
+ (RCC_CCIPR1_I2C1SEL >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< MSIK clock used as I2C1 clock source */
+#define LL_RCC_I2C2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C2 clock source */
+#define LL_RCC_I2C2_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U) | \
+ (RCC_CCIPR1_I2C2SEL_0 >> RCC_CCIPR1_I2C2SEL_Pos)) /*!< SYSCLK clock used as I2C2 clock source */
+#define LL_RCC_I2C2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U) | \
+ (RCC_CCIPR1_I2C2SEL_1 >> RCC_CCIPR1_I2C2SEL_Pos)) /*!< HSI clock used as I2C2 clock source */
+#define LL_RCC_I2C2_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U) | \
+ (RCC_CCIPR1_I2C2SEL >> RCC_CCIPR1_I2C2SEL_Pos)) /*!< MSIK clock used as I2C2 clock source */
+#define LL_RCC_I2C3_CLKSOURCE_PCLK3 ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U)) /*!< PCLK3 clock used as I2C3 clock source */
+#define LL_RCC_I2C3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | \
+ (RCC_CCIPR3_I2C3SEL_0 >> RCC_CCIPR3_I2C3SEL_Pos)) /*!< SYSCLK clock used as I2C3 clock source */
+#define LL_RCC_I2C3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | \
+ (RCC_CCIPR3_I2C3SEL_1 >> RCC_CCIPR3_I2C3SEL_Pos)) /*!< HSI clock used as I2C3 clock source */
+#define LL_RCC_I2C3_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | \
+ (RCC_CCIPR3_I2C3SEL >> RCC_CCIPR3_I2C3SEL_Pos)) /*!< MSIK clock used as I2C3 clock source */
+#define LL_RCC_I2C4_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C4SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C4 clock source */
+#define LL_RCC_I2C4_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C4SEL_Pos << 16U) | \
+ (RCC_CCIPR1_I2C4SEL_0 >> RCC_CCIPR1_I2C4SEL_Pos)) /*!< SYSCLK clock used as I2C4 clock source */
+#define LL_RCC_I2C4_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C4SEL_Pos << 16U) | \
+ (RCC_CCIPR1_I2C4SEL_1 >> RCC_CCIPR1_I2C4SEL_Pos)) /*!< HSI clock used as I2C4 clock source */
+#define LL_RCC_I2C4_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C4SEL_Pos << 16U) | \
+ (RCC_CCIPR1_I2C4SEL >> RCC_CCIPR1_I2C4SEL_Pos)) /*!< MSIK clock used as I2C4 clock source */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_SPI_CLKSOURCE Peripheral SPIx clock source selection
+ * @{
+ */
+#define LL_RCC_SPI1_CLKSOURCE_PCLK2 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U)) /*!< PCLK2 clock used as SPI1 clock source */
+#define LL_RCC_SPI1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | \
+ (RCC_CCIPR1_SPI1SEL_0 >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< SYSCLK clock used as SPI1 clock source */
+#define LL_RCC_SPI1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | \
+ (RCC_CCIPR1_SPI1SEL_1 >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< HSI clock used as SPI1 clock source */
+#define LL_RCC_SPI1_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | \
+ (RCC_CCIPR1_SPI1SEL >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< MSIK clock used as SPI1 clock source */
+#define LL_RCC_SPI2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI2SEL_Pos << 16U)) /*!< PCLK1 clock used as SPI2 clock source */
+#define LL_RCC_SPI2_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI2SEL_Pos << 16U) | \
+ (RCC_CCIPR1_SPI2SEL_0 >> RCC_CCIPR1_SPI2SEL_Pos)) /*!< SYSCLK clock used as SPI2 clock source */
+#define LL_RCC_SPI2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI2SEL_Pos << 16U) | \
+ (RCC_CCIPR1_SPI2SEL_1 >> RCC_CCIPR1_SPI2SEL_Pos)) /*!< HSI clock used as SPI2 clock source */
+#define LL_RCC_SPI2_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI2SEL_Pos << 16U) | \
+ (RCC_CCIPR1_SPI2SEL >> RCC_CCIPR1_SPI2SEL_Pos)) /*!< MSIK clock used as SPI2 clock source */
+#define LL_RCC_SPI3_CLKSOURCE_PCLK3 ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U)) /*!< PCLK3 clock used as SPI3 clock source */
+#define LL_RCC_SPI3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | \
+ (RCC_CCIPR3_SPI3SEL_0 >> RCC_CCIPR3_SPI3SEL_Pos)) /*!< SYSCLK clock used as SPI3 clock source */
+#define LL_RCC_SPI3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | \
+ (RCC_CCIPR3_SPI3SEL_1 >> RCC_CCIPR3_SPI3SEL_Pos)) /*!< HSI clock used as SPI3 clock source */
+#define LL_RCC_SPI3_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | \
+ (RCC_CCIPR3_SPI3SEL >> RCC_CCIPR3_SPI3SEL_Pos)) /*!< MSIK clock used as SPI3 clock source */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_LPTIM_CLKSOURCE Peripheral LPTIMx clock source selection
+ * @{
+ */
+#define LL_RCC_LPTIM1_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U)) /*!< MSIK clock used as LPTIM1 clock source */
+#define LL_RCC_LPTIM1_CLKSOURCE_LSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U) | \
+ (RCC_CCIPR3_LPTIM1SEL_0 >> RCC_CCIPR3_LPTIM1SEL_Pos)) /*!< LSI clock used as LPTIM1 clock source */
+#define LL_RCC_LPTIM1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U) | \
+ (RCC_CCIPR3_LPTIM1SEL_1 >> RCC_CCIPR3_LPTIM1SEL_Pos)) /*!< HSI clock used as LPTIM1 clock source */
+#define LL_RCC_LPTIM1_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U) | \
+ (RCC_CCIPR3_LPTIM1SEL >> RCC_CCIPR3_LPTIM1SEL_Pos)) /*!< LSE clock used as LPTIM1 clock source */
+#define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U)) /*!< PCLK1 clock used as LPTIM2 clock source */
+#define LL_RCC_LPTIM2_CLKSOURCE_LSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U) | \
+ (RCC_CCIPR1_LPTIM2SEL_0 >> RCC_CCIPR1_LPTIM2SEL_Pos)) /*!< LSI clock used as LPTIM2 clock source */
+#define LL_RCC_LPTIM2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U) | \
+ (RCC_CCIPR1_LPTIM2SEL_1 >> RCC_CCIPR1_LPTIM2SEL_Pos)) /*!< HSI clock used as LPTIM2 clock source */
+#define LL_RCC_LPTIM2_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U) | \
+ (RCC_CCIPR1_LPTIM2SEL >> RCC_CCIPR1_LPTIM2SEL_Pos)) /*!< LSE clock used as LPTIM2 clock source */
+#define LL_RCC_LPTIM34_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM34SEL_Pos << 16U)) /*!< MSIK clock used as LPTIM34 clock source*/
+#define LL_RCC_LPTIM34_CLKSOURCE_LSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM34SEL_Pos << 16U) | \
+ (RCC_CCIPR3_LPTIM34SEL_0 >> RCC_CCIPR3_LPTIM34SEL_Pos)) /*!< LSI clock used as LPTIM34 clock source */
+#define LL_RCC_LPTIM34_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM34SEL_Pos << 16U) | \
+ (RCC_CCIPR3_LPTIM34SEL_1 >> RCC_CCIPR3_LPTIM34SEL_Pos)) /*!< HSI clock used as LPTIM34 clock source */
+#define LL_RCC_LPTIM34_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM34SEL_Pos << 16U) | \
+ (RCC_CCIPR3_LPTIM34SEL >> RCC_CCIPR3_LPTIM34SEL_Pos)) /*!< LSE clock used as LPTIM34 clock source */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE Peripheral FDCAN kernel clock source selection
+ * @{
+ */
+#define LL_RCC_FDCAN_CLKSOURCE_HSE 0x00000000U /*!< HSE clock used as FDCAN kernel clock source */
+#define LL_RCC_FDCAN_CLKSOURCE_PLL1 RCC_CCIPR1_FDCANSEL_0 /*!< PLL1 Q clock used as FDCAN kernel clock source */
+#define LL_RCC_FDCAN_CLKSOURCE_PLL2 RCC_CCIPR1_FDCANSEL_1 /*!< PLL2 P clock used as FDCAN kernel clock source */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_SAI_CLKSOURCE Peripheral SAIx clock source selection
+ * @{
+ */
+#define LL_RCC_SAI1_CLKSOURCE_PLL2 (RCC_CCIPR2_SAI1SEL << 16U) /*!< PLL2 clock used as SAI1 clock source */
+#define LL_RCC_SAI1_CLKSOURCE_PLL3 ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_0) /*!< PLL3 clock used as SAI1 clock source */
+#define LL_RCC_SAI1_CLKSOURCE_PLL1 ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_1) /*!< PLL1 clock used as SAI1 clock source */
+#define LL_RCC_SAI1_CLKSOURCE_HSI ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_2) /*!< HSI clock used as SAI1 clock source */
+#define LL_RCC_SAI1_CLKSOURCE_PIN ((RCC_CCIPR2_SAI1SEL << 16U) | (RCC_CCIPR2_SAI1SEL_1 | \
+ RCC_CCIPR2_SAI1SEL_0)) /*!< External input clock used as SAI1 clock source */
+#define LL_RCC_SAI2_CLKSOURCE_PLL2 (RCC_CCIPR2_SAI2SEL << 16U) /*!< PLL2 clock used as SAI2 clock source */
+#define LL_RCC_SAI2_CLKSOURCE_PLL3 ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_0) /*!< PLL3 clock used as SAI2 clock source */
+#define LL_RCC_SAI2_CLKSOURCE_PLL1 ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_1) /*!< PLL1clock used as SAI2 clock source */
+#define LL_RCC_SAI2_CLKSOURCE_HSI ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_2) /*!< HSI clock used as SAI2 clock source */
+#define LL_RCC_SAI2_CLKSOURCE_PIN ((RCC_CCIPR2_SAI2SEL << 16U) | (RCC_CCIPR2_SAI2SEL_1 | \
+ RCC_CCIPR2_SAI2SEL_0)) /*!< External input clock used as SAI2 clock source */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_SDMMC_KERNELCLKSOURCE Peripheral SDMMC1/2 kernel clock source selection
+ * @{
+ */
+#define LL_RCC_SDMMC12_KERNELCLKSOURCE_48CLK 0x00000000U /*!< 48MHz clock from internal multiplexor used as SDMMC1/2 clock source */
+#define LL_RCC_SDMMC12_KERNELCLKSOURCE_PLL1 RCC_CCIPR2_SDMMCSEL /*!< PLL1 "P" used as SDMMC1/2 clock source */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_SDMMC12_CLKSOURCE Peripheral SDMMC clock source selection
+ * @{
+ */
+#define LL_RCC_SDMMC12_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as SDMMC1/2 clock source */
+#define LL_RCC_SDMMC12_CLKSOURCE_PLL2 RCC_CCIPR1_CLK48MSEL_0 /*!< PLL2 "Q" clock used as SDMMC1/2 clock source */
+#define LL_RCC_SDMMC12_CLKSOURCE_PLL1 RCC_CCIPR1_CLK48MSEL_1 /*!< PLL1 "Q" clock used as SDMMC1/2 clock source */
+#define LL_RCC_SDMMC12_CLKSOURCE_MSIK RCC_CCIPR1_CLK48MSEL /*!< MSIK clock used as SDMMC1/2 clock source */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
+ * @{
+ */
+#define LL_RCC_RNG_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as RNG clock source */
+#define LL_RCC_RNG_CLKSOURCE_HSI48_DIV2 RCC_CCIPR2_RNGSEL_0 /*!< HSI48/2 clock used as RNG clock source */
+#define LL_RCC_RNG_CLKSOURCE_HSI RCC_CCIPR2_RNGSEL_1 /*!< HSI clock used as RNG clock source */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
+ * @{
+ */
+#define LL_RCC_USB_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as USB clock source */
+#define LL_RCC_USB_CLKSOURCE_PLL2 RCC_CCIPR1_CLK48MSEL_0 /*!< PLL2 "Q" clock used as USB clock source */
+#define LL_RCC_USB_CLKSOURCE_PLL1 RCC_CCIPR1_CLK48MSEL_1 /*!< PLL1 "Q" clock used as USB clock source */
+#define LL_RCC_USB_CLKSOURCE_MSIK RCC_CCIPR1_CLK48MSEL /*!< MSIK clock used as USB clock source */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_ADCDAC_CLKSOURCE Peripheral ADCx and DAC1 clock source selection
+ * @{
+ */
+#define LL_RCC_ADCDAC_CLKSOURCE_HCLK 0x00000000U /*!< No clock used as ADCx/DAC1 clock source */
+#define LL_RCC_ADCDAC_CLKSOURCE_SYSCLK RCC_CCIPR3_ADCDACSEL_0 /*!< SYSCLK clock used as ADCx/DAC1 clock source */
+#define LL_RCC_ADCDAC_CLKSOURCE_PLL2 RCC_CCIPR3_ADCDACSEL_1 /*!< PLL2 clock used as ADCx/DAC1 clock source */
+#define LL_RCC_ADCDAC_CLKSOURCE_HSI RCC_CCIPR3_ADCDACSEL_2 /*!< HSI clock used as ADCx/DAC1 clock source */
+#define LL_RCC_ADCDAC_CLKSOURCE_HSE (RCC_CCIPR3_ADCDACSEL_1 | RCC_CCIPR3_ADCDACSEL_0) /*!< HSE clock used as ADCx/DAC1 clock source */
+#define LL_RCC_ADCDAC_CLKSOURCE_MSIK (RCC_CCIPR3_ADCDACSEL_2 | RCC_CCIPR3_ADCDACSEL_0) /*!< MSIK clock used as ADCx/DAC1 clock source */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_DAC1_CLKSOURCE Peripheral DAC1 clock source selection
+ * @{
+ */
+#define LL_RCC_DAC1_CLKSOURCE_LSE 0x00000000U /*!< LSE clock used as DAC1 clock */
+#define LL_RCC_DAC1_CLKSOURCE_LSI RCC_CCIPR3_DAC1SEL /*!< LSI clock used as DAC1 clock */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_ADF1_CLKSOURCE Peripheral ADF1 clock source selection
+ * @{
+ */
+#define LL_RCC_ADF1_CLKSOURCE_HCLK 0x00000000U /*!< HCLK clock used as ADF1 clock */
+#define LL_RCC_ADF1_CLKSOURCE_PLL1 RCC_CCIPR3_ADF1SEL_0 /*!< PLL1 clock used as ADF1 clock */
+#define LL_RCC_ADF1_CLKSOURCE_PLL3 RCC_CCIPR3_ADF1SEL_1 /*!< PLL3 clock used as ADF1 clock */
+#define LL_RCC_ADF1_CLKSOURCE_MSIK RCC_CCIPR3_ADF1SEL_2 /*!< MSIK clock used as ADF1 clock */
+#define LL_RCC_ADF1_CLKSOURCE_PIN (RCC_CCIPR3_ADF1SEL_1 | RCC_CCIPR3_ADF1SEL_0) /*!< PIN SAI1_EXTCLK clock used as ADF1 clock */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_MDF1_CLKSOURCE Peripheral MDF1 clock source selection
+ * @{
+ */
+#define LL_RCC_MDF1_CLKSOURCE_HCLK 0x00000000U /*!< HCLK clock used as MDF1 clock */
+#define LL_RCC_MDF1_CLKSOURCE_PLL1 RCC_CCIPR2_MDF1SEL_0 /*!< PLL1 clock used as MDF1 clock */
+#define LL_RCC_MDF1_CLKSOURCE_PLL3 RCC_CCIPR2_MDF1SEL_1 /*!< PLL3 clock used as MDF1 clock */
+#define LL_RCC_MDF1_CLKSOURCE_MSIK RCC_CCIPR2_MDF1SEL_2 /*!< MSIK clock used as MDF1 clock */
+#define LL_RCC_MDF1_CLKSOURCE_PIN (RCC_CCIPR2_MDF1SEL_1 | RCC_CCIPR2_MDF1SEL_0) /*!< PIN SAI1_EXTCLK clock used as MDF1 clock */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_OCTOSPI_CLKSOURCE Peripheral OCTOSPI kernel clock source selection
+ * @{
+ */
+#define LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK clock used as OctoSPI kernel clock source */
+#define LL_RCC_OCTOSPI_CLKSOURCE_MSIK RCC_CCIPR2_OCTOSPISEL_0 /*!< MSIK clock used as OctoSPI kernel clock source */
+#define LL_RCC_OCTOSPI_CLKSOURCE_PLL1 RCC_CCIPR2_OCTOSPISEL_1 /*!< PLL1 "Q" clock used as OctoSPI kernel clock source */
+#define LL_RCC_OCTOSPI_CLKSOURCE_PLL2 (RCC_CCIPR2_OCTOSPISEL_1|RCC_CCIPR2_OCTOSPISEL_0) /*!< PLL2 "Q" clock used as OctoSPI kernel clock source */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_TIM_INPUT_CAPTURE_CLOCKSource TIM Input capture clock source selection
+ * @{
+ */
+#define LL_RCC_TIMIC_CLKSOURCE_NONE 0x00000000U /*!< No clock available for TIM16/TIM17 and LPTIM2 input capture */
+#define LL_RCC_TIMIC_CLKSOURCE_HSI_DIV256 RCC_CCIPR1_TIMICSEL_2 /*!< HSI/256 selected for TIM16/TIM17 and LPTIM2 input capture */
+#define LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV1024 RCC_CCIPR1_TIMICSEL_2 /*!< MSIS/1024 selected for TIM16/TIM17 and LPTIM2 input capture */
+#define LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV4 (RCC_CCIPR1_TIMICSEL_2 | RCC_CCIPR1_TIMICSEL_1) /*!< MSIS/4 selected for TIM16/TIM17 and LPTIM2 input capture */
+#define LL_RCC_TIMIC_CLKSOURCE_MSIK_DIV4 (RCC_CCIPR1_TIMICSEL_2 | RCC_CCIPR1_TIMICSEL_0) /*!< MSIK/4 selected for TIM16/TIM17 and LPTIM2 input capture */
+#define LL_RCC_TIMIC_CLKSOURCE_MSIK_DIV1024 (RCC_CCIPR1_TIMICSEL_2 | RCC_CCIPR1_TIMICSEL_1 | \
+ RCC_CCIPR1_TIMICSEL_0) /*!< MSIK/1024 selected for TIM16/TIM17 and LPTIM2 input capture */
+/**
+ * @}
+ */
+
+
+/** @defgroup RCC_LL_EC_SAES_CLKSOURCE Peripheral SAES clock source selection
+ * @{
+ */
+#define LL_RCC_SAES_CLKSOURCE_SHSI 0x00000000U /*!< SHSI clock used as SAES clock source */
+#define LL_RCC_SAES_CLKSOURCE_SHSI_DIV2 RCC_CCIPR2_SAESSEL /*!< SHSI_DIV2 clock used as SAES clock source */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_USART Peripheral USARTx get clock source
+ * @{
+ */
+#define LL_RCC_USART1_CLKSOURCE RCC_CCIPR1_USART1SEL /*!< USART1 Clock source selection */
+#define LL_RCC_USART2_CLKSOURCE RCC_CCIPR1_USART2SEL /*!< USART2 Clock source selection */
+#define LL_RCC_USART3_CLKSOURCE RCC_CCIPR1_USART3SEL /*!< USART3 Clock source selection */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_UART Peripheral UARTx get clock source
+ * @{
+ */
+#define LL_RCC_UART4_CLKSOURCE RCC_CCIPR1_UART4SEL /*!< UART4 Clock source selection */
+#define LL_RCC_UART5_CLKSOURCE RCC_CCIPR1_UART5SEL /*!< UART5 Clock source selection */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_SPI Peripheral SPIx get clock source
+ * @{
+ */
+#define LL_RCC_SPI1_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | \
+ (RCC_CCIPR1_SPI1SEL >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< SPI1 Clock source selection */
+#define LL_RCC_SPI2_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI2SEL_Pos << 16U) | \
+ (RCC_CCIPR1_SPI2SEL >> RCC_CCIPR1_SPI2SEL_Pos)) /*!< SPI2 Clock source selection */
+#define LL_RCC_SPI3_CLKSOURCE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | \
+ (RCC_CCIPR3_SPI3SEL >> RCC_CCIPR3_SPI3SEL_Pos)) /*!< SPI3 Clock source selection */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_LPUART Peripheral LPUARTx get clock source
+ * @{
+ */
+#define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR3_LPUART1SEL /*!< LPUART1 Clock source selection */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_I2C Peripheral I2Cx get clock source
+ * @{
+ */
+#define LL_RCC_I2C1_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | \
+ (RCC_CCIPR1_I2C1SEL >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< I2C1 Clock source selection */
+#define LL_RCC_I2C2_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U) | \
+ (RCC_CCIPR1_I2C2SEL >> RCC_CCIPR1_I2C2SEL_Pos)) /*!< I2C2 Clock source selection */
+#define LL_RCC_I2C3_CLKSOURCE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | \
+ (RCC_CCIPR3_I2C3SEL >> RCC_CCIPR3_I2C3SEL_Pos)) /*!< I2C3 Clock source selection */
+#define LL_RCC_I2C4_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C4SEL_Pos << 16U) | \
+ (RCC_CCIPR1_I2C4SEL >> RCC_CCIPR1_I2C4SEL_Pos)) /*!< I2C4 Clock source selection */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_LPTIM Peripheral LPTIMx get clock source
+ * @{
+ */
+#define LL_RCC_LPTIM1_CLKSOURCE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U) | \
+ (RCC_CCIPR3_LPTIM1SEL >> RCC_CCIPR3_LPTIM1SEL_Pos)) /*!< LPTIM1 Clock source selection */
+#define LL_RCC_LPTIM2_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U) | \
+ (RCC_CCIPR1_LPTIM2SEL >> RCC_CCIPR1_LPTIM2SEL_Pos)) /*!< LPTIM2 Clock source selection */
+#define LL_RCC_LPTIM34_CLKSOURCE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM34SEL_Pos << 16U) | \
+ (RCC_CCIPR3_LPTIM34SEL >> RCC_CCIPR3_LPTIM34SEL_Pos)) /*!< LPTIM3 and LPTIM4 Clock source selection */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_SAI Peripheral SAIx get clock source
+ * @{
+ */
+#define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR2_SAI1SEL /*!< SAI1 Clock source selection */
+#define LL_RCC_SAI2_CLKSOURCE RCC_CCIPR2_SAI2SEL /*!< SAI2 Clock source selection */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_SDMMC_KERNEL Peripheral SDMMC get kernel clock source
+ * @{
+ */
+#define LL_RCC_SDMMC_KERNELCLKSOURCE RCC_CCIPR2_SDMMCSEL /*!< SDMMC1/2 Kernel Clock source selection */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_SDMMC1/2 Peripheral SDMMC get clock source
+ * @{
+ */
+#define LL_RCC_SDMMC_CLKSOURCE RCC_CCIPR1_CLK48MSEL /*!< SDMMC1/2 Clock source selection */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
+ * @{
+ */
+#define LL_RCC_RNG_CLKSOURCE RCC_CCIPR2_RNGSEL /*!< RNG Clock source selection */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
+ * @{
+ */
+#define LL_RCC_USB_CLKSOURCE RCC_CCIPR1_CLK48MSEL /*!< USB Clock source selection */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_ADCDAC Peripheral ADCDAC get clock source
+ * @{
+ */
+#define LL_RCC_ADCDAC_CLKSOURCE RCC_CCIPR3_ADCDACSEL /*!< ADCDACs Clock source selection */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_MDF1 Peripheral MDF1 get clock source
+ * @{
+ */
+#define LL_RCC_MDF1_CLKSOURCE RCC_CCIPR2_MDF1SEL /* MDF1 Clock source selection */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_DAC1 Peripheral DAC1 get clock source
+ * @{
+ */
+#define LL_RCC_DAC1_CLKSOURCE RCC_CCIPR3_DAC1SEL /* DAC1 Clock source selection */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_ADF1 Peripheral ADF1 get clock source
+ * @{
+ */
+#define LL_RCC_ADF1_CLKSOURCE RCC_CCIPR3_ADF1SEL /*!< ADF1 Clock source selection */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_FDCAN Peripheral FDCAN get kernel clock source
+ * @{
+ */
+#define LL_RCC_FDCAN_CLKSOURCE RCC_CCIPR1_FDCANSEL /*!< FDCAN Kernel Clock source selection */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_OCTOSPI Peripheral OCTOSPI get clock source
+ * @{
+ */
+#define LL_RCC_OCTOSPI_CLKSOURCE RCC_CCIPR2_OCTOSPISEL /*!< OctoSPI Clock source selection */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_SAES Peripheral SAES get clock source
+ * @{
+ */
+#define LL_RCC_SAES_CLKSOURCE RCC_CCIPR2_SAESSEL /*!< SAES Clock source selection */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_PLL1SOURCE PLL1 entry clock source
+ * @{
+ */
+#define LL_RCC_PLL1SOURCE_NONE 0x00000000U /*!< No clock selected as main PLL1 entry clock source */
+#define LL_RCC_PLL1SOURCE_MSIS RCC_PLL1CFGR_PLL1SRC_0 /*!< MSIS clock selected as main PLL1 entry clock source */
+#define LL_RCC_PLL1SOURCE_HSI RCC_PLL1CFGR_PLL1SRC_1 /*!< HSI clock selected as main PLL1 entry clock source */
+#define LL_RCC_PLL1SOURCE_HSE (RCC_PLL1CFGR_PLL1SRC_0 | RCC_PLL1CFGR_PLL1SRC_1) /*!< HSE clock selected as main PLL1 entry clock source */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_PLLINPUTRANGE All PLLs input ranges
+ * @{
+ */
+#define LL_RCC_PLLINPUTRANGE_4_8 0x00000002U /*!< VCO input range: 4 to 8 MHz */
+#define LL_RCC_PLLINPUTRANGE_8_16 0x00000003U /*!< VCO input range: 8 to 16 MHz */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_PLL2SOURCE PLL2 entry clock source
+ * @{
+ */
+#define LL_RCC_PLL2SOURCE_NONE 0x00000000U /*!< No clock selected as main PLL2 entry clock source */
+#define LL_RCC_PLL2SOURCE_MSIS RCC_PLL2CFGR_PLL2SRC_0 /*!< MSIS clock selected as main PLL2 entry clock source */
+#define LL_RCC_PLL2SOURCE_HSI RCC_PLL2CFGR_PLL2SRC_1 /*!< HSI clock selected as main PLL2 entry clock source */
+#define LL_RCC_PLL2SOURCE_HSE (RCC_PLL2CFGR_PLL2SRC_0 | RCC_PLL2CFGR_PLL2SRC_1) /*!< HSE clock selected as main PLL2 entry clock source */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_PLL3SOURCE PLL3 entry clock source
+ * @{
+ */
+#define LL_RCC_PLL3SOURCE_NONE 0x00000000U /*!< No clock selected as main PLL3 entry clock source */
+#define LL_RCC_PLL3SOURCE_MSIS RCC_PLL3CFGR_PLL3SRC_0 /*!< MSIS clock selected as main PLL3 entry clock source */
+#define LL_RCC_PLL3SOURCE_HSI RCC_PLL3CFGR_PLL3SRC_1 /*!< HSI clock selected as main PLL3 entry clock source */
+#define LL_RCC_PLL3SOURCE_HSE (RCC_PLL3CFGR_PLL3SRC_0 | RCC_PLL3CFGR_PLL3SRC_1) /*!< HSE clock selected as main PLL3 entry clock source */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_MSIRANGESEL MSI clock range selection
+ * @{
+ */
+#define LL_RCC_MSIRANGESEL_STANDBY 0U /*!< MSI Range is provided by MSISRANGE */
+#define LL_RCC_MSIRANGESEL_RUN 1U /*!< MSI Range is provided by MSISRANGE */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_Security_Services Security Services
+ * @note Only available when system implements security (TZEN=1)
+ * @{
+ */
+#define LL_RCC_ALL_NSEC 0U /*!< No security on RCC resources (default) */
+#define LL_RCC_ALL_SEC RCC_SECURE_MASK /*!< Security on all RCC resources */
+
+#define LL_RCC_HSI_SEC RCC_SECCFGR_HSISEC /*!< HSI clock configuration security */
+#define LL_RCC_HSI_NSEC 0U /*!< HSI clock configuration secure/non-secure access */
+#define LL_RCC_HSE_SEC RCC_SECCFGR_HSESEC /*!< HSE clock configuration security */
+#define LL_RCC_HSE_NSEC 0U /*!< HSE clock configuration secure/non-secure access */
+#define LL_RCC_MSI_SEC RCC_SECCFGR_MSISEC /*!< MSI clock configuration security */
+#define LL_RCC_MSI_NSEC 0U /*!< MSI clock configuration secure/non-secure access */
+#define LL_RCC_LSE_SEC RCC_SECCFGR_LSESEC /*!< LSE clock configuration security */
+#define LL_RCC_LSE_NSEC 0U /*!< LSE clock configuration secure/non-secure access */
+#define LL_RCC_LSI_SEC RCC_SECCFGR_LSISEC /*!< LSI clock configuration security */
+#define LL_RCC_LSI_NSEC 0U /*!< LSI clock configuration secure/non-secure access */
+#define LL_RCC_SYSCLK_SEC RCC_SECCFGR_SYSCLKSEC /*!< SYSCLK clock; STOPWUCK and MCO output configuration security */
+#define LL_RCC_SYSCLK_NSEC 0U /*!< SYSCLK clock; STOPWUCK and MCO output configuration secure/non-secure access */
+#define LL_RCC_PRESCALERS_SEC RCC_SECCFGR_PRESCSEC /*!< AHBx/APBx prescaler configuration security */
+#define LL_RCC_PRESCALERS_NSEC 0U /*!< AHBx/APBx prescaler configuration secure/non-secure access */
+#define LL_RCC_PLL1_SEC RCC_SECCFGR_PLL1SEC /*!< PLL1 clock configuration security */
+#define LL_RCC_PLL1_NSEC 0U /*!< main PLL1 clock configuration secure/non-secure access */
+#define LL_RCC_PLL2_SEC RCC_SECCFGR_PLL2SEC /*!< PLL2 clock configuration security */
+#define LL_RCC_PLL2_NSEC 0U /*!< main PLL2 clock configuration secure/non-secure access */
+#define LL_RCC_PLL3_SEC RCC_SECCFGR_PLL3SEC /*!< PLL3 clock configuration security */
+#define LL_RCC_PLL3_NSEC 0U /*!< main PLL3 clock configuration secure/non-secure access */
+#define LL_RCC_CLK48M_SEC RCC_SECCFGR_CLK48MSEC /*!< 48MHz clock source selection security */
+#define LL_RCC_CLK48M_NSEC 0U /*!< 48MHz clock source selection secure/non-secure access */
+#define LL_RCC_HSI48_SEC RCC_SECCFGR_HSI48SEC /*!< HSI48 clock configuration security */
+#define LL_RCC_HSI48_NSEC 0U /*!< HSI48 clock configuration secure/non-secure access */
+#define LL_RCC_RESET_FLAGS_SEC RCC_SECCFGR_RMVFSEC /*!< Remove reset flag security */
+#define LL_RCC_RESET_FLAGS_NSEC 0U
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
+ * @{
+ */
+
+/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in RCC register
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in RCC register
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
+ * @{
+ */
+
+/**
+ * @brief Helper macro to calculate the PLL1CLK frequency on system domain
+ * @note ex: @ref __LL_RCC_CALC_PLL1CLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL1_GetDivider (),
+ * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetR ());
+ * @param __INPUTFREQ__ PLL1 Input frequency (based on MSI/HSE/HSI)
+ * @param __PLL1M__ parameter can be a value between 1 and 16
+ * @param __PLL1N__ parameter can be a value between 4 and 512
+ * @param __PLL1R__ parameter can be a value between 1 and 128
+ * @retval PLL1 clock frequency (in Hz)
+ */
+
+#define __LL_RCC_CALC_PLL1CLK_FREQ(__INPUTFREQ__, __PLL1M__, __PLL1N__, __PLL1R__) ((((__INPUTFREQ__) /(__PLL1M__)) * \
+ (__PLL1N__)) / (__PLL1R__))
+
+/**
+ * @brief Helper macro to calculate the PLL1CLK frequency used on SAI domain
+ * @note ex: @ref __LL_RCC_CALC_PLL1CLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL1_GetDivider (),
+ * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetP ());
+ * @param __INPUTFREQ__ PLL1 Input frequency (based on MSI/HSE/HSI)
+ * @param __PLL1M__ parameter can be a value between 1 and 16
+ * @param __PLL1N__ parameter can be a value between 4 and 512
+ * @param __PLL1P__ parameter can be a value between 2 and 128
+ * @retval PLL1 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLL1CLK_SAI_FREQ(__INPUTFREQ__, __PLL1M__, __PLL1N__, __PLL1P__) ((((__INPUTFREQ__) \
+ /(__PLL1M__)) * (__PLL1N__)) / (__PLL1P__))
+
+/**
+ * @brief Helper macro to calculate the PLL1CLK frequency used on 48M domain
+ * @note ex: @ref __LL_RCC_CALC_PLL1CLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL1_GetDivider (),
+ * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetQ ());
+ * @param __INPUTFREQ__ PLL1 Input frequency (based on MSI/HSE/HSI)
+ * @param __PLL1M__ parameter can be a value between 1 and 16
+ * @param __PLL1N__ parameter can be a value between 4 and 512
+ * @param __PLL1Q__ parameter can be a value between 1 and 128
+ * @retval PLL clock frequency (in Hz)
+ */
+
+#define __LL_RCC_CALC_PLL1CLK_48M_FREQ(__INPUTFREQ__, __PLL1M__, __PLL1N__, __PLL1Q__) ((((__INPUTFREQ__) \
+ /(__PLL1M__)) * (__PLL1N__)) / (__PLL1Q__))
+
+/**
+ * @brief Helper macro to calculate the PLL2 frequency used for SAI domain
+ * @note ex: @ref __LL_RCC_CALC_PLL2CLK_SAI_FREQ (HSE_ALUE,@ref LL_RCC_PLL2_GetDivider (),
+ * @ref LL_RCC_PLL2_GetN (), @ref LL_RCC_PLL2_GetP ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
+ * @param __PLL2M__ parameter can be a value between 1 and 16
+ * @param __PLL2N__ parameter can be a value between 4 and 512
+ * @param __PLL2P__ parameter can be a value between 2 and 128
+ * @retval PLL2 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLL2CLK_SAI_FREQ(__INPUTFREQ__, __PLL2M__, __PLL2N__, __PLL2P__) ((((__INPUTFREQ__) \
+ /(__PLL2M__)) * (__PLL2N__)) / (__PLL2P__))
+
+/**
+ * @brief Helper macro to calculate the PLL2 frequency used on 48M domain
+ * @note ex: @ref __LL_RCC_CALC_PLL2CLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL2_GetDivider (),
+ * @ref LL_RCC_PLL2_GetN (), @ref LL_RCC_PLL2_GetQ ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
+ * @param __PLL2M__ parameter can be a value between 1 and 16
+ * @param __PLL2N__ parameter can be a value between 4 and 512
+ * @param __PLL2Q__ parameter can be a value between 1 and 128
+ * @retval PLL2 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLL2CLK_48M_FREQ(__INPUTFREQ__, __PLL2M__, __PLL2N__, __PLL2Q__) ((((__INPUTFREQ__) \
+ /(__PLL2M__)) * (__PLL2N__)) / (__PLL2Q__))
+
+/**
+ * @brief Helper macro to calculate the PLL2 frequency used on ADC domain
+ * @note ex: @ref __LL_RCC_CALC_PLL2CLK_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL2_GetDivider (),
+ * @ref LL_RCC_PLL2_GetN (), @ref LL_RCC_PLL2_GetR ());
+ * @param __INPUTFREQ__ PLL2 Input frequency (based on MSI/HSE/HSI)
+ * @param __PLL2M__ parameter can be a value between 1 and 16
+ * @param __PLL2N__ parameter can be a value between 4 and 512
+ * @param __PLL2R__ parameter can be a value between 1 and 128
+ * @retval PLL2 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLL2CLK_ADC_FREQ(__INPUTFREQ__, __PLL2M__, __PLL2N__, __PLL2R__) ((((__INPUTFREQ__) \
+ /(__PLL2M__)) * (__PLL2N__)) / (__PLL2R__))
+
+/**
+ * @brief Helper macro to calculate the PLL3 frequency used for SAI domain
+ * @note ex: @ref __LL_RCC_CALC_PLL3CLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL3_GetDivider (),
+ * @ref LL_RCC_PLL3_GetN (), @ref LL_RCC_PLL3_GetP ());
+ * @param __INPUTFREQ__ PLL3 Input frequency (based on MSI/HSE/HSI)
+ * @param __PLL3M__ parameter can be a value between 1 and 16
+ * @param __PLL3N__ parameter can be a value between 4 and 512
+ * @param __PLL3P__ parameter can be a value between 2 and 128
+ * @retval PLL3 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLL3CLK_SAI_FREQ(__INPUTFREQ__, __PLL3M__, __PLL3N__, __PLL3P__)((((__INPUTFREQ__) \
+ /(__PLL3M__)) * (__PLL3N__)) / (__PLL3P__))
+
+/**
+ * @brief Helper macro to calculate the PLL2 frequency used on 48M domain
+ * @note ex: @ref __LL_RCC_CALC_PLL3CLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL3_GetDivider (),
+ * @ref LL_RCC_PLL3_GetN (), @ref LL_RCC_PLL3_GetQ ());
+ * @param __INPUTFREQ__ PLL3 Input frequency (based on MSI/HSE/HSI)
+ * @param __PLL3M__ parameter can be a value between 1 and 16
+ * @param __PLL3N__ parameter can be a value between 4 and 512
+ * @param __PLL3Q__ parameter can be a value between 1 and 128
+ * @retval PLL3 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLL3CLK_48M_FREQ(__INPUTFREQ__, __PLL3M__, __PLL3N__, __PLL3Q__) ((((__INPUTFREQ__) \
+ /(__PLL3M__)) * (__PLL3N__)) / (__PLL3Q__))
+
+/**
+ * @brief Helper macro to calculate the HCLK frequency
+ * @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
+ * @param __AHBPRESCALER__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SYSCLK_DIV_1
+ * @arg @ref LL_RCC_SYSCLK_DIV_2
+ * @arg @ref LL_RCC_SYSCLK_DIV_4
+ * @arg @ref LL_RCC_SYSCLK_DIV_8
+ * @arg @ref LL_RCC_SYSCLK_DIV_16
+ * @arg @ref LL_RCC_SYSCLK_DIV_64
+ * @arg @ref LL_RCC_SYSCLK_DIV_128
+ * @arg @ref LL_RCC_SYSCLK_DIV_256
+ * @arg @ref LL_RCC_SYSCLK_DIV_512
+ * @retval HCLK clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> \
+ AHBPrescTable[((__AHBPRESCALER__)& RCC_CFGR2_HPRE) \
+ >> RCC_CFGR2_HPRE_Pos])
+
+/**
+ * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
+ * @param __HCLKFREQ__ HCLK frequency
+ * @param __APB1PRESCALER__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_APB1_DIV_1
+ * @arg @ref LL_RCC_APB1_DIV_2
+ * @arg @ref LL_RCC_APB1_DIV_4
+ * @arg @ref LL_RCC_APB1_DIV_8
+ * @arg @ref LL_RCC_APB1_DIV_16
+ * @retval PCLK1 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> \
+ (APBPrescTable[((__APB1PRESCALER__)& \
+ RCC_CFGR2_PPRE1) >> RCC_CFGR2_PPRE1_Pos]))
+
+/**
+ * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
+ * @param __HCLKFREQ__ HCLK frequency
+ * @param __APB2PRESCALER__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_APB2_DIV_1
+ * @arg @ref LL_RCC_APB2_DIV_2
+ * @arg @ref LL_RCC_APB2_DIV_4
+ * @arg @ref LL_RCC_APB2_DIV_8
+ * @arg @ref LL_RCC_APB2_DIV_16
+ * @retval PCLK2 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >>\
+ APBPrescTable[(__APB2PRESCALER__) >> \
+ RCC_CFGR2_PPRE2_Pos])
+
+/**
+ * @brief Helper macro to calculate the PCLK3 frequency (ABP3)
+ * @param __HCLKFREQ__ HCLK frequency
+ * @param __APB3PRESCALER__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_APB3_DIV_1
+ * @arg @ref LL_RCC_APB3_DIV_2
+ * @arg @ref LL_RCC_APB3_DIV_4
+ * @arg @ref LL_RCC_APB3_DIV_8
+ * @arg @ref LL_RCC_APB3_DIV_16
+ * @retval PCLK3 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> \
+ APBPrescTable[(__APB3PRESCALER__) >> \
+ RCC_CFGR3_PPRE3_Pos])
+
+/**
+ * @brief Helper macro to calculate the MSIS frequency (in Hz)
+ * @note __MSISSEL__ can be retrieved thanks to function LL_RCC_MSI_IsEnabledRangeSelect()
+ * @note if __MSISSEL__ is equal to LL_RCC_MSIRANGESEL_STANDBY,
+ * __MSISRANGE__can be retrieved by LL_RCC_MSI_GetRangeAfterStandby()
+ * else by LL_RCC_MSI_GetRange()
+ * ex: __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ * (LL_RCC_MSI_IsEnabledRangeSelect()?
+ * LL_RCC_MSI_GetRange():
+ * LL_RCC_MSI_GetRangeAfterStandby()))
+ * @param __MSISSEL__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_MSIRANGESEL_STANDBY
+ * @arg @ref LL_RCC_MSIRANGESEL_RUN
+ * @param __MSISRANGE__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_MSISRANGE_0
+ * @arg @ref LL_RCC_MSISRANGE_1
+ * @arg @ref LL_RCC_MSISRANGE_2
+ * @arg @ref LL_RCC_MSISRANGE_3
+ * @arg @ref LL_RCC_MSISRANGE_4
+ * @arg @ref LL_RCC_MSISRANGE_5
+ * @arg @ref LL_RCC_MSISRANGE_6
+ * @arg @ref LL_RCC_MSISRANGE_7
+ * @arg @ref LL_RCC_MSISRANGE_8
+ * @arg @ref LL_RCC_MSISRANGE_9
+ * @arg @ref LL_RCC_MSISRANGE_10
+ * @arg @ref LL_RCC_MSISRANGE_11
+ * @arg @ref LL_RCC_MSISRANGE_12
+ * @arg @ref LL_RCC_MSISRANGE_13
+ * @arg @ref LL_RCC_MSISRANGE_14
+ * @arg @ref LL_RCC_MSISRANGE_15
+ * @retval MSI clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_MSIS_FREQ(__MSISSEL__, __MSISRANGE__) (((__MSISSEL__) == LL_RCC_MSIRANGESEL_RUN) ? \
+ (MSIRangeTable[((__MSISRANGE__) >> 28U) & 0x0FU]) : \
+ (MSIRangeTable[((__MSISRANGE__) >> 12U) & 0x0FU]))
+
+
+/**
+ * @brief Helper macro to calculate the MSIK frequency (in Hz)
+ * @note __MSIKSEL__ can be retrieved thanks to function LL_RCC_MSIK_IsEnabledRangeSelect()
+ * @note if __MSIKSEL__ is equal to LL_RCC_MSIKRANGESEL_STANDBY,
+ * __MSIKRANGE__can be retrieved by LL_RCC_MSIK_GetRangeAfterStandby()
+ * else by LL_RCC_MSIK_GetRange()
+ * ex: __LL_RCC_CALC_MSIK_FREQ(LL_RCC_MSIK_IsEnabledRangeSelect(),
+ * (LL_RCC_MSIK_IsEnabledRangeSelect()?
+ * LL_RCC_MSIK_GetRange():
+ * LL_RCC_MSIK_GetRangeAfterStandby()))
+ * @param __MSIKSEL__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_MSIRANGESEL_STANDBY
+ * @arg @ref LL_RCC_MSIRANGESEL_RUN
+ * @param __MSIKRANGE__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_MSIKRANGE_0
+ * @arg @ref LL_RCC_MSIKRANGE_1
+ * @arg @ref LL_RCC_MSIKRANGE_2
+ * @arg @ref LL_RCC_MSIKRANGE_3
+ * @arg @ref LL_RCC_MSIKRANGE_4
+ * @arg @ref LL_RCC_MSIKRANGE_5
+ * @arg @ref LL_RCC_MSIKRANGE_6
+ * @arg @ref LL_RCC_MSIKRANGE_7
+ * @arg @ref LL_RCC_MSIKRANGE_8
+ * @arg @ref LL_RCC_MSIKRANGE_9
+ * @arg @ref LL_RCC_MSIKRANGE_10
+ * @arg @ref LL_RCC_MSIKRANGE_11
+ * @arg @ref LL_RCC_MSIKRANGE_12
+ * @arg @ref LL_RCC_MSIKRANGE_13
+ * @arg @ref LL_RCC_MSIKRANGE_14
+ * @arg @ref LL_RCC_MSIKRANGE_15
+ * @retval MSIK clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_MSIK_FREQ(__MSIKSEL__, __MSIKRANGE__) (((__MSIKSEL__) == LL_RCC_MSIRANGESEL_RUN) ? \
+ (MSIRangeTable[((__MSIKRANGE__) >> 24U) & 0x0FU]) : \
+ (MSIRangeTable[((__MSIKRANGE__) >> 8U) & 0x0FU]))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
+ * @{
+ */
+
+/** @defgroup RCC_LL_EF_HSE HSE
+ * @{
+ */
+
+/**
+ * @brief Enable the Clock Security System.
+ * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_CSSON);
+}
+
+/**
+ * @brief Enable HSE external oscillator (HSE Bypass)
+ * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_HSEBYP);
+}
+
+/**
+ * @brief Disable HSE external oscillator (HSE Bypass)
+ * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
+}
+
+/**
+ * @brief Enable HSE crystal oscillator (HSE ON)
+ * @rmtoll CR HSEON LL_RCC_HSE_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_Enable(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_HSEON);
+}
+
+/**
+ * @brief Disable HSE crystal oscillator (HSE ON)
+ * @rmtoll CR HSEON LL_RCC_HSE_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_Disable(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
+}
+
+/**
+ * @brief Check if HSE oscillator Ready
+ * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
+{
+ return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == RCC_CR_HSERDY) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set external HSE clock mode
+ * @note This bit can be written only if the HSE oscillator is disabled
+ * @rmtoll CR HSEEXT LL_RCC_HSE_SetClockMode
+ * @param HSEMode This parameter can be one of the following values:
+ * @arg @ref LL_RCC_HSE_ANALOG_MODE
+ * @arg @ref LL_RCC_HSE_DIGITAL_MODE
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_SetClockMode(uint32_t HSEMode)
+{
+ MODIFY_REG(RCC->CR, RCC_CR_HSEEXT, HSEMode);
+}
+
+/**
+ * @brief Get Externel HSE clock mode
+ * @rmtoll CR HSEEXT LL_RCC_HSE_GetClockMode
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_HSE_ANALOG_MODE
+ * @arg @ref LL_RCC_HSE_DIGITAL_MODE
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSE_GetClockMode(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSEEXT));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_HSI HSI
+ * @{
+ */
+
+/**
+ * @brief Enable HSI even in stop mode
+ * @note HSI oscillator is forced ON even in Stop mode
+ * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_HSIKERON);
+}
+
+/**
+ * @brief Disable HSI in stop mode
+ * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
+}
+
+/**
+ * @brief Check if HSI is enabled in stop mode
+ * @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void)
+{
+ return ((READ_BIT(RCC->CR, RCC_CR_HSIKERON) == RCC_CR_HSIKERON) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable HSI oscillator
+ * @rmtoll CR HSION LL_RCC_HSI_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSI_Enable(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_HSION);
+}
+
+/**
+ * @brief Disable HSI oscillator
+ * @rmtoll CR HSION LL_RCC_HSI_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSI_Disable(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_HSION);
+}
+
+/**
+ * @brief Check if HSI clock is ready
+ * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
+{
+ return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RCC_CR_HSIRDY) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get HSI Calibration value
+ * @note When HSITRIM is written, HSICAL is updated with the sum of
+ * HSITRIM and the factory trim value
+ * @rmtoll ICSCR3 HSICAL LL_RCC_HSI_GetCalibration
+ * @retval Between Min_Data = 0 and Max_Data = 127
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
+{
+ return (uint32_t)(READ_BIT(RCC->ICSCR3, RCC_ICSCR3_HSICAL) >> RCC_ICSCR3_HSICAL_Pos);
+}
+
+/**
+ * @brief Set HSI Calibration trimming
+ * @note user-programmable trimming value that is added to the HSICAL
+ * @note Default value is 64, which, when added to the HSICAL value,
+ * should trim the HSI to 16 MHz +/- 1 %
+ * @rmtoll ICSCR3 HSITRIM LL_RCC_HSI_SetCalibTrimming
+ * @param Value Between Min_Data = 0 and Max_Data = 127
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
+{
+ MODIFY_REG(RCC->ICSCR3, RCC_ICSCR3_HSITRIM, Value << RCC_ICSCR3_HSITRIM_Pos);
+}
+
+/**
+ * @brief Get HSI Calibration trimming
+ * @rmtoll ICSC3R HSITRIM LL_RCC_HSI_GetCalibTrimming
+ * @retval Between Min_Data = 0 and Max_Data = 127
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
+{
+ return (uint32_t)(READ_BIT(RCC->ICSCR3, RCC_ICSCR3_HSITRIM) >> RCC_ICSCR3_HSITRIM_Pos);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_HSI48 HSI48
+ * @{
+ */
+
+/**
+ * @brief Enable HSI48
+ * @rmtoll CR HSI48ON LL_RCC_HSI48_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSI48_Enable(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_HSI48ON);
+}
+
+/**
+ * @brief Disable HSI48
+ * @rmtoll CR HSI48ON LL_RCC_HSI48_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSI48_Disable(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);
+}
+
+/**
+ * @brief Check if HSI48 oscillator Ready
+ * @rmtoll CR HSI48RDY LL_RCC_HSI48_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
+{
+ return ((READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == RCC_CR_HSI48RDY) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get HSI48 Calibration value
+ * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration
+ * @retval Between Min_Data = 0x00 and Max_Data = 0x1FF
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_LSE LSE
+ * @{
+ */
+
+/**
+ * @brief Enable Low Speed External (LSE) crystal.
+ * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_Enable(void)
+{
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+}
+
+/**
+ * @brief Disable Low Speed External (LSE) crystal.
+ * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_Disable(void)
+{
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+}
+
+/**
+ * @brief Enable external clock source (LSE bypass).
+ * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
+{
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
+}
+
+/**
+ * @brief Disable external clock source (LSE bypass).
+ * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
+{
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
+}
+
+/**
+ * @brief Set LSE oscillator drive capability
+ * @note The oscillator is in Xtal mode when it is not in bypass mode.
+ * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
+ * @param LSEDrive This parameter can be one of the following values:
+ * @arg @ref LL_RCC_LSEDRIVE_LOW
+ * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
+ * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
+ * @arg @ref LL_RCC_LSEDRIVE_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
+{
+ MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
+}
+
+/**
+ * @brief Get LSE oscillator drive capability
+ * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_LSEDRIVE_LOW
+ * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
+ * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
+ * @arg @ref LL_RCC_LSEDRIVE_HIGH
+ */
+__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
+{
+ return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
+}
+
+/**
+ * @brief Enable Clock security system on LSE.
+ * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
+{
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
+}
+
+/**
+ * @brief Disable Clock security system on LSE.
+ * @note Clock security system can be disabled only after a LSE
+ * failure detection. In that case it MUST be disabled by software.
+ * @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
+{
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
+}
+
+/**
+ * @brief Check if LSE oscillator Ready
+ * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
+{
+ return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RCC_BDCR_LSERDY) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable LSE oscillator propagation for system clock
+ * @rmtoll BDCR LSESYSEN LL_RCC_LSE_EnablePropagation
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_EnablePropagation(void)
+{
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN);
+}
+
+/**
+ * @brief Check if LSESYS oscillator Ready
+ * @rmtoll BDCR LSESYSRDY LL_RCC_LSESYS_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_LSESYS_IsReady(void)
+{
+ return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) == RCC_BDCR_LSESYSRDY) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Disable LSE oscillator propagation for system clock
+ * @rmtoll BDCR LSESYSEN LL_RCC_LSE_DisablePropagation
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_DisablePropagation(void)
+{
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN);
+}
+
+/**
+ * @brief Check if LSE oscillator propagation for system clock Ready
+ * @rmtoll BDCR LSESYSRDY LL_RCC_LSE_IsPropagationReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_LSE_IsPropagationReady(void)
+{
+ return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) == RCC_BDCR_LSESYSRDY) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if CSS on LSE failure Detection
+ * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
+{
+ return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == RCC_BDCR_LSECSSD) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_LSI LSI
+ * @{
+ */
+
+/**
+ * @brief Enable LSI Oscillator
+ * @rmtoll BDCR LSION LL_RCC_LSI_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSI_Enable(void)
+{
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSION);
+}
+
+/**
+ * @brief Disable LSI Oscillator
+ * @rmtoll BDCR LSION LL_RCC_LSI_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSI_Disable(void)
+{
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSION);
+}
+
+/**
+ * @brief Check if LSI is Ready
+ * @rmtoll BDCR LSIRDY LL_RCC_LSI_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
+{
+ return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSIRDY) == RCC_BDCR_LSIRDY) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set LSI prescaler
+ * @rmtoll BDCR LSIPREDIV LL_RCC_LSI_SetPrescaler
+ * @param LSIPrescaler This parameter can be one of the following values:
+ * @arg @ref LL_RCC_LSI_DIV_1
+ * @arg @ref LL_RCC_LSI_DIV_128
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSI_SetPrescaler(uint32_t LSIPrescaler)
+{
+ MODIFY_REG(RCC->BDCR, RCC_BDCR_LSIPREDIV, LSIPrescaler);
+}
+
+/**
+ * @brief Get LSI prescaler
+ * @rmtoll BDCR LSIPREDIV LL_RCC_LSI_GetPrescaler
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_LSI_DIV_1
+ * @arg @ref LL_RCC_LSI_DIV_128
+ */
+__STATIC_INLINE uint32_t LL_RCC_LSI_GetPrescaler(void)
+{
+ return (READ_BIT(RCC->BDCR, RCC_BDCR_LSIPREDIV));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_MSIK MSIK
+ * @{
+ */
+
+/**
+ * @brief Enable MSIK oscillator
+ * @rmtoll CR MSIKON LL_RCC_MSIK_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_MSIK_Enable(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_MSIKON);
+}
+
+/**
+ * @brief Disable MSIK oscillator
+ * @rmtoll CR MSIKON LL_RCC_MSIK_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_MSIK_Disable(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_MSIKON);
+}
+
+/**
+ * @brief Check if MSIK oscillator Ready
+ * @rmtoll CR MSIKRDY LL_RCC_MSIK_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_MSIK_IsReady(void)
+{
+ return ((READ_BIT(RCC->CR, RCC_CR_MSIKRDY) == RCC_CR_MSIKRDY) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_SHSI SHSI
+ * @{
+ */
+
+/**
+ * @brief Enable SHSI oscillator
+ * @rmtoll CR SHSION LL_RCC_SHSI_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SHSI_Enable(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_SHSION);
+}
+
+/**
+ * @brief Disable SHSI oscillator
+ * @rmtoll CR SHSION LL_RCC_SHSI_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SHSI_Disable(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_SHSION);
+}
+
+/**
+ * @brief Check if SHSI oscillator Ready
+ * @rmtoll CR SHSIRDY LL_RCC_SHSI_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_SHSI_IsReady(void)
+{
+ return ((READ_BIT(RCC->CR, RCC_CR_SHSIRDY) == RCC_CR_SHSIRDY) ? 1UL : 0UL);
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_MSI MSI
+ * @{
+ */
+
+/**
+ * @brief Enable MSIS oscillator
+ * @rmtoll CR MSISON LL_RCC_MSIS_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_MSIS_Enable(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_MSISON);
+}
+
+/**
+ * @brief Disable MSIS oscillator
+ * @rmtoll CR MSISON LL_RCC_MSIS_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_MSIS_Disable(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_MSISON);
+}
+
+/**
+ * @brief Check if MSIS oscillator Ready
+ * @rmtoll CR MSISRDY LL_RCC_MSIS_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_MSIS_IsReady(void)
+{
+ return ((READ_BIT(RCC->CR, RCC_CR_MSISRDY) == RCC_CR_MSISRDY) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable MSI PLL-mode (Hardware auto calibration with LSE)
+ * @note MSIPLLEN must be enabled after LSE is enabled (LSEON enabled)
+ * and ready (LSERDY set by hardware)
+ * @note hardware protection to avoid enabling MSIPLLEN if LSE is not
+ * ready
+ * @rmtoll CR MSIPLLEN LL_RCC_MSI_EnablePLLMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_MSI_EnablePLLMode(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_MSIPLLEN);
+}
+
+/**
+ * @brief Disable MSI-PLL mode
+ * @note cleared by hardware when LSE is disabled (LSEON = 0) or when
+ * the Clock Security System on LSE detects a LSE failure
+ * @rmtoll CR MSIPLLEN LL_RCC_MSI_DisablePLLMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_MSI_DisablePLLMode(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN);
+}
+
+/**
+ * @brief Set clock source in PLL mode
+ * @rmtoll CR MSIPLLSEL LL_RCC_SetMSIPLLMode
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLMODE_MSIS
+ * @arg @ref LL_RCC_PLLMODE_MSIK
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetMSIPLLMode(uint32_t Source)
+{
+ MODIFY_REG(RCC->CR, RCC_CR_MSIPLLSEL, Source);
+}
+
+/**
+ * @brief Get Clock source in PLL Mode
+ * @rmtoll CR MSIPLLSEL LL_RCC_GetMSIPLLMode
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLMODE_MSIS
+ * @arg @ref LL_RCC_PLLMODE_MSIK
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetMSIPLLMode(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIPLLSEL));
+}
+
+/**
+ * @brief Enable MSI fast mode
+ * @rmtoll CR MSIPLLFAST LL_RCC_Enable_MSIPLLFAST
+ * @note This bit is used only if PLL mode is selected.
+ */
+__STATIC_INLINE void LL_RCC_Enable_MSIPLLFAST(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_MSIPLLFAST);
+}
+
+/**
+ * @brief Disable MSI fast mode
+ * @rmtoll CR MSIPLLFAST LL_RCC_Disable_MSIPLLFAST
+ * @note This bit is used only if PLL mode is selected.
+ */
+__STATIC_INLINE void LL_RCC_Disable_MSIPLLFAST(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLFAST);
+}
+
+/**
+ * @brief Check if MSI PLL Fast Mode is enable
+ * @rmtoll CR MSIPLLFAST LL_RCC_MSI_IsEnabledMSIPLLFAST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledMSIPLLFAST(void)
+{
+ return ((READ_BIT(RCC->CR, RCC_CR_MSIPLLFAST) == RCC_CR_MSIPLLFAST) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set MSI Bias mode
+ * @rmtoll ICSCR1 MSIBIAS LL_RCC_MSI_SetMSIBiasMode
+ * @param BiasMode This parameter can be one of the following values:
+ * @arg @ref LL_RCC_MSIBIASMODE_CONTINUOUS
+ * @arg @ref LL_RCC_MSIBIASMODE_SAMPLING
+
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_MSI_SetMSIBiasMode(uint32_t BiasMode)
+{
+ MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSIBIAS, BiasMode);
+}
+
+/**
+ * @brief Get MSI Bias mode
+ * @rmtoll ICSCR1 MSIBIAS LL_RCC_MSI_GetMSIBiasMode
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_MSIBIASMODE_CONTINUOUS
+ * @arg @ref LL_RCC_MSIBIASMODE_SAMPLING
+
+ */
+__STATIC_INLINE uint32_t LL_RCC_MSI_GetMSIBiasMode(void)
+{
+ return (uint32_t)(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIBIAS));
+}
+
+/**
+ * @brief Enable MSIK even in stop mode
+ * @note MSIK oscillator is forced ON even in Stop mode
+ * @rmtoll CR MSIKERON LL_RCC_MSIK_EnableInStopMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_MSIK_EnableInStopMode(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_MSIKERON);
+}
+
+/**
+ * @brief Disable MSIK in stop mode
+ * @rmtoll CR MSIKERON LL_RCC_MSIK_DisableInStopMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_MSIK_DisableInStopMode(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_MSIKERON);
+}
+
+/**
+ * @brief Check if MSIK is enabled in stop mode
+ * @rmtoll CR MSIKERON LL_RCC_MSIK_IsEnabledInStopMode
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_MSIK_IsEnabledInStopMode(void)
+{
+ return ((READ_BIT(RCC->CR, RCC_CR_MSIKERON) == RCC_CR_MSIKERON) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable MSI clock range selection with MSIRANGE register
+ * @note Write 0 has no effect. After a standby or a reset
+ * MSIRGSEL is at 0 and the MSI range value is provided by
+ * MSISRANGE
+ * @rmtoll ICSCR1 MSIRGSEL LL_RCC_MSI_EnableRangeSelection
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_MSI_EnableRangeSelection(void)
+{
+ SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL);
+}
+
+/**
+ * @brief Check if MSI clock range is selected with MSIRANGE register
+ * @rmtoll ICSCR1 MSIRGSEL LL_RCC_MSI_IsEnabledRangeSelect
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledRangeSelect(void)
+{
+ return ((READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL) == RCC_ICSCR1_MSIRGSEL) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure the Internal Multi Speed oscillator (MSI) clock range in run mode.
+ * @rmtoll ICSCR1 MSISRANGE LL_RCC_MSIS_SetRange
+ * @param Range This parameter can be one of the following values:
+ * @arg @ref LL_RCC_MSISRANGE_0
+ * @arg @ref LL_RCC_MSISRANGE_1
+ * @arg @ref LL_RCC_MSISRANGE_2
+ * @arg @ref LL_RCC_MSISRANGE_3
+ * @arg @ref LL_RCC_MSISRANGE_4
+ * @arg @ref LL_RCC_MSISRANGE_5
+ * @arg @ref LL_RCC_MSISRANGE_6
+ * @arg @ref LL_RCC_MSISRANGE_7
+ * @arg @ref LL_RCC_MSISRANGE_8
+ * @arg @ref LL_RCC_MSISRANGE_9
+ * @arg @ref LL_RCC_MSISRANGE_10
+ * @arg @ref LL_RCC_MSISRANGE_11
+ * @arg @ref LL_RCC_MSISRANGE_12
+ * @arg @ref LL_RCC_MSISRANGE_13
+ * @arg @ref LL_RCC_MSISRANGE_14
+ * @arg @ref LL_RCC_MSISRANGE_15
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_MSIS_SetRange(uint32_t Range)
+{
+ MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSISRANGE, Range);
+}
+
+/**
+ * @brief Get the Internal Multi Speed oscillator (MSI) clock range in run mode.
+ * @rmtoll ICSCR1 MSISRANGE LL_RCC_MSIS_GetRange
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_MSISRANGE_0
+ * @arg @ref LL_RCC_MSISRANGE_1
+ * @arg @ref LL_RCC_MSISRANGE_2
+ * @arg @ref LL_RCC_MSISRANGE_3
+ * @arg @ref LL_RCC_MSISRANGE_4
+ * @arg @ref LL_RCC_MSISRANGE_5
+ * @arg @ref LL_RCC_MSISRANGE_6
+ * @arg @ref LL_RCC_MSISRANGE_7
+ * @arg @ref LL_RCC_MSISRANGE_8
+ * @arg @ref LL_RCC_MSISRANGE_9
+ * @arg @ref LL_RCC_MSISRANGE_10
+ * @arg @ref LL_RCC_MSISRANGE_11
+ * @arg @ref LL_RCC_MSISRANGE_12
+ * @arg @ref LL_RCC_MSISRANGE_13
+ * @arg @ref LL_RCC_MSISRANGE_14
+ * @arg @ref LL_RCC_MSISRANGE_15
+ */
+__STATIC_INLINE uint32_t LL_RCC_MSIS_GetRange(void)
+{
+ return (uint32_t)(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSISRANGE));
+}
+
+/**
+ * @brief Configure MSIS range used after standby
+ * @rmtoll CSR MSISSRANGE LL_RCC_MSIS_SetRangeAfterStandby
+ * @param Range This parameter can be one of the following values:
+ * @arg @ref LL_RCC_MSISRANGE_4
+ * @arg @ref LL_RCC_MSISRANGE_5
+ * @arg @ref LL_RCC_MSISRANGE_6
+ * @arg @ref LL_RCC_MSISRANGE_7
+ * @arg @ref LL_RCC_MSISRANGE_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_MSIS_SetRangeAfterStandby(uint32_t Range)
+{
+ MODIFY_REG(RCC->CSR, RCC_CSR_MSISSRANGE, Range);
+}
+
+/**
+ * @brief Get MSIS range used after standby
+ * @rmtoll CSR MSISSRANGE LL_RCC_MSIS_GetRangeAfterStandby
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_MSISSRANGE_4
+ * @arg @ref LL_RCC_MSISSRANGE_5
+ * @arg @ref LL_RCC_MSISSRANGE_6
+ * @arg @ref LL_RCC_MSISSRANGE_7
+ * @arg @ref LL_RCC_MSISSRANGE_8
+ */
+__STATIC_INLINE uint32_t LL_RCC_MSIS_GetRangeAfterStandby(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISSRANGE));
+}
+
+/**
+ * @brief Set MSI OSCILLATORx Calibration trimming
+ * @note user-programmable trimming value that is added to the MSICALx
+ * @rmtoll ICSCR2 MSITRIMx LL_RCC_MSI_SetCalibTrimming
+ * @param Value Between Min_Data = 0 and Max_Data = 31
+ * @param Oscillator This parameter can be one of the following values:
+ * @arg @ref LL_RCC_MSI_OSCILLATOR_0
+ * @arg @ref LL_RCC_MSI_OSCILLATOR_1
+ * @arg @ref LL_RCC_MSI_OSCILLATOR_2
+ * @arg @ref LL_RCC_MSI_OSCILLATOR_3
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value, uint32_t Oscillator)
+{
+ MODIFY_REG(RCC->ICSCR2, (RCC_ICSCR2_MSITRIM0 >> Oscillator), Value << (RCC_ICSCR2_MSITRIM0_Pos - Oscillator));
+}
+
+/**
+ * @brief Get MSI OSCILLATORx Calibration trimming
+ * @rmtoll ICSCR2 MSITRIMx LL_RCC_MSI_GetCalibTrimming
+ * @retval Between 0 and 31
+ * @param Oscillator This parameter can be one of the following values:
+ * @arg @ref LL_RCC_MSI_OSCILLATOR_0
+ * @arg @ref LL_RCC_MSI_OSCILLATOR_1
+ * @arg @ref LL_RCC_MSI_OSCILLATOR_2
+ * @arg @ref LL_RCC_MSI_OSCILLATOR_3
+ */
+__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(uint32_t Oscillator)
+{
+ return (uint32_t)(READ_BIT(RCC->ICSCR2,
+ (RCC_ICSCR2_MSITRIM0 >> Oscillator)) >> (RCC_ICSCR2_MSITRIM0_Pos - Oscillator));
+}
+
+/**
+ * @brief Get MSI OSCILLATORx Calibration value
+ * @note When MSITRIMx is written, MSICALx is updated with the sum of
+ * MSITRIMx and the factory trim value
+ * @rmtoll ICSCR1 MSICALx LL_RCC_MSI_GetCalibration
+ * @param Oscillator This parameter can be one of the following values:
+ * @arg @ref LL_RCC_MSI_OSCILLATOR_0
+ * @arg @ref LL_RCC_MSI_OSCILLATOR_1
+ * @arg @ref LL_RCC_MSI_OSCILLATOR_2
+ * @arg @ref LL_RCC_MSI_OSCILLATOR_3
+ * @retval Between Min_Data = 0 and Max_Data = 31
+ */
+__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(uint32_t Oscillator)
+{
+ return (uint32_t)(READ_BIT(RCC->ICSCR1, (RCC_ICSCR1_MSICAL0 >> Oscillator)) >> (RCC_ICSCR1_MSICAL0_Pos - Oscillator));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_MSIK MSIK
+ * @{
+ */
+
+/**
+ * @brief Configure the Internal Multi Speed oscillator (MSIK) clock range in run mode.
+ * @rmtoll ICSCR1 MSIKRANGE LL_RCC_MSIK_SetRange
+ * @param Range This parameter can be one of the following values:
+ * @arg @ref LL_RCC_MSIKRANGE_0
+ * @arg @ref LL_RCC_MSIKRANGE_1
+ * @arg @ref LL_RCC_MSIKRANGE_2
+ * @arg @ref LL_RCC_MSIKRANGE_3
+ * @arg @ref LL_RCC_MSIKRANGE_4
+ * @arg @ref LL_RCC_MSIKRANGE_5
+ * @arg @ref LL_RCC_MSIKRANGE_6
+ * @arg @ref LL_RCC_MSIKRANGE_7
+ * @arg @ref LL_RCC_MSIKRANGE_8
+ * @arg @ref LL_RCC_MSIKRANGE_9
+ * @arg @ref LL_RCC_MSIKRANGE_10
+ * @arg @ref LL_RCC_MSIKRANGE_11
+ * @arg @ref LL_RCC_MSIKRANGE_12
+ * @arg @ref LL_RCC_MSIKRANGE_13
+ * @arg @ref LL_RCC_MSIKRANGE_14
+ * @arg @ref LL_RCC_MSIKRANGE_15
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_MSIK_SetRange(uint32_t Range)
+{
+ MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSIKRANGE, Range);
+}
+
+/**
+ * @brief Get the Internal Multi Speed oscillator (MSIK) clock range in run mode.
+ * @rmtoll ICSCR1 MSIKRANGE LL_RCC_MSIK_GetRange
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_MSIKRANGE_0
+ * @arg @ref LL_RCC_MSIKRANGE_1
+ * @arg @ref LL_RCC_MSIKRANGE_2
+ * @arg @ref LL_RCC_MSIKRANGE_3
+ * @arg @ref LL_RCC_MSIKRANGE_4
+ * @arg @ref LL_RCC_MSIKRANGE_5
+ * @arg @ref LL_RCC_MSIKRANGE_6
+ * @arg @ref LL_RCC_MSIKRANGE_7
+ * @arg @ref LL_RCC_MSIKRANGE_8
+ * @arg @ref LL_RCC_MSIKRANGE_9
+ * @arg @ref LL_RCC_MSIKRANGE_10
+ * @arg @ref LL_RCC_MSIKRANGE_11
+ * @arg @ref LL_RCC_MSIKRANGE_12
+ * @arg @ref LL_RCC_MSIKRANGE_13
+ * @arg @ref LL_RCC_MSIKRANGE_14
+ * @arg @ref LL_RCC_MSIKRANGE_15
+ */
+__STATIC_INLINE uint32_t LL_RCC_MSIK_GetRange(void)
+{
+ return (uint32_t)(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIKRANGE));
+}
+
+/**
+ * @brief Configure MSIK range used after standby
+ * @rmtoll CSR MSIKSRANGE LL_RCC_MSIK_SetRangeAfterStandby
+ * @param Range This parameter can be one of the following values:
+ * @arg @ref LL_RCC_MSIKSRANGE_4
+ * @arg @ref LL_RCC_MSIKSRANGE_5
+ * @arg @ref LL_RCC_MSIKSRANGE_6
+ * @arg @ref LL_RCC_MSIKSRANGE_7
+ * @arg @ref LL_RCC_MSIKSRANGE_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_MSIK_SetRangeAfterStandby(uint32_t Range)
+{
+ MODIFY_REG(RCC->CSR, RCC_CSR_MSIKSRANGE, Range);
+}
+
+/**
+ * @brief Get MSIK range used after standby
+ * @rmtoll CSR MSIKSRANGE LL_RCC_MSIK_GetRangeAfterStandby
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_MSIKSRANGE_4
+ * @arg @ref LL_RCC_MSIKSRANGE_5
+ * @arg @ref LL_RCC_MSIKSRANGE_6
+ * @arg @ref LL_RCC_MSIKSRANGE_7
+ * @arg @ref LL_RCC_MSIKSRANGE_8
+ */
+__STATIC_INLINE uint32_t LL_RCC_MSIK_GetRangeAfterStandby(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSIKSRANGE));
+}
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_LSCO LSCO
+ * @{
+ */
+
+/**
+ * @brief Enable Low speed clock
+ * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSCO_Enable(void)
+{
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
+}
+
+/**
+ * @brief Disable Low speed clock
+ * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSCO_Disable(void)
+{
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
+}
+
+/**
+ * @brief Configure Low speed clock selection
+ * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
+ * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
+{
+ MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source);
+}
+
+/**
+ * @brief Get Low speed clock selection
+ * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
+ * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
+ */
+__STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
+{
+ return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_System System
+ * @{
+ */
+
+/**
+ * @brief Configure the system clock source
+ * @rmtoll CFGR1 SW LL_RCC_SetSysClkSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_MSIS
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL1
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
+{
+ MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SW, Source);
+}
+
+/**
+ * @brief Get the system clock source
+ * @rmtoll CFGR1 SWS LL_RCC_GetSysClkSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSIS
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL1
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_SWS));
+}
+
+/**
+ * @brief Set AHB prescaler
+ * @rmtoll CFGR2 HPRE LL_RCC_SetAHBPrescaler
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SYSCLK_DIV_1
+ * @arg @ref LL_RCC_SYSCLK_DIV_2
+ * @arg @ref LL_RCC_SYSCLK_DIV_4
+ * @arg @ref LL_RCC_SYSCLK_DIV_8
+ * @arg @ref LL_RCC_SYSCLK_DIV_16
+ * @arg @ref LL_RCC_SYSCLK_DIV_64
+ * @arg @ref LL_RCC_SYSCLK_DIV_128
+ * @arg @ref LL_RCC_SYSCLK_DIV_256
+ * @arg @ref LL_RCC_SYSCLK_DIV_512
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
+{
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, Prescaler);
+}
+
+/**
+ * @brief Set Systick clock source
+ * @rmtoll CCIPR1 SYSTICKSEL LL_RCC_SetSystickClockSource
+ * @param SystickSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSI
+ * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetSystickClockSource(uint32_t SystickSource)
+{
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, SystickSource);
+}
+
+/**
+ * @brief Set APB1 prescaler
+ * @rmtoll CFGR2 PPRE1 LL_RCC_SetAPB1Prescaler
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_RCC_APB1_DIV_1
+ * @arg @ref LL_RCC_APB1_DIV_2
+ * @arg @ref LL_RCC_APB1_DIV_4
+ * @arg @ref LL_RCC_APB1_DIV_8
+ * @arg @ref LL_RCC_APB1_DIV_16
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
+{
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, Prescaler);
+}
+
+/**
+ * @brief Set APB2 prescaler
+ * @rmtoll CFGR2 PPRE2 LL_RCC_SetAPB2Prescaler
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_RCC_APB2_DIV_1
+ * @arg @ref LL_RCC_APB2_DIV_2
+ * @arg @ref LL_RCC_APB2_DIV_4
+ * @arg @ref LL_RCC_APB2_DIV_8
+ * @arg @ref LL_RCC_APB2_DIV_16
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
+{
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, Prescaler);
+}
+
+/**
+ * @brief Set APB3 prescaler
+ * @rmtoll CFGR3 PPRE3 LL_RCC_SetAPB3Prescaler
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_RCC_APB3_DIV_1
+ * @arg @ref LL_RCC_APB3_DIV_2
+ * @arg @ref LL_RCC_APB3_DIV_4
+ * @arg @ref LL_RCC_APB3_DIV_8
+ * @arg @ref LL_RCC_APB3_DIV_16
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetAPB3Prescaler(uint32_t Prescaler)
+{
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_PPRE3, Prescaler);
+}
+
+/**
+ * @brief Get AHB prescaler
+ * @rmtoll CFGR2 HPRE LL_RCC_GetAHBPrescaler
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_SYSCLK_DIV_1
+ * @arg @ref LL_RCC_SYSCLK_DIV_2
+ * @arg @ref LL_RCC_SYSCLK_DIV_4
+ * @arg @ref LL_RCC_SYSCLK_DIV_8
+ * @arg @ref LL_RCC_SYSCLK_DIV_16
+ * @arg @ref LL_RCC_SYSCLK_DIV_64
+ * @arg @ref LL_RCC_SYSCLK_DIV_128
+ * @arg @ref LL_RCC_SYSCLK_DIV_256
+ * @arg @ref LL_RCC_SYSCLK_DIV_512
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_HPRE));
+}
+
+/**
+ * @brief Get Sysctick clock source
+ * @rmtoll CCIPR1 SYSTICKSEL LL_RCC_SetSystickClockSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSI
+ * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetSystickClockSource(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL));
+}
+
+/**
+ * @brief Get APB1 prescaler
+ * @rmtoll CFGR2 PPRE1 LL_RCC_GetAPB1Prescaler
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_APB1_DIV_1
+ * @arg @ref LL_RCC_APB1_DIV_2
+ * @arg @ref LL_RCC_APB1_DIV_4
+ * @arg @ref LL_RCC_APB1_DIV_8
+ * @arg @ref LL_RCC_APB1_DIV_16
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE1));
+}
+
+/**
+ * @brief Get APB2 prescaler
+ * @rmtoll CFGR2 PPRE2 LL_RCC_GetAPB2Prescaler
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_APB2_DIV_1
+ * @arg @ref LL_RCC_APB2_DIV_2
+ * @arg @ref LL_RCC_APB2_DIV_4
+ * @arg @ref LL_RCC_APB2_DIV_8
+ * @arg @ref LL_RCC_APB2_DIV_16
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE2));
+}
+
+/**
+ * @brief Get APB3 prescaler
+ * @rmtoll CFGR3 PPRE3 LL_RCC_GetAPB2Prescaler
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_APB3_DIV_1
+ * @arg @ref LL_RCC_APB3_DIV_2
+ * @arg @ref LL_RCC_APB3_DIV_4
+ * @arg @ref LL_RCC_APB3_DIV_8
+ * @arg @ref LL_RCC_APB3_DIV_16
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB3Prescaler(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_PPRE3));
+}
+
+/**
+ * @brief Set Clock After Wake-Up From Stop mode
+ * @rmtoll CFGR1 STOPWUCK LL_RCC_SetClkAfterWakeFromStop
+ * @param Clock This parameter can be one of the following values:
+ * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSIS
+ * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)
+{
+ MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPWUCK, Clock);
+}
+
+/**
+ * @brief Get Clock After Wake-Up From Stop mode
+ * @rmtoll CFGR1 STOPWUCK LL_RCC_GetClkAfterWakeFromStop
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSIS
+ * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_STOPWUCK));
+}
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_MCO MCO
+ * @{
+ */
+
+/**
+ * @brief Configure MCOx
+ * @rmtoll CFGR1 MCOSEL LL_RCC_ConfigMCO\n
+ * CFGR1 MCOPRE LL_RCC_ConfigMCO
+ * @param MCOxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
+ * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
+ * @arg @ref LL_RCC_MCO1SOURCE_MSIS
+ * @arg @ref LL_RCC_MCO1SOURCE_HSI
+ * @arg @ref LL_RCC_MCO1SOURCE_HSE
+ * @arg @ref LL_RCC_MCO1SOURCE_HSI48
+ * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
+ * @arg @ref LL_RCC_MCO1SOURCE_LSI
+ * @arg @ref LL_RCC_MCO1SOURCE_LSE
+ * @param MCOxPrescaler This parameter can be one of the following values:
+ * @arg @ref LL_RCC_MCO1_DIV_1
+ * @arg @ref LL_RCC_MCO1_DIV_2
+ * @arg @ref LL_RCC_MCO1_DIV_4
+ * @arg @ref LL_RCC_MCO1_DIV_8
+ * @arg @ref LL_RCC_MCO1_DIV_16
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
+{
+ MODIFY_REG(RCC->CFGR1, RCC_CFGR1_MCOSEL | RCC_CFGR1_MCOPRE, MCOxSource | MCOxPrescaler);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
+ * @{
+ */
+
+/**
+ * @brief Configure USARTx clock source
+ * @rmtoll CCIPR1 USART1SEL LL_RCC_SetUSARTClockSource\n
+ * CCIPR1 USART2SEL LL_RCC_SetUSARTClockSource\n
+ * CCIPR1 USART3SEL LL_RCC_SetUSARTClockSource
+ * @param USARTxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
+{
+ MODIFY_REG(RCC->CCIPR1, USARTxSource >> 16U, (USARTxSource & 0x0000FFFFU));
+}
+
+/**
+ * @brief Configure UARTx clock source
+ * @rmtoll CCIPR1 UART4SEL LL_RCC_SetUARTClockSource\n
+ * CCIPR1 UART5SEL LL_RCC_SetUARTClockSource
+ * @param UARTxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
+{
+ MODIFY_REG(RCC->CCIPR1, UARTxSource >> 16U, (UARTxSource & 0x0000FFFFU));
+}
+
+/**
+ * @brief Configure LPUARTx clock source
+ * @rmtoll CCIPR3 LPUART1SEL LL_RCC_SetLPUARTClockSource
+ * @param LPUARTxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK3
+ * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_LPUART1_CLKSOURCE_MSIK
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
+{
+ MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_LPUART1SEL, LPUARTxSource);
+}
+
+/**
+ * @brief Configure I2Cx clock source
+ * @rmtoll CCIPR1 I2C1SEL LL_RCC_SetI2CClockSource\n
+ * CCIPR1 I2C2SEL LL_RCC_SetI2CClockSource\n
+ * CCIPR3 I2C3SEL LL_RCC_SetI2CClockSource\n
+ * CCIPR1 I2C4SEL LL_RCC_SetI2CClockSource
+ * @param I2CxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_I2C1_CLKSOURCE_MSIK
+ * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_I2C2_CLKSOURCE_MSIK
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK3
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE_MSIK
+ * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_I2C4_CLKSOURCE_MSIK
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
+{
+ __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (I2CxSource >> 24U));
+ MODIFY_REG(*reg, 3U << (((I2CxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((I2CxSource & 0x000000FFU) << \
+ (((I2CxSource & 0x00FF0000U) >> 16U) & \
+ 0x1FU)));
+}
+
+/**
+ * @brief Configure SPIx clock source
+ * @rmtoll CCIPR1 SPI1SEL LL_RCC_SetSPIClockSource\n
+ * CCIPR1 SPI1SEL LL_RCC_SetSPIClockSource\n
+ * CCIPR1 SPI2SEL LL_RCC_SetSPIClockSource\n
+ * CCIPR3 SPI3SEL LL_RCC_SetSPIClockSource
+ * @param SPIxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SPI1_CLKSOURCE_PCLK2
+ * @arg @ref LL_RCC_SPI1_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_SPI1_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_SPI1_CLKSOURCE_MSIK
+ * @arg @ref LL_RCC_SPI2_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_SPI2_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_SPI2_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_SPI2_CLKSOURCE_MSIK
+ * @arg @ref LL_RCC_SPI3_CLKSOURCE_PCLK3
+ * @arg @ref LL_RCC_SPI3_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_SPI3_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_SPI3_CLKSOURCE_MSIK
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t SPIxSource)
+{
+ __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (SPIxSource >> 24U));
+ MODIFY_REG(*reg, 3U << (((SPIxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((SPIxSource & 0x000000FFU) << \
+ (((SPIxSource & 0x00FF0000U) >> 16U) & \
+ 0x1FU)));
+}
+
+/**
+ * @brief Configure LPTIMx clock source
+ * @rmtoll CCIPR1 LPTIM2SEL LL_RCC_SetLPTIMClockSource\n
+ * CCIPR3 LPTIM2SEL LL_RCC_SetLPTIMClockSource\n
+ * CCIPR3 LPTIM34SEL LL_RCC_SetLPTIMClockSource
+ * @param LPTIMxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_MSIK
+ * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
+ * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
+ * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_LPTIM34_CLKSOURCE_MSIK
+ * @arg @ref LL_RCC_LPTIM34_CLKSOURCE_LSI
+ * @arg @ref LL_RCC_LPTIM34_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_LPTIM34_CLKSOURCE_LSE
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
+{
+ __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (LPTIMxSource >> 24U));
+ MODIFY_REG(*reg, 3U << (((LPTIMxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((LPTIMxSource & 0x000000FFU) << \
+ (((LPTIMxSource & 0x00FF0000U) >> 16U) & \
+ 0x1FU)));
+}
+
+/**
+ * @brief Configure FDCAN kernel clock source
+ * @rmtoll CCIPR1 FDCANSEL LL_RCC_SetFDCANClockSource
+ * @param FDCANxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
+ * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1
+ * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t FDCANxSource)
+{
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_FDCANSEL, FDCANxSource);
+}
+
+/**
+ * @brief Configure SAIx clock source
+ * @rmtoll CCIPR2 SAI1SEL LL_RCC_SetSAIClockSource\n
+ * CCIPR2 SAI2SEL LL_RCC_SetSAIClockSource
+ * @param SAIxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL1
+ * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL2
+ * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3
+ * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN
+ * @arg @ref LL_RCC_SAI2_CLKSOURCE_HSI
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
+{
+ MODIFY_REG(RCC->CCIPR2, (SAIxSource >> 16U), (SAIxSource & 0x0000FFFFU));
+}
+
+/**
+ * @brief Configure SDMMC1/2 kernel clock source
+ * @rmtoll CCIPR2 SDMMCSEL LL_RCC_SetSDMMCKernelClockSource
+ * @param SDMMCxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SDMMC12_KERNELCLKSOURCE_48CLK
+ * @arg @ref LL_RCC_SDMMC12_KERNELCLKSOURCE_PLL1 "P"
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetSDMMCKernelClockSource(uint32_t SDMMCxSource)
+{
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL, SDMMCxSource);
+}
+
+/**
+ * @brief Configure SDMMC1/2 clock source
+ * @rmtoll CCIPR1 CLK48MSEL LL_RCC_SetSDMMCClockSource
+ * @param SDMMCxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SDMMC12_CLKSOURCE_HSI48
+ * @arg @ref LL_RCC_SDMMC12_CLKSOURCE_PLL1
+ * @arg @ref LL_RCC_SDMMC12_CLKSOURCE_PLL2
+ * @arg @ref LL_RCC_SDMMC12_CLKSOURCE_MSIK
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource)
+{
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL, SDMMCxSource);
+}
+
+/**
+ * @brief Configure RNG clock source
+ * @rmtoll CCIPR2 RNGSEL LL_RCC_SetRNGClockSource
+ * @param RNGxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
+ * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48_DIV2
+ * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
+{
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_RNGSEL, RNGxSource);
+}
+
+/**
+ * @brief Configure USB clock source
+ * @rmtoll CCIPR1 CLK48MSEL LL_RCC_SetUSBClockSource
+ * @param USBxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
+ * @arg @ref LL_RCC_USB_CLKSOURCE_PLL1
+ * @arg @ref LL_RCC_USB_CLKSOURCE_PLL2
+ * @arg @ref LL_RCC_USB_CLKSOURCE_MSIK
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
+{
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL, USBxSource);
+}
+
+/**
+ * @brief Configure ADC clock source
+ * @rmtoll CCIPR3 ADCDACSEL LL_RCC_SetADCDACClockSource
+ * @param ADCxDAC1Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HCLK
+ * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_PLL2
+ * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HSE
+ * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_MSIK
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetADCDACClockSource(uint32_t ADCxDAC1Source)
+{
+ MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_ADCDACSEL, ADCxDAC1Source);
+}
+
+/**
+ * @brief Configure DAC1 clock source
+ * @rmtoll CCIPR3 DAC1SEL LL_RCC_SetDAC1ClockSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_DAC1_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_DAC1_CLKSOURCE_LSI
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetDAC1ClockSource(uint32_t Source)
+{
+ MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_DAC1SEL, Source);
+}
+
+/**
+ * @brief Configure ADF1 clock source
+ * @rmtoll CCIPR3 ADF1SEL LL_RCC_SetADF1ClockSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_ADF1_CLKSOURCE_HCLK
+ * @arg @ref LL_RCC_ADF1_CLKSOURCE_PLL1
+ * @arg @ref LL_RCC_ADF1_CLKSOURCE_PLL3
+ * @arg @ref LL_RCC_ADF1_CLKSOURCE_MSIK
+ * @arg @ref LL_RCC_ADF1_CLKSOURCE_PIN
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetADF1ClockSource(uint32_t Source)
+{
+ MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_ADF1SEL, Source);
+}
+
+/**
+ * @brief Configure MDF1 clock source
+ * @rmtoll CCIPR3 MDF1SEL LL_RCC_SetMDF1ClockSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_MDF1_CLKSOURCE_HCLK
+ * @arg @ref LL_RCC_MDF1_CLKSOURCE_PLL1
+ * @arg @ref LL_RCC_MDF1_CLKSOURCE_PLL3
+ * @arg @ref LL_RCC_MDF1_CLKSOURCE_MSIK
+ * @arg @ref LL_RCC_MDF1_CLKSOURCE_PIN
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetMDF1ClockSource(uint32_t Source)
+{
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_MDF1SEL, Source);
+}
+
+/**
+ * @brief Configure OCTOSPI kernel clock source
+ * @rmtoll CCIPR2 OSPISEL LL_RCC_SetOCTOSPIClockSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_MSIK
+ * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL1
+ * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL2
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetOCTOSPIClockSource(uint32_t Source)
+{
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OCTOSPISEL, Source);
+}
+
+/**
+ * @brief Configure SAES clock source
+ * @rmtoll CCIPR2 SAESSEL LL_RCC_SetSAESClockSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SAES_CLKSOURCE_SHSI
+ * @arg @ref LL_RCC_SAES_CLKSOURCE_SHSI_DIV2
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetSAESClockSource(uint32_t Source)
+{
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAESSEL, Source);
+}
+
+/**
+ * @brief Get USARTx clock source
+ * @rmtoll CCIPR1 USART1SEL LL_RCC_GetUSARTClockSource\n
+ * CCIPR1 USART2SEL LL_RCC_GetUSARTClockSource\n
+ * CCIPR1 USART3SEL LL_RCC_GetUSARTClockSource
+ * @param USARTx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_USART1_CLKSOURCE
+ * @arg @ref LL_RCC_USART2_CLKSOURCE
+ * @arg @ref LL_RCC_USART3_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
+{
+ return (uint32_t)(READ_BIT(RCC->CCIPR1, USARTx) | (USARTx << 16U));
+}
+
+/**
+ * @brief Get UARTx clock source
+ * @rmtoll CCIPR1 UART4SEL LL_RCC_GetUARTClockSource\n
+ * CCIPR1 UART5SEL LL_RCC_GetUARTClockSource
+ * @param UARTx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_UART4_CLKSOURCE
+ * @arg @ref LL_RCC_UART5_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
+{
+ return (uint32_t)(READ_BIT(RCC->CCIPR1, UARTx) | (UARTx << 16U));
+}
+
+/**
+ * @brief Get LPUARTx clock source
+ * @rmtoll CCIPR1 LPUART1SEL LL_RCC_GetLPUARTClockSource
+ * @param LPUARTx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_LPUART1_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK3
+ * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
+{
+ return (uint32_t)(READ_BIT(RCC->CCIPR3, LPUARTx));
+}
+
+/**
+ * @brief Get I2Cx clock source
+ * @rmtoll CCIPR1 I2C1SEL LL_RCC_GetI2CClockSource\n
+ * CCIPR1 I2C2SEL LL_RCC_GetI2CClockSource\n
+ * CCIPR3 I2C3SEL LL_RCC_GetI2CClockSource\n
+ * CCIPR1 I2C4SEL LL_RCC_GetI2CClockSource
+ * @param I2Cx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_I2C1_CLKSOURCE
+ * @arg @ref LL_RCC_I2C2_CLKSOURCE
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE
+ * @arg @ref LL_RCC_I2C4_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK3
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
+{
+ __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (I2Cx >> 24U));
+ return (uint32_t)((READ_BIT(*reg, (3UL << (((I2Cx & 0x00FF0000UL) >> 16U) & 0x1FUL))) >> \
+ (((I2Cx & 0x00FF0000UL) >> 16U) & 0x1FUL)) | (I2Cx & 0xFFFF0000UL));
+}
+
+/**
+ * @brief Get SPIx clock source
+ * @rmtoll CCIPR1 SPI1SEL LL_RCC_GetSPIClockSource\n
+ * CCIPR1 SPI2SEL LL_RCC_GetSPIClockSource\n
+ * CCIPR3 SPI3SEL LL_RCC_GetSPIClockSource
+ * @param SPIx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SPI1_CLKSOURCE
+ * @arg @ref LL_RCC_SPI2_CLKSOURCE
+ * @arg @ref LL_RCC_SPI3_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_SPI1_CLKSOURCE_PCLK2
+ * @arg @ref LL_RCC_SPI1_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_SPI1_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_SPI1_CLKSOURCE_MSIK
+ * @arg @ref LL_RCC_SPI2_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_SPI2_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_SPI2_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_SPI2_CLKSOURCE_MSIK
+ * @arg @ref LL_RCC_SPI3_CLKSOURCE_PCLK3
+ * @arg @ref LL_RCC_SPI3_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_SPI3_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_SPI3_CLKSOURCE_MSIK
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetSPIClockSource(uint32_t SPIx)
+{
+ __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (SPIx >> 24U));
+ return (uint32_t)((READ_BIT(*reg, (3UL << (((SPIx & 0x00FF0000UL) >> 16U) & 0x1FUL))) >> \
+ (((SPIx & 0x00FF0000UL) >> 16U) & 0x1FUL)) | (SPIx & 0xFFFF0000UL));
+}
+
+/**
+ * @brief Get LPTIMx clock source
+ * @rmtoll CCIPR1 LPTIM2SEL LL_RCC_GetLPTIMClockSource\n
+ * CCIPR3 LPTIM2SEL LL_RCC_GetLPTIMClockSource\n
+ * CCIPR3 LPTIM34SEL LL_RCC_GetLPTIMClockSource
+ * @param LPTIMx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
+ * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
+ * @arg @ref LL_RCC_LPTIM34_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_MSIK
+ * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
+ * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
+ * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_LPTIM34_CLKSOURCE_MSIK
+ * @arg @ref LL_RCC_LPTIM34_CLKSOURCE_LSI
+ * @arg @ref LL_RCC_LPTIM34_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_LPTIM34_CLKSOURCE_LSE
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
+{
+ __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (LPTIMx >> 24U));
+ return (uint32_t)((READ_BIT(*reg, (3UL << (((LPTIMx & 0x00FF0000UL) >> 16U) & 0x1FUL))) >> \
+ (((LPTIMx & 0x00FF0000UL) >> 16U) & 0x1FUL)) | (LPTIMx & 0xFFFF0000UL));
+}
+
+/**
+ * @brief Set Tim Input capture clock source
+ * @rmtoll CCIPR1 TIMICSEL LL_RCC_SetTIMICClockSource
+ * @param TIMICSource This parameter can be one of the following combined values:
+ * @arg @ref LL_RCC_TIMIC_CLKSOURCE_NONE
+ * @arg @ref LL_RCC_TIMIC_CLKSOURCE_HSI_DIV256
+ * @arg @ref LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV1024
+ * @arg @ref LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV4
+ * @arg @ref LL_RCC_TIMIC_CLKSOURCE_MSIK_DIV4
+ * @arg @ref LL_RCC_TIMIC_CLKSOURCE_MSIK_DIV1024
+ * @note HSI, MSI and MSIK clocks without division are also available when TIMICSEL[2] is 1.
+ * @note combination to be avoided :
+ * LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV1024 and LL_RCC_CLKSOURCE_TIMIC_MSIK_DIV1024
+ * LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV4 and LL_RCC_CLKSOURCE_TIMIC_MSIK_DIV4
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetTIMICClockSource(uint32_t TIMICSource)
+{
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL, TIMICSource);
+}
+
+/**
+ * @brief Get Tim Input capture clock source
+ * @rmtoll CCIPR1 TIMICSEL LL_RCC_GetTIMICClockSource
+ * @retval Returned value can be one of the following combined values:
+ * @arg @ref LL_RCC_TIMIC_CLKSOURCE_NONE
+ * @arg @ref LL_RCC_TIMIC_CLKSOURCE_HSI_DIV256
+ * @arg @ref LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV1024
+ * @arg @ref LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV4
+ * @arg @ref LL_RCC_TIMIC_CLKSOURCE_MSIK_DIV4
+ * @arg @ref LL_RCC_TIMIC_CLKSOURCE_MSIK_DIV1024
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetTIMICClockSource(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL));
+}
+
+/**
+ * @brief Get FDCAN kernel clock source
+ * @rmtoll CCIPR1 FDCANSEL LL_RCC_GetFDCANClockSource
+ * @param FDCANx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_FDCAN_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
+ * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1
+ * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t FDCANx)
+{
+ return (uint32_t)(READ_BIT(RCC->CCIPR1, FDCANx));
+}
+
+/**
+ * @brief Get SAIx clock source
+ * @rmtoll CCIPR2 SAI1SEL LL_RCC_GetSAIClockSource\n
+ * CCIPR2 SAI2SEL LL_RCC_GetSAIClockSource
+ * @param SAIx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE
+ * @arg @ref LL_RCC_SAI2_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL1
+ * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL2
+ * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3
+ * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN
+ * @arg @ref LL_RCC_SAI2_CLKSOURCE_HSI
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
+{
+ return (uint32_t)(READ_BIT(RCC->CCIPR2, SAIx) | (SAIx << 16U));
+}
+
+/**
+ * @brief Get SDMMCx kernel clock source
+ * @rmtoll CCIPR2 SDMMCSEL LL_RCC_GetSDMMCKernelClockSource
+ * @param SDMMCx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SDMMC_KERNELCLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_SDMMC12_KERNELCLKSOURCE_48CLK
+ * @arg @ref LL_RCC_SDMMC12_KERNELCLKSOURCE_PLL1 "P"
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetSDMMCKernelClockSource(uint32_t SDMMCx)
+{
+ return (uint32_t)(READ_BIT(RCC->CCIPR2, SDMMCx));
+}
+
+/**
+ * @brief Get SDMMC1/2 clock source
+ * @rmtoll CCIPR1 CLK48MSEL LL_RCC_GetSDMMC12ClockSource
+ * @param SDMMCx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SDMMC_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_SDMMC12_CLKSOURCE_HSI48
+ * @arg @ref LL_RCC_SDMMC12_CLKSOURCE_PLL1
+ * @arg @ref LL_RCC_SDMMC12_CLKSOURCE_PLL2
+ * @arg @ref LL_RCC_SDMMC12_CLKSOURCE_MSIK
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx)
+{
+ return (uint32_t)(READ_BIT(RCC->CCIPR1, SDMMCx));
+}
+
+/**
+ * @brief Get RNGx clock source
+ * @rmtoll CCIPR2 RNGSEL LL_RCC_GetRNGClockSource
+ * @param RNGx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_RNG_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
+ * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48_DIV2
+ * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
+{
+ return (uint32_t)(READ_BIT(RCC->CCIPR2, RNGx));
+}
+
+/**
+ * @brief Get USBx clock source
+ * @rmtoll CCIPR1 CLK48MSEL LL_RCC_GetUSBClockSource
+ * @param USBx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_USB_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
+ * @arg @ref LL_RCC_USB_CLKSOURCE_PLL1
+ * @arg @ref LL_RCC_USB_CLKSOURCE_PLL2
+ * @arg @ref LL_RCC_USB_CLKSOURCE_MSIK
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
+{
+ return (uint32_t)(READ_BIT(RCC->CCIPR1, USBx));
+}
+
+/**
+ * @brief Get ADCx clock source
+ * @rmtoll CCIPR3 ADCDACSEL LL_RCC_SetADCDACClockSource
+ * @param ADCxDAC1 This parameter can be one of the following values:
+ * @arg @ref LL_RCC_ADCDAC_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HCLK
+ * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_PLL2
+ * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_MSIK
+ * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HSE
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetADCDACClockSource(uint32_t ADCxDAC1)
+{
+ return (uint32_t)(READ_BIT(RCC->CCIPR3, ADCxDAC1));
+}
+
+/**
+ * @brief Get DFSDM Audio Clock Source
+ * @rmtoll CCIPR3 ADF1SEL LL_RCC_GetADF1ClockSource
+ * @param ADF1x This parameter can be one of the following values:
+ * @arg @ref LL_RCC_ADF1_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_ADF1_CLKSOURCE_HCLK
+ * @arg @ref LL_RCC_ADF1_CLKSOURCE_PLL1
+ * @arg @ref LL_RCC_ADF1_CLKSOURCE_PLL3
+ * @arg @ref LL_RCC_ADF1_CLKSOURCE_MSIK
+ * @arg @ref LL_RCC_ADF1_CLKSOURCE_PIN
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetADF1ClockSource(uint32_t ADF1x)
+{
+ return (uint32_t)(READ_BIT(RCC->CCIPR3, ADF1x));
+}
+
+/**
+ * @brief Get DAC1 Clock Source
+ * @rmtoll CCIPR3 DAC1SEL LL_RCC_GetDAC1ClockSource
+ * @param DAC1x This parameter can be one of the following values:
+ * @arg @ref LL_RCC_DAC1_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_DAC1_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_DAC1_CLKSOURCE_LSI
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetDAC1ClockSource(uint32_t DAC1x)
+{
+ return (uint32_t)(READ_BIT(RCC->CCIPR3, DAC1x));
+}
+
+/**
+ * @brief Get MDF1 Clock Source
+ * @rmtoll CCIPR2 MDF1SEL LL_RCC_GetMDF1ClockSource
+ * @param MDF1x This parameter can be one of the following values:
+ * @arg @ref LL_RCC_MDF1_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_MDF1_CLKSOURCE_HCLK
+ * @arg @ref LL_RCC_MDF1_CLKSOURCE_PLL1
+ * @arg @ref LL_RCC_MDF1_CLKSOURCE_PLL3
+ * @arg @ref LL_RCC_MDF1_CLKSOURCE_MSIK
+ * @arg @ref LL_RCC_MDF1_CLKSOURCE_PIN
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetMDF1ClockSource(uint32_t MDF1x)
+{
+ return (uint32_t)(READ_BIT(RCC->CCIPR2, MDF1x));
+}
+
+/**
+ * @brief Get OCTOSPI clock source
+ * @rmtoll CCIPR2 OSPISEL LL_RCC_GetOCTOSPIClockSource
+ * @param OCTOSPIx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_MSIK
+ * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL1
+ * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL2
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetOCTOSPIClockSource(uint32_t OCTOSPIx)
+{
+ return (uint32_t)(READ_BIT(RCC->CCIPR2, OCTOSPIx));
+}
+/**
+ * @}
+ */
+
+/**
+ * @brief Get SAES kernel clock source
+ * @rmtoll CCIPR2 SAESSEL LL_RCC_GetSAESClockSource
+ * @param SAESx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SAES_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_SAES_CLKSOURCE_SHSI
+ * @arg @ref LL_RCC_SAES_CLKSOURCE_SHSI_DIV2
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetSAESClockSource(uint32_t SAESx)
+{
+ return (uint32_t)(READ_BIT(RCC->CCIPR2, SAESx));
+}
+
+/** @defgroup RCC_LL_EF_RTC RTC
+ * @{
+ */
+
+/**
+ * @brief Set RTC Clock Source
+ * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
+ * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
+ * set). The BDRST bit can be used to reset them.
+ * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
+{
+ MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
+}
+
+/**
+ * @brief Get RTC Clock Source
+ * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
+{
+ return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
+}
+
+/**
+ * @brief Enable RTC
+ * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableRTC(void)
+{
+ SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
+}
+
+/**
+ * @brief Disable RTC
+ * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableRTC(void)
+{
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
+}
+
+/**
+ * @brief Check if RTC has been enabled or not
+ * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
+{
+ return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == RCC_BDCR_RTCEN) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Force the Backup domain reset
+ * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
+{
+ SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
+}
+
+/**
+ * @brief Release the Backup domain reset
+ * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
+{
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup RCC_LL_EF_PLL1 PLL1
+ * @{
+ */
+
+/**
+ * @brief Enable PLL1
+ * @rmtoll CR PLL1ON LL_RCC_PLL1_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL1_Enable(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_PLL1ON);
+}
+
+/**
+ * @brief Disable PLL1
+ * @note Cannot be disabled if the PLL1 clock is used as the system clock
+ * @rmtoll CR PLLON LL_RCC_PLL1_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL1_Disable(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON);
+}
+
+/**
+ * @brief Check if PLL1 Ready
+ * @rmtoll CR PLL1RDY LL_RCC_PLL1_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL1_IsReady(void)
+{
+ return ((READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == RCC_CR_PLL1RDY) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure PLL1 used for SYSCLK Domain
+ * @note PLL1 Source, PLLM, PLLN and PLLR can be written only when PLL1 is disabled.
+ * @note PLLN/PLLR can be written only when PLL is disabled.
+ * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_ConfigDomain_SYS\n
+ * PLL1CFGR PLL1M LL_RCC_PLL1_ConfigDomain_SYS\n
+ * PLL1CFGR PLL1N LL_RCC_PLL1_ConfigDomain_SYS\n
+ * PLL1CFGR PLL1R LL_RCC_PLL1_ConfigDomain_SYS
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLL1SOURCE_NONE
+ * @arg @ref LL_RCC_PLL1SOURCE_MSIS
+ * @arg @ref LL_RCC_PLL1SOURCE_HSI
+ * @arg @ref LL_RCC_PLL1SOURCE_HSE
+ * @param PLLM parameter can be a value between 1 and 16
+ * @param PLLR parameter can be a value between 1 and 128
+ * @param PLLN parameter can be a value between 4 and 512
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL1_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
+{
+ MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | \
+ ((PLLM - 1UL) << RCC_PLL1CFGR_PLL1M_Pos));
+ MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N | RCC_PLL1DIVR_PLL1R, ((PLLN - 1UL) << \
+ RCC_PLL1DIVR_PLL1N_Pos) | ((PLLR - 1UL) << \
+ RCC_PLL1DIVR_PLL1R_Pos));
+}
+
+/**
+ * @brief Configure PLL1 used for SAI domain clock
+ * @note PLL1 Source, PLLM, PLLN and PLLPDIV can be written only when PLL1 is disabled.
+ * @note This can be selected for SAI1 or SAI2
+ * @rmtoll PLLC1FGR PLL1SRC LL_RCC_PLL1_ConfigDomain_SAI\n
+ * PLLC1FGR PLL1M LL_RCC_PLL1_ConfigDomain_SAI\n
+ * PLLC1FGR PLL1N LL_RCC_PLL1_ConfigDomain_SAI\n
+ * PLLC1FGR PLL1P LL_RCC_PLL1_ConfigDomain_SAI
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLL1SOURCE_NONE
+ * @arg @ref LL_RCC_PLL1SOURCE_MSIS
+ * @arg @ref LL_RCC_PLL1SOURCE_HSI
+ * @arg @ref LL_RCC_PLL1SOURCE_HSE
+ * @param PLLM parameter can be a value between 1 and 16
+ * @param PLLN parameter can be a value between 4 and 512
+ * @param PLLP parameter can be a value between 2 and 128
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
+{
+ MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | \
+ ((PLLM - 1UL) << RCC_PLL1CFGR_PLL1M_Pos));
+ MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N | RCC_PLL1DIVR_PLL1P, ((PLLN - 1UL) << \
+ RCC_PLL1DIVR_PLL1N_Pos) | ((PLLP - 1UL) << \
+ RCC_PLL1DIVR_PLL1P_Pos));
+}
+
+/**
+ * @brief Configure PLL1 used for 48Mhz domain clock
+ * @note PLL1 Source, PLLM, PLLN and PLLQ can be written only when PLL1 is disabled.
+ * @note This can be selected for USB, SDMMC
+ * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_ConfigDomain_48M\n
+ * PLL1CFGR PLL1M LL_RCC_PLL1_ConfigDomain_48M\n
+ * PLL1CFGR PLL1N LL_RCC_PLL1_ConfigDomain_48M\n
+ * PLL1CFGR PLL1Q LL_RCC_PLL1_ConfigDomain_48M
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLL1SOURCE_NONE
+ * @arg @ref LL_RCC_PLL1SOURCE_MSIS
+ * @arg @ref LL_RCC_PLL1SOURCE_HSI
+ * @arg @ref LL_RCC_PLL1SOURCE_HSE
+ * @param PLLM parameter can be a value between 1 and 16
+ * @param PLLN parameter can be a value between 4 and 512
+ * @param PLLQ parameter can be a value between 1 and 128
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
+{
+ MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | \
+ ((PLLM - 1UL) << RCC_PLL1CFGR_PLL1M_Pos));
+ MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N | RCC_PLL1DIVR_PLL1Q, ((PLLN - 1UL) << \
+ RCC_PLL1DIVR_PLL1N_Pos) | ((PLLQ - 1UL) << \
+ RCC_PLL1DIVR_PLL1Q_Pos));
+}
+
+/**
+ * @brief Configure PLL clock source
+ * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_SetMainSource
+ * @param PLL1Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLL1SOURCE_NONE
+ * @arg @ref LL_RCC_PLL1SOURCE_MSIS
+ * @arg @ref LL_RCC_PLL1SOURCE_HSI
+ * @arg @ref LL_RCC_PLL1SOURCE_HSE
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL1_SetMainSource(uint32_t PLL1Source)
+{
+ MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC, PLL1Source);
+}
+
+/**
+ * @brief Get the oscillator used as PLL1 clock source.
+ * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_GetMainSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLL1SOURCE_NONE
+ * @arg @ref LL_RCC_PLL1SOURCE_MSIS
+ * @arg @ref LL_RCC_PLL1SOURCE_HSI
+ * @arg @ref LL_RCC_PLL1SOURCE_HSE
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL1_GetMainSource(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC));
+}
+
+/**
+ * @brief Set Main PLL1 multiplication factor for VCO
+ * @rmtoll PLL1CFGR PLL1N LL_RCC_PLL1_SetN
+ * @param PLL1N parameter can be a value between 4 and 512
+ */
+__STATIC_INLINE void LL_RCC_PLL1_SetN(uint32_t PLL1N)
+{
+ MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N, (PLL1N - 1UL) << RCC_PLL1DIVR_PLL1N_Pos);
+}
+
+/**
+ * @brief Get Main PLL1 multiplication factor for VCO
+ * @rmtoll PLL1CFGR PLL1N LL_RCC_PLL1_GetN
+ * @retval Between 4 and 512
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL1_GetN(void)
+{
+ return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N) >> RCC_PLL1DIVR_PLL1N_Pos) + 1UL);
+}
+
+
+/**
+ * @brief Set Main PLL1 division factor for PLL1P
+ * @note Used for SAI1 and SAI2 clock
+ * @rmtoll PLL1CFGR PLL1P LL_RCC_PLL1_SetP
+ * @param PLL1P parameter can be a value between 2 and 128
+ */
+__STATIC_INLINE void LL_RCC_PLL1_SetP(uint32_t PLL1P)
+{
+ MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1P, (PLL1P - 1UL) << RCC_PLL1DIVR_PLL1P_Pos);
+}
+
+/**
+ * @brief Get Main PLL1 division factor for PLL1P
+ * @note Used for SAI1 and SAI2 clock
+ * @rmtoll PLL1CFGR PLL1P LL_RCC_PLL1_GetP
+ * @retval Between 2 and 128
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL1_GetP(void)
+{
+ return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + 1UL);
+}
+
+
+/**
+ * @brief Set Main PLL division factor for PLLQ
+ * @note Used for PLL48M1CLK selected for USB, SDMMC (48 MHz clock)
+ * @rmtoll PLLCFGR PLL1Q LL_RCC_PLL1_SetQ
+ * @param PLL1Q parameter can be a value between 1 and 128
+ */
+__STATIC_INLINE void LL_RCC_PLL1_SetQ(uint32_t PLL1Q)
+{
+ MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1Q, (PLL1Q - 1UL) << RCC_PLL1DIVR_PLL1Q_Pos);
+}
+
+/**
+ * @brief Get Main PLL division factor for PLLQ
+ * @note Used for PLL48M1CLK selected for USB, SDMMC (48 MHz clock)
+ * @rmtoll PLL1CFGR PLL1Q LL_RCC_PLL1_GetQ
+ * @retval Between 1 and 128
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL1_GetQ(void)
+{
+ return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1Q) >> RCC_PLL1DIVR_PLL1Q_Pos) + 1UL);
+}
+
+/**
+ * @brief Set Main PLL division factor for PLL1R
+ * @note Used for PLL1CLK selected for USB, SDMMC (48 MHz clock)
+ * @rmtoll PLL1DIVR PLL1R LL_RCC_PLL1_SetR
+ * @param PLL1R parameter can be a value between 1 and 128
+ */
+__STATIC_INLINE void LL_RCC_PLL1_SetR(uint32_t PLL1R)
+{
+ MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1R, (PLL1R - 1UL) << RCC_PLL1DIVR_PLL1R_Pos);
+}
+
+/**
+ * @brief Get Main PLL1 division factor for PLL1R
+ * @note Used for PLL1CLK (system clock)
+ * @rmtoll PLL1DIVR PLL1R LL_RCC_PLL1_GetR
+ * @retval Between 1 and 128
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL1_GetR(void)
+{
+ return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1UL);
+}
+
+/**
+ * @brief Set Division factor for the main PLL and other PLL
+ * @rmtoll PLL1CFGR PLL1M LL_RCC_PLL1_SetDivider
+ * @param PLL1M parameter can be a value between 1 and 16
+ */
+__STATIC_INLINE void LL_RCC_PLL1_SetDivider(uint32_t PLL1M)
+{
+ MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M, (PLL1M - 1UL) << RCC_PLL1CFGR_PLL1M_Pos);
+}
+
+/**
+ * @brief Get Division factor for the main PLL and other PLL
+ * @rmtoll PLL1CFGR PLL1M LL_RCC_PLL1_GetDivider
+ * @retval Between 1 and 16
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL1_GetDivider(void)
+{
+ return (uint32_t)((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1UL);
+}
+
+/**
+ * @brief Enable PLL1 output mapped on SAI domain clock
+ * @rmtoll PLL1CFGR PLL1PEN LL_RCC_PLL1_EnableDomain_SAI
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL1_EnableDomain_SAI(void)
+{
+ SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN);
+}
+
+/**
+ * @brief Disable PLL1 output mapped on SAI domain clock
+ * @note Cannot be disabled if the PLL1 clock is used as the system
+ * clock
+ * @note In order to save power, when the PLL1CLK of the PLL1 is
+ * not used, should be 0
+ * @rmtoll PLL1CFGR PLL1PEN LL_RCC_PLL1_DisableDomain_SAI
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL1_DisableDomain_SAI(void)
+{
+ CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN);
+}
+
+/**
+ * @brief Enable PLL output mapped on 48MHz domain clock
+ * @rmtoll PLL1CFGR PLL1QEN LL_RCC_PLL1_EnableDomain_48M
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL1_EnableDomain_48M(void)
+{
+ SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN);
+}
+
+/**
+ * @brief Disable PLL1 output mapped on 48MHz domain clock
+ * @note Cannot be disabled if the PLL clock is used as the system
+ * clock
+ * @note In order to save power, when the PLL1CLK of the PLL1 is
+ * not used, should be 0
+ * @rmtoll PLL1CFGR PLL1QEN LL_RCC_PLL1_DisableDomain_48M
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL1_DisableDomain_48M(void)
+{
+ CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN);
+}
+
+/**
+ * @brief Enable PLL1 output mapped on SYSCLK domain
+ * @rmtoll PLL1CFGR PLL1REN LL_RCC_PLL1_EnableDomain_SYS
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL1_EnableDomain_SYS(void)
+{
+ SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN);
+}
+
+/**
+ * @brief Disable PLL1 output mapped on SYSCLK domain
+ * @note Cannot be disabled if the PLL1 clock is used as the system
+ * clock
+ * @note In order to save power, when the PLL1CLK of the PLL1 is
+ * not used, Main PLL1 should be 0
+ * @rmtoll PLL1CFGR PLL1REN LL_RCC_PLL1_DisableDomain_SYS
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL1_DisableDomain_SYS(void)
+{
+ CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN);
+}
+
+/**
+ * @brief Enable PLL1 FRACN
+ * @rmtoll PLL1CFGR PLL1FRACEN LL_RCC_PLL1FRACN_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL1FRACN_Enable(void)
+{
+ SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN);
+}
+
+/**
+ * @brief Check if PLL1 FRACN is enabled
+ * @rmtoll PLL1CFGR PLL1FRACEN LL_RCC_PLL1FRACN_IsEnabled
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL1FRACN_IsEnabled(void)
+{
+ return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) == RCC_PLL1CFGR_PLL1FRACEN) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Disable PLL1 FRACN
+ * @rmtoll PLL1CFGR PLL1FRACEN LL_RCC_PLL1FRACN_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL1FRACN_Disable(void)
+{
+ CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN);
+}
+
+/**
+ * @brief Set PLL1 FRACN Coefficient
+ * @rmtoll PLL1FRACR PLL1FRACN LL_RCC_PLL1_SetFRACN
+ * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF)
+ */
+__STATIC_INLINE void LL_RCC_PLL1_SetFRACN(uint32_t FRACN)
+{
+ MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_PLL1FRACN, FRACN << RCC_PLL1FRACR_PLL1FRACN_Pos);
+}
+
+/**
+ * @brief Get PLL1 FRACN Coefficient
+ * @rmtoll PLL1FRACR PLL1FRACN LL_RCC_PLL1_GetFRACN
+ * @retval A value between 0 and 8191 (0x1FFF)
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL1_GetFRACN(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_PLL1FRACN) >> RCC_PLL1FRACR_PLL1FRACN_Pos);
+}
+
+/**
+ * @brief Set PLL1 VCO Input Range
+ * @note This API shall be called only when PLL1 is disabled.
+ * @rmtoll PLL1CFGR PLL1RGE LL_RCC_PLL1_SetVCOInputRange
+ * @param InputRange This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLINPUTRANGE_4_8
+ * @arg @ref LL_RCC_PLLINPUTRANGE_8_16
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL1_SetVCOInputRange(uint32_t InputRange)
+{
+ MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RGE, InputRange << RCC_PLL1CFGR_PLL1RGE_Pos);
+}
+
+/**
+ * @brief Set PLL1 EPOD Prescaler booster input clock
+ * @rmtoll PLL1CFGR PLL1MBOOST LL_RCC_SetPll1EPodPrescaler
+ * @param BoostDiv This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLL1MBOOST_DIV_1
+ * @arg @ref LL_RCC_PLL1MBOOST_DIV_2
+ * @arg @ref LL_RCC_PLL1MBOOST_DIV_4
+ * @arg @ref LL_RCC_PLL1MBOOST_DIV_6
+ * @arg @ref LL_RCC_PLL1MBOOST_DIV_8
+ * @arg @ref LL_RCC_PLL1MBOOST_DIV_10
+ * @arg @ref LL_RCC_PLL1MBOOST_DIV_12
+ * @arg @ref LL_RCC_PLL1MBOOST_DIV_14
+ * @arg @ref LL_RCC_PLL1MBOOST_DIV_16
+ */
+__STATIC_INLINE void LL_RCC_SetPll1EPodPrescaler(uint32_t BoostDiv)
+{
+ MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1MBOOST, BoostDiv);
+}
+
+/**
+ * @brief Get PLL1 EPOD Prescaler booster input clock
+ * @rmtoll PLL1CFGR PLL1MBOOST LL_RCC_GetPll1EPodPrescaler
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLL1MBOOST_DIV_1
+ * @arg @ref LL_RCC_PLL1MBOOST_DIV_2
+ * @arg @ref LL_RCC_PLL1MBOOST_DIV_4
+ * @arg @ref LL_RCC_PLL1MBOOST_DIV_6
+ * @arg @ref LL_RCC_PLL1MBOOST_DIV_8
+ * @arg @ref LL_RCC_PLL1MBOOST_DIV_10
+ * @arg @ref LL_RCC_PLL1MBOOST_DIV_12
+ * @arg @ref LL_RCC_PLL1MBOOST_DIV_14
+ * @arg @ref LL_RCC_PLL1MBOOST_DIV_16
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetPll1EPodPrescaler(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1MBOOST));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_PLL2 PLL2
+ * @{
+ */
+
+/**
+ * @brief Enable PLL2
+ * @rmtoll CR PLL2ON LL_RCC_PLL2_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL2_Enable(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_PLL2ON);
+}
+
+/**
+ * @brief Disable PLL2
+ * @rmtoll CR PLL2ON LL_RCC_PLL2_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL2_Disable(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
+}
+
+/**
+ * @brief Check if PLL2 Ready
+ * @rmtoll CR PLL2RDY LL_RCC_PLL2_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void)
+{
+ return ((READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == RCC_CR_PLL2RDY) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure PLL2 used for 48Mhz domain clock
+ * @note PLL2 Source, PLLM, PLLN and PLLQ can be written only when PLL2 is disabled.
+ * @note This can be selected for USB, SDMMC
+ * @rmtoll PLL2CFGR PLL2SRC LL_RCC_PLL2_ConfigDomain_48M\n
+ * PLL2CFGR PLL2M LL_RCC_PLL2_ConfigDomain_48M\n
+ * PLL2CFGR PLL2N LL_RCC_PLL2_ConfigDomain_48M\n
+ * PLL2CFGR PLL2Q LL_RCC_PLL2_ConfigDomain_48M
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLL2SOURCE_NONE
+ * @arg @ref LL_RCC_PLL2SOURCE_MSIS
+ * @arg @ref LL_RCC_PLL2SOURCE_HSI
+ * @arg @ref LL_RCC_PLL2SOURCE_HSE
+ * @param PLLM parameter can be a value between 1 and 16
+ * @param PLLN parameter can be a value between 4 and 512
+ * @param PLLQ parameter can be a value between 1 and 128
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL2_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
+{
+ MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC | RCC_PLL2CFGR_PLL2M, Source | \
+ ((PLLM - 1UL) << RCC_PLL2CFGR_PLL2M_Pos));
+ MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2N | RCC_PLL2DIVR_PLL2Q, ((PLLN - 1UL) << \
+ RCC_PLL2DIVR_PLL2N_Pos) | ((PLLQ - 1UL) << \
+ RCC_PLL2DIVR_PLL2Q_Pos));
+}
+
+/**
+ * @brief Configure PLL2 used for SAI domain clock
+ * @note PLL1 Source, PLLM, PLLN and PLL2P can be written only when PLL1 is disabled.
+ * @note This can be selected for SAI1 or SAI2
+ * @rmtoll PLLC2FGR PLL2SRC LL_RCC_PLL2_ConfigDomain_SAI\n
+ * PLLC2FGR PLL2M LL_RCC_PLL2_ConfigDomain_SAI\n
+ * PLLC2FGR PLL2N LL_RCC_PLL2_ConfigDomain_SAI\n
+ * PLLC2FGR PLL2P LL_RCC_PLL2_ConfigDomain_SAI
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLL2SOURCE_NONE
+ * @arg @ref LL_RCC_PLL2SOURCE_MSIS
+ * @arg @ref LL_RCC_PLL2SOURCE_HSI
+ * @arg @ref LL_RCC_PLL2SOURCE_HSE
+ * @param PLLM parameter can be a value between 1 and 16
+ * @param PLLN parameter can be a value between 4 and 512
+ * @param PLLP parameter can be a value between 2 and 128
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
+{
+ MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC | RCC_PLL2CFGR_PLL2M, Source | \
+ ((PLLM - 1UL) << RCC_PLL2CFGR_PLL2M_Pos));
+ MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2N | RCC_PLL2DIVR_PLL2P, ((PLLN - 1UL) << \
+ RCC_PLL2DIVR_PLL2N_Pos) | ((PLLP - 1UL) << \
+ RCC_PLL2DIVR_PLL2P_Pos));
+}
+
+/**
+ * @brief Configure PLL2 used for ADC domain clock
+ * @note PLL2SRC/PLL2M/PLL2N/PLL2R can be written only when PLL2 is disabled.
+ * @note This can be selected for ADC
+ * @rmtoll PLL2CFGR PLL2SRC LL_RCC_PLL2_ConfigDomain_ADC\n
+ * PLL2CFGR PLL2M LL_RCC_PLL2_ConfigDomain_ADC\n
+ * PLL2CFGR PLL2N LL_RCC_PLL2_ConfigDomain_ADC\n
+ * PLL2CFGR PLL2R LL_RCC_PLL2_ConfigDomain_ADC
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLL2SOURCE_NONE
+ * @arg @ref LL_RCC_PLL2SOURCE_MSIS
+ * @arg @ref LL_RCC_PLL2SOURCE_HSI
+ * @arg @ref LL_RCC_PLL2SOURCE_HSE
+ * @param PLLM parameter can be a value between 1 and 16
+ * @param PLLR parameter can be a value between 1 and 128
+ * @param PLLN parameter can be a value between 4 and 512
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL2_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
+{
+ MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC | RCC_PLL2CFGR_PLL2M, Source | \
+ ((PLLM - 1UL) << RCC_PLL2CFGR_PLL2M_Pos));
+ MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2N | RCC_PLL2DIVR_PLL2R, ((PLLN - 1UL) << \
+ RCC_PLL2DIVR_PLL2N_Pos) | ((PLLR - 1UL) << \
+ RCC_PLL2DIVR_PLL2R_Pos));
+}
+
+/**
+ * @brief Configure PLL2 clock source
+ * @rmtoll PLL2CFGR PLL2SRC LL_RCC_PLL2_SetSource
+ * @param PLL2Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLL2SOURCE_NONE
+ * @arg @ref LL_RCC_PLL2SOURCE_MSIS
+ * @arg @ref LL_RCC_PLL2SOURCE_HSI
+ * @arg @ref LL_RCC_PLL2SOURCE_HSE
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL2_SetSource(uint32_t PLL2Source)
+{
+ MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC, PLL2Source);
+}
+
+/**
+ * @brief Get the oscillator used as PLL2 clock source.
+ * @rmtoll PLL2CFGR PLL2SRC LL_RCC_PLL2_GetSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLL2SOURCE_NONE
+ * @arg @ref LL_RCC_PLL2SOURCE_MSIS
+ * @arg @ref LL_RCC_PLL2SOURCE_HSI
+ * @arg @ref LL_RCC_PLL2SOURCE_HSE
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_GetSource(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC));
+}
+
+/**
+ * @brief Set Main PLL2 multiplication factor for VCO
+ * @rmtoll PLL2CFGR PLL2N LL_RCC_PLL2_SetN
+ * @param PLL2N parameter can be a value between 4 and 512
+ */
+__STATIC_INLINE void LL_RCC_PLL2_SetN(uint32_t PLL2N)
+{
+ MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2N, (PLL2N - 1UL) << RCC_PLL2DIVR_PLL2N_Pos);
+}
+
+/**
+ * @brief Get Main PLL2 multiplication factor for VCO
+ * @rmtoll PLL2CFGR PLL2N LL_RCC_PLL2_GetN
+ * @retval Between 4 and 512
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_GetN(void)
+{
+ return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2N) >> RCC_PLL2DIVR_PLL2N_Pos) + 1UL);
+}
+
+
+/**
+ * @brief Set Main PLL2 division factor for PLL2P
+ * @note Used for SAI1 and SAI2 clock
+ * @rmtoll PLL2CFGR PLL2P LL_RCC_PLL2_SetP
+ * @param PLL2P parameter can be a value between 2 and 128
+ */
+__STATIC_INLINE void LL_RCC_PLL2_SetP(uint32_t PLL2P)
+{
+ MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2P, (PLL2P - 1UL) << RCC_PLL2DIVR_PLL2P_Pos);
+}
+
+/**
+ * @brief Get Main PLL2 division factor for PLL2P
+ * @note Used for SAI1 and SAI2 clock
+ * @rmtoll PLL2CFGR PLL2P LL_RCC_PLL2_GetP
+ * @retval Between 2 and 128
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_GetP(void)
+{
+ return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2P) >> RCC_PLL2DIVR_PLL2P_Pos) + 1UL);
+}
+
+
+/**
+ * @brief Set Main PLL division factor for PLLQ
+ * @note Used for PLL48M1CLK selected for USB, SDMMC (48 MHz clock)
+ * @rmtoll PLLCFGR PLL2Q LL_RCC_PLL2_SetQ
+ * @param PLL2Q parameter can be a value between 1 and 128
+ */
+__STATIC_INLINE void LL_RCC_PLL2_SetQ(uint32_t PLL2Q)
+{
+ MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2Q, (PLL2Q - 1UL) << RCC_PLL2DIVR_PLL2Q_Pos);
+}
+
+/**
+ * @brief Get Main PLL division factor for PLLQ
+ * @note Used for PLL48M1CLK selected for USB, SDMMC (48 MHz clock)
+ * @rmtoll PLL2CFGR PLL2Q LL_RCC_PLL2_GetQ
+ * @retval Between 1 and 128
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_GetQ(void)
+{
+ return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2Q) >> RCC_PLL2DIVR_PLL2Q_Pos) + 1UL);
+}
+
+/**
+ * @brief Set Main PLL division factor for PLLQ
+ * @note Used for PLL2CLK selected for USB, SDMMC (48 MHz clock)
+ * @rmtoll PLL2CFGR PLL2R LL_RCC_PLL2_SetR
+ * @param PLL2R parameter can be a value between 1 and 128
+ */
+__STATIC_INLINE void LL_RCC_PLL2_SetR(uint32_t PLL2R)
+{
+ MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2R, (PLL2R - 1UL) << RCC_PLL2DIVR_PLL2R_Pos);
+}
+
+/**
+ * @brief Get Main PLL2 division factor for PLL2R
+ * @note Used for PLL2CLK (system clock)
+ * @rmtoll PLL2DIVR PLL2R LL_RCC_PLL2_GetR
+ * @retval Between 1 and 128
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_GetR(void)
+{
+ return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2Q) >> RCC_PLL2DIVR_PLL2Q_Pos) + 1UL);
+}
+
+/**
+ * @brief Set Division factor for the main PLL and other PLL
+ * @rmtoll PLL2CFGR PLL2M LL_RCC_PLL2_SetDivider
+ * @param PLL2M parameter can be a value between 1 and 16
+ */
+__STATIC_INLINE void LL_RCC_PLL2_SetDivider(uint32_t PLL2M)
+{
+ MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2M, (PLL2M - 1UL) << RCC_PLL2CFGR_PLL2M_Pos);
+}
+
+/**
+ * @brief Get Division factor for the main PLL and other PLL
+ * @rmtoll PLL2CFGR PLL2M LL_RCC_PLL2_GetDivider
+ * @retval Between 1 and 16
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_GetDivider(void)
+{
+ return (uint32_t)((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M_Pos) + 1UL);
+}
+
+/**
+ * @brief Enable PLL2 output mapped on SAI domain clock
+ * @rmtoll PLL2CFGR PLL2PEN LL_RCC_PLL2_EnableDomain_SAI
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL2_EnableDomain_SAI(void)
+{
+ SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN);
+}
+
+/**
+ * @brief Disable PLL2 output mapped on SAI domain clock
+ * @note In order to save power, when of the PLL2 is
+ * not used, should be 0
+ * @rmtoll PLL2CFGR PLL2PEN LL_RCC_PLL2_DisableDomain_SAI
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL2_DisableDomain_SAI(void)
+{
+ CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN);
+}
+
+/**
+ * @brief Enable PLL2 output mapped on 48MHz domain clock
+ * @rmtoll PLL2CFGR PLL2QEN LL_RCC_PLL2_EnableDomain_48M
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL2_EnableDomain_48M(void)
+{
+ SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2QEN);
+}
+
+/**
+ * @brief Disable PLL2 output mapped on 48MHz domain clock
+ * @note In order to save power, when of the PLLSAI1 is
+ * not used, should be 0
+ * @rmtoll PLL2CFGR PLL2QEN LL_RCC_PLL2_DisableDomain_48M
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL2_DisableDomain_48M(void)
+{
+ CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2QEN);
+}
+
+/**
+ * @brief Enable PLL2 output mapped on ADC domain clock
+ * @rmtoll PLL2CFGR PLL2REN LL_RCC_PLL2_EnableDomain_ADC
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL2_EnableDomain_ADC(void)
+{
+ SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2REN);
+}
+
+/**
+ * @brief Disable PLL2 output mapped on ADC domain clock
+ * @note In order to save power, when of the PLLSAI1 is
+ * not used, Main PLLSAI1 should be 0
+ * @rmtoll PLL2CFGR PLL2REN LL_RCC_PLL2_DisableDomain_ADC
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL2_DisableDomain_ADC(void)
+{
+ CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2REN);
+}
+
+/**
+ * @brief Enable PLL2 FRACN
+ * @rmtoll PLL2CFGR PLL2FRACEN LL_RCC_PLL2FRACN_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL2FRACN_Enable(void)
+{
+ SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN);
+}
+
+/**
+ * @brief Check if PLL2 FRACN is enabled
+ * @rmtoll PLL2CFGR PLL2FRACEN LL_RCC_PLL2FRACN_IsEnabled
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL2FRACN_IsEnabled(void)
+{
+ return ((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN) == RCC_PLL2CFGR_PLL2FRACEN) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Disable PLL2 FRACN
+ * @rmtoll PLL2CFGR PLL2FRACEN LL_RCC_PLL2FRACN_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL2FRACN_Disable(void)
+{
+ CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN);
+}
+
+/**
+ * @brief Set PLL2 FRACN Coefficient
+ * @rmtoll PLL2FRACR PLL2FRACN LL_RCC_PLL2_SetFRACN
+ * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF)
+ */
+__STATIC_INLINE void LL_RCC_PLL2_SetFRACN(uint32_t FRACN)
+{
+ MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_PLL2FRACN, FRACN << RCC_PLL2FRACR_PLL2FRACN_Pos);
+}
+
+/**
+ * @brief Get PLL2 FRACN Coefficient
+ * @rmtoll PLL2FRACR PLL2FRACN LL_RCC_PLL2_GetFRACN
+ * @retval A value between 0 and 8191 (0x1FFF)
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_GetFRACN(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLL2FRACR, RCC_PLL2FRACR_PLL2FRACN) >> RCC_PLL2FRACR_PLL2FRACN_Pos);
+}
+
+/**
+ * @brief Set PLL2 VCO Input Range
+ * @note This API shall be called only when PLL2 is disabled.
+ * @rmtoll PLL2CFGR PLL2RGE LL_RCC_PLL2_SetVCOInputRange
+ * @param InputRange This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLINPUTRANGE_4_8
+ * @arg @ref LL_RCC_PLLINPUTRANGE_8_16
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL2_SetVCOInputRange(uint32_t InputRange)
+{
+ MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2RGE, InputRange << RCC_PLL2CFGR_PLL2RGE_Pos);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_PLL3 PLL3
+ * @{
+ */
+
+/**
+ * @brief Enable PLL3
+ * @rmtoll CR PLL3ON LL_RCC_PLL3_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL3_Enable(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_PLL3ON);
+}
+
+/**
+ * @brief Disable PLL3
+ * @rmtoll CR PLL3ON LL_RCC_PLL3_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL3_Disable(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
+}
+
+/**
+ * @brief Check if PLL3 Ready
+ * @rmtoll CR PLL3RDY LL_RCC_PLL3_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL3_IsReady(void)
+{
+ return ((READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == RCC_CR_PLL3RDY) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure PLL3 used for SAI domain clock
+ * @note PLL3SRC/PLL3M/PLL3N/PLL3PDIV can be written only when PLL3 is disabled.
+ * @note This can be selected for SAI1 or SAI2
+ * @rmtoll PLL3CFGR PLL3SRC LL_RCC_PLL3_ConfigDomain_SAI\n
+ * PLL3CFGR PLL3M LL_RCC_PLL3_ConfigDomain_SAI\n
+ * PLL3CFGR PLL3N LL_RCC_PLL3_ConfigDomain_SAI\n
+ * PLL3DIVR PLL3P LL_RCC_PLL3_ConfigDomain_SAI
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLL3SOURCE_NONE
+ * @arg @ref LL_RCC_PLL3SOURCE_MSIS
+ * @arg @ref LL_RCC_PLL3SOURCE_HSI
+ * @arg @ref LL_RCC_PLL3SOURCE_HSE
+ * @param PLLM parameter can be a value between 1 and 16
+ * @param PLLN parameter can be a value between 4 and 512
+ * @param PLLP parameter can be a value between 2 and 128
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL3_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
+{
+ MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3SRC | RCC_PLL3CFGR_PLL3M, Source | \
+ ((PLLM - 1UL) << RCC_PLL3CFGR_PLL3M_Pos));
+ MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3N | RCC_PLL3DIVR_PLL3P, ((PLLN - 1UL) << \
+ RCC_PLL3DIVR_PLL3N_Pos) | ((PLLP - 1UL) << \
+ RCC_PLL3DIVR_PLL3P_Pos));
+}
+
+
+/**
+ * @brief Configure PLL3 used for 48Mhz domain clock
+ * @note PLL3 Source, PLLM, PLLN and PLLQ can be written only when PLL3 is disabled.
+ * @note This can be selected for USB, SDMMC
+ * @rmtoll PLL3CFGR PLL3SRC LL_RCC_PLL3_ConfigDomain_48M\n
+ * PLL3CFGR PLL3M LL_RCC_PLL3_ConfigDomain_48M\n
+ * PLL3CFGR PLL3N LL_RCC_PLL3_ConfigDomain_48M\n
+ * PLL3CFGR PLL3Q LL_RCC_PLL3_ConfigDomain_48M
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLL3SOURCE_NONE
+ * @arg @ref LL_RCC_PLL3SOURCE_MSIS
+ * @arg @ref LL_RCC_PLL3SOURCE_HSI
+ * @arg @ref LL_RCC_PLL3SOURCE_HSE
+ * @param PLLM parameter can be a value between 1 and 16
+ * @param PLLN parameter can be a value between 4 and 512
+ * @param PLLQ parameter can be a value between 1 and 128
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL3_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
+{
+ MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3SRC | RCC_PLL3CFGR_PLL3M, Source | \
+ ((PLLM - 1UL) << RCC_PLL3CFGR_PLL3M_Pos));
+ MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3N | RCC_PLL3DIVR_PLL3Q, ((PLLN - 1UL) << \
+ RCC_PLL3DIVR_PLL3N_Pos) | ((PLLQ - 1UL) << \
+ RCC_PLL3DIVR_PLL3Q_Pos));
+}
+
+
+/**
+ * @brief Configure PLL3 clock source
+ * @rmtoll PLL3CFGR PLL3SRC LL_RCC_PLL3_SetSource
+ * @param PLLSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLL3SOURCE_NONE
+ * @arg @ref LL_RCC_PLL3SOURCE_MSIS
+ * @arg @ref LL_RCC_PLL3SOURCE_HSI
+ * @arg @ref LL_RCC_PLL3SOURCE_HSE
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL3_SetSource(uint32_t PLLSource)
+{
+ MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3SRC, PLLSource);
+}
+
+/**
+ * @brief Get the oscillator used as PLL3 clock source.
+ * @rmtoll PLL3CFGR PLL3SRC LL_RCC_PLL3_GetSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLL3SOURCE_NONE
+ * @arg @ref LL_RCC_PLL3SOURCE_MSIS
+ * @arg @ref LL_RCC_PLL3SOURCE_HSI
+ * @arg @ref LL_RCC_PLL3SOURCE_HSE
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL3_GetSource(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3SRC));
+}
+
+/**
+ * @brief Set Main PLL3 multiplication factor for VCO
+ * @rmtoll PLL3CFGR PLL3N LL_RCC_PLL3_SetN
+ * @param PLL3N parameter can be a value between 4 and 512
+ */
+__STATIC_INLINE void LL_RCC_PLL3_SetN(uint32_t PLL3N)
+{
+ MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3N, (PLL3N - 1UL) << RCC_PLL3DIVR_PLL3N_Pos);
+}
+
+/**
+ * @brief Get Main PLL3 multiplication factor for VCO
+ * @rmtoll PLL3CFGR PLL3N LL_RCC_PLL3_GetN
+ * @retval Between 4 and 512
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL3_GetN(void)
+{
+ return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3N) >> RCC_PLL3DIVR_PLL3N_Pos) + 1UL);
+}
+
+
+/**
+ * @brief Set Main PLL3 division factor for PLL3P
+ * @note Used for SAI1 and SAI2 clock
+ * @rmtoll PLL3CFGR PLL3P LL_RCC_PLL3_SetP
+ * @param PLL3P parameter can be a value between 2 and 128
+ */
+__STATIC_INLINE void LL_RCC_PLL3_SetP(uint32_t PLL3P)
+{
+ MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3P, (PLL3P - 1UL) << RCC_PLL3DIVR_PLL3P_Pos);
+}
+
+/**
+ * @brief Get Main PLL3 division factor for PLL3P
+ * @note Used for SAI1 and SAI2 clock
+ * @rmtoll PLL3CFGR PLL3P LL_RCC_PLL3_GetP
+ * @retval Between 2 and 128
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL3_GetP(void)
+{
+ return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3P) >> RCC_PLL3DIVR_PLL3P_Pos) + 1UL);
+}
+
+
+/**
+ * @brief Set Main PLL division factor for PLLQ
+ * @note Used for PLL48M1CLK selected for USB, SDMMC (48 MHz clock)
+ * @rmtoll PLLCFGR PLL3Q LL_RCC_PLL3_SetQ
+ * @param PLL3Q parameter can be a value between 1 and 128
+ */
+__STATIC_INLINE void LL_RCC_PLL3_SetQ(uint32_t PLL3Q)
+{
+ MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3Q, (PLL3Q - 1UL) << RCC_PLL3DIVR_PLL3Q_Pos);
+}
+
+/**
+ * @brief Get Main PLL division factor for PLLQ
+ * @note Used for PLL48M1CLK selected for USB, SDMMC (48 MHz clock)
+ * @rmtoll PLL3CFGR PLL3Q LL_RCC_PLL3_GetQ
+ * @retval Between 1 and 128
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL3_GetQ(void)
+{
+ return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3Q) >> RCC_PLL3DIVR_PLL3Q_Pos) + 1UL);
+}
+
+/**
+ * @brief Set Main PLL division factor for PLLQ
+ * @note Used for PLL3CLK selected for USB, SDMMC (48 MHz clock)
+ * @rmtoll PLL3CFGR PLL3R LL_RCC_PLL3_SetR
+ * @param PLL3R parameter can be a value between 1 and 128
+ */
+__STATIC_INLINE void LL_RCC_PLL3_SetR(uint32_t PLL3R)
+{
+ MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3R, (PLL3R - 1UL) << RCC_PLL3DIVR_PLL3R_Pos);
+}
+
+/**
+ * @brief Get Main PLL3 division factor for PLL3R
+ * @note Used for PLL3CLK (system clock)
+ * @rmtoll PLL3DIVR PLL3R LL_RCC_PLL3_GetR
+ * @retval Between 1 and 128
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL3_GetR(void)
+{
+ return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3R) >> RCC_PLL3DIVR_PLL3R_Pos) + 1UL);
+}
+
+/**
+ * @brief Set Division factor for the main PLL and other PLL
+ * @rmtoll PLL3CFGR PLL3M LL_RCC_PLL3_SetDivider
+ * @param PLL3M parameter can be a value between 1 and 16
+ */
+__STATIC_INLINE void LL_RCC_PLL3_SetDivider(uint32_t PLL3M)
+{
+ MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3M, (PLL3M - 1UL) << RCC_PLL3CFGR_PLL3M_Pos);
+}
+
+/**
+ * @brief Get Division factor for the main PLL and other PLL
+ * @rmtoll PLL3CFGR PLL3M LL_RCC_PLL3_GetDivider
+ * @retval Between 1 and 16
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL3_GetDivider(void)
+{
+ return (uint32_t)((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3M) >> RCC_PLL3CFGR_PLL3M_Pos) + 1UL);
+}
+
+/**
+ * @brief Enable PLL3 output mapped on SAI domain clock
+ * @rmtoll PLL3CFGR PLL3PEN LL_RCC_PLL3_EnableDomain_SAI
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL3_EnableDomain_SAI(void)
+{
+ SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN);
+}
+
+/**
+ * @brief Disable PLL3 output mapped on SAI domain clock
+ * @note In order to save power, when of the PLLSAI2 is
+ * not used, should be 0
+ * @rmtoll PLL3CFGR PLL3PEN LL_RCC_PLL3_DisableDomain_SAI
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL3_DisableDomain_SAI(void)
+{
+ CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN);
+}
+
+/**
+ * @brief Enable PLL2 output mapped on 48MHz domain clock
+ * @rmtoll PLL3CFGR PLL3QEN LL_RCC_PLL3_EnableDomain_48M
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL3_EnableDomain_48M(void)
+{
+ SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3QEN);
+}
+
+/**
+ * @brief Disable PLL3 output mapped on 48MHz domain clock
+ * @note In order to save power, when of the PLL3 is
+ * not used, should be 0
+ * @rmtoll PLL3CFGR PLL3QEN LL_RCC_PLL3_DisableDomain_48M
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL3_DisableDomain_48M(void)
+{
+ CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3QEN);
+}
+
+/**
+ * @brief Enable PLL3 FRACN
+ * @rmtoll PLL3CFGR PLL3FRACEN LL_RCC_PLL3FRACN_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL3FRACN_Enable(void)
+{
+ SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN);
+}
+
+/**
+ * @brief Check if PLL3 FRACN is enabled
+ * @rmtoll PLL3CFGR PLL3FRACEN LL_RCC_PLL3FRACN_IsEnabled
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL3FRACN_IsEnabled(void)
+{
+ return ((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN) == RCC_PLL3CFGR_PLL3FRACEN) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Disable PLL3 FRACN
+ * @rmtoll PLL3CFGR PLL3FRACEN LL_RCC_PLL3FRACN_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL3FRACN_Disable(void)
+{
+ CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN);
+}
+
+/**
+ * @brief Set PLL3 FRACN Coefficient
+ * @rmtoll PLL3FRACR PLL3FRACN LL_RCC_PLL3_SetFRACN
+ * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF)
+ */
+__STATIC_INLINE void LL_RCC_PLL3_SetFRACN(uint32_t FRACN)
+{
+ MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_PLL3FRACN, FRACN << RCC_PLL3FRACR_PLL3FRACN_Pos);
+}
+
+/**
+ * @brief Get PLL3 FRACN Coefficient
+ * @rmtoll PLL3FRACR PLL3FRACN LL_RCC_PLL3_GetFRACN
+ * @retval A value between 0 and 8191 (0x1FFF)
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL3_GetFRACN(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLL3FRACR, RCC_PLL3FRACR_PLL3FRACN) >> RCC_PLL3FRACR_PLL3FRACN_Pos);
+}
+
+/**
+ * @brief Set PLL3 VCO Input Range
+ * @note This API shall be called only when PLL3 is disabled.
+ * @rmtoll PLL3CFGR PLL3RGE LL_RCC_PLL3_SetVCOInputRange
+ * @param InputRange This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLINPUTRANGE_4_8
+ * @arg @ref LL_RCC_PLLINPUTRANGE_8_16
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL3_SetVCOInputRange(uint32_t InputRange)
+{
+ MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3RGE, InputRange << RCC_PLL3CFGR_PLL3RGE_Pos);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_PRIV Privileged mode
+ * @{
+ */
+
+/**
+ * @brief Enable privileged mode
+ * @rmtoll PRIVCFGR SPRIV LL_RCC_EnablePrivilegedMode
+ * @rmtoll PRIVCFGR NSPRIV LL_RCC_EnablePrivilegedMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnablePrivilegedMode(void)
+{
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV);
+#else
+ SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV);
+#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */
+}
+
+/**
+ * @brief Disable Privileged mode
+ * @rmtoll CR PRIV LL_RCC_DisablePrivilegedMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisablePrivilegedMode(void)
+{
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV);
+#else
+ CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV);
+#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */
+}
+
+/**
+ * @brief Check if Privileged mode has been enabled or not
+ * @rmtoll CR PRIV LL_RCC_IsEnabledPrivilegedMode
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledPrivilegedMode(void)
+{
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ return ((READ_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV) == RCC_PRIVCFGR_SPRIV) ? 1UL : 0UL);
+#else
+ return ((READ_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV) == RCC_PRIVCFGR_NSPRIV) ? 1UL : 0UL);
+#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
+ * @{
+ */
+
+/**
+ * @brief Clear LSI ready interrupt flag
+ * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
+{
+ SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
+}
+
+/**
+ * @brief Clear LSE ready interrupt flag
+ * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
+{
+ SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
+}
+
+/**
+ * @brief Clear MSI ready interrupt flag
+ * @rmtoll CICR MSISRDYC LL_RCC_ClearFlag_MSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void)
+{
+ SET_BIT(RCC->CICR, RCC_CICR_MSISRDYC);
+}
+
+/**
+ * @brief Clear HSI ready interrupt flag
+ * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
+{
+ SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
+}
+
+/**
+ * @brief Clear HSE ready interrupt flag
+ * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
+{
+ SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
+}
+
+
+/**
+ * @brief Clear HSI48 ready interrupt flag
+ * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
+{
+ SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
+}
+
+/**
+ * @brief Clear PLL1 ready interrupt flag
+ * @rmtoll CICR PLL1RDYC LL_RCC_ClearFlag_PLL1RDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLL1RDY(void)
+{
+ SET_BIT(RCC->CICR, RCC_CICR_PLL1RDYC);
+}
+
+/**
+ * @brief Clear PLL2 ready interrupt flag
+ * @rmtoll CICR PLL2RDYC LL_RCC_ClearFlag_PLL2RDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void)
+{
+ SET_BIT(RCC->CICR, RCC_CICR_PLL2RDYC);
+}
+
+/**
+ * @brief Clear PLL3 ready interrupt flag
+ * @rmtoll CICR PLL3RDYC LL_RCC_ClearFlag_PLL3RDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLL3RDY(void)
+{
+ SET_BIT(RCC->CICR, RCC_CICR_PLL3RDYC);
+}
+
+/**
+ * @brief Clear Clock security system interrupt flag
+ * @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
+{
+ SET_BIT(RCC->CICR, RCC_CICR_CSSC);
+}
+
+/**
+ * @brief Clear MSIK ready interrupt flag
+ * @rmtoll CICR MSIKRDYC LL_RCC_ClearFlag_MSIKRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_MSIKRDY(void)
+{
+ SET_BIT(RCC->CICR, RCC_CICR_MSIKRDYC);
+}
+
+/**
+ * @brief Clear SHSI ready interrupt flag
+ * @rmtoll CICR SHSIRDYC LL_RCC_ClearFlag_SHSIRDY
+ * @retval None
+ */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+__STATIC_INLINE void LL_RCC_ClearFlag_SHSIRDY(void)
+{
+ SET_BIT(RCC->CICR, RCC_CICR_SHSIRDYC);
+}
+#endif /*(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)*/
+
+
+/**
+ * @brief Check if LSI ready interrupt occurred or not
+ * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
+{
+ return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == RCC_CIFR_LSIRDYF) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if LSE ready interrupt occurred or not
+ * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
+{
+ return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == RCC_CIFR_LSERDYF) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if MSI ready interrupt occurred or not
+ * @rmtoll CIFR MSISRDYF LL_RCC_IsActiveFlag_MSIRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void)
+{
+ return ((READ_BIT(RCC->CIFR, RCC_CIFR_MSISRDYF) == RCC_CIFR_MSISRDYF) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if HSI ready interrupt occurred or not
+ * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
+{
+ return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == RCC_CIFR_HSIRDYF) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if HSE ready interrupt occurred or not
+ * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
+{
+ return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == RCC_CIFR_HSERDYF) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if HSI48 ready interrupt occurred or not
+ * @rmtoll CIFR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
+{
+ return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == RCC_CIFR_HSI48RDYF) ? 1UL : 0UL);
+}
+/**
+ * @brief Check if PLL1 ready interrupt occurred or not
+ * @rmtoll CIFR PLL1RDYF LL_RCC_IsActiveFlag_PLL1RDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL1RDY(void)
+{
+ return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL1RDYF) == RCC_CIFR_PLL1RDYF) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if PLL2 ready interrupt occurred or not
+ * @rmtoll CIFR PLL2RDYF LL_RCC_IsActiveFlag_PLL2RDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void)
+{
+ return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL2RDYF) == RCC_CIFR_PLL2RDYF) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if PLL3 ready interrupt occurred or not
+ * @rmtoll CIFR PLL3RDYF LL_RCC_IsActiveFlag_PLL3RDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL3RDY(void)
+{
+ return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL3RDYF) == RCC_CIFR_PLL3RDYF) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Clock security system interrupt occurred or not
+ * @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
+{
+ return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == RCC_CIFR_CSSF) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Clock security system interrupt occurred or not
+ * @rmtoll CIFR MSIKRDYF LL_RCC_IsActiveFlag_MSIKRDYF
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIKRDY(void)
+{
+ return ((READ_BIT(RCC->CIFR, RCC_CIFR_MSIKRDYF) == RCC_CIFR_MSIKRDYF) ? 1UL : 0UL);
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ * @brief Check if Clock security system interrupt occurred or not
+ * @rmtoll CIFR SHSIRDYF LL_RCC_IsActiveFlag_SHSIRDYF
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SHSIRDY(void)
+{
+ return ((READ_BIT(RCC->CIFR, RCC_CIFR_SHSIRDYF) == RCC_CIFR_SHSIRDYF) ? 1UL : 0UL);
+}
+#endif /*(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)*/
+
+/**
+ * @brief Check if RCC flag Independent Watchdog reset is set or not.
+ * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
+{
+ return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == RCC_CSR_IWDGRSTF) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if RCC flag Low Power reset is set or not.
+ * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
+{
+ return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == RCC_CSR_LPWRRSTF) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if RCC flag is set or not.
+ * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
+{
+ return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == RCC_CSR_OBLRSTF) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if RCC flag Pin reset is set or not.
+ * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
+{
+ return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == RCC_CSR_PINRSTF) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if RCC flag Software reset is set or not.
+ * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
+{
+ return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == RCC_CSR_SFTRSTF) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if RCC flag Window Watchdog reset is set or not.
+ * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
+{
+ return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == RCC_CSR_WWDGRSTF) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if RCC flag BOR reset is set or not.
+ * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
+{
+ return ((READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == RCC_CSR_BORRSTF) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set RMVF bit to clear the reset flags.
+ * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
+{
+ SET_BIT(RCC->CSR, RCC_CSR_RMVF);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_IT_Management IT Management
+ * @{
+ */
+
+/**
+ * @brief Enable LSI ready interrupt
+ * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
+{
+ SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
+}
+
+/**
+ * @brief Enable LSE ready interrupt
+ * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
+{
+ SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
+}
+
+/**
+ * @brief Enable MSI ready interrupt
+ * @rmtoll CIER MSIRDYIE LL_RCC_EnableIT_MSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void)
+{
+ SET_BIT(RCC->CIER, RCC_CIER_MSISRDYIE);
+}
+
+/**
+ * @brief Enable HSI ready interrupt
+ * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
+{
+ SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
+}
+
+/**
+ * @brief Enable HSE ready interrupt
+ * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
+{
+ SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
+}
+
+/**
+ * @brief Enable HSI48 ready interrupt
+ * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
+{
+ SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
+}
+
+/**
+ * @brief Enable PLL1 ready interrupt
+ * @rmtoll CIER PLL1RDYIE LL_RCC_EnableIT_PLL1RDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_PLL1RDY(void)
+{
+ SET_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);
+}
+
+/**
+ * @brief Enable PLL2 ready interrupt
+ * @rmtoll CIER PLL2RDYIE LL_RCC_EnableIT_PLL2RDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void)
+{
+ SET_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE);
+}
+
+/**
+ * @brief Enable PLL3 ready interrupt
+ * @rmtoll CIER PLL3RDYIE LL_RCC_EnableIT_PLL3RDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_PLL3RDY(void)
+{
+ SET_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE);
+}
+
+/**
+ * @brief Enable MSIKRDYIE ready interrupt
+ * @rmtoll CIER MSIKRDYIE LL_RCC_EnableIT_MSIKRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_MSIKRDY(void)
+{
+ SET_BIT(RCC->CIER, RCC_CIER_MSIKRDYIE);
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ * @brief Enable SHSIRDYIE ready interrupt
+ * @rmtoll CIER SHSIRDYIE LL_RCC_EnableIT_SHSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_SHSIRDY(void)
+{
+ SET_BIT(RCC->CIER, RCC_CIER_SHSIRDYIE);
+}
+#endif /*(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)*/
+
+/**
+ * @brief Disable LSI ready interrupt
+ * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
+{
+ CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
+}
+
+/**
+ * @brief Disable LSE ready interrupt
+ * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
+{
+ CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
+}
+
+/**
+ * @brief Disable MSI ready interrupt
+ * @rmtoll CIER MSISRDYIE LL_RCC_DisableIT_MSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void)
+{
+ CLEAR_BIT(RCC->CIER, RCC_CIER_MSISRDYIE);
+}
+
+/**
+ * @brief Disable HSI ready interrupt
+ * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
+{
+ CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
+}
+
+/**
+ * @brief Disable HSE ready interrupt
+ * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
+{
+ CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
+}
+
+/**
+ * @brief Disable HSI48 ready interrupt
+ * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
+{
+ CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
+}
+
+/**
+ * @brief Disable PLL1 ready interrupt
+ * @rmtoll CIER PLL1RDYIE LL_RCC_DisableIT_PLL1RDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_PLL1RDY(void)
+{
+ CLEAR_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);
+}
+
+/**
+ * @brief Disable PLL2 ready interrupt
+ * @rmtoll CIER PLL2RDYIE LL_RCC_DisableIT_PLL2RDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void)
+{
+ CLEAR_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE);
+}
+
+/**
+ * @brief Disable PLL3 ready interrupt
+ * @rmtoll CIER PLL3RDYIE LL_RCC_DisableIT_PLL3RDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_PLL3RDY(void)
+{
+ CLEAR_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE);
+}
+
+/**
+ * @brief Disable MSIKRDYIE ready interrupt
+ * @rmtoll CIER MSIKRDYIE LL_RCC_DisableIT_MSIKRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_MSIKRDY(void)
+{
+ CLEAR_BIT(RCC->CIER, RCC_CIER_MSIKRDYIE);
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ * @brief Disable SHSIRDYIE ready interrupt
+ * @rmtoll CIER SHSIRDYIE LL_RCC_DisableIT_SHSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_SHSIRDY(void)
+{
+ CLEAR_BIT(RCC->CIER, RCC_CIER_SHSIRDYIE);
+}
+#endif /*(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)*/
+
+/**
+ * @brief Checks if LSI ready interrupt source is enabled or disabled.
+ * @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
+{
+ return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Checks if LSE ready interrupt source is enabled or disabled.
+ * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
+{
+ return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Checks if MSI ready interrupt source is enabled or disabled.
+ * @rmtoll CIER MSIRDYIE LL_RCC_IsEnabledIT_MSIRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void)
+{
+ return ((READ_BIT(RCC->CIER, RCC_CIER_MSISRDYIE) == RCC_CIER_MSISRDYIE) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Checks if HSI ready interrupt source is enabled or disabled.
+ * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
+{
+ return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Checks if HSE ready interrupt source is enabled or disabled.
+ * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
+{
+ return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Checks if HSI48 ready interrupt source is enabled or disabled.
+ * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
+{
+ return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE) ? 1UL : 0UL);
+}
+/**
+ * @brief Checks if PLL1 ready interrupt source is enabled or disabled.
+ * @rmtoll CIER PLL1RDYIE LL_RCC_IsEnabledIT_PLL1RDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL1RDY(void)
+{
+ return ((READ_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE) == RCC_CIER_PLL1RDYIE) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Checks if PLL2 ready interrupt source is enabled or disabled.
+ * @rmtoll CIER PLL2RDYIE LL_RCC_IsEnabledIT_PLL2RDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL2RDY(void)
+{
+ return ((READ_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE) == RCC_CIER_PLL2RDYIE) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Checks if PLL3 ready interrupt source is enabled or disabled.
+ * @rmtoll CIER PLL3RDYIE LL_RCC_IsEnabledIT_PLL3RDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL3RDY(void)
+{
+ return ((READ_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE) == RCC_CIER_PLL3RDYIE) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Checks if MSIK ready interrupt source is enabled or disabled.
+ * @rmtoll CIER MSIKRDYIE LL_RCC_IsEnabledIT_MSIKRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIKRDY(void)
+{
+ return ((READ_BIT(RCC->CIER, RCC_CIER_MSIKRDYIE) == RCC_CIER_MSIKRDYIE) ? 1UL : 0UL);
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ * @brief Checks if SHSI ready interrupt source is enabled or disabled.
+ * @rmtoll CIER SHSIRDYIE LL_RCC_IsEnabledIT_SHSIRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_SHSIRDY(void)
+{
+ return ((READ_BIT(RCC->CIER, RCC_CIER_SHSIRDYIE) == RCC_CIER_SHSIRDYIE) ? 1UL : 0UL);
+}
+#endif /*(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)*/
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_Security_Services Security Services
+ * @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ * @brief Configure RCC resources security
+ * @note Only available from secure state when system implements security (TZEN=1)
+ * @rmtoll SECCFGR HSISEC LL_RCC_ConfigSecure\n
+ * SECCFGR HSESEC LL_RCC_ConfigSecure\n
+ * SECCFGR MSISEC LL_RCC_ConfigSecure\n
+ * SECCFGR LSISEC LL_RCC_ConfigSecure\n
+ * SECCFGR LSESEC LL_RCC_ConfigSecure\n
+ * SECCFGR SYSCLKSEC LL_RCC_ConfigSecure\n
+ * SECCFGR PRESCSEC LL_RCC_ConfigSecure\n
+ * SECCFGR PLL1SEC LL_RCC_ConfigSecure\n
+ * SECCFGR PLL2SEC LL_RCC_ConfigSecure\n
+ * SECCFGR PLL3SEC LL_RCC_ConfigSecure\n
+ * SECCFGR CLK48MSEC LL_RCC_ConfigSecure\n
+ * SECCFGR HSI48SEC LL_RCC_ConfigSecure\n
+ * SECCFGR RMVFSEC LL_RCC_ConfigSecure
+ * @param SecureConfig This parameter can be one or a combination of the following values:
+ * @arg @ref LL_RCC_ALL_NSEC & LL_RCC_ALL_SEC
+ * @arg @ref LL_RCC_HSI_SEC & LL_RCC_HSI_NSEC
+ * @arg @ref LL_RCC_HSE_SEC & LL_RCC_HSE_NSEC
+ * @arg @ref LL_RCC_MSI_SEC & LL_RCC_MSI_NSEC
+ * @arg @ref LL_RCC_LSE_SEC & LL_RCC_LSE_NSEC
+ * @arg @ref LL_RCC_LSI_SEC & LL_RCC_LSI_NSEC
+ * @arg @ref LL_RCC_SYSCLK_SEC & LL_RCC_SYSCLK_NSEC
+ * @arg @ref LL_RCC_PRESCALERS_SEC & LL_RCC_PRESCALERS_NSEC
+ * @arg @ref LL_RCC_PLL1_SEC & LL_RCC_PLL1_NSEC
+ * @arg @ref LL_RCC_PLL2_SEC & LL_RCC_PLL2_NSEC
+ * @arg @ref LL_RCC_PLL3_SEC & LL_RCC_PLL3_NSEC
+ * @arg @ref LL_RCC_CLK48M_SEC & LL_RCC_CLK48M_NSEC
+ * @arg @ref LL_RCC_HSI48_SEC & LL_RCC_HSI48_NSEC
+ * @arg @ref LL_RCC_RESET_FLAGS_SEC & LL_RCC_RESET_FLAGS_NSEC
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ConfigSecure(uint32_t SecureConfig)
+{
+ WRITE_REG(RCC->SECCFGR, SecureConfig);
+}
+#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */
+
+/**
+ * @brief Get RCC resources security status
+ * @note Only available from secure state when system implements security (TZEN=1)
+ * @rmtoll SECCFGR HSISEC LL_RCC_GetConfigSecure\n
+ * SECCFGR HSESEC LL_RCC_GetConfigSecure\n
+ * SECCFGR MSISEC LL_RCC_GetConfigSecure\n
+ * SECCFGR LSISEC LL_RCC_GetConfigSecure\n
+ * SECCFGR LSESEC LL_RCC_GetConfigSecure\n
+ * SECCFGR SYSCLKSEC LL_RCC_GetConfigSecure\n
+ * SECCFGR PRESCSEC LL_RCC_GetConfigSecure\n
+ * SECCFGR PLL1SEC LL_RCC_GetConfigSecure\n
+ * SECCFGR PLL2SEC LL_RCC_GetConfigSecure\n
+ * SECCFGR PLL3SEC LL_RCC_GetConfigSecure\n
+ * SECCFGR CLK48MSEC LL_RCC_GetConfigSecure\n
+ * SECCFGR HSI48SEC LL_RCC_GetConfigSecure\n
+ * SECCFGR RMVFSEC LL_RCC_GetConfigSecure
+ * @retval Returned value can be one or a combination of the following values:
+ * @arg @ref LL_RCC_ALL_NSEC & LL_RCC_ALL_SEC
+ * @arg @ref LL_RCC_HSI_SEC & LL_RCC_HSI_NSEC
+ * @arg @ref LL_RCC_HSE_SEC & LL_RCC_HSE_NSEC
+ * @arg @ref LL_RCC_MSI_SEC & LL_RCC_MSI_NSEC
+ * @arg @ref LL_RCC_LSE_SEC & LL_RCC_LSE_NSEC
+ * @arg @ref LL_RCC_LSI_SEC & LL_RCC_LSI_NSEC
+ * @arg @ref LL_RCC_SYSCLK_SEC & LL_RCC_SYSCLK_NSEC
+ * @arg @ref LL_RCC_PRESCALERS_SEC & LL_RCC_PRESCALERS_NSEC
+ * @arg @ref LL_RCC_PLL1_SEC & LL_RCC_PLL1_NSEC
+ * @arg @ref LL_RCC_PLL2_SEC & LL_RCC_PLL2_NSEC
+ * @arg @ref LL_RCC_PLL3_SEC & LL_RCC_PLL3_NSEC
+ * @arg @ref LL_RCC_CLK48M_SEC & LL_RCC_CLK48M_NSEC
+ * @arg @ref LL_RCC_HSI48_SEC & LL_RCC_HSI48_NSEC
+ * @arg @ref LL_RCC_RESET_FLAGS_SEC & LL_RCC_RESET_FLAGS_NSEC
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetConfigSecure(void)
+{
+ return (uint32_t)(READ_BIT(RCC->SECCFGR, RCC_SECURE_MASK));
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_EF_Init De-initialization function
+ * @{
+ */
+ErrorStatus LL_RCC_DeInit(void);
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
+ * @{
+ */
+void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
+uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
+uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
+uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
+uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
+uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
+uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource);
+uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
+uint32_t LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource);
+uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);
+uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
+uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
+uint32_t LL_RCC_GetADCDACClockFreq(uint32_t ADCxSource);
+uint32_t LL_RCC_GetADF1ClockFreq(uint32_t ADF1Source);
+uint32_t LL_RCC_GetMDF1ClockFreq(uint32_t MDF1Source);
+uint32_t LL_RCC_GetDAC1ClockFreq(uint32_t DAC1Source);
+uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource);
+uint32_t LL_RCC_GetSAESClockFreq(uint32_t SAESxSource);
+uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource);
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(RCC) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32u5xx_LL_RCC_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rng.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rng.h
new file mode 100644
index 00000000..0812b0ba
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rng.h
@@ -0,0 +1,714 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_rng.h
+ * @author MCD Application Team
+ * @brief Header file of RNG LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_LL_RNG_H
+#define STM32U5xx_LL_RNG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx.h"
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined (RNG)
+
+/** @defgroup RNG_LL RNG
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RNG_LL_ES_Init_Struct RNG Exported Init structures
+ * @{
+ */
+
+
+/**
+ * @brief LL RNG Init Structure Definition
+ */
+typedef struct
+{
+ uint32_t ClockErrorDetection; /*!< Clock error detection.
+ This parameter can be one value of @ref RNG_LL_CED.
+ This parameter can be modified using unitary
+ functions @ref LL_RNG_EnableClkErrorDetect(). */
+} LL_RNG_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RNG_LL_Exported_Constants RNG Exported Constants
+ * @{
+ */
+
+/** @defgroup RNG_LL_CED Clock Error Detection
+ * @{
+ */
+#define LL_RNG_CED_ENABLE 0x00000000U /*!< Clock error detection enabled */
+#define LL_RNG_CED_DISABLE RNG_CR_CED /*!< Clock error detection disabled */
+/**
+ * @}
+ */
+/** @defgroup RNG_LL_ARDIS Auto reset disable
+ * @{
+ */
+#define LL_RNG_ARDIS_ENABLE 0x00000000U /*!< ARDIS enabled automatic reset to clear SECS bit*/
+#define LL_RNG_ARDIS_DISABLE RNG_CR_ARDIS /*!< ARDIS disabled no automatic reset to clear SECS bit*/
+/**
+ * @}
+ */
+
+/** @defgroup RNG_LL_Clock_Divider_Factor Value used to configure an internal
+ * programmable divider acting on the incoming RNG clock
+ * @{
+ */
+#define LL_RNG_CLKDIV_BY_1 (0x00000000UL) /*!< No clock division */
+#define LL_RNG_CLKDIV_BY_2 (RNG_CR_CLKDIV_0) /*!< 2 RNG clock cycles per internal RNG clock */
+#define LL_RNG_CLKDIV_BY_4 (RNG_CR_CLKDIV_1) /*!< 4 RNG clock cycles per internal RNG clock */
+#define LL_RNG_CLKDIV_BY_8 (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 8 RNG clock cycles per internal RNG clock */
+#define LL_RNG_CLKDIV_BY_16 (RNG_CR_CLKDIV_2) /*!< 16 RNG clock cycles per internal RNG clock */
+#define LL_RNG_CLKDIV_BY_32 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0) /*!< 32 RNG clock cycles per internal RNG clock */
+#define LL_RNG_CLKDIV_BY_64 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1) /*!< 64 RNG clock cycles per internal RNG clock */
+#define LL_RNG_CLKDIV_BY_128 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 128 RNG clock cycles per internal RNG clock */
+#define LL_RNG_CLKDIV_BY_256 (RNG_CR_CLKDIV_3) /*!< 256 RNG clock cycles per internal RNG clock */
+#define LL_RNG_CLKDIV_BY_512 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0) /*!< 512 RNG clock cycles per internal RNG clock */
+#define LL_RNG_CLKDIV_BY_1024 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1) /*!< 1024 RNG clock cycles per internal RNG clock */
+#define LL_RNG_CLKDIV_BY_2048 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 2048 RNG clock cycles per internal RNG clock */
+#define LL_RNG_CLKDIV_BY_4096 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2) /*!< 4096 RNG clock cycles per internal RNG clock */
+#define LL_RNG_CLKDIV_BY_8192 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0) /*!< 8192 RNG clock cycles per internal RNG clock */
+#define LL_RNG_CLKDIV_BY_16384 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1) /*!< 16384 RNG clock cycles per internal RNG clock */
+#define LL_RNG_CLKDIV_BY_32768 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 32768 RNG clock cycles per internal RNG clock */
+/**
+ * @}
+ */
+
+/** @defgroup RNG_LL_NIST_Compliance NIST Compliance configuration
+ * @{
+ */
+#define LL_RNG_NIST_COMPLIANT (0x00000000UL) /*!< Default NIST compliant configuration*/
+#define LL_RNG_CUSTOM_NIST (RNG_CR_NISTC) /*!< Custom NIST configuration */
+
+/**
+ * @}
+ */
+
+/** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_RNG_ReadReg function
+ * @{
+ */
+#define LL_RNG_SR_DRDY RNG_SR_DRDY /*!< Register contains valid random data */
+#define LL_RNG_SR_CECS RNG_SR_CECS /*!< Clock error current status */
+#define LL_RNG_SR_SECS RNG_SR_SECS /*!< Seed error current status */
+#define LL_RNG_SR_CEIS RNG_SR_CEIS /*!< Clock error interrupt status */
+#define LL_RNG_SR_SEIS RNG_SR_SEIS /*!< Seed error interrupt status */
+/**
+ * @}
+ */
+
+/** @defgroup RNG_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros
+ * @{
+ */
+#define LL_RNG_CR_IE RNG_CR_IE /*!< RNG Interrupt enable */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RNG_LL_Exported_Macros RNG Exported Macros
+ * @{
+ */
+
+/** @defgroup RNG_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in RNG register
+ * @param __INSTANCE__ RNG Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in RNG register
+ * @param __INSTANCE__ RNG Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RNG_LL_Exported_Functions RNG Exported Functions
+ * @{
+ */
+/** @defgroup RNG_LL_EF_Configuration RNG Configuration functions
+ * @{
+ */
+
+/**
+ * @brief Enable Random Number Generation
+ * @rmtoll CR RNGEN LL_RNG_Enable
+ * @param RNGx RNG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RNG_Enable(RNG_TypeDef *RNGx)
+{
+ SET_BIT(RNGx->CR, RNG_CR_RNGEN);
+}
+
+/**
+ * @brief Disable Random Number Generation
+ * @rmtoll CR RNGEN LL_RNG_Disable
+ * @param RNGx RNG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx)
+{
+ CLEAR_BIT(RNGx->CR, RNG_CR_RNGEN);
+}
+
+/**
+ * @brief Check if Random Number Generator is enabled
+ * @rmtoll CR RNGEN LL_RNG_IsEnabled
+ * @param RNGx RNG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx)
+{
+ return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable Clock Error Detection
+ * @rmtoll CR CED LL_RNG_EnableClkErrorDetect
+ * @param RNGx RNG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx)
+{
+ CLEAR_BIT(RNGx->CR, RNG_CR_CED);
+}
+
+/**
+ * @brief Disable RNG Clock Error Detection
+ * @rmtoll CR CED LL_RNG_DisableClkErrorDetect
+ * @param RNGx RNG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx)
+{
+ SET_BIT(RNGx->CR, RNG_CR_CED);
+}
+
+/**
+ * @brief Check if RNG Clock Error Detection is enabled
+ * @rmtoll CR CED LL_RNG_IsEnabledClkErrorDetect
+ * @param RNGx RNG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(RNG_TypeDef *RNGx)
+{
+ return ((READ_BIT(RNGx->CR, RNG_CR_CED) != (RNG_CR_CED)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set RNG Conditioning Soft Reset bit
+ * @rmtoll CR CONDRST LL_RNG_EnableCondReset
+ * @param RNGx RNG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RNG_EnableCondReset(RNG_TypeDef *RNGx)
+{
+ SET_BIT(RNGx->CR, RNG_CR_CONDRST);
+}
+
+/**
+ * @brief Reset RNG Conditioning Soft Reset bit
+ * @rmtoll CR CONDRST LL_RNG_DisableCondReset
+ * @param RNGx RNG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RNG_DisableCondReset(RNG_TypeDef *RNGx)
+{
+ CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
+}
+
+/**
+ * @brief Check if RNG Conditioning Soft Reset bit is set
+ * @rmtoll CR CONDRST LL_RNG_IsEnabledCondReset
+ * @param RNGx RNG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RNG_IsEnabledCondReset(RNG_TypeDef *RNGx)
+{
+ return ((READ_BIT(RNGx->CR, RNG_CR_CONDRST) == (RNG_CR_CONDRST)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable RNG Config Lock
+ * @rmtoll CR CONFIGLOCK LL_RNG_ConfigLock
+ * @param RNGx RNG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RNG_ConfigLock(RNG_TypeDef *RNGx)
+{
+ SET_BIT(RNGx->CR, RNG_CR_CONFIGLOCK);
+}
+
+/**
+ * @brief Check if RNG Config Lock is enabled
+ * @rmtoll CR CONFIGLOCK LL_RNG_IsConfigLocked
+ * @param RNGx RNG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RNG_IsConfigLocked(RNG_TypeDef *RNGx)
+{
+ return ((READ_BIT(RNGx->CR, RNG_CR_CONFIGLOCK) == (RNG_CR_CONFIGLOCK)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable NIST Compliance
+ * @rmtoll CR NISTC LL_RNG_EnableNistCompliance
+ * @param RNGx RNG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RNG_EnableNistCompliance(RNG_TypeDef *RNGx)
+{
+ CLEAR_BIT(RNGx->CR, RNG_CR_NISTC);
+}
+
+/**
+ * @brief Disable NIST Compliance
+ * @rmtoll CR NISTC LL_RNG_DisableNistCompliance
+ * @param RNGx RNG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RNG_DisableNistCompliance(RNG_TypeDef *RNGx)
+{
+ SET_BIT(RNGx->CR, RNG_CR_NISTC);
+}
+
+/**
+ * @brief Check if NIST Compliance is enabled
+ * @rmtoll CR NISTC LL_RNG_IsEnabledNistCompliance
+ * @param RNGx RNG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RNG_IsEnabledNistCompliance(RNG_TypeDef *RNGx)
+{
+ return ((READ_BIT(RNGx->CR, RNG_CR_NISTC) != (RNG_CR_NISTC)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set RNG Config1 Configuration field value
+ * @rmtoll CR RNG_CONFIG1 LL_RNG_SetConfig1
+ * @param RNGx RNG Instance
+ * @param Config1 Value between 0 and 0x3F
+ * @retval None
+ */
+__STATIC_INLINE void LL_RNG_SetConfig1(RNG_TypeDef *RNGx, uint32_t Config1)
+{
+ MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG1, Config1 << RNG_CR_RNG_CONFIG1_Pos);
+}
+
+/**
+ * @brief Get RNG Config1 Configuration field value
+ * @rmtoll CR RNG_CONFIG1 LL_RNG_GetConfig1
+ * @param RNGx RNG Instance
+ * @retval Returned Value expressed on 6 bits : Value between 0 and 0x3F
+ */
+__STATIC_INLINE uint32_t LL_RNG_GetConfig1(RNG_TypeDef *RNGx)
+{
+ return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG1) >> RNG_CR_RNG_CONFIG1_Pos);
+}
+
+/**
+ * @brief Set RNG Config2 Configuration field value
+ * @rmtoll CR RNG_CONFIG2 LL_RNG_SetConfig2
+ * @param RNGx RNG Instance
+ * @param Config2 Value between 0 and 0x7
+ * @retval None
+ */
+__STATIC_INLINE void LL_RNG_SetConfig2(RNG_TypeDef *RNGx, uint32_t Config2)
+{
+ MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG2, Config2 << RNG_CR_RNG_CONFIG2_Pos);
+}
+
+/**
+ * @brief Get RNG Config2 Configuration field value
+ * @rmtoll CR RNG_CONFIG2 LL_RNG_GetConfig2
+ * @param RNGx RNG Instance
+ * @retval Returned Value expressed on 3 bits : Value between 0 and 0x7
+ */
+__STATIC_INLINE uint32_t LL_RNG_GetConfig2(RNG_TypeDef *RNGx)
+{
+ return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG2) >> RNG_CR_RNG_CONFIG2_Pos);
+}
+
+/**
+ * @brief Set RNG Config3 Configuration field value
+ * @rmtoll CR RNG_CONFIG3 LL_RNG_SetConfig3
+ * @param RNGx RNG Instance
+ * @param Config3 Value between 0 and 0xF
+ * @retval None
+ */
+__STATIC_INLINE void LL_RNG_SetConfig3(RNG_TypeDef *RNGx, uint32_t Config3)
+{
+ MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG3, Config3 << RNG_CR_RNG_CONFIG3_Pos);
+}
+
+/**
+ * @brief Get RNG Config3 Configuration field value
+ * @rmtoll CR RNG_CONFIG3 LL_RNG_GetConfig3
+ * @param RNGx RNG Instance
+ * @retval Returned Value expressed on 4 bits : Value between 0 and 0xF
+ */
+__STATIC_INLINE uint32_t LL_RNG_GetConfig3(RNG_TypeDef *RNGx)
+{
+ return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG3) >> RNG_CR_RNG_CONFIG3_Pos);
+}
+
+/**
+ * @brief Set RNG Clock divider factor
+ * @rmtoll CR CLKDIV LL_RNG_SetClockDivider
+ * @param RNGx RNG Instance
+ * @param Divider can be one of the following values:
+ * @arg @ref LL_RNG_CLKDIV_BY_1
+ * @arg @ref LL_RNG_CLKDIV_BY_2
+ * @arg @ref LL_RNG_CLKDIV_BY_4
+ * @arg @ref LL_RNG_CLKDIV_BY_8
+ * @arg @ref LL_RNG_CLKDIV_BY_16
+ * @arg @ref LL_RNG_CLKDIV_BY_32
+ * @arg @ref LL_RNG_CLKDIV_BY_64
+ * @arg @ref LL_RNG_CLKDIV_BY_128
+ * @arg @ref LL_RNG_CLKDIV_BY_256
+ * @arg @ref LL_RNG_CLKDIV_BY_512
+ * @arg @ref LL_RNG_CLKDIV_BY_1024
+ * @arg @ref LL_RNG_CLKDIV_BY_2048
+ * @arg @ref LL_RNG_CLKDIV_BY_4096
+ * @arg @ref LL_RNG_CLKDIV_BY_8192
+ * @arg @ref LL_RNG_CLKDIV_BY_16384
+ * @arg @ref LL_RNG_CLKDIV_BY_32768
+ * @retval None
+ */
+__STATIC_INLINE void LL_RNG_SetClockDivider(RNG_TypeDef *RNGx, uint32_t Divider)
+{
+ MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV, Divider << RNG_CR_CLKDIV_Pos);
+}
+
+/**
+ * @brief Get RNG Clock divider factor
+ * @rmtoll CR CLKDIV LL_RNG_GetClockDivider
+ * @param RNGx RNG Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RNG_CLKDIV_BY_1
+ * @arg @ref LL_RNG_CLKDIV_BY_2
+ * @arg @ref LL_RNG_CLKDIV_BY_4
+ * @arg @ref LL_RNG_CLKDIV_BY_8
+ * @arg @ref LL_RNG_CLKDIV_BY_16
+ * @arg @ref LL_RNG_CLKDIV_BY_32
+ * @arg @ref LL_RNG_CLKDIV_BY_64
+ * @arg @ref LL_RNG_CLKDIV_BY_128
+ * @arg @ref LL_RNG_CLKDIV_BY_256
+ * @arg @ref LL_RNG_CLKDIV_BY_512
+ * @arg @ref LL_RNG_CLKDIV_BY_1024
+ * @arg @ref LL_RNG_CLKDIV_BY_2048
+ * @arg @ref LL_RNG_CLKDIV_BY_4096
+ * @arg @ref LL_RNG_CLKDIV_BY_8192
+ * @arg @ref LL_RNG_CLKDIV_BY_16384
+ * @arg @ref LL_RNG_CLKDIV_BY_32768
+ */
+__STATIC_INLINE uint32_t LL_RNG_GetClockDivider(RNG_TypeDef *RNGx)
+{
+ return (uint32_t)READ_BIT(RNGx->CR, RNG_CR_CLKDIV);
+}
+/**
+ * @}
+ */
+
+/** @defgroup RNG_LL_EF_FLAG_Management FLAG Management
+ * @{
+ */
+
+/**
+ * @brief Indicate if the RNG Data ready Flag is set or not
+ * @rmtoll SR DRDY LL_RNG_IsActiveFlag_DRDY
+ * @param RNGx RNG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx)
+{
+ return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate if the Clock Error Current Status Flag is set or not
+ * @rmtoll SR CECS LL_RNG_IsActiveFlag_CECS
+ * @param RNGx RNG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx)
+{
+ return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate if the Seed Error Current Status Flag is set or not
+ * @rmtoll SR SECS LL_RNG_IsActiveFlag_SECS
+ * @param RNGx RNG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx)
+{
+ return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate if the Clock Error Interrupt Status Flag is set or not
+ * @rmtoll SR CEIS LL_RNG_IsActiveFlag_CEIS
+ * @param RNGx RNG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx)
+{
+ return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate if the Seed Error Interrupt Status Flag is set or not
+ * @rmtoll SR SEIS LL_RNG_IsActiveFlag_SEIS
+ * @param RNGx RNG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef *RNGx)
+{
+ return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear Clock Error interrupt Status (CEIS) Flag
+ * @rmtoll SR CEIS LL_RNG_ClearFlag_CEIS
+ * @param RNGx RNG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RNG_ClearFlag_CEIS(RNG_TypeDef *RNGx)
+{
+ WRITE_REG(RNGx->SR, ~RNG_SR_CEIS);
+}
+
+/**
+ * @brief Clear Seed Error interrupt Status (SEIS) Flag
+ * @rmtoll SR SEIS LL_RNG_ClearFlag_SEIS
+ * @param RNGx RNG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RNG_ClearFlag_SEIS(RNG_TypeDef *RNGx)
+{
+ WRITE_REG(RNGx->SR, ~RNG_SR_SEIS);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RNG_LL_EF_IT_Management IT Management
+ * @{
+ */
+
+/**
+ * @brief Enable Random Number Generator Interrupt
+ * (applies for either Seed error, Clock Error or Data ready interrupts)
+ * @rmtoll CR IE LL_RNG_EnableIT
+ * @param RNGx RNG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RNG_EnableIT(RNG_TypeDef *RNGx)
+{
+ SET_BIT(RNGx->CR, RNG_CR_IE);
+}
+
+/**
+ * @brief Disable Random Number Generator Interrupt
+ * (applies for either Seed error, Clock Error or Data ready interrupts)
+ * @rmtoll CR IE LL_RNG_DisableIT
+ * @param RNGx RNG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx)
+{
+ CLEAR_BIT(RNGx->CR, RNG_CR_IE);
+}
+
+/**
+ * @brief Check if Random Number Generator Interrupt is enabled
+ * (applies for either Seed error, Clock Error or Data ready interrupts)
+ * @rmtoll CR IE LL_RNG_IsEnabledIT
+ * @param RNGx RNG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx)
+{
+ return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RNG_LL_EF_Data_Management Data Management
+ * @{
+ */
+
+/**
+ * @brief Return32-bit Random Number value
+ * @rmtoll DR RNDATA LL_RNG_ReadRandData32
+ * @param RNGx RNG Instance
+ * @retval Generated 32-bit random value
+ */
+__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx)
+{
+ return (uint32_t)(READ_REG(RNGx->DR));
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @brief Enable Auto reset
+ * @rmtoll CR ARDIS LL_RNG_EnableArdis
+ * @param RNGx RNG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RNG_EnableArdis(RNG_TypeDef *RNGx)
+{
+ CLEAR_BIT(RNGx->CR, RNG_CR_ARDIS);
+}
+
+/**
+ * @brief Disable Auto reset
+ * @rmtoll CR ARDIS LL_RNG_DisableArdis
+ * @param RNGx RNG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RNG_DisableArdis(RNG_TypeDef *RNGx)
+{
+ SET_BIT(RNGx->CR, RNG_CR_ARDIS);
+}
+
+/**
+ * @brief Check if RNG Auto reset is enabled
+ * @rmtoll CR ARDIS LL_RNG_IsEnabledArdis
+ * @param RNGx RNG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RNG_IsEnabledArdis(RNG_TypeDef *RNGx)
+{
+ return ((READ_BIT(RNGx->CR, RNG_CR_ARDIS) != (RNG_CR_ARDIS)) ? 1UL : 0UL);
+}
+
+/** @defgroup RNG_LL_EF_Health_Test_Control Health Test Control
+ * @{
+ */
+
+/**
+ * @brief Set RNG Health Test Control
+ * @rmtoll HTCR HTCFG LL_RNG_SetHealthConfig
+ * @param RNGx RNG Instance
+ * @param HTCFG can be values of 32 bits
+ * @retval None
+ */
+__STATIC_INLINE void LL_RNG_SetHealthConfig(RNG_TypeDef *RNGx, uint32_t HTCFG)
+{
+ WRITE_REG(RNGx->HTCR, HTCFG);
+}
+
+/**
+ * @brief Get RNG Health Test Control
+ * @rmtoll HTCR HTCFG LL_RNG_GetHealthConfig
+ * @param RNGx RNG Instance
+ * @retval Return 32-bit RNG Health Test configuration
+ */
+__STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(RNG_TypeDef *RNGx)
+{
+ return (uint32_t)READ_REG(RNGx->HTCR);
+}
+
+/**
+ * @}
+ */
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct);
+void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct);
+ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* RNG */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32U5xx_LL_RNG_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rtc.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rtc.h
new file mode 100644
index 00000000..32c93961
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rtc.h
@@ -0,0 +1,5927 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_rtc.h
+ * @author MCD Application Team
+ * @brief Header file of RTC LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_LL_RTC_H
+#define STM32U5xx_LL_RTC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx.h"
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined(RTC)
+
+/** @defgroup RTC_LL RTC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RTC_LL_Private_Constants RTC Private Constants
+ * @{
+ */
+/* Masks Definition */
+#define RTC_LL_INIT_MASK 0xFFFFFFFFU
+#define RTC_LL_RSF_MASK 0xFFFFFF5FU
+
+/* Write protection defines */
+#define RTC_WRITE_PROTECTION_DISABLE (uint8_t)0xFF
+#define RTC_WRITE_PROTECTION_ENABLE_1 (uint8_t)0xCA
+#define RTC_WRITE_PROTECTION_ENABLE_2 (uint8_t)0x53
+
+/* Defines used to combine date & time */
+#define RTC_OFFSET_WEEKDAY 24U
+#define RTC_OFFSET_DAY 16U
+#define RTC_OFFSET_MONTH 8U
+#define RTC_OFFSET_HOUR 16U
+#define RTC_OFFSET_MINUTE 8U
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RTC_LL_Private_Macros RTC Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+#if !defined (UNUSED)
+#define UNUSED(x) ((void)(x))
+#endif /* !defined (UNUSED) */
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RTC_LL_ES_INIT RTC Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief RTC Init structures definition
+ */
+typedef struct
+{
+ uint32_t HourFormat; /*!< Specifies the RTC Hours Format.
+ This parameter can be a value of @ref RTC_LL_EC_HOURFORMAT
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RTC_SetHourFormat(). */
+
+ uint32_t AsynchPrescaler; /*!< Specifies the RTC Asynchronous Predivider value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RTC_SetAsynchPrescaler(). */
+
+ uint32_t SynchPrescaler; /*!< Specifies the RTC Synchronous Predivider value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RTC_SetSynchPrescaler(). */
+} LL_RTC_InitTypeDef;
+
+/**
+ * @brief RTC Time structure definition
+ */
+typedef struct
+{
+ uint32_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
+ This parameter can be a value of @ref RTC_LL_EC_TIME_FORMAT
+ This feature can be modified afterwards using unitary function
+ @ref LL_RTC_TIME_SetFormat(). */
+
+ uint8_t Hours; /*!< Specifies the RTC Time Hours.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the
+ @ref LL_RTC_TIME_FORMAT_PM is selected.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the
+ @ref LL_RTC_TIME_FORMAT_AM_OR_24 is selected.
+ This feature can be modified afterwards using unitary function
+ @ref LL_RTC_TIME_SetHour(). */
+
+ uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 59
+ This feature can be modified afterwards using unitary function
+ @ref LL_RTC_TIME_SetMinute(). */
+
+ uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 59
+ This feature can be modified afterwards using unitary function
+ @ref LL_RTC_TIME_SetSecond(). */
+} LL_RTC_TimeTypeDef;
+
+/**
+ * @brief RTC Date structure definition
+ */
+typedef struct
+{
+ uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.
+ This parameter can be a value of @ref RTC_LL_EC_WEEKDAY
+ This feature can be modified afterwards using unitary function
+ @ref LL_RTC_DATE_SetWeekDay(). */
+
+ uint8_t Month; /*!< Specifies the RTC Date Month.
+ This parameter can be a value of @ref RTC_LL_EC_MONTH
+ This feature can be modified afterwards using unitary function
+ @ref LL_RTC_DATE_SetMonth(). */
+
+ uint8_t Day; /*!< Specifies the RTC Date Day.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 31
+ This feature can be modified afterwards using unitary function
+ @ref LL_RTC_DATE_SetDay(). */
+
+ uint8_t Year; /*!< Specifies the RTC Date Year.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 99
+ This feature can be modified afterwards using unitary function
+ @ref LL_RTC_DATE_SetYear(). */
+} LL_RTC_DateTypeDef;
+
+/**
+ * @brief RTC Alarm structure definition
+ */
+typedef struct
+{
+ LL_RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members. */
+
+ uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
+ This parameter can be a value of @ref RTC_LL_EC_ALMA_MASK for ALARM A or
+ @ref RTC_LL_EC_ALMB_MASK for ALARM B.
+ This feature can be modified afterwards using unitary function
+ @ref LL_RTC_ALMA_SetMask() for ALARM A
+ or @ref LL_RTC_ALMB_SetMask() for ALARM B
+ */
+
+ uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on day or WeekDay.
+ This parameter can be a value of @ref RTC_LL_EC_ALMA_WEEKDAY_SELECTION
+ for ALARM A or @ref RTC_LL_EC_ALMB_WEEKDAY_SELECTION for ALARM B
+ This feature can be modified afterwards using unitary function
+ @ref LL_RTC_ALMA_EnableWeekday() or @ref LL_RTC_ALMA_DisableWeekday()
+ for ALARM A or @ref LL_RTC_ALMB_EnableWeekday() or
+ @ref LL_RTC_ALMB_DisableWeekday() for ALARM B
+ */
+
+ uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Day/WeekDay.
+ If AlarmDateWeekDaySel set to day, this parameter must be a number
+ between Min_Data = 1 and Max_Data = 31.
+ This feature can be modified afterwards using unitary function
+ @ref LL_RTC_ALMA_SetDay()
+ for ALARM A or @ref LL_RTC_ALMB_SetDay() for ALARM B.
+ If AlarmDateWeekDaySel set to Weekday, this parameter can be a value of
+ @ref RTC_LL_EC_WEEKDAY.
+ This feature can be modified afterwards using unitary function
+ @ref LL_RTC_ALMA_SetWeekDay()
+ for ALARM A or @ref LL_RTC_ALMB_SetWeekDay() for ALARM B.
+ */
+} LL_RTC_AlarmTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RTC_LL_Exported_Constants RTC Exported Constants
+ * @{
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RTC_LL_EC_FORMAT FORMAT
+ * @{
+ */
+#define LL_RTC_FORMAT_BIN 0x00000000U /*!< Binary data format */
+#define LL_RTC_FORMAT_BCD 0x00000001U /*!< BCD data format */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_ALMA_WEEKDAY_SELECTION RTC Alarm A Date WeekDay
+ * @{
+ */
+#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE 0x00000000U /*!< Alarm A Date is selected */
+#define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL /*!< Alarm A WeekDay is selected */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_ALMB_WEEKDAY_SELECTION RTC Alarm B Date WeekDay
+ * @{
+ */
+#define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE 0x00000000U /*!< Alarm B Date is selected */
+#define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL /*!< Alarm B WeekDay is selected */
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup RTC_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_RTC_ReadReg function
+ * @{
+ */
+#define LL_RTC_SCR_SSRUF RTC_SCR_CSSRUF
+#define LL_RTC_SCR_ITSF RTC_SCR_CITSF
+#define LL_RTC_SCR_TSOVF RTC_SCR_CTSOVF
+#define LL_RTC_SCR_TSF RTC_SCR_CTSF
+#define LL_RTC_SCR_WUTF RTC_SCR_CWUTF
+#define LL_RTC_SCR_ALRBF RTC_SCR_CALRBF
+#define LL_RTC_SCR_ALRAF RTC_SCR_CALRAF
+
+#define LL_RTC_ICSR_RECALPF RTC_ICSR_RECALPF
+#define LL_RTC_ICSR_BCDU_2 RTC_ICSR_BCDU_2
+#define LL_RTC_ICSR_BCDU_1 RTC_ICSR_BCDU_1
+#define LL_RTC_ICSR_BCDU_0 RTC_ICSR_BCDU_0
+#define LL_RTC_ICSR_BIN_1 RTC_ICSR_BIN_1
+#define LL_RTC_ICSR_BIN_0 RTC_ICSR_BIN_0
+#define LL_RTC_ICSR_INITF RTC_ICSR_INITF
+#define LL_RTC_ICSR_RSF RTC_ICSR_RSF
+#define LL_RTC_ICSR_INITS RTC_ICSR_INITS
+#define LL_RTC_ICSR_SHPF RTC_ICSR_SHPF
+#define LL_RTC_ICSR_WUTWF RTC_ICSR_WUTWF
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_RTC_ReadReg and LL_RTC_WriteReg functions
+ * @{
+ */
+#define LL_RTC_CR_TSIE RTC_CR_TSIE
+#define LL_RTC_CR_WUTIE RTC_CR_WUTIE
+#define LL_RTC_CR_ALRBIE RTC_CR_ALRBIE
+#define LL_RTC_CR_ALRAIE RTC_CR_ALRAIE
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_WEEKDAY WEEK DAY
+ * @{
+ */
+#define LL_RTC_WEEKDAY_MONDAY (uint8_t)0x01 /*!< Monday */
+#define LL_RTC_WEEKDAY_TUESDAY (uint8_t)0x02 /*!< Tuesday */
+#define LL_RTC_WEEKDAY_WEDNESDAY (uint8_t)0x03 /*!< Wednesday */
+#define LL_RTC_WEEKDAY_THURSDAY (uint8_t)0x04 /*!< Thrusday */
+#define LL_RTC_WEEKDAY_FRIDAY (uint8_t)0x05 /*!< Friday */
+#define LL_RTC_WEEKDAY_SATURDAY (uint8_t)0x06 /*!< Saturday */
+#define LL_RTC_WEEKDAY_SUNDAY (uint8_t)0x07 /*!< Sunday */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_MONTH MONTH
+ * @{
+ */
+#define LL_RTC_MONTH_JANUARY (uint8_t)0x01 /*!< January */
+#define LL_RTC_MONTH_FEBRUARY (uint8_t)0x02 /*!< February */
+#define LL_RTC_MONTH_MARCH (uint8_t)0x03 /*!< March */
+#define LL_RTC_MONTH_APRIL (uint8_t)0x04 /*!< April */
+#define LL_RTC_MONTH_MAY (uint8_t)0x05 /*!< May */
+#define LL_RTC_MONTH_JUNE (uint8_t)0x06 /*!< June */
+#define LL_RTC_MONTH_JULY (uint8_t)0x07 /*!< July */
+#define LL_RTC_MONTH_AUGUST (uint8_t)0x08 /*!< August */
+#define LL_RTC_MONTH_SEPTEMBER (uint8_t)0x09 /*!< September */
+#define LL_RTC_MONTH_OCTOBER (uint8_t)0x10 /*!< October */
+#define LL_RTC_MONTH_NOVEMBER (uint8_t)0x11 /*!< November */
+#define LL_RTC_MONTH_DECEMBER (uint8_t)0x12 /*!< December */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_HOURFORMAT HOUR FORMAT
+ * @{
+ */
+#define LL_RTC_HOURFORMAT_24HOUR 0x00000000U /*!< 24 hour/day format */
+#define LL_RTC_HOURFORMAT_AMPM RTC_CR_FMT /*!< AM/PM hour format */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_ALARMOUT ALARM OUTPUT
+ * @{
+ */
+#define LL_RTC_ALARMOUT_DISABLE 0x00000000U /*!< Output disabled */
+#define LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0 /*!< Alarm A output enabled */
+#define LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1 /*!< Alarm B output enabled */
+#define LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL /*!< Wakeup output enabled */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE ALARM OUTPUT TYPE
+ * @{
+ */
+#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN 0x00000000U /*!< RTC_ALARM is open-drain output */
+#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL RTC_CR_TAMPALRM_TYPE /*!< RTC_ALARM is push-pull output */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_OUTPUTPOLARITY_PIN OUTPUT POLARITY PIN
+ * @{
+ */
+#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH 0x00000000U /*!< Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)*/
+#define LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL /*!< Pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL) */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_TIME_FORMAT TIME FORMAT
+ * @{
+ */
+#define LL_RTC_TIME_FORMAT_AM_OR_24 0x00000000U /*!< AM or 24-hour format */
+#define LL_RTC_TIME_FORMAT_PM RTC_TR_PM /*!< PM */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_SHIFT_SECOND SHIFT SECOND
+ * @{
+ */
+#define LL_RTC_SHIFT_SECOND_DELAY 0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */
+#define LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_ALMA_MASK ALARMA MASK
+ * @{
+ */
+#define LL_RTC_ALMA_MASK_NONE 0x00000000U /*!< No masks applied on Alarm A*/
+#define LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4 /*!< Date/day do not care in Alarm A comparison */
+#define LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3 /*!< Hours do not care in Alarm A comparison */
+#define LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2 /*!< Minutes do not care in Alarm A comparison */
+#define LL_RTC_ALMA_MASK_SECONDS RTC_ALRMAR_MSK1 /*!< Seconds do not care in Alarm A comparison */
+#define LL_RTC_ALMA_MASK_ALL (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1) /*!< Masks all */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_ALMA_TIME_FORMAT ALARMA TIME FORMAT
+ * @{
+ */
+#define LL_RTC_ALMA_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */
+#define LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM /*!< PM */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_ALMA_SUBSECONDBIN_AUTOCLR RTC Alarm Sub Seconds with binary mode auto clear Definitions
+ * @{
+ */
+#define LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_NO 0UL /*!< The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running. */
+#define LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_YES RTC_ALRMASSR_SSCLR /*!< The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRMABINR -> SS[31:0] value and is automatically reloaded with 0xFFFF FFFF when reaching RTC_ALRMABINR -> SS[31:0]. */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_ALMB_MASK ALARMB MASK
+ * @{
+ */
+#define LL_RTC_ALMB_MASK_NONE 0x00000000U /*!< No masks applied on Alarm B*/
+#define LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4 /*!< Date/day do not care in Alarm B comparison */
+#define LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3 /*!< Hours do not care in Alarm B comparison */
+#define LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2 /*!< Minutes do not care in Alarm B comparison */
+#define LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1 /*!< Seconds do not care in Alarm B comparison */
+#define LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1) /*!< Masks all */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_ALMB_TIME_FORMAT ALARMB TIME FORMAT
+ * @{
+ */
+#define LL_RTC_ALMB_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */
+#define LL_RTC_ALMB_TIME_FORMAT_PM RTC_ALRMBR_PM /*!< PM */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_ALMB_SUBSECONDBIN_AUTOCLR Alarm Sub Seconds with binary mode auto clear Definitions
+ * @{
+ */
+#define LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_NO 0UL /*!< The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running. */
+#define LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_YES RTC_ALRMBSSR_SSCLR /*!< The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRMABINR -> SS[31:0] value and is automatically reloaded with 0xFFFF FFFF when reaching RTC_ALRMABINR -> SS[31:0]. */
+/**
+ * @}
+ */
+/** @defgroup RTC_LL_EC_TIMESTAMP_EDGE TIMESTAMP EDGE
+ * @{
+ */
+#define LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U /*!< RTC_TS input rising edge generates a time-stamp event */
+#define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE /*!< RTC_TS input falling edge generates a time-stamp even */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_TS_TIME_FORMAT TIMESTAMP TIME FORMAT
+ * @{
+ */
+#define LL_RTC_TS_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */
+#define LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM /*!< PM */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_TAMPER TAMPER
+ * @{
+ */
+#define LL_RTC_TAMPER_1 TAMP_CR1_TAMP1E /*!< Tamper 1 input detection */
+#define LL_RTC_TAMPER_2 TAMP_CR1_TAMP2E /*!< Tamper 2 input detection */
+#define LL_RTC_TAMPER_3 TAMP_CR1_TAMP3E /*!< Tamper 3 input detection */
+#define LL_RTC_TAMPER_4 TAMP_CR1_TAMP4E /*!< Tamper 4 input detection */
+#define LL_RTC_TAMPER_5 TAMP_CR1_TAMP5E /*!< Tamper 5 input detection */
+#define LL_RTC_TAMPER_6 TAMP_CR1_TAMP6E /*!< Tamper 6 input detection */
+#define LL_RTC_TAMPER_7 TAMP_CR1_TAMP7E /*!< Tamper 7 input detection */
+#define LL_RTC_TAMPER_8 TAMP_CR1_TAMP8E /*!< Tamper 8 input detection */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_TAMPER_MASK TAMPER MASK
+ * @{
+ */
+#define LL_RTC_TAMPER_MASK_TAMPER1 TAMP_CR2_TAMP1MSK /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */
+#define LL_RTC_TAMPER_MASK_TAMPER2 TAMP_CR2_TAMP2MSK /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */
+#define LL_RTC_TAMPER_MASK_TAMPER3 TAMP_CR2_TAMP3MSK /*!< Tamper 3 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_TAMPER_NOERASE TAMPER NO ERASE
+ * @{
+ */
+#define LL_RTC_TAMPER_NOERASE_TAMPER1 TAMP_CR2_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */
+#define LL_RTC_TAMPER_NOERASE_TAMPER2 TAMP_CR2_TAMP2NOERASE /*!< Tamper 2 event does not erase the backup registers. */
+#define LL_RTC_TAMPER_NOERASE_TAMPER3 TAMP_CR2_TAMP3NOERASE /*!< Tamper 3 event does not erase the backup registers. */
+#define LL_RTC_TAMPER_NOERASE_TAMPER4 TAMP_CR2_TAMP4NOERASE /*!< Tamper 4 event does not erase the backup registers. */
+#define LL_RTC_TAMPER_NOERASE_TAMPER5 TAMP_CR2_TAMP5NOERASE /*!< Tamper 5 event does not erase the backup registers. */
+#define LL_RTC_TAMPER_NOERASE_TAMPER6 TAMP_CR2_TAMP6NOERASE /*!< Tamper 6 event does not erase the backup registers. */
+#define LL_RTC_TAMPER_NOERASE_TAMPER7 TAMP_CR2_TAMP7NOERASE /*!< Tamper 7 event does not erase the backup registers. */
+#define LL_RTC_TAMPER_NOERASE_TAMPER8 TAMP_CR2_TAMP8NOERASE /*!< Tamper 8 event does not erase the backup registers. */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_TAMPER_DURATION TAMPER DURATION
+ * @{
+ */
+#define LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */
+#define LL_RTC_TAMPER_DURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */
+#define LL_RTC_TAMPER_DURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */
+#define LL_RTC_TAMPER_DURATION_8RTCCLK TAMP_FLTCR_TAMPPRCH /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_TAMPER_FILTER TAMPER FILTER
+ * @{
+ */
+#define LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */
+#define LL_RTC_TAMPER_FILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0 /*!< Tamper is activated after 2 consecutive samples at the active level */
+#define LL_RTC_TAMPER_FILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1 /*!< Tamper is activated after 4 consecutive samples at the active level */
+#define LL_RTC_TAMPER_FILTER_8SAMPLE TAMP_FLTCR_TAMPFLT /*!< Tamper is activated after 8 consecutive samples at the active level. */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV TAMPER SAMPLING FREQUENCY DIVIDER
+ * @{
+ */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_16384 TAMP_FLTCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_8192 TAMP_FLTCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_4096 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_2048 TAMP_FLTCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_1024 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_512 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 512 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_256 TAMP_FLTCR_TAMPFREQ /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 256 */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL TAMPER ACTIVE LEVEL
+ * @{
+ */
+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 TAMP_CR2_TAMP1TRG /*!< Tamper 1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 TAMP_CR2_TAMP2TRG /*!< Tamper 2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 TAMP_CR2_TAMP3TRG /*!< Tamper 3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP4 TAMP_CR2_TAMP4TRG /*!< Tamper 4 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP5 TAMP_CR2_TAMP5TRG /*!< Tamper 5 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP6 TAMP_CR2_TAMP6TRG /*!< Tamper 6 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP7 TAMP_CR2_TAMP7TRG /*!< Tamper 7 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP8 TAMP_CR2_TAMP8TRG /*!< Tamper 8 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
+/**
+ * @}
+ */
+
+
+/** @defgroup RTC_LL_EC_INTERNAL INTERNAL TAMPER
+ * @{
+ */
+#define LL_RTC_TAMPER_ITAMP1 TAMP_CR1_ITAMP1E /*!< Internal tamper 1: RTC supply voltage monitoring */
+#define LL_RTC_TAMPER_ITAMP2 TAMP_CR1_ITAMP2E /*!< Internal tamper 2: Temperature monitoring */
+#define LL_RTC_TAMPER_ITAMP3 TAMP_CR1_ITAMP3E /*!< Internal tamper 3: LSE monitoring */
+#define LL_RTC_TAMPER_ITAMP5 TAMP_CR1_ITAMP5E /*!< Internal tamper 5: RTC calendar overflow */
+#define LL_RTC_TAMPER_ITAMP6 TAMP_CR1_ITAMP6E /*!< Internal tamper 6: JTAG/SWD access when RDP > 0 */
+#define LL_RTC_TAMPER_ITAMP7 TAMP_CR1_ITAMP7E /*!< Internal tamper 7: ADC4 analog watchdog monitoring 1 */
+#define LL_RTC_TAMPER_ITAMP8 TAMP_CR1_ITAMP8E /*!< Internal tamper 8: Monotonic counter overflow */
+#define LL_RTC_TAMPER_ITAMP9 TAMP_CR1_ITAMP9E /*!< Internal tamper 9: Cryptograpic IPs fault*/
+#define LL_RTC_TAMPER_ITAMP11 TAMP_CR1_ITAMP11E /*!< Internal tamper 11: IWDG reset when tamper flag is set */
+#define LL_RTC_TAMPER_ITAMP12 TAMP_CR1_ITAMP12E /*!< Internal tamper 12: ADC4 analog watchdog monitoring 2*/
+#define LL_RTC_TAMPER_ITAMP13 TAMP_CR1_ITAMP13E /*!< Internal tamper 13: ADC4 analog watchdog monitoring 3 */
+/**
+ * @}
+ */
+
+
+/** @defgroup RTC_LL_EC_ACTIVE_MODE ACTIVE TAMPER MODE
+ * @{
+ */
+#define LL_RTC_TAMPER_ATAMP_TAMP1AM TAMP_ATCR1_TAMP1AM /*!< tamper 1 is active */
+#define LL_RTC_TAMPER_ATAMP_TAMP2AM TAMP_ATCR1_TAMP2AM /*!< tamper 2 is active */
+#define LL_RTC_TAMPER_ATAMP_TAMP3AM TAMP_ATCR1_TAMP3AM /*!< tamper 3 is active */
+#define LL_RTC_TAMPER_ATAMP_TAMP4AM TAMP_ATCR1_TAMP4AM /*!< tamper 4 is active */
+#define LL_RTC_TAMPER_ATAMP_TAMP5AM TAMP_ATCR1_TAMP5AM /*!< tamper 5 is active */
+#define LL_RTC_TAMPER_ATAMP_TAMP6AM TAMP_ATCR1_TAMP6AM /*!< tamper 6 is active */
+#define LL_RTC_TAMPER_ATAMP_TAMP7AM TAMP_ATCR1_TAMP7AM /*!< tamper 7 is active */
+#define LL_RTC_TAMPER_ATAMP_TAMP8AM TAMP_ATCR1_TAMP8AM /*!< tamper 8 is active */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_ACTIVE_ASYNC_PRESCALER ACTIVE TAMPER ASYNCHRONOUS PRESCALER CLOCK
+ * @{
+ */
+#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK 0u /*!< RTCCLK */
+#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_2 TAMP_ATCR1_ATCKSEL_0 /*!< RTCCLK/2 */
+#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_4 TAMP_ATCR1_ATCKSEL_1 /*!< RTCCLK/4 */
+#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_8 (TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/8 */
+#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_16 TAMP_ATCR1_ATCKSEL_2 /*!< RTCCLK/16 */
+#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_32 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/32 */
+#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_64 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1) /*!< RTCCLK/64 */
+#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_128 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/128 */
+/**
+ * @}
+ */
+
+
+/** @defgroup RTC_LL_EC_ACTIVE_OUTPUT_SELECTION ACTIVE TAMPER OUTPUT SELECTION
+ * @{
+ */
+#define LL_RTC_TAMPER_ATAMP1IN_ATAMP1OUT (0u << TAMP_ATCR2_ATOSEL1_Pos)
+#define LL_RTC_TAMPER_ATAMP1IN_ATAMP2OUT (1u << TAMP_ATCR2_ATOSEL1_Pos)
+#define LL_RTC_TAMPER_ATAMP1IN_ATAMP3OUT (2u << TAMP_ATCR2_ATOSEL1_Pos)
+#define LL_RTC_TAMPER_ATAMP1IN_ATAMP4OUT (3u << TAMP_ATCR2_ATOSEL1_Pos)
+#define LL_RTC_TAMPER_ATAMP1IN_ATAMP5OUT (4u << TAMP_ATCR2_ATOSEL1_Pos)
+#define LL_RTC_TAMPER_ATAMP1IN_ATAMP6OUT (5u << TAMP_ATCR2_ATOSEL1_Pos)
+#define LL_RTC_TAMPER_ATAMP1IN_ATAMP7OUT (6u << TAMP_ATCR2_ATOSEL1_Pos)
+#define LL_RTC_TAMPER_ATAMP1IN_ATAMP8OUT (7u << TAMP_ATCR2_ATOSEL1_Pos)
+
+#define LL_RTC_TAMPER_ATAMP2IN_ATAMP1OUT (0u << TAMP_ATCR2_ATOSEL2_Pos)
+#define LL_RTC_TAMPER_ATAMP2IN_ATAMP2OUT (1u << TAMP_ATCR2_ATOSEL2_Pos)
+#define LL_RTC_TAMPER_ATAMP2IN_ATAMP3OUT (2u << TAMP_ATCR2_ATOSEL2_Pos)
+#define LL_RTC_TAMPER_ATAMP2IN_ATAMP4OUT (3u << TAMP_ATCR2_ATOSEL2_Pos)
+#define LL_RTC_TAMPER_ATAMP2IN_ATAMP5OUT (4u << TAMP_ATCR2_ATOSEL2_Pos)
+#define LL_RTC_TAMPER_ATAMP2IN_ATAMP6OUT (5u << TAMP_ATCR2_ATOSEL2_Pos)
+#define LL_RTC_TAMPER_ATAMP2IN_ATAMP7OUT (6u << TAMP_ATCR2_ATOSEL2_Pos)
+#define LL_RTC_TAMPER_ATAMP2IN_ATAMP8OUT (7u << TAMP_ATCR2_ATOSEL2_Pos)
+
+#define LL_RTC_TAMPER_ATAMP3IN_ATAMP1OUT (0u << TAMP_ATCR2_ATOSEL3_Pos)
+#define LL_RTC_TAMPER_ATAMP3IN_ATAMP2OUT (1u << TAMP_ATCR2_ATOSEL3_Pos)
+#define LL_RTC_TAMPER_ATAMP3IN_ATAMP3OUT (2u << TAMP_ATCR2_ATOSEL3_Pos)
+#define LL_RTC_TAMPER_ATAMP3IN_ATAMP4OUT (3u << TAMP_ATCR2_ATOSEL3_Pos)
+#define LL_RTC_TAMPER_ATAMP3IN_ATAMP5OUT (4u << TAMP_ATCR2_ATOSEL3_Pos)
+#define LL_RTC_TAMPER_ATAMP3IN_ATAMP6OUT (5u << TAMP_ATCR2_ATOSEL3_Pos)
+#define LL_RTC_TAMPER_ATAMP3IN_ATAMP7OUT (6u << TAMP_ATCR2_ATOSEL3_Pos)
+#define LL_RTC_TAMPER_ATAMP3IN_ATAMP8OUT (7u << TAMP_ATCR2_ATOSEL3_Pos)
+
+#define LL_RTC_TAMPER_ATAMP4IN_ATAMP1OUT (0u << TAMP_ATCR2_ATOSEL4_Pos)
+#define LL_RTC_TAMPER_ATAMP4IN_ATAMP2OUT (1u << TAMP_ATCR2_ATOSEL4_Pos)
+#define LL_RTC_TAMPER_ATAMP4IN_ATAMP3OUT (2u << TAMP_ATCR2_ATOSEL4_Pos)
+#define LL_RTC_TAMPER_ATAMP4IN_ATAMP4OUT (3u << TAMP_ATCR2_ATOSEL4_Pos)
+#define LL_RTC_TAMPER_ATAMP4IN_ATAMP5OUT (4u << TAMP_ATCR2_ATOSEL4_Pos)
+#define LL_RTC_TAMPER_ATAMP4IN_ATAMP6OUT (5u << TAMP_ATCR2_ATOSEL4_Pos)
+#define LL_RTC_TAMPER_ATAMP4IN_ATAMP7OUT (6u << TAMP_ATCR2_ATOSEL4_Pos)
+#define LL_RTC_TAMPER_ATAMP4IN_ATAMP8OUT (7u << TAMP_ATCR2_ATOSEL4_Pos)
+
+#define LL_RTC_TAMPER_ATAMP5IN_ATAMP1OUT (0u << TAMP_ATCR2_ATOSEL5_Pos)
+#define LL_RTC_TAMPER_ATAMP5IN_ATAMP2OUT (1u << TAMP_ATCR2_ATOSEL5_Pos)
+#define LL_RTC_TAMPER_ATAMP5IN_ATAMP3OUT (2u << TAMP_ATCR2_ATOSEL5_Pos)
+#define LL_RTC_TAMPER_ATAMP5IN_ATAMP4OUT (3u << TAMP_ATCR2_ATOSEL5_Pos)
+#define LL_RTC_TAMPER_ATAMP5IN_ATAMP5OUT (4u << TAMP_ATCR2_ATOSEL5_Pos)
+#define LL_RTC_TAMPER_ATAMP5IN_ATAMP6OUT (5u << TAMP_ATCR2_ATOSEL5_Pos)
+#define LL_RTC_TAMPER_ATAMP5IN_ATAMP7OUT (6u << TAMP_ATCR2_ATOSEL5_Pos)
+#define LL_RTC_TAMPER_ATAMP5IN_ATAMP8OUT (7u << TAMP_ATCR2_ATOSEL5_Pos)
+
+#define LL_RTC_TAMPER_ATAMP6IN_ATAMP1OUT (0u << TAMP_ATCR2_ATOSEL6_Pos)
+#define LL_RTC_TAMPER_ATAMP6IN_ATAMP2OUT (1u << TAMP_ATCR2_ATOSEL6_Pos)
+#define LL_RTC_TAMPER_ATAMP6IN_ATAMP3OUT (2u << TAMP_ATCR2_ATOSEL6_Pos)
+#define LL_RTC_TAMPER_ATAMP6IN_ATAMP4OUT (3u << TAMP_ATCR2_ATOSEL6_Pos)
+#define LL_RTC_TAMPER_ATAMP6IN_ATAMP5OUT (4u << TAMP_ATCR2_ATOSEL6_Pos)
+#define LL_RTC_TAMPER_ATAMP6IN_ATAMP6OUT (5u << TAMP_ATCR2_ATOSEL6_Pos)
+#define LL_RTC_TAMPER_ATAMP6IN_ATAMP7OUT (6u << TAMP_ATCR2_ATOSEL6_Pos)
+#define LL_RTC_TAMPER_ATAMP6IN_ATAMP8OUT (7u << TAMP_ATCR2_ATOSEL6_Pos)
+
+#define LL_RTC_TAMPER_ATAMP7IN_ATAMP1OUT (0u << TAMP_ATCR2_ATOSEL7_Pos)
+#define LL_RTC_TAMPER_ATAMP7IN_ATAMP2OUT (1u << TAMP_ATCR2_ATOSEL7_Pos)
+#define LL_RTC_TAMPER_ATAMP7IN_ATAMP3OUT (2u << TAMP_ATCR2_ATOSEL7_Pos)
+#define LL_RTC_TAMPER_ATAMP7IN_ATAMP4OUT (3u << TAMP_ATCR2_ATOSEL7_Pos)
+#define LL_RTC_TAMPER_ATAMP7IN_ATAMP5OUT (4u << TAMP_ATCR2_ATOSEL7_Pos)
+#define LL_RTC_TAMPER_ATAMP7IN_ATAMP6OUT (5u << TAMP_ATCR2_ATOSEL7_Pos)
+#define LL_RTC_TAMPER_ATAMP7IN_ATAMP7OUT (6u << TAMP_ATCR2_ATOSEL7_Pos)
+#define LL_RTC_TAMPER_ATAMP7IN_ATAMP8OUT (7u << TAMP_ATCR2_ATOSEL7_Pos)
+
+#define LL_RTC_TAMPER_ATAMP8IN_ATAMP1OUT (0u << TAMP_ATCR2_ATOSEL8_Pos)
+#define LL_RTC_TAMPER_ATAMP8IN_ATAMP2OUT (1u << TAMP_ATCR2_ATOSEL8_Pos)
+#define LL_RTC_TAMPER_ATAMP8IN_ATAMP3OUT (2u << TAMP_ATCR2_ATOSEL8_Pos)
+#define LL_RTC_TAMPER_ATAMP8IN_ATAMP4OUT (3u << TAMP_ATCR2_ATOSEL8_Pos)
+#define LL_RTC_TAMPER_ATAMP8IN_ATAMP5OUT (4u << TAMP_ATCR2_ATOSEL8_Pos)
+#define LL_RTC_TAMPER_ATAMP8IN_ATAMP6OUT (5u << TAMP_ATCR2_ATOSEL8_Pos)
+#define LL_RTC_TAMPER_ATAMP8IN_ATAMP7OUT (6u << TAMP_ATCR2_ATOSEL8_Pos)
+#define LL_RTC_TAMPER_ATAMP8IN_ATAMP8OUT (7u << TAMP_ATCR2_ATOSEL8_Pos)
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_BKP BACKUP
+ * @{
+ */
+#define LL_RTC_BKP_NUMBER RTC_BACKUP_NB
+#define LL_RTC_BKP_DR0 0U
+#define LL_RTC_BKP_DR1 1U
+#define LL_RTC_BKP_DR2 2U
+#define LL_RTC_BKP_DR3 3U
+#define LL_RTC_BKP_DR4 4U
+#define LL_RTC_BKP_DR5 5U
+#define LL_RTC_BKP_DR6 6U
+#define LL_RTC_BKP_DR7 7U
+#define LL_RTC_BKP_DR8 8U
+#define LL_RTC_BKP_DR9 9U
+#define LL_RTC_BKP_DR10 10U
+#define LL_RTC_BKP_DR11 11U
+#define LL_RTC_BKP_DR12 12U
+#define LL_RTC_BKP_DR13 13U
+#define LL_RTC_BKP_DR14 14U
+#define LL_RTC_BKP_DR15 15U
+#define LL_RTC_BKP_DR16 16U
+#define LL_RTC_BKP_DR17 17U
+#define LL_RTC_BKP_DR18 18U
+#define LL_RTC_BKP_DR19 19U
+#define LL_RTC_BKP_DR20 20U
+#define LL_RTC_BKP_DR21 21U
+#define LL_RTC_BKP_DR22 22U
+#define LL_RTC_BKP_DR23 23U
+#define LL_RTC_BKP_DR24 24U
+#define LL_RTC_BKP_DR25 25U
+#define LL_RTC_BKP_DR26 26U
+#define LL_RTC_BKP_DR27 27U
+#define LL_RTC_BKP_DR28 28U
+#define LL_RTC_BKP_DR29 29U
+#define LL_RTC_BKP_DR30 30U
+#define LL_RTC_BKP_DR31 31U
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_WAKEUPCLOCK_DIV WAKEUP CLOCK DIV
+ * @{
+ */
+#define LL_RTC_WAKEUPCLOCK_DIV_16 0x00000000U /*!< RTC/16 clock is selected */
+#define LL_RTC_WAKEUPCLOCK_DIV_8 RTC_CR_WUCKSEL_0 /*!< RTC/8 clock is selected */
+#define LL_RTC_WAKEUPCLOCK_DIV_4 RTC_CR_WUCKSEL_1 /*!< RTC/4 clock is selected */
+#define LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0) /*!< RTC/2 clock is selected */
+#define LL_RTC_WAKEUPCLOCK_CKSPRE RTC_CR_WUCKSEL_2 /*!< ck_spre (usually 1 Hz) clock is selected */
+#define LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1) /*!< ck_spre (usually 1 Hz) clock is selected and 2exp16 is added to the WUT counter value*/
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_CALIB_OUTPUT Calibration output
+ * @{
+ */
+#define LL_RTC_CALIB_OUTPUT_NONE 0x00000000U /*!< Calibration output disabled */
+#define LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 1 Hz */
+#define LL_RTC_CALIB_OUTPUT_512HZ RTC_CR_COE /*!< Calibration output is 512 Hz */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_CALIB_INSERTPULSE Calibration pulse insertion
+ * @{
+ */
+#define LL_RTC_CALIB_INSERTPULSE_NONE 0x00000000U /*!< No RTCCLK pulses are added */
+#define LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP /*!< One RTCCLK pulse is effectively inserted every 2exp11 pulses (frequency increased by 488.5 ppm) */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_CALIB_PERIOD Calibration period
+ * @{
+ */
+#define LL_RTC_CALIB_PERIOD_32SEC 0x00000000U /*!< Use a 32-second calibration cycle period */
+#define LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< Use a 16-second calibration cycle period */
+#define LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< Use a 8-second calibration cycle period */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_CALIB_LOWPOWER Calibration low power
+ * @{
+ */
+#define LL_RTC_CALIB_LOWPOWER_NONE 0x00000000U /*!< High conso mode */
+#define LL_RTC_CALIB_LOWPOWER_SET RTC_CALR_LPCAL /*!< low power mode */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_BINARY_MODE Binary mode (Sub Second Register)
+ * @{
+ */
+#define LL_RTC_BINARY_NONE 0x00000000U /*!< Free running BCD calendar mode (Binary mode disabled). */
+#define LL_RTC_BINARY_ONLY RTC_ICSR_BIN_0 /*!< Free running Binary mode (BCD mode disabled) */
+#define LL_RTC_BINARY_MIX RTC_ICSR_BIN_1 /*!< Free running BCD calendar and Binary mode enable */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_BINARY_MIX_BCDU Calendar second incrementation in Binary mix mode
+ * @{
+ */
+#define LL_RTC_BINARY_MIX_BCDU_0 0x00000000u /*!< 1s calendar increment is generated each time SS[7:0] = 0 */
+#define LL_RTC_BINARY_MIX_BCDU_1 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time SS[8:0] = 0 */
+#define LL_RTC_BINARY_MIX_BCDU_2 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time SS[9:0] = 0 */
+#define LL_RTC_BINARY_MIX_BCDU_3 (0x3UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time SS[10:0] = 0 */
+#define LL_RTC_BINARY_MIX_BCDU_4 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time SS[11:0] = 0 */
+#define LL_RTC_BINARY_MIX_BCDU_5 (0x5UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time SS[12:0] = 0 */
+#define LL_RTC_BINARY_MIX_BCDU_6 (0x6UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time SS[13:0] = 0 */
+#define LL_RTC_BINARY_MIX_BCDU_7 (0x7UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time SS[14:0] = 0 */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_SECURE_RTC_FULL Secure full rtc
+ * @{
+ */
+#define LL_RTC_SECURE_FULL_YES RTC_SECCFGR_SEC /*!< RTC full secure */
+#define LL_RTC_SECURE_FULL_NO 0U /*!< RTC is not full secure, features can be secure. See RTC_LL_EC_SECURE_RTC_FEATURE */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_UNSECURE_RTC_FEATURE UnSecure features rtc in case of LL_RTC_SECURE_FULL_NO.
+ * @{
+ */
+#define LL_RTC_UNSECURE_FEATURE_INIT ~RTC_SECCFGR_INITSEC /*!< Initialization feature is not secure */
+#define LL_RTC_UNSECURE_FEATURE_CAL ~RTC_SECCFGR_CALSEC /*!< Calibration feature is not secure */
+#define LL_RTC_UNSECURE_FEATURE_TS ~RTC_SECCFGR_TSSEC /*!< Time stamp feature is not secure */
+#define LL_RTC_UNSECURE_FEATURE_WUT ~RTC_SECCFGR_WUTSEC /*!< Wake up timer feature is not secure */
+#define LL_RTC_UNSECURE_FEATURE_ALRA ~RTC_SECCFGR_ALRASEC /*!< Alarm A feature is not secure */
+#define LL_RTC_UNSECURE_FEATURE_ALRB ~RTC_SECCFGR_ALRBSEC /*!< Alarm B feature is not secure */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_SECURE_TAMP Secure tamp
+ * @{
+ */
+#define LL_TAMP_SECURE_FULL_YES TAMP_SECCFGR_TAMPSEC /*!< TAMP full secure */
+#define LL_TAMP_SECURE_FULL_NO 0U /*!< TAMP is not secure */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_PRIVILEGE_RTC_FULL Privilege full rtc
+ * @{
+ */
+#define LL_RTC_PRIVILEGE_FULL_YES RTC_PRIVCFGR_PRIV /*!< RTC full privilege */
+#define LL_RTC_PRIVILEGE_FULL_NO 0U /*!< RTC is not full privilege, features can be unprivilege. See RTC_LL_EC_PRIVILEGE_RTC_FEATURE */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_PRIVILEGE_RTC_FEATURE Privilege rtc features in case of LL_RTC_PRIVILEGE_FULL_NO.
+ * @{
+ */
+#define LL_RTC_PRIVILEGE_FEATURE_INIT RTC_PRIVCFGR_INITPRIV /*!< Initialization feature is privilege*/
+#define LL_RTC_PRIVILEGE_FEATURE_CAL RTC_PRIVCFGR_CALPRIV /*!< Calibration feature is privilege */
+#define LL_RTC_PRIVILEGE_FEATURE_TS RTC_PRIVCFGR_TSPRIV /*!< Time stamp feature is privilege */
+#define LL_RTC_PRIVILEGE_FEATURE_WUT RTC_PRIVCFGR_WUTPRIV /*!< Wake up timer feature is privilege */
+#define LL_RTC_PRIVILEGE_FEATURE_ALRA RTC_PRIVCFGR_ALRAPRIV /*!< Alarm A feature is privilege */
+#define LL_RTC_PRIVILEGE_FEATURE_ALRB RTC_PRIVCFGR_ALRBPRIV /*!< Alarm B feature is privilege */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_PRIVILEGE_TAMP_FULL Privilege full tamp
+ * @{
+ */
+#define LL_TAMP_PRIVILEGE_FULL_YES TAMP_PRIVCFGR_TAMPPRIV /*!< TAMP full privilege */
+#define LL_TAMP_PRIVILEGE_FULL_NO 0U /*!< TAMP is not privilege */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_PRIVILEGE_BACKUP_REG_ZONE Privilege Backup register privilege zone
+ * @{
+ */
+#define LL_RTC_PRIVILEGE_BKUP_ZONE_NONE 0U
+#define LL_RTC_PRIVILEGE_BKUP_ZONE_1 TAMP_PRIVCFGR_BKPRWPRIV
+#define LL_RTC_PRIVILEGE_BKUP_ZONE_2 TAMP_PRIVCFGR_BKPWPRIV
+#define LL_RTC_PRIVILEGE_BKUP_ZONE_ALL (LL_RTC_PRIVILEGE_BKUP_ZONE_1 | LL_RTC_PRIVILEGE_BKUP_ZONE_2)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RTC_LL_Exported_Macros RTC Exported Macros
+ * @{
+ */
+
+/** @defgroup RTC_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in RTC register
+ * @param __INSTANCE__ RTC Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in RTC register
+ * @param __INSTANCE__ RTC Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EM_Convert Convert helper Macros
+ * @{
+ */
+
+/**
+ * @brief Helper macro to convert a value from 2 digit decimal format to BCD format
+ * @param __VALUE__ Byte to be converted
+ * @retval Converted byte
+ */
+#define __LL_RTC_CONVERT_BIN2BCD(__VALUE__) ((uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U)))
+
+/**
+ * @brief Helper macro to convert a value from BCD format to 2 digit decimal format
+ * @param __VALUE__ BCD value to be converted
+ * @retval Converted byte
+ */
+#define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) ((uint8_t)((((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> \
+ (uint8_t)0x4U) * 10U) + ((__VALUE__) & (uint8_t)0x0FU)))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EM_Date Date helper Macros
+ * @{
+ */
+
+/**
+ * @brief Helper macro to retrieve weekday.
+ * @param __RTC_DATE__ Date returned by @ref LL_RTC_DATE_Get function.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_WEEKDAY_MONDAY
+ * @arg @ref LL_RTC_WEEKDAY_TUESDAY
+ * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+ * @arg @ref LL_RTC_WEEKDAY_THURSDAY
+ * @arg @ref LL_RTC_WEEKDAY_FRIDAY
+ * @arg @ref LL_RTC_WEEKDAY_SATURDAY
+ * @arg @ref LL_RTC_WEEKDAY_SUNDAY
+ */
+#define __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)
+
+/**
+ * @brief Helper macro to retrieve Year in BCD format
+ * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get
+ * @retval Year in BCD format (0x00 . . . 0x99)
+ */
+#define __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU)
+
+/**
+ * @brief Helper macro to retrieve Month in BCD format
+ * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_MONTH_JANUARY
+ * @arg @ref LL_RTC_MONTH_FEBRUARY
+ * @arg @ref LL_RTC_MONTH_MARCH
+ * @arg @ref LL_RTC_MONTH_APRIL
+ * @arg @ref LL_RTC_MONTH_MAY
+ * @arg @ref LL_RTC_MONTH_JUNE
+ * @arg @ref LL_RTC_MONTH_JULY
+ * @arg @ref LL_RTC_MONTH_AUGUST
+ * @arg @ref LL_RTC_MONTH_SEPTEMBER
+ * @arg @ref LL_RTC_MONTH_OCTOBER
+ * @arg @ref LL_RTC_MONTH_NOVEMBER
+ * @arg @ref LL_RTC_MONTH_DECEMBER
+ */
+#define __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)
+
+/**
+ * @brief Helper macro to retrieve Day in BCD format
+ * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get
+ * @retval Day in BCD format (0x01 . . . 0x31)
+ */
+#define __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EM_Time Time helper Macros
+ * @{
+ */
+
+/**
+ * @brief Helper macro to retrieve hour in BCD format
+ * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
+ * @retval Hours in BCD format (0x01. . .0x12 or between Min_Data=0x00 and Max_Data=0x23)
+ */
+#define __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)
+
+/**
+ * @brief Helper macro to retrieve minute in BCD format
+ * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
+ * @retval Minutes in BCD format (0x00. . .0x59)
+ */
+#define __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)
+
+/**
+ * @brief Helper macro to retrieve second in BCD format
+ * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
+ * @retval Seconds in format (0x00. . .0x59)
+ */
+#define __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RTC_LL_Exported_Functions RTC Exported Functions
+ * @{
+ */
+
+/** @defgroup RTC_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Set Hours format (24 hour/day or AM/PM hour format)
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+ * @rmtoll RTC_CR FMT LL_RTC_SetHourFormat
+ * @param RTCx RTC Instance
+ * @param HourFormat This parameter can be one of the following values:
+ * @arg @ref LL_RTC_HOURFORMAT_24HOUR
+ * @arg @ref LL_RTC_HOURFORMAT_AMPM
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_SetHourFormat(RTC_TypeDef *RTCx, uint32_t HourFormat)
+{
+ MODIFY_REG(RTCx->CR, RTC_CR_FMT, HourFormat);
+}
+
+/**
+ * @brief Get Hours format (24 hour/day or AM/PM hour format)
+ * @rmtoll RTC_CR FMT LL_RTC_GetHourFormat
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_HOURFORMAT_24HOUR
+ * @arg @ref LL_RTC_HOURFORMAT_AMPM
+ */
+__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_FMT));
+}
+
+/**
+ * @brief Select the flag to be routed to RTC_ALARM output
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll RTC_CR OSEL LL_RTC_SetAlarmOutEvent
+ * @param RTCx RTC Instance
+ * @param AlarmOutput This parameter can be one of the following values:
+ * @arg @ref LL_RTC_ALARMOUT_DISABLE
+ * @arg @ref LL_RTC_ALARMOUT_ALMA
+ * @arg @ref LL_RTC_ALARMOUT_ALMB
+ * @arg @ref LL_RTC_ALARMOUT_WAKEUP
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_SetAlarmOutEvent(RTC_TypeDef *RTCx, uint32_t AlarmOutput)
+{
+ MODIFY_REG(RTCx->CR, RTC_CR_OSEL, AlarmOutput);
+}
+
+/**
+ * @brief Get the flag to be routed to RTC_ALARM output
+ * @rmtoll RTC_CR OSEL LL_RTC_GetAlarmOutEvent
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_ALARMOUT_DISABLE
+ * @arg @ref LL_RTC_ALARMOUT_ALMA
+ * @arg @ref LL_RTC_ALARMOUT_ALMB
+ * @arg @ref LL_RTC_ALARMOUT_WAKEUP
+ */
+__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL));
+}
+
+/**
+ * @brief Set RTC_ALARM output type (ALARM in push-pull or open-drain output)
+ * @rmtoll RTC_CR TAMPALRM_TYPE LL_RTC_SetAlarmOutputType
+ * @param RTCx RTC Instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
+ * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Output)
+{
+ MODIFY_REG(RTCx->CR, RTC_CR_TAMPALRM_TYPE, Output);
+}
+
+/**
+ * @brief Get RTC_ALARM output type (ALARM in push-pull or open-drain output)
+ * @rmtoll RTC_CR TAMPALRM_TYPE LL_RTC_SetAlarmOutputType
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
+ * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
+ */
+__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_TYPE));
+}
+
+/**
+ * @brief Enable initialization mode
+ * @note Initialization mode is used to program time and date register (RTC_TR and RTC_DR)
+ * and prescaler register (RTC_PRER).
+ * Counters are stopped and start counting from the new value when INIT is reset.
+ * @rmtoll RTC_ICSR INIT LL_RTC_EnableInitMode
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx)
+{
+ /* Set the Initialization mode */
+ SET_BIT(RTCx->ICSR, RTC_ICSR_INIT);
+}
+
+/**
+ * @brief Disable initialization mode (Free running mode)
+ * @rmtoll RTC_ICSR INIT LL_RTC_DisableInitMode
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx)
+{
+ /* Exit Initialization mode */
+ CLEAR_BIT(RTCx->ICSR, RTC_ICSR_INIT);
+
+}
+
+/**
+ * @brief Set Binary mode (Sub Second Register)
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function).
+ * @rmtoll RTC_ICSR BIN LL_RTC_SetBinaryMode
+ * @param RTCx RTC Instance
+ * @param BinaryMode can be one of the following values:
+ * @arg @ref LL_RTC_BINARY_NONE
+ * @arg @ref LL_RTC_BINARY_ONLY
+ * @arg @ref LL_RTC_BINARY_MIX
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_SetBinaryMode(RTC_TypeDef *RTCx, uint32_t BinaryMode)
+{
+ MODIFY_REG(RTCx->ICSR, RTC_ICSR_BIN, BinaryMode);
+}
+
+/**
+ * @brief Get Binary mode (Sub Second Register)
+ * @rmtoll RTC_ICSR BIN LL_RTC_GetBinaryMode
+ * @param RTCx RTC Instance
+ * @retval This parameter can be one of the following values:
+ * @arg @ref LL_RTC_BINARY_NONE
+ * @arg @ref LL_RTC_BINARY_ONLY
+ * @arg @ref LL_RTC_BINARY_MIX
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_RTC_GetBinaryMode(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ICSR, RTC_ICSR_BIN));
+}
+
+/**
+ * @brief Set Binary Mix mode BCDU
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function).
+ * @rmtoll RTC_ICSR BCDU LL_RTC_SetBinMixBCDU
+ * @param RTCx RTC Instance
+ * @param BinMixBcdU can be one of the following values:
+ * @arg @ref LL_RTC_BINARY_MIX_BCDU_0
+ * @arg @ref LL_RTC_BINARY_MIX_BCDU_1
+ * @arg @ref LL_RTC_BINARY_MIX_BCDU_2
+ * @arg @ref LL_RTC_BINARY_MIX_BCDU_3
+ * @arg @ref LL_RTC_BINARY_MIX_BCDU_4
+ * @arg @ref LL_RTC_BINARY_MIX_BCDU_5
+ * @arg @ref LL_RTC_BINARY_MIX_BCDU_6
+ * @arg @ref LL_RTC_BINARY_MIX_BCDU_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_SetBinMixBCDU(RTC_TypeDef *RTCx, uint32_t BinMixBcdU)
+{
+ MODIFY_REG(RTCx->ICSR, RTC_ICSR_BCDU, BinMixBcdU);
+}
+
+/**
+ * @brief Get Binary Mix mode BCDU
+ * @rmtoll RTC_ICSR BCDU LL_RTC_GetBinMixBCDU
+ * @param RTCx RTC Instance
+ * @retval This parameter can be one of the following values:
+ * @arg @ref LL_RTC_BINARY_MIX_BCDU_0
+ * @arg @ref LL_RTC_BINARY_MIX_BCDU_1
+ * @arg @ref LL_RTC_BINARY_MIX_BCDU_2
+ * @arg @ref LL_RTC_BINARY_MIX_BCDU_3
+ * @arg @ref LL_RTC_BINARY_MIX_BCDU_4
+ * @arg @ref LL_RTC_BINARY_MIX_BCDU_5
+ * @arg @ref LL_RTC_BINARY_MIX_BCDU_6
+ * @arg @ref LL_RTC_BINARY_MIX_BCDU_7
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_RTC_GetBinMixBCDU(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ICSR, RTC_ICSR_BCDU));
+}
+
+/**
+ * @brief Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted)
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll RTC_CR POL LL_RTC_SetOutputPolarity
+ * @param RTCx RTC Instance
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH
+ * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_SetOutputPolarity(RTC_TypeDef *RTCx, uint32_t Polarity)
+{
+ MODIFY_REG(RTCx->CR, RTC_CR_POL, Polarity);
+}
+
+/**
+ * @brief Get Output polarity
+ * @rmtoll RTC_CR POL LL_RTC_GetOutputPolarity
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH
+ * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW
+ */
+__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_POL));
+}
+
+/**
+ * @brief Enable Bypass the shadow registers
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll RTC_CR BYPSHAD LL_RTC_EnableShadowRegBypass
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableShadowRegBypass(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_BYPSHAD);
+}
+
+/**
+ * @brief Disable Bypass the shadow registers
+ * @rmtoll RTC_CR BYPSHAD LL_RTC_DisableShadowRegBypass
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_BYPSHAD);
+}
+
+/**
+ * @brief Check if Shadow registers bypass is enabled or not.
+ * @rmtoll RTC_CR BYPSHAD LL_RTC_IsShadowRegBypassEnabled
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef *RTCx)
+{
+ return ((READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD)) ? 1U : 0U);
+}
+
+/**
+ * @brief Enable RTC_REFIN reference clock detection (50 or 60 Hz)
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+ * @rmtoll RTC_CR REFCKON LL_RTC_EnableRefClock
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableRefClock(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_REFCKON);
+}
+
+/**
+ * @brief Disable RTC_REFIN reference clock detection (50 or 60 Hz)
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+ * @rmtoll RTC_CR REFCKON LL_RTC_DisableRefClock
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableRefClock(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_REFCKON);
+}
+
+/**
+ * @brief Set Asynchronous prescaler factor
+ * @rmtoll RTC_PRER PREDIV_A LL_RTC_SetAsynchPrescaler
+ * @param RTCx RTC Instance
+ * @param AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7F
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler)
+{
+ MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_PRER_PREDIV_A_Pos);
+}
+
+/**
+ * @brief Set Synchronous prescaler factor
+ * @rmtoll RTC_PRER PREDIV_S LL_RTC_SetSynchPrescaler
+ * @param RTCx RTC Instance
+ * @param SynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7FFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchPrescaler)
+{
+ MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_S, SynchPrescaler);
+}
+
+/**
+ * @brief Get Asynchronous prescaler factor
+ * @rmtoll RTC_PRER PREDIV_A LL_RTC_GetAsynchPrescaler
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data = 0 and Max_Data = 0x7F
+ */
+__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos);
+}
+
+/**
+ * @brief Get Synchronous prescaler factor
+ * @rmtoll RTC_PRER PREDIV_S LL_RTC_GetSynchPrescaler
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data = 0 and Max_Data = 0x7FFF
+ */
+__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_S));
+}
+
+/**
+ * @brief Enable the write protection for RTC registers.
+ * @rmtoll RTC_WPR KEY LL_RTC_EnableWriteProtection
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx)
+{
+ WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_DISABLE);
+}
+
+/**
+ * @brief Disable the write protection for RTC registers.
+ * @rmtoll RTC_WPR KEY LL_RTC_DisableWriteProtection
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx)
+{
+ WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_1);
+ WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2);
+}
+
+/**
+ * @brief Enable tamper output.
+ * @note When the tamper output is enabled, all external and internal tamper flags
+ * are ORed and routed to the TAMPALRM output.
+ * @rmtoll RTC_CR TAMPOE LL_RTC_EnableTamperOutput
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableTamperOutput(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_TAMPOE);
+}
+
+/**
+ * @brief Disable tamper output.
+ * @rmtoll RTC_CR TAMPOE LL_RTC_DisableTamperOutput
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableTamperOutput(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_TAMPOE);
+}
+
+/**
+ * @brief Check if tamper output is enabled or not.
+ * @rmtoll RTC_CR TAMPOE LL_RTC_IsTamperOutputEnabled
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsTamperOutputEnabled(RTC_TypeDef *RTCx)
+{
+ return ((READ_BIT(RTCx->CR, RTC_CR_TAMPOE) == (RTC_CR_TAMPOE)) ? 1U : 0U);
+}
+
+/**
+ * @brief Enable internal pull-up in output mode.
+ * @rmtoll RTC_CR TAMPALRM_PU LL_RTC_EnableAlarmPullUp
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableAlarmPullUp(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU);
+}
+
+/**
+ * @brief Disable internal pull-up in output mode.
+ * @rmtoll RTC_CR TAMPALRM_PU LL_RTC_EnableAlarmPullUp
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableAlarmPullUp(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU);
+}
+
+/**
+ * @brief Check if internal pull-up in output mode is enabled or not.
+ * @rmtoll RTC_CR TAMPALRM_PU LL_RTC_IsAlarmPullUpEnabled
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsAlarmPullUpEnabled(RTC_TypeDef *RTCx)
+{
+ return ((READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU) == (RTC_CR_TAMPALRM_PU)) ? 1U : 0U);
+}
+
+/**
+ * @brief Enable RTC_OUT2 output
+ * @note RTC_OUT2 mapping depends on both OSEL (@ref LL_RTC_SetAlarmOutEvent)
+ * and COE (@ref LL_RTC_CAL_SetOutputFreq) settings.
+ * @note RTC_OUT2 is not available ins VBAT mode.
+ * @rmtoll RTC_CR OUT2EN LL_RTC_EnableOutput2
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableOutput2(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_OUT2EN);
+}
+
+/**
+ * @brief Disable RTC_OUT2 output
+ * @rmtoll RTC_CR OUT2EN LL_RTC_DisableOutput2
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableOutput2(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_OUT2EN);
+}
+
+/**
+ * @brief Check if RTC_OUT2 output is enabled or not.
+ * @rmtoll RTC_CR OUT2EN LL_RTC_IsOutput2Enabled
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsOutput2Enabled(RTC_TypeDef *RTCx)
+{
+ return ((READ_BIT(RTCx->CR, RTC_CR_OUT2EN) == (RTC_CR_OUT2EN)) ? 1U : 0U);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_Time Time
+ * @{
+ */
+
+/**
+ * @brief Set time format (AM/24-hour or PM notation)
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+ * @rmtoll RTC_TR PM LL_RTC_TIME_SetFormat
+ * @param RTCx RTC Instance
+ * @param TimeFormat This parameter can be one of the following values:
+ * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
+ * @arg @ref LL_RTC_TIME_FORMAT_PM
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
+{
+ MODIFY_REG(RTCx->TR, RTC_TR_PM, TimeFormat);
+}
+
+/**
+ * @brief Get time format (AM or PM notation)
+ * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * before reading this bit
+ * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
+ * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
+ * @rmtoll RTC_TR PM LL_RTC_TIME_GetFormat
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
+ * @arg @ref LL_RTC_TIME_FORMAT_PM
+ */
+__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TR, RTC_TR_PM));
+}
+
+/**
+ * @brief Set Hours in BCD format
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert hour from binary to BCD format
+ * @rmtoll RTC_TR HT LL_RTC_TIME_SetHour\n
+ * RTC_TR HU LL_RTC_TIME_SetHour
+ * @param RTCx RTC Instance
+ * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
+{
+ MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU),
+ (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)));
+}
+
+/**
+ * @brief Get Hours in BCD format
+ * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * before reading this bit
+ * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
+ * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert hour from BCD to
+ * Binary format
+ * @rmtoll RTC_TR HT LL_RTC_TIME_GetHour\n
+ * RTC_TR HU LL_RTC_TIME_GetHour
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+ */
+__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)((READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU))) >> RTC_TR_HU_Pos);
+}
+
+/**
+ * @brief Set Minutes in BCD format
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
+ * @rmtoll RTC_TR MNT LL_RTC_TIME_SetMinute\n
+ * RTC_TR MNU LL_RTC_TIME_SetMinute
+ * @param RTCx RTC Instance
+ * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
+{
+ MODIFY_REG(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU),
+ (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)));
+}
+
+/**
+ * @brief Get Minutes in BCD format
+ * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * before reading this bit
+ * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
+ * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert minute from BCD
+ * to Binary format
+ * @rmtoll RTC_TR MNT LL_RTC_TIME_GetMinute\n
+ * RTC_TR MNU LL_RTC_TIME_GetMinute
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x59
+ */
+__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos);
+}
+
+/**
+ * @brief Set Seconds in BCD format
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
+ * @rmtoll RTC_TR ST LL_RTC_TIME_SetSecond\n
+ * RTC_TR SU LL_RTC_TIME_SetSecond
+ * @param RTCx RTC Instance
+ * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
+{
+ MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU),
+ (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos)));
+}
+
+/**
+ * @brief Get Seconds in BCD format
+ * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * before reading this bit
+ * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
+ * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD
+ * to Binary format
+ * @rmtoll RTC_TR ST LL_RTC_TIME_GetSecond\n
+ * RTC_TR SU LL_RTC_TIME_GetSecond
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x59
+ */
+__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos);
+}
+
+/**
+ * @brief Set time (hour, minute and second) in BCD format
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+ * @note TimeFormat and Hours should follow the same format
+ * @rmtoll RTC_TR PM LL_RTC_TIME_Config\n
+ * RTC_TR HT LL_RTC_TIME_Config\n
+ * RTC_TR HU LL_RTC_TIME_Config\n
+ * RTC_TR MNT LL_RTC_TIME_Config\n
+ * RTC_TR MNU LL_RTC_TIME_Config\n
+ * RTC_TR ST LL_RTC_TIME_Config\n
+ * RTC_TR SU LL_RTC_TIME_Config
+ * @param RTCx RTC Instance
+ * @param Format12_24 This parameter can be one of the following values:
+ * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
+ * @arg @ref LL_RTC_TIME_FORMAT_PM
+ * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+ * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59
+ * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes,
+ uint32_t Seconds)
+{
+ uint32_t temp;
+
+ temp = Format12_24 | \
+ (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)) | \
+ (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)) | \
+ (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos));
+ MODIFY_REG(RTCx->TR, (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU), temp);
+}
+
+/**
+ * @brief Get time (hour, minute and second) in BCD format
+ * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * before reading this bit
+ * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
+ * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
+ * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
+ * are available to get independently each parameter.
+ * @rmtoll RTC_TR HT LL_RTC_TIME_Get\n
+ * RTC_TR HU LL_RTC_TIME_Get\n
+ * RTC_TR MNT LL_RTC_TIME_Get\n
+ * RTC_TR MNU LL_RTC_TIME_Get\n
+ * RTC_TR ST LL_RTC_TIME_Get\n
+ * RTC_TR SU LL_RTC_TIME_Get
+ * @param RTCx RTC Instance
+ * @retval Combination of hours, minutes and seconds (Format: 0x00HHMMSS).
+ */
+__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx)
+{
+ uint32_t temp;
+
+ temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU));
+ return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) \
+ << RTC_OFFSET_HOUR) | (((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | \
+ ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)) << RTC_OFFSET_MINUTE) | \
+ ((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos)));
+}
+
+/**
+ * @brief Memorize whether the daylight saving time change has been performed
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll RTC_CR BKP LL_RTC_TIME_EnableDayLightStore
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_BKP);
+}
+
+/**
+ * @brief Disable memorization whether the daylight saving time change has been performed.
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll RTC_CR BKP LL_RTC_TIME_DisableDayLightStore
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_BKP);
+}
+
+/**
+ * @brief Check if RTC Day Light Saving stored operation has been enabled or not
+ * @rmtoll RTC_CR BKP LL_RTC_TIME_IsDayLightStoreEnabled
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx)
+{
+ return ((READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP)) ? 1U : 0U);
+}
+
+/**
+ * @brief Subtract 1 hour (winter time change)
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll RTC_CR SUB1H LL_RTC_TIME_DecHour
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_DecHour(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_SUB1H);
+}
+
+/**
+ * @brief Add 1 hour (summer time change)
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll RTC_CR ADD1H LL_RTC_TIME_IncHour
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_ADD1H);
+}
+
+/**
+ * @brief Get Sub second value in the synchronous prescaler counter.
+ * @note You can use both SubSeconds value and SecondFraction (PREDIV_S through
+ * LL_RTC_GetSynchPrescaler function) terms returned to convert Calendar
+ * SubSeconds value in second fraction ratio with time unit following
+ * generic formula:
+ * ==> Seconds fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
+ * This conversion can be performed only if no shift operation is pending
+ * (ie. SHFP=0) when PREDIV_S >= SS.
+ * @rmtoll RTC_SSR SS LL_RTC_TIME_GetSubSecond
+ * @param RTCx RTC Instance
+ * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF
+ * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS));
+}
+
+/**
+ * @brief Synchronize to a remote clock with a high degree of precision.
+ * @note This operation effectively subtracts from (delays) or advance the clock of a fraction of a second.
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note When REFCKON is set, firmware must not write to Shift control register.
+ * @rmtoll RTC_SHIFTR ADD1S LL_RTC_TIME_Synchronize\n
+ * RTC_SHIFTR SUBFS LL_RTC_TIME_Synchronize
+ * @param RTCx RTC Instance
+ * @param ShiftSecond This parameter can be one of the following values:
+ * @arg @ref LL_RTC_SHIFT_SECOND_DELAY
+ * @arg @ref LL_RTC_SHIFT_SECOND_ADVANCE
+ * @param Fraction Number of Seconds Fractions (any value from 0 to 0x7FFF)
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_Synchronize(RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction)
+{
+ WRITE_REG(RTCx->SHIFTR, ShiftSecond | Fraction);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_Date Date
+ * @{
+ */
+
+/**
+ * @brief Set Year in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Year from binary to BCD format
+ * @rmtoll RTC_DR YT LL_RTC_DATE_SetYear\n
+ * RTC_DR YU LL_RTC_DATE_SetYear
+ * @param RTCx RTC Instance
+ * @param Year Value between Min_Data=0x00 and Max_Data=0x99
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year)
+{
+ MODIFY_REG(RTCx->DR, (RTC_DR_YT | RTC_DR_YU),
+ (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)));
+}
+
+/**
+ * @brief Get Year in BCD format
+ * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * before reading this bit
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format
+ * @rmtoll RTC_DR YT LL_RTC_DATE_GetYear\n
+ * RTC_DR YU LL_RTC_DATE_GetYear
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x99
+ */
+__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU))) >> RTC_DR_YU_Pos);
+}
+
+/**
+ * @brief Set Week day
+ * @rmtoll RTC_DR WDU LL_RTC_DATE_SetWeekDay
+ * @param RTCx RTC Instance
+ * @param WeekDay This parameter can be one of the following values:
+ * @arg @ref LL_RTC_WEEKDAY_MONDAY
+ * @arg @ref LL_RTC_WEEKDAY_TUESDAY
+ * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+ * @arg @ref LL_RTC_WEEKDAY_THURSDAY
+ * @arg @ref LL_RTC_WEEKDAY_FRIDAY
+ * @arg @ref LL_RTC_WEEKDAY_SATURDAY
+ * @arg @ref LL_RTC_WEEKDAY_SUNDAY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
+{
+ MODIFY_REG(RTCx->DR, RTC_DR_WDU, WeekDay << RTC_DR_WDU_Pos);
+}
+
+/**
+ * @brief Get Week day
+ * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * before reading this bit
+ * @rmtoll RTC_DR WDU LL_RTC_DATE_GetWeekDay
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_WEEKDAY_MONDAY
+ * @arg @ref LL_RTC_WEEKDAY_TUESDAY
+ * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+ * @arg @ref LL_RTC_WEEKDAY_THURSDAY
+ * @arg @ref LL_RTC_WEEKDAY_FRIDAY
+ * @arg @ref LL_RTC_WEEKDAY_SATURDAY
+ * @arg @ref LL_RTC_WEEKDAY_SUNDAY
+ */
+__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_DR_WDU_Pos);
+}
+
+/**
+ * @brief Set Month in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Month from binary to BCD format
+ * @rmtoll RTC_DR MT LL_RTC_DATE_SetMonth\n
+ * RTC_DR MU LL_RTC_DATE_SetMonth
+ * @param RTCx RTC Instance
+ * @param Month This parameter can be one of the following values:
+ * @arg @ref LL_RTC_MONTH_JANUARY
+ * @arg @ref LL_RTC_MONTH_FEBRUARY
+ * @arg @ref LL_RTC_MONTH_MARCH
+ * @arg @ref LL_RTC_MONTH_APRIL
+ * @arg @ref LL_RTC_MONTH_MAY
+ * @arg @ref LL_RTC_MONTH_JUNE
+ * @arg @ref LL_RTC_MONTH_JULY
+ * @arg @ref LL_RTC_MONTH_AUGUST
+ * @arg @ref LL_RTC_MONTH_SEPTEMBER
+ * @arg @ref LL_RTC_MONTH_OCTOBER
+ * @arg @ref LL_RTC_MONTH_NOVEMBER
+ * @arg @ref LL_RTC_MONTH_DECEMBER
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month)
+{
+ MODIFY_REG(RTCx->DR, (RTC_DR_MT | RTC_DR_MU),
+ (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)));
+}
+
+/**
+ * @brief Get Month in BCD format
+ * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * before reading this bit
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
+ * @rmtoll RTC_DR MT LL_RTC_DATE_GetMonth\n
+ * RTC_DR MU LL_RTC_DATE_GetMonth
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_MONTH_JANUARY
+ * @arg @ref LL_RTC_MONTH_FEBRUARY
+ * @arg @ref LL_RTC_MONTH_MARCH
+ * @arg @ref LL_RTC_MONTH_APRIL
+ * @arg @ref LL_RTC_MONTH_MAY
+ * @arg @ref LL_RTC_MONTH_JUNE
+ * @arg @ref LL_RTC_MONTH_JULY
+ * @arg @ref LL_RTC_MONTH_AUGUST
+ * @arg @ref LL_RTC_MONTH_SEPTEMBER
+ * @arg @ref LL_RTC_MONTH_OCTOBER
+ * @arg @ref LL_RTC_MONTH_NOVEMBER
+ * @arg @ref LL_RTC_MONTH_DECEMBER
+ */
+__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU))) >> RTC_DR_MU_Pos);
+}
+
+/**
+ * @brief Set Day in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
+ * @rmtoll RTC_DR DT LL_RTC_DATE_SetDay\n
+ * RTC_DR DU LL_RTC_DATE_SetDay
+ * @param RTCx RTC Instance
+ * @param Day Value between Min_Data=0x01 and Max_Data=0x31
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
+{
+ MODIFY_REG(RTCx->DR, (RTC_DR_DT | RTC_DR_DU),
+ (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos)));
+}
+
+/**
+ * @brief Get Day in BCD format
+ * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * before reading this bit
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
+ * @rmtoll RTC_DR DT LL_RTC_DATE_GetDay\n
+ * RTC_DR DU LL_RTC_DATE_GetDay
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x01 and Max_Data=0x31
+ */
+__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU))) >> RTC_DR_DU_Pos);
+}
+
+/**
+ * @brief Set date (WeekDay, Day, Month and Year) in BCD format
+ * @rmtoll RTC_DR WDU LL_RTC_DATE_Config\n
+ * RTC_DR MT LL_RTC_DATE_Config\n
+ * RTC_DR MU LL_RTC_DATE_Config\n
+ * RTC_DR DT LL_RTC_DATE_Config\n
+ * RTC_DR DU LL_RTC_DATE_Config\n
+ * RTC_DR YT LL_RTC_DATE_Config\n
+ * RTC_DR YU LL_RTC_DATE_Config
+ * @param RTCx RTC Instance
+ * @param WeekDay This parameter can be one of the following values:
+ * @arg @ref LL_RTC_WEEKDAY_MONDAY
+ * @arg @ref LL_RTC_WEEKDAY_TUESDAY
+ * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+ * @arg @ref LL_RTC_WEEKDAY_THURSDAY
+ * @arg @ref LL_RTC_WEEKDAY_FRIDAY
+ * @arg @ref LL_RTC_WEEKDAY_SATURDAY
+ * @arg @ref LL_RTC_WEEKDAY_SUNDAY
+ * @param Day Value between Min_Data=0x01 and Max_Data=0x31
+ * @param Month This parameter can be one of the following values:
+ * @arg @ref LL_RTC_MONTH_JANUARY
+ * @arg @ref LL_RTC_MONTH_FEBRUARY
+ * @arg @ref LL_RTC_MONTH_MARCH
+ * @arg @ref LL_RTC_MONTH_APRIL
+ * @arg @ref LL_RTC_MONTH_MAY
+ * @arg @ref LL_RTC_MONTH_JUNE
+ * @arg @ref LL_RTC_MONTH_JULY
+ * @arg @ref LL_RTC_MONTH_AUGUST
+ * @arg @ref LL_RTC_MONTH_SEPTEMBER
+ * @arg @ref LL_RTC_MONTH_OCTOBER
+ * @arg @ref LL_RTC_MONTH_NOVEMBER
+ * @arg @ref LL_RTC_MONTH_DECEMBER
+ * @param Year Value between Min_Data=0x00 and Max_Data=0x99
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month,
+ uint32_t Year)
+{
+ uint32_t temp;
+
+ temp = (WeekDay << RTC_DR_WDU_Pos) | \
+ (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)) | \
+ (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)) | \
+ (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos));
+
+ MODIFY_REG(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU), temp);
+}
+
+/**
+ * @brief Get date (WeekDay, Day, Month and Year) in BCD format
+ * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * before reading this bit
+ * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH,
+ * and __LL_RTC_GET_DAY are available to get independently each parameter.
+ * @rmtoll RTC_DR WDU LL_RTC_DATE_Get\n
+ * RTC_DR MT LL_RTC_DATE_Get\n
+ * RTC_DR MU LL_RTC_DATE_Get\n
+ * RTC_DR DT LL_RTC_DATE_Get\n
+ * RTC_DR DU LL_RTC_DATE_Get\n
+ * RTC_DR YT LL_RTC_DATE_Get\n
+ * RTC_DR YU LL_RTC_DATE_Get
+ * @param RTCx RTC Instance
+ * @retval Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY).
+ */
+__STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx)
+{
+ uint32_t temp;
+
+ temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU));
+ return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \
+ (((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)) \
+ << RTC_OFFSET_DAY) | (((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | \
+ ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)) << RTC_OFFSET_MONTH) | \
+ ((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos)));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_ALARMA ALARMA
+ * @{
+ */
+
+/**
+ * @brief Enable Alarm A
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll RTC_CR ALRAE LL_RTC_ALMA_Enable
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_Enable(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_ALRAE);
+}
+
+/**
+ * @brief Disable Alarm A
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll RTC_CR ALRAE LL_RTC_ALMA_Disable
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_Disable(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_ALRAE);
+}
+
+/**
+ * @brief Specify the Alarm A masks.
+ * @rmtoll RTC_ALRMAR MSK4 LL_RTC_ALMA_SetMask\n
+ * RTC_ALRMAR MSK3 LL_RTC_ALMA_SetMask\n
+ * RTC_ALRMAR MSK2 LL_RTC_ALMA_SetMask\n
+ * RTC_ALRMAR MSK1 LL_RTC_ALMA_SetMask
+ * @param RTCx RTC Instance
+ * @param Mask This parameter can be a combination of the following values:
+ * @arg @ref LL_RTC_ALMA_MASK_NONE
+ * @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY
+ * @arg @ref LL_RTC_ALMA_MASK_HOURS
+ * @arg @ref LL_RTC_ALMA_MASK_MINUTES
+ * @arg @ref LL_RTC_ALMA_MASK_SECONDS
+ * @arg @ref LL_RTC_ALMA_MASK_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)
+{
+ MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1, Mask);
+}
+
+/**
+ * @brief Get the Alarm A masks.
+ * @rmtoll RTC_ALRMAR MSK4 LL_RTC_ALMA_GetMask\n
+ * RTC_ALRMAR MSK3 LL_RTC_ALMA_GetMask\n
+ * RTC_ALRMAR MSK2 LL_RTC_ALMA_GetMask\n
+ * RTC_ALRMAR MSK1 LL_RTC_ALMA_GetMask
+ * @param RTCx RTC Instance
+ * @retval Returned value can be can be a combination of the following values:
+ * @arg @ref LL_RTC_ALMA_MASK_NONE
+ * @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY
+ * @arg @ref LL_RTC_ALMA_MASK_HOURS
+ * @arg @ref LL_RTC_ALMA_MASK_MINUTES
+ * @arg @ref LL_RTC_ALMA_MASK_SECONDS
+ * @arg @ref LL_RTC_ALMA_MASK_ALL
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1));
+}
+
+/**
+ * @brief Enable AlarmA Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care)
+ * @rmtoll RTC_ALRMAR WDSEL LL_RTC_ALMA_EnableWeekday
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_EnableWeekday(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);
+}
+
+/**
+ * @brief Disable AlarmA Week day selection (DU[3:0] represents the date )
+ * @rmtoll RTC_ALRMAR WDSEL LL_RTC_ALMA_DisableWeekday
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_DisableWeekday(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);
+}
+
+/**
+ * @brief Set ALARM A Day in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
+ * @rmtoll RTC_ALRMAR DT LL_RTC_ALMA_SetDay\n
+ * RTC_ALRMAR DU LL_RTC_ALMA_SetDay
+ * @param RTCx RTC Instance
+ * @param Day Value between Min_Data=0x01 and Max_Data=0x31
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
+{
+ MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU),
+ (((Day & 0xF0U) << (RTC_ALRMAR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMAR_DU_Pos)));
+}
+
+/**
+ * @brief Get ALARM A Day in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
+ * @rmtoll RTC_ALRMAR DT LL_RTC_ALMA_GetDay\n
+ * RTC_ALRMAR DU LL_RTC_ALMA_GetDay
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x01 and Max_Data=0x31
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU))) >> RTC_ALRMAR_DU_Pos);
+}
+
+/**
+ * @brief Set ALARM A Weekday
+ * @rmtoll RTC_ALRMAR DU LL_RTC_ALMA_SetWeekDay
+ * @param RTCx RTC Instance
+ * @param WeekDay This parameter can be one of the following values:
+ * @arg @ref LL_RTC_WEEKDAY_MONDAY
+ * @arg @ref LL_RTC_WEEKDAY_TUESDAY
+ * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+ * @arg @ref LL_RTC_WEEKDAY_THURSDAY
+ * @arg @ref LL_RTC_WEEKDAY_FRIDAY
+ * @arg @ref LL_RTC_WEEKDAY_SATURDAY
+ * @arg @ref LL_RTC_WEEKDAY_SUNDAY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
+{
+ MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_DU, WeekDay << RTC_ALRMAR_DU_Pos);
+}
+
+/**
+ * @brief Get ALARM A Weekday
+ * @rmtoll RTC_ALRMAR DU LL_RTC_ALMA_GetWeekDay
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_WEEKDAY_MONDAY
+ * @arg @ref LL_RTC_WEEKDAY_TUESDAY
+ * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+ * @arg @ref LL_RTC_WEEKDAY_THURSDAY
+ * @arg @ref LL_RTC_WEEKDAY_FRIDAY
+ * @arg @ref LL_RTC_WEEKDAY_SATURDAY
+ * @arg @ref LL_RTC_WEEKDAY_SUNDAY
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos);
+}
+
+/**
+ * @brief Set Alarm A time format (AM/24-hour or PM notation)
+ * @rmtoll RTC_ALRMAR PM LL_RTC_ALMA_SetTimeFormat
+ * @param RTCx RTC Instance
+ * @param TimeFormat This parameter can be one of the following values:
+ * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
+ * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
+{
+ MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM, TimeFormat);
+}
+
+/**
+ * @brief Get Alarm A time format (AM or PM notation)
+ * @rmtoll RTC_ALRMAR PM LL_RTC_ALMA_GetTimeFormat
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
+ * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_PM));
+}
+
+/**
+ * @brief Set ALARM A Hours in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
+ * @rmtoll RTC_ALRMAR HT LL_RTC_ALMA_SetHour\n
+ * RTC_ALRMAR HU LL_RTC_ALMA_SetHour
+ * @param RTCx RTC Instance
+ * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
+{
+ MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU),
+ (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)));
+}
+
+/**
+ * @brief Get ALARM A Hours in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
+ * @rmtoll RTC_ALRMAR HT LL_RTC_ALMA_GetHour\n
+ * RTC_ALRMAR HU LL_RTC_ALMA_GetHour
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU))) >> RTC_ALRMAR_HU_Pos);
+}
+
+/**
+ * @brief Set ALARM A Minutes in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
+ * @rmtoll RTC_ALRMAR MNT LL_RTC_ALMA_SetMinute\n
+ * RTC_ALRMAR MNU LL_RTC_ALMA_SetMinute
+ * @param RTCx RTC Instance
+ * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
+{
+ MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU),
+ (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)));
+}
+
+/**
+ * @brief Get ALARM A Minutes in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
+ * @rmtoll RTC_ALRMAR MNT LL_RTC_ALMA_GetMinute\n
+ * RTC_ALRMAR MNU LL_RTC_ALMA_GetMinute
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x59
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU))) >> RTC_ALRMAR_MNU_Pos);
+}
+
+/**
+ * @brief Set ALARM A Seconds in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
+ * @rmtoll RTC_ALRMAR ST LL_RTC_ALMA_SetSecond\n
+ * RTC_ALRMAR SU LL_RTC_ALMA_SetSecond
+ * @param RTCx RTC Instance
+ * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
+{
+ MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU),
+ (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos)));
+}
+
+/**
+ * @brief Get ALARM A Seconds in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
+ * @rmtoll RTC_ALRMAR ST LL_RTC_ALMA_GetSecond\n
+ * RTC_ALRMAR SU LL_RTC_ALMA_GetSecond
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x59
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU))) >> RTC_ALRMAR_SU_Pos);
+}
+
+/**
+ * @brief Set Alarm A Time (hour, minute and second) in BCD format
+ * @rmtoll RTC_ALRMAR PM LL_RTC_ALMA_ConfigTime\n
+ * RTC_ALRMAR HT LL_RTC_ALMA_ConfigTime\n
+ * RTC_ALRMAR HU LL_RTC_ALMA_ConfigTime\n
+ * RTC_ALRMAR MNT LL_RTC_ALMA_ConfigTime\n
+ * RTC_ALRMAR MNU LL_RTC_ALMA_ConfigTime\n
+ * RTC_ALRMAR ST LL_RTC_ALMA_ConfigTime\n
+ * RTC_ALRMAR SU LL_RTC_ALMA_ConfigTime
+ * @param RTCx RTC Instance
+ * @param Format12_24 This parameter can be one of the following values:
+ * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
+ * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
+ * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+ * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59
+ * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes,
+ uint32_t Seconds)
+{
+ uint32_t temp;
+
+ temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)) | \
+ (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \
+ (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos));
+
+ MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | \
+ RTC_ALRMAR_ST | RTC_ALRMAR_SU, temp);
+}
+
+/**
+ * @brief Get Alarm B Time (hour, minute and second) in BCD format
+ * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
+ * are available to get independently each parameter.
+ * @rmtoll RTC_ALRMAR HT LL_RTC_ALMA_GetTime\n
+ * RTC_ALRMAR HU LL_RTC_ALMA_GetTime\n
+ * RTC_ALRMAR MNT LL_RTC_ALMA_GetTime\n
+ * RTC_ALRMAR MNU LL_RTC_ALMA_GetTime\n
+ * RTC_ALRMAR ST LL_RTC_ALMA_GetTime\n
+ * RTC_ALRMAR SU LL_RTC_ALMA_GetTime
+ * @param RTCx RTC Instance
+ * @retval Combination of hours, minutes and seconds.
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)((LL_RTC_ALMA_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMA_GetMinute(RTCx) << \
+ RTC_OFFSET_MINUTE) | LL_RTC_ALMA_GetSecond(RTCx));
+}
+
+/**
+ * @brief Set Alarm A Mask the most-significant bits starting at this bit
+ * @note This register can be written only when ALRAE is reset in RTC_CR register,
+ * or in initialization mode.
+ * @rmtoll RTC_ALRMASSR MASKSS LL_RTC_ALMA_SetSubSecondMask
+ * @param RTCx RTC Instance
+ * @param Mask If binary mode is none, Value between Min_Data=0x0 and Max_Data=0xF
+ * else Value between Min_Data=0x0 and Max_Data=0x3F
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
+{
+ MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS, Mask << RTC_ALRMASSR_MASKSS_Pos);
+}
+
+/**
+ * @brief Get Alarm A Mask the most-significant bits starting at this bit
+ * @rmtoll RTC_ALRMASSR MASKSS LL_RTC_ALMA_GetSubSecondMask
+ * @param RTCx RTC Instance
+ * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0xF
+ * else Value between Min_Data=0x0 and Max_Data=0x3F
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_ALRMASSR_MASKSS_Pos);
+}
+
+/**
+ * @brief Set Alarm A Binary mode auto clear
+ * @note This register can be written only when ALRAE is reset in RTC_CR register,
+ * or in initialization mode.
+ * @rmtoll RTC_ALRABINR SSCLR LL_RTC_ALMA_SetBinAutoClr
+ * @param RTCx RTC Instance
+ * @param BinaryAutoClr This parameter can be one of the following values:
+ * @arg @ref LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_NO
+ * @arg @ref LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_YES
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_SetBinAutoClr(RTC_TypeDef *RTCx, uint32_t BinaryAutoClr)
+{
+ MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_SSCLR, BinaryAutoClr);
+}
+
+/**
+ * @brief Get Alarm A Binary mode auto clear
+ * @rmtoll RTC_ALRABINR SSCLR LL_RTC_ALMA_GetBinAutoClr
+ * @param RTCx RTC Instance
+ * @retval It can be one of the following values:
+ * @arg @ref LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_NO
+ * @arg @ref LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_YES
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetBinAutoClr(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SSCLR));
+}
+
+/**
+ * @brief Set Alarm A Sub seconds value
+ * @rmtoll RCT_ALRMASSR SS LL_RTC_ALMA_SetSubSecond
+ * @param RTCx RTC Instance
+ * @param Subsecond If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF
+ * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond)
+{
+ MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_SS, Subsecond);
+}
+
+/**
+ * @brief Get Alarm A Sub seconds value
+ * @rmtoll RCT_ALRMASSR SS LL_RTC_ALMA_GetSubSecond
+ * @param RTCx RTC Instance
+ * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF
+ * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SS));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_ALARMB ALARMB
+ * @{
+ */
+
+/**
+ * @brief Enable Alarm B
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll RTC_CR ALRBE LL_RTC_ALMB_Enable
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_Enable(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_ALRBE);
+}
+
+/**
+ * @brief Disable Alarm B
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll RTC_CR ALRBE LL_RTC_ALMB_Disable
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_Disable(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_ALRBE);
+}
+
+/**
+ * @brief Specify the Alarm B masks.
+ * @rmtoll RTC_ALRMBR MSK4 LL_RTC_ALMB_SetMask\n
+ * RTC_ALRMBR MSK3 LL_RTC_ALMB_SetMask\n
+ * RTC_ALRMBR MSK2 LL_RTC_ALMB_SetMask\n
+ * RTC_ALRMBR MSK1 LL_RTC_ALMB_SetMask
+ * @param RTCx RTC Instance
+ * @param Mask This parameter can be a combination of the following values:
+ * @arg @ref LL_RTC_ALMB_MASK_NONE
+ * @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY
+ * @arg @ref LL_RTC_ALMB_MASK_HOURS
+ * @arg @ref LL_RTC_ALMB_MASK_MINUTES
+ * @arg @ref LL_RTC_ALMB_MASK_SECONDS
+ * @arg @ref LL_RTC_ALMB_MASK_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)
+{
+ MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1, Mask);
+}
+
+/**
+ * @brief Get the Alarm B masks.
+ * @rmtoll RTC_ALRMBR MSK4 LL_RTC_ALMB_GetMask\n
+ * RTC_ALRMBR MSK3 LL_RTC_ALMB_GetMask\n
+ * RTC_ALRMBR MSK2 LL_RTC_ALMB_GetMask\n
+ * RTC_ALRMBR MSK1 LL_RTC_ALMB_GetMask
+ * @param RTCx RTC Instance
+ * @retval Returned value can be can be a combination of the following values:
+ * @arg @ref LL_RTC_ALMB_MASK_NONE
+ * @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY
+ * @arg @ref LL_RTC_ALMB_MASK_HOURS
+ * @arg @ref LL_RTC_ALMB_MASK_MINUTES
+ * @arg @ref LL_RTC_ALMB_MASK_SECONDS
+ * @arg @ref LL_RTC_ALMB_MASK_ALL
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1));
+}
+
+/**
+ * @brief Enable AlarmB Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care)
+ * @rmtoll RTC_ALRMBR WDSEL LL_RTC_ALMB_EnableWeekday
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_EnableWeekday(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);
+}
+
+/**
+ * @brief Disable AlarmB Week day selection (DU[3:0] represents the date )
+ * @rmtoll RTC_ALRMBR WDSEL LL_RTC_ALMB_DisableWeekday
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_DisableWeekday(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);
+}
+
+/**
+ * @brief Set ALARM B Day in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
+ * @rmtoll RTC_ALRMBR DT LL_RTC_ALMB_SetDay\n
+ * RTC_ALRMBR DU LL_RTC_ALMB_SetDay
+ * @param RTCx RTC Instance
+ * @param Day Value between Min_Data=0x01 and Max_Data=0x31
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
+{
+ MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU),
+ (((Day & 0xF0U) << (RTC_ALRMBR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMBR_DU_Pos)));
+}
+
+/**
+ * @brief Get ALARM B Day in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
+ * @rmtoll RTC_ALRMBR DT LL_RTC_ALMB_GetDay\n
+ * RTC_ALRMBR DU LL_RTC_ALMB_GetDay
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x01 and Max_Data=0x31
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU))) >> RTC_ALRMBR_DU_Pos);
+}
+
+/**
+ * @brief Set ALARM B Weekday
+ * @rmtoll RTC_ALRMBR DU LL_RTC_ALMB_SetWeekDay
+ * @param RTCx RTC Instance
+ * @param WeekDay This parameter can be one of the following values:
+ * @arg @ref LL_RTC_WEEKDAY_MONDAY
+ * @arg @ref LL_RTC_WEEKDAY_TUESDAY
+ * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+ * @arg @ref LL_RTC_WEEKDAY_THURSDAY
+ * @arg @ref LL_RTC_WEEKDAY_FRIDAY
+ * @arg @ref LL_RTC_WEEKDAY_SATURDAY
+ * @arg @ref LL_RTC_WEEKDAY_SUNDAY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
+{
+ MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_DU, WeekDay << RTC_ALRMBR_DU_Pos);
+}
+
+/**
+ * @brief Get ALARM B Weekday
+ * @rmtoll RTC_ALRMBR DU LL_RTC_ALMB_GetWeekDay
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_WEEKDAY_MONDAY
+ * @arg @ref LL_RTC_WEEKDAY_TUESDAY
+ * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+ * @arg @ref LL_RTC_WEEKDAY_THURSDAY
+ * @arg @ref LL_RTC_WEEKDAY_FRIDAY
+ * @arg @ref LL_RTC_WEEKDAY_SATURDAY
+ * @arg @ref LL_RTC_WEEKDAY_SUNDAY
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos);
+}
+
+/**
+ * @brief Set ALARM B time format (AM/24-hour or PM notation)
+ * @rmtoll RTC_ALRMBR PM LL_RTC_ALMB_SetTimeFormat
+ * @param RTCx RTC Instance
+ * @param TimeFormat This parameter can be one of the following values:
+ * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
+ * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
+{
+ MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM, TimeFormat);
+}
+
+/**
+ * @brief Get ALARM B time format (AM or PM notation)
+ * @rmtoll RTC_ALRMBR PM LL_RTC_ALMB_GetTimeFormat
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
+ * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_PM));
+}
+
+/**
+ * @brief Set ALARM B Hours in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
+ * @rmtoll RTC_ALRMBR HT LL_RTC_ALMB_SetHour\n
+ * RTC_ALRMBR HU LL_RTC_ALMB_SetHour
+ * @param RTCx RTC Instance
+ * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
+{
+ MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU),
+ (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)));
+}
+
+/**
+ * @brief Get ALARM B Hours in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
+ * @rmtoll RTC_ALRMBR HT LL_RTC_ALMB_GetHour\n
+ * RTC_ALRMBR HU LL_RTC_ALMB_GetHour
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU))) >> RTC_ALRMBR_HU_Pos);
+}
+
+/**
+ * @brief Set ALARM B Minutes in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
+ * @rmtoll RTC_ALRMBR MNT LL_RTC_ALMB_SetMinute\n
+ * RTC_ALRMBR MNU LL_RTC_ALMB_SetMinute
+ * @param RTCx RTC Instance
+ * @param Minutes between Min_Data=0x00 and Max_Data=0x59
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
+{
+ MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU),
+ (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)));
+}
+
+/**
+ * @brief Get ALARM B Minutes in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
+ * @rmtoll RTC_ALRMBR MNT LL_RTC_ALMB_GetMinute\n
+ * RTC_ALRMBR MNU LL_RTC_ALMB_GetMinute
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x59
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU))) >> RTC_ALRMBR_MNU_Pos);
+}
+
+/**
+ * @brief Set ALARM B Seconds in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
+ * @rmtoll RTC_ALRMBR ST LL_RTC_ALMB_SetSecond\n
+ * RTC_ALRMBR SU LL_RTC_ALMB_SetSecond
+ * @param RTCx RTC Instance
+ * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
+{
+ MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU),
+ (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos)));
+}
+
+/**
+ * @brief Get ALARM B Seconds in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
+ * @rmtoll RTC_ALRMBR ST LL_RTC_ALMB_GetSecond\n
+ * RTC_ALRMBR SU LL_RTC_ALMB_GetSecond
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x59
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU))) >> RTC_ALRMBR_SU_Pos);
+}
+
+/**
+ * @brief Set Alarm B Time (hour, minute and second) in BCD format
+ * @rmtoll RTC_ALRMBR PM LL_RTC_ALMB_ConfigTime\n
+ * RTC_ALRMBR HT LL_RTC_ALMB_ConfigTime\n
+ * RTC_ALRMBR HU LL_RTC_ALMB_ConfigTime\n
+ * RTC_ALRMBR MNT LL_RTC_ALMB_ConfigTime\n
+ * RTC_ALRMBR MNU LL_RTC_ALMB_ConfigTime\n
+ * RTC_ALRMBR ST LL_RTC_ALMB_ConfigTime\n
+ * RTC_ALRMBR SU LL_RTC_ALMB_ConfigTime
+ * @param RTCx RTC Instance
+ * @param Format12_24 This parameter can be one of the following values:
+ * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
+ * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
+ * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+ * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59
+ * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes,
+ uint32_t Seconds)
+{
+ uint32_t temp;
+
+ temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)) | \
+ (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \
+ (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos));
+
+ MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM | RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | \
+ RTC_ALRMBR_ST | RTC_ALRMBR_SU, temp);
+}
+
+/**
+ * @brief Get Alarm B Time (hour, minute and second) in BCD format
+ * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
+ * are available to get independently each parameter.
+ * @rmtoll RTC_ALRMBR HT LL_RTC_ALMB_GetTime\n
+ * RTC_ALRMBR HU LL_RTC_ALMB_GetTime\n
+ * RTC_ALRMBR MNT LL_RTC_ALMB_GetTime\n
+ * RTC_ALRMBR MNU LL_RTC_ALMB_GetTime\n
+ * RTC_ALRMBR ST LL_RTC_ALMB_GetTime\n
+ * RTC_ALRMBR SU LL_RTC_ALMB_GetTime
+ * @param RTCx RTC Instance
+ * @retval Combination of hours, minutes and seconds.
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)((LL_RTC_ALMB_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMB_GetMinute(RTCx) << \
+ RTC_OFFSET_MINUTE) | LL_RTC_ALMB_GetSecond(RTCx));
+}
+
+/**
+ * @brief Set Alarm B Mask the most-significant bits starting at this bit
+ * @note This register can be written only when ALRBE is reset in RTC_CR register,
+ * or in initialization mode.
+ * @rmtoll RTC_ALRMBSSR MASKSS LL_RTC_ALMB_SetSubSecondMask
+ * @param RTCx RTC Instance
+ * @param Mask If binary mode is none, Value between Min_Data=0x0 and Max_Data=0xF
+ * else Value between Min_Data=0x0 and Max_Data=0x3F
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
+{
+ MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS, Mask << RTC_ALRMBSSR_MASKSS_Pos);
+}
+
+/**
+ * @brief Get Alarm B Mask the most-significant bits starting at this bit
+ * @rmtoll RTC_ALRMBSSR MASKSS LL_RTC_ALMB_GetSubSecondMask
+ * @param RTCx RTC Instance
+ * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0xF
+ * else Value between Min_Data=0x0 and Max_Data=0x3F
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS) >> RTC_ALRMBSSR_MASKSS_Pos);
+}
+
+/**
+ * @brief Set Alarm B Binary mode auto clear
+ * @note This register can be written only when ALRBE is reset in RTC_CR register,
+ * or in initialization mode.
+ * @rmtoll RTC_ALRBBINR SSCLR LL_RTC_ALMB_SetBinAutoClr
+ * @param RTCx RTC Instance
+ * @param BinaryAutoClr This parameter can be one of the following values:
+ * @arg @ref LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_NO
+ * @arg @ref LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_YES
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_SetBinAutoClr(RTC_TypeDef *RTCx, uint32_t BinaryAutoClr)
+{
+ MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_SSCLR, BinaryAutoClr);
+}
+
+/**
+ * @brief Get Alarm B Binary mode auto clear
+ * @rmtoll RTC_ALRBBINR SSCLR LL_RTC_ALMB_GetBinAutoClr
+ * @param RTCx RTC Instance
+ * @retval It can be one of the following values:
+ * @arg @ref LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_NO
+ * @arg @ref LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_YES
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetBinAutoClr(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SSCLR));
+}
+
+/**
+ * @brief Set Alarm B Sub seconds value
+ * @rmtoll RTC_ALRMBSSR SS LL_RTC_ALMB_SetSubSecond
+ * @param RTCx RTC Instance
+ * @param Subsecond If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF
+ * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond)
+{
+ MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS, Subsecond);
+}
+
+/**
+ * @brief Get Alarm B Sub seconds value
+ * @rmtoll RTC_ALRMBSSR SS LL_RTC_ALMB_GetSubSecond
+ * @param RTCx RTC Instance
+ * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF
+ * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_Timestamp Timestamp
+ * @{
+ */
+
+/**
+ * @brief Enable internal event timestamp
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll RTC_CR ITSE LL_RTC_TS_EnableInternalEvent
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TS_EnableInternalEvent(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_ITSE);
+}
+
+/**
+ * @brief Disable internal event timestamp
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll RTC_CR ITSE LL_RTC_TS_DisableInternalEvent
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TS_DisableInternalEvent(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_ITSE);
+}
+
+/**
+ * @brief Enable Timestamp
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll RTC_CR TSE LL_RTC_TS_Enable
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TS_Enable(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_TSE);
+}
+
+/**
+ * @brief Disable Timestamp
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll RTC_CR TSE LL_RTC_TS_Disable
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TS_Disable(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_TSE);
+}
+
+/**
+ * @brief Set Time-stamp event active edge
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting
+ * @rmtoll RTC_CR TSEDGE LL_RTC_TS_SetActiveEdge
+ * @param RTCx RTC Instance
+ * @param Edge This parameter can be one of the following values:
+ * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING
+ * @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge)
+{
+ MODIFY_REG(RTCx->CR, RTC_CR_TSEDGE, Edge);
+}
+
+/**
+ * @brief Get Time-stamp event active edge
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll RTC_CR TSEDGE LL_RTC_TS_GetActiveEdge
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING
+ * @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TSEDGE));
+}
+
+/**
+ * @brief Get Timestamp AM/PM notation (AM or 24-hour format)
+ * @rmtoll RTC_TSTR PM LL_RTC_TS_GetTimeFormat
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_TS_TIME_FORMAT_AM
+ * @arg @ref LL_RTC_TS_TIME_FORMAT_PM
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_PM));
+}
+
+/**
+ * @brief Get Timestamp Hours in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
+ * @rmtoll RTC_TSTR HT LL_RTC_TS_GetHour\n
+ * RTC_TSTR HU LL_RTC_TS_GetHour
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_TSTR_HU_Pos);
+}
+
+/**
+ * @brief Get Timestamp Minutes in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
+ * @rmtoll RTC_TSTR MNT LL_RTC_TS_GetMinute\n
+ * RTC_TSTR MNU LL_RTC_TS_GetMinute
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x59
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos);
+}
+
+/**
+ * @brief Get Timestamp Seconds in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
+ * @rmtoll RTC_TSTR ST LL_RTC_TS_GetSecond\n
+ * RTC_TSTR SU LL_RTC_TS_GetSecond
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x59
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_ST | RTC_TSTR_SU));
+}
+
+/**
+ * @brief Get Timestamp time (hour, minute and second) in BCD format
+ * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
+ * are available to get independently each parameter.
+ * @rmtoll RTC_TSTR HT LL_RTC_TS_GetTime\n
+ * RTC_TSTR HU LL_RTC_TS_GetTime\n
+ * RTC_TSTR MNT LL_RTC_TS_GetTime\n
+ * RTC_TSTR MNU LL_RTC_TS_GetTime\n
+ * RTC_TSTR ST LL_RTC_TS_GetTime\n
+ * RTC_TSTR SU LL_RTC_TS_GetTime
+ * @param RTCx RTC Instance
+ * @retval Combination of hours, minutes and seconds.
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TSTR,
+ RTC_TSTR_HT | RTC_TSTR_HU | RTC_TSTR_MNT | RTC_TSTR_MNU | RTC_TSTR_ST | RTC_TSTR_SU));
+}
+
+/**
+ * @brief Get Timestamp Week day
+ * @rmtoll RTC_TSDR WDU LL_RTC_TS_GetWeekDay
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_WEEKDAY_MONDAY
+ * @arg @ref LL_RTC_WEEKDAY_TUESDAY
+ * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+ * @arg @ref LL_RTC_WEEKDAY_THURSDAY
+ * @arg @ref LL_RTC_WEEKDAY_FRIDAY
+ * @arg @ref LL_RTC_WEEKDAY_SATURDAY
+ * @arg @ref LL_RTC_WEEKDAY_SUNDAY
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos);
+}
+
+/**
+ * @brief Get Timestamp Month in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
+ * @rmtoll RTC_TSDR MT LL_RTC_TS_GetMonth\n
+ * RTC_TSDR MU LL_RTC_TS_GetMonth
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_MONTH_JANUARY
+ * @arg @ref LL_RTC_MONTH_FEBRUARY
+ * @arg @ref LL_RTC_MONTH_MARCH
+ * @arg @ref LL_RTC_MONTH_APRIL
+ * @arg @ref LL_RTC_MONTH_MAY
+ * @arg @ref LL_RTC_MONTH_JUNE
+ * @arg @ref LL_RTC_MONTH_JULY
+ * @arg @ref LL_RTC_MONTH_AUGUST
+ * @arg @ref LL_RTC_MONTH_SEPTEMBER
+ * @arg @ref LL_RTC_MONTH_OCTOBER
+ * @arg @ref LL_RTC_MONTH_NOVEMBER
+ * @arg @ref LL_RTC_MONTH_DECEMBER
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_TSDR_MU_Pos);
+}
+
+/**
+ * @brief Get Timestamp Day in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
+ * @rmtoll RTC_TSDR DT LL_RTC_TS_GetDay\n
+ * RTC_TSDR DU LL_RTC_TS_GetDay
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x01 and Max_Data=0x31
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_DT | RTC_TSDR_DU));
+}
+
+/**
+ * @brief Get Timestamp date (WeekDay, Day and Month) in BCD format
+ * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_MONTH,
+ * and __LL_RTC_GET_DAY are available to get independently each parameter.
+ * @rmtoll RTC_TSDR WDU LL_RTC_TS_GetDate\n
+ * RTC_TSDR MT LL_RTC_TS_GetDate\n
+ * RTC_TSDR MU LL_RTC_TS_GetDate\n
+ * RTC_TSDR DT LL_RTC_TS_GetDate\n
+ * RTC_TSDR DU LL_RTC_TS_GetDate
+ * @param RTCx RTC Instance
+ * @retval Combination of Weekday, Day and Month
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU | RTC_TSDR_MT | RTC_TSDR_MU | RTC_TSDR_DT | RTC_TSDR_DU));
+}
+
+/**
+ * @brief Get time-stamp sub second value
+ * @rmtoll RTC_TSDR SS LL_RTC_TS_GetSubSecond
+ * @param RTCx RTC Instance
+ * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF
+ * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TSSSR, RTC_TSSSR_SS));
+}
+
+/**
+ * @brief Activate timestamp on tamper detection event
+ * @rmtoll RTC_CR TAMPTS LL_RTC_TS_EnableOnTamper
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TS_EnableOnTamper(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_TAMPTS);
+}
+
+/**
+ * @brief Disable timestamp on tamper detection event
+ * @rmtoll RTC_CR TAMPTS LL_RTC_TS_DisableOnTamper
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_TAMPTS);
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_Tamper Tamper
+ * @{
+ */
+
+/**
+ * @brief Enable TAMPx input detection
+ * @rmtoll TAMP_CR1 TAMP1E LL_RTC_TAMPER_Enable\n
+ * TAMP_CR1 TAMP2E... LL_RTC_TAMPER_Enable\n
+ * @param RTCx RTC Instance
+ * @param Tamper This parameter can be a combination of the following values:
+ * @arg @ref RTC_LL_EC_TAMPER
+ *
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->CR1, Tamper);
+}
+
+/**
+ * @brief Clear TAMPx input detection
+ * @rmtoll TAMP_CR1 TAMP1E LL_RTC_TAMPER_Disable\n
+ * TAMP_CR1 TAMP2E... LL_RTC_TAMPER_Disable
+ * @param RTCx RTC Instance
+ * @param Tamper This parameter can be a combination of the following values:
+ * @arg @ref RTC_LL_EC_TAMPER
+ *
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper)
+{
+ UNUSED(RTCx);
+ CLEAR_BIT(TAMP->CR1, Tamper);
+}
+
+/**
+ * @brief Enable Tamper mask flag
+ * @note Associated Tamper IT must not enabled when tamper mask is set.
+ * @rmtoll TAMP_CR2 TAMP1MF LL_RTC_TAMPER_EnableMask\n
+ * TAMP_CR2 TAMP2MF... LL_RTC_TAMPER_EnableMask
+ * @param RTCx RTC Instance
+ * @param Mask This parameter can be a combination of the following values:
+ * @arg @ref RTC_LL_EC_TAMPER_MASK
+ *
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_EnableMask(RTC_TypeDef *RTCx, uint32_t Mask)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->CR2, Mask);
+}
+
+/**
+ * @brief Disable Tamper mask flag
+ * @rmtoll TAMP_CR2 TAMP1MF LL_RTC_TAMPER_DisableMask\n
+ * TAMP_CR2 TAMP2MF... LL_RTC_TAMPER_DisableMask
+ * @param RTCx RTC Instance
+ * @param Mask This parameter can be a combination of the following values:
+ * @arg @ref RTC_LL_EC_TAMPER_MASK
+ *
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_DisableMask(RTC_TypeDef *RTCx, uint32_t Mask)
+{
+ UNUSED(RTCx);
+ CLEAR_BIT(TAMP->CR2, Mask);
+}
+
+/**
+ * @brief Enable backup register erase after Tamper event detection
+ * @rmtoll TAMP_CR2 TAMP1NOERASE LL_RTC_TAMPER_EnableEraseBKP\n
+ * TAMP_CR2 TAMP2NOERASE... LL_RTC_TAMPER_EnableEraseBKP
+ * @param RTCx RTC Instance
+ * @param Tamper This parameter can be a combination of the following values:
+ * @arg @ref RTC_LL_EC_TAMPER_NOERASE
+ *
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper)
+{
+ UNUSED(RTCx);
+ CLEAR_BIT(TAMP->CR2, Tamper);
+}
+
+/**
+ * @brief Disable backup register erase after Tamper event detection
+ * @rmtoll TAMP_CR2 TAMP1NOERASE LL_RTC_TAMPER_DisableEraseBKP\n
+ * TAMP_CR2 TAMP2NOERASE... LL_RTC_TAMPER_DisableEraseBKP
+ * @param RTCx RTC Instance
+ * @param Tamper This parameter can be a combination of the following values:
+ * @arg @ref RTC_LL_EC_TAMPER_NOERASE
+ *
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->CR2, Tamper);
+}
+
+/**
+ * @brief Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)
+ * @rmtoll TAMP_FLTCR TAMPPUDIS LL_RTC_TAMPER_DisablePullUp
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPPUDIS);
+}
+
+/**
+ * @brief Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling)
+ * @rmtoll TAMP_FLTCR TAMPPUDIS LL_RTC_TAMPER_EnablePullUp
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ CLEAR_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPPUDIS);
+}
+
+/**
+ * @brief Set RTC_TAMPx precharge duration
+ * @rmtoll TAMP_FLTCR TAMPPRCH LL_RTC_TAMPER_SetPrecharge
+ * @param RTCx RTC Instance
+ * @param Duration This parameter can be one of the following values:
+ * @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK
+ * @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK
+ * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK
+ * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(RTC_TypeDef *RTCx, uint32_t Duration)
+{
+ UNUSED(RTCx);
+ MODIFY_REG(TAMP->FLTCR, TAMP_FLTCR_TAMPPRCH, Duration);
+}
+
+/**
+ * @brief Get RTC_TAMPx precharge duration
+ * @rmtoll TAMP_FLTCR TAMPPRCH LL_RTC_TAMPER_GetPrecharge
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK
+ * @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK
+ * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK
+ * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
+ */
+__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return (uint32_t)(READ_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPPRCH));
+}
+
+/**
+ * @brief Set RTC_TAMPx filter count
+ * @rmtoll TAMP_FLTCR TAMPFLT LL_RTC_TAMPER_SetFilterCount
+ * @param RTCx RTC Instance
+ * @param FilterCount This parameter can be one of the following values:
+ * @arg @ref LL_RTC_TAMPER_FILTER_DISABLE
+ * @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE
+ * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE
+ * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(RTC_TypeDef *RTCx, uint32_t FilterCount)
+{
+ UNUSED(RTCx);
+ MODIFY_REG(TAMP->FLTCR, TAMP_FLTCR_TAMPFLT, FilterCount);
+}
+
+/**
+ * @brief Get RTC_TAMPx filter count
+ * @rmtoll TAMP_FLTCR TAMPFLT LL_RTC_TAMPER_GetFilterCount
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_TAMPER_FILTER_DISABLE
+ * @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE
+ * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE
+ * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
+ */
+__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return (uint32_t)(READ_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPFLT));
+}
+
+/**
+ * @brief Set Tamper sampling frequency
+ * @rmtoll TAMP_FLTCR TAMPFREQ LL_RTC_TAMPER_SetSamplingFreq
+ * @param RTCx RTC Instance
+ * @param SamplingFreq This parameter can be one of the following values:
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(RTC_TypeDef *RTCx, uint32_t SamplingFreq)
+{
+ UNUSED(RTCx);
+ MODIFY_REG(TAMP->FLTCR, TAMP_FLTCR_TAMPFREQ, SamplingFreq);
+}
+
+/**
+ * @brief Get Tamper sampling frequency
+ * @rmtoll TAMP_FLTCR TAMPFREQ LL_RTC_TAMPER_GetSamplingFreq
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
+ */
+__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return (uint32_t)(READ_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPFREQ));
+}
+
+/**
+ * @brief Enable Active level for Tamper input
+ * @rmtoll TAMP_CR2 TAMP1TRG LL_RTC_TAMPER_EnableActiveLevel\n
+ * TAMP_CR2 TAMP2TRG... LL_RTC_TAMPER_EnableActiveLevel
+ * @param RTCx RTC Instance
+ * @param Tamper This parameter can be a combination of the following values:
+ * @arg @ref RTC_LL_EC_TAMPER_ACTIVELEVEL
+ *
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->CR2, Tamper);
+}
+
+/**
+ * @brief Disable Active level for Tamper input
+ * @rmtoll TAMP_CR2 TAMP1TRG LL_RTC_TAMPER_DisableActiveLevel\n
+ * TAMP_CR2 TAMP2TRG... LL_RTC_TAMPER_DisableActiveLevel
+ * @param RTCx RTC Instance
+ * @param Tamper This parameter can be a combination of the following values:
+ * @arg @ref RTC_LL_EC_TAMPER_ACTIVELEVEL
+ *
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
+{
+ UNUSED(RTCx);
+ CLEAR_BIT(TAMP->CR2, Tamper);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_Internal_Tamper Internal Tamper
+ * @{
+ */
+
+/**
+ * @brief Enable internal tamper detection.
+ * @rmtoll TAMP_CR1 ITAMP1E LL_RTC_TAMPER_ITAMP_Enable\n
+ * TAMP_CR1 ITAMP2E.. LL_RTC_TAMPER_ITAMP_Enable\n
+ * @param RTCx RTC Instance
+ * @param InternalTamper This parameter can be a combination of the following values:
+ * @arg @ref RTC_LL_EC_INTERNAL
+ *
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Enable(RTC_TypeDef *RTCx, uint32_t InternalTamper)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->CR1, InternalTamper);
+}
+
+/**
+ * @brief Disable internal tamper detection.
+ * @rmtoll TAMP_CR1 ITAMP1E LL_RTC_TAMPER_ITAMP_Disable\n
+ * TAMP_CR1 ITAMP2E LL_RTC_TAMPER_ITAMP_Disable\n
+ * TAMP_CR1 ITAMP3E LL_RTC_TAMPER_ITAMP_Disable\n
+ * TAMP_CR1 ITAMP5E LL_RTC_TAMPER_ITAMP_Disable\n
+ * TAMP_CR1 ITAMP8E LL_RTC_TAMPER_ITAMP_Disable
+ * @param RTCx RTC Instance
+ * @param InternalTamper This parameter can be a combination of the following values:
+ * @arg @ref RTC_LL_EC_INTERNAL
+ *
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Disable(RTC_TypeDef *RTCx, uint32_t InternalTamper)
+{
+ UNUSED(RTCx);
+ CLEAR_BIT(TAMP->CR1, InternalTamper);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_Active_Tamper Active Tamper
+ * @{
+ */
+/**
+ * @brief Enable tamper active mode.
+ * @rmtoll TAMP_ATCR1 TAMP1AM LL_RTC_TAMPER_ATAMP_EnableActiveMode\n
+ * @rmtoll TAMP_ATCR1 TAMP2AM LL_RTC_TAMPER_ATAMP_EnableActiveMode\n
+ * @rmtoll TAMP_ATCR1 TAMPxAM LL_RTC_TAMPER_ATAMP_EnableActiveMode\n
+ * @param Tamper to configure as active. This parameter can be a combination of the following values:
+ * @arg @ref RTC_LL_EC_ACTIVE_MODE
+ *
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_EnableActiveMode(uint32_t Tamper)
+{
+ SET_BIT(TAMP->ATCR1, Tamper);
+}
+
+/**
+ * @brief Disable tamper active mode.
+ * @rmtoll TAMP_ATCR1 TAMP1AM LL_RTC_TAMPER_ATAMP_DisableActiveMode\n
+ * @rmtoll TAMP_ATCR1 TAMP2AM LL_RTC_TAMPER_ATAMP_DisableActiveMode\n
+ * @rmtoll TAMP_ATCR1 TAMPxAM LL_RTC_TAMPER_ATAMP_DisableActiveMode\n
+ * @param Tamper to configure as active. This parameter can be a combination of the following values:
+ * @arg @ref RTC_LL_EC_ACTIVE_MODE
+ *
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_DisableActiveMode(uint32_t Tamper)
+{
+ CLEAR_BIT(TAMP->ATCR1, Tamper);
+}
+
+/**
+ * @brief Enable active tamper filter.
+ * @rmtoll TAMP_ATCR1 FLTEN LL_RTC_TAMPER_ATAMP_EnableFilter\n
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_EnableFilter(void)
+{
+ SET_BIT(TAMP->ATCR1, TAMP_ATCR1_FLTEN);
+}
+
+/**
+ * @brief Disable active tamper filter.
+ * @rmtoll TAMP_ATCR1 FLTEN LL_RTC_TAMPER_ATAMP_DisableFilter\n
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_DisableFilter(void)
+{
+ CLEAR_BIT(TAMP->ATCR1, TAMP_ATCR1_FLTEN);
+}
+
+/**
+ * @brief Set Active tamper output change period.
+ * @rmtoll TAMP_ATCR1 ATPER LL_RTC_TAMPER_ATAMP_SetOutputChangePeriod\n
+ * @param ActiveOutputChangePeriod This parameter can be a value from 0 to 7
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_SetOutputChangePeriod(uint32_t ActiveOutputChangePeriod)
+{
+ MODIFY_REG(TAMP->ATCR1, TAMP_ATCR1_ATPER, (ActiveOutputChangePeriod << TAMP_ATCR1_ATPER_Pos));
+}
+
+/**
+ * @brief Get Active tamper output change period.
+ * @rmtoll TAMP_ATCR1 ATPER LL_RTC_TAMPER_ATAMP_GetOutputChangePeriod\n
+ * @retval Output change period. This parameter can be a value from 0 to 7.
+ */
+__STATIC_INLINE uint32_t LL_RTC_TAMPER_ATAMP_GetOutputChangePeriod(void)
+{
+ return (READ_BIT(TAMP->ATCR1, TAMP_ATCR1_ATPER) >> TAMP_ATCR1_ATPER_Pos);
+}
+
+/**
+ * @brief Set Active tamper asynchronous prescaler clock selection.
+ * @rmtoll TAMP_ATCR1 ATCKSEL LL_RTC_TAMPER_ATAMP_SetAsyncPrescaler\n
+ * @param ActiveAsynvPrescaler Specifies the Active Tamper asynchronous Prescaler clock.
+ This parameter can be a value of the following values:
+ * @arg @ref RTC_LL_EC_ACTIVE_ASYNC_PRESCALER
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_SetAsyncPrescaler(uint32_t ActiveAsynvPrescaler)
+{
+ MODIFY_REG(TAMP->ATCR1, TAMP_ATCR1_ATCKSEL, ActiveAsynvPrescaler);
+}
+
+/**
+ * @brief Get Active tamper asynchronous prescaler clock selection.
+ * @rmtoll TAMP_ATCR1 ATCKSEL LL_RTC_TAMPER_ATAMP_GetAsyncPrescaler\n
+ * @retval One of @arg @ref RTC_LL_EC_ACTIVE_ASYNC_PRESCALER
+ */
+__STATIC_INLINE uint32_t LL_RTC_TAMPER_ATAMP_GetAsyncPrescaler(void)
+{
+ return (READ_BIT(TAMP->ATCR1, TAMP_ATCR1_ATCKSEL));
+}
+
+/**
+ * @brief Enable active tamper output sharing.
+ * @rmtoll TAMP_ATCR1 ATOSHARE LL_RTC_TAMPER_ATAMP_EnableOutputSharing\n
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_EnableOutputSharing(void)
+{
+ SET_BIT(TAMP->ATCR1, TAMP_ATCR1_ATOSHARE);
+}
+
+/**
+ * @brief Disable active tamper output sharing.
+ * @rmtoll TAMP_ATCR1 ATOSHARE LL_RTC_TAMPER_ATAMP_DisableOutputSharing\n
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_DisableOutputSharing(void)
+{
+ CLEAR_BIT(TAMP->ATCR1, TAMP_ATCR1_ATOSHARE);
+}
+
+/**
+ * @brief Set Active tamper output selection.
+ * @rmtoll TAMP_ATCR2 ATCKSEL LL_RTC_TAMPER_ATAMP_SetSharedOuputSelection\n
+ * @param OutputSelection Specifies all the output selection of the Active Tamper.
+ This parameter is a combinasation of the following values:
+ * One of @arg @ref RTC_LL_EC_ACTIVE_OUTPUT_SELECTION
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_SetSharedOuputSelection(uint32_t OutputSelection)
+{
+ MODIFY_REG(TAMP->ATCR2, (TAMP_ATCR2_ATOSEL1 | TAMP_ATCR2_ATOSEL2 | TAMP_ATCR2_ATOSEL3 | TAMP_ATCR2_ATOSEL4 | \
+ TAMP_ATCR2_ATOSEL5 | TAMP_ATCR2_ATOSEL6 | TAMP_ATCR2_ATOSEL7 | TAMP_ATCR2_ATOSEL8), \
+ OutputSelection);
+}
+
+/**
+ * @brief Get Active tamper asynchronous prescaler clock selection.
+ * @rmtoll TAMP_ATCR2 ATCKSEL LL_RTC_TAMPER_ATAMP_GetAsyncPrescaler\n
+ * @retval A combination of @arg @ref RTC_LL_EC_ACTIVE_OUTPUT_SELECTION
+ */
+__STATIC_INLINE uint32_t LL_RTC_TAMPER_ATAMP_GetSharedOuputSelection(void)
+{
+ return (READ_BIT(TAMP->ATCR2, (TAMP_ATCR2_ATOSEL1 | TAMP_ATCR2_ATOSEL2 | TAMP_ATCR2_ATOSEL3 | TAMP_ATCR2_ATOSEL4 | \
+ TAMP_ATCR2_ATOSEL5 | TAMP_ATCR2_ATOSEL6 | TAMP_ATCR2_ATOSEL7 | TAMP_ATCR2_ATOSEL8)));
+}
+
+/**
+ * @brief Write active tamper seed.
+ * @rmtoll TAMP_ATSEEDR SEED LL_RTC_TAMPER_ATAMP_WriteSeed\n
+ * @param Seed
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_WriteSeed(uint32_t Seed)
+{
+ WRITE_REG(TAMP->ATSEEDR, Seed);
+}
+
+/**
+ * @brief Get active tamper initialization status flag.
+ * @rmtoll TAMP_ATOR INITS LL_RTC_IsActiveFlag_ATAMP_INITS
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ATAMP_INITS(void)
+{
+ return ((READ_BIT(TAMP->ATOR, TAMP_ATOR_INITS) == (TAMP_ATOR_INITS)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get active tamper seed running status flag.
+ * @rmtoll TAMP_ATOR INITS LL_RTC_IsActiveFlag_ATAMP_INITS
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ATAMP_SEEDF(void)
+{
+ return ((READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) == (TAMP_ATOR_SEEDF)) ? 1U : 0U);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_Wakeup Wakeup
+ * @{
+ */
+
+/**
+ * @brief Enable Wakeup timer
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll RTC_CR WUTE LL_RTC_WAKEUP_Enable
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_WAKEUP_Enable(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_WUTE);
+}
+
+/**
+ * @brief Disable Wakeup timer
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll RTC_CR WUTE LL_RTC_WAKEUP_Disable
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_WUTE);
+}
+
+/**
+ * @brief Check if Wakeup timer is enabled or not
+ * @rmtoll RTC_CR WUTE LL_RTC_WAKEUP_IsEnabled
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx)
+{
+ return ((READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) ? 1U : 0U);
+}
+
+/**
+ * @brief Select Wakeup clock
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ICSR WUTWF bit = 1
+ * @rmtoll RTC_CR WUCKSEL LL_RTC_WAKEUP_SetClock
+ * @param RTCx RTC Instance
+ * @param WakeupClock This parameter can be one of the following values:
+ * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16
+ * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8
+ * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4
+ * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2
+ * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
+ * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupClock)
+{
+ MODIFY_REG(RTCx->CR, RTC_CR_WUCKSEL, WakeupClock);
+}
+
+/**
+ * @brief Get Wakeup clock
+ * @rmtoll RTC_CR WUCKSEL LL_RTC_WAKEUP_GetClock
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16
+ * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8
+ * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4
+ * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2
+ * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
+ * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
+ */
+__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL));
+}
+
+/**
+ * @brief Set Wakeup auto-reload value
+ * @note Bit can be written only when WUTWF is set to 1 in RTC_ICSR
+ * @rmtoll RTC_WUTR WUT LL_RTC_WAKEUP_SetAutoReload
+ * @param RTCx RTC Instance
+ * @param Value Value between Min_Data=0x00 and Max_Data=0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Value)
+{
+ MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUT, Value);
+}
+
+/**
+ * @brief Get Wakeup auto-reload value
+ * @rmtoll RTC_WUTR WUT LL_RTC_WAKEUP_GetAutoReload
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_Backup_Registers Backup_Registers
+ * @{
+ */
+
+/**
+ * @brief Writes a data in a specified Backup data register.
+ * @rmtoll TAMP_BKPxR BKP LL_RTC_BKP_SetRegister
+ * @param RTCx RTC Instance
+ * @param BackupRegister This parameter can be one of the following values:
+ * @arg @ref LL_RTC_BKP_DR0
+ * @arg @ref LL_RTC_BKP_DR1
+ * @arg @ref LL_RTC_BKP_DR2
+ * @arg @ref LL_RTC_BKP_DR3
+ * @arg @ref LL_RTC_BKP_DR4 ...
+ * @param Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_BKP_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data)
+{
+ __IO uint32_t tmp;
+
+ UNUSED(RTCx);
+
+ tmp = (uint32_t)(&(TAMP->BKP0R));
+ tmp += (BackupRegister * 4U);
+
+ /* Write the specified register */
+ *(__IO uint32_t *)tmp = (uint32_t)Data;
+}
+
+/**
+ * @brief Reads data from the specified RTC Backup data Register.
+ * @rmtoll TAMP_BKPxR BKP LL_RTC_BKP_GetRegister
+ * @param RTCx RTC Instance
+ * @param BackupRegister This parameter can be one of the following values:
+ * @arg @ref LL_RTC_BKP_DR0
+ * @arg @ref LL_RTC_BKP_DR1
+ * @arg @ref LL_RTC_BKP_DR2
+ * @arg @ref LL_RTC_BKP_DR3
+ * @arg @ref LL_RTC_BKP_DR4 ...
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister)
+{
+ uint32_t tmp;
+
+ UNUSED(RTCx);
+
+ tmp = (uint32_t)(&(TAMP->BKP0R));
+ tmp += (BackupRegister * 4U);
+
+ /* Read the specified register */
+ return (*(__IO uint32_t *)tmp);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_Calibration Calibration
+ * @{
+ */
+
+/**
+ * @brief Set Calibration output frequency (1 Hz or 512 Hz)
+ * @note Bits are write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll RTC_CR COE LL_RTC_CAL_SetOutputFreq\n
+ * RTC_CR COSEL LL_RTC_CAL_SetOutputFreq
+ * @param RTCx RTC Instance
+ * @param Frequency This parameter can be one of the following values:
+ * @arg @ref LL_RTC_CALIB_OUTPUT_NONE
+ * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ
+ * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Frequency)
+{
+ MODIFY_REG(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL, Frequency);
+}
+
+/**
+ * @brief Get Calibration output frequency (1 Hz or 512 Hz)
+ * @rmtoll RTC_CR COE LL_RTC_CAL_GetOutputFreq\n
+ * RTC_CR COSEL LL_RTC_CAL_GetOutputFreq
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_CALIB_OUTPUT_NONE
+ * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ
+ * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
+ */
+__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL));
+}
+
+/**
+ * @brief Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm)
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note Bit can be written only when RECALPF is set to 0 in RTC_ICSR
+ * @rmtoll RTC_CALR CALP LL_RTC_CAL_SetPulse
+ * @param RTCx RTC Instance
+ * @param Pulse This parameter can be one of the following values:
+ * @arg @ref LL_RTC_CALIB_INSERTPULSE_NONE
+ * @arg @ref LL_RTC_CALIB_INSERTPULSE_SET
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse)
+{
+ MODIFY_REG(RTCx->CALR, RTC_CALR_CALP, Pulse);
+}
+
+/**
+ * @brief Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm)
+ * @rmtoll RTC_CALR CALP LL_RTC_CAL_IsPulseInserted
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx)
+{
+ return ((READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)) ? 1U : 0U);
+}
+
+/**
+ * @brief Set the calibration cycle period
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note Bit can be written only when RECALPF is set to 0 in RTC_ICSR
+ * @rmtoll RTC_CALR CALW8 LL_RTC_CAL_SetPeriod\n
+ * RTC_CALR CALW16 LL_RTC_CAL_SetPeriod
+ * @param RTCx RTC Instance
+ * @param Period This parameter can be one of the following values:
+ * @arg @ref LL_RTC_CALIB_PERIOD_32SEC
+ * @arg @ref LL_RTC_CALIB_PERIOD_16SEC
+ * @arg @ref LL_RTC_CALIB_PERIOD_8SEC
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period)
+{
+ MODIFY_REG(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16, Period);
+}
+
+/**
+ * @brief Get the calibration cycle period
+ * @rmtoll RTC_CALR CALW8 LL_RTC_CAL_GetPeriod\n
+ * RTC_CALR CALW16 LL_RTC_CAL_GetPeriod
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_CALIB_PERIOD_32SEC
+ * @arg @ref LL_RTC_CALIB_PERIOD_16SEC
+ * @arg @ref LL_RTC_CALIB_PERIOD_8SEC
+ */
+__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16));
+}
+
+/**
+ * @brief Set Calibration minus
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note Bit can be written only when RECALPF is set to 0 in RTC_ICSR
+ * @rmtoll RTC_CALR CALM LL_RTC_CAL_SetMinus
+ * @param RTCx RTC Instance
+ * @param CalibMinus Value between Min_Data=0x00 and Max_Data=0x1FF
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus)
+{
+ MODIFY_REG(RTCx->CALR, RTC_CALR_CALM, CalibMinus);
+}
+
+/**
+ * @brief Get Calibration minus
+ * @rmtoll RTC_CALR CALM LL_RTC_CAL_GetMinus
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data= 0x1FF
+ */
+__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM));
+}
+
+/**
+ * @brief Enable Calibration Low Power
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note Bit can be written only when RECALPF is set to 0
+ * @rmtoll RTC_CALR LPCAL LL_RTC_CAL_LowPower_Enable
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_CAL_LowPower_Enable(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CALR, RTC_CALR_LPCAL);
+}
+
+/**
+ * @brief Disable Calibration Low Power
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note Bit can be written only when RECALPF is set to 0
+ * @rmtoll RTC_CALR LPCAL LL_RTC_CAL_LowPower_Disable
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_CAL_LowPower_Disable(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CALR, RTC_CALR_LPCAL);
+}
+
+/**
+ * @brief Check if Calibration Low Power is enabled or not
+ * @rmtoll RTC_CALR LPCAL LL_RTC_CAL_LowPower_IsEnabled
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_CAL_LowPower_IsEnabled(RTC_TypeDef *RTCx)
+{
+ return ((READ_BIT(RTCx->CALR, RTC_CALR_LPCAL) == (RTC_CALR_LPCAL)) ? 1U : 0U);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Get Internal Time-stamp flag
+ * @rmtoll RTC_SR ITSF LL_RTC_IsActiveFlag_ITS
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef *RTCx)
+{
+ return ((READ_BIT(RTCx->SR, RTC_SR_ITSF) == (RTC_SR_ITSF)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get Recalibration pending Flag
+ * @rmtoll RTC_ICSR RECALPF LL_RTC_IsActiveFlag_RECALP
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx)
+{
+ return ((READ_BIT(RTCx->ICSR, RTC_ICSR_RECALPF) == (RTC_ICSR_RECALPF)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get Time-stamp overflow flag
+ * @rmtoll RTC_SR TSOVF LL_RTC_IsActiveFlag_TSOV
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx)
+{
+ return ((READ_BIT(RTCx->SR, RTC_SR_TSOVF) == (RTC_SR_TSOVF)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get Time-stamp flag
+ * @rmtoll RTC_SR TSF LL_RTC_IsActiveFlag_TS
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx)
+{
+ return ((READ_BIT(RTCx->SR, RTC_SR_TSF) == (RTC_SR_TSF)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get Wakeup timer flag
+ * @rmtoll RTC_SR WUTF LL_RTC_IsActiveFlag_WUT
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx)
+{
+ return ((READ_BIT(RTCx->SR, RTC_SR_WUTF) == (RTC_SR_WUTF)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get Alarm B flag
+ * @rmtoll RTC_SR ALRBF LL_RTC_IsActiveFlag_ALRB
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx)
+{
+ return ((READ_BIT(RTCx->SR, RTC_SR_ALRBF) == (RTC_SR_ALRBF)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get Alarm A flag
+ * @rmtoll RTC_SR ALRAF LL_RTC_IsActiveFlag_ALRA
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx)
+{
+ return ((READ_BIT(RTCx->SR, RTC_SR_ALRAF) == (RTC_SR_ALRAF)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get SSR Underflow flag
+ * @rmtoll RTC_SR SSRUF LL_RTC_IsActiveFlag_SSRU
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SSRU(RTC_TypeDef *RTCx)
+{
+ return ((READ_BIT(RTCx->SR, RTC_SR_SSRUF) == (RTC_SR_SSRUF)) ? 1U : 0U);
+}
+
+/**
+ * @brief Clear Internal Time-stamp flag
+ * @rmtoll RTC_SCR CITSF LL_RTC_ClearFlag_ITS
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_ITS(RTC_TypeDef *RTCx)
+{
+ WRITE_REG(RTCx->SCR, RTC_SCR_CITSF);
+}
+
+/**
+ * @brief Clear Time-stamp overflow flag
+ * @rmtoll RTC_SCR CTSOVF LL_RTC_ClearFlag_TSOV
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_TSOV(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->SCR, RTC_SCR_CTSOVF);
+}
+
+/**
+ * @brief Clear Time-stamp flag
+ * @rmtoll RTC_SCR CTSF LL_RTC_ClearFlag_TS
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_TS(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->SCR, RTC_SCR_CTSF);
+}
+
+/**
+ * @brief Clear Wakeup timer flag
+ * @rmtoll RTC_SCR CWUTF LL_RTC_ClearFlag_WUT
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_WUT(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->SCR, RTC_SCR_CWUTF);
+}
+
+/**
+ * @brief Clear Alarm B flag
+ * @rmtoll RTC_SCR CALRBF LL_RTC_ClearFlag_ALRB
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_ALRB(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->SCR, RTC_SCR_CALRBF);
+}
+
+/**
+ * @brief Clear Alarm A flag
+ * @rmtoll RTC_SCR CALRAF LL_RTC_ClearFlag_ALRA
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx)
+{
+ WRITE_REG(RTCx->SCR, RTC_SCR_CALRAF);
+}
+
+/**
+ * @brief Clear SSR Underflow flag
+ * @rmtoll RTC_SCR CSSRUF LL_RTC_ClearFlag_SSRU
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_SSRU(RTC_TypeDef *RTCx)
+{
+ WRITE_REG(RTCx->SCR, RTC_SCR_CSSRUF);
+}
+
+/**
+ * @brief Get Initialization flag
+ * @rmtoll RTC_ICSR INITF LL_RTC_IsActiveFlag_INIT
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx)
+{
+ return ((READ_BIT(RTCx->ICSR, RTC_ICSR_INITF) == (RTC_ICSR_INITF)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get Registers synchronization flag
+ * @rmtoll RTC_ICSR RSF LL_RTC_IsActiveFlag_RS
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx)
+{
+ return ((READ_BIT(RTCx->ICSR, RTC_ICSR_RSF) == (RTC_ICSR_RSF)) ? 1U : 0U);
+}
+
+/**
+ * @brief Clear Registers synchronization flag
+ * @rmtoll RTC_ICSR RSF LL_RTC_ClearFlag_RS
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx)
+{
+ WRITE_REG(RTCx->ICSR, (~((RTC_ICSR_RSF | RTC_ICSR_INIT) & 0x000000FFU) | (RTCx->ICSR & RTC_ICSR_INIT)));
+}
+
+/**
+ * @brief Get Initialization status flag
+ * @rmtoll RTC_ICSR INITS LL_RTC_IsActiveFlag_INITS
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx)
+{
+ return ((READ_BIT(RTCx->ICSR, RTC_ICSR_INITS) == (RTC_ICSR_INITS)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get Shift operation pending flag
+ * @rmtoll RTC_ICSR SHPF LL_RTC_IsActiveFlag_SHP
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx)
+{
+ return ((READ_BIT(RTCx->ICSR, RTC_ICSR_SHPF) == (RTC_ICSR_SHPF)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get Wakeup timer write flag
+ * @rmtoll RTC_ICSR WUTWF LL_RTC_IsActiveFlag_WUTW
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx)
+{
+ return ((READ_BIT(RTCx->ICSR, RTC_ICSR_WUTWF) == (RTC_ICSR_WUTWF)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get Alarm A masked flag.
+ * @rmtoll RTC_MISR ALRAMF LL_RTC_IsActiveFlag_ALRAM
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAM(RTC_TypeDef *RTCx)
+{
+ return ((READ_BIT(RTCx->MISR, RTC_MISR_ALRAMF) == (RTC_MISR_ALRAMF)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get SSR Underflow masked flag.
+ * @rmtoll RTC_MISR SSRUMF LL_RTC_IsActiveFlag_SSRUM
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SSRUM(RTC_TypeDef *RTCx)
+{
+ return ((READ_BIT(RTCx->MISR, RTC_MISR_SSRUMF) == (RTC_MISR_SSRUMF)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get Alarm B masked flag.
+ * @rmtoll RTC_MISR ALRBMF LL_RTC_IsActiveFlag_ALRBM
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBM(RTC_TypeDef *RTCx)
+{
+ return ((READ_BIT(RTCx->MISR, RTC_MISR_ALRBMF) == (RTC_MISR_ALRBMF)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get Wakeup timer masked flag.
+ * @rmtoll RTC_MISR WUTMF LL_RTC_IsActiveFlag_WUTM
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTM(RTC_TypeDef *RTCx)
+{
+ return ((READ_BIT(RTCx->MISR, RTC_MISR_WUTMF) == (RTC_MISR_WUTMF)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get Time-stamp masked flag.
+ * @rmtoll RTC_MISR TSMF LL_RTC_IsActiveFlag_TSM
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSM(RTC_TypeDef *RTCx)
+{
+ return ((READ_BIT(RTCx->MISR, RTC_MISR_TSMF) == (RTC_MISR_TSMF)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get Time-stamp overflow masked flag.
+ * @rmtoll RTC_MISR TSOVMF LL_RTC_IsActiveFlag_TSOVM
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOVM(RTC_TypeDef *RTCx)
+{
+ return ((READ_BIT(RTCx->MISR, RTC_MISR_TSOVMF) == (RTC_MISR_TSOVMF)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get Internal Time-stamp masked flag.
+ * @rmtoll RTC_MISR ITSMF LL_RTC_IsActiveFlag_ITSM
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITSM(RTC_TypeDef *RTCx)
+{
+ return ((READ_BIT(RTCx->MISR, RTC_MISR_ITSMF) == (RTC_MISR_ITSMF)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get tamper 1 detection flag.
+ * @rmtoll TAMP_SR TAMP1F LL_RTC_IsActiveFlag_TAMP1
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP1F) == (TAMP_SR_TAMP1F)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get tamper 2 detection flag.
+ * @rmtoll TAMP_SR TAMP2F LL_RTC_IsActiveFlag_TAMP2
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP2F) == (TAMP_SR_TAMP2F)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get tamper 3 detection flag.
+ * @rmtoll TAMP_SR TAMP3F LL_RTC_IsActiveFlag_TAMP3
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP3F) == (TAMP_SR_TAMP3F)) ? 1U : 0U);
+}
+/**
+ * @brief Get tamper 4 detection flag.
+ * @rmtoll TAMP_SR TAMP4F LL_RTC_IsActiveFlag_TAMP4
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP4(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP4F) == (TAMP_SR_TAMP4F)) ? 1U : 0U);
+}
+/**
+ * @brief Get tamper 5 detection flag.
+ * @rmtoll TAMP_SR TAMP5F LL_RTC_IsActiveFlag_TAMP5
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP5(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP5F) == (TAMP_SR_TAMP5F)) ? 1U : 0U);
+}
+/**
+ * @brief Get tamper 6 detection flag.
+ * @rmtoll TAMP_SR TAMP6F LL_RTC_IsActiveFlag_TAMP6
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP6(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP6F) == (TAMP_SR_TAMP6F)) ? 1U : 0U);
+}
+/**
+ * @brief Get tamper 7 detection flag.
+ * @rmtoll TAMP_SR TAMP7F LL_RTC_IsActiveFlag_TAMP7
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP7(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP7F) == (TAMP_SR_TAMP7F)) ? 1U : 0U);
+}
+/**
+ * @brief Get tamper 8 detection flag.
+ * @rmtoll TAMP_SR TAMP8F LL_RTC_IsActiveFlag_TAMP8
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP8(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP8F) == (TAMP_SR_TAMP8F)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get internal tamper 1 detection flag.
+ * @rmtoll TAMP_SR ITAMP1F LL_RTC_IsActiveFlag_ITAMP1
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP1(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP1F) == (TAMP_SR_ITAMP1F)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get internal tamper 2 detection flag.
+ * @rmtoll TAMP_SR ITAMP2F LL_RTC_IsActiveFlag_ITAMP2
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP2(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP2F) == (TAMP_SR_ITAMP2F)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get internal tamper 3 detection flag.
+ * @rmtoll TAMP_SR ITAMP3F LL_RTC_IsActiveFlag_ITAMP3
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP3F) == (TAMP_SR_ITAMP3F)) ? 1U : 0U);
+}
+
+
+/**
+ * @brief Get internal tamper 5 detection flag.
+ * @rmtoll TAMP_SR ITAMP5F LL_RTC_IsActiveFlag_ITAMP5
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP5F) == (TAMP_SR_ITAMP5F)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get internal tamper 6 detection flag.
+ * @rmtoll TAMP_SR ITAMP6F LL_RTC_IsActiveFlag_ITAMP6
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP6(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP6F) == (TAMP_SR_ITAMP6F)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get internal tamper 8 detection flag.
+ * @rmtoll TAMP_SR ITAMP8F LL_RTC_IsActiveFlag_ITAMP8
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP8(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP8F) == (TAMP_SR_ITAMP8F)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get internal tamper 9 detection flag.
+ * @rmtoll TAMP_SR ITAMP9F LL_RTC_IsActiveFlag_ITAMP9
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP9(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP9F) == (TAMP_SR_ITAMP9F)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get internal tamper 11 detection flag.
+ * @rmtoll TAMP_SR ITAMP11F LL_RTC_IsActiveFlag_ITAMP11
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP11(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP11F) == (TAMP_SR_ITAMP11F)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get internal tamper 12 detection flag.
+ * @rmtoll TAMP_SR ITAMP12F LL_RTC_IsActiveFlag_ITAMP12
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP12(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP12F) == (TAMP_SR_ITAMP12F)) ? 1U : 0U);
+}
+/**
+ * @brief Get internal tamper 13 detection flag.
+ * @rmtoll TAMP_SR ITAMP13F LL_RTC_IsActiveFlag_ITAMP13
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP13(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP13F) == (TAMP_SR_ITAMP13F)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get tamper 1 interrupt masked flag.
+ * @rmtoll TAMP_MISR TAMP1MF LL_RTC_IsActiveFlag_TAMP1M
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1M(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP1MF) == (TAMP_MISR_TAMP1MF)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get tamper 2 interrupt masked flag.
+ * @rmtoll TAMP_MISR TAMP2MF LL_RTC_IsActiveFlag_TAMP2M
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2M(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP2MF) == (TAMP_MISR_TAMP2MF)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get tamper 3 interrupt masked flag.
+ * @rmtoll TAMP_MISR TAMP3MF LL_RTC_IsActiveFlag_TAMP3M
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3M(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP3MF) == (TAMP_MISR_TAMP3MF)) ? 1U : 0U);
+}
+/**
+ * @brief Get tamper 4 interrupt masked flag.
+ * @rmtoll TAMP_MISR TAMP4MF LL_RTC_IsActiveFlag_TAMP4M
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP4M(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP4MF) == (TAMP_MISR_TAMP4MF)) ? 1U : 0U);
+}
+/**
+ * @brief Get tamper 5 interrupt masked flag.
+ * @rmtoll TAMP_MISR TAMP5MF LL_RTC_IsActiveFlag_TAMP5M
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP5M(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP5MF) == (TAMP_MISR_TAMP5MF)) ? 1U : 0U);
+}
+/**
+ * @brief Get tamper 6 interrupt masked flag.
+ * @rmtoll TAMP_MISR TAMP3MF LL_RTC_IsActiveFlag_TAMP6M
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP6M(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP6MF) == (TAMP_MISR_TAMP6MF)) ? 1U : 0U);
+}
+/**
+ * @brief Get tamper 7 interrupt masked flag.
+ * @rmtoll TAMP_MISR TAMP7MF LL_RTC_IsActiveFlag_TAMP7M
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP7M(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP7MF) == (TAMP_MISR_TAMP7MF)) ? 1U : 0U);
+}
+/**
+ * @brief Get tamper 8 interrupt masked flag.
+ * @rmtoll TAMP_MISR TAMP8MF LL_RTC_IsActiveFlag_TAMP8M
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP8M(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP8MF) == (TAMP_MISR_TAMP8MF)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get internal tamper 1 interrupt masked flag.
+ * @rmtoll TAMP_MISR ITAMP1MF LL_RTC_IsActiveFlag_ITAMP1M
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP1M(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP1MF) == (TAMP_MISR_ITAMP1MF)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get internal tamper 2 interrupt masked flag.
+ * @rmtoll TAMP_MISR ITAMP2MF LL_RTC_IsActiveFlag_ITAMP2M
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP2M(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP2MF) == (TAMP_MISR_ITAMP2MF)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get internal tamper 3 interrupt masked flag.
+ * @rmtoll TAMP_MISR ITAMP3MF LL_RTC_IsActiveFlag_ITAMP3M
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3M(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP3MF) == (TAMP_MISR_ITAMP3MF)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get internal tamper 5 interrupt masked flag.
+ * @rmtoll TAMP_MISR ITAMP5MF LL_RTC_IsActiveFlag_ITAMP5M
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5M(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP5MF) == (TAMP_MISR_ITAMP5MF)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get internal tamper 8 interrupt masked flag.
+ * @rmtoll TAMP_MISR ITAMP8MF LL_RTC_IsActiveFlag_ITAMP8M
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP8M(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP8MF) == (TAMP_MISR_ITAMP8MF)) ? 1U : 0U);
+}
+
+/**
+ * @brief Clear tamper 1 detection flag.
+ * @rmtoll TAMP_SCR CTAMP1F LL_RTC_ClearFlag_TAMP1
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP1F);
+}
+
+/**
+ * @brief Clear tamper 2 detection flag.
+ * @rmtoll TAMP_SCR CTAMP2F LL_RTC_ClearFlag_TAMP2
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP2F);
+}
+
+/**
+ * @brief Clear tamper 3 detection flag.
+ * @rmtoll TAMP_SCR CTAMP3F LL_RTC_ClearFlag_TAMP3
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP3F);
+}
+/**
+ * @brief Clear tamper 4 detection flag.
+ * @rmtoll TAMP_SCR CTAMP3F LL_RTC_ClearFlag_TAMP4
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_TAMP4(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP4F);
+}
+/**
+ * @brief Clear tamper 5 detection flag.
+ * @rmtoll TAMP_SCR CTAMP5F LL_RTC_ClearFlag_TAMP5
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_TAMP5(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP5F);
+}
+/**
+ * @brief Clear tamper 6 detection flag.
+ * @rmtoll TAMP_SCR CTAMP6F LL_RTC_ClearFlag_TAMP6
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_TAMP6(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP6F);
+}
+/**
+ * @brief Clear tamper 7 detection flag.
+ * @rmtoll TAMP_SCR CTAMP7F LL_RTC_ClearFlag_TAMP7
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_TAMP7(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP7F);
+}
+/**
+ * @brief Clear tamper 8 detection flag.
+ * @rmtoll TAMP_SCR CTAMP8F LL_RTC_ClearFlag_TAMP8
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_TAMP8(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP8F);
+}
+
+/**
+ * @brief Clear internal tamper 1 detection flag.
+ * @rmtoll TAMP_SCR CITAMP1F LL_RTC_ClearFlag_ITAMP1
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP1(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->SCR, TAMP_SCR_CITAMP1F);
+}
+
+/**
+ * @brief Clear internal tamper 2 detection flag.
+ * @rmtoll TAMP_SCR CITAMP2F LL_RTC_ClearFlag_ITAMP2
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP2(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->SCR, TAMP_SCR_CITAMP2F);
+}
+
+/**
+ * @brief Clear internal tamper 3 detection flag.
+ * @rmtoll TAMP_SCR CITAMP3F LL_RTC_ClearFlag_ITAMP3
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP3(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->SCR, TAMP_SCR_CITAMP3F);
+}
+
+/**
+ * @brief Clear internal tamper 5 detection flag.
+ * @rmtoll TAMP_SCR CITAMP5F LL_RTC_ClearFlag_ITAMP5
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP5(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->SCR, TAMP_SCR_CITAMP5F);
+}
+
+/**
+ * @brief Clear internal tamper 8 detection flag.
+ * @rmtoll TAMP_SCR CITAMP8F LL_RTC_ClearFlag_ITAMP8
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP8(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->SCR, TAMP_SCR_CITAMP8F);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_SECURITY SECURITY_Management
+ * @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ * @brief Set RTC secure level.
+ * @note secure features are relevant if LL_RTC_SECURE_FULL_NO.
+ * @rmtoll RTC_SECCFGR SEC LL_RTC_SetRtcSecure
+ * @rmtoll RTC_SECCFGR INITSEC LL_RTC_SetRtcSecure
+ * @rmtoll RTC_SECCFGR CALSEC LL_RTC_SetRtcSecure
+ * @rmtoll RTC_SECCFGR TSSEC LL_RTC_SetRtcSecure
+ * @rmtoll RTC_SECCFGR WUTSEC LL_RTC_SetRtcSecure
+ * @rmtoll RTC_SECCFGR ALRASEC LL_RTC_SetRtcSecure
+ * @rmtoll RTC_SECCFGR ALRBSEC LL_RTC_SetRtcSecure
+ * @param RTCx RTC Instance
+ * @param rtcSecure This parameter can be a combination of the following values:
+ * @arg @ref LL_RTC_SECURE_FULL_YES
+ * @arg @ref LL_RTC_SECURE_FULL_NO
+ * @arg @ref LL_RTC_UNSECURE_FEATURE_INIT
+ * @arg @ref LL_RTC_UNSECURE_FEATURE_CAL
+ * @arg @ref LL_RTC_UNSECURE_FEATURE_TS
+ * @arg @ref LL_RTC_UNSECURE_FEATURE_WUT
+ * @arg @ref LL_RTC_UNSECURE_FEATURE_ALRA
+ * @arg @ref LL_RTC_UNSECURE_FEATURE_ALRB
+
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_SetRtcSecure(RTC_TypeDef *RTCx, uint32_t rtcSecure)
+{
+ MODIFY_REG(RTCx->SECCFGR, RTC_SECCFGR_SEC | RTC_SECCFGR_INITSEC | RTC_SECCFGR_CALSEC | RTC_SECCFGR_TSSEC | \
+ RTC_SECCFGR_WUTSEC | RTC_SECCFGR_ALRASEC | RTC_SECCFGR_ALRBSEC, rtcSecure);
+}
+#endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/**
+ * @brief Get RTC secure level.
+ * @note Secure features is relevant if LL_RTC_SECURE_FULL_YES.
+ * @rmtoll RTC_SECCFGR SEC LL_RTC_SetRtcSecure
+ * @rmtoll RTC_SECCFGR INISEC LL_RTC_SetRtcSecure
+ * @rmtoll RTC_SECCFGR CALSEC LL_RTC_SetRtcSecure
+ * @rmtoll RTC_SECCFGR TSSEC LL_RTC_SetRtcSecure
+ * @rmtoll RTC_SECCFGR WUTSEC LL_RTC_SetRtcSecure
+ * @rmtoll RTC_SECCFGR ALRASEC LL_RTC_SetRtcSecure
+ * @rmtoll RTC_SECCFGR ALRBSEC LL_RTC_SetRtcSecure
+ * @param RTCx RTC Instance
+ * @retval Combination of the following values:
+ * @arg @ref LL_RTC_SECURE_FULL_YES
+ * @arg @ref LL_RTC_SECURE_FULL_NO
+ * @arg @ref LL_RTC_UNSECURE_FEATURE_INIT
+ * @arg @ref LL_RTC_UNSECURE_FEATURE_CAL
+ * @arg @ref LL_RTC_UNSECURE_FEATURE_TS
+ * @arg @ref LL_RTC_UNSECURE_FEATURE_WUT
+ * @arg @ref LL_RTC_UNSECURE_FEATURE_ALRA
+ * @arg @ref LL_RTC_UNSECURE_FEATURE_ALRB
+ */
+__STATIC_INLINE uint32_t LL_RTC_GetRtcSecure(RTC_TypeDef *RTCx)
+{
+ return READ_BIT(RTCx->SECCFGR, RTC_SECCFGR_SEC | RTC_SECCFGR_INITSEC | RTC_SECCFGR_CALSEC | RTC_SECCFGR_TSSEC | \
+ RTC_SECCFGR_WUTSEC | RTC_SECCFGR_ALRASEC | RTC_SECCFGR_ALRBSEC);
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ * @brief Set TAMPER secure level.
+ * @rmtoll TAMP_SECCFGR TAMPSEC LL_RTC_SetTampSecure
+ * @param RTCx RTC Instance
+ * @param tampSecure This parameter can be one of the following values:
+ * @arg @ref LL_TAMP_SECURE_FULL_YES
+ * @arg @ref LL_TAMP_SECURE_FULL_NO
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_SetTampSecure(RTC_TypeDef *RTCx, uint32_t tampSecure)
+{
+ UNUSED(RTCx);
+ MODIFY_REG(TAMP->SECCFGR, TAMP_SECCFGR_TAMPSEC, tampSecure);
+}
+#endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/**
+ * @brief Get TAMPER secure level.
+ * @rmtoll TAMP_SECCFGR TAMPSEC LL_RTC_GetTampSecure
+ * @param RTCx RTC Instance
+ * @retval This parameter can be one of the following values:
+ * @arg @ref LL_TAMP_SECURE_FULL_YES
+ * @arg @ref LL_TAMP_SECURE_FULL_NO
+ */
+__STATIC_INLINE uint32_t LL_RTC_GetTampSecure(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return READ_BIT(TAMP->SECCFGR, TAMP_SECCFGR_TAMPSEC);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_PRIVILEGE PRIVILEGE_Management
+ * @{
+ */
+
+/**
+ * @brief Set RTC privilege level.
+ * @note Privilege features are relevant if LL_RTC_PRIVILEGE_FULL_NO.
+ * @rmtoll RTC_PRIVCFGR PRIV LL_RTC_SetRtcPrivilege
+ * @rmtoll RTC_PRIVCFGR INITPRIV LL_RTC_SetRtcPrivilege
+ * @rmtoll RTC_PRIVCFGR CALPRIV LL_RTC_SetRtcPrivilege
+ * @rmtoll RTC_PRIVCFGR TSPRIV LL_RTC_SetRtcPrivilege
+ * @rmtoll RTC_PRIVCFGR WUTPRIV LL_RTC_SetRtcPrivilege
+ * @rmtoll RTC_PRIVCFGR ALRAPRIV LL_RTC_SetRtcPrivilege
+ * @rmtoll RTC_PRIVCFGR ALRBPRIV LL_RTC_SetRtcPrivilege
+ * @param RTCx RTC Instance
+ * @param rtcPrivilege This parameter can be a combination of the following values:
+ * @arg @ref LL_RTC_PRIVILEGE_FULL_YES
+ * @arg @ref LL_RTC_PRIVILEGE_FULL_NO
+ * @arg @ref LL_RTC_PRIVILEGE_FEATURE_INIT
+ * @arg @ref LL_RTC_PRIVILEGE_FEATURE_CAL
+ * @arg @ref LL_RTC_PRIVILEGE_FEATURE_TS
+ * @arg @ref LL_RTC_PRIVILEGE_FEATURE_WUT
+ * @arg @ref LL_RTC_PRIVILEGE_FEATURE_ALRA
+ * @arg @ref LL_RTC_PRIVILEGE_FEATURE_ALRB
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_SetRtcPrivilege(RTC_TypeDef *RTCx, uint32_t rtcPrivilege)
+{
+ MODIFY_REG(RTCx->PRIVCFGR, RTC_PRIVCFGR_PRIV | RTC_PRIVCFGR_INITPRIV | RTC_PRIVCFGR_CALPRIV | RTC_PRIVCFGR_TSPRIV | \
+ RTC_PRIVCFGR_WUTPRIV | RTC_PRIVCFGR_ALRAPRIV | RTC_PRIVCFGR_ALRBPRIV, rtcPrivilege);
+}
+
+/**
+ * @brief Get RTC privilege level.
+ * @note Privilege features are relevant if LL_RTC_PRIVILEGE_FULL_NO.
+ * @rmtoll RTC_PRIVCFGR PRIV LL_RTC_SetRtcPrivilege
+ * @rmtoll RTC_PRIVCFGR INITPRIV LL_RTC_SetRtcPrivilege
+ * @rmtoll RTC_PRIVCFGR CALPRIV LL_RTC_SetRtcPrivilege
+ * @rmtoll RTC_PRIVCFGR TSPRIV LL_RTC_SetRtcPrivilege
+ * @rmtoll RTC_PRIVCFGR WUTPRIV LL_RTC_SetRtcPrivilege
+ * @rmtoll RTC_PRIVCFGR ALRAPRIV LL_RTC_SetRtcPrivilege
+ * @rmtoll RTC_PRIVCFGR ALRBPRIV LL_RTC_SetRtcPrivilege
+ * @param RTCx RTC Instance
+ * @retval Combination of the following values:
+ * @arg @ref LL_RTC_PRIVILEGE_FULL_YES
+ * @arg @ref LL_RTC_PRIVILEGE_FULL_NO
+ * @arg @ref LL_RTC_PRIVILEGE_FEATURE_INIT
+ * @arg @ref LL_RTC_PRIVILEGE_FEATURE_CAL
+ * @arg @ref LL_RTC_PRIVILEGE_FEATURE_TS
+ * @arg @ref LL_RTC_PRIVILEGE_FEATURE_WUT
+ * @arg @ref LL_RTC_PRIVILEGE_FEATURE_ALRA
+ * @arg @ref LL_RTC_PRIVILEGE_FEATURE_ALRB
+ */
+__STATIC_INLINE uint32_t LL_RTC_GetRtcPrivilege(RTC_TypeDef *RTCx)
+{
+ return READ_BIT(RTCx->PRIVCFGR, RTC_PRIVCFGR_PRIV | RTC_PRIVCFGR_INITPRIV | RTC_PRIVCFGR_CALPRIV | \
+ RTC_PRIVCFGR_TSPRIV | RTC_PRIVCFGR_WUTPRIV | RTC_PRIVCFGR_ALRAPRIV | RTC_PRIVCFGR_ALRBPRIV);
+}
+
+/**
+ * @brief Set TAMPER privilege level.
+ * @rmtoll TAMP_SECCFGR TAMPPRIV LL_RTC_SetTampPrivilege
+ * @param RTCx RTC Instance
+ * @param tampPrivilege This parameter can be one of the following values:
+ * @arg @ref LL_TAMP_PRIVILEGE_FULL_YES
+ * @arg @ref LL_TAMP_PRIVILEGE_FULL_NO
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_SetTampPrivilege(RTC_TypeDef *RTCx, uint32_t tampPrivilege)
+{
+ UNUSED(RTCx);
+ MODIFY_REG(TAMP->PRIVCFGR, TAMP_PRIVCFGR_TAMPPRIV, tampPrivilege);
+}
+
+/**
+ * @brief Get TAMPER privilege level.
+ * @rmtoll TAMP_SECCFGR TAMPSEC LL_RTC_GetTampPrivilege
+ * @param RTCx RTC Instance
+ * @retval This parameter can be one of the following values:
+ * @arg @ref LL_TAMP_PRIVILEGE_FULL_YES
+ * @arg @ref LL_TAMP_PRIVILEGE_FULL_NO
+ */
+__STATIC_INLINE uint32_t LL_RTC_GetTampPrivilege(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return READ_BIT(TAMP->PRIVCFGR, TAMP_PRIVCFGR_TAMPPRIV);
+}
+
+/**
+ * @brief Set Backup Registers privilege level.
+ * @note bckupRegisterPrivilege is only writable in secure mode or if trustzone is disabled
+ * @rmtoll TAMP_PRIVCFGR BKPWPRIV LL_RTC_SetTampPrivilege
+ * @rmtoll TAMP_PRIVCFGR BKPRWPRIV LL_RTC_SetTampPrivilege
+ * @param RTCx RTC Instance
+ * @param bckupRegisterPrivilege This parameter can be one of the following values:
+ * @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_NONE
+ * @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_1
+ * @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_2
+ * @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_SetBackupRegisterPrivilege(RTC_TypeDef *RTCx, uint32_t bckupRegisterPrivilege)
+{
+ UNUSED(RTCx);
+ MODIFY_REG(TAMP->PRIVCFGR, (TAMP_PRIVCFGR_BKPWPRIV | TAMP_PRIVCFGR_BKPRWPRIV), bckupRegisterPrivilege);
+}
+
+/**
+ * @brief Get Backup Registers privilege level.
+ * @rmtoll TAMP_PRIVCFGR BKPWPRIV LL_RTC_SetTampPrivilege
+ * @rmtoll TAMP_PRIVCFGR BKPRWPRIV LL_RTC_SetTampPrivilege
+ * @param RTCx RTC Instance
+ * @retval This parameter can be one of the following values:
+ * @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_NONE
+ * @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_1
+ * @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_2
+ * @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_ALL
+ */
+__STATIC_INLINE uint32_t LL_RTC_GetBackupRegisterPrivilege(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return READ_BIT(TAMP->PRIVCFGR, (TAMP_PRIVCFGR_BKPWPRIV | TAMP_PRIVCFGR_BKPRWPRIV));
+}
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_BACKUP_REG_PROTECTION PROTECTION_BACKUP_REG_Management
+ * @brief Backup register protection is common to security and privilege.
+ * @{
+ */
+
+/**
+ * @brief Set Backup registers protection level.
+ * @note Zone 1 : read protection write protection
+ * @note Zone 2 : read non-protection write protection
+ * @note Zone 3 : read non-protection write non-protection
+ * @note zone 1 : start from 0 to startZone2 start value
+ * @note zone 2 : start from startZone2 start value to startZone3 start value
+ * @note zone 3 : start from to startZone3 to the end of BACKUPREG
+ * @note Warning : this parameter is only writable in secure mode or if trustzone is disabled
+ * @rmtoll TAMP_SECCFGR BKPWSEC LL_RTC_SetBackupRegProtection
+ * @rmtoll TAMP_SECCFGR BKPRWSEC LL_RTC_SetBackupRegProtection
+ * @param RTCx RTC Instance
+ * @param startZone2 This parameter can be one of the following values:
+ * @arg @ref LL_RTC_BKP_DR0
+ * @arg @ref LL_RTC_BKP_DR1
+ * @arg @ref LL_RTC_BKP_DR2
+ * @arg @ref LL_RTC_BKP_DR3
+ * @arg @ref LL_RTC_BKP_DR4 ...
+ * @param startZone3 This parameter can be one of the following values:
+ * @arg @ref LL_RTC_BKP_DR0
+ * @arg @ref LL_RTC_BKP_DR1
+ * @arg @ref LL_RTC_BKP_DR2
+ * @arg @ref LL_RTC_BKP_DR3
+ * @arg @ref LL_RTC_BKP_DR4 ...
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_SetBackupRegProtection(RTC_TypeDef *RTCx, uint32_t startZone2, uint32_t startZone3)
+{
+ UNUSED(RTCx);
+ MODIFY_REG(TAMP->SECCFGR, (TAMP_SECCFGR_BKPRWSEC_Msk | TAMP_SECCFGR_BKPWSEC_Msk), (startZone2 << \
+ TAMP_SECCFGR_BKPRWSEC_Pos) | (startZone3 << TAMP_SECCFGR_BKPWSEC_Pos));
+}
+
+/**
+ * @brief Get Backup registers protection level start zone 2.
+ * @note Zone 1 : read protection write protection
+ * @note Zone 2 : read non-protection/non-privile write protection
+ * @note Zone 3 : read non-protection write non-protection
+ * @rmtoll TAMP_SECCFGR BKPRWSEC LL_RTC_GetBackupRegProtectionStartZone2
+ * @param RTCx RTC Instance
+ * @retval Start zone 2
+ */
+__STATIC_INLINE uint32_t LL_RTC_GetBackupRegProtectionStartZone2(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return READ_BIT(TAMP->SECCFGR, TAMP_SECCFGR_BKPRWSEC_Msk) >> TAMP_SECCFGR_BKPRWSEC_Pos;
+}
+
+/**
+ * @brief Get Backup registers protection level start zone 3.
+ * @note Zone 1 : read protection write protection
+ * @note Zone 2 : read non-protection write protection
+ * @note Zone 3 : read non-protection write non-protection
+ * @rmtoll TAMP_SECCFGR BKPWSEC LL_RTC_GetBackupRegProtectionStartZone3
+ * @param RTCx RTC Instance
+ * @retval Start zone 2
+ */
+__STATIC_INLINE uint32_t LL_RTC_GetBackupRegProtectionStartZone3(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return READ_BIT(TAMP->SECCFGR, TAMP_SECCFGR_BKPWSEC_Msk) >> TAMP_SECCFGR_BKPWSEC_Pos;
+}
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable Time-stamp interrupt
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll RTC_CR TSIE LL_RTC_EnableIT_TS
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_TS(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_TSIE);
+}
+
+/**
+ * @brief Disable Time-stamp interrupt
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll RTC_CR TSIE LL_RTC_DisableIT_TS
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_TS(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_TSIE);
+}
+
+/**
+ * @brief Enable Wakeup timer interrupt
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll RTC_CR WUTIE LL_RTC_EnableIT_WUT
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_WUT(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_WUTIE);
+}
+
+/**
+ * @brief Disable Wakeup timer interrupt
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll RTC_CR WUTIE LL_RTC_DisableIT_WUT
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_WUT(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_WUTIE);
+}
+
+/**
+ * @brief Enable Alarm B interrupt
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll RTC_CR ALRBIE LL_RTC_EnableIT_ALRB
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_ALRB(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_ALRBIE);
+}
+
+/**
+ * @brief Disable Alarm B interrupt
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll RTC_CR ALRBIE LL_RTC_DisableIT_ALRB
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_ALRB(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_ALRBIE);
+}
+
+/**
+ * @brief Enable Alarm A interrupt
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll RTC_CR ALRAIE LL_RTC_EnableIT_ALRA
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_ALRA(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_ALRAIE);
+}
+
+/**
+ * @brief Disable Alarm A interrupt
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll RTC_CR ALRAIE LL_RTC_DisableIT_ALRA
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_ALRA(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_ALRAIE);
+}
+
+/**
+ * @brief Enable SSR Underflow interrupt
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll RTC_CR SSRUIE LL_RTC_EnableIT_SSRU
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_SSRU(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_SSRUIE);
+}
+
+/**
+ * @brief Disable SSR Underflow interrupt
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll RTC_CR SSRUIE LL_RTC_DisableIT_SSRU
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_SSRU(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_SSRUIE);
+}
+
+/**
+ * @brief Check if Time-stamp interrupt is enabled or not
+ * @rmtoll RTC_CR TSIE LL_RTC_IsEnabledIT_TS
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx)
+{
+ return ((READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE)) ? 1U : 0U);
+}
+
+/**
+ * @brief Check if Wakeup timer interrupt is enabled or not
+ * @rmtoll RTC_CR WUTIE LL_RTC_IsEnabledIT_WUT
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx)
+{
+ return ((READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE)) ? 1U : 0U);
+}
+
+/**
+ * @brief Check if Alarm B interrupt is enabled or not
+ * @rmtoll RTC_CR ALRBIE LL_RTC_IsEnabledIT_ALRB
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx)
+{
+ return ((READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE)) ? 1U : 0U);
+}
+
+/**
+ * @brief Check if Alarm A interrupt is enabled or not
+ * @rmtoll RTC_CR ALRAIE LL_RTC_IsEnabledIT_ALRA
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx)
+{
+ return ((READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)) ? 1U : 0U);
+}
+
+/**
+ * @brief Check if SSR Underflow interrupt is enabled or not
+ * @rmtoll RTC_CR SSRUIE LL_RTC_IsEnabledIT_SSRU
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_SSRU(RTC_TypeDef *RTCx)
+{
+ return ((READ_BIT(RTCx->CR, RTC_CR_SSRUIE) == (RTC_CR_SSRUIE)) ? 1U : 0U);
+}
+
+/**
+ * @brief Enable tamper 1 interrupt.
+ * @rmtoll TAMP_IER TAMP1IE LL_RTC_EnableIT_TAMP1
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_TAMP1(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->IER, TAMP_IER_TAMP1IE);
+}
+
+/**
+ * @brief Disable tamper 1 interrupt.
+ * @rmtoll TAMP_IER TAMP1IE LL_RTC_DisableIT_TAMP1
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_TAMP1(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP1IE);
+}
+
+/**
+ * @brief Enable tamper 2 interrupt.
+ * @rmtoll TAMP_IER TAMP2IE LL_RTC_EnableIT_TAMP2
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_TAMP2(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->IER, TAMP_IER_TAMP2IE);
+}
+
+/**
+ * @brief Disable tamper 2 interrupt.
+ * @rmtoll TAMP_IER TAMP2IE LL_RTC_DisableIT_TAMP2
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_TAMP2(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP2IE);
+}
+
+/**
+ * @brief Enable tamper 3 interrupt.
+ * @rmtoll TAMP_IER TAMP3IE LL_RTC_EnableIT_TAMP3
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_TAMP3(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->IER, TAMP_IER_TAMP3IE);
+}
+/**
+ * @brief Disable tamper 3 interrupt.
+ * @rmtoll TAMP_IER TAMP3IE LL_RTC_DisableIT_TAMP3
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_TAMP3(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP3IE);
+}
+/**
+ * @brief Enable tamper 4 interrupt.
+ * @rmtoll TAMP_IER TAMP4IE LL_RTC_EnableIT_TAMP4
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_TAMP4(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->IER, TAMP_IER_TAMP4IE);
+}
+/**
+ * @brief Disable tamper 4 interrupt.
+ * @rmtoll TAMP_IER TAMP4IE LL_RTC_DisableIT_TAMP4
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_TAMP4(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP4IE);
+}
+
+/**
+ * @brief Enable tamper 5 interrupt.
+ * @rmtoll TAMP_IER TAMP5IE LL_RTC_EnableIT_TAMP5
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_TAMP5(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->IER, TAMP_IER_TAMP5IE);
+}
+/**
+ * @brief Disable tamper 5 interrupt.
+ * @rmtoll TAMP_IER TAMP5IE LL_RTC_DisableIT_TAMP5
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_TAMP5(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP5IE);
+}
+
+/**
+ * @brief Enable tamper 6 interrupt.
+ * @rmtoll TAMP_IER TAMP6IE LL_RTC_EnableIT_TAMP6
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_TAMP6(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->IER, TAMP_IER_TAMP6IE);
+}
+/**
+ * @brief Disable tamper 6 interrupt.
+ * @rmtoll TAMP_IER TAMP6IE LL_RTC_DisableIT_TAMP6
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_TAMP6(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP6IE);
+}
+
+/**
+ * @brief Enable tamper 7 interrupt.
+ * @rmtoll TAMP_IER TAMP7IE LL_RTC_EnableIT_TAMP7
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_TAMP7(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->IER, TAMP_IER_TAMP7IE);
+}
+/**
+ * @brief Disable tamper 7 interrupt.
+ * @rmtoll TAMP_IER TAMP7IE LL_RTC_DisableIT_TAMP7
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_TAMP7(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP7IE);
+}
+
+/**
+ * @brief Enable tamper 8 interrupt.
+ * @rmtoll TAMP_IER TAMP8IE LL_RTC_EnableIT_TAMP8
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_TAMP8(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->IER, TAMP_IER_TAMP8IE);
+}
+/**
+ * @brief Disable tamper 8 interrupt.
+ * @rmtoll TAMP_IER TAMP8IE LL_RTC_DisableIT_TAMP8
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_TAMP8(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP8IE);
+}
+
+/**
+ * @brief Enable internal tamper 1 interrupt.
+ * @rmtoll TAMP_IER ITAMP1IE LL_RTC_EnableIT_ITAMP1
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_ITAMP1(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->IER, TAMP_IER_ITAMP1IE);
+}
+
+/**
+ * @brief Disable internal tamper 1 interrupt.
+ * @rmtoll TAMP_IER ITAMP1IE LL_RTC_DisableIT_ITAMP1
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_ITAMP1(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP1IE);
+}
+
+/**
+ * @brief Enable internal tamper 2 interrupt.
+ * @rmtoll TAMP_IER ITAMP2IE LL_RTC_EnableIT_ITAMP2
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_ITAMP2(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->IER, TAMP_IER_ITAMP2IE);
+}
+
+/**
+ * @brief Disable internal tamper 2 interrupt.
+ * @rmtoll TAMP_IER ITAMP2IE LL_RTC_DisableIT_ITAMP2
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_ITAMP2(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP2IE);
+}
+
+/**
+ * @brief Enable internal tamper 3 interrupt.
+ * @rmtoll TAMP_IER ITAMP3IE LL_RTC_EnableIT_ITAMP3
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_ITAMP3(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->IER, TAMP_IER_ITAMP3IE);
+}
+/**
+ * @brief Disable internal tamper 3 interrupt.
+ * @rmtoll TAMP_IER ITAMP3IE LL_RTC_DisableIT_ITAMP3
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_ITAMP3(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP3IE);
+}
+
+/**
+ * @brief Enable internal tamper 5 interrupt.
+ * @rmtoll TAMP_IER ITAMP5IE LL_RTC_EnableIT_ITAMP5
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_ITAMP5(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->IER, TAMP_IER_ITAMP5IE);
+}
+/**
+ * @brief Disable internal tamper 5 interrupt.
+ * @rmtoll TAMP_IER ITAMP5IE LL_RTC_DisableIT_ITAMP5
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_ITAMP5(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP5IE);
+}
+
+/**
+ * @brief Enable internal tamper 6 interrupt.
+ * @rmtoll TAMP_IER ITAMP6IE LL_RTC_EnableIT_ITAMP6
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_ITAMP6(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->IER, TAMP_IER_ITAMP6IE);
+}
+/**
+ * @brief Disable internal tamper 6 interrupt.
+ * @rmtoll TAMP_IER ITAMP6IE LL_RTC_DisableIT_ITAMP6
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_ITAMP6(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP6IE);
+}
+
+/**
+ * @brief Enable internal tamper 7 interrupt.
+ * @rmtoll TAMP_IER ITAMP7IE LL_RTC_EnableIT_ITAMP7
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_ITAMP7(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->IER, TAMP_IER_ITAMP7IE);
+}
+/**
+ * @brief Disable internal tamper 7 interrupt.
+ * @rmtoll TAMP_IER ITAMP7IE LL_RTC_DisableIT_ITAMP7
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_ITAMP7(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP7IE);
+}
+
+/**
+ * @brief Enable internal tamper 8 interrupt.
+ * @rmtoll TAMP_IER ITAMP8IE LL_RTC_EnableIT_ITAMP8
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_ITAMP8(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->IER, TAMP_IER_ITAMP8IE);
+}
+/**
+ * @brief Disable internal tamper 8 interrupt.
+ * @rmtoll TAMP_IER TAMP8IE LL_RTC_DisableIT_ITAMP8
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_ITAMP8(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP8IE);
+}
+
+/**
+ * @brief Enable internal tamper 9 interrupt.
+ * @rmtoll TAMP_IER ITAMP9IE LL_RTC_EnableIT_ITAMP9
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_ITAMP9(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->IER, TAMP_IER_ITAMP9IE);
+}
+/**
+ * @brief Disable internal tamper 9 interrupt.
+ * @rmtoll TAMP_IER ITAMP9IE LL_RTC_DisableIT_ITAMP9
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_ITAMP9(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP9IE);
+}
+
+/**
+ * @brief Enable internal tamper 11 interrupt.
+ * @rmtoll TAMP_IER ITAMP11IE LL_RTC_EnableIT_ITAMP11
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_ITAMP11(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->IER, TAMP_IER_ITAMP11IE);
+}
+/**
+ * @brief Disable internal tamper 11 interrupt.
+ * @rmtoll TAMP_IER ITAMP11IE LL_RTC_DisableIT_ITAMP11
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_ITAMP11(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP11IE);
+}
+/**
+ * @brief Enable internal tamper 12 interrupt.
+ * @rmtoll TAMP_IER ITAMP12IE LL_RTC_EnableIT_ITAM12
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_ITAMP12(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->IER, TAMP_IER_ITAMP12IE);
+}
+/**
+ * @brief Disable internal tamper 12 interrupt.
+ * @rmtoll TAMP_IER TAMP12IE LL_RTC_DisableIT_ITAMP12
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_ITAMP12(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP12IE);
+}
+/**
+ * @brief Enable internal tamper 13 interrupt.
+ * @rmtoll TAMP_IER ITAMP13IE LL_RTC_EnableIT_ITAMP13
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_ITAMP13(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->IER, TAMP_IER_ITAMP13IE);
+}
+/**
+ * @brief Disable internal tamper 13 interrupt.
+ * @rmtoll TAMP_IER TAMP13IE LL_RTC_DisableIT_ITAMP13
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_ITAMP13(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP13IE);
+}
+
+/**
+ * @brief Check if tamper 1 interrupt is enabled or not.
+ * @rmtoll TAMP_IER TAMP1IE LL_RTC_IsEnabledIT_TAMP1
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP1IE) == (TAMP_IER_TAMP1IE)) ? 1U : 0U);
+}
+
+/**
+ * @brief Check if tamper 2 interrupt is enabled or not.
+ * @rmtoll TAMP_IER TAMP2IE LL_RTC_IsEnabledIT_TAMP2
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP2IE) == (TAMP_IER_TAMP2IE)) ? 1U : 0U);
+}
+
+/**
+ * @brief Check if tamper 3 interrupt is enabled or not.
+ * @rmtoll TAMP_IER TAMP3IE LL_RTC_IsEnabledIT_TAMP3
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP3IE) == (TAMP_IER_TAMP3IE)) ? 1U : 0U);
+}
+/**
+ * @brief Check if tamper 4 interrupt is enabled or not.
+ * @rmtoll TAMP_IER TAMP4IE LL_RTC_IsEnabledIT_TAMP4
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP4(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP4IE) == (TAMP_IER_TAMP4IE)) ? 1U : 0U);
+}
+/**
+ * @brief Check if tamper 5 interrupt is enabled or not.
+ * @rmtoll TAMP_IER TAMP1IE LL_RTC_IsEnabledIT_TAMP5
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP5(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP5IE) == (TAMP_IER_TAMP5IE)) ? 1U : 0U);
+}
+/**
+ * @brief Check if tamper 6 interrupt is enabled or not.
+ * @rmtoll TAMP_IER TAMP6IE LL_RTC_IsEnabledIT_TAMP6
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP6(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP6IE) == (TAMP_IER_TAMP6IE)) ? 1U : 0U);
+}
+/**
+ * @brief Check if tamper 7 interrupt is enabled or not.
+ * @rmtoll TAMP_IER TAMP1IE LL_RTC_IsEnabledIT_TAMP7
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP7(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP7IE) == (TAMP_IER_TAMP7IE)) ? 1U : 0U);
+}
+/**
+ * @brief Check if tamper 8 interrupt is enabled or not.
+ * @rmtoll TAMP_IER TAMP8IE LL_RTC_IsEnabledIT_TAMP8
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP8(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP8IE) == (TAMP_IER_TAMP8IE)) ? 1U : 0U);
+}
+
+/**
+ * @brief Check if internal tamper 1 interrupt is enabled or not.
+ * @rmtoll TAMP_IER ITAMP1IE LL_RTC_IsEnabledIT_ITAMP1
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP1(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP1IE) == (TAMP_IER_ITAMP1IE)) ? 1U : 0U);
+}
+
+/**
+ * @brief Check if internal tamper 2 interrupt is enabled or not.
+ * @rmtoll TAMP_IER ITAMP2IE LL_RTC_IsEnabledIT_ITAMP2
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP2(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP2IE) == (TAMP_IER_ITAMP2IE)) ? 1U : 0U);
+}
+
+/**
+ * @brief Check if internal tamper 3 interrupt is enabled or not.
+ * @rmtoll TAMP_IER ITAMP3IE LL_RTC_IsEnabledIT_ITAMP3
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP3(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP3IE) == (TAMP_IER_ITAMP3IE)) ? 1U : 0U);
+}
+
+/**
+ * @brief Check if internal tamper 5 interrupt is enabled or not.
+ * @rmtoll TAMP_IER ITAMP5IE LL_RTC_IsEnabledIT_ITAMP5
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP5(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP5IE) == (TAMP_IER_ITAMP5IE)) ? 1U : 0U);
+}
+
+/**
+ * @brief Check if internal tamper 6 interrupt is enabled or not.
+ * @rmtoll TAMP_IER ITAMP6IE LL_RTC_IsEnabledIT_ITAMP6
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP6(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP6IE) == (TAMP_IER_ITAMP6IE)) ? 1U : 0U);
+}
+
+/**
+ * @brief Check if internal tamper 7 interrupt is enabled or not.
+ * @rmtoll TAMP_IER ITAMP7IE LL_RTC_IsEnabledIT_ITAMP7
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP7(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP7IE) == (TAMP_IER_ITAMP7IE)) ? 1U : 0U);
+}
+
+/**
+ * @brief Check if internal tamper 8 interrupt is enabled or not.
+ * @rmtoll TAMP_IER ITAMP8IE LL_RTC_IsEnabledIT_ITAMP8
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP8(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP8IE) == (TAMP_IER_ITAMP8IE)) ? 1U : 0U);
+}
+
+/**
+ * @brief Check if internal tamper 9 interrupt is enabled or not.
+ * @rmtoll TAMP_IER ITAMP9IE LL_RTC_IsEnabledIT_ITAMP9
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP9(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP9IE) == (TAMP_IER_ITAMP9IE)) ? 1U : 0U);
+}
+
+/**
+ * @brief Check if internal tamper 11 interrupt is enabled or not.
+ * @rmtoll TAMP_IER ITAMP11IE LL_RTC_IsEnabledIT_ITAMP11
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP11(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP11IE) == (TAMP_IER_ITAMP11IE)) ? 1U : 0U);
+}
+
+/**
+ * @brief Check if internal tamper 12 interrupt is enabled or not.
+ * @rmtoll TAMP_IER ITAMP12IE LL_RTC_IsEnabledIT_ITAMP12
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP12(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP12IE) == (TAMP_IER_ITAMP12IE)) ? 1U : 0U);
+}
+
+/**
+ * @brief Check if internal tamper 13 interrupt is enabled or not.
+ * @rmtoll TAMP_IER ITAMP13IE LL_RTC_IsEnabledIT_ITAMP13
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP13(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP13IE) == (TAMP_IER_ITAMP13IE)) ? 1U : 0U);
+}
+
+/**
+ * @brief Increment Monotonic counter.
+ * @rmtoll TAMP_COUNTR COUNT LL_RTC_IncrementMonotonicCounter
+ * @param RTCx RTC Instance
+ * @retval None.
+ */
+__STATIC_INLINE void LL_RTC_IncrementMonotonicCounter(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ WRITE_REG(TAMP->COUNTR, 0u);
+}
+
+/**
+ * @brief Increment Monotonic counter.
+ * @rmtoll TAMP_COUNTR COUNT LL_RTC_GetMonotonicCounter
+ * @param RTCx RTC Instance
+ * @retval Monotonic counter value.
+ */
+__STATIC_INLINE uint32_t LL_RTC_GetMonotonicCounter(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ return READ_REG(TAMP->COUNTR);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RTC_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx);
+ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct);
+void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct);
+ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct);
+void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct);
+ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct);
+void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct);
+ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
+ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
+void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
+void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
+ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx);
+ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx);
+ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(RTC) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_LL_RTC_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_sdmmc.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_sdmmc.h
new file mode 100644
index 00000000..f850cddf
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_sdmmc.h
@@ -0,0 +1,1143 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_sdmmc.h
+ * @author MCD Application Team
+ * @brief Header file of SDMMC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_LL_SDMMC_H
+#define STM32U5xx_LL_SDMMC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+/** @addtogroup STM32U5xx_Driver
+ * @{
+ */
+
+/** @addtogroup SDMMC_LL
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
+ * @{
+ */
+
+/**
+ * @brief SDMMC Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t ClockEdge; /*!< Specifies the SDMMC_CCK clock transition on which Data and Command change.
+ This parameter can be a value of @ref SDMMC_LL_Clock_Edge */
+
+ uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or
+ disabled when the bus is idle.
+ This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */
+
+ uint32_t BusWide; /*!< Specifies the SDMMC bus width.
+ This parameter can be a value of @ref SDMMC_LL_Bus_Wide */
+
+ uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
+ This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */
+
+ uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 1023 */
+
+#if (USE_SD_TRANSCEIVER != 0U)
+ uint32_t TranceiverPresent; /*!< Specifies if there is a 1V8 Transceiver/Switcher.
+ This parameter can be a value of @ref SDMMC_LL_TRANSCEIVER_PRESENT */
+#endif /* USE_SD_TRANSCEIVER */
+} SDMMC_InitTypeDef;
+
+
+/**
+ * @brief SDMMC Command Control structure
+ */
+typedef struct
+{
+ uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent
+ to a card as part of a command message. If a command
+ contains an argument, it must be loaded into this register
+ before writing the command to the command register. */
+
+ uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and
+ Max_Data = 64 */
+
+ uint32_t Response; /*!< Specifies the SDMMC response type.
+ This parameter can be a value of @ref SDMMC_LL_Response_Type */
+
+ uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is
+ enabled or disabled.
+ This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */
+
+ uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM)
+ is enabled or disabled.
+ This parameter can be a value of @ref SDMMC_LL_CPSM_State */
+} SDMMC_CmdInitTypeDef;
+
+
+/**
+ * @brief SDMMC Data Control structure
+ */
+typedef struct
+{
+ uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
+
+ uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */
+
+ uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
+ This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */
+
+ uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
+ is a read or write.
+ This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
+
+ uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
+ This parameter can be a value of @ref SDMMC_LL_Transfer_Type */
+
+ uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM)
+ is enabled or disabled.
+ This parameter can be a value of @ref SDMMC_LL_DPSM_State */
+} SDMMC_DataInitTypeDef;
+
+/** @defgroup SDEx_Exported_Types_Group1 SD Card Internal DMA Buffer structure
+ * @{
+ */
+typedef struct
+{
+ __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list configuration register */
+ __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register */
+ __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register */
+} SDMMC_DMALinkNodeTypeDef;
+
+typedef struct
+{
+ uint32_t BufferAddress; /*!< Node Buffer address */
+ uint32_t BufferSize ; /*!< Node Buffer size */
+} SDMMC_DMALinkNodeConfTypeDef;
+
+typedef struct
+{
+ SDMMC_DMALinkNodeTypeDef *pHeadNode; /*!< Linked List Node Head */
+ SDMMC_DMALinkNodeTypeDef *pTailNode; /*!< Linked List Node Head */
+ uint32_t NodesCounter ; /*!< Node is ready for execution */
+} SDMMC_DMALinkedListTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
+ * @{
+ */
+#define SDMMC_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
+#define SDMMC_ERROR_CMD_CRC_FAIL ((uint32_t)0x00000001U) /*!< Command response received (but CRC check failed) */
+#define SDMMC_ERROR_DATA_CRC_FAIL ((uint32_t)0x00000002U) /*!< Data block sent/received (CRC check failed) */
+#define SDMMC_ERROR_CMD_RSP_TIMEOUT ((uint32_t)0x00000004U) /*!< Command response timeout */
+#define SDMMC_ERROR_DATA_TIMEOUT ((uint32_t)0x00000008U) /*!< Data timeout */
+#define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /*!< Transmit FIFO underrun */
+#define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /*!< Receive FIFO overrun */
+#define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /*!< Misaligned address */
+#define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */
+#define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /*!< An error in the sequence of erase command occurs */
+#define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /*!< An invalid selection for erase groups */
+#define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /*!< Attempt to program a write protect block */
+#define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */
+#define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /*!< CRC check of the previous command failed */
+#define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /*!< Command is not legal for the card state */
+#define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /*!< Card internal ECC was applied but failed to correct the data */
+#define SDMMC_ERROR_CC_ERR ((uint32_t)0x00008000U) /*!< Internal card controller error */
+#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR ((uint32_t)0x00010000U) /*!< General or unknown error */
+#define SDMMC_ERROR_STREAM_READ_UNDERRUN ((uint32_t)0x00020000U) /*!< The card could not sustain data reading in stream rmode */
+#define SDMMC_ERROR_STREAM_WRITE_OVERRUN ((uint32_t)0x00040000U) /*!< The card could not sustain data programming in stream mode */
+#define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /*!< CID/CSD overwrite error */
+#define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /*!< Only partial address space was erased */
+#define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /*!< Command has been executed without using internal ECC */
+#define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */
+#define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /*!< Error in sequence of authentication */
+#define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /*!< Error in case of invalid voltage range */
+#define SDMMC_ERROR_ADDR_OUT_OF_RANGE ((uint32_t)0x02000000U) /*!< Error when addressed block is out of range */
+#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE ((uint32_t)0x04000000U) /*!< Error when command request is not applicable */
+#define SDMMC_ERROR_INVALID_PARAMETER ((uint32_t)0x08000000U) /*!< the used parameter is not valid */
+#define SDMMC_ERROR_UNSUPPORTED_FEATURE ((uint32_t)0x10000000U) /*!< Error when feature is not insupported */
+#define SDMMC_ERROR_BUSY ((uint32_t)0x20000000U) /*!< Error when transfer process is busy */
+#define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /*!< Error while DMA transfer */
+#define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /*!< Timeout error */
+
+/**
+ * @brief SDMMC Commands Index
+ */
+#define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0U) /*!< Resets the SD memory card. */
+#define SDMMC_CMD_SEND_OP_COND ((uint8_t)1U) /*!< Sends host capacity support information and activates the card's initialization process. */
+#define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
+#define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */
+#define SDMMC_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */
+#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line.*/
+#define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
+#define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */
+#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information and asks the card whether card supports voltage. */
+#define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
+#define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */
+#define SDMMC_CMD_VOLTAGE_SWITCH ((uint8_t)11U) /*!< SD card Voltage switch to 1.8V mode. */
+#define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12U) /*!< Forces the card to stop transmission. */
+#define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */
+#define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */
+#define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */
+#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands (read, write, lock). Default block length is fixed to 512 Bytes. Not effective */
+/*!< for SDHS and SDXC. */
+#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */
+#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by STOP_TRANSMISSION command. */
+#define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
+#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */
+#define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */
+#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */
+#define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
+#define SDMMC_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */
+#define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */
+#define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28U) /*!< Sets the write protection bit of the addressed group. */
+#define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29U) /*!< Clears the write protection bit of the addressed group. */
+#define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */
+#define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */
+#define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */
+#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command system set by switch function command (CMD6). */
+#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased. Reserved for each command system set by switch function command (CMD6). */
+#define SDMMC_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */
+#define SDMMC_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */
+#define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */
+#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by the SET_BLOCK_LEN command. */
+#define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather than a standard command. */
+#define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card for general purpose/application specific commands. */
+#define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */
+
+/**
+ * @brief Following commands are SD Card Specific commands.
+ * SDMMC_APP_CMD should be sent before sending these commands.
+ */
+#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus widths are given in SCR register. */
+#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */
+#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 32bit+CRC data block. */
+#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line. */
+#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */
+#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */
+#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */
+#define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */
+
+/**
+ * @brief Following commands are SD Card Specific security commands.
+ * SDMMC_CMD_APP_CMD should be sent before sending these commands.
+ */
+#define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43U)
+#define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44U)
+#define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U)
+#define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U)
+#define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U)
+#define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U)
+#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U)
+#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U)
+#define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U)
+#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U)
+#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U)
+
+/**
+ * @brief Masks for errors Card Status R1 (OCR Register)
+ */
+#define SDMMC_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U)
+#define SDMMC_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U)
+#define SDMMC_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000U)
+#define SDMMC_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000U)
+#define SDMMC_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000U)
+#define SDMMC_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000U)
+#define SDMMC_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000U)
+#define SDMMC_OCR_COM_CRC_FAILED ((uint32_t)0x00800000U)
+#define SDMMC_OCR_ILLEGAL_CMD ((uint32_t)0x00400000U)
+#define SDMMC_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000U)
+#define SDMMC_OCR_CC_ERROR ((uint32_t)0x00100000U)
+#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000U)
+#define SDMMC_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000U)
+#define SDMMC_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000U)
+#define SDMMC_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000U)
+#define SDMMC_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000U)
+#define SDMMC_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000U)
+#define SDMMC_OCR_ERASE_RESET ((uint32_t)0x00002000U)
+#define SDMMC_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U)
+#define SDMMC_OCR_ERRORBITS ((uint32_t)0xFDFFE008U)
+
+/**
+ * @brief Masks for R6 Response
+ */
+#define SDMMC_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U)
+#define SDMMC_R6_ILLEGAL_CMD ((uint32_t)0x00004000U)
+#define SDMMC_R6_COM_CRC_FAILED ((uint32_t)0x00008000U)
+
+#define SDMMC_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000U)
+#define SDMMC_HIGH_CAPACITY ((uint32_t)0x40000000U)
+#define SDMMC_STD_CAPACITY ((uint32_t)0x00000000U)
+#define SDMMC_CHECK_PATTERN ((uint32_t)0x000001AAU)
+#define SD_SWITCH_1_8V_CAPACITY ((uint32_t)0x01000000U)
+#define SDMMC_DDR50_SWITCH_PATTERN ((uint32_t)0x80FFFF04U)
+#define SDMMC_SDR104_SWITCH_PATTERN ((uint32_t)0x80FF1F03U)
+#define SDMMC_SDR50_SWITCH_PATTERN ((uint32_t)0x80FF1F02U)
+#define SDMMC_SDR25_SWITCH_PATTERN ((uint32_t)0x80FFFF01U)
+
+#define SDMMC_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU)
+
+#define SDMMC_MAX_TRIAL ((uint32_t)0x0000FFFFU)
+
+#define SDMMC_ALLZERO ((uint32_t)0x00000000U)
+
+#define SDMMC_WIDE_BUS_SUPPORT ((uint32_t)0x00040000U)
+#define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U)
+#define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U)
+
+#define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU)
+
+#define SDMMC_0TO7BITS ((uint32_t)0x000000FFU)
+#define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U)
+#define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U)
+#define SDMMC_24TO31BITS ((uint32_t)0xFF000000U)
+#define SDMMC_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFFU)
+
+#define SDMMC_HALFFIFO ((uint32_t)0x00000008U)
+#define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U)
+
+/**
+ * @brief Command Class supported
+ */
+#define SDMMC_CCCC_ERASE ((uint32_t)0x00000020U)
+
+#define SDMMC_CMDTIMEOUT ((uint32_t)5000U) /* Command send and response timeout */
+#define SDMMC_MAXERASETIMEOUT ((uint32_t)63000U) /* Max erase Timeout 63 s */
+#define SDMMC_STOPTRANSFERTIMEOUT ((uint32_t)100000000U) /* Timeout for STOP TRANSMISSION command */
+
+/** @defgroup SDMMC_LL_Clock_Edge Clock Edge
+ * @{
+ */
+#define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000U)
+#define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE
+
+#define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \
+ ((EDGE) == SDMMC_CLOCK_EDGE_FALLING))
+/**
+ * @}
+ */
+
+/** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving
+ * @{
+ */
+#define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000U)
+#define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV
+
+#define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \
+ ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup SDMMC_LL_Bus_Wide Bus Width
+ * @{
+ */
+#define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000U)
+#define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0
+#define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1
+
+#define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \
+ ((WIDE) == SDMMC_BUS_WIDE_4B) || \
+ ((WIDE) == SDMMC_BUS_WIDE_8B))
+/**
+ * @}
+ */
+
+/** @defgroup SDMMC_LL_Speed_Mode
+ * @{
+ */
+#define SDMMC_SPEED_MODE_AUTO ((uint32_t)0x00000000U)
+#define SDMMC_SPEED_MODE_DEFAULT ((uint32_t)0x00000001U)
+#define SDMMC_SPEED_MODE_HIGH ((uint32_t)0x00000002U)
+#define SDMMC_SPEED_MODE_ULTRA ((uint32_t)0x00000003U)
+#define SDMMC_SPEED_MODE_DDR ((uint32_t)0x00000004U)
+
+#define IS_SDMMC_SPEED_MODE(MODE) (((MODE) == SDMMC_SPEED_MODE_AUTO) || \
+ ((MODE) == SDMMC_SPEED_MODE_DEFAULT) || \
+ ((MODE) == SDMMC_SPEED_MODE_HIGH) || \
+ ((MODE) == SDMMC_SPEED_MODE_ULTRA) || \
+ ((MODE) == SDMMC_SPEED_MODE_DDR))
+
+/**
+ * @}
+ */
+
+/** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control
+ * @{
+ */
+#define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000U)
+#define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN
+
+#define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \
+ ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup SDMMC_LL_Clock_Division Clock Division
+ * @{
+ */
+/* SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV] */
+#define IS_SDMMC_CLKDIV(DIV) ((DIV) < 0x400U)
+/**
+ * @}
+ */
+
+/** @defgroup SDMMC_LL_TRANSCEIVER_PRESENT Transceiver Present
+ * @{
+ */
+#define SDMMC_TRANSCEIVER_UNKNOWN ((uint32_t)0x00000000U)
+#define SDMMC_TRANSCEIVER_NOT_PRESENT ((uint32_t)0x00000001U)
+#define SDMMC_TRANSCEIVER_PRESENT ((uint32_t)0x00000002U)
+
+/**
+ * @}
+ */
+
+/** @defgroup SDMMC_LL_Command_Index Command Index
+ * @{
+ */
+#define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40U)
+/**
+ * @}
+ */
+
+/** @defgroup SDMMC_LL_Response_Type Response Type
+ * @{
+ */
+#define SDMMC_RESPONSE_NO ((uint32_t)0x00000000U)
+#define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0
+#define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP
+
+#define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) || \
+ ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \
+ ((RESPONSE) == SDMMC_RESPONSE_LONG))
+/**
+ * @}
+ */
+
+/** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt
+ * @{
+ */
+#define SDMMC_WAIT_NO ((uint32_t)0x00000000U)
+#define SDMMC_WAIT_IT SDMMC_CMD_WAITINT
+#define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND
+
+#define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \
+ ((WAIT) == SDMMC_WAIT_IT) || \
+ ((WAIT) == SDMMC_WAIT_PEND))
+/**
+ * @}
+ */
+
+/** @defgroup SDMMC_LL_CPSM_State CPSM State
+ * @{
+ */
+#define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000U)
+#define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN
+
+#define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \
+ ((CPSM) == SDMMC_CPSM_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup SDMMC_LL_Response_Registers Response Register
+ * @{
+ */
+#define SDMMC_RESP1 ((uint32_t)0x00000000U)
+#define SDMMC_RESP2 ((uint32_t)0x00000004U)
+#define SDMMC_RESP3 ((uint32_t)0x00000008U)
+#define SDMMC_RESP4 ((uint32_t)0x0000000CU)
+
+#define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \
+ ((RESP) == SDMMC_RESP2) || \
+ ((RESP) == SDMMC_RESP3) || \
+ ((RESP) == SDMMC_RESP4))
+
+/** @defgroup SDMMC_Internal_DMA_Mode SDMMC Internal DMA Mode
+ * @{
+ */
+#define SDMMC_DISABLE_IDMA ((uint32_t)0x00000000)
+#define SDMMC_ENABLE_IDMA_SINGLE_BUFF (SDMMC_IDMA_IDMAEN)
+#define SDMMC_ENABLE_IDMA_DOUBLE_BUFF0 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE)
+#define SDMMC_ENABLE_IDMA_DOUBLE_BUFF1 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE | SDMMC_IDMA_IDMABACT)
+
+/**
+ * @}
+ */
+
+/** @defgroup SDMMC_LL_Data_Length Data Length
+ * @{
+ */
+#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
+/**
+ * @}
+ */
+
+/** @defgroup SDMMC_LL_Data_Block_Size Data Block Size
+ * @{
+ */
+#define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000U)
+#define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0
+#define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1
+#define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1)
+#define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2
+#define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2)
+#define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
+#define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0| \
+ SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
+#define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3
+#define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3)
+#define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
+#define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0| \
+ SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
+#define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
+#define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0| \
+ SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
+#define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1| \
+ SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
+
+#define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B))
+/**
+ * @}
+ */
+
+/** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction
+ * @{
+ */
+#define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000U)
+#define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR
+
+#define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \
+ ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC))
+/**
+ * @}
+ */
+
+/** @defgroup SDMMC_LL_Transfer_Type Transfer Type
+ * @{
+ */
+#define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U)
+#define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE_1
+
+#define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \
+ ((MODE) == SDMMC_TRANSFER_MODE_STREAM))
+/**
+ * @}
+ */
+
+/** @defgroup SDMMC_LL_DPSM_State DPSM State
+ * @{
+ */
+#define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000U)
+#define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN
+
+#define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\
+ ((DPSM) == SDMMC_DPSM_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode
+ * @{
+ */
+#define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000U)
+#define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD)
+
+#define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \
+ ((MODE) == SDMMC_READ_WAIT_MODE_DATA2))
+/**
+ * @}
+ */
+
+/** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources
+ * @{
+ */
+#define SDMMC_IT_CCRCFAIL SDMMC_MASK_CCRCFAILIE
+#define SDMMC_IT_DCRCFAIL SDMMC_MASK_DCRCFAILIE
+#define SDMMC_IT_CTIMEOUT SDMMC_MASK_CTIMEOUTIE
+#define SDMMC_IT_DTIMEOUT SDMMC_MASK_DTIMEOUTIE
+#define SDMMC_IT_TXUNDERR SDMMC_MASK_TXUNDERRIE
+#define SDMMC_IT_RXOVERR SDMMC_MASK_RXOVERRIE
+#define SDMMC_IT_CMDREND SDMMC_MASK_CMDRENDIE
+#define SDMMC_IT_CMDSENT SDMMC_MASK_CMDSENTIE
+#define SDMMC_IT_DATAEND SDMMC_MASK_DATAENDIE
+#define SDMMC_IT_DHOLD SDMMC_MASK_DHOLDIE
+#define SDMMC_IT_DBCKEND SDMMC_MASK_DBCKENDIE
+#define SDMMC_IT_DABORT SDMMC_MASK_DABORTIE
+#define SDMMC_IT_TXFIFOHE SDMMC_MASK_TXFIFOHEIE
+#define SDMMC_IT_RXFIFOHF SDMMC_MASK_RXFIFOHFIE
+#define SDMMC_IT_RXFIFOF SDMMC_MASK_RXFIFOFIE
+#define SDMMC_IT_TXFIFOE SDMMC_MASK_TXFIFOEIE
+#define SDMMC_IT_BUSYD0END SDMMC_MASK_BUSYD0ENDIE
+#define SDMMC_IT_SDIOIT SDMMC_MASK_SDIOITIE
+#define SDMMC_IT_ACKFAIL SDMMC_MASK_ACKFAILIE
+#define SDMMC_IT_ACKTIMEOUT SDMMC_MASK_ACKTIMEOUTIE
+#define SDMMC_IT_VSWEND SDMMC_MASK_VSWENDIE
+#define SDMMC_IT_CKSTOP SDMMC_MASK_CKSTOPIE
+#define SDMMC_IT_IDMABTC SDMMC_MASK_IDMABTCIE
+/**
+ * @}
+ */
+
+/** @defgroup SDMMC_LL_Flags Flags
+ * @{
+ */
+#define SDMMC_FLAG_CCRCFAIL SDMMC_STA_CCRCFAIL
+#define SDMMC_FLAG_DCRCFAIL SDMMC_STA_DCRCFAIL
+#define SDMMC_FLAG_CTIMEOUT SDMMC_STA_CTIMEOUT
+#define SDMMC_FLAG_DTIMEOUT SDMMC_STA_DTIMEOUT
+#define SDMMC_FLAG_TXUNDERR SDMMC_STA_TXUNDERR
+#define SDMMC_FLAG_RXOVERR SDMMC_STA_RXOVERR
+#define SDMMC_FLAG_CMDREND SDMMC_STA_CMDREND
+#define SDMMC_FLAG_CMDSENT SDMMC_STA_CMDSENT
+#define SDMMC_FLAG_DATAEND SDMMC_STA_DATAEND
+#define SDMMC_FLAG_DHOLD SDMMC_STA_DHOLD
+#define SDMMC_FLAG_DBCKEND SDMMC_STA_DBCKEND
+#define SDMMC_FLAG_DABORT SDMMC_STA_DABORT
+#define SDMMC_FLAG_DPSMACT SDMMC_STA_DPSMACT
+#define SDMMC_FLAG_CMDACT SDMMC_STA_CPSMACT
+#define SDMMC_FLAG_TXFIFOHE SDMMC_STA_TXFIFOHE
+#define SDMMC_FLAG_RXFIFOHF SDMMC_STA_RXFIFOHF
+#define SDMMC_FLAG_TXFIFOF SDMMC_STA_TXFIFOF
+#define SDMMC_FLAG_RXFIFOF SDMMC_STA_RXFIFOF
+#define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE
+#define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE
+#define SDMMC_FLAG_BUSYD0 SDMMC_STA_BUSYD0
+#define SDMMC_FLAG_BUSYD0END SDMMC_STA_BUSYD0END
+#define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT
+#define SDMMC_FLAG_ACKFAIL SDMMC_STA_ACKFAIL
+#define SDMMC_FLAG_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT
+#define SDMMC_FLAG_VSWEND SDMMC_STA_VSWEND
+#define SDMMC_FLAG_CKSTOP SDMMC_STA_CKSTOP
+#define SDMMC_FLAG_IDMATE SDMMC_STA_IDMATE
+#define SDMMC_FLAG_IDMABTC SDMMC_STA_IDMABTC
+
+#define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\
+ SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\
+ SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\
+ SDMMC_FLAG_DHOLD | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT |\
+ SDMMC_FLAG_BUSYD0END | SDMMC_FLAG_SDIOIT | SDMMC_FLAG_ACKFAIL |\
+ SDMMC_FLAG_ACKTIMEOUT | SDMMC_FLAG_VSWEND | SDMMC_FLAG_CKSTOP |\
+ SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC))
+
+#define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\
+ SDMMC_FLAG_CMDSENT | SDMMC_FLAG_BUSYD0END))
+
+#define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\
+ SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DHOLD |\
+ SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT | SDMMC_FLAG_IDMATE |\
+ SDMMC_FLAG_IDMABTC))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
+ * @{
+ */
+
+/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
+ * @brief SDMMC_LL registers bit address in the alias region
+ * @{
+ */
+/* ---------------------- SDMMC registers bit mask --------------------------- */
+/* --- CLKCR Register ---*/
+/* CLKCR register clear mask */
+#define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\
+ SDMMC_CLKCR_WIDBUS |\
+ SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN |\
+ SDMMC_CLKCR_DDR | SDMMC_CLKCR_BUSSPEED |\
+ SDMMC_CLKCR_SELCLKRX))
+
+/* --- DCTRL Register ---*/
+/* SDMMC DCTRL Clear Mask */
+#define DCTRL_CLEAR_MASK ((uint32_t)(SDMMC_DCTRL_DTEN | SDMMC_DCTRL_DTDIR |\
+ SDMMC_DCTRL_DTMODE | SDMMC_DCTRL_DBLOCKSIZE))
+
+/* --- CMD Register ---*/
+/* CMD Register clear mask */
+#define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\
+ SDMMC_CMD_WAITINT | SDMMC_CMD_WAITPEND |\
+ SDMMC_CMD_CPSMEN | SDMMC_CMD_CMDSUSPEND))
+
+/* SDMMC Initialization Frequency (400KHz max) for Peripheral CLK 200MHz*/
+#define SDMMC_INIT_CLK_DIV ((uint8_t)0xFA)
+
+/* SDMMC Default Speed Frequency (25Mhz max) for Peripheral CLK 200MHz*/
+#define SDMMC_NSPEED_CLK_DIV ((uint8_t)0x4)
+
+/* SDMMC High Speed Frequency (50Mhz max) for Peripheral CLK 200MHz*/
+#define SDMMC_HSPEED_CLK_DIV ((uint8_t)0x2)
+/**
+ * @}
+ */
+
+/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+
+/**
+ * @brief Enable the SDMMC device interrupt.
+ * @param __INSTANCE__ Pointer to SDMMC register base
+ * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
+ * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
+ * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
+ * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
+ * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
+ * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
+ * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+ * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
+ * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
+ * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
+ * @retval None
+ */
+#define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the SDMMC device interrupt.
+ * @param __INSTANCE__ Pointer to SDMMC register base
+ * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
+ * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
+ * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
+ * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
+ * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
+ * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
+ * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+ * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
+ * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
+ * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
+ * @retval None
+ */
+#define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
+
+/**
+ * @brief Checks whether the specified SDMMC flag is set or not.
+ * @param __INSTANCE__ Pointer to SDMMC register base
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
+ * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+ * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
+ * @arg SDMMC_FLAG_DTIMEOUT: Data timeout
+ * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
+ * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
+ * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
+ * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
+ * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
+ * @arg SDMMC_FLAG_DHOLD: Data transfer Hold
+ * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
+ * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
+ * @arg SDMMC_FLAG_DPSMACT: Data path state machine active
+ * @arg SDMMC_FLAG_CPSMACT: Command path state machine active
+ * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
+ * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
+ * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full
+ * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full
+ * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty
+ * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty
+ * @arg SDMMC_FLAG_BUSYD0: Inverted value of SDMMC_D0 line (Busy)
+ * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected
+ * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received
+ * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received
+ * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
+ * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion
+ * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure
+ * @arg SDMMC_FLAG_IDMATE: IDMA transfer error
+ * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete
+ * @retval The new state of SDMMC_FLAG (SET or RESET).
+ */
+#define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U)
+
+
+/**
+ * @brief Clears the SDMMC pending flags.
+ * @param __INSTANCE__ Pointer to SDMMC register base
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
+ * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+ * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
+ * @arg SDMMC_FLAG_DTIMEOUT: Data timeout
+ * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
+ * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
+ * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
+ * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
+ * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
+ * @arg SDMMC_FLAG_DHOLD: Data transfer Hold
+ * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
+ * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
+ * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected
+ * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received
+ * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received
+ * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
+ * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion
+ * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure
+ * @arg SDMMC_FLAG_IDMATE: IDMA transfer error
+ * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete
+ * @retval None
+ */
+#define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
+
+/**
+ * @brief Checks whether the specified SDMMC interrupt has occurred or not.
+ * @param __INSTANCE__ Pointer to SDMMC register base
+ * @param __INTERRUPT__ specifies the SDMMC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
+ * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
+ * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
+ * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
+ * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
+ * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
+ * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+ * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
+ * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
+ * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
+ * @retval The new state of SDMMC_IT (SET or RESET).
+ */
+#define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+ * @brief Clears the SDMMC's interrupt pending bits.
+ * @param __INSTANCE__ Pointer to SDMMC register base
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
+ * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
+ * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
+ * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
+ * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
+ * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
+ * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+ * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
+ * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
+ * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
+ * @retval None
+ */
+#define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
+
+/**
+ * @brief Enable Start the SD I/O Read Wait operation.
+ * @param __INSTANCE__ Pointer to SDMMC register base
+ * @retval None
+ */
+#define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART)
+
+/**
+ * @brief Disable Start the SD I/O Read Wait operations.
+ * @param __INSTANCE__ Pointer to SDMMC register base
+ * @retval None
+ */
+#define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART)
+
+/**
+ * @brief Enable Start the SD I/O Read Wait operation.
+ * @param __INSTANCE__ Pointer to SDMMC register base
+ * @retval None
+ */
+#define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP)
+
+/**
+ * @brief Disable Stop the SD I/O Read Wait operations.
+ * @param __INSTANCE__ Pointer to SDMMC register base
+ * @retval None
+ */
+#define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP)
+
+/**
+ * @brief Enable the SD I/O Mode Operation.
+ * @param __INSTANCE__ Pointer to SDMMC register base
+ * @retval None
+ */
+#define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN)
+
+/**
+ * @brief Disable the SD I/O Mode Operation.
+ * @param __INSTANCE__ Pointer to SDMMC register base
+ * @retval None
+ */
+#define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN)
+
+/**
+ * @brief Enable the SD I/O Suspend command sending.
+ * @param __INSTANCE__ Pointer to SDMMC register base
+ * @retval None
+ */
+#define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSUSPEND)
+
+/**
+ * @brief Disable the SD I/O Suspend command sending.
+ * @param __INSTANCE__ Pointer to SDMMC register base
+ * @retval None
+ */
+#define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSUSPEND)
+
+/**
+ * @brief Enable the CMDTRANS mode.
+ * @param __INSTANCE__ Pointer to SDMMC register base
+ * @retval None
+ */
+#define __SDMMC_CMDTRANS_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDTRANS)
+
+/**
+ * @brief Disable the CMDTRANS mode.
+ * @param __INSTANCE__ Pointer to SDMMC register base
+ * @retval None
+ */
+#define __SDMMC_CMDTRANS_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDTRANS)
+
+/**
+ * @brief Enable the CMDSTOP mode.
+ * @param __INSTANCE__ Pointer to SDMMC register base
+ * @retval None
+ */
+#define __SDMMC_CMDSTOP_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSTOP)
+
+/**
+ * @brief Disable the CMDSTOP mode.
+ * @param __INSTANCE__ Pointer to SDMMC register base
+ * @retval None
+ */
+#define __SDMMC_CMDSTOP_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSTOP)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SDMMC_LL_Exported_Functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions **********************************/
+/** @addtogroup HAL_SDMMC_LL_Group1
+ * @{
+ */
+HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init);
+/**
+ * @}
+ */
+
+/* I/O operation functions *****************************************************/
+/** @addtogroup HAL_SDMMC_LL_Group2
+ * @{
+ */
+uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx);
+HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData);
+/**
+ * @}
+ */
+
+/* Peripheral Control functions ************************************************/
+/** @addtogroup HAL_SDMMC_LL_Group3
+ * @{
+ */
+HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx);
+HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx);
+HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx);
+
+/* Command path state machine (CPSM) management functions */
+HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command);
+uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response);
+
+/* Data path state machine (DPSM) management functions */
+HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data);
+uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx);
+
+/* SDMMC Cards mode management functions */
+HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode);
+/**
+ * @}
+ */
+
+/* SDMMC Commands management functions ******************************************/
+/** @addtogroup HAL_SDMMC_LL_Group4
+ * @{
+ */
+uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize);
+uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
+uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
+uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);
+uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);
+uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
+uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
+uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
+uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
+uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx, uint32_t EraseType);
+uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint32_t Addr);
+uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth);
+uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA);
+uint32_t SDMMC_CmdSetRelAddMmc(SDMMC_TypeDef *SDMMCx, uint16_t RCA);
+uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+/**
+ * @}
+ */
+
+/* SDMMC Responses management functions *****************************************/
+/** @addtogroup HAL_SDMMC_LL_Group5
+ * @{
+ */
+uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout);
+uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA);
+uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx);
+/**
+ * @}
+ */
+
+/* Linked List functions *******************************************************/
+/** @addtogroup HAL_SDMMC_LL_Group6
+ * @{
+ */
+uint32_t SDMMC_DMALinkedList_BuildNode(SDMMC_DMALinkNodeTypeDef *pNode, SDMMC_DMALinkNodeConfTypeDef *pNodeConf);
+uint32_t SDMMC_DMALinkedList_InsertNode(SDMMC_DMALinkedListTypeDef *pLinkedList, SDMMC_DMALinkNodeTypeDef *pPrevNode,
+ SDMMC_DMALinkNodeTypeDef *pNode);
+uint32_t SDMMC_DMALinkedList_RemoveNode(SDMMC_DMALinkedListTypeDef *pLinkedList, SDMMC_DMALinkNodeTypeDef *pNode);
+uint32_t SDMMC_DMALinkedList_LockNode(SDMMC_DMALinkNodeTypeDef *pNode);
+uint32_t SDMMC_DMALinkedList_UnlockNode(SDMMC_DMALinkNodeTypeDef *pNode);
+uint32_t SDMMC_DMALinkedList_EnableCircularMode(SDMMC_DMALinkedListTypeDef *pLinkedList);
+uint32_t SDMMC_DMALinkedList_DisableCircularMode(SDMMC_DMALinkedListTypeDef *pLinkedList);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_LL_SDMMC_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_spi.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_spi.h
new file mode 100644
index 00000000..a02c5da8
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_spi.h
@@ -0,0 +1,2701 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_spi.h
+ * @author MCD Application Team
+ * @brief Header file of SPI LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_LL_SPI_H
+#define STM32U5xx_LL_SPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx.h"
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined(SPI1) || defined(SPI2) || defined(SPI3)
+
+/** @defgroup SPI_LL SPI
+ * @{
+ */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SPI_LL_Private_Macros SPI Private Macros
+ * @{
+ */
+#define IS_LL_SPI_GRP1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) ||\
+ ((__INSTANCE__) == SPI2)
+
+#define IS_LL_SPI_GRP2_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPI3)
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup SPI_LL_Exported_Types SPI Exported Types
+ * @{
+ */
+
+/**
+ * @brief SPI Init structures definition
+ */
+typedef struct
+{
+ uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
+ This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_SPI_SetTransferDirection().*/
+
+ uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
+ This parameter can be a value of @ref SPI_LL_EC_MODE.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_SPI_SetMode().*/
+
+ uint32_t DataWidth; /*!< Specifies the SPI data width.
+ This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_SPI_SetDataWidth().*/
+
+ uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
+ This parameter can be a value of @ref SPI_LL_EC_POLARITY.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_SPI_SetClockPolarity().*/
+
+ uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
+ This parameter can be a value of @ref SPI_LL_EC_PHASE.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_SPI_SetClockPhase().*/
+
+ uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin)
+ or by software using the SSI bit.
+
+ This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_SPI_SetNSSMode().*/
+
+ uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure
+ the transmit and receive SCK clock.
+ This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
+ @note The communication clock is derived from the master clock.
+ The slave clock does not need to be set.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_SPI_SetBaudRatePrescaler().*/
+
+ uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
+ This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_SPI_SetTransferBitOrder().*/
+
+ uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
+ This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
+
+ This feature can be modified afterwards using unitary functions
+ @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
+
+ uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
+ This parameter must be a number between Min_Data = 0x00
+ and Max_Data = 0xFFFFFFFF.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_SPI_SetCRCPolynomial().*/
+
+} LL_SPI_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
+ * @{
+ */
+
+/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_SPI_ReadReg function
+ * @{
+ */
+#define LL_SPI_SR_RXP (SPI_SR_RXP)
+#define LL_SPI_SR_TXP (SPI_SR_TXP)
+#define LL_SPI_SR_DXP (SPI_SR_DXP)
+#define LL_SPI_SR_EOT (SPI_SR_EOT)
+#define LL_SPI_SR_TXTF (SPI_SR_TXTF)
+#define LL_SPI_SR_UDR (SPI_SR_UDR)
+#define LL_SPI_SR_CRCE (SPI_SR_CRCE)
+#define LL_SPI_SR_MODF (SPI_SR_MODF)
+#define LL_SPI_SR_OVR (SPI_SR_OVR)
+#define LL_SPI_SR_TIFRE (SPI_SR_TIFRE)
+#define LL_SPI_SR_SUSP (SPI_SR_SUSP)
+#define LL_SPI_SR_TXC (SPI_SR_TXC)
+#define LL_SPI_SR_RXWNE (SPI_SR_RXWNE)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
+ * @{
+ */
+#define LL_SPI_IER_RXPIE (SPI_IER_RXPIE)
+#define LL_SPI_IER_TXPIE (SPI_IER_TXPIE)
+#define LL_SPI_IER_DXPIE (SPI_IER_DXPIE)
+#define LL_SPI_IER_EOTIE (SPI_IER_EOTIE)
+#define LL_SPI_IER_TXTFIE (SPI_IER_TXTFIE)
+#define LL_SPI_IER_UDRIE (SPI_IER_UDRIE)
+#define LL_SPI_IER_OVRIE (SPI_IER_OVRIE)
+#define LL_SPI_IER_CRCEIE (SPI_IER_CRCEIE)
+#define LL_SPI_IER_TIFREIE (SPI_IER_TIFREIE)
+#define LL_SPI_IER_MODFIE (SPI_IER_MODFIE)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_MODE Mode
+ * @{
+ */
+#define LL_SPI_MODE_MASTER (SPI_CFG2_MASTER)
+#define LL_SPI_MODE_SLAVE (0x00000000UL)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_SS_LEVEL SS Level
+ * @{
+ */
+#define LL_SPI_SS_LEVEL_HIGH (SPI_CR1_SSI)
+#define LL_SPI_SS_LEVEL_LOW (0x00000000UL)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_SS_IDLENESS SS Idleness
+ * @{
+ */
+#define LL_SPI_SS_IDLENESS_00CYCLE (0x00000000UL)
+#define LL_SPI_SS_IDLENESS_01CYCLE (SPI_CFG2_MSSI_0)
+#define LL_SPI_SS_IDLENESS_02CYCLE (SPI_CFG2_MSSI_1)
+#define LL_SPI_SS_IDLENESS_03CYCLE (SPI_CFG2_MSSI_0 | SPI_CFG2_MSSI_1)
+#define LL_SPI_SS_IDLENESS_04CYCLE (SPI_CFG2_MSSI_2)
+#define LL_SPI_SS_IDLENESS_05CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0)
+#define LL_SPI_SS_IDLENESS_06CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1)
+#define LL_SPI_SS_IDLENESS_07CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
+#define LL_SPI_SS_IDLENESS_08CYCLE (SPI_CFG2_MSSI_3)
+#define LL_SPI_SS_IDLENESS_09CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_0)
+#define LL_SPI_SS_IDLENESS_10CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1)
+#define LL_SPI_SS_IDLENESS_11CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
+#define LL_SPI_SS_IDLENESS_12CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2)
+#define LL_SPI_SS_IDLENESS_13CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0)
+#define LL_SPI_SS_IDLENESS_14CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1)
+#define LL_SPI_SS_IDLENESS_15CYCLE (SPI_CFG2_MSSI_3\
+ | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_ID_IDLENESS Master Inter-Data Idleness
+ * @{
+ */
+#define LL_SPI_ID_IDLENESS_00CYCLE (0x00000000UL)
+#define LL_SPI_ID_IDLENESS_01CYCLE (SPI_CFG2_MIDI_0)
+#define LL_SPI_ID_IDLENESS_02CYCLE (SPI_CFG2_MIDI_1)
+#define LL_SPI_ID_IDLENESS_03CYCLE (SPI_CFG2_MIDI_0 | SPI_CFG2_MIDI_1)
+#define LL_SPI_ID_IDLENESS_04CYCLE (SPI_CFG2_MIDI_2)
+#define LL_SPI_ID_IDLENESS_05CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0)
+#define LL_SPI_ID_IDLENESS_06CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1)
+#define LL_SPI_ID_IDLENESS_07CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
+#define LL_SPI_ID_IDLENESS_08CYCLE (SPI_CFG2_MIDI_3)
+#define LL_SPI_ID_IDLENESS_09CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_0)
+#define LL_SPI_ID_IDLENESS_10CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1)
+#define LL_SPI_ID_IDLENESS_11CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
+#define LL_SPI_ID_IDLENESS_12CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2)
+#define LL_SPI_ID_IDLENESS_13CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0)
+#define LL_SPI_ID_IDLENESS_14CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1)
+#define LL_SPI_ID_IDLENESS_15CYCLE (SPI_CFG2_MIDI_3\
+ | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_TXCRCINIT_ALL TXCRC Init All
+ * @{
+ */
+#define LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL)
+#define LL_SPI_TXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_TCRCINI)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_RXCRCINIT_ALL RXCRC Init All
+ * @{
+ */
+#define LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL)
+#define LL_SPI_RXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_RCRCINI)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_UDR_CONFIG_REGISTER UDR Config Register
+ * @{
+ */
+#define LL_SPI_UDR_CONFIG_REGISTER_PATTERN (0x00000000UL)
+#define LL_SPI_UNDERRUN_BEHAV_LAST_RECEIVED (SPI_CFG1_UDRCFG)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_PROTOCOL Protocol
+ * @{
+ */
+#define LL_SPI_PROTOCOL_MOTOROLA (0x00000000UL)
+#define LL_SPI_PROTOCOL_TI (SPI_CFG2_SP_0)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_PHASE Phase
+ * @{
+ */
+#define LL_SPI_PHASE_1EDGE (0x00000000UL)
+#define LL_SPI_PHASE_2EDGE (SPI_CFG2_CPHA)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_POLARITY Polarity
+ * @{
+ */
+#define LL_SPI_POLARITY_LOW (0x00000000UL)
+#define LL_SPI_POLARITY_HIGH (SPI_CFG2_CPOL)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_NSS_POLARITY NSS Polarity
+ * @{
+ */
+#define LL_SPI_NSS_POLARITY_LOW (0x00000000UL)
+#define LL_SPI_NSS_POLARITY_HIGH (SPI_CFG2_SSIOP)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
+ * @{
+ */
+#define LL_SPI_BAUDRATEPRESCALER_BYPASS (SPI_CFG1_BPASS)
+#define LL_SPI_BAUDRATEPRESCALER_DIV2 (0x00000000UL)
+#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CFG1_MBR_0)
+#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CFG1_MBR_1)
+#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0)
+#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CFG1_MBR_2)
+#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_0)
+#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1)
+#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_BIT_ORDER Bit Order
+ * @{
+ */
+#define LL_SPI_LSB_FIRST (SPI_CFG2_LSBFRST)
+#define LL_SPI_MSB_FIRST (0x00000000UL)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
+ * @{
+ */
+#define LL_SPI_FULL_DUPLEX (0x00000000UL)
+#define LL_SPI_SIMPLEX_TX (SPI_CFG2_COMM_0)
+#define LL_SPI_SIMPLEX_RX (SPI_CFG2_COMM_1)
+#define LL_SPI_HALF_DUPLEX_RX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1)
+#define LL_SPI_HALF_DUPLEX_TX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1|SPI_CR1_HDDIR)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_DATAWIDTH Data Width
+ * @{
+ */
+#define LL_SPI_DATAWIDTH_4BIT (SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1)
+#define LL_SPI_DATAWIDTH_5BIT (SPI_CFG1_DSIZE_2)
+#define LL_SPI_DATAWIDTH_6BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
+#define LL_SPI_DATAWIDTH_7BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
+#define LL_SPI_DATAWIDTH_8BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
+#define LL_SPI_DATAWIDTH_9BIT (SPI_CFG1_DSIZE_3)
+#define LL_SPI_DATAWIDTH_10BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0)
+#define LL_SPI_DATAWIDTH_11BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1)
+#define LL_SPI_DATAWIDTH_12BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
+#define LL_SPI_DATAWIDTH_13BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2)
+#define LL_SPI_DATAWIDTH_14BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
+#define LL_SPI_DATAWIDTH_15BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
+#define LL_SPI_DATAWIDTH_16BIT (SPI_CFG1_DSIZE_3\
+ | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
+#define LL_SPI_DATAWIDTH_17BIT (SPI_CFG1_DSIZE_4)
+#define LL_SPI_DATAWIDTH_18BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0)
+#define LL_SPI_DATAWIDTH_19BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_1)
+#define LL_SPI_DATAWIDTH_20BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1)
+#define LL_SPI_DATAWIDTH_21BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2)
+#define LL_SPI_DATAWIDTH_22BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
+#define LL_SPI_DATAWIDTH_23BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
+#define LL_SPI_DATAWIDTH_24BIT (SPI_CFG1_DSIZE_4\
+ | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
+#define LL_SPI_DATAWIDTH_25BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3)
+#define LL_SPI_DATAWIDTH_26BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0)
+#define LL_SPI_DATAWIDTH_27BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1)
+#define LL_SPI_DATAWIDTH_28BIT (SPI_CFG1_DSIZE_4\
+ | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
+#define LL_SPI_DATAWIDTH_29BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2)
+#define LL_SPI_DATAWIDTH_30BIT (SPI_CFG1_DSIZE_4\
+ | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
+#define LL_SPI_DATAWIDTH_31BIT (SPI_CFG1_DSIZE_4\
+ | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
+#define LL_SPI_DATAWIDTH_32BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3\
+ | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_FIFO_TH FIFO Threshold
+ * @{
+ */
+#define LL_SPI_FIFO_TH_01DATA (0x00000000UL)
+#define LL_SPI_FIFO_TH_02DATA (SPI_CFG1_FTHLV_0)
+#define LL_SPI_FIFO_TH_03DATA (SPI_CFG1_FTHLV_1)
+#define LL_SPI_FIFO_TH_04DATA (SPI_CFG1_FTHLV_0 | SPI_CFG1_FTHLV_1)
+#define LL_SPI_FIFO_TH_05DATA (SPI_CFG1_FTHLV_2)
+#define LL_SPI_FIFO_TH_06DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0)
+#define LL_SPI_FIFO_TH_07DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1)
+#define LL_SPI_FIFO_TH_08DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
+#define LL_SPI_FIFO_TH_09DATA (SPI_CFG1_FTHLV_3)
+#define LL_SPI_FIFO_TH_10DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_0)
+#define LL_SPI_FIFO_TH_11DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1)
+#define LL_SPI_FIFO_TH_12DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
+#define LL_SPI_FIFO_TH_13DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2)
+#define LL_SPI_FIFO_TH_14DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0)
+#define LL_SPI_FIFO_TH_15DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1)
+#define LL_SPI_FIFO_TH_16DATA (SPI_CFG1_FTHLV_3\
+ | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
+ * @{
+ */
+#define LL_SPI_CRCCALCULATION_DISABLE (0x00000000UL) /*!< CRC calculation disabled */
+#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CFG1_CRCEN) /*!< CRC calculation enabled */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup SPI_LL_EC_CRC CRC
+ * @{
+ */
+#define LL_SPI_CRC_4BIT (SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1)
+#define LL_SPI_CRC_5BIT (SPI_CFG1_CRCSIZE_2)
+#define LL_SPI_CRC_6BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
+#define LL_SPI_CRC_7BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
+#define LL_SPI_CRC_8BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
+#define LL_SPI_CRC_9BIT (SPI_CFG1_CRCSIZE_3)
+#define LL_SPI_CRC_10BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0)
+#define LL_SPI_CRC_11BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1)
+#define LL_SPI_CRC_12BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
+#define LL_SPI_CRC_13BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2)
+#define LL_SPI_CRC_14BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
+#define LL_SPI_CRC_15BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
+#define LL_SPI_CRC_16BIT (SPI_CFG1_CRCSIZE_3\
+ | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
+#define LL_SPI_CRC_17BIT (SPI_CFG1_CRCSIZE_4)
+#define LL_SPI_CRC_18BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0)
+#define LL_SPI_CRC_19BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_1)
+#define LL_SPI_CRC_20BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1)
+#define LL_SPI_CRC_21BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2)
+#define LL_SPI_CRC_22BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
+#define LL_SPI_CRC_23BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
+#define LL_SPI_CRC_24BIT (SPI_CFG1_CRCSIZE_4\
+ | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
+#define LL_SPI_CRC_25BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3)
+#define LL_SPI_CRC_26BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0)
+#define LL_SPI_CRC_27BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1)
+#define LL_SPI_CRC_28BIT (SPI_CFG1_CRCSIZE_4\
+ | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
+#define LL_SPI_CRC_29BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2)
+#define LL_SPI_CRC_30BIT (SPI_CFG1_CRCSIZE_4\
+ | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
+#define LL_SPI_CRC_31BIT (SPI_CFG1_CRCSIZE_4\
+ | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
+#define LL_SPI_CRC_32BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3\
+ | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_NSS_MODE NSS Mode
+ * @{
+ */
+#define LL_SPI_NSS_SOFT (SPI_CFG2_SSM)
+#define LL_SPI_NSS_HARD_INPUT (0x00000000UL)
+#define LL_SPI_NSS_HARD_OUTPUT (SPI_CFG2_SSOE)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_RX_FIFO RxFIFO Packing LeVel
+ * @{
+ */
+#define LL_SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packet available is the RxFIFO */
+#define LL_SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0)
+#define LL_SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1)
+#define LL_SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_AUTOCR_TRIGSEL Autonomous Trigger selection
+ * @brief SPI Autonomous Trigger selection
+ * @{
+ */
+#define LL_SPI_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for SPI1 and SPI2 */
+#define LL_SPI_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for SPI3 */
+
+/*!< HW Trigger signal is GPDMA_CH0_TRG */
+#define LL_SPI_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x00000000U))
+/*!< HW Trigger signal is GPDMA_CH1_TRG */
+#define LL_SPI_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x1U << SPI_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is GPDMA_CH2_TRG */
+#define LL_SPI_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x2U << SPI_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is GPDMA_CH3_TRG */
+#define LL_SPI_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x3U << SPI_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is EXTI4_TRG */
+#define LL_SPI_GRP1_EXTI4_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x4U << SPI_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is EXTI9_TRG */
+#define LL_SPI_GRP1_EXTI9_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x5U << SPI_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is LPTIM1_CH1_TRG */
+#define LL_SPI_GRP1_LPTIM1_CH1_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x6U << SPI_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is LPTIM2_CH1_TRG */
+#define LL_SPI_GRP1_LPTIM2_CH1_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x7U << SPI_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is COMP1_TRG */
+#define LL_SPI_GRP1_COMP1_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x8U << SPI_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is COMP2_TRG */
+#define LL_SPI_GRP1_COMP2_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x9U << SPI_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is RTC_ALRA_TRG */
+#define LL_SPI_GRP1_RTC_ALRA_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0xAU << SPI_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is RTC_WUT_TRG */
+#define LL_SPI_GRP1_RTC_WUT_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0xBU << SPI_AUTOCR_TRIGSEL_Pos))
+
+/*!< HW Trigger signal is LPDMA_CH0_TRG */
+#define LL_SPI_GRP2_LPDMA_CH0_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x00000000U))
+/*!< HW Trigger signal is LPDMA_CH1_TRG */
+#define LL_SPI_GRP2_LPDMA_CH1_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x1U << SPI_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is LPDMA_CH2_TRG */
+#define LL_SPI_GRP2_LPDMA_CH2_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x2U << SPI_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is LPDMA_CH3_TRG */
+#define LL_SPI_GRP2_LPDMA_CH3_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x3U << SPI_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is EXTI4_TRG */
+#define LL_SPI_GRP2_EXTI4_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x4U << SPI_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is EXTI8_TRG */
+#define LL_SPI_GRP2_EXTI8_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x5U << SPI_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is LPTIM1_CH1_TRG */
+#define LL_SPI_GRP2_LPTIM1_CH1_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x6U << SPI_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is LPTIM3_CH1_TRG */
+#define LL_SPI_GRP2_LPTIM3_CH1_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x7U << SPI_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is COMP1_TRG */
+#define LL_SPI_GRP2_COMP1_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x8U << SPI_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is COMP2_TRG */
+#define LL_SPI_GRP2_COMP2_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x9U << SPI_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is RTC_ALRA_TRG */
+#define LL_SPI_GRP2_RTC_ALRA_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0xAU << SPI_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is RTC_WUT_TRG */
+#define LL_SPI_GRP2_RTC_WUT_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0xBU << SPI_AUTOCR_TRIGSEL_Pos))
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_AUTOCR_TRIGPOL Autonomous Trigger Polarity
+ * @brief SPI Autonomous Trigger Polarity
+ * @{
+ */
+#define LL_SPI_TRIG_POLARITY_RISING 0x00000000U /*!< SPI triggered on rising edge */
+#define LL_SPI_TRIG_POLARITY_FALLING SPI_AUTOCR_TRIGPOL /*!< SPI triggered on falling edge */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
+ * @{
+ */
+
+/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in SPI register
+ * @param __INSTANCE__ SPI Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in SPI register
+ * @param __INSTANCE__ SPI Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
+ * @{
+ */
+
+/** @defgroup SPI_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Enable SPI peripheral
+ * @rmtoll CR1 SPE LL_SPI_Enable
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR1, SPI_CR1_SPE);
+}
+
+/**
+ * @brief Disable SPI peripheral
+ * @note When disabling the SPI, follow the procedure described in the Reference Manual.
+ * @rmtoll CR1 SPE LL_SPI_Disable
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
+}
+
+/**
+ * @brief Check if SPI peripheral is enabled
+ * @rmtoll CR1 SPE LL_SPI_IsEnabled
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0)
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Swap the MOSI and MISO pin
+ * @note This configuration can not be changed when SPI is enabled.
+ * @rmtoll CFG2 IOSWP LL_SPI_EnableIOSwap
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableIOSwap(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CFG2, SPI_CFG2_IOSWP);
+}
+
+/**
+ * @brief Restore default function for MOSI and MISO pin
+ * @note This configuration can not be changed when SPI is enabled.
+ * @rmtoll CFG2 IOSWP LL_SPI_DisableIOSwap
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableIOSwap(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CFG2, SPI_CFG2_IOSWP);
+}
+
+/**
+ * @brief Check if MOSI and MISO pin are swapped
+ * @rmtoll CFG2 IOSWP LL_SPI_IsEnabledIOSwap
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0)
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOSwap(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->CFG2, SPI_CFG2_IOSWP) == (SPI_CFG2_IOSWP)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable GPIO control
+ * @note This configuration can not be changed when SPI is enabled.
+ * @rmtoll CFG2 AFCNTR LL_SPI_EnableGPIOControl
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableGPIOControl(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR);
+}
+
+/**
+ * @brief Disable GPIO control
+ * @note This configuration can not be changed when SPI is enabled.
+ * @rmtoll CFG2 AFCNTR LL_SPI_DisableGPIOControl
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableGPIOControl(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR);
+}
+
+/**
+ * @brief Check if GPIO control is active
+ * @rmtoll CFG2 AFCNTR LL_SPI_IsEnabledGPIOControl
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0)
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledGPIOControl(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR) == (SPI_CFG2_AFCNTR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set SPI Mode to Master or Slave
+ * @note This configuration can not be changed when SPI is enabled.
+ * @rmtoll CFG2 MASTER LL_SPI_SetMode
+ * @param SPIx SPI Instance
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_SPI_MODE_MASTER
+ * @arg @ref LL_SPI_MODE_SLAVE
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
+{
+ MODIFY_REG(SPIx->CFG2, SPI_CFG2_MASTER, Mode);
+}
+
+/**
+ * @brief Get SPI Mode (Master or Slave)
+ * @rmtoll CFG2 MASTER LL_SPI_GetMode
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_MODE_MASTER
+ * @arg @ref LL_SPI_MODE_SLAVE
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MASTER));
+}
+
+/**
+ * @brief Configure the Idleness applied by master between active edge of SS and first send data
+ * @rmtoll CFG2 MSSI LL_SPI_SetMasterSSIdleness
+ * @param SPIx SPI Instance
+ * @param MasterSSIdleness This parameter can be one of the following values:
+ * @arg @ref LL_SPI_SS_IDLENESS_00CYCLE
+ * @arg @ref LL_SPI_SS_IDLENESS_01CYCLE
+ * @arg @ref LL_SPI_SS_IDLENESS_02CYCLE
+ * @arg @ref LL_SPI_SS_IDLENESS_03CYCLE
+ * @arg @ref LL_SPI_SS_IDLENESS_04CYCLE
+ * @arg @ref LL_SPI_SS_IDLENESS_05CYCLE
+ * @arg @ref LL_SPI_SS_IDLENESS_06CYCLE
+ * @arg @ref LL_SPI_SS_IDLENESS_07CYCLE
+ * @arg @ref LL_SPI_SS_IDLENESS_08CYCLE
+ * @arg @ref LL_SPI_SS_IDLENESS_09CYCLE
+ * @arg @ref LL_SPI_SS_IDLENESS_10CYCLE
+ * @arg @ref LL_SPI_SS_IDLENESS_11CYCLE
+ * @arg @ref LL_SPI_SS_IDLENESS_12CYCLE
+ * @arg @ref LL_SPI_SS_IDLENESS_13CYCLE
+ * @arg @ref LL_SPI_SS_IDLENESS_14CYCLE
+ * @arg @ref LL_SPI_SS_IDLENESS_15CYCLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetMasterSSIdleness(SPI_TypeDef *SPIx, uint32_t MasterSSIdleness)
+{
+ MODIFY_REG(SPIx->CFG2, SPI_CFG2_MSSI, MasterSSIdleness);
+}
+
+/**
+ * @brief Get the configured Idleness applied by master
+ * @rmtoll CFG2 MSSI LL_SPI_GetMasterSSIdleness
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_SS_IDLENESS_00CYCLE
+ * @arg @ref LL_SPI_SS_IDLENESS_01CYCLE
+ * @arg @ref LL_SPI_SS_IDLENESS_02CYCLE
+ * @arg @ref LL_SPI_SS_IDLENESS_03CYCLE
+ * @arg @ref LL_SPI_SS_IDLENESS_04CYCLE
+ * @arg @ref LL_SPI_SS_IDLENESS_05CYCLE
+ * @arg @ref LL_SPI_SS_IDLENESS_06CYCLE
+ * @arg @ref LL_SPI_SS_IDLENESS_07CYCLE
+ * @arg @ref LL_SPI_SS_IDLENESS_08CYCLE
+ * @arg @ref LL_SPI_SS_IDLENESS_09CYCLE
+ * @arg @ref LL_SPI_SS_IDLENESS_10CYCLE
+ * @arg @ref LL_SPI_SS_IDLENESS_11CYCLE
+ * @arg @ref LL_SPI_SS_IDLENESS_12CYCLE
+ * @arg @ref LL_SPI_SS_IDLENESS_13CYCLE
+ * @arg @ref LL_SPI_SS_IDLENESS_14CYCLE
+ * @arg @ref LL_SPI_SS_IDLENESS_15CYCLE
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetMasterSSIdleness(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MSSI));
+}
+
+/**
+ * @brief Configure the idleness applied by master between data frame
+ * @rmtoll CFG2 MIDI LL_SPI_SetInterDataIdleness
+ * @param SPIx SPI Instance
+ * @param MasterInterDataIdleness This parameter can be one of the following values:
+ * @arg @ref LL_SPI_ID_IDLENESS_00CYCLE
+ * @arg @ref LL_SPI_ID_IDLENESS_01CYCLE
+ * @arg @ref LL_SPI_ID_IDLENESS_02CYCLE
+ * @arg @ref LL_SPI_ID_IDLENESS_03CYCLE
+ * @arg @ref LL_SPI_ID_IDLENESS_04CYCLE
+ * @arg @ref LL_SPI_ID_IDLENESS_05CYCLE
+ * @arg @ref LL_SPI_ID_IDLENESS_06CYCLE
+ * @arg @ref LL_SPI_ID_IDLENESS_07CYCLE
+ * @arg @ref LL_SPI_ID_IDLENESS_08CYCLE
+ * @arg @ref LL_SPI_ID_IDLENESS_09CYCLE
+ * @arg @ref LL_SPI_ID_IDLENESS_10CYCLE
+ * @arg @ref LL_SPI_ID_IDLENESS_11CYCLE
+ * @arg @ref LL_SPI_ID_IDLENESS_12CYCLE
+ * @arg @ref LL_SPI_ID_IDLENESS_13CYCLE
+ * @arg @ref LL_SPI_ID_IDLENESS_14CYCLE
+ * @arg @ref LL_SPI_ID_IDLENESS_15CYCLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetInterDataIdleness(SPI_TypeDef *SPIx, uint32_t MasterInterDataIdleness)
+{
+ MODIFY_REG(SPIx->CFG2, SPI_CFG2_MIDI, MasterInterDataIdleness);
+}
+
+/**
+ * @brief Get the configured inter data idleness
+ * @rmtoll CFG2 MIDI LL_SPI_SetInterDataIdleness
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_ID_IDLENESS_00CYCLE
+ * @arg @ref LL_SPI_ID_IDLENESS_01CYCLE
+ * @arg @ref LL_SPI_ID_IDLENESS_02CYCLE
+ * @arg @ref LL_SPI_ID_IDLENESS_03CYCLE
+ * @arg @ref LL_SPI_ID_IDLENESS_04CYCLE
+ * @arg @ref LL_SPI_ID_IDLENESS_05CYCLE
+ * @arg @ref LL_SPI_ID_IDLENESS_06CYCLE
+ * @arg @ref LL_SPI_ID_IDLENESS_07CYCLE
+ * @arg @ref LL_SPI_ID_IDLENESS_08CYCLE
+ * @arg @ref LL_SPI_ID_IDLENESS_09CYCLE
+ * @arg @ref LL_SPI_ID_IDLENESS_10CYCLE
+ * @arg @ref LL_SPI_ID_IDLENESS_11CYCLE
+ * @arg @ref LL_SPI_ID_IDLENESS_12CYCLE
+ * @arg @ref LL_SPI_ID_IDLENESS_13CYCLE
+ * @arg @ref LL_SPI_ID_IDLENESS_14CYCLE
+ * @arg @ref LL_SPI_ID_IDLENESS_15CYCLE
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetInterDataIdleness(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MIDI));
+}
+
+/**
+ * @brief Set transfer size
+ * @note Count is the number of frame to be transferred
+ * @rmtoll CR2 TSIZE LL_SPI_SetTransferSize
+ * @param SPIx SPI Instance
+ * @param Count 0..0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetTransferSize(SPI_TypeDef *SPIx, uint32_t Count)
+{
+ MODIFY_REG(SPIx->CR2, SPI_CR2_TSIZE, Count);
+}
+
+/**
+ * @brief Get transfer size
+ * @note Count is the number of frame to be transferred
+ * @rmtoll CR2 TSIZE LL_SPI_GetTransferSize
+ * @param SPIx SPI Instance
+ * @retval 0..0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetTransferSize(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_TSIZE));
+}
+
+/**
+ * @brief Lock the AF configuration of associated IOs
+ * @note Once this bit is set, the AF configuration remains locked until a hardware reset occurs.
+ * the reset of the IOLock bit is done by hardware. for that, LL_SPI_DisableIOLock can not exist.
+ * @rmtoll CR1 IOLOCK LL_SPI_EnableIOLock
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableIOLock(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR1, SPI_CR1_IOLOCK);
+}
+
+/**
+ * @brief Check if the AF configuration is locked.
+ * @rmtoll CR1 IOLOCK LL_SPI_IsEnabledIOLock
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0)
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOLock(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->CR1, SPI_CR1_IOLOCK) == (SPI_CR1_IOLOCK)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set Tx CRC Initialization Pattern
+ * @rmtoll CR1 TCRCINI LL_SPI_SetTxCRCInitPattern
+ * @param SPIx SPI Instance
+ * @param TXCRCInitAll This parameter can be one of the following values:
+ * @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN
+ * @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetTxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t TXCRCInitAll)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_RCRCINI, TXCRCInitAll);
+}
+
+/**
+ * @brief Get Tx CRC Initialization Pattern
+ * @rmtoll CR1 TCRCINI LL_SPI_GetTxCRCInitPattern
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN
+ * @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetTxCRCInitPattern(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_TCRCINI));
+}
+
+/**
+ * @brief Set Rx CRC Initialization Pattern
+ * @rmtoll CR1 RCRCINI LL_SPI_SetRxCRCInitPattern
+ * @param SPIx SPI Instance
+ * @param RXCRCInitAll This parameter can be one of the following values:
+ * @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN
+ * @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetRxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t RXCRCInitAll)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_RCRCINI, RXCRCInitAll);
+}
+
+/**
+ * @brief Get Rx CRC Initialization Pattern
+ * @rmtoll CR1 RCRCINI LL_SPI_GetRxCRCInitPattern
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN
+ * @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetRxCRCInitPattern(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RCRCINI));
+}
+
+/**
+ * @brief Set internal SS input level ignoring what comes from PIN.
+ * @note This configuration has effect only with config LL_SPI_NSS_SOFT
+ * @rmtoll CR1 SSI LL_SPI_SetInternalSSLevel
+ * @param SPIx SPI Instance
+ * @param SSLevel This parameter can be one of the following values:
+ * @arg @ref LL_SPI_SS_LEVEL_HIGH
+ * @arg @ref LL_SPI_SS_LEVEL_LOW
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetInternalSSLevel(SPI_TypeDef *SPIx, uint32_t SSLevel)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_SSI, SSLevel);
+}
+
+/**
+ * @brief Get internal SS input level
+ * @rmtoll CR1 SSI LL_SPI_GetInternalSSLevel
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_SS_LEVEL_HIGH
+ * @arg @ref LL_SPI_SS_LEVEL_LOW
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetInternalSSLevel(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_SSI));
+}
+
+/**
+ * @brief Enable CRC computation on 33/17 bits
+ * @rmtoll CR1 CRC33_17 LL_SPI_EnableFullSizeCRC
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableFullSizeCRC(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR1, SPI_CR1_CRC33_17);
+}
+
+/**
+ * @brief Disable CRC computation on 33/17 bits
+ * @rmtoll CR1 CRC33_17 LL_SPI_DisableFullSizeCRC
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableFullSizeCRC(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR1, SPI_CR1_CRC33_17);
+}
+
+/**
+ * @brief Check if Enable CRC computation on 33/17 bits is enabled
+ * @rmtoll CR1 CRC33_17 LL_SPI_IsEnabledFullSizeCRC
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0)
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledFullSizeCRC(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->CR1, SPI_CR1_CRC33_17) == (SPI_CR1_CRC33_17)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Suspend an ongoing transfer for Master configuration
+ * @rmtoll CR1 CSUSP LL_SPI_SuspendMasterTransfer
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SuspendMasterTransfer(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR1, SPI_CR1_CSUSP);
+}
+
+/**
+ * @brief Start effective transfer on wire for Master configuration
+ * @rmtoll CR1 CSTART LL_SPI_StartMasterTransfer
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_StartMasterTransfer(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR1, SPI_CR1_CSTART);
+}
+
+/**
+ * @brief Check if there is an unfinished master transfer
+ * @rmtoll CR1 CSTART LL_SPI_IsActiveMasterTransfer
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0)
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveMasterTransfer(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->CR1, SPI_CR1_CSTART) == (SPI_CR1_CSTART)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable Master Rx auto suspend in case of overrun
+ * @rmtoll CR1 MASRX LL_SPI_EnableMasterRxAutoSuspend
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableMasterRxAutoSuspend(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR1, SPI_CR1_MASRX);
+}
+
+/**
+ * @brief Disable Master Rx auto suspend in case of overrun
+ * @rmtoll CR1 MASRX LL_SPI_DisableMasterRxAutoSuspend
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableMasterRxAutoSuspend(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR1, SPI_CR1_MASRX);
+}
+
+/**
+ * @brief Check if Master Rx auto suspend is activated
+ * @rmtoll CR1 MASRX LL_SPI_IsEnabledMasterRxAutoSuspend
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0)
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledMasterRxAutoSuspend(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->CR1, SPI_CR1_MASRX) == (SPI_CR1_MASRX)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set Underrun behavior
+ * @note This configuration can not be changed when SPI is enabled.
+ * @rmtoll CFG1 UDRCFG LL_SPI_SetUDRConfiguration
+ * @param SPIx SPI Instance
+ * @param UDRConfig This parameter can be one of the following values:
+ * @arg @ref LL_SPI_UDR_CONFIG_REGISTER_PATTERN
+ * @arg @ref LL_SPI_UNDERRUN_BEHAV_LAST_RECEIVED
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetUDRConfiguration(SPI_TypeDef *SPIx, uint32_t UDRConfig)
+{
+ MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRCFG, UDRConfig);
+}
+
+/**
+ * @brief Get Underrun behavior
+ * @rmtoll CFG1 UDRCFG LL_SPI_GetUDRConfiguration
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_UDR_CONFIG_REGISTER_PATTERN
+ * @arg @ref LL_SPI_UNDERRUN_BEHAV_LAST_RECEIVED
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetUDRConfiguration(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRCFG));
+}
+
+
+/**
+ * @brief Set Serial protocol used
+ * @note This configuration can not be changed when SPI is enabled.
+ * @rmtoll CFG2 SP LL_SPI_SetStandard
+ * @param SPIx SPI Instance
+ * @param Standard This parameter can be one of the following values:
+ * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
+ * @arg @ref LL_SPI_PROTOCOL_TI
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
+{
+ MODIFY_REG(SPIx->CFG2, SPI_CFG2_SP, Standard);
+}
+
+/**
+ * @brief Get Serial protocol used
+ * @rmtoll CFG2 SP LL_SPI_GetStandard
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
+ * @arg @ref LL_SPI_PROTOCOL_TI
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SP));
+}
+
+/**
+ * @brief Set Clock phase
+ * @note This configuration can not be changed when SPI is enabled.
+ * This bit is not used in SPI TI mode.
+ * @rmtoll CFG2 CPHA LL_SPI_SetClockPhase
+ * @param SPIx SPI Instance
+ * @param ClockPhase This parameter can be one of the following values:
+ * @arg @ref LL_SPI_PHASE_1EDGE
+ * @arg @ref LL_SPI_PHASE_2EDGE
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
+{
+ MODIFY_REG(SPIx->CFG2, SPI_CFG2_CPHA, ClockPhase);
+}
+
+/**
+ * @brief Get Clock phase
+ * @rmtoll CFG2 CPHA LL_SPI_GetClockPhase
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_PHASE_1EDGE
+ * @arg @ref LL_SPI_PHASE_2EDGE
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPHA));
+}
+
+/**
+ * @brief Set Clock polarity
+ * @note This configuration can not be changed when SPI is enabled.
+ * This bit is not used in SPI TI mode.
+ * @rmtoll CFG2 CPOL LL_SPI_SetClockPolarity
+ * @param SPIx SPI Instance
+ * @param ClockPolarity This parameter can be one of the following values:
+ * @arg @ref LL_SPI_POLARITY_LOW
+ * @arg @ref LL_SPI_POLARITY_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
+{
+ MODIFY_REG(SPIx->CFG2, SPI_CFG2_CPOL, ClockPolarity);
+}
+
+/**
+ * @brief Get Clock polarity
+ * @rmtoll CFG2 CPOL LL_SPI_GetClockPolarity
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_POLARITY_LOW
+ * @arg @ref LL_SPI_POLARITY_HIGH
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPOL));
+}
+
+/**
+ * @brief Set NSS polarity
+ * @note This configuration can not be changed when SPI is enabled.
+ * This bit is not used in SPI TI mode.
+ * @rmtoll CFG2 SSIOP LL_SPI_SetNSSPolarity
+ * @param SPIx SPI Instance
+ * @param NSSPolarity This parameter can be one of the following values:
+ * @arg @ref LL_SPI_NSS_POLARITY_LOW
+ * @arg @ref LL_SPI_NSS_POLARITY_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetNSSPolarity(SPI_TypeDef *SPIx, uint32_t NSSPolarity)
+{
+ MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSIOP, NSSPolarity);
+}
+
+/**
+ * @brief Get NSS polarity
+ * @rmtoll CFG2 SSIOP LL_SPI_GetNSSPolarity
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_NSS_POLARITY_LOW
+ * @arg @ref LL_SPI_NSS_POLARITY_HIGH
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetNSSPolarity(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSIOP));
+}
+
+/**
+ * @brief Set Baudrate Prescaler
+ * @note This configuration can not be changed when SPI is enabled.
+ * SPI BaudRate = fPCLK/Pescaler.
+ * @rmtoll CFG1 MBR BPASS LL_SPI_SetBaudRatePrescaler
+ * @param SPIx SPI Instance
+ * @param Baudrate This parameter can be one of the following values:
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_BYPASS
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Baudrate)
+{
+ MODIFY_REG(SPIx->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS), Baudrate);
+}
+
+/**
+ * @brief Get Baudrate Prescaler
+ * @rmtoll CFG1 MBR BPASS LL_SPI_GetBaudRatePrescaler
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_BYPASS
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS)));
+}
+
+/**
+ * @brief Set Transfer Bit Order
+ * @note This configuration can not be changed when SPI is enabled.
+ * This bit is not used in SPI TI mode.
+ * @rmtoll CFG2 LSBFRST LL_SPI_SetTransferBitOrder
+ * @param SPIx SPI Instance
+ * @param BitOrder This parameter can be one of the following values:
+ * @arg @ref LL_SPI_LSB_FIRST
+ * @arg @ref LL_SPI_MSB_FIRST
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
+{
+ MODIFY_REG(SPIx->CFG2, SPI_CFG2_LSBFRST, BitOrder);
+}
+
+/**
+ * @brief Get Transfer Bit Order
+ * @rmtoll CFG2 LSBFRST LL_SPI_GetTransferBitOrder
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_LSB_FIRST
+ * @arg @ref LL_SPI_MSB_FIRST
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_LSBFRST));
+}
+
+/**
+ * @brief Set Transfer Mode
+ * @note This configuration can not be changed when SPI is enabled except for half duplex direction
+ * using LL_SPI_SetHalfDuplexDirection.
+ * @rmtoll CR1 HDDIR LL_SPI_SetTransferDirection\n
+ * CFG2 COMM LL_SPI_SetTransferDirection
+ * @param SPIx SPI Instance
+ * @param TransferDirection This parameter can be one of the following values:
+ * @arg @ref LL_SPI_FULL_DUPLEX
+ * @arg @ref LL_SPI_SIMPLEX_TX
+ * @arg @ref LL_SPI_SIMPLEX_RX
+ * @arg @ref LL_SPI_HALF_DUPLEX_RX
+ * @arg @ref LL_SPI_HALF_DUPLEX_TX
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, TransferDirection & SPI_CR1_HDDIR);
+ MODIFY_REG(SPIx->CFG2, SPI_CFG2_COMM, TransferDirection & SPI_CFG2_COMM);
+}
+
+/**
+ * @brief Get Transfer Mode
+ * @rmtoll CR1 HDDIR LL_SPI_GetTransferDirection\n
+ * CFG2 COMM LL_SPI_GetTransferDirection
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_FULL_DUPLEX
+ * @arg @ref LL_SPI_SIMPLEX_TX
+ * @arg @ref LL_SPI_SIMPLEX_RX
+ * @arg @ref LL_SPI_HALF_DUPLEX_RX
+ * @arg @ref LL_SPI_HALF_DUPLEX_TX
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
+{
+ uint32_t Hddir = READ_BIT(SPIx->CR1, SPI_CR1_HDDIR);
+ uint32_t Comm = READ_BIT(SPIx->CFG2, SPI_CFG2_COMM);
+ return (Hddir | Comm);
+}
+
+/**
+ * @brief Set direction for Half-Duplex Mode
+ * @note In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex.
+ * @rmtoll CR1 HDDIR LL_SPI_SetHalfDuplexDirection
+ * @param SPIx SPI Instance
+ * @param HalfDuplexDirection This parameter can be one of the following values:
+ * @arg @ref LL_SPI_HALF_DUPLEX_RX
+ * @arg @ref LL_SPI_HALF_DUPLEX_TX
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetHalfDuplexDirection(SPI_TypeDef *SPIx, uint32_t HalfDuplexDirection)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, HalfDuplexDirection & SPI_CR1_HDDIR);
+}
+
+/**
+ * @brief Get direction for Half-Duplex Mode
+ * @note In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex.
+ * @rmtoll CR1 HDDIR LL_SPI_GetHalfDuplexDirection
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_HALF_DUPLEX_RX
+ * @arg @ref LL_SPI_HALF_DUPLEX_TX
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetHalfDuplexDirection(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_HDDIR) | SPI_CFG2_COMM);
+}
+
+/**
+ * @brief Set Frame Data Size
+ * @note This configuration can not be changed when SPI is enabled.
+ * @rmtoll CFG1 DSIZE LL_SPI_SetDataWidth
+ * @param SPIx SPI Instance
+ * @param DataWidth This parameter can be one of the following values:
+ * @arg @ref LL_SPI_DATAWIDTH_4BIT
+ * @arg @ref LL_SPI_DATAWIDTH_5BIT
+ * @arg @ref LL_SPI_DATAWIDTH_6BIT
+ * @arg @ref LL_SPI_DATAWIDTH_7BIT
+ * @arg @ref LL_SPI_DATAWIDTH_8BIT
+ * @arg @ref LL_SPI_DATAWIDTH_9BIT
+ * @arg @ref LL_SPI_DATAWIDTH_10BIT
+ * @arg @ref LL_SPI_DATAWIDTH_11BIT
+ * @arg @ref LL_SPI_DATAWIDTH_12BIT
+ * @arg @ref LL_SPI_DATAWIDTH_13BIT
+ * @arg @ref LL_SPI_DATAWIDTH_14BIT
+ * @arg @ref LL_SPI_DATAWIDTH_15BIT
+ * @arg @ref LL_SPI_DATAWIDTH_16BIT
+ * @arg @ref LL_SPI_DATAWIDTH_17BIT
+ * @arg @ref LL_SPI_DATAWIDTH_18BIT
+ * @arg @ref LL_SPI_DATAWIDTH_19BIT
+ * @arg @ref LL_SPI_DATAWIDTH_20BIT
+ * @arg @ref LL_SPI_DATAWIDTH_21BIT
+ * @arg @ref LL_SPI_DATAWIDTH_22BIT
+ * @arg @ref LL_SPI_DATAWIDTH_23BIT
+ * @arg @ref LL_SPI_DATAWIDTH_24BIT
+ * @arg @ref LL_SPI_DATAWIDTH_25BIT
+ * @arg @ref LL_SPI_DATAWIDTH_26BIT
+ * @arg @ref LL_SPI_DATAWIDTH_27BIT
+ * @arg @ref LL_SPI_DATAWIDTH_28BIT
+ * @arg @ref LL_SPI_DATAWIDTH_29BIT
+ * @arg @ref LL_SPI_DATAWIDTH_30BIT
+ * @arg @ref LL_SPI_DATAWIDTH_31BIT
+ * @arg @ref LL_SPI_DATAWIDTH_32BIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
+{
+ MODIFY_REG(SPIx->CFG1, SPI_CFG1_DSIZE, DataWidth);
+}
+
+/**
+ * @brief Get Frame Data Size
+ * @rmtoll CFG1 DSIZE LL_SPI_GetDataWidth
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_DATAWIDTH_4BIT
+ * @arg @ref LL_SPI_DATAWIDTH_5BIT
+ * @arg @ref LL_SPI_DATAWIDTH_6BIT
+ * @arg @ref LL_SPI_DATAWIDTH_7BIT
+ * @arg @ref LL_SPI_DATAWIDTH_8BIT
+ * @arg @ref LL_SPI_DATAWIDTH_9BIT
+ * @arg @ref LL_SPI_DATAWIDTH_10BIT
+ * @arg @ref LL_SPI_DATAWIDTH_11BIT
+ * @arg @ref LL_SPI_DATAWIDTH_12BIT
+ * @arg @ref LL_SPI_DATAWIDTH_13BIT
+ * @arg @ref LL_SPI_DATAWIDTH_14BIT
+ * @arg @ref LL_SPI_DATAWIDTH_15BIT
+ * @arg @ref LL_SPI_DATAWIDTH_16BIT
+ * @arg @ref LL_SPI_DATAWIDTH_17BIT
+ * @arg @ref LL_SPI_DATAWIDTH_18BIT
+ * @arg @ref LL_SPI_DATAWIDTH_19BIT
+ * @arg @ref LL_SPI_DATAWIDTH_20BIT
+ * @arg @ref LL_SPI_DATAWIDTH_21BIT
+ * @arg @ref LL_SPI_DATAWIDTH_22BIT
+ * @arg @ref LL_SPI_DATAWIDTH_23BIT
+ * @arg @ref LL_SPI_DATAWIDTH_24BIT
+ * @arg @ref LL_SPI_DATAWIDTH_25BIT
+ * @arg @ref LL_SPI_DATAWIDTH_26BIT
+ * @arg @ref LL_SPI_DATAWIDTH_27BIT
+ * @arg @ref LL_SPI_DATAWIDTH_28BIT
+ * @arg @ref LL_SPI_DATAWIDTH_29BIT
+ * @arg @ref LL_SPI_DATAWIDTH_30BIT
+ * @arg @ref LL_SPI_DATAWIDTH_31BIT
+ * @arg @ref LL_SPI_DATAWIDTH_32BIT
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_DSIZE));
+}
+
+/**
+ * @brief Set threshold of FIFO that triggers a transfer event
+ * @note This configuration can not be changed when SPI is enabled.
+ * @rmtoll CFG1 FTHLV LL_SPI_SetFIFOThreshold
+ * @param SPIx SPI Instance
+ * @param Threshold This parameter can be one of the following values:
+ * @arg @ref LL_SPI_FIFO_TH_01DATA
+ * @arg @ref LL_SPI_FIFO_TH_02DATA
+ * @arg @ref LL_SPI_FIFO_TH_03DATA
+ * @arg @ref LL_SPI_FIFO_TH_04DATA
+ * @arg @ref LL_SPI_FIFO_TH_05DATA
+ * @arg @ref LL_SPI_FIFO_TH_06DATA
+ * @arg @ref LL_SPI_FIFO_TH_07DATA
+ * @arg @ref LL_SPI_FIFO_TH_08DATA
+ * @arg @ref LL_SPI_FIFO_TH_09DATA
+ * @arg @ref LL_SPI_FIFO_TH_10DATA
+ * @arg @ref LL_SPI_FIFO_TH_11DATA
+ * @arg @ref LL_SPI_FIFO_TH_12DATA
+ * @arg @ref LL_SPI_FIFO_TH_13DATA
+ * @arg @ref LL_SPI_FIFO_TH_14DATA
+ * @arg @ref LL_SPI_FIFO_TH_15DATA
+ * @arg @ref LL_SPI_FIFO_TH_16DATA
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
+{
+ MODIFY_REG(SPIx->CFG1, SPI_CFG1_FTHLV, Threshold);
+}
+
+/**
+ * @brief Get threshold of FIFO that triggers a transfer event
+ * @rmtoll CFG1 FTHLV LL_SPI_GetFIFOThreshold
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_FIFO_TH_01DATA
+ * @arg @ref LL_SPI_FIFO_TH_02DATA
+ * @arg @ref LL_SPI_FIFO_TH_03DATA
+ * @arg @ref LL_SPI_FIFO_TH_04DATA
+ * @arg @ref LL_SPI_FIFO_TH_05DATA
+ * @arg @ref LL_SPI_FIFO_TH_06DATA
+ * @arg @ref LL_SPI_FIFO_TH_07DATA
+ * @arg @ref LL_SPI_FIFO_TH_08DATA
+ * @arg @ref LL_SPI_FIFO_TH_09DATA
+ * @arg @ref LL_SPI_FIFO_TH_10DATA
+ * @arg @ref LL_SPI_FIFO_TH_11DATA
+ * @arg @ref LL_SPI_FIFO_TH_12DATA
+ * @arg @ref LL_SPI_FIFO_TH_13DATA
+ * @arg @ref LL_SPI_FIFO_TH_14DATA
+ * @arg @ref LL_SPI_FIFO_TH_15DATA
+ * @arg @ref LL_SPI_FIFO_TH_16DATA
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetFIFOThreshold(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_FTHLV));
+}
+
+/**
+ * @brief Enable CRC
+ * @note This configuration can not be changed when SPI is enabled.
+ * @rmtoll CFG1 CRCEN LL_SPI_EnableCRC
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CFG1, SPI_CFG1_CRCEN);
+}
+
+/**
+ * @brief Disable CRC
+ * @rmtoll CFG1 CRCEN LL_SPI_DisableCRC
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CFG1, SPI_CFG1_CRCEN);
+}
+
+/**
+ * @brief Check if CRC is enabled
+ * @rmtoll CFG1 CRCEN LL_SPI_IsEnabledCRC
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->CFG1, SPI_CFG1_CRCEN) == SPI_CFG1_CRCEN) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set CRC Length
+ * @note This configuration can not be changed when SPI is enabled.
+ * @rmtoll CFG1 CRCSIZE LL_SPI_SetCRCWidth
+ * @param SPIx SPI Instance
+ * @param CRCLength This parameter can be one of the following values:
+ * @arg @ref LL_SPI_CRC_4BIT
+ * @arg @ref LL_SPI_CRC_5BIT
+ * @arg @ref LL_SPI_CRC_6BIT
+ * @arg @ref LL_SPI_CRC_7BIT
+ * @arg @ref LL_SPI_CRC_8BIT
+ * @arg @ref LL_SPI_CRC_9BIT
+ * @arg @ref LL_SPI_CRC_10BIT
+ * @arg @ref LL_SPI_CRC_11BIT
+ * @arg @ref LL_SPI_CRC_12BIT
+ * @arg @ref LL_SPI_CRC_13BIT
+ * @arg @ref LL_SPI_CRC_14BIT
+ * @arg @ref LL_SPI_CRC_15BIT
+ * @arg @ref LL_SPI_CRC_16BIT
+ * @arg @ref LL_SPI_CRC_17BIT
+ * @arg @ref LL_SPI_CRC_18BIT
+ * @arg @ref LL_SPI_CRC_19BIT
+ * @arg @ref LL_SPI_CRC_20BIT
+ * @arg @ref LL_SPI_CRC_21BIT
+ * @arg @ref LL_SPI_CRC_22BIT
+ * @arg @ref LL_SPI_CRC_23BIT
+ * @arg @ref LL_SPI_CRC_24BIT
+ * @arg @ref LL_SPI_CRC_25BIT
+ * @arg @ref LL_SPI_CRC_26BIT
+ * @arg @ref LL_SPI_CRC_27BIT
+ * @arg @ref LL_SPI_CRC_28BIT
+ * @arg @ref LL_SPI_CRC_29BIT
+ * @arg @ref LL_SPI_CRC_30BIT
+ * @arg @ref LL_SPI_CRC_31BIT
+ * @arg @ref LL_SPI_CRC_32BIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
+{
+ MODIFY_REG(SPIx->CFG1, SPI_CFG1_CRCSIZE, CRCLength);
+}
+
+/**
+ * @brief Get CRC Length
+ * @rmtoll CFG1 CRCSIZE LL_SPI_GetCRCWidth
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_CRC_4BIT
+ * @arg @ref LL_SPI_CRC_5BIT
+ * @arg @ref LL_SPI_CRC_6BIT
+ * @arg @ref LL_SPI_CRC_7BIT
+ * @arg @ref LL_SPI_CRC_8BIT
+ * @arg @ref LL_SPI_CRC_9BIT
+ * @arg @ref LL_SPI_CRC_10BIT
+ * @arg @ref LL_SPI_CRC_11BIT
+ * @arg @ref LL_SPI_CRC_12BIT
+ * @arg @ref LL_SPI_CRC_13BIT
+ * @arg @ref LL_SPI_CRC_14BIT
+ * @arg @ref LL_SPI_CRC_15BIT
+ * @arg @ref LL_SPI_CRC_16BIT
+ * @arg @ref LL_SPI_CRC_17BIT
+ * @arg @ref LL_SPI_CRC_18BIT
+ * @arg @ref LL_SPI_CRC_19BIT
+ * @arg @ref LL_SPI_CRC_20BIT
+ * @arg @ref LL_SPI_CRC_21BIT
+ * @arg @ref LL_SPI_CRC_22BIT
+ * @arg @ref LL_SPI_CRC_23BIT
+ * @arg @ref LL_SPI_CRC_24BIT
+ * @arg @ref LL_SPI_CRC_25BIT
+ * @arg @ref LL_SPI_CRC_26BIT
+ * @arg @ref LL_SPI_CRC_27BIT
+ * @arg @ref LL_SPI_CRC_28BIT
+ * @arg @ref LL_SPI_CRC_29BIT
+ * @arg @ref LL_SPI_CRC_30BIT
+ * @arg @ref LL_SPI_CRC_31BIT
+ * @arg @ref LL_SPI_CRC_32BIT
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_CRCSIZE));
+}
+
+/**
+ * @brief Set NSS Mode
+ * @note This configuration can not be changed when SPI is enabled.
+ * This bit is not used in SPI TI mode.
+ * @rmtoll CFG2 SSM LL_SPI_SetNSSMode\n
+ * CFG2 SSOE LL_SPI_SetNSSMode
+ * @param SPIx SPI Instance
+ * @param NSS This parameter can be one of the following values:
+ * @arg @ref LL_SPI_NSS_SOFT
+ * @arg @ref LL_SPI_NSS_HARD_INPUT
+ * @arg @ref LL_SPI_NSS_HARD_OUTPUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
+{
+ MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE, NSS);
+}
+
+/**
+ * @brief Set NSS Mode
+ * @rmtoll CFG2 SSM LL_SPI_GetNSSMode\n
+ * CFG2 SSOE LL_SPI_GetNSSMode
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_NSS_SOFT
+ * @arg @ref LL_SPI_NSS_HARD_INPUT
+ * @arg @ref LL_SPI_NSS_HARD_OUTPUT
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE));
+}
+
+/**
+ * @brief Enable NSS pulse mgt
+ * @note This configuration can not be changed when SPI is enabled.
+ * This bit is not used in SPI TI mode.
+ * @rmtoll CFG2 SSOM LL_SPI_EnableNSSPulseMgt
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CFG2, SPI_CFG2_SSOM);
+}
+
+/**
+ * @brief Disable NSS pulse mgt
+ * @note This configuration can not be changed when SPI is enabled.
+ * This bit is not used in SPI TI mode.
+ * @rmtoll CFG2 SSOM LL_SPI_DisableNSSPulseMgt
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CFG2, SPI_CFG2_SSOM);
+}
+
+/**
+ * @brief Check if NSS pulse is enabled
+ * @rmtoll CFG2 SSOM LL_SPI_IsEnabledNSSPulse
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0)
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->CFG2, SPI_CFG2_SSOM) == SPI_CFG2_SSOM) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Check if there is enough data in FIFO to read a full packet
+ * @rmtoll SR RXP LL_SPI_IsActiveFlag_RXP
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0)
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXP(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->SR, SPI_SR_RXP) == (SPI_SR_RXP)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if there is enough space in FIFO to hold a full packet
+ * @rmtoll SR TXP LL_SPI_IsActiveFlag_TXP
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0)
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXP(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->SR, SPI_SR_TXP) == (SPI_SR_TXP)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if there enough space in FIFO to hold a full packet, AND enough data to read a full packet
+ * @rmtoll SR DXP LL_SPI_IsActiveFlag_DXP
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0)
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_DXP(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->SR, SPI_SR_DXP) == (SPI_SR_DXP)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check that end of transfer event occurred
+ * @rmtoll SR EOT LL_SPI_IsActiveFlag_EOT
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_EOT(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->SR, SPI_SR_EOT) == (SPI_SR_EOT)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check that all required data has been filled in the fifo according to transfer size
+ * @rmtoll SR TXTF LL_SPI_IsActiveFlag_TXTF
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXTF(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->SR, SPI_SR_TXTF) == (SPI_SR_TXTF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Underrun error flag
+ * @rmtoll SR UDR LL_SPI_IsActiveFlag_UDR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get CRC error flag
+ * @rmtoll SR CRCE LL_SPI_IsActiveFlag_CRCERR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->SR, SPI_SR_CRCE) == (SPI_SR_CRCE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Mode fault error flag
+ * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Overrun error flag
+ * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get TI Frame format error flag
+ * @rmtoll SR TIFRE LL_SPI_IsActiveFlag_FRE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->SR, SPI_SR_TIFRE) == (SPI_SR_TIFRE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if a suspend operation is done
+ * @rmtoll SR SUSP LL_SPI_IsActiveFlag_SUSP
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0)
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_SUSP(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->SR, SPI_SR_SUSP) == (SPI_SR_SUSP)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if last TxFIFO or CRC frame transmission is completed
+ * @rmtoll SR TXC LL_SPI_IsActiveFlag_TXC
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXC(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->SR, SPI_SR_TXC) == (SPI_SR_TXC)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if at least one 32-bit data is available in RxFIFO
+ * @rmtoll SR RXWNE LL_SPI_IsActiveFlag_RXWNE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0)
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXWNE(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->SR, SPI_SR_RXWNE) == (SPI_SR_RXWNE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get number of data framed remaining in current TSIZE
+ * @rmtoll SR CTSIZE LL_SPI_GetRemainingDataFrames
+ * @param SPIx SPI Instance
+ * @retval 0..0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetRemainingDataFrames(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_CTSIZE) >> SPI_SR_CTSIZE_Pos);
+}
+
+/**
+ * @brief Get RxFIFO packing Level
+ * @rmtoll SR RXPLVL LL_SPI_GetRxFIFOPackingLevel
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_RX_FIFO_0PACKET
+ * @arg @ref LL_SPI_RX_FIFO_1PACKET
+ * @arg @ref LL_SPI_RX_FIFO_2PACKET
+ * @arg @ref LL_SPI_RX_FIFO_3PACKET
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOPackingLevel(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_RXPLVL));
+}
+
+/**
+ * @brief Clear End Of Transfer flag
+ * @rmtoll IFCR EOTC LL_SPI_ClearFlag_EOT
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_ClearFlag_EOT(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->IFCR, SPI_IFCR_EOTC);
+}
+
+/**
+ * @brief Clear TXTF flag
+ * @rmtoll IFCR TXTFC LL_SPI_ClearFlag_TXTF
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_ClearFlag_TXTF(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->IFCR, SPI_IFCR_TXTFC);
+}
+
+/**
+ * @brief Clear Underrun error flag
+ * @rmtoll IFCR UDRC LL_SPI_ClearFlag_UDR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_ClearFlag_UDR(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->IFCR, SPI_IFCR_UDRC);
+}
+
+/**
+ * @brief Clear Overrun error flag
+ * @rmtoll IFCR OVRC LL_SPI_ClearFlag_OVR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->IFCR, SPI_IFCR_OVRC);
+}
+
+/**
+ * @brief Clear CRC error flag
+ * @rmtoll IFCR CRCEC LL_SPI_ClearFlag_CRCERR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->IFCR, SPI_IFCR_CRCEC);
+}
+
+/**
+ * @brief Clear Mode fault error flag
+ * @rmtoll IFCR MODFC LL_SPI_ClearFlag_MODF
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->IFCR, SPI_IFCR_MODFC);
+}
+
+/**
+ * @brief Clear Frame format error flag
+ * @rmtoll IFCR TIFREC LL_SPI_ClearFlag_FRE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->IFCR, SPI_IFCR_TIFREC);
+}
+
+/**
+ * @brief Clear SUSP flag
+ * @rmtoll IFCR SUSPC LL_SPI_ClearFlag_SUSP
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_ClearFlag_SUSP(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->IFCR, SPI_IFCR_SUSPC);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable Rx Packet available IT
+ * @rmtoll IER RXPIE LL_SPI_EnableIT_RXP
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableIT_RXP(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->IER, SPI_IER_RXPIE);
+}
+
+/**
+ * @brief Enable Tx Packet space available IT
+ * @rmtoll IER TXPIE LL_SPI_EnableIT_TXP
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableIT_TXP(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->IER, SPI_IER_TXPIE);
+}
+
+/**
+ * @brief Enable Duplex Packet available IT
+ * @rmtoll IER DXPIE LL_SPI_EnableIT_DXP
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableIT_DXP(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->IER, SPI_IER_DXPIE);
+}
+
+/**
+ * @brief Enable End Of Transfer IT
+ * @rmtoll IER EOTIE LL_SPI_EnableIT_EOT
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableIT_EOT(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->IER, SPI_IER_EOTIE);
+}
+
+/**
+ * @brief Enable TXTF IT
+ * @rmtoll IER TXTFIE LL_SPI_EnableIT_TXTF
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableIT_TXTF(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->IER, SPI_IER_TXTFIE);
+}
+
+/**
+ * @brief Enable Underrun IT
+ * @rmtoll IER UDRIE LL_SPI_EnableIT_UDR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableIT_UDR(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->IER, SPI_IER_UDRIE);
+}
+
+/**
+ * @brief Enable Overrun IT
+ * @rmtoll IER OVRIE LL_SPI_EnableIT_OVR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableIT_OVR(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->IER, SPI_IER_OVRIE);
+}
+
+/**
+ * @brief Enable CRC Error IT
+ * @rmtoll IER CRCEIE LL_SPI_EnableIT_CRCERR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableIT_CRCERR(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->IER, SPI_IER_CRCEIE);
+}
+
+/**
+ * @brief Enable TI Frame Format Error IT
+ * @rmtoll IER TIFREIE LL_SPI_EnableIT_FRE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableIT_FRE(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->IER, SPI_IER_TIFREIE);
+}
+
+/**
+ * @brief Enable MODF IT
+ * @rmtoll IER MODFIE LL_SPI_EnableIT_MODF
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableIT_MODF(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->IER, SPI_IER_MODFIE);
+}
+
+/**
+ * @brief Disable Rx Packet available IT
+ * @rmtoll IER RXPIE LL_SPI_DisableIT_RXP
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableIT_RXP(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->IER, SPI_IER_RXPIE);
+}
+
+/**
+ * @brief Disable Tx Packet space available IT
+ * @rmtoll IER TXPIE LL_SPI_DisableIT_TXP
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableIT_TXP(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->IER, SPI_IER_TXPIE);
+}
+
+/**
+ * @brief Disable Duplex Packet available IT
+ * @rmtoll IER DXPIE LL_SPI_DisableIT_DXP
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableIT_DXP(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->IER, SPI_IER_DXPIE);
+}
+
+/**
+ * @brief Disable End Of Transfer IT
+ * @rmtoll IER EOTIE LL_SPI_DisableIT_EOT
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableIT_EOT(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->IER, SPI_IER_EOTIE);
+}
+
+/**
+ * @brief Disable TXTF IT
+ * @rmtoll IER TXTFIE LL_SPI_DisableIT_TXTF
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableIT_TXTF(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->IER, SPI_IER_TXTFIE);
+}
+
+/**
+ * @brief Disable Underrun IT
+ * @rmtoll IER UDRIE LL_SPI_DisableIT_UDR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableIT_UDR(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->IER, SPI_IER_UDRIE);
+}
+
+/**
+ * @brief Disable Overrun IT
+ * @rmtoll IER OVRIE LL_SPI_DisableIT_OVR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableIT_OVR(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->IER, SPI_IER_OVRIE);
+}
+
+/**
+ * @brief Disable CRC Error IT
+ * @rmtoll IER CRCEIE LL_SPI_DisableIT_CRCERR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableIT_CRCERR(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->IER, SPI_IER_CRCEIE);
+}
+
+/**
+ * @brief Disable TI Frame Format Error IT
+ * @rmtoll IER TIFREIE LL_SPI_DisableIT_FRE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableIT_FRE(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->IER, SPI_IER_TIFREIE);
+}
+
+/**
+ * @brief Disable MODF IT
+ * @rmtoll IER MODFIE LL_SPI_DisableIT_MODF
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableIT_MODF(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->IER, SPI_IER_MODFIE);
+}
+
+/**
+ * @brief Check if Rx Packet available IT is enabled
+ * @rmtoll IER RXPIE LL_SPI_IsEnabledIT_RXP
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0)
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXP(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->IER, SPI_IER_RXPIE) == (SPI_IER_RXPIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Tx Packet space available IT is enabled
+ * @rmtoll IER TXPIE LL_SPI_IsEnabledIT_TXP
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0)
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXP(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->IER, SPI_IER_TXPIE) == (SPI_IER_TXPIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Duplex Packet available IT is enabled
+ * @rmtoll IER DXPIE LL_SPI_IsEnabledIT_DXP
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0)
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_DXP(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->IER, SPI_IER_DXPIE) == (SPI_IER_DXPIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if End Of Transfer IT is enabled
+ * @rmtoll IER EOTIE LL_SPI_IsEnabledIT_EOT
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0)
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_EOT(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->IER, SPI_IER_EOTIE) == (SPI_IER_EOTIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if TXTF IT is enabled
+ * @rmtoll IER TXTFIE LL_SPI_IsEnabledIT_TXTF
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0)
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXTF(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->IER, SPI_IER_TXTFIE) == (SPI_IER_TXTFIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Underrun IT is enabled
+ * @rmtoll IER UDRIE LL_SPI_IsEnabledIT_UDR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0)
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_UDR(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->IER, SPI_IER_UDRIE) == (SPI_IER_UDRIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Overrun IT is enabled
+ * @rmtoll IER OVRIE LL_SPI_IsEnabledIT_OVR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0)
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_OVR(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->IER, SPI_IER_OVRIE) == (SPI_IER_OVRIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if CRC Error IT is enabled
+ * @rmtoll IER CRCEIE LL_SPI_IsEnabledIT_CRCERR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0)
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_CRCERR(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->IER, SPI_IER_CRCEIE) == (SPI_IER_CRCEIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if TI Frame Format Error IT is enabled
+ * @rmtoll IER TIFREIE LL_SPI_IsEnabledIT_FRE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0)
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_FRE(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->IER, SPI_IER_TIFREIE) == (SPI_IER_TIFREIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if MODF IT is enabled
+ * @rmtoll IER MODFIE LL_SPI_IsEnabledIT_MODF
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0)
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_MODF(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->IER, SPI_IER_MODFIE) == (SPI_IER_MODFIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_DMA_Management DMA Management
+ * @{
+ */
+
+/**
+ * @brief Enable DMA Rx
+ * @rmtoll CFG1 RXDMAEN LL_SPI_EnableDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN);
+}
+
+/**
+ * @brief Disable DMA Rx
+ * @rmtoll CFG1 RXDMAEN LL_SPI_DisableDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN);
+}
+
+/**
+ * @brief Check if DMA Rx is enabled
+ * @rmtoll CFG1 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0)
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN) == (SPI_CFG1_RXDMAEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable DMA Tx
+ * @rmtoll CFG1 TXDMAEN LL_SPI_EnableDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN);
+}
+
+/**
+ * @brief Disable DMA Tx
+ * @rmtoll CFG1 TXDMAEN LL_SPI_DisableDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN);
+}
+
+/**
+ * @brief Check if DMA Tx is enabled
+ * @rmtoll CFG1 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0)
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN) == (SPI_CFG1_TXDMAEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_DATA_Management DATA_Management
+ * @{
+ */
+
+/**
+ * @brief Read Data Register
+ * @rmtoll RXDR . LL_SPI_ReceiveData8
+ * @param SPIx SPI Instance
+ * @retval 0..0xFF
+ */
+__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
+{
+ return (*((__IO uint8_t *)&SPIx->RXDR));
+}
+
+/**
+ * @brief Read Data Register
+ * @rmtoll RXDR . LL_SPI_ReceiveData16
+ * @param SPIx SPI Instance
+ * @retval 0..0xFFFF
+ */
+__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
+{
+ return (uint16_t)(READ_REG(SPIx->RXDR));
+}
+
+/**
+ * @brief Read Data Register
+ * @rmtoll RXDR . LL_SPI_ReceiveData32
+ * @param SPIx SPI Instance
+ * @retval 0..0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_SPI_ReceiveData32(SPI_TypeDef *SPIx)
+{
+ return (*((__IO uint32_t *)&SPIx->RXDR));
+}
+
+/**
+ * @brief Write Data Register
+ * @rmtoll TXDR . LL_SPI_TransmitData8
+ * @param SPIx SPI Instance
+ * @param TxData 0..0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
+{
+ *((__IO uint8_t *)&SPIx->TXDR) = TxData;
+}
+
+/**
+ * @brief Write Data Register
+ * @rmtoll TXDR . LL_SPI_TransmitData16
+ * @param SPIx SPI Instance
+ * @param TxData 0..0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
+{
+#if defined (__GNUC__)
+ __IO uint16_t *spitxdr = ((__IO uint16_t *)&SPIx->TXDR);
+ *spitxdr = TxData;
+#else
+ SPIx->TXDR = TxData;
+#endif /* __GNUC__ */
+}
+
+/**
+ * @brief Write Data Register
+ * @rmtoll TXDR . LL_SPI_TransmitData32
+ * @param SPIx SPI Instance
+ * @param TxData 0..0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData)
+{
+ *((__IO uint32_t *)&SPIx->TXDR) = TxData;
+}
+
+/**
+ * @brief Set polynomial for CRC calcul
+ * @rmtoll CRCPOLY CRCPOLY LL_SPI_SetCRCPolynomial
+ * @param SPIx SPI Instance
+ * @param CRCPoly 0..0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
+{
+ WRITE_REG(SPIx->CRCPOLY, CRCPoly);
+}
+
+/**
+ * @brief Get polynomial for CRC calcul
+ * @rmtoll CRCPOLY CRCPOLY LL_SPI_GetCRCPolynomial
+ * @param SPIx SPI Instance
+ * @retval 0..0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_REG(SPIx->CRCPOLY));
+}
+
+/**
+ * @brief Set the underrun pattern
+ * @rmtoll UDRDR UDRDR LL_SPI_SetUDRPattern
+ * @param SPIx SPI Instance
+ * @param Pattern 0..0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetUDRPattern(SPI_TypeDef *SPIx, uint32_t Pattern)
+{
+ WRITE_REG(SPIx->UDRDR, Pattern);
+}
+
+/**
+ * @brief Get the underrun pattern
+ * @rmtoll UDRDR UDRDR LL_SPI_GetUDRPattern
+ * @param SPIx SPI Instance
+ * @retval 0..0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetUDRPattern(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_REG(SPIx->UDRDR));
+}
+
+/**
+ * @brief Get Rx CRC
+ * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
+ * @param SPIx SPI Instance
+ * @retval 0..0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_REG(SPIx->RXCRC));
+}
+
+/**
+ * @brief Get Tx CRC
+ * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
+ * @param SPIx SPI Instance
+ * @retval 0..0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_REG(SPIx->TXCRC));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_AutonomousMode Configuration functions related to Autonomous mode feature
+ * @{
+ */
+
+/**
+ * @brief Enable Selected Trigger
+ * @rmtoll AUTOCR TRIGEN LL_SPI_Enable_SelectedTrigger
+ * @param SPIx SPI Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_Enable_SelectedTrigger(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGEN);
+}
+
+/**
+ * @brief Disable Selected Trigger
+ * @rmtoll AUTOCR TRIGEN LL_SPI_Disable_SelectedTrigger
+ * @param SPIx SPI Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_Disable_SelectedTrigger(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGEN);
+}
+
+/**
+ * @brief Indicate if selected Trigger is disabled or enabled
+ * @rmtoll AUTOCR TRIGEN LL_SPI_IsEnabled_SelectedTrigger
+ * @param SPIx SPI Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabled_SelectedTrigger(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGEN) == (SPI_AUTOCR_TRIGEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set the trigger polarity
+ * @rmtoll AUTOCR TRIGPOL LL_SPI_SetTriggerPolarity
+ * @param SPIx SPI Instance.
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_SPI_TRIG_POLARITY_RISING
+ * @arg @ref LL_SPI_TRIG_POLARITY_FALLING
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetTriggerPolarity(SPI_TypeDef *SPIx, uint32_t Polarity)
+{
+ MODIFY_REG(SPIx->AUTOCR, SPI_AUTOCR_TRIGPOL, Polarity);
+}
+
+/**
+ * @brief Get the trigger polarity
+ * @rmtoll AUTOCR TRIGPOL LL_SPI_GetTriggerPolarity
+ * @param SPIx SPI Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_TRIG_POLARITY_RISING
+ * @arg @ref LL_SPI_TRIG_POLARITY_FALLING
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetTriggerPolarity(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGPOL));
+}
+
+/**
+ * @brief Set the selected trigger
+ * @rmtoll AUTOCR TRIGSEL LL_SPI_SetSelectedTrigger
+ * @param SPIx SPI Instance.
+ * @param Trigger This parameter can be one of the following values:
+ * @arg @ref LL_SPI_GRP1_GPDMA_CH0_TCF_TRG
+ * @arg @ref LL_SPI_GRP1_GPDMA_CH1_TCF_TRG
+ * @arg @ref LL_SPI_GRP1_GPDMA_CH2_TCF_TRG
+ * @arg @ref LL_SPI_GRP1_GPDMA_CH3_TCF_TRG
+ * @arg @ref LL_SPI_GRP1_EXTI4_TRG
+ * @arg @ref LL_SPI_GRP1_EXTI9_TRG
+ * @arg @ref LL_SPI_GRP1_LPTIM1_CH1_TRG
+ * @arg @ref LL_SPI_GRP1_LPTIM2_CH1_TRG
+ * @arg @ref LL_SPI_GRP1_COMP1_TRG
+ * @arg @ref LL_SPI_GRP1_COMP2_TRG
+ * @arg @ref LL_SPI_GRP1_RTC_ALRA_TRG
+ * @arg @ref LL_SPI_GRP1_RTC_WUT_TRG
+ * @arg @ref LL_SPI_GRP2_LPDMA_CH0_TCF_TRG
+ * @arg @ref LL_SPI_GRP2_LPDMA_CH1_TCF_TRG
+ * @arg @ref LL_SPI_GRP2_LPDMA_CH2_TCF_TRG
+ * @arg @ref LL_SPI_GRP2_LPDMA_CH3_TCF_TRG
+ * @arg @ref LL_SPI_GRP2_EXTI4_TRG
+ * @arg @ref LL_SPI_GRP2_EXTI8_TRG
+ * @arg @ref LL_SPI_GRP2_LPTIM1_CH1_TRG
+ * @arg @ref LL_SPI_GRP2_LPTIM3_CH1_TRG
+ * @arg @ref LL_SPI_GRP2_COMP1_TRG
+ * @arg @ref LL_SPI_GRP2_COMP2_TRG
+ * @arg @ref LL_SPI_GRP2_RTC_ALRA_TRG
+ * @arg @ref LL_SPI_GRP2_RTC_WUT_TRG
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetSelectedTrigger(SPI_TypeDef *SPIx, uint32_t Trigger)
+{
+ MODIFY_REG(SPIx->AUTOCR, SPI_AUTOCR_TRIGSEL, (Trigger & SPI_AUTOCR_TRIGSEL_Msk));
+}
+
+/**
+ * @brief Get the selected trigger
+ * @rmtoll AUTOCR TRIGSEL LL_SPI_GetSelectedTrigger
+ * @param SPIx SPI Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_GRP1_GPDMA_CH0_TCF_TRG
+ * @arg @ref LL_SPI_GRP1_GPDMA_CH1_TCF_TRG
+ * @arg @ref LL_SPI_GRP1_GPDMA_CH2_TCF_TRG
+ * @arg @ref LL_SPI_GRP1_GPDMA_CH3_TCF_TRG
+ * @arg @ref LL_SPI_GRP1_EXTI4_TRG
+ * @arg @ref LL_SPI_GRP1_EXTI9_TRG
+ * @arg @ref LL_SPI_GRP1_LPTIM1_CH1_TRG
+ * @arg @ref LL_SPI_GRP1_LPTIM2_CH1_TRG
+ * @arg @ref LL_SPI_GRP1_COMP1_TRG
+ * @arg @ref LL_SPI_GRP1_COMP2_TRG
+ * @arg @ref LL_SPI_GRP1_RTC_ALRA_TRG
+ * @arg @ref LL_SPI_GRP1_RTC_WUT_TRG
+ * @arg @ref LL_SPI_GRP2_LPDMA_CH0_TCF_TRG
+ * @arg @ref LL_SPI_GRP2_LPDMA_CH1_TCF_TRG
+ * @arg @ref LL_SPI_GRP2_LPDMA_CH2_TCF_TRG
+ * @arg @ref LL_SPI_GRP2_LPDMA_CH3_TCF_TRG
+ * @arg @ref LL_SPI_GRP2_EXTI4_TRG
+ * @arg @ref LL_SPI_GRP2_EXTI8_TRG
+ * @arg @ref LL_SPI_GRP2_LPTIM1_CH1_TRG
+ * @arg @ref LL_SPI_GRP2_LPTIM3_CH1_TRG
+ * @arg @ref LL_SPI_GRP2_COMP1_TRG
+ * @arg @ref LL_SPI_GRP2_COMP2_TRG
+ * @arg @ref LL_SPI_GRP2_RTC_ALRA_TRG
+ * @arg @ref LL_SPI_GRP2_RTC_WUT_TRG
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetSelectedTrigger(SPI_TypeDef *SPIx)
+{
+ if (IS_LL_SPI_GRP2_INSTANCE(SPIx))
+ {
+ return (uint32_t)((READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGSEL) | LL_SPI_TRIG_GRP2));
+ }
+ else
+ {
+ return (uint32_t)((READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGSEL) | LL_SPI_TRIG_GRP1));
+ }
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
+ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
+void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+/**
+ * @}
+ */
+
+
+#endif /* defined(SPI1) || defined(SPI2) || defined(SPI3) */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_LL_SPI_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_system.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_system.h
new file mode 100644
index 00000000..724c597c
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_system.h
@@ -0,0 +1,1496 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_system.h
+ * @author MCD Application Team
+ * @brief Header file of SYSTEM LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The LL SYSTEM driver contains a set of generic APIs that can be
+ used by user:
+ (+) Some of the FLASH features need to be handled in the SYSTEM file.
+ (+) Access to DBGCMU registers
+ (+) Access to SYSCFG registers
+ (+) Access to VREFBUF registers
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_LL_SYSTEM_H
+#define STM32U5xx_LL_SYSTEM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx.h"
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF)
+
+/** @defgroup SYSTEM_LL SYSTEM
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
+ * @{
+ */
+
+/**
+ * @brief Power-down in Run mode Flash key
+ */
+#define LL_FLASH_PDKEY1_1 0x04152637U /*!< Flash Bank1 power down key1 */
+#define LL_FLASH_PDKEY1_2 0xFAFBFCFDU /*!< Flash Bank1 power down key2: used with FLASH_PDKEY1
+ to unlock the RUN_PD bit in FLASH_ACR */
+
+#define LL_FLASH_PDKEY2_1 0x40516273U /*!< Flash Bank2 power down key1 */
+#define LL_FLASH_PDKEY2_2 0xAFBFCFDFU /*!< Flash Bank2 power down key2: used with FLASH_PDKEY2_1
+ to unlock the RUN_PD bit in FLASH_ACR */
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_CS1 SYSCFG Vdd compensation cell Code selection
+ * @{
+ */
+#define LL_SYSCFG_VDD_CELL_CODE 0U /*VDD I/Os code from the cell
+ (available in the SYSCFG_CCVR)*/
+#define LL_SYSCFG_VDD_REGISTER_CODE SYSCFG_CCCSR_CS1 /*VDD I/Os code from the SYSCFG compensation
+ cell code register (SYSCFG_CCCR)*/
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_CS2 SYSCFG VddIO2 compensation cell Code selection
+ * @{
+ */
+#define LL_SYSCFG_VDDIO2_CELL_CODE 0U /*VDDIO2 I/Os code from the cell
+ (available in the SYSCFG_CCVR)*/
+#define LL_SYSCFG_VDDIO2_REGISTER_CODE SYSCFG_CCCSR_CS2 /*VDDIO2 I/Os code from the SYSCFG compensation
+ cell code register (SYSCFG_CCCR)*/
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_ERASE_MEMORIES_STATUS SYSCFG MEMORIES ERASE STATUS
+ * @{
+ */
+#define LL_SYSCFG_MEMORIES_ERASE_ON_GOING 0U /*Memory erase on going*/
+#define LL_SYSCFG_MEMORIES_ERASE_ENDED SYSCFG_MESR_MCLR /*Memory erase done */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
+ * @{
+ */
+
+/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
+ * @{
+ */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
+ * @{
+ */
+#define LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal
+ with Break Input of TIM1/8/15/16/17 */
+#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection
+ with TIM1/8/15/16/17 Break Input and also the PVDE
+ and PLS bits of the Power Control Interface */
+#define LL_SYSCFG_TIMBREAK_SRAM_ECC_LOCK SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM ECC double error signal
+ with Break Input of TIM1/8/15/16/17 */
+#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM33
+ with Break Input of TIM1/15/16/17 */
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_SECURE_ATTRIBUTES Secure attributes
+ * @note Only available when system implements security (TZEN=1)
+ * @{
+ */
+#define LL_SYSCFG_CLOCK_SEC SYSCFG_SECCFGR_SYSCFGSEC /*!< SYSCFG clock configuration secure-only access */
+#define LL_SYSCFG_CLOCK_NSEC 0U /*!< SYSCFG clock configuration secure/non-secure access */
+#define LL_SYSCFG_CLASSB_SEC SYSCFG_SECCFGR_CLASSBSEC /*!< Class B configuration secure-only access */
+#define LL_SYSCFG_CLASSB_NSEC 0U /*!< Class B configuration secure/non-secure access */
+#define LL_SYSCFG_FPU_SEC SYSCFG_SECCFGR_FPUSEC /*!< FPU configuration secure-only access */
+#define LL_SYSCFG_FPU_NSEC 0U /*!< FPU configuration secure/non-secure access */
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
+ * @{
+ */
+#define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
+#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
+ * @{
+ */
+#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP /*!< The counter clock of TIM2 is stopped when the core is halted*/
+#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP /*!< The counter clock of TIM3 is stopped when the core is halted*/
+#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP /*!< The counter clock of TIM4 is stopped when the core is halted*/
+#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP /*!< The counter clock of TIM5 is stopped when the core is halted*/
+#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP /*!< The counter clock of TIM6 is stopped when the core is halted*/
+#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP /*!< The counter clock of TIM7 is stopped when the core is halted*/
+#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP /*!< The window watchdog counter clock is stopped when the core is halted*/
+#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP /*!< The independent watchdog counter clock is stopped when the core is halted*/
+#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP /*!< The I2C1 SMBus timeout is frozen*/
+#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP /*!< The I2C2 SMBus timeout is frozen*/
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
+ * @{
+ */
+#define LL_DBGMCU_APB1_GRP2_I2C4_STOP DBGMCU_APB1FZR2_DBG_I2C4_STOP /*!< The I2C4 SMBus timeout is frozen*/
+#define LL_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted*/
+#define LL_DBGMCU_APB1_GRP2_FDCAN_STOP DBGMCU_APB1FZR2_DBG_FDCAN_STOP /*!< The counter clock of FDCAN is stopped when the core is halted*/
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
+ * @{
+ */
+#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP /*!< The counter clock of TIM1 is stopped when the core is halted*/
+#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZR_DBG_TIM8_STOP /*!< The counter clock of TIM8 is stopped when the core is halted*/
+#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZR_DBG_TIM15_STOP /*!< The counter clock of TIM15 is stopped when the core is halted*/
+#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP /*!< The counter clock of TIM16 is stopped when the core is halted*/
+#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP /*!< The counter clock of TIM17 is stopped when the core is halted*/
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_APB3_GRP1_STOP_IP DBGMCU APB3 GRP1 STOP IP
+ * @{
+ */
+#define LL_DBGMCU_APB3_GRP1_I2C3_STOP DBGMCU_APB3FZR_DBG_I2C3_STOP /*!< The counter clock of I2C3 is stopped when the core is halted*/
+#define LL_DBGMCU_APB3_GRP1_LPTIM1_STOP DBGMCU_APB3FZR_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted*/
+#define LL_DBGMCU_APB3_GRP1_LPTIM3_STOP DBGMCU_APB3FZR_DBG_LPTIM3_STOP /*!< The counter clock of LPTIM3 is stopped when the core is halted*/
+#define LL_DBGMCU_APB3_GRP1_LPTIM4_STOP DBGMCU_APB3FZR_DBG_LPTIM4_STOP /*!< The counter clock of LPTIM4 is stopped when the core is halted*/
+#define LL_DBGMCU_APB3_GRP1_RTC_STOP DBGMCU_APB3FZR_DBG_RTC_STOP /*!< The counter clock of RTC is stopped when the core is halted*/
+/**
+ * @}
+ */
+
+
+#if defined(VREFBUF)
+/** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE
+ * @{
+ */
+#define LL_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */
+#define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREF_OUT2) */
+#define LL_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 0 (VREF_OUT3) */
+#define LL_VREFBUF_VOLTAGE_SCALE3 VREFBUF_CSR_VRS_2 /*!< Voltage reference scale 1 (VREF_OUT4) */
+/**
+ * @}
+ */
+#endif /* VREFBUF */
+
+/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
+ * @{
+ */
+#define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH zero wait state */
+#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH one wait state */
+#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH two wait states */
+#define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH three wait states */
+#define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH four wait states */
+#define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait states */
+#define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */
+#define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven wait states */
+#define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight wait states */
+#define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH nine wait states */
+#define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH ten wait states */
+#define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH eleven wait states */
+#define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH twelve wait states */
+#define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH thirteen wait states */
+#define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH fourteen wait states */
+#define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH fifteen wait states */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
+ * @{
+ */
+
+/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
+ * @{
+ */
+
+/**
+ * @brief Enable I/O analog switch voltage booster.
+ * @note When voltage booster is enabled, I/O analog switches are supplied
+ * by a dedicated voltage booster, from VDD power domain. This is
+ * the recommended configuration with low VDDA voltage operation.
+ * @note The I/O analog switch voltage booster is relevant for peripherals
+ * using I/O in analog input: ADC, COMP, OPAMP.
+ * However, COMP and OPAMP inputs have a high impedance and
+ * voltage booster do not impact performance significantly.
+ * Therefore, the voltage booster is mainly intended for
+ * usage with ADC.
+ * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_EnableAnalogBooster
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
+{
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
+}
+
+/**
+ * @brief Disable I/O analog switch voltage booster.
+ * @note When voltage booster is enabled, I/O analog switches are supplied
+ * by a dedicated voltage booster, from VDD power domain. This is
+ * the recommended configuration with low VDDA voltage operation.
+ * @note The I/O analog switch voltage booster is relevant for peripherals
+ * using I/O in analog input: ADC, COMP, OPAMP.
+ * However, COMP and OPAMP inputs have a high impedance and
+ * voltage booster do not impact performance significantly.
+ * Therefore, the voltage booster is mainly intended for
+ * usage with ADC.
+ * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_DisableAnalogBooster
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
+{
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
+}
+
+/**
+ * @brief Enable the I2C fast mode plus driving capability.
+ * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n
+ * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_EnableFastModePlus
+ * @param ConfigFastModePlus This parameter can be a combination of the following values:
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
+{
+ SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
+}
+
+/**
+ * @brief Disable the I2C fast mode plus driving capability.
+ * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n
+ * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_DisableFastModePlus
+ * @param ConfigFastModePlus This parameter can be a combination of the following values:
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
+{
+ CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
+}
+
+/**
+ * @brief Enable Floating Point Unit Invalid operation Interrupt
+ * @rmtoll SYSCFG_FPUIMR FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void)
+{
+ SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_0);
+}
+
+/**
+ * @brief Enable Floating Point Unit Divide-by-zero Interrupt
+ * @rmtoll SYSCFG_FPUIMR FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void)
+{
+ SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_1);
+}
+
+/**
+ * @brief Enable Floating Point Unit Underflow Interrupt
+ * @rmtoll SYSCFG_FPUIMR FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void)
+{
+ SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_2);
+}
+
+/**
+ * @brief Enable Floating Point Unit Overflow Interrupt
+ * @rmtoll SYSCFG_FPUIMR FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void)
+{
+ SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_3);
+}
+
+/**
+ * @brief Enable Floating Point Unit Input denormal Interrupt
+ * @rmtoll SYSCFG_FPUIMR FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void)
+{
+ SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_4);
+}
+
+/**
+ * @brief Enable Floating Point Unit Inexact Interrupt
+ * @rmtoll SYSCFG_FPUIMR FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void)
+{
+ SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_5);
+}
+
+/**
+ * @brief Disable Floating Point Unit Invalid operation Interrupt
+ * @rmtoll SYSCFG_FPUIMR FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void)
+{
+ CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_0);
+}
+
+/**
+ * @brief Disable Floating Point Unit Divide-by-zero Interrupt
+ * @rmtoll SYSCFG_FPUIMR FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void)
+{
+ CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_1);
+}
+
+/**
+ * @brief Disable Floating Point Unit Underflow Interrupt
+ * @rmtoll SYSCFG_FPUIMR FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void)
+{
+ CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_2);
+}
+
+/**
+ * @brief Disable Floating Point Unit Overflow Interrupt
+ * @rmtoll SYSCFG_FPUIMR FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void)
+{
+ CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_3);
+}
+
+/**
+ * @brief Disable Floating Point Unit Input denormal Interrupt
+ * @rmtoll SYSCFG_FPUIMR FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void)
+{
+ CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_4);
+}
+
+/**
+ * @brief Disable Floating Point Unit Inexact Interrupt
+ * @rmtoll SYSCFG_FPUIMR FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void)
+{
+ CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_5);
+}
+
+/**
+ * @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
+ * @rmtoll SYSCFG_FPUIMR FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void)
+{
+ return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_0) == SYSCFG_FPUIMR_FPU_IE_0) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
+ * @rmtoll SYSCFG_FPUIMR FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void)
+{
+ return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_1) == SYSCFG_FPUIMR_FPU_IE_1) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
+ * @rmtoll SYSCFG_FPUIMR FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void)
+{
+ return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_2) == SYSCFG_FPUIMR_FPU_IE_2) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
+ * @rmtoll SYSCFG_FPUIMR FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void)
+{
+ return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_3) == SYSCFG_FPUIMR_FPU_IE_3) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
+ * @rmtoll SYSCFG_FPUIMR FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void)
+{
+ return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_4) == SYSCFG_FPUIMR_FPU_IE_4) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
+ * @rmtoll SYSCFG_FPUIMR FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)
+{
+ return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_5) == SYSCFG_FPUIMR_FPU_IE_5) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set connections to TIM1/8/15/16/17 Break inputs
+ * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs\n
+ * SYSCFG_CFGR2 SPL LL_SYSCFG_SetTIMBreakInputs\n
+ * SYSCFG_CFGR2 PVDL LL_SYSCFG_SetTIMBreakInputs\n
+ * SYSCFG_CFGR2 ECCL LL_SYSCFG_SetTIMBreakInputs
+ * @param Break This parameter can be a combination of the following values:
+ * @arg @ref LL_SYSCFG_TIMBREAK_ECC
+ * @arg @ref LL_SYSCFG_TIMBREAK_PVD
+ * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_ECC_LOCK
+ * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
+{
+ MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL, Break);
+}
+
+/**
+ * @brief Get connections to TIM1/8/15/16/17 Break inputs
+ * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs\n
+ * SYSCFG_CFGR2 SPL LL_SYSCFG_GetTIMBreakInputs\n
+ * SYSCFG_CFGR2 PVDL LL_SYSCFG_GetTIMBreakInputs\n
+ * SYSCFG_CFGR2 ECCL LL_SYSCFG_GetTIMBreakInputs
+ * @retval Returned value can be can be a combination of the following values:
+ * @arg @ref LL_SYSCFG_TIMBREAK_ECC
+ * @arg @ref LL_SYSCFG_TIMBREAK_PVD
+ * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_ECC_LOCK
+ * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL
+ | SYSCFG_CFGR2_ECCL));
+}
+
+
+
+/** @defgroup SYSTEM_LL_EF_SYSCFG_Secure_Management Secure Management
+ * @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ * @brief Configure Secure mode
+ * @note Only available from secure state when system implements security (TZEN=1)
+ * @rmtoll SECCFGR SYSCFGSEC LL_SYSCFG_ConfigSecure\n
+ * SECCFGR CLASSBSEC LL_SYSCFG_ConfigSecure\n
+ * SECCFGR FPUSEC LL_SYSCFG_ConfigSecure
+ * @param Configuration This parameter shall be the full combination
+ * of the following values:
+ * @arg @ref LL_SYSCFG_CLOCK_SEC or LL_SYSCFG_CLOCK_NSEC
+ * @arg @ref LL_SYSCFG_CLASSB_SEC or LL_SYSCFG_CLASSB_NSEC
+ * @arg @ref LL_SYSCFG_FPU_SEC or LL_SYSCFG_FPU_NSEC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_ConfigSecure(uint32_t Configuration)
+{
+ WRITE_REG(SYSCFG->SECCFGR, Configuration);
+}
+
+#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */
+
+/**
+ * @brief Get Secure mode configuration
+ * @note Only available when system implements security (TZEN=1)
+ * @rmtoll SECCFGR SYSCFGSEC LL_SYSCFG_ConfigSecure\n
+ * SECCFGR CLASSBSEC LL_SYSCFG_ConfigSecure\n
+ * SECCFGR FPUSEC LL_SYSCFG_ConfigSecure
+ * @retval Returned value is the combination of the following values:
+ * @arg @ref LL_SYSCFG_CLOCK_SEC or LL_SYSCFG_CLOCK_NSEC
+ * @arg @ref LL_SYSCFG_CLASSB_SEC or LL_SYSCFG_CLASSB_NSEC
+ * @arg @ref LL_SYSCFG_FPU_SEC or LL_SYSCFG_FPU_NSEC
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetConfigSecure(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->SECCFGR, 0xBU));
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EF_COMPENSATION SYSCFG COMPENSATION
+ * @{
+ */
+
+/**
+ * @brief Get the compensation cell value of the GPIO PMOS transistor supplied by VDD
+ * @rmtoll CCVR PCV1 LL_SYSCFG_GetPMOSVddCompensationValue
+ * @retval Returned value is the PMOS compensation cell
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddCompensationValue(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV1));
+}
+
+/**
+ * @brief Get the compensation cell value of the GPIO NMOS transistor supplied by VDD
+ * @rmtoll CCVR NCV1 LL_SYSCFG_GetNMOSVddCompensationValue
+ * @retval Returned value is the NMOS compensation cell
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddCompensationValue(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV1));
+}
+
+/**
+ * @brief Get the compensation cell value of the GPIO PMOS transistor supplied by VDDIO2
+ * @rmtoll CCVR PCV2 LL_SYSCFG_GetPMOSVddIO2CompensationValue
+ * @retval Returned value is the PMOS compensation cell
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddIO2CompensationValue(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV2));
+}
+
+/**
+ * @brief Get the compensation cell value of the GPIO NMOS transistor supplied by VDDIO2
+ * @rmtoll CCVR NCV2 LL_SYSCFG_GetNMOSVddIO2CompensationValue
+ * @retval Returned value is the NMOS compensation cell
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddIO2CompensationValue(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV2));
+}
+
+/**
+ * @brief Set the compensation cell code of the GPIO PMOS transistor supplied by VDD
+ * @rmtoll CCCR PCC1 LL_SYSCFG_SetPMOSVddCompensationCode
+ * @param PMOSCode PMOS compensation code
+ * This code is applied to the PMOS compensation cell when the CS1 bit of the
+ * SYSCFG_CMPCR is set
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetPMOSVddCompensationCode(uint32_t PMOSCode)
+{
+ MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC1, PMOSCode << SYSCFG_CCCR_PCC1_Pos);
+}
+
+/**
+ * @brief Get the compensation cell code of the GPIO PMOS transistor supplied by VDD
+ * @rmtoll CCCR PCC1 LL_SYSCFG_GetPMOSVddCompensationCode
+ * @retval Returned value is the PMOS compensation cell
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddCompensationCode(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC1));
+}
+
+/**
+ * @brief Set the compensation cell code of the GPIO PMOS transistor supplied by VDDIO2
+ * @rmtoll CCCR PCC2 LL_SYSCFG_SetPMOSVddIO2CompensationCode
+ * @param PMOSCode PMOS compensation code
+ * This code is applied to the PMOS compensation cell when the CS2 bit of the
+ * SYSCFG_CMPCR is set
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetPMOSVddIO2CompensationCode(uint32_t PMOSCode)
+{
+ MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC2, PMOSCode << SYSCFG_CCCR_PCC2_Pos);
+}
+
+
+/**
+ * @brief Get the compensation cell code of the GPIO PMOS transistor supplied by VDDIO2
+ * @rmtoll CCCR PCC2 LL_SYSCFG_GetPMOSVddIO2CompensationCode
+ * @retval Returned value is the PMOS compensation
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddIO2CompensationCode(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC2));
+}
+
+/**
+ * @brief Set the compensation cell code of the GPIO NMOS transistor supplied by VDD
+ * @rmtoll CCCR PCC2 LL_SYSCFG_SetNMOSVddCompensationCode
+ * @param NMOSCode NMOS compensation code
+ * This code is applied to the NMOS compensation cell when the CS2 bit of the
+ * SYSCFG_CMPCR is set
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetNMOSVddCompensationCode(uint32_t NMOSCode)
+{
+ MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC1, NMOSCode << SYSCFG_CCCR_NCC1_Pos);
+}
+
+/**
+ * @brief Get the compensation cell code of the GPIO NMOS transistor supplied by VDD
+ * @rmtoll CCCR NCC1 LL_SYSCFG_GetNMOSVddCompensationCode
+ * @retval Returned value is the Vdd compensation cell code for NMOS transistors
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddCompensationCode(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC1));
+}
+
+/**
+ * @brief Set the compensation cell code of the GPIO NMOS transistor supplied by VDDIO2
+ * @rmtoll CCCR NCC2 LL_SYSCFG_SetNMOSVddIO2CompensationCode
+ * @param NMOSCode NMOS compensation code
+ * This code is applied to the NMOS compensation cell when the CS2 bit of the
+ * SYSCFG_CMPCR is set
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetNMOSVddIO2CompensationCode(uint32_t NMOSCode)
+{
+ MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC2, NMOSCode << SYSCFG_CCCR_NCC2_Pos);
+}
+
+
+/**
+ * @brief Get the compensation cell code of the GPIO NMOS transistor supplied by VDDIO2
+ * @rmtoll CCCR NCC2 LL_SYSCFG_GetNMOSVddIO2CompensationCode
+ * @retval Returned value is the NMOS compensation cell code
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddIO2CompensationCode(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC2));
+}
+
+/**
+ * @brief Enable the Compensation Cell of GPIO supplied by VDD
+ * @rmtoll CCCSR EN1 LL_SYSCFG_EnableVddCompensationCell
+ * @note The vdd compensation cell can be used only when the device supply
+ * voltage ranges from 1.71 to 3.6 V
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableVddCompensationCell(void)
+{
+ SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1);
+}
+
+/**
+ * @brief Enable the Compensation Cell of GPIO supplied by VDDIO2
+ * @rmtoll CCCSR EN2 LL_SYSCFG_EnableVddIO2CompensationCell
+ * @note The Vdd I/O compensation cell can be used only when the device supply
+ * voltage ranges from 1.08 to 3.6 V
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableVddIO2CompensationCell(void)
+{
+ SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2);
+}
+
+/**
+ * @brief Disable the Compensation Cell of GPIO supplied by VDD
+ * @rmtoll CCCSR EN1 LL_SYSCFG_EnableVddCompensationCell
+ * @note The Vdd compensation cell can be used only when the device supply
+ * voltage ranges from 1.71 to 3.6 V
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableVddCompensationCell(void)
+{
+ CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1);
+}
+
+/**
+ * @brief Disable the Compensation Cell of GPIO supplied by VDDIO2
+ * @rmtoll CCCSR EN2 LL_SYSCFG_EnableVddIOCompensationCell
+ * @note The Vdd I/O compensation cell can be used only when the device supply
+ * voltage ranges from 1.08 to 3.6 V
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableVddIO2CompensationCell(void)
+{
+ CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2);
+}
+
+/**
+ * @brief Check if the Compensation Cell of GPIO supplied by VDD is enable
+ * @rmtoll CCCSR EN1 LL_SYSCFG_IsEnabled_VddCompensationCell
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabled_VddCompensationCell(void)
+{
+ return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1) == SYSCFG_CCCSR_EN1) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the Compensation Cell of GPIO supplied by VDDIO2 is enable
+ * @rmtoll CCCSR EN2 LL_SYSCFG_IsEnabled_VddIO2CompensationCell
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabled_VddIO2CompensationCell(void)
+{
+ return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2) == SYSCFG_CCCSR_EN2) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Compensation Cell ready Flag of GPIO supplied by VDD
+ * @rmtoll CCCSR RDY1 LL_SYSCFG_IsActiveFlag_VddCMPCR
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VddCMPCR(void)
+{
+ return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_RDY1) == (SYSCFG_CCCSR_RDY1)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Compensation Cell ready Flag of GPIO supplied by VDDIO2
+ * @rmtoll CCCSR RDY1 LL_SYSCFG_IsActiveFlag_VddIO2CMPCR
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VddIO2CMPCR(void)
+{
+ return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_RDY2) == (SYSCFG_CCCSR_RDY2)) ? 1UL : 0UL);
+}
+
+
+/**
+ * @brief Set the compensation cell code selection of GPIO supplied by VDD
+ * @rmtoll CCCSR CS1 LL_SYSCFG_SetVddCellCompensationCode
+ * @param CompCode: Selects the code to be applied for the Vdd compensation cell
+ * This parameter can be one of the following values:
+ * @arg LL_SYSCFG_VDD_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)
+ * @arg LL_SYSCFG_VDD_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetVddCellCompensationCode(uint32_t CompCode)
+{
+ SET_BIT(SYSCFG->CCCSR, CompCode);
+}
+
+/**
+ * @brief Set the compensation cell code selection of GPIO supplied by VDDIO2
+ * @rmtoll CCCSR CS2 LL_SYSCFG_SetVddIO2CellCompensationCode
+ * @param CompCode: Selects the code to be applied for the VddIO compensation cell
+ * This parameter can be one of the following values:
+ * @arg LL_SYSCFG_VDDIO2_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)
+ * @arg LL_SYSCFG_VDDIO2_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetVddIO2CellCompensationCode(uint32_t CompCode)
+{
+ SET_BIT(SYSCFG->CCCSR, CompCode);
+}
+
+/**
+ * @brief Get the compensation cell code selection of GPIO supplied by VDD
+ * @rmtoll CCCSR CS1 LL_SYSCFG_GetVddCellCompensationCode
+ * @retval Returned value can be one of the following values:
+ * @arg LL_SYSCFG_VDD_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR)
+ * @arg LL_SYSCFG_VDD_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR)
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetVddCellCompensationCode(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS1));
+}
+
+/**
+ * @brief Get the compensation cell code selection of GPIO supplied by VDDIO2
+ * @rmtoll CCCSR CS2 LL_SYSCFG_GetVddIOCellCompensationCode
+ * @retval Returned value can be one of the following values:
+ * @arg LL_SYSCFG_VDDIO2_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR)
+ * @arg LL_SYSCFG_VDDIO2_REGISTER_CODE: Selected Code is from the SYSCFG compensation
+ cell code register (SYSCFG_CCCR)
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetVddIO2CellCompensationCode(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS2));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
+ * @{
+ */
+
+/**
+ * @brief Return the device identifier
+ * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
+ * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF (ex: device ID is 0x6415)
+ */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
+{
+ return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
+}
+
+/**
+ * @brief Return the device revision identifier
+ * @note This field indicates the revision of the device.
+ * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
+ * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
+{
+ return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
+}
+
+/**
+ * @brief Enable the Debug Module during STOP mode
+ * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+ * @brief Disable the Debug Module during STOP mode
+ * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+ * @brief Enable the Debug Module during STANDBY mode
+ * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+ * @brief Disable the Debug Module during STANDBY mode
+ * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+
+/**
+ * @brief Enable the Debug Clock Trace
+ * @rmtoll DBGMCU_CR TRACE_CLKEN LL_DBGMCU_EnableTraceClock
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_EnableTraceClock(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_CLKEN);
+}
+
+/**
+ * @brief Disable the Debug Clock Trace
+ * @rmtoll DBGMCU_CR TRACE_CLKEN LL_DBGMCU_DisableTraceClock
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_DisableTraceClock(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_CLKEN);
+}
+
+
+/**
+ * @brief Check if clock trace is enabled or disabled.
+ * @rmtoll DBGMCU_CR_TRACE_CLKEN LL_DBGMCU_IsEnabledTraceClock
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DBGMCU_IsEnabledTraceClock(void)
+{
+ return ((READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_CLKEN) == DBGMCU_CR_TRACE_CLKEN) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set Trace pin assignment control
+ * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
+ * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
+ * @param PinAssignment This parameter can be one of the following values:
+ * @arg @ref LL_DBGMCU_TRACE_NONE
+ * @arg @ref LL_DBGMCU_TRACE_ASYNCH
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
+{
+ MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
+}
+
+/**
+ * @brief Get Trace pin assignment control
+ * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
+ * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DBGMCU_TRACE_NONE
+ * @arg @ref LL_DBGMCU_TRACE_ASYNCH
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
+ */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
+{
+ return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
+}
+
+/**
+ * @brief Freeze APB1 peripherals (group1 peripherals)
+ * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
+{
+ SET_BIT(DBGMCU->APB1FZR1, Periphs);
+}
+
+/**
+ * @brief Freeze APB1 peripherals (group2 peripherals)
+ * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
+{
+ SET_BIT(DBGMCU->APB1FZR2, Periphs);
+}
+
+/**
+ * @brief Unfreeze APB1 peripherals (group1 peripherals)
+ * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
+
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
+{
+ CLEAR_BIT(DBGMCU->APB1FZR1, Periphs);
+}
+
+/**
+ * @brief Unfreeze APB1 peripherals (group2 peripherals)
+ * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
+{
+ CLEAR_BIT(DBGMCU->APB1FZR2, Periphs);
+}
+
+/**
+ * @brief Freeze APB2 peripherals
+ * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
+{
+ SET_BIT(DBGMCU->APB2FZR, Periphs);
+}
+
+/**
+ * @brief Unfreeze APB2 peripherals
+ * @rmtoll DBGMCU_APB2FZR DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
+{
+ CLEAR_BIT(DBGMCU->APB2FZR, Periphs);
+}
+
+/**
+ * @brief Freeze APB3 peripherals
+ * @rmtoll DBGMCU_APB3FZ DBG_TIMx_STOP LL_DBGMCU_APB3_GRP1_FreezePeriph
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB3_GRP1_I2C3_STOP
+ * @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM1_STOP
+ * @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM3_STOP
+ * @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM4_STOP
+ * @arg @ref LL_DBGMCU_APB3_GRP1_RTC_STOP
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB3_GRP1_FreezePeriph(uint32_t Periphs)
+{
+ SET_BIT(DBGMCU->APB3FZR, Periphs);
+}
+
+/**
+ * @brief Unfreeze APB3 peripherals
+ * @rmtoll DBGMCU_APB3FZR DBG_TIMx_STOP LL_DBGMCU_APB3_GRP1_UnFreezePeriph
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB3_GRP1_I2C3_STOP
+ * @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM1_STOP
+ * @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM3_STOP
+ * @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM4_STOP
+ * @arg @ref LL_DBGMCU_APB3_GRP1_RTC_STOP
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB3_GRP1_UnFreezePeriph(uint32_t Periphs)
+{
+ CLEAR_BIT(DBGMCU->APB3FZR, Periphs);
+}
+
+/**
+ * @}
+ */
+
+#if defined(VREFBUF)
+/** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF
+ * @{
+ */
+
+/**
+ * @brief Enable Internal voltage reference
+ * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_VREFBUF_Enable(void)
+{
+ SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
+}
+
+/**
+ * @brief Disable Internal voltage reference
+ * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_VREFBUF_Disable(void)
+{
+ CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
+}
+
+/**
+ * @brief Enable high impedance (VREF+pin is high impedance)
+ * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_EnableHIZ
+ * @retval None
+ */
+__STATIC_INLINE void LL_VREFBUF_EnableHIZ(void)
+{
+ SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
+}
+
+/**
+ * @brief Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
+ * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_DisableHIZ
+ * @retval None
+ */
+__STATIC_INLINE void LL_VREFBUF_DisableHIZ(void)
+{
+ CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
+}
+
+/**
+ * @brief Set the Voltage reference scale
+ * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_SetVoltageScaling
+ * @param Scale This parameter can be one of the following values:
+ * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
+ * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
+ * @arg @ref LL_VREFBUF_VOLTAGE_SCALE2
+ * @arg @ref LL_VREFBUF_VOLTAGE_SCALE3
+ * @retval None
+ */
+__STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale)
+{
+ MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale);
+}
+
+/**
+ * @brief Get the Voltage reference scale
+ * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_GetVoltageScaling
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
+ * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
+ * @arg @ref LL_VREFBUF_VOLTAGE_SCALE2
+ * @arg @ref LL_VREFBUF_VOLTAGE_SCALE3
+ */
+__STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void)
+{
+ return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS));
+}
+
+/**
+ * @brief Check if Voltage reference buffer is ready
+ * @rmtoll VREFBUF_CSR VRR LL_VREFBUF_IsVREFReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void)
+{
+ return ((READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == VREFBUF_CSR_VRR) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get the trimming code for VREFBUF calibration
+ * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_GetTrimming
+ * @retval Between 0 and 0x3F
+ */
+__STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void)
+{
+ return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM));
+}
+
+/**
+ * @brief Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)
+ * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_SetTrimming
+ * @param Value Between 0 and 0x3F
+ * @retval None
+ */
+__STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value)
+{
+ WRITE_REG(VREFBUF->CCR, Value);
+}
+
+/**
+ * @}
+ */
+#endif /* VREFBUF */
+
+/** @defgroup SYSTEM_LL_EF_FLASH FLASH
+ * @{
+ */
+/**
+ * @brief Set FLASH Latency
+ * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
+ * @param Latency This parameter can be one of the following values:
+ * @arg @ref LL_FLASH_LATENCY_0
+ * @arg @ref LL_FLASH_LATENCY_1
+ * @arg @ref LL_FLASH_LATENCY_2
+ * @arg @ref LL_FLASH_LATENCY_3
+ * @arg @ref LL_FLASH_LATENCY_4
+ * @arg @ref LL_FLASH_LATENCY_5
+ * @arg @ref LL_FLASH_LATENCY_6
+ * @arg @ref LL_FLASH_LATENCY_7
+ * @arg @ref LL_FLASH_LATENCY_8
+ * @arg @ref LL_FLASH_LATENCY_9
+ * @arg @ref LL_FLASH_LATENCY_10
+ * @arg @ref LL_FLASH_LATENCY_11
+ * @arg @ref LL_FLASH_LATENCY_12
+ * @arg @ref LL_FLASH_LATENCY_13
+ * @arg @ref LL_FLASH_LATENCY_14
+ * @arg @ref LL_FLASH_LATENCY_15
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
+{
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
+}
+
+/**
+ * @brief Get FLASH Latency
+ * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_FLASH_LATENCY_0
+ * @arg @ref LL_FLASH_LATENCY_1
+ * @arg @ref LL_FLASH_LATENCY_2
+ * @arg @ref LL_FLASH_LATENCY_3
+ * @arg @ref LL_FLASH_LATENCY_4
+ * @arg @ref LL_FLASH_LATENCY_5
+ * @arg @ref LL_FLASH_LATENCY_6
+ * @arg @ref LL_FLASH_LATENCY_7
+ * @arg @ref LL_FLASH_LATENCY_8
+ * @arg @ref LL_FLASH_LATENCY_9
+ * @arg @ref LL_FLASH_LATENCY_10
+ * @arg @ref LL_FLASH_LATENCY_11
+ * @arg @ref LL_FLASH_LATENCY_12
+ * @arg @ref LL_FLASH_LATENCY_13
+ * @arg @ref LL_FLASH_LATENCY_14
+ * @arg @ref LL_FLASH_LATENCY_15
+ */
+__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
+{
+ return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
+}
+
+/**
+ * @brief Enable Flash Power-down mode during run mode or Low-power run mode
+ * @note Flash memory can be put in power-down mode only when the code is executed
+ * from RAM
+ * @note Flash must not be accessed when power down is enabled
+ * @note Flash must not be put in power-down while a program or an erase operation
+ * is on-going
+ * @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n
+ * FLASH_PDKEYR PDKEY1_1 LL_FLASH_EnableRunPowerDown\n
+ * FLASH_PDKEYR PDKEY1_2 LL_FLASH_EnableRunPowerDown\n
+ * FLASH_PDKEYR PDKEY2_1 LL_FLASH_EnableRunPowerDown\n
+ * FLASH_PDKEYR PDKEY2_2 LL_FLASH_EnableRunPowerDown
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void)
+{
+ /* Following values must be written consecutively to unlock the RUN_PD bit in
+ FLASH_ACR */
+ WRITE_REG(FLASH->PDKEY1R, LL_FLASH_PDKEY1_1);
+ WRITE_REG(FLASH->PDKEY1R, LL_FLASH_PDKEY1_2);
+ WRITE_REG(FLASH->PDKEY2R, LL_FLASH_PDKEY2_1);
+ WRITE_REG(FLASH->PDKEY2R, LL_FLASH_PDKEY2_2);
+
+ /*Request to enter flash in power mode */
+ SET_BIT(FLASH->ACR, FLASH_ACR_PDREQ1 | FLASH_ACR_PDREQ2);
+}
+
+/**
+ * @brief Enable flash Power-down mode during run mode or Low-power run mode of bank1
+ * @note Bank 1 of flash memory can be put in power-down mode only when the code is executed
+ * from RAM
+ * @note Bank1 of flash must not be accessed when power down is enabled
+ * @note Bank1 of flash must not be put in power-down while a program or an erase operation
+ * is on-going
+ * @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n
+ * FLASH_PDKEYR PDKEY1_1 LL_FLASH_EnableRunPowerDown\n
+ * FLASH_PDKEYR PDKEY1_2 LL_FLASH_EnableRunPowerDown\n
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_EnableRunPowerDownBank1(void)
+{
+ /* Following values must be written consecutively to unlock the RUN_PD bit in
+ FLASH_ACR */
+ WRITE_REG(FLASH->PDKEY1R, LL_FLASH_PDKEY1_1);
+ WRITE_REG(FLASH->PDKEY1R, LL_FLASH_PDKEY1_2);
+
+ /*Request to enter flash in power mode */
+ SET_BIT(FLASH->ACR, FLASH_ACR_PDREQ1);
+}
+
+/**
+ * @brief Enable flash Power-down mode during run mode or Low-power run mode of Bank2
+ * @note Bank 2 of flash memory can be put in power-down mode only when the code is executed
+ * from RAM
+ * @note Bank2 of flash must not be accessed when power down is enabled
+ * @note Bank2 of flash must not be put in power-down while a program or an erase operation
+ * is on-going
+ * @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n
+ * FLASH_PDKEYR PDKEY2_1 LL_FLASH_EnableRunPowerDown\n
+ * FLASH_PDKEYR PDKEY2_2 LL_FLASH_EnableRunPowerDown\n
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_EnableRunPowerDownBank2(void)
+{
+ /* Following values must be written consecutively to unlock the RUN_PD bit in
+ FLASH_ACR */
+ WRITE_REG(FLASH->PDKEY2R, LL_FLASH_PDKEY2_1);
+ WRITE_REG(FLASH->PDKEY2R, LL_FLASH_PDKEY2_2);
+
+ /*Request to enter flash in power mode */
+ SET_BIT(FLASH->ACR, FLASH_ACR_PDREQ2);
+}
+
+/**
+ * @brief Enable Flash Power-down mode during Sleep or Low-power sleep mode
+ * @note Flash must not be put in power-down while a program or an erase operation
+ * is on-going
+ * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_EnableSleepPowerDown
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void)
+{
+ SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
+}
+
+/**
+ * @brief Disable Flash Power-down mode during Sleep or Low-power sleep mode
+ * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_DisableSleepPowerDown
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void)
+{
+ CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
+}
+/**
+ * @}
+ */
+
+
+/** @defgroup SYSTEM_LL_EF_ERASE_MEMORIE_STATUS ERASE MEMORIE STATUS
+ * @{
+ */
+
+/**
+ * @brief Clear Status of End of Erase for ICACHE and PKA RAMs
+ * @rmtoll MESR IPMEE LL_SYSCFG_ClearEraseEndStatus
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_ClearEraseEndStatus(void)
+{
+ SET_BIT(SYSCFG->MESR, SYSCFG_MESR_IPMEE);
+}
+
+/**
+ * @brief Get Status of End of Erase for ICACHE and PKA RAMs
+ * @rmtoll MESR IPMEE LL_SYSCFG_GetEraseEndStatus
+ * @retval Returned value can be one of the following values:
+ * @arg LL_SYSCFG_MEMORIES_ERASE_ON_GOING : Erase of memories not yet done
+ * @arg LL_SYSCFG_MEMORIES_ERASE_ENDED: Erase of memories ended
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetEraseEndStatus(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->MESR, SYSCFG_MESR_IPMEE));
+}
+
+
+/**
+ * @brief Clear Status of End of Erase after reset for SRAM2, BKPRAM, ICACHE, DCACHE,PKA rams
+ * @rmtoll MESR MCLR LL_SYSCFG_ClearEraseAfterResetStatus
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_ClearEraseAfterResetStatus(void)
+{
+ SET_BIT(SYSCFG->MESR, SYSCFG_MESR_MCLR);
+}
+
+/**
+ * @brief Get Status of End of Erase after reset for SRAM2, BKPRAM, ICACHE, DCACHE,PKA rams
+ * @rmtoll MESR MCLR LL_SYSCFG_GetEraseAfterResetStatus
+ * @retval Returned value can be one of the following values:
+ * @arg LL_SYSCFG_MEMORIES_ERASE_ON_GOING : Erase of memories not yet done
+ * @arg LL_SYSCFG_MEMORIES_ERASE_ENDED: Erase of memories ended
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetEraseAfterResetStatus(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->MESR, SYSCFG_MESR_MCLR));
+}
+/**
+ * @}
+ */
+
+#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32u5xx_LL_SYSTEM_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_tim.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_tim.h
new file mode 100644
index 00000000..8b10417b
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_tim.h
@@ -0,0 +1,6349 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_tim.h
+ * @author MCD Application Team
+ * @brief Header file of TIM LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32U5xx_LL_TIM_H
+#define __STM32U5xx_LL_TIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx.h"
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined (TIM1) \
+ || defined (TIM2) \
+ || defined (TIM3) \
+ || defined (TIM4) \
+ || defined (TIM5) \
+ || defined (TIM6) \
+ || defined (TIM7) \
+ || defined (TIM8) \
+ || defined (TIM15) \
+ || defined (TIM16) \
+ || defined (TIM17) \
+ || defined (TIM20)
+
+/** @defgroup TIM_LL TIM
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Variables TIM Private Variables
+ * @{
+ */
+static const uint8_t OFFSET_TAB_CCMRx[] =
+{
+ 0x00U, /* 0: TIMx_CH1 */
+ 0x00U, /* 1: TIMx_CH1N */
+ 0x00U, /* 2: TIMx_CH2 */
+ 0x00U, /* 3: TIMx_CH2N */
+ 0x04U, /* 4: TIMx_CH3 */
+ 0x04U, /* 5: TIMx_CH3N */
+ 0x04U, /* 6: TIMx_CH4 */
+ 0x04U, /* 7: TIMx_CH4N */
+ 0x38U, /* 8: TIMx_CH5 */
+ 0x38U /* 9: TIMx_CH6 */
+
+};
+
+static const uint8_t SHIFT_TAB_OCxx[] =
+{
+ 0U, /* 0: OC1M, OC1FE, OC1PE */
+ 0U, /* 1: - NA */
+ 8U, /* 2: OC2M, OC2FE, OC2PE */
+ 0U, /* 3: - NA */
+ 0U, /* 4: OC3M, OC3FE, OC3PE */
+ 0U, /* 5: - NA */
+ 8U, /* 6: OC4M, OC4FE, OC4PE */
+ 0U, /* 7: - NA */
+ 0U, /* 8: OC5M, OC5FE, OC5PE */
+ 8U /* 9: OC6M, OC6FE, OC6PE */
+};
+
+static const uint8_t SHIFT_TAB_ICxx[] =
+{
+ 0U, /* 0: CC1S, IC1PSC, IC1F */
+ 0U, /* 1: - NA */
+ 8U, /* 2: CC2S, IC2PSC, IC2F */
+ 0U, /* 3: - NA */
+ 0U, /* 4: CC3S, IC3PSC, IC3F */
+ 0U, /* 5: - NA */
+ 8U, /* 6: CC4S, IC4PSC, IC4F */
+ 0U, /* 7: - NA */
+ 0U, /* 8: - NA */
+ 0U /* 9: - NA */
+};
+
+static const uint8_t SHIFT_TAB_CCxP[] =
+{
+ 0U, /* 0: CC1P */
+ 2U, /* 1: CC1NP */
+ 4U, /* 2: CC2P */
+ 6U, /* 3: CC2NP */
+ 8U, /* 4: CC3P */
+ 10U, /* 5: CC3NP */
+ 12U, /* 6: CC4P */
+ 14U, /* 7: CC4NP */
+ 16U, /* 8: CC5P */
+ 20U /* 9: CC6P */
+};
+
+static const uint8_t SHIFT_TAB_OISx[] =
+{
+ 0U, /* 0: OIS1 */
+ 1U, /* 1: OIS1N */
+ 2U, /* 2: OIS2 */
+ 3U, /* 3: OIS2N */
+ 4U, /* 4: OIS3 */
+ 5U, /* 5: OIS3N */
+ 6U, /* 6: OIS4 */
+ 7U, /* 7: OIS4N */
+ 8U, /* 8: OIS5 */
+ 10U /* 9: OIS6 */
+};
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Constants TIM Private Constants
+ * @{
+ */
+
+/* Defines used for the bit position in the register and perform offsets */
+#define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
+
+/* Generic bit definitions for TIMx_AF1 register */
+#define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */
+#define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL /*!< TIMx ETR source selection */
+
+
+/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
+#define DT_DELAY_1 ((uint8_t)0x7F)
+#define DT_DELAY_2 ((uint8_t)0x3F)
+#define DT_DELAY_3 ((uint8_t)0x1F)
+#define DT_DELAY_4 ((uint8_t)0x1F)
+
+/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
+#define DT_RANGE_1 ((uint8_t)0x00)
+#define DT_RANGE_2 ((uint8_t)0x80)
+#define DT_RANGE_3 ((uint8_t)0xC0)
+#define DT_RANGE_4 ((uint8_t)0xE0)
+
+/** Legacy definitions for compatibility purpose
+@cond 0
+ */
+/**
+@endcond
+ */
+
+#define OCREF_CLEAR_SELECT_POS (28U)
+#define OCREF_CLEAR_SELECT_MSK (0x1U << OCREF_CLEAR_SELECT_POS) /*!< 0x10000000 */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Macros TIM Private Macros
+ * @{
+ */
+/** @brief Convert channel id into channel index.
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH4N
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval none
+ */
+#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
+ (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
+ ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
+ ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
+ ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
+ ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
+ ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
+ ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
+ ((__CHANNEL__) == LL_TIM_CHANNEL_CH4N) ? 7U :\
+ ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 8U : 9U)
+
+/** @brief Calculate the deadtime sampling period(in ps).
+ * @param __TIMCLK__ timer input clock frequency (in Hz).
+ * @param __CKD__ This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+ * @retval none
+ */
+#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
+ (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
+ ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
+ ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
+/**
+ * @}
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief TIM Time Base configuration structure definition.
+ */
+typedef struct
+{
+ uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
+ This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_SetPrescaler().*/
+
+ uint32_t CounterMode; /*!< Specifies the counter mode.
+ This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_SetCounterMode().*/
+
+ uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
+ Auto-Reload Register at the next update event.
+ This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+ Some timer instances may support 32 bits counters. In that case this parameter must
+ be a number between 0x0000 and 0xFFFFFFFF.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_SetAutoReload().*/
+
+ uint32_t ClockDivision; /*!< Specifies the clock division.
+ This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_SetClockDivision().*/
+
+ uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
+ reaches zero, an update event is generated and counting restarts
+ from the RCR value (N).
+ This means in PWM mode that (N+1) corresponds to:
+ - the number of PWM periods in edge-aligned mode
+ - the number of half PWM period in center-aligned mode
+ GP timers: this parameter must be a number between Min_Data = 0x00 and
+ Max_Data = 0xFF.
+ Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
+ Max_Data = 0xFFFF.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_SetRepetitionCounter().*/
+} LL_TIM_InitTypeDef;
+
+/**
+ * @brief TIM Output Compare configuration structure definition.
+ */
+typedef struct
+{
+ uint32_t OCMode; /*!< Specifies the output mode.
+ This parameter can be a value of @ref TIM_LL_EC_OCMODE.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_OC_SetMode().*/
+
+ uint32_t OCState; /*!< Specifies the TIM Output Compare state.
+ This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
+
+ This feature can be modified afterwards using unitary functions
+ @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+
+ uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
+ This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
+
+ This feature can be modified afterwards using unitary functions
+ @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+
+ uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
+ This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+
+ This feature can be modified afterwards using unitary function
+ LL_TIM_OC_SetCompareCHx (x=1..6).*/
+
+ uint32_t OCPolarity; /*!< Specifies the output polarity.
+ This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_OC_SetPolarity().*/
+
+ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
+ This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_OC_SetPolarity().*/
+
+
+ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_OC_SetIdleState().*/
+
+ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_OC_SetIdleState().*/
+} LL_TIM_OC_InitTypeDef;
+
+/**
+ * @brief TIM Input Capture configuration structure definition.
+ */
+
+typedef struct
+{
+
+ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetPolarity().*/
+
+ uint32_t ICActiveInput; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetActiveInput().*/
+
+ uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetPrescaler().*/
+
+ uint32_t ICFilter; /*!< Specifies the input capture filter.
+ This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetFilter().*/
+} LL_TIM_IC_InitTypeDef;
+
+
+/**
+ * @brief TIM Encoder interface configuration structure definition.
+ */
+typedef struct
+{
+ uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
+ This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_SetEncoderMode().*/
+
+ uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
+ This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetPolarity().*/
+
+ uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
+ This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetActiveInput().*/
+
+ uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
+ This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetPrescaler().*/
+
+ uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
+ This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetFilter().*/
+
+ uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
+ This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetPolarity().*/
+
+ uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
+ This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetActiveInput().*/
+
+ uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
+ This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetPrescaler().*/
+
+ uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
+ This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetFilter().*/
+
+} LL_TIM_ENCODER_InitTypeDef;
+
+/**
+ * @brief TIM Hall sensor interface configuration structure definition.
+ */
+typedef struct
+{
+
+ uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
+ This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetPolarity().*/
+
+ uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
+ Prescaler must be set to get a maximum counter period longer than the
+ time interval between 2 consecutive changes on the Hall inputs.
+ This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetPrescaler().*/
+
+ uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
+ This parameter can be a value of
+ @ref TIM_LL_EC_IC_FILTER.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetFilter().*/
+
+ uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
+ A positive pulse (TRGO event) is generated with a programmable delay every time
+ a change occurs on the Hall inputs.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_OC_SetCompareCH2().*/
+} LL_TIM_HALLSENSOR_InitTypeDef;
+
+/**
+ * @brief BDTR (Break and Dead Time) structure definition
+ */
+typedef struct
+{
+ uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
+ This parameter can be a value of @ref TIM_LL_EC_OSSR
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_SetOffStates()
+
+ @note This bit-field cannot be modified as long as LOCK level 2 has been
+ programmed. */
+
+ uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
+ This parameter can be a value of @ref TIM_LL_EC_OSSI
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_SetOffStates()
+
+ @note This bit-field cannot be modified as long as LOCK level 2 has been
+ programmed. */
+
+ uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
+ This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
+
+ @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
+ register has been written, their content is frozen until the next reset.*/
+
+ uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
+ switching-on of the outputs.
+ This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_OC_SetDeadTime()
+
+ @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
+ programmed. */
+
+ uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
+ This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
+
+ This feature can be modified afterwards using unitary functions
+ @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
+
+ @note This bit-field can not be modified as long as LOCK level 1 has been
+ programmed. */
+
+ uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
+ This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_ConfigBRK()
+
+ @note This bit-field can not be modified as long as LOCK level 1 has been
+ programmed. */
+
+ uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
+ This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_ConfigBRK()
+
+ @note This bit-field can not be modified as long as LOCK level 1 has been
+ programmed. */
+
+ uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.
+ This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE
+
+ This feature can be modified afterwards using unitary functions
+ @ref LL_TIM_ConfigBRK()
+
+ @note Bidirectional break input is only supported by advanced timers instances.
+
+ @note This bit-field can not be modified as long as LOCK level 1 has been
+ programmed. */
+
+ uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
+ This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
+
+ This feature can be modified afterwards using unitary functions
+ @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
+
+ @note This bit-field can not be modified as long as LOCK level 1 has been
+ programmed. */
+
+ uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
+ This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_ConfigBRK2()
+
+ @note This bit-field can not be modified as long as LOCK level 1 has been
+ programmed. */
+
+ uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
+ This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_ConfigBRK2()
+
+ @note This bit-field can not be modified as long as LOCK level 1 has been
+ programmed. */
+
+ uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.
+ This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE
+
+ This feature can be modified afterwards using unitary functions
+ @ref LL_TIM_ConfigBRK2()
+
+ @note Bidirectional break input is only supported by advanced timers instances.
+
+ @note This bit-field can not be modified as long as LOCK level 1 has been
+ programmed. */
+
+ uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
+ This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
+
+ This feature can be modified afterwards using unitary functions
+ @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
+
+ @note This bit-field can not be modified as long as LOCK level 1 has been
+ programmed. */
+} LL_TIM_BDTR_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
+ * @{
+ */
+
+/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_TIM_ReadReg function.
+ * @{
+ */
+#define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
+#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
+#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
+#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
+#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
+#define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
+#define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
+#define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
+#define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
+#define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
+#define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
+#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
+#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
+#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
+#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
+#define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */
+#define LL_TIM_SR_IDXF TIM_SR_IDXF /*!< Index interrupt flag */
+#define LL_TIM_SR_DIRF TIM_SR_DIRF /*!< Direction Change interrupt flag */
+#define LL_TIM_SR_IERRF TIM_SR_IERRF /*!< Index Error flag */
+#define LL_TIM_SR_TERRF TIM_SR_TERRF /*!< Transition Error flag */
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
+ * @{
+ */
+#define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
+#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
+ * @{
+ */
+#define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
+#define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
+ * @{
+ */
+#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
+#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup TIM_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
+ * @{
+ */
+#define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
+#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
+#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
+#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
+#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
+#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
+#define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
+#define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
+#define LL_TIM_DIER_IDXIE TIM_DIER_IDXIE /*!< Index interrupt enable */
+#define LL_TIM_DIER_DIRIE TIM_DIER_DIRIE /*!< Direction Change interrupt enable */
+#define LL_TIM_DIER_IERRIE TIM_DIER_IERRIE /*!< Index Error interrupt enable */
+#define LL_TIM_DIER_TERRIE TIM_DIER_TERRIE /*!< Transition Error interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
+ * @{
+ */
+#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
+#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
+ * @{
+ */
+#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
+#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
+ * @{
+ */
+#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!TIMx_CCRy else active.*/
+#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!TIMx_CCRy else inactive*/
+#define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in TIM register.
+ * @param __INSTANCE__ TIM Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
+ * @{
+ */
+
+/**
+ * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
+ * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
+ * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
+ * to TIMx_CNT register bit 31)
+ * @param __CNT__ Counter value
+ * @retval UIF status bit
+ */
+#define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
+ (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
+
+/**
+ * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
+ * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __CKD__ This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+ * @param __DT__ deadtime duration (in ns)
+ * @retval DTG[0:7]
+ */
+#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
+ ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
+ (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
+ (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
+ (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
+ (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
+ (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
+ (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
+ (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
+ (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
+ (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
+ (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
+ 0U)
+
+/**
+ * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
+ * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __CNTCLK__ counter clock frequency (in Hz)
+ * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
+ (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
+
+/**
+ * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
+ * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __PSC__ prescaler
+ * @param __FREQ__ output signal frequency (in Hz)
+ * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
+ ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
+
+/**
+ * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
+ * output signal frequency.
+ * @note ex: @ref __LL_TIM_CALC_ARR_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10000);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __PSC__ prescaler
+ * @param __FREQ__ output signal frequency (in Hz)
+ * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __LL_TIM_CALC_ARR_DITHER(__TIMCLK__, __PSC__, __FREQ__) \
+ ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? \
+ (uint32_t)((((uint64_t)(__TIMCLK__) * 16U/((__FREQ__) * ((__PSC__) + 1U))) - 16U)) : 0U)
+
+/**
+ * @brief HELPER macro calculating the compare value required to achieve the required timer output compare
+ * active/inactive delay.
+ * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __PSC__ prescaler
+ * @param __DELAY__ timer output compare active/inactive delay (in us)
+ * @retval Compare value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
+ ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
+ / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
+
+/**
+ * @brief HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer
+ * output compare active/inactive delay.
+ * @note ex: @ref __LL_TIM_CALC_DELAY_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __PSC__ prescaler
+ * @param __DELAY__ timer output compare active/inactive delay (in us)
+ * @retval Compare value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __LL_TIM_CALC_DELAY_DITHER(__TIMCLK__, __PSC__, __DELAY__) \
+ ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__) * 16U) \
+ / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
+
+/**
+ * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
+ * (when the timer operates in one pulse mode).
+ * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __PSC__ prescaler
+ * @param __DELAY__ timer output compare active/inactive delay (in us)
+ * @param __PULSE__ pulse duration (in us)
+ * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
+ ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
+ + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
+
+/**
+ * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
+ * pulse duration (when the timer operates in one pulse mode).
+ * @note ex: @ref __LL_TIM_CALC_PULSE_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __PSC__ prescaler
+ * @param __DELAY__ timer output compare active/inactive delay (in us)
+ * @param __PULSE__ pulse duration (in us)
+ * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __LL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
+ ((uint32_t)(__LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__PULSE__)) \
+ + __LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__DELAY__))))
+
+/**
+ * @brief HELPER macro retrieving the ratio of the input capture prescaler
+ * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
+ * @param __ICPSC__ This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ICPSC_DIV1
+ * @arg @ref LL_TIM_ICPSC_DIV2
+ * @arg @ref LL_TIM_ICPSC_DIV4
+ * @arg @ref LL_TIM_ICPSC_DIV8
+ * @retval Input capture prescaler ratio (1, 2, 4 or 8)
+ */
+#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
+ ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
+
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
+ * @{
+ */
+
+/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
+ * @{
+ */
+/**
+ * @brief Enable timer counter.
+ * @rmtoll CR1 CEN LL_TIM_EnableCounter
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->CR1, TIM_CR1_CEN);
+}
+
+/**
+ * @brief Disable timer counter.
+ * @rmtoll CR1 CEN LL_TIM_DisableCounter
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
+}
+
+/**
+ * @brief Indicates whether the timer counter is enabled.
+ * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable update event generation.
+ * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
+}
+
+/**
+ * @brief Disable update event generation.
+ * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
+}
+
+/**
+ * @brief Indicates whether update event generation is enabled.
+ * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
+ * @param TIMx Timer instance
+ * @retval Inverted state of bit (0 or 1).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set update event source
+ * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
+ * generate an update interrupt or DMA request if enabled:
+ * - Counter overflow/underflow
+ * - Setting the UG bit
+ * - Update generation through the slave mode controller
+ * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
+ * overflow/underflow generates an update interrupt or DMA request if enabled.
+ * @rmtoll CR1 URS LL_TIM_SetUpdateSource
+ * @param TIMx Timer instance
+ * @param UpdateSource This parameter can be one of the following values:
+ * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+ * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
+{
+ MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
+}
+
+/**
+ * @brief Get actual event update source
+ * @rmtoll CR1 URS LL_TIM_GetUpdateSource
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+ * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
+}
+
+/**
+ * @brief Set one pulse mode (one shot v.s. repetitive).
+ * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
+ * @param TIMx Timer instance
+ * @param OnePulseMode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+ * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
+{
+ MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
+}
+
+/**
+ * @brief Get actual one pulse mode.
+ * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+ * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
+}
+
+/**
+ * @brief Set the timer counter counting mode.
+ * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+ * check whether or not the counter mode selection feature is supported
+ * by a timer instance.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
+ * CR1 CMS LL_TIM_SetCounterMode
+ * @param TIMx Timer instance
+ * @param CounterMode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_COUNTERMODE_UP
+ * @arg @ref LL_TIM_COUNTERMODE_DOWN
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
+{
+ MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
+}
+
+/**
+ * @brief Get actual counter mode.
+ * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+ * check whether or not the counter mode selection feature is supported
+ * by a timer instance.
+ * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
+ * CR1 CMS LL_TIM_GetCounterMode
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_COUNTERMODE_UP
+ * @arg @ref LL_TIM_COUNTERMODE_DOWN
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
+{
+ uint32_t counter_mode;
+
+ counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
+
+ if (counter_mode == 0U)
+ {
+ counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
+ }
+
+ return counter_mode;
+}
+
+/**
+ * @brief Enable auto-reload (ARR) preload.
+ * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
+}
+
+/**
+ * @brief Disable auto-reload (ARR) preload.
+ * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
+}
+
+/**
+ * @brief Indicates whether auto-reload (ARR) preload is enabled.
+ * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
+ * (when supported) and the digital filters.
+ * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+ * whether or not the clock division feature is supported by the timer
+ * instance.
+ * @rmtoll CR1 CKD LL_TIM_SetClockDivision
+ * @param TIMx Timer instance
+ * @param ClockDivision This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
+{
+ MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
+}
+
+/**
+ * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
+ * generators (when supported) and the digital filters.
+ * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+ * whether or not the clock division feature is supported by the timer
+ * instance.
+ * @rmtoll CR1 CKD LL_TIM_GetClockDivision
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
+}
+
+/**
+ * @brief Set the counter value.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note If dithering is activated, pay attention to the Counter value interpretation
+ * @rmtoll CNT CNT LL_TIM_SetCounter
+ * @param TIMx Timer instance
+ * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
+{
+ WRITE_REG(TIMx->CNT, Counter);
+}
+
+/**
+ * @brief Get the counter value.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note If dithering is activated, pay attention to the Counter value interpretation
+ * @rmtoll CNT CNT LL_TIM_GetCounter
+ * @param TIMx Timer instance
+ * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CNT));
+}
+
+/**
+ * @brief Get the current direction of the counter
+ * @rmtoll CR1 DIR LL_TIM_GetDirection
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_COUNTERDIRECTION_UP
+ * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
+}
+
+/**
+ * @brief Set the prescaler value.
+ * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
+ * @note The prescaler can be changed on the fly as this control register is buffered. The new
+ * prescaler ratio is taken into account at the next update event.
+ * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
+ * @rmtoll PSC PSC LL_TIM_SetPrescaler
+ * @param TIMx Timer instance
+ * @param Prescaler between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
+{
+ WRITE_REG(TIMx->PSC, Prescaler);
+}
+
+/**
+ * @brief Get the prescaler value.
+ * @rmtoll PSC PSC LL_TIM_GetPrescaler
+ * @param TIMx Timer instance
+ * @retval Prescaler value between Min_Data=0 and Max_Data=65535
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->PSC));
+}
+
+/**
+ * @brief Set the auto-reload value.
+ * @note The counter is blocked while the auto-reload value is null.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
+ * In case dithering is activated,macro __LL_TIM_CALC_ARR_DITHER can be used instead, to calculate the AutoReload
+ * parameter.
+ * @rmtoll ARR ARR LL_TIM_SetAutoReload
+ * @param TIMx Timer instance
+ * @param AutoReload between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
+{
+ WRITE_REG(TIMx->ARR, AutoReload);
+}
+
+/**
+ * @brief Get the auto-reload value.
+ * @rmtoll ARR ARR LL_TIM_GetAutoReload
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note If dithering is activated, pay attention to the returned value interpretation
+ * @param TIMx Timer instance
+ * @retval Auto-reload value
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->ARR));
+}
+
+/**
+ * @brief Set the repetition counter value.
+ * @note For advanced timer instances RepetitionCounter can be up to 65535.
+ * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a repetition counter.
+ * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
+ * @param TIMx Timer instance
+ * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
+{
+ WRITE_REG(TIMx->RCR, RepetitionCounter);
+}
+
+/**
+ * @brief Get the repetition counter value.
+ * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a repetition counter.
+ * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
+ * @param TIMx Timer instance
+ * @retval Repetition counter value
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->RCR));
+}
+
+/**
+ * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
+ * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
+ * in an atomic way.
+ * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
+}
+
+/**
+ * @brief Disable update interrupt flag (UIF) remapping.
+ * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
+}
+
+/**
+ * @brief Indicate whether update interrupt flag (UIF) copy is set.
+ * @param Counter Counter value
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(uint32_t Counter)
+{
+ return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable dithering.
+ * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides dithering.
+ * @rmtoll CR1 DITHEN LL_TIM_EnableDithering
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDithering(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->CR1, TIM_CR1_DITHEN);
+}
+
+/**
+ * @brief Disable dithering.
+ * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides dithering.
+ * @rmtoll CR1 DITHEN LL_TIM_DisableDithering
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDithering(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->CR1, TIM_CR1_DITHEN);
+}
+
+/**
+ * @brief Indicates whether dithering is activated.
+ * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides dithering.
+ * @rmtoll CR1 DITHEN LL_TIM_IsEnabledDithering
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDithering(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->CR1, TIM_CR1_DITHEN) == (TIM_CR1_DITHEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
+ * @{
+ */
+/**
+ * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
+ * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
+ * they are updated only when a commutation event (COM) occurs.
+ * @note Only on channels that have a complementary output.
+ * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance is able to generate a commutation event.
+ * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
+}
+
+/**
+ * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
+ * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance is able to generate a commutation event.
+ * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
+}
+
+/**
+ * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
+ * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance is able to generate a commutation event.
+ * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
+ * @param TIMx Timer instance
+ * @param CCUpdateSource This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
+ * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
+{
+ MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
+}
+
+/**
+ * @brief Set the trigger of the capture/compare DMA request.
+ * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
+ * @param TIMx Timer instance
+ * @param DMAReqTrigger This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CCDMAREQUEST_CC
+ * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
+{
+ MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
+}
+
+/**
+ * @brief Get actual trigger of the capture/compare DMA request.
+ * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_CCDMAREQUEST_CC
+ * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+ */
+__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
+}
+
+/**
+ * @brief Set the lock level to freeze the
+ * configuration of several capture/compare parameters.
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * the lock mechanism is supported by a timer instance.
+ * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
+ * @param TIMx Timer instance
+ * @param LockLevel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_LOCKLEVEL_OFF
+ * @arg @ref LL_TIM_LOCKLEVEL_1
+ * @arg @ref LL_TIM_LOCKLEVEL_2
+ * @arg @ref LL_TIM_LOCKLEVEL_3
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
+{
+ MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
+}
+
+/**
+ * @brief Enable capture/compare channels.
+ * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
+ * CCER CC1NE LL_TIM_CC_EnableChannel\n
+ * CCER CC2E LL_TIM_CC_EnableChannel\n
+ * CCER CC2NE LL_TIM_CC_EnableChannel\n
+ * CCER CC3E LL_TIM_CC_EnableChannel\n
+ * CCER CC3NE LL_TIM_CC_EnableChannel\n
+ * CCER CC4E LL_TIM_CC_EnableChannel\n
+ * CCER CC4NE LL_TIM_CC_EnableChannel\n
+ * CCER CC5E LL_TIM_CC_EnableChannel\n
+ * CCER CC6E LL_TIM_CC_EnableChannel
+ * @param TIMx Timer instance
+ * @param Channels This parameter can be a combination of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH4N
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+ SET_BIT(TIMx->CCER, Channels);
+}
+
+/**
+ * @brief Disable capture/compare channels.
+ * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
+ * CCER CC1NE LL_TIM_CC_DisableChannel\n
+ * CCER CC2E LL_TIM_CC_DisableChannel\n
+ * CCER CC2NE LL_TIM_CC_DisableChannel\n
+ * CCER CC3E LL_TIM_CC_DisableChannel\n
+ * CCER CC3NE LL_TIM_CC_DisableChannel\n
+ * CCER CC4E LL_TIM_CC_DisableChannel\n
+ * CCER CC4NE LL_TIM_CC_DisableChannel\n
+ * CCER CC5E LL_TIM_CC_DisableChannel\n
+ * CCER CC6E LL_TIM_CC_DisableChannel
+ * @param TIMx Timer instance
+ * @param Channels This parameter can be a combination of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH4N
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+ CLEAR_BIT(TIMx->CCER, Channels);
+}
+
+/**
+ * @brief Indicate whether channel(s) is(are) enabled.
+ * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC4NE LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC6E LL_TIM_CC_IsEnabledChannel
+ * @param TIMx Timer instance
+ * @param Channels This parameter can be a combination of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH4N
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+ return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
+ * @{
+ */
+/**
+ * @brief Configure an output channel.
+ * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
+ * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
+ * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
+ * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
+ * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
+ * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
+ * CCER CC1P LL_TIM_OC_ConfigOutput\n
+ * CCER CC2P LL_TIM_OC_ConfigOutput\n
+ * CCER CC3P LL_TIM_OC_ConfigOutput\n
+ * CCER CC4P LL_TIM_OC_ConfigOutput\n
+ * CCER CC5P LL_TIM_OC_ConfigOutput\n
+ * CCER CC6P LL_TIM_OC_ConfigOutput\n
+ * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
+ * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
+ * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
+ * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
+ * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
+ * CR2 OIS6 LL_TIM_OC_ConfigOutput
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @param Configuration This parameter must be a combination of all the following values:
+ * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
+ * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
+ MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
+ (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
+ MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
+ (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+ * @brief Define the behavior of the output reference signal OCxREF from which
+ * OCx and OCxN (when relevant) are derived.
+ * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
+ * CCMR1 OC2M LL_TIM_OC_SetMode\n
+ * CCMR2 OC3M LL_TIM_OC_SetMode\n
+ * CCMR2 OC4M LL_TIM_OC_SetMode\n
+ * CCMR3 OC5M LL_TIM_OC_SetMode\n
+ * CCMR3 OC6M LL_TIM_OC_SetMode
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_OCMODE_FROZEN
+ * @arg @ref LL_TIM_OCMODE_ACTIVE
+ * @arg @ref LL_TIM_OCMODE_INACTIVE
+ * @arg @ref LL_TIM_OCMODE_TOGGLE
+ * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+ * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+ * @arg @ref LL_TIM_OCMODE_PWM1
+ * @arg @ref LL_TIM_OCMODE_PWM2
+ * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
+ * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
+ * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
+ * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
+ * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
+ * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
+ * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only)
+ * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only)
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
+}
+
+/**
+ * @brief Get the output compare mode of an output channel.
+ * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
+ * CCMR1 OC2M LL_TIM_OC_GetMode\n
+ * CCMR2 OC3M LL_TIM_OC_GetMode\n
+ * CCMR2 OC4M LL_TIM_OC_GetMode\n
+ * CCMR3 OC5M LL_TIM_OC_GetMode\n
+ * CCMR3 OC6M LL_TIM_OC_GetMode
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_OCMODE_FROZEN
+ * @arg @ref LL_TIM_OCMODE_ACTIVE
+ * @arg @ref LL_TIM_OCMODE_INACTIVE
+ * @arg @ref LL_TIM_OCMODE_TOGGLE
+ * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+ * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+ * @arg @ref LL_TIM_OCMODE_PWM1
+ * @arg @ref LL_TIM_OCMODE_PWM2
+ * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
+ * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
+ * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
+ * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
+ * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
+ * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
+ * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only)
+ * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only)
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
+}
+
+/**
+ * @brief Set the polarity of an output channel.
+ * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
+ * CCER CC1NP LL_TIM_OC_SetPolarity\n
+ * CCER CC2P LL_TIM_OC_SetPolarity\n
+ * CCER CC2NP LL_TIM_OC_SetPolarity\n
+ * CCER CC3P LL_TIM_OC_SetPolarity\n
+ * CCER CC3NP LL_TIM_OC_SetPolarity\n
+ * CCER CC4P LL_TIM_OC_SetPolarity\n
+ * CCER CC4NP LL_TIM_OC_SetPolarity\n
+ * CCER CC5P LL_TIM_OC_SetPolarity\n
+ * CCER CC6P LL_TIM_OC_SetPolarity
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH4N
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_TIM_OCPOLARITY_HIGH
+ * @arg @ref LL_TIM_OCPOLARITY_LOW
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+ * @brief Get the polarity of an output channel.
+ * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
+ * CCER CC1NP LL_TIM_OC_GetPolarity\n
+ * CCER CC2P LL_TIM_OC_GetPolarity\n
+ * CCER CC2NP LL_TIM_OC_GetPolarity\n
+ * CCER CC3P LL_TIM_OC_GetPolarity\n
+ * CCER CC3NP LL_TIM_OC_GetPolarity\n
+ * CCER CC4P LL_TIM_OC_GetPolarity\n
+ * CCER CC4NP LL_TIM_OC_GetPolarity\n
+ * CCER CC5P LL_TIM_OC_GetPolarity\n
+ * CCER CC6P LL_TIM_OC_GetPolarity
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH4N
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_OCPOLARITY_HIGH
+ * @arg @ref LL_TIM_OCPOLARITY_LOW
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+ * @brief Set the IDLE state of an output channel
+ * @note This function is significant only for the timer instances
+ * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
+ * can be used to check whether or not a timer instance provides
+ * a break input.
+ * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
+ * CR2 OIS2N LL_TIM_OC_SetIdleState\n
+ * CR2 OIS2 LL_TIM_OC_SetIdleState\n
+ * CR2 OIS2N LL_TIM_OC_SetIdleState\n
+ * CR2 OIS3 LL_TIM_OC_SetIdleState\n
+ * CR2 OIS3N LL_TIM_OC_SetIdleState\n
+ * CR2 OIS4 LL_TIM_OC_SetIdleState\n
+ * CR2 OIS4N LL_TIM_OC_SetIdleState\n
+ * CR2 OIS5 LL_TIM_OC_SetIdleState\n
+ * CR2 OIS6 LL_TIM_OC_SetIdleState
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH4N
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @param IdleState This parameter can be one of the following values:
+ * @arg @ref LL_TIM_OCIDLESTATE_LOW
+ * @arg @ref LL_TIM_OCIDLESTATE_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+ * @brief Get the IDLE state of an output channel
+ * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
+ * CR2 OIS2N LL_TIM_OC_GetIdleState\n
+ * CR2 OIS2 LL_TIM_OC_GetIdleState\n
+ * CR2 OIS2N LL_TIM_OC_GetIdleState\n
+ * CR2 OIS3 LL_TIM_OC_GetIdleState\n
+ * CR2 OIS3N LL_TIM_OC_GetIdleState\n
+ * CR2 OIS4 LL_TIM_OC_GetIdleState\n
+ * CR2 OIS4N LL_TIM_OC_GetIdleState\n
+ * CR2 OIS5 LL_TIM_OC_GetIdleState\n
+ * CR2 OIS6 LL_TIM_OC_GetIdleState
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH4N
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_OCIDLESTATE_LOW
+ * @arg @ref LL_TIM_OCIDLESTATE_HIGH
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+ * @brief Enable fast mode for the output channel.
+ * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
+ * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
+ * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
+ * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
+ * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
+ * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
+ * CCMR3 OC6FE LL_TIM_OC_EnableFast
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+
+}
+
+/**
+ * @brief Disable fast mode for the output channel.
+ * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
+ * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
+ * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
+ * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
+ * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
+ * CCMR3 OC6FE LL_TIM_OC_DisableFast
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+
+}
+
+/**
+ * @brief Indicates whether fast mode is enabled for the output channel.
+ * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
+ * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
+ * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
+ * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
+ * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
+ * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
+ return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
+ * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
+ * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
+ * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
+ * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
+ * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
+ * CCMR3 OC6PE LL_TIM_OC_EnablePreload
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+ * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
+ * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
+ * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
+ * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
+ * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
+ * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
+ * CCMR3 OC6PE LL_TIM_OC_DisablePreload
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+ * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
+ * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
+ * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
+ * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
+ * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
+ * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
+ * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
+ return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable clearing the output channel on an external event.
+ * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
+ * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance can clear the OCxREF signal on an external event.
+ * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
+ * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
+ * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
+ * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
+ * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
+ * CCMR3 OC6CE LL_TIM_OC_EnableClear
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+ * @brief Disable clearing the output channel on an external event.
+ * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance can clear the OCxREF signal on an external event.
+ * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
+ * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
+ * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
+ * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
+ * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
+ * CCMR3 OC6CE LL_TIM_OC_DisableClear
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+ * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
+ * @note This function enables clearing the output channel on an external event.
+ * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
+ * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance can clear the OCxREF signal on an external event.
+ * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
+ * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
+ * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
+ * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
+ * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
+ * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
+ return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
+ * the Ocx and OCxN signals).
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * dead-time insertion feature is supported by a timer instance.
+ * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
+ * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
+ * @param TIMx Timer instance
+ * @param DeadTime between Min_Data=0 and Max_Data=255
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
+{
+ MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
+}
+
+/**
+ * @brief Set compare value for output channel 1 (TIMx_CCR1).
+ * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 1 is supported by a timer instance.
+ * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
+ * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
+ * @param TIMx Timer instance
+ * @param CompareValue between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+ WRITE_REG(TIMx->CCR1, CompareValue);
+}
+
+/**
+ * @brief Set compare value for output channel 2 (TIMx_CCR2).
+ * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 2 is supported by a timer instance.
+ * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
+ * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
+ * @param TIMx Timer instance
+ * @param CompareValue between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+ WRITE_REG(TIMx->CCR2, CompareValue);
+}
+
+/**
+ * @brief Set compare value for output channel 3 (TIMx_CCR3).
+ * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+ * output channel is supported by a timer instance.
+ * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
+ * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
+ * @param TIMx Timer instance
+ * @param CompareValue between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+ WRITE_REG(TIMx->CCR3, CompareValue);
+}
+
+/**
+ * @brief Set compare value for output channel 4 (TIMx_CCR4).
+ * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 4 is supported by a timer instance.
+ * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
+ * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
+ * @param TIMx Timer instance
+ * @param CompareValue between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+ WRITE_REG(TIMx->CCR4, CompareValue);
+}
+
+/**
+ * @brief Set compare value for output channel 5 (TIMx_CCR5).
+ * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 5 is supported by a timer instance.
+ * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
+ * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
+ * @param TIMx Timer instance
+ * @param CompareValue between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+ MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
+}
+
+/**
+ * @brief Set compare value for output channel 6 (TIMx_CCR6).
+ * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 6 is supported by a timer instance.
+ * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
+ * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
+ * @param TIMx Timer instance
+ * @param CompareValue between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+ WRITE_REG(TIMx->CCR6, CompareValue);
+}
+
+/**
+ * @brief Get compare value (TIMx_CCR1) set for output channel 1.
+ * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 1 is supported by a timer instance.
+ * @note If dithering is activated, pay attention to the returned value interpretation.
+ * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
+ * @param TIMx Timer instance
+ * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR1));
+}
+
+/**
+ * @brief Get compare value (TIMx_CCR2) set for output channel 2.
+ * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 2 is supported by a timer instance.
+ * @note If dithering is activated, pay attention to the returned value interpretation.
+ * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
+ * @param TIMx Timer instance
+ * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR2));
+}
+
+/**
+ * @brief Get compare value (TIMx_CCR3) set for output channel 3.
+ * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 3 is supported by a timer instance.
+ * @note If dithering is activated, pay attention to the returned value interpretation.
+ * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
+ * @param TIMx Timer instance
+ * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR3));
+}
+
+/**
+ * @brief Get compare value (TIMx_CCR4) set for output channel 4.
+ * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 4 is supported by a timer instance.
+ * @note If dithering is activated, pay attention to the returned value interpretation.
+ * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
+ * @param TIMx Timer instance
+ * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR4));
+}
+
+/**
+ * @brief Get compare value (TIMx_CCR5) set for output channel 5.
+ * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 5 is supported by a timer instance.
+ * @note If dithering is activated, pay attention to the returned value interpretation.
+ * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
+ * @param TIMx Timer instance
+ * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
+}
+
+/**
+ * @brief Get compare value (TIMx_CCR6) set for output channel 6.
+ * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 6 is supported by a timer instance.
+ * @note If dithering is activated, pay attention to the returned value interpretation.
+ * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
+ * @param TIMx Timer instance
+ * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR6));
+}
+
+/**
+ * @brief Select on which reference signal the OC5REF is combined to.
+ * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports the combined 3-phase PWM mode.
+ * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
+ * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
+ * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
+ * @param TIMx Timer instance
+ * @param GroupCH5 This parameter can be a combination of the following values:
+ * @arg @ref LL_TIM_GROUPCH5_NONE
+ * @arg @ref LL_TIM_GROUPCH5_OC1REFC
+ * @arg @ref LL_TIM_GROUPCH5_OC2REFC
+ * @arg @ref LL_TIM_GROUPCH5_OC3REFC
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
+{
+ MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
+}
+
+/**
+ * @brief Set the pulse on compare pulse width prescaler.
+ * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
+ * whether or not the pulse on compare feature is supported by the timer
+ * instance.
+ * @rmtoll ECR PWPRSC LL_TIM_OC_SetPulseWidthPrescaler
+ * @param TIMx Timer instance
+ * @param PulseWidthPrescaler This parameter can be one of the following values:
+ * @arg @ref LL_TIM_PWPRSC_X1
+ * @arg @ref LL_TIM_PWPRSC_X2
+ * @arg @ref LL_TIM_PWPRSC_X4
+ * @arg @ref LL_TIM_PWPRSC_X8
+ * @arg @ref LL_TIM_PWPRSC_X16
+ * @arg @ref LL_TIM_PWPRSC_X32
+ * @arg @ref LL_TIM_PWPRSC_X64
+ * @arg @ref LL_TIM_PWPRSC_X128
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetPulseWidthPrescaler(TIM_TypeDef *TIMx, uint32_t PulseWidthPrescaler)
+{
+ MODIFY_REG(TIMx->ECR, TIM_ECR_PWPRSC, PulseWidthPrescaler);
+}
+
+/**
+ * @brief Get the pulse on compare pulse width prescaler.
+ * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
+ * whether or not the pulse on compare feature is supported by the timer
+ * instance.
+ * @rmtoll ECR PWPRSC LL_TIM_OC_GetPulseWidthPrescaler
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_PWPRSC_X1
+ * @arg @ref LL_TIM_PWPRSC_X2
+ * @arg @ref LL_TIM_PWPRSC_X4
+ * @arg @ref LL_TIM_PWPRSC_X8
+ * @arg @ref LL_TIM_PWPRSC_X16
+ * @arg @ref LL_TIM_PWPRSC_X32
+ * @arg @ref LL_TIM_PWPRSC_X64
+ * @arg @ref LL_TIM_PWPRSC_X128
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidthPrescaler(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PWPRSC));
+}
+
+/**
+ * @brief Set the pulse on compare pulse width duration.
+ * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
+ * whether or not the pulse on compare feature is supported by the timer
+ * instance.
+ * @rmtoll ECR PW LL_TIM_OC_SetPulseWidth
+ * @param TIMx Timer instance
+ * @param PulseWidth This parameter can be between Min_Data=0 and Max_Data=255
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetPulseWidth(TIM_TypeDef *TIMx, uint32_t PulseWidth)
+{
+ MODIFY_REG(TIMx->ECR, TIM_ECR_PW, PulseWidth << TIM_ECR_PW_Pos);
+}
+
+/**
+ * @brief Get the pulse on compare pulse width duration.
+ * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
+ * whether or not the pulse on compare feature is supported by the timer
+ * instance.
+ * @rmtoll ECR PW LL_TIM_OC_GetPulseWidth
+ * @param TIMx Timer instance
+ * @retval Returned value can be between Min_Data=0 and Max_Data=255:
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidth(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PW));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
+ * @{
+ */
+/**
+ * @brief Configure input channel.
+ * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
+ * CCMR1 IC1PSC LL_TIM_IC_Config\n
+ * CCMR1 IC1F LL_TIM_IC_Config\n
+ * CCMR1 CC2S LL_TIM_IC_Config\n
+ * CCMR1 IC2PSC LL_TIM_IC_Config\n
+ * CCMR1 IC2F LL_TIM_IC_Config\n
+ * CCMR2 CC3S LL_TIM_IC_Config\n
+ * CCMR2 IC3PSC LL_TIM_IC_Config\n
+ * CCMR2 IC3F LL_TIM_IC_Config\n
+ * CCMR2 CC4S LL_TIM_IC_Config\n
+ * CCMR2 IC4PSC LL_TIM_IC_Config\n
+ * CCMR2 IC4F LL_TIM_IC_Config\n
+ * CCER CC1P LL_TIM_IC_Config\n
+ * CCER CC1NP LL_TIM_IC_Config\n
+ * CCER CC2P LL_TIM_IC_Config\n
+ * CCER CC2NP LL_TIM_IC_Config\n
+ * CCER CC3P LL_TIM_IC_Config\n
+ * CCER CC3NP LL_TIM_IC_Config\n
+ * CCER CC4P LL_TIM_IC_Config\n
+ * CCER CC4NP LL_TIM_IC_Config
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param Configuration This parameter must be a combination of all the following values:
+ * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
+ * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
+ * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
+ ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
+ << SHIFT_TAB_ICxx[iChannel]);
+ MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+ (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+ * @brief Set the active input.
+ * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
+ * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
+ * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
+ * CCMR2 CC4S LL_TIM_IC_SetActiveInput
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param ICActiveInput This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+ * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+ * @arg @ref LL_TIM_ACTIVEINPUT_TRC
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+ * @brief Get the current active input.
+ * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
+ * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
+ * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
+ * CCMR2 CC4S LL_TIM_IC_GetActiveInput
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+ * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+ * @arg @ref LL_TIM_ACTIVEINPUT_TRC
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+ * @brief Set the prescaler of input channel.
+ * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
+ * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
+ * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
+ * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param ICPrescaler This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ICPSC_DIV1
+ * @arg @ref LL_TIM_ICPSC_DIV2
+ * @arg @ref LL_TIM_ICPSC_DIV4
+ * @arg @ref LL_TIM_ICPSC_DIV8
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+ * @brief Get the current prescaler value acting on an input channel.
+ * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
+ * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
+ * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
+ * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_ICPSC_DIV1
+ * @arg @ref LL_TIM_ICPSC_DIV2
+ * @arg @ref LL_TIM_ICPSC_DIV4
+ * @arg @ref LL_TIM_ICPSC_DIV8
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+ * @brief Set the input filter duration.
+ * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
+ * CCMR1 IC2F LL_TIM_IC_SetFilter\n
+ * CCMR2 IC3F LL_TIM_IC_SetFilter\n
+ * CCMR2 IC4F LL_TIM_IC_SetFilter
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param ICFilter This parameter can be one of the following values:
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+ * @brief Get the input filter duration.
+ * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
+ * CCMR1 IC2F LL_TIM_IC_GetFilter\n
+ * CCMR2 IC3F LL_TIM_IC_GetFilter\n
+ * CCMR2 IC4F LL_TIM_IC_GetFilter
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+ * @brief Set the input channel polarity.
+ * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
+ * CCER CC1NP LL_TIM_IC_SetPolarity\n
+ * CCER CC2P LL_TIM_IC_SetPolarity\n
+ * CCER CC2NP LL_TIM_IC_SetPolarity\n
+ * CCER CC3P LL_TIM_IC_SetPolarity\n
+ * CCER CC3NP LL_TIM_IC_SetPolarity\n
+ * CCER CC4P LL_TIM_IC_SetPolarity\n
+ * CCER CC4NP LL_TIM_IC_SetPolarity
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param ICPolarity This parameter can be one of the following values:
+ * @arg @ref LL_TIM_IC_POLARITY_RISING
+ * @arg @ref LL_TIM_IC_POLARITY_FALLING
+ * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+ ICPolarity << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+ * @brief Get the current input channel polarity.
+ * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
+ * CCER CC1NP LL_TIM_IC_GetPolarity\n
+ * CCER CC2P LL_TIM_IC_GetPolarity\n
+ * CCER CC2NP LL_TIM_IC_GetPolarity\n
+ * CCER CC3P LL_TIM_IC_GetPolarity\n
+ * CCER CC3NP LL_TIM_IC_GetPolarity\n
+ * CCER CC4P LL_TIM_IC_GetPolarity\n
+ * CCER CC4NP LL_TIM_IC_GetPolarity
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_IC_POLARITY_RISING
+ * @arg @ref LL_TIM_IC_POLARITY_FALLING
+ * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
+ SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+ * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
+ * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an XOR input.
+ * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
+}
+
+/**
+ * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
+ * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an XOR input.
+ * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
+}
+
+/**
+ * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
+ * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an XOR input.
+ * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get captured value for input channel 1.
+ * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+ * input channel 1 is supported by a timer instance.
+ * @note If dithering is activated, pay attention to the returned value interpretation.
+ * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
+ * @param TIMx Timer instance
+ * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR1));
+}
+
+/**
+ * @brief Get captured value for input channel 2.
+ * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+ * input channel 2 is supported by a timer instance.
+ * @note If dithering is activated, pay attention to the returned value interpretation.
+ * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
+ * @param TIMx Timer instance
+ * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR2));
+}
+
+/**
+ * @brief Get captured value for input channel 3.
+ * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+ * input channel 3 is supported by a timer instance.
+ * @note If dithering is activated, pay attention to the returned value interpretation.
+ * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
+ * @param TIMx Timer instance
+ * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR3));
+}
+
+/**
+ * @brief Get captured value for input channel 4.
+ * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+ * input channel 4 is supported by a timer instance.
+ * @note If dithering is activated, pay attention to the returned value interpretation.
+ * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
+ * @param TIMx Timer instance
+ * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR4));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
+ * @{
+ */
+/**
+ * @brief Enable external clock mode 2.
+ * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
+ * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports external clock mode2.
+ * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+}
+
+/**
+ * @brief Disable external clock mode 2.
+ * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports external clock mode2.
+ * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+}
+
+/**
+ * @brief Indicate whether external clock mode 2 is enabled.
+ * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports external clock mode2.
+ * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set the clock source of the counter clock.
+ * @note when selected clock source is external clock mode 1, the timer input
+ * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
+ * function. This timer input must be configured by calling
+ * the @ref LL_TIM_IC_Config() function.
+ * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports external clock mode1.
+ * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports external clock mode2.
+ * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
+ * SMCR ECE LL_TIM_SetClockSource
+ * @param TIMx Timer instance
+ * @param ClockSource This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
+ * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
+ * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
+{
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
+}
+
+/**
+ * @brief Set the encoder interface mode.
+ * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports the encoder mode.
+ * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
+ * @param TIMx Timer instance
+ * @param EncoderMode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
+ * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
+ * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
+ * @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2
+ * @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1
+ * @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2
+ * @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12
+ * @arg @ref LL_TIM_ENCODERMODE_X1_TI1
+ * @arg @ref LL_TIM_ENCODERMODE_X1_TI2
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
+{
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
+ * @{
+ */
+/**
+ * @brief Set the trigger output (TRGO) used for timer synchronization .
+ * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance can operate as a master timer.
+ * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
+ * @param TIMx Timer instance
+ * @param TimerSynchronization This parameter can be one of the following values:
+ * @arg @ref LL_TIM_TRGO_RESET
+ * @arg @ref LL_TIM_TRGO_ENABLE
+ * @arg @ref LL_TIM_TRGO_UPDATE
+ * @arg @ref LL_TIM_TRGO_CC1IF
+ * @arg @ref LL_TIM_TRGO_OC1REF
+ * @arg @ref LL_TIM_TRGO_OC2REF
+ * @arg @ref LL_TIM_TRGO_OC3REF
+ * @arg @ref LL_TIM_TRGO_OC4REF
+ * @arg @ref LL_TIM_TRGO_ENCODERCLK
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
+{
+ MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
+}
+
+/**
+ * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
+ * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance can be used for ADC synchronization.
+ * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
+ * @param TIMx Timer Instance
+ * @param ADCSynchronization This parameter can be one of the following values:
+ * @arg @ref LL_TIM_TRGO2_RESET
+ * @arg @ref LL_TIM_TRGO2_ENABLE
+ * @arg @ref LL_TIM_TRGO2_UPDATE
+ * @arg @ref LL_TIM_TRGO2_CC1F
+ * @arg @ref LL_TIM_TRGO2_OC1
+ * @arg @ref LL_TIM_TRGO2_OC2
+ * @arg @ref LL_TIM_TRGO2_OC3
+ * @arg @ref LL_TIM_TRGO2_OC4
+ * @arg @ref LL_TIM_TRGO2_OC5
+ * @arg @ref LL_TIM_TRGO2_OC6
+ * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
+ * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
+ * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
+ * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
+ * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
+ * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
+{
+ MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
+}
+
+/**
+ * @brief Set the synchronization mode of a slave timer.
+ * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance can operate as a slave timer.
+ * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
+ * @param TIMx Timer instance
+ * @param SlaveMode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_SLAVEMODE_DISABLED
+ * @arg @ref LL_TIM_SLAVEMODE_RESET
+ * @arg @ref LL_TIM_SLAVEMODE_GATED
+ * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
+ * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
+ * @arg @ref LL_TIM_SLAVEMODE_COMBINED_GATEDRESET
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
+{
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
+}
+
+/**
+ * @brief Set the selects the trigger input to be used to synchronize the counter.
+ * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance can operate as a slave timer.
+ * @rmtoll SMCR TS LL_TIM_SetTriggerInput
+ * @param TIMx Timer instance
+ * @param TriggerInput This parameter can be one of the following values:
+ * @arg @ref LL_TIM_TS_ITR0
+ * @arg @ref LL_TIM_TS_ITR1
+ * @arg @ref LL_TIM_TS_ITR2
+ * @arg @ref LL_TIM_TS_ITR3
+ * @arg @ref LL_TIM_TS_TI1F_ED
+ * @arg @ref LL_TIM_TS_TI1FP1
+ * @arg @ref LL_TIM_TS_TI2FP2
+ * @arg @ref LL_TIM_TS_ETRF
+ * @arg @ref LL_TIM_TS_ITR4
+ * @arg @ref LL_TIM_TS_ITR5
+ * @arg @ref LL_TIM_TS_ITR6
+ * @arg @ref LL_TIM_TS_ITR7
+ * @arg @ref LL_TIM_TS_ITR8
+ * @arg @ref LL_TIM_TS_ITR11
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
+{
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
+}
+
+/**
+ * @brief Enable the Master/Slave mode.
+ * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance can operate as a slave timer.
+ * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+}
+
+/**
+ * @brief Disable the Master/Slave mode.
+ * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance can operate as a slave timer.
+ * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+}
+
+/**
+ * @brief Indicates whether the Master/Slave mode is enabled.
+ * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance can operate as a slave timer.
+ * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure the external trigger (ETR) input.
+ * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an external trigger input.
+ * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
+ * SMCR ETPS LL_TIM_ConfigETR\n
+ * SMCR ETF LL_TIM_ConfigETR
+ * @param TIMx Timer instance
+ * @param ETRPolarity This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
+ * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
+ * @param ETRPrescaler This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
+ * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
+ * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
+ * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
+ * @param ETRFilter This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV1
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
+ uint32_t ETRFilter)
+{
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
+}
+
+/**
+ * @brief Select the external trigger (ETR) input source.
+ * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
+ * not a timer instance supports ETR source selection.
+ * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource
+ * @param TIMx Timer instance
+ * @param ETRSource This parameter can be one of the following values:
+ *
+ * TIM1: any combination of ETR_RMP where
+ *
+ * @arg @ref LL_TIM_TIM1_ETRSOURCE_GPIO
+ * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP1
+ * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP2
+ * @arg @ref LL_TIM_TIM1_ETRSOURCE_MSIK
+ * @arg @ref LL_TIM_TIM1_ETRSOURCE_HSI
+ * @arg @ref LL_TIM_TIM1_ETRSOURCE_MSIS
+ * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1
+ * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2
+ * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3
+ * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD1
+ * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD2
+ * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD3
+ *
+ * TIM2: any combination of ETR_RMP where
+ *
+ * @arg @ref LL_TIM_TIM2_ETRSOURCE_GPIO
+ * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP1
+ * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP2
+ * @arg @ref LL_TIM_TIM2_ETRSOURCE_MSIK
+ * @arg @ref LL_TIM_TIM2_ETRSOURCE_HSI
+ * @arg @ref LL_TIM_TIM2_ETRSOURCE_MSIS
+ * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM3_ETR
+ * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM4_ETR
+ * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM5_ETR
+ * @arg @ref LL_TIM_TIM2_ETRSOURCE_LSE
+ *
+ * TIM3: any combination of ETR_RMP where
+ *
+ * @arg @ref LL_TIM_TIM3_ETRSOURCE_GPIO
+ * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP1
+ * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP2
+ * @arg @ref LL_TIM_TIM3_ETRSOURCE_MSIK
+ * @arg @ref LL_TIM_TIM3_ETRSOURCE_HSI
+ * @arg @ref LL_TIM_TIM3_ETRSOURCE_MSIS
+ * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM2_ETR
+ * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM4_ETR
+ * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC1_AWD1
+ * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC1_AWD2
+ * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC1_AWD3
+ *
+ * TIM4: any combination of ETR_RMP where
+ *
+ * @arg @ref LL_TIM_TIM4_ETRSOURCE_GPIO
+ * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP1
+ * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP2
+ * @arg @ref LL_TIM_TIM4_ETRSOURCE_MSIK
+ * @arg @ref LL_TIM_TIM4_ETRSOURCE_HSI
+ * @arg @ref LL_TIM_TIM4_ETRSOURCE_MSIS
+ * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM3_ETR
+ * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM5_ETR
+ *
+ * TIM5: any combination of ETR_RMP where
+ *
+ * @arg @ref LL_TIM_TIM5_ETRSOURCE_GPIO
+ * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP1
+ * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP2
+ * @arg @ref LL_TIM_TIM5_ETRSOURCE_MSIK
+ * @arg @ref LL_TIM_TIM5_ETRSOURCE_HSI
+ * @arg @ref LL_TIM_TIM5_ETRSOURCE_MSIS
+ * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM2_ETR
+ * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM3_ETR
+ *
+ * TIM8: any combination of ETR_RMP where
+ *
+ * . . ETR_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM8_ETRSOURCE_GPIO
+ * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP1
+ * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP2
+ * @arg @ref LL_TIM_TIM8_ETRSOURCE_MSIK
+ * @arg @ref LL_TIM_TIM8_ETRSOURCE_HSI
+ * @arg @ref LL_TIM_TIM8_ETRSOURCE_MSIS
+ * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC1_AWD1
+ * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC1_AWD2
+ * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC1_AWD3
+ * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC4_AWD1
+ * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC4_AWD2
+ * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC4_AWD3
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
+{
+ MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
+}
+
+/**
+ * @brief Enable SMS preload.
+ * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports the preload of SMS field in SMCR register.
+ * @rmtoll SMCR SMSPE LL_TIM_EnableSMSPreload
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableSMSPreload(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->SMCR, TIM_SMCR_SMSPE);
+}
+
+/**
+ * @brief Disable SMS preload.
+ * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports the preload of SMS field in SMCR register.
+ * @rmtoll SMCR SMSPE LL_TIM_DisableSMSPreload
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableSMSPreload(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->SMCR, TIM_SMCR_SMSPE);
+}
+
+/**
+ * @brief Indicate whether SMS preload is enabled.
+ * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports the preload of SMS field in SMCR register.
+ * @rmtoll SMCR SMSPE LL_TIM_IsEnabledSMSPreload
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledSMSPreload(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPE) == (TIM_SMCR_SMSPE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set the preload source of SMS.
+ * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports the preload of SMS field in SMCR register.
+ * @rmtoll SMCR SMSPS LL_TIM_SetSMSPreloadSource\n
+ * @param TIMx Timer instance
+ * @param PreloadSource This parameter can be one of the following values:
+ * @arg @ref LL_TIM_SMSPS_TIMUPDATE
+ * @arg @ref LL_TIM_SMSPS_INDEX
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetSMSPreloadSource(TIM_TypeDef *TIMx, uint32_t PreloadSource)
+{
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMSPS, PreloadSource);
+}
+
+/**
+ * @brief Get the preload source of SMS.
+ * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports the preload of SMS field in SMCR register.
+ * @rmtoll SMCR SMSPS LL_TIM_GetSMSPreloadSource\n
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_SMSPS_TIMUPDATE
+ * @arg @ref LL_TIM_SMSPS_INDEX
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetSMSPreloadSource(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPS));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Break_Function Break function configuration
+ * @{
+ */
+/**
+ * @brief Enable the break function.
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR BKE LL_TIM_EnableBRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+}
+
+/**
+ * @brief Disable the break function.
+ * @rmtoll BDTR BKE LL_TIM_DisableBRK
+ * @param TIMx Timer instance
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+}
+
+/**
+ * @brief Configure the break input.
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @note Bidirectional mode is only supported by advanced timer instances.
+ * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance is an advanced-control timer.
+ * @note In bidirectional mode (BKBID bit set), the Break input is configured both
+ * in input mode and in open drain output mode. Any active Break event will
+ * assert a low logic level on the Break input to indicate an internal break
+ * event to external devices.
+ * @note When bidirectional mode isn't supported, BreakAFMode must be set to
+ * LL_TIM_BREAK_AFMODE_INPUT.
+ * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
+ * BDTR BKF LL_TIM_ConfigBRK\n
+ * BDTR BKBID LL_TIM_ConfigBRK
+ * @param TIMx Timer instance
+ * @param BreakPolarity This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK_POLARITY_LOW
+ * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
+ * @param BreakFilter This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
+ * @param BreakAFMode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK_AFMODE_INPUT
+ * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter,
+ uint32_t BreakAFMode)
+{
+ MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode);
+}
+
+/**
+ * @brief Disarm the break input (when it operates in bidirectional mode).
+ * @note The break input can be disarmed only when it is configured in
+ * bidirectional mode and when when MOE is reset.
+ * @note Purpose is to be able to have the input voltage back to high-state,
+ * whatever the time constant on the output .
+ * @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
+}
+
+/**
+ * @brief Re-arm the break input (when it operates in bidirectional mode).
+ * @note The Break input is automatically armed as soon as MOE bit is set.
+ * @rmtoll BDTR BKDSRM LL_TIM_ReArmBRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
+}
+
+/**
+ * @brief Enable the break 2 function.
+ * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a second break input.
+ * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
+}
+
+/**
+ * @brief Disable the break 2 function.
+ * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a second break input.
+ * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
+}
+
+/**
+ * @brief Configure the break 2 input.
+ * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a second break input.
+ * @note Bidirectional mode is only supported by advanced timer instances.
+ * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance is an advanced-control timer.
+ * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
+ * in input mode and in open drain output mode. Any active Break event will
+ * assert a low logic level on the Break 2 input to indicate an internal break
+ * event to external devices.
+ * @note When bidirectional mode isn't supported, Break2AFMode must be set to
+ * LL_TIM_BREAK2_AFMODE_INPUT.
+ * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
+ * BDTR BK2F LL_TIM_ConfigBRK2\n
+ * BDTR BK2BID LL_TIM_ConfigBRK2
+ * @param TIMx Timer instance
+ * @param Break2Polarity This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
+ * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
+ * @param Break2Filter This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
+ * @param Break2AFMode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
+ * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,
+ uint32_t Break2AFMode)
+{
+ MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode);
+}
+
+/**
+ * @brief Disarm the break 2 input (when it operates in bidirectional mode).
+ * @note The break 2 input can be disarmed only when it is configured in
+ * bidirectional mode and when when MOE is reset.
+ * @note Purpose is to be able to have the input voltage back to high-state,
+ * whatever the time constant on the output.
+ * @rmtoll BDTR BK2DSRM LL_TIM_DisarmBRK2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
+}
+
+/**
+ * @brief Re-arm the break 2 input (when it operates in bidirectional mode).
+ * @note The Break 2 input is automatically armed as soon as MOE bit is set.
+ * @rmtoll BDTR BK2DSRM LL_TIM_ReArmBRK2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
+}
+
+/**
+ * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
+ * BDTR OSSR LL_TIM_SetOffStates
+ * @param TIMx Timer instance
+ * @param OffStateIdle This parameter can be one of the following values:
+ * @arg @ref LL_TIM_OSSI_DISABLE
+ * @arg @ref LL_TIM_OSSI_ENABLE
+ * @param OffStateRun This parameter can be one of the following values:
+ * @arg @ref LL_TIM_OSSR_DISABLE
+ * @arg @ref LL_TIM_OSSR_ENABLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
+{
+ MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
+}
+
+/**
+ * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
+}
+
+/**
+ * @brief Disable automatic output (MOE can be set only by software).
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
+}
+
+/**
+ * @brief Indicate whether automatic output is enabled.
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
+ * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
+ * software and is reset in case of break or break2 event
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
+}
+
+/**
+ * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
+ * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
+ * software and is reset in case of break or break2 event.
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
+}
+
+/**
+ * @brief Indicates whether outputs are enabled.
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable the signals connected to the designated timer break input.
+ * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance allows for break input selection.
+ * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n
+ * AF1 BKCMP1E LL_TIM_EnableBreakInputSource\n
+ * AF1 BKCMP2E LL_TIM_EnableBreakInputSource\n
+ * AF1 BKDF1BK0E LL_TIM_EnableBreakInputSource\n
+ * AF2 BK2INE LL_TIM_EnableBreakInputSource\n
+ * AF2 BK2CMP1E LL_TIM_EnableBreakInputSource\n
+ * AF2 BK2CMP2E LL_TIM_EnableBreakInputSource\n
+ * AF2 BK2DF1BK1E LL_TIM_EnableBreakInputSource
+ * @param TIMx Timer instance
+ * @param BreakInput This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK_INPUT_BKIN
+ * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
+ * @arg @ref LL_TIM_BKIN_SOURCE_MDF1
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
+{
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+ SET_BIT(*pReg, Source);
+}
+
+/**
+ * @brief Disable the signals connected to the designated timer break input.
+ * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance allows for break input selection.
+ * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n
+ * AF1 BKCMP1E LL_TIM_DisableBreakInputSource\n
+ * AF1 BKCMP2E LL_TIM_DisableBreakInputSource\n
+ * AF1 BKDF1BK0E LL_TIM_DisableBreakInputSource\n
+ * AF2 BK2INE LL_TIM_DisableBreakInputSource\n
+ * AF2 BK2CMP1E LL_TIM_DisableBreakInputSource\n
+ * AF2 BK2CMP2E LL_TIM_DisableBreakInputSource\n
+ * AF2 BK2DF1BK1E LL_TIM_DisableBreakInputSource
+ * @param TIMx Timer instance
+ * @param BreakInput This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK_INPUT_BKIN
+ * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
+ * @arg @ref LL_TIM_BKIN_SOURCE_MDF1
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
+{
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+ CLEAR_BIT(*pReg, Source);
+}
+
+/**
+ * @brief Set the polarity of the break signal for the timer break input.
+ * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance allows for break input selection.
+ * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n
+ * AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n
+ * AF1 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n
+ * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
+ * AF2 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n
+ * AF2 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity
+ * @param TIMx Timer instance
+ * @param BreakInput This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK_INPUT_BKIN
+ * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BKIN_POLARITY_LOW
+ * @arg @ref LL_TIM_BKIN_POLARITY_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
+ uint32_t Polarity)
+{
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+ MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
+}
+/**
+ * @brief Enable asymmetrical deadtime.
+ * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides asymmetrical deadtime.
+ * @rmtoll DTR2 DTAE LL_TIM_EnableAsymmetricalDeadTime
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableAsymmetricalDeadTime(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE);
+}
+
+/**
+ * @brief Disable asymmetrical dead-time.
+ * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides asymmetrical deadtime.
+ * @rmtoll DTR2 DTAE LL_TIM_DisableAsymmetricalDeadTime
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableAsymmetricalDeadTime(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE);
+}
+
+/**
+ * @brief Indicates whether asymmetrical deadtime is activated.
+ * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides asymmetrical deadtime.
+ * @rmtoll DTR2 DTAE LL_TIM_IsEnabledAsymmetricalDeadTime
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAsymmetricalDeadTime(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and the
+ * rising edge of OCxN signals).
+ * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
+ * asymmetrical dead-time insertion feature is supported by a timer instance.
+ * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
+ * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
+ * (LOCK bits in TIMx_BDTR register).
+ * @rmtoll DTR2 DTGF LL_TIM_SetFallingDeadTime
+ * @param TIMx Timer instance
+ * @param DeadTime between Min_Data=0 and Max_Data=255
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetFallingDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
+{
+ MODIFY_REG(TIMx->DTR2, TIM_DTR2_DTGF, DeadTime);
+}
+
+/**
+ * @brief Get the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and
+ * the rising edge of OCxN signals).
+ * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
+ * asymmetrical dead-time insertion feature is supported by a timer instance.
+ * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
+ * (LOCK bits in TIMx_BDTR register).
+ * @rmtoll DTR2 DTGF LL_TIM_GetFallingDeadTime
+ * @param TIMx Timer instance
+ * @retval Returned value can be between Min_Data=0 and Max_Data=255:
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetFallingDeadTime(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->DTR2, TIM_DTR2_DTGF));
+}
+
+/**
+ * @brief Enable deadtime preload.
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides deadtime preload.
+ * @rmtoll DTR2 DTPE LL_TIM_EnableDeadTimePreload
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDeadTimePreload(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DTR2, TIM_DTR2_DTPE);
+}
+
+/**
+ * @brief Disable dead-time preload.
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides deadtime preload.
+ * @rmtoll DTR2 DTPE LL_TIM_DisableDeadTimePreload
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDeadTimePreload(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTPE);
+}
+
+/**
+ * @brief Indicates whether deadtime preload is activated.
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides deadtime preload.
+ * @rmtoll DTR2 DTPE LL_TIM_IsEnabledDeadTimePreload
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDeadTimePreload(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTPE) == (TIM_DTR2_DTPE)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
+ * @{
+ */
+/**
+ * @brief Configures the timer DMA burst feature.
+ * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
+ * not a timer instance supports the DMA burst mode.
+ * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
+ * DCR DBA LL_TIM_ConfigDMABurst
+ * @param TIMx Timer instance
+ * @param DMABurstBaseAddress This parameter can be one of the following values:
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_DTR2
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_ECR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_OR1
+ * @param DMABurstLength This parameter can be one of the following values:
+ * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
+ * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_19TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_20TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_21TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_22TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_23TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_24TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_25TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_26TRANSFERS
+ * @param DMABurstSource This parameter can be one of the following values:
+ * @arg @ref LL_TIM_DMA_UPDATE
+ * @arg @ref LL_TIM_DMA_CC1
+ * @arg @ref LL_TIM_DMA_CC2
+ * @arg @ref LL_TIM_DMA_CC3
+ * @arg @ref LL_TIM_DMA_CC4
+ * @arg @ref LL_TIM_DMA_COM
+ * @arg @ref LL_TIM_DMA_TRIGGER
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength,
+ uint32_t DMABurstSource)
+{
+ MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA | TIM_DCR_DBSS),
+ (DMABurstBaseAddress | DMABurstLength | DMABurstSource));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Encoder Encoder configuration
+ * @{
+ */
+
+/**
+ * @brief Enable encoder index.
+ * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an index input.
+ * @rmtoll ECR IE LL_TIM_EnableEncoderIndex
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableEncoderIndex(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->ECR, TIM_ECR_IE);
+}
+
+/**
+ * @brief Disable encoder index.
+ * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an index input.
+ * @rmtoll ECR IE LL_TIM_DisableEncoderIndex
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableEncoderIndex(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->ECR, TIM_ECR_IE);
+}
+
+/**
+ * @brief Indicate whether encoder index is enabled.
+ * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an index input.
+ * @rmtoll ECR IE LL_TIM_IsEnabledEncoderIndex
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledEncoderIndex(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->ECR, TIM_ECR_IE) == (TIM_ECR_IE)) ? 1U : 0U);
+}
+
+/**
+ * @brief Set index direction
+ * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an index input.
+ * @rmtoll ECR IDIR LL_TIM_SetIndexDirection
+ * @param TIMx Timer instance
+ * @param IndexDirection This parameter can be one of the following values:
+ * @arg @ref LL_TIM_INDEX_UP_DOWN
+ * @arg @ref LL_TIM_INDEX_UP
+ * @arg @ref LL_TIM_INDEX_DOWN
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetIndexDirection(TIM_TypeDef *TIMx, uint32_t IndexDirection)
+{
+ MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR, IndexDirection);
+}
+
+/**
+ * @brief Get actual index direction
+ * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an index input.
+ * @rmtoll ECR IDIR LL_TIM_GetIndexDirection
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_INDEX_UP_DOWN
+ * @arg @ref LL_TIM_INDEX_UP
+ * @arg @ref LL_TIM_INDEX_DOWN
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetIndexDirection(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IDIR));
+}
+
+/**
+ * @brief Set index blanking
+ * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an index input.
+ * @rmtoll ECR IBLK LL_TIM_SetIndexBlanking
+ * @param TIMx Timer instance
+ * @param Indexblanking This parameter can be one of the following values:
+ * @arg @ref LL_TIM_INDEX_BLANK_ALWAYS
+ * @arg @ref LL_TIM_INDEX_BLANK_TI3
+ * @arg @ref LL_TIM_INDEX_BLANK_TI4
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetIndexblanking(TIM_TypeDef *TIMx, uint32_t Indexblanking)
+{
+ MODIFY_REG(TIMx->ECR, TIM_ECR_IBLK, Indexblanking);
+}
+
+/**
+ * @brief Get actual index blanking
+ * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an index input.
+ * @rmtoll ECR IBLK LL_TIM_GetIndexblanking
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_INDEX_BLANK_ALWAYS
+ * @arg @ref LL_TIM_INDEX_BLANK_TI3
+ * @arg @ref LL_TIM_INDEX_BLANK_TI4
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetIndexblanking(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IBLK));
+}
+
+
+/**
+ * @brief Enable first index.
+ * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an index input.
+ * @rmtoll ECR FIDX LL_TIM_EnableFirstIndex
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableFirstIndex(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->ECR, TIM_ECR_FIDX);
+}
+
+/**
+ * @brief Disable first index.
+ * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an index input.
+ * @rmtoll ECR FIDX LL_TIM_DisableFirstIndex
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableFirstIndex(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->ECR, TIM_ECR_FIDX);
+}
+
+/**
+ * @brief Indicates whether first index is enabled.
+ * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an index input.
+ * @rmtoll ECR FIDX LL_TIM_IsEnabledFirstIndex
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledFirstIndex(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->ECR, TIM_ECR_FIDX) == (TIM_ECR_FIDX)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set index positioning
+ * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an index input.
+ * @rmtoll ECR IPOS LL_TIM_SetIndexPositionning
+ * @param TIMx Timer instance
+ * @param IndexPositionning This parameter can be one of the following values:
+ * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN
+ * @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP
+ * @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN
+ * @arg @ref LL_TIM_INDEX_POSITION_UP_UP
+ * @arg @ref LL_TIM_INDEX_POSITION_DOWN
+ * @arg @ref LL_TIM_INDEX_POSITION_UP
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetIndexPositionning(TIM_TypeDef *TIMx, uint32_t IndexPositionning)
+{
+ MODIFY_REG(TIMx->ECR, TIM_ECR_IPOS, IndexPositionning);
+}
+
+/**
+ * @brief Get actual index positioning
+ * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an index input.
+ * @rmtoll ECR IPOS LL_TIM_GetIndexPositionning
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN
+ * @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP
+ * @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN
+ * @arg @ref LL_TIM_INDEX_POSITION_UP_UP
+ * @arg @ref LL_TIM_INDEX_POSITION_DOWN
+ * @arg @ref LL_TIM_INDEX_POSITION_UP
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetIndexPositionning(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IPOS));
+}
+
+/**
+ * @brief Configure encoder index.
+ * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an index input.
+ * @rmtoll ECR IDIR LL_TIM_ConfigIDX\n
+ * ECR IBLK LL_TIM_ConfigIDX\n
+ * ECR FIDX LL_TIM_ConfigIDX\n
+ * ECR IPOS LL_TIM_ConfigIDX
+ * @param TIMx Timer instance
+ * @param Configuration This parameter must be a combination of all the following values:
+ * @arg @ref LL_TIM_INDEX_UP or @ref LL_TIM_INDEX_DOWN or @ref LL_TIM_INDEX_UP_DOWN
+ * @arg @ref LL_TIM_INDEX_BLANK_ALWAYS or @ref LL_TIM_INDEX_BLANK_TI3 or @ref LL_TIM_INDEX_BLANK_TI4
+ * @arg @ref LL_TIM_INDEX_ALL or @ref LL_TIM_INDEX_FIRST_ONLY
+ * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN or ... or @ref LL_TIM_INDEX_POSITION_UP
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration)
+{
+ MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_IBLK | TIM_ECR_FIDX | TIM_ECR_IPOS, Configuration);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
+ * @{
+ */
+/**
+ * @brief Remap TIM inputs (input channel, internal/external triggers).
+ * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
+ * a some timer inputs can be remapped.
+ * @rmtoll TIM1_TISEL TI1SEL LL_TIM_SetRemap\n
+ * TIM2_TISEL TI1SEL LL_TIM_SetRemap\n
+ * TIM2_TISEL TI2SEL LL_TIM_SetRemap\n
+ * TIM2_TISEL TI4SEL LL_TIM_SetRemap\n
+ * TIM3_TISEL TI1SEL LL_TIM_SetRemap\n
+ * TIM3_TISEL TI2SEL LL_TIM_SetRemap\n
+ * TIM4_TISEL TI1SEL LL_TIM_SetRemap\n
+ * TIM4_TISEL TI2SEL LL_TIM_SetRemap\n
+ * TIM5_TISEL TI1SEL LL_TIM_SetRemap\n
+ * TIM5_TISEL TI2SEL LL_TIM_SetRemap\n
+ * TIM8_TISEL TI1SEL LL_TIM_SetRemap\n
+ * TIM15_TISEL TI1SEL LL_TIM_SetRemap\n
+ * TIM15_TISEL TI2SEL LL_TIM_SetRemap\n
+ * TIM16_TISEL TI1SEL LL_TIM_SetRemap\n
+ * TIM17_TISEL TI1SEL LL_TIM_SetRemap\n
+ *
+ * @param TIMx Timer instance
+ * @param Remap Remap param depends on the TIMx. Description available only
+ * in CHM version of the User Manual (not in .pdf).
+ * Otherwise see Reference Manual description of TISEL registers.
+ *
+ * Below description summarizes "Timer Instance" and "Remap" param combinations:
+ *
+ * TIM1: one of the following values:
+ * @arg LL_TIM_TIM1_TI1_RMP_GPIO: TIM1 TI1 is connected to GPIO
+ * @arg LL_TIM_TIM1_TI1_RMP_COMP1: TIM1 TI1 is connected to COMP1 output
+ * @arg LL_TIM_TIM1_TI1_RMP_COMP2: TIM1 TI1 is connected to COMP2 output
+ *
+ * TIM2: one of the following values:
+ * @arg LL_TIM_TIM2_TI1_RMP_GPIO: TIM2 TI1 is connected to GPIO
+ * @arg LL_TIM_TIM2_TI1_RMP_COMP1: TIM2 TI1 is connected to COMP1 output
+ * @arg LL_TIM_TIM2_TI1_RMP_COMP2: TIM2 TI1 is connected to COMP2 output
+ * @arg LL_TIM_TIM2_TI2_RMP_GPIO: TIM2 TI2 is connected to GPIO
+ * @arg LL_TIM_TIM2_TI2_RMP_COMP1: TIM2 TI2 is connected to COMP1 output
+ * @arg LL_TIM_TIM2_TI2_RMP_COMP2: TIM2 TI2 is connected to COMP2 output
+ * @arg LL_TIM_TIM2_TI4_RMP_GPIO: TIM2 TI4 is connected to GPIO
+ * @arg LL_TIM_TIM2_TI4_RMP_COMP1: TIM2 TI4 is connected to COMP1 output
+ * @arg LL_TIM_TIM2_TI4_RMP_COMP2: TIM2 TI4 is connected to COMP2 output
+ *
+ * TIM3: one of the following values:
+ * @arg LL_TIM_TIM3_TI1_RMP_GPIO: TIM3 TI1 is connected to GPIO
+ * @arg LL_TIM_TIM3_TI1_RMP_COMP1: TIM3 TI1 is connected to COMP1 output
+ * @arg LL_TIM_TIM3_TI1_RMP_COMP2: TIM3 TI1 is connected to COMP2 output
+ * @arg LL_TIM_TIM3_TI2_RMP_GPIO: TIM3 TI2 is connected to GPIO
+ * @arg LL_TIM_TIM3_TI2_RMP_COMP1: TIM3 TI2 is connected to COMP1 output
+ * @arg LL_TIM_TIM3_TI2_RMP_COMP2: TIM3 TI2 is connected to COMP2 output
+ *
+ * TIM4: one of the following values:
+ * @arg LL_TIM_TIM4_TI1_RMP_GPIO: TIM4 TI1 is connected to GPIO
+ * @arg LL_TIM_TIM4_TI1_RMP_COMP1: TIM4 TI1 is connected to COMP1 output
+ * @arg LL_TIM_TIM4_TI1_RMP_COMP2: TIM4 TI1 is connected to COMP2 output
+ * @arg LL_TIM_TIM4_TI2_RMP_GPIO: TIM4 TI2 is connected to GPIO
+ * @arg LL_TIM_TIM4_TI2_RMP_COMP1: TIM4 TI2 is connected to COMP1 output
+ * @arg LL_TIM_TIM4_TI2_RMP_COMP2: TIM4 TI2 is connected to COMP2 output
+ *
+ * TIM5: one of the following values:
+ * @arg LL_TIM_TIM5_TI1_RMP_GPIO: TIM5 TI1 is connected to GPIO
+ * @arg LL_TIM_TIM5_TI1_RMP_LSI: TIM5 TI1 is connected to LSI
+ * @arg LL_TIM_TIM5_TI1_RMP_LSE: TIM5 TI1 is connected to LSE
+ * @arg LL_TIM_TIM5_TI1_RMP_RTC: TIM5 TI1 is connected to RTC Wakeup
+ * @arg LL_TIM_TIM5_TI1_RMP_COMP1: TIM5 TI1 is connected to COMP1 output
+ * @arg LL_TIM_TIM5_TI1_RMP_COMP2: TIM5 TI1 is connected to COMP2 output
+ * @arg LL_TIM_TIM5_TI2_RMP_GPIO: TIM5 TI2 is connected to GPIO
+ * @arg LL_TIM_TIM5_TI2_RMP_COMP1: TIM5 TI2 is connected to COMP1 output
+ * @arg LL_TIM_TIM5_TI2_RMP_COMP2: TIM5 TI2 is connected to COMP2 output
+ *
+ * TIM8: one of the following values:
+ * @arg TIM_TIM8_TI1_RMP_GPIO: TIM8 TI1 is connected to GPIO
+ * @arg TIM_TIM8_TI1_RMP_COMP2: TIM8 TI1 is connected to COMP2 output
+ *
+ * TIM15: one of the following values:
+ * @arg LL_TIM_TIM15_TI1_RMP_GPIO: TIM15 TI1 is connected to GPIO
+ * @arg LL_TIM_TIM15_TI1_RMP_LSE: TIM15 TI1 is connected to LSE
+ * @arg LL_TIM_TIM15_TI1_RMP_COMP1: TIM15 TI1 is connected to COMP1 output
+ * @arg LL_TIM_TIM15_TI1_RMP_COMP2: TIM15 TI1 is connected to COMP2 output
+ * @arg LL_TIM_TIM15_TI2_RMP_GPIO: TIM15 TI2 is connected to GPIO
+ * @arg LL_TIM_TIM15_TI2_RMP_COMP2: TIM15 TI2 is connected to COMP2 output
+ *
+ * TIM16: one of the following values:
+ * @arg LL_TIM_TIM16_TI1_RMP_GPIO: TIM16 TI1 is connected to GPIO
+ * @arg LL_TIM_TIM16_TI1_RMP_MCO: TIM16 TI1 is connected to MCO
+ * @arg LL_TIM_TIM16_TI1_RMP_HSE_DIV32: TIM16 TI1 is connected to HSE DIV32
+ * @arg LL_TIM_TIM16_TI1_RMP_RTC: TIM16 TI1 is connected to RTC
+ * @arg LL_TIM_TIM16_TI1_RMP_LSE: TIM16 TI1 is connected to LSE
+ * @arg LL_TIM_TIM16_TI1_RMP_LSI: TIM16 TI1 is connected to LSI
+ * @arg LL_TIM_TIM16_TI1_RMP_MSIS_1024: TIM16 TI1 is connected to MSIS/1024
+ * @arg LL_TIM_TIM16_TI1_RMP_MSIS_4: TIM16 TI1 is connected to MSIS/4
+ * @arg LL_TIM_TIM16_TI1_RMP_HSI_256: TIM16 TI1 is connected to HSI/256
+ *
+ * TIM17: one of the following values:
+ * @arg LL_TIM_TIM17_TI1_RMP_GPIO: TIM17 TI1 is connected to GPIO
+ * @arg LL_TIM_TIM17_TI1_RMP_MCO: TIM17 TI1 is connected to MCO
+ * @arg LL_TIM_TIM17_TI1_RMP_HSE_DIV32: TIM17 TI1 is connected to HSE DIV32
+ * @arg LL_TIM_TIM17_TI1_RMP_RTC: TIM17 TI1 is connected to RTC
+ * @arg LL_TIM_TIM17_TI1_RMP_LSE: TIM17 TI1 is connected to LSE
+ * @arg LL_TIM_TIM17_TI1_RMP_LSI: TIM17 TI1 is connected to LSI
+ * @arg LL_TIM_TIM17_TI1_RMP_MSIS_1024: TIM17 TI1 is connected to MSIS/1024
+ * @arg LL_TIM_TIM17_TI1_RMP_MSIS_4: TIM17 TI1 is connected to MSIS/4
+ * @arg LL_TIM_TIM17_TI1_RMP_HSI_256: TIM17 TI1 is connected to HSI/256
+ *
+ *
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
+{
+ MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap);
+}
+
+/**
+ * @brief Enable request for HSE/32 clock used for TISEL remap.
+ * @note Only TIM16 and TIM17 support HSE/32 remap
+ * @note The Cut1.x contains a limitation when using HSE/32 as input capture for TIM16
+ * @note Bug ID 56: On TIM16, the HSE/32 input capture requires the set of HSE32EN bit of TIM17 Option Register
+ * @rmtoll OR HSE32EN LL_TIM_EnableHSE32
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableHSE32(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->OR1, TIM_OR1_HSE32EN);
+}
+
+/**
+ * @brief Disable request for HSE/32 clock used for TISEL remap.
+ * @note Only TIM16 and TIM17 support HSE/32 remap
+ * @rmtoll OR HSE32EN LL_TIM_DisableHSE32
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableHSE32(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->OR1, TIM_OR1_HSE32EN);
+}
+
+/**
+ * @brief Indicate whether request for HSE/32 clock is enabled.
+ * @note Only TIM16 and TIM17 support HSE/32 remap
+ * @rmtoll OR HSE32EN LL_TIM_IsEnabledHSE32
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledHSE32(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->OR1, TIM_OR1_HSE32EN) == (TIM_OR1_HSE32EN)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
+ * @{
+ */
+/**
+ * @brief Set the OCREF clear input source
+ * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
+ * @note This function can only be used in Output compare and PWM modes.
+ * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
+ * @rmtoll AF2 OCRSEL LL_TIM_SetOCRefClearInputSource
+ * @param TIMx Timer instance
+ * @param OCRefClearInputSource This parameter can be one of the following values:
+ * @arg @ref LL_TIM_OCREF_CLR_INT_ETR
+ * @arg @ref LL_TIM_OCREF_CLR_INT_COMP1
+ * @arg @ref LL_TIM_OCREF_CLR_INT_COMP2
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
+{
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS,
+ ((OCRefClearInputSource & OCREF_CLEAR_SELECT_MSK) >> OCREF_CLEAR_SELECT_POS) << TIM_SMCR_OCCS_Pos);
+ MODIFY_REG(TIMx->AF2, TIM1_AF2_OCRSEL, OCRefClearInputSource);
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
+ * @{
+ */
+/**
+ * @brief Clear the update interrupt flag (UIF).
+ * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
+}
+
+/**
+ * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
+ * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
+ * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
+ * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
+ * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
+ * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
+ * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
+ * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
+ * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
+ * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
+ * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
+ * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
+ * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
+ * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the commutation interrupt flag (COMIF).
+ * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
+}
+
+/**
+ * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
+ * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the trigger interrupt flag (TIF).
+ * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
+}
+
+/**
+ * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
+ * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the break interrupt flag (BIF).
+ * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
+}
+
+/**
+ * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
+ * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the break 2 interrupt flag (B2IF).
+ * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
+}
+
+/**
+ * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
+ * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
+ * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
+ * (Capture/Compare 1 interrupt is pending).
+ * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
+ * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
+ * (Capture/Compare 2 over-capture interrupt is pending).
+ * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
+ * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
+ * (Capture/Compare 3 over-capture interrupt is pending).
+ * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
+ * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
+ * (Capture/Compare 4 over-capture interrupt is pending).
+ * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the system break interrupt flag (SBIF).
+ * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
+}
+
+/**
+ * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
+ * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the transition error interrupt flag (TERRF).
+ * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides encoder error management.
+ * @rmtoll SR TERRF LL_TIM_ClearFlag_TERR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_TERR(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_TERRF));
+}
+
+/**
+ * @brief Indicate whether transition error interrupt flag (TERRF) is set (transition error interrupt is pending).
+ * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides encoder error management.
+ * @rmtoll SR TERRF LL_TIM_IsActiveFlag_TERR
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TERR(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SR, TIM_SR_TERRF) == (TIM_SR_TERRF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the index error interrupt flag (IERRF).
+ * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides encoder error management.
+ * @rmtoll SR IERRF LL_TIM_ClearFlag_IERR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_IERR(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_IERRF));
+}
+
+/**
+ * @brief Indicate whether index error interrupt flag (IERRF) is set (index error interrupt is pending).
+ * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides encoder error management.
+ * @rmtoll SR IERRF LL_TIM_IsActiveFlag_IERR
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IERR(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SR, TIM_SR_IERRF) == (TIM_SR_IERRF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the direction change interrupt flag (DIRF).
+ * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides encoder interrupt management.
+ * @rmtoll SR DIRF LL_TIM_ClearFlag_DIR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_DIR(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_DIRF));
+}
+
+/**
+ * @brief Indicate whether direction change interrupt flag (DIRF) is set (direction change interrupt is pending).
+ * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides encoder interrupt management.
+ * @rmtoll SR DIRF LL_TIM_IsActiveFlag_DIR
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_DIR(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SR, TIM_SR_DIRF) == (TIM_SR_DIRF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the index interrupt flag (IDXF).
+ * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides encoder interrupt management.
+ * @rmtoll SR IDXF LL_TIM_ClearFlag_IDX
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_IDX(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_IDXF));
+}
+
+/**
+ * @brief Indicate whether index interrupt flag (IDXF) is set (index interrupt is pending).
+ * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides encoder interrupt management.
+ * @rmtoll SR IDXF LL_TIM_IsActiveFlag_IDX
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IDX(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SR, TIM_SR_IDXF) == (TIM_SR_IDXF)) ? 1UL : 0UL);
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_IT_Management IT-Management
+ * @{
+ */
+/**
+ * @brief Enable update interrupt (UIE).
+ * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_UIE);
+}
+
+/**
+ * @brief Disable update interrupt (UIE).
+ * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
+}
+
+/**
+ * @brief Indicates whether the update interrupt (UIE) is enabled.
+ * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable capture/compare 1 interrupt (CC1IE).
+ * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
+}
+
+/**
+ * @brief Disable capture/compare 1 interrupt (CC1IE).
+ * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
+ * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable capture/compare 2 interrupt (CC2IE).
+ * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
+}
+
+/**
+ * @brief Disable capture/compare 2 interrupt (CC2IE).
+ * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
+ * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable capture/compare 3 interrupt (CC3IE).
+ * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
+}
+
+/**
+ * @brief Disable capture/compare 3 interrupt (CC3IE).
+ * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
+ * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable capture/compare 4 interrupt (CC4IE).
+ * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
+}
+
+/**
+ * @brief Disable capture/compare 4 interrupt (CC4IE).
+ * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
+ * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable commutation interrupt (COMIE).
+ * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
+}
+
+/**
+ * @brief Disable commutation interrupt (COMIE).
+ * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
+}
+
+/**
+ * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
+ * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable trigger interrupt (TIE).
+ * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_TIE);
+}
+
+/**
+ * @brief Disable trigger interrupt (TIE).
+ * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
+}
+
+/**
+ * @brief Indicates whether the trigger interrupt (TIE) is enabled.
+ * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable break interrupt (BIE).
+ * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_BIE);
+}
+
+/**
+ * @brief Disable break interrupt (BIE).
+ * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
+}
+
+/**
+ * @brief Indicates whether the break interrupt (BIE) is enabled.
+ * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable transition error interrupt (TERRIE).
+ * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides encoder error management.
+ * @rmtoll DIER TERRIE LL_TIM_EnableIT_TERR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_TERR(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_TERRIE);
+}
+
+/**
+ * @brief Disable transition error interrupt (TERRIE).
+ * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides encoder error management.
+ * @rmtoll DIER TERRIE LL_TIM_DisableIT_TERR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_TERR(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_TERRIE);
+}
+
+/**
+ * @brief Indicates whether the transition error interrupt (TERRIE) is enabled.
+ * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides encoder error management.
+ * @rmtoll DIER TERRIE LL_TIM_IsEnabledIT_TERR
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TERR(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_TERRIE) == (TIM_DIER_TERRIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable index error interrupt (IERRIE).
+ * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides encoder error management.
+ * @rmtoll DIER IERRIE LL_TIM_EnableIT_IERR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_IERR(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_IERRIE);
+}
+
+/**
+ * @brief Disable index error interrupt (IERRIE).
+ * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides encoder error management.
+ * @rmtoll DIER IERRIE LL_TIM_DisableIT_IERR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_IERR(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_IERRIE);
+}
+
+/**
+ * @brief Indicates whether the index error interrupt (IERRIE) is enabled.
+ * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides encoder error management.
+ * @rmtoll DIER IERRIE LL_TIM_IsEnabledIT_IERR
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IERR(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_IERRIE) == (TIM_DIER_IERRIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable direction change interrupt (DIRIE).
+ * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides encoder interrupt management.
+ * @rmtoll DIER DIRIE LL_TIM_EnableIT_DIR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_DIR(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_DIRIE);
+}
+
+/**
+ * @brief Disable direction change interrupt (DIRIE).
+ * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides encoder interrupt management.
+ * @rmtoll DIER DIRIE LL_TIM_DisableIT_DIR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_DIR(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_DIRIE);
+}
+
+/**
+ * @brief Indicates whether the direction change interrupt (DIRIE) is enabled.
+ * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides encoder interrupt management.
+ * @rmtoll DIER DIRIE LL_TIM_IsEnabledIT_DIR
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_DIR(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_DIRIE) == (TIM_DIER_DIRIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable index interrupt (IDXIE).
+ * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides encoder interrupt management.
+ * @rmtoll DIER IDXIE LL_TIM_EnableIT_IDX
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_IDX(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_IDXIE);
+}
+
+/**
+ * @brief Disable index interrupt (IDXIE).
+ * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides encoder interrupt management.
+ * @rmtoll DIER IDXIE LL_TIM_DisableIT_IDX
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_IDX(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_IDXIE);
+}
+
+/**
+ * @brief Indicates whether the index interrupt (IDXIE) is enabled.
+ * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides encoder interrupt management.
+ * @rmtoll DIER IDXIE LL_TIM_IsEnabledIT_IDX
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IDX(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_IDXIE) == (TIM_DIER_IDXIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_DMA_Management DMA Management
+ * @{
+ */
+/**
+ * @brief Enable update DMA request (UDE).
+ * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_UDE);
+}
+
+/**
+ * @brief Disable update DMA request (UDE).
+ * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
+}
+
+/**
+ * @brief Indicates whether the update DMA request (UDE) is enabled.
+ * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable capture/compare 1 DMA request (CC1DE).
+ * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
+}
+
+/**
+ * @brief Disable capture/compare 1 DMA request (CC1DE).
+ * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
+ * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable capture/compare 2 DMA request (CC2DE).
+ * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
+}
+
+/**
+ * @brief Disable capture/compare 2 DMA request (CC2DE).
+ * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
+ * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable capture/compare 3 DMA request (CC3DE).
+ * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
+}
+
+/**
+ * @brief Disable capture/compare 3 DMA request (CC3DE).
+ * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
+ * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable capture/compare 4 DMA request (CC4DE).
+ * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
+}
+
+/**
+ * @brief Disable capture/compare 4 DMA request (CC4DE).
+ * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
+ * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable commutation DMA request (COMDE).
+ * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
+}
+
+/**
+ * @brief Disable commutation DMA request (COMDE).
+ * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
+}
+
+/**
+ * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
+ * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable trigger interrupt (TDE).
+ * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_TDE);
+}
+
+/**
+ * @brief Disable trigger interrupt (TDE).
+ * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
+}
+
+/**
+ * @brief Indicates whether the trigger interrupt (TDE) is enabled.
+ * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
+ * @{
+ */
+/**
+ * @brief Generate an update event.
+ * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_UG);
+}
+
+/**
+ * @brief Generate Capture/Compare 1 event.
+ * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
+}
+
+/**
+ * @brief Generate Capture/Compare 2 event.
+ * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
+}
+
+/**
+ * @brief Generate Capture/Compare 3 event.
+ * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
+}
+
+/**
+ * @brief Generate Capture/Compare 4 event.
+ * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
+}
+
+/**
+ * @brief Generate commutation event.
+ * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_COMG);
+}
+
+/**
+ * @brief Generate trigger event.
+ * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_TG);
+}
+
+/**
+ * @brief Generate break event.
+ * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_BG);
+}
+
+/**
+ * @brief Generate break 2 event.
+ * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_B2G);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
+ * @{
+ */
+
+ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
+void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
+ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
+void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
+ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
+void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
+void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
+ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
+void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
+ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
+void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
+ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM15 || TIM16 || TIM17 || TIM20 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32U5xx_LL_TIM_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_ucpd.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_ucpd.h
new file mode 100644
index 00000000..bb1a8b67
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_ucpd.h
@@ -0,0 +1,1885 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_ucpd.h
+ * @author MCD Application Team
+ * @brief Header file of UCPD LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_LL_UCPD_H
+#define STM32U5xx_LL_UCPD_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx.h"
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined (UCPD1)
+
+/** @defgroup UCPD_LL UCPD
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup UCPD_LL_ES_INIT UCPD Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief UCPD Init structures definition
+ */
+typedef struct
+{
+ uint32_t psc_ucpdclk; /*!< Specify the prescaler for the UCPD clock.
+ This parameter can be a value of @ref UCPD_LL_EC_PSC.
+ This feature can be modified afterwards using function @ref LL_UCPD_SetPSCClk().
+ */
+
+ uint32_t transwin; /*!< Specify the number of cycles (minus 1) of the half bit clock (see HBITCLKDIV)
+ to achieve a legal tTransitionWindow (set according to peripheral clock to define
+ an interval of between 12 and 20 us).
+ This parameter can be a value between Min_Data=0x1 and Max_Data=0x1F
+ This value can be modified afterwards using function @ref LL_UCPD_SetTransWin().
+ */
+
+ uint32_t IfrGap; /*!< Specify the definition of the clock divider (minus 1) in order to generate
+ tInterframeGap from the peripheral clock.
+ This parameter can be a value between Min_Data=0x1 and Max_Data=0x1F
+ This feature can be modified afterwards using function @ref LL_UCPD_SetIfrGap().
+ */
+
+ uint32_t HbitClockDiv; /*!< Specify the number of cycles (minus one) at UCPD peripheral for a half bit clock
+ e.g. program 3 for a bit clock that takes 8 cycles of the peripheral clock :
+ "UCPD1_CLK".
+ This parameter can be a value between Min_Data=0x0 and Max_Data=0x3F.
+ This feature can be modified using function @ref LL_UCPD_SetHbitClockDiv().
+ */
+
+} LL_UCPD_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UCPD_LL_Exported_Constants UCPD Exported Constants
+ * @{
+ */
+
+/** @defgroup UCPD_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_ucpd_ReadReg function
+ * @{
+ */
+#define LL_UCPD_SR_TXIS UCPD_SR_TXIS /*!< Transmit interrupt status */
+#define LL_UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC /*!< Transmit message discarded interrupt */
+#define LL_UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT /*!< Transmit message sent interrupt */
+#define LL_UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT /*!< Transmit message abort interrupt */
+#define LL_UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC /*!< HRST discarded interrupt */
+#define LL_UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT /*!< HRST sent interrupt */
+#define LL_UCPD_SR_TXUND UCPD_SR_TXUND /*!< Tx data underrun condition interrupt */
+#define LL_UCPD_SR_RXNE UCPD_SR_RXNE /*!< Receive data register not empty interrupt */
+#define LL_UCPD_SR_RXORDDET UCPD_SR_RXORDDET /*!< Rx ordered set (4 K-codes) detected interrupt */
+#define LL_UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET /*!< Rx Hard Reset detect interrupt */
+#define LL_UCPD_SR_RXOVR UCPD_SR_RXOVR /*!< Rx data overflow interrupt */
+#define LL_UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND /*!< Rx message received */
+#define LL_UCPD_SR_RXERR UCPD_SR_RXERR /*!< Rx error */
+#define LL_UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1 /*!< Type C voltage level event on CC1 */
+#define LL_UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2 /*!< Type C voltage level event on CC2 */
+#define LL_UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1 /*!__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in UCPD register
+ * @param __INSTANCE__ UCPD Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_UCPD_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup UCPD_LL_Exported_Functions UCPD Exported Functions
+ * @{
+ */
+
+/** @defgroup UCPD_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/** @defgroup UCPD_LL_EF_CFG1 CFG1 register
+ * @{
+ */
+/**
+ * @brief Enable UCPD peripheral
+ * @rmtoll CFG1 UCPDEN LL_UCPD_Enable
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_Enable(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN);
+}
+
+/**
+ * @brief Disable UCPD peripheral
+ * @note When disabling the UCPD, follow the procedure described in the Reference Manual.
+ * @rmtoll CFG1 UCPDEN LL_UCPD_Disable
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_Disable(UCPD_TypeDef *UCPDx)
+{
+ CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN);
+}
+
+/**
+ * @brief Check if UCPD peripheral is enabled
+ * @rmtoll CFG1 UCPDEN LL_UCPD_IsEnabled
+ * @param UCPDx UCPD Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_UCPD_IsEnabled(UCPD_TypeDef const *const UCPDx)
+{
+ return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN) == (UCPD_CFG1_UCPDEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set the receiver ordered set detection enable
+ * @rmtoll CFG1 RXORDSETEN LL_UCPD_SetRxOrderSet
+ * @param UCPDx UCPD Instance
+ * @param OrderSet This parameter can be combination of the following values:
+ * @arg @ref LL_UCPD_ORDERSET_SOP
+ * @arg @ref LL_UCPD_ORDERSET_SOP1
+ * @arg @ref LL_UCPD_ORDERSET_SOP2
+ * @arg @ref LL_UCPD_ORDERSET_HARDRST
+ * @arg @ref LL_UCPD_ORDERSET_CABLERST
+ * @arg @ref LL_UCPD_ORDERSET_SOP1_DEBUG
+ * @arg @ref LL_UCPD_ORDERSET_SOP2_DEBUG
+ * @arg @ref LL_UCPD_ORDERSET_SOP_EXT1
+ * @arg @ref LL_UCPD_ORDERSET_SOP_EXT2
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_SetRxOrderSet(UCPD_TypeDef *UCPDx, uint32_t OrderSet)
+{
+ MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_RXORDSETEN, OrderSet);
+}
+
+/**
+ * @brief Set the prescaler for ucpd clock
+ * @rmtoll CFG1 UCPDCLK LL_UCPD_SetPSCClk
+ * @param UCPDx UCPD Instance
+ * @param Psc This parameter can be one of the following values:
+ * @arg @ref LL_UCPD_PSC_DIV1
+ * @arg @ref LL_UCPD_PSC_DIV2
+ * @arg @ref LL_UCPD_PSC_DIV4
+ * @arg @ref LL_UCPD_PSC_DIV8
+ * @arg @ref LL_UCPD_PSC_DIV16
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_SetPSCClk(UCPD_TypeDef *UCPDx, uint32_t Psc)
+{
+ MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_PSC_UCPDCLK, Psc);
+}
+
+/**
+ * @brief Set the number of cycles (minus 1) of the half bit clock
+ * @rmtoll CFG1 TRANSWIN LL_UCPD_SetTransWin
+ * @param UCPDx UCPD Instance
+ * @param TransWin a value between Min_Data=0x1 and Max_Data=0x1F
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_SetTransWin(UCPD_TypeDef *UCPDx, uint32_t TransWin)
+{
+ MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_TRANSWIN, TransWin << UCPD_CFG1_TRANSWIN_Pos);
+}
+
+/**
+ * @brief Set the clock divider value to generate an interframe gap
+ * @rmtoll CFG1 IFRGAP LL_UCPD_SetIfrGap
+ * @param UCPDx UCPD Instance
+ * @param IfrGap a value between Min_Data=0x1 and Max_Data=0x1F
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_SetIfrGap(UCPD_TypeDef *UCPDx, uint32_t IfrGap)
+{
+ MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_IFRGAP, IfrGap << UCPD_CFG1_IFRGAP_Pos);
+}
+
+/**
+ * @brief Set the clock divider value to generate an interframe gap
+ * @rmtoll CFG1 HBITCLKDIV LL_UCPD_SetHbitClockDiv
+ * @param UCPDx UCPD Instance
+ * @param HbitClock a value between Min_Data=0x0 and Max_Data=0x3F
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_SetHbitClockDiv(UCPD_TypeDef *UCPDx, uint32_t HbitClock)
+{
+ MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_HBITCLKDIV, HbitClock << UCPD_CFG1_HBITCLKDIV_Pos);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UCPD_LL_EF_CFG2 CFG2 register
+ * @{
+ */
+
+/**
+ * @brief Enable Rx Analog Filter
+ * @rmtoll CFG2 RXAFILTEN LL_UCPD_RxAnalogFilterEnable
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_RxAnalogFilterEnable(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->CFG2, UCPD_CFG2_RXAFILTEN);
+}
+
+/**
+ * @brief Disable Rx Analog Filter
+ * @rmtoll CFG2 RXAFILTEN LL_UCPD_RxAnalogFilterDisable
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_RxAnalogFilterDisable(UCPD_TypeDef *UCPDx)
+{
+ CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_RXAFILTEN);
+}
+
+/**
+ * @brief Enable the wakeup mode
+ * @rmtoll CFG2 WUPEN LL_UCPD_WakeUpEnable
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_WakeUpEnable(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->CFG2, UCPD_CFG2_WUPEN);
+}
+
+/**
+ * @brief Disable the wakeup mode
+ * @rmtoll CFG2 WUPEN LL_UCPD_WakeUpDisable
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_WakeUpDisable(UCPD_TypeDef *UCPDx)
+{
+ CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_WUPEN);
+}
+
+/**
+ * @brief Force clock enable
+ * @rmtoll CFG2 FORCECLK LL_UCPD_ForceClockEnable
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_ForceClockEnable(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->CFG2, UCPD_CFG2_FORCECLK);
+}
+
+/**
+ * @brief Force clock disable
+ * @rmtoll CFG2 FORCECLK LL_UCPD_ForceClockDisable
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_ForceClockDisable(UCPD_TypeDef *UCPDx)
+{
+ CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_FORCECLK);
+}
+
+/**
+ * @brief RxFilter enable
+ * @rmtoll CFG2 RXFILTDIS LL_UCPD_RxFilterEnable
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_RxFilterEnable(UCPD_TypeDef *UCPDx)
+{
+ CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_RXFILTDIS);
+}
+
+/**
+ * @brief RxFilter disable
+ * @rmtoll CFG2 RXFILTDIS LL_UCPD_RxFilterDisable
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_RxFilterDisable(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->CFG2, UCPD_CFG2_RXFILTDIS);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup UCPD_LL_EF_CR CR register
+ * @{
+ */
+/**
+ * @brief Type C detector for CC2 enable
+ * @rmtoll CR CC2TCDIS LL_UCPD_TypeCDetectionCC2Enable
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_TypeCDetectionCC2Enable(UCPD_TypeDef *UCPDx)
+{
+ CLEAR_BIT(UCPDx->CR, UCPD_CR_CC2TCDIS);
+}
+
+/**
+ * @brief Type C detector for CC2 disable
+ * @rmtoll CR CC2TCDIS LL_UCPD_TypeCDetectionCC2Disable
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_TypeCDetectionCC2Disable(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->CR, UCPD_CR_CC2TCDIS);
+}
+
+/**
+ * @brief Type C detector for CC1 enable
+ * @rmtoll CR CC1TCDIS LL_UCPD_TypeCDetectionCC1Enable
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_TypeCDetectionCC1Enable(UCPD_TypeDef *UCPDx)
+{
+ CLEAR_BIT(UCPDx->CR, UCPD_CR_CC1TCDIS);
+}
+
+/**
+ * @brief Type C detector for CC1 disable
+ * @rmtoll CR CC1TCDIS LL_UCPD_TypeCDetectionCC1Disable
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_TypeCDetectionCC1Disable(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->CR, UCPD_CR_CC1TCDIS);
+}
+
+/**
+ * @brief Source Vconn discharge enable
+ * @rmtoll CR RDCH LL_UCPD_VconnDischargeEnable
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_VconnDischargeEnable(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->CR, UCPD_CR_RDCH);
+}
+
+/**
+ * @brief Source Vconn discharge disable
+ * @rmtoll CR RDCH LL_UCPD_VconnDischargeDisable
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_VconnDischargeDisable(UCPD_TypeDef *UCPDx)
+{
+ CLEAR_BIT(UCPDx->CR, UCPD_CR_RDCH);
+}
+
+/**
+ * @brief Signal Fast Role Swap request
+ * @rmtoll CR FRSTX LL_UCPD_VconnDischargeDisable
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_SignalFRSTX(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->CR, UCPD_CR_FRSTX);
+}
+
+/**
+ * @brief Fast Role swap RX detection enable
+ * @rmtoll CR FRSRXEN LL_UCPD_FRSDetectionEnable
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_FRSDetectionEnable(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->CR, UCPD_CR_FRSRXEN);
+}
+
+/**
+ * @brief Fast Role swap RX detection disable
+ * @rmtoll CR FRSRXEN LL_UCPD_FRSDetectionDisable
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_FRSDetectionDisable(UCPD_TypeDef *UCPDx)
+{
+ CLEAR_BIT(UCPDx->CR, UCPD_CR_FRSRXEN);
+}
+
+/**
+ * @brief Set cc enable
+ * @rmtoll CR CC1VCONNEN LL_UCPD_SetccEnable
+ * @param UCPDx UCPD Instance
+ * @param CCEnable This parameter can be one of the following values:
+ * @arg @ref LL_UCPD_CCENABLE_NONE
+ * @arg @ref LL_UCPD_CCENABLE_CC1
+ * @arg @ref LL_UCPD_CCENABLE_CC2
+ * @arg @ref LL_UCPD_CCENABLE_CC1CC2
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_SetccEnable(UCPD_TypeDef *UCPDx, uint32_t CCEnable)
+{
+ MODIFY_REG(UCPDx->CR, UCPD_CR_CCENABLE, CCEnable);
+}
+
+/**
+ * @brief Set UCPD SNK role
+ * @rmtoll CR ANAMODE LL_UCPD_SetSNKRole
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_SetSNKRole(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->CR, UCPD_CR_ANAMODE);
+}
+
+/**
+ * @brief Set UCPD SRC role
+ * @rmtoll CR ANAMODE LL_UCPD_SetSRCRole
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_SetSRCRole(UCPD_TypeDef *UCPDx)
+{
+ CLEAR_BIT(UCPDx->CR, UCPD_CR_ANAMODE);
+}
+
+/**
+ * @brief Get UCPD Role
+ * @rmtoll CR ANAMODE LL_UCPD_GetRole
+ * @param UCPDx UCPD Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_UCPD_ROLE_SNK
+ * @arg @ref LL_UCPD_ROLE_SRC
+ */
+__STATIC_INLINE uint32_t LL_UCPD_GetRole(UCPD_TypeDef const *const UCPDx)
+{
+ return (uint32_t)(READ_BIT(UCPDx->CR, UCPD_CR_ANAMODE));
+}
+
+/**
+ * @brief Set Rp resistor
+ * @rmtoll CR ANASUBMODE LL_UCPD_SetRpResistor
+ * @param UCPDx UCPD Instance
+ * @param Resistor This parameter can be one of the following values:
+ * @arg @ref LL_UCPD_RESISTOR_DEFAULT
+ * @arg @ref LL_UCPD_RESISTOR_1_5A
+ * @arg @ref LL_UCPD_RESISTOR_3_0A
+ * @arg @ref LL_UCPD_RESISTOR_NONE
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_SetRpResistor(UCPD_TypeDef *UCPDx, uint32_t Resistor)
+{
+ MODIFY_REG(UCPDx->CR, UCPD_CR_ANASUBMODE, Resistor);
+}
+
+/**
+ * @brief Set CC pin
+ * @rmtoll CR PHYCCSEL LL_UCPD_SetCCPin
+ * @param UCPDx UCPD Instance
+ * @param CCPin This parameter can be one of the following values:
+ * @arg @ref LL_UCPD_CCPIN_CC1
+ * @arg @ref LL_UCPD_CCPIN_CC2
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_SetCCPin(UCPD_TypeDef *UCPDx, uint32_t CCPin)
+{
+ MODIFY_REG(UCPDx->CR, UCPD_CR_PHYCCSEL, CCPin);
+}
+
+/**
+ * @brief Rx enable
+ * @rmtoll CR PHYRXEN LL_UCPD_RxEnable
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_RxEnable(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->CR, UCPD_CR_PHYRXEN);
+}
+
+/**
+ * @brief Rx disable
+ * @rmtoll CR PHYRXEN LL_UCPD_RxDisable
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_RxDisable(UCPD_TypeDef *UCPDx)
+{
+ CLEAR_BIT(UCPDx->CR, UCPD_CR_PHYRXEN);
+}
+
+/**
+ * @brief Set Rx mode
+ * @rmtoll CR RXMODE LL_UCPD_SetRxMode
+ * @param UCPDx UCPD Instance
+ * @param RxMode This parameter can be one of the following values:
+ * @arg @ref LL_UCPD_RXMODE_NORMAL
+ * @arg @ref LL_UCPD_RXMODE_BIST_TEST_DATA
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_SetRxMode(UCPD_TypeDef *UCPDx, uint32_t RxMode)
+{
+ MODIFY_REG(UCPDx->CR, UCPD_CR_RXMODE, RxMode);
+}
+
+/**
+ * @brief Send Hard Reset
+ * @rmtoll CR TXHRST LL_UCPD_SendHardReset
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_SendHardReset(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->CR, UCPD_CR_TXHRST);
+}
+
+/**
+ * @brief Send message
+ * @rmtoll CR TXSEND LL_UCPD_SendMessage
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_SendMessage(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->CR, UCPD_CR_TXSEND);
+}
+
+/**
+ * @brief Set Tx mode
+ * @rmtoll CR TXMODE LL_UCPD_SetTxMode
+ * @param UCPDx UCPD Instance
+ * @param TxMode This parameter can be one of the following values:
+ * @arg @ref LL_UCPD_TXMODE_NORMAL
+ * @arg @ref LL_UCPD_TXMODE_CABLE_RESET
+ * @arg @ref LL_UCPD_TXMODE_BIST_CARRIER2
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_SetTxMode(UCPD_TypeDef *UCPDx, uint32_t TxMode)
+{
+ MODIFY_REG(UCPDx->CR, UCPD_CR_TXMODE, TxMode);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UCPD_LL_EF_IT_Management Interrupt Management
+ * @{
+ */
+
+/**
+ * @brief Enable FRS interrupt
+ * @rmtoll IMR FRSEVTIE LL_UCPD_EnableIT_FRS
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_EnableIT_FRS(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->IMR, UCPD_IMR_FRSEVTIE);
+}
+
+/**
+ * @brief Enable type c event on CC2
+ * @rmtoll IMR TYPECEVT2IE LL_UCPD_EnableIT_TypeCEventCC2
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_EnableIT_TypeCEventCC2(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT2IE);
+}
+
+/**
+ * @brief Enable type c event on CC1
+ * @rmtoll IMR TYPECEVT1IE LL_UCPD_EnableIT_TypeCEventCC1
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_EnableIT_TypeCEventCC1(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT1IE);
+}
+
+/**
+ * @brief Enable Rx message end interrupt
+ * @rmtoll IMR RXMSGENDIE LL_UCPD_EnableIT_RxMsgEnd
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_EnableIT_RxMsgEnd(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->IMR, UCPD_IMR_RXMSGENDIE);
+}
+
+/**
+ * @brief Enable Rx overrun interrupt
+ * @rmtoll IMR RXOVRIE LL_UCPD_EnableIT_RxOvr
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_EnableIT_RxOvr(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->IMR, UCPD_IMR_RXOVRIE);
+}
+
+/**
+ * @brief Enable Rx hard resrt interrupt
+ * @rmtoll IMR RXHRSTDETIE LL_UCPD_EnableIT_RxHRST
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_EnableIT_RxHRST(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->IMR, UCPD_IMR_RXHRSTDETIE);
+}
+
+/**
+ * @brief Enable Rx orderset interrupt
+ * @rmtoll IMR RXORDDETIE LL_UCPD_EnableIT_RxOrderSet
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_EnableIT_RxOrderSet(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->IMR, UCPD_IMR_RXORDDETIE);
+}
+
+/**
+ * @brief Enable Rx non empty interrupt
+ * @rmtoll IMR RXNEIE LL_UCPD_EnableIT_RxNE
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_EnableIT_RxNE(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->IMR, UCPD_IMR_RXNEIE);
+}
+
+/**
+ * @brief Enable TX underrun interrupt
+ * @rmtoll IMR TXUNDIE LL_UCPD_EnableIT_TxUND
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_EnableIT_TxUND(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->IMR, UCPD_IMR_TXUNDIE);
+}
+
+/**
+ * @brief Enable hard reset sent interrupt
+ * @rmtoll IMR HRSTSENTIE LL_UCPD_EnableIT_TxHRSTSENT
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_EnableIT_TxHRSTSENT(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->IMR, UCPD_IMR_HRSTSENTIE);
+}
+
+/**
+ * @brief Enable hard reset discard interrupt
+ * @rmtoll IMR HRSTDISCIE LL_UCPD_EnableIT_TxHRSTDISC
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_EnableIT_TxHRSTDISC(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->IMR, UCPD_IMR_HRSTDISCIE);
+}
+
+/**
+ * @brief Enable Tx message abort interrupt
+ * @rmtoll IMR TXMSGABTIE LL_UCPD_EnableIT_TxMSGABT
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_EnableIT_TxMSGABT(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->IMR, UCPD_IMR_TXMSGABTIE);
+}
+
+/**
+ * @brief Enable Tx message sent interrupt
+ * @rmtoll IMR TXMSGSENTIE LL_UCPD_EnableIT_TxMSGSENT
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_EnableIT_TxMSGSENT(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->IMR, UCPD_IMR_TXMSGSENTIE);
+}
+
+/**
+ * @brief Enable Tx message discarded interrupt
+ * @rmtoll IMR TXMSGDISCIE LL_UCPD_EnableIT_TxMSGDISC
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_EnableIT_TxMSGDISC(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->IMR, UCPD_IMR_TXMSGDISCIE);
+}
+
+/**
+ * @brief Enable Tx data receive interrupt
+ * @rmtoll IMR TXISIE LL_UCPD_EnableIT_TxIS
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_EnableIT_TxIS(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->IMR, UCPD_IMR_TXISIE);
+}
+
+/**
+ * @brief Disable FRS interrupt
+ * @rmtoll IMR FRSEVTIE LL_UCPD_DisableIT_FRS
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_DisableIT_FRS(UCPD_TypeDef *UCPDx)
+{
+ CLEAR_BIT(UCPDx->IMR, UCPD_IMR_FRSEVTIE);
+}
+
+/**
+ * @brief Disable type c event on CC2
+ * @rmtoll IMR TYPECEVT2IE LL_UCPD_DisableIT_TypeCEventCC2
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_DisableIT_TypeCEventCC2(UCPD_TypeDef *UCPDx)
+{
+ CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT2IE);
+}
+
+/**
+ * @brief Disable type c event on CC1
+ * @rmtoll IMR TYPECEVT1IE LL_UCPD_DisableIT_TypeCEventCC1
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_DisableIT_TypeCEventCC1(UCPD_TypeDef *UCPDx)
+{
+ CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT1IE);
+}
+
+/**
+ * @brief Disable Rx message end interrupt
+ * @rmtoll IMR RXMSGENDIE LL_UCPD_DisableIT_RxMsgEnd
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_DisableIT_RxMsgEnd(UCPD_TypeDef *UCPDx)
+{
+ CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXMSGENDIE);
+}
+
+/**
+ * @brief Disable Rx overrun interrupt
+ * @rmtoll IMR RXOVRIE LL_UCPD_DisableIT_RxOvr
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_DisableIT_RxOvr(UCPD_TypeDef *UCPDx)
+{
+ CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXOVRIE);
+}
+
+/**
+ * @brief Disable Rx hard resrt interrupt
+ * @rmtoll IMR RXHRSTDETIE LL_UCPD_DisableIT_RxHRST
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_DisableIT_RxHRST(UCPD_TypeDef *UCPDx)
+{
+ CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXHRSTDETIE);
+}
+
+/**
+ * @brief Disable Rx orderset interrupt
+ * @rmtoll IMR RXORDDETIE LL_UCPD_DisableIT_RxOrderSet
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_DisableIT_RxOrderSet(UCPD_TypeDef *UCPDx)
+{
+ CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXORDDETIE);
+}
+
+/**
+ * @brief Disable Rx non empty interrupt
+ * @rmtoll IMR RXNEIE LL_UCPD_DisableIT_RxNE
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_DisableIT_RxNE(UCPD_TypeDef *UCPDx)
+{
+ CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXNEIE);
+}
+
+/**
+ * @brief Disable TX underrun interrupt
+ * @rmtoll IMR TXUNDIE LL_UCPD_DisableIT_TxUND
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_DisableIT_TxUND(UCPD_TypeDef *UCPDx)
+{
+ CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXUNDIE);
+}
+
+/**
+ * @brief Disable hard reset sent interrupt
+ * @rmtoll IMR HRSTSENTIE LL_UCPD_DisableIT_TxHRSTSENT
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_DisableIT_TxHRSTSENT(UCPD_TypeDef *UCPDx)
+{
+ CLEAR_BIT(UCPDx->IMR, UCPD_IMR_HRSTSENTIE);
+}
+
+/**
+ * @brief Disable hard reset discard interrupt
+ * @rmtoll IMR HRSTDISCIE LL_UCPD_DisableIT_TxHRSTDISC
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_DisableIT_TxHRSTDISC(UCPD_TypeDef *UCPDx)
+{
+ CLEAR_BIT(UCPDx->IMR, UCPD_IMR_HRSTDISCIE);
+}
+
+/**
+ * @brief Disable Tx message abort interrupt
+ * @rmtoll IMR TXMSGABTIE LL_UCPD_DisableIT_TxMSGABT
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_DisableIT_TxMSGABT(UCPD_TypeDef *UCPDx)
+{
+ CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXMSGABTIE);
+}
+
+/**
+ * @brief Disable Tx message sent interrupt
+ * @rmtoll IMR TXMSGSENTIE LL_UCPD_DisableIT_TxMSGSENT
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_DisableIT_TxMSGSENT(UCPD_TypeDef *UCPDx)
+{
+ CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXMSGSENTIE);
+}
+
+/**
+ * @brief Disable Tx message discarded interrupt
+ * @rmtoll IMR TXMSGDISCIE LL_UCPD_DisableIT_TxMSGDISC
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_DisableIT_TxMSGDISC(UCPD_TypeDef *UCPDx)
+{
+ CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXMSGDISCIE);
+}
+
+/**
+ * @brief Disable Tx data receive interrupt
+ * @rmtoll IMR TXISIE LL_UCPD_DisableIT_TxIS
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_DisableIT_TxIS(UCPD_TypeDef *UCPDx)
+{
+ CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXISIE);
+}
+
+/**
+ * @brief Check if FRS interrupt enabled
+ * @rmtoll IMR FRSEVTIE LL_UCPD_DisableIT_FRS
+ * @param UCPDx UCPD Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_FRS(UCPD_TypeDef const *const UCPDx)
+{
+ return ((READ_BIT(UCPDx->IMR, UCPD_IMR_FRSEVTIE) == UCPD_IMR_FRSEVTIE) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if type c event on CC2 enabled
+ * @rmtoll IMR TYPECEVT2IE LL_UCPD_DisableIT_TypeCEventCC2
+ * @param UCPDx UCPD Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TypeCEventCC2(UCPD_TypeDef const *const UCPDx)
+{
+ return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT2IE) == UCPD_IMR_TYPECEVT2IE) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if type c event on CC1 enabled
+ * @rmtoll IMR2 TYPECEVT1IE LL_UCPD_IsEnableIT_TypeCEventCC1
+ * @param UCPDx UCPD Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TypeCEventCC1(UCPD_TypeDef const *const UCPDx)
+{
+ return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT1IE) == UCPD_IMR_TYPECEVT1IE) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Rx message end interrupt enabled
+ * @rmtoll IMR RXMSGENDIE LL_UCPD_IsEnableIT_RxMsgEnd
+ * @param UCPDx UCPD Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxMsgEnd(UCPD_TypeDef const *const UCPDx)
+{
+ return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXMSGENDIE) == UCPD_IMR_RXMSGENDIE) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Rx overrun interrupt enabled
+ * @rmtoll IMR RXOVRIE LL_UCPD_IsEnableIT_RxOvr
+ * @param UCPDx UCPD Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOvr(UCPD_TypeDef const *const UCPDx)
+{
+ return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXOVRIE) == UCPD_IMR_RXOVRIE) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Rx hard resrt interrupt enabled
+ * @rmtoll IMR RXHRSTDETIE LL_UCPD_IsEnableIT_RxHRST
+ * @param UCPDx UCPD Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxHRST(UCPD_TypeDef const *const UCPDx)
+{
+ return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXHRSTDETIE) == UCPD_IMR_RXHRSTDETIE) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Rx orderset interrupt enabled
+ * @rmtoll IMR RXORDDETIE LL_UCPD_IsEnableIT_RxOrderSet
+ * @param UCPDx UCPD Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOrderSet(UCPD_TypeDef const *const UCPDx)
+{
+ return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXORDDETIE) == UCPD_IMR_RXORDDETIE) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Rx non empty interrupt enabled
+ * @rmtoll IMR RXNEIE LL_UCPD_IsEnableIT_RxNE
+ * @param UCPDx UCPD Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxNE(UCPD_TypeDef const *const UCPDx)
+{
+ return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXNEIE) == UCPD_IMR_RXNEIE) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if TX underrun interrupt enabled
+ * @rmtoll IMR TXUNDIE LL_UCPD_IsEnableIT_TxUND
+ * @param UCPDx UCPD Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxUND(UCPD_TypeDef const *const UCPDx)
+{
+ return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXUNDIE) == UCPD_IMR_TXUNDIE) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if hard reset sent interrupt enabled
+ * @rmtoll IMR HRSTSENTIE LL_UCPD_IsEnableIT_TxHRSTSENT
+ * @param UCPDx UCPD Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxHRSTSENT(UCPD_TypeDef const *const UCPDx)
+{
+ return ((READ_BIT(UCPDx->IMR, UCPD_IMR_HRSTSENTIE) == UCPD_IMR_HRSTSENTIE) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if hard reset discard interrupt enabled
+ * @rmtoll IMR HRSTDISCIE LL_UCPD_IsEnableIT_TxHRSTDISC
+ * @param UCPDx UCPD Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxHRSTDISC(UCPD_TypeDef const *const UCPDx)
+{
+ return ((READ_BIT(UCPDx->IMR, UCPD_IMR_HRSTDISCIE) == UCPD_IMR_HRSTDISCIE) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Tx message abort interrupt enabled
+ * @rmtoll IMR TXMSGABTIE LL_UCPD_IsEnableIT_TxMSGABT
+ * @param UCPDx UCPD Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGABT(UCPD_TypeDef const *const UCPDx)
+{
+ return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXMSGABTIE) == UCPD_IMR_TXMSGABTIE) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Tx message sent interrupt enabled
+ * @rmtoll IMR TXMSGSENTIE LL_UCPD_IsEnableIT_TxMSGSENT
+ * @param UCPDx UCPD Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGSENT(UCPD_TypeDef const *const UCPDx)
+{
+ return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXMSGSENTIE) == UCPD_IMR_TXMSGSENTIE) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Tx message discarded interrupt enabled
+ * @rmtoll IMR TXMSGDISCIE LL_UCPD_IsEnableIT_TxMSGDISC
+ * @param UCPDx UCPD Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGDISC(UCPD_TypeDef const *const UCPDx)
+{
+ return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXMSGDISCIE) == UCPD_IMR_TXMSGDISCIE) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Tx data receive interrupt enabled
+ * @rmtoll IMR TXISIE LL_UCPD_IsEnableIT_TxIS
+ * @param UCPDx UCPD Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxIS(UCPD_TypeDef const *const UCPDx)
+{
+ return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXISIE) == UCPD_IMR_TXISIE) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UCPD_LL_EF_IT_Clear Interrupt Clear
+ * @{
+ */
+
+/**
+ * @brief Clear FRS interrupt
+ * @rmtoll ICR FRSEVTIE LL_UCPD_ClearFlag_FRS
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_ClearFlag_FRS(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->ICR, UCPD_ICR_FRSEVTCF);
+}
+
+/**
+ * @brief Clear type c event on CC2
+ * @rmtoll IIMR TYPECEVT2IE LL_UCPD_ClearFlag_TypeCEventCC2
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_ClearFlag_TypeCEventCC2(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->ICR, UCPD_ICR_TYPECEVT2CF);
+}
+
+/**
+ * @brief Clear type c event on CC1
+ * @rmtoll IIMR TYPECEVT1IE LL_UCPD_ClearFlag_TypeCEventCC1
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_ClearFlag_TypeCEventCC1(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->ICR, UCPD_ICR_TYPECEVT1CF);
+}
+
+/**
+ * @brief Clear Rx message end interrupt
+ * @rmtoll ICR RXMSGENDIE LL_UCPD_ClearFlag_RxMsgEnd
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_ClearFlag_RxMsgEnd(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->ICR, UCPD_ICR_RXMSGENDCF);
+}
+
+/**
+ * @brief Clear Rx overrun interrupt
+ * @rmtoll ICR RXOVRIE LL_UCPD_ClearFlag_RxOvr
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_ClearFlag_RxOvr(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->ICR, UCPD_ICR_RXOVRCF);
+}
+
+/**
+ * @brief Clear Rx hard resrt interrupt
+ * @rmtoll ICR RXHRSTDETIE LL_UCPD_ClearFlag_RxHRST
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_ClearFlag_RxHRST(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->ICR, UCPD_ICR_RXHRSTDETCF);
+}
+
+/**
+ * @brief Clear Rx orderset interrupt
+ * @rmtoll ICR RXORDDETIE LL_UCPD_ClearFlag_RxOrderSet
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_ClearFlag_RxOrderSet(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->ICR, UCPD_ICR_RXORDDETCF);
+}
+
+/**
+ * @brief Clear TX underrun interrupt
+ * @rmtoll ICR TXUNDIE LL_UCPD_ClearFlag_TxUND
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_ClearFlag_TxUND(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->ICR, UCPD_ICR_TXUNDCF);
+}
+
+/**
+ * @brief Clear hard reset sent interrupt
+ * @rmtoll ICR HRSTSENTIE LL_UCPD_ClearFlag_TxHRSTSENT
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_ClearFlag_TxHRSTSENT(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->ICR, UCPD_ICR_HRSTSENTCF);
+}
+
+/**
+ * @brief Clear hard reset discard interrupt
+ * @rmtoll ICR HRSTDISCIE LL_UCPD_ClearFlag_TxHRSTDISC
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_ClearFlag_TxHRSTDISC(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->ICR, UCPD_ICR_HRSTDISCCF);
+}
+
+/**
+ * @brief Clear Tx message abort interrupt
+ * @rmtoll ICR TXMSGABTIE LL_UCPD_ClearFlag_TxMSGABT
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGABT(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->ICR, UCPD_ICR_TXMSGABTCF);
+}
+
+/**
+ * @brief Clear Tx message sent interrupt
+ * @rmtoll ICR TXMSGSENTIE LL_UCPD_ClearFlag_TxMSGSENT
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGSENT(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->ICR, UCPD_ICR_TXMSGSENTCF);
+}
+
+/**
+ * @brief Clear Tx message discarded interrupt
+ * @rmtoll ICR TXMSGDISCIE LL_UCPD_ClearFlag_TxMSGDISC
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGDISC(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->ICR, UCPD_ICR_TXMSGDISCCF);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UCPD_LL_EF_FLAG_Management FLAG Management
+ * @{
+ */
+
+/**
+ * @brief Check if FRS interrupt
+ * @rmtoll SR FRSEVT LL_UCPD_IsActiveFlag_FRS
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_FRS(UCPD_TypeDef const *const UCPDx)
+{
+ return ((READ_BIT(UCPDx->SR, UCPD_SR_FRSEVT) == UCPD_SR_FRSEVT) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if type c event on CC2
+ * @rmtoll SR TYPECEVT2 LL_UCPD_IsActiveFlag_TypeCEventCC2
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC2(UCPD_TypeDef const *const UCPDx)
+{
+ return ((READ_BIT(UCPDx->SR, UCPD_SR_TYPECEVT2) == UCPD_SR_TYPECEVT2) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if type c event on CC1
+ * @rmtoll SR TYPECEVT1 LL_UCPD_IsActiveFlag_TypeCEventCC1
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC1(UCPD_TypeDef const *const UCPDx)
+{
+ return ((READ_BIT(UCPDx->SR, UCPD_SR_TYPECEVT1) == UCPD_SR_TYPECEVT1) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Rx message end interrupt
+ * @rmtoll SR RXMSGEND LL_UCPD_IsActiveFlag_RxMsgEnd
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxMsgEnd(UCPD_TypeDef const *const UCPDx)
+{
+ return ((READ_BIT(UCPDx->SR, UCPD_SR_RXMSGEND) == UCPD_SR_RXMSGEND) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Rx overrun interrupt
+ * @rmtoll SR RXOVR LL_UCPD_IsActiveFlag_RxOvr
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOvr(UCPD_TypeDef const *const UCPDx)
+{
+ return ((READ_BIT(UCPDx->SR, UCPD_SR_RXOVR) == UCPD_SR_RXOVR) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Rx hard resrt interrupt
+ * @rmtoll SR RXHRSTDET LL_UCPD_IsActiveFlag_RxHRST
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxHRST(UCPD_TypeDef const *const UCPDx)
+{
+ return ((READ_BIT(UCPDx->SR, UCPD_SR_RXHRSTDET) == UCPD_SR_RXHRSTDET) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Rx orderset interrupt
+ * @rmtoll SR RXORDDET LL_UCPD_IsActiveFlag_RxOrderSet
+ * @param UCPDx UCPD Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOrderSet(UCPD_TypeDef const *const UCPDx)
+{
+ return ((READ_BIT(UCPDx->SR, UCPD_SR_RXORDDET) == UCPD_SR_RXORDDET) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Rx non empty interrupt
+ * @rmtoll SR RXNE LL_UCPD_IsActiveFlag_RxNE
+ * @param UCPDx UCPD Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxNE(UCPD_TypeDef const *const UCPDx)
+{
+ return ((READ_BIT(UCPDx->SR, UCPD_SR_RXNE) == UCPD_SR_RXNE) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if TX underrun interrupt
+ * @rmtoll SR TXUND LL_UCPD_IsActiveFlag_TxUND
+ * @param UCPDx UCPD Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxUND(UCPD_TypeDef const *const UCPDx)
+{
+ return ((READ_BIT(UCPDx->SR, UCPD_SR_TXUND) == UCPD_SR_TXUND) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if hard reset sent interrupt
+ * @rmtoll SR HRSTSENT LL_UCPD_IsActiveFlag_TxHRSTSENT
+ * @param UCPDx UCPD Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTSENT(UCPD_TypeDef const *const UCPDx)
+{
+ return ((READ_BIT(UCPDx->SR, UCPD_SR_HRSTSENT) == UCPD_SR_HRSTSENT) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if hard reset discard interrupt
+ * @rmtoll SR HRSTDISC LL_UCPD_IsActiveFlag_TxHRSTDISC
+ * @param UCPDx UCPD Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTDISC(UCPD_TypeDef const *const UCPDx)
+{
+ return ((READ_BIT(UCPDx->SR, UCPD_SR_HRSTDISC) == UCPD_SR_HRSTDISC) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Tx message abort interrupt
+ * @rmtoll SR TXMSGABT LL_UCPD_IsActiveFlag_TxMSGABT
+ * @param UCPDx UCPD Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGABT(UCPD_TypeDef const *const UCPDx)
+{
+ return ((READ_BIT(UCPDx->SR, UCPD_SR_TXMSGABT) == UCPD_SR_TXMSGABT) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Tx message sent interrupt
+ * @rmtoll SR TXMSGSENT LL_UCPD_IsActiveFlag_TxMSGSENT
+ * @param UCPDx UCPD Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGSENT(UCPD_TypeDef const *const UCPDx)
+{
+ return ((READ_BIT(UCPDx->SR, UCPD_SR_TXMSGSENT) == UCPD_SR_TXMSGSENT) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Tx message discarded interrupt
+ * @rmtoll SR TXMSGDISC LL_UCPD_IsActiveFlag_TxMSGDISC
+ * @param UCPDx UCPD Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGDISC(UCPD_TypeDef const *const UCPDx)
+{
+ return ((READ_BIT(UCPDx->SR, UCPD_SR_TXMSGDISC) == UCPD_SR_TXMSGDISC) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Tx data receive interrupt
+ * @rmtoll SR TXIS LL_UCPD_IsActiveFlag_TxIS
+ * @param UCPDx UCPD Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxIS(UCPD_TypeDef const *const UCPDx)
+{
+ return ((READ_BIT(UCPDx->SR, UCPD_SR_TXIS) == UCPD_SR_TXIS) ? 1UL : 0UL);
+}
+
+/**
+ * @brief return the vstate value for CC2
+ * @rmtoll SR TXIS LL_UCPD_GetTypeCVstateCC2
+ * @param UCPDx UCPD Instance
+ * @retval val
+ */
+__STATIC_INLINE uint32_t LL_UCPD_GetTypeCVstateCC2(UCPD_TypeDef const *const UCPDx)
+{
+ return UCPDx->SR & UCPD_SR_TYPEC_VSTATE_CC2;
+}
+
+/**
+ * @brief return the vstate value for CC1
+ * @rmtoll SR TXIS LL_UCPD_GetTypeCVstateCC1
+ * @param UCPDx UCPD Instance
+ * @retval val
+ */
+__STATIC_INLINE uint32_t LL_UCPD_GetTypeCVstateCC1(UCPD_TypeDef const *const UCPDx)
+{
+ return UCPDx->SR & UCPD_SR_TYPEC_VSTATE_CC1;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup UCPD_LL_EF_DMA_Management DMA Management
+ * @{
+ */
+
+/**
+ * @brief Rx DMA Enable
+ * @rmtoll CFG1 RXDMAEN LL_UCPD_RxDMAEnable
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_RxDMAEnable(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN);
+}
+
+/**
+ * @brief Rx DMA Disable
+ * @rmtoll CFG1 RXDMAEN LL_UCPD_RxDMADisable
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_RxDMADisable(UCPD_TypeDef *UCPDx)
+{
+ CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN);
+}
+
+/**
+ * @brief Tx DMA Enable
+ * @rmtoll CFG1 TXDMAEN LL_UCPD_TxDMAEnable
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_TxDMAEnable(UCPD_TypeDef *UCPDx)
+{
+ SET_BIT(UCPDx->CFG1, UCPD_CFG1_TXDMAEN);
+}
+
+/**
+ * @brief Tx DMA Disable
+ * @rmtoll CFG1 TXDMAEN LL_UCPD_TxDMADisable
+ * @param UCPDx UCPD Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_TxDMADisable(UCPD_TypeDef *UCPDx)
+{
+ CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_TXDMAEN);
+}
+
+/**
+ * @brief Check if DMA Tx is enabled
+ * @rmtoll CR2 TXDMAEN LL_UCPD_IsEnabledTxDMA
+ * @param UCPDx UCPD Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_UCPD_IsEnabledTxDMA(UCPD_TypeDef const *const UCPDx)
+{
+ return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_TXDMAEN) == (UCPD_CFG1_TXDMAEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if DMA Rx is enabled
+ * @rmtoll CR2 RXDMAEN LL_UCPD_IsEnabledRxDMA
+ * @param UCPDx UCPD Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_UCPD_IsEnabledRxDMA(UCPD_TypeDef const *const UCPDx)
+{
+ return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN) == (UCPD_CFG1_RXDMAEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UCPD_LL_EF_DATA_Management DATA Management
+ * @{
+ */
+
+/**
+ * @brief write the orderset for Tx message
+ * @rmtoll TX_ORDSET TXORDSET LL_UCPD_WriteTxOrderSet
+ * @param UCPDx UCPD Instance
+ * @param TxOrderSet one of the following value
+ * @arg @ref LL_UCPD_ORDERED_SET_SOP
+ * @arg @ref LL_UCPD_ORDERED_SET_SOP1
+ * @arg @ref LL_UCPD_ORDERED_SET_SOP2
+ * @arg @ref LL_UCPD_ORDERED_SET_HARD_RESET
+ * @arg @ref LL_UCPD_ORDERED_SET_CABLE_RESET
+ * @arg @ref LL_UCPD_ORDERED_SET_SOP1_DEBUG
+ * @arg @ref LL_UCPD_ORDERED_SET_SOP2_DEBUG
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_WriteTxOrderSet(UCPD_TypeDef *UCPDx, uint32_t TxOrderSet)
+{
+ WRITE_REG(UCPDx->TX_ORDSET, TxOrderSet);
+}
+
+/**
+ * @brief write the Tx paysize
+ * @rmtoll TX_PAYSZ TXPAYSZ LL_UCPD_WriteTxPaySize
+ * @param UCPDx UCPD Instance
+ * @param TxPaySize
+ * @retval None.
+ */
+__STATIC_INLINE void LL_UCPD_WriteTxPaySize(UCPD_TypeDef *UCPDx, uint32_t TxPaySize)
+{
+ WRITE_REG(UCPDx->TX_PAYSZ, TxPaySize);
+}
+
+/**
+ * @brief Write data
+ * @rmtoll TXDR DR LL_UCPD_WriteData
+ * @param UCPDx UCPD Instance
+ * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None.
+ */
+__STATIC_INLINE void LL_UCPD_WriteData(UCPD_TypeDef *UCPDx, uint8_t Data)
+{
+ WRITE_REG(UCPDx->TXDR, Data);
+}
+
+/**
+ * @brief read RX the orderset
+ * @rmtoll RX_ORDSET RXORDSET LL_UCPD_ReadRxOrderSet
+ * @param UCPDx UCPD Instance
+ * @retval RxOrderSet one of the following value
+ * @arg @ref LL_UCPD_RXORDSET_SOP
+ * @arg @ref LL_UCPD_RXORDSET_SOP1
+ * @arg @ref LL_UCPD_RXORDSET_SOP2
+ * @arg @ref LL_UCPD_RXORDSET_SOP1_DEBUG
+ * @arg @ref LL_UCPD_RXORDSET_SOP2_DEBUG
+ * @arg @ref LL_UCPD_RXORDSET_CABLE_RESET
+ * @arg @ref LL_UCPD_RXORDSET_SOPEXT1
+ * @arg @ref LL_UCPD_RXORDSET_SOPEXT2
+ */
+__STATIC_INLINE uint32_t LL_UCPD_ReadRxOrderSet(UCPD_TypeDef const *const UCPDx)
+{
+ return READ_BIT(UCPDx->RX_ORDSET, UCPD_RX_ORDSET_RXORDSET);
+}
+
+/**
+ * @brief Read the Rx paysize
+ * @rmtoll TX_PAYSZ TXPAYSZ LL_UCPD_ReadRxPaySize
+ * @param UCPDx UCPD Instance
+ * @retval RXPaysize.
+ */
+__STATIC_INLINE uint32_t LL_UCPD_ReadRxPaySize(UCPD_TypeDef const *const UCPDx)
+{
+ return READ_BIT(UCPDx->TX_PAYSZ, UCPD_RX_PAYSZ_RXPAYSZ);
+}
+
+/**
+ * @brief Read data
+ * @rmtoll TXDR RXDATA LL_UCPD_ReadData
+ * @param UCPDx UCPD Instance
+ * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_UCPD_ReadData(UCPD_TypeDef const *const UCPDx)
+{
+ return READ_REG(UCPDx->RXDR);
+}
+
+/**
+ * @brief Set Rx OrderSet Ext1
+ * @rmtoll RX_ORDEXT1 RXSOPX1 LL_UCPD_SetRxOrdExt1
+ * @param UCPDx UCPD Instance
+ * @param SOPExt Value between Min_Data=0x00000 and Max_Data=0xFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_SetRxOrdExt1(UCPD_TypeDef *UCPDx, uint32_t SOPExt)
+{
+ WRITE_REG(UCPDx->RX_ORDEXT1, SOPExt);
+}
+
+/**
+ * @brief Set Rx OrderSet Ext2
+ * @rmtoll RX_ORDEXT2 RXSOPX2 LL_UCPD_SetRxOrdExt2
+ * @param UCPDx UCPD Instance
+ * @param SOPExt Value between Min_Data=0x00000 and Max_Data=0xFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_UCPD_SetRxOrdExt2(UCPD_TypeDef *UCPDx, uint32_t SOPExt)
+{
+ WRITE_REG(UCPDx->RX_ORDEXT2, SOPExt);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup UCPD_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx);
+ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStruct);
+void LL_UCPD_StructInit(LL_UCPD_InitTypeDef *UCPD_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+#endif /* defined (UCPD1) */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_LL_UCPD_H */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_usart.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_usart.h
new file mode 100644
index 00000000..054b2a92
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_usart.h
@@ -0,0 +1,4489 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_usart.h
+ * @author MCD Application Team
+ * @brief Header file of USART LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_LL_USART_H
+#define STM32U5xx_LL_USART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx.h"
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5)
+
+/** @defgroup USART_LL USART
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup USART_LL_Private_Variables USART Private Variables
+ * @{
+ */
+/* Array used to get the USART prescaler division decimal values versus @ref USART_LL_EC_PRESCALER values */
+static const uint32_t USART_PRESCALER_TAB[] =
+{
+ 1UL,
+ 2UL,
+ 4UL,
+ 6UL,
+ 8UL,
+ 10UL,
+ 12UL,
+ 16UL,
+ 32UL,
+ 64UL,
+ 128UL,
+ 256UL
+};
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_Private_Macros USART Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_ES_INIT USART Exported Init structures
+ * @{
+ */
+
+/**
+ * @brief LL USART Init Structure definition
+ */
+typedef struct
+{
+ uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate.
+ This parameter can be a value of @ref USART_LL_EC_PRESCALER.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetPrescaler().*/
+
+ uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetBaudRate().*/
+
+ uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetDataWidth().*/
+
+ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref USART_LL_EC_STOPBITS.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetStopBitsLength().*/
+
+ uint32_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref USART_LL_EC_PARITY.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetParity().*/
+
+ uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref USART_LL_EC_DIRECTION.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetTransferDirection().*/
+
+ uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
+ This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetHWFlowCtrl().*/
+
+ uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8.
+ This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetOverSampling().*/
+
+} LL_USART_InitTypeDef;
+
+/**
+ * @brief LL USART Clock Init Structure definition
+ */
+typedef struct
+{
+ uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or disabled.
+ This parameter can be a value of @ref USART_LL_EC_CLOCK.
+
+ USART HW configuration can be modified afterwards using unitary functions
+ @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().
+ For more details, refer to description of this function. */
+
+ uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock.
+ This parameter can be a value of @ref USART_LL_EC_POLARITY.
+
+ USART HW configuration can be modified afterwards using unitary
+ functions @ref LL_USART_SetClockPolarity().
+ For more details, refer to description of this function. */
+
+ uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref USART_LL_EC_PHASE.
+
+ USART HW configuration can be modified afterwards using unitary
+ functions @ref LL_USART_SetClockPhase().
+ For more details, refer to description of this function. */
+
+ uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+ This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
+
+ USART HW configuration can be modified afterwards using unitary
+ functions @ref LL_USART_SetLastClkPulseOutput().
+ For more details, refer to description of this function. */
+
+} LL_USART_ClockInitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup USART_LL_Exported_Constants USART Exported Constants
+ * @{
+ */
+
+/** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines
+ * @brief Flags defines which can be used with LL_USART_WriteReg function
+ * @{
+ */
+#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */
+#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */
+#define LL_USART_ICR_NECF USART_ICR_NECF /*!< Noise error detected clear flag */
+#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */
+#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */
+#define LL_USART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty clear flag */
+#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */
+#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission completed before guard time clear flag */
+#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection clear flag */
+#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */
+#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout clear flag */
+#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block clear flag */
+#define LL_USART_ICR_UDRCF USART_ICR_UDRCF /*!< SPI Slave Underrun clear flag */
+#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_USART_ReadReg function
+ * @{
+ */
+#define LL_USART_ISR_PE USART_ISR_PE /*!< Parity error flag */
+#define LL_USART_ISR_FE USART_ISR_FE /*!< Framing error flag */
+#define LL_USART_ISR_NE USART_ISR_NE /*!< Noise detected flag */
+#define LL_USART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */
+#define LL_USART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */
+#define LL_USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */
+#define LL_USART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */
+#define LL_USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/
+#define LL_USART_ISR_LBDF USART_ISR_LBDF /*!< LIN break detection flag */
+#define LL_USART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */
+#define LL_USART_ISR_CTS USART_ISR_CTS /*!< CTS flag */
+#define LL_USART_ISR_RTOF USART_ISR_RTOF /*!< Receiver timeout flag */
+#define LL_USART_ISR_EOBF USART_ISR_EOBF /*!< End of block flag */
+#define LL_USART_ISR_UDR USART_ISR_UDR /*!< SPI Slave underrun error flag */
+#define LL_USART_ISR_ABRE USART_ISR_ABRE /*!< Auto baud rate error flag */
+#define LL_USART_ISR_ABRF USART_ISR_ABRF /*!< Auto baud rate flag */
+#define LL_USART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */
+#define LL_USART_ISR_CMF USART_ISR_CMF /*!< Character match flag */
+#define LL_USART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */
+#define LL_USART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */
+#define LL_USART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */
+#define LL_USART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */
+#define LL_USART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */
+#define LL_USART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */
+#define LL_USART_ISR_TCBGT USART_ISR_TCBGT /*!< Transmission complete before guard time completion flag */
+#define LL_USART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */
+#define LL_USART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions
+ * @{
+ */
+#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */
+#define LL_USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty interrupt enable */
+#define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */
+#define LL_USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO not full interrupt enable */
+#define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */
+#define LL_USART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */
+#define LL_USART_CR1_RTOIE USART_CR1_RTOIE /*!< Receiver timeout interrupt enable */
+#define LL_USART_CR1_EOBIE USART_CR1_EOBIE /*!< End of Block interrupt enable */
+#define LL_USART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */
+#define LL_USART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */
+#define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detection interrupt enable */
+#define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */
+#define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */
+#define LL_USART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */
+#define LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE /*!< Transmission complete before guard time interrupt enable */
+#define LL_USART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_FIFOTHRESHOLD FIFO Threshold
+ * @{
+ */
+#define LL_USART_FIFOTHRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */
+#define LL_USART_FIFOTHRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */
+#define LL_USART_FIFOTHRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */
+#define LL_USART_FIFOTHRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */
+#define LL_USART_FIFOTHRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */
+#define LL_USART_FIFOTHRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_DIRECTION Communication Direction
+ * @{
+ */
+#define LL_USART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */
+#define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */
+#define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */
+#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_PARITY Parity Control
+ * @{
+ */
+#define LL_USART_PARITY_NONE 0x00000000U /*!< Parity control disabled */
+#define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */
+#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_WAKEUP Wakeup
+ * @{
+ */
+#define LL_USART_WAKEUP_IDLELINE 0x00000000U /*!< USART wake up from Mute mode on Idle Line */
+#define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< USART wake up from Mute mode on Address Mark */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_DATAWIDTH Datawidth
+ * @{
+ */
+#define LL_USART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
+#define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
+#define LL_USART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
+ * @{
+ */
+#define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */
+#define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_EC_CLOCK Clock Signal
+ * @{
+ */
+
+#define LL_USART_CLOCK_DISABLE 0x00000000U /*!< Clock signal not provided */
+#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
+ * @{
+ */
+#define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U /*!< The clock pulse of the last data bit is not output to the SCLK pin */
+#define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /*!< The clock pulse of the last data bit is output to the SCLK pin */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_PHASE Clock Phase
+ * @{
+ */
+#define LL_USART_PHASE_1EDGE 0x00000000U /*!< The first clock transition is the first data capture edge */
+#define LL_USART_PHASE_2EDGE USART_CR2_CPHA /*!< The second clock transition is the first data capture edge */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_POLARITY Clock Polarity
+ * @{
+ */
+#define LL_USART_POLARITY_LOW 0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/
+#define LL_USART_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCLK pin outside transmission window */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_PRESCALER Clock Source Prescaler
+ * @{
+ */
+#define LL_USART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */
+#define LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */
+#define LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */
+#define LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */
+#define LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */
+#define LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */
+#define LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */
+#define LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */
+#define LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */
+#define LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */
+#define LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */
+#define LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_STOPBITS Stop Bits
+ * @{
+ */
+#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 stop bit */
+#define LL_USART_STOPBITS_1 0x00000000U /*!< 1 stop bit */
+#define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 stop bits */
+#define LL_USART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_TXRX TX RX Pins Swap
+ * @{
+ */
+#define LL_USART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */
+#define LL_USART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
+ * @{
+ */
+#define LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */
+#define LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
+ * @{
+ */
+#define LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */
+#define LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion
+ * @{
+ */
+#define LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
+#define LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_BITORDER Bit Order
+ * @{
+ */
+#define LL_USART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */
+#define LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, following the start bit */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection
+ * @{
+ */
+#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U /*!< Measurement of the start bit is used to detect the baud rate */
+#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0 /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */
+#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1 /*!< 0x7F frame detection */
+#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection
+ * @{
+ */
+#define LL_USART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */
+#define LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_HWCONTROL Hardware Control
+ * @{
+ */
+#define LL_USART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */
+#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
+#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
+#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
+ * @{
+ */
+#define LL_USART_IRDA_POWER_NORMAL 0x00000000U /*!< IrDA normal power mode */
+#define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /*!< IrDA low power mode */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
+ * @{
+ */
+#define LL_USART_LINBREAK_DETECT_10B 0x00000000U /*!< 10-bit break detection method selected */
+#define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL /*!< 11-bit break detection method selected */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity
+ * @{
+ */
+#define LL_USART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */
+#define LL_USART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data
+ * @{
+ */
+#define LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
+#define LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_AUTOCR_TRIGSEL Autonomous Trigger Selection
+ * @brief USART Autonomous Trigger selection
+ * @{
+ */
+#define LL_USART_GPDMA1_CH0_TCF_TRG 0U /*!< USART GPDMA1 channel0 Internal Trigger */
+#define LL_USART_GPDMA1_CH1_TCF_TRG 1U /*!< USART GPDMA1 channel1 Internal Trigger */
+#define LL_USART_GPDMA1_CH2_TCF_TRG 2U /*!< USART GPDMA1 channel2 Internal Trigger */
+#define LL_USART_GPDMA1_CH3_TCF_TRG 3U /*!< USART GPDMA1 channel3 Internal Trigger */
+#define LL_USART_EXTI_LINE6_TRG 4U /*!< USART EXTI line 6 Internal Trigger */
+#define LL_USART_EXTI_LINE9_TRG 5U /*!< USART EXTI line 9 Internal Trigger */
+#define LL_USART_LPTIM1_OUT_TRG 6U /*!< USART LPTIM1 out Internal Trigger */
+#define LL_USART_LPTIM2_OUT_TRG 7U /*!< USART LPTIM2 out Internal Trigger */
+#define LL_USART_COMP1_OUT_TRG 8U /*!< USART COMP1 out Internal Trigger */
+#define LL_USART_COMP2_OUT_TRG 9U /*!< USART COMP2 out Internal Trigger */
+#define LL_USART_RTC_ALRA_TRG 10U /*!< USART RTC alarm Internal Trigger */
+#define LL_USART_RTC_WUT_TRG 11U /*!< USART RTC wakeup Internal Trigger */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_AUTOCR_TRIGPOL Autonomous Trigger Polarity
+ * @brief USART Autonomous Trigger Polarity
+ * @{
+ */
+#define LL_USART_TRIG_POLARITY_RISING 0x00000000U /*!< USART triggered on rising edge */
+#define LL_USART_TRIG_POLARITY_FALLING USART_AUTOCR_TRIGPOL /*!< USART triggered on falling edge */
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup USART_LL_Exported_Macros USART Exported Macros
+ * @{
+ */
+
+/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in USART register
+ * @param __INSTANCE__ USART Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in USART register
+ * @param __INSTANCE__ USART Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
+ * @{
+ */
+
+/**
+ * @brief Compute USARTDIV value according to Peripheral Clock and
+ * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
+ * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+ * @param __PRESCALER__ This parameter can be one of the following values:
+ * @arg @ref LL_USART_PRESCALER_DIV1
+ * @arg @ref LL_USART_PRESCALER_DIV2
+ * @arg @ref LL_USART_PRESCALER_DIV4
+ * @arg @ref LL_USART_PRESCALER_DIV6
+ * @arg @ref LL_USART_PRESCALER_DIV8
+ * @arg @ref LL_USART_PRESCALER_DIV10
+ * @arg @ref LL_USART_PRESCALER_DIV12
+ * @arg @ref LL_USART_PRESCALER_DIV16
+ * @arg @ref LL_USART_PRESCALER_DIV32
+ * @arg @ref LL_USART_PRESCALER_DIV64
+ * @arg @ref LL_USART_PRESCALER_DIV128
+ * @arg @ref LL_USART_PRESCALER_DIV256
+ * @param __BAUDRATE__ Baud rate value to achieve
+ * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
+ */
+#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
+ (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\
+ + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
+
+/**
+ * @brief Compute USARTDIV value according to Peripheral Clock and
+ * expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
+ * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+ * @param __PRESCALER__ This parameter can be one of the following values:
+ * @arg @ref LL_USART_PRESCALER_DIV1
+ * @arg @ref LL_USART_PRESCALER_DIV2
+ * @arg @ref LL_USART_PRESCALER_DIV4
+ * @arg @ref LL_USART_PRESCALER_DIV6
+ * @arg @ref LL_USART_PRESCALER_DIV8
+ * @arg @ref LL_USART_PRESCALER_DIV10
+ * @arg @ref LL_USART_PRESCALER_DIV12
+ * @arg @ref LL_USART_PRESCALER_DIV16
+ * @arg @ref LL_USART_PRESCALER_DIV32
+ * @arg @ref LL_USART_PRESCALER_DIV64
+ * @arg @ref LL_USART_PRESCALER_DIV128
+ * @arg @ref LL_USART_PRESCALER_DIV256
+ * @param __BAUDRATE__ Baud rate value to achieve
+ * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
+ */
+#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
+ ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\
+ + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup USART_LL_Exported_Functions USART Exported Functions
+ * @{
+ */
+
+/** @defgroup USART_LL_EF_Configuration Configuration functions
+ * @{
+ */
+
+/**
+ * @brief USART Enable
+ * @rmtoll CR1 UE LL_USART_Enable
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_UE);
+}
+
+/**
+ * @brief USART Disable (all USART prescalers and outputs are disabled)
+ * @note When USART is disabled, USART prescalers and outputs are stopped immediately,
+ * and current operations are discarded. The configuration of the USART is kept, but all the status
+ * flags, in the USARTx_ISR are set to their default values.
+ * @rmtoll CR1 UE LL_USART_Disable
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
+}
+
+/**
+ * @brief Indicate if USART is enabled
+ * @rmtoll CR1 UE LL_USART_IsEnabled
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief FIFO Mode Enable
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 FIFOEN LL_USART_EnableFIFO
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableFIFO(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_FIFOEN);
+}
+
+/**
+ * @brief FIFO Mode Disable
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 FIFOEN LL_USART_DisableFIFO
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_FIFOEN);
+}
+
+/**
+ * @brief Indicate if FIFO Mode is enabled
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 FIFOEN LL_USART_IsEnabledFIFO
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure TX FIFO Threshold
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 TXFTCFG LL_USART_SetTXFIFOThreshold
+ * @param USARTx USART Instance
+ * @param Threshold This parameter can be one of the following values:
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+ * @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+ * @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+ * @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
+{
+ ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
+}
+
+/**
+ * @brief Return TX FIFO Threshold Configuration
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 TXFTCFG LL_USART_GetTXFIFOThreshold
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+ * @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+ * @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+ * @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+ */
+__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
+}
+
+/**
+ * @brief Configure RX FIFO Threshold
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 RXFTCFG LL_USART_SetRXFIFOThreshold
+ * @param USARTx USART Instance
+ * @param Threshold This parameter can be one of the following values:
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+ * @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+ * @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+ * @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
+{
+ ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
+}
+
+/**
+ * @brief Return RX FIFO Threshold Configuration
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 RXFTCFG LL_USART_GetRXFIFOThreshold
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+ * @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+ * @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+ * @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+ */
+__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
+}
+
+/**
+ * @brief Configure TX and RX FIFOs Threshold
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 TXFTCFG LL_USART_ConfigFIFOsThreshold\n
+ * CR3 RXFTCFG LL_USART_ConfigFIFOsThreshold
+ * @param USARTx USART Instance
+ * @param TXThreshold This parameter can be one of the following values:
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+ * @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+ * @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+ * @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+ * @param RXThreshold This parameter can be one of the following values:
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+ * @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+ * @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+ * @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold)
+{
+ ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) |
+ (RXThreshold << USART_CR3_RXFTCFG_Pos));
+}
+
+/**
+ * @brief USART enabled in STOP Mode.
+ * @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that
+ * USART clock selection is HSI or LSE in RCC.
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 UESM LL_USART_EnableInStopMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+ * @brief USART disabled in STOP Mode.
+ * @note When this function is disabled, USART is not able to wake up the MCU from Stop mode
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 UESM LL_USART_DisableInStopMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+ * @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 UESM LL_USART_IsEnabledInStopMode
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit)
+ * @rmtoll CR1 RE LL_USART_EnableDirectionRx
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE);
+}
+
+/**
+ * @brief Receiver Disable
+ * @rmtoll CR1 RE LL_USART_DisableDirectionRx
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
+}
+
+/**
+ * @brief Transmitter Enable
+ * @rmtoll CR1 TE LL_USART_EnableDirectionTx
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE);
+}
+
+/**
+ * @brief Transmitter Disable
+ * @rmtoll CR1 TE LL_USART_DisableDirectionTx
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
+}
+
+/**
+ * @brief Configure simultaneously enabled/disabled states
+ * of Transmitter and Receiver
+ * @rmtoll CR1 RE LL_USART_SetTransferDirection\n
+ * CR1 TE LL_USART_SetTransferDirection
+ * @param USARTx USART Instance
+ * @param TransferDirection This parameter can be one of the following values:
+ * @arg @ref LL_USART_DIRECTION_NONE
+ * @arg @ref LL_USART_DIRECTION_RX
+ * @arg @ref LL_USART_DIRECTION_TX
+ * @arg @ref LL_USART_DIRECTION_TX_RX
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
+{
+ ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
+}
+
+/**
+ * @brief Return enabled/disabled states of Transmitter and Receiver
+ * @rmtoll CR1 RE LL_USART_GetTransferDirection\n
+ * CR1 TE LL_USART_GetTransferDirection
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_DIRECTION_NONE
+ * @arg @ref LL_USART_DIRECTION_RX
+ * @arg @ref LL_USART_DIRECTION_TX
+ * @arg @ref LL_USART_DIRECTION_TX_RX
+ */
+__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
+}
+
+/**
+ * @brief Configure Parity (enabled/disabled and parity mode if enabled).
+ * @note This function selects if hardware parity control (generation and detection) is enabled or disabled.
+ * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
+ * (9th or 8th bit depending on data width) and parity is checked on the received data.
+ * @rmtoll CR1 PS LL_USART_SetParity\n
+ * CR1 PCE LL_USART_SetParity
+ * @param USARTx USART Instance
+ * @param Parity This parameter can be one of the following values:
+ * @arg @ref LL_USART_PARITY_NONE
+ * @arg @ref LL_USART_PARITY_EVEN
+ * @arg @ref LL_USART_PARITY_ODD
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
+}
+
+/**
+ * @brief Return Parity configuration (enabled/disabled and parity mode if enabled)
+ * @rmtoll CR1 PS LL_USART_GetParity\n
+ * CR1 PCE LL_USART_GetParity
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_PARITY_NONE
+ * @arg @ref LL_USART_PARITY_EVEN
+ * @arg @ref LL_USART_PARITY_ODD
+ */
+__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
+}
+
+/**
+ * @brief Set Receiver Wake Up method from Mute mode.
+ * @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod
+ * @param USARTx USART Instance
+ * @param Method This parameter can be one of the following values:
+ * @arg @ref LL_USART_WAKEUP_IDLELINE
+ * @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
+}
+
+/**
+ * @brief Return Receiver Wake Up method from Mute mode
+ * @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_WAKEUP_IDLELINE
+ * @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+ */
+__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
+}
+
+/**
+ * @brief Set Word length (i.e. nb of data bits, excluding start and stop bits)
+ * @rmtoll CR1 M0 LL_USART_SetDataWidth\n
+ * CR1 M1 LL_USART_SetDataWidth
+ * @param USARTx USART Instance
+ * @param DataWidth This parameter can be one of the following values:
+ * @arg @ref LL_USART_DATAWIDTH_7B
+ * @arg @ref LL_USART_DATAWIDTH_8B
+ * @arg @ref LL_USART_DATAWIDTH_9B
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
+}
+
+/**
+ * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits)
+ * @rmtoll CR1 M0 LL_USART_GetDataWidth\n
+ * CR1 M1 LL_USART_GetDataWidth
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_DATAWIDTH_7B
+ * @arg @ref LL_USART_DATAWIDTH_8B
+ * @arg @ref LL_USART_DATAWIDTH_9B
+ */
+__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
+}
+
+/**
+ * @brief Allow switch between Mute Mode and Active mode
+ * @rmtoll CR1 MME LL_USART_EnableMuteMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME);
+}
+
+/**
+ * @brief Prevent Mute Mode use. Set Receiver in active mode permanently.
+ * @rmtoll CR1 MME LL_USART_DisableMuteMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME);
+}
+
+/**
+ * @brief Indicate if switch between Mute Mode and Active mode is allowed
+ * @rmtoll CR1 MME LL_USART_IsEnabledMuteMode
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set Oversampling to 8-bit or 16-bit mode
+ * @rmtoll CR1 OVER8 LL_USART_SetOverSampling
+ * @param USARTx USART Instance
+ * @param OverSampling This parameter can be one of the following values:
+ * @arg @ref LL_USART_OVERSAMPLING_16
+ * @arg @ref LL_USART_OVERSAMPLING_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
+}
+
+/**
+ * @brief Return Oversampling mode
+ * @rmtoll CR1 OVER8 LL_USART_GetOverSampling
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_OVERSAMPLING_16
+ * @arg @ref LL_USART_OVERSAMPLING_8
+ */
+__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
+}
+
+/**
+ * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput
+ * @param USARTx USART Instance
+ * @param LastBitClockPulse This parameter can be one of the following values:
+ * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+ * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
+}
+
+/**
+ * @brief Retrieve Clock pulse of the last data bit output configuration
+ * (Last bit Clock pulse output to the SCLK pin or not)
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+ * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+ */
+__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
+}
+
+/**
+ * @brief Select the phase of the clock output on the SCLK pin in synchronous mode
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CPHA LL_USART_SetClockPhase
+ * @param USARTx USART Instance
+ * @param ClockPhase This parameter can be one of the following values:
+ * @arg @ref LL_USART_PHASE_1EDGE
+ * @arg @ref LL_USART_PHASE_2EDGE
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
+}
+
+/**
+ * @brief Return phase of the clock output on the SCLK pin in synchronous mode
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CPHA LL_USART_GetClockPhase
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_PHASE_1EDGE
+ * @arg @ref LL_USART_PHASE_2EDGE
+ */
+__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
+}
+
+/**
+ * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CPOL LL_USART_SetClockPolarity
+ * @param USARTx USART Instance
+ * @param ClockPolarity This parameter can be one of the following values:
+ * @arg @ref LL_USART_POLARITY_LOW
+ * @arg @ref LL_USART_POLARITY_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
+}
+
+/**
+ * @brief Return polarity of the clock output on the SCLK pin in synchronous mode
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CPOL LL_USART_GetClockPolarity
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_POLARITY_LOW
+ * @arg @ref LL_USART_POLARITY_HIGH
+ */
+__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
+}
+
+/**
+ * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
+ * - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function
+ * - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function
+ * @rmtoll CR2 CPHA LL_USART_ConfigClock\n
+ * CR2 CPOL LL_USART_ConfigClock\n
+ * CR2 LBCL LL_USART_ConfigClock
+ * @param USARTx USART Instance
+ * @param Phase This parameter can be one of the following values:
+ * @arg @ref LL_USART_PHASE_1EDGE
+ * @arg @ref LL_USART_PHASE_2EDGE
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_USART_POLARITY_LOW
+ * @arg @ref LL_USART_POLARITY_HIGH
+ * @param LBCPOutput This parameter can be one of the following values:
+ * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+ * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);
+}
+
+/**
+ * @brief Configure Clock source prescaler for baudrate generator and oversampling
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll PRESC PRESCALER LL_USART_SetPrescaler
+ * @param USARTx USART Instance
+ * @param PrescalerValue This parameter can be one of the following values:
+ * @arg @ref LL_USART_PRESCALER_DIV1
+ * @arg @ref LL_USART_PRESCALER_DIV2
+ * @arg @ref LL_USART_PRESCALER_DIV4
+ * @arg @ref LL_USART_PRESCALER_DIV6
+ * @arg @ref LL_USART_PRESCALER_DIV8
+ * @arg @ref LL_USART_PRESCALER_DIV10
+ * @arg @ref LL_USART_PRESCALER_DIV12
+ * @arg @ref LL_USART_PRESCALER_DIV16
+ * @arg @ref LL_USART_PRESCALER_DIV32
+ * @arg @ref LL_USART_PRESCALER_DIV64
+ * @arg @ref LL_USART_PRESCALER_DIV128
+ * @arg @ref LL_USART_PRESCALER_DIV256
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+ MODIFY_REG(USARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
+}
+
+/**
+ * @brief Retrieve the Clock source prescaler for baudrate generator and oversampling
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll PRESC PRESCALER LL_USART_GetPrescaler
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_PRESCALER_DIV1
+ * @arg @ref LL_USART_PRESCALER_DIV2
+ * @arg @ref LL_USART_PRESCALER_DIV4
+ * @arg @ref LL_USART_PRESCALER_DIV6
+ * @arg @ref LL_USART_PRESCALER_DIV8
+ * @arg @ref LL_USART_PRESCALER_DIV10
+ * @arg @ref LL_USART_PRESCALER_DIV12
+ * @arg @ref LL_USART_PRESCALER_DIV16
+ * @arg @ref LL_USART_PRESCALER_DIV32
+ * @arg @ref LL_USART_PRESCALER_DIV64
+ * @arg @ref LL_USART_PRESCALER_DIV128
+ * @arg @ref LL_USART_PRESCALER_DIV256
+ */
+__STATIC_INLINE uint32_t LL_USART_GetPrescaler(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->PRESC, USART_PRESC_PRESCALER));
+}
+
+/**
+ * @brief Enable Clock output on SCLK pin
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+ * @brief Disable Clock output on SCLK pin
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+ * @brief Indicate if Clock output on SCLK pin is enabled
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set the length of the stop bits
+ * @rmtoll CR2 STOP LL_USART_SetStopBitsLength
+ * @param USARTx USART Instance
+ * @param StopBits This parameter can be one of the following values:
+ * @arg @ref LL_USART_STOPBITS_0_5
+ * @arg @ref LL_USART_STOPBITS_1
+ * @arg @ref LL_USART_STOPBITS_1_5
+ * @arg @ref LL_USART_STOPBITS_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+ * @brief Retrieve the length of the stop bits
+ * @rmtoll CR2 STOP LL_USART_GetStopBitsLength
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_STOPBITS_0_5
+ * @arg @ref LL_USART_STOPBITS_1
+ * @arg @ref LL_USART_STOPBITS_1_5
+ * @arg @ref LL_USART_STOPBITS_2
+ */
+__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
+}
+
+/**
+ * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits)
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Data Width configuration using @ref LL_USART_SetDataWidth() function
+ * - Parity Control and mode configuration using @ref LL_USART_SetParity() function
+ * - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function
+ * @rmtoll CR1 PS LL_USART_ConfigCharacter\n
+ * CR1 PCE LL_USART_ConfigCharacter\n
+ * CR1 M0 LL_USART_ConfigCharacter\n
+ * CR1 M1 LL_USART_ConfigCharacter\n
+ * CR2 STOP LL_USART_ConfigCharacter
+ * @param USARTx USART Instance
+ * @param DataWidth This parameter can be one of the following values:
+ * @arg @ref LL_USART_DATAWIDTH_7B
+ * @arg @ref LL_USART_DATAWIDTH_8B
+ * @arg @ref LL_USART_DATAWIDTH_9B
+ * @param Parity This parameter can be one of the following values:
+ * @arg @ref LL_USART_PARITY_NONE
+ * @arg @ref LL_USART_PARITY_EVEN
+ * @arg @ref LL_USART_PARITY_ODD
+ * @param StopBits This parameter can be one of the following values:
+ * @arg @ref LL_USART_STOPBITS_0_5
+ * @arg @ref LL_USART_STOPBITS_1
+ * @arg @ref LL_USART_STOPBITS_1_5
+ * @arg @ref LL_USART_STOPBITS_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,
+ uint32_t StopBits)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
+ MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+ * @brief Configure TX/RX pins swapping setting.
+ * @rmtoll CR2 SWAP LL_USART_SetTXRXSwap
+ * @param USARTx USART Instance
+ * @param SwapConfig This parameter can be one of the following values:
+ * @arg @ref LL_USART_TXRX_STANDARD
+ * @arg @ref LL_USART_TXRX_SWAPPED
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig);
+}
+
+/**
+ * @brief Retrieve TX/RX pins swapping configuration.
+ * @rmtoll CR2 SWAP LL_USART_GetTXRXSwap
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_TXRX_STANDARD
+ * @arg @ref LL_USART_TXRX_SWAPPED
+ */
+__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP));
+}
+
+/**
+ * @brief Configure RX pin active level logic
+ * @rmtoll CR2 RXINV LL_USART_SetRXPinLevel
+ * @param USARTx USART Instance
+ * @param PinInvMethod This parameter can be one of the following values:
+ * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
+ * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod);
+}
+
+/**
+ * @brief Retrieve RX pin active level logic configuration
+ * @rmtoll CR2 RXINV LL_USART_GetRXPinLevel
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
+ * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
+ */
+__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV));
+}
+
+/**
+ * @brief Configure TX pin active level logic
+ * @rmtoll CR2 TXINV LL_USART_SetTXPinLevel
+ * @param USARTx USART Instance
+ * @param PinInvMethod This parameter can be one of the following values:
+ * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
+ * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod);
+}
+
+/**
+ * @brief Retrieve TX pin active level logic configuration
+ * @rmtoll CR2 TXINV LL_USART_GetTXPinLevel
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
+ * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
+ */
+__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV));
+}
+
+/**
+ * @brief Configure Binary data logic.
+ * @note Allow to define how Logical data from the data register are send/received :
+ * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
+ * @rmtoll CR2 DATAINV LL_USART_SetBinaryDataLogic
+ * @param USARTx USART Instance
+ * @param DataLogic This parameter can be one of the following values:
+ * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
+ * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic);
+}
+
+/**
+ * @brief Retrieve Binary data configuration
+ * @rmtoll CR2 DATAINV LL_USART_GetBinaryDataLogic
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
+ * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
+ */
+__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV));
+}
+
+/**
+ * @brief Configure transfer bit order (either Less or Most Significant Bit First)
+ * @note MSB First means data is transmitted/received with the MSB first, following the start bit.
+ * LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+ * @rmtoll CR2 MSBFIRST LL_USART_SetTransferBitOrder
+ * @param USARTx USART Instance
+ * @param BitOrder This parameter can be one of the following values:
+ * @arg @ref LL_USART_BITORDER_LSBFIRST
+ * @arg @ref LL_USART_BITORDER_MSBFIRST
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
+}
+
+/**
+ * @brief Return transfer bit order (either Less or Most Significant Bit First)
+ * @note MSB First means data is transmitted/received with the MSB first, following the start bit.
+ * LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+ * @rmtoll CR2 MSBFIRST LL_USART_GetTransferBitOrder
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_BITORDER_LSBFIRST
+ * @arg @ref LL_USART_BITORDER_MSBFIRST
+ */
+__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST));
+}
+
+/**
+ * @brief Enable Auto Baud-Rate Detection
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * Auto Baud Rate detection feature is supported by the USARTx instance.
+ * @rmtoll CR2 ABREN LL_USART_EnableAutoBaudRate
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR2, USART_CR2_ABREN);
+}
+
+/**
+ * @brief Disable Auto Baud-Rate Detection
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * Auto Baud Rate detection feature is supported by the USARTx instance.
+ * @rmtoll CR2 ABREN LL_USART_DisableAutoBaudRate
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN);
+}
+
+/**
+ * @brief Indicate if Auto Baud-Rate Detection mechanism is enabled
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * Auto Baud Rate detection feature is supported by the USARTx instance.
+ * @rmtoll CR2 ABREN LL_USART_IsEnabledAutoBaud
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set Auto Baud-Rate mode bits
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * Auto Baud Rate detection feature is supported by the USARTx instance.
+ * @rmtoll CR2 ABRMODE LL_USART_SetAutoBaudRateMode
+ * @param USARTx USART Instance
+ * @param AutoBaudRateMode This parameter can be one of the following values:
+ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
+ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
+ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
+ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode);
+}
+
+/**
+ * @brief Return Auto Baud-Rate mode
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * Auto Baud Rate detection feature is supported by the USARTx instance.
+ * @rmtoll CR2 ABRMODE LL_USART_GetAutoBaudRateMode
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
+ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
+ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
+ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
+ */
+__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));
+}
+
+/**
+ * @brief Enable Receiver Timeout
+ * @rmtoll CR2 RTOEN LL_USART_EnableRxTimeout
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR2, USART_CR2_RTOEN);
+}
+
+/**
+ * @brief Disable Receiver Timeout
+ * @rmtoll CR2 RTOEN LL_USART_DisableRxTimeout
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN);
+}
+
+/**
+ * @brief Indicate if Receiver Timeout feature is enabled
+ * @rmtoll CR2 RTOEN LL_USART_IsEnabledRxTimeout
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set Address of the USART node.
+ * @note This is used in multiprocessor communication during Mute mode or Stop mode,
+ * for wake up with address mark detection.
+ * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7.
+ * (b7-b4 should be set to 0)
+ * 8bits address node is used when 7-bit Address Detection is selected in ADDM7.
+ * (This is used in multiprocessor communication during Mute mode or Stop mode,
+ * for wake up with 7-bit address mark detection.
+ * The MSB of the character sent by the transmitter should be equal to 1.
+ * It may also be used for character detection during normal reception,
+ * Mute mode inactive (for example, end of block detection in ModBus protocol).
+ * In this case, the whole received character (8-bit) is compared to the ADD[7:0]
+ * value and CMF flag is set on match)
+ * @rmtoll CR2 ADD LL_USART_ConfigNodeAddress\n
+ * CR2 ADDM7 LL_USART_ConfigNodeAddress
+ * @param USARTx USART Instance
+ * @param AddressLen This parameter can be one of the following values:
+ * @arg @ref LL_USART_ADDRESS_DETECT_4B
+ * @arg @ref LL_USART_ADDRESS_DETECT_7B
+ * @param NodeAddress 4 or 7 bit Address of the USART node.
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
+ (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
+}
+
+/**
+ * @brief Return 8 bit Address of the USART node as set in ADD field of CR2.
+ * @note If 4-bit Address Detection is selected in ADDM7,
+ * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
+ * If 7-bit Address Detection is selected in ADDM7,
+ * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
+ * @rmtoll CR2 ADD LL_USART_GetNodeAddress
+ * @param USARTx USART Instance
+ * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
+ */
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
+}
+
+/**
+ * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
+ * @rmtoll CR2 ADDM7 LL_USART_GetNodeAddressLen
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_ADDRESS_DETECT_4B
+ * @arg @ref LL_USART_ADDRESS_DETECT_7B
+ */
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7));
+}
+
+/**
+ * @brief Enable RTS HW Flow Control
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+ * @brief Disable RTS HW Flow Control
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+ * @brief Enable CTS HW Flow Control
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+ * @brief Disable CTS HW Flow Control
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+ * @brief Configure HW Flow Control mode (both CTS and RTS)
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n
+ * CR3 CTSE LL_USART_SetHWFlowCtrl
+ * @param USARTx USART Instance
+ * @param HardwareFlowControl This parameter can be one of the following values:
+ * @arg @ref LL_USART_HWCONTROL_NONE
+ * @arg @ref LL_USART_HWCONTROL_RTS
+ * @arg @ref LL_USART_HWCONTROL_CTS
+ * @arg @ref LL_USART_HWCONTROL_RTS_CTS
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
+{
+ MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
+}
+
+/**
+ * @brief Return HW Flow Control configuration (both CTS and RTS)
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n
+ * CR3 CTSE LL_USART_GetHWFlowCtrl
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_HWCONTROL_NONE
+ * @arg @ref LL_USART_HWCONTROL_RTS
+ * @arg @ref LL_USART_HWCONTROL_CTS
+ * @arg @ref LL_USART_HWCONTROL_RTS_CTS
+ */
+__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
+}
+
+/**
+ * @brief Enable One bit sampling method
+ * @rmtoll CR3 ONEBIT LL_USART_EnableOneBitSamp
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+}
+
+/**
+ * @brief Disable One bit sampling method
+ * @rmtoll CR3 ONEBIT LL_USART_DisableOneBitSamp
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+}
+
+/**
+ * @brief Indicate if One bit sampling method is enabled
+ * @rmtoll CR3 ONEBIT LL_USART_IsEnabledOneBitSamp
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable Overrun detection
+ * @rmtoll CR3 OVRDIS LL_USART_EnableOverrunDetect
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+ * @brief Disable Overrun detection
+ * @rmtoll CR3 OVRDIS LL_USART_DisableOverrunDetect
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+ * @brief Indicate if Overrun detection is enabled
+ * @rmtoll CR3 OVRDIS LL_USART_IsEnabledOverrunDetect
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure USART BRR register for achieving expected Baud Rate value.
+ * @note Compute and set USARTDIV value in BRR Register (full BRR content)
+ * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
+ * @note Peripheral clock and Baud rate values provided as function parameters should be valid
+ * (Baud rate value != 0)
+ * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
+ * @rmtoll BRR BRR LL_USART_SetBaudRate
+ * @param USARTx USART Instance
+ * @param PeriphClk Peripheral Clock
+ * @param PrescalerValue This parameter can be one of the following values:
+ * @arg @ref LL_USART_PRESCALER_DIV1
+ * @arg @ref LL_USART_PRESCALER_DIV2
+ * @arg @ref LL_USART_PRESCALER_DIV4
+ * @arg @ref LL_USART_PRESCALER_DIV6
+ * @arg @ref LL_USART_PRESCALER_DIV8
+ * @arg @ref LL_USART_PRESCALER_DIV10
+ * @arg @ref LL_USART_PRESCALER_DIV12
+ * @arg @ref LL_USART_PRESCALER_DIV16
+ * @arg @ref LL_USART_PRESCALER_DIV32
+ * @arg @ref LL_USART_PRESCALER_DIV64
+ * @arg @ref LL_USART_PRESCALER_DIV128
+ * @arg @ref LL_USART_PRESCALER_DIV256
+ * @param OverSampling This parameter can be one of the following values:
+ * @arg @ref LL_USART_OVERSAMPLING_16
+ * @arg @ref LL_USART_OVERSAMPLING_8
+ * @param BaudRate Baud Rate
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
+ uint32_t OverSampling,
+ uint32_t BaudRate)
+{
+ uint32_t usartdiv;
+ uint32_t brrtemp;
+
+ if (PrescalerValue > LL_USART_PRESCALER_DIV256)
+ {
+ /* Do not overstep the size of USART_PRESCALER_TAB */
+ }
+ else if (BaudRate == 0U)
+ {
+ /* Can Not divide per 0 */
+ }
+ else if (OverSampling == LL_USART_OVERSAMPLING_8)
+ {
+ usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
+ brrtemp = usartdiv & 0xFFF0U;
+ brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+ USARTx->BRR = brrtemp;
+ }
+ else
+ {
+ USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
+ }
+}
+
+/**
+ * @brief Return current Baud Rate value, according to USARTDIV present in BRR register
+ * (full BRR content), and to used Peripheral Clock and Oversampling mode values
+ * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
+ * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
+ * @rmtoll BRR BRR LL_USART_GetBaudRate
+ * @param USARTx USART Instance
+ * @param PeriphClk Peripheral Clock
+ * @param PrescalerValue This parameter can be one of the following values:
+ * @arg @ref LL_USART_PRESCALER_DIV1
+ * @arg @ref LL_USART_PRESCALER_DIV2
+ * @arg @ref LL_USART_PRESCALER_DIV4
+ * @arg @ref LL_USART_PRESCALER_DIV6
+ * @arg @ref LL_USART_PRESCALER_DIV8
+ * @arg @ref LL_USART_PRESCALER_DIV10
+ * @arg @ref LL_USART_PRESCALER_DIV12
+ * @arg @ref LL_USART_PRESCALER_DIV16
+ * @arg @ref LL_USART_PRESCALER_DIV32
+ * @arg @ref LL_USART_PRESCALER_DIV64
+ * @arg @ref LL_USART_PRESCALER_DIV128
+ * @arg @ref LL_USART_PRESCALER_DIV256
+ * @param OverSampling This parameter can be one of the following values:
+ * @arg @ref LL_USART_OVERSAMPLING_16
+ * @arg @ref LL_USART_OVERSAMPLING_8
+ * @retval Baud Rate
+ */
+__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
+ uint32_t OverSampling)
+{
+ uint32_t usartdiv;
+ uint32_t brrresult = 0x0U;
+ uint32_t periphclkpresc = (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue]));
+
+ usartdiv = USARTx->BRR;
+
+ if (usartdiv == 0U)
+ {
+ /* Do not perform a division by 0 */
+ }
+ else if (OverSampling == LL_USART_OVERSAMPLING_8)
+ {
+ usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
+ if (usartdiv != 0U)
+ {
+ brrresult = (periphclkpresc * 2U) / usartdiv;
+ }
+ }
+ else
+ {
+ if ((usartdiv & 0xFFFFU) != 0U)
+ {
+ brrresult = periphclkpresc / usartdiv;
+ }
+ }
+ return (brrresult);
+}
+
+/**
+ * @brief Set Receiver Time Out Value (expressed in nb of bits duration)
+ * @rmtoll RTOR RTO LL_USART_SetRxTimeout
+ * @param USARTx USART Instance
+ * @param Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout)
+{
+ MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout);
+}
+
+/**
+ * @brief Get Receiver Time Out Value (expressed in nb of bits duration)
+ * @rmtoll RTOR RTO LL_USART_GetRxTimeout
+ * @param USARTx USART Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
+ */
+__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO));
+}
+
+/**
+ * @brief Set Block Length value in reception
+ * @rmtoll RTOR BLEN LL_USART_SetBlockLength
+ * @param USARTx USART Instance
+ * @param BlockLength Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength)
+{
+ MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos);
+}
+
+/**
+ * @brief Get Block Length value in reception
+ * @rmtoll RTOR BLEN LL_USART_GetBlockLength
+ * @param USARTx USART Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature
+ * @{
+ */
+
+/**
+ * @brief Enable IrDA mode
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll CR3 IREN LL_USART_EnableIrda
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+ * @brief Disable IrDA mode
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll CR3 IREN LL_USART_DisableIrda
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+ * @brief Indicate if IrDA mode is enabled
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll CR3 IREN LL_USART_IsEnabledIrda
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure IrDA Power Mode (Normal or Low Power)
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode
+ * @param USARTx USART Instance
+ * @param PowerMode This parameter can be one of the following values:
+ * @arg @ref LL_USART_IRDA_POWER_NORMAL
+ * @arg @ref LL_USART_IRDA_POWER_LOW
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
+{
+ MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
+}
+
+/**
+ * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power)
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_IRDA_POWER_NORMAL
+ * @arg @ref LL_USART_PHASE_2EDGE
+ */
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
+}
+
+/**
+ * @brief Set Irda prescaler value, used for dividing the USART clock source
+ * to achieve the Irda Low Power frequency (8 bits value)
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler
+ * @param USARTx USART Instance
+ * @param PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+ MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)PrescalerValue);
+}
+
+/**
+ * @brief Return Irda prescaler value, used for dividing the USART clock source
+ * to achieve the Irda Low Power frequency (8 bits value)
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler
+ * @param USARTx USART Instance
+ * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
+ */
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature
+ * @{
+ */
+
+/**
+ * @brief Enable Smartcard NACK transmission
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_NACK);
+}
+
+/**
+ * @brief Disable Smartcard NACK transmission
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
+}
+
+/**
+ * @brief Indicate if Smartcard NACK transmission is enabled
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable Smartcard mode
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 SCEN LL_USART_EnableSmartcard
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+ * @brief Disable Smartcard mode
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 SCEN LL_USART_DisableSmartcard
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+ * @brief Indicate if Smartcard mode is enabled
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @note This bit-field specifies the number of retries in transmit and receive, in Smartcard mode.
+ * In transmission mode, it specifies the number of automatic retransmission retries, before
+ * generating a transmission error (FE bit set).
+ * In reception mode, it specifies the number or erroneous reception trials, before generating a
+ * reception error (RXNE and PE bits set)
+ * @rmtoll CR3 SCARCNT LL_USART_SetSmartcardAutoRetryCount
+ * @param USARTx USART Instance
+ * @param AutoRetryCount Value between Min_Data=0 and Max_Data=7
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount)
+{
+ MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos);
+}
+
+/**
+ * @brief Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount
+ * @param USARTx USART Instance
+ * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)
+ */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos);
+}
+
+/**
+ * @brief Set Smartcard prescaler value, used for dividing the USART clock
+ * source to provide the SMARTCARD Clock (5 bits value)
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler
+ * @param USARTx USART Instance
+ * @param PrescalerValue Value between Min_Data=0 and Max_Data=31
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+ MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)PrescalerValue);
+}
+
+/**
+ * @brief Return Smartcard prescaler value, used for dividing the USART clock
+ * source to provide the SMARTCARD Clock (5 bits value)
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler
+ * @param USARTx USART Instance
+ * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
+ */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+}
+
+/**
+ * @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods
+ * (GT[7:0] bits : Guard time value)
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime
+ * @param USARTx USART Instance
+ * @param GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
+{
+ MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos));
+}
+
+/**
+ * @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods
+ * (GT[7:0] bits : Guard time value)
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime
+ * @param USARTx USART Instance
+ * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
+ */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
+ * @{
+ */
+
+/**
+ * @brief Enable Single Wire Half-Duplex mode
+ * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * Half-Duplex mode is supported by the USARTx instance.
+ * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+ * @brief Disable Single Wire Half-Duplex mode
+ * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * Half-Duplex mode is supported by the USARTx instance.
+ * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+ * @brief Indicate if Single Wire Half-Duplex mode is enabled
+ * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * Half-Duplex mode is supported by the USARTx instance.
+ * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Configuration_SPI_SLAVE Configuration functions related to SPI Slave feature
+ * @{
+ */
+/**
+ * @brief Enable SPI Synchronous Slave mode
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+ * SPI Slave mode feature is supported by the USARTx instance.
+ * @rmtoll CR2 SLVEN LL_USART_EnableSPISlave
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR2, USART_CR2_SLVEN);
+}
+
+/**
+ * @brief Disable SPI Synchronous Slave mode
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+ * SPI Slave mode feature is supported by the USARTx instance.
+ * @rmtoll CR2 SLVEN LL_USART_DisableSPISlave
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR2, USART_CR2_SLVEN);
+}
+
+/**
+ * @brief Indicate if SPI Synchronous Slave mode is enabled
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+ * SPI Slave mode feature is supported by the USARTx instance.
+ * @rmtoll CR2 SLVEN LL_USART_IsEnabledSPISlave
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable SPI Slave Selection using NSS input pin
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+ * SPI Slave mode feature is supported by the USARTx instance.
+ * @note SPI Slave Selection depends on NSS input pin
+ * (The slave is selected when NSS is low and deselected when NSS is high).
+ * @rmtoll CR2 DIS_NSS LL_USART_EnableSPISlaveSelect
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR2, USART_CR2_DIS_NSS);
+}
+
+/**
+ * @brief Disable SPI Slave Selection using NSS input pin
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+ * SPI Slave mode feature is supported by the USARTx instance.
+ * @note SPI Slave will be always selected and NSS input pin will be ignored.
+ * @rmtoll CR2 DIS_NSS LL_USART_DisableSPISlaveSelect
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR2, USART_CR2_DIS_NSS);
+}
+
+/**
+ * @brief Indicate if SPI Slave Selection depends on NSS input pin
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+ * SPI Slave mode feature is supported by the USARTx instance.
+ * @rmtoll CR2 DIS_NSS LL_USART_IsEnabledSPISlaveSelect
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature
+ * @{
+ */
+
+/**
+ * @brief Set LIN Break Detection Length
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen
+ * @param USARTx USART Instance
+ * @param LINBDLength This parameter can be one of the following values:
+ * @arg @ref LL_USART_LINBREAK_DETECT_10B
+ * @arg @ref LL_USART_LINBREAK_DETECT_11B
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
+}
+
+/**
+ * @brief Return LIN Break Detection Length
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_LINBREAK_DETECT_10B
+ * @arg @ref LL_USART_LINBREAK_DETECT_11B
+ */
+__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
+}
+
+/**
+ * @brief Enable LIN mode
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LINEN LL_USART_EnableLIN
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+ * @brief Disable LIN mode
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LINEN LL_USART_DisableLIN
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+ * @brief Indicate if LIN mode is enabled
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
+ * @{
+ */
+
+/**
+ * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR1 DEDT LL_USART_SetDEDeassertionTime
+ * @param USARTx USART Instance
+ * @param Time Value between Min_Data=0 and Max_Data=31
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
+}
+
+/**
+ * @brief Return DEDT (Driver Enable De-Assertion Time)
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR1 DEDT LL_USART_GetDEDeassertionTime
+ * @param USARTx USART Instance
+ * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
+ */
+__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
+}
+
+/**
+ * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR1 DEAT LL_USART_SetDEAssertionTime
+ * @param USARTx USART Instance
+ * @param Time Value between Min_Data=0 and Max_Data=31
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
+}
+
+/**
+ * @brief Return DEAT (Driver Enable Assertion Time)
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR1 DEAT LL_USART_GetDEAssertionTime
+ * @param USARTx USART Instance
+ * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
+ */
+__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
+}
+
+/**
+ * @brief Enable Driver Enable (DE) Mode
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR3 DEM LL_USART_EnableDEMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+ * @brief Disable Driver Enable (DE) Mode
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR3 DEM LL_USART_DisableDEMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+ * @brief Indicate if Driver Enable (DE) Mode is enabled
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR3 DEM LL_USART_IsEnabledDEMode
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Select Driver Enable Polarity
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR3 DEP LL_USART_SetDESignalPolarity
+ * @param USARTx USART Instance
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_USART_DE_POLARITY_HIGH
+ * @arg @ref LL_USART_DE_POLARITY_LOW
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity)
+{
+ MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity);
+}
+
+/**
+ * @brief Return Driver Enable Polarity
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR3 DEP LL_USART_GetDESignalPolarity
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_DE_POLARITY_HIGH
+ * @arg @ref LL_USART_DE_POLARITY_LOW
+ */
+__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
+ * @{
+ */
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
+ * @note In UART mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - CLKEN bit in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - IREN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * @note Other remaining configurations items related to Asynchronous Mode
+ * (as Baud Rate, Word length, Parity, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigAsyncMode\n
+ * CR2 CLKEN LL_USART_ConfigAsyncMode\n
+ * CR3 SCEN LL_USART_ConfigAsyncMode\n
+ * CR3 IREN LL_USART_ConfigAsyncMode\n
+ * CR3 HDSEL LL_USART_ConfigAsyncMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
+{
+ /* In Asynchronous mode, the following bits must be kept cleared:
+ - LINEN, CLKEN bits in the USART_CR2 register,
+ - SCEN, IREN and HDSEL bits in the USART_CR3 register.
+ */
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Synchronous Mode
+ * @note In Synchronous mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - IREN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * This function also sets the USART in Synchronous mode.
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+ * @note Other remaining configurations items related to Synchronous Mode
+ * (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigSyncMode\n
+ * CR2 CLKEN LL_USART_ConfigSyncMode\n
+ * CR3 SCEN LL_USART_ConfigSyncMode\n
+ * CR3 IREN LL_USART_ConfigSyncMode\n
+ * CR3 HDSEL LL_USART_ConfigSyncMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
+{
+ /* In Synchronous mode, the following bits must be kept cleared:
+ - LINEN bit in the USART_CR2 register,
+ - SCEN, IREN and HDSEL bits in the USART_CR3 register.
+ */
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+ /* set the UART/USART in Synchronous mode */
+ SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in LIN Mode
+ * @note In LIN mode, the following bits must be kept cleared:
+ * - STOP and CLKEN bits in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - IREN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * This function also set the UART/USART in LIN mode.
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+ * - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
+ * @note Other remaining configurations items related to LIN Mode
+ * (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 CLKEN LL_USART_ConfigLINMode\n
+ * CR2 STOP LL_USART_ConfigLINMode\n
+ * CR2 LINEN LL_USART_ConfigLINMode\n
+ * CR3 IREN LL_USART_ConfigLINMode\n
+ * CR3 SCEN LL_USART_ConfigLINMode\n
+ * CR3 HDSEL LL_USART_ConfigLINMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
+{
+ /* In LIN mode, the following bits must be kept cleared:
+ - STOP and CLKEN bits in the USART_CR2 register,
+ - IREN, SCEN and HDSEL bits in the USART_CR3 register.
+ */
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
+ /* Set the UART/USART in LIN mode */
+ SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Half Duplex Mode
+ * @note In Half Duplex mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - CLKEN bit in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - IREN bit in the USART_CR3 register,
+ * This function also sets the UART/USART in Half Duplex mode.
+ * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * Half-Duplex mode is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
+ * @note Other remaining configurations items related to Half Duplex Mode
+ * (as Baud Rate, Word length, Parity, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigHalfDuplexMode\n
+ * CR2 CLKEN LL_USART_ConfigHalfDuplexMode\n
+ * CR3 HDSEL LL_USART_ConfigHalfDuplexMode\n
+ * CR3 SCEN LL_USART_ConfigHalfDuplexMode\n
+ * CR3 IREN LL_USART_ConfigHalfDuplexMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
+{
+ /* In Half Duplex mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN and IREN bits in the USART_CR3 register.
+ */
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
+ /* set the UART/USART in Half Duplex mode */
+ SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Smartcard Mode
+ * @note In Smartcard mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - IREN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * This function also configures Stop bits to 1.5 bits and
+ * sets the USART in Smartcard mode (SCEN bit).
+ * Clock Output is also enabled (CLKEN).
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+ * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+ * - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
+ * @note Other remaining configurations items related to Smartcard Mode
+ * (as Baud Rate, Word length, Parity, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigSmartcardMode\n
+ * CR2 STOP LL_USART_ConfigSmartcardMode\n
+ * CR2 CLKEN LL_USART_ConfigSmartcardMode\n
+ * CR3 HDSEL LL_USART_ConfigSmartcardMode\n
+ * CR3 SCEN LL_USART_ConfigSmartcardMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
+{
+ /* In Smartcard mode, the following bits must be kept cleared:
+ - LINEN bit in the USART_CR2 register,
+ - IREN and HDSEL bits in the USART_CR3 register.
+ */
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
+ /* Configure Stop bits to 1.5 bits */
+ /* Synchronous mode is activated by default */
+ SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
+ /* set the UART/USART in Smartcard mode */
+ SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Irda Mode
+ * @note In IRDA mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - STOP and CLKEN bits in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * This function also sets the UART/USART in IRDA mode (IREN bit).
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+ * - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
+ * @note Other remaining configurations items related to Irda Mode
+ * (as Baud Rate, Word length, Power mode, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigIrdaMode\n
+ * CR2 CLKEN LL_USART_ConfigIrdaMode\n
+ * CR2 STOP LL_USART_ConfigIrdaMode\n
+ * CR3 SCEN LL_USART_ConfigIrdaMode\n
+ * CR3 HDSEL LL_USART_ConfigIrdaMode\n
+ * CR3 IREN LL_USART_ConfigIrdaMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
+{
+ /* In IRDA mode, the following bits must be kept cleared:
+ - LINEN, STOP and CLKEN bits in the USART_CR2 register,
+ - SCEN and HDSEL bits in the USART_CR3 register.
+ */
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
+ /* set the UART/USART in IRDA mode */
+ SET_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Multi processor Mode
+ * (several USARTs connected in a network, one of the USARTs can be the master,
+ * its TX output connected to the RX inputs of the other slaves USARTs).
+ * @note In MultiProcessor mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - CLKEN bit in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - IREN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * @note Other remaining configurations items related to Multi processor Mode
+ * (as Baud Rate, Wake Up Method, Node address, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigMultiProcessMode\n
+ * CR2 CLKEN LL_USART_ConfigMultiProcessMode\n
+ * CR3 SCEN LL_USART_ConfigMultiProcessMode\n
+ * CR3 HDSEL LL_USART_ConfigMultiProcessMode\n
+ * CR3 IREN LL_USART_ConfigMultiProcessMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
+{
+ /* In Multi Processor mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - IREN, SCEN and HDSEL bits in the USART_CR3 register.
+ */
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Check if the USART Parity Error Flag is set or not
+ * @rmtoll ISR PE LL_USART_IsActiveFlag_PE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART Framing Error Flag is set or not
+ * @rmtoll ISR FE LL_USART_IsActiveFlag_FE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART Noise error detected Flag is set or not
+ * @rmtoll ISR NE LL_USART_IsActiveFlag_NE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART OverRun Error Flag is set or not
+ * @rmtoll ISR ORE LL_USART_IsActiveFlag_ORE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART IDLE line detected Flag is set or not
+ * @rmtoll ISR IDLE LL_USART_IsActiveFlag_IDLE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
+}
+
+/* Legacy define */
+#define LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE
+
+/**
+ * @brief Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll ISR RXNE_RXFNE LL_USART_IsActiveFlag_RXNE_RXFNE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART Transmission Complete Flag is set or not
+ * @rmtoll ISR TC LL_USART_IsActiveFlag_TC
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
+}
+
+/* Legacy define */
+#define LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF
+
+/**
+ * @brief Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll ISR TXE_TXFNF LL_USART_IsActiveFlag_TXE_TXFNF
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART LIN Break Detection Flag is set or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll ISR LBDF LL_USART_IsActiveFlag_LBD
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART CTS interrupt Flag is set or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll ISR CTSIF LL_USART_IsActiveFlag_nCTS
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART CTS Flag is set or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll ISR CTS LL_USART_IsActiveFlag_CTS
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART Receiver Time Out Flag is set or not
+ * @rmtoll ISR RTOF LL_USART_IsActiveFlag_RTO
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART End Of Block Flag is set or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll ISR EOBF LL_USART_IsActiveFlag_EOB
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the SPI Slave Underrun error flag is set or not
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+ * SPI Slave mode feature is supported by the USARTx instance.
+ * @rmtoll ISR UDR LL_USART_IsActiveFlag_UDR
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART Auto-Baud Rate Error Flag is set or not
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * Auto Baud Rate detection feature is supported by the USARTx instance.
+ * @rmtoll ISR ABRE LL_USART_IsActiveFlag_ABRE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART Auto-Baud Rate Flag is set or not
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * Auto Baud Rate detection feature is supported by the USARTx instance.
+ * @rmtoll ISR ABRF LL_USART_IsActiveFlag_ABR
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART Busy Flag is set or not
+ * @rmtoll ISR BUSY LL_USART_IsActiveFlag_BUSY
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART Character Match Flag is set or not
+ * @rmtoll ISR CMF LL_USART_IsActiveFlag_CM
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART Send Break Flag is set or not
+ * @rmtoll ISR SBKF LL_USART_IsActiveFlag_SBK
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART Receive Wake Up from mute mode Flag is set or not
+ * @rmtoll ISR RWU LL_USART_IsActiveFlag_RWU
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART Transmit Enable Acknowledge Flag is set or not
+ * @rmtoll ISR TEACK LL_USART_IsActiveFlag_TEACK
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART Receive Enable Acknowledge Flag is set or not
+ * @rmtoll ISR REACK LL_USART_IsActiveFlag_REACK
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART TX FIFO Empty Flag is set or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll ISR TXFE LL_USART_IsActiveFlag_TXFE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART RX FIFO Full Flag is set or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll ISR RXFF LL_USART_IsActiveFlag_RXFF
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not
+ * @rmtoll ISR TCBGT LL_USART_IsActiveFlag_TCBGT
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART TX FIFO Threshold Flag is set or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll ISR TXFT LL_USART_IsActiveFlag_TXFT
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART RX FIFO Threshold Flag is set or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll ISR RXFT LL_USART_IsActiveFlag_RXFT
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear Parity Error Flag
+ * @rmtoll ICR PECF LL_USART_ClearFlag_PE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_PECF);
+}
+
+/**
+ * @brief Clear Framing Error Flag
+ * @rmtoll ICR FECF LL_USART_ClearFlag_FE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_FECF);
+}
+
+/**
+ * @brief Clear Noise Error detected Flag
+ * @rmtoll ICR NECF LL_USART_ClearFlag_NE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_NECF);
+}
+
+/**
+ * @brief Clear OverRun Error Flag
+ * @rmtoll ICR ORECF LL_USART_ClearFlag_ORE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_ORECF);
+}
+
+/**
+ * @brief Clear IDLE line detected Flag
+ * @rmtoll ICR IDLECF LL_USART_ClearFlag_IDLE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_IDLECF);
+}
+
+/**
+ * @brief Clear TX FIFO Empty Flag
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll ICR TXFECF LL_USART_ClearFlag_TXFE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_TXFE(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_TXFECF);
+}
+
+/**
+ * @brief Clear Transmission Complete Flag
+ * @rmtoll ICR TCCF LL_USART_ClearFlag_TC
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_TCCF);
+}
+
+/**
+ * @brief Clear Smartcard Transmission Complete Before Guard Time Flag
+ * @rmtoll ICR TCBGTCF LL_USART_ClearFlag_TCBGT
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF);
+}
+
+/**
+ * @brief Clear LIN Break Detection Flag
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll ICR LBDCF LL_USART_ClearFlag_LBD
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_LBDCF);
+}
+
+/**
+ * @brief Clear CTS Interrupt Flag
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll ICR CTSCF LL_USART_ClearFlag_nCTS
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_CTSCF);
+}
+
+/**
+ * @brief Clear Receiver Time Out Flag
+ * @rmtoll ICR RTOCF LL_USART_ClearFlag_RTO
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_RTOCF);
+}
+
+/**
+ * @brief Clear End Of Block Flag
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll ICR EOBCF LL_USART_ClearFlag_EOB
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_EOBCF);
+}
+
+/**
+ * @brief Clear SPI Slave Underrun Flag
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+ * SPI Slave mode feature is supported by the USARTx instance.
+ * @rmtoll ICR UDRCF LL_USART_ClearFlag_UDR
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_UDR(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_UDRCF);
+}
+
+/**
+ * @brief Clear Character Match Flag
+ * @rmtoll ICR CMCF LL_USART_ClearFlag_CM
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_CMCF);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable IDLE Interrupt
+ * @rmtoll CR1 IDLEIE LL_USART_EnableIT_IDLE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+}
+
+/* Legacy define */
+#define LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE
+
+/**
+ * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_EnableIT_RXNE_RXFNE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+}
+
+/**
+ * @brief Enable Transmission Complete Interrupt
+ * @rmtoll CR1 TCIE LL_USART_EnableIT_TC
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE);
+}
+
+/* Legacy define */
+#define LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF
+
+/**
+ * @brief Enable TX Empty and TX FIFO Not Full Interrupt
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_EnableIT_TXE_TXFNF
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+}
+
+/**
+ * @brief Enable Parity Error Interrupt
+ * @rmtoll CR1 PEIE LL_USART_EnableIT_PE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+ * @brief Enable Character Match Interrupt
+ * @rmtoll CR1 CMIE LL_USART_EnableIT_CM
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+ * @brief Enable Receiver Timeout Interrupt
+ * @rmtoll CR1 RTOIE LL_USART_EnableIT_RTO
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE);
+}
+
+/**
+ * @brief Enable End Of Block Interrupt
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR1 EOBIE LL_USART_EnableIT_EOB
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE);
+}
+
+/**
+ * @brief Enable TX FIFO Empty Interrupt
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 TXFEIE LL_USART_EnableIT_TXFE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXFEIE);
+}
+
+/**
+ * @brief Enable RX FIFO Full Interrupt
+ * @rmtoll CR1 RXFFIE LL_USART_EnableIT_RXFF
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXFFIE);
+}
+
+/**
+ * @brief Enable LIN Break Detection Interrupt
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
+}
+
+/**
+ * @brief Enable Error Interrupt
+ * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+ * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
+ * 0: Interrupt is inhibited
+ * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
+ * @rmtoll CR3 EIE LL_USART_EnableIT_ERROR
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+ * @brief Enable CTS Interrupt
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+ * @brief Enable TX FIFO Threshold Interrupt
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 TXFTIE LL_USART_EnableIT_TXFT
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TXFTIE);
+}
+
+/**
+ * @brief Enable Smartcard Transmission Complete Before Guard Time Interrupt
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 TCBGTIE LL_USART_EnableIT_TCBGT
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
+}
+
+/**
+ * @brief Enable RX FIFO Threshold Interrupt
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 RXFTIE LL_USART_EnableIT_RXFT
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_RXFTIE);
+}
+
+/**
+ * @brief Disable IDLE Interrupt
+ * @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+}
+
+/* Legacy define */
+#define LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE
+
+/**
+ * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_DisableIT_RXNE_RXFNE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+}
+
+/**
+ * @brief Disable Transmission Complete Interrupt
+ * @rmtoll CR1 TCIE LL_USART_DisableIT_TC
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
+}
+
+/* Legacy define */
+#define LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF
+
+/**
+ * @brief Disable TX Empty and TX FIFO Not Full Interrupt
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_DisableIT_TXE_TXFNF
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+}
+
+/**
+ * @brief Disable Parity Error Interrupt
+ * @rmtoll CR1 PEIE LL_USART_DisableIT_PE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+ * @brief Disable Character Match Interrupt
+ * @rmtoll CR1 CMIE LL_USART_DisableIT_CM
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+ * @brief Disable Receiver Timeout Interrupt
+ * @rmtoll CR1 RTOIE LL_USART_DisableIT_RTO
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE);
+}
+
+/**
+ * @brief Disable End Of Block Interrupt
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR1 EOBIE LL_USART_DisableIT_EOB
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE);
+}
+
+/**
+ * @brief Disable TX FIFO Empty Interrupt
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 TXFEIE LL_USART_DisableIT_TXFE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE);
+}
+
+/**
+ * @brief Disable RX FIFO Full Interrupt
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 RXFFIE LL_USART_DisableIT_RXFF
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE);
+}
+
+/**
+ * @brief Disable LIN Break Detection Interrupt
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
+}
+
+/**
+ * @brief Disable Error Interrupt
+ * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+ * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
+ * 0: Interrupt is inhibited
+ * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
+ * @rmtoll CR3 EIE LL_USART_DisableIT_ERROR
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+ * @brief Disable CTS Interrupt
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+ * @brief Disable TX FIFO Threshold Interrupt
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 TXFTIE LL_USART_DisableIT_TXFT
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE);
+}
+
+/**
+ * @brief Disable Smartcard Transmission Complete Before Guard Time Interrupt
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 TCBGTIE LL_USART_DisableIT_TCBGT
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
+}
+
+/**
+ * @brief Disable RX FIFO Threshold Interrupt
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 RXFTIE LL_USART_DisableIT_RXFT
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE);
+}
+
+/**
+ * @brief Check if the USART IDLE Interrupt source is enabled or disabled.
+ * @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
+}
+
+/* Legacy define */
+#define LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE
+
+/**
+ * @brief Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled.
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_IsEnabledIT_RXNE_RXFNE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART Transmission Complete Interrupt is enabled or disabled.
+ * @rmtoll CR1 TCIE LL_USART_IsEnabledIT_TC
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
+}
+
+/* Legacy define */
+#define LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF
+
+/**
+ * @brief Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_IsEnabledIT_TXE_TXFNF
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART Parity Error Interrupt is enabled or disabled.
+ * @rmtoll CR1 PEIE LL_USART_IsEnabledIT_PE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART Character Match Interrupt is enabled or disabled.
+ * @rmtoll CR1 CMIE LL_USART_IsEnabledIT_CM
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART Receiver Timeout Interrupt is enabled or disabled.
+ * @rmtoll CR1 RTOIE LL_USART_IsEnabledIT_RTO
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART End Of Block Interrupt is enabled or disabled.
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR1 EOBIE LL_USART_IsEnabledIT_EOB
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART TX FIFO Empty Interrupt is enabled or disabled
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 TXFEIE LL_USART_IsEnabledIT_TXFE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART RX FIFO Full Interrupt is enabled or disabled
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 RXFFIE LL_USART_IsEnabledIT_RXFF
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled.
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART Error Interrupt is enabled or disabled.
+ * @rmtoll CR3 EIE LL_USART_IsEnabledIT_ERROR
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART CTS Interrupt is enabled or disabled.
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if USART TX FIFO Threshold Interrupt is enabled or disabled
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 TXFTIE LL_USART_IsEnabledIT_TXFT
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 TCBGTIE LL_USART_IsEnabledIT_TCBGT
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if USART RX FIFO Threshold Interrupt is enabled or disabled
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 RXFTIE LL_USART_IsEnabledIT_RXFT
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_DMA_Management DMA_Management
+ * @{
+ */
+
+/**
+ * @brief Enable DMA Mode for reception
+ * @rmtoll CR3 DMAR LL_USART_EnableDMAReq_RX
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+ * @brief Disable DMA Mode for reception
+ * @rmtoll CR3 DMAR LL_USART_DisableDMAReq_RX
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+ * @brief Check if DMA Mode is enabled for reception
+ * @rmtoll CR3 DMAR LL_USART_IsEnabledDMAReq_RX
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable DMA Mode for transmission
+ * @rmtoll CR3 DMAT LL_USART_EnableDMAReq_TX
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+ * @brief Disable DMA Mode for transmission
+ * @rmtoll CR3 DMAT LL_USART_DisableDMAReq_TX
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+ * @brief Check if DMA Mode is enabled for transmission
+ * @rmtoll CR3 DMAT LL_USART_IsEnabledDMAReq_TX
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable DMA Disabling on Reception Error
+ * @rmtoll CR3 DDRE LL_USART_EnableDMADeactOnRxErr
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+ * @brief Disable DMA Disabling on Reception Error
+ * @rmtoll CR3 DDRE LL_USART_DisableDMADeactOnRxErr
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+ * @brief Indicate if DMA Disabling on Reception Error is disabled
+ * @rmtoll CR3 DDRE LL_USART_IsEnabledDMADeactOnRxErr
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get the data register address used for DMA transfer
+ * @rmtoll RDR RDR LL_USART_DMA_GetRegAddr\n
+ * @rmtoll TDR TDR LL_USART_DMA_GetRegAddr
+ * @param USARTx USART Instance
+ * @param Direction This parameter can be one of the following values:
+ * @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT
+ * @arg @ref LL_USART_DMA_REG_DATA_RECEIVE
+ * @retval Address of data register
+ */
+__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction)
+{
+ uint32_t data_reg_addr;
+
+ if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
+ {
+ /* return address of TDR register */
+ data_reg_addr = (uint32_t) &(USARTx->TDR);
+ }
+ else
+ {
+ /* return address of RDR register */
+ data_reg_addr = (uint32_t) &(USARTx->RDR);
+ }
+
+ return data_reg_addr;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Data_Management Data_Management
+ * @{
+ */
+
+/**
+ * @brief Read Receiver Data register (Receive Data value, 8 bits)
+ * @rmtoll RDR RDR LL_USART_ReceiveData8
+ * @param USARTx USART Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
+{
+ return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU);
+}
+
+/**
+ * @brief Read Receiver Data register (Receive Data value, 9 bits)
+ * @rmtoll RDR RDR LL_USART_ReceiveData9
+ * @param USARTx USART Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x1FF
+ */
+__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx)
+{
+ return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
+}
+
+/**
+ * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits)
+ * @rmtoll TDR TDR LL_USART_TransmitData8
+ * @param USARTx USART Instance
+ * @param Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)
+{
+ USARTx->TDR = Value;
+}
+
+/**
+ * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits)
+ * @rmtoll TDR TDR LL_USART_TransmitData9
+ * @param USARTx USART Instance
+ * @param Value between Min_Data=0x00 and Max_Data=0x1FF
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
+{
+ USARTx->TDR = (uint16_t)(Value & 0x1FFUL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Execution Execution
+ * @{
+ */
+
+/**
+ * @brief Request an Automatic Baud Rate measurement on next received data frame
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * Auto Baud Rate detection feature is supported by the USARTx instance.
+ * @rmtoll RQR ABRRQ LL_USART_RequestAutoBaudRate
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_ABRRQ);
+}
+
+/**
+ * @brief Request Break sending
+ * @rmtoll RQR SBKRQ LL_USART_RequestBreakSending
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
+}
+
+/**
+ * @brief Put USART in mute mode and set the RWU flag
+ * @rmtoll RQR MMRQ LL_USART_RequestEnterMuteMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_MMRQ);
+}
+
+/**
+ * @brief Request a Receive Data and FIFO flush
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @note Allows to discard the received data without reading them, and avoid an overrun
+ * condition.
+ * @rmtoll RQR RXFRQ LL_USART_RequestRxDataFlush
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
+}
+
+/**
+ * @brief Request a Transmit data and FIFO flush
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll RQR TXFRQ LL_USART_RequestTxDataFlush
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_TXFRQ);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_Autonomous_Mode Configuration functions related to Autonomous mode feature
+ * @{
+ */
+
+/**
+ * @brief Enable Selected Trigger
+ * @rmtoll AUTOCR TRIGEN LL_USART_Enable_SelectedTrigger
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_Enable_SelectedTrigger(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->AUTOCR, USART_AUTOCR_TRIGEN);
+}
+
+/**
+ * @brief Disable Selected Trigger
+ * @rmtoll AUTOCR TRIGEN LL_USART_Disable_SelectedTrigger
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_Disable_SelectedTrigger(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->AUTOCR, USART_AUTOCR_TRIGEN);
+}
+
+/**
+ * @brief Indicate if Selected Trigger is disabled or enabled
+ * @rmtoll AUTOCR TRIGEN LL_USART_IsEnabled_SelectedTrigger
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabled_SelectedTrigger(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->AUTOCR, USART_AUTOCR_TRIGEN) == (USART_AUTOCR_TRIGEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable Autonomous Send Idle Frame feature
+ * @rmtoll AUTOCR IDLEDIS LL_USART_Enable_AutonomousSendIdleFrame
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_Enable_AutonomousSendIdleFrame(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->AUTOCR, USART_AUTOCR_IDLEDIS);
+}
+
+/**
+ * @brief Disable Autonomous Send Idle Frame feature
+ * @rmtoll AUTOCR IDLEDIS LL_USART_Disable_AutonomousSendIdleFrame
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_Disable_AutonomousSendIdleFrame(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->AUTOCR, USART_AUTOCR_IDLEDIS);
+}
+
+/**
+ * @brief Indicate if Autonomous send Idle Frame feature is disabled or enabled
+ * @rmtoll AUTOCR IDLEDIS LL_USART_IsEnabled_AutonomousSendIdleFrame
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabled_AutonomousSendIdleFrame(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->AUTOCR, USART_AUTOCR_IDLEDIS) == (USART_AUTOCR_IDLEDIS)) ? 0UL : 1UL);
+}
+
+/**
+ * @brief Configure the Number of transferred data in bytes
+ * @rmtoll AUTOCR TDN LL_USART_SetNbTxData
+ * @param USARTx USART Instance
+ * @param Nbdata This parameter can be a value between 0 and 0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetNbTxData(USART_TypeDef *USARTx, uint32_t Nbdata)
+{
+ MODIFY_REG(USARTx->AUTOCR, USART_AUTOCR_TDN, (uint16_t)Nbdata);
+}
+
+/**
+ * @brief Retrieve the Number of transferred data in bytes
+ * @rmtoll AUTOCR TDN LL_USART_GetNbTxData
+ * @param USARTx USART Instance
+ * @retval Returned value can be a value between 0 and 0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_USART_GetNbTxData(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->AUTOCR, USART_AUTOCR_TDN));
+}
+
+/**
+ * @brief Set the trigger polarity
+ * @rmtoll AUTOCR TRIGPOL LL_USART_SetTriggerPolarity
+ * @param USARTx USART Instance
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_USART_TRIG_POLARITY_RISING
+ * @arg @ref LL_USART_TRIG_POLARITY_FALLING
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetTriggerPolarity(USART_TypeDef *USARTx, uint32_t Polarity)
+{
+ MODIFY_REG(USARTx->AUTOCR, USART_AUTOCR_TRIGPOL, Polarity);
+}
+
+/**
+ * @brief Get the trigger polarity
+ * @rmtoll AUTOCR TRIGPOL LL_USART_GetTriggerPolarity
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_TRIG_POLARITY_RISING
+ * @arg @ref LL_USART_TRIG_POLARITY_FALLING
+ */
+__STATIC_INLINE uint32_t LL_USART_GetTriggerPolarity(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->AUTOCR, USART_AUTOCR_TRIGPOL));
+}
+
+/**
+ * @brief Set the selected trigger
+ * @rmtoll AUTOCR TRIGSEL LL_USART_SetSelectedTrigger
+ * @param USARTx USART Instance
+ * @param Trigger This parameter can be one of the following values:
+ * @arg @ref LL_USART_GPDMA1_CH0_TCF_TRG
+ * @arg @ref LL_USART_GPDMA1_CH1_TCF_TRG
+ * @arg @ref LL_USART_GPDMA1_CH2_TCF_TRG
+ * @arg @ref LL_USART_GPDMA1_CH3_TCF_TRG
+ * @arg @ref LL_USART_EXTI_LINE6_TRG
+ * @arg @ref LL_USART_EXTI_LINE9_TRG
+ * @arg @ref LL_USART_LPTIM1_OUT_TRG
+ * @arg @ref LL_USART_LPTIM2_OUT_TRG
+ * @arg @ref LL_USART_COMP1_OUT_TRG
+ * @arg @ref LL_USART_COMP2_OUT_TRG
+ * @arg @ref LL_USART_RTC_ALRA_TRG
+ * @arg @ref LL_USART_RTC_WUT_TRG
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetSelectedTrigger(USART_TypeDef *USARTx, uint32_t Trigger)
+{
+ MODIFY_REG(USARTx->AUTOCR, USART_AUTOCR_TRIGSEL, (Trigger << USART_AUTOCR_TRIGSEL_Pos));
+}
+
+/**
+ * @brief Get the selected trigger
+ * @rmtoll AUTOCR TRIGSEL LL_USART_GetSelectedTrigger
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_GPDMA1_CH0_TCF_TRG
+ * @arg @ref LL_USART_GPDMA1_CH1_TCF_TRG
+ * @arg @ref LL_USART_GPDMA1_CH2_TCF_TRG
+ * @arg @ref LL_USART_GPDMA1_CH3_TCF_TRG
+ * @arg @ref LL_USART_EXTI_LINE6_TRG
+ * @arg @ref LL_USART_EXTI_LINE9_TRG
+ * @arg @ref LL_USART_LPTIM1_OUT_TRG
+ * @arg @ref LL_USART_LPTIM2_OUT_TRG
+ * @arg @ref LL_USART_COMP1_OUT_TRG
+ * @arg @ref LL_USART_COMP2_OUT_TRG
+ * @arg @ref LL_USART_RTC_ALRA_TRG
+ * @arg @ref LL_USART_RTC_WUT_TRG
+ */
+__STATIC_INLINE uint32_t LL_USART_GetSelectedTrigger(USART_TypeDef *USARTx)
+{
+ return (uint32_t)((READ_BIT(USARTx->AUTOCR, USART_AUTOCR_TRIGSEL) >> USART_AUTOCR_TRIGSEL_Pos));
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct);
+void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* USART1 || USART2 || USART3 || UART4 || UART5 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_LL_USART_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_usb.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_usb.h
new file mode 100644
index 00000000..82f50cc1
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_usb.h
@@ -0,0 +1,520 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_usb.h
+ * @author MCD Application Team
+ * @brief Header file of USB Low Layer HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_LL_USB_H
+#define STM32U5xx_LL_USB_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal_def.h"
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup USB_LL
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief USB Mode definition
+ */
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+
+typedef enum
+{
+ USB_DEVICE_MODE = 0,
+ USB_HOST_MODE = 1,
+ USB_DRD_MODE = 2
+} USB_OTG_ModeTypeDef;
+
+/**
+ * @brief URB States definition
+ */
+typedef enum
+{
+ URB_IDLE = 0,
+ URB_DONE,
+ URB_NOTREADY,
+ URB_NYET,
+ URB_ERROR,
+ URB_STALL
+} USB_OTG_URBStateTypeDef;
+
+/**
+ * @brief Host channel States definition
+ */
+typedef enum
+{
+ HC_IDLE = 0,
+ HC_XFRC,
+ HC_HALTED,
+ HC_NAK,
+ HC_NYET,
+ HC_STALL,
+ HC_XACTERR,
+ HC_BBLERR,
+ HC_DATATGLERR
+} USB_OTG_HCStateTypeDef;
+
+/**
+ * @brief USB Instance Initialization Structure definition
+ */
+typedef struct
+{
+ uint32_t dev_endpoints; /*!< Device Endpoints number.
+ This parameter depends on the used USB core.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+ uint32_t Host_channels; /*!< Host Channels number.
+ This parameter Depends on the used USB core.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+ uint32_t speed; /*!< USB Core speed.
+ This parameter can be any value of @ref PCD_Speed/HCD_Speed
+ (HCD_SPEED_xxx, HCD_SPEED_xxx) */
+
+ uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */
+
+ uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
+
+ uint32_t phy_itface; /*!< Select the used PHY interface.
+ This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */
+
+ uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
+
+ uint32_t low_power_enable; /*!< Enable or disable the low power mode. */
+
+ uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */
+
+ uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
+
+ uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */
+
+ uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */
+
+ uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */
+
+} USB_OTG_CfgTypeDef;
+
+typedef struct
+{
+ uint8_t num; /*!< Endpoint number
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+ uint8_t is_in; /*!< Endpoint direction
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint8_t is_stall; /*!< Endpoint stall condition
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint8_t type; /*!< Endpoint type
+ This parameter can be any value of @ref USB_LL_EP_Type */
+
+ uint8_t data_pid_start; /*!< Initial data PID
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint8_t even_odd_frame; /*!< IFrame parity
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint16_t tx_fifo_num; /*!< Transmission FIFO number
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+ uint32_t maxpacket; /*!< Endpoint Max packet size
+ This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
+
+ uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
+
+ uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */
+
+ uint32_t xfer_len; /*!< Current transfer length */
+
+ uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
+} USB_OTG_EPTypeDef;
+
+typedef struct
+{
+ uint8_t dev_addr; /*!< USB device address.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 255 */
+
+ uint8_t ch_num; /*!< Host channel number.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+ uint8_t ep_num; /*!< Endpoint number.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+ uint8_t ep_is_in; /*!< Endpoint direction
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint8_t speed; /*!< USB Host Channel speed.
+ This parameter can be any value of @ref HCD_Device_Speed:
+ (HCD_DEVICE_SPEED_xxx) */
+
+ uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */
+
+ uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */
+
+ uint8_t ep_type; /*!< Endpoint Type.
+ This parameter can be any value of @ref USB_LL_EP_Type */
+
+ uint16_t max_packet; /*!< Endpoint Max packet size.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
+
+ uint8_t data_pid; /*!< Initial data PID.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */
+
+ uint32_t XferSize; /*!< OTG Channel transfer size. */
+
+ uint32_t xfer_len; /*!< Current transfer length. */
+
+ uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */
+
+ uint8_t toggle_in; /*!< IN transfer current toggle flag.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint8_t toggle_out; /*!< OUT transfer current toggle flag
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */
+
+ uint32_t ErrCnt; /*!< Host channel error count. */
+
+ USB_OTG_URBStateTypeDef urb_state; /*!< URB state.
+ This parameter can be any value of @ref USB_OTG_URBStateTypeDef */
+
+ USB_OTG_HCStateTypeDef state; /*!< Host Channel state.
+ This parameter can be any value of @ref USB_OTG_HCStateTypeDef */
+} USB_OTG_HCTypeDef;
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PCD_Exported_Constants PCD Exported Constants
+ * @{
+ */
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+/** @defgroup USB_OTG_CORE VERSION ID
+ * @{
+ */
+#define USB_OTG_CORE_ID_300A 0x4F54300AU
+#define USB_OTG_CORE_ID_310A 0x4F54310AU
+/**
+ * @}
+ */
+
+/** @defgroup USB_Core_Mode_ USB Core Mode
+ * @{
+ */
+#define USB_OTG_MODE_DEVICE 0U
+#define USB_OTG_MODE_HOST 1U
+#define USB_OTG_MODE_DRD 2U
+/**
+ * @}
+ */
+
+/** @defgroup USB_LL Device Speed
+ * @{
+ */
+#define USBD_HS_SPEED 0U
+#define USBD_HSINFS_SPEED 1U
+#define USBH_HS_SPEED 0U
+#define USBD_FS_SPEED 2U
+#define USBH_FSLS_SPEED 1U
+/**
+ * @}
+ */
+
+/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed
+ * @{
+ */
+#define USB_OTG_SPEED_HIGH 0U
+#define USB_OTG_SPEED_HIGH_IN_FULL 1U
+#define USB_OTG_SPEED_FULL 3U
+/**
+ * @}
+ */
+
+/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY
+ * @{
+ */
+#define USB_OTG_ULPI_PHY 1U
+#define USB_OTG_EMBEDDED_PHY 2U
+#define USB_OTG_HS_EMBEDDED_PHY 3U
+/**
+ * @}
+ */
+
+/** @defgroup USB_LL_Turnaround_Timeout Turnaround Timeout Value
+ * @{
+ */
+#ifndef USBD_HS_TRDT_VALUE
+#define USBD_HS_TRDT_VALUE 9U
+#endif /* USBD_HS_TRDT_VALUE */
+#ifndef USBD_FS_TRDT_VALUE
+#define USBD_FS_TRDT_VALUE 5U
+#define USBD_DEFAULT_TRDT_VALUE 9U
+#endif /* USBD_HS_TRDT_VALUE */
+/**
+ * @}
+ */
+
+/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS
+ * @{
+ */
+#define USB_OTG_HS_MAX_PACKET_SIZE 512U
+#define USB_OTG_FS_MAX_PACKET_SIZE 64U
+#define USB_OTG_MAX_EP0_SIZE 64U
+/**
+ * @}
+ */
+
+/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency
+ * @{
+ */
+#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1)
+#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1)
+#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1)
+/**
+ * @}
+ */
+
+/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval
+ * @{
+ */
+#define DCFG_FRAME_INTERVAL_80 0U
+#define DCFG_FRAME_INTERVAL_85 1U
+#define DCFG_FRAME_INTERVAL_90 2U
+#define DCFG_FRAME_INTERVAL_95 3U
+/**
+ * @}
+ */
+
+/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
+ * @{
+ */
+#define EP_MPS_64 0U
+#define EP_MPS_32 1U
+#define EP_MPS_16 2U
+#define EP_MPS_8 3U
+/**
+ * @}
+ */
+
+/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed
+ * @{
+ */
+#define EP_SPEED_LOW 0U
+#define EP_SPEED_FULL 1U
+#define EP_SPEED_HIGH 2U
+/**
+ * @}
+ */
+
+/** @defgroup USB_LL_EP_Type USB Low Layer EP Type
+ * @{
+ */
+#define EP_TYPE_CTRL 0U
+#define EP_TYPE_ISOC 1U
+#define EP_TYPE_BULK 2U
+#define EP_TYPE_INTR 3U
+#define EP_TYPE_MSK 3U
+/**
+ * @}
+ */
+
+/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines
+ * @{
+ */
+#define STS_GOUT_NAK 1U
+#define STS_DATA_UPDT 2U
+#define STS_XFER_COMP 3U
+#define STS_SETUP_COMP 4U
+#define STS_SETUP_UPDT 6U
+/**
+ * @}
+ */
+
+/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines
+ * @{
+ */
+#define HCFG_30_60_MHZ 0U
+#define HCFG_48_MHZ 1U
+#define HCFG_6_MHZ 2U
+/**
+ * @}
+ */
+
+/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines
+ * @{
+ */
+#define HPRT0_PRTSPD_HIGH_SPEED 0U
+#define HPRT0_PRTSPD_FULL_SPEED 1U
+#define HPRT0_PRTSPD_LOW_SPEED 2U
+/**
+ * @}
+ */
+
+#define HCCHAR_CTRL 0U
+#define HCCHAR_ISOC 1U
+#define HCCHAR_BULK 2U
+#define HCCHAR_INTR 3U
+
+#define HC_PID_DATA0 0U
+#define HC_PID_DATA2 1U
+#define HC_PID_DATA1 2U
+#define HC_PID_SETUP 3U
+
+#define GRXSTS_PKTSTS_IN 2U
+#define GRXSTS_PKTSTS_IN_XFER_COMP 3U
+#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U
+#define GRXSTS_PKTSTS_CH_HALTED 7U
+
+#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE)
+#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE)
+
+#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE))
+#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE\
+ + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
+
+#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE\
+ + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
+
+#define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE))
+
+#define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE))
+#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE\
+ + USB_OTG_HOST_CHANNEL_BASE\
+ + ((i) * USB_OTG_HOST_CHANNEL_SIZE)))
+
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+#define EP_ADDR_MSK 0xFU
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros
+ * @{
+ */
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))
+#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))
+
+#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))
+#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions
+ * @{
+ */
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
+HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
+HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed);
+HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode);
+HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed);
+HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num);
+HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);
+HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);
+HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
+ uint8_t ch_ep_num, uint16_t len, uint8_t dma);
+
+void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
+HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address);
+HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup);
+uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
+uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
+void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
+
+HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
+HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq);
+HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state);
+uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
+ uint8_t epnum, uint8_t dev_address, uint8_t speed,
+ uint8_t ep_type, uint16_t mps);
+HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx,
+ USB_OTG_HCTypeDef *hc, uint8_t dma);
+
+uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);
+HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num);
+HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32U5xx_LL_USB_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_utils.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_utils.h
new file mode 100644
index 00000000..f763b599
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_utils.h
@@ -0,0 +1,335 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_utils.h
+ * @author MCD Application Team
+ * @brief Header file of UTILS LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The LL UTILS driver contains a set of generic APIs that can be
+ used by user:
+ (+) Device electronic signature
+ (+) Timing functions
+ (+) PLL configuration functions
+
+ @endverbatim
+ */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32U5xx_LL_UTILS_H
+#define __STM32U5xx_LL_UTILS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx.h"
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup UTILS_LL UTILS
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
+ * @{
+ */
+
+/* Max delay can be used in LL_mDelay */
+#define LL_MAX_DELAY 0xFFFFFFFFU
+
+/**
+ * @brief Unique device ID register base address
+ */
+#define UID_BASE_ADDRESS UID_BASE
+
+/**
+ * @brief Flash size data register base address
+ */
+#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
+
+/**
+ * @brief Package data register base address
+ */
+#define PACKAGE_BASE_ADDRESS PACKAGE_BASE
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
+ * @{
+ */
+
+/**
+ * @brief UTILS PLL structure definition
+ */
+typedef struct
+{
+ uint32_t PLLM; /*!< Division factor for PLL VCO input clock.
+ This parameter can be a value of @ref RCC_LL_EC_PLL1MBOOST_DIV
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+
+ uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock.
+ This parameter must be a number between Min_Data = 8 and Max_Data = 86
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+
+ uint32_t PLLR; /*!< Division for the main system clock.
+ This parameter can be a value of @ref RCC_LL_EC_PLLR_DIV
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+} LL_UTILS_PLLInitTypeDef;
+
+/**
+ * @brief UTILS System, AHB and APB buses clock configuration structure definition
+ */
+typedef struct
+{
+ uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
+ This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_SetAHBPrescaler(). */
+
+ uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+ This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_SetAPB1Prescaler(). */
+
+ uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
+ This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_SetAPB2Prescaler(). */
+
+ uint32_t APB3CLKDivider; /*!< The APB3 clock (PCLK3) divider. This clock is derived from the AHB clock (HCLK).
+ This parameter can be a value of @ref RCC_LL_EC_APB3_DIV
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_SetAPB3Prescaler(). */
+
+} LL_UTILS_ClkInitTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
+ * @{
+ */
+
+/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
+ * @{
+ */
+#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
+#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
+/**
+ * @}
+ */
+
+/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
+ * @{
+ */
+#define LL_UTILS_PACKAGETYPE_LQFP64 0x00000000U /*!< LQFP64 package type */
+#define LL_UTILS_PACKAGETYPE_LQFP100 0x00000002U /*!< LQFP100 package type */
+#define LL_UTILS_PACKAGETYPE_UFBGA132 0x00000003U /*!< UFBGA132 package type */
+#define LL_UTILS_PACKAGETYPE_LQFP144 0x00000004U /*!< LQFP144 package type */
+#define LL_UTILS_PACKAGETYPE_LQFP48 0x00000005U /*!< LQFP48 package type */
+#define LL_UTILS_PACKAGETYPE_UFBGA169 0x00000007U /*!< UFBGA169 package type */
+#define LL_UTILS_PACKAGETYPE_LQFP64_SMPS 0x00000008U /*!< LQFP64 with internal SMPS package type */
+#define LL_UTILS_PACKAGETYPE_WLSCP90_SMPS 0x00000009U /*!< WLSCP90 with internal SMPS package type */
+#define LL_UTILS_PACKAGETYPE_LQFP100_SMPS 0x0000000AU /*!< LQFP100 with internal SMPS package type */
+#define LL_UTILS_PACKAGETYPE_UFBGA132_SMPS 0x0000000BU /*!< UFBGA132 with internal SMPS package type */
+#define LL_UTILS_PACKAGETYPE_LQFP144_SMPS 0x0000000CU /*!< LQFP144 with internal SMPS package type */
+#define LL_UTILS_PACKAGETYPE_LQFP48_SMPS 0x0000000DU /*!< LQFP48 with internal SMPS package type */
+#define LL_UTILS_PACKAGETYPE_UFBGA169_SMPS 0x0000000FU /*!< UFBGA169 with internal SMPS package type */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
+ * @{
+ */
+
+/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
+ * @{
+ */
+
+/**
+ * @brief Get Word0 of the unique device identifier (UID based on 96 bits)
+ * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format
+ */
+__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
+{
+ return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
+}
+
+/**
+ * @brief Get Word1 of the unique device identifier (UID based on 96 bits)
+ * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])
+ */
+__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
+{
+ return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
+}
+
+/**
+ * @brief Get Word2 of the unique device identifier (UID based on 96 bits)
+ * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24]
+ */
+__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
+{
+ return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
+}
+
+/**
+ * @brief Get Flash memory size
+ * @note This bitfield indicates the size of the device Flash memory expressed in
+ * Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
+ * @retval FLASH_SIZE[15:0]: Flash memory size
+ */
+__STATIC_INLINE uint32_t LL_GetFlashSize(void)
+{
+ return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFFU);
+}
+
+/**
+ * @brief Get Package type
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_UTILS_PACKAGETYPE_LQFP64
+ * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100
+ * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA132
+ * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144
+ * @arg @ref LL_UTILS_PACKAGETYPE_LQFP48
+ * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169
+ * @arg @ref LL_UTILS_PACKAGETYPE_LQFP64_SMPS
+ * @arg @ref LL_UTILS_PACKAGETYPE_WLSCP90_SMPS
+ * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_SMPS
+ * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA132_SMPS
+ * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_SMPS
+ * @arg @ref LL_UTILS_PACKAGETYPE_LQFP48_SMPS
+ * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169_SMPS
+ */
+__STATIC_INLINE uint32_t LL_GetPackageType(void)
+{
+ return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UTILS_LL_EF_DELAY DELAY
+ * @{
+ */
+
+/**
+ * @brief This function configures the Cortex-M SysTick source of the time base.
+ * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
+ * @note When a RTOS is used, it is recommended to avoid changing the SysTick
+ * configuration by calling this function, for a delay use rather osDelay RTOS service.
+ * @param Ticks Number of ticks
+ * @retval None
+ */
+__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
+{
+ /* Configure the SysTick to have interrupt in 1ms time base */
+ SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
+}
+
+void LL_Init1msTick(uint32_t HCLKFrequency);
+void LL_mDelay(uint32_t Delay);
+
+/**
+ * @}
+ */
+
+/** @defgroup LL_UTILS_Aliased_Functions LL UTILS Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define LL_PLL1_ConfigSystemClock_MSI LL_PLL_ConfigSystemClock_MSI
+#define LL_PLL1_ConfigSystemClock_HSI LL_PLL_ConfigSystemClock_HSI
+#define LL_PLL1_ConfigSystemClock_HSE LL_PLL_ConfigSystemClock_HSE
+/**
+ * @}
+ */
+
+/** @defgroup UTILS_EF_SYSTEM SYSTEM
+ * @{
+ */
+
+void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
+ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+ LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+ LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
+ LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+ LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32U5xx_LL_UTILS_H */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_wwdg.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_wwdg.h
new file mode 100644
index 00000000..90885fce
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_wwdg.h
@@ -0,0 +1,328 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_wwdg.h
+ * @author MCD Application Team
+ * @brief Header file of WWDG LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_LL_WWDG_H
+#define STM32U5xx_LL_WWDG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx.h"
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined (WWDG)
+
+/** @defgroup WWDG_LL WWDG
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
+ * @{
+ */
+
+/** @defgroup WWDG_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions
+ * @{
+ */
+#define LL_WWDG_CFR_EWI WWDG_CFR_EWI
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
+ * @{
+ */
+#define LL_WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */
+#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
+#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
+#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */
+#define LL_WWDG_PRESCALER_16 WWDG_CFR_WDGTB_2 /*!< WWDG counter clock = (PCLK1/4096)/16 */
+#define LL_WWDG_PRESCALER_32 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/32 */
+#define LL_WWDG_PRESCALER_64 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/64 */
+#define LL_WWDG_PRESCALER_128 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/128 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
+ * @{
+ */
+/** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
+ * @{
+ */
+/**
+ * @brief Write a value in WWDG register
+ * @param __INSTANCE__ WWDG Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in WWDG register
+ * @param __INSTANCE__ WWDG Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
+ * @{
+ */
+
+/** @defgroup WWDG_LL_EF_Configuration Configuration
+ * @{
+ */
+/**
+ * @brief Enable Window Watchdog. The watchdog is always disabled after a reset.
+ * @note It is enabled by setting the WDGA bit in the WWDG_CR register,
+ * then it cannot be disabled again except by a reset.
+ * This bit is set by software and only cleared by hardware after a reset.
+ * When WDGA = 1, the watchdog can generate a reset.
+ * @rmtoll CR WDGA LL_WWDG_Enable
+ * @param WWDGx WWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
+{
+ SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
+}
+
+/**
+ * @brief Checks if Window Watchdog is enabled
+ * @rmtoll CR WDGA LL_WWDG_IsEnabled
+ * @param WWDGx WWDG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
+{
+ return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set the Watchdog counter value to provided value (7-bits T[6:0])
+ * @note When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
+ * This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
+ * A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
+ * Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
+ * @rmtoll CR T LL_WWDG_SetCounter
+ * @param WWDGx WWDG Instance
+ * @param Counter 0..0x7F (7 bit counter value)
+ * @retval None
+ */
+__STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
+{
+ MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
+}
+
+/**
+ * @brief Return current Watchdog Counter Value (7 bits counter value)
+ * @rmtoll CR T LL_WWDG_GetCounter
+ * @param WWDGx WWDG Instance
+ * @retval 7 bit Watchdog Counter value
+ */
+__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
+{
+ return (READ_BIT(WWDGx->CR, WWDG_CR_T));
+}
+
+/**
+ * @brief Set the time base of the prescaler (WDGTB).
+ * @note Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
+ * is decremented every (4096 x 2expWDGTB) PCLK cycles
+ * @rmtoll CFR WDGTB LL_WWDG_SetPrescaler
+ * @param WWDGx WWDG Instance
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_WWDG_PRESCALER_1
+ * @arg @ref LL_WWDG_PRESCALER_2
+ * @arg @ref LL_WWDG_PRESCALER_4
+ * @arg @ref LL_WWDG_PRESCALER_8
+ * @arg @ref LL_WWDG_PRESCALER_16
+ * @arg @ref LL_WWDG_PRESCALER_32
+ * @arg @ref LL_WWDG_PRESCALER_64
+ * @arg @ref LL_WWDG_PRESCALER_128
+ * @retval None
+ */
+__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
+{
+ MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
+}
+
+/**
+ * @brief Return current Watchdog Prescaler Value
+ * @rmtoll CFR WDGTB LL_WWDG_GetPrescaler
+ * @param WWDGx WWDG Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_WWDG_PRESCALER_1
+ * @arg @ref LL_WWDG_PRESCALER_2
+ * @arg @ref LL_WWDG_PRESCALER_4
+ * @arg @ref LL_WWDG_PRESCALER_8
+ * @arg @ref LL_WWDG_PRESCALER_16
+ * @arg @ref LL_WWDG_PRESCALER_32
+ * @arg @ref LL_WWDG_PRESCALER_64
+ * @arg @ref LL_WWDG_PRESCALER_128
+ */
+__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
+{
+ return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
+}
+
+/**
+ * @brief Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
+ * @note This window value defines when write in the WWDG_CR register
+ * to program Watchdog counter is allowed.
+ * Watchdog counter value update must occur only when the counter value
+ * is lower than the Watchdog window register value.
+ * Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
+ * (in the control register) is refreshed before the downcounter has reached
+ * the watchdog window register value.
+ * Physically is possible to set the Window lower then 0x40 but it is not recommended.
+ * To generate an immediate reset, it is possible to set the Counter lower than 0x40.
+ * @rmtoll CFR W LL_WWDG_SetWindow
+ * @param WWDGx WWDG Instance
+ * @param Window 0x00..0x7F (7 bit Window value)
+ * @retval None
+ */
+__STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
+{
+ MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
+}
+
+/**
+ * @brief Return current Watchdog Window Value (7 bits value)
+ * @rmtoll CFR W LL_WWDG_GetWindow
+ * @param WWDGx WWDG Instance
+ * @retval 7 bit Watchdog Window value
+ */
+__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
+{
+ return (READ_BIT(WWDGx->CFR, WWDG_CFR_W));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+/**
+ * @brief Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
+ * @note This bit is set by hardware when the counter has reached the value 0x40.
+ * It must be cleared by software by writing 0.
+ * A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
+ * @rmtoll SR EWIF LL_WWDG_IsActiveFlag_EWKUP
+ * @param WWDGx WWDG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
+{
+ return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear WWDG Early Wakeup Interrupt Flag (EWIF)
+ * @rmtoll SR EWIF LL_WWDG_ClearFlag_EWKUP
+ * @param WWDGx WWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
+{
+ WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_LL_EF_IT_Management IT_Management
+ * @{
+ */
+/**
+ * @brief Enable the Early Wakeup Interrupt.
+ * @note When set, an interrupt occurs whenever the counter reaches value 0x40.
+ * This interrupt is only cleared by hardware after a reset
+ * @rmtoll CFR EWI LL_WWDG_EnableIT_EWKUP
+ * @param WWDGx WWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
+{
+ SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
+}
+
+/**
+ * @brief Check if Early Wakeup Interrupt is enabled
+ * @rmtoll CFR EWI LL_WWDG_IsEnabledIT_EWKUP
+ * @param WWDGx WWDG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
+{
+ return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* WWDG */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_LL_WWDG_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/LICENSE.md b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/LICENSE.md
new file mode 100644
index 00000000..9226612a
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/LICENSE.md
@@ -0,0 +1,27 @@
+Copyright 2021 STMicroelectronics.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice,
+this list of conditions and the following disclaimer in the documentation and/or
+other materials provided with the distribution.
+
+3. Neither the name of the copyright holder nor the names of its contributors
+may be used to endorse or promote products derived from this software without
+specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/README.md b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/README.md
new file mode 100644
index 00000000..a01782ac
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/README.md
@@ -0,0 +1,53 @@
+# STM32CubeU5 HAL Driver MCU Component
+
+## Overview
+
+**STM32Cube** is an STMicroelectronics original initiative to ease the developers life by reducing efforts, time and cost.
+
+**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform, delivered for each STM32 series.
+ * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product
+ * The STM32 HAL-LL drivers : an abstraction drivers layer, the API ensuring maximized portability across the STM32 portfolio
+ * The BSP Drivers of each evaluation or demonstration board provided by this STM32 series
+ * A consistent set of middlewares components such as RTOS, FatFS, TCP-IP, Graphic ...
+ * A full set of software projects (basic examples, applications or demonstrations) for each board provided by this STM32 series
+
+Two models of publication are proposed for the STM32Cube embedded software:
+ * The monolithic **MCU Package** : all STM32Cube software modules of one STM32 series are present (Drivers, Middlewares, Projects, Utilities) in the repo (usual name **STM32Cubexx**, xx corresponding to the STM32 series)
+ * The **MCU component** : progressively from June 2021, each STM32Cube software module being part of the STM32Cube MCU Package, are delivered as an individual repo, allowing the user to select and get only the required software functions.
+
+## Description
+
+This **stm32u5xx_hal_driver** MCU component repo is one element of the STM32CubeU5 MCU embedded software package, providing the **HAL-LL Drivers** part.
+
+## License
+
+Copyright (c) 2021 STMicroelectronics.
+
+This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component.
+If no LICENSE file comes with this software, it is provided AS-IS.
+
+## Release note
+
+Details about the content of this release are available in the release note [here](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/stm32u5xx_hal_driver/blob/master/Release_Notes.html).
+
+
+## Compatibility information
+
+In this table, you can find the successive versions of this HAL-LL Driver component, in line with the corresponding versions of the full MCU package:
+
+It is **crucial** that you use a consistent set of versions for the CMSIS Core - CMSIS Device - HAL, as mentioned in this table.
+
+HAL Driver | CMSIS Device | CMSIS Core | Was delivered in the full MCU package
+------------- | --------------- | ---------- | -------------------------------------
+Tag v1.0.0 | Tag v1.0.0 | Tag v560_cm33 | Tag v1.0.0 (and following, if any, till next tag)
+Tag v1.0.1 | Tag v1.0.1 | Tag v560_cm33 | Tag v1.0.1 (and following, if any, till next tag)
+Tag v1.0.2 | Tag v1.0.2 | Tag v560_cm33 | Tag v1.0.2 (and following, if any, till next tag)
+
+
+The full **STM32CubeU5** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeU5).
+
+## Troubleshooting
+
+If you have any issue with the **Software content** of this repo, you can [file an issue on Github](https://github.com/STMicroelectronics/stm32u5xx_hal_driver/issues/new/choose).
+
+For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus).
\ No newline at end of file
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c
new file mode 100644
index 00000000..102c82bd
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c
@@ -0,0 +1,793 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal.c
+ * @author MCD Application Team
+ * @brief HAL module driver.
+ * This is the common part of the HAL initialization
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The common HAL driver contains a set of generic and common APIs that can be
+ used by the PPP peripheral drivers and the user to start using the HAL.
+ [..]
+ The HAL contains two APIs' categories:
+ (+) Common HAL APIs
+ (+) Services HAL APIs
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup HAL HAL
+ * @brief HAL module driver
+ * @{
+ */
+
+#ifdef HAL_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup HAL_Private_Defines HAL Private Defines
+ * @{
+ */
+/**
+ * @brief STM32U5xx HAL Driver version number 1.0.2
+ */
+#define __STM32U5xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
+#define __STM32U5xx_HAL_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */
+#define __STM32U5xx_HAL_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
+#define __STM32U5xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
+#define __STM32U5xx_HAL_VERSION ((__STM32U5xx_HAL_VERSION_MAIN << 24U)\
+ |(__STM32U5xx_HAL_VERSION_SUB1 << 16U)\
+ |(__STM32U5xx_HAL_VERSION_SUB2 << 8U )\
+ |(__STM32U5xx_HAL_VERSION_RC))
+
+#define VREFBUF_TIMEOUT_VALUE 10U /* 10 ms (to be confirmed) */
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Exported variables --------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Variables HAL Exported Variables
+ * @{
+ */
+__IO uint32_t uwTick;
+uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
+HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Functions HAL Exported Functions
+ * @{
+ */
+
+/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
+ * @brief Initialization and de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initializes the Flash interface the NVIC allocation and initial clock
+ configuration. It initializes the systick also when timeout is needed
+ and the backup domain when enabled.
+ (+) De-Initializes common part of the HAL.
+ (+) Configure The time base source to have 1ms time base with a dedicated
+ Tick interrupt priority.
+ (++) SysTick timer is used by default as source of time base, but user
+ can eventually implement his proper time base source (a general purpose
+ timer for example or other time source), keeping in mind that Time base
+ duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
+ handled in milliseconds basis.
+ (++) Time base configuration function (HAL_InitTick ()) is called automatically
+ at the beginning of the program after reset by HAL_Init() or at any time
+ when clock is configured, by HAL_RCC_ClockConfig().
+ (++) Source of time base is configured to generate interrupts at regular
+ time intervals. Care must be taken if HAL_Delay() is called from a
+ peripheral ISR process, the Tick interrupt line must have higher priority
+ (numerically lower) than the peripheral interrupt. Otherwise the caller
+ ISR process will be blocked.
+ (++) functions affecting time base configurations are declared as __weak
+ to make override possible in case of other implementations in user file.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the Flash prefetch, the time base source, NVIC and any required global low
+ * level hardware by calling the HAL_MspInit() callback function to be optionally defined
+ * in user file stm32u5xx_hal_msp.c.
+ *
+ * @note HAL_Init() function is called at the beginning of program after reset and before
+ * the clock configuration.
+ *
+ * @note In the default implementation the System Timer (Systick) is used as source of time base.
+ * The Systick configuration is based on MSI clock, as MSI is the clock
+ * used after a system Reset and the NVIC configuration is set to Priority group 4.
+ * Once done, time base tick starts incrementing: the tick variable counter is incremented
+ * each 1ms in the SysTick_Handler() interrupt handler.
+ *
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_Init(void)
+{
+ /* Configure Flash prefetch */
+#if (PREFETCH_ENABLE != 0U)
+ __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
+#endif /* PREFETCH_ENABLE */
+
+ /* Set Interrupt Group Priority */
+ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+ /* Update the SystemCoreClock global variable */
+ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos];
+
+ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
+ if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Init the low level hardware */
+ HAL_MspInit();
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief This function de-Initializes common part of the HAL and stops the systick.
+ * This function is optional.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DeInit(void)
+{
+ /* Reset of all peripherals */
+ __HAL_RCC_APB1_FORCE_RESET();
+ __HAL_RCC_APB1_RELEASE_RESET();
+
+ __HAL_RCC_APB2_FORCE_RESET();
+ __HAL_RCC_APB2_RELEASE_RESET();
+
+ __HAL_RCC_AHB1_FORCE_RESET();
+ __HAL_RCC_AHB1_RELEASE_RESET();
+
+ __HAL_RCC_AHB2_FORCE_RESET();
+ __HAL_RCC_AHB2_RELEASE_RESET();
+
+ __HAL_RCC_AHB3_FORCE_RESET();
+ __HAL_RCC_AHB3_RELEASE_RESET();
+
+ /* De-Init the low level hardware */
+ HAL_MspDeInit();
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the MSP.
+ * @retval None
+ */
+__weak void HAL_MspInit(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the MSP.
+ * @retval None
+ */
+__weak void HAL_MspDeInit(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief This function configures the source of the time base.
+ * The time source is configured to have 1ms time base with a dedicated
+ * Tick interrupt priority.
+ * @note This function is called automatically at the beginning of program after
+ * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
+ * @note In the default implementation, SysTick timer is the source of time base.
+ * It is used to generate interrupts at regular time intervals.
+ * Care must be taken if HAL_Delay() is called from a peripheral ISR process,
+ * The SysTick interrupt must have higher priority (numerically lower)
+ * than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+ * The function is declared as __weak to be overwritten in case of other
+ * implementation in user file.
+ * @param TickPriority: Tick interrupt priority.
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+ /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/
+ if ((uint32_t)uwTickFreq == 0UL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Configure the SysTick to have interrupt in 1ms time basis*/
+ if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Configure the SysTick IRQ priority */
+ if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+ {
+ HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
+ uwTickPrio = TickPriority;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Group2 HAL Control functions
+ * @brief HAL Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### HAL Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Provide a tick value in millisecond
+ (+) Provide a blocking delay in millisecond
+ (+) Suspend the time base source interrupt
+ (+) Resume the time base source interrupt
+ (+) Get the HAL API driver version
+ (+) Get the device identifier
+ (+) Get the device revision identifier
+ (+) Enable/Disable Debug module during SLEEP mode
+ (+) Enable/Disable Debug module during STOP mode
+ (+) Enable/Disable Debug module during STANDBY mode
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function is called to increment a global variable "uwTick"
+ * used as application time base.
+ * @note In the default implementation, this variable is incremented each 1ms
+ * in Systick ISR.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_IncTick(void)
+{
+ uwTick += (uint32_t)uwTickFreq;
+}
+
+/**
+ * @brief Provides a tick value in millisecond.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval tick value
+ */
+__weak uint32_t HAL_GetTick(void)
+{
+ return uwTick;
+}
+
+/**
+ * @brief This function returns a tick priority.
+ * @retval tick priority
+ */
+uint32_t HAL_GetTickPrio(void)
+{
+ return uwTickPrio;
+}
+
+/**
+ * @brief Set new tick Freq.
+ * @retval Status
+ */
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ assert_param(IS_TICKFREQ(Freq));
+
+ if (uwTickFreq != Freq)
+ {
+ /* Apply the new tick Freq */
+ status = HAL_InitTick(uwTickPrio);
+
+ if (status == HAL_OK)
+ {
+ uwTickFreq = Freq;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Return tick frequency.
+ * @retval tick period in Hz
+ */
+HAL_TickFreqTypeDef HAL_GetTickFreq(void)
+{
+ return uwTickFreq;
+}
+
+/**
+ * @brief This function provides minimum delay (in milliseconds) based
+ * on variable incremented.
+ * @note In the default implementation , SysTick timer is the source of time base.
+ * It is used to generate interrupts at regular time intervals where uwTick
+ * is incremented.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @param Delay specifies the delay time length, in milliseconds.
+ * @retval None
+ */
+__weak void HAL_Delay(uint32_t Delay)
+{
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t wait = Delay;
+
+ /* Add a freq to guarantee minimum wait */
+ if (wait < HAL_MAX_DELAY)
+ {
+ wait += (uint32_t)(uwTickFreq);
+ }
+
+ while ((HAL_GetTick() - tickstart) < wait)
+ {
+ }
+}
+
+/**
+ * @brief Suspend Tick increment.
+ * @note In the default implementation , SysTick timer is the source of time base. It is
+ * used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
+ * is called, the SysTick interrupt will be disabled and so Tick increment
+ * is suspended.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_SuspendTick(void)
+{
+ /* Disable SysTick Interrupt */
+ SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
+}
+
+/**
+ * @brief Resume Tick increment.
+ * @note In the default implementation , SysTick timer is the source of time base. It is
+ * used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
+ * is called, the SysTick interrupt will be enabled and so Tick increment
+ * is resumed.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_ResumeTick(void)
+{
+ /* Enable SysTick Interrupt */
+ SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
+}
+
+/**
+ * @brief Returns the HAL revision
+ * @retval version : 0xXYZR (8bits for each decimal, R for RC)
+ */
+uint32_t HAL_GetHalVersion(void)
+{
+ return __STM32U5xx_HAL_VERSION;
+}
+
+/**
+ * @brief Returns the device revision identifier.
+ * @retval Device revision identifier
+ */
+uint32_t HAL_GetREVID(void)
+{
+ return ((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> 16);
+}
+
+/**
+ * @brief Returns the device identifier.
+ * @retval Device identifier
+ */
+uint32_t HAL_GetDEVID(void)
+{
+ return (DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID);
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions
+ * @brief HAL Debug functions
+ *
+@verbatim
+ ===============================================================================
+ ##### HAL Debug functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Enable/Disable Debug module during STOP0/STOP1/STOP2 modes
+ (+) Enable/Disable Debug module during STANDBY mode
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable the Debug Module during STOP0/STOP1/STOP2 modes.
+ * @retval None
+ */
+void HAL_DBGMCU_EnableDBGStopMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+ * @brief Disable the Debug Module during STOP0/STOP1/STOP2 modes.
+ * @retval None
+ */
+void HAL_DBGMCU_DisableDBGStopMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+ * @brief Enable the Debug Module during STANDBY mode.
+ * @retval None
+ */
+void HAL_DBGMCU_EnableDBGStandbyMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+ * @brief Disable the Debug Module during STANDBY mode.
+ * @retval None
+ */
+void HAL_DBGMCU_DisableDBGStandbyMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Exported_Functions_Group4 HAL SYSCFG configuration functions
+ * @brief HAL SYSCFG configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### HAL SYSCFG configuration functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure the Voltage reference buffer
+ (+) Enable/Disable the Voltage reference buffer
+ (+) Enable/Disable the I/O analog switch voltage booster
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the internal voltage reference buffer voltage scale.
+ * @param VoltageScaling: specifies the output voltage to achieve
+ * This parameter can be one of the following values:
+ * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 1.5 V.
+ * This requires VDDA equal to or higher than 1.8 V.
+ * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT1 around 1.8 V.
+ * This requires VDDA equal to or higher than 2.1 V.
+ * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE2: VREF_OUT1 around 2.048 V.
+ * This requires VDDA equal to or higher than 2.4 V.
+ * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE3: VREF_OUT1 around 2.5 V.
+ * This requires VDDA equal to or higher than 2.8 V.
+ * @retval None
+ */
+void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling)
+{
+ /* Check the parameters */
+ assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling));
+
+ MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling);
+}
+
+/**
+ * @brief Configure the internal voltage reference buffer high impedance mode.
+ * @param Mode: specifies the high impedance mode
+ * This parameter can be one of the following values:
+ * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output.
+ * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance.
+ * @retval None
+ */
+void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode)
+{
+ /* Check the parameters */
+ assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode));
+
+ MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode);
+}
+
+/**
+ * @brief Tune the Internal Voltage Reference buffer (VREFBUF).
+ * @retval None
+ */
+void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue)
+{
+ /* Check the parameters */
+ assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue));
+
+ MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue);
+}
+
+/**
+ * @brief Enable the Internal Voltage Reference buffer (VREFBUF).
+ * @retval HAL_OK/HAL_TIMEOUT
+ */
+HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void)
+{
+ uint32_t tickstart;
+
+ SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait for VRR bit */
+ while (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0UL)
+ {
+ if ((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the Internal Voltage Reference buffer (VREFBUF).
+ *
+ * @retval None
+ */
+void HAL_SYSCFG_DisableVREFBUF(void)
+{
+ CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
+}
+
+/**
+ * @brief Enable the I/O analog switch voltage booster
+ *
+ * @retval None
+ */
+void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void)
+{
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
+}
+
+/**
+ * @brief Disable the I/O analog switch voltage booster
+ *
+ * @retval None
+ */
+void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void)
+{
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Exported_Functions_Group5 HAL SYSCFG lock management functions
+ * @brief SYSCFG lock management functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### SYSCFG lock functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Lock the SYSCFG item(s).
+ * @note Setting lock(s) depends on privilege mode in secure/non-secure code
+ * Lock(s) cleared only at system reset
+ * @param Item Item(s) to set lock on.
+ * This parameter can be a combination of @ref SYSCFG_Lock_items
+ * @retval None
+ */
+void HAL_SYSCFG_Lock(uint32_t Item)
+{
+ /* Check the parameters */
+ assert_param(IS_SYSCFG_LOCK_ITEMS(Item));
+
+ /* Privilege secure/non-secure locks */
+ SYSCFG->CNSLCKR = (0xFFFFU & Item); /* non-secure lock item in 16 lowest bits */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ /* Privilege secure only locks */
+ SYSCFG->CSLCKR = ((0xFFFF0000U & Item) >> 16U); /* Secure-only lock item in 16 highest bits */
+#endif /* __ARM_FEATURE_CMSE */
+}
+
+/**
+ * @brief Get the lock state of SYSCFG item.
+ * @note Getting lock(s) depends on privilege mode in secure/non-secure code
+ * @param pItem pointer to return locked items
+ * the return value can be a combination of @ref SYSCFG_Lock_items
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem)
+{
+ uint32_t tmp_lock;
+
+ /* Check null pointer */
+ if (pItem == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Get the non-secure lock state */
+ tmp_lock = SYSCFG->CNSLCKR;
+
+ /* Get the secure lock state in secure code */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ tmp_lock |= (SYSCFG->CSLCKR << 16U);
+#endif /* __ARM_FEATURE_CMSE */
+
+ /* Return overall lock status */
+ *pItem = tmp_lock;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+
+/** @defgroup HAL_Exported_Functions_Group6 HAL SYSCFG attributes management functions
+ * @brief SYSCFG attributes management functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### SYSCFG attributes functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the SYSCFG item attribute(s).
+ * @note Available attributes are to secure SYSCFG items, so this function is
+ * only available in secure
+ * @param Item Item(s) to set attributes on.
+ * This parameter can be a one or a combination of @ref SYSCFG_Attributes_items
+ * @param Attributes specifies the secure/non-secure attributes.
+ * @retval None
+ */
+void HAL_SYSCFG_ConfigAttributes(uint32_t Item, uint32_t Attributes)
+{
+ uint32_t tmp;
+
+ /* Check the parameters */
+ assert_param(IS_SYSCFG_ITEMS_ATTRIBUTES(Item));
+ assert_param(IS_SYSCFG_ATTRIBUTES(Attributes));
+
+ tmp = SYSCFG_S->SECCFGR;
+
+ /* Set or reset Item */
+ if ((Attributes & SYSCFG_SEC) != 0x00U)
+ {
+ tmp |= Item;
+ }
+ else
+ {
+ tmp &= ~Item;
+ }
+
+ /* Set secure attributes */
+ SYSCFG_S->SECCFGR = tmp;
+}
+
+/**
+ * @brief Get the attribute of a SYSCFG item.
+ * @note Available attributes are to secure SYSCFG items, so this function is
+ * only available in secure
+ * @param Item Single item to get secure/non-secure attribute from.
+ * @param pAttributes pointer to return the attribute.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes)
+{
+ /* Check null pointer */
+ if (pAttributes == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SYSCFG_ITEMS_ATTRIBUTES(Item));
+
+ /* Get the secure attribute state */
+ if ((SYSCFG_S->SECCFGR & Item) != 0U)
+ {
+ *pAttributes = SYSCFG_SEC;
+ }
+ else
+ {
+ *pAttributes = SYSCFG_NSEC;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+#endif /* __ARM_FEATURE_CMSE */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_adc.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_adc.c
new file mode 100644
index 00000000..96379030
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_adc.c
@@ -0,0 +1,4118 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_adc.c
+ * @author MCD Application Team
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Analog to Digital Converter (ADC)
+ * peripheral:
+ * + Initialization and de-initialization functions
+ * ++ Initialization and Configuration of ADC
+ * + Operation functions
+ * ++ Start, stop, get result of conversions of regular
+ * group, using 3 possible modes: polling, interruption or DMA.
+ * + Control functions
+ * ++ Channels configuration on regular group
+ * ++ Analog Watchdog configuration
+ * + State functions
+ * ++ ADC state machine management
+ * ++ Interrupts and flags management
+ * Other functions (extended functions) are available in file
+ * "stm32u5xx_hal_adc_ex.c".
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### ADC peripheral features #####
+ ==============================================================================
+ [..]
+ (+) 14-bit, 12-bit, 10-bit or 8-bit configurable resolution.
+
+ (+) Interrupt generation at the end of regular conversion and in case of
+ analog watchdog or overrun events.
+
+ (+) Single and continuous conversion modes.
+
+ (+) Scan mode for conversion of several channels sequentially.
+
+ (+) Data alignment with in-built data coherency.
+
+ (+) Programmable sampling time (channel wise)
+
+ (+) External trigger (timer or EXTI) with configurable polarity
+
+ (+) DMA request generation for transfer of conversions data of regular group.
+
+ (+) Configurable delay between conversions in Dual interleaved mode.
+
+ (+) ADC channels selectable single/differential input.
+
+ (+) ADC offset shared on 4 offset instances.
+ (+) ADC calibration
+
+ (+) ADC conversion of regular group.
+
+ (+) ADC supply requirements: 1.62 V to 3.6 V.
+
+ (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
+ Vdda or to an external voltage reference).
+
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+
+ *** Configuration of top level parameters related to ADC ***
+ ============================================================
+ [..]
+
+ (#) Enable the ADC interface
+ (++) As prerequisite, ADC clock must be configured at RCC top level.
+
+ (++) Two clock settings are mandatory:
+ (+++) ADC clock (core clock, also possibly conversion clock).
+
+ (+++) ADC clock (conversions clock).
+ Six possible clock sources: synchronous clock derived from AHB clock
+ or asynchronous clock derived from system clock, the PLL2, the HSE, the HSI or the MSIK.
+
+ (+++) Example:
+ Into HAL_ADC_MspInit() (recommended code location) or with
+ other device clock parameters configuration:
+ (+++) __HAL_RCC_ADC_CLK_ENABLE(); (mandatory)
+
+ RCC_ADCCLKSOURCE_PLL2 enable: (optional: if asynchronous clock selected)
+ (+++) RCC_PeriphClkInitTypeDef RCC_PeriphClkInit;
+ (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC;
+ (+++) PeriphClkInit.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2;
+ (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
+
+ (++) ADC clock source and clock prescaler are configured at ADC level with
+ parameter "ClockPrescaler" using function HAL_ADC_Init().
+
+ (#) ADC pins configuration
+ (++) Enable the clock for the ADC GPIOs
+ using macro __HAL_RCC_GPIOx_CLK_ENABLE()
+ (++) Configure these ADC pins in analog mode
+ using function HAL_GPIO_Init()
+
+ (#) Optionally, in case of usage of ADC with interruptions:
+ (++) Configure the NVIC for ADC
+ using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
+ (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
+ into the function of corresponding ADC interruption vector
+ ADCx_IRQHandler().
+
+ (#) Optionally, in case of usage of DMA:
+ (++) Configure the DMA (DMA channel, mode normal or circular, ...)
+ using function HAL_DMA_Init().
+ (++) Configure the NVIC for DMA
+ using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
+ (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
+ into the function of corresponding DMA interruption vector
+ DMAx_Channelx_IRQHandler().
+
+ *** Configuration of ADC, group regular, channels parameters ***
+ ================================================================
+ [..]
+
+ (#) Configure the ADC parameters (resolution, data alignment, ...)
+ and regular group parameters (conversion trigger, sequencer, ...)
+ using function HAL_ADC_Init().
+
+ (#) Configure the channels for regular group parameters (channel number,
+ channel rank into sequencer, ..., into regular group)
+ using function HAL_ADC_ConfigChannel().
+
+ (#) Optionally, configure the analog watchdog parameters (channels
+ monitored, thresholds, ...)
+ using function HAL_ADC_AnalogWDGConfig().
+
+ *** Execution of ADC conversions ***
+ ====================================
+ [..]
+
+ (#) Optionally, perform an automatic ADC calibration to improve the
+ conversion accuracy
+ using function HAL_ADCEx_Calibration_Start().
+
+ (#) ADC driver can be used among three modes: polling, interruption,
+ transfer by DMA.
+
+ (++) ADC conversion by polling:
+ (+++) Activate the ADC peripheral and start conversions
+ using function HAL_ADC_Start()
+ (+++) Wait for ADC conversion completion
+ using function HAL_ADC_PollForConversion()
+ (+++) Retrieve conversion results
+ using function HAL_ADC_GetValue()
+ (+++) Stop conversion and disable the ADC peripheral
+ using function HAL_ADC_Stop()
+
+ (++) ADC conversion by interruption:
+ (+++) Activate the ADC peripheral and start conversions
+ using function HAL_ADC_Start_IT()
+ (+++) Wait for ADC conversion completion by call of function
+ HAL_ADC_ConvCpltCallback()
+ (this function must be implemented in user program)
+ (+++) Retrieve conversion results
+ using function HAL_ADC_GetValue()
+ (+++) Stop conversion and disable the ADC peripheral
+ using function HAL_ADC_Stop_IT()
+
+ (++) ADC conversion with transfer by DMA:
+ (+++) Activate the ADC peripheral and start conversions
+ using function HAL_ADC_Start_DMA()
+ (+++) Wait for ADC conversion completion by call of function
+ HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
+ (these functions must be implemented in user program)
+ (+++) Conversion results are automatically transferred by DMA into
+ destination variable address.
+ (+++) Stop conversion and disable the ADC peripheral
+ using function HAL_ADC_Stop_DMA()
+
+ [..]
+
+ (@) Callback functions must be implemented in user program:
+ (+@) HAL_ADC_ErrorCallback()
+ (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
+ (+@) HAL_ADC_ConvCpltCallback()
+ (+@) HAL_ADC_ConvHalfCpltCallback
+
+ *** Deinitialization of ADC ***
+ ============================================================
+ [..]
+
+ (#) Disable the ADC interface
+ (++) ADC clock can be hard reset and disabled at RCC top level.
+ (++) Hard reset of ADC peripherals
+ using macro __HAL_RCC_ADCx_FORCE_RESET(), __HAL_RCC_ADCx_RELEASE_RESET().
+ (++) ADC clock disable
+ using the equivalent macro/functions as configuration step.
+ (+++) Example:
+ Into HAL_ADC_MspDeInit() (recommended code location) or with
+ other device clock parameters configuration:
+ (+++) __HAL_RCC_ADC_CLK_DISABLE(); (if not used anymore)
+ RCC_ADCDACCLKSOURCE_HSI restore: (optional)
+ (+++) RCC_PeriphClkInitTypeDef RCC_PeriphClkInit;
+ (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC;
+ (+++) PeriphClkInit.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HSI;
+ (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
+
+ (#) ADC pins configuration
+ (++) Disable the clock for the ADC GPIOs
+ using macro __HAL_RCC_GPIOx_CLK_DISABLE()
+
+ (#) Optionally, in case of usage of ADC with interruptions:
+ (++) Disable the NVIC for ADC
+ using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
+
+ (#) Optionally, in case of usage of DMA:
+ (++) Deinitialize the DMA
+ using function HAL_DMA_Init().
+ (++) Disable the NVIC for DMA
+ using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
+
+ [..]
+
+ *** Callback registration ***
+ =============================================
+ [..]
+
+ The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions @ref HAL_ADC_RegisterCallback()
+ to register an interrupt callback.
+ [..]
+
+ Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks:
+ (+) ConvCpltCallback : ADC conversion complete callback
+ (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
+ (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
+ (+) ErrorCallback : ADC error callback
+ (+) InjectedConvCpltCallback : ADC group injected conversion complete callback
+ (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback
+ (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
+ (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
+ (+) EndOfSamplingCallback : ADC end of sampling callback
+ (+) MspInitCallback : ADC Msp Init callback
+ (+) MspDeInitCallback : ADC Msp DeInit callback
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+ [..]
+
+ Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default
+ weak function.
+ [..]
+
+ @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) ConvCpltCallback : ADC conversion complete callback
+ (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
+ (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
+ (+) ErrorCallback : ADC error callback
+ (+) InjectedConvCpltCallback : ADC group injected conversion complete callback
+ (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback
+ (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
+ (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
+ (+) EndOfSamplingCallback : ADC end of sampling callback
+ (+) MspInitCallback : ADC Msp Init callback
+ (+) MspDeInitCallback : ADC Msp DeInit callback
+ [..]
+
+ By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ [..]
+
+ If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+ [..]
+
+ Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only.
+ Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ [..]
+
+ Then, the user first registers the MspInit/MspDeInit user callbacks
+ using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit()
+ or @ref HAL_ADC_Init() function.
+ [..]
+
+ When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup ADC ADC
+ * @brief ADC HAL module driver
+ * @{
+ */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Constants ADC Private Constants
+ * @{
+ */
+#define ADC_CFGR_FIELDS_1 ((uint32_t)(ADC_CFGR1_RES |\
+ ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD |\
+ ADC_CFGR1_DISCEN | ADC_CFGR1_DISCNUM |\
+ ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated
+when no regular conversion is on-going */
+
+#define ADC_CFGR2_FIELDS ((uint32_t)(ADC_CFGR2_ROVSE | ADC_CFGR2_OVSR |\
+ ADC_CFGR2_OVSS | ADC_CFGR2_TROVS |\
+ ADC_CFGR2_ROVSM)) /*!< ADC_CFGR2 fields of parameters that can be updated when no conversion
+(neither regular nor injected) is on-going */
+
+/* Timeout values for ADC operations (enable settling time, */
+/* disable settling time, ...). */
+/* Values defined to be higher than worst cases: low clock frequency, */
+/* maximum prescalers. */
+#define ADC_ENABLE_TIMEOUT (2UL) /*!< ADC enable time-out value */
+#define ADC_DISABLE_TIMEOUT (2UL) /*!< ADC disable time-out value */
+
+/* Timeout to wait for current conversion on going to be completed. */
+/* Timeout fixed to worst case, for 1 channel. */
+/* - maximum sampling time (830.5 adc_clk) */
+/* - ADC resolution (Tsar 14 bits= 14.5 adc_clk) */
+/* - ADC clock with prescaler 256 */
+/* 823 * 256 = 210688 clock cycles max */
+/* Unit: cycles of CPU clock. */
+#define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 210688) /*!< ADC conversion completion time-out value */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Functions ADC Exported Functions
+ * @{
+ */
+
+/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief ADC Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the ADC.
+ (+) De-initialize the ADC.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the ADC peripheral and regular group according to
+ * parameters specified in structure "ADC_InitTypeDef".
+ * @note As prerequisite, ADC clock must be configured at RCC top level
+ * (refer to description of RCC configuration for ADC
+ * in header of this file).
+ * @note Possibility to update parameters on the fly:
+ * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
+ * coming from ADC state reset. Following calls to this function can
+ * be used to reconfigure some parameters of ADC_InitTypeDef
+ * structure on the fly, without modifying MSP configuration. If ADC
+ * MSP has to be modified again, HAL_ADC_DeInit() must be called
+ * before HAL_ADC_Init().
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_InitTypeDef".
+ * @note This function configures the ADC within 2 scopes: scope of entire
+ * ADC and scope of regular group. For parameters details, see comments
+ * of structure "ADC_InitTypeDef".
+ * @note Parameters related to common ADC registers (ADC clock mode) are set
+ * only if all ADCs are disabled.
+ * If this is not the case, these common parameters setting are
+ * bypassed without error reporting: it can be the intended behaviour in
+ * case of update of a parameter of ADC_InitTypeDef on the fly,
+ * without disabling the other ADCs.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ uint32_t tmpCFGR1 = 0UL;
+ uint32_t tmpCFGR2 = 0UL;
+ uint32_t tmp_adc_reg_is_conversion_on_going;
+ __IO uint32_t wait_loop_index;
+ uint32_t tmp_adc_is_conversion_on_going_regular;
+ uint32_t tmp_adc_is_conversion_on_going_injected;
+
+ /* Check ADC handle */
+ if (hadc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
+ assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+ assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+
+ if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
+ {
+ assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
+ assert_param(IS_ADC_GAIN_COMPENSATION(hadc->Init.GainCompensation));
+ assert_param(IS_ADC_CONVERSIONDATAMGT(hadc->Init.ConversionDataManagement));
+ assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
+ }
+ else
+ {
+ assert_param(IS_ADC4_SCAN_MODE(hadc->Init.ScanConvMode));
+ assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
+ assert_param(IS_ADC4_LOW_POWER(hadc->Init.LowPowerAutoPowerOff));
+ assert_param(IS_ADC4_VREF_PROT(hadc->Init.VrefProtection));
+ assert_param(IS_ADC4_EXTTRIG(hadc->Init.ExternalTrigConv));
+ assert_param(IS_ADC_TRIGGER_FREQ(hadc->Init.TriggerFrequencyMode));
+ }
+ assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
+ assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
+
+ if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
+ {
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
+ if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
+ {
+ assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
+ if (hadc->Init.DiscontinuousConvMode == ENABLE)
+ {
+ assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
+ }
+ }
+ else
+ {
+ if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
+ {
+ assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
+ }
+ }
+ }
+
+ /* DISCEN and CONT bits cannot be set at the same time */
+ assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
+
+ /* Actions performed only if ADC is coming from state reset: */
+ /* - Initialization of ADC MSP */
+ if (hadc->State == HAL_ADC_STATE_RESET)
+ {
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ /* Init the ADC Callback settings */
+ hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */
+ hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */
+ hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */
+ hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */
+ if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
+ {
+ hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */
+ hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback; /* Legacy weak callback */
+ }
+ hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; /* Legacy weak callback */
+ hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; /* Legacy weak callback */
+ hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; /* Legacy weak callback */
+
+ if (hadc->MspInitCallback == NULL)
+ {
+ hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware */
+ hadc->MspInitCallback(hadc);
+#else
+ /* Init the low level hardware */
+ HAL_ADC_MspInit(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Initialize Lock */
+ hadc->Lock = HAL_UNLOCKED;
+ }
+
+ /* - Exit from deep-power-down mode and ADC voltage regulator enable */
+ if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL)
+ {
+ /* Disable ADC deep power down mode */
+ LL_ADC_DisableDeepPowerDown(hadc->Instance);
+
+ /* System was in deep power down mode, calibration must
+ be relaunched or a previously saved calibration factor
+ re-applied once the ADC voltage regulator is enabled */
+ }
+
+ if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
+ {
+ /* Enable ADC internal voltage regulator */
+ LL_ADC_EnableInternalRegulator(hadc->Instance);
+
+ /* Note: Variable divided by 2 to compensate partially */
+ /* CPU processing cycles, scaling in us split to not */
+ /* exceed 32 bits register capacity and handle low frequency. */
+ wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
+ while (wait_loop_index != 0UL)
+ {
+ wait_loop_index--;
+ }
+ }
+
+ /* Verification that ADC voltage regulator is correctly enabled, whether */
+ /* or not ADC is coming from state reset (if any potential problem of */
+ /* clocking, voltage regulator would not be enabled). */
+ if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ /* Configuration of ADC parameters if previous preliminary actions are */
+ /* correctly completed and if there is no conversion on going on regular */
+ /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
+ /* called to update a parameter on the fly). */
+ tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+
+ if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
+ && (tmp_adc_reg_is_conversion_on_going == 0UL)
+ )
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_BUSY_INTERNAL);
+
+ /* Configuration of common ADC parameters */
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated only when ADC is disabled: */
+ /* - clock configuration */
+ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ {
+ if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
+ {
+ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
+ {
+ /* Reset configuration of ADC common register CCR: */
+ /* */
+ /* - ADC clock mode and ACC prescaler (CKMODE and PRESC bits)are set */
+ /* according to adc->Init.ClockPrescaler. It selects the clock */
+ /* source and sets the clock division factor. */
+ /* */
+ /* Some parameters of this register are not reset, since they are set */
+ /* by other functions and must be kept in case of usage of this */
+ /* function on the fly (update of a parameter of ADC_InitTypeDef */
+ /* without needing to reconfigure all other ADC groups/channels */
+ /* parameters): */
+ /* - when multimode feature is available, multimode-related */
+ /* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */
+ /* HAL_ADCEx_MultiModeConfigChannel() ) */
+ /* - internal measurement paths: Vbat, temperature sensor, Vref */
+ /* (set into HAL_ADC_ConfigChannel() or */
+ /* HAL_ADCEx_InjectedConfigChannel() ) */
+ LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler);
+ }
+ }
+ else
+ {
+ /* Some parameters of this register are not reset, since they are set */
+ /* by other functions and must be kept in case of usage of this */
+ /* function on the fly (update of a parameter of ADC_InitTypeDef */
+ /* without needing to reconfigure all other ADC groups/channels */
+ /* parameters): */
+ /* - internal measurement paths: Vbat, temperature sensor, Vref */
+ /* (set into HAL_ADC_ConfigChannel() ) */
+
+ /* Configuration of ADC resolution */
+ MODIFY_REG(hadc->Instance->CFGR1,
+ ADC_CFGR1_RES,
+ __LL_ADC_RESOLUTION_ADC1_TO_ADC4(hadc->Init.Resolution)); /* Convert resolution for the ADC4 */
+
+ /* Configuration of ADC clock mode: clock source AHB or HSI with */
+ /* selectable prescaler. */
+ MODIFY_REG(ADC4_COMMON->CCR,
+ ADC_CCR_PRESC,
+ hadc->Init.ClockPrescaler & ADC_CCR_PRESC);
+ }
+ }
+ if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
+ {
+ /* Configuration of ADC: */
+ /* - resolution Init.Resolution */
+ /* - external trigger to start conversion Init.ExternalTrigConv */
+ /* - external trigger polarity Init.ExternalTrigConvEdge */
+ /* - continuous conversion mode Init.ContinuousConvMode */
+ /* - overrun Init.Overrun */
+ /* - discontinuous mode Init.DiscontinuousConvMode */
+ /* - discontinuous mode channel count Init.NbrOfDiscConversion */
+
+ tmpCFGR1 = (/*ADC_CFGR_AUTODELAY((uint32_t)hadc->Init.LowPowerAutoWait) |*/
+ ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
+ hadc->Init.Overrun |
+ hadc->Init.Resolution |
+ ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
+ }
+ else
+ {
+ /* Configuration of ADC: */
+ /* - discontinuous mode */
+ /* - LowPowerAutoWait mode */
+ /* - LowPowerAutoPowerOff mode */
+ /* - continuous conversion mode */
+ /* - overrun */
+ /* - external trigger to start conversion */
+ /* - external trigger polarity */
+ /* - data alignment */
+ /* - resolution */
+ /* - scan direction */
+ /* - DMA continuous request */
+ tmpCFGR1 |= (ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
+ ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
+ ADC_CFGR_OVERRUN(hadc->Init.Overrun) |
+ hadc->Init.DataAlign |
+ ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode) |
+ ADC_CFGR_DMACONTREQ(hadc, (uint32_t)hadc->Init.DMAContinuousRequests));
+ }
+
+ if (hadc->Init.DiscontinuousConvMode == ENABLE)
+ {
+ if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
+ {
+ tmpCFGR1 |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
+ }
+ else
+ {
+ if (hadc->Init.ContinuousConvMode == DISABLE)
+ {
+ /* Enable the selected ADC group regular discontinuous mode */
+ tmpCFGR1 |= ADC_CFGR1_DISCEN;
+ }
+ else
+ {
+ /* ADC regular group discontinuous was intended to be enabled, */
+ /* but ADC regular group modes continuous and sequencer discontinuous */
+ /* cannot be enabled simultaneously. */
+
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ }
+ }
+ }
+
+ if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
+ {
+ /* Enable external trigger if trigger selection is different of software */
+ /* start. */
+ /* Note: This configuration keeps the hardware feature of parameter */
+ /* ExternalTrigConvEdge "trigger edge none" equivalent to */
+ /* software start. */
+ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
+ {
+ tmpCFGR1 |= ((hadc->Init.ExternalTrigConv & ADC_CFGR1_EXTSEL) | hadc->Init.ExternalTrigConvEdge);
+ }
+ /* Update Configuration Register CFGR */
+ MODIFY_REG(hadc->Instance->CFGR1, ADC_CFGR_FIELDS_1, tmpCFGR1);
+ }
+ else
+ {
+ /* Enable external trigger if trigger selection is different of software */
+ /* start. */
+ /* Note: This configuration keeps the hardware feature of parameter */
+ /* ExternalTrigConvEdge "trigger edge none" equivalent to */
+ /* software start. */
+ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
+ {
+ tmpCFGR1 |= ((hadc->Init.ExternalTrigConv & ADC4_CFGR1_EXTSEL) | hadc->Init.ExternalTrigConvEdge);
+ }
+ /* Update ADC configuration register with previous settings */
+ MODIFY_REG(hadc->Instance->CFGR1,
+ ADC_CFGR1_DISCEN |
+ ADC4_CFGR1_WAIT |
+ ADC_CFGR1_CONT |
+ ADC_CFGR1_OVRMOD |
+ ADC_CFGR1_EXTSEL |
+ ADC_CFGR1_EXTEN |
+ ADC4_CFGR1_ALIGN |
+ ADC4_CFGR1_SCANDIR |
+ ADC4_CFGR1_DMACFG,
+ tmpCFGR1);
+
+ if (hadc->Init.LowPowerAutoPowerOff != ADC_LOW_POWER_NONE)
+ {
+ SET_BIT(hadc->Instance->PW, hadc->Init.LowPowerAutoPowerOff);
+ }
+
+ if (hadc->Init.VrefProtection != ADC_VREF_PPROT_NONE)
+ {
+ SET_BIT(hadc->Instance->PW, hadc->Init.VrefProtection);
+ }
+
+ }
+
+ if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
+ {
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on regular and injected groups: */
+ /* - Conversion data management Init.ConversionDataManagement */
+ /* - LowPowerAutoWait feature Init.LowPowerAutoWait */
+ /* - Oversampling parameters Init.Oversampling */
+ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+ tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+ if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+ && (tmp_adc_is_conversion_on_going_injected == 0UL)
+ )
+ {
+ tmpCFGR1 = (ADC_CFGR_AUTODELAY((uint32_t)hadc->Init.LowPowerAutoWait) |
+ ADC_CFGR_DMACONTREQ(hadc, (uint32_t)hadc->Init.ConversionDataManagement));
+
+ MODIFY_REG(hadc->Instance->CFGR1, ADC4_CFGR_FIELDS_2, tmpCFGR1);
+ if (hadc->Init.GainCompensation != 0UL)
+ {
+ LL_ADC_SetGainCompensation(hadc->Instance, hadc->Init.GainCompensation);
+ }
+
+ if (hadc->Init.OversamplingMode == ENABLE)
+ {
+ assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio));
+ assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift));
+ assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode));
+ assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset));
+
+ if ((hadc->Init.ExternalTrigConv == ADC_SOFTWARE_START)
+ || (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE))
+ {
+ /* Multi trigger is not applicable to software-triggered conversions */
+ assert_param((hadc->Init.Oversampling.TriggeredMode == ADC_TRIGGEREDMODE_SINGLE_TRIGGER));
+ }
+
+ /* Configuration of Oversampler: */
+ /* - Oversampling Ratio */
+ /* - Right bit shift */
+ /* - Left bit shift */
+ /* - Triggered mode */
+ /* - Oversampling mode (continued/resumed) */
+ /* - trigger frequency mode */
+ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS,
+ ADC_CFGR2_ROVSE |
+ (hadc->Init.Oversampling.Ratio << ADC_CFGR2_OVSR_Pos) |
+ hadc->Init.Oversampling.RightBitShift |
+ hadc->Init.Oversampling.TriggeredMode |
+ hadc->Init.Oversampling.OversamplingStopReset |
+ (hadc->Init.TriggerFrequencyMode >> 2UL));
+ }
+ else
+ {
+ /* Disable ADC oversampling scope on ADC group regular */
+ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
+ }
+
+ /* Set the LeftShift parameter: it is applied to the final result with or without oversampling */
+ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_LSHIFT, hadc->Init.LeftBitShift);
+ }
+ /* Configuration of regular group sequencer: */
+ /* - if scan mode is disabled, regular channels sequence length is set to */
+ /* 0x00: 1 channel converted (channel on regular rank 1) */
+ /* Parameter "NbrOfConversion" is discarded. */
+ /* Note: Scan mode is not present by hardware on this device, but */
+ /* emulated by software for alignment over all STM32 devices. */
+ /* - if scan mode is enabled, regular channels sequence length is set to */
+ /* parameter "NbrOfConversion". */
+ if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
+ {
+ /* Set number of ranks in regular group sequencer */
+ MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
+ }
+ else
+ {
+ CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
+ }
+
+ /* Initialize the ADC state */
+ /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
+
+ }
+ else
+ {
+ /* Configuration of ADC: */
+ /* - oversampling enable */
+ /* - oversampling ratio */
+ /* - oversampling shift */
+ /* - oversampling discontinuous mode (triggered mode) */
+ /* - trigger frequency mode */
+ tmpCFGR2 |= (hadc->Init.Oversampling.Ratio |
+ hadc->Init.Oversampling.RightBitShift |
+ hadc->Init.Oversampling.TriggeredMode |
+ hadc->Init.TriggerFrequencyMode
+ );
+
+ if (hadc->Init.OversamplingMode == ENABLE)
+ {
+ SET_BIT(tmpCFGR2, ADC_CFGR2_ROVSE);
+ }
+ MODIFY_REG(hadc->Instance->CFGR2,
+ ADC_CFGR2_LFTRIG | ADC_CFGR2_ROVSE | ADC4_CFGR2_OVSR | ADC_CFGR2_OVSS | ADC_CFGR2_TROVS,
+ tmpCFGR2);
+
+
+ /* Channel sampling time configuration */
+ LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1, \
+ hadc->Init.SamplingTimeCommon1);
+ LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_2, \
+ hadc->Init.SamplingTimeCommon2);
+
+ /* Configuration of regular group sequencer: */
+ /* - if scan mode is disabled, regular channels sequence length is set to */
+ /* 0x00: 1 channel converted (channel on regular rank 1) */
+ /* Parameter "NbrOfConversion" is discarded. */
+ /* Note: Scan mode is not present by hardware on this device, but */
+ /* emulated by software for alignment over all STM32 devices. */
+ /* - if scan mode is enabled, regular channels sequence length is set to */
+ /* parameter "NbrOfConversion". */
+ /* Channels must be configured into each rank using function */
+ /* "HAL_ADC_ConfigChannel()". */
+ if (hadc->Init.ScanConvMode == ADC4_SCAN_DISABLE)
+ {
+ /* Set sequencer scan length by clearing ranks above rank 1 */
+ /* and do not modify rank 1 value. */
+ SET_BIT(hadc->Instance->CHSELR, ADC_CHSELR_SQ2_TO_SQ8);
+
+ }
+ else if (hadc->Init.ScanConvMode == ADC4_SCAN_ENABLE)
+ {
+ /* Count number of ranks available in HAL ADC handle variable */
+ uint32_t ADCGroupRegularSequencerRanksCount;
+
+ /* Parse all ranks from 1 to 8 */
+ for (ADCGroupRegularSequencerRanksCount = 0UL; ADCGroupRegularSequencerRanksCount < (8UL); \
+ ADCGroupRegularSequencerRanksCount++)
+ {
+ /* Check each sequencer rank until value of end of sequence */
+ if (((hadc->ADCGroupRegularSequencerRanks >> (ADCGroupRegularSequencerRanksCount * 4UL)) & ADC_CHSELR_SQ1) ==
+ ADC_CHSELR_SQ1)
+ {
+ break;
+ }
+ }
+
+ if (ADCGroupRegularSequencerRanksCount == 1UL)
+ {
+ /* Set ADC group regular sequencer: */
+ /* Set sequencer scan length by clearing ranks above rank 1 */
+ /* and do not modify rank 1 value. */
+ SET_BIT(hadc->Instance->CHSELR, ADC_CHSELR_SQ2_TO_SQ8);
+ }
+ else
+ {
+ /* Set ADC group regular sequencer: */
+ /* - Set ADC group regular sequencer to value memorized */
+ /* in HAL ADC handle */
+ /* Note: This value maybe be initialized at a unknown value, */
+ /* therefore after the first call of "HAL_ADC_Init()", */
+ /* each rank corresponding to parameter "NbrOfConversion" */
+ /* must be set using "HAL_ADC_ConfigChannel()". */
+ /* - Set sequencer scan length by clearing ranks above maximum rank */
+ /* and do not modify other ranks value. */
+ MODIFY_REG(hadc->Instance->CHSELR,
+ ADC_CHSELR_SQ_ALL,
+ (ADC_CHSELR_SQ2_TO_SQ8 << (((hadc->Init.NbrOfConversion - 1UL) * ADC4_REGULAR_RANK_2) & 0x1FUL)) \
+ | (hadc->ADCGroupRegularSequencerRanks)
+ );
+ }
+ }
+
+ /* Check back that ADC registers have effectively been configured to */
+ /* ensure of no potential problem of ADC core IP clocking. */
+ /* Check through register CFGR1 (excluding analog watchdog configuration: */
+ /* set into separate dedicated function, and bits of ADC resolution set */
+ /* out of temporary variable 'tmpCFGR1'). */
+ if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_RES))
+ == tmpCFGR1)
+ {
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Set the ADC state */
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+ }
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Deinitialize the ADC peripheral registers to their default reset
+ * values, with deinitialization of the ADC MSP.
+ * @note For devices with several ADCs: reset of ADC common registers is done
+ * only if all ADCs sharing the same common group are disabled.
+ * (function "HAL_ADC_MspDeInit()" is also called under the same conditions:
+ * all ADC instances use the same core clock at RCC level, disabling
+ * the core clock reset all ADC instances).
+ * If this is not the case, reset of these common parameters reset is
+ * bypassed without error reporting: it can be the intended behavior in
+ * case of reset of a single ADC while the other ADCs sharing the same
+ * common group is still running.
+ * @note By default, HAL_ADC_DeInit() set ADC in mode deep power-down:
+ * this saves more power by reducing leakage currents
+ * and is particularly interesting before entering MCU low-power modes.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check ADC handle */
+ if (hadc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
+
+ /* Stop potential conversion on going */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_READY;
+ }
+ }
+
+ /* Note: HAL ADC deInit is done independently of ADC conversion stop */
+ /* and disable return status. In case of status fail, attempt to */
+ /* perform deinitialization anyway and it is up user code in */
+ /* in HAL_ADC_MspDeInit() to reset the ADC peripheral using */
+ /* system RCC hard reset. */
+
+ /* ========== Reset ADC registers ========== */
+ /* Reset register IER */
+ if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
+ {
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 |
+ ADC_IT_JQOVF | ADC_IT_OVR |
+ ADC_IT_JEOS | ADC_IT_JEOC |
+ ADC_IT_EOS | ADC_IT_EOC |
+ ADC_IT_EOSMP | ADC_IT_RDY));
+
+ /* Reset register ISR */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
+ ADC_FLAG_JQOVF | ADC_FLAG_OVR |
+ ADC_FLAG_JEOS | ADC_FLAG_JEOC |
+ ADC_FLAG_EOS | ADC_FLAG_EOC |
+ ADC_FLAG_EOSMP | ADC_FLAG_RDY));
+
+ /* Reset register CR */
+ /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART,
+ ADC_CR_ADCAL, ADC_CR_ADDIS and ADC_CR_ADEN are in access mode "read-set":
+ no direct reset applicable.
+ Update CR register to reset value where doable by software */
+ CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN);
+ SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
+
+ /* Reset register CFGR */
+ CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_AWD1CH | ADC_CFGR1_JAUTO | ADC_CFGR1_JAWD1EN |
+ ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_JDISCEN |
+ ADC_CFGR1_DISCNUM | ADC_CFGR1_DISCEN | ADC_CFGR1_AUTDLY |
+ ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD |
+ ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL |
+ ADC_CFGR1_RES | ADC_CFGR1_DMNGT);
+
+ /* Reset register CFGR2 */
+ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS |
+ ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE);
+
+ /* Reset register SMPR1 */
+ CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_FIELDS);
+
+ /* Reset register SMPR2 */
+ CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 |
+ ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 |
+ ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10);
+
+ /* Reset register LTR1 and HTR1 */
+ CLEAR_BIT(hadc->Instance->LTR1, ADC_LTR_LT);
+ CLEAR_BIT(hadc->Instance->HTR1, ADC_HTR_HT);
+
+ /* Reset register LTR2 and HTR2*/
+ CLEAR_BIT(hadc->Instance->LTR2, ADC_LTR_LT);
+ CLEAR_BIT(hadc->Instance->HTR2, ADC_HTR_HT);
+
+ /* Reset register LTR3 and HTR3 */
+ CLEAR_BIT(hadc->Instance->LTR3, ADC_LTR_LT);
+ CLEAR_BIT(hadc->Instance->HTR3, ADC_HTR_HT);
+
+ /* Reset register SQR1 */
+ CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 |
+ ADC_SQR1_SQ1 | ADC_SQR1_L);
+
+ /* Reset register SQR2 */
+ CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 |
+ ADC_SQR2_SQ6 | ADC_SQR2_SQ5);
+
+ /* Reset register SQR3 */
+ CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 |
+ ADC_SQR3_SQ11 | ADC_SQR3_SQ10);
+
+ /* Reset register SQR4 */
+ CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
+
+ /* Register JSQR was reset when the ADC was disabled */
+
+ /* Reset register DR */
+ /* bits in access mode read only, no direct reset applicable*/
+
+ /* Reset register OFR1 */
+ CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSAT | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
+ /* Reset register OFR2 */
+ CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSAT | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
+ /* Reset register OFR3 */
+ CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSAT | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
+ /* Reset register OFR4 */
+ CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSAT | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
+
+ /* Reset register GCOMP */
+ CLEAR_BIT(hadc->Instance->GCOMP, ADC_GCOMP_GCOMP | ADC_GCOMP_GCOMPCOEFF);
+
+ /* Reset registers JDR1, JDR2, JDR3, JDR4 */
+ /* bits in access mode read only, no direct reset applicable*/
+
+ /* Reset register AWD2CR */
+ CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
+
+ /* Reset register AWD3CR */
+ CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
+
+ /* Reset register DIFSEL */
+ CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL);
+
+ /* Reset register PCSEL */
+ CLEAR_BIT(hadc->Instance->PCSEL, ADC_PCSEL_PCSEL);
+
+ /* Reset register CALFACT */
+ CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CAPTURE_COEF | ADC_CALFACT_LATCH_COEF);
+ }
+ else
+ {
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 |
+ ADC_IT_AWD1 | ADC_IT_OVR |
+ ADC_IT_EOS | ADC_IT_EOC |
+ ADC_IT_EOSMP | ADC_IT_RDY));
+
+ /* Reset register ISR */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 |
+ ADC_FLAG_AWD1 | ADC_FLAG_OVR |
+ ADC_FLAG_EOS | ADC_FLAG_EOC |
+ ADC_FLAG_EOSMP | ADC_FLAG_RDY));
+
+ /* Reset register CR */
+ /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */
+ /* "read-set": no direct reset applicable. */
+
+ /* Reset register CFGR1 */
+ hadc->Instance->CFGR1 &= ~(ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN |
+ ADC4_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD |
+ ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC4_CFGR1_ALIGN | ADC_CFGR1_RES |
+ ADC4_CFGR1_SCANDIR | ADC4_CFGR1_DMACFG | ADC4_CFGR1_DMAEN);
+
+ /* Reset register CFGR2 */
+ /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */
+ /* already done above. */
+ hadc->Instance->CFGR2 &= ~(ADC_CFGR2_ROVSE | ADC4_CFGR2_OVSR |
+ ADC_CFGR2_TROVS | ADC4_CFGR2_LFTRIG);
+
+ /* Reset register SMPR */
+ hadc->Instance->SMPR1 &= ~ADC_SMPR1_SMP1;
+
+ /* Reset register TR1 */
+ hadc->Instance->AWD1TR &= ~(ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1);
+
+ /* Reset register CHSELR */
+ hadc->Instance->CHSELR &= ~(ADC_CHSELR_SQ_ALL);
+
+ /* Reset register DR */
+ /* bits in access mode read only, no direct reset applicable */
+
+ /* Reset register CCR */
+ ADC12_COMMON->CCR &= ~(ADC_CCR_VBATEN | ADC_CCR_VSENSEEN | ADC_CCR_VREFEN | ADC_CCR_PRESC);
+ }
+
+ /* ========== Reset common ADC registers ========== */
+
+ /* Software is allowed to change common parameters only when all the other
+ ADCs are disabled. */
+ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
+ {
+ /* Reset configuration of ADC common register CCR:
+ - clock mode: CKMODE, PRESCEN
+ - multimode related parameters (when this feature is available): MDMA,
+ DMACFG, DELAY, DUAL (set by HAL_ADCEx_MultiModeConfigChannel() API)
+ - internal measurement paths: Vbat, temperature sensor, Vref (set into
+ HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() )
+ */
+ ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc);
+ }
+
+ /* DeInit the low level hardware.
+ For example:
+ __HAL_RCC_ADC_FORCE_RESET();
+ __HAL_RCC_ADC_RELEASE_RESET();
+ __HAL_RCC_ADC_CLK_DISABLE();
+ Keep in mind that all ADCs use the same clock: disabling
+ the clock will reset all ADCs.
+ */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ if (hadc->MspDeInitCallback == NULL)
+ {
+ hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware: RCC clock, NVIC */
+ hadc->MspDeInitCallback(hadc);
+#else
+ /* DeInit the low level hardware: RCC clock, NVIC */
+ HAL_ADC_MspDeInit(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ if (hadc->Instance == ADC4)
+ {
+ /* Reset HAL ADC handle variable */
+ hadc->ADCGroupRegularSequencerRanks = 0x00000000UL;
+ }
+ else
+ {
+ /* Reset injected channel configuration parameters */
+ hadc->InjectionConfig.ContextQueue = 0;
+ hadc->InjectionConfig.ChannelCount = 0;
+ }
+
+ /* Set ADC state */
+ hadc->State = HAL_ADC_STATE_RESET;
+
+ __HAL_UNLOCK(hadc);
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Initialize the ADC MSP.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_MspInit must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief DeInitialize the ADC MSP.
+ * @param hadc ADC handle
+ * @note All ADC instances use the same core clock at RCC level, disabling
+ * the core clock reset all ADC instances).
+ * @retval None
+ */
+__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_MspDeInit must be implemented in the user file.
+ */
+}
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User ADC Callback
+ * To be used instead of the weak predefined callback
+ * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
+ * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
+ * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
+ * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
+ * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
+ * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID
+ * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID
+ * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID
+ * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID
+ * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
+ * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
+ * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
+ pADC_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
+ {
+ switch (CallbackID)
+ {
+ case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
+ hadc->ConvCpltCallback = pCallback;
+ break;
+
+ case HAL_ADC_CONVERSION_HALF_CB_ID :
+ hadc->ConvHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
+ hadc->LevelOutOfWindowCallback = pCallback;
+ break;
+
+ case HAL_ADC_ERROR_CB_ID :
+ hadc->ErrorCallback = pCallback;
+ break;
+
+ case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
+ hadc->InjectedConvCpltCallback = pCallback;
+ break;
+
+ case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID :
+ hadc->InjectedQueueOverflowCallback = pCallback;
+ break;
+
+ case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
+ hadc->LevelOutOfWindow2Callback = pCallback;
+ break;
+
+ case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
+ hadc->LevelOutOfWindow3Callback = pCallback;
+ break;
+
+ case HAL_ADC_END_OF_SAMPLING_CB_ID :
+ hadc->EndOfSamplingCallback = pCallback;
+ break;
+
+ case HAL_ADC_MSPINIT_CB_ID :
+ hadc->MspInitCallback = pCallback;
+ break;
+
+ case HAL_ADC_MSPDEINIT_CB_ID :
+ hadc->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_ADC_STATE_RESET == hadc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_ADC_MSPINIT_CB_ID :
+ hadc->MspInitCallback = pCallback;
+ break;
+
+ case HAL_ADC_MSPDEINIT_CB_ID :
+ hadc->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Unregister a ADC Callback
+ * ADC callback is redirected to the weak predefined callback
+ * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
+ * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
+ * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
+ * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
+ * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
+ * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID
+ * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID
+ * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID
+ * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID
+ * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
+ * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
+ * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
+ {
+ switch (CallbackID)
+ {
+ case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
+ hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
+ break;
+
+ case HAL_ADC_CONVERSION_HALF_CB_ID :
+ hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
+ break;
+
+ case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
+ hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
+ break;
+
+ case HAL_ADC_ERROR_CB_ID :
+ hadc->ErrorCallback = HAL_ADC_ErrorCallback;
+ break;
+
+ case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
+ hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback;
+ break;
+
+ case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID :
+ hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback;
+ break;
+
+ case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
+ hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback;
+ break;
+
+ case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
+ hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback;
+ break;
+
+ case HAL_ADC_END_OF_SAMPLING_CB_ID :
+ hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback;
+ break;
+
+ case HAL_ADC_MSPINIT_CB_ID :
+ hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_ADC_MSPDEINIT_CB_ID :
+ hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_ADC_STATE_RESET == hadc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_ADC_MSPINIT_CB_ID :
+ hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_ADC_MSPDEINIT_CB_ID :
+ hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions
+ * @brief ADC IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start conversion of regular group.
+ (+) Stop conversion of regular group.
+ (+) Poll for conversion complete on regular group.
+ (+) Poll for conversion event.
+ (+) Get result of regular channel conversion.
+ (+) Start conversion of regular group and enable interruptions.
+ (+) Stop conversion of regular group and disable interruptions.
+ (+) Handle ADC interrupt request
+ (+) Start conversion of regular group and enable DMA transfer.
+ (+) Stop conversion of regular group and disable ADC DMA transfer.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable ADC, start conversion of regular group.
+ * @note Interruptions enabled in this function: None.
+ * @note Case of multimode enabled (when multimode feature is available):
+ * if ADC is Slave, ADC is enabled but conversion is not started,
+ * if ADC is master, ADC is enabled and multimode conversion is started.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Perform ADC enable and conversion start if no conversion is on going */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+ HAL_ADC_STATE_REG_BUSY);
+
+ if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
+ {
+ /* Set ADC error code */
+ /* Check if a conversion is on going on ADC group injected */
+ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ /* Reset ADC error code fields related to regular conversions only */
+ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+ }
+ else
+ {
+ /* Reset all ADC error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+ }
+ else
+ {
+ /* Set ADC error code */
+ /* Reset all ADC error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Clear ADC group regular conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* Case of multimode enabled (when multimode feature is available): */
+ /* - if ADC is slave and dual regular conversions are enabled, ADC is */
+ /* enabled only (conversion is not started), */
+ /* - if ADC is master, ADC is enabled and conversion is started. */
+
+ if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
+ {
+ if (READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_JAUTO) != 0UL)
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+ }
+ }
+
+ /* Start ADC group regular conversion */
+ LL_ADC_REG_StartConversion(hadc->Instance);
+ }
+ else
+ {
+ __HAL_UNLOCK(hadc);
+ }
+ }
+ else
+ {
+ tmp_hal_status = HAL_BUSY;
+ }
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Stop ADC conversion of regular group (and injected channels in
+ * case of auto_injection mode), disable ADC peripheral.
+ * @note: ADC peripheral disable is forcing stop of potential
+ * conversion on injected group. If injected group is under use, it
+ * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential conversion on going, on ADC groups regular and injected */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* 2. Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+
+ __HAL_UNLOCK(hadc);
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Wait for regular group conversion to be completed.
+ * @note ADC conversion flags EOS (end of sequence) and EOC (end of
+ * conversion) are cleared by this function, with an exception:
+ * if low power feature "LowPowerAutoWait" is enabled, flags are
+ * not cleared to not interfere with this feature until data register
+ * is read using function HAL_ADC_GetValue().
+ * @note This function cannot be used in a particular setup: ADC configured
+ * in DMA mode and polling for end of each conversion (ADC init
+ * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
+ * In this case, DMA resets the flag EOC and polling cannot be
+ * performed on each conversion. Nevertheless, polling can still
+ * be performed on the complete sequence (ADC init
+ * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
+ * @param hadc ADC handle
+ * @param Timeout Timeout value in millisecond.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
+{
+ uint32_t tickstart;
+ uint32_t tmp_flag_end;
+ uint32_t tmp_cfgr;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* If end of conversion selected to end of sequence conversions */
+ if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
+ {
+ tmp_flag_end = ADC_FLAG_EOS;
+ }
+ /* If end of conversion selected to end of unitary conversion */
+ else /* ADC_EOC_SINGLE_CONV */
+ {
+ /* Verification that ADC configuration is compliant with polling for */
+ /* each conversion: */
+ /* Particular case is ADC configured in DMA mode and ADC sequencer with */
+ /* several ranks and polling for end of each conversion. */
+ /* For code simplicity sake, this particular case is generalized to */
+ /* ADC configured in DMA mode and and polling for end of each conversion. */
+
+ if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
+ {
+ /* Check ADC DMA mode */
+ if (READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMNGT_0) != 0UL)
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ return HAL_ERROR;
+ }
+ else
+ {
+ tmp_flag_end = (ADC_FLAG_EOC);
+ }
+ }
+ else
+ {
+ if ((hadc->Instance->CFGR1 & ADC4_CFGR1_DMAEN) != 0UL)
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ return HAL_ERROR;
+ }
+ else
+ {
+ tmp_flag_end = (ADC_FLAG_EOC);
+ }
+ }
+ }
+
+ /* Get tick count */
+ tickstart = HAL_GetTick();
+
+ /* Wait until End of unitary conversion or sequence conversions flag is raised */
+ while ((hadc->Instance->ISR & tmp_flag_end) == 0UL)
+ {
+ /* Check if timeout is disabled (set to infinite wait) */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
+ {
+ /* New check to avoid false timeout detection in case of preemption */
+ if ((hadc->Instance->ISR & tmp_flag_end) == 0UL)
+ {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Update ADC state machine */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going. */
+ if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
+ && (hadc->Init.ContinuousConvMode == DISABLE)
+ )
+ {
+ if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
+ {
+ /* Check whether end of sequence is reached */
+ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
+ {
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+
+ /* Retrieve handle ADC CFGR register */
+ tmp_cfgr = READ_REG(hadc->Instance->CFGR1);
+
+ /* Clear polled flag */
+ if (tmp_flag_end == ADC_FLAG_EOS)
+ {
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS);
+ }
+ else
+ {
+ /* Clear end of conversion EOC flag of regular group if low power feature */
+ /* "LowPowerAutoWait " is disabled, to not interfere with this feature */
+ /* until data register is read using function HAL_ADC_GetValue(). */
+ if (READ_BIT(tmp_cfgr, ADC_CFGR1_AUTDLY) == 0UL)
+ {
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
+ }
+ }
+ }
+ else
+ {
+ /* Check whether end of sequence is reached */
+ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
+ {
+ /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
+ /* ADSTART==0 (no conversion on going) */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* Disable ADC end of single conversion interrupt on group regular */
+ /* Note: Overrun interrupt was enabled with EOC interrupt in */
+ /* HAL_Start_IT(), but is not disabled here because can be used */
+ /* by overrun IRQ process below. */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
+
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ else
+ {
+ /* Change ADC state to error state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ }
+ }
+
+ /* Clear end of conversion flag of regular group if low power feature */
+ /* "LowPowerAutoWait " is disabled, to not interfere with this feature */
+ /* until data register is read using function HAL_ADC_GetValue(). */
+ if (hadc->Init.LowPowerAutoWait == DISABLE)
+ {
+ /* Clear regular group conversion flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
+ }
+
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Poll for ADC event.
+ * @param hadc ADC handle
+ * @param EventType the ADC event type.
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_EOSMP_EVENT ADC End of Sampling event
+ * @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog,
+ * present on all STM32 devices)
+ * @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog,
+ * not present on all STM32 families)
+ * @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog,
+ * not present on all STM32 families)
+ * @arg @ref ADC_OVR_EVENT ADC Overrun event
+ * @arg @ref ADC_JQOVF_EVENT ADC Injected context queue overflow event
+ * @param Timeout Timeout value in millisecond.
+ * @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR.
+ * Indeed, the latter is reset only if hadc->Init.Overrun field is set
+ * to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten
+ * by a new converted data as soon as OVR is cleared.
+ * To reset OVR flag once the preserved data is retrieved, the user can resort
+ * to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_EVENT_TYPE(EventType));
+
+ /* Get tick count */
+ tickstart = HAL_GetTick();
+
+ /* Check selected event flag */
+ while (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL)
+ {
+ /* Check if timeout is disabled (set to infinite wait) */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
+ {
+ /* New check to avoid false timeout detection in case of preemption */
+ if (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL)
+ {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ switch (EventType)
+ {
+ /* End Of Sampling event */
+ case ADC_EOSMP_EVENT:
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
+
+ /* Clear the End Of Sampling flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
+
+ break;
+
+ /* Analog watchdog (level out of window) event */
+ /* Note: In case of several analog watchdog enabled, if needed to know */
+ /* which one triggered and on which ADCx, test ADC state of analog watchdog */
+ /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()". */
+ /* For example: */
+ /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " */
+ /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD2) != 0UL) " */
+ /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD3) != 0UL) " */
+
+ /* Check analog watchdog 1 flag */
+ case ADC_AWD_EVENT:
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
+
+ break;
+
+ /* Check analog watchdog 2 flag */
+ case ADC_AWD2_EVENT:
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
+
+ break;
+
+ /* Check analog watchdog 3 flag */
+ case ADC_AWD3_EVENT:
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
+
+ break;
+
+ /* Injected context queue overflow event */
+ case ADC_JQOVF_EVENT:
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
+
+ /* Set ADC error code to Injected context queue overflow */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
+
+ /* Clear ADC Injected context queue overflow flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
+
+ break;
+
+ /* Overrun event */
+ default: /* Case ADC_OVR_EVENT */
+ /* If overrun is set to overwrite previous data, overrun event is not */
+ /* considered as an error. */
+ /* (cf ref manual "Managing conversions without using the DMA and without */
+ /* overrun ") */
+ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
+
+ /* Set ADC error code to overrun */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+ }
+ else
+ {
+ /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN
+ otherwise, data register is potentially overwritten by new converted data as soon
+ as OVR is cleared. */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+ }
+ break;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable ADC, start conversion of regular group with interruption.
+ * @note Interruptions enabled in this function according to initialization
+ * setting : EOC (end of conversion), EOS (end of sequence),
+ * OVR overrun.
+ * Each of these interruptions has its dedicated callback function.
+ * @note Case of multimode enabled (when multimode feature is available):
+ * HAL_ADC_Start_IT() must be called for ADC Slave first, then for
+ * ADC Master.
+ * For ADC Slave, ADC is enabled only (conversion is not started).
+ * For ADC Master, ADC is enabled and multimode conversion is started.
+ * @note To guarantee a proper reset of all interruptions once all the needed
+ * conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure
+ * a correct stop of the IT-based conversions.
+ * @note By default, HAL_ADC_Start_IT() does not enable the End Of Sampling
+ * interruption. If required (e.g. in case of oversampling with trigger
+ * mode), the user must:
+ * 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP)
+ * 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP)
+ * before calling HAL_ADC_Start_IT().
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Perform ADC enable and conversion start if no conversion is on going */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ __HAL_LOCK(hadc);
+
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+ HAL_ADC_STATE_REG_BUSY);
+
+
+ /* Set ADC error code */
+ /* Check if a conversion is on going on ADC group injected */
+ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
+ {
+ /* Reset ADC error code fields related to regular conversions only */
+ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+ }
+ else
+ {
+ /* Reset all ADC error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Clear ADC group regular conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Disable all interruptions before enabling the desired ones */
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+
+ /* Enable ADC end of conversion interrupt */
+ switch (hadc->Init.EOCSelection)
+ {
+ case ADC_EOC_SEQ_CONV:
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS);
+ break;
+ /* case ADC_EOC_SINGLE_CONV */
+ default:
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
+ break;
+ }
+
+ /* Enable ADC overrun interrupt */
+ /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is
+ ADC_IT_OVR enabled; otherwise data overwrite is considered as normal
+ behavior and no CPU time is lost for a non-processed interruption */
+ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
+ {
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+ }
+
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* Case of multimode enabled (when multimode feature is available): */
+ /* - if ADC is slave and dual regular conversions are enabled, ADC is */
+ /* enabled only (conversion is not started), */
+ /* - if ADC is master, ADC is enabled and conversion is started. */
+ /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
+ if (READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_JAUTO) != 0UL)
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+
+ /* Enable as well injected interruptions in case
+ HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
+ allows to start regular and injected conversions when JAUTO is
+ set with a single call to HAL_ADC_Start_IT() */
+ switch (hadc->Init.EOCSelection)
+ {
+ case ADC_EOC_SEQ_CONV:
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
+ break;
+ /* case ADC_EOC_SINGLE_CONV */
+ default:
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+ break;
+ }
+ }
+
+ /* Start ADC group regular conversion */
+ LL_ADC_REG_StartConversion(hadc->Instance);
+
+ }
+ else
+ {
+ __HAL_UNLOCK(hadc);
+ }
+
+ }
+ else
+ {
+ tmp_hal_status = HAL_BUSY;
+ }
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Stop ADC conversion of regular group (and injected group in
+ * case of auto_injection mode), disable interrution of
+ * end-of-conversion, disable ADC peripheral.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential conversion on going, on ADC groups regular and injected */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Disable ADC end of conversion interrupt for regular group */
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+
+ /* 2. Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+
+ __HAL_UNLOCK(hadc);
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Enable ADC, start conversion of regular group and transfer result through DMA.
+ * @note Interruptions enabled in this function:
+ * overrun (if applicable), DMA half transfer, DMA transfer complete.
+ * Each of these interruptions has its dedicated callback function.
+ * @note Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_DMA()
+ * is designed for single-ADC mode only. For multimode, the dedicated
+ * HAL_ADCEx_MultiModeStart_DMA() function must be used.
+ * @param hadc ADC handle
+ * @param pData Destination Buffer address.
+ * @param Length Number of data to be transferred from ADC peripheral to memory
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, const uint32_t *pData, uint32_t Length)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+ uint32_t LengthInBytes;
+ DMA_NodeConfTypeDef node_conf;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Perform ADC enable and conversion start if no conversion is on going */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ __HAL_LOCK(hadc);
+
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+ HAL_ADC_STATE_REG_BUSY);
+
+ if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
+ {
+ /* Check if a conversion is on going on ADC group injected */
+ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
+ {
+ /* Reset ADC error code fields related to regular conversions only */
+ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+ }
+ else
+ {
+ /* Reset all ADC error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+ }
+ else
+ {
+ /* Reset all ADC error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Set the DMA transfer complete callback */
+ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
+
+ /* Set the DMA half transfer complete callback */
+ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
+
+ /* Set the DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
+
+
+ /* Manage ADC and DMA start: ADC overrun interruption, DMA start, */
+ /* ADC start (in case of SW start): */
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC */
+ /* operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* With DMA, overrun event is always considered as an error even if
+ hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore,
+ ADC_IT_OVR is enabled. */
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+
+ if (hadc->Instance == ADC4)
+ {
+ /* Enable ADC DMA mode */
+ hadc->Instance->CFGR1 |= ADC4_CFGR1_DMAEN;
+ }
+
+ /* Start the DMA channel */
+ /* Check linkedlist mode */
+ if ((hadc->DMA_Handle->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if ((hadc->DMA_Handle->LinkedListQueue != NULL) && (hadc->DMA_Handle->LinkedListQueue->Head != NULL))
+ {
+ /* Length should be converted to number of bytes */
+ if (HAL_DMAEx_List_GetNodeConfig(&node_conf, hadc->DMA_Handle->LinkedListQueue->Head) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Length should be converted to number of bytes */
+ if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
+ {
+ /* Word -> Bytes */
+ LengthInBytes = Length * 4U;
+ }
+ else if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
+ {
+ /* Halfword -> Bytes */
+ LengthInBytes = Length * 2U;
+ }
+ else /* Bytes */
+ {
+ /* Same size already expressed in Bytes */
+ LengthInBytes = Length;
+ }
+
+ hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = (uint32_t)LengthInBytes;
+ hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = \
+ (uint32_t)&hadc->Instance->DR;
+ hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
+ tmp_hal_status = HAL_DMAEx_List_Start_IT(hadc->DMA_Handle);
+ }
+ else
+ {
+ tmp_hal_status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Length should be converted to number of bytes */
+ if (hadc->DMA_Handle->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
+ {
+ /* Word -> Bytes */
+ LengthInBytes = Length * 4U;
+ }
+ else if (hadc->DMA_Handle->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
+ {
+ /* Halfword -> Bytes */
+ LengthInBytes = Length * 2U;
+ }
+ else /* Bytes */
+ {
+ /* Same size already expressed in Bytes */
+ LengthInBytes = Length;
+ }
+
+ tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, \
+ LengthInBytes);
+ }
+
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* Start ADC group regular conversion */
+ LL_ADC_REG_StartConversion(hadc->Instance);
+ }
+ else
+ {
+ __HAL_UNLOCK(hadc);
+ }
+ }
+ else
+ {
+ tmp_hal_status = HAL_BUSY;
+ }
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Stop ADC conversion of regular group (and injected group in
+ * case of auto_injection mode), disable ADC DMA transfer, disable
+ * ADC peripheral.
+ * @note: ADC peripheral disable is forcing stop of potential
+ * conversion on ADC group injected. If ADC group injected is under use, it
+ * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
+ * @note Case of multimode enabled (when multimode feature is available):
+ * HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only.
+ * For multimode, the dedicated HAL_ADCEx_MultiModeStop_DMA() API must be used.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential ADC group regular conversion on going */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK)
+ {
+ if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
+ {
+ /* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */
+ MODIFY_REG(hadc->Instance->CFGR1, ADC_CFGR1_DMNGT_0 | ADC_CFGR1_DMNGT_1, 0UL);
+ }
+ else
+ {
+ /* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */
+ CLEAR_BIT(hadc->Instance->CFGR1, ADC4_CFGR1_DMAEN);
+ }
+
+ /* Disable the DMA channel (in case of DMA in circular mode or stop */
+ /* while DMA transfer is on going) */
+ if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
+ {
+ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+ /* Check if DMA channel effectively disabled */
+ if (tmp_hal_status != HAL_OK)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+ }
+ }
+
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+ /* 2. Disable the ADC peripheral */
+ /* Update "tmp_hal_status" only if DMA channel disabling passed, */
+ /* to keep in memory a potential failing status. */
+ if (tmp_hal_status == HAL_OK)
+ {
+ tmp_hal_status = ADC_Disable(hadc);
+ }
+ else
+ {
+ (void)ADC_Disable(hadc);
+ }
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
+ }
+ else
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_READY);
+ }
+ }
+ }
+
+ __HAL_UNLOCK(hadc);
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Get ADC regular group conversion result.
+ * @note Reading register DR automatically clears ADC flag EOC
+ * (ADC group regular end of unitary conversion).
+ * @note This function does not clear ADC flag EOS
+ * (ADC group regular end of sequence conversion).
+ * Occurrence of flag EOS rising:
+ * - If sequencer is composed of 1 rank, flag EOS is equivalent
+ * to flag EOC.
+ * - If sequencer is composed of several ranks, during the scan
+ * sequence flag EOC only is raised, at the end of the scan sequence
+ * both flags EOC and EOS are raised.
+ * To clear this flag, either use function:
+ * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
+ * model polling: @ref HAL_ADC_PollForConversion()
+ * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
+ * @param hadc ADC handle
+ * @retval ADC group regular conversion data
+ */
+uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Note: EOC flag is not cleared here by software because automatically */
+ /* cleared by hardware when reading register DR. */
+
+ /* Return ADC converted value */
+ return hadc->Instance->DR;
+}
+
+/**
+ * @brief Handle ADC interrupt request.
+ * @param hadc ADC handle
+ * @retval None
+ */
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
+{
+ uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */
+ uint32_t tmp_isr = hadc->Instance->ISR;
+ uint32_t tmp_ier = hadc->Instance->IER;
+ uint32_t tmp_adc_inj_is_trigger_source_sw_start;
+ uint32_t tmp_adc_reg_is_trigger_source_sw_start;
+ uint32_t tmp_cfgr;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
+
+ /* ========== Check End of Sampling flag for ADC group regular ========== */
+ if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP))
+ {
+ /* Update state machine on end of sampling status if not in error state */
+ if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
+ }
+
+ /* End Of Sampling callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->EndOfSamplingCallback(hadc);
+#else
+ HAL_ADCEx_EndOfSamplingCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+ /* Clear regular group conversion flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
+ }
+
+ /* ====== Check ADC group regular end of unitary conversion sequence conversions ===== */
+ if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
+ (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)))
+ {
+ /* Update state machine on conversion status if not in error state */
+ if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+ }
+
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going */
+ /* to disable interruption. */
+ if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
+ {
+ if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
+ {
+ /* Get relevant register CFGR in ADC instance of ADC master or slave */
+ /* in function of multimode state (for devices with multimode */
+ /* available). */
+ tmp_cfgr = READ_REG(hadc->Instance->CFGR1);
+
+ /* Carry on if continuous mode is disabled */
+ if (READ_BIT(tmp_cfgr, ADC_CFGR1_CONT) != ADC_CFGR1_CONT)
+ {
+ /* If End of Sequence is reached, disable interrupts */
+ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
+ {
+ /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
+ /* ADSTART==0 (no conversion on going) */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* Disable ADC end of sequence conversion interrupt */
+ /* Note: Overrun interrupt was enabled with EOC interrupt in */
+ /* HAL_Start_IT(), but is not disabled here because can be used */
+ /* by overrun IRQ process below. */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
+
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+ else
+ {
+ /* Change ADC state to error state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going */
+ /* to disable interruption. */
+ if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
+ && (hadc->Init.ContinuousConvMode == DISABLE)
+ )
+ {
+ /* If End of Sequence is reached, disable interrupts */
+ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
+ {
+ /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
+ /* ADSTART==0 (no conversion on going) */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* Disable ADC end of single conversion interrupt on group regular */
+ /* Note: Overrun interrupt was enabled with EOC interrupt in */
+ /* HAL_Start_IT(), but is not disabled here because can be used */
+ /* by overrun IRQ process below. */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
+
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_READY);
+ }
+ else
+ {
+ /* Change ADC state to error state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ }
+ }
+ }
+ }
+
+ /* Conversion complete callback */
+ /* Note: Into callback function "HAL_ADC_ConvCpltCallback()", */
+ /* to determine if conversion has been triggered from EOC or EOS, */
+ /* possibility to use: */
+ /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ConvCpltCallback(hadc);
+#else
+ HAL_ADC_ConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+ /* Clear regular group conversion flag */
+ /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */
+ /* conversion flags clear induces the release of the preserved data.*/
+ /* Therefore, if the preserved data value is needed, it must be */
+ /* read preliminarily into HAL_ADC_ConvCpltCallback(). */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
+ }
+
+ if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
+ {
+ /* ====== Check ADC group injected end of unitary conversion sequence conversions ===== */
+ if ((((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) ||
+ (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)))
+ {
+ /* Update state machine on conversion status if not in error state */
+ if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
+ }
+
+ /* Retrieve ADC configuration */
+ tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance);
+ tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
+ /* Get relevant register CFGR in ADC instance of ADC master or slave */
+ /* in function of multimode state (for devices with multimode */
+ /* available). */
+
+ tmp_cfgr = READ_REG(hadc->Instance->CFGR1);
+
+ /* Disable interruption if no further conversion upcoming by injected */
+ /* external trigger or by automatic injected conversion with regular */
+ /* group having no further conversion upcoming (same conditions as */
+ /* regular group interruption disabling above), */
+ /* and if injected scan sequence is completed. */
+ if (tmp_adc_inj_is_trigger_source_sw_start != 0UL)
+ {
+ if ((READ_BIT(tmp_cfgr, ADC_CFGR1_JAUTO) == 0UL) ||
+ ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
+ (READ_BIT(tmp_cfgr, ADC_CFGR1_CONT) == 0UL)))
+ {
+ /* If End of Sequence is reached, disable interrupts */
+ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
+ {
+ /* Particular case if injected contexts queue is enabled: */
+ /* when the last context has been fully processed, JSQR is reset */
+ /* by the hardware. Even if no injected conversion is planned to come */
+ /* (queue empty, triggers are ignored), it can start again */
+ /* immediately after setting a new context (JADSTART is still set). */
+ /* Therefore, state of HAL ADC injected group is kept to busy. */
+ /* No ADC_CFGR1_JQM for STM32U5 */
+
+ /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
+ /* JADSTART==0 (no conversion on going) */
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* Disable ADC end of sequence conversion interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
+
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+
+ if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+ }
+ }
+ }
+
+ /* Injected Conversion complete callback */
+ /* Note: HAL_ADCEx_InjectedConvCpltCallback can resort to
+ if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or
+ if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether
+ interruption has been triggered by end of conversion or end of
+ sequence. */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->InjectedConvCpltCallback(hadc);
+#else
+ HAL_ADCEx_InjectedConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+ /* Clear injected group conversion flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS);
+ }
+ } /* Specific ADC1 only */
+
+ /* ========== Check Analog watchdog 1 flag ========== */
+ if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+
+ /* Level out of window 1 callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->LevelOutOfWindowCallback(hadc);
+#else
+ HAL_ADC_LevelOutOfWindowCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
+ }
+
+ /* ========== Check analog watchdog 2 flag ========== */
+ if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2))
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
+
+ /* Level out of window 2 callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->LevelOutOfWindow2Callback(hadc);
+#else
+ HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
+ }
+
+ /* ========== Check analog watchdog 3 flag ========== */
+ if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3))
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
+
+ /* Level out of window 3 callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->LevelOutOfWindow3Callback(hadc);
+#else
+ HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
+ }
+
+ /* ========== Check Overrun flag ========== */
+ if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR))
+ {
+ /* If overrun is set to overwrite previous data (default setting), */
+ /* overrun event is not considered as an error. */
+ /* (cf ref manual "Managing conversions without using the DMA and without */
+ /* overrun ") */
+ /* Exception for usage with DMA overrun event always considered as an */
+ /* error. */
+ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
+ {
+ overrun_error = 1UL;
+ }
+ else
+ {
+ /* Check DMA configuration */
+ if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
+ {
+ /* Multimode not set or feature not available or ADC independent */
+ if ((hadc->Instance->CFGR1 & ADC_CFGR1_DMNGT) != 0UL)
+ {
+ overrun_error = 1UL;
+ }
+ }
+ else
+ {
+ /* Check DMA configuration */
+ if (LL_ADC_REG_GetDMATransfer(hadc->Instance) != LL_ADC_REG_DMA_TRANSFER_NONE_ADC4)
+ {
+ overrun_error = 1UL;
+ }
+ }
+ }
+
+ if (overrun_error == 1UL)
+ {
+ /* Change ADC state to error state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
+
+ /* Set ADC error code to overrun */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+
+ /* Error callback */
+ /* Note: In case of overrun, ADC conversion data is preserved until */
+ /* flag OVR is reset. */
+ /* Therefore, old ADC conversion data can be retrieved in */
+ /* function "HAL_ADC_ErrorCallback()". */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ErrorCallback(hadc);
+#else
+ HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ }
+
+ /* Clear ADC overrun flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+ }
+
+ if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
+ {
+ /* ========== Check Injected context queue overflow flag ========== */
+ if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF))
+ {
+ /* Change ADC state to overrun state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
+
+ /* Set ADC error code to Injected context queue overflow */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
+
+ /* Clear the Injected context queue overflow flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
+
+ /* Injected context queue overflow callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->InjectedQueueOverflowCallback(hadc);
+#else
+ HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ }
+ } /* Speceific ADC1 only */
+
+}
+
+/**
+ * @brief Conversion complete callback in non-blocking mode.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_ConvCpltCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Conversion DMA half-transfer callback in non-blocking mode.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Analog watchdog 1 callback in non-blocking mode.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief ADC error callback in non-blocking mode
+ * (ADC conversion with interruption or transfer by DMA).
+ * @note In case of error due to overrun when using ADC with DMA transfer
+ * (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
+ * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
+ * - If needed, restart a new ADC conversion using function
+ * "HAL_ADC_Start_DMA()"
+ * (this function is also clearing overrun flag)
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_ErrorCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure channels on regular group
+ (+) Configure the analog watchdog
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure a channel to be assigned to ADC group regular.
+ * @note In case of usage of internal measurement channels:
+ * Vbat/VrefInt/TempSensor.
+ * These internal paths can be disabled using function
+ * HAL_ADC_DeInit().
+ * @note Possibility to update parameters on the fly:
+ * This function initializes channel into ADC group regular,
+ * following calls to this function can be used to reconfigure
+ * some parameters of structure "ADC_ChannelConfTypeDef" on the fly,
+ * without resetting the ADC.
+ * The setting of these parameters is conditioned to ADC state:
+ * Refer to comments of structure "ADC_ChannelConfTypeDef".
+ * @param hadc ADC handle
+ * @param pConfig Structure of ADC channel assigned to ADC group regular.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *pConfig)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ uint32_t tmp_offset_shifted;
+ uint32_t tmp_config_internal_channel;
+ __IO uint32_t wait_loop_index = 0;
+ uint32_t tmp_adc_is_conversion_on_going_regular;
+ uint32_t tmp_adc_is_conversion_on_going_injected;
+ uint32_t tmp_channel;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
+ {
+ assert_param(IS_ADC_REGULAR_RANK(pConfig->Rank));
+ assert_param(IS_ADC_SAMPLE_TIME(pConfig->SamplingTime));
+ assert_param(IS_ADC_SINGLE_DIFFERENTIAL(pConfig->SingleDiff));
+ assert_param(IS_ADC_OFFSET_NUMBER(pConfig->OffsetNumber));
+ assert_param(IS_ADC_RANGE(hadc->Instance, ADC_GET_RESOLUTION(hadc), pConfig->Offset));
+ /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
+ ignored (considered as reset) */
+ assert_param(!((pConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE)));
+
+ /* Verification of channel number */
+ if (pConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
+ {
+ assert_param(IS_ADC_CHANNEL(pConfig->Channel));
+ }
+ else
+ {
+ assert_param(IS_ADC1_DIFF_CHANNEL(pConfig->Channel));
+ }
+ }
+ else
+ {
+ assert_param(IS_ADC4_SAMPLE_TIME(pConfig->SamplingTime));
+
+ if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) ||
+ (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD))
+ {
+ assert_param(IS_ADC4_REGULAR_RANK_SEQ_FIXED(pConfig->Rank));
+ }
+ else
+ {
+ assert_param(IS_ADC4_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
+
+ assert_param(IS_ADC4_REGULAR_RANK(pConfig->Rank));
+ }
+ }
+
+ __HAL_LOCK(hadc);
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on regular group: */
+ /* - Channel number */
+ /* - Channel rank */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
+ {
+ /* ADC channels preselection */
+ hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)pConfig->Channel) & 0x1FUL));
+
+ /* Set ADC group regular sequence: channel on the selected scan sequence rank */
+ LL_ADC_REG_SetSequencerRanks(hadc->Instance, pConfig->Rank, pConfig->Channel);
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on regular group: */
+ /* - Channel sampling time */
+ /* - Channel offset */
+ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+ tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+ if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+ && (tmp_adc_is_conversion_on_going_injected == 0UL)
+ )
+ {
+ /* Set sampling time of the selected ADC channel */
+ LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, pConfig->SamplingTime);
+
+ /* Configure the offset: offset enable/disable, channel, offset value */
+
+ /* Shift the offset with respect to the selected ADC resolution. */
+ /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
+ tmp_offset_shifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)pConfig->Offset);
+
+ if (pConfig->OffsetNumber != ADC_OFFSET_NONE)
+ {
+ /* Set ADC selected offset number */
+ LL_ADC_SetOffset(hadc->Instance, pConfig->OffsetNumber, pConfig->Channel, tmp_offset_shifted);
+ assert_param(IS_ADC_OFFSET_SIGN(pConfig->OffsetSign));
+ assert_param(IS_FUNCTIONAL_STATE(pConfig->OffsetSignedSaturation));
+ /* Set ADC selected offset sign */
+ LL_ADC_SetOffsetSign(hadc->Instance, pConfig->OffsetNumber, pConfig->OffsetSign);
+ /* Set ADC selected offset signed saturation */
+ LL_ADC_SetOffsetSignedSaturation(hadc->Instance, pConfig->OffsetNumber, \
+ (pConfig->OffsetSignedSaturation == ENABLE) \
+ ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE \
+ : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
+ }
+ else
+ {
+ /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is enabled.
+ If this is the case, offset OFRx is disabled since
+ pConfig->OffsetNumber = ADC_OFFSET_NONE. */
+ if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(pConfig->Channel))
+ {
+ CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSAT);
+ }
+ if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(pConfig->Channel))
+ {
+ CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSAT);
+ }
+ if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(pConfig->Channel))
+ {
+ CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSAT);
+ }
+ if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(pConfig->Channel))
+ {
+ CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSAT);
+ }
+ }
+ }
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated only when ADC is disabled: */
+ /* - Single or differential mode */
+ /* - Internal measurement channels: Vbat/VrefInt/TempSensor */
+ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ {
+ /* Set mode single-ended or differential input of the selected ADC channel */
+ LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfig->Channel, pConfig->SingleDiff);
+
+ /* Configuration of differential mode */
+ if (pConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED)
+ {
+ /* Set sampling time of the selected ADC channel */
+ /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
+ tmp_channel = __LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel) \
+ + 1UL) & 0x1FUL);
+ LL_ADC_SetChannelSamplingTime(hadc->Instance, tmp_channel, pConfig->SamplingTime);
+ }
+ /* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */
+ /* If internal channel selected, enable dedicated internal buffers and */
+ /* paths. */
+ /* Note: these internal measurement paths can be disabled using */
+ /* HAL_ADC_DeInit(). */
+
+ if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel))
+ {
+ /* Configuration of common ADC parameters */
+
+ tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+
+ /* Software is allowed to change common parameters only when all ADCs */
+ /* of the common group are disabled. */
+ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
+ {
+ /* If the requested internal measurement path has already been enabled, */
+ /* bypass the configuration processing. */
+ if ((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
+ && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
+ {
+ if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+ LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
+
+ /* Delay for temperature sensor stabilization time */
+ /* Wait loop initialization and execution */
+ /* Note: Variable divided by 2 to compensate partially */
+ /* CPU processing cycles, scaling in us split to not */
+ /* exceed 32 bits register capacity and handle low frequency. */
+ wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) \
+ * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
+ while (wait_loop_index != 0UL)
+ {
+ wait_loop_index--;
+ }
+ }
+ }
+ else if ((pConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel \
+ & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
+ {
+ if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+ LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
+ }
+ }
+ else if ((pConfig->Channel == ADC_CHANNEL_VREFINT)
+ && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
+ {
+ if (ADC_VREFINT_INSTANCE(hadc))
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+ LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
+ }
+ }
+ else
+ {
+ /* nothing to do */
+ }
+ }
+ /* If the requested internal measurement path has already been */
+ /* enabled and other ADC of the common group are enabled, internal */
+ /* measurement paths cannot be enabled. */
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+ }
+ }
+ }
+ else
+ {
+ /* Remap Internal Channels for Cut1 vs Cut2 */
+ tmp_channel = pConfig->Channel;
+ if (HAL_GetREVID() == REV_ID_A) /* STM32U5 silicon Rev.A */
+ {
+ if (pConfig->Channel == ADC4_CHANNEL_TEMPSENSOR)
+ {
+ tmp_channel = (LL_ADC_CHANNEL_22 | ADC_CHANNEL_ID_INTERNAL_CH);
+ }
+ else if (pConfig->Channel == ADC4_CHANNEL_VBAT)
+ {
+ tmp_channel = (LL_ADC_CHANNEL_23 | ADC_CHANNEL_ID_INTERNAL_CH);
+ }
+ else if (pConfig->Channel == ADC_CHANNEL_VCORE)
+ {
+ tmp_channel = (LL_ADC_CHANNEL_VREFINT | LL_ADC_CHANNEL_DIFFERENCIATION_VREFINT_VCORE);
+ }
+ else if (pConfig->Channel == ADC_CHANNEL_DAC1CH1_ADC4)
+ {
+ tmp_channel = (LL_ADC_CHANNEL_20 | ADC_CHANNEL_ID_INTERNAL_CH);
+ }
+ else if (pConfig->Channel == ADC_CHANNEL_DAC1CH2_ADC4)
+ {
+ tmp_channel = (LL_ADC_CHANNEL_21 | ADC_CHANNEL_ID_INTERNAL_CH);
+ }
+ else
+ {
+ tmp_channel = pConfig->Channel;
+ }
+ }
+
+ /* Configure channel: depending on rank setting, add it or remove it from */
+ /* ADC sequencer. */
+ /* If sequencer set to not fully configurable with channel rank set to */
+ /* none, remove the channel from the sequencer. */
+ /* Otherwise (sequencer set to fully configurable or to to not fully */
+ /* configurable with channel rank to be set), configure the selected */
+ /* channel. */
+ if (pConfig->Rank != ADC4_RANK_NONE)
+ {
+ /* Regular sequence configuration */
+ /* Note: ADC channel configuration requires few ADC clock cycles */
+ /* to be ready. Processing of ADC settings in this function */
+ /* induce that a specific wait time is not necessary. */
+ /* For more details on ADC channel configuration ready, */
+ /* refer to function "LL_ADC_IsActiveFlag_CCRDY()". */
+ if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) ||
+ (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD))
+ {
+ /* Sequencer set to not fully configurable: */
+ /* Set the channel by enabling the corresponding bitfield. */
+ LL_ADC_REG_SetSequencerChAdd(hadc->Instance, tmp_channel);
+ }
+ else
+ {
+ /* Sequencer set to fully configurable: */
+ /* Set the channel by entering it into the selected rank. */
+
+ /* Memorize the channel set into variable in HAL ADC handle */
+ MODIFY_REG(hadc->ADCGroupRegularSequencerRanks,
+ ADC_CHSELR_SQ1 << (pConfig->Rank & 0x1FUL),
+ __LL_ADC_CHANNEL_TO_DECIMAL_NB(tmp_channel) << (pConfig->Rank & 0x1FUL));
+
+ /* If the selected rank is below ADC group regular sequencer length, */
+ /* apply the configuration in ADC register. */
+ /* Note: Otherwise, configuration is not applied. */
+ /* To apply it, parameter'NbrOfConversion' must be increased. */
+ if (((pConfig->Rank >> 2UL) + 1UL) <= hadc->Init.NbrOfConversion)
+ {
+ if (HAL_GetREVID() <= REV_ID_A) /* STM32U5 silicon Rev.A */
+ {
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(tmp_channel) >= 20UL)
+ {
+ tmp_channel = (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(tmp_channel) - 9UL));
+ }
+ }
+ LL_ADC_REG_SetSequencerRanks(hadc->Instance, pConfig->Rank, tmp_channel);
+ }
+ }
+
+ /* Set sampling time of the selected ADC channel */
+ LL_ADC_SetChannelSamplingTime(hadc->Instance, tmp_channel, pConfig->SamplingTime);
+
+
+ /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */
+ /* internal measurement paths enable: If internal channel selected, */
+ /* enable dedicated internal buffers and path. */
+ /* Note: these internal measurement paths can be disabled using */
+ /* HAL_ADC_DeInit() or removing the channel from sequencer with */
+ /* channel configuration parameter "Rank". */
+ if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel))
+ {
+ tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+
+ /* If the requested internal measurement path has already been enabled, */
+ /* bypass the configuration processing. */
+ if ((pConfig->Channel == ADC4_CHANNEL_TEMPSENSOR) \
+ && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+ LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
+
+ /* Delay for temperature sensor stabilization time */
+ /* Wait loop initialization and execution */
+ /* Note: Variable divided by 2 to compensate partially */
+ /* CPU processing cycles, scaling in us split to not */
+ /* exceed 32 bits register capacity and handle low frequency. */
+ wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
+ while (wait_loop_index != 0UL)
+ {
+ wait_loop_index--;
+ }
+ }
+ else if ((pConfig->Channel == ADC4_CHANNEL_VBAT) && ((tmp_config_internal_channel \
+ & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+ LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
+ }
+ else if ((pConfig->Channel == ADC_CHANNEL_VREFINT) \
+ && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+ LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
+ }
+ else if ((pConfig->Channel == ADC_CHANNEL_VCORE) \
+ && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
+ {
+ if (ADC_VCORE_INSTANCE(hadc))
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+ LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
+ if (HAL_GetREVID() <= REV_ID_A) /* STM32U5 silicon Rev.A */
+ {
+ SET_BIT((hadc->Instance->OR), ADC_OR_CHN0SEL);
+ }
+ }
+ }
+ else
+ {
+ /* nothing to do */
+ }
+ /* If STM32U5 silicon Rev.B, ADC_CHANNEL_DAC1CH1 and ADC_CHANNEL_DAC1CH2 are both on Channel 21
+ and selection is done via ADC_OR[0] register */
+ if (HAL_GetREVID() == REV_ID_B) /* STM32U5 silicon Rev.B */
+ {
+ if ((pConfig->Channel == ADC_CHANNEL_DAC1CH2_ADC4) \
+ && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
+ {
+ SET_BIT((hadc->Instance->OR), ADC_OR_CHN0SEL);
+ }
+ }
+ }
+ }
+ else
+ {
+ /* Regular sequencer configuration */
+ /* Note: Case of sequencer set to fully configurable: */
+ /* Sequencer rank cannot be disabled, only affected to */
+ /* another channel. */
+ /* To remove a rank, use parameter 'NbrOfConversion". */
+ if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) ||
+ (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD))
+ {
+ /* Sequencer set to not fully configurable: */
+ /* Reset the channel by disabling the corresponding bitfield. */
+ LL_ADC_REG_SetSequencerChRem(hadc->Instance, tmp_channel);
+ }
+
+ /* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */
+ /* If internal channel selected, enable dedicated internal buffers and */
+ /* paths. */
+ if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel))
+ {
+ tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+
+ if (pConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+ ~LL_ADC_PATH_INTERNAL_TEMPSENSOR & tmp_config_internal_channel);
+ }
+ else if (pConfig->Channel == ADC_CHANNEL_VBAT)
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+ ~LL_ADC_PATH_INTERNAL_VBAT & tmp_config_internal_channel);
+ }
+ else if (pConfig->Channel == ADC_CHANNEL_VREFINT)
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+ ~LL_ADC_PATH_INTERNAL_VREFINT & tmp_config_internal_channel);
+ }
+ else if (pConfig->Channel == ADC_CHANNEL_VCORE)
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+ ~LL_ADC_PATH_INTERNAL_VREFINT & tmp_config_internal_channel);
+ if (HAL_GetREVID() <= REV_ID_A) /* STM32U5 silicon Rev.A */
+ {
+ SET_BIT((hadc->Instance->OR), ADC_OR_CHN0SEL);
+ }
+ }
+ else
+ {
+ /* nothing to do */
+ }
+ /* If STM32U5 silicon Rev.B, ADC_CHANNEL_DAC1CH1 and ADC_CHANNEL_DAC1CH2 are both on Channel 21
+ and selection is done via ADC_OR[0] register */
+ if (HAL_GetREVID() == REV_ID_B) /* STM32U5 silicon Rev.B */
+ {
+ if ((pConfig->Channel == ADC_CHANNEL_DAC1CH2_ADC4) \
+ && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
+ {
+ SET_BIT((hadc->Instance->OR), ADC_OR_CHN0SEL);
+ }
+ }
+ }
+ }
+ }
+ }
+
+ /* If a conversion is on going on regular group, no update on regular */
+ /* channel could be done on neither of the channel configuration structure */
+ /* parameters. */
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ __HAL_UNLOCK(hadc);
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Configure the analog watchdog.
+ * @note Possibility to update parameters on the fly:
+ * This function initializes the selected analog watchdog, successive
+ * calls to this function can be used to reconfigure some parameters
+ * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting
+ * the ADC.
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_AnalogWDGConfTypeDef".
+ * @param hadc ADC handle
+ * @param pAnalogWDGConfig Structure of ADC analog watchdog configuration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ uint32_t tmp_awd_high_threshold_shifted;
+ uint32_t tmp_awd_low_threshold_shifted;
+ uint32_t tmp_adc_is_conversion_on_going_regular;
+ uint32_t tmp_adc_is_conversion_on_going_injected;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(pAnalogWDGConfig->WatchdogNumber));
+ assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(pAnalogWDGConfig->WatchdogMode));
+ assert_param(IS_FUNCTIONAL_STATE(pAnalogWDGConfig->ITMode));
+
+ if ((pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) ||
+ (pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) ||
+ (pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC))
+ {
+ assert_param(IS_ADC_CHANNEL(pAnalogWDGConfig->Channel));
+ }
+
+ /* Verify thresholds range */
+ if (hadc->Init.OversamplingMode == ENABLE)
+ {
+ /* Case of oversampling enabled: thresholds are compared to oversampling
+ intermediate computation (after ratio, before shift application) */
+ assert_param(IS_ADC_RANGE(hadc->Instance, ADC_GET_RESOLUTION(hadc),
+ pAnalogWDGConfig->HighThreshold / (hadc->Init.Oversampling.Ratio + 1UL)));
+ assert_param(IS_ADC_RANGE(hadc->Instance, ADC_GET_RESOLUTION(hadc),
+ pAnalogWDGConfig->LowThreshold / (hadc->Init.Oversampling.Ratio + 1UL)));
+ }
+ else
+ {
+ /* Verify if thresholds are within the selected ADC resolution */
+ assert_param(IS_ADC_RANGE(hadc->Instance, ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->HighThreshold));
+ assert_param(IS_ADC_RANGE(hadc->Instance, ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->LowThreshold));
+ }
+
+ __HAL_LOCK(hadc);
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on ADC groups regular and injected: */
+ /* - Analog watchdog channels */
+ /* - Analog watchdog thresholds */
+ if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
+ {
+ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+ tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+ }
+ else
+ {
+ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+ tmp_adc_is_conversion_on_going_injected = 0UL; /* No injected channels for ADC4 so force \
+ tmp_adc_is_conversion_on_going_injected to 0 */
+ }
+ if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+ && (tmp_adc_is_conversion_on_going_injected == 0UL)
+ )
+ {
+ /* Analog watchdog configuration */
+ if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
+ {
+ /* Configuration of analog watchdog: */
+ /* - Set the analog watchdog enable mode: one or overall group of */
+ /* channels, on groups regular and-or injected. */
+ switch (pAnalogWDGConfig->WatchdogMode)
+ {
+ case ADC_ANALOGWATCHDOG_SINGLE_REG:
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
+ __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel,
+ LL_ADC_GROUP_REGULAR));
+ break;
+
+ case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
+ __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel,
+ LL_ADC_GROUP_INJECTED));
+ break;
+
+ case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
+ __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel,
+ LL_ADC_GROUP_REGULAR_INJECTED));
+ break;
+
+ case ADC_ANALOGWATCHDOG_ALL_REG:
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG);
+ break;
+
+ case ADC_ANALOGWATCHDOG_ALL_INJEC:
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_INJ);
+ break;
+
+ case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
+ break;
+
+ default: /* ADC_ANALOGWATCHDOG_NONE */
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_DISABLE);
+ break;
+ }
+
+ if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
+ {
+ /* Set the filtering configuration */
+ assert_param(IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(pAnalogWDGConfig->FilteringConfig));
+ LL_ADC_SetAWDFilteringConfiguration(hadc->Instance, hadc->Instance->HTR1, pAnalogWDGConfig->FilteringConfig);
+ }
+
+ /* Shift the offset in function of the selected ADC resolution: */
+ /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */
+ /* are set to 0 */
+ tmp_awd_high_threshold_shifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->HighThreshold);
+ tmp_awd_low_threshold_shifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->LowThreshold);
+
+ /* Set ADC analog watchdog thresholds value of both thresholds high and low */
+ LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, tmp_awd_high_threshold_shifted,
+ tmp_awd_low_threshold_shifted);
+
+ /* Update state, clear previous result related to AWD1 */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+
+ /* Clear flag ADC analog watchdog */
+ /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
+ /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
+ /* (in case left enabled by previous ADC operations). */
+ LL_ADC_ClearFlag_AWD1(hadc->Instance);
+
+ /* Configure ADC analog watchdog interrupt */
+ if (pAnalogWDGConfig->ITMode == ENABLE)
+ {
+ LL_ADC_EnableIT_AWD1(hadc->Instance);
+ }
+ else
+ {
+ LL_ADC_DisableIT_AWD1(hadc->Instance);
+ }
+ }
+ /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */
+ else
+ {
+ switch (pAnalogWDGConfig->WatchdogMode)
+ {
+ case ADC_ANALOGWATCHDOG_SINGLE_REG:
+ case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
+ case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
+ /* Update AWD by bitfield to keep the possibility to monitor */
+ /* several channels by successive calls of this function. */
+ if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
+ {
+ SET_BIT(hadc->Instance->AWD2CR, (1UL \
+ << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel) & 0x1FUL)));
+ }
+ else
+ {
+ SET_BIT(hadc->Instance->AWD3CR, (1UL \
+ << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel) & 0x1FUL)));
+ }
+ break;
+
+ case ADC_ANALOGWATCHDOG_ALL_REG:
+ case ADC_ANALOGWATCHDOG_ALL_INJEC:
+ case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, \
+ LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
+ break;
+
+ default: /* ADC_ANALOGWATCHDOG_NONE */
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE);
+ break;
+ }
+
+ /* Shift the thresholds in function of the selected ADC resolution */
+ /* have to be left-aligned on bit 15, the LSB (right bits) are set to 0 */
+ tmp_awd_high_threshold_shifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->HighThreshold);
+ tmp_awd_low_threshold_shifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->LowThreshold);
+
+ if (hadc->Instance == ADC4)
+ {
+ /* Set ADC analog watchdog thresholds value of both thresholds high and low */
+ LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, pAnalogWDGConfig->WatchdogNumber,
+ tmp_awd_high_threshold_shifted,
+ tmp_awd_low_threshold_shifted);
+ }
+ else /* ADC1 or ADC2 */
+ {
+ if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
+ {
+ /* Set ADC analog watchdog thresholds value of both thresholds high and low */
+ MODIFY_REG(hadc->Instance->LTR2, ADC_LTR_LT, tmp_awd_low_threshold_shifted);
+ MODIFY_REG(hadc->Instance->HTR2, ADC_HTR_HT, tmp_awd_high_threshold_shifted);
+ }
+ else
+ {
+ /* Set ADC analog watchdog thresholds value of both thresholds high and low */
+ MODIFY_REG(hadc->Instance->LTR3, ADC_LTR_LT, tmp_awd_low_threshold_shifted);
+ MODIFY_REG(hadc->Instance->HTR3, ADC_HTR_HT, tmp_awd_high_threshold_shifted);
+ }
+ }
+
+ if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
+ {
+ /* Update state, clear previous result related to AWD2 */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2);
+
+ /* Clear flag ADC analog watchdog */
+ /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
+ /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
+ /* (in case left enabled by previous ADC operations). */
+ LL_ADC_ClearFlag_AWD2(hadc->Instance);
+
+ /* Configure ADC analog watchdog interrupt */
+ if (pAnalogWDGConfig->ITMode == ENABLE)
+ {
+ LL_ADC_EnableIT_AWD2(hadc->Instance);
+ }
+ else
+ {
+ LL_ADC_DisableIT_AWD2(hadc->Instance);
+ }
+ }
+ /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
+ else
+ {
+ /* Update state, clear previous result related to AWD3 */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3);
+
+ /* Clear flag ADC analog watchdog */
+ /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
+ /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
+ /* (in case left enabled by previous ADC operations). */
+ LL_ADC_ClearFlag_AWD3(hadc->Instance);
+
+ /* Configure ADC analog watchdog interrupt */
+ if (pAnalogWDGConfig->ITMode == ENABLE)
+ {
+ LL_ADC_EnableIT_AWD3(hadc->Instance);
+ }
+ else
+ {
+ LL_ADC_DisableIT_AWD3(hadc->Instance);
+ }
+ }
+ }
+
+ }
+ /* If a conversion is on going on ADC group regular or injected, no update */
+ /* could be done on neither of the AWD configuration structure parameters. */
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+ __HAL_UNLOCK(hadc);
+
+ return tmp_hal_status;
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
+ * @brief ADC Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral state and errors functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions to get in run-time the status of the
+ peripheral.
+ (+) Check the ADC state
+ (+) Check the ADC error code
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the ADC handle state.
+ * @note ADC state machine is managed by bitfields, ADC status must be
+ * compared with states bits.
+ * For example:
+ * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
+ * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
+ * @param hadc ADC handle
+ * @retval ADC handle state (bitfield on 32 bits)
+ */
+uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Return ADC handle state */
+ return hadc->State;
+}
+
+/**
+ * @brief Return the ADC error code.
+ * @param hadc ADC handle
+ * @retval ADC error code (bitfield on 32 bits)
+ */
+uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ return hadc->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Private_Functions ADC Private Functions
+ * @{
+ */
+
+/**
+ * @brief Stop ADC conversion.
+ * @param hadc ADC handle
+ * @param ConversionGroup ADC group regular and/or injected.
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_REGULAR_GROUP ADC regular conversion type.
+ * @arg @ref ADC_INJECTED_GROUP ADC injected conversion type.
+ * @arg @ref ADC_REGULAR_INJECTED_GROUP ADC regular and injected conversion type.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
+{
+ uint32_t tickstart;
+ uint32_t conversion_timeout_cpu_cycles = 0UL;
+ uint32_t conversion_group_reassigned = ConversionGroup;
+ uint32_t tmp_adc_cr_adstart_jadstart;
+ uint32_t tmp_adc_is_conversion_on_going_regular;
+ uint32_t tmp_adc_is_conversion_on_going_injected;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
+
+ /* Verification if ADC is not already stopped (on regular and injected */
+ /* groups) to bypass this function if not needed. */
+ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+ tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+ if ((tmp_adc_is_conversion_on_going_regular != 0UL) || (tmp_adc_is_conversion_on_going_injected != 0UL))
+ {
+ /* Particular case of continuous auto-injection mode combined with */
+ /* auto-delay mode. */
+ /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not */
+ /* injected group stop ADC_CR_JADSTP). */
+ /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1 */
+ /* (see reference manual). */
+ if (((hadc->Instance->CFGR1 & ADC_CFGR1_JAUTO) != 0UL)
+ && (hadc->Init.ContinuousConvMode == ENABLE)
+ && (hadc->Init.LowPowerAutoWait == ENABLE)
+ )
+ {
+ /* Use stop of regular group */
+ conversion_group_reassigned = ADC_REGULAR_GROUP;
+
+ /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
+ while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL)
+ {
+ if (conversion_timeout_cpu_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES * 4UL))
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+ conversion_timeout_cpu_cycles++;
+ }
+
+ /* Clear JEOS */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
+ }
+
+ /* Stop potential conversion on going on ADC group regular */
+ if (conversion_group_reassigned != ADC_INJECTED_GROUP)
+ {
+ /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
+ {
+ if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
+ {
+ /* Stop ADC group regular conversion */
+ LL_ADC_REG_StopConversion(hadc->Instance);
+ }
+ }
+ }
+
+ /* Stop potential conversion on going on ADC group injected */
+ if (conversion_group_reassigned != ADC_REGULAR_GROUP)
+ {
+ /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
+ {
+ if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
+ {
+ /* Stop ADC group injected conversion */
+ LL_ADC_INJ_StopConversion(hadc->Instance);
+ }
+ }
+ }
+
+ /* Selection of start and stop bits with respect to the regular or injected group */
+ switch (conversion_group_reassigned)
+ {
+ case ADC_REGULAR_INJECTED_GROUP:
+ tmp_adc_cr_adstart_jadstart = (ADC_CR_ADSTART | ADC_CR_JADSTART);
+ break;
+ case ADC_INJECTED_GROUP:
+ tmp_adc_cr_adstart_jadstart = ADC_CR_JADSTART;
+ break;
+ /* Case ADC_REGULAR_GROUP only*/
+ default:
+ tmp_adc_cr_adstart_jadstart = ADC_CR_ADSTART;
+ break;
+ }
+
+ /* Wait for conversion effectively stopped */
+ tickstart = HAL_GetTick();
+
+ while ((hadc->Instance->CR & tmp_adc_cr_adstart_jadstart) != 0UL)
+ {
+ if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
+ {
+ /* New check to avoid false timeout detection in case of preemption */
+ if ((hadc->Instance->CR & tmp_adc_cr_adstart_jadstart) != 0UL)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable the selected ADC.
+ * @note Prerequisite condition to use this function: ADC must be disabled
+ * and voltage regulator must be enabled (done into HAL_ADC_Init()).
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
+{
+ uint32_t tickstart;
+
+ /* ADC enable and wait for ADC ready (in case of ADC is disabled or */
+ /* enabling phase not yet completed: flag ADC ready not yet set). */
+ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
+ /* causes: ADC clock not running, ...). */
+ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ {
+ /* Check if conditions to enable the ADC are fulfilled */
+ if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
+ | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+
+ LL_ADC_Enable(hadc->Instance);
+
+ /* If low power mode AutoPowerOff is enabled, power-on/off phases are */
+ /* performed automatically by hardware and flag ADC ready is not set. */
+ if ((hadc->Init.LowPowerAutoPowerOff == ADC_LOW_POWER_NONE) || (hadc->Instance != ADC4))
+ {
+ /* Wait for ADC effectively enabled */
+ tickstart = HAL_GetTick();
+ /* Poll for ADC ready flag raised except case of multimode enabled
+ and ADC slave selected. */
+ while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
+ {
+ /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit
+ has been cleared (after a calibration), ADEN bit is reset by the
+ calibration logic.
+ The workaround is to continue setting ADEN until ADRDY is becomes 1.
+ Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
+ 4 ADC clock cycle duration */
+ /* Note: Test of ADC enabled required due to hardware constraint to */
+ /* not enable ADC if already enabled. */
+ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ {
+ LL_ADC_Enable(hadc->Instance);
+ }
+
+ if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
+ {
+ /* New check to avoid false timeout detection in case of preemption */
+ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the selected ADC.
+ * @note Prerequisite condition to use this function: ADC conversions must be
+ * stopped.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc)
+{
+ uint32_t tickstart;
+ const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance);
+
+ /* Verification if ADC is not already disabled: */
+ /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
+ /* disabled. */
+ if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
+ && (tmp_adc_is_disable_on_going == 0UL)
+ )
+ {
+ /* Check if conditions to disable the ADC are fulfilled */
+ if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN)
+ {
+ /* Disable the ADC peripheral */
+ LL_ADC_Disable(hadc->Instance);
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY));
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+
+ /* Wait for ADC effectively disabled */
+ /* Get tick count */
+ tickstart = HAL_GetTick();
+
+ while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
+ {
+ if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
+ {
+ /* New check to avoid false timeout detection in case of preemption */
+ if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DMA transfer complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Retrieve ADC handle corresponding to current DMA handle */
+ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Update state machine on conversion status if not in error state */
+ if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL)
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going */
+ /* to disable interruption. */
+ /* Is it the end of the regular sequence ? */
+ if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL)
+ {
+ /* Are conversions software-triggered ? */
+ if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
+ {
+ /* Is CONT bit set ? */
+ if (READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_CONT) == 0UL)
+ {
+ /* CONT bit is not set, no more conversions expected */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+ }
+ }
+ else
+ {
+ /* DMA End of Transfer interrupt was triggered but conversions sequence
+ is not over. If DMACFG is set to 0, conversions are stopped. */
+ if (READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMNGT) == 0UL)
+ {
+ /* DMACFG bit is not set, conversions are stopped. */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+ }
+
+ /* Conversion complete callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ConvCpltCallback(hadc);
+#else
+ HAL_ADC_ConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ }
+ else /* DMA and-or internal error occurred */
+ {
+ if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL)
+ {
+ /* Call HAL ADC Error Callback function */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ErrorCallback(hadc);
+#else
+ HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Call ADC DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback(hdma);
+ }
+ }
+}
+
+/**
+ * @brief DMA half transfer complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Retrieve ADC handle corresponding to current DMA handle */
+ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Half conversion callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ConvHalfCpltCallback(hadc);
+#else
+ HAL_ADC_ConvHalfCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA error callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void ADC_DMAError(DMA_HandleTypeDef *hdma)
+{
+ /* Retrieve ADC handle corresponding to current DMA handle */
+ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+
+ /* Set ADC error code to DMA error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
+
+ /* Error callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ErrorCallback(hadc);
+#else
+ HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_ADC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_adc_ex.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_adc_ex.c
new file mode 100644
index 00000000..071dcd4b
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_adc_ex.c
@@ -0,0 +1,2387 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_adc_ex.c
+ * @author MCD Application Team
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Analog to Digital Converter (ADC)
+ * peripheral:
+ * + Operation functions
+ * ++ Start, stop, get result of conversions of ADC group injected,
+ * using 2 possible modes: polling, interruption.
+ * ++ Calibration
+ * +++ ADC automatic self-calibration
+ * +++ Calibration factors get or set
+ * ++ Multimode feature when available
+ * + Control functions
+ * ++ Channels configuration on ADC group injected
+ * + State functions
+ * ++ ADC group injected contexts queue management
+ * Other functions (generic functions) are available in file
+ * "stm32u5xx_hal_adc.c".
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ [..]
+ (@) Sections "ADC peripheral features" and "How to use this driver" are
+ available in file of generic functions "stm32u5xx_hal_adc.c".
+ [..]
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup ADCEx ADCEx
+ * @brief ADC Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup ADCEx_Private_Constants ADC Extended Private Constants
+ * @{
+ */
+
+#define ADC_JSQR_FIELDS ((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\
+ ADC_JSQR_JSQ1 | ADC_JSQR_JSQ2 |\
+ ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime
+once the ADC is enabled */
+
+/* Fixed timeout value for ADC calibration. */
+/* Values defined to be higher than worst cases: low clock frequency, */
+/* maximum prescalers. */
+/* Ex of profile low frequency : f_ADC at 4,577 Khz (minimum value */
+/* according to Data sheet), calibration_time MAX = 16384 / f_ADC */
+/* 16384 / 4577.63671875 = 3.58s */
+/* At maximum CPU speed (400 MHz), this means */
+/* 3.58 * 400 MHz = 1432000000 CPU cycles */
+#define ADC_CALIBRATION_TIMEOUT (1432000000U) /*!< ADC calibration time-out value */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
+ * @brief Extended IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+
+ (+) Perform the ADC self-calibration for single or differential ending.
+ (+) Get calibration factors for single or differential ending.
+ (+) Set calibration factors for single or differential ending.
+
+ (+) Start conversion of ADC group injected.
+ (+) Stop conversion of ADC group injected.
+ (+) Poll for conversion complete on ADC group injected.
+ (+) Get result of ADC group injected channel conversion.
+ (+) Start conversion of ADC group injected and enable interruptions.
+ (+) Stop conversion of ADC group injected and disable interruptions.
+
+ (+) When multimode feature is available, start multimode and enable DMA transfer.
+ (+) Stop multimode and disable ADC DMA transfer.
+ (+) Get result of multimode conversion.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Perform an ADC automatic self-calibration
+ * Calibration prerequisite: ADC must be disabled (execute this
+ * function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
+ * @param hadc ADC handle
+ * @param CalibrationMode Selection of calibration offset or
+ * linear calibration offset.
+ * @arg ADC_CALIB_OFFSET Channel in mode calibration offset
+ * @arg ADC_CALIB_OFFSET_LINEARITY Channel in mode linear calibration offset
+ * @param SingleDiff Selection of single-ended or differential input
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
+ * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+ __IO uint32_t wait_loop_index = 0UL;
+
+ UNUSED(SingleDiff); /* STM32U5 calibration is not making difference between Single and Diff ended */
+ /* We keep this to be inligne with old products API and for any further use */
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
+
+ __HAL_LOCK(hadc);
+
+ /* Calibration prerequisite: ADC must be disabled. */
+
+ /* Disable the ADC (if not already disabled) */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_BUSY_INTERNAL);
+
+ /* Start ADC calibration in mode single-ended or differential */
+ LL_ADC_StartCalibration(hadc->Instance, CalibrationMode);
+
+ /* Wait for calibration completion */
+ while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
+ {
+ wait_loop_index++;
+ if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
+ }
+ else
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Note: No need to update variable "tmp_hal_status" here: already set */
+ /* to state "HAL_ERROR" by function disabling the ADC. */
+ }
+
+ __HAL_UNLOCK(hadc);
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Get the calibration factor.
+ * @param hadc ADC handle.
+ * @param SingleDiff This parameter can be only:
+ * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
+ * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
+ * @retval Calibration value.
+ */
+uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
+{
+ uint32_t Calib_Val = 0UL;
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
+
+ if (hadc->Instance != ADC4)
+ {
+ tmp_hal_status = ADC_Enable(hadc); /* ADC need to be enabled to performe calibration for ADC1/2 and not for ADC4 */
+ }
+
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Return the selected ADC calibration value */
+ Calib_Val = LL_ADC_GetCalibrationOffsetFactor(hadc->Instance, SingleDiff);
+ }
+
+ if (hadc->Instance != ADC4)
+ {
+ tmp_hal_status = ADC_Disable(hadc);
+ UNUSED(tmp_hal_status);
+ }
+ return Calib_Val;
+}
+
+/**
+ * @brief Get the calibration factor from automatic conversion result
+ * @param hadc ADC handle
+ * @param pLinearCalib_Buffer: Linear calibration factor
+ * @retval HAL state
+ */
+HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t *pLinearCalib_Buffer)
+{
+ uint32_t cnt;
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Enable the ADC ADEN = 1 to be able to read the linear calibration factor */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ if (tmp_hal_status == HAL_OK)
+ {
+ SET_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CAPTURE_COEF);
+ CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_LATCH_COEF);
+ for (cnt = 0UL; cnt <= 8UL; cnt++)
+ {
+ MODIFY_REG(hadc->Instance->CR,
+ (ADC_CR_CALINDEX3 | ADC_CR_CALINDEX2 | ADC_CR_CALINDEX1 | ADC_CR_CALINDEX0),
+ (cnt << ADC_CR_CALINDEX0_Pos)); /* LinearityWord == CalibIndex (1 to 8 for linearity reading)*/
+ pLinearCalib_Buffer[cnt] = (uint32_t)(READ_BIT(hadc->Instance->CALFACT2, ADC_CALFACT2_CALFACT_Msk));
+ }
+ }
+ CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CAPTURE_COEF);
+ tmp_hal_status = ADC_Disable(hadc);
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Set the calibration factor to overwrite automatic conversion result.
+ * ADC must be enabled and no conversion is ongoing.
+ * @param hadc ADC handle
+ * @param SingleDiff This parameter can be only:
+ * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
+ * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
+ * @param CalibrationFactor Calibration factor (coded on 7 bits maximum)
+ * @retval HAL state
+ */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff,
+ uint32_t CalibrationFactor)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ uint32_t tmp_adc_is_conversion_on_going_regular;
+ uint32_t tmp_adc_is_conversion_on_going_injected;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
+ assert_param(IS_ADC_CALFACT(CalibrationFactor));
+
+ __HAL_LOCK(hadc);
+
+ /* Verification of hardware constraints before modifying the calibration */
+ /* factors register: ADC must be enabled, no conversion on going. */
+ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+ tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+
+ if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
+ && (tmp_adc_is_conversion_on_going_regular == 0UL)
+ && (tmp_adc_is_conversion_on_going_injected == 0UL)
+ )
+ {
+ /* Set the selected ADC calibration value */
+ LL_ADC_SetCalibrationOffsetFactor(hadc->Instance, SingleDiff, CalibrationFactor);
+ }
+ else
+ {
+ /* Update ADC state machine */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ /* Update ADC error code */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ /* Update ADC state machine to error */
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ __HAL_UNLOCK(hadc);
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Set the linear calibration factor
+ * @param hadc ADC handle
+ * @param pLinearCalib_Buffer: Linear calibration factor
+ * @retval HAL state
+ */
+HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t *pLinearCalib_Buffer)
+{
+ uint32_t cnt;
+ __IO uint32_t wait_loop_index;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* - Exit from deep-power-down mode and ADC voltage regulator enable */
+ /* Exit deep power down mode if still in that state */
+ if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_DEEPPWD))
+ {
+ /* Exit deep power down mode */
+ CLEAR_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
+
+ /* System was in deep power down mode, calibration must
+ be relaunched or a previously saved calibration factor
+ re-applied once the ADC voltage regulator is enabled */
+ }
+
+ if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
+ {
+ /* Enable ADC internal voltage regulator */
+ SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN);
+ /* Delay for ADC stabilization time */
+ /* Wait loop initialization and execution */
+ /* Note: Variable divided by 2 to compensate partially */
+ /* CPU processing cycles. */
+ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / (1000000UL * 2UL)));
+ while (wait_loop_index != 0UL)
+ {
+ wait_loop_index--;
+ }
+ }
+
+ /* Verification that ADC voltage regulator is correctly enabled, whether */
+ /* or not ADC is coming from state reset (if any potential problem of */
+ /* clocking, voltage regulator would not be enabled). */
+ if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+ if (ADC_Enable(hadc) == HAL_OK)
+ {
+ /* We need to wait till ADC_ISR_ADRDY flag go up to set calibration values. */
+ /* However this is already done by ADC_Enable(). */
+ /* Therefore a simple check of the flag could help to ensure ADC is ready. */
+ if ((hadc->Instance->ISR & ADC_ISR_ADRDY) == 0UL)
+ {
+ return HAL_ERROR;
+ }
+
+ CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_LATCH_COEF | ADC_CALFACT_CAPTURE_COEF);
+ for (cnt = 0UL; cnt <= 8UL; cnt++)
+ {
+ MODIFY_REG(hadc->Instance->CR,
+ (ADC_CR_CALINDEX3 | ADC_CR_CALINDEX2 | ADC_CR_CALINDEX1 | ADC_CR_CALINDEX0),
+ (cnt << ADC_CR_CALINDEX0_Pos)); /* LinearityWord == CalibIndex (1 to 8 for linearity reading)*/
+ MODIFY_REG(hadc->Instance->CALFACT2, ADC_CALFACT2_CALFACT, pLinearCalib_Buffer[cnt]);
+ }
+ }
+ SET_BIT(hadc->Instance->CALFACT, ADC_CALFACT_LATCH_COEF);
+ CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CAPTURE_COEF);
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable ADC, start conversion of injected group.
+ * @note Interruptions enabled in this function: None.
+ * @note Case of multimode enabled when multimode feature is available:
+ * HAL_ADCEx_InjectedStart() API must be called for ADC slave first,
+ * then for ADC master.
+ * For ADC slave, ADC is enabled only (conversion is not started).
+ * For ADC master, ADC is enabled and multimode conversion is started.
+ * @param hadc ADC handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+#if defined(ADC_MULTIMODE_SUPPORT)
+ uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
+ {
+ tmp_hal_status = HAL_BUSY;
+ }
+ else
+ {
+ /* In case of software trigger detection enabled, JQDIS must be set
+ (which can be done only if ADSTART and JADSTART are both cleared).
+ If JQDIS is not set at that point, returns an error
+ - since software trigger detection is disabled. User needs to
+ resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
+ - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
+ the queue is empty */
+
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Check if a regular conversion is ongoing */
+ if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL)
+ {
+ /* Reset ADC error code field related to injected conversions only */
+ CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
+ }
+ else
+ {
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Set ADC state */
+ /* - Clear state bitfield related to injected group conversion results */
+ /* - Set state bitfield related to injected operation */
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+ /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+ - if ADC instance is master or if multimode feature is not available
+ - if multimode setting is disabled (ADC instance slave in independent mode) */
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+ || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ )
+ {
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Clear ADC group injected group conversion flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
+
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Enable conversion of injected group, if automatic injected conversion */
+ /* is disabled. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* Case of multimode enabled (when multimode feature is available): */
+ /* if ADC is slave, */
+ /* - ADC is enabled only (conversion is not started), */
+ /* - if multimode only concerns regular conversion, ADC is enabled */
+ /* and conversion is started. */
+ /* If ADC is master or independent, */
+ /* - ADC is enabled and conversion is started. */
+#if defined(ADC_MULTIMODE_SUPPORT)
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+ || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
+ )
+ {
+ /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
+ if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
+ {
+ LL_ADC_INJ_StartConversion(hadc->Instance);
+ }
+ }
+ else
+ {
+ /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
+ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ }
+#else
+ if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
+ {
+ LL_ADC_INJ_StartConversion(hadc->Instance);
+ }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ }
+ else
+ {
+ __HAL_UNLOCK(hadc);
+ }
+ }
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Stop conversion of injected channels. Disable ADC peripheral if
+ * no regular conversion is on going.
+ * @note If ADC must be disabled and if conversion is on going on
+ * regular group, function HAL_ADC_Stop must be used to stop both
+ * injected and regular groups, and disable the ADC.
+ * @note If injected group mode auto-injection is enabled,
+ * function HAL_ADC_Stop must be used.
+ * @note In case of multimode enabled (when multimode feature is available),
+ * HAL_ADCEx_InjectedStop() must be called for ADC master first, then for ADC slave.
+ * For ADC master, conversion is stopped and ADC is disabled.
+ * For ADC slave, ADC is disabled only (conversion stop of ADC master
+ * has already stopped conversion of ADC slave).
+ * @param hadc ADC handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential conversion on going on injected group only. */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if injected conversions are effectively stopped */
+ /* and if no conversion on regular group is on-going */
+ if (tmp_hal_status == HAL_OK)
+ {
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* 2. Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
+ }
+ }
+ /* Conversion on injected group is stopped, but ADC not disabled since */
+ /* conversion on regular group is still running. */
+ else
+ {
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+ }
+ }
+
+ __HAL_UNLOCK(hadc);
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Wait for injected group conversion to be completed.
+ * @param hadc ADC handle
+ * @param Timeout Timeout value in millisecond.
+ * @note Depending on hadc->Init.EOCSelection, JEOS or JEOC is
+ * checked and cleared depending on AUTDLY bit status.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
+{
+ uint32_t tickstart;
+ uint32_t tmp_flag_end;
+ uint32_t tmp_adc_inj_is_trigger_source_sw_start;
+ uint32_t tmp_adc_reg_is_trigger_source_sw_start;
+ uint32_t tmp_cfgr;
+#if defined(ADC_MULTIMODE_SUPPORT)
+ const ADC_TypeDef *tmp_adc_master;
+ uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* If end of sequence selected */
+ if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
+ {
+ tmp_flag_end = ADC_FLAG_JEOS;
+ }
+ else /* end of conversion selected */
+ {
+ tmp_flag_end = ADC_FLAG_JEOC;
+ }
+
+ tickstart = HAL_GetTick();
+
+ /* Wait until End of Conversion or Sequence flag is raised */
+ while ((hadc->Instance->ISR & tmp_flag_end) == 0UL)
+ {
+ /* Check if timeout is disabled (set to infinite wait) */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
+ {
+ if ((hadc->Instance->ISR & tmp_flag_end) == 0UL)
+ {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Retrieve ADC configuration */
+ tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance);
+ tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
+ /* Get relevant register CFGR in ADC instance of ADC master or slave */
+ /* in function of multimode state (for devices with multimode */
+ /* available). */
+#if defined(ADC_MULTIMODE_SUPPORT)
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+ || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
+ )
+ {
+ tmp_cfgr = READ_REG(hadc->Instance->CFGR1);
+ }
+ else
+ {
+ tmp_adc_master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+ tmp_cfgr = READ_REG(tmp_adc_master->CFGR1);
+ }
+#else
+ tmp_cfgr = READ_REG(hadc->Instance->CFGR1);
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Update ADC state machine */
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
+
+ /* Determine whether any further conversion upcoming on group injected */
+ /* by external trigger or by automatic injected conversion */
+ /* from group regular. */
+ if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL) ||
+ ((READ_BIT(tmp_cfgr, ADC_CFGR1_JAUTO) == 0UL) &&
+ ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
+ (READ_BIT(tmp_cfgr, ADC_CFGR1_CONT) == 0UL))))
+ {
+ /* Check whether end of sequence is reached */
+ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
+ {
+ /* Particular case if injected contexts queue is enabled: */
+ /* when the last context has been fully processed, JSQR is reset */
+ /* by the hardware. Even if no injected conversion is planned to come */
+ /* (queue empty, triggers are ignored), it can start again */
+ /* immediately after setting a new context (JADSTART is still set). */
+ /* Therefore, state of HAL ADC injected group is kept to busy. */
+
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+
+ if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+ }
+
+ /* Clear polled flag */
+ if (tmp_flag_end == ADC_FLAG_JEOS)
+ {
+ /* Clear end of sequence JEOS flag of injected group if low power feature */
+ /* "LowPowerAutoWait " is disabled, to not interfere with this feature. */
+ /* For injected groups, no new conversion will start before JEOS is */
+ /* cleared. */
+ if (READ_BIT(tmp_cfgr, ADC_CFGR1_AUTDLY) == 0UL)
+ {
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
+ }
+ }
+ else
+ {
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable ADC, start conversion of injected group with interruption.
+ * @note Interruptions enabled in this function according to initialization
+ * setting : JEOC (end of conversion) or JEOS (end of sequence)
+ * @note Case of multimode enabled (when multimode feature is enabled):
+ * HAL_ADCEx_InjectedStart_IT() API must be called for ADC slave first,
+ * then for ADC master.
+ * For ADC slave, ADC is enabled only (conversion is not started).
+ * For ADC master, ADC is enabled and multimode conversion is started.
+ * @param hadc ADC handle.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+#if defined(ADC_MULTIMODE_SUPPORT)
+ uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
+ {
+ tmp_hal_status = HAL_BUSY;
+ }
+ else
+ {
+ /* In case of software trigger detection enabled, JQDIS must be set
+ (which can be done only if ADSTART and JADSTART are both cleared).
+ If JQDIS is not set at that point, returns an error
+ - since software trigger detection is disabled. User needs to
+ resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
+ - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
+ the queue is empty */
+
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Check if a regular conversion is ongoing */
+ if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL)
+ {
+ /* Reset ADC error code field related to injected conversions only */
+ CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
+ }
+ else
+ {
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Set ADC state */
+ /* - Clear state bitfield related to injected group conversion results */
+ /* - Set state bitfield related to injected operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
+ HAL_ADC_STATE_INJ_BUSY);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+ /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+ - if ADC instance is master or if multimode feature is not available
+ - if multimode setting is disabled (ADC instance slave in independent mode) */
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+ || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ )
+ {
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Clear ADC group injected group conversion flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
+
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Enable ADC end of conversion interrupt */
+ switch (hadc->Init.EOCSelection)
+ {
+ case ADC_EOC_SEQ_CONV:
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
+ break;
+ /* case ADC_EOC_SINGLE_CONV */
+ default:
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+ break;
+ }
+
+ /* Enable conversion of injected group, if automatic injected conversion */
+ /* is disabled. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* Case of multimode enabled (when multimode feature is available): */
+ /* if ADC is slave, */
+ /* - ADC is enabled only (conversion is not started), */
+ /* - if multimode only concerns regular conversion, ADC is enabled */
+ /* and conversion is started. */
+ /* If ADC is master or independent, */
+ /* - ADC is enabled and conversion is started. */
+#if defined(ADC_MULTIMODE_SUPPORT)
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+ || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
+ )
+ {
+ /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
+ if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
+ {
+ LL_ADC_INJ_StartConversion(hadc->Instance);
+ }
+ }
+ else
+ {
+ /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
+ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ }
+#else
+ if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
+ {
+ LL_ADC_INJ_StartConversion(hadc->Instance);
+ }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ }
+ else
+ {
+ __HAL_UNLOCK(hadc);
+ }
+ }
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Stop conversion of injected channels, disable interruption of
+ * end-of-conversion. Disable ADC peripheral if no regular conversion
+ * is on going.
+ * @note If ADC must be disabled and if conversion is on going on
+ * regular group, function HAL_ADC_Stop must be used to stop both
+ * injected and regular groups, and disable the ADC.
+ * @note If injected group mode auto-injection is enabled,
+ * function HAL_ADC_Stop must be used.
+ * @note Case of multimode enabled (when multimode feature is available):
+ * HAL_ADCEx_InjectedStop_IT() API must be called for ADC master first,
+ * then for ADC slave.
+ * For ADC master, conversion is stopped and ADC is disabled.
+ * For ADC slave, ADC is disabled only (conversion stop of ADC master
+ * has already stopped conversion of ADC slave).
+ * @note In case of auto-injection mode, HAL_ADC_Stop() must be used.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential conversion on going on injected group only. */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if injected conversions are effectively stopped */
+ /* and if no conversion on the other group (regular group) is intended to */
+ /* continue. */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Disable ADC end of conversion interrupt for injected channels */
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_FLAG_JQOVF));
+
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* 2. Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
+ }
+ }
+ /* Conversion on injected group is stopped, but ADC not disabled since */
+ /* conversion on regular group is still running. */
+ else
+ {
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+ }
+ }
+
+ __HAL_UNLOCK(hadc);
+
+ return tmp_hal_status;
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Enable ADC, start MultiMode conversion and transfer regular results through DMA.
+ * @note Multimode must have been previously configured using
+ * HAL_ADCEx_MultiModeConfigChannel() function.
+ * Interruptions enabled in this function:
+ * overrun, DMA half transfer, DMA transfer complete.
+ * Each of these interruptions has its dedicated callback function.
+ * @note State field of Slave ADC handle is not updated in this configuration:
+ * user should not rely on it for information related to Slave regular
+ * conversions.
+ * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
+ * @param pData Destination Buffer address.
+ * @param Length Length of data to be transferred from ADC peripheral to memory (in bytes).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, const uint32_t *pData, uint32_t Length)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+ ADC_HandleTypeDef tmp_hadc_slave;
+ ADC_Common_TypeDef *tmp_adc_common;
+ uint32_t LengthInBytes;
+ DMA_NodeConfTypeDef node_conf;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+ assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
+ {
+ tmp_hal_status = HAL_BUSY;
+ }
+ else
+ {
+ __HAL_LOCK(hadc);
+
+ /* Temporary handle minimum initialization */
+ __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
+ ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
+
+ /* Set a temporary handle of the ADC slave associated to the ADC master */
+ ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
+
+ if (tmp_hadc_slave.Instance == NULL)
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ __HAL_UNLOCK(hadc);
+ return HAL_ERROR;
+ }
+
+ /* Enable the ADC peripherals: master and slave (in case if not already */
+ /* enabled previously) */
+ tmp_hal_status = ADC_Enable(hadc);
+ if (tmp_hal_status == HAL_OK)
+ {
+ tmp_hal_status = ADC_Enable(&tmp_hadc_slave);
+ }
+
+ /* Start multimode conversion of ADCs pair */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ (HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR \
+ | HAL_ADC_STATE_REG_EOSMP),
+ HAL_ADC_STATE_REG_BUSY);
+
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Set the DMA transfer complete callback */
+ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
+
+ /* Set the DMA half transfer complete callback */
+ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
+
+ /* Set the DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
+
+ /* Pointer to the common control register */
+ tmp_adc_common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
+
+ /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
+ /* start (in case of SW start): */
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Enable ADC overrun interrupt */
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+
+ /* Length should be converted to number of bytes */
+ LengthInBytes = Length * 4U;
+
+ /* Start the DMA channel */
+ if ((hadc->DMA_Handle->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if ((hadc->DMA_Handle->LinkedListQueue != NULL) && (hadc->DMA_Handle->LinkedListQueue->Head != NULL))
+ {
+ /* Length should be converted to number of bytes */
+ if (HAL_DMAEx_List_GetNodeConfig(&node_conf, hadc->DMA_Handle->LinkedListQueue->Head) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Length should be converted to number of bytes */
+ if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
+ {
+ /* Word -> Bytes */
+ LengthInBytes = Length * 4U;
+ }
+ else if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
+ {
+ /* Halfword -> Bytes */
+ LengthInBytes = Length * 2U;
+ }
+ else /* Bytes */
+ {
+ /* Same size already expressed in Bytes */
+ LengthInBytes = Length;
+ }
+
+ hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = (uint32_t)LengthInBytes;
+ hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = \
+ (uint32_t)&tmp_adc_common->CDR;
+ hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
+
+ tmp_hal_status = HAL_DMAEx_List_Start_IT(hadc->DMA_Handle);
+ }
+ else
+ {
+ tmp_hal_status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Length should be converted to number of bytes */
+ if (hadc->DMA_Handle->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
+ {
+ /* Word -> Bytes */
+ LengthInBytes = Length * 4U;
+ }
+ else if (hadc->DMA_Handle->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
+ {
+ /* Halfword -> Bytes */
+ LengthInBytes = Length * 2U;
+ }
+ else /* Bytes */
+ {
+ /* Same size already expressed in Bytes */
+ LengthInBytes = Length;
+ }
+
+ tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmp_adc_common->CDR, (uint32_t)pData, \
+ LengthInBytes);
+ }
+
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* Start ADC group regular conversion */
+ LL_ADC_REG_StartConversion(hadc->Instance);
+ }
+ else
+ {
+ __HAL_UNLOCK(hadc);
+ }
+ }
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.
+ * @note Multimode is kept enabled after this function. MultiMode DMA bits
+ * (MDMA and DMACFG bits of common CCR register) are maintained. To disable
+ * Multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
+ * reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
+ * resort to HAL_ADCEx_DisableMultiMode() API.
+ * @note In case of DMA configured in circular mode, function
+ * HAL_ADC_Stop_DMA() must be called after this function with handle of
+ * ADC slave, to properly disable the DMA channel.
+ * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+ uint32_t tickstart;
+ ADC_HandleTypeDef tmp_hadc_slave;
+ uint32_t tmp_hadc_slave_conversion_on_going;
+ HAL_StatusTypeDef tmp_hadc_slave_disable_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential multimode conversion on going, on regular and injected groups */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Temporary handle minimum initialization */
+ __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
+ ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
+
+ /* Set a temporary handle of the ADC slave associated to the ADC master */
+ ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
+
+ if (tmp_hadc_slave.Instance == NULL)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+
+ /* Procedure to disable the ADC peripheral: wait for conversions */
+ /* effectively stopped (ADC master and ADC slave), then disable ADC */
+
+ /* 1. Wait for ADC conversion completion for ADC master and ADC slave */
+ tickstart = HAL_GetTick();
+
+ tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
+ while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
+ || (tmp_hadc_slave_conversion_on_going == 1UL)
+ )
+ {
+ if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
+ {
+ /* New check to avoid false timeout detection in case of preemption */
+ tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
+
+ if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
+ || (tmp_hadc_slave_conversion_on_going == 1UL)
+ )
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ }
+
+ tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
+ }
+
+ /* Disable the DMA channel (in case of DMA in circular mode or stop */
+ /* while DMA transfer is on going) */
+ /* Note: DMA channel of ADC slave should be stopped after this function */
+ /* with HAL_ADC_Stop_DMA() API. */
+ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+ /* Check if DMA channel effectively disabled */
+ if (tmp_hal_status == HAL_ERROR)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+ }
+
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+ /* 2. Disable the ADC peripherals: master and slave */
+ /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */
+ /* memory a potential failing status. */
+ if (tmp_hal_status == HAL_OK)
+ {
+ tmp_hadc_slave_disable_status = ADC_Disable(&tmp_hadc_slave);
+ if ((ADC_Disable(hadc) == HAL_OK) &&
+ (tmp_hadc_slave_disable_status == HAL_OK))
+ {
+ tmp_hal_status = HAL_OK;
+ }
+ }
+ else
+ {
+ /* In case of error, attempt to disable ADC master and slave without status assert */
+ (void) ADC_Disable(hadc);
+ (void) ADC_Disable(&tmp_hadc_slave);
+ }
+
+ /* Set ADC state (ADC master) */
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
+ }
+
+ __HAL_UNLOCK(hadc);
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Return the last ADC Master and Slave regular conversions results when in multimode configuration.
+ * @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used)
+ * @retval The converted data values.
+ */
+uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc)
+{
+ const ADC_Common_TypeDef *tmp_adc_common;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+
+ /* Prevent unused argument(s) compilation warning if no assert_param check */
+ /* and possible no usage in __LL_ADC_COMMON_INSTANCE() below */
+ UNUSED(hadc);
+
+ /* Pointer to the common control register */
+ tmp_adc_common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
+
+ /* Return the multi mode conversion value */
+ return tmp_adc_common->CDR;
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @brief Get ADC injected group conversion result.
+ * @note Reading register JDRx automatically clears ADC flag JEOC
+ * (ADC group injected end of unitary conversion).
+ * @note This function does not clear ADC flag JEOS
+ * (ADC group injected end of sequence conversion)
+ * Occurrence of flag JEOS rising:
+ * - If sequencer is composed of 1 rank, flag JEOS is equivalent
+ * to flag JEOC.
+ * - If sequencer is composed of several ranks, during the scan
+ * sequence flag JEOC only is raised, at the end of the scan sequence
+ * both flags JEOC and EOS are raised.
+ * Flag JEOS must not be cleared by this function because
+ * it would not be compliant with low power features
+ * (feature low power auto-wait, not available on all STM32 families).
+ * To clear this flag, either use function:
+ * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
+ * model polling: @ref HAL_ADCEx_InjectedPollForConversion()
+ * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
+ * @param hadc ADC handle
+ * @param InjectedRank the converted ADC injected rank.
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_INJECTED_RANK_1 ADC group injected rank 1
+ * @arg @ref ADC_INJECTED_RANK_2 ADC group injected rank 2
+ * @arg @ref ADC_INJECTED_RANK_3 ADC group injected rank 3
+ * @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4
+ * @retval ADC group injected conversion data
+ */
+uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
+{
+ uint32_t tmp_jdr;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
+
+ /* Get ADC converted value */
+ switch (InjectedRank)
+ {
+ case ADC_INJECTED_RANK_4:
+ tmp_jdr = hadc->Instance->JDR4;
+ break;
+ case ADC_INJECTED_RANK_3:
+ tmp_jdr = hadc->Instance->JDR3;
+ break;
+ case ADC_INJECTED_RANK_2:
+ tmp_jdr = hadc->Instance->JDR2;
+ break;
+ case ADC_INJECTED_RANK_1:
+ default:
+ tmp_jdr = hadc->Instance->JDR1;
+ break;
+ }
+
+ return tmp_jdr;
+}
+
+/**
+ * @brief Injected conversion complete callback in non-blocking mode.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADCEx_InjectedConvCpltCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Injected context queue overflow callback.
+ * @note This callback is called if injected context queue is enabled
+ (parameter "QueueInjectedContext" in injected channel configuration)
+ and if a new injected context is set when queue is full (maximum 2
+ contexts).
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Analog watchdog 2 callback in non-blocking mode.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Analog watchdog 3 callback in non-blocking mode.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file.
+ */
+}
+
+
+/**
+ * @brief End Of Sampling callback in non-blocking mode.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file.
+ */
+}
+
+
+/**
+ * @brief Stop ADC conversion of regular group (and injected channels in
+ * case of auto_injection mode), disable ADC peripheral if no
+ * conversion is on going on injected group.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential regular conversion on going */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+
+ /* Disable ADC peripheral if regular conversions are effectively stopped
+ and if no injected conversions are on-going */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Clear HAL_ADC_STATE_REG_BUSY bit */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* 2. Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
+ }
+ }
+ /* Conversion on injected group is stopped, but ADC not disabled since */
+ /* conversion on regular group is still running. */
+ else
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+ }
+ }
+
+ __HAL_UNLOCK(hadc);
+
+ return tmp_hal_status;
+}
+
+
+/**
+ * @brief Stop ADC conversion of ADC groups regular and injected,
+ * disable interrution of end-of-conversion,
+ * disable ADC peripheral if no conversion is on going
+ * on injected group.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential regular conversion on going */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped
+ and if no injected conversion is on-going */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Clear HAL_ADC_STATE_REG_BUSY bit */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ /* Disable all regular-related interrupts */
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+
+ /* 2. Disable ADC peripheral if no injected conversions are on-going */
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ tmp_hal_status = ADC_Disable(hadc);
+ /* if no issue reported */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
+ }
+ }
+ else
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+ }
+ }
+
+ __HAL_UNLOCK(hadc);
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Stop ADC conversion of regular group (and injected group in
+ * case of auto_injection mode), disable ADC DMA transfer, disable
+ * ADC peripheral if no conversion is on going
+ * on injected group.
+ * @note HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode only.
+ * For multimode (when multimode feature is available),
+ * HAL_ADCEx_RegularMultiModeStop_DMA() API must be used.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential regular conversion on going */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped
+ and if no injected conversion is on-going */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Clear HAL_ADC_STATE_REG_BUSY bit */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
+ MODIFY_REG(hadc->Instance->CFGR1, ADC_CFGR1_DMNGT_0 | ADC_CFGR1_DMNGT_1, 0UL);
+
+ /* Disable the DMA channel (in case of DMA in circular mode or stop while */
+ /* while DMA transfer is on going) */
+ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+ /* Check if DMA channel effectively disabled */
+ if (tmp_hal_status != HAL_OK)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+ }
+
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+ /* 2. Disable the ADC peripheral */
+ /* Update "tmp_hal_status" only if DMA channel disabling passed, */
+ /* to keep in memory a potential failing status. */
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ if (tmp_hal_status == HAL_OK)
+ {
+ tmp_hal_status = ADC_Disable(hadc);
+ }
+ else
+ {
+ (void)ADC_Disable(hadc);
+ }
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
+ }
+ }
+ else
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+ }
+ }
+
+ __HAL_UNLOCK(hadc);
+
+ return tmp_hal_status;
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected
+ * conversion is on-going.
+ * @note Multimode is kept enabled after this function. Multimode DMA bits
+ * (MDMA and DMACFG bits of common CCR register) are maintained. To disable
+ * multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
+ * reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
+ * resort to HAL_ADCEx_DisableMultiMode() API.
+ * @note In case of DMA configured in circular mode, function
+ * HAL_ADCEx_RegularStop_DMA() must be called after this function with handle of
+ * ADC slave, to properly disable the DMA channel.
+ * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+ ADC_HandleTypeDef tmp_hadc_slave;
+ uint32_t tmp_hadc_slave_conversion_on_going;
+ uint32_t tickstart;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential multimode conversion on going, on regular groups */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Clear HAL_ADC_STATE_REG_BUSY bit */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ /* Temporary handle minimum initialization */
+ __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
+ ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
+
+ /* Set a temporary handle of the ADC slave associated to the ADC master */
+ ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
+
+ if (tmp_hadc_slave.Instance == NULL)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ __HAL_UNLOCK(hadc);
+ return HAL_ERROR;
+ }
+
+ /* Procedure to disable the ADC peripheral: wait for conversions */
+ /* effectively stopped (ADC master and ADC slave), then disable ADC */
+
+ /* 1. Wait for ADC conversion completion for ADC master and ADC slave */
+ tickstart = HAL_GetTick();
+
+ tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
+ while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
+ || (tmp_hadc_slave_conversion_on_going == 1UL)
+ )
+ {
+ if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ __HAL_UNLOCK(hadc);
+ return HAL_ERROR;
+ }
+
+ tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
+ }
+
+ /* Disable the DMA channel (in case of DMA in circular mode or stop */
+ /* while DMA transfer is on going) */
+ /* Note: DMA channel of ADC slave should be stopped after this function */
+ /* with HAL_ADCEx_RegularStop_DMA() API. */
+ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+ /* Check if DMA channel effectively disabled */
+ if (tmp_hal_status != HAL_OK)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+ }
+
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+ /* 2. Disable the ADC peripherals: master and slave if no injected */
+ /* conversion is on-going. */
+ /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */
+ /* memory a potential failing status. */
+ if (tmp_hal_status == HAL_OK)
+ {
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ tmp_hal_status = ADC_Disable(hadc);
+ if (tmp_hal_status == HAL_OK)
+ {
+ if (LL_ADC_INJ_IsConversionOngoing((&tmp_hadc_slave)->Instance) == 0UL)
+ {
+ tmp_hal_status = ADC_Disable(&tmp_hadc_slave);
+ }
+ }
+ }
+
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Both Master and Slave ADC's could be disabled. Update Master State */
+ /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
+ }
+ else
+ {
+ /* injected (Master or Slave) conversions are still on-going,
+ no Master State change */
+ }
+ }
+ }
+
+ __HAL_UNLOCK(hadc);
+
+ return tmp_hal_status;
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions
+ * @brief ADC Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure channels on injected group
+ (+) Configure multimode when multimode feature is available
+ (+) Enable or Disable Injected Queue
+ (+) Disable ADC voltage regulator
+ (+) Enter ADC deep-power-down mode
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure a channel to be assigned to ADC group injected.
+ * @note Possibility to update parameters on the fly:
+ * This function initializes injected group, following calls to this
+ * function can be used to reconfigure some parameters of structure
+ * "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC.
+ * The setting of these parameters is conditioned to ADC state:
+ * Refer to comments of structure "ADC_InjectionConfTypeDef".
+ * @note In case of usage of internal measurement channels:
+ * Vbat/VrefInt/TempSensor.
+ * These internal paths can be disabled using function
+ * HAL_ADC_DeInit().
+ * @note Caution: For Injected Context Queue use, a context must be fully
+ * defined before start of injected conversion. All channels are configured
+ * consecutively for the same ADC instance. Therefore, the number of calls to
+ * HAL_ADCEx_InjectedConfigChannel() must be equal to the value of parameter
+ * InjectedNbrOfConversion for each context.
+ * - Example 1: If 1 context is intended to be used (or if there is no use of the
+ * Injected Queue Context feature) and if the context contains 3 injected ranks
+ * (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be
+ * called once for each channel (i.e. 3 times) before starting a conversion.
+ * This function must not be called to configure a 4th injected channel:
+ * it would start a new context into context queue.
+ * - Example 2: If 2 contexts are intended to be used and each of them contains
+ * 3 injected ranks (InjectedNbrOfConversion = 3),
+ * HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and
+ * for each context (3 channels x 2 contexts = 6 calls). Conversion can
+ * start once the 1st context is set, that is after the first three
+ * HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly.
+ * @param hadc ADC handle
+ * @param pConfigInjected Structure of ADC injected group and ADC channel for
+ * injected group.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *pConfigInjected)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ uint32_t tmp_offset_shifted;
+ uint32_t tmp_config_internal_channel;
+ uint32_t tmp_adc_is_conversion_on_going_regular;
+ uint32_t tmp_adc_is_conversion_on_going_injected;
+ __IO uint32_t wait_loop_index;
+ uint32_t tmp_jsqr_context_queue_being_built = 0U;
+ uint32_t tmp_channel;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_SAMPLE_TIME(pConfigInjected->InjectedSamplingTime));
+ assert_param(IS_ADC_SINGLE_DIFFERENTIAL(pConfigInjected->InjectedSingleDiff));
+ assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->AutoInjectedConv));
+ assert_param(IS_ADC_EXTTRIGINJEC_EDGE(pConfigInjected->ExternalTrigInjecConvEdge));
+ assert_param(IS_ADC_EXTTRIGINJEC(pConfigInjected->ExternalTrigInjecConv));
+ assert_param(IS_ADC_OFFSET_NUMBER(pConfigInjected->InjectedOffsetNumber));
+ assert_param(IS_ADC_OFFSET_SIGN(pConfigInjected->InjectedOffsetSign));
+ assert_param(IS_ADC_RANGE(hadc->Instance, ADC_GET_RESOLUTION(hadc), pConfigInjected->InjectedOffset));
+ assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjecOversamplingMode));
+
+ if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
+ {
+ assert_param(IS_ADC_INJECTED_RANK(pConfigInjected->InjectedRank));
+ assert_param(IS_ADC_INJECTED_NB_CONV(pConfigInjected->InjectedNbrOfConversion));
+ assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjectedDiscontinuousConvMode));
+ }
+
+ /* Check offset range according to oversampling setting */
+ if (hadc->Init.OversamplingMode == ENABLE)
+ {
+ assert_param(IS_ADC_RANGE(hadc->Instance, ADC_GET_RESOLUTION(hadc),
+ pConfigInjected->InjectedOffset / (hadc->Init.Oversampling.Ratio + 1U)));
+ }
+ else
+ {
+ assert_param(IS_ADC_RANGE(hadc->Instance, ADC_GET_RESOLUTION(hadc), pConfigInjected->InjectedOffset));
+ }
+
+ /* JDISCEN and JAUTO bits can't be set at the same time */
+ assert_param(!((pConfigInjected->InjectedDiscontinuousConvMode == ENABLE) \
+ && (pConfigInjected->AutoInjectedConv == ENABLE)));
+
+ /* DISCEN and JAUTO bits can't be set at the same time */
+ assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (pConfigInjected->AutoInjectedConv == ENABLE)));
+
+ /* Verification of channel number */
+ if (pConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
+ {
+ assert_param(IS_ADC_CHANNEL(pConfigInjected->InjectedChannel));
+ }
+ else
+ {
+ if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
+ {
+ assert_param(IS_ADC1_DIFF_CHANNEL(pConfigInjected->InjectedChannel));
+ }
+ }
+
+ __HAL_LOCK(hadc);
+
+ /* Configuration of injected group sequencer: */
+ /* Hardware constraint: Must fully define injected context register JSQR */
+ /* before make it entering into injected sequencer queue. */
+ /* */
+ /* - if scan mode is disabled: */
+ /* * Injected channels sequence length is set to 0x00: 1 channel */
+ /* converted (channel on injected rank 1) */
+ /* Parameter "InjectedNbrOfConversion" is discarded. */
+ /* * Injected context register JSQR setting is simple: register is fully */
+ /* defined on one call of this function (for injected rank 1) and can */
+ /* be entered into queue directly. */
+ /* - if scan mode is enabled: */
+ /* * Injected channels sequence length is set to parameter */
+ /* "InjectedNbrOfConversion". */
+ /* * Injected context register JSQR setting more complex: register is */
+ /* fully defined over successive calls of this function, for each */
+ /* injected channel rank. It is entered into queue only when all */
+ /* injected ranks have been set. */
+ /* Note: Scan mode is not present by hardware on this device, but used */
+ /* by software for alignment over all STM32 devices. */
+
+ if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) ||
+ (pConfigInjected->InjectedNbrOfConversion == 1U))
+ {
+ /* Configuration of context register JSQR: */
+ /* - number of ranks in injected group sequencer: fixed to 1st rank */
+ /* (scan mode disabled, only rank 1 used) */
+ /* - external trigger to start conversion */
+ /* - external trigger polarity */
+ /* - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */
+
+ if (pConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
+ {
+ /* Enable external trigger if trigger selection is different of */
+ /* software start. */
+ /* Note: This configuration keeps the hardware feature of parameter */
+ /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
+ /* software start. */
+ if (pConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
+ {
+ tmp_jsqr_context_queue_being_built = (ADC_JSQR_RK(pConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1)
+ | (pConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
+ | pConfigInjected->ExternalTrigInjecConvEdge
+ );
+ }
+ else
+ {
+ tmp_jsqr_context_queue_being_built = (ADC_JSQR_RK(pConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1));
+ }
+
+ MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_jsqr_context_queue_being_built);
+ /* For debug and informative reasons, hadc handle saves JSQR setting */
+ hadc->InjectionConfig.ContextQueue = tmp_jsqr_context_queue_being_built;
+ }
+ }
+ else
+ {
+ /* Case of scan mode enabled, several channels to set into injected group */
+ /* sequencer. */
+ /* */
+ /* Procedure to define injected context register JSQR over successive */
+ /* calls of this function, for each injected channel rank: */
+ /* 1. Start new context and set parameters related to all injected */
+ /* channels: injected sequence length and trigger. */
+
+ /* if hadc->InjectionConfig.ChannelCount is equal to 0, this is the first */
+ /* call of the context under setting */
+ if (hadc->InjectionConfig.ChannelCount == 0U)
+ {
+ /* Initialize number of channels that will be configured on the context */
+ /* being built */
+ hadc->InjectionConfig.ChannelCount = pConfigInjected->InjectedNbrOfConversion;
+ /* Handle hadc saves the context under build up over each HAL_ADCEx_InjectedConfigChannel()
+ call, this context will be written in JSQR register at the last call.
+ At this point, the context is merely reset */
+ hadc->InjectionConfig.ContextQueue = 0x00000000U;
+
+ /* Configuration of context register JSQR: */
+ /* - number of ranks in injected group sequencer */
+ /* - external trigger to start conversion */
+ /* - external trigger polarity */
+
+ /* Enable external trigger if trigger selection is different of */
+ /* software start. */
+ /* Note: This configuration keeps the hardware feature of parameter */
+ /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
+ /* software start. */
+ if (pConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
+ {
+ tmp_jsqr_context_queue_being_built = ((pConfigInjected->InjectedNbrOfConversion - 1U)
+ | (pConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
+ | pConfigInjected->ExternalTrigInjecConvEdge
+ );
+ }
+ else
+ {
+ tmp_jsqr_context_queue_being_built = ((pConfigInjected->InjectedNbrOfConversion - 1U));
+ }
+ }
+
+ /* 2. Continue setting of context under definition with parameter */
+ /* related to each channel: channel rank sequence */
+ /* Clear the old JSQx bits for the selected rank */
+ tmp_jsqr_context_queue_being_built &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, pConfigInjected->InjectedRank);
+
+ /* Set the JSQx bits for the selected rank */
+ tmp_jsqr_context_queue_being_built |= ADC_JSQR_RK(pConfigInjected->InjectedChannel, pConfigInjected->InjectedRank);
+
+ /* Decrease channel count */
+ hadc->InjectionConfig.ChannelCount--;
+
+ /* 3. tmp_jsqr_context_queue_being_built is fully built for this HAL_ADCEx_InjectedConfigChannel()
+ call, aggregate the setting to those already built during the previous
+ HAL_ADCEx_InjectedConfigChannel() calls (for the same context of course) */
+ hadc->InjectionConfig.ContextQueue |= tmp_jsqr_context_queue_being_built;
+
+ /* 4. End of context setting: if this is the last channel set, then write context
+ into register JSQR and make it enter into queue */
+ if (hadc->InjectionConfig.ChannelCount == 0U)
+ {
+ MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, hadc->InjectionConfig.ContextQueue);
+ }
+ }
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on injected group: */
+ /* - Injected context queue: Queue disable (active context is kept) or */
+ /* enable (context decremented, up to 2 contexts queued) */
+ /* - Injected discontinuous mode: can be enabled only if auto-injected */
+ /* mode is disabled. */
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* ADC channels preselection */
+ hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel) & 0x1FUL));
+
+ /* If auto-injected mode is disabled: no constraint */
+ if (pConfigInjected->AutoInjectedConv == DISABLE)
+ {
+ MODIFY_REG(hadc->Instance->CFGR1,
+ ADC_CFGR1_JDISCEN,
+ ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)pConfigInjected->InjectedDiscontinuousConvMode));
+ }
+ /* If auto-injected mode is enabled: Injected discontinuous setting is */
+ /* discarded. */
+ else
+ {
+ MODIFY_REG(hadc->Instance->CFGR1,
+ ADC_CFGR1_JDISCEN,
+ ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)pConfigInjected->InjectedDiscontinuousConvMode));
+ }
+ }
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on regular and injected groups: */
+ /* - Automatic injected conversion: can be enabled if injected group */
+ /* external triggers are disabled. */
+ /* - Channel sampling time */
+ /* - Channel offset */
+ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+ tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+
+ if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+ && (tmp_adc_is_conversion_on_going_injected == 0UL)
+ )
+ {
+ /* If injected group external triggers are disabled (set to injected */
+ /* software start): no constraint */
+ if ((pConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
+ || (pConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
+ {
+ if (pConfigInjected->AutoInjectedConv == ENABLE)
+ {
+ SET_BIT(hadc->Instance->CFGR1, ADC_CFGR1_JAUTO);
+ }
+ else
+ {
+ CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_JAUTO);
+ }
+ }
+ /* If Automatic injected conversion was intended to be set and could not */
+ /* due to injected group external triggers enabled, error is reported. */
+ else
+ {
+ if (pConfigInjected->AutoInjectedConv == ENABLE)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+ else
+ {
+ CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_JAUTO);
+ }
+ }
+
+ if (pConfigInjected->InjecOversamplingMode == ENABLE)
+ {
+ assert_param(IS_ADC_OVERSAMPLING_RATIO(pConfigInjected->InjecOversampling.Ratio));
+ assert_param(IS_ADC_RIGHT_BIT_SHIFT(pConfigInjected->InjecOversampling.RightBitShift));
+
+ /* JOVSE must be reset in case of triggered regular mode */
+ assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS) ==
+ (ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS)));
+
+ /* Configuration of Injected Oversampler: */
+ /* - Oversampling Ratio */
+ /* - Right bit shift */
+
+ /* Enable OverSampling mode */
+ MODIFY_REG(hadc->Instance->CFGR2,
+ ADC_CFGR2_JOVSE | ADC_CFGR2_OVSR | ADC_CFGR2_OVSS,
+ ADC_CFGR2_JOVSE | pConfigInjected->InjecOversampling.Ratio |
+ pConfigInjected->InjecOversampling.RightBitShift
+ );
+ }
+ else
+ {
+ /* Disable Regular OverSampling */
+ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_JOVSE);
+ }
+
+ /* Set sampling time of the selected ADC channel */
+ LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfigInjected->InjectedChannel,
+ pConfigInjected->InjectedSamplingTime);
+
+ /* Configure the offset: offset enable/disable, channel, offset value */
+
+ /* Shift the offset with respect to the selected ADC resolution. */
+ /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
+ tmp_offset_shifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, pConfigInjected->InjectedOffset);
+
+ if (pConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE)
+ {
+ /* Set ADC selected offset number */
+ LL_ADC_SetOffset(hadc->Instance, pConfigInjected->InjectedOffsetNumber, pConfigInjected->InjectedChannel,
+ tmp_offset_shifted);
+ /* Set ADC selected offset sign */
+ LL_ADC_SetOffsetSign(hadc->Instance, pConfigInjected->InjectedOffsetNumber, pConfigInjected->InjectedOffsetSign);
+ /* Set ADC selected offset signed saturation */
+ LL_ADC_SetOffsetSignedSaturation(hadc->Instance, pConfigInjected->InjectedOffsetNumber,
+ (pConfigInjected->InjectedOffsetSignedSaturation == ENABLE)
+ ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE \
+ : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
+ }
+ else
+ {
+ /* Scan each offset register to check if the selected channel is targeted. */
+ /* If this is the case, the corresponding offset number is disabled. */
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) ==
+ __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
+ {
+ LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_1, pConfigInjected->InjectedChannel,
+ LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
+ }
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) ==
+ __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
+ {
+ LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_2, pConfigInjected->InjectedChannel,
+ LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
+ }
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) ==
+ __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
+ {
+ LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_4, pConfigInjected->InjectedChannel,
+ LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
+ }
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) ==
+ __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
+ {
+ LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_4, pConfigInjected->InjectedChannel,
+ LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
+ }
+ }
+ }
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated only when ADC is disabled: */
+ /* - Single or differential mode */
+ /* - Internal measurement channels: Vbat/VrefInt/TempSensor */
+ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ {
+ /* Set mode single-ended or differential input of the selected ADC channel */
+ LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfigInjected->InjectedChannel, pConfigInjected->InjectedSingleDiff);
+
+ /* Configuration of differential mode */
+ /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
+ if (pConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED)
+ {
+ /* Set sampling time of the selected ADC channel */
+ tmp_channel = __LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel) \
+ + 1UL) & 0x1FUL);
+ LL_ADC_SetChannelSamplingTime(hadc->Instance, tmp_channel, pConfigInjected->InjectedSamplingTime);
+ }
+
+ /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */
+ /* internal measurement paths enable: If internal channel selected, */
+ /* enable dedicated internal buffers and path. */
+ /* Note: these internal measurement paths can be disabled using */
+ /* HAL_ADC_DeInit(). */
+
+ if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfigInjected->InjectedChannel))
+ {
+ /* Configuration of common ADC parameters (continuation) */
+ /* Software is allowed to change common parameters only when all ADCs */
+ /* of the common group are disabled. */
+ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
+ {
+ tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+
+ /* If the requested internal measurement path has already been enabled, */
+ /* bypass the configuration processing. */
+ if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR)
+ && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
+ {
+ if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+ LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
+
+ /* Delay for temperature sensor stabilization time */
+ /* Wait loop initialization and execution */
+ /* Note: Variable divided by 2 to compensate partially */
+ /* CPU processing cycles, scaling in us split to not */
+ /* exceed 32 bits register capacity and handle low frequency. */
+ wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
+ while (wait_loop_index != 0UL)
+ {
+ wait_loop_index--;
+ }
+ }
+ }
+ else if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)
+ && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
+ {
+ if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+ LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
+ }
+ }
+ else if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)
+ && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
+ {
+ if (ADC_VREFINT_INSTANCE(hadc))
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+ LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
+ }
+ }
+ else
+ {
+ /* nothing to do */
+ }
+ }
+ /* If the requested internal measurement path has already been enabled */
+ /* and other ADC of the common group are enabled, internal */
+ /* measurement paths cannot be enabled. */
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+ }
+ }
+
+ __HAL_UNLOCK(hadc);
+
+ return tmp_hal_status;
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Enable ADC multimode and configure multimode parameters
+ * @note Possibility to update parameters on the fly:
+ * This function initializes multimode parameters, following
+ * calls to this function can be used to reconfigure some parameters
+ * of structure "ADC_MultiModeTypeDef" on the fly, without resetting
+ * the ADCs.
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_MultiModeTypeDef".
+ * @note To move back configuration from multimode to single mode, ADC must
+ * be reset (using function HAL_ADC_Init() ).
+ * @param hadc Master ADC handle
+ * @param pMultimode Structure of ADC multimode configuration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *pMultimode)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ ADC_Common_TypeDef *tmpADC_Common;
+ ADC_HandleTypeDef tmphadcSlave;
+ uint32_t tmphadcSlave_conversion_on_going;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_MULTIMODE(pMultimode->Mode));
+ if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
+ {
+ assert_param(IS_ADC_DUAL_DATA_MODE(pMultimode->DualModeData));
+ assert_param(IS_ADC_SAMPLING_DELAY(pMultimode->TwoSamplingDelay));
+ }
+
+ __HAL_LOCK(hadc);
+
+ /* Temporary handle minimum initialization */
+ __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
+ ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
+
+ ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
+
+ if (tmphadcSlave.Instance == NULL)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on regular group: */
+ /* - Multimode DMA configuration */
+ /* - Multimode DMA mode */
+ tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
+ if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ && (tmphadcSlave_conversion_on_going == 0UL))
+ {
+ /* Pointer to the common control register */
+ tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
+
+ /* If multimode is selected, configure all pMultimode parameters. */
+ /* Otherwise, reset pMultimode parameters (can be used in case of */
+ /* transition from multimode to independent mode). */
+ if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
+ {
+ MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DAMDF, pMultimode->DualModeData);
+
+ /* Parameters that can be updated only when ADC is disabled: */
+ /* - Multimode mode selection */
+ /* - Multimode delay */
+ /* Note: Delay range depends on selected resolution: */
+ /* from 1 to 12 clock cycles for 12 bits */
+ /* from 1 to 10 clock cycles for 10 bits, */
+ /* from 1 to 8 clock cycles for 8 bits */
+ /* from 1 to 6 clock cycles for 6 bits */
+ /* If a higher delay is selected, it will be clipped to maximum delay */
+ /* range */
+ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
+ {
+ MODIFY_REG(tmpADC_Common->CCR, (ADC_CCR_DUAL | ADC_CCR_DELAY), \
+ (pMultimode->Mode | pMultimode->TwoSamplingDelay));
+ }
+ }
+ else /* ADC_MODE_INDEPENDENT */
+ {
+ CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DAMDF);
+
+ /* Parameters that can be updated only when ADC is disabled: */
+ /* - Multimode mode selection */
+ /* - Multimode delay */
+ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
+ {
+ CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY);
+ }
+ }
+ }
+ /* If one of the ADC sharing the same common group is enabled, no update */
+ /* could be done on neither of the multimode structure parameters. */
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ __HAL_UNLOCK(hadc);
+
+ return tmp_hal_status;
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @brief Disable ADC voltage regulator.
+ * @note Disabling voltage regulator allows to save power. This operation can
+ * be carried out only when ADC is disabled.
+ * @note To enable again the voltage regulator, the user is expected to
+ * resort to HAL_ADC_Init() API.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */
+ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ {
+ LL_ADC_DisableInternalRegulator(hadc->Instance);
+ tmp_hal_status = HAL_OK;
+ }
+ else
+ {
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Enter ADC deep-power-down mode
+ * @note This mode is achieved in setting DEEPPWD bit and allows to save power
+ * in reducing leakage currents. It is particularly interesting before
+ * entering stop modes.
+ * @note Setting DEEPPWD automatically clears ADVREGEN bit and disables the
+ * ADC voltage regulator. This means that this API encompasses
+ * HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal
+ * calibration is lost.
+ * @note To exit the ADC deep-power-down mode, the user is expected to
+ * resort to HAL_ADC_Init() API as well as to relaunch a calibration
+ * with HAL_ADCEx_Calibration_Start() API or to re-apply a previously
+ * saved calibration factor.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */
+ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ {
+ LL_ADC_EnableDeepPowerDown(hadc->Instance);
+ tmp_hal_status = HAL_OK;
+ }
+ else
+ {
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ return tmp_hal_status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_ADC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_comp.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_comp.c
new file mode 100644
index 00000000..ec4c3a72
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_comp.c
@@ -0,0 +1,1066 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_comp.c
+ * @author MCD Application Team
+ * @brief COMP HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the COMP peripheral:
+ * + Initialization and de-initialization functions
+ * + Start/Stop operation functions in polling mode
+ * + Start/Stop operation functions in interrupt mode (through EXTI interrupt)
+ * + Peripheral control functions
+ * + Peripheral state functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### COMP Peripheral features #####
+ ==============================================================================
+
+ [..]
+ The STM32U5xx device family integrates two analog comparators instances:
+ COMP1, COMP2.
+ (#) Comparators input minus (inverting input) and input plus (non inverting input)
+ can be set to internal references or to GPIO pins
+ (refer to GPIO list in reference manual).
+
+ (#) Comparators output level is available using HAL_COMP_GetOutputLevel()
+ and can be redirected to other peripherals: GPIO pins (in mode
+ alternate functions for comparator), timers.
+ (refer to GPIO list in reference manual).
+
+ (#) The comparators have interrupt capability through the EXTI controller
+ with wake-up from sleep and stop modes:
+ (++) COMP1 is internally connected to EXTI Line 20
+ (++) COMP2 is internally connected to EXTI Line 21
+
+ (#) Pairs of comparators instances can be combined in window mode
+ (2 consecutive instances odd and even COMP and COMP).
+
+ From the corresponding IRQ handler, the right interrupt source can be retrieved
+ using macro __HAL_COMP_COMPx_EXTI_GET_FLAG().
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This driver provides functions to configure and program the comparator instances
+ of STM32U5xx devices.
+
+ To use the comparator, perform the following steps:
+
+ (#) Initialize the COMP low level resources by implementing the HAL_COMP_MspInit():
+ (++) Configure the GPIO connected to comparator inputs plus and minus in analog mode
+ using HAL_GPIO_Init().
+ (++) If needed, configure the GPIO connected to comparator output in alternate function mode
+ using HAL_GPIO_Init().
+ (++) If required enable the COMP interrupt by configuring and enabling EXTI line in Interrupt mode and
+ selecting the desired sensitivity level using HAL_GPIO_Init() function. After that enable the comparator
+ interrupt vector using HAL_NVIC_EnableIRQ() function.
+
+ (#) Configure the comparator using HAL_COMP_Init() function:
+ (++) Select the input minus (inverting input)
+ (++) Select the input plus (non-inverting input)
+ (++) Select the hysteresis
+ (++) Select the blanking source
+ (++) Select the output polarity
+ (++) Select the power mode
+ (++) Select the window mode
+
+ -@@- HAL_COMP_Init() calls internally __HAL_RCC_SYSCFG_CLK_ENABLE()
+ to enable internal control clock of the comparators.
+ However, this is a legacy strategy. In future STM32 families,
+ COMP clock enable must be implemented by user in "HAL_COMP_MspInit()".
+ Therefore, for compatibility anticipation, it is recommended to
+ implement __HAL_RCC_SYSCFG_CLK_ENABLE() in "HAL_COMP_MspInit()".
+
+ (#) Reconfiguration on-the-fly of comparator can be done by calling again
+ function HAL_COMP_Init() with new input structure parameters values.
+
+ (#) Enable the comparator using HAL_COMP_Start() function.
+
+ (#) Use HAL_COMP_TriggerCallback() or HAL_COMP_GetOutputLevel() functions
+ to manage comparator outputs (events and output level).
+
+ (#) Disable the comparator using HAL_COMP_Stop() function.
+
+ (#) De-initialize the comparator using HAL_COMP_DeInit() function.
+
+ (#) For safety purpose, comparator configuration can be locked using HAL_COMP_Lock() function.
+ The only way to unlock the comparator is a device hardware reset.
+
+ *** Callback registration ***
+ =============================================
+ [..]
+
+ The compilation flag USE_HAL_COMP_REGISTER_CALLBACKS, when set to 1,
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions HAL_COMP_RegisterCallback()
+ to register an interrupt callback.
+ [..]
+
+ Function HAL_COMP_RegisterCallback() allows to register following callbacks:
+ (+) TriggerCallback : callback for COMP trigger.
+ (+) MspInitCallback : callback for Msp Init.
+ (+) MspDeInitCallback : callback for Msp DeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+ [..]
+
+ Use function HAL_COMP_UnRegisterCallback to reset a callback to the default
+ weak function.
+ [..]
+
+ HAL_COMP_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TriggerCallback : callback for COMP trigger.
+ (+) MspInitCallback : callback for Msp Init.
+ (+) MspDeInitCallback : callback for Msp DeInit.
+ [..]
+
+ By default, after the HAL_COMP_Init() and when the state is HAL_COMP_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ example HAL_COMP_TriggerCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak functions in the HAL_COMP_Init()/ HAL_COMP_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ [..]
+
+ If MspInit or MspDeInit are not null, the HAL_COMP_Init()/ HAL_COMP_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+ [..]
+
+ Callbacks can be registered/unregistered in HAL_COMP_STATE_READY state only.
+ Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ in HAL_COMP_STATE_READY or HAL_COMP_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ [..]
+
+ Then, the user first registers the MspInit/MspDeInit user callbacks
+ using HAL_COMP_RegisterCallback() before calling HAL_COMP_DeInit()
+ or HAL_COMP_Init() function.
+ [..]
+
+ When the compilation flag USE_HAL_COMP_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+
+#if defined (COMP1) || defined (COMP2)
+
+/** @defgroup COMP COMP
+ * @brief COMP HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup COMP_Private_Constants
+ * @{
+ */
+
+/* Delay for COMP startup time. */
+/* Note: Delay required to reach propagation delay specification. */
+/* Literal set to maximum value (refer to device datasheet, */
+/* parameter "tSTART"). */
+/* Unit: us */
+#define COMP_DELAY_STARTUP_US (80UL) /*!< Delay for COMP startup time */
+
+/* Delay for COMP voltage scaler stabilization time. */
+/* Literal set to maximum value (refer to device datasheet, */
+/* parameter "tSTART_SCALER"). */
+/* Unit: us */
+#define COMP_DELAY_VOLTAGE_SCALER_STAB_US (200UL) /*!< Delay for COMP voltage scaler stabilization time */
+
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup COMP_Exported_Functions COMP Exported Functions
+ * @{
+ */
+
+/** @defgroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions
+ * @brief Initialization and de-initialization functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions to initialize and de-initialize comparators
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the COMP according to the specified
+ * parameters in the COMP_InitTypeDef and initialize the associated handle.
+ * @note If the selected comparator is locked, initialization can't be performed.
+ * To unlock the configuration, perform a system reset.
+ * @param hcomp COMP handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
+{
+ uint32_t tmp_csr;
+ uint32_t exti_line;
+ uint32_t comp_voltage_scaler_initialized; /* Value "0" if comparator voltage scaler is not initialized */
+ __IO uint32_t wait_loop_index = 0UL;
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the COMP handle allocation and lock status */
+ if (hcomp == NULL)
+ {
+ status = HAL_ERROR;
+ }
+ else if (__HAL_COMP_IS_LOCKED(hcomp))
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check the parameters */
+ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+ assert_param(IS_COMP_INPUT_PLUS(hcomp->Instance, hcomp->Init.InputPlus));
+ assert_param(IS_COMP_INPUT_MINUS(hcomp->Instance, hcomp->Init.InputMinus));
+ assert_param(IS_COMP_OUTPUTPOL(hcomp->Init.OutputPol));
+ assert_param(IS_COMP_POWERMODE(hcomp->Init.Mode));
+ assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis));
+ assert_param(IS_COMP_BLANKINGSRCE(hcomp->Init.BlankingSrce));
+ assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode));
+ assert_param(IS_COMP_WINDOWMODE(hcomp->Instance, hcomp->Init.WindowMode));
+ if (hcomp->Init.WindowMode != COMP_WINDOWMODE_DISABLE)
+ {
+ assert_param(IS_COMP_WINDOWOUTPUT(hcomp->Init.WindowOutput));
+ }
+
+ if (hcomp->State == HAL_COMP_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hcomp->Lock = HAL_UNLOCKED;
+
+ /* Set COMP error code to none */
+ COMP_CLEAR_ERRORCODE(hcomp);
+
+
+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
+ /* Init the COMP Callback settings */
+ hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */
+
+ if (hcomp->MspInitCallback == NULL)
+ {
+ hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware */
+ /* Note: Internal control clock of the comparators must */
+ /* be enabled in "HAL_COMP_MspInit()" */
+ /* using "__HAL_RCC_SYSCFG_CLK_ENABLE()". */
+ hcomp->MspInitCallback(hcomp);
+#else
+ /* Init the low level hardware */
+ /* Note: Internal control clock of the comparators must */
+ /* be enabled in "HAL_COMP_MspInit()" */
+ /* using "__HAL_RCC_SYSCFG_CLK_ENABLE()". */
+ HAL_COMP_MspInit(hcomp);
+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
+ }
+
+ /* Memorize voltage scaler state before initialization */
+ comp_voltage_scaler_initialized = READ_BIT(hcomp->Instance->CSR, (COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0));
+
+ /* Set COMP parameters */
+ tmp_csr = (hcomp->Init.InputMinus
+ | hcomp->Init.InputPlus
+ | hcomp->Init.BlankingSrce
+ | hcomp->Init.Hysteresis
+ | hcomp->Init.OutputPol
+ | hcomp->Init.Mode
+ );
+
+ /* Set parameters in COMP register */
+ /* Note: Update all bits except read-only, lock and enable bits */
+ MODIFY_REG(hcomp->Instance->CSR,
+ COMP_CSR_PWRMODE | COMP_CSR_INMSEL | COMP_CSR_INPSEL |
+ COMP_CSR_WINMODE | COMP_CSR_POLARITY | COMP_CSR_HYST |
+ COMP_CSR_BLANKSEL,
+ tmp_csr
+ );
+
+ /* Set window mode */
+ /* Note: Window mode bit is located into 1 out of the 2 pairs of COMP */
+ /* instances. Therefore, this function can update another COMP */
+ /* instance that the one currently selected. */
+
+ if (hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)
+ {
+ CLEAR_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINMODE);
+ SET_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINMODE);
+ }
+ else if (hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON)
+ {
+ SET_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINMODE);
+ CLEAR_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINMODE);
+ }
+ else
+ {
+ CLEAR_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINMODE);
+ CLEAR_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINMODE);
+ }
+
+ /* Set window mode output */
+ /* Note: Window mode mode output can also be used when window mode */
+ /* is disabled, to use comparators in independent mode with their */
+ /* output connected through exclusive-or circuitry. */
+ switch (hcomp->Init.WindowOutput)
+ {
+ case COMP_WINDOWOUTPUT_COMP1:
+ SET_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINOUT);
+ CLEAR_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINOUT);
+ break;
+
+ case COMP_WINDOWOUTPUT_COMP2:
+ CLEAR_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINOUT);
+ SET_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINOUT);
+ break;
+
+ case COMP_WINDOWOUTPUT_BOTH:
+ SET_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINOUT);
+ SET_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINOUT);
+ break;
+
+ default: /* COMP_WINDOWOUTPUT_EACH_COMP */
+ CLEAR_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINOUT);
+ CLEAR_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINOUT);
+ break;
+ }
+
+ /* Delay for COMP scaler bridge voltage stabilization */
+ /* Apply the delay if voltage scaler bridge is required and not already enabled */
+ if ((READ_BIT(hcomp->Instance->CSR, (COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)) != 0UL) &&
+ (comp_voltage_scaler_initialized == 0UL))
+ {
+ /* Wait loop initialization and execution */
+ /* Note: Variable divided by 2 to compensate partially */
+ /* CPU processing cycles, scaling in us split to not */
+ /* exceed 32 bits register capacity and handle low frequency. */
+ wait_loop_index = ((COMP_DELAY_VOLTAGE_SCALER_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
+ while (wait_loop_index != 0UL)
+ {
+ wait_loop_index--;
+ }
+ }
+
+ /* Get the EXTI line corresponding to the selected COMP instance */
+ exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
+
+ /* Manage EXTI settings */
+ if ((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != 0UL)
+ {
+ /* Configure EXTI rising edge */
+ if ((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != 0UL)
+ {
+ SET_BIT(EXTI->RTSR1, exti_line);
+ }
+ else
+ {
+ CLEAR_BIT(EXTI->RTSR1, exti_line);
+ }
+
+ /* Configure EXTI falling edge */
+ if ((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != 0UL)
+ {
+ SET_BIT(EXTI->FTSR1, exti_line);
+ }
+ else
+ {
+ CLEAR_BIT(EXTI->FTSR1, exti_line);
+ }
+
+ /* Clear COMP EXTI pending bit (if any) */
+ WRITE_REG(EXTI->RPR1, exti_line);
+ WRITE_REG(EXTI->FPR1, exti_line);
+
+
+ /* Configure EXTI event mode */
+ if ((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL)
+ {
+ SET_BIT(EXTI->EMR1, exti_line);
+ }
+ else
+ {
+ CLEAR_BIT(EXTI->EMR1, exti_line);
+ }
+
+ /* Configure EXTI interrupt mode */
+ if ((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL)
+ {
+ SET_BIT(EXTI->IMR1, exti_line);
+ }
+ else
+ {
+ CLEAR_BIT(EXTI->IMR1, exti_line);
+ }
+ }
+ else
+ {
+ /* Disable EXTI event mode */
+ CLEAR_BIT(EXTI->EMR1, exti_line);
+
+ /* Disable EXTI interrupt mode */
+ CLEAR_BIT(EXTI->IMR1, exti_line);
+ }
+
+ /* Set HAL COMP handle state */
+ /* Note: Transition from state reset to state ready, */
+ /* otherwise (coming from state ready or busy) no state update. */
+ if (hcomp->State == HAL_COMP_STATE_RESET)
+ {
+ hcomp->State = HAL_COMP_STATE_READY;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief DeInitialize the COMP peripheral.
+ * @note Deinitialization cannot be performed if the COMP configuration is locked.
+ * To unlock the configuration, perform a system reset.
+ * @param hcomp COMP handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the COMP handle allocation and lock status */
+ if (hcomp == NULL)
+ {
+ status = HAL_ERROR;
+ }
+ else if (__HAL_COMP_IS_LOCKED(hcomp))
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check the parameter */
+ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+
+ /* Set COMP_CSR register to reset value */
+ WRITE_REG(hcomp->Instance->CSR, 0x00000000UL);
+
+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
+ if (hcomp->MspDeInitCallback == NULL)
+ {
+ hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware: GPIO, RCC clock, NVIC */
+ hcomp->MspDeInitCallback(hcomp);
+#else
+ /* DeInit the low level hardware: GPIO, RCC clock, NVIC */
+ HAL_COMP_MspDeInit(hcomp);
+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
+
+ /* Set HAL COMP handle state */
+ hcomp->State = HAL_COMP_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hcomp);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initialize the COMP MSP.
+ * @param hcomp COMP handle
+ * @retval None
+ */
+__weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcomp);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_COMP_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the COMP MSP.
+ * @param hcomp COMP handle
+ * @retval None
+ */
+__weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcomp);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_COMP_MspDeInit could be implemented in the user file
+ */
+}
+
+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User COMP Callback
+ * To be used instead of the weak predefined callback
+ * @param hcomp Pointer to a COMP_HandleTypeDef structure that contains
+ * the configuration information for the specified COMP.
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_COMP_TRIGGER_CB_ID Trigger callback ID
+ * @arg @ref HAL_COMP_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID,
+ pCOMP_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ if (HAL_COMP_STATE_READY == hcomp->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_COMP_TRIGGER_CB_ID :
+ hcomp->TriggerCallback = pCallback;
+ break;
+
+ case HAL_COMP_MSPINIT_CB_ID :
+ hcomp->MspInitCallback = pCallback;
+ break;
+
+ case HAL_COMP_MSPDEINIT_CB_ID :
+ hcomp->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_COMP_STATE_RESET == hcomp->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_COMP_MSPINIT_CB_ID :
+ hcomp->MspInitCallback = pCallback;
+ break;
+
+ case HAL_COMP_MSPDEINIT_CB_ID :
+ hcomp->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Unregister a COMP Callback
+ * COMP callback is redirected to the weak predefined callback
+ * @param hcomp Pointer to a COMP_HandleTypeDef structure that contains
+ * the configuration information for the specified COMP.
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_COMP_TRIGGER_CB_ID Trigger callback ID
+ * @arg @ref HAL_COMP_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (HAL_COMP_STATE_READY == hcomp->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_COMP_TRIGGER_CB_ID :
+ hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */
+ break;
+
+ case HAL_COMP_MSPINIT_CB_ID :
+ hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_COMP_MSPDEINIT_CB_ID :
+ hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_COMP_STATE_RESET == hcomp->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_COMP_MSPINIT_CB_ID :
+ hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_COMP_MSPDEINIT_CB_ID :
+ hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_Exported_Functions_Group2 Start-Stop operation functions
+ * @brief Start-Stop operation functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start a comparator instance.
+ (+) Stop a comparator instance.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start the comparator.
+ * @param hcomp COMP handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
+{
+ __IO uint32_t wait_loop_index = 0UL;
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the COMP handle allocation and lock status */
+ if (hcomp == NULL)
+ {
+ status = HAL_ERROR;
+ }
+ else if (__HAL_COMP_IS_LOCKED(hcomp))
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check the parameter */
+ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+
+ if (hcomp->State == HAL_COMP_STATE_READY)
+ {
+ /* Enable the selected comparator */
+ SET_BIT(hcomp->Instance->CSR, COMP_CSR_EN);
+
+ /* Set HAL COMP handle state */
+ hcomp->State = HAL_COMP_STATE_BUSY;
+
+ /* Delay for COMP startup time */
+ /* Wait loop initialization and execution */
+ /* Note: Variable divided by 2 to compensate partially */
+ /* CPU processing cycles, scaling in us split to not */
+ /* exceed 32 bits register capacity and handle low frequency. */
+ wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
+ while (wait_loop_index != 0UL)
+ {
+ wait_loop_index--;
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Stop the comparator.
+ * @param hcomp COMP handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the COMP handle allocation and lock status */
+ if (hcomp == NULL)
+ {
+ status = HAL_ERROR;
+ }
+ else if (__HAL_COMP_IS_LOCKED(hcomp))
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check the parameter */
+ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+
+ /* Check compliant states: HAL_COMP_STATE_READY or HAL_COMP_STATE_BUSY */
+ /* (all states except HAL_COMP_STATE_RESET and except locked status. */
+ if (hcomp->State != HAL_COMP_STATE_RESET)
+ {
+ /* Disable the selected comparator */
+ CLEAR_BIT(hcomp->Instance->CSR, COMP_CSR_EN);
+
+ /* Set HAL COMP handle state */
+ hcomp->State = HAL_COMP_STATE_READY;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Comparator IRQ handler.
+ * @param hcomp COMP handle
+ * @retval None
+ */
+void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
+{
+ /* Get the EXTI line corresponding to the selected COMP instance */
+ uint32_t exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
+
+ /* Check COMP EXTI flag */
+ if (READ_BIT(EXTI->RPR1, exti_line) != 0UL)
+ {
+ /* Check whether comparator is in independent or window mode */
+ if (READ_BIT(hcomp->Instance->CSR, COMP_CSR_WINMODE) != 0UL)
+ {
+ /* Clear COMP EXTI line pending bit of the pair of comparators */
+ /* in window mode. */
+ /* Note: Pair of comparators in window mode can both trig IRQ when */
+ /* input voltage is changing from "out of window" area */
+ /* (low or high ) to the other "out of window" area (high or low).*/
+ /* Both flags must be cleared to call comparator trigger */
+ /* callback is called once. */
+ WRITE_REG(EXTI->RPR1, (COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2));
+ }
+ else
+ {
+ /* Clear COMP EXTI line pending bit */
+ WRITE_REG(EXTI->RPR1, exti_line);
+ }
+
+ /* COMP trigger user callback */
+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
+ hcomp->TriggerCallback(hcomp);
+#else
+ HAL_COMP_TriggerCallback(hcomp);
+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Check whether comparator is in independent or window mode */
+ if (READ_BIT(hcomp->Instance->CSR, COMP_CSR_WINMODE) != 0UL)
+ {
+ /* Clear COMP EXTI line pending bit of the pair of comparators */
+ /* in window mode. */
+ /* Note: Pair of comparators in window mode can both trig IRQ when */
+ /* input voltage is changing from "out of window" area */
+ /* (low or high ) to the other "out of window" area (high or low).*/
+ /* Both flags must be cleared to call comparator trigger */
+ /* callback is called once. */
+ WRITE_REG(EXTI->FPR1, (COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2));
+ }
+ else
+ {
+ /* Clear COMP EXTI line pending bit */
+ WRITE_REG(EXTI->FPR1, exti_line);
+ }
+
+ /* COMP trigger user callback */
+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
+ hcomp->TriggerCallback(hcomp);
+#else
+ HAL_COMP_TriggerCallback(hcomp);
+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
+ }
+
+ /* Change COMP state */
+ hcomp->State = HAL_COMP_STATE_READY;
+
+ /* COMP trigger user callback */
+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
+ hcomp->TriggerCallback(hcomp);
+#else
+ HAL_COMP_TriggerCallback(hcomp);
+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Management functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the comparators.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Lock the selected comparator configuration.
+ * @note A system reset is required to unlock the comparator configuration.
+ * @note Locking the comparator from reset state is possible
+ * if __HAL_RCC_SYSCFG_CLK_ENABLE() is being called before.
+ * @param hcomp COMP handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the COMP handle allocation and lock status */
+ if (hcomp == NULL)
+ {
+ status = HAL_ERROR;
+ }
+ else if (__HAL_COMP_IS_LOCKED(hcomp))
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check the parameter */
+ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+
+ /* Set HAL COMP handle state */
+ switch (hcomp->State)
+ {
+ case HAL_COMP_STATE_RESET:
+ hcomp->State = HAL_COMP_STATE_RESET_LOCKED;
+ break;
+ case HAL_COMP_STATE_READY:
+ hcomp->State = HAL_COMP_STATE_READY_LOCKED;
+ break;
+ default: /* HAL_COMP_STATE_BUSY */
+ hcomp->State = HAL_COMP_STATE_BUSY_LOCKED;
+ break;
+ }
+
+ /* Set the lock bit corresponding to selected comparator */
+ __HAL_COMP_LOCK(hcomp);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Return the output level (high or low) of the selected comparator.
+ * The output level depends on the selected polarity.
+ * If the polarity is not inverted:
+ * - Comparator output is low when the input plus is at a lower
+ * voltage than the input minus
+ * - Comparator output is high when the input plus is at a higher
+ * voltage than the input minus
+ * If the polarity is inverted:
+ * - Comparator output is high when the input plus is at a lower
+ * voltage than the input minus
+ * - Comparator output is low when the input plus is at a higher
+ * voltage than the input minus
+ * @param hcomp COMP handle
+ * @retval Returns the selected comparator output level:
+ * @arg COMP_OUTPUT_LEVEL_LOW
+ * @arg COMP_OUTPUT_LEVEL_HIGH
+ *
+ */
+uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp)
+{
+ /* Check the parameter */
+ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+
+ return (uint32_t)((READ_BIT(hcomp->Instance->CSR, COMP_CSR_VALUE)) >> COMP_CSR_VALUE_Pos);
+
+}
+
+/**
+ * @brief Comparator trigger callback.
+ * @param hcomp COMP handle
+ * @retval None
+ */
+__weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcomp);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_COMP_TriggerCallback should be implemented in the user file
+ */
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection permit to get in run-time the status of the peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the COMP handle state.
+ * @param hcomp COMP handle
+ * @retval HAL state
+ */
+HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp)
+{
+ /* Check the COMP handle allocation */
+ if (hcomp == NULL)
+ {
+ return HAL_COMP_STATE_RESET;
+ }
+
+ /* Check the parameter */
+ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+
+ /* Return HAL COMP handle state */
+ return hcomp->State;
+}
+
+/**
+ * @brief Return the COMP error code.
+ * @param hcomp COMP handle
+ * @retval COMP error code
+ */
+uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp)
+{
+ /* Check the parameters */
+ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+
+ return hcomp->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* COMP1 || COMP2 */
+
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cordic.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cordic.c
new file mode 100644
index 00000000..043a7314
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cordic.c
@@ -0,0 +1,1415 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_cordic.c
+ * @author MCD Application Team
+ * @brief CORDIC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the CORDIC peripheral:
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ * + Callback functions
+ * + IRQ handler management
+ * + Peripheral State functions
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ * @verbatim
+ ================================================================================
+ ##### How to use this driver #####
+ ================================================================================
+ [..]
+ The CORDIC HAL driver can be used as follows:
+
+ (#) Initialize the CORDIC low level resources by implementing the HAL_CORDIC_MspInit():
+ (++) Enable the CORDIC interface clock using __HAL_RCC_CORDIC_CLK_ENABLE()
+ (++) In case of using interrupts (e.g. HAL_CORDIC_Calculate_IT())
+ (+++) Configure the CORDIC interrupt priority using HAL_NVIC_SetPriority()
+ (+++) Enable the CORDIC IRQ handler using HAL_NVIC_EnableIRQ()
+ (+++) In CORDIC IRQ handler, call HAL_CORDIC_IRQHandler()
+ (++) In case of using DMA to control data transfer (e.g. HAL_CORDIC_Calculate_DMA())
+ (+++) Enable the DMA2 interface clock using
+ __HAL_RCC_DMA2_CLK_ENABLE()
+ (+++) Configure and enable two DMA channels one for managing data transfer from
+ memory to peripheral (input channel) and another channel for managing data
+ transfer from peripheral to memory (output channel)
+ (+++) Associate the initialized DMA handle to the CORDIC DMA handle
+ using __HAL_LINKDMA()
+ (+++) Configure the priority and enable the NVIC for the transfer complete
+ interrupt on the two DMA channels.
+ Resort to HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
+
+ (#) Initialize the CORDIC HAL using HAL_CORDIC_Init(). This function
+ (++) resorts to HAL_CORDIC_MspInit() for low-level initialization,
+
+ (#) Configure CORDIC processing (calculation) using HAL_CORDIC_Configure().
+ This function configures:
+ (++) Processing functions: Cosine, Sine, Phase, Modulus, Arctangent,
+ Hyperbolic cosine, Hyperbolic sine, Hyperbolic arctangent,
+ Natural log, Square root
+ (++) Scaling factor: 1 to 2exp(-7)
+ (++) Width of input data: 32 bits input data size (Q1.31 format) or 16 bits
+ input data size (Q1.15 format)
+ (++) Width of output data: 32 bits output data size (Q1.31 format) or 16 bits
+ output data size (Q1.15 format)
+ (++) Number of 32-bit write expected for one calculation: One 32-bits write
+ or Two 32-bit write
+ (++) Number of 32-bit read expected after one calculation: One 32-bits read
+ or Two 32-bit read
+ (++) Precision: 1 to 15 cycles for calculation (the more cycles, the better precision)
+
+ (#) Four processing (calculation) functions are available:
+ (++) Polling mode: processing API is blocking function
+ i.e. it processes the data and wait till the processing is finished
+ API is HAL_CORDIC_Calculate
+ (++) Polling Zero-overhead mode: processing API is blocking function
+ i.e. it processes the data and wait till the processing is finished
+ A bit faster than standard polling mode, but blocking also AHB bus
+ API is HAL_CORDIC_CalculateZO
+ (++) Interrupt mode: processing API is not blocking functions
+ i.e. it processes the data under interrupt
+ API is HAL_CORDIC_Calculate_IT
+ (++) DMA mode: processing API is not blocking functions and the CPU is
+ not used for data transfer,
+ i.e. the data transfer is ensured by DMA
+ API is HAL_CORDIC_Calculate_DMA
+
+ (#) Call HAL_CORDIC_DeInit() to de-initialize the CORDIC peripheral. This function
+ (++) resorts to HAL_CORDIC_MspDeInit() for low-level de-initialization,
+
+ *** Callback registration ***
+ =============================================
+
+ The compilation define USE_HAL_CORDIC_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Function @ref HAL_CORDIC_RegisterCallback() to register an interrupt callback.
+
+ Function @ref HAL_CORDIC_RegisterCallback() allows to register following callbacks:
+ (+) ErrorCallback : Error Callback.
+ (+) CalculateCpltCallback : Calculate complete Callback.
+ (+) MspInitCallback : CORDIC MspInit.
+ (+) MspDeInitCallback : CORDIC MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_CORDIC_UnRegisterCallback() to reset a callback to the default
+ weak function.
+ @ref HAL_CORDIC_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) ErrorCallback : Error Callback.
+ (+) CalculateCpltCallback : Calculate complete Callback.
+ (+) MspInitCallback : CORDIC MspInit.
+ (+) MspDeInitCallback : CORDIC MspDeInit.
+
+ By default, after the HAL_CORDIC_Init() and when the state is HAL_CORDIC_STATE_RESET,
+ all callbacks are set to the corresponding weak functions:
+ examples @ref HAL_CORDIC_ErrorCallback(), @ref HAL_CORDIC_CalculateCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak function in the HAL_CORDIC_Init()/ @ref HAL_CORDIC_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ if not, MspInit or MspDeInit are not null, the HAL_CORDIC_Init()/ @ref HAL_CORDIC_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in HAL_CORDIC_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_CORDIC_STATE_READY or HAL_CORDIC_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_CORDIC_RegisterCallback() before calling @ref HAL_CORDIC_DeInit()
+ or HAL_CORDIC_Init() function.
+
+ When The compilation define USE_HAL_CORDIC_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
+ @endverbatim
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+#if defined(CORDIC)
+#ifdef HAL_CORDIC_MODULE_ENABLED
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CORDIC CORDIC
+ * @brief CORDIC HAL driver modules.
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/** @defgroup CORDIC_Private_Functions CORDIC Private Functions
+ * @{
+ */
+static void CORDIC_WriteInDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_t **ppInBuff);
+static void CORDIC_ReadOutDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_t **ppOutBuff);
+static void CORDIC_DMAInCplt(DMA_HandleTypeDef *hdma);
+static void CORDIC_DMAOutCplt(DMA_HandleTypeDef *hdma);
+static void CORDIC_DMAError(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup CORDIC_Exported_Functions CORDIC Exported Functions
+ * @{
+ */
+
+/** @defgroup CORDIC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the CORDIC peripheral and the associated handle
+ (+) DeInitialize the CORDIC peripheral
+ (+) Initialize the CORDIC MSP (MCU Specific Package)
+ (+) De-Initialize the CORDIC MSP
+
+ [..]
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the CORDIC peripheral and the associated handle.
+ * @param hcordic pointer to a CORDIC_HandleTypeDef structure.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CORDIC_Init(CORDIC_HandleTypeDef *hcordic)
+{
+ /* Check the CORDIC handle allocation */
+ if (hcordic == NULL)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+
+ /* Check the instance */
+ assert_param(IS_CORDIC_ALL_INSTANCE(hcordic->Instance));
+
+#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
+ if (hcordic->State == HAL_CORDIC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hcordic->Lock = HAL_UNLOCKED;
+
+ /* Reset callbacks to legacy functions */
+ hcordic->ErrorCallback = HAL_CORDIC_ErrorCallback; /* Legacy weak ErrorCallback */
+ hcordic->CalculateCpltCallback = HAL_CORDIC_CalculateCpltCallback; /* Legacy weak CalculateCpltCallback */
+
+ if (hcordic->MspInitCallback == NULL)
+ {
+ hcordic->MspInitCallback = HAL_CORDIC_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Initialize the low level hardware */
+ hcordic->MspInitCallback(hcordic);
+ }
+#else
+ if (hcordic->State == HAL_CORDIC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hcordic->Lock = HAL_UNLOCKED;
+
+ /* Initialize the low level hardware */
+ HAL_CORDIC_MspInit(hcordic);
+ }
+#endif /* (USE_HAL_CORDIC_REGISTER_CALLBACKS) */
+
+ /* Set CORDIC error code to none */
+ hcordic->ErrorCode = HAL_CORDIC_ERROR_NONE;
+
+ /* Reset pInBuff and pOutBuff */
+ hcordic->pInBuff = NULL;
+ hcordic->pOutBuff = NULL;
+
+ /* Reset NbCalcToOrder and NbCalcToGet */
+ hcordic->NbCalcToOrder = 0U;
+ hcordic->NbCalcToGet = 0U;
+
+ /* Reset DMADirection */
+ hcordic->DMADirection = CORDIC_DMA_DIR_NONE;
+
+ /* Change CORDIC peripheral state */
+ hcordic->State = HAL_CORDIC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitialize the CORDIC peripheral.
+ * @param hcordic pointer to a CORDIC_HandleTypeDef structure.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CORDIC_DeInit(CORDIC_HandleTypeDef *hcordic)
+{
+ /* Check the CORDIC handle allocation */
+ if (hcordic == NULL)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CORDIC_ALL_INSTANCE(hcordic->Instance));
+
+ /* Change CORDIC peripheral state */
+ hcordic->State = HAL_CORDIC_STATE_BUSY;
+
+#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
+ if (hcordic->MspDeInitCallback == NULL)
+ {
+ hcordic->MspDeInitCallback = HAL_CORDIC_MspDeInit;
+ }
+
+ /* De-Initialize the low level hardware */
+ hcordic->MspDeInitCallback(hcordic);
+#else
+ /* De-Initialize the low level hardware: CLOCK, NVIC, DMA */
+ HAL_CORDIC_MspDeInit(hcordic);
+#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
+
+ /* Set CORDIC error code to none */
+ hcordic->ErrorCode = HAL_CORDIC_ERROR_NONE;
+
+ /* Reset pInBuff and pOutBuff */
+ hcordic->pInBuff = NULL;
+ hcordic->pOutBuff = NULL;
+
+ /* Reset NbCalcToOrder and NbCalcToGet */
+ hcordic->NbCalcToOrder = 0U;
+ hcordic->NbCalcToGet = 0U;
+
+ /* Reset DMADirection */
+ hcordic->DMADirection = CORDIC_DMA_DIR_NONE;
+
+ /* Change CORDIC peripheral state */
+ hcordic->State = HAL_CORDIC_STATE_RESET;
+
+ /* Reset Lock */
+ hcordic->Lock = HAL_UNLOCKED;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the CORDIC MSP.
+ * @param hcordic CORDIC handle
+ * @retval None
+ */
+__weak void HAL_CORDIC_MspInit(CORDIC_HandleTypeDef *hcordic)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcordic);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CORDIC_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the CORDIC MSP.
+ * @param hcordic CORDIC handle
+ * @retval None
+ */
+__weak void HAL_CORDIC_MspDeInit(CORDIC_HandleTypeDef *hcordic)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcordic);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CORDIC_MspDeInit can be implemented in the user file
+ */
+}
+
+#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
+/**
+ * @brief Register a CORDIC CallBack.
+ * To be used instead of the weak predefined callback.
+ * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
+ * the configuration information for CORDIC module
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_CORDIC_ERROR_CB_ID error Callback ID
+ * @arg @ref HAL_CORDIC_CALCULATE_CPLT_CB_ID calculate complete Callback ID
+ * @arg @ref HAL_CORDIC_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_CORDIC_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CORDIC_RegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID,
+ void (* pCallback)(CORDIC_HandleTypeDef *_hcordic))
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ return HAL_ERROR;
+ }
+
+ if (hcordic->State == HAL_CORDIC_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CORDIC_ERROR_CB_ID :
+ hcordic->ErrorCallback = pCallback;
+ break;
+
+ case HAL_CORDIC_CALCULATE_CPLT_CB_ID :
+ hcordic->CalculateCpltCallback = pCallback;
+ break;
+
+ case HAL_CORDIC_MSPINIT_CB_ID :
+ hcordic->MspInitCallback = pCallback;
+ break;
+
+ case HAL_CORDIC_MSPDEINIT_CB_ID :
+ hcordic->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hcordic->State == HAL_CORDIC_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CORDIC_MSPINIT_CB_ID :
+ hcordic->MspInitCallback = pCallback;
+ break;
+
+ case HAL_CORDIC_MSPDEINIT_CB_ID :
+ hcordic->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
+
+#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
+/**
+ * @brief Unregister a CORDIC CallBack.
+ * CORDIC callback is redirected to the weak predefined callback.
+ * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
+ * the configuration information for CORDIC module
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_CORDIC_ERROR_CB_ID error Callback ID
+ * @arg @ref HAL_CORDIC_CALCULATE_CPLT_CB_ID calculate complete Callback ID
+ * @arg @ref HAL_CORDIC_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_CORDIC_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CORDIC_UnRegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (hcordic->State == HAL_CORDIC_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CORDIC_ERROR_CB_ID :
+ hcordic->ErrorCallback = HAL_CORDIC_ErrorCallback;
+ break;
+
+ case HAL_CORDIC_CALCULATE_CPLT_CB_ID :
+ hcordic->CalculateCpltCallback = HAL_CORDIC_CalculateCpltCallback;
+ break;
+
+ case HAL_CORDIC_MSPINIT_CB_ID :
+ hcordic->MspInitCallback = HAL_CORDIC_MspInit;
+ break;
+
+ case HAL_CORDIC_MSPDEINIT_CB_ID :
+ hcordic->MspDeInitCallback = HAL_CORDIC_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hcordic->State == HAL_CORDIC_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CORDIC_MSPINIT_CB_ID :
+ hcordic->MspInitCallback = HAL_CORDIC_MspInit;
+ break;
+
+ case HAL_CORDIC_MSPDEINIT_CB_ID :
+ hcordic->MspDeInitCallback = HAL_CORDIC_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_Exported_Functions_Group2 Peripheral Control functions
+ * @brief Control functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure the CORDIC peripheral: function, precision, scaling factor,
+ number of input data and output data, size of input data and output data.
+ (+) Calculate output data of CORDIC processing on input date, using the
+ existing CORDIC configuration
+ [..] Four processing functions are available for calculation:
+ (+) Polling mode
+ (+) Polling mode, with Zero-Overhead register access
+ (+) Interrupt mode
+ (+) DMA mode
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the CORDIC processing according to the specified
+ parameters in the CORDIC_ConfigTypeDef structure.
+ * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
+ * the configuration information for CORDIC module
+ * @param sConfig pointer to a CORDIC_ConfigTypeDef structure that
+ * contains the CORDIC configuration information.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, CORDIC_ConfigTypeDef *sConfig)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_CORDIC_FUNCTION(sConfig->Function));
+ assert_param(IS_CORDIC_PRECISION(sConfig->Precision));
+ assert_param(IS_CORDIC_SCALE(sConfig->Scale));
+ assert_param(IS_CORDIC_NBWRITE(sConfig->NbWrite));
+ assert_param(IS_CORDIC_NBREAD(sConfig->NbRead));
+ assert_param(IS_CORDIC_INSIZE(sConfig->InSize));
+ assert_param(IS_CORDIC_OUTSIZE(sConfig->OutSize));
+
+ /* Check handle state is ready */
+ if (hcordic->State == HAL_CORDIC_STATE_READY)
+ {
+ /* Apply all configuration parameters in CORDIC control register */
+ MODIFY_REG(hcordic->Instance->CSR, \
+ (CORDIC_CSR_FUNC | CORDIC_CSR_PRECISION | CORDIC_CSR_SCALE | \
+ CORDIC_CSR_NARGS | CORDIC_CSR_NRES | CORDIC_CSR_ARGSIZE | CORDIC_CSR_RESSIZE), \
+ (sConfig->Function | sConfig->Precision | sConfig->Scale | \
+ sConfig->NbWrite | sConfig->NbRead | sConfig->InSize | sConfig->OutSize));
+ }
+ else
+ {
+ /* Set CORDIC error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_NOT_READY;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Carry out data of CORDIC processing in polling mode,
+ * according to the existing CORDIC configuration.
+ * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
+ * the configuration information for CORDIC module.
+ * @param pInBuff Pointer to buffer containing input data for CORDIC processing.
+ * @param pOutBuff Pointer to buffer where output data of CORDIC processing will be stored.
+ * @param NbCalc Number of CORDIC calculation to process.
+ * @param Timeout Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
+ uint32_t NbCalc, uint32_t Timeout)
+{
+ uint32_t tickstart;
+ uint32_t index;
+ int32_t *p_tmp_in_buff = pInBuff;
+ int32_t *p_tmp_out_buff = pOutBuff;
+
+ /* Check parameters setting */
+ if ((pInBuff == NULL) || (pOutBuff == NULL) || (NbCalc == 0U))
+ {
+ /* Update the error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_PARAM;
+
+ /* Return error status */
+ return HAL_ERROR;
+ }
+
+ /* Check handle state is ready */
+ if (hcordic->State == HAL_CORDIC_STATE_READY)
+ {
+ /* Reset CORDIC error code */
+ hcordic->ErrorCode = HAL_CORDIC_ERROR_NONE;
+
+ /* Change the CORDIC state */
+ hcordic->State = HAL_CORDIC_STATE_BUSY;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Write of input data in Write Data register, and increment input buffer pointer */
+ CORDIC_WriteInDataIncrementPtr(hcordic, &p_tmp_in_buff);
+
+ /* Calculation is started.
+ Provide next set of input data, until number of calculation is achieved */
+ for (index = (NbCalc - 1U); index > 0U; index--)
+ {
+ /* Write of input data in Write Data register, and increment input buffer pointer */
+ CORDIC_WriteInDataIncrementPtr(hcordic, &p_tmp_in_buff);
+
+ /* Wait for RRDY flag to be raised */
+ do
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if ((HAL_GetTick() - tickstart) > Timeout)
+ {
+ /* Set CORDIC error code */
+ hcordic->ErrorCode = HAL_CORDIC_ERROR_TIMEOUT;
+
+ /* Change the CORDIC state */
+ hcordic->State = HAL_CORDIC_STATE_READY;
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+ }
+ } while (HAL_IS_BIT_CLR(hcordic->Instance->CSR, CORDIC_CSR_RRDY));
+
+ /* Read output data from Read Data register, and increment output buffer pointer */
+ CORDIC_ReadOutDataIncrementPtr(hcordic, &p_tmp_out_buff);
+ }
+
+ /* Read output data from Read Data register, and increment output buffer pointer */
+ CORDIC_ReadOutDataIncrementPtr(hcordic, &p_tmp_out_buff);
+
+ /* Change the CORDIC state */
+ hcordic->State = HAL_CORDIC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Set CORDIC error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_NOT_READY;
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Carry out data of CORDIC processing in Zero-Overhead mode (output data being read
+ * soon as input data are written), according to the existing CORDIC configuration.
+ * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
+ * the configuration information for CORDIC module.
+ * @param pInBuff Pointer to buffer containing input data for CORDIC processing.
+ * @param pOutBuff Pointer to buffer where output data of CORDIC processing will be stored.
+ * @param NbCalc Number of CORDIC calculation to process.
+ * @param Timeout Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
+ uint32_t NbCalc, uint32_t Timeout)
+{
+ uint32_t tickstart;
+ uint32_t index;
+ int32_t *p_tmp_in_buff = pInBuff;
+ int32_t *p_tmp_out_buff = pOutBuff;
+
+ /* Check parameters setting */
+ if ((pInBuff == NULL) || (pOutBuff == NULL) || (NbCalc == 0U))
+ {
+ /* Update the error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_PARAM;
+
+ /* Return error status */
+ return HAL_ERROR;
+ }
+
+ /* Check handle state is ready */
+ if (hcordic->State == HAL_CORDIC_STATE_READY)
+ {
+ /* Reset CORDIC error code */
+ hcordic->ErrorCode = HAL_CORDIC_ERROR_NONE;
+
+ /* Change the CORDIC state */
+ hcordic->State = HAL_CORDIC_STATE_BUSY;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Write of input data in Write Data register, and increment input buffer pointer */
+ CORDIC_WriteInDataIncrementPtr(hcordic, &p_tmp_in_buff);
+
+ /* Calculation is started.
+ Provide next set of input data, until number of calculation is achieved */
+ for (index = (NbCalc - 1U); index > 0U; index--)
+ {
+ /* Write of input data in Write Data register, and increment input buffer pointer */
+ CORDIC_WriteInDataIncrementPtr(hcordic, &p_tmp_in_buff);
+
+ /* Read output data from Read Data register, and increment output buffer pointer
+ The reading is performed in Zero-Overhead mode:
+ reading is ordered immediately without waiting result ready flag */
+ CORDIC_ReadOutDataIncrementPtr(hcordic, &p_tmp_out_buff);
+
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if ((HAL_GetTick() - tickstart) > Timeout)
+ {
+ /* Set CORDIC error code */
+ hcordic->ErrorCode = HAL_CORDIC_ERROR_TIMEOUT;
+
+ /* Change the CORDIC state */
+ hcordic->State = HAL_CORDIC_STATE_READY;
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Read output data from Read Data register, and increment output buffer pointer
+ The reading is performed in Zero-Overhead mode:
+ reading is ordered immediately without waiting result ready flag */
+ CORDIC_ReadOutDataIncrementPtr(hcordic, &p_tmp_out_buff);
+
+ /* Change the CORDIC state */
+ hcordic->State = HAL_CORDIC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Set CORDIC error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_NOT_READY;
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Carry out data of CORDIC processing in interrupt mode,
+ * according to the existing CORDIC configuration.
+ * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
+ * the configuration information for CORDIC module.
+ * @param pInBuff Pointer to buffer containing input data for CORDIC processing.
+ * @param pOutBuff Pointer to buffer where output data of CORDIC processing will be stored.
+ * @param NbCalc Number of CORDIC calculation to process.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
+ uint32_t NbCalc)
+{
+ int32_t *tmp_pInBuff = pInBuff;
+
+ /* Check parameters setting */
+ if ((pInBuff == NULL) || (pOutBuff == NULL) || (NbCalc == 0U))
+ {
+ /* Update the error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_PARAM;
+
+ /* Return error status */
+ return HAL_ERROR;
+ }
+
+ /* Check handle state is ready */
+ if (hcordic->State == HAL_CORDIC_STATE_READY)
+ {
+ /* Reset CORDIC error code */
+ hcordic->ErrorCode = HAL_CORDIC_ERROR_NONE;
+
+ /* Change the CORDIC state */
+ hcordic->State = HAL_CORDIC_STATE_BUSY;
+
+ /* Store the buffers addresses and number of calculations in handle,
+ provisioning initial write of input data that will be done */
+ if (HAL_IS_BIT_SET(hcordic->Instance->CSR, CORDIC_CSR_NARGS))
+ {
+ /* Two writes of input data are expected */
+ tmp_pInBuff++;
+ tmp_pInBuff++;
+ }
+ else
+ {
+ /* One write of input data is expected */
+ tmp_pInBuff++;
+ }
+ hcordic->pInBuff = tmp_pInBuff;
+ hcordic->pOutBuff = pOutBuff;
+ hcordic->NbCalcToOrder = NbCalc - 1U;
+ hcordic->NbCalcToGet = NbCalc;
+
+ /* Enable Result Ready Interrupt */
+ __HAL_CORDIC_ENABLE_IT(hcordic, CORDIC_IT_IEN);
+
+ /* Set back pointer to start of input data buffer */
+ tmp_pInBuff = pInBuff;
+
+ /* Initiate the processing by providing input data
+ in the Write Data register */
+ WRITE_REG(hcordic->Instance->WDATA, (uint32_t)*tmp_pInBuff);
+
+ /* Check if second write of input data is expected */
+ if (HAL_IS_BIT_SET(hcordic->Instance->CSR, CORDIC_CSR_NARGS))
+ {
+ /* Increment pointer to input data */
+ tmp_pInBuff++;
+
+ /* Perform second write of input data */
+ WRITE_REG(hcordic->Instance->WDATA, (uint32_t)*tmp_pInBuff);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Set CORDIC error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_NOT_READY;
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Carry out input and/or output data of CORDIC processing in DMA mode,
+ * according to the existing CORDIC configuration.
+ * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
+ * the configuration information for CORDIC module.
+ * @param pInBuff Pointer to buffer containing input data for CORDIC processing.
+ * @param pOutBuff Pointer to buffer where output data of CORDIC processing will be stored.
+ * @param NbCalc Number of CORDIC calculation to process.
+ * @param DMADirection Direction of DMA transfers.
+ * This parameter can be one of the following values:
+ * @arg @ref CORDIC_DMA_Direction CORDIC DMA direction
+ * @note pInBuff or pOutBuff is unused in case of unique DMADirection transfer, and can
+ * be set to NULL value in this case.
+ * @note pInBuff and pOutBuff buffers must be 32-bit aligned to ensure a correct
+ * DMA transfer to and from the Peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
+ uint32_t NbCalc, uint32_t DMADirection)
+{
+ HAL_StatusTypeDef status;
+ uint32_t sizeinbuff;
+ uint32_t sizeoutbuff;
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ /* Check the parameters */
+ assert_param(IS_CORDIC_DMA_DIRECTION(DMADirection));
+
+ /* Check parameters setting */
+ if (NbCalc == 0U)
+ {
+ /* Update the error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_PARAM;
+
+ /* Return error status */
+ return HAL_ERROR;
+ }
+
+ /* Check if CORDIC DMA direction "Out" is requested */
+ if ((DMADirection == CORDIC_DMA_DIR_OUT) || (DMADirection == CORDIC_DMA_DIR_IN_OUT))
+ {
+ /* Check parameters setting */
+ if (pOutBuff == NULL)
+ {
+ /* Update the error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_PARAM;
+
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ }
+
+ /* Check if CORDIC DMA direction "In" is requested */
+ if ((DMADirection == CORDIC_DMA_DIR_IN) || (DMADirection == CORDIC_DMA_DIR_IN_OUT))
+ {
+ /* Check parameters setting */
+ if (pInBuff == NULL)
+ {
+ /* Update the error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_PARAM;
+
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ }
+
+ if (hcordic->State == HAL_CORDIC_STATE_READY)
+ {
+ /* Reset CORDIC error code */
+ hcordic->ErrorCode = HAL_CORDIC_ERROR_NONE;
+
+ /* Change the CORDIC state */
+ hcordic->State = HAL_CORDIC_STATE_BUSY;
+
+ /* Get DMA direction */
+ hcordic->DMADirection = DMADirection;
+
+ /* Check if CORDIC DMA direction "Out" is requested */
+ if ((DMADirection == CORDIC_DMA_DIR_OUT) || (DMADirection == CORDIC_DMA_DIR_IN_OUT))
+ {
+ /* Set the CORDIC DMA transfer complete callback */
+ hcordic->hdmaOut->XferCpltCallback = CORDIC_DMAOutCplt;
+ /* Set the DMA error callback */
+ hcordic->hdmaOut->XferErrorCallback = CORDIC_DMAError;
+
+ /* Check number of output data at each calculation,
+ to retrieve the size of output data buffer */
+ if (HAL_IS_BIT_SET(hcordic->Instance->CSR, CORDIC_CSR_NRES))
+ {
+ sizeoutbuff = 2U * NbCalc;
+ }
+ else
+ {
+ sizeoutbuff = NbCalc;
+ }
+
+ /* Convert the output buffer size into corresponding number of bytes.
+ This is necessary as the DMA handles the data at byte-level. */
+ sizeoutbuff = 4U * sizeoutbuff;
+
+ outputaddr = (uint32_t)pOutBuff;
+
+ /* Enable the DMA stream managing CORDIC output data read */
+
+ if ((hcordic->hdmaOut->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if ((hcordic->hdmaOut->LinkedListQueue != NULL) && (hcordic->hdmaOut->LinkedListQueue->Head != NULL))
+ {
+ /* Enable the DMA channel */
+ hcordic->hdmaOut->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] =
+ sizeoutbuff; /* Set DMA data size */
+ hcordic->hdmaOut->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
+ (uint32_t)&hcordic->Instance->RDATA; /* Set DMA source address */
+ hcordic->hdmaOut->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
+ outputaddr; /* Set DMA destination address */
+
+ status = HAL_DMAEx_List_Start_IT(hcordic->hdmaOut);
+ }
+ else
+ {
+ /* Update the error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_DMA;
+
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_DMA_Start_IT(hcordic->hdmaOut, (uint32_t)&hcordic->Instance->RDATA, outputaddr, sizeoutbuff);
+ }
+
+ if (status != HAL_OK)
+ {
+ /* Update the error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_DMA;
+ /* Return error status */
+ return HAL_ERROR;
+ }
+
+ /* Enable output data Read DMA requests */
+ SET_BIT(hcordic->Instance->CSR, CORDIC_DMA_REN);
+ }
+
+ /* Check if CORDIC DMA direction "In" is requested */
+ if ((DMADirection == CORDIC_DMA_DIR_IN) || (DMADirection == CORDIC_DMA_DIR_IN_OUT))
+ {
+ /* Set the CORDIC DMA transfer complete callback */
+ hcordic->hdmaIn->XferCpltCallback = CORDIC_DMAInCplt;
+ /* Set the DMA error callback */
+ hcordic->hdmaIn->XferErrorCallback = CORDIC_DMAError;
+
+ /* Check number of input data expected for each calculation,
+ to retrieve the size of input data buffer */
+ if (HAL_IS_BIT_SET(hcordic->Instance->CSR, CORDIC_CSR_NARGS))
+ {
+ sizeinbuff = 2U * NbCalc;
+ }
+ else
+ {
+ sizeinbuff = NbCalc;
+ }
+
+ /* Convert the input buffer size into corresponding number of bytes.
+ This is necessary as the DMA handles the data at byte-level. */
+ sizeinbuff = 4U * sizeinbuff;
+
+ inputaddr = (uint32_t)pInBuff;
+
+ /* Enable the DMA stream managing CORDIC input data write */
+ if ((hcordic->hdmaIn->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if ((hcordic->hdmaIn->LinkedListQueue != NULL) && (hcordic->hdmaIn->LinkedListQueue->Head != NULL))
+ {
+ /* Enable the DMA channel */
+ hcordic->hdmaIn->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] =
+ sizeinbuff; /* Set DMA data size */
+ hcordic->hdmaIn->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
+ inputaddr; /* Set DMA source address */
+ hcordic->hdmaIn->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
+ (uint32_t)&hcordic->Instance->WDATA; /* Set DMA destination address */
+
+ status = HAL_DMAEx_List_Start_IT(hcordic->hdmaIn);
+ }
+ else
+ {
+ /* Update the error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_DMA;
+
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_DMA_Start_IT(hcordic->hdmaIn, inputaddr, (uint32_t)&hcordic->Instance->WDATA, sizeinbuff);
+ }
+
+ if (status != HAL_OK)
+ {
+ /* Update the error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_DMA;
+
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable input data Write DMA request */
+ SET_BIT(hcordic->Instance->CSR, CORDIC_DMA_WEN);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Set CORDIC error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_NOT_READY;
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_Exported_Functions_Group3 Callback functions
+ * @brief Callback functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Callback functions #####
+ ==============================================================================
+ [..] This section provides Interruption and DMA callback functions:
+ (+) DMA or Interrupt calculate complete
+ (+) DMA or Interrupt error
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief CORDIC error callback.
+ * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
+ * the configuration information for CORDIC module
+ * @retval None
+ */
+__weak void HAL_CORDIC_ErrorCallback(CORDIC_HandleTypeDef *hcordic)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcordic);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_CORDIC_ErrorCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief CORDIC calculate complete callback.
+ * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
+ * the configuration information for CORDIC module
+ * @retval None
+ */
+__weak void HAL_CORDIC_CalculateCpltCallback(CORDIC_HandleTypeDef *hcordic)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcordic);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_CORDIC_CalculateCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_Exported_Functions_Group4 IRQ handler management
+ * @brief IRQ handler.
+ *
+@verbatim
+ ==============================================================================
+ ##### IRQ handler management #####
+ ==============================================================================
+[..] This section provides IRQ handler function.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Handle CORDIC interrupt request.
+ * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
+ * the configuration information for CORDIC module
+ * @retval None
+ */
+void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic)
+{
+ /* Check if calculation complete interrupt is enabled and if result ready
+ flag is raised */
+ if (__HAL_CORDIC_GET_IT_SOURCE(hcordic, CORDIC_IT_IEN) != 0U)
+ {
+ if (__HAL_CORDIC_GET_FLAG(hcordic, CORDIC_FLAG_RRDY) != 0U)
+ {
+ /* Decrement number of calculations to get */
+ hcordic->NbCalcToGet--;
+
+ /* Read output data from Read Data register, and increment output buffer pointer */
+ CORDIC_ReadOutDataIncrementPtr(hcordic, &(hcordic->pOutBuff));
+
+ /* Check if calculations are still to be ordered */
+ if (hcordic->NbCalcToOrder > 0U)
+ {
+ /* Decrement number of calculations to order */
+ hcordic->NbCalcToOrder--;
+
+ /* Continue the processing by providing another write of input data
+ in the Write Data register, and increment input buffer pointer */
+ CORDIC_WriteInDataIncrementPtr(hcordic, &(hcordic->pInBuff));
+ }
+
+ /* Check if all calculations results are got */
+ if (hcordic->NbCalcToGet == 0U)
+ {
+ /* Disable Result Ready Interrupt */
+ __HAL_CORDIC_DISABLE_IT(hcordic, CORDIC_IT_IEN);
+
+ /* Change the CORDIC state */
+ hcordic->State = HAL_CORDIC_STATE_READY;
+
+ /* Call calculation complete callback */
+#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
+ /*Call registered callback*/
+ hcordic->CalculateCpltCallback(hcordic);
+#else
+ /*Call legacy weak (surcharged) callback*/
+ HAL_CORDIC_CalculateCpltCallback(hcordic);
+#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
+ }
+ }
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_Exported_Functions_Group5 Peripheral State functions
+ * @brief Peripheral State functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the CORDIC handle state.
+ * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
+ * the configuration information for CORDIC module
+ * @retval HAL state
+ */
+HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(CORDIC_HandleTypeDef *hcordic)
+{
+ /* Return CORDIC handle state */
+ return hcordic->State;
+}
+
+/**
+ * @brief Return the CORDIC peripheral error.
+ * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
+ * the configuration information for CORDIC module
+ * @note The returned error is a bit-map combination of possible errors
+ * @retval Error bit-map
+ */
+uint32_t HAL_CORDIC_GetError(CORDIC_HandleTypeDef *hcordic)
+{
+ /* Return CORDIC error code */
+ return hcordic->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CORDIC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Write input data for CORDIC processing, and increment input buffer pointer.
+ * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
+ * the configuration information for CORDIC module.
+ * @param ppInBuff Pointer to pointer to input buffer.
+ * @retval none
+ */
+static void CORDIC_WriteInDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_t **ppInBuff)
+{
+ /* First write of input data in the Write Data register */
+ WRITE_REG(hcordic->Instance->WDATA, (uint32_t) **ppInBuff);
+
+ /* Increment input data pointer */
+ (*ppInBuff)++;
+
+ /* Check if second write of input data is expected */
+ if (HAL_IS_BIT_SET(hcordic->Instance->CSR, CORDIC_CSR_NARGS))
+ {
+ /* Second write of input data in the Write Data register */
+ WRITE_REG(hcordic->Instance->WDATA, (uint32_t) **ppInBuff);
+
+ /* Increment input data pointer */
+ (*ppInBuff)++;
+ }
+}
+
+/**
+ * @brief Read output data of CORDIC processing, and increment output buffer pointer.
+ * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
+ * the configuration information for CORDIC module.
+ * @param ppOutBuff Pointer to pointer to output buffer.
+ * @retval none
+ */
+static void CORDIC_ReadOutDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_t **ppOutBuff)
+{
+ /* First read of output data from the Read Data register */
+ **ppOutBuff = (int32_t)READ_REG(hcordic->Instance->RDATA);
+
+ /* Increment output data pointer */
+ (*ppOutBuff)++;
+
+ /* Check if second read of output data is expected */
+ if (HAL_IS_BIT_SET(hcordic->Instance->CSR, CORDIC_CSR_NRES))
+ {
+ /* Second read of output data from the Read Data register */
+ **ppOutBuff = (int32_t)READ_REG(hcordic->Instance->RDATA);
+
+ /* Increment output data pointer */
+ (*ppOutBuff)++;
+ }
+}
+
+/**
+ * @brief DMA CORDIC Input Data process complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void CORDIC_DMAInCplt(DMA_HandleTypeDef *hdma)
+{
+ CORDIC_HandleTypeDef *hcordic = (CORDIC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Disable the DMA transfer for input request */
+ CLEAR_BIT(hcordic->Instance->CSR, CORDIC_DMA_WEN);
+
+ /* Check if DMA direction is CORDIC Input only (no DMA for CORDIC Output) */
+ if (hcordic->DMADirection == CORDIC_DMA_DIR_IN)
+ {
+ /* Change the CORDIC DMA direction to none */
+ hcordic->DMADirection = CORDIC_DMA_DIR_NONE;
+
+ /* Change the CORDIC state to ready */
+ hcordic->State = HAL_CORDIC_STATE_READY;
+
+ /* Call calculation complete callback */
+#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
+ /*Call registered callback*/
+ hcordic->CalculateCpltCallback(hcordic);
+#else
+ /*Call legacy weak (surcharged) callback*/
+ HAL_CORDIC_CalculateCpltCallback(hcordic);
+#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief DMA CORDIC Output Data process complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void CORDIC_DMAOutCplt(DMA_HandleTypeDef *hdma)
+{
+ CORDIC_HandleTypeDef *hcordic = (CORDIC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Disable the DMA transfer for output request */
+ CLEAR_BIT(hcordic->Instance->CSR, CORDIC_DMA_REN);
+
+ /* Change the CORDIC DMA direction to none */
+ hcordic->DMADirection = CORDIC_DMA_DIR_NONE;
+
+ /* Change the CORDIC state to ready */
+ hcordic->State = HAL_CORDIC_STATE_READY;
+
+ /* Call calculation complete callback */
+#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
+ /*Call registered callback*/
+ hcordic->CalculateCpltCallback(hcordic);
+#else
+ /*Call legacy weak (surcharged) callback*/
+ HAL_CORDIC_CalculateCpltCallback(hcordic);
+#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA CORDIC communication error callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void CORDIC_DMAError(DMA_HandleTypeDef *hdma)
+{
+ CORDIC_HandleTypeDef *hcordic = (CORDIC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Set CORDIC handle state to error */
+ hcordic->State = HAL_CORDIC_STATE_READY;
+
+ /* Set CORDIC handle error code to DMA error */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_DMA;
+
+ /* Call user callback */
+#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
+ /*Call registered callback*/
+ hcordic->ErrorCallback(hcordic);
+#else
+ /*Call legacy weak (surcharged) callback*/
+ HAL_CORDIC_ErrorCallback(hcordic);
+#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_CORDIC_MODULE_ENABLED */
+#endif /* CORDIC */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cortex.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cortex.c
new file mode 100644
index 00000000..76e529ba
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cortex.c
@@ -0,0 +1,680 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_cortex.c
+ * @author MCD Application Team
+ * @brief CORTEX HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the CORTEX:
+ * + Initialization and Configuration functions
+ * + Peripheral Control functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+
+ [..]
+ *** How to configure Interrupts using CORTEX HAL driver ***
+ ===========================================================
+ [..]
+ This section provides functions allowing to configure the NVIC interrupts (IRQ).
+ The Cortex-M33 exceptions are managed by CMSIS functions.
+
+ (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function.
+ (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
+ (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
+
+ -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
+ The pending IRQ priority will be managed only by the sub priority.
+
+ -@- IRQ priority order (sorted by highest to lowest priority):
+ (+@) Lowest pre-emption priority
+ (+@) Lowest sub priority
+ (+@) Lowest hardware priority (IRQ number)
+
+ [..]
+ *** How to configure SysTick using CORTEX HAL driver ***
+ ========================================================
+ [..]
+ Setup SysTick Timer for time base.
+
+ (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
+ is a CMSIS function that:
+ (++) Configures the SysTick Reload register with value passed as function parameter.
+ (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
+ (++) Resets the SysTick Counter register.
+ (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
+ (++) Enables the SysTick Interrupt.
+ (++) Starts the SysTick Counter.
+
+ (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
+ __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
+ HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
+ inside the stm32u5xx_hal_cortex.h file.
+
+ (+) You can change the SysTick IRQ priority by calling the
+ HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
+ call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
+
+ (+) To adjust the SysTick time base, use the following formula:
+
+ Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
+ (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
+ (++) Reload Value should not exceed 0xFFFFFF
+
+ [..]
+ *** How to configure MPU (secure and non secure) using CORTEX HAL driver ***
+ ===========================================================
+ [..]
+ This section provides functions allowing to Enable and configure the MPU secure and non-secure.
+
+ (#) Enable the MPU using HAL_MPU_Enable() function.
+ (#) Disable the MPU using HAL_MPU_Disable() function.
+ (#) Enable the MPU using HAL_MPU_Enable_NS() function to address the non secure MPU.
+ (#) Disable the MPU using HAL_MPU_Disable_NS() function to address the non secure MPU.
+ (#) Configure the MPU region using HAL_MPU_ConfigRegion()
+ and HAL_MPU_ConfigRegion_NS() to address the non secure MPU.
+ (#) Configure the MPU Memory attributes using HAL_MPU_ConfigMemoryAttributes()
+ and HAL_MPU_ConfigMemoryAttributes_NS() to address the non secure MPU.
+
+ @endverbatim
+ ******************************************************************************
+
+ The table below gives the allowed values of the pre-emption priority and subpriority according
+ to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
+
+========================================================================================================================
+ NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
+========================================================================================================================
+ NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bit for pre-emption priority
+ | | | 4 bits for subpriority
+------------------------------------------------------------------------------------------------------------------------
+ NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bit for pre-emption priority
+ | | | 3 bits for subpriority
+------------------------------------------------------------------------------------------------------------------------
+ NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
+ | | | 2 bits for subpriority
+------------------------------------------------------------------------------------------------------------------------
+ NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
+ | | | 1 bit for subpriority
+------------------------------------------------------------------------------------------------------------------------
+ NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority
+ | | | 0 bit for subpriority
+========================================================================================================================
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CORTEX
+ * @{
+ */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CORTEX_Private_Functions CORTEX Private Functions
+ * @{
+ */
+static void MPU_ConfigRegion(MPU_Type *MPUx, const MPU_Region_InitTypeDef *const pMPU_RegionInit);
+static void MPU_ConfigMemoryAttributes(MPU_Type *MPUx, const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit);
+/**
+ * @}
+ */
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup CORTEX_Exported_Functions
+ * @{
+ */
+
+
+/** @addtogroup CORTEX_Exported_Functions_Group1
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and Configuration functions #####
+ ==============================================================================
+ [..]
+ This section provides the CORTEX HAL driver functions allowing to configure Interrupts
+ SysTick functionalities
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Set the priority grouping field (pre-emption priority and subpriority)
+ * using the required unlock sequence.
+ * @param PriorityGroup: The priority grouping bits length.
+ * This parameter can be one of the following values:
+ * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
+ * 4 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
+ * 3 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
+ * 2 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
+ * 1 bit for subpriority
+ * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
+ * 0 bit for subpriority
+ * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
+ * The pending IRQ priority will be managed only by the subpriority.
+ * @retval None
+ */
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+
+ /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
+ NVIC_SetPriorityGrouping(PriorityGroup);
+}
+
+/**
+ * @brief Set the priority of an interrupt.
+ * @param IRQn: External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
+ * CMSIS device file (stm32u5xxxx.h))
+ * @param PreemptPriority: The pre-emption priority for the IRQn channel.
+ * This parameter can be a value between 0 and 15
+ * A lower priority value indicates a higher priority
+ * @param SubPriority: the subpriority level for the IRQ channel.
+ * This parameter can be a value between 0 and 15
+ * A lower priority value indicates a higher priority.
+ * @retval None
+ */
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t prioritygroup;
+
+ /* Check the parameters */
+ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
+
+ prioritygroup = NVIC_GetPriorityGrouping();
+
+ NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
+}
+
+/**
+ * @brief Enable a device specific interrupt in the NVIC interrupt controller.
+ * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
+ * function should be called before.
+ * @param IRQn External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
+ * CMSIS device file (stm32u5xxxx.h))
+ * @retval None
+ */
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+ /* Enable interrupt */
+ NVIC_EnableIRQ(IRQn);
+}
+
+/**
+ * @brief Disable a device specific interrupt in the NVIC interrupt controller.
+ * @param IRQn External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
+ * CMSIS device file (stm32u5xxxx.h))
+ * @retval None
+ */
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+ /* Disable interrupt */
+ NVIC_DisableIRQ(IRQn);
+}
+
+/**
+ * @brief Initiate a system reset request to reset the MCU.
+ * @retval None
+ */
+void HAL_NVIC_SystemReset(void)
+{
+ /* System Reset */
+ NVIC_SystemReset();
+}
+
+/**
+ * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick):
+ * Counter is in free running mode to generate periodic interrupts.
+ * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
+ * @retval status: - 0 Function succeeded.
+ * - 1 Function failed.
+ */
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
+{
+ return SysTick_Config(TicksNumb);
+}
+/**
+ * @}
+ */
+
+/** @addtogroup CORTEX_Exported_Functions_Group2
+ * @brief Cortex control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the CORTEX
+ (NVIC, SYSTICK, MPU) functionalities.
+
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Get the priority grouping field from the NVIC Interrupt Controller.
+ * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
+ */
+uint32_t HAL_NVIC_GetPriorityGrouping(void)
+{
+ /* Get the PRIGROUP[10:8] field value */
+ return NVIC_GetPriorityGrouping();
+}
+
+/**
+ * @brief Get the priority of an interrupt.
+ * @param IRQn: External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
+ * CMSIS device file (stm32u5xxxx.h))
+ * @param PriorityGroup: the priority grouping bits length.
+ * This parameter can be one of the following values:
+ * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
+ * 4 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
+ * 3 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
+ * 2 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
+ * 1 bit for subpriority
+ * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
+ * 0 bit for subpriority
+ * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
+ * @param pSubPriority: Pointer on the Subpriority value (starting from 0).
+ * @retval None
+ */
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *const pPreemptPriority,
+ uint32_t *const pSubPriority)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+ /* Get priority for Cortex-M system or device specific interrupts */
+ NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
+}
+
+/**
+ * @brief Set Pending bit of an external interrupt.
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
+ * CMSIS device file (stm32u5xxxx.h))
+ * @retval None
+ */
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ /* Set interrupt pending */
+ NVIC_SetPendingIRQ(IRQn);
+}
+
+/**
+ * @brief Get Pending Interrupt (read the pending register in the NVIC
+ * and return the pending bit for the specified interrupt).
+ * @param IRQn External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
+ * CMSIS device file (stm32u5xxxx.h))
+ * @retval status: - 0 Interrupt status is not pending.
+ * - 1 Interrupt status is pending.
+ */
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ /* Return 1 if pending else 0 */
+ return NVIC_GetPendingIRQ(IRQn);
+}
+
+/**
+ * @brief Clear the pending bit of an external interrupt.
+ * @param IRQn External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
+ * CMSIS device file (stm32u5xxxx.h))
+ * @retval None
+ */
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ /* Clear pending interrupt */
+ NVIC_ClearPendingIRQ(IRQn);
+}
+
+/**
+ * @brief Get active interrupt (read the active register in NVIC and return the active bit).
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
+ * CMSIS device file (stm32u5xxxx.h))
+ * @retval status: - 0 Interrupt status is not pending.
+ * - 1 Interrupt status is pending.
+ */
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
+{
+ /* Return 1 if active else 0 */
+ return NVIC_GetActive(IRQn);
+}
+
+/**
+ * @brief Configure the SysTick clock source.
+ * @param CLKSource: specifies the SysTick clock source.
+ * This parameter can be one of the following values:
+ * @arg SYSTICK_CLKSOURCE_LSI: LSI clock selected as SysTick clock source.
+ * @arg SYSTICK_CLKSOURCE_LSE: LSE clock selected as SysTick clock source.
+ * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
+ * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
+ * @retval None
+ */
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
+ switch (CLKSource)
+ {
+ /* Select HCLK as Systick clock source */
+ case SYSTICK_CLKSOURCE_HCLK:
+ SET_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk);
+ break;
+ /* Select HCLK_DIV8 as Systick clock source */
+ case SYSTICK_CLKSOURCE_HCLK_DIV8:
+ CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk);
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, (0x00000000U));
+ break;
+ /* Select LSI as Systick clock source */
+ case SYSTICK_CLKSOURCE_LSI:
+ CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk);
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, RCC_CCIPR1_SYSTICKSEL_0);
+ break;
+ /* Select LSE as Systick clock source */
+ case SYSTICK_CLKSOURCE_LSE:
+ CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk);
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, RCC_CCIPR1_SYSTICKSEL_1);
+ break;
+ default:
+ /* Nothing to do */
+ break;
+ }
+}
+
+/**
+ * @brief Handle SYSTICK interrupt request.
+ * @retval None
+ */
+void HAL_SYSTICK_IRQHandler(void)
+{
+ HAL_SYSTICK_Callback();
+}
+
+/**
+ * @brief SYSTICK callback.
+ * @retval None
+ */
+__weak void HAL_SYSTICK_Callback(void)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SYSTICK_Callback could be implemented in the user file
+ */
+}
+
+
+/**
+ * @brief Enable the MPU.
+ * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
+ * NMI, FAULTMASK and privileged access to the default memory
+ * This parameter can be one of the following values:
+ * @arg MPU_HFNMI_PRIVDEF_NONE
+ * @arg MPU_HARDFAULT_NMI
+ * @arg MPU_PRIVILEGED_DEFAULT
+ * @arg MPU_HFNMI_PRIVDEF
+ * @retval None
+ */
+void HAL_MPU_Enable(uint32_t MPU_Control)
+{
+ /* Enable the MPU */
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+
+ /* Enable fault exceptions */
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+
+ /* Follow ARM recommendation with */
+ /* - Data Memory Barrier and Instruction Synchronization to insure MPU usage */
+ __DMB(); /* Force memory writes before continuing */
+ __ISB(); /* Flush and refill pipeline with updated permissions */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ * @brief Enable the non-secure MPU.
+ * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
+ * NMI, FAULTMASK and privileged access to the default memory
+ * This parameter can be one of the following values:
+ * @arg MPU_HFNMI_PRIVDEF_NONE
+ * @arg MPU_HARDFAULT_NMI
+ * @arg MPU_PRIVILEGED_DEFAULT
+ * @arg MPU_HFNMI_PRIVDEF
+ * @retval None
+ */
+void HAL_MPU_Enable_NS(uint32_t MPU_Control)
+{
+ /* Enable the MPU */
+ MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+
+ /* Enable fault exceptions */
+ SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+
+ /* Follow ARM recommendation with */
+ /* - Data Memory Barrier and Instruction Synchronization to insure MPU usage */
+ __DMB(); /* Force memory writes before continuing */
+ __ISB(); /* Flush and refill pipeline with updated permissions */
+}
+#endif /* __ARM_FEATURE_CMSE */
+
+/**
+ * @brief Disable the MPU.
+ * @retval None
+ */
+void HAL_MPU_Disable(void)
+{
+ __DMB(); /* Force any outstanding transfers to complete before disabling MPU */
+
+ /* Disable the MPU */
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ * @brief Disable the non-secure MPU.
+ * @retval None
+ */
+void HAL_MPU_Disable_NS(void)
+{
+ __DMB(); /* Force any outstanding transfers to complete before disabling MPU */
+
+ /* Disable the MPU */
+ MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+}
+#endif /* __ARM_FEATURE_CMSE */
+
+/**
+ * @brief Initialize and configure the Region and the memory to be protected.
+ * @param pMPU_RegionInit: Pointer to a MPU_Region_InitTypeDef structure that contains
+ * the initialization and configuration information.
+ * @retval None
+ */
+void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *const pMPU_RegionInit)
+{
+ MPU_ConfigRegion(MPU, pMPU_RegionInit);
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ * @brief Initialize and configure the Region and the memory to be protected for non-secure MPU.
+ * @param pMPU_RegionInit: Pointer to a MPU_Region_InitTypeDef structure that contains
+ * the initialization and configuration information.
+ * @retval None
+ */
+void HAL_MPU_ConfigRegion_NS(const MPU_Region_InitTypeDef *const pMPU_RegionInit)
+{
+ MPU_ConfigRegion(MPU_NS, pMPU_RegionInit);
+}
+#endif /* __ARM_FEATURE_CMSE */
+
+/**
+ * @brief Initialize and configure the memory attributes.
+ * @param pMPU_AttributesInit: Pointer to a MPU_Attributes_InitTypeDef structure that contains
+ * the initialization and configuration information.
+ * @retval None
+ */
+void HAL_MPU_ConfigMemoryAttributes(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit)
+{
+ MPU_ConfigMemoryAttributes(MPU, pMPU_AttributesInit);
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ * @brief Initialize and configure the memory attributes for non-secure MPU.
+ * @param pMPU_AttributesInit: Pointer to a MPU_Attributes_InitTypeDef structure that contains
+ * the initialization and configuration information.
+ * @retval None
+ */
+void HAL_MPU_ConfigMemoryAttributes_NS(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit)
+{
+ MPU_ConfigMemoryAttributes(MPU_NS, pMPU_AttributesInit);
+}
+#endif /* __ARM_FEATURE_CMSE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CORTEX_Private_Functions
+ * @{
+ */
+static void MPU_ConfigRegion(MPU_Type *MPUx, const MPU_Region_InitTypeDef *const pMPU_RegionInit)
+{
+ /* Check the parameters */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ assert_param(IS_MPU_INSTANCE(MPUx));
+#endif /* __ARM_FEATURE_CMSE */
+ assert_param(IS_MPU_REGION_NUMBER(pMPU_RegionInit->Number));
+ assert_param(IS_MPU_REGION_ENABLE(pMPU_RegionInit->Enable));
+
+ /* Follow ARM recommendation with Data Memory Barrier prior to MPU configuration */
+ __DMB();
+
+ /* Set the Region number */
+ MPUx->RNR = pMPU_RegionInit->Number;
+
+ if (pMPU_RegionInit->Enable != MPU_REGION_DISABLE)
+ {
+ /* Check the parameters */
+ assert_param(IS_MPU_INSTRUCTION_ACCESS(pMPU_RegionInit->DisableExec));
+ assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(pMPU_RegionInit->AccessPermission));
+ assert_param(IS_MPU_ACCESS_SHAREABLE(pMPU_RegionInit->IsShareable));
+
+ MPUx->RBAR = (((uint32_t)pMPU_RegionInit->BaseAddress & 0xFFFFFFE0UL) |
+ ((uint32_t)pMPU_RegionInit->IsShareable << MPU_RBAR_SH_Pos) |
+ ((uint32_t)pMPU_RegionInit->AccessPermission << MPU_RBAR_AP_Pos) |
+ ((uint32_t)pMPU_RegionInit->DisableExec << MPU_RBAR_XN_Pos));
+
+ MPUx->RLAR = (((uint32_t)pMPU_RegionInit->LimitAddress & 0xFFFFFFE0UL) |
+ ((uint32_t)pMPU_RegionInit->AttributesIndex << MPU_RLAR_AttrIndx_Pos) |
+ ((uint32_t)pMPU_RegionInit->Enable << MPU_RLAR_EN_Pos));
+ }
+ else
+ {
+ MPUx->RBAR = 0U;
+ MPUx->RLAR = 0U;
+ }
+}
+
+static void MPU_ConfigMemoryAttributes(MPU_Type *MPUx, const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit)
+{
+ __IO uint32_t *p_mair;
+ uint32_t attr_values;
+ uint32_t attr_number;
+
+ /* Check the parameters */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ assert_param(IS_MPU_INSTANCE(MPUx));
+#endif /* __ARM_FEATURE_CMSE */
+ assert_param(IS_MPU_ATTRIBUTES_NUMBER(pMPU_AttributesInit->Number));
+ /* No need to check Attributes value as all 0x0..0xFF possible */
+
+ /* Follow ARM recommendation with Data Memory Barrier prior to MPUx configuration */
+ __DMB();
+
+ if (pMPU_AttributesInit->Number < MPU_ATTRIBUTES_NUMBER4)
+ {
+ /* Program MPU_MAIR0 */
+ p_mair = &(MPUx->MAIR0);
+ attr_number = pMPU_AttributesInit->Number;
+ }
+ else
+ {
+ /* Program MPU_MAIR1 */
+ p_mair = &(MPUx->MAIR1);
+ attr_number = (uint32_t)pMPU_AttributesInit->Number - 4U;
+ }
+
+ attr_values = *(p_mair);
+ attr_values &= ~(0xFFUL << (attr_number * 8U));
+ *(p_mair) = attr_values | ((uint32_t)pMPU_AttributesInit->Attributes << (attr_number * 8U));
+}
+/**
+ * @}
+ */
+
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_crc.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_crc.c
new file mode 100644
index 00000000..bb2b98ea
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_crc.c
@@ -0,0 +1,516 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_crc.c
+ * @author MCD Application Team
+ * @brief CRC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Cyclic Redundancy Check (CRC) peripheral:
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ (+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
+ (+) Initialize CRC calculator
+ (++) specify generating polynomial (peripheral default or non-default one)
+ (++) specify initialization value (peripheral default or non-default one)
+ (++) specify input data format
+ (++) specify input or output data inversion mode if any
+ (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
+ input data buffer starting with the previously computed CRC as
+ initialization value
+ (+) Use HAL_CRC_Calculate() function to compute the CRC value of the
+ input data buffer starting with the defined initialization value
+ (default or non-default) to initiate CRC calculation
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CRC CRC
+ * @brief CRC HAL module driver.
+ * @{
+ */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup CRC_Private_Functions CRC Private Functions
+ * @{
+ */
+static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
+static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup CRC_Exported_Functions CRC Exported Functions
+ * @{
+ */
+
+/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the CRC according to the specified parameters
+ in the CRC_InitTypeDef and create the associated handle
+ (+) DeInitialize the CRC peripheral
+ (+) Initialize the CRC MSP (MCU Specific Package)
+ (+) DeInitialize the CRC MSP
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the CRC according to the specified
+ * parameters in the CRC_InitTypeDef and create the associated handle.
+ * @param hcrc CRC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
+{
+ /* Check the CRC handle allocation */
+ if (hcrc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
+
+ if (hcrc->State == HAL_CRC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hcrc->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware */
+ HAL_CRC_MspInit(hcrc);
+ }
+
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ /* check whether or not non-default generating polynomial has been
+ * picked up by user */
+ assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse));
+ if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
+ {
+ /* initialize peripheral with default generating polynomial */
+ WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
+ }
+ else
+ {
+ /* initialize CRC peripheral with generating polynomial defined by user */
+ if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* check whether or not non-default CRC initial value has been
+ * picked up by user */
+ assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
+ if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
+ {
+ WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
+ }
+ else
+ {
+ WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
+ }
+
+
+ /* set input data inversion mode */
+ assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode));
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
+
+ /* set output data inversion mode */
+ assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode));
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
+
+ /* makes sure the input data format (bytes, halfwords or words stream)
+ * is properly specified by user */
+ assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitialize the CRC peripheral.
+ * @param hcrc CRC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
+{
+ /* Check the CRC handle allocation */
+ if (hcrc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
+
+ /* Check the CRC peripheral state */
+ if (hcrc->State == HAL_CRC_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ /* Reset CRC calculation unit */
+ __HAL_CRC_DR_RESET(hcrc);
+
+ /* Reset IDR register content */
+ CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR);
+
+ /* DeInit the low level hardware */
+ HAL_CRC_MspDeInit(hcrc);
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_RESET;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcrc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRC MSP.
+ * @param hcrc CRC handle
+ * @retval None
+ */
+__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcrc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CRC_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the CRC MSP.
+ * @param hcrc CRC handle
+ * @retval None
+ */
+__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcrc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CRC_MspDeInit can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
+ * @brief management functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+ using combination of the previous CRC value and the new one.
+
+ [..] or
+
+ (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+ independently of the previous CRC value.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+ * starting with the previously computed CRC as initialization value.
+ * @param hcrc CRC handle
+ * @param pBuffer pointer to the input data buffer, exact input data format is
+ * provided by hcrc->InputDataFormat.
+ * @param BufferLength input data buffer length (number of bytes if pBuffer
+ * type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
+ * number of words if pBuffer type is * uint32_t).
+ * @note By default, the API expects a uint32_t pointer as input buffer parameter.
+ * Input buffer pointers with other types simply need to be cast in uint32_t
+ * and the API will internally adjust its input data processing based on the
+ * handle field hcrc->InputDataFormat.
+ * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+ */
+uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t index; /* CRC input data buffer index */
+ uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ switch (hcrc->InputDataFormat)
+ {
+ case CRC_INPUTDATA_FORMAT_WORDS:
+ /* Enter Data to the CRC calculator */
+ for (index = 0U; index < BufferLength; index++)
+ {
+ hcrc->Instance->DR = pBuffer[index];
+ }
+ temp = hcrc->Instance->DR;
+ break;
+
+ case CRC_INPUTDATA_FORMAT_BYTES:
+ temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
+ break;
+
+ case CRC_INPUTDATA_FORMAT_HALFWORDS:
+ temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */
+ break;
+ default:
+ break;
+ }
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_READY;
+
+ /* Return the CRC computed value */
+ return temp;
+}
+
+/**
+ * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+ * starting with hcrc->Instance->INIT as initialization value.
+ * @param hcrc CRC handle
+ * @param pBuffer pointer to the input data buffer, exact input data format is
+ * provided by hcrc->InputDataFormat.
+ * @param BufferLength input data buffer length (number of bytes if pBuffer
+ * type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
+ * number of words if pBuffer type is * uint32_t).
+ * @note By default, the API expects a uint32_t pointer as input buffer parameter.
+ * Input buffer pointers with other types simply need to be cast in uint32_t
+ * and the API will internally adjust its input data processing based on the
+ * handle field hcrc->InputDataFormat.
+ * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+ */
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t index; /* CRC input data buffer index */
+ uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ /* Reset CRC Calculation Unit (hcrc->Instance->INIT is
+ * written in hcrc->Instance->DR) */
+ __HAL_CRC_DR_RESET(hcrc);
+
+ switch (hcrc->InputDataFormat)
+ {
+ case CRC_INPUTDATA_FORMAT_WORDS:
+ /* Enter 32-bit input data to the CRC calculator */
+ for (index = 0U; index < BufferLength; index++)
+ {
+ hcrc->Instance->DR = pBuffer[index];
+ }
+ temp = hcrc->Instance->DR;
+ break;
+
+ case CRC_INPUTDATA_FORMAT_BYTES:
+ /* Specific 8-bit input data handling */
+ temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
+ break;
+
+ case CRC_INPUTDATA_FORMAT_HALFWORDS:
+ /* Specific 16-bit input data handling */
+ temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */
+ break;
+
+ default:
+ break;
+ }
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_READY;
+
+ /* Return the CRC computed value */
+ return temp;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
+ * @brief Peripheral State functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the CRC handle state.
+ * @param hcrc CRC handle
+ * @retval HAL state
+ */
+HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
+{
+ /* Return CRC handle state */
+ return hcrc->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Enter 8-bit input data to the CRC calculator.
+ * Specific data handling to optimize processing time.
+ * @param hcrc CRC handle
+ * @param pBuffer pointer to the input data buffer
+ * @param BufferLength input data buffer length
+ * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+ */
+static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t i; /* input data buffer index */
+ uint16_t data;
+ __IO uint16_t *pReg;
+
+ /* Processing time optimization: 4 bytes are entered in a row with a single word write,
+ * last bytes must be carefully fed to the CRC calculator to ensure a correct type
+ * handling by the peripheral */
+ for (i = 0U; i < (BufferLength / 4U); i++)
+ {
+ hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \
+ ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \
+ ((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \
+ (uint32_t)pBuffer[(4U * i) + 3U];
+ }
+ /* last bytes specific handling */
+ if ((BufferLength % 4U) != 0U)
+ {
+ if ((BufferLength % 4U) == 1U)
+ {
+ *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */
+ }
+ if ((BufferLength % 4U) == 2U)
+ {
+ data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
+ pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */
+ *pReg = data;
+ }
+ if ((BufferLength % 4U) == 3U)
+ {
+ data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
+ pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */
+ *pReg = data;
+
+ *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */
+ }
+ }
+
+ /* Return the CRC computed value */
+ return hcrc->Instance->DR;
+}
+
+/**
+ * @brief Enter 16-bit input data to the CRC calculator.
+ * Specific data handling to optimize processing time.
+ * @param hcrc CRC handle
+ * @param pBuffer pointer to the input data buffer
+ * @param BufferLength input data buffer length
+ * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+ */
+static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t i; /* input data buffer index */
+ __IO uint16_t *pReg;
+
+ /* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
+ * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
+ * a correct type handling by the peripheral */
+ for (i = 0U; i < (BufferLength / 2U); i++)
+ {
+ hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U];
+ }
+ if ((BufferLength % 2U) != 0U)
+ {
+ pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */
+ *pReg = pBuffer[2U * i];
+ }
+
+ /* Return the CRC computed value */
+ return hcrc->Instance->DR;
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_CRC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_crc_ex.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_crc_ex.c
new file mode 100644
index 00000000..62bac9e8
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_crc_ex.c
@@ -0,0 +1,223 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_crc_ex.c
+ * @author MCD Application Team
+ * @brief Extended CRC HAL module driver.
+ * This file provides firmware functions to manage the extended
+ * functionalities of the CRC peripheral.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+================================================================================
+ ##### How to use this driver #####
+================================================================================
+ [..]
+ (+) Set user-defined generating polynomial through HAL_CRCEx_Polynomial_Set()
+ (+) Configure Input or Output data inversion
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CRCEx CRCEx
+ * @brief CRC Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup CRCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions
+ * @brief Extended Initialization and Configuration functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended configuration functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure the generating polynomial
+ (+) Configure the input data inversion
+ (+) Configure the output data inversion
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Initialize the CRC polynomial if different from default one.
+ * @param hcrc CRC handle
+ * @param Pol CRC generating polynomial (7, 8, 16 or 32-bit long).
+ * This parameter is written in normal representation, e.g.
+ * @arg for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
+ * @arg for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
+ * @param PolyLength CRC polynomial length.
+ * This parameter can be one of the following values:
+ * @arg @ref CRC_POLYLENGTH_7B 7-bit long CRC (generating polynomial of degree 7)
+ * @arg @ref CRC_POLYLENGTH_8B 8-bit long CRC (generating polynomial of degree 8)
+ * @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16)
+ * @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */
+
+ /* Check the parameters */
+ assert_param(IS_CRC_POL_LENGTH(PolyLength));
+
+ /* check polynomial definition vs polynomial size:
+ * polynomial length must be aligned with polynomial
+ * definition. HAL_ERROR is reported if Pol degree is
+ * larger than that indicated by PolyLength.
+ * Look for MSB position: msb will contain the degree of
+ * the second to the largest polynomial member. E.g., for
+ * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
+ while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
+ {
+ }
+
+ switch (PolyLength)
+ {
+ case CRC_POLYLENGTH_7B:
+ if (msb >= HAL_CRC_LENGTH_7B)
+ {
+ status = HAL_ERROR;
+ }
+ break;
+ case CRC_POLYLENGTH_8B:
+ if (msb >= HAL_CRC_LENGTH_8B)
+ {
+ status = HAL_ERROR;
+ }
+ break;
+ case CRC_POLYLENGTH_16B:
+ if (msb >= HAL_CRC_LENGTH_16B)
+ {
+ status = HAL_ERROR;
+ }
+ break;
+
+ case CRC_POLYLENGTH_32B:
+ /* no polynomial definition vs. polynomial length issue possible */
+ break;
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+ if (status == HAL_OK)
+ {
+ /* set generating polynomial */
+ WRITE_REG(hcrc->Instance->POL, Pol);
+
+ /* set generating polynomial size */
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Set the Reverse Input data mode.
+ * @param hcrc CRC handle
+ * @param InputReverseMode Input Data inversion mode.
+ * This parameter can be one of the following values:
+ * @arg @ref CRC_INPUTDATA_INVERSION_NONE no change in bit order (default value)
+ * @arg @ref CRC_INPUTDATA_INVERSION_BYTE Byte-wise bit reversal
+ * @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD HalfWord-wise bit reversal
+ * @arg @ref CRC_INPUTDATA_INVERSION_WORD Word-wise bit reversal
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
+{
+ /* Check the parameters */
+ assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode));
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ /* set input data inversion mode */
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode);
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the Reverse Output data mode.
+ * @param hcrc CRC handle
+ * @param OutputReverseMode Output Data inversion mode.
+ * This parameter can be one of the following values:
+ * @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion (default value)
+ * @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
+{
+ /* Check the parameters */
+ assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode));
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ /* set output data inversion mode */
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode);
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+
+
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+
+#endif /* HAL_CRC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cryp.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cryp.c
new file mode 100644
index 00000000..8c5b070a
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cryp.c
@@ -0,0 +1,5723 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_cryp.c
+ * @author MCD Application Team
+ * @brief CRYP HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Cryptography (CRYP) peripheral:
+ * + Initialization, de-initialization, set config and get config functions
+ * + DMA callback functions
+ * + CRYP IRQ handler management
+ * + Peripheral State functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The CRYP HAL driver can be used as follows:
+
+ (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
+ (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()or __HAL_RCC_AES_CLK_ENABLE
+ (##) In case of using interrupts (e.g. HAL_CRYP_Encrypt_IT())
+ (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
+ (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
+ (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
+ (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_Encrypt_DMA())
+ (+++) Enable the DMAx interface clock using __RCC_DMAx_CLK_ENABLE()
+ (+++) Configure and enable two DMA channels one for managing data transfer from
+ memory to peripheral (input channel) and another stream for managing data
+ transfer from peripheral to memory (output channel)
+ (+++) Associate the initialized DMA handle to the CRYP DMA handle
+ using __HAL_LINKDMA()
+ (+++) Configure the priority and enable the NVIC for the transfer complete
+ interrupt on the two DMA channels. The output channel should have higher
+ priority than the input channel HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
+
+ (#)Initialize the CRYP according to the specified parameters :
+ (##) The data type: 1-bit, 8-bit, 16-bit or 32-bit.
+ (##) The key size: 128, 192 or 256.
+ (##) The AES Algorithm ECB/CBC/CTR/GCM or CCM.
+ (##) The initialization vector (counter). It is not used in ECB mode.
+ (##) The key buffer used for encryption/decryption.
+ (+++) In some specific configurations, the key is written by the application
+ code out of the HAL scope. In that case, user can still resort to the
+ HAL APIs as usual but must make sure that pKey pointer is set to NULL.
+ (##) The DataWidthUnit field. It specifies whether the data length (or the payload
+ length for authentication algorithms) is in words or bytes.
+ (##) The Header used only in AES GCM and CCM Algorithm for authentication.
+ (##) The HeaderSize used to give size of header buffer in word or bytes, depending upon HeaderWidthUnit field.
+ (##) The HeaderWidthUnit field. It specifies whether the header length
+ (for authentication algorithms) is in words or bytes.
+ (##) The B0 block is the first authentication block used only in AES CCM mode.
+ (##) The KeyIVConfigSkip used to process several messages in a row.
+ (##) The KeyMode used to special key operation modes (for SAES : wrapped key, shared key with AES peripheral).
+ (##) The KeySelect, Only for SAES, used to select key from different key source.
+ (##) The KeyProtection, Only for SAES, used for security context enforcement.
+
+ (#)Three processing (encryption/decryption) functions are available:
+ (##) Polling mode: encryption and decryption APIs are blocking functions
+ i.e. they process the data and wait till the processing is finished,
+ e.g. HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
+ (##) Interrupt mode: encryption and decryption APIs are not blocking functions
+ i.e. they process the data under interrupt,
+ e.g. HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
+ (##) DMA mode: encryption and decryption APIs are not blocking functions
+ i.e. the data transfer is ensured by DMA,
+ e.g. HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA
+
+ (#)When the processing function is called at first time after HAL_CRYP_Init()
+ the CRYP peripheral is configured and processes the buffer in input.
+ At second call, no need to Initialize the CRYP, user have to get current configuration via
+ HAL_CRYP_GetConfig() API, then only HAL_CRYP_SetConfig() is requested to set
+ new parametres, finally user can start encryption/decryption.
+
+ (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
+
+ (#)To process a single message with consecutive calls to HAL_CRYP_Encrypt() or HAL_CRYP_Decrypt()
+ without having to configure again the Key or the Initialization Vector between each API call,
+ the field KeyIVConfigSkip of the initialization structure must be set to CRYP_KEYIVCONFIG_ONCE.
+ Same is true for consecutive calls of HAL_CRYP_Encrypt_IT(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt_DMA()
+ or HAL_CRYP_Decrypt_DMA().
+
+ [..]
+ The cryptographic processor supports following standards:
+ (#) The advanced encryption standard (AES) supported:
+ (##)128-bit data block processing
+ (##) chaining modes supported :
+ (+++) Electronic Code Book(ECB)
+ (+++) Cipher Block Chaining (CBC)
+ (+++) Counter mode (CTR)
+ (+++) Galois/counter mode (GCM/GMAC)
+ (+++) Counter with Cipher Block Chaining-Message(CCM)
+ (##) keys length Supported : 128-bit and 256-bit
+
+ [..]
+ (@) Specific care must be taken to format the key and the Initialization Vector IV!
+
+ [..] If the key is defined as a 128-bit long array key[127..0] = {b127 ... b0} where
+ b127 is the MSB and b0 the LSB, the key must be stored in MCU memory
+ (+) as a sequence of words where the MSB word comes first (occupies the
+ lowest memory address)
+ (++) address n+0 : 0b b127 .. b120 b119 .. b112 b111 .. b104 b103 .. b96
+ (++) address n+4 : 0b b95 .. b88 b87 .. b80 b79 .. b72 b71 .. b64
+ (++) address n+8 : 0b b63 .. b56 b55 .. b48 b47 .. b40 b39 .. b32
+ (++) address n+C : 0b b31 .. b24 b23 .. b16 b15 .. b8 b7 .. b0
+ [..] Hereafter, another illustration when considering a 128-bit long key made of 16 bytes {B15..B0}.
+ The 4 32-bit words that make the key must be stored as follows in MCU memory:
+ (+) address n+0 : 0x B15 B14 B13 B12
+ (+) address n+4 : 0x B11 B10 B9 B8
+ (+) address n+8 : 0x B7 B6 B5 B4
+ (+) address n+C : 0x B3 B2 B1 B0
+ [..] which leads to the expected setting
+ (+) AES_KEYR3 = 0x B15 B14 B13 B12
+ (+) AES_KEYR2 = 0x B11 B10 B9 B8
+ (+) AES_KEYR1 = 0x B7 B6 B5 B4
+ (+) AES_KEYR0 = 0x B3 B2 B1 B0
+
+ [..] Same format must be applied for a 256-bit long key made of 32 bytes {B31..B0}.
+ The 8 32-bit words that make the key must be stored as follows in MCU memory:
+ (+) address n+00 : 0x B31 B30 B29 B28
+ (+) address n+04 : 0x B27 B26 B25 B24
+ (+) address n+08 : 0x B23 B22 B21 B20
+ (+) address n+0C : 0x B19 B18 B17 B16
+ (+) address n+10 : 0x B15 B14 B13 B12
+ (+) address n+14 : 0x B11 B10 B9 B8
+ (+) address n+18 : 0x B7 B6 B5 B4
+ (+) address n+1C : 0x B3 B2 B1 B0
+ [..] which leads to the expected setting
+ (+) AES_KEYR7 = 0x B31 B30 B29 B28
+ (+) AES_KEYR6 = 0x B27 B26 B25 B24
+ (+) AES_KEYR5 = 0x B23 B22 B21 B20
+ (+) AES_KEYR4 = 0x B19 B18 B17 B16
+ (+) AES_KEYR3 = 0x B15 B14 B13 B12
+ (+) AES_KEYR2 = 0x B11 B10 B9 B8
+ (+) AES_KEYR1 = 0x B7 B6 B5 B4
+ (+) AES_KEYR0 = 0x B3 B2 B1 B0
+
+ [..] Initialization Vector IV (4 32-bit words) format must follow the same as
+ that of a 128-bit long key.
+
+ [..] Note that key and IV registers are not sensitive to swap mode selection.
+
+ [..] This section describes the AES Galois/counter mode (GCM) supported by the peripherals:
+ (#) Algorithm supported :
+ (##) Galois/counter mode (GCM)
+ (##) Galois message authentication code (GMAC) :is exactly the same as
+ GCM algorithm composed only by an header.
+ (#) Four phases are performed in GCM :
+ (##) Init phase: peripheral prepares the GCM hash subkey (H) and do the IV processing
+ (##) Header phase: peripheral processes the Additional Authenticated Data (AAD), with hash
+ computation only.
+ (##) Payload phase: peripheral processes the plaintext (P) with hash computation + keystream
+ encryption + data XORing. It works in a similar way for ciphertext (C).
+ (##) Final phase: peripheral generates the authenticated tag (T) using the last block of data.
+ HAL_CRYPEx_AESGCM_GenerateAuthTAG API used in this phase to generate 4 words which correspond
+ to the Tag. user should consider only part of this 4 words, if Tag length is less than 128 bits.
+ (#) structure of message construction in GCM is defined as below :
+ (##) 16 bytes Initial Counter Block (ICB)composed of IV and counter
+ (##) The authenticated header A (also knows as Additional Authentication Data AAD)
+ this part of the message is only authenticated, not encrypted.
+ (##) The plaintext message P is both authenticated and encrypted as ciphertext.
+ GCM standard specifies that ciphertext has same bit length as the plaintext.
+ (##) The last block is composed of the length of A (on 64 bits) and the length of ciphertext
+ (on 64 bits)
+
+ [..] A more detailed description of the GCM message structure is available below.
+
+ [..] This section describe The AES Counter with Cipher Block Chaining-Message
+ Authentication Code (CCM) supported by the peripheral:
+ (#) Specific parameters for CCM :
+
+ (##) B0 block : follows NIST Special Publication 800-38C,
+ (##) B1 block (header)
+ (##) CTRx block : control blocks
+
+ [..] A detailed description of the CCM message structure is available below.
+
+ (#) CCM in peripheral:
+ (##) To perform message payload encryption or decryption AES is configured in CTR mode.
+ (##) For authentication two phases are performed :
+ - Header phase: peripheral processes the Additional Authenticated Data (AAD) first, then the cleartext message
+ only cleartext payload (not the ciphertext payload) is used and no outpout.
+ (##) Final phase: peripheral generates the authenticated tag (T) using the last block of data.
+ HAL_CRYPEx_AESCCM_GenerateAuthTAG API used in this phase to generate 4 words which correspond to the Tag.
+ user should consider only part of this 4 words, if Tag length is less than 128 bits
+ *** Callback registration ***
+ =============================
+
+ [..]
+ The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions @ref HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback()
+ to register an interrupt callback.
+
+ [..]
+ Function @ref HAL_CRYP_RegisterCallback() allows to register following callbacks:
+ (+) InCpltCallback : Input FIFO transfer completed callback.
+ (+) OutCpltCallback : Output FIFO transfer completed callback.
+ (+) ErrorCallback : callback for error detection.
+ (+) MspInitCallback : CRYP MspInit.
+ (+) MspDeInitCallback : CRYP MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ [..]
+ Use function @ref HAL_CRYP_UnRegisterCallback() to reset a callback to the default
+ weak function.
+ @ref HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) InCpltCallback : Input FIFO transfer completed callback.
+ (+) OutCpltCallback : Output FIFO transfer completed callback.
+ (+) ErrorCallback : callback for error detection.
+ (+) MspInitCallback : CRYP MspInit.
+ (+) MspDeInitCallback : CRYP MspDeInit.
+
+ [..]
+ By default, after the @ref HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET
+ all callbacks are set to the corresponding weak functions :
+ examples @ref HAL_CRYP_InCpltCallback() , @ref HAL_CRYP_OutCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak function in the @ref HAL_CRYP_Init()/ @ref HAL_CRYP_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ if not, MspInit or MspDeInit are not null, the @ref HAL_CRYP_Init() / @ref HAL_CRYP_DeInit()
+ keep and use the user MspInit/MspDeInit functions (registered beforehand)
+
+ [..]
+ Callbacks can be registered/unregistered in HAL_CRYP_STATE_READY state only.
+ Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
+ in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_CRYP_RegisterCallback() before calling @ref HAL_CRYP_DeInit()
+ or @ref HAL_CRYP_Init() function.
+
+ [..]
+ When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
+
+ *** Suspend/Resume feature ***
+ ==============================
+
+ [..]
+ The compilation define USE_HAL_CRYP_SUSPEND_RESUME when set to 1
+ allows the user to resort to the suspend/resume feature.
+ A low priority block processing can be suspended to process a high priority block
+ instead. When the high priority block processing is over, the low priority block
+ processing can be resumed, restarting from the point where it was suspended. This
+ feature is applicable only in non-blocking interrupt mode.
+
+ [..] User must resort to HAL_CRYP_Suspend() to suspend the low priority block
+ processing. This API manages the hardware block processing suspension and saves all the
+ internal data that will be needed to restart later on. Upon HAL_CRYP_Suspend() completion,
+ the user can launch the processing of any other block (high priority block processing).
+
+ [..] When the high priority block processing is over, user must invoke HAL_CRYP_Resume()
+ to resume the low priority block processing. Ciphering (or deciphering) restarts from
+ the suspension point and ends as usual.
+
+ [..] HAL_CRYP_Suspend() reports an error when the suspension request is sent too late
+ (i.e when the low priority block processing is about to end). There is no use to
+ suspend the tag generation processing for authentication algorithms.
+
+ [..]
+ (@) If the key is written out of HAL scope (case pKey pointer set to NULL by the user),
+ the block processing suspension/resumption mechanism is NOT applicable.
+
+ [..]
+ (@) If the Key and Initialization Vector are configured only once and configuration is
+ skipped for consecutive processings (case KeyIVConfigSkip set to CRYP_KEYIVCONFIG_ONCE),
+ the block processing suspension/resumption mechanism is NOT applicable.
+
+ @endverbatim
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CRYP
+ * @{
+ */
+
+#if defined(AES)
+#ifdef HAL_CRYP_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup CRYP_Private_Defines
+ * @{
+ */
+#define CRYP_TIMEOUT_KEYPREPARATION 82U /* The latency of key preparation operation is 82 clock cycles.*/
+#define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey
+ is 299 clock cycles.*/
+#define CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /* The latency of GCM/CCM header phase is 290 clock cycles.*/
+
+#define CRYP_PHASE_READY 0x00000001U /*!< CRYP peripheral is ready for initialization. */
+#define CRYP_PHASE_PROCESS 0x00000002U /*!< CRYP peripheral is in processing phase */
+#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
+#define CRYP_PHASE_HEADER_SUSPENDED 0x00000004U /*!< GCM/GMAC/CCM header phase is suspended */
+#define CRYP_PHASE_PAYLOAD_SUSPENDED 0x00000005U /*!< GCM/CCM payload phase is suspended */
+#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
+#define CRYP_PHASE_HEADER_DMA_FEED 0x00000006U /*!< GCM/GMAC/CCM header is fed to the peripheral in DMA mode */
+
+#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< Encryption mode(Mode 1) */
+#define CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0 /*!< Key derivation mode only used when performing ECB and CBC decryptions (Mode 2) */
+#define CRYP_OPERATINGMODE_DECRYPT AES_CR_MODE_1 /*!< Decryption (Mode 3) */
+#define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */
+#define CRYP_PHASE_HEADER AES_CR_GCMPH_0 /*!< GCM/GMAC or CCM header phase */
+#define CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */
+#define CRYP_PHASE_FINAL AES_CR_GCMPH /*!< GCM/GMAC or CCM final phase */
+
+/* CTR1 information to use in CCM algorithm */
+#define CRYP_CCM_CTR1_0 0x07FFFFFFU
+#define CRYP_CCM_CTR1_1 0xFFFFFF00U
+#define CRYP_CCM_CTR1_2 0x00000001U
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @addtogroup CRYP_Private_Macros
+ * @{
+ */
+
+#define CRYP_SET_PHASE(__HANDLE__, __PHASE__)\
+ MODIFY_REG((__HANDLE__)->Instance->CR, AES_CR_GCMPH, (uint32_t)(__PHASE__))
+
+/**
+ * @}
+ */
+
+/* Private struct -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup CRYP_Private_Functions
+ * @{
+ */
+
+static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
+static HAL_StatusTypeDef CRYP_SetHeaderDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size);
+static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
+static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
+static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
+static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize);
+static void CRYP_SetIV(CRYP_HandleTypeDef *hcryp);
+static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp);
+static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
+static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcrypt, uint32_t Timeout);
+static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
+static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Output);
+static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Input);
+static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Output);
+static void CRYP_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Input);
+static void CRYP_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Output, uint32_t KeySize);
+static void CRYP_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Input, uint32_t KeySize);
+static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp);
+#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
+
+
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @addtogroup CRYP_Exported_Functions
+ * @{
+ */
+
+/** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions.
+ *
+@verbatim
+ ========================================================================================
+ ##### Initialization, de-initialization and Set and Get configuration functions #####
+ ========================================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the CRYP
+ (+) DeInitialize the CRYP
+ (+) Initialize the CRYP MSP
+ (+) DeInitialize the CRYP MSP
+ (+) configure CRYP (HAL_CRYP_SetConfig) with the specified parameters in the CRYP_ConfigTypeDef
+ Parameters which are configured in This section are :
+ (+) Key size
+ (+) Data Type : 32,16, 8 or 1bit
+ (+) AlgoMode : ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard.
+ (+) Get CRYP configuration (HAL_CRYP_GetConfig) from the specified parameters in the CRYP_HandleTypeDef
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the CRYP according to the specified
+ * parameters in the CRYP_ConfigTypeDef and creates the associated handle.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
+{
+ uint32_t cr_value;
+
+ /* Check the CRYP handle allocation */
+ if (hcryp == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check parameters */
+ assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
+ assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
+ assert_param(IS_CRYP_ALGORITHM(hcryp->Init.Algorithm));
+ assert_param(IS_CRYP_INIT(hcryp->Init.KeyIVConfigSkip));
+
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ if (hcryp->State == HAL_CRYP_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hcryp->Lock = HAL_UNLOCKED;
+
+ hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak InCpltCallback */
+ hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */
+ hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */
+
+ if (hcryp->MspInitCallback == NULL)
+ {
+ hcryp->MspInitCallback = HAL_CRYP_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware */
+ hcryp->MspInitCallback(hcryp);
+ }
+#else
+ if (hcryp->State == HAL_CRYP_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hcryp->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware */
+ HAL_CRYP_MspInit(hcryp);
+ }
+#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
+
+ if (hcryp->Instance == AES)
+ {
+ /* Set the key size, data type and Algorithm */
+ cr_value = (uint32_t)(hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm | hcryp->Init.KeyMode);
+ /* Set the key size, data type, algorithm and mode */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD | AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, cr_value);
+ }
+ else
+ {
+ cr_value = (uint32_t)(hcryp->Init.KeyMode | hcryp->Init.DataType | hcryp->Init.KeySize | \
+ hcryp->Init.Algorithm | hcryp->Init.KeySelect | hcryp->Init.KeyProtection);
+ /* Set the key size, data type, algorithm, Key selection and key protection */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD | AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD | AES_CR_KEYSEL |
+ AES_CR_KEYPROT, cr_value);
+ }
+ /* Reset Error Code field */
+ hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
+
+ /* Reset peripheral Key and IV configuration flag */
+ hcryp->KeyIVConfig = 0U;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Set the default CRYP phase */
+ hcryp->Phase = CRYP_PHASE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief De-Initializes the CRYP peripheral.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
+{
+ /* Check the CRYP handle allocation */
+ if (hcryp == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the default CRYP phase */
+ hcryp->Phase = CRYP_PHASE_READY;
+
+ /* Reset CrypInCount and CrypOutCount */
+ hcryp->CrypInCount = 0;
+ hcryp->CrypOutCount = 0;
+ hcryp->CrypHeaderCount = 0;
+
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Set IPRST for software reset */
+ SET_BIT(hcryp->Instance->CR, AES_CR_IPRST);
+
+ /* Clear IPRST to allow writing registers */
+ CLEAR_BIT(hcryp->Instance->CR, AES_CR_IPRST);
+
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ if (hcryp->MspDeInitCallback == NULL)
+ {
+ hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; /* Legacy weak MspDeInit */
+ }
+ /* DeInit the low level hardware */
+ hcryp->MspDeInitCallback(hcryp);
+#else
+ /* DeInit the low level hardware: CLOCK, NVIC.*/
+ HAL_CRYP_MspDeInit(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_RESET;
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the CRYP according to the specified
+ * parameters in the CRYP_ConfigTypeDef
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure
+ * @param pConf pointer to a CRYP_ConfigTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
+{
+ /* Check the CRYP handle allocation */
+ if ((hcryp == NULL) || (pConf == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check parameters */
+ assert_param(IS_CRYP_KEYSIZE(pConf->KeySize));
+ assert_param(IS_CRYP_DATATYPE(pConf->DataType));
+ assert_param(IS_CRYP_ALGORITHM(pConf->Algorithm));
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+ __HAL_LOCK(hcryp);
+
+ /* Set CRYP parameters */
+ hcryp->Init.DataType = pConf->DataType;
+ hcryp->Init.pKey = pConf->pKey;
+ hcryp->Init.Algorithm = pConf->Algorithm;
+ hcryp->Init.KeySize = pConf->KeySize;
+ hcryp->Init.pInitVect = pConf->pInitVect;
+ hcryp->Init.Header = pConf->Header;
+ hcryp->Init.HeaderSize = pConf->HeaderSize;
+ hcryp->Init.B0 = pConf->B0;
+ hcryp->Init.DataWidthUnit = pConf->DataWidthUnit;
+ hcryp->Init.KeyMode = pConf->KeyMode;
+ hcryp->Init.HeaderWidthUnit = pConf->HeaderWidthUnit;
+ hcryp->Init.KeyIVConfigSkip = pConf->KeyIVConfigSkip;
+
+ if (hcryp->Instance == AES)
+ {
+ /* Set the key size(This bit field is do not care in the DES or TDES modes)
+ data type, AlgoMode and operating mode */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD | AES_CR_KMOD,
+ hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm | hcryp->Init.KeyMode);
+ }
+ else
+ {
+ hcryp->Init.KeySelect = pConf->KeySelect;
+ hcryp->Init.KeyProtection = pConf->KeyProtection;
+
+ /* In case of HSW, HW or SW key selection, we should specify Key mode selection (SAES_CR_KMOD) */
+ if ((hcryp->Init.KeySelect != CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_WRAPPED))
+ {
+ /* Set key mode selection (Normal, Wrapped or Shared key )*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD, CRYP_KEYMODE_WRAPPED);
+ }
+
+ /* Set the key size data type, AlgoMode and operating mode */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD | \
+ AES_CR_KEYSEL | AES_CR_KEYPROT, hcryp->Init.DataType | hcryp->Init.KeySize | \
+ hcryp->Init.Algorithm | hcryp->Init.KeySelect | hcryp->Init.KeyProtection);
+ }
+ /* Clear error flags */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RWEIF);
+ __HAL_UNLOCK(hcryp);
+
+ /* Reset Error Code field */
+ hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Set the default CRYP phase */
+ hcryp->Phase = CRYP_PHASE_READY;
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Busy error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Get CRYP Configuration parameters in associated handle.
+ * @param pConf pointer to a CRYP_ConfigTypeDef structure
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
+{
+ /* Check the CRYP handle allocation */
+ if ((hcryp == NULL) || (pConf == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+ __HAL_LOCK(hcryp);
+
+ /* Get CRYP parameters */
+ pConf->DataType = hcryp->Init.DataType;
+ pConf->pKey = hcryp->Init.pKey;
+ pConf->Algorithm = hcryp->Init.Algorithm;
+ pConf->KeySize = hcryp->Init.KeySize;
+ pConf->pInitVect = hcryp->Init.pInitVect;
+ pConf->Header = hcryp->Init.Header;
+ pConf->HeaderSize = hcryp->Init.HeaderSize;
+ pConf->B0 = hcryp->Init.B0;
+ pConf->DataWidthUnit = hcryp->Init.DataWidthUnit;
+ pConf->KeyMode = hcryp->Init.KeyMode;
+ pConf->KeySelect = hcryp->Init.KeySelect;
+ pConf->KeyProtection = hcryp->Init.KeyProtection;
+ pConf->KeyIVConfigSkip = hcryp->Init.KeyIVConfigSkip;
+ pConf->HeaderWidthUnit = hcryp->Init.HeaderWidthUnit;
+
+ __HAL_UNLOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Busy error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ return HAL_ERROR;
+ }
+}
+/**
+ * @brief Initializes the CRYP MSP.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval None
+ */
+__weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcryp);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CRYP_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes CRYP MSP.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval None
+ */
+__weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcryp);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CRYP_MspDeInit could be implemented in the user file
+ */
+}
+
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+/**
+ * @brief Register a User CRYP Callback
+ * To be used instead of the weak predefined callback
+ * @param hcryp cryp handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
+ * @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
+ * @arg @ref HAL_CRYP_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID,
+ pCRYP_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ __HAL_LOCK(hcryp);
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CRYP_INPUT_COMPLETE_CB_ID :
+ hcryp->InCpltCallback = pCallback;
+ break;
+
+ case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
+ hcryp->OutCpltCallback = pCallback;
+ break;
+
+ case HAL_CRYP_ERROR_CB_ID :
+ hcryp->ErrorCallback = pCallback;
+ break;
+
+ case HAL_CRYP_MSPINIT_CB_ID :
+ hcryp->MspInitCallback = pCallback;
+ break;
+
+ case HAL_CRYP_MSPDEINIT_CB_ID :
+ hcryp->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hcryp->State == HAL_CRYP_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CRYP_MSPINIT_CB_ID :
+ hcryp->MspInitCallback = pCallback;
+ break;
+
+ case HAL_CRYP_MSPDEINIT_CB_ID :
+ hcryp->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ __HAL_UNLOCK(hcryp);
+
+ return status;
+}
+
+/**
+ * @brief Unregister an CRYP Callback
+ * CRYP callback is redirected to the weak predefined callback
+ * @param hcryp cryp handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
+ * @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
+ * @arg @ref HAL_CRYP_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ __HAL_LOCK(hcryp);
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CRYP_INPUT_COMPLETE_CB_ID :
+ hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak InCpltCallback */
+ break;
+
+ case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
+ hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */
+ break;
+
+ case HAL_CRYP_ERROR_CB_ID :
+ hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_CRYP_MSPINIT_CB_ID :
+ hcryp->MspInitCallback = HAL_CRYP_MspInit;
+ break;
+
+ case HAL_CRYP_MSPDEINIT_CB_ID :
+ hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hcryp->State == HAL_CRYP_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CRYP_MSPINIT_CB_ID :
+ hcryp->MspInitCallback = HAL_CRYP_MspInit;
+ break;
+
+ case HAL_CRYP_MSPDEINIT_CB_ID :
+ hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ __HAL_UNLOCK(hcryp);
+
+ return status;
+}
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+
+#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
+/**
+ * @brief Request CRYP processing suspension when in interruption mode.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @note Set the handle field SuspendRequest to the appropriate value so that
+ * the on-going CRYP processing is suspended as soon as the required
+ * conditions are met.
+ * @note HAL_CRYP_ProcessSuspend() can only be invoked when the processing is done
+ * in non-blocking interrupt mode.
+ * @note It is advised not to suspend the CRYP processing when the DMA controller
+ * is managing the data transfer.
+ * @retval None
+ */
+void HAL_CRYP_ProcessSuspend(CRYP_HandleTypeDef *hcryp)
+{
+ /* Set Handle SuspendRequest field */
+ hcryp->SuspendRequest = HAL_CRYP_SUSPEND;
+}
+
+/**
+ * @brief CRYP processing suspension and peripheral internal parameters storage.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @note peripheral internal parameters are stored to be readily available when
+ * suspended processing is resumed later on.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp)
+{
+ HAL_CRYP_STATETypeDef state;
+
+ /* Request suspension */
+ HAL_CRYP_ProcessSuspend(hcryp);
+
+ do
+ {
+ state = HAL_CRYP_GetState(hcryp);
+ } while ((state != HAL_CRYP_STATE_SUSPENDED) && (state != HAL_CRYP_STATE_READY));
+
+ if (HAL_CRYP_GetState(hcryp) == HAL_CRYP_STATE_READY)
+ {
+ /* Processing was already over or was about to end. No suspension done */
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Suspend Processing */
+
+ /* If authentication algorithms on-going, carry out first saving steps
+ before disable the peripheral */
+ if ((hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) || \
+ (hcryp->Init.Algorithm == CRYP_AES_CCM))
+ {
+ /* Save Suspension registers */
+ CRYP_Read_SuspendRegisters(hcryp, hcryp->SUSPxR_saved);
+ /* Save Key */
+ CRYP_Read_KeyRegisters(hcryp, hcryp->Key_saved, hcryp->Init.KeySize);
+ /* Save IV */
+ CRYP_Read_IVRegisters(hcryp, hcryp->IV_saved);
+ }
+ /* Disable AES */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Save low-priority block CRYP handle parameters */
+ hcryp->Init_saved = hcryp->Init;
+ hcryp->pCrypInBuffPtr_saved = hcryp->pCrypInBuffPtr;
+ hcryp->pCrypOutBuffPtr_saved = hcryp->pCrypOutBuffPtr;
+ hcryp->CrypInCount_saved = hcryp->CrypInCount;
+ hcryp->CrypOutCount_saved = hcryp->CrypOutCount;
+ hcryp->Phase_saved = hcryp->Phase;
+ hcryp->State_saved = hcryp->State;
+ hcryp->Size_saved = ((hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)\
+ ? (hcryp->Size / 4U) : hcryp->Size);
+ hcryp->SizesSum_saved = hcryp->SizesSum;
+ hcryp->CrypHeaderCount_saved = hcryp->CrypHeaderCount;
+ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
+
+ if ((hcryp->Init.Algorithm == CRYP_AES_CBC) || \
+ (hcryp->Init.Algorithm == CRYP_AES_CTR))
+ {
+ /* Save Initialisation Vector registers */
+ CRYP_Read_IVRegisters(hcryp, hcryp->IV_saved);
+ }
+
+ /* Save Control register */
+ hcryp->CR_saved = hcryp->Instance->CR;
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief CRYP processing resumption.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @note Processing restarts at the exact point where it was suspended, based
+ * on the parameters saved at suspension time.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp)
+{
+ /* Check the CRYP handle allocation */
+ if (hcryp == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ if (hcryp->State_saved != HAL_CRYP_STATE_SUSPENDED)
+ {
+ /* CRYP was not suspended */
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Restore low-priority block CRYP handle parameters */
+ hcryp->Init = hcryp->Init_saved;
+ hcryp->State = hcryp->State_saved;
+
+ /* Chaining algorithms case */
+ if ((hcryp->Init_saved.Algorithm == CRYP_AES_ECB) || \
+ (hcryp->Init_saved.Algorithm == CRYP_AES_CBC) || \
+ (hcryp->Init_saved.Algorithm == CRYP_AES_CTR))
+ {
+ /* Restore low-priority block CRYP handle parameters */
+ if ((hcryp->Init.Algorithm == CRYP_AES_CBC) || \
+ (hcryp->Init.Algorithm == CRYP_AES_CTR))
+ {
+ hcryp->Init.pInitVect = hcryp->IV_saved;
+ }
+ __HAL_CRYP_DISABLE(hcryp);
+
+ (void) HAL_CRYP_Init(hcryp);
+ }
+ else /* Authentication algorithms case */
+ {
+ /* Restore low-priority block CRYP handle parameters */
+ hcryp->Phase = hcryp->Phase_saved;
+ hcryp->CrypHeaderCount = hcryp->CrypHeaderCount_saved;
+ hcryp->SizesSum = hcryp->SizesSum_saved;
+
+ /* Disable AES and write-back SUSPxR registers */;
+ __HAL_CRYP_DISABLE(hcryp);
+ /* Restore AES Suspend Registers */
+ CRYP_Write_SuspendRegisters(hcryp, hcryp->SUSPxR_saved);
+ /* Restore Control, Key and IV Registers, then enable AES */
+ hcryp->Instance->CR = hcryp->CR_saved;
+ CRYP_Write_KeyRegisters(hcryp, hcryp->Key_saved, hcryp->Init.KeySize);
+ CRYP_Write_IVRegisters(hcryp, hcryp->IV_saved);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* At the same time, set handle state back to READY to be able to resume the AES calculations
+ without the processing APIs returning HAL_BUSY when called. */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ }
+
+ /* Resume low-priority block processing under IT */
+ hcryp->ResumingFlag = 1U;
+ if (READ_BIT(hcryp->CR_saved, AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
+ {
+ if (HAL_CRYP_Encrypt_IT(hcryp, hcryp->pCrypInBuffPtr_saved, hcryp->Size_saved,
+ hcryp->pCrypOutBuffPtr_saved) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ if (HAL_CRYP_Decrypt_IT(hcryp, hcryp->pCrypInBuffPtr_saved, hcryp->Size_saved,
+ hcryp->pCrypOutBuffPtr_saved) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ }
+ }
+ return HAL_OK;
+}
+#endif /* defined (USE_HAL_CRYP_SUSPEND_RESUME) */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Exported_Functions_Group2 Encryption Decryption functions
+ * @brief Encryption Decryption functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Encrypt Decrypt functions #####
+ ==============================================================================
+ [..] This section provides API allowing to Encrypt/Decrypt Data following
+ (+) Standard AES algorithms supported by the peripheral:
+ - Electronic Code Book(ECB)
+ - Cipher Block Chaining (CBC)
+ - Counter mode (CTR)
+ - Cipher Block Chaining (CBC)
+ - Counter mode (CTR)
+ - Galois/counter mode (GCM)
+ - Counter with Cipher Block Chaining-Message(CCM)
+ [..] Three processing functions are available:
+ (+) Polling mode : HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
+ (+) Interrupt mode : HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
+ (+) DMA mode : HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA
+
+@endverbatim
+ * @{
+ */
+
+/* GCM message structure additional details
+
+ ICB
+ +-------------------------------------------------------+
+ | Initialization vector (IV) | Counter |
+ |----------------|----------------|-----------|---------|
+ 127 95 63 31 0
+
+
+ Bit Number Register Contents
+ ---------- --------------- -----------
+ 127 ...96 CRYP_IV1R[31:0] ICB[127:96]
+ 95 ...64 CRYP_IV1L[31:0] B0[95:64]
+ 63 ... 32 CRYP_IV0R[31:0] ICB[63:32]
+ 31 ... 0 CRYP_IV0L[31:0] ICB[31:0], where 32-bit counter= 0x2
+
+
+ GCM last block definition
+ +-------------------------------------------------------------------+
+ | Bit[0] | Bit[32] | Bit[64] | Bit[96] |
+ |-----------|--------------------|-----------|----------------------|
+ | 0x0 | Header length[31:0]| 0x0 | Payload length[31:0] |
+ |-----------|--------------------|-----------|----------------------|
+*/
+
+/* CCM message blocks description
+
+ (##) B0 block : According to NIST Special Publication 800-38C,
+ The first block B0 is formatted as follows, where l(m) is encoded in
+ most-significant-byte first order:
+
+ Octet Number Contents
+ ------------ ---------
+ 0 Flags
+ 1 ... 15-q Nonce N
+ 16-q ... 15 Q
+
+ the Flags field is formatted as follows:
+
+ Bit Number Contents
+ ---------- ----------------------
+ 7 Reserved (always zero)
+ 6 Adata
+ 5 ... 3 (t-2)/2
+ 2 ... 0 [q-1]3
+
+ - Q: a bit string representation of the octet length of P (plaintext)
+ - q The octet length of the binary representation of the octet length of the payload
+ - A nonce (N), n The octet length of the where n+q=15.
+ - Flags: most significant octet containing four flags for control information,
+ - t The octet length of the MAC.
+ (##) B1 block (header) : associated data length(a) concatenated with Associated Data (A)
+ the associated data length expressed in bytes (a) defined as below:
+ - If 0 < a < 216-28, then it is encoded as [a]16, i.e. two octets
+ - If 216-28 < a < 232, then it is encoded as 0xff || 0xfe || [a]32, i.e. six octets
+ - If 232 < a < 264, then it is encoded as 0xff || 0xff || [a]64, i.e. ten octets
+ (##) CTRx block : control blocks
+ - Generation of CTR1 from first block B0 information :
+ equal to B0 with first 5 bits zeroed and most significant bits storing octet
+ length of P also zeroed, then incremented by one
+
+ Bit Number Register Contents
+ ---------- --------------- -----------
+ 127 ...96 CRYP_IV1R[31:0] B0[127:96], where Q length bits are set to 0, except for
+ bit 0 that is set to 1
+ 95 ...64 CRYP_IV1L[31:0] B0[95:64]
+ 63 ... 32 CRYP_IV0R[31:0] B0[63:32]
+ 31 ... 0 CRYP_IV0L[31:0] B0[31:0], where flag bits set to 0
+
+ - Generation of CTR0: same as CTR1 with bit[0] set to zero.
+*/
+
+/**
+ * @brief Encryption mode.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pInput Pointer to the input buffer (plaintext)
+ * @param Size Length of the plaintext buffer either in word or in byte, according to DataWidthUnit
+ * @param pOutput Pointer to the output buffer(ciphertext)
+ * @param Timeout Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint16_t Size, uint32_t *pOutput,
+ uint32_t Timeout)
+{
+ uint32_t algo;
+ HAL_StatusTypeDef status;
+#ifdef USE_FULL_ASSERT
+ uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
+
+ /* Check input buffer size */
+ assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
+#endif /* USE_FULL_ASSERT */
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Change state Busy */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+ __HAL_LOCK(hcryp);
+
+ /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters */
+ hcryp->CrypInCount = 0U;
+ hcryp->CrypOutCount = 0U;
+ hcryp->pCrypInBuffPtr = pInput;
+ hcryp->pCrypOutBuffPtr = pOutput;
+
+ /* Calculate Size parameter in Byte */
+ if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
+ {
+ hcryp->Size = Size * 4U;
+ }
+ else
+ {
+ hcryp->Size = Size;
+ }
+
+ if (hcryp->Instance == AES)
+ {
+ /* Set the operating mode */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
+ }
+ else
+ {
+ /* Set the operating mode and normal key selection */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE | AES_CR_KMOD, CRYP_OPERATINGMODE_ENCRYPT | CRYP_KEYMODE_NORMAL);
+ }
+ /* Algo get algorithm selected */
+ algo = hcryp->Instance->CR & AES_CR_CHMOD;
+
+ switch (algo)
+ {
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+ /* AES encryption */
+ status = CRYP_AES_Encrypt(hcryp, Timeout);
+ break;
+
+ case CRYP_AES_GCM_GMAC:
+ /* AES GCM encryption */
+ status = CRYP_AESGCM_Process(hcryp, Timeout);
+ break;
+
+ case CRYP_AES_CCM:
+ /* AES CCM encryption */
+ status = CRYP_AESCCM_Process(hcryp, Timeout);
+ break;
+
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ }
+ }
+ else
+ {
+ /* Busy error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ status = HAL_ERROR;
+ }
+ return status;
+}
+
+/**
+ * @brief Decryption mode.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pInput Pointer to the input buffer (ciphertext )
+ * @param Size Length of the input buffer either in word or in byte, according to DataWidthUnit
+ * @param pOutput Pointer to the output buffer(plaintext)
+ * @param Timeout Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint16_t Size, uint32_t *pOutput,
+ uint32_t Timeout)
+{
+ HAL_StatusTypeDef status;
+ uint32_t algo;
+#ifdef USE_FULL_ASSERT
+ uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
+
+ /* Check input buffer size */
+ assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
+#endif /* USE_FULL_ASSERT */
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Change state Busy */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+ __HAL_LOCK(hcryp);
+
+ /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
+ hcryp->CrypInCount = 0U;
+ hcryp->CrypOutCount = 0U;
+ hcryp->pCrypInBuffPtr = pInput;
+ hcryp->pCrypOutBuffPtr = pOutput;
+
+ /* Calculate Size parameter in Byte*/
+ if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
+ {
+ hcryp->Size = Size * 4U;
+ }
+ else
+ {
+ hcryp->Size = Size;
+ }
+
+ /* Set Decryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
+
+ /* algo get algorithm selected */
+ algo = hcryp->Instance->CR & AES_CR_CHMOD;
+
+ switch (algo)
+ {
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+ /* AES decryption */
+ status = CRYP_AES_Decrypt(hcryp, Timeout);
+ break;
+
+ case CRYP_AES_GCM_GMAC:
+ /* AES GCM decryption */
+ status = CRYP_AESGCM_Process(hcryp, Timeout);
+ break;
+
+ case CRYP_AES_CCM:
+ /* AES CCM decryption */
+ status = CRYP_AESCCM_Process(hcryp, Timeout);
+ break;
+
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ }
+ }
+ else
+ {
+ /* Busy error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Encryption in interrupt mode.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pInput Pointer to the input buffer (plaintext)
+ * @param Size Length of the input buffer either in word or in byte, according to DataWidthUnit
+ * @param pOutput Pointer to the output buffer(ciphertext)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint16_t Size, uint32_t *pOutput)
+{
+ HAL_StatusTypeDef status;
+ uint32_t algo;
+#ifdef USE_FULL_ASSERT
+ uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
+
+ /* Check input buffer size */
+ assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
+#endif /* USE_FULL_ASSERT */
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Change state Busy */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+ __HAL_LOCK(hcryp);
+
+ /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
+#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
+ if (hcryp->ResumingFlag == 1U)
+ {
+ hcryp->ResumingFlag = 0U;
+ if (hcryp->Phase != CRYP_PHASE_HEADER_SUSPENDED)
+ {
+ hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved;
+ hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved;
+ }
+ else
+ {
+ hcryp->CrypInCount = 0U;
+ hcryp->CrypOutCount = 0U;
+ }
+ }
+ else
+#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
+ {
+ hcryp->CrypInCount = 0U;
+ hcryp->CrypOutCount = 0U;
+ }
+
+ hcryp->pCrypInBuffPtr = pInput;
+ hcryp->pCrypOutBuffPtr = pOutput;
+
+ /* Calculate Size parameter in Byte*/
+ if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
+ {
+ hcryp->Size = Size * 4U;
+ }
+ else
+ {
+ hcryp->Size = Size;
+ }
+
+ /* Set encryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
+
+ /* algo get algorithm selected */
+ algo = hcryp->Instance->CR & AES_CR_CHMOD;
+
+ switch (algo)
+ {
+
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+ /* AES encryption */
+ status = CRYP_AES_Encrypt_IT(hcryp);
+ break;
+
+ case CRYP_AES_GCM_GMAC:
+ /* AES GCM encryption */
+ status = CRYP_AESGCM_Process_IT(hcryp);
+ break;
+
+ case CRYP_AES_CCM:
+ /* AES CCM encryption */
+ status = CRYP_AESCCM_Process_IT(hcryp);
+ break;
+
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Busy error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Decryption in interrupt mode.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pInput Pointer to the input buffer (ciphertext )
+ * @param Size Length of the input buffer either in word or in byte, according to DataWidthUnit
+ * @param pOutput Pointer to the output buffer(plaintext)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint16_t Size, uint32_t *pOutput)
+{
+ HAL_StatusTypeDef status;
+ uint32_t algo;
+#ifdef USE_FULL_ASSERT
+ uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
+
+ /* Check input buffer size */
+ assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
+#endif /* USE_FULL_ASSERT */
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Change state Busy */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+ __HAL_LOCK(hcryp);
+
+ /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
+#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
+ if (hcryp->ResumingFlag == 1U)
+ {
+ hcryp->ResumingFlag = 0U;
+ if (hcryp->Phase != CRYP_PHASE_HEADER_SUSPENDED)
+ {
+ hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved;
+ hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved;
+ }
+ else
+ {
+ hcryp->CrypInCount = 0U;
+ hcryp->CrypOutCount = 0U;
+ }
+ }
+ else
+#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
+ {
+ hcryp->CrypInCount = 0U;
+ hcryp->CrypOutCount = 0U;
+ }
+ hcryp->pCrypInBuffPtr = pInput;
+ hcryp->pCrypOutBuffPtr = pOutput;
+
+ /* Calculate Size parameter in Byte*/
+ if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
+ {
+ hcryp->Size = Size * 4U;
+ }
+ else
+ {
+ hcryp->Size = Size;
+ }
+
+ /* Set decryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
+
+ /* algo get algorithm selected */
+ algo = hcryp->Instance->CR & AES_CR_CHMOD;
+
+ switch (algo)
+ {
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+ /* AES decryption */
+ status = CRYP_AES_Decrypt_IT(hcryp);
+ break;
+
+ case CRYP_AES_GCM_GMAC:
+ /* AES GCM decryption */
+ status = CRYP_AESGCM_Process_IT(hcryp);
+ break;
+
+ case CRYP_AES_CCM:
+ /* AES CCM decryption */
+ status = CRYP_AESCCM_Process_IT(hcryp);
+ break;
+
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Busy error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Encryption in DMA mode.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pInput Pointer to the input buffer (plaintext)
+ * @param Size Length of the input buffer either in word or in byte, according to DataWidthUnit
+ * @param pOutput Pointer to the output buffer(ciphertext)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint16_t Size, uint32_t *pOutput)
+{
+ HAL_StatusTypeDef status;
+ uint32_t count;
+ uint32_t algo;
+ uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+#ifdef USE_FULL_ASSERT
+ uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
+
+ /* Check input buffer size */
+ assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
+#endif /* USE_FULL_ASSERT */
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Change state Busy */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+ __HAL_LOCK(hcryp);
+
+ /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
+ hcryp->CrypInCount = 0U;
+ hcryp->CrypOutCount = 0U;
+ hcryp->pCrypInBuffPtr = pInput;
+ hcryp->pCrypOutBuffPtr = pOutput;
+
+ /* Calculate Size parameter in Byte*/
+ if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
+ {
+ hcryp->Size = Size * 4U;
+ }
+ else
+ {
+ hcryp->Size = Size;
+ }
+
+ /* Set encryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
+
+ /* algo get algorithm selected */
+ algo = hcryp->Instance->CR & AES_CR_CHMOD;
+
+ switch (algo)
+ {
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+ {
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ dokeyivconfig = 0U;
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ }
+ }
+
+ if ((dokeyivconfig == 1U) && (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG))
+ {
+ if (hcryp->Instance == AES)
+ {
+ /* Set the Key */
+ if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
+ {
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+ }
+ else /* After sharing the key, AES should set KMOD[1:0] to 00.*/
+ {
+ hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED;
+ }
+ }
+ else
+ {
+ /* We should re-write Key, in the case where we change key after first operation */
+ if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
+ {
+ /* Set the Key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+ }
+ /* Wait for KEYVALID flag to be set */
+ count = CRYP_TIMEOUT_KEYPREPARATION;
+ do
+ {
+ count--;
+ if (count == 0U)
+ {
+ /* Disable the SAES peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_KEYVALID));
+ }
+ /* Set the Initialization Vector */
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ CRYP_SetIV(hcryp);
+ }
+ } /* If (dokeyivconfig == 1U) */
+
+ /* Peripheral Key configuration to not do, IV to configure for CBC */
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYNOCONFIG)
+ {
+ if (hcryp->Init.Algorithm == CRYP_AES_CBC)
+ {
+ /* Set the Initialization Vector */
+ CRYP_SetIV(hcryp);
+ }
+ }
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Start DMA process transfer for AES */
+ CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size), (uint32_t)(hcryp->pCrypOutBuffPtr));
+ status = HAL_OK;
+ break;
+
+ case CRYP_AES_GCM_GMAC:
+ /* AES GCM encryption */
+ status = CRYP_AESGCM_Process_DMA(hcryp);
+ break;
+
+ case CRYP_AES_CCM:
+ /* AES CCM encryption */
+ status = CRYP_AESCCM_Process_DMA(hcryp);
+ break;
+
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Busy error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Decryption in DMA mode.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pInput Pointer to the input buffer (ciphertext )
+ * @param Size Length of the input buffer either in word or in byte, according to DataWidthUnit
+ * @param pOutput Pointer to the output buffer(plaintext)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint16_t Size, uint32_t *pOutput)
+{
+ HAL_StatusTypeDef status;
+ uint32_t algo;
+#ifdef USE_FULL_ASSERT
+ uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
+
+ /* Check input buffer size */
+ assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
+#endif /* USE_FULL_ASSERT */
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
+ {
+
+ /* Change state Busy */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+ __HAL_LOCK(hcryp);
+
+ /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
+ hcryp->CrypInCount = 0U;
+ hcryp->CrypOutCount = 0U;
+ hcryp->pCrypInBuffPtr = pInput;
+ hcryp->pCrypOutBuffPtr = pOutput;
+
+ /* Calculate Size parameter in Byte*/
+ if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
+ {
+ hcryp->Size = Size * 4U;
+ }
+ else
+ {
+ hcryp->Size = Size;
+ }
+
+ /* Set decryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
+
+ /* algo get algorithm selected */
+ algo = hcryp->Instance->CR & AES_CR_CHMOD;
+
+ switch (algo)
+ {
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+ /* AES decryption */
+ status = CRYP_AES_Decrypt_DMA(hcryp);
+ break;
+
+ case CRYP_AES_GCM_GMAC:
+ /* AES GCM decryption */
+ status = CRYP_AESGCM_Process_DMA(hcryp);
+ break;
+
+ case CRYP_AES_CCM:
+ /* AES CCM decryption */
+ status = CRYP_AESCCM_Process_DMA(hcryp);
+ break;
+
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Busy error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ status = HAL_ERROR;
+ }
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Exported_Functions_Group3 CRYP IRQ handler management
+ * @brief CRYP IRQ handler.
+ *
+@verbatim
+ ==============================================================================
+ ##### CRYP IRQ handler management #####
+ ==============================================================================
+[..] This section provides CRYP IRQ handler and callback functions.
+ (+) HAL_CRYP_IRQHandler CRYP interrupt request
+ (+) HAL_CRYP_InCpltCallback input data transfer complete callback
+ (+) HAL_CRYP_OutCpltCallback output data transfer complete callback
+ (+) HAL_CRYP_ErrorCallback CRYP error callback
+ (+) HAL_CRYP_GetState return the CRYP state
+ (+) HAL_CRYP_GetError return the CRYP error code
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function handles cryptographic interrupt request.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval None
+ */
+void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
+{
+ /* Check if Read or write error occurred */
+ if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_RWEIE) != RESET)
+ {
+ /* If write Error occurred */
+ if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_WRERR) != RESET)
+ {
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_WRITE;
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RWEIF);
+ }
+ /* If read Error occurred */
+ if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_RDERR) != RESET)
+ {
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_READ;
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RWEIF);
+ }
+ }
+ /* Check if Key error occurred */
+ if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_KEIE) != RESET)
+ {
+ if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_KEIF) != RESET)
+ {
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_KEY;
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_KEIF);
+ /*Call weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+ }
+ }
+
+ if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_CCF) != RESET)
+ {
+ if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET)
+ {
+ /* Clear computation complete flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+ if ((hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) || (hcryp->Init.Algorithm == CRYP_AES_CCM))
+ {
+ /* if header phase */
+ if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER)
+ {
+ CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
+ }
+ else /* if payload phase */
+ {
+ CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
+ }
+ }
+ else /* AES Algorithm ECB,CBC or CTR*/
+ {
+ CRYP_AES_IT(hcryp);
+ }
+ }
+ }
+}
+
+/**
+ * @brief Return the CRYP error code.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for the CRYP peripheral
+ * @retval CRYP error code
+ */
+uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp)
+{
+ return hcryp->ErrorCode;
+}
+
+/**
+ * @brief Returns the CRYP state.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @retval HAL state
+ */
+HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
+{
+ return hcryp->State;
+}
+
+/**
+ * @brief Input FIFO transfer completed callback.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @retval None
+ */
+__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcryp);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CRYP_InCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Output FIFO transfer completed callback.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @retval None
+ */
+__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcryp);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CRYP_OutCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief CRYP error callback.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @retval None
+ */
+__weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcryp);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CRYP_ErrorCallback could be implemented in the user file
+ */
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup CRYP_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Encryption in ECB/CBC & CTR Algorithm with AES Standard
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure
+ * @param Timeout specify Timeout value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
+ uint16_t incount; /* Temporary CrypInCount Value */
+ uint16_t outcount; /* Temporary CrypOutCount Value */
+ uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+ uint32_t tickstart;
+
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+ {
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ dokeyivconfig = 0U;
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ }
+ }
+
+ if ((dokeyivconfig == 1U) && (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG))
+ {
+ if (hcryp->Instance == AES)
+ {
+ /* Set the Key */
+ if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
+ {
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+ }
+ else /* After sharing the key, AES should set KMOD[1:0] to 00.*/
+ {
+ hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED;
+ }
+ }
+ else
+ {
+ /* We should re-write Key, in the case where we change key after first operation */
+ if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
+ {
+ /* Set the Key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+ }
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_KEYVALID))
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ }
+ }
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ /* Set the Initialization Vector */
+ CRYP_SetIV(hcryp);
+ }
+ } /* If (dokeyivconfig == 1U) */
+
+ /* Peripheral Key configuration to not do, IV to configure for CBC */
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYNOCONFIG)
+ {
+ if (hcryp->Init.Algorithm == CRYP_AES_CBC)
+ {
+ /* Set the Initialization Vector*/
+ CRYP_SetIV(hcryp);
+ }
+ }
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ incount = hcryp->CrypInCount;
+ outcount = hcryp->CrypOutCount;
+ while ((incount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
+ {
+ /* Write plain data and get cipher data */
+ CRYP_AES_ProcessData(hcryp, Timeout);
+ incount = hcryp->CrypInCount;
+ outcount = hcryp->CrypOutCount;
+ }
+
+ /* Disable CRYP */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Encryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp)
+{
+ uint32_t count;
+ uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+ {
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ dokeyivconfig = 0U;
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ }
+ }
+
+ if ((dokeyivconfig == 1U) && (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG))
+ {
+ if (hcryp->Instance == AES)
+ {
+ /* Set the Key */
+ if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
+ {
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+ }
+ else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
+ {
+ hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED;
+ }
+ }
+ else
+ {
+ /* we should re-write Key, in the case where we change key after first operation*/
+ if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
+ {
+ /* Set the Key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+ }
+ /* Wait for KEYVALID flag to be set */
+ count = CRYP_TIMEOUT_KEYPREPARATION;
+ do
+ {
+ count--;
+ if (count == 0U)
+ {
+ /* Disable the SAES peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_KEYVALID));
+ }
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ /* Set the Initialization Vector*/
+ CRYP_SetIV(hcryp);
+ }
+ } /* if (dokeyivconfig == 1U) */
+ /* Peripheral Key configuration to not do, IV to configure for CBC */
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYNOCONFIG)
+ {
+ if (hcryp->Init.Algorithm == CRYP_AES_CBC)
+ {
+ /* Set the Initialization Vector*/
+ CRYP_SetIV(hcryp);
+ }
+ }
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ if (hcryp->Size != 0U)
+ {
+
+ /* Enable computation complete flag and Key, Read and Write error interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Write the input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ }
+ else
+ {
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Decryption in ECB/CBC & CTR mode with AES Standard
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure
+ * @param Timeout Specify Timeout value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
+ uint16_t incount; /* Temporary CrypInCount Value */
+ uint16_t outcount; /* Temporary CrypOutCount Value */
+ uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+ {
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ dokeyivconfig = 0U;
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ }
+ }
+
+ if (dokeyivconfig == 1U)
+ {
+ if (hcryp->Instance == AES)
+ {
+ /* Key preparation for ECB/CBC */
+ if (hcryp->Init.Algorithm != CRYP_AES_CTR) /*ECB or CBC*/
+ {
+ /* key preparation for decryption, operating mode 2*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD, CRYP_KEYMODE_NORMAL);
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
+
+ /* Set the Key */
+ if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
+ {
+ if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
+ {
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+ }
+ else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
+ {
+ hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED;
+ }
+ }
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Wait for CCF flag to be raised */
+ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+ /* Return to decryption operating mode(Mode 3)*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
+ }
+ else /*Algorithm CTR */
+ {
+ /* Set the Key */
+ if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
+ {
+ if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
+ {
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+ }
+ else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
+ {
+ hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED;
+ }
+ }
+ }
+ }
+ else /*SAES*/
+ {
+ /* key preparation for decryption, operating mode 2*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
+
+ /* we should re-write Key, in the case where we change key after first operation*/
+ if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
+ {
+ if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
+ {
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+ }
+ }
+
+ /* Enable SAES */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Wait for CCF flag to be raised */
+ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+ /* End of Key preparation for ECB/CBC */
+ /* Return to decryption operating mode(Mode 3)*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
+ }
+ /* Set IV */
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ /* Set the Initialization Vector*/
+ CRYP_SetIV(hcryp);
+ }
+ } /* if (dokeyivconfig == 1U) */
+
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ incount = hcryp->CrypInCount;
+ outcount = hcryp->CrypOutCount;
+ while ((incount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
+ {
+ /* Write plain data and get cipher data */
+ CRYP_AES_ProcessData(hcryp, Timeout);
+ incount = hcryp->CrypInCount;
+ outcount = hcryp->CrypOutCount;
+ }
+
+ /* Disable CRYP */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ return HAL_OK;
+}
+/**
+ * @brief Decryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp)
+{
+ uint32_t count;
+ uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+ {
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ dokeyivconfig = 0U;
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ }
+ }
+
+ if (dokeyivconfig == 1U)
+ {
+ if (hcryp->Instance == AES)
+ {
+ /* Key preparation for ECB/CBC */
+ if (hcryp->Init.Algorithm != CRYP_AES_CTR)
+ {
+ /* key preparation for decryption, operating mode 2*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD, CRYP_KEYMODE_NORMAL);
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
+
+ /* Set the Key */
+ if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
+ {
+ if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
+ {
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+ }
+ else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
+ {
+ hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED;
+ }
+ }
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Wait for CCF flag to be raised */
+ count = CRYP_TIMEOUT_KEYPREPARATION;
+ do
+ {
+ count--;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+ /* Return to decryption operating mode(Mode 3)*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
+ }
+
+ else /*Algorithm CTR */
+ {
+ if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
+ {
+ if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
+ {
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+ }
+ else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
+ {
+ hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED;
+ }
+ }
+ }
+ }
+ else /*SAES*/
+ {
+ /* key preparation for decryption, operating mode 2*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
+
+ /* we should re-write Key, in the case where we change key after first operation*/
+ if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
+ {
+ if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
+ {
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+ }
+ }
+ /* Enable SAES */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Wait for CCF flag to be raised */
+ count = CRYP_TIMEOUT_KEYPREPARATION;
+ do
+ {
+ count--;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+ /* End of Key preparation for ECB/CBC */
+ /* Return to decryption operating mode(Mode 3)*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
+ }
+ /* Set IV */
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ /* Set the Initialization Vector*/
+ CRYP_SetIV(hcryp);
+ }
+ } /* if (dokeyivconfig == 1U) */
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+ if (hcryp->Size != 0U)
+ {
+ /* Enable computation complete flag and error interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Write the input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ }
+ else
+ {
+ __HAL_UNLOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ }
+
+ return HAL_OK;
+}
+/**
+ * @brief Decryption in ECB/CBC & CTR mode with AES Standard using DMA mode
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp)
+{
+ uint32_t count;
+ uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+ {
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ dokeyivconfig = 0U;
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ }
+ }
+
+ if (dokeyivconfig == 1U)
+ {
+ if (hcryp->Instance == AES)
+ {
+ /* Key preparation for ECB/CBC */
+ if (hcryp->Init.Algorithm != CRYP_AES_CTR)
+ {
+ /* key preparation for decryption, operating mode 2*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD, CRYP_KEYMODE_NORMAL);
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
+
+ /* Set the Key */
+ if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
+ {
+ if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
+ {
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+ }
+ else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
+ {
+ hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED;
+ }
+ }
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Wait for CCF flag to be raised */
+ count = CRYP_TIMEOUT_KEYPREPARATION;
+ do
+ {
+ count--;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+ /* Return to decryption operating mode(Mode 3)*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
+ }
+ else /*Algorithm CTR */
+ {
+ /* Set the Key */
+ if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
+ {
+ if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
+ {
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+ }
+ else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
+ {
+ hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED;
+ }
+ }
+ }
+ }
+ else /*SAES*/
+ {
+ /* key preparation for decryption, operating mode 2*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
+
+ /* we should re-write Key, in the case where we change key after first operation*/
+ if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
+ {
+ if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
+ {
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+ }
+ }
+ /* Enable SAES */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Wait for CCF flag to be raised */
+ count = CRYP_TIMEOUT_KEYPREPARATION;
+ do
+ {
+ count--;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+ /* End of Key preparation for ECB/CBC */
+ /* Return to decryption operating mode(Mode 3)*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
+ }
+
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ /* Set the Initialization Vector*/
+ CRYP_SetIV(hcryp);
+ }
+ } /* if (dokeyivconfig == 1U) */
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ if (hcryp->Size != 0U)
+ {
+ /* Set the input and output addresses and start DMA transfer */
+ CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size), (uint32_t)(hcryp->pCrypOutBuffPtr));
+ }
+ else
+ {
+ __HAL_UNLOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ }
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief DMA CRYP input data process complete callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
+{
+ CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ uint32_t loopcounter;
+ uint32_t headersize_in_bytes;
+ uint32_t tmp;
+ uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
+ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
+ 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
+ }; /* 8-bit data type */
+
+ /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit
+ in the DMACR register */
+ CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
+
+ if (hcryp->Phase == CRYP_PHASE_HEADER_DMA_FEED)
+ {
+ /* DMA is disabled, CCF is meaningful. Wait for computation completion before moving forward */
+ CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE);
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
+ {
+ headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
+ }
+ else
+ {
+ headersize_in_bytes = hcryp->Init.HeaderSize;
+ }
+
+ if ((headersize_in_bytes % 16U) != 0U)
+ {
+ /* Write last words that couldn't be fed by DMA */
+ hcryp->CrypHeaderCount = (uint16_t)((headersize_in_bytes / 16U) * 4U);
+ for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ }
+ /* If the header size is a multiple of words */
+ if ((headersize_in_bytes % 4U) == 0U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ }
+ else
+ {
+ /* Enter last bytes, padded with zeros */
+ tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
+ hcryp->Instance->DINR = tmp;
+ loopcounter++;
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ }
+
+ /* Wait for computation completion before moving forward */
+ CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE);
+ } /* if ((headersize_in_bytes % 16U) != 0U) */
+
+ /* Set to 0 the number of non-valid bytes using NPBLB register*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
+
+ /* Select payload phase once the header phase is performed */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+ /* Initiate payload DMA IN and processed data DMA OUT transfers */
+ (void)CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp);
+ }
+ /* Call input data transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA CRYP output data process complete callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
+{
+ uint32_t count;
+ uint32_t npblb;
+ uint32_t lastwordsize;
+ uint32_t temp[4]; /* Temporary CrypOutBuff */
+ uint32_t mode;
+
+ CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Disable the DMA transfer for output FIFO request by resetting
+ the DMAOUTEN bit in the CR register */
+
+ CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);
+
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+ /* Last block transfer in case of GCM or CCM with Size not %16*/
+ if (((hcryp->Size) % 16U) != 0U)
+ {
+ /* set CrypInCount and CrypOutCount to exact number of word already computed via DMA */
+ hcryp->CrypInCount = (hcryp->Size / 16U) * 4U;
+ hcryp->CrypOutCount = hcryp->CrypInCount;
+
+ /* Compute the number of padding bytes in last block of payload */
+ npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - ((uint32_t)hcryp->Size);
+
+ mode = hcryp->Instance->CR & AES_CR_MODE;
+ if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) ||
+ ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
+ {
+ /* Specify the number of non-valid bytes using NPBLB register*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
+ }
+
+ /* Number of valid words (lastwordsize) in last block */
+ if ((npblb % 4U) == 0U)
+ {
+ lastwordsize = (16U - npblb) / 4U;
+ }
+ else
+ {
+ lastwordsize = ((16U - npblb) / 4U) + 1U;
+ }
+
+ /* Last block optionally pad the data with zeros*/
+ for (count = 0U; count < lastwordsize; count++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ }
+ while (count < 4U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
+ count++;
+ }
+
+ CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE);
+
+ /*Read the output block from the output FIFO */
+ for (count = 0U; count < 4U; count++)
+ {
+ /* Read the output block from the output FIFO and put them in temporary buffer
+ then get CrypOutBuff from temporary buffer */
+ temp[count] = hcryp->Instance->DOUTR;
+ }
+
+ count = 0U;
+ while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (count < 4U))
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[count];
+ hcryp->CrypOutCount++;
+ count++;
+ }
+ }
+
+ if (((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC)
+ && ((hcryp->Init.Algorithm & CRYP_AES_CCM) != CRYP_AES_CCM))
+ {
+ /* Disable CRYP (not allowed in GCM)*/
+ __HAL_CRYP_DISABLE(hcryp);
+ }
+
+ /* Change the CRYP state to ready */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+
+ /* Call output data transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Output complete callback*/
+ hcryp->OutCpltCallback(hcryp);
+#else
+ /*Call legacy weak Output complete callback*/
+ HAL_CRYP_OutCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA CRYP communication error callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
+{
+ CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* DMA error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
+
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+ /* Call error callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief Set the DMA configuration and start the DMA transfer
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param inputaddr address of the input buffer
+ * @param Size size of the input and output buffers in words, must be a multiple of 4.
+ * @param outputaddr address of the output buffer
+ * @retval None
+ */
+static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
+{
+ HAL_StatusTypeDef status;
+
+ /* Set the CRYP DMA transfer complete callback */
+ hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
+
+ /* Set the DMA input error callback */
+ hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
+
+ /* Set the CRYP DMA transfer complete callback */
+ hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
+
+ /* Set the DMA output error callback */
+ hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
+
+ if ((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC)
+ {
+ /* Enable CRYP (not allowed in GCM & CCM)*/
+ __HAL_CRYP_ENABLE(hcryp);
+ }
+
+ /* Enable the DMA input channel */
+ if ((hcryp->hdmain->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if ((hcryp->hdmain->LinkedListQueue != NULL) && (hcryp->hdmain->LinkedListQueue->Head != NULL))
+ {
+ /* Enable the DMA channel */
+ hcryp->hdmain->LinkedListQueue->Head->\
+ LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = Size; /* Set DMA data size */
+ hcryp->hdmain->LinkedListQueue->Head->\
+ LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = inputaddr; /* Set DMA source address */
+ hcryp->hdmain->LinkedListQueue->Head->\
+ LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hcryp->Instance->DINR; /* Set DMA destination address */
+
+ status = HAL_DMAEx_List_Start_IT(hcryp->hdmain);
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size);
+ }
+
+ if (status != HAL_OK)
+ {
+ /* DMA error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
+
+ /*Call registered error callback*/
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ /* Enable the DMA output channel */
+ if ((hcryp->hdmaout->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if ((hcryp->hdmaout->LinkedListQueue != NULL) && (hcryp->hdmaout->LinkedListQueue->Head != NULL))
+ {
+ /* Enable the DMA channel */
+ hcryp->hdmaout->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = \
+ Size; /* Set DMA data size */
+ hcryp->hdmaout->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = \
+ (uint32_t)&hcryp->Instance->DOUTR; /* Set DMA source address */
+ hcryp->hdmaout->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = \
+ outputaddr; /* Set DMA destination address */
+
+ status = HAL_DMAEx_List_Start_IT(hcryp->hdmaout);
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size);
+ }
+
+ if (status != HAL_OK)
+ {
+ /* DMA error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
+
+ /* Call error callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ /* Enable In and Out DMA requests */
+ SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN));
+}
+
+/**
+ * @brief Set the DMA configuration and start the header DMA transfer
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param inputaddr address of the input buffer
+ * @param Size size of the input buffer in words, must be a multiple of 4
+ * @retval None
+ */
+static HAL_StatusTypeDef CRYP_SetHeaderDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size)
+{
+ HAL_StatusTypeDef status;
+
+ /* Set the CRYP DMA transfer complete callback */
+ hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
+
+ /* Set the DMA input error callback */
+ hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
+
+ /* Mark that header is fed to the peripheral in DMA mode */
+ hcryp->Phase = CRYP_PHASE_HEADER_DMA_FEED;
+
+ /* Enable the DMA input channel */
+ if ((hcryp->hdmain->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if ((hcryp->hdmain->LinkedListQueue != NULL) && (hcryp->hdmain->LinkedListQueue->Head != NULL))
+ {
+ /* Enable the DMA channel */
+ hcryp->hdmain->LinkedListQueue->Head->\
+ LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = Size; /* Set DMA data size */
+ hcryp->hdmain->LinkedListQueue->Head->\
+ LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = inputaddr; /* Set DMA source address */
+ hcryp->hdmain->LinkedListQueue->Head->\
+ LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hcryp->Instance->DINR; /* Set DMA destination address */
+
+ status = HAL_DMAEx_List_Start_IT(hcryp->hdmain);
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size);
+ }
+ if (status != HAL_OK)
+ {
+ /* DMA error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
+
+ /* Call error callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+
+ /* Enable IN DMA requests */
+ SET_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
+
+ return status;
+}
+
+/**
+ * @brief Process Data: Write Input data in polling mode and used in AES functions.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param Timeout Specify Timeout value
+ * @retval None
+ */
+static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
+
+ uint32_t temp[4]; /* Temporary CrypOutBuff */
+ uint32_t i;
+
+ /* Write the input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+
+ /* Wait for CCF flag to be raised */
+ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /*Call registered error callback*/
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+ /* Read the output block from the output FIFO and put them in temporary buffer then
+ get CrypOutBuff from temporary buffer*/
+ for (i = 0U; i < 4U; i++)
+ {
+ temp[i] = hcryp->Instance->DOUTR;
+ }
+ i = 0U;
+ while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+ hcryp->CrypOutCount++;
+ i++;
+ }
+}
+
+/**
+ * @brief Handle CRYP block input/output data handling under interruption.
+ * @note The function is called under interruption only, once
+ * interruptions have been enabled by HAL_CRYP_Encrypt_IT or HAL_CRYP_Decrypt_IT.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @retval HAL status
+ */
+static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
+{
+ uint32_t temp[4]; /* Temporary CrypOutBuff */
+ uint32_t i;
+
+ if (hcryp->State == HAL_CRYP_STATE_BUSY)
+ {
+ /* Read the output block from the output FIFO and put them in temporary buffer then
+ get CrypOutBuff from temporary buffer*/
+ for (i = 0U; i < 4U; i++)
+ {
+ temp[i] = hcryp->Instance->DOUTR;
+ }
+ i = 0U;
+ while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+ hcryp->CrypOutCount++;
+ i++;
+ }
+ if (hcryp->CrypOutCount == (hcryp->Size / 4U))
+ {
+ /* Disable Computation Complete flag and errors interrupts */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Disable CRYP */
+ __HAL_CRYP_DISABLE(hcryp);
+ __HAL_UNLOCK(hcryp);
+
+ /* Call Output transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Output complete callback*/
+ hcryp->OutCpltCallback(hcryp);
+#else
+ /*Call legacy weak Output complete callback*/
+ HAL_CRYP_OutCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ else
+ {
+#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
+ /* If suspension flag has been raised, suspend processing
+ only if not already at the end of the payload */
+ if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
+ {
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+ /* reset SuspendRequest */
+ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
+ /* Disable Computation Complete Flag and Errors Interrupts */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_SUSPENDED;
+ /* Mark that the payload phase is suspended */
+ hcryp->Phase = CRYP_PHASE_PAYLOAD_SUSPENDED;
+ __HAL_UNLOCK(hcryp);
+ }
+ else
+#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
+ {
+ /* Write the input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+
+ if (hcryp->CrypInCount == (hcryp->Size / 4U))
+ {
+ /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ }
+ }
+ }
+ else
+ {
+ /* Busy error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief Writes Key in Key registers.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param KeySize Size of Key
+ * @note If pKey is NULL, the Key registers are not written.
+ * @retval None
+ */
+static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize)
+{
+ if (hcryp->Init.pKey != NULL)
+ {
+ switch (KeySize)
+ {
+ case CRYP_KEYSIZE_256B:
+ hcryp->Instance->KEYR7 = *(uint32_t *)(hcryp->Init.pKey);
+ hcryp->Instance->KEYR6 = *(uint32_t *)(hcryp->Init.pKey + 1U);
+ hcryp->Instance->KEYR5 = *(uint32_t *)(hcryp->Init.pKey + 2U);
+ hcryp->Instance->KEYR4 = *(uint32_t *)(hcryp->Init.pKey + 3U);
+ hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey + 4U);
+ hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 5U);
+ hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 6U);
+ hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 7U);
+ break;
+ case CRYP_KEYSIZE_128B:
+ hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey);
+ hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 1U);
+ hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 2U);
+ hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 3U);
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+/**
+ * @brief Writes initialization vector in IV registers.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @note If IV is NULL, the IV registers are not written.
+ * @retval None
+ */
+static void CRYP_SetIV(CRYP_HandleTypeDef *hcryp)
+{
+ if (hcryp->Init.pInitVect != NULL)
+ {
+ /* Set the Initialization Vector*/
+ hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
+ hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
+ hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
+ }
+}
+
+/**
+ * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
+ uint32_t tickstart;
+ uint32_t wordsize = ((uint32_t)hcryp->Size / 4U);
+ uint32_t npblb;
+ uint32_t temp[4]; /* Temporary CrypOutBuff */
+ uint32_t index;
+ uint32_t lastwordsize;
+ uint32_t incount; /* Temporary CrypInCount Value */
+ uint32_t outcount; /* Temporary CrypOutCount Value */
+ uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+ {
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ dokeyivconfig = 0U;
+ hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
+ }
+ }
+ else
+ {
+ hcryp->SizesSum = hcryp->Size;
+ }
+
+ if (dokeyivconfig == 1U)
+ {
+
+ /* Reset CrypHeaderCount */
+ hcryp->CrypHeaderCount = 0U;
+
+ /****************************** Init phase **********************************/
+
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
+
+ /* Set the Key */
+ if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
+ {
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+ }
+ else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
+ {
+ hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED;
+ }
+
+ /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
+ CRYP_SetIV(hcryp);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* just wait for hash computation */
+ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+ /************************ Header phase *************************************/
+
+ if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /*************************Payload phase ************************************/
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Select payload phase once the header phase is performed */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+ /* Set to 0 the number of non-valid bytes using NPBLB register*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
+
+ } /* if (dokeyivconfig == 1U) */
+
+ if ((hcryp->Size % 16U) != 0U)
+ {
+ /* recalculate wordsize */
+ wordsize = ((wordsize / 4U) * 4U);
+ }
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Write input data and get output Data */
+ incount = hcryp->CrypInCount;
+ outcount = hcryp->CrypOutCount;
+ while ((incount < wordsize) && (outcount < wordsize))
+ {
+ /* Write plain data and get cipher data */
+ CRYP_AES_ProcessData(hcryp, Timeout);
+
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state & error code */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ incount = hcryp->CrypInCount;
+ outcount = hcryp->CrypOutCount;
+ }
+
+ if ((hcryp->Size % 16U) != 0U)
+ {
+ /* Compute the number of padding bytes in last block of payload */
+ npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - ((uint32_t)hcryp->Size);
+
+ /* Set Npblb in case of AES GCM payload encryption to get right tag*/
+ if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
+ {
+ /* Set to 0 the number of non-valid bytes using NPBLB register*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
+ }
+ /* Number of valid words (lastwordsize) in last block */
+ if ((npblb % 4U) == 0U)
+ {
+ lastwordsize = (16U - npblb) / 4U;
+ }
+ else
+ {
+ lastwordsize = ((16U - npblb) / 4U) + 1U;
+ }
+ /* last block optionally pad the data with zeros*/
+ for (index = 0U; index < lastwordsize; index ++)
+ {
+ /* Write the last Input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ }
+ while (index < 4U)
+ {
+ /* pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0U;
+ index++;
+ }
+ /* Wait for CCF flag to be raised */
+ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+ /*Read the output block from the output FIFO */
+ for (index = 0U; index < 4U; index++)
+ {
+ /* Read the output block from the output FIFO and put them in temporary buffer then
+ get CrypOutBuff from temporary buffer */
+ temp[index] = hcryp->Instance->DOUTR;
+ }
+ for (index = 0U; index < lastwordsize; index++)
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp[index];
+ hcryp->CrypOutCount++;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG in interrupt mode
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
+{
+ uint32_t count;
+ uint32_t loopcounter;
+ uint32_t lastwordsize;
+ uint32_t npblb;
+ uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+ uint32_t headersize_in_bytes;
+ uint32_t tmp;
+ uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
+ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
+ 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
+ }; /* 8-bit data type */
+
+#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
+ if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED))
+ {
+ CRYP_PhaseProcessingResume(hcryp);
+ return HAL_OK;
+ }
+#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
+
+ /* Manage header size given in bytes to handle cases where
+ header size is not a multiple of 4 bytes */
+ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
+ {
+ headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
+ }
+ else
+ {
+ headersize_in_bytes = hcryp->Init.HeaderSize;
+ }
+
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+ {
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ dokeyivconfig = 0U;
+ hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
+ }
+ }
+ else
+ {
+ hcryp->SizesSum = hcryp->Size;
+ }
+
+ /* Configure Key, IV and process message (header and payload) */
+ if (dokeyivconfig == 1U)
+ {
+ /* Reset CrypHeaderCount */
+ hcryp->CrypHeaderCount = 0U;
+
+ /******************************* Init phase *********************************/
+
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
+
+ /* Set the Key */
+ if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
+ {
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+ }
+ else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
+ {
+ hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED;
+ }
+
+ /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
+ CRYP_SetIV(hcryp);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* just wait for hash computation */
+ count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+ do
+ {
+ count--;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+ /***************************** Header phase *********************************/
+
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
+ /* Enable computation complete flag and error interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ if (hcryp->Init.HeaderSize == 0U) /*header phase is skipped*/
+ {
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Select payload phase once the header phase is performed */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
+
+ /* Set to 0 the number of non-valid bytes using NPBLB register*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
+
+ /* Write the payload Input block in the IN FIFO */
+ if (hcryp->Size == 0U)
+ {
+ /* Disable interrupts */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ }
+ else if (hcryp->Size >= 16U)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ if (hcryp->CrypInCount == (hcryp->Size / 4U))
+ {
+ /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ }
+ else /* Size < 16Bytes : first block is the last block*/
+ {
+ /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption:
+ Workaround is implemented in polling mode, so if last block of
+ payload <128bit do not use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */
+
+
+ /* Compute the number of padding bytes in last block of payload */
+ npblb = 16U - ((uint32_t)hcryp->Size);
+
+ if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
+ {
+ /* Set to 0 the number of non-valid bytes using NPBLB register*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
+ }
+
+ /* Number of valid words (lastwordsize) in last block */
+ if ((npblb % 4U) == 0U)
+ {
+ lastwordsize = (16U - npblb) / 4U;
+ }
+ else
+ {
+ lastwordsize = ((16U - npblb) / 4U) + 1U;
+ }
+
+ /* last block optionally pad the data with zeros*/
+ for (loopcounter = 0U; loopcounter < lastwordsize ; loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ }
+ while (loopcounter < 4U)
+ {
+ /* pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ }
+ }
+ /* Enter header data */
+ /* Cher first whether header length is small enough to enter the full header in one shot */
+ else if (headersize_in_bytes <= 16U)
+ {
+ /* Write header data, padded with zeros if need be */
+ for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ }
+ /* If the header size is a multiple of words */
+ if ((headersize_in_bytes % 4U) == 0U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ hcryp->CrypHeaderCount++;
+ }
+ }
+ else
+ {
+ /* Enter last bytes, padded with zeros */
+ tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
+ hcryp->Instance->DINR = tmp;
+ loopcounter++;
+ hcryp->CrypHeaderCount++ ;
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ hcryp->CrypHeaderCount++;
+ }
+ }
+ /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Write the first input header block in the Input FIFO,
+ the following header data will be fed after interrupt occurrence */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+ }
+
+ } /* end of if (dokeyivconfig == 1U) */
+ else /* Key and IV have already been configured,
+ header has already been processed;
+ only process here message payload */
+ {
+
+ /* Enable computation complete flag and error interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
+
+ /* Set to 0 the number of non-valid bytes using NPBLB register*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
+
+ /* Write the payload Input block in the IN FIFO */
+ if (hcryp->Size == 0U)
+ {
+ /* Disable interrupts */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ }
+ else if (hcryp->Size >= 16U)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ if (hcryp->CrypInCount == (hcryp->Size / 4U))
+ {
+ /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ }
+ else /* Size < 16Bytes : first block is the last block*/
+ {
+ /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption:
+ Workaround is implemented in polling mode, so if last block of
+ payload <128bit do not use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */
+
+
+ /* Compute the number of padding bytes in last block of payload */
+ npblb = 16U - ((uint32_t)hcryp->Size);
+
+ if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
+ {
+ /* Set to 0 the number of non-valid bytes using NPBLB register*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
+ }
+
+ /* Number of valid words (lastwordsize) in last block */
+ if ((npblb % 4U) == 0U)
+ {
+ lastwordsize = (16U - npblb) / 4U;
+ }
+ else
+ {
+ lastwordsize = ((16U - npblb) / 4U) + 1U;
+ }
+
+ /* last block optionally pad the data with zeros*/
+ for (loopcounter = 0U; loopcounter < lastwordsize ; loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ }
+ while (loopcounter < 4U)
+ {
+ /* pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG using DMA
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
+{
+ uint32_t count;
+ uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+ {
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ dokeyivconfig = 0U;
+ hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
+ }
+ }
+ else
+ {
+ hcryp->SizesSum = hcryp->Size;
+ }
+
+ if (dokeyivconfig == 1U)
+ {
+
+ /* Reset CrypHeaderCount */
+ hcryp->CrypHeaderCount = 0U;
+
+ /*************************** Init phase ************************************/
+
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
+
+ /* Set the Key */
+ if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
+ {
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+ }
+ else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
+ {
+ hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED;
+ }
+
+ /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
+ CRYP_SetIV(hcryp);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* just wait for hash computation */
+ count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+ do
+ {
+ count--;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+ /************************ Header phase *************************************/
+
+ if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ }
+ else
+ {
+ /* Initialization and header phases already done, only do payload phase */
+ if (CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ } /* if (DoKeyIVConfig == 1U) */
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief AES CCM encryption/decryption processing in polling mode
+ * encrypt/decrypt are performed with authentication preparation.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
+ uint32_t tickstart;
+ uint32_t wordsize = ((uint32_t)hcryp->Size / 4U);
+ uint32_t loopcounter;
+ uint32_t npblb;
+ uint32_t lastwordsize;
+ uint32_t temp[4]; /* Temporary CrypOutBuff */
+ uint32_t incount; /* Temporary CrypInCount Value */
+ uint32_t outcount; /* Temporary CrypOutCount Value */
+ uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+ {
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ dokeyivconfig = 0U;
+ hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
+ }
+ }
+ else
+ {
+ hcryp->SizesSum = hcryp->Size;
+ }
+
+ if (dokeyivconfig == 1U)
+ {
+ /* Reset CrypHeaderCount */
+ hcryp->CrypHeaderCount = 0U;
+
+ /********************** Init phase ******************************************/
+
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
+
+ /* Set the Key */
+ if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
+ {
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+ }
+ else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
+ {
+ hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED;
+ }
+
+ /* Set the initialization vector (IV) with B0 */
+ hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.B0);
+ hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U);
+ hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.B0 + 2U);
+ hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.B0 + 3U);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* just wait for hash computation */
+ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+ /************************ Header phase *************************************/
+ /* Header block(B1) : associated data length expressed in bytes concatenated
+ with Associated Data (A)*/
+ if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /*************************Payload phase ************************************/
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Select payload phase once the header phase is performed */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
+
+ /* Set to 0 the number of non-valid bytes using NPBLB register*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
+
+ } /* if (dokeyivconfig == 1U) */
+
+ if ((hcryp->Size % 16U) != 0U)
+ {
+ /* recalculate wordsize */
+ wordsize = ((wordsize / 4U) * 4U);
+ }
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Write input data and get output data */
+ incount = hcryp->CrypInCount;
+ outcount = hcryp->CrypOutCount;
+ while ((incount < wordsize) && (outcount < wordsize))
+ {
+ /* Write plain data and get cipher data */
+ CRYP_AES_ProcessData(hcryp, Timeout);
+
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ incount = hcryp->CrypInCount;
+ outcount = hcryp->CrypOutCount;
+ }
+
+ if ((hcryp->Size % 16U) != 0U)
+ {
+ /* Compute the number of padding bytes in last block of payload */
+ npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - ((uint32_t)hcryp->Size);
+
+ if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_DECRYPT)
+ {
+ /* Set Npblb in case of AES CCM payload decryption to get right tag */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20);
+
+ }
+ /* Number of valid words (lastwordsize) in last block */
+ if ((npblb % 4U) == 0U)
+ {
+ lastwordsize = (16U - npblb) / 4U;
+ }
+ else
+ {
+ lastwordsize = ((16U - npblb) / 4U) + 1U;
+ }
+
+ /* Write the last input block in the IN FIFO */
+ for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter ++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ }
+
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0U;
+ loopcounter++;
+ }
+ /* just wait for hash computation */
+ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+ for (loopcounter = 0U; loopcounter < 4U; loopcounter++)
+ {
+ /* Read the output block from the output FIFO and put them in temporary buffer then
+ get CrypOutBuff from temporary buffer */
+ temp[loopcounter] = hcryp->Instance->DOUTR;
+ }
+ for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[loopcounter];
+ hcryp->CrypOutCount++;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief AES CCM encryption/decryption process in interrupt mode
+ * encrypt/decrypt are performed with authentication preparation.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
+{
+ uint32_t count;
+ uint32_t loopcounter;
+ uint32_t lastwordsize;
+ uint32_t npblb;
+ uint32_t mode;
+ uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+
+#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
+ if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED))
+ {
+ CRYP_PhaseProcessingResume(hcryp);
+ return HAL_OK;
+ }
+#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
+
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+ {
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ dokeyivconfig = 0U;
+ hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
+ }
+ }
+ else
+ {
+ hcryp->SizesSum = hcryp->Size;
+ }
+
+ /* Configure Key, IV and process message (header and payload) */
+ if (dokeyivconfig == 1U)
+ {
+ /* Reset CrypHeaderCount */
+ hcryp->CrypHeaderCount = 0U;
+
+ /********************** Init phase ******************************************/
+
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
+
+ /* Set the Key */
+ if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
+ {
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+ }
+ else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
+ {
+ hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED;
+ }
+
+ /* Set the initialization vector (IV) with B0 */
+ hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.B0);
+ hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U);
+ hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.B0 + 2U);
+ hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.B0 + 3U);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* just wait for hash computation */
+ count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+ do
+ {
+ count--;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+ /***************************** Header phase *********************************/
+
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
+ /* Enable computation complete flag and error interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ if (hcryp->Init.HeaderSize == 0U) /*header phase is skipped*/
+ {
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+ /* Select payload phase once the header phase is performed */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+ /* Set to 0 the number of non-valid bytes using NPBLB register*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
+
+ if (hcryp->Init.Algorithm == CRYP_AES_CCM)
+ {
+ /* Increment CrypHeaderCount to pass in CRYP_GCMCCM_SetPayloadPhase_IT */
+ hcryp->CrypHeaderCount++;
+ }
+ /* Write the payload Input block in the IN FIFO */
+ if (hcryp->Size == 0U)
+ {
+ /* Disable interrupts */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ }
+ else if (hcryp->Size >= 16U)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+
+ if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
+ {
+ /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ }
+ else /* Size < 4 words : first block is the last block*/
+ {
+ /* Compute the number of padding bytes in last block of payload */
+ npblb = 16U - (uint32_t)hcryp->Size;
+
+ mode = hcryp->Instance->CR & AES_CR_MODE;
+ if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) ||
+ ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
+ {
+ /* Specify the number of non-valid bytes using NPBLB register*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
+ }
+
+ /* Number of valid words (lastwordsize) in last block */
+ if ((npblb % 4U) == 0U)
+ {
+ lastwordsize = (16U - npblb) / 4U;
+ }
+ else
+ {
+ lastwordsize = ((16U - npblb) / 4U) + 1U;
+ }
+
+ /* Last block optionally pad the data with zeros*/
+ for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ }
+ while (loopcounter < 4U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ }
+ }
+ else if ((hcryp->Init.HeaderSize) < 4U) /*HeaderSize < 4 */
+ {
+ /* Last block optionally pad the data with zeros*/
+ for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+ }
+ while (loopcounter < 4U)
+ {
+ /* pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ }
+ else
+ {
+ /* Write the input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+ }
+
+ } /* end of if (dokeyivconfig == 1U) */
+ else /* Key and IV have already been configured,
+ header has already been processed;
+ only process here message payload */
+ {
+ /* Write the payload Input block in the IN FIFO */
+ if (hcryp->Size == 0U)
+ {
+ /* Disable interrupts */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ }
+ else if (hcryp->Size >= 16U)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+
+ if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
+ {
+ /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ }
+ else /* Size < 4 words : first block is the last block*/
+ {
+ /* Compute the number of padding bytes in last block of payload */
+ npblb = 16U - (uint32_t)hcryp->Size;
+
+ mode = hcryp->Instance->CR & AES_CR_MODE;
+ if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) ||
+ ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
+ {
+ /* Specify the number of non-valid bytes using NPBLB register*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
+ }
+
+ /* Number of valid words (lastwordsize) in last block */
+ if ((npblb % 4U) == 0U)
+ {
+ lastwordsize = (16U - npblb) / 4U;
+ }
+ else
+ {
+ lastwordsize = ((16U - npblb) / 4U) + 1U;
+ }
+
+ /* Last block optionally pad the data with zeros*/
+ for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ }
+ while (loopcounter < 4U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief AES CCM encryption/decryption process in DMA mode
+ * encrypt/decrypt are performed with authentication preparation.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
+{
+ uint32_t count;
+ uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+ {
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ dokeyivconfig = 0U;
+ hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
+ }
+ }
+ else
+ {
+ hcryp->SizesSum = hcryp->Size;
+ }
+
+ if (dokeyivconfig == 1U)
+ {
+
+ /* Reset CrypHeaderCount */
+ hcryp->CrypHeaderCount = 0U;
+
+
+ /********************** Init phase ******************************************/
+
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
+
+ /* Set the Key */
+ if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
+ {
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+ }
+ else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
+ {
+ hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED;
+ }
+
+ /* Set the initialization vector (IV) with B0 */
+ hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.B0);
+ hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U);
+ hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.B0 + 2U);
+ hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.B0 + 3U);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* just wait for hash computation */
+ count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+ do
+ {
+ count--;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+
+ /********************* Header phase *****************************************/
+
+ if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ }
+ else
+ {
+ /* Initialization and header phases already done, only do payload phase */
+ if (CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ } /* if (DoKeyIVConfig == 1U) */
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Sets the payload phase in interrupt mode
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval state
+ */
+static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
+{
+ uint32_t loopcounter;
+ uint32_t temp[4]; /* Temporary CrypOutBuff */
+ uint32_t lastwordsize;
+ uint32_t npblb;
+ uint32_t mode;
+ uint16_t incount; /* Temporary CrypInCount Value */
+ uint16_t outcount; /* Temporary CrypOutCount Value */
+ uint32_t i;
+
+ /***************************** Payload phase *******************************/
+
+ /* Read the output block from the output FIFO and put them in temporary buffer then
+ get CrypOutBuff from temporary buffer*/
+ for (i = 0U; i < 4U; i++)
+ {
+ temp[i] = hcryp->Instance->DOUTR;
+ }
+ i = 0U;
+ while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+ hcryp->CrypOutCount++;
+ i++;
+ }
+ incount = hcryp->CrypInCount;
+ outcount = hcryp->CrypOutCount;
+ if ((outcount >= (hcryp->Size / 4U)) && ((incount * 4U) >= hcryp->Size))
+ {
+
+ /* When in CCM with Key and IV configuration skipped, don't disable interruptions */
+ if (!((hcryp->Init.Algorithm == CRYP_AES_CCM) && (hcryp->KeyIVConfig == 1U)))
+ {
+ /* Disable computation complete flag and errors interrupts */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
+ }
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+
+ /* Call output transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Output complete callback*/
+ hcryp->OutCpltCallback(hcryp);
+#else
+ /*Call legacy weak Output complete callback*/
+ HAL_CRYP_OutCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+
+ else if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U)
+ {
+
+#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
+ /* If suspension flag has been raised, suspend processing
+ only if not already at the end of the payload */
+ if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
+ {
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+ /* reset SuspendRequest */
+ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
+ /* Disable Computation Complete Flag and Errors Interrupts */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_SUSPENDED;
+ /* Mark that the payload phase is suspended */
+ hcryp->Phase = CRYP_PHASE_PAYLOAD_SUSPENDED;
+ __HAL_UNLOCK(hcryp);
+ }
+ else
+#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
+ {
+ /* Write the input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
+ {
+ /* Call output transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ }
+ }
+ else /* Last block of payload < 128bit*/
+ {
+ /* Compute the number of padding bytes in last block of payload */
+ npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - ((uint32_t)hcryp->Size);
+
+ mode = hcryp->Instance->CR & AES_CR_MODE;
+ if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) ||
+ ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
+ {
+ /* Specify the number of non-valid bytes using NPBLB register*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
+ }
+
+ /* Number of valid words (lastwordsize) in last block */
+ if ((npblb % 4U) == 0U)
+ {
+ lastwordsize = (16U - npblb) / 4U;
+ }
+ else
+ {
+ lastwordsize = ((16U - npblb) / 4U) + 1U;
+ }
+
+ /* Last block optionally pad the data with zeros*/
+ for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ }
+ while (loopcounter < 4U)
+ {
+ /* pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ }
+}
+
+/**
+ * @brief Sets the payload phase in DMA mode
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval state
+ */
+static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcryp)
+{
+ uint32_t index;
+ uint32_t npblb;
+ uint32_t lastwordsize;
+ uint32_t temp[4]; /* Temporary CrypOutBuff */
+ uint32_t count;
+ uint32_t reg;
+
+ /************************ Payload phase ************************************/
+ if (hcryp->Size == 0U)
+ {
+ /* Process unLocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Change the CRYP state and phase */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ }
+ else if (hcryp->Size >= 16U)
+ {
+ /*DMA transfer must not include the last block in case of Size is not %16 */
+ CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (uint16_t)((hcryp->Size / 16U) * 16U),
+ (uint32_t)(hcryp->pCrypOutBuffPtr));
+ }
+ else /* length of input data is < 16 */
+ {
+ /* Compute the number of padding bytes in last block of payload */
+ npblb = 16U - (uint32_t)hcryp->Size;
+
+ /* Set Npblb in case of AES GCM payload encryption or AES CCM payload decryption to get right tag*/
+ reg = hcryp->Instance->CR & (AES_CR_CHMOD | AES_CR_MODE);
+ if ((reg == (CRYP_AES_GCM_GMAC | CRYP_OPERATINGMODE_ENCRYPT)) || \
+ (reg == (CRYP_AES_CCM | CRYP_OPERATINGMODE_DECRYPT)))
+ {
+ /* Specify the number of non-valid bytes using NPBLB register*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
+ }
+
+ /* Number of valid words (lastwordsize) in last block */
+ if ((npblb % 4U) == 0U)
+ {
+ lastwordsize = (16U - npblb) / 4U;
+ }
+ else
+ {
+ lastwordsize = ((16U - npblb) / 4U) + 1U;
+ }
+
+ /* last block optionally pad the data with zeros*/
+ for (index = 0U; index < lastwordsize; index ++)
+ {
+ /* Write the last Input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ }
+ while (index < 4U)
+ {
+ /* pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0U;
+ index++;
+ }
+ /* Wait for CCF flag to be raised */
+ count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+ /*Read the output block from the output FIFO */
+ for (index = 0U; index < 4U; index++)
+ {
+ /* Read the output block from the output FIFO and put them in temporary
+ buffer then get CrypOutBuff from temporary buffer */
+ temp[index] = hcryp->Instance->DOUTR;
+ }
+ for (index = 0U; index < lastwordsize; index++)
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
+ hcryp->CrypOutCount++;
+ }
+
+ /* Change the CRYP state to ready */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Sets the header phase in polling mode
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module(Header & HeaderSize)
+ * @param Timeout Timeout value
+ * @retval state
+ */
+static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
+ uint32_t loopcounter;
+ uint32_t size_in_bytes;
+ uint32_t tmp;
+ uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
+ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
+ 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
+ }; /* 8-bit data type */
+
+ /***************************** Header phase for GCM/GMAC or CCM *********************************/
+ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
+ {
+ size_in_bytes = hcryp->Init.HeaderSize * 4U;
+ }
+ else
+ {
+ size_in_bytes = hcryp->Init.HeaderSize;
+ }
+
+ if ((size_in_bytes != 0U))
+ {
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* If size_in_bytes is a multiple of blocks (a multiple of four 32-bits words ) */
+ if ((size_in_bytes % 16U) == 0U)
+ {
+ /* No padding */
+ for (loopcounter = 0U; (loopcounter < (size_in_bytes / 4U)); loopcounter += 4U)
+ {
+ /* Write the input block in the data input register */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+
+ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+ }
+ }
+ else
+ {
+ /* Write header block in the IN FIFO without last block */
+ for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 16U) * 4U)); loopcounter += 4U)
+ {
+ /* Write the input block in the data input register */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+
+ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+ }
+ /* Write last complete words */
+ for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 4U) % 4U)); loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+ }
+ /* If the header size is a multiple of words */
+ if ((size_in_bytes % 4U) == 0U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ }
+ else
+ {
+ /* Enter last bytes, padded with zeros */
+ tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ tmp &= mask[(hcryp->Init.DataType * 2U) + (size_in_bytes % 4U)];
+ hcryp->Instance->DINR = tmp;
+ loopcounter++;
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ }
+
+ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+ }
+ }
+ else
+ {
+ /*Workaround 1: only AES, before re-enabling the peripheral, datatype can be configured.*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
+
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Sets the header phase when using DMA in process
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module(Header & HeaderSize)
+ * @retval None
+ */
+static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp)
+{
+ uint32_t loopcounter;
+ uint32_t headersize_in_bytes;
+ uint32_t tmp;
+ uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
+ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
+ 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
+ }; /* 8-bit data type */
+
+ /***************************** Header phase for GCM/GMAC or CCM *********************************/
+ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
+ {
+ headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
+ }
+ else
+ {
+ headersize_in_bytes = hcryp->Init.HeaderSize;
+ }
+
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* If header size is at least equal to 16 bytes, feed the header through DMA.
+ If size_in_bytes is not a multiple of blocks (is not a multiple of four 32-bit words ),
+ last bytes feeding and padding will be done in CRYP_DMAInCplt() */
+ if (headersize_in_bytes >= 16U)
+ {
+ /* Initiate header DMA transfer */
+ if (CRYP_SetHeaderDMAConfig(hcryp, (uint32_t)(hcryp->Init.Header),
+ (uint16_t)((headersize_in_bytes / 16U) * 16U)) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ if (headersize_in_bytes != 0U)
+ {
+ /* Header length is larger than 0 and strictly less than 16 bytes */
+ /* Write last complete words */
+ for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ }
+ /* If the header size is a multiple of words */
+ if ((headersize_in_bytes % 4U) == 0U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ }
+ else
+ {
+ /* Enter last bytes, padded with zeros */
+ tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
+ hcryp->Instance->DINR = tmp;
+ loopcounter++;
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ }
+
+ if (CRYP_WaitOnCCFlag(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+ } /* if (headersize_in_bytes != 0U) */
+
+ /* Move to payload phase if header length is null or
+ if the header length was less than 16 and header written by software instead of DMA */
+
+ /* Set to 0 the number of non-valid bytes using NPBLB register*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
+
+ /* Select payload phase once the header phase is performed */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+ /* Initiate payload DMA IN and processed data DMA OUT transfers */
+ if (CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ } /* if (headersize_in_bytes >= 16U) */
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Sets the header phase in interrupt mode
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module(Header & HeaderSize)
+ * @retval None
+ */
+static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
+{
+ uint32_t loopcounter;
+ uint32_t lastwordsize;
+ uint32_t npblb;
+ uint32_t mode;
+ uint32_t headersize_in_bytes;
+ uint32_t tmp;
+ uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
+ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
+ 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
+ }; /* 8-bit data type */
+
+ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
+ {
+ headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
+ }
+ else
+ {
+ headersize_in_bytes = hcryp->Init.HeaderSize;
+ }
+
+ /***************************** Header phase *********************************/
+ /* Test whether or not the header phase is over.
+ If the test below is true, move to payload phase */
+ if (headersize_in_bytes <= ((uint32_t)(hcryp->CrypHeaderCount) * 4U))
+ {
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+ /* Select payload phase */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
+ /* Set to 0 the number of non-valid bytes using NPBLB register*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
+
+ if (hcryp->Init.Algorithm == CRYP_AES_CCM)
+ {
+ /* Increment CrypHeaderCount to pass in CRYP_GCMCCM_SetPayloadPhase_IT */
+ hcryp->CrypHeaderCount++;
+ }
+ /* Write the payload Input block in the IN FIFO */
+ if (hcryp->Size == 0U)
+ {
+ /* Disable interrupts */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ }
+ else if (hcryp->Size >= 16U)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+
+ if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
+ {
+ /* Call the input data transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ }
+ else /* Size < 4 words : first block is the last block*/
+ {
+ /* Compute the number of padding bytes in last block of payload */
+ npblb = 16U - ((uint32_t)hcryp->Size);
+ mode = hcryp->Instance->CR & AES_CR_MODE;
+ if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) ||
+ ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
+ {
+ /* Specify the number of non-valid bytes using NPBLB register*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
+ }
+
+ /* Number of valid words (lastwordsize) in last block */
+ if ((npblb % 4U) == 0U)
+ {
+ lastwordsize = (16U - npblb) / 4U;
+ }
+ else
+ {
+ lastwordsize = ((16U - npblb) / 4U) + 1U;
+ }
+
+ /* Last block optionally pad the data with zeros*/
+ for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ }
+ while (loopcounter < 4U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ }
+ }
+ else if ((((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U))
+ {
+ /* Can enter full 4 header words */
+#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
+ /* If suspension flag has been raised, suspend processing
+ only if not already at the end of the header */
+ if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
+ {
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+ /* reset SuspendRequest */
+ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
+ /* Disable Computation Complete Flag and Errors Interrupts */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_SUSPENDED;
+ /* Mark that the payload phase is suspended */
+ hcryp->Phase = CRYP_PHASE_HEADER_SUSPENDED;
+ __HAL_UNLOCK(hcryp);
+ }
+ else
+#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
+ {
+ /* Write the input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+ }
+ }
+ else /* Write last header block (4 words), padded with zeros if needed */
+ {
+
+ for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ }
+ /* If the header size is a multiple of words */
+ if ((headersize_in_bytes % 4U) == 0U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ hcryp->CrypHeaderCount++;
+ }
+ }
+ else
+ {
+ /* Enter last bytes, padded with zeros */
+ tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
+ hcryp->Instance->DINR = tmp;
+ loopcounter++;
+ hcryp->CrypHeaderCount++;
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ hcryp->CrypHeaderCount++;
+ }
+ }
+ }
+}
+
+/**
+ * @brief Handle CRYP hardware block Timeout when waiting for CCF flag to be raised.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @param Timeout Timeout duration.
+ * @note This function can only be used in thread mode.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ __HAL_CRYP_DISABLE(hcryp);
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Wait for Computation Complete Flag (CCF) to raise then clear it.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @param Timeout Timeout duration.
+ * @note This function can be used in thread or handler mode.
+ * @retval HAL status
+ */
+static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
+ uint32_t count = Timeout;
+
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+}
+
+#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
+/**
+ * @brief In case of message processing suspension, read the Initialization Vector.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @param Output Pointer to the buffer containing the saved Initialization Vector.
+ * @note This value has to be stored for reuse by writing the AES_IVRx registers
+ * as soon as the suspended processing has to be resumed.
+ * @retval None
+ */
+static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Output)
+{
+ uint32_t outputaddr = (uint32_t)Output;
+
+ *(uint32_t *)(outputaddr) = hcryp->Instance->IVR3;
+ outputaddr += 4U;
+ *(uint32_t *)(outputaddr) = hcryp->Instance->IVR2;
+ outputaddr += 4U;
+ *(uint32_t *)(outputaddr) = hcryp->Instance->IVR1;
+ outputaddr += 4U;
+ *(uint32_t *)(outputaddr) = hcryp->Instance->IVR0;
+}
+
+/**
+ * @brief In case of message processing resumption, rewrite the Initialization
+ * Vector in the AES_IVRx registers.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @param Input Pointer to the buffer containing the saved Initialization Vector to
+ * write back in the CRYP hardware block.
+ * @note AES must be disabled when reconfiguring the IV values.
+ * @retval None
+ */
+static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Input)
+{
+ uint32_t ivaddr = (uint32_t)Input;
+
+ hcryp->Instance->IVR3 = *(uint32_t *)(ivaddr);
+ ivaddr += 4U;
+ hcryp->Instance->IVR2 = *(uint32_t *)(ivaddr);
+ ivaddr += 4U;
+ hcryp->Instance->IVR1 = *(uint32_t *)(ivaddr);
+ ivaddr += 4U;
+ hcryp->Instance->IVR0 = *(uint32_t *)(ivaddr);
+}
+
+/**
+ * @brief In case of message GCM/GMAC/CCM processing suspension,
+ * read the Suspend Registers.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @param Output Pointer to the buffer containing the saved Suspend Registers.
+ * @note These values have to be stored for reuse by writing back the AES_SUSPxR registers
+ * as soon as the suspended processing has to be resumed.
+ * @retval None
+ */
+static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Output)
+{
+ uint32_t outputaddr = (uint32_t)Output;
+ uint32_t count = 0U;
+
+ /* In case of GCM payload phase encryption, check that suspension can be carried out */
+ if (READ_BIT(hcryp->Instance->CR, (AES_CR_CHMOD | AES_CR_GCMPH | AES_CR_MODE)) == (CRYP_AES_GCM_GMAC |
+ AES_CR_GCMPH_1 | 0x0))
+ {
+
+ /* Wait for BUSY flag to be cleared */
+ count = 0xFFF;
+ do
+ {
+ count--;
+ if (count == 0U)
+ {
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ HAL_CRYP_ErrorCallback(hcryp);
+ return;
+ }
+ } while (HAL_IS_BIT_SET(hcryp->Instance->SR, AES_SR_BUSY));
+
+ }
+
+ *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP7R;
+ outputaddr += 4U;
+ *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP6R;
+ outputaddr += 4U;
+ *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP5R;
+ outputaddr += 4U;
+ *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP4R;
+ outputaddr += 4U;
+ *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP3R;
+ outputaddr += 4U;
+ *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP2R;
+ outputaddr += 4U;
+ *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP1R;
+ outputaddr += 4U;
+ *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP0R;
+}
+
+/**
+ * @brief In case of message GCM/GMAC/CCM processing resumption, rewrite the Suspend
+ * Registers in the AES_SUSPxR registers.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @param Input Pointer to the buffer containing the saved suspend registers to
+ * write back in the CRYP hardware block.
+ * @note AES must be disabled when reconfiguring the suspend registers.
+ * @retval None
+ */
+static void CRYP_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Input)
+{
+ uint32_t ivaddr = (uint32_t)Input;
+
+ hcryp->Instance->SUSP7R = *(uint32_t *)(ivaddr);
+ ivaddr += 4U;
+ hcryp->Instance->SUSP6R = *(uint32_t *)(ivaddr);
+ ivaddr += 4U;
+ hcryp->Instance->SUSP5R = *(uint32_t *)(ivaddr);
+ ivaddr += 4U;
+ hcryp->Instance->SUSP4R = *(uint32_t *)(ivaddr);
+ ivaddr += 4U;
+ hcryp->Instance->SUSP3R = *(uint32_t *)(ivaddr);
+ ivaddr += 4U;
+ hcryp->Instance->SUSP2R = *(uint32_t *)(ivaddr);
+ ivaddr += 4U;
+ hcryp->Instance->SUSP1R = *(uint32_t *)(ivaddr);
+ ivaddr += 4U;
+ hcryp->Instance->SUSP0R = *(uint32_t *)(ivaddr);
+}
+
+/**
+ * @brief In case of message GCM/GMAC/CCM processing suspension, read the Key Registers.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @param Output Pointer to the buffer containing the saved Key Registers.
+ * @param KeySize Indicates the key size (128 or 256 bits).
+ * @note These values have to be stored for reuse by writing back the AES_KEYRx registers
+ * as soon as the suspended processing has to be resumed.
+ * @retval None
+ */
+static void CRYP_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Output, uint32_t KeySize)
+{
+ uint32_t keyaddr = (uint32_t)Output;
+
+ switch (KeySize)
+ {
+ case CRYP_KEYSIZE_256B:
+ *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey);
+ keyaddr += 4U;
+ *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 1U);
+ keyaddr += 4U;
+ *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 2U);
+ keyaddr += 4U;
+ *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 3U);
+ keyaddr += 4U;
+ *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 4U);
+ keyaddr += 4U;
+ *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 5U);
+ keyaddr += 4U;
+ *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 6U);
+ keyaddr += 4U;
+ *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 7U);
+ break;
+ case CRYP_KEYSIZE_128B:
+ *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey);
+ keyaddr += 4U;
+ *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 1U);
+ keyaddr += 4U;
+ *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 2U);
+ keyaddr += 4U;
+ *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 3U);
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief In case of message GCM/GMAC (CCM/CMAC when applicable) processing resumption, rewrite the Key
+ * Registers in the AES_KEYRx registers.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @param Input Pointer to the buffer containing the saved key registers to
+ * write back in the CRYP hardware block.
+ * @param KeySize Indicates the key size (128 or 256 bits)
+ * @note AES must be disabled when reconfiguring the Key registers.
+ * @retval None
+ */
+static void CRYP_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Input, uint32_t KeySize)
+{
+ uint32_t keyaddr = (uint32_t)Input;
+
+ if (KeySize == CRYP_KEYSIZE_256B)
+ {
+ hcryp->Instance->KEYR7 = *(uint32_t *)(keyaddr);
+ keyaddr += 4U;
+ hcryp->Instance->KEYR6 = *(uint32_t *)(keyaddr);
+ keyaddr += 4U;
+ hcryp->Instance->KEYR5 = *(uint32_t *)(keyaddr);
+ keyaddr += 4U;
+ hcryp->Instance->KEYR4 = *(uint32_t *)(keyaddr);
+ keyaddr += 4U;
+ }
+
+ hcryp->Instance->KEYR3 = *(uint32_t *)(keyaddr);
+ keyaddr += 4U;
+ hcryp->Instance->KEYR2 = *(uint32_t *)(keyaddr);
+ keyaddr += 4U;
+ hcryp->Instance->KEYR1 = *(uint32_t *)(keyaddr);
+ keyaddr += 4U;
+ hcryp->Instance->KEYR0 = *(uint32_t *)(keyaddr);
+}
+
+/**
+ * @brief Authentication phase resumption in case of GCM/GMAC/CCM process in interrupt mode
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module(Header & HeaderSize)
+ * @retval None
+ */
+static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp)
+{
+ uint32_t loopcounter;
+ uint16_t lastwordsize;
+ uint16_t npblb;
+ uint32_t cr_temp;
+
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RWEIF | CRYP_CLEAR_CCF);
+
+ /* Enable computation complete flag and error interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Case of header phase resumption =================================================*/
+ if (hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED)
+ {
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
+ if (((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount) >= 4U))
+ {
+ /* Write the input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+ }
+ else /*HeaderSize < 4 or HeaderSize >4 & HeaderSize %4 != 0*/
+ {
+ /* Last block optionally pad the data with zeros*/
+ for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+ }
+ while (loopcounter < 4U)
+ {
+ /* pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ }
+ }
+ /* Case of payload phase resumption =================================================*/
+ else
+ {
+ if (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED)
+ {
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Select payload phase once the header phase is performed */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
+
+ /* Set to 0 the number of non-valid bytes using NPBLB register*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
+
+ if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U)
+ {
+ /* Write the input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
+ {
+ /* Call output transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ }
+ else /* Last block of payload < 128bit*/
+ {
+ /* Compute the number of padding bytes in last block of payload */
+ npblb = (((hcryp->Size / 16U) + 1U) * 16U) - (hcryp->Size);
+ cr_temp = hcryp->Instance->CR;
+ if ((((cr_temp & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) ||
+ (((cr_temp & AES_CR_MODE) == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
+ {
+ /* Specify the number of non-valid bytes using NPBLB register*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, ((uint32_t)npblb) << 20U);
+ }
+
+ /* Number of valid words (lastwordsize) in last block */
+ if ((npblb % 4U) == 0U)
+ {
+ lastwordsize = (16U - npblb) / 4U;
+ }
+ else
+ {
+ lastwordsize = ((16U - npblb) / 4U) + 1U;
+ }
+
+ /* Last block optionally pad the data with zeros*/
+ for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ }
+ while (loopcounter < 4U)
+ {
+ /* pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ }
+ }
+ }
+}
+#endif /* defined (USE_HAL_CRYP_SUSPEND_RESUME) */
+/**
+ * @}
+ */
+
+
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#endif /* AES */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cryp_ex.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cryp_ex.c
new file mode 100644
index 00000000..4a82064a
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cryp_ex.c
@@ -0,0 +1,817 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_cryp_ex.c
+ * @author MCD Application Team
+ * @brief CRYPEx HAL module driver.
+ * This file provides firmware functions to manage the extended
+ * functionalities of the Cryptography (CRYP) peripheral.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CRYPEx
+ * @{
+ */
+
+#if defined(AES)
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup CRYPEx_Private_Defines
+ * @{
+ */
+
+#define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */
+#define CRYP_PHASE_HEADER AES_CR_GCMPH_0 /*!< GCM/GMAC or CCM header phase */
+#define CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */
+#define CRYP_PHASE_FINAL AES_CR_GCMPH /*!< GCM/GMAC or CCM final phase */
+
+#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< Encryption mode */
+#define CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0 /*!< Key derivation mode only used when performing ECB and CBC decryptions */
+#define CRYP_OPERATINGMODE_DECRYPT AES_CR_MODE_1 /*!< Decryption */
+#define CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT AES_CR_MODE /*!< Key derivation and decryption only used when performing ECB and CBC decryptions */
+
+#define CRYPEx_PHASE_PROCESS 0x02U /*!< CRYP peripheral is in processing phase */
+#define CRYPEx_PHASE_FINAL 0x03U /*!< CRYP peripheral is in final phase this is relevant only with CCM and GCM modes */
+
+/* CTR0 information to use in CCM algorithm */
+#define CRYP_CCM_CTR0_0 0x07FFFFFFU
+#define CRYP_CCM_CTR0_3 0xFFFFFF00U
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static HAL_StatusTypeDef CRYPEx_KeyDecrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static HAL_StatusTypeDef CRYPEx_KeyEncrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static void CRYPEx_SetKey(const CRYP_HandleTypeDef *hcryp, uint32_t KeySize);
+/* Exported functions---------------------------------------------------------*/
+/** @addtogroup CRYPEx_Exported_Functions
+ * @{
+ */
+
+/** @defgroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions
+ * @brief Extended processing functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Extended AES processing functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to generate the authentication
+ TAG in Polling mode
+ (#)HAL_CRYPEx_AESGCM_GenerateAuthTAG
+ (#)HAL_CRYPEx_AESCCM_GenerateAuthTAG
+ they should be used after Encrypt/Decrypt operation.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief generate the GCM authentication TAG.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pAuthTag Pointer to the authentication buffer
+ * the pAuthTag generated here is 128bits length, if the TAG length is
+ * less than 128bits, user should consider only the valid part of pAuthTag
+ * buffer which correspond exactly to TAG length.
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *pAuthTag, uint32_t Timeout)
+{
+ /* Assume first Init.HeaderSize is in words */
+ uint64_t headerlength = (uint64_t)hcryp->Init.HeaderSize * 32U; /* Header length in bits */
+ uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* Input length in bits */
+ uint32_t tagaddr = (uint32_t)pAuthTag;
+ uint32_t i;
+ uint32_t tickstart;
+
+ /* Correct headerlength if Init.HeaderSize is actually in bytes */
+ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_BYTE)
+ {
+ headerlength /= 4U;
+ }
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ __HAL_LOCK(hcryp);
+
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if (hcryp->Phase == CRYPEx_PHASE_PROCESS)
+ {
+ /* Change the CRYP phase */
+ hcryp->Phase = CRYPEx_PHASE_FINAL;
+
+ /* Select final phase */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL);
+
+ /* Set the encrypt operating mode */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
+
+ /* Write into the AES_DINR register the number of bits in header (64 bits)
+ followed by the number of bits in the payload */
+ hcryp->Instance->DINR = 0U;
+ hcryp->Instance->DINR = (uint32_t)(headerlength);
+ hcryp->Instance->DINR = 0U;
+ hcryp->Instance->DINR = (uint32_t)(inputlength);
+
+ /* Wait for CCF flag to be raised */
+ tickstart = HAL_GetTick();
+ while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Read the authentication TAG in the output FIFO */
+ for (i = 0U; i < 4U; i++)
+ {
+ *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
+ tagaddr += 4U;
+ }
+
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+ /* Disable the peripheral */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ }
+ else /* Initialization phase has not been performed */
+ {
+ /* Disable the Peripheral */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Sequence error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE;
+
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Busy error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ return HAL_ERROR;
+ }
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief AES CCM Authentication TAG generation.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pAuthTag Pointer to the authentication buffer
+ * the pAuthTag generated here is 128bits length, if the TAG length is
+ * less than 128bits, user should consider only the valid part of pAuthTag
+ * buffer which correspond exactly to TAG length.
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *pAuthTag, uint32_t Timeout)
+{
+ uint32_t tagaddr = (uint32_t)pAuthTag;
+ uint32_t i;
+ uint32_t tickstart;
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ __HAL_LOCK(hcryp);
+
+ /* Disable interrupts in case they were kept enabled to proceed
+ a single message in several iterations */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
+
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if (hcryp->Phase == CRYPEx_PHASE_PROCESS)
+ {
+ /* Change the CRYP phase */
+ hcryp->Phase = CRYPEx_PHASE_FINAL;
+ /* Select final phase */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL);
+
+ /* Set encrypt operating mode */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
+
+ /* Wait for CCF flag to be raised */
+ tickstart = HAL_GetTick();
+ while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ /* Disable the CRYP peripheral Clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Read the authentication TAG in the output FIFO */
+ for (i = 0U; i < 4U; i++)
+ {
+ *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
+ tagaddr += 4U;
+ }
+
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+
+ /* Disable CRYP */
+ __HAL_CRYP_DISABLE(hcryp);
+ }
+ else /* Initialization phase has not been performed */
+ {
+ /* Disable the peripheral */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Sequence error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE;
+
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Busy error code field */
+ hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY;
+ return HAL_ERROR;
+ }
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup CRYPEx_Exported_Functions_Group2 Wrap and Unwrap key functions
+ * @brief Wrap and Unwrap key functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Wrap and Unwrap key #####
+ ==============================================================================
+ [..] This section provides API allowing to wrap (encrypt) and unwrap (decrypt)
+ key using one of the following keys, and AES Algorithm.
+ Key selection :
+ - Derived hardware unique key (DHUK)
+ - XOR of DHUK and BHK
+ - Boot hardware key (BHK)
+ - Key registers AES_KEYx
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Wrap (encrypt) application keys.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pInput Pointer to the Key buffer to encrypt
+ * @param pOutput Pointer to the Key buffer encrypted
+ * @param Timeout Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYPEx_WrapKey(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint32_t *pOutput, uint32_t Timeout)
+{
+ HAL_StatusTypeDef status;
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Change state Busy */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+ __HAL_LOCK(hcryp);
+
+ /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
+ hcryp->CrypInCount = 0U;
+ hcryp->CrypOutCount = 0U;
+ hcryp->pCrypInBuffPtr = pInput;
+ hcryp->pCrypOutBuffPtr = pOutput;
+
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Set the operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD, CRYP_KEYMODE_WRAPPED);
+
+ status = CRYPEx_KeyEncrypt(hcryp, Timeout);
+ }
+ else
+ {
+ /* Busy error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Unwrap (Decrypt) application keys.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pInput Pointer to the Key buffer to decrypt
+ * @param Timeout Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYPEx_UnwrapKey(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint32_t Timeout)
+{
+ HAL_StatusTypeDef status;
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Change state Busy */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ __HAL_LOCK(hcryp);
+
+ /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters */
+ hcryp->CrypInCount = 0U;
+ hcryp->CrypOutCount = 0U;
+ hcryp->pCrypInBuffPtr = pInput;
+
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Set the operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD, CRYP_KEYMODE_WRAPPED);
+
+ status = CRYPEx_KeyDecrypt(hcryp, Timeout);
+ }
+ else
+ {
+ /* Busy error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRYPEx_Exported_Functions_Group3 Encrypt/Decrypt Shared key functions
+ * @brief Encrypt/Decrypt Shared key functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Encrypt/Decrypt Shared key functions #####
+ ==============================================================================
+ [..] This section provides API allowing to Encrypt/Decrypt Shared key
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Encrypt Shared key.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pKey Pointer to the Key buffer to share
+ * @param pOutput Pointer to the Key buffer encrypted
+ * @param ID Key share identification
+ * @param Timeout Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYPEx_EncryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_t *pKey, uint32_t *pOutput, uint32_t ID,
+ uint32_t Timeout)
+{
+ HAL_StatusTypeDef status;
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Change state Busy */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+ __HAL_LOCK(hcryp);
+
+ /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters */
+ hcryp->CrypInCount = 0U;
+ hcryp->CrypOutCount = 0U;
+ hcryp->pCrypInBuffPtr = pKey;
+ hcryp->pCrypOutBuffPtr = pOutput;
+
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Set the operating mode */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD | AES_CR_KSHAREID, CRYP_KEYMODE_SHARED | ID);
+
+ status = CRYPEx_KeyEncrypt(hcryp, Timeout);
+ }
+ else
+ {
+ /* Busy error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Decrypt Shared key.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pKey Pointer to the Key buffer to share
+ * @param ID Key share identification
+ * @param Timeout Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYPEx_DecryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_t *pKey, uint32_t ID, uint32_t Timeout)
+{
+ HAL_StatusTypeDef status;
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Change state Busy */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+ __HAL_LOCK(hcryp);
+
+ /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters */
+ hcryp->CrypInCount = 0U;
+ hcryp->CrypOutCount = 0U;
+ hcryp->pCrypInBuffPtr = pKey;
+
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Set the operating mode */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD | AES_CR_KSHAREID, CRYP_KEYMODE_SHARED | ID);
+
+ status = CRYPEx_KeyDecrypt(hcryp, Timeout);
+ }
+ else
+ {
+ /* Busy error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup CRYP_Private_Functions
+ * @{
+ */
+/**
+ * @brief Key Decryption
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure
+ * @param Timeout specify Timeout value
+ * @note It is strongly recommended to select hardware secret keys
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CRYPEx_KeyDecrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
+ uint32_t incount; /* Temporary CrypInCount Value */
+ uint32_t i;
+ uint32_t tickstart;
+
+ /* key preparation for decryption, operating mode 2*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
+
+ /* It is strongly recommended to select hardware secret keys */
+ if (hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL)
+ {
+ /* Set the Key */
+ CRYPEx_SetKey(hcryp, hcryp->Init.KeySize);
+ }
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Wait for CCF flag to be raised */
+ tickstart = HAL_GetTick();
+ while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ }
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+ /* End of Key preparation for ECB/CBC */
+ /* Return to decryption operating mode(Mode 3)*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
+
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ /* Set the Initialization Vector */
+ hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
+ hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
+ hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
+ }
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = CRYPEx_PHASE_PROCESS;
+
+ if (hcryp->Init.KeySize == CRYP_KEYSIZE_128B)
+ {
+ incount = 4U;
+ }
+ else
+ {
+ incount = 8U;
+ }
+ while (hcryp->CrypInCount < incount)
+ {
+ /* Write four times to input the key to encrypt */
+ for (i = 0U; i < 4U; i++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ }
+ /* Wait for CCF flag to be raised */
+ tickstart = HAL_GetTick();
+ while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+ }
+
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_OK;
+}
+
+/**
+ * @brief Key Encryption
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure
+ * @param Timeout specify Timeout value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CRYPEx_KeyEncrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
+ uint32_t incount; /* Temporary CrypInCount Value */
+ uint32_t i;
+ uint32_t tickstart;
+ uint32_t temp; /* Temporary CrypOutBuff */
+
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
+
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ /* Set the Initialization Vector */
+ hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
+ hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
+ hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
+ }
+ /* It is strongly recommended to select hardware secret keys */
+ if (hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL)
+ {
+ /* Set the Key */
+ CRYPEx_SetKey(hcryp, hcryp->Init.KeySize);
+ }
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait for Valid KEY flag to set */
+ while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_KEYVALID))
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = CRYPEx_PHASE_PROCESS;
+
+ if (hcryp->Init.KeySize == CRYP_KEYSIZE_128B)
+ {
+ incount = 4U;
+ }
+ else
+ {
+ incount = 8U;
+ }
+ while (hcryp->CrypInCount < incount)
+ {
+ for (i = 0U; i < 4U; i++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ }
+ /* Wait for CCF flag to be raised */
+ tickstart = HAL_GetTick();
+ while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+ /* Read the output block from the output FIFO and put them in temporary buffer then
+ get CrypOutBuff from temporary buffer */
+ for (i = 0U; i < 4U; i++)
+ {
+ temp = hcryp->Instance->DOUTR;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
+ hcryp->CrypOutCount++;
+ }
+ }
+
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_OK;
+}
+
+/**
+ * @brief Write Key in Key registers.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param KeySize Size of Key
+ * @note If pKey is NULL, the Key registers are not written.
+ * @retval None
+ */
+static void CRYPEx_SetKey(const CRYP_HandleTypeDef *hcryp, uint32_t KeySize)
+{
+ if (hcryp->Init.pKey != NULL)
+ {
+ switch (KeySize)
+ {
+ case CRYP_KEYSIZE_256B:
+ hcryp->Instance->KEYR7 = *(uint32_t *)(hcryp->Init.pKey);
+ hcryp->Instance->KEYR6 = *(uint32_t *)(hcryp->Init.pKey + 1U);
+ hcryp->Instance->KEYR5 = *(uint32_t *)(hcryp->Init.pKey + 2U);
+ hcryp->Instance->KEYR4 = *(uint32_t *)(hcryp->Init.pKey + 3U);
+ hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey + 4U);
+ hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 5U);
+ hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 6U);
+ hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 7U);
+ break;
+ case CRYP_KEYSIZE_128B:
+ hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey);
+ hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 1U);
+ hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 2U);
+ hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 3U);
+ break;
+ default:
+ break;
+ }
+ }
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#endif /* AES */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dac.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dac.c
new file mode 100644
index 00000000..0cc58d4c
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dac.c
@@ -0,0 +1,1760 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_dac.c
+ * @author MCD Application Team
+ * @brief DAC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Digital to Analog Converter (DAC) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State and Errors functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### DAC Peripheral features #####
+ ==============================================================================
+ [..]
+ *** DAC Channels ***
+ ====================
+ [..]
+ STM32U5 devices integrate two 12-bit Digital Analog Converters
+
+ The 2 converters (i.e. channel1 & channel2)
+ can be used independently or simultaneously (dual mode):
+ (#) DAC channel1 with DAC_OUT1 (PA4) as output or connected to on-chip
+ peripherals (ex. ADC).
+ (#) DAC channel2 with DAC_OUT2 (PA5) as output or connected to on-chip
+ peripherals (ex. ADC).
+
+ *** DAC Triggers ***
+ ====================
+ [..]
+ Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
+ and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
+ [..]
+ Digital to Analog conversion can be triggered by:
+ (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
+ The used pin (GPIOx_PIN_9) must be configured in input mode.
+
+ (#) Timers TRGO: TIM1, TIM2, TIM4, TIM5, TIM6, TIM7, TIM8 and TIM15
+ (DAC_TRIGGER_T1_TRGO, DAC_TRIGGER_T2_TRGO...)
+
+ (#) Low Power Timers TRGO: LPTIM1 and LPTIM3
+ (DAC_TRIGGER_LPTIM1_OUT, DAC_TRIGGER_LPTIM3_OUT)
+
+ (#) Software using DAC_TRIGGER_SOFTWARE
+ [..]
+ The trigger selection depends on the PWR mode:
+ in stop0, stop1 and stop2 we should select DAC_TRIGGER_EXT_IT9,
+ DAC_TRIGGER_LPTIM1_OUT or DAC_TRIGGER_LPTIM3_OUT.The other triggers
+ are not functional.
+
+ *** DAC Buffer mode feature ***
+ ===============================
+ [..]
+ Each DAC channel integrates an output buffer that can be used to
+ reduce the output impedance, and to drive external loads directly
+ without having to add an external operational amplifier.
+ To enable, the output buffer use
+ sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
+ [..]
+ (@) Refer to the device datasheet for more details about output
+ impedance value with and without output buffer.
+
+ *** GPIO configurations guidelines ***
+ =====================
+ [..]
+ When a DAC channel is used (ex channel1 on PA4) and the other is not
+ (ex channel2 on PA5 is configured in Analog and disabled).
+ Channel1 may disturb channel2 as coupling effect.
+ Note that there is no coupling on channel2 as soon as channel2 is turned on.
+ Coupling on adjacent channel could be avoided as follows:
+ when unused PA5 is configured as INPUT PULL-UP or DOWN.
+ PA5 is configured in ANALOG just before it is turned on.
+
+ *** DAC Sample and Hold feature ***
+ ========================
+ [..]
+ For each converter, 2 modes are supported: normal mode and
+ "sample and hold" mode (i.e. low power mode).
+ In the sample and hold mode, the DAC core converts data, then holds the
+ converted voltage on a capacitor. When not converting, the DAC cores and
+ buffer are completely turned off between samples and the DAC output is
+ tri-stated, therefore reducing the overall power consumption. A new
+ stabilization period is needed before each new conversion.
+
+ The sample and hold allow setting internal or external voltage @
+ low power consumption cost (output value can be at any given rate either
+ by CPU or DMA).
+
+ The Sample and hold block and registers uses either LSI & run in
+ several power modes: run mode, sleep mode, low power run, low power sleep
+ mode & stop1 mode.
+
+ Low power stop1 mode allows only static conversion.
+
+ To enable Sample and Hold mode
+ Enable LSI using HAL_RCC_OscConfig with RCC_OSCILLATORTYPE_LSI &
+ RCC_LSI_ON parameters.
+
+ Use DAC_InitStructure.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_ENABLE;
+ & DAC_ChannelConfTypeDef.DAC_SampleAndHoldConfig.DAC_SampleTime,
+ DAC_HoldTime & DAC_RefreshTime;
+
+ *** DAC calibration feature ***
+ ===================================
+ [..]
+ (#) The 2 converters (channel1 & channel2) provide calibration capabilities.
+ (++) Calibration aims at correcting some offset of output buffer.
+ (++) The DAC uses either factory calibration settings OR user defined
+ calibration (trimming) settings (i.e. trimming mode).
+ (++) The user defined settings can be figured out using self calibration
+ handled by HAL_DACEx_SelfCalibrate.
+ (++) HAL_DACEx_SelfCalibrate:
+ (+++) Runs automatically the calibration.
+ (+++) Enables the user trimming mode
+ (+++) Updates a structure with trimming values with fresh calibration
+ results.
+ The user may store the calibration results for larger
+ (ex monitoring the trimming as a function of temperature
+ for instance)
+
+ *** DAC wave generation feature ***
+ ===================================
+ [..]
+ Both DAC channels can be used to generate
+ (#) Noise wave
+ (#) Triangle wave
+
+ *** DAC data format ***
+ =======================
+ [..]
+ The DAC data format can be:
+ (#) 8-bit right alignment using DAC_ALIGN_8B_R
+ (#) 12-bit left alignment using DAC_ALIGN_12B_L
+ (#) 12-bit right alignment using DAC_ALIGN_12B_R
+
+ *** DAC data value to voltage correspondence ***
+ ================================================
+ [..]
+ The analog output voltage on each DAC channel pin is determined
+ by the following equation:
+ [..]
+ DAC_OUTx = VREF+ * DOR / 4095
+ (+) with DOR is the Data Output Register
+ [..]
+ VREF+ is the input voltage reference (refer to the device datasheet)
+ [..]
+ e.g. To set DAC_OUT1 to 0.7V, use
+ (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
+
+ *** DMA requests ***
+ =====================
+ [..]
+ A DMA request can be generated when an external trigger (but not a software trigger)
+ occurs if DMA requests are enabled using HAL_DAC_Start_DMA().
+ DMA requests are mapped as following:
+ GPDMA requests are mapped as following:
+ (+) DAC channel1 mapped on GPDMA request 2 (can be any GPDMA channel)
+ (+) DAC channel2 mapped on GPDMA request 3 (can be any GPDMA channel)
+ LPDMA requests are mapped as following:
+ (+) DAC channel1 mapped on LPDMA request 8 (can be any LPDMA channel)
+ (+) DAC channel2 mapped on LPDMA request 9 (can be any LPDMA channel)
+
+ *** High frequency interface mode ***
+ =====================================
+ [..]
+ The high frequency interface informs DAC instance about the bus frequency in use.
+ It is mandatory information for DAC (as internal timing of DAC is bus frequency dependent)
+ provided thanks to parameter DAC_HighFrequency handled in HAL_DAC_ConfigChannel () function.
+ Use of DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC value of DAC_HighFrequency is recommended
+ function figured out the correct setting.
+ The high frequency mode is same for all converters of a same DAC instance. Either same
+ parameter DAC_HighFrequency is used for all DAC converters or again self
+ DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC detection parameter.
+
+ [..]
+ (@) For Dual mode and specific signal (Triangle and noise) generation please
+ refer to Extended Features Driver description
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (+) DAC APB clock must be enabled to get write access to DAC
+ registers using HAL_DAC_Init()
+ (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
+ (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
+ (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA() functions.
+
+ *** Calibration mode IO operation ***
+ ======================================
+ [..]
+ (+) Retrieve the factory trimming (calibration settings) using HAL_DACEx_GetTrimOffset()
+ (+) Run the calibration using HAL_DACEx_SelfCalibrate()
+ (+) Update the trimming while DAC running using HAL_DACEx_SetUserTrimming()
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Start the DAC peripheral using HAL_DAC_Start()
+ (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
+ (+) Stop the DAC peripheral using HAL_DAC_Stop()
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
+ of data to be transferred at each end of conversion
+ First issued trigger will start the conversion of the value previously set by HAL_DAC_SetValue().
+ (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
+ function is executed and user can add his own code by customization of function pointer
+ HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
+ (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
+ function is executed and user can add his own code by customization of function pointer
+ HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
+ (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
+ add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
+ (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
+ HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2()
+ function is executed and user can add his own code by customization of function pointer
+ HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and
+ add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1()
+ (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
+
+ *** Callback registration ***
+ =============================================
+ [..]
+ The compilation define USE_HAL_DAC_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ Use Functions @ref HAL_DAC_RegisterCallback() to register a user callback,
+ it allows to register following callbacks:
+ (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
+ (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
+ (+) ErrorCallbackCh1 : callback when an error occurs on Ch1.
+ (+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1.
+ (+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2.
+ (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
+ (+) ErrorCallbackCh2 : callback when an error occurs on Ch2.
+ (+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2.
+ (+) MspInitCallback : DAC MspInit.
+ (+) MspDeInitCallback : DAC MspdeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_DAC_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function. It allows to reset following callbacks:
+ (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
+ (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
+ (+) ErrorCallbackCh1 : callback when an error occurs on Ch1.
+ (+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1.
+ (+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2.
+ (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
+ (+) ErrorCallbackCh2 : callback when an error occurs on Ch2.
+ (+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2.
+ (+) MspInitCallback : DAC MspInit.
+ (+) MspDeInitCallback : DAC MspdeInit.
+ (+) All Callbacks
+ This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+ By default, after the @ref HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
+ all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_DAC_Init
+ and @ref HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_DAC_Init and @ref HAL_DAC_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_DAC_RegisterCallback before calling @ref HAL_DAC_DeInit
+ or @ref HAL_DAC_Init function.
+
+ When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
+ *** DAC HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in DAC HAL driver.
+
+ (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
+ (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
+ (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
+ (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
+
+ [..]
+ (@) You can refer to the DAC HAL driver header file for more useful macros
+
+@endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+#if defined(DAC1)
+
+/** @defgroup DAC DAC
+ * @brief DAC driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup DAC_Private_Constants DAC Private Constants
+ * @{
+ */
+#define TIMEOUT_DAC_CALIBCONFIG 1U /* 1 ms */
+#define HFSEL_ENABLE_THRESHOLD_80MHZ 80000000U /* 80 MHz */
+#define HFSEL_ENABLE_THRESHOLD_160MHZ 160000000U /* 160 MHz */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions -------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Functions DAC Exported Functions
+ * @{
+ */
+
+/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the DAC.
+ (+) De-initialize the DAC.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the DAC peripheral according to the specified parameters
+ * in the DAC_InitStruct and initialize the associated handle.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac)
+{
+ /* Check DAC handle */
+ if (hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
+
+ if (hdac->State == HAL_DAC_STATE_RESET)
+ {
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ /* Init the DAC Callback settings */
+ hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
+ hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
+ hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
+ hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
+
+ hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
+ hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
+ hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
+ hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
+
+ if (hdac->MspInitCallback == NULL)
+ {
+ hdac->MspInitCallback = HAL_DAC_MspInit;
+ }
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
+ /* Allocate lock resource and initialize it */
+ hdac->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ /* Init the low level hardware */
+ hdac->MspInitCallback(hdac);
+#else
+ /* Init the low level hardware */
+ HAL_DAC_MspInit(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+ }
+
+ /* Initialize the DAC state*/
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Set DAC error code to none */
+ hdac->ErrorCode = HAL_DAC_ERROR_NONE;
+
+ /* Initialize the DAC state*/
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Deinitialize the DAC peripheral registers to their default reset values.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac)
+{
+ /* Check DAC handle */
+ if (hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ if (hdac->MspDeInitCallback == NULL)
+ {
+ hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ hdac->MspDeInitCallback(hdac);
+#else
+ /* DeInit the low level hardware */
+ HAL_DAC_MspDeInit(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
+ /* Set DAC error code to none */
+ hdac->ErrorCode = HAL_DAC_ERROR_NONE;
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the DAC MSP.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_DAC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the DAC MSP.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_DAC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Exported_Functions_Group2 IO operation functions
+ * @brief IO operation functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start conversion.
+ (+) Stop conversion.
+ (+) Start conversion and enable DMA transfer.
+ (+) Stop conversion and disable DMA transfer.
+ (+) Get result of conversion.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables DAC and starts conversion of channel.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Enable the Peripheral */
+ __HAL_DAC_ENABLE(hdac, Channel);
+ /* Ensure minimum wait before using peripheral after enabling it */
+ HAL_Delay(1);
+
+ if (Channel == DAC_CHANNEL_1)
+ {
+ /* Check if software trigger enabled */
+ if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE)
+ {
+ /* Enable the selected DAC software conversion */
+ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
+ }
+ }
+
+ else
+ {
+ /* Check if software trigger enabled */
+ if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (Channel & 0x10UL)))
+ {
+ /* Enable the selected DAC software conversion*/
+ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
+ }
+ }
+
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables DAC and stop conversion of channel.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+
+ /* Disable the Peripheral */
+ __HAL_DAC_DISABLE(hdac, Channel);
+ /* Ensure minimum wait before enabling peripheral after disabling it */
+ HAL_Delay(1);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables DAC and starts conversion of channel.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to DAC peripheral
+ * @param Alignment Specifies the data alignment for DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
+ * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
+ * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
+ uint32_t Alignment)
+{
+ HAL_StatusTypeDef status;
+ uint32_t tmpreg;
+ uint32_t LengthInBytes;
+ DMA_NodeConfTypeDef node_conf;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+ assert_param(IS_DAC_ALIGN(Alignment));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ if (Channel == DAC_CHANNEL_1)
+ {
+ /* Set the DMA transfer complete callback for channel1 */
+ hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
+
+ /* Set the DMA half transfer complete callback for channel1 */
+ hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
+
+ /* Set the DMA error callback for channel1 */
+ hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
+
+ /* Enable the selected DAC channel1 DMA request */
+ SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
+
+ /* Case of use of channel 1 */
+ switch (Alignment)
+ {
+ case DAC_ALIGN_12B_R:
+ /* Get DHR12R1 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
+ break;
+ case DAC_ALIGN_12B_L:
+ /* Get DHR12L1 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
+ break;
+ default: /* case DAC_ALIGN_8B_R */
+ /* Get DHR8R1 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
+ break;
+ }
+ }
+
+ else
+ {
+ /* Set the DMA transfer complete callback for channel2 */
+ hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
+
+ /* Set the DMA half transfer complete callback for channel2 */
+ hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
+
+ /* Set the DMA error callback for channel2 */
+ hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
+
+ /* Enable the selected DAC channel2 DMA request */
+ SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
+
+ /* Case of use of channel 2 */
+ switch (Alignment)
+ {
+ case DAC_ALIGN_12B_R:
+ /* Get DHR12R2 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
+ break;
+ case DAC_ALIGN_12B_L:
+ /* Get DHR12L2 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
+ break;
+ default: /* case DAC_ALIGN_8B_R */
+ /* Get DHR8R2 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
+ break;
+ }
+ }
+
+
+ /* Enable the DMA channel */
+ if (Channel == DAC_CHANNEL_1)
+ {
+ /* Enable the DAC DMA underrun interrupt */
+ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
+
+ /* Enable the DMA channel */
+ /* Check linkedlist mode */
+ if ((hdac->DMA_Handle1->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if ((hdac->DMA_Handle1->LinkedListQueue != NULL) && (hdac->DMA_Handle1->LinkedListQueue->Head != NULL))
+ {
+ /* Length should be converted to number of bytes */
+ if (HAL_DMAEx_List_GetNodeConfig(&node_conf, hdac->DMA_Handle1->LinkedListQueue->Head) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Length should be converted to number of bytes */
+ if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
+ {
+ /* Word -> Bytes */
+ LengthInBytes = Length * 4U;
+ }
+ else if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
+ {
+ /* Halfword -> Bytes */
+ LengthInBytes = Length * 2U;
+ }
+ else /* Bytes */
+ {
+ /* Same size already expressed in Bytes */
+ LengthInBytes = Length;
+ }
+
+ /* Set DMA data size */
+ hdac->DMA_Handle1->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = LengthInBytes;
+
+ /* Set DMA source address */
+ hdac->DMA_Handle1->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
+
+ /* Set DMA destination address */
+ hdac->DMA_Handle1->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = tmpreg;
+
+ /* Enable the DMA channel */
+ status = HAL_DMAEx_List_Start_IT(hdac->DMA_Handle1);
+ }
+ else
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Length should be converted to number of bytes */
+ if (hdac->DMA_Handle1->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
+ {
+ /* Word -> Bytes */
+ LengthInBytes = Length * 4U;
+ }
+ else if (hdac->DMA_Handle1->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
+ {
+ /* Halfword -> Bytes */
+ LengthInBytes = Length * 2U;
+ }
+ else /* Bytes */
+ {
+ /* Same size already expressed in Bytes */
+ LengthInBytes = Length;
+ }
+
+ /* Enable the DMA channel */
+ status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, LengthInBytes);
+ }
+ }
+
+ else
+ {
+ /* Enable the DAC DMA underrun interrupt */
+ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
+
+ /* Enable the DMA channel */
+ /* Check linkedlist mode */
+ if ((hdac->DMA_Handle2->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if ((hdac->DMA_Handle2->LinkedListQueue != NULL) && (hdac->DMA_Handle2->LinkedListQueue->Head != NULL))
+ {
+ /* Length should be converted to number of bytes */
+ if (HAL_DMAEx_List_GetNodeConfig(&node_conf, hdac->DMA_Handle2->LinkedListQueue->Head) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Length should be converted to number of bytes */
+ if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
+ {
+ /* Word -> Bytes */
+ LengthInBytes = Length * 4U;
+ }
+ else if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
+ {
+ /* Halfword -> Bytes */
+ LengthInBytes = Length * 2U;
+ }
+ else /* Bytes */
+ {
+ /* Same size already expressed in Bytes */
+ LengthInBytes = Length;
+ }
+
+ /* Set DMA data size */
+ hdac->DMA_Handle2->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = LengthInBytes;
+
+ /* Set DMA source address */
+ hdac->DMA_Handle2->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
+
+ /* Set DMA destination address */
+ hdac->DMA_Handle2->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = tmpreg;
+
+ /* Enable the DMA channel */
+ status = HAL_DMAEx_List_Start_IT(hdac->DMA_Handle2);
+ }
+ else
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Length should be converted to number of bytes */
+ if (hdac->DMA_Handle2->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
+ {
+ /* Word -> Bytes */
+ LengthInBytes = Length * 4U;
+ }
+ else if (hdac->DMA_Handle2->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
+ {
+ /* Halfword -> Bytes */
+ LengthInBytes = Length * 2U;
+ }
+ else /* Bytes */
+ {
+ /* Same size already expressed in Bytes */
+ LengthInBytes = Length;
+ }
+
+ /* Enable the DMA channel */
+ status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, LengthInBytes);
+ }
+ }
+
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdac);
+
+ if (status == HAL_OK)
+ {
+ /* Enable the Peripheral */
+ __HAL_DAC_ENABLE(hdac, Channel);
+ /* Ensure minimum wait before using peripheral after enabling it */
+ HAL_Delay(1);
+ }
+ else
+ {
+ hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Disables DAC and stop conversion of channel.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+
+ /* Disable the selected DAC channel DMA request */
+ hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << (Channel & 0x10UL));
+
+ /* Disable the Peripheral */
+ __HAL_DAC_DISABLE(hdac, Channel);
+ /* Ensure minimum wait before enabling peripheral after disabling it */
+ HAL_Delay(1);
+
+ /* Disable the DMA channel */
+
+ /* Channel1 is used */
+ if (Channel == DAC_CHANNEL_1)
+ {
+ /* Disable the DMA channel */
+ (void)HAL_DMA_Abort(hdac->DMA_Handle1);
+
+ /* Disable the DAC DMA underrun interrupt */
+ __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
+ }
+
+ else /* Channel2 is used for */
+ {
+ /* Disable the DMA channel */
+ (void)HAL_DMA_Abort(hdac->DMA_Handle2);
+
+ /* Disable the DAC DMA underrun interrupt */
+ __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
+ }
+
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Handles DAC interrupt request
+ * This function uses the interruption of DMA
+ * underrun.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
+{
+ if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
+ {
+ /* Check underrun flag of DAC channel 1 */
+ if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
+ {
+ /* Change DAC state to error state */
+ hdac->State = HAL_DAC_STATE_ERROR;
+
+ /* Set DAC error code to channel1 DMA underrun error */
+ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
+
+ /* Clear the underrun flag */
+ __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1);
+
+ /* Disable the selected DAC channel1 DMA request */
+ CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
+
+ /* Error callback */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ hdac->DMAUnderrunCallbackCh1(hdac);
+#else
+ HAL_DAC_DMAUnderrunCallbackCh1(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+ }
+ }
+
+
+ if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
+ {
+ /* Check underrun flag of DAC channel 2 */
+ if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
+ {
+ /* Change DAC state to error state */
+ hdac->State = HAL_DAC_STATE_ERROR;
+
+ /* Set DAC error code to channel2 DMA underrun error */
+ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2);
+
+ /* Clear the underrun flag */
+ __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2);
+
+ /* Disable the selected DAC channel2 DMA request */
+ CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
+
+ /* Error callback */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ hdac->DMAUnderrunCallbackCh2(hdac);
+#else
+ HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+ }
+ }
+
+}
+
+/**
+ * @brief Set the specified data holding register value for DAC channel.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @param Alignment Specifies the data alignment.
+ * This parameter can be one of the following values:
+ * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
+ * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
+ * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
+ * @param Data Data to be loaded in the selected data holding register.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
+{
+ __IO uint32_t tmp = 0UL;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+ assert_param(IS_DAC_ALIGN(Alignment));
+ /* In case DMA Double data mode is activated, DATA range is almost full uin32_t one: no check */
+ if ((hdac->Instance->MCR & (DAC_MCR_DMADOUBLE1 << (Channel & 0x10UL))) == 0UL)
+ {
+ assert_param(IS_DAC_DATA(Data));
+ }
+
+ tmp = (uint32_t)hdac->Instance;
+ if (Channel == DAC_CHANNEL_1)
+ {
+ tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
+ }
+
+ else
+ {
+ tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
+ }
+
+
+ /* Set the DAC channel selected data holding register */
+ *(__IO uint32_t *) tmp = Data;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Conversion complete callback in non-blocking mode for Channel1
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Conversion half DMA transfer callback in non-blocking mode for Channel1
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Error DAC callback for Channel1.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DMA underrun DAC callback for channel1.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure channels.
+ (+) Set the specified data holding register value for DAC channel.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the last data output value of the selected DAC channel.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @retval The selected DAC channel data output value.
+ */
+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+
+ /* Returns the DAC channel data output register value */
+ if (Channel == DAC_CHANNEL_1)
+ {
+ return hdac->Instance->DOR1;
+ }
+
+ else
+ {
+ return hdac->Instance->DOR2;
+ }
+
+}
+
+/**
+ * @brief Configures the selected DAC channel.
+ * @note By calling this function, if the application will be run in stop
+ * mode, the DAC_Trigger field of the structure sConfig
+ * should be one of the following values:
+ * - DAC_TRIGGER_STOP_LPTIM1_OUT
+ * - DAC_TRIGGER_STOP_LPTIM3_OUT
+ * - DAC_TRIGGER_STOP_EXT_IT9
+ * For application where DAC is not run in stop mode, the DAC trigger
+ * should be a value of @ref DAC_trigger_selection
+ * @note By calling this function, the high frequency interface mode (HFSEL bits)
+ * will be set. This parameter scope is the DAC instance. As the function
+ * is called for each channel, the @ref DAC_HighFrequency of @arg sConfig
+ * must be the same at each call.
+ * (or DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC self detect).
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param sConfig DAC configuration structure.
+ * @param Channel The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
+{
+ uint32_t tmpreg1;
+ uint32_t tmpreg2;
+ uint32_t tickstart;
+ uint32_t hclkfreq;
+ uint32_t connectOnChip;
+
+ /* Check the DAC parameters */
+ assert_param(IS_DAC_AUTONOMOUS(sConfig->DAC_AutonomousMode));
+ assert_param(IS_DAC_HIGH_FREQUENCY_MODE(sConfig->DAC_HighFrequency));
+ assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
+ assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
+ assert_param(IS_DAC_CHIP_CONNECTION(sConfig->DAC_ConnectOnChipPeripheral));
+ assert_param(IS_DAC_TRIMMING(sConfig->DAC_UserTrimming));
+ if ((sConfig->DAC_UserTrimming) == DAC_TRIMMING_USER)
+ {
+ assert_param(IS_DAC_TRIMMINGVALUE(sConfig->DAC_TrimmingValue));
+ }
+ assert_param(IS_DAC_SAMPLEANDHOLD(sConfig->DAC_SampleAndHold));
+ if ((sConfig->DAC_SampleAndHold) == DAC_SAMPLEANDHOLD_ENABLE)
+ {
+ assert_param(IS_DAC_SAMPLETIME(sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime));
+ assert_param(IS_DAC_HOLDTIME(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime));
+ assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime));
+ }
+ assert_param(IS_DAC_CHANNEL(Channel));
+ assert_param(IS_FUNCTIONAL_STATE(sConfig->DAC_DMADoubleDataMode));
+ assert_param(IS_FUNCTIONAL_STATE(sConfig->DAC_SignedFormat));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Sample and hold configuration */
+ if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE)
+ {
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ if (Channel == DAC_CHANNEL_1)
+ {
+ /* SHSR1 can be written when BWST1 is cleared */
+ while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL)
+ {
+ /* Check for the Timeout */
+ if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
+ {
+ /* New check to avoid false timeout detection in case of preemption */
+ if (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL)
+ {
+ /* Update error code */
+ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
+
+ /* Change the DMA state */
+ hdac->State = HAL_DAC_STATE_TIMEOUT;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ HAL_Delay(1);
+ hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
+ }
+
+ else /* Channel 2 */
+ {
+ /* SHSR2 can be written when BWST2 is cleared */
+ while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL)
+ {
+ /* Check for the Timeout */
+ if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
+ {
+ /* New check to avoid false timeout detection in case of preemption */
+ if (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL)
+ {
+ /* Update error code */
+ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
+
+ /* Change the DMA state */
+ hdac->State = HAL_DAC_STATE_TIMEOUT;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ HAL_Delay(1U);
+ hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
+ }
+
+
+ /* HoldTime */
+ MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL),
+ (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL));
+ /* RefreshTime */
+ MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL),
+ (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL));
+ }
+
+ /* Autonomous mode configuration */
+ MODIFY_REG(hdac->Instance->AUTOCR, DAC_AUTOCR_AUTOMODE, sConfig->DAC_AutonomousMode);
+
+ if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER)
+ /* USER TRIMMING */
+ {
+ /* Get the DAC CCR value */
+ tmpreg1 = hdac->Instance->CCR;
+ /* Clear trimming value */
+ tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << (Channel & 0x10UL));
+ /* Configure for the selected trimming offset */
+ tmpreg2 = sConfig->DAC_TrimmingValue;
+ /* Calculate CCR register value depending on DAC_Channel */
+ tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
+ /* Write to DAC CCR */
+ hdac->Instance->CCR = tmpreg1;
+ }
+ /* else factory trimming is used (factory setting are available at reset)*/
+ /* SW Nothing has nothing to do */
+
+ /* Get the DAC MCR value */
+ tmpreg1 = hdac->Instance->MCR;
+ /* Clear DAC_MCR_MODEx bits */
+ tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL));
+ /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */
+ if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL)
+ {
+ connectOnChip = 0x00000000UL;
+ }
+ else if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_INTERNAL)
+ {
+ connectOnChip = DAC_MCR_MODE1_0;
+ }
+ else /* (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_BOTH) */
+ {
+ if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_ENABLE)
+ {
+ connectOnChip = DAC_MCR_MODE1_0;
+ }
+ else
+ {
+ connectOnChip = 0x00000000UL;
+ }
+ }
+ tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | connectOnChip);
+ /* Clear DAC_MCR_DMADOUBLEx */
+ tmpreg1 &= ~(((uint32_t)(DAC_MCR_DMADOUBLE1)) << (Channel & 0x10UL));
+ /* Configure for the selected DAC channel: DMA double data mode */
+ tmpreg2 |= (sConfig->DAC_DMADoubleDataMode == ENABLE) ? DAC_MCR_DMADOUBLE1 : 0UL;
+ /* Clear DAC_MCR_SINFORMATx */
+ tmpreg1 &= ~(((uint32_t)(DAC_MCR_SINFORMAT1)) << (Channel & 0x10UL));
+ /* Configure for the selected DAC channel: Signed format */
+ tmpreg2 |= (sConfig->DAC_SignedFormat == ENABLE) ? DAC_MCR_SINFORMAT1 : 0UL;
+ /* Clear DAC_MCR_HFSEL bits */
+ tmpreg1 &= ~(DAC_MCR_HFSEL);
+ /* Configure for both DAC channels: high frequency mode */
+ if (DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC == sConfig->DAC_HighFrequency)
+ {
+ hclkfreq = HAL_RCC_GetHCLKFreq();
+ if (hclkfreq > HFSEL_ENABLE_THRESHOLD_160MHZ)
+ {
+ tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ;
+ }
+ else if (hclkfreq > HFSEL_ENABLE_THRESHOLD_80MHZ)
+ {
+ tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ;
+ }
+ else
+ {
+ tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE;
+ }
+ }
+ else
+ {
+ tmpreg1 |= sConfig->DAC_HighFrequency;
+ }
+ /* Calculate MCR register value depending on DAC_Channel */
+ tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
+ /* Write to DAC MCR */
+ hdac->Instance->MCR = tmpreg1;
+
+ /* DAC in normal operating mode hence clear DAC_CR_CENx bit */
+ CLEAR_BIT(hdac->Instance->CR, DAC_CR_CEN1 << (Channel & 0x10UL));
+
+ /* Get the DAC CR value */
+ tmpreg1 = hdac->Instance->CR;
+ /* Clear TENx, TSELx, WAVEx and MAMPx bits */
+ tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << (Channel & 0x10UL));
+ /* Configure for the selected DAC channel: trigger */
+ /* Set TSELx and TENx bits according to DAC_Trigger value */
+ tmpreg2 = sConfig->DAC_Trigger;
+ /* Calculate CR register value depending on DAC_Channel */
+ tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
+ /* Write to DAC CR */
+ hdac->Instance->CR = tmpreg1;
+ /* Disable wave generation */
+ CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL)));
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
+ * @brief Peripheral State and Errors functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Errors functions #####
+ ==============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Check the DAC state.
+ (+) Check the DAC Errors.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the DAC handle state
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval HAL state
+ */
+HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac)
+{
+ /* Return DAC handle state */
+ return hdac->State;
+}
+
+
+/**
+ * @brief Return the DAC error code
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval DAC Error Code
+ */
+uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
+{
+ return hdac->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DAC_Exported_Functions_Group1
+ * @{
+ */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User DAC Callback
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hdac DAC handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_DAC_ERROR_INVALID_CALLBACK DAC Error Callback ID
+ * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 Complete Callback ID
+ * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
+ * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
+ * @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
+ * @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
+ * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
+ * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
+ * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
+ * @arg @ref HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID
+ * @arg @ref HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID
+ *
+ * @param pCallback pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
+ pDAC_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ if (hdac->State == HAL_DAC_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DAC_CH1_COMPLETE_CB_ID :
+ hdac->ConvCpltCallbackCh1 = pCallback;
+ break;
+ case HAL_DAC_CH1_HALF_COMPLETE_CB_ID :
+ hdac->ConvHalfCpltCallbackCh1 = pCallback;
+ break;
+ case HAL_DAC_CH1_ERROR_ID :
+ hdac->ErrorCallbackCh1 = pCallback;
+ break;
+ case HAL_DAC_CH1_UNDERRUN_CB_ID :
+ hdac->DMAUnderrunCallbackCh1 = pCallback;
+ break;
+
+ case HAL_DAC_CH2_COMPLETE_CB_ID :
+ hdac->ConvCpltCallbackCh2 = pCallback;
+ break;
+ case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
+ hdac->ConvHalfCpltCallbackCh2 = pCallback;
+ break;
+ case HAL_DAC_CH2_ERROR_ID :
+ hdac->ErrorCallbackCh2 = pCallback;
+ break;
+ case HAL_DAC_CH2_UNDERRUN_CB_ID :
+ hdac->DMAUnderrunCallbackCh2 = pCallback;
+ break;
+
+ case HAL_DAC_MSPINIT_CB_ID :
+ hdac->MspInitCallback = pCallback;
+ break;
+ case HAL_DAC_MSPDEINIT_CB_ID :
+ hdac->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* Update the error code */
+ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hdac->State == HAL_DAC_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DAC_MSPINIT_CB_ID :
+ hdac->MspInitCallback = pCallback;
+ break;
+ case HAL_DAC_MSPDEINIT_CB_ID :
+ hdac->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* Update the error code */
+ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdac);
+ return status;
+}
+
+/**
+ * @brief Unregister a User DAC Callback
+ * DAC Callback is redirected to the weak (surcharged) predefined callback
+ * @param hdac DAC handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 transfer Complete Callback ID
+ * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
+ * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
+ * @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
+ * @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
+ * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
+ * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
+ * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
+ * @arg @ref HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID
+ * @arg @ref HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID
+ * @arg @ref HAL_DAC_ALL_CB_ID DAC All callbacks
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ if (hdac->State == HAL_DAC_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DAC_CH1_COMPLETE_CB_ID :
+ hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
+ break;
+ case HAL_DAC_CH1_HALF_COMPLETE_CB_ID :
+ hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
+ break;
+ case HAL_DAC_CH1_ERROR_ID :
+ hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
+ break;
+ case HAL_DAC_CH1_UNDERRUN_CB_ID :
+ hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
+ break;
+
+ case HAL_DAC_CH2_COMPLETE_CB_ID :
+ hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
+ break;
+ case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
+ hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
+ break;
+ case HAL_DAC_CH2_ERROR_ID :
+ hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
+ break;
+ case HAL_DAC_CH2_UNDERRUN_CB_ID :
+ hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
+ break;
+
+ case HAL_DAC_MSPINIT_CB_ID :
+ hdac->MspInitCallback = HAL_DAC_MspInit;
+ break;
+ case HAL_DAC_MSPDEINIT_CB_ID :
+ hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
+ break;
+ case HAL_DAC_ALL_CB_ID :
+ hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
+ hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
+ hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
+ hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
+
+ hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
+ hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
+ hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
+ hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
+
+ hdac->MspInitCallback = HAL_DAC_MspInit;
+ hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
+ break;
+ default :
+ /* Update the error code */
+ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hdac->State == HAL_DAC_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DAC_MSPINIT_CB_ID :
+ hdac->MspInitCallback = HAL_DAC_MspInit;
+ break;
+ case HAL_DAC_MSPDEINIT_CB_ID :
+ hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
+ break;
+ default :
+ /* Update the error code */
+ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdac);
+ return status;
+}
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief DMA conversion complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ hdac->ConvCpltCallbackCh1(hdac);
+#else
+ HAL_DAC_ConvCpltCallbackCh1(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
+ hdac->State = HAL_DAC_STATE_READY;
+}
+
+/**
+ * @brief DMA half transfer complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ /* Conversion complete callback */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ hdac->ConvHalfCpltCallbackCh1(hdac);
+#else
+ HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA error callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Set DAC error code to DMA error */
+ hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
+
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ hdac->ErrorCallbackCh1(hdac);
+#else
+ HAL_DAC_ErrorCallbackCh1(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
+ hdac->State = HAL_DAC_STATE_READY;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* DAC1 */
+
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dac_ex.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dac_ex.c
new file mode 100644
index 00000000..16fdb1d5
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dac_ex.c
@@ -0,0 +1,1040 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_dac_ex.c
+ * @author MCD Application Team
+ * @brief Extended DAC HAL module driver.
+ * This file provides firmware functions to manage the extended
+ * functionalities of the DAC peripheral.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+
+ *** Dual mode IO operation ***
+ ==============================
+ [..]
+ (+) Use HAL_DACEx_DualStart() to enable both channel and start conversion
+ for dual mode operation.
+ If software trigger is selected, using HAL_DACEx_DualStart() will start
+ the conversion of the value previously set by HAL_DACEx_DualSetValue().
+ (+) Use HAL_DACEx_DualStop() to disable both channel and stop conversion
+ for dual mode operation.
+ (+) Use HAL_DACEx_DualStart_DMA() to enable both channel and start conversion
+ for dual mode operation using DMA to feed DAC converters.
+ First issued trigger will start the conversion of the value previously
+ set by HAL_DACEx_DualSetValue().
+ The same callbacks that are used in single mode are called in dual mode to notify
+ transfer completion (half complete or complete), errors or underrun.
+ (+) Use HAL_DACEx_DualStop_DMA() to disable both channel and stop conversion
+ for dual mode operation using DMA to feed DAC converters.
+ (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) :
+ Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
+ HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in
+ Channel 1 and Channel 2.
+
+ *** Signal generation operation ***
+ ===================================
+ [..]
+ (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
+ (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
+
+ (+) HAL_DACEx_SelfCalibrate to calibrate one DAC channel.
+ (+) HAL_DACEx_SetUserTrimming to set user trimming value.
+ (+) HAL_DACEx_GetTrimOffset to retrieve trimming value (factory setting
+ after reset, user setting if HAL_DACEx_SetUserTrimming have been used
+ at least one time after reset).
+
+ *** Autonomous Mode operation ***
+ ===================================
+ [..]
+ (+) Use HAL_DACx_SetConfigAutonomousMode() to configure the autonomous mode
+ (+) Use HAL_DACx_GetConfigAutonomousMode() to get the current configuration of the autonomous mode
+ (+) Use HAL_DACx_ClearConfigAutonomousMode() to clear the configuration of the autonomous mode
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+
+#if defined(DAC1)
+
+/** @defgroup DACEx DACEx
+ * @brief DAC Extended HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup DACEx_Exported_Functions DACEx Exported Functions
+ * @{
+ */
+
+/** @defgroup DACEx_Exported_Functions_Group2 IO operation functions
+ * @brief Extended IO operation functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Extended features functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start conversion.
+ (+) Stop conversion.
+ (+) Start conversion and enable DMA transfer.
+ (+) Stop conversion and disable DMA transfer.
+ (+) Get result of conversion.
+ (+) Get result of dual mode conversion.
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Enables DAC and starts conversion of both channels.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac)
+{
+ uint32_t tmp_swtrig = 0UL;
+
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Enable the Peripheral */
+ __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_1);
+ __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2);
+ /* Ensure minimum wait before using peripheral after enabling it */
+ HAL_Delay(1);
+
+ /* Check if software trigger enabled */
+ if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE)
+ {
+ tmp_swtrig |= DAC_SWTRIGR_SWTRIG1;
+ }
+ if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (DAC_CHANNEL_2 & 0x10UL)))
+ {
+ tmp_swtrig |= DAC_SWTRIGR_SWTRIG2;
+ }
+ /* Enable the selected DAC software conversion*/
+ SET_BIT(hdac->Instance->SWTRIGR, tmp_swtrig);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables DAC and stop conversion of both channels.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac)
+{
+
+ /* Disable the Peripheral */
+ __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1);
+ __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_2);
+ /* Ensure minimum wait before enabling peripheral after disabling it */
+ HAL_Delay(1);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables DAC and starts conversion of both channel 1 and 2 of the same DAC.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel The DAC channel that will request data from DMA.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @param pData The destination peripheral Buffer address.
+ * @param Length The length of data to be transferred from memory to DAC peripheral
+ * @param Alignment Specifies the data alignment for DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
+ * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
+ * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
+ uint32_t Alignment)
+{
+ HAL_StatusTypeDef status;
+ uint32_t tmpreg;
+ uint32_t LengthInBytes;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+ assert_param(IS_DAC_ALIGN(Alignment));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ if (Channel == DAC_CHANNEL_1)
+ {
+ /* Set the DMA transfer complete callback for channel1 */
+ hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
+
+ /* Set the DMA half transfer complete callback for channel1 */
+ hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
+
+ /* Set the DMA error callback for channel1 */
+ hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
+
+ /* Enable the selected DAC channel1 DMA request */
+ SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
+ }
+ else
+ {
+ /* Set the DMA transfer complete callback for channel2 */
+ hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
+
+ /* Set the DMA half transfer complete callback for channel2 */
+ hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
+
+ /* Set the DMA error callback for channel2 */
+ hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
+
+ /* Enable the selected DAC channel2 DMA request */
+ SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
+ }
+
+ switch (Alignment)
+ {
+ case DAC_ALIGN_12B_R:
+ /* Get DHR12R1 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR12RD;
+ break;
+ case DAC_ALIGN_12B_L:
+ /* Get DHR12L1 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR12LD;
+ break;
+ default: /* case DAC_ALIGN_8B_R */
+ /* Get DHR8R1 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR8RD;
+ break;
+ }
+
+ /* Enable the DMA channel */
+ if (Channel == DAC_CHANNEL_1)
+ {
+ /* Enable the DAC DMA underrun interrupt */
+ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
+
+ /* Length should be converted to number of bytes */
+ LengthInBytes = Length * 4U;
+
+ /* Check linkedlist mode */
+ if ((hdac->DMA_Handle1->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if ((hdac->DMA_Handle1->LinkedListQueue != NULL) && (hdac->DMA_Handle1->LinkedListQueue->Head != NULL))
+ {
+ /* Set DMA data size */
+ hdac->DMA_Handle1->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = LengthInBytes;
+
+ /* Set DMA source address */
+ hdac->DMA_Handle1->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
+
+ /* Set DMA destination address */
+ hdac->DMA_Handle1->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = tmpreg;
+
+ /* Enable the DMA channel */
+ status = HAL_DMAEx_List_Start_IT(hdac->DMA_Handle1);
+ }
+ else
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Enable the DMA channel */
+ status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, LengthInBytes);
+ }
+ }
+ else
+ {
+ /* Enable the DAC DMA underrun interrupt */
+ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
+
+ /* Length should be converted to number of bytes */
+ LengthInBytes = Length * 4U;
+
+ /* Check linkedlist mode */
+ if ((hdac->DMA_Handle2->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if ((hdac->DMA_Handle2->LinkedListQueue != NULL) && (hdac->DMA_Handle2->LinkedListQueue->Head != NULL))
+ {
+ /* Set DMA data size */
+ hdac->DMA_Handle2->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = LengthInBytes;
+
+ /* Set DMA source address */
+ hdac->DMA_Handle2->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
+
+ /* Set DMA destination address */
+ hdac->DMA_Handle2->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = tmpreg;
+
+ /* Enable the DMA channel */
+ status = HAL_DMAEx_List_Start_IT(hdac->DMA_Handle2);
+ }
+ else
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Enable the DMA channel */
+ status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, LengthInBytes);
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdac);
+
+ if (status == HAL_OK)
+ {
+ /* Enable the Peripheral */
+ __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_1);
+ __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2);
+ /* Ensure minimum wait before using peripheral after enabling it */
+ HAL_Delay(1);
+ }
+ else
+ {
+ hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Disables DAC and stop conversion both channel.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel The DAC channel that requests data from DMA.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
+{
+ HAL_StatusTypeDef status;
+
+
+ /* Disable the selected DAC channel DMA request */
+ CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2 | DAC_CR_DMAEN1);
+
+ /* Disable the Peripheral */
+ __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1);
+ __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_2);
+ /* Ensure minimum wait before enabling peripheral after disabling it */
+ HAL_Delay(1);
+
+ /* Disable the DMA channel */
+
+ /* Channel1 is used */
+ if (Channel == DAC_CHANNEL_1)
+ {
+ /* Disable the DMA channel */
+ status = HAL_DMA_Abort(hdac->DMA_Handle1);
+
+ /* Disable the DAC DMA underrun interrupt */
+ __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
+ }
+ else
+ {
+ /* Disable the DMA channel */
+ status = HAL_DMA_Abort(hdac->DMA_Handle2);
+
+ /* Disable the DAC DMA underrun interrupt */
+ __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
+ }
+
+ /* Check if DMA Channel effectively disabled */
+ if (status != HAL_OK)
+ {
+ /* Update DAC state machine to error */
+ hdac->State = HAL_DAC_STATE_ERROR;
+ }
+ else
+ {
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+ }
+
+ /* Return function status */
+ return status;
+}
+
+
+/**
+ * @brief Enable or disable the selected DAC channel wave generation.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @param Amplitude Select max triangle amplitude.
+ * This parameter can be one of the following values:
+ * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
+ * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
+ * @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
+ * @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
+ * @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
+ * @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
+ * @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
+ * @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
+ * @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
+ * @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
+ * @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
+ * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+ assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Enable the triangle wave generation for the selected DAC channel */
+ MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL),
+ (DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL));
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable or disable the selected DAC channel wave generation.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @param Amplitude Unmask DAC channel LFSR for noise wave generation.
+ * This parameter can be one of the following values:
+ * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+ assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Enable the noise wave generation for the selected DAC channel */
+ MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL),
+ (DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL));
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Set the specified data holding register value for dual DAC channel.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Alignment Specifies the data alignment for dual channel DAC.
+ * This parameter can be one of the following values:
+ * DAC_ALIGN_8B_R: 8bit right data alignment selected
+ * DAC_ALIGN_12B_L: 12bit left data alignment selected
+ * DAC_ALIGN_12B_R: 12bit right data alignment selected
+ * @param Data1 Data for DAC Channel1 to be loaded in the selected data holding register.
+ * @param Data2 Data for DAC Channel2 to be loaded in the selected data holding register.
+ * @note In dual mode, a unique register access is required to write in both
+ * DAC channels at the same time.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
+{
+ uint32_t data;
+ uint32_t tmp;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALIGN(Alignment));
+ assert_param(IS_DAC_DATA(Data1));
+ assert_param(IS_DAC_DATA(Data2));
+
+ /* Calculate and set dual DAC data holding register value */
+ if (Alignment == DAC_ALIGN_8B_R)
+ {
+ data = ((uint32_t)Data2 << 8U) | Data1;
+ }
+ else
+ {
+ data = ((uint32_t)Data2 << 16U) | Data1;
+ }
+
+ tmp = (uint32_t)hdac->Instance;
+ tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
+
+ /* Set the dual DAC selected data holding register */
+ *(__IO uint32_t *)tmp = data;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Conversion complete callback in non-blocking mode for Channel2.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Conversion half DMA transfer callback in non-blocking mode for Channel2.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Error DAC callback for Channel2.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DMA underrun DAC callback for Channel2.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
+ */
+}
+
+
+/**
+ * @brief Run the self calibration of one DAC channel.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param sConfig DAC channel configuration structure.
+ * @param Channel The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @retval Updates DAC_TrimmingValue. , DAC_UserTrimming set to DAC_UserTrimming
+ * @retval HAL status
+ * @note Calibration runs about 7 ms.
+ */
+HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ __IO uint32_t tmp;
+ uint32_t trimmingvalue;
+ uint32_t delta;
+
+ /* store/restore channel configuration structure purpose */
+ uint32_t oldmodeconfiguration;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+
+ /* Check the DAC handle allocation */
+ /* Check if DAC running */
+ if (hdac == NULL)
+ {
+ status = HAL_ERROR;
+ }
+ else if (hdac->State == HAL_DAC_STATE_BUSY)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Store configuration */
+ oldmodeconfiguration = (hdac->Instance->MCR & (DAC_MCR_MODE1 << (Channel & 0x10UL)));
+
+ /* Disable the selected DAC channel */
+ CLEAR_BIT((hdac->Instance->CR), (DAC_CR_EN1 << (Channel & 0x10UL)));
+ /* Wait for ready bit to be de-asserted */
+ HAL_Delay(1);
+
+ /* Set mode in MCR for calibration */
+ MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), 0U);
+
+ /* Set DAC Channel1 DHR register to the middle value */
+ tmp = (uint32_t)hdac->Instance;
+
+ if (Channel == DAC_CHANNEL_1)
+ {
+ tmp += DAC_DHR12R1_ALIGNMENT(DAC_ALIGN_12B_R);
+ }
+ else
+ {
+ tmp += DAC_DHR12R2_ALIGNMENT(DAC_ALIGN_12B_R);
+ }
+
+ *(__IO uint32_t *) tmp = 0x0800UL;
+
+ /* Enable the selected DAC channel calibration */
+ /* i.e. set DAC_CR_CENx bit */
+ SET_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL)));
+
+ /* Init trimming counter */
+ /* Medium value */
+ trimmingvalue = 16UL;
+ delta = 8UL;
+ while (delta != 0UL)
+ {
+ /* Set candidate trimming */
+ MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
+
+ /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */
+ /* i.e. minimum time needed between two calibration steps */
+ HAL_Delay(1);
+
+ if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL)))
+ {
+ /* DAC_SR_CAL_FLAGx is HIGH try higher trimming */
+ trimmingvalue -= delta;
+ }
+ else
+ {
+ /* DAC_SR_CAL_FLAGx is LOW try lower trimming */
+ trimmingvalue += delta;
+ }
+ delta >>= 1UL;
+ }
+
+ /* Still need to check if right calibration is current value or one step below */
+ /* Indeed the first value that causes the DAC_SR_CAL_FLAGx bit to change from 0 to 1 */
+ /* Set candidate trimming */
+ MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
+
+ /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */
+ /* i.e. minimum time needed between two calibration steps */
+ HAL_Delay(1U);
+
+ if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL)
+ {
+ /* Trimming is actually one value more */
+ trimmingvalue++;
+ /* Set right trimming */
+ MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
+ }
+
+ /* Disable the selected DAC channel calibration */
+ /* i.e. clear DAC_CR_CENx bit */
+ CLEAR_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL)));
+
+ sConfig->DAC_TrimmingValue = trimmingvalue;
+ sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
+
+ /* Restore configuration */
+ MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), oldmodeconfiguration);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdac);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Set the trimming mode and trimming value (user trimming mode applied).
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param sConfig DAC configuration structure updated with new DAC trimming value.
+ * @param Channel The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @param NewTrimmingValue DAC new trimming value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel,
+ uint32_t NewTrimmingValue)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+ assert_param(IS_DAC_NEWTRIMMINGVALUE(NewTrimmingValue));
+
+ /* Check the DAC handle allocation */
+ if (hdac == NULL)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Set new trimming */
+ MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (NewTrimmingValue << (Channel & 0x10UL)));
+
+ /* Update trimming mode */
+ sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
+ sConfig->DAC_TrimmingValue = NewTrimmingValue;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdac);
+ }
+ return status;
+}
+
+/**
+ * @brief Return the DAC trimming value.
+ * @param hdac DAC handle
+ * @param Channel The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @retval Trimming value : range: 0->31
+ *
+ */
+uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel)
+{
+ /* Check the parameter */
+ assert_param(IS_DAC_CHANNEL(Channel));
+
+ /* Retrieve trimming */
+ return ((hdac->Instance->CCR & (DAC_CCR_OTRIM1 << (Channel & 0x10UL))) >> (Channel & 0x10UL));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DACEx_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Extended Peripheral Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Set the specified data holding register value for DAC channel.
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Return the last data output value of the selected DAC channel.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval The selected DAC channel data output value.
+ */
+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac)
+{
+ uint32_t tmp = 0UL;
+
+ tmp |= hdac->Instance->DOR1;
+
+ tmp |= hdac->Instance->DOR2 << 16UL;
+
+ /* Returns the DAC channel data output register value */
+ return tmp;
+}
+
+
+/**
+ * @}
+ */
+/**
+ * @brief Set autonomous mode Configuration.
+ * @note The autonomous mode applies to the 2 channels of a DAC block (same for both channels)
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param sConfig pointer to Autonomous mode structure parameters.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DACEx_SetConfigAutonomousMode(DAC_HandleTypeDef *hdac, DAC_AutonomousModeConfTypeDef *sConfig)
+{
+ assert_param(IS_DAC_AUTONOMOUS(sConfig->AutonomousModeState));
+
+ if (hdac->State == HAL_DAC_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hdac);
+
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* NOTE: The set/reset of the bit automode in the AUTOCR
+ register is for both dac_channel1 and dac_channel2 */
+
+ /* Update the AUTOCR register */
+ MODIFY_REG(hdac->Instance->AUTOCR, DAC_AUTOCR_AUTOMODE, sConfig->AutonomousModeState);
+
+ /* Update the DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdac);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Get autonomous mode Configuration.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param sConfig pointer to Autonomous mode structure parameters.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DACEx_GetConfigAutonomousMode(DAC_HandleTypeDef *hdac, DAC_AutonomousModeConfTypeDef *sConfig)
+{
+ /* Fill Autonomous structure parameter */
+ sConfig->AutonomousModeState = READ_BIT(hdac->Instance->AUTOCR, DAC_AUTOCR_AUTOMODE);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Clear autonomous mode Configuration.
+ * @note The autonomous mode applies to the 2 channels of a DAC block (same for both channels)
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DACEx_ClearConfigAutonomousMode(DAC_HandleTypeDef *hdac)
+{
+ if (hdac->State == HAL_DAC_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hdac);
+
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* NOTE: The set/reset of the bit automode in the AUTOCR
+ register is for both dac_channel1 and dac_channel2 */
+
+ /* Clear AUTOCR register */
+ CLEAR_BIT(hdac->Instance->AUTOCR, DAC_AUTOCR_AUTOMODE);
+
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdac);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DACEx_Private_Functions DACEx private functions
+ * @brief Extended private functions
+ * @{
+ */
+
+
+/**
+ * @brief DMA conversion complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ hdac->ConvCpltCallbackCh2(hdac);
+#else
+ HAL_DACEx_ConvCpltCallbackCh2(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
+ hdac->State = HAL_DAC_STATE_READY;
+}
+
+/**
+ * @brief DMA half transfer complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ /* Conversion complete callback */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ hdac->ConvHalfCpltCallbackCh2(hdac);
+#else
+ HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA error callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Set DAC error code to DMA error */
+ hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
+
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ hdac->ErrorCallbackCh2(hdac);
+#else
+ HAL_DACEx_ErrorCallbackCh2(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
+ hdac->State = HAL_DAC_STATE_READY;
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* DAC1 */
+
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dcache.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dcache.c
new file mode 100644
index 00000000..fae4473f
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dcache.c
@@ -0,0 +1,1429 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_dcache.c
+ * @author MCD Application Team
+ * @brief DCACHE HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the DCACHE.
+ * + Initialization and Configuration
+ * + Cache coherency command
+ * + Monitoring management
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ (#) Configure and enable the MPU to override default config if needed, please refers
+ to ARM manual for default memory attribute. Then enable DCache.
+
+ [..]
+ (+) Use HAL_DCACHE_Invalidate() to invalidate the full cache content:
+ (++) Cache content is lost, and reloaded when needed.
+ (++) Used for complete invalidate of the dcache in case.
+ (++) Blocking call until operation is done.
+ (+) Use HAL_DCACHE_InvalidateByAddr() to invalidate cache content for specific range:
+ (++) Cache content for specific range is lost, and reloaded when needed.
+ (++) Used when excepting a buffer to be updated by a peripheral (typically DMA transfer)
+ (++) Blocking call until operation is done.
+ (+) Use HAL_DCACHE_CleanByAddr() to clean cache content for a specific range:
+ (++) Cache content for specific range is written back to memory.
+ (++) Used when buffer is updated by CPU before usage by a peripheral (typically DMA transfer)
+ (++) Blocking call until operation is done.
+ (+) Use HAL_DCACHE_CleanInvalidateByAddr() to clean and invalidate cache content for a specific range:
+ (++) Cache content for specific range is written back to memory, and reloaded when needed.
+ (++) Used when sharing buffer between CPU and other peripheral.
+ (++) Recommended to use for MPU reprogramming.
+ (++) Blocking call until operation is done.
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Configure the DCACHE interrupt priority using HAL_NVIC_SetPriority()
+ (+) Enable the DCACHE IRQ handler using HAL_NVIC_EnableIRQ()
+ (+) Override weak definition for following callback (if needed):
+ (++)HAL_DCACHE_CleanAndInvalidateByAddrCallback()
+ (++)HAL_DCACHE_InvalidateCompleteCallback()
+ (++)HAL_DCACHE_InvalidateByAddrCallback()
+ (++)HAL_DCACHE_CleanByAddrCallback()
+ (++)HAL_DCACHE_ErrorCallback()
+ (+) Use HAL_DCACHE__IT() to start a DCache operation with IT enabled.
+ (+) Use HAL_DCACHE_IRQHandler() called under DCACHE_IRQHandler() Interrupt subroutine
+
+ [..] Use HAL_DCACHE_GetState() function to return the DCACHE state and HAL_DCACHE_GetError()
+ in case of error detection.
+
+ *** DCACHE HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in DCACHE HAL driver.
+
+ (+) __HAL_DCACHE_ENABLE_IT : Enable DCACHE interrupts.
+ (+) __HAL_DCACHE_DISABLE_IT : Disable DCACHE interrupts.
+ (+) __HAL_DCACHE_GET_IT_SOURCE: Check whether the specified DCACHE interrupt source is enabled or not.
+ (+) __HAL_DCACHE_GET_FLAG : Check whether the selected DCACHE flag is set or not.
+ (+) __HAL_DCACHE_CLEAR_FLAG : Clear the selected DCACHE flags.
+
+ [..]
+ (@) You can refer to the header file of the DCACHE HAL driver for more useful macros.
+
+ [..]
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup DCACHE DCACHE
+ * @brief HAL DCACHE module driver
+ * @{
+ */
+#ifdef HAL_DCACHE_MODULE_ENABLED
+
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup DCACHE_Private_Macros DCACHE Private Macros
+ * @{
+ */
+#define IS_DCACHE_REGION_SIZE(__SIZE__) ((__SIZE__) > 0U)
+
+#define IS_DCACHE_MONITOR_TYPE(__TYPE__) (((__TYPE__) & ~DCACHE_MONITOR_ALL) == 0U)
+
+#define IS_DCACHE_SINGLE_MONITOR_TYPE(__TYPE__) (((__TYPE__) == DCACHE_MONITOR_READ_HIT) || \
+ ((__TYPE__) == DCACHE_MONITOR_READ_MISS) || \
+ ((__TYPE__) == DCACHE_MONITOR_WRITE_HIT) || \
+ ((__TYPE__) == DCACHE_MONITOR_WRITE_MISS))
+
+#define IS_DCACHE_READ_BURST_TYPE(__OUTPUTBURSTTYPE__) (((__OUTPUTBURSTTYPE__) == DCACHE_READ_BURST_WRAP) || \
+ ((__OUTPUTBURSTTYPE__) == DCACHE_READ_BURST_INCR))
+
+/**
+ * @}
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup DCACHE_Private_Constants DCACHE Private Constants
+ * @{
+ */
+#define DCACHE_COMMAND_TIMEOUT_VALUE 200U /* 200ms*/
+#define DCACHE_DISABLE_TIMEOUT_VALUE 1U /* 1ms */
+
+#define DCACHE_COMMAND_INVALIDATE DCACHE_CR_CACHECMD_1
+#define DCACHE_COMMAND_CLEAN DCACHE_CR_CACHECMD_0
+#define DCACHE_COMMAND_CLEAN_INVALIDATE (DCACHE_CR_CACHECMD_0|DCACHE_CR_CACHECMD_1)
+
+#define DCACHE_POLLING_MODE 0U
+#define DCACHE_IT_MODE 1U
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static HAL_StatusTypeDef DCACHE_CommandByAddr(DCACHE_HandleTypeDef *hdcache, uint32_t Command,
+ const uint32_t *const pAddr, uint32_t dSize, uint32_t mode);
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DCACHE_Exported_Functions DCACHE Exported Functions
+ * @{
+ */
+
+/** @defgroup DCACHE_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ deinitialize the DCACHEx peripheral:
+
+ (+) User must implement HAL_DCACHE_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, MPU, IT and NVIC ).
+
+ (+) Call the function HAL_DCACHE_Init() to configure the selected device with
+ the selected configuration:
+ (++) ReadBurstType
+
+ (+) Call the function HAL_DCACHE_DeInit() to restore the reset configuration
+ of the selected DCACHEx peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the DCACHE according to the specified parameters
+ * in the DCACHE_InitTypeDef and initialize the associated handle.
+ * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
+ * the configuration information for the specified DCACHE.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCACHE_Init(DCACHE_HandleTypeDef *hdcache)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the DCACHE handle allocation */
+ if (hdcache == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
+ assert_param(IS_DCACHE_READ_BURST_TYPE(hdcache->Init.ReadBurstType));
+
+ if (hdcache->State == HAL_DCACHE_STATE_RESET)
+ {
+ /* Init the DCACHE Callback settings with legacy weak */
+ hdcache->ErrorCallback = HAL_DCACHE_ErrorCallback;
+ hdcache->CleanByAddrCallback = HAL_DCACHE_CleanByAddrCallback;
+ hdcache->InvalidateByAddrCallback = HAL_DCACHE_InvalidateByAddrCallback;
+ hdcache->InvalidateCompleteCallback = HAL_DCACHE_InvalidateCompleteCallback;
+ hdcache->CleanAndInvalidateByAddrCallback = HAL_DCACHE_CleanAndInvalidateByAddrCallback;
+
+ if (hdcache->MspInitCallback == NULL)
+ {
+ hdcache->MspInitCallback = HAL_DCACHE_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hdcache->MspInitCallback(hdcache);
+ }
+
+ hdcache->State = HAL_DCACHE_STATE_BUSY;
+
+ /* Disable the selected DCACHE peripheral */
+ if (HAL_DCACHE_Disable(hdcache) != HAL_OK)
+ {
+ /* Return timeout status */
+ status = HAL_TIMEOUT;
+ }
+ else
+ {
+ /* Set requested read burst type */
+ MODIFY_REG(hdcache->Instance->CR, DCACHE_CR_HBURST, hdcache->Init.ReadBurstType);
+
+ /* Enable the selected DCACHE peripheral */
+ if (HAL_DCACHE_Enable(hdcache) != HAL_OK)
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ }
+ hdcache->State = HAL_DCACHE_STATE_READY;
+
+ return status;
+}
+
+/**
+ * @brief DeInitialize the Data cache.
+ * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
+ * the configuration information for the specified DCACHEx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCACHE_DeInit(DCACHE_HandleTypeDef *hdcache)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the dcache handle allocation */
+ if (hdcache == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
+
+ /* Before the lunch of the disable operation check first whether or not DCACHE clock is enabled */
+ if (hdcache->State != HAL_DCACHE_STATE_RESET)
+ {
+ /* Disable cache with reset value */
+ if (HAL_DCACHE_Disable(hdcache) != HAL_OK)
+ {
+ /* Update error code */
+ hdcache->ErrorCode = HAL_DCACHE_ERROR_TIMEOUT;
+
+ /* Change the DCACHE state */
+ hdcache->State = HAL_DCACHE_STATE_ERROR;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* reset monitor values */
+ (void)HAL_DCACHE_Monitor_Reset(hdcache, DCACHE_MONITOR_ALL);
+
+ /* Reset all remaining bit */
+ WRITE_REG(hdcache->Instance->CR, 0U);
+ WRITE_REG(hdcache->Instance->CMDRSADDRR, 0U);
+ WRITE_REG(hdcache->Instance->CMDREADDRR, 0U);
+ WRITE_REG(hdcache->Instance->FCR, DCACHE_FCR_CCMDENDF | DCACHE_FCR_CERRF | DCACHE_FCR_CBSYENDF);
+
+ if (hdcache->MspDeInitCallback == NULL)
+ {
+ hdcache->MspDeInitCallback = HAL_DCACHE_MspDeInit;
+ }
+
+ /* DeInit the low level hardware */
+ hdcache->MspDeInitCallback(hdcache);
+
+ /* Return to the reset state */
+ hdcache->State = HAL_DCACHE_STATE_RESET;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initialize the DCACHE MSP.
+ * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
+ * the configuration information for the specified DCACHEx peripheral.
+ * @retval None
+ */
+__weak void HAL_DCACHE_MspInit(DCACHE_HandleTypeDef *hdcache)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdcache);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_DCACHE_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the DCACHE MSP.
+ * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
+ * the configuration information for the specified DCACHEx peripheral.
+ * @retval None
+ */
+__weak void HAL_DCACHE_MspDeInit(DCACHE_HandleTypeDef *hdcache)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdcache);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_DCACHE_MspDeInit can be implemented in the user file
+ */
+}
+
+/** @defgroup DCACHE_Exported_Functions_Group2 IO operation functions
+ * @brief IO operation functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Enable the Data cache.
+ (+) Disable the Data cache.
+ (+) Set Read Burst Type.
+ (+) Invalidate the Data cache.
+ (+) Invalidate the Data cache with interrupt.
+ (+) Clean the Data cache by Addr.
+ (+) Invalidate the Data cache by Addr.
+ (+) Clean and Invalidate the Data cache by Addr.
+ (+) Clean the Data cache by Addr with interrupt.
+ (+) Invalidate the Data cache by Addr with interrupt.
+ (+) Clean and Invalidate the Data cache by Addr with interrupt.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable the Data cache.
+ * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
+ * the configuration information for the specified DCACHEx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCACHE_Enable(DCACHE_HandleTypeDef *hdcache)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the dcache handle allocation */
+ if (hdcache == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
+
+ /* Check no ongoing operation */
+ if (READ_BIT(hdcache->Instance->SR, (DCACHE_SR_BUSYF | DCACHE_SR_BUSYCMDF)) != 0U)
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ SET_BIT(hdcache->Instance->CR, DCACHE_CR_EN);
+ }
+
+ hdcache->State = HAL_DCACHE_STATE_READY;
+
+ return status;
+}
+
+/**
+ * @brief Disable the Data cache.
+ * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
+ * the configuration information for the specified DCACHEx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCACHE_Disable(DCACHE_HandleTypeDef *hdcache)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ uint32_t tickstart;
+
+ /* Check the parameters */
+ assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
+
+ /* Change DCACHE state */
+ hdcache->State = HAL_DCACHE_STATE_BUSY;
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Before disable check first whether or not DCACHE clock is enabled */
+ if (hdcache->State != HAL_DCACHE_STATE_RESET)
+ {
+ CLEAR_BIT(hdcache->Instance->CR, DCACHE_CR_EN);
+
+ /* Wait for end of data cache disabling */
+ while (READ_BIT(hdcache->Instance->SR, (DCACHE_SR_BUSYF | DCACHE_SR_BUSYCMDF)) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > DCACHE_DISABLE_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hdcache->ErrorCode = HAL_DCACHE_ERROR_TIMEOUT;
+
+ /* Change the DCACHE state */
+ hdcache->State = HAL_DCACHE_STATE_ERROR;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ }
+
+ hdcache->State = HAL_DCACHE_STATE_RESET;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Set Read Burst Type.
+ * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
+ * the configuration information for the specified DCACHEx peripheral.
+ * @param ReadBurstType Burst type to be applied for Data Cache
+ * DCACHE_READ_BURST_WRAP, DCACHE_READ_BURST_INC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCACHE_SetReadBurstType(DCACHE_HandleTypeDef *hdcache, uint32_t ReadBurstType)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the dcache handle allocation */
+ if (hdcache == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
+ assert_param(IS_DCACHE_READ_BURST_TYPE(ReadBurstType));
+
+ /* check DCACHE state */
+ if (hdcache->State == HAL_DCACHE_STATE_RESET)
+ {
+ /* Set requested read burst type */
+ if (ReadBurstType == DCACHE_READ_BURST_WRAP)
+ {
+ CLEAR_BIT(hdcache->Instance->CR, DCACHE_CR_HBURST);
+ }
+ else
+ {
+ SET_BIT(hdcache->Instance->CR, DCACHE_CR_HBURST);
+ }
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Invalidate the Data cache.
+ * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
+ * the configuration information for the specified DCACHEx peripheral.
+ * @note This function waits for end of full cache invalidation
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCACHE_Invalidate(DCACHE_HandleTypeDef *hdcache)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tickstart;
+
+ /* Check the dcache handle allocation */
+ if (hdcache == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
+
+ /* Check no ongoing operation */
+ if (READ_BIT(hdcache->Instance->SR, (DCACHE_SR_BUSYF | DCACHE_SR_BUSYCMDF)) != 0U)
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Make sure flags are reset */
+ WRITE_REG(hdcache->Instance->FCR, (DCACHE_FCR_CBSYENDF | DCACHE_FCR_CCMDENDF));
+
+ /* Set no operation on address range */
+ MODIFY_REG(hdcache->Instance->CR, DCACHE_CR_CACHECMD, 0U);
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Launch cache invalidation */
+ SET_BIT(hdcache->Instance->CR, DCACHE_CR_CACHEINV);
+
+ /* Wait for end of cache invalidation */
+ while (READ_BIT(hdcache->Instance->SR, DCACHE_FCR_CBSYENDF) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > DCACHE_COMMAND_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Invalidate the Data cache for a specific region.
+ * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
+ * the configuration information for the specified DCACHEx peripheral.
+ * @param pAddr Start address of the region to be Invalidated
+ * @param dSize Size of the region to be Invalidated(in bytes)
+ * @note This function waits for end of cache Invalidation
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCACHE_InvalidateByAddr(DCACHE_HandleTypeDef *hdcache, const uint32_t *const pAddr,
+ uint32_t dSize)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check the dcache handle allocation */
+ if (hdcache == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
+ assert_param(IS_DCACHE_REGION_SIZE(dSize));
+
+ status = DCACHE_CommandByAddr(hdcache, DCACHE_COMMAND_INVALIDATE, pAddr, dSize, DCACHE_POLLING_MODE);
+
+ return status;
+}
+
+/**
+ * @brief Clean the Data cache by Addr.
+ * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
+ * the configuration information for the specified DCACHEx peripheral.
+ * @param pAddr Start address of the region to be Cleaned
+ * @param dSize Size of the region to be Cleaned (in bytes)
+ * @note This function waits for end of cache Clean
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCACHE_CleanByAddr(DCACHE_HandleTypeDef *hdcache, const uint32_t *const pAddr, uint32_t dSize)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check the dcache handle allocation */
+ if (hdcache == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
+ assert_param(IS_DCACHE_REGION_SIZE(dSize));
+
+ status = DCACHE_CommandByAddr(hdcache, DCACHE_COMMAND_CLEAN, pAddr, dSize, DCACHE_POLLING_MODE);
+
+ return status;
+}
+
+/**
+ * @brief Clean and Invalidate the Data cache by Addr.
+ * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
+ * the configuration information for the specified DCACHEx peripheral.
+ * @param pAddr Start address of the region to be Cleaned and Invalidated
+ * @param dSize Size of the region to be Cleaned and Invalidated (in bytes)
+ * @note This function waits for end of cache Clean and Invalidation
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCACHE_CleanInvalidByAddr(DCACHE_HandleTypeDef *hdcache, const uint32_t *const pAddr,
+ uint32_t dSize)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check the dcache handle allocation */
+ if (hdcache == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
+ assert_param(IS_DCACHE_REGION_SIZE(dSize));
+
+ status = DCACHE_CommandByAddr(hdcache, DCACHE_COMMAND_CLEAN_INVALIDATE, pAddr, dSize, DCACHE_POLLING_MODE);
+
+ return status;
+}
+
+/**
+ * @brief Invalidate the Data cache with interrupt.
+ * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
+ * the configuration information for the specified DCACHEx peripheral.
+ * @note This function launches maintenance operation and returns immediately.
+ * User application shall resort to interrupt generation to check
+ * the end of operation.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCACHE_Invalidate_IT(DCACHE_HandleTypeDef *hdcache)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the dcache handle allocation */
+ if (hdcache == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
+
+ /* Check no ongoing operation */
+ if (READ_BIT(hdcache->Instance->SR, (DCACHE_SR_BUSYF | DCACHE_SR_BUSYCMDF)) != 0U)
+ {
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Make sure BSYENDF is reset */
+ WRITE_REG(hdcache->Instance->FCR, (DCACHE_FCR_CBSYENDF | DCACHE_FCR_CCMDENDF));
+
+ /* Set no operation on address range for callback under interrupt */
+ MODIFY_REG(hdcache->Instance->CR, DCACHE_CR_CACHECMD, 0U);
+
+ /* Enable end of cache invalidation interrupt */
+ SET_BIT(hdcache->Instance->IER, DCACHE_IER_BSYENDIE);
+
+ /* Launch cache invalidation */
+ SET_BIT(hdcache->Instance->CR, DCACHE_CR_CACHEINV);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Invalidate the Data cache by Addr with interrupt.
+ * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
+ * the configuration information for the specified DCACHEx peripheral.
+ * @param pAddr Start address of the region to be Invalidated
+ * @param dSize Size of the region to be Invalidated
+ * @note This function launches maintenance operation and returns immediately.
+ * User application shall resort to interrupt generation to check
+ * the end of operation.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCACHE_InvalidateByAddr_IT(DCACHE_HandleTypeDef *hdcache, const uint32_t *const pAddr,
+ uint32_t dSize)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check the dcache handle allocation */
+ if (hdcache == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
+ assert_param(IS_DCACHE_REGION_SIZE(dSize));
+
+ status = DCACHE_CommandByAddr(hdcache, DCACHE_COMMAND_INVALIDATE, pAddr, dSize, DCACHE_IT_MODE);
+
+ return status;
+}
+
+/**
+ * @brief Clean the Data cache by Addr with interrupt.
+ * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
+ * the configuration information for the specified DCACHEx peripheral.
+ * @param pAddr Start address of the region to be Cleaned
+ * @param dSize Size of the region to be Cleaned
+ * @note This function launches maintenance operation and returns immediately.
+ * User application shall resort to interrupt generation to check
+ * the end of operation.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCACHE_CleanByAddr_IT(DCACHE_HandleTypeDef *hdcache, const uint32_t *const pAddr,
+ uint32_t dSize)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check the dcache handle allocation */
+ if (hdcache == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
+ assert_param(IS_DCACHE_REGION_SIZE(dSize));
+
+ status = DCACHE_CommandByAddr(hdcache, DCACHE_COMMAND_CLEAN, pAddr, dSize, DCACHE_IT_MODE);
+
+ return status;
+}
+
+/**
+ * @brief Clean and Invalidate the Data cache by Addr with interrupt.
+ * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
+ * the configuration information for the specified DCACHEx peripheral.
+ * @param pAddr Start address of the region to be Cleaned and Invalidated
+ * @param dSize Size of the region to be Cleaned and Invalidated
+ * @note This function launches maintenance operation and returns immediately.
+ * User application shall resort to interrupt generation to check
+ * the end of operation.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCACHE_CleanInvalidByAddr_IT(DCACHE_HandleTypeDef *hdcache, const uint32_t *const pAddr,
+ uint32_t dSize)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check the dcache handle allocation */
+ if (hdcache == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
+ assert_param(IS_DCACHE_REGION_SIZE(dSize));
+
+ status = DCACHE_CommandByAddr(hdcache, DCACHE_COMMAND_CLEAN_INVALIDATE, pAddr, dSize, DCACHE_IT_MODE);
+
+ return status;
+}
+
+/**
+ * @brief Handle the Data Cache interrupt request.
+ * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
+ * the configuration information for the specified DCACHEx peripheral.
+ * @note This API should be called under the DCACHE_IRQHandler().
+ * @retval None
+ */
+void HAL_DCACHE_IRQHandler(DCACHE_HandleTypeDef *hdcache)
+{
+ /* Get current interrupt flags and interrupt sources value */
+ uint32_t itflags = READ_REG(hdcache->Instance->SR);
+ uint32_t itsources = READ_REG(hdcache->Instance->IER);
+
+ /* Check the parameters */
+ assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
+
+ /* Check Data cache Error interrupt flag */
+ if (((itflags & itsources) & DCACHE_FLAG_ERROR) != 0U)
+ {
+ /* Clear DCACHE error pending flag */
+ __HAL_DCACHE_CLEAR_FLAG(hdcache, DCACHE_FLAG_ERROR);
+
+ /* Data cache error interrupt user callback */
+ hdcache->ErrorCallback(hdcache);
+ }
+
+ if (READ_BIT(hdcache->Instance->CR, DCACHE_CR_CACHECMD) == 0U) /* no operation by range */
+ {
+ /* Clear DCACHE busyend pending flag */
+ __HAL_DCACHE_CLEAR_FLAG(hdcache, DCACHE_FLAG_BUSYEND);
+
+ /* Data cache invalidate complete interrupt user callback */
+ hdcache->InvalidateCompleteCallback(hdcache);
+ }
+ else if (READ_BIT(hdcache->Instance->CR, DCACHE_CR_CACHECMD_1 | DCACHE_CR_CACHECMD_0) == \
+ (DCACHE_CR_CACHECMD_1 | DCACHE_CR_CACHECMD_0))
+ {
+ /* Clear DCACHE cmdend pending flag */
+ __HAL_DCACHE_CLEAR_FLAG(hdcache, DCACHE_FLAG_CMDEND);
+
+ /* Data cache clean and invalidate range cmdend interrupt user callback */
+ hdcache->CleanAndInvalidateByAddrCallback(hdcache);
+ }
+ else if (READ_BIT(hdcache->Instance->CR, DCACHE_CR_CACHECMD_0) == DCACHE_CR_CACHECMD_0)
+ {
+ /* Clear DCACHE cmdend pending flag */
+ __HAL_DCACHE_CLEAR_FLAG(hdcache, DCACHE_FLAG_CMDEND);
+
+ /* Data cache clean range cmdend interrupt user callback */
+ hdcache->CleanByAddrCallback(hdcache);
+ }
+ else
+ {
+ /* Clear DCACHE cmdend pending flag */
+ __HAL_DCACHE_CLEAR_FLAG(hdcache, DCACHE_FLAG_CMDEND);
+
+ /* Data cache Invalidate range cmdend interrupt user callback */
+ hdcache->InvalidateByAddrCallback(hdcache);
+ }
+
+}
+
+/**
+ * @brief Cache clean command by address callback.
+ * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
+ * the configuration information for the specified DCACHEx peripheral.
+ * @retval None
+ */
+__weak void HAL_DCACHE_CleanByAddrCallback(DCACHE_HandleTypeDef *hdcache)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdcache);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_DCACHE_CleanByAddrCallback() should be implemented in the user file
+ */
+}
+
+/**
+ * @brief Cache Invalidate command by address callback.
+ * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
+ * the configuration information for the specified DCACHEx peripheral.
+ * @retval None
+ */
+__weak void HAL_DCACHE_InvalidateByAddrCallback(DCACHE_HandleTypeDef *hdcache)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdcache);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_DCACHE_InvalidateByAddrCallback() should be implemented in the user file
+ */
+}
+
+/**
+ * @brief Cache clean and Invalidate command by address callback.
+ * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
+ * the configuration information for the specified DCACHEx peripheral.
+ * @retval None
+ */
+__weak void HAL_DCACHE_CleanAndInvalidateByAddrCallback(DCACHE_HandleTypeDef *hdcache)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdcache);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_DCACHE_CleanAndInvalidateByAddrCallback() should be implemented in the user file
+ */
+}
+
+/**
+ * @brief Cache full invalidation complete callback.
+ * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
+ * the configuration information for the specified DCACHEx peripheral.
+ * @retval None
+ */
+__weak void HAL_DCACHE_InvalidateCompleteCallback(DCACHE_HandleTypeDef *hdcache)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdcache);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_DCACHE_InvalidateCompleteCallback() should be implemented in the user file
+ */
+}
+
+/**
+ * @brief Error callback.
+ * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
+ * the configuration information for the specified DCACHEx peripheral.
+ * @retval None
+ */
+__weak void HAL_DCACHE_ErrorCallback(DCACHE_HandleTypeDef *hdcache)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdcache);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_DCACHE_ErrorCallback() should be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DCACHE_Exported_Functions_Group3 Peripheral State,
+ * @brief Peripheral State,
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State #####
+ ===============================================================================
+ [..]
+ This subsection permit to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the DCACHE handle state.
+ * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
+ * the configuration information for the specified DCACHEx peripheral.
+ * @retval HAL state
+ */
+HAL_DCACHE_StateTypeDef HAL_DCACHE_GetState(DCACHE_HandleTypeDef *hdcache)
+{
+ /* Return DCACHE handle state */
+ return hdcache->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @brief Return the DCACHE error code
+ * @param hdcache pointer to a DCACHE_HandleTypeDef structure that contains
+ * the configuration information for the specified DCACHE.
+ * @retval DCACHE Error Code
+ */
+uint32_t HAL_DCACHE_GetError(DCACHE_HandleTypeDef *hdcache)
+{
+ return hdcache->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DCACHE_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DCACHE_Exported_Functions_Group1
+ * @{
+ */
+
+/**
+ * @brief Register a User DCACHE Callback
+ * To be used instead of the weak predefined callback
+ * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
+ * the configuration information for the specified DCACHEx peripheral.
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_DCACHE_CLEAN_BY_ADDRESS_CB_ID Clean By Addr callback ID
+ * @arg @ref HAL_DCACHE_INVALIDATE_BY_ADDRESS_CB_ID Invalidate By Addr callback ID
+ * @arg @ref HAL_DCACHE_CLEAN_AND_INVALIDATE_BY_ADDRESS_CB_ID Clean and Invalidate By Addr callback ID
+ * @arg @ref HAL_DCACHE_INVALIDATE_COMPLETE_CB_ID Invalidate Complete ID
+ * @arg @ref HAL_DCACHE_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_DCACHE_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_DCACHE_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCACHE_RegisterCallback(DCACHE_HandleTypeDef *hdcache, HAL_DCACHE_CallbackIDTypeDef CallbackID,
+ pDCACHE_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hdcache->ErrorCode |= HAL_DCACHE_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ if (HAL_DCACHE_STATE_READY == hdcache->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DCACHE_CLEAN_BY_ADDRESS_CB_ID :
+ hdcache->CleanByAddrCallback = pCallback;
+ break;
+
+ case HAL_DCACHE_INVALIDATE_BY_ADDRESS_CB_ID :
+ hdcache->InvalidateByAddrCallback = pCallback;
+ break;
+
+ case HAL_DCACHE_CLEAN_AND_INVALIDATE_BY_ADDRESS_CB_ID :
+ hdcache->CleanAndInvalidateByAddrCallback = pCallback;
+ break;
+
+ case HAL_DCACHE_INVALIDATE_COMPLETE_CB_ID :
+ hdcache->InvalidateCompleteCallback = pCallback;
+ break;
+
+ case HAL_DCACHE_ERROR_CB_ID :
+ hdcache->ErrorCallback = pCallback;
+ break;
+
+ case HAL_DCACHE_MSPINIT_CB_ID :
+ hdcache->MspInitCallback = pCallback;
+ break;
+
+ case HAL_DCACHE_MSPDEINIT_CB_ID :
+ hdcache->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hdcache->ErrorCode |= HAL_DCACHE_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_DCACHE_STATE_RESET == hdcache->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DCACHE_MSPINIT_CB_ID :
+ hdcache->MspInitCallback = pCallback;
+ break;
+
+ case HAL_DCACHE_MSPDEINIT_CB_ID :
+ hdcache->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hdcache->ErrorCode |= HAL_DCACHE_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hdcache->ErrorCode |= HAL_DCACHE_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Unregister an DCACHE Callback
+ * DCACHE callback is redirected to the weak predefined callback
+ * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
+ * the configuration information for the specified DCACHEx peripheral.
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_DCACHE_CLEAN_BY_ADDRESS_CB_ID Clean By Addr callback ID
+ * @arg @ref HAL_DCACHE_INVALIDATE_BY_ADDRESS_CB_ID Invalidate By Addr callback ID
+ * @arg @ref HAL_DCACHE_CLEAN_AND_INVALIDATE_BY_ADDRESS_CB_ID Clean and Invalidate By Addr callback ID
+ * @arg @ref HAL_DCACHE_INVALIDATE_COMPLETE_CB_ID Invalidate Complete callback ID
+ * @arg @ref HAL_DCACHE_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_DCACHE_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_DCACHE_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCACHE_UnRegisterCallback(DCACHE_HandleTypeDef *hdcache, HAL_DCACHE_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (HAL_DCACHE_STATE_READY == hdcache->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DCACHE_CLEAN_BY_ADDRESS_CB_ID :
+ /* Legacy weak Clean By Addr Callback */
+ hdcache->CleanByAddrCallback = HAL_DCACHE_CleanByAddrCallback;
+ break;
+
+ case HAL_DCACHE_INVALIDATE_BY_ADDRESS_CB_ID :
+ /* Legacy weak Invalidate By Addr Callback */
+ hdcache->InvalidateByAddrCallback = HAL_DCACHE_InvalidateByAddrCallback;
+ break;
+
+ case HAL_DCACHE_CLEAN_AND_INVALIDATE_BY_ADDRESS_CB_ID :
+ /* Legacy weak Clean and Invalidate By Addr Callback */
+ hdcache->InvalidateByAddrCallback = HAL_DCACHE_CleanAndInvalidateByAddrCallback;
+ break;
+
+ case HAL_DCACHE_INVALIDATE_COMPLETE_CB_ID :
+ /* Legacy weak Invalidate Complete Callback */
+ hdcache->InvalidateCompleteCallback = HAL_DCACHE_InvalidateCompleteCallback;
+ break;
+
+ case HAL_DCACHE_ERROR_CB_ID :
+ /* Legacy weak ErrorCallback */
+ hdcache->ErrorCallback = HAL_DCACHE_ErrorCallback;
+ break;
+
+ case HAL_DCACHE_MSPINIT_CB_ID :
+ /* Legacy weak MspInit */
+ hdcache->MspInitCallback = HAL_DCACHE_MspInit;
+ break;
+
+ case HAL_DCACHE_MSPDEINIT_CB_ID :
+ /* Legacy weak MspDeInit */
+ hdcache->MspDeInitCallback = HAL_DCACHE_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hdcache->ErrorCode |= HAL_DCACHE_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_DCACHE_STATE_RESET == hdcache->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DCACHE_MSPINIT_CB_ID :
+ /* Legacy weak MspInit */
+ hdcache->MspInitCallback = HAL_DCACHE_MspInit;
+ break;
+
+ case HAL_DCACHE_MSPDEINIT_CB_ID :
+ /* Legacy weak MspDeInit */
+ hdcache->MspDeInitCallback = HAL_DCACHE_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hdcache->ErrorCode |= HAL_DCACHE_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hdcache->ErrorCode |= HAL_DCACHE_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Start the Data Cache performance monitoring.
+ * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
+ * the configuration information for the specified DCACHEx peripheral.
+ * @param MonitorType Monitoring type
+ * This parameter can be a combination of the following values:
+ * @arg DCACHE_MONITOR_READ_HIT
+ * @arg DCACHE_MONITOR_READ_MISS
+ * @arg DCACHE_MONITOR_WRITE_HIT
+ * @arg DCACHE_MONITOR_WRITE_MISS
+ * @arg DCACHE_MONITOR_ALL
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCACHE_Monitor_Start(DCACHE_HandleTypeDef *hdcache, uint32_t MonitorType)
+{
+ /* Check the dcache handle allocation */
+ if (hdcache == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
+ assert_param(IS_DCACHE_MONITOR_TYPE(MonitorType));
+
+ SET_BIT(hdcache->Instance->CR, MonitorType);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the Data Cache performance monitoring.
+ * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
+ * the configuration information for the specified DCACHEx peripheral.
+ * @note Stopping the monitoring does not reset the values.
+ * @param MonitorType Monitoring type
+ * This parameter can be a combination of the following values:
+ * @arg DCACHE_MONITOR_READ_HIT
+ * @arg DCACHE_MONITOR_READ_MISS
+ * @arg DCACHE_MONITOR_WRITE_HIT
+ * @arg DCACHE_MONITOR_WRITE_MISS
+ * @arg DCACHE_MONITOR_ALL
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCACHE_Monitor_Stop(DCACHE_HandleTypeDef *hdcache, uint32_t MonitorType)
+{
+ /* Check the dcache handle allocation */
+ if (hdcache == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
+ assert_param(IS_DCACHE_MONITOR_TYPE(MonitorType));
+
+ CLEAR_BIT(hdcache->Instance->CR, MonitorType);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Reset the Data Cache performance monitoring values.
+ * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
+ * the configuration information for the specified DCACHEx peripheral.
+ * @param MonitorType Monitoring type
+ * This parameter can be a combination of the following values:
+ * @arg DCACHE_MONITOR_READ_HIT
+ * @arg DCACHE_MONITOR_READ_MISS
+ * @arg DCACHE_MONITOR_WRITE_HIT
+ * @arg DCACHE_MONITOR_WRITE_MISS
+ * @arg DCACHE_MONITOR_ALL
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCACHE_Monitor_Reset(DCACHE_HandleTypeDef *hdcache, uint32_t MonitorType)
+{
+ /* Check the dcache handle allocation */
+ if (hdcache == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
+ assert_param(IS_DCACHE_MONITOR_TYPE(MonitorType));
+
+ /* Force/Release reset */
+ SET_BIT(hdcache->Instance->CR, (MonitorType << 2U));
+ CLEAR_BIT(hdcache->Instance->CR, (MonitorType << 2U));
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get the Data Cache performance Read Hit monitoring value.
+ * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
+ * the configuration information for the specified DCACHEx peripheral.
+ * @note Upon reaching the maximum value, monitor does not wrap.
+ * @retval Read Hit monitoring value
+ */
+uint32_t HAL_DCACHE_Monitor_GetReadHitValue(DCACHE_HandleTypeDef *hdcache)
+{
+ /* Check the parameters */
+ assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
+
+ /*return the Read Hit monitor value*/
+ return hdcache->Instance->RHMONR;
+}
+
+/**
+ * @brief Get the Data Cache performance Read Miss monitoring value.
+ * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
+ * the configuration information for the specified DCACHEx peripheral.
+ * @note Upon reaching the maximum value, monitor does not wrap.
+ * @retval Read Miss monitoring value
+ */
+uint32_t HAL_DCACHE_Monitor_GetReadMissValue(DCACHE_HandleTypeDef *hdcache)
+{
+ /* Check the parameters */
+ assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
+
+ /*return the Read Miss monitor value*/
+ return hdcache->Instance->RMMONR;
+}
+
+/**
+ * @brief Get the Data Cache performance Write Hit monitoring value.
+ * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
+ * the configuration information for the specified DCACHEx peripheral.
+ * @note Upon reaching the maximum value, monitor does not wrap.
+ * @retval Write Hit monitoring value
+ */
+uint32_t HAL_DCACHE_Monitor_GetWriteHitValue(DCACHE_HandleTypeDef *hdcache)
+{
+ /* Check the parameters */
+ assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
+
+ /*return the Write Hit monitor value*/
+ return hdcache->Instance->WHMONR;
+}
+
+/**
+ * @brief Get the Data Cache performance Write Miss monitoring value.
+ * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
+ * the configuration information for the specified DCACHEx peripheral.
+ * @note Upon reaching the maximum value, monitor does not wrap.
+ * @retval Write Miss monitoring value
+ */
+uint32_t HAL_DCACHE_Monitor_GetWriteMissValue(DCACHE_HandleTypeDef *hdcache)
+{
+ /* Check the parameters */
+ assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
+
+ /*return the Write Miss monitor value*/
+ return hdcache->Instance->WMMONR;
+}
+/**
+ * @}
+ */
+
+/**
+ * @brief launch dcache command Clean, Invalidate or clean and invalidate by Addr.
+ * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
+ * the configuration information for the specified DCACHEx peripheral.
+ * @param Command command to be applied for the dcache
+ * DCACHE_COMMAND_INVALIDATE, DCACHE_COMMAND_CLEAN, DCACHE_COMMAND_CLEAN_INVALIDATE
+ * @param pAddr Start address of region to be Cleaned, Invalidated or Cleaned and Invalidated.
+ * @param dSize Size of the region to be Cleaned, Invalidated or Cleaned and Invalidated (in bytes).
+ * @param mode mode to be applied for the dcache
+ * DCACHE_IT_MODE, DCACHE_POLLING_MODE.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef DCACHE_CommandByAddr(DCACHE_HandleTypeDef *hdcache, uint32_t Command,
+ const uint32_t *const pAddr, uint32_t dSize, uint32_t mode)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t op_addr = (uint32_t)pAddr;
+ uint32_t tickstart;
+
+ /* Set HAL_DCACHE_STATE_BUSY */
+ hdcache->State = HAL_DCACHE_STATE_BUSY;
+
+ /* Check no ongoing operation */
+ if (READ_BIT(hdcache->Instance->SR, (DCACHE_SR_BUSYF | DCACHE_SR_BUSYCMDF)) != 0U)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Make sure flags are reset */
+ WRITE_REG(hdcache->Instance->FCR, (DCACHE_FCR_CBSYENDF | DCACHE_FCR_CCMDENDF));
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Fill area start address */
+ WRITE_REG(hdcache->Instance->CMDRSADDRR, op_addr);
+
+ /* Fill area end address */
+ WRITE_REG(hdcache->Instance->CMDREADDRR, (op_addr + dSize - 1U));
+
+ /* Set command */
+ MODIFY_REG(hdcache->Instance->CR, DCACHE_CR_CACHECMD, Command);
+
+ /* Enable IT if required */
+ if (mode == DCACHE_IT_MODE)
+ {
+ /* Enable end of cache command interrupt */
+ SET_BIT(hdcache->Instance->IER, DCACHE_IER_CMDENDIE);
+
+ /* Launch cache command */
+ SET_BIT(hdcache->Instance->CR, DCACHE_CR_STARTCMD);
+ }
+ else
+ {
+
+ /* Make sure that end of cache command interrupt is disabled */
+ CLEAR_BIT(hdcache->Instance->IER, DCACHE_IER_CMDENDIE);
+
+ /* Launch cache command */
+ SET_BIT(hdcache->Instance->CR, DCACHE_CR_STARTCMD);
+
+ /* Wait for end of cache command */
+ while (READ_BIT(hdcache->Instance->SR, DCACHE_SR_CMDENDF) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > DCACHE_COMMAND_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hdcache->ErrorCode = HAL_DCACHE_ERROR_TIMEOUT;
+
+ /* Change the DCACHE state */
+ hdcache->State = HAL_DCACHE_STATE_ERROR;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ }
+ }
+ }
+
+ /* Set HAL_DCACHE_STATE_READY */
+ hdcache->State = HAL_DCACHE_STATE_READY;
+
+ return status;
+}
+
+
+#endif /* HAL_DCACHE_MODULE_ENABLED */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dcmi.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dcmi.c
new file mode 100644
index 00000000..cc8e295c
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dcmi.c
@@ -0,0 +1,1374 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_dcmi.c
+ * @author MCD Application Team
+ * @brief DCMI HAL module driver
+ * This file provides firmware functions to manage the following
+ * functionalities of the Digital Camera Interface (DCMI) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State and Error functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The sequence below describes how to use this driver to capture image
+ from a camera module connected to the DCMI Interface.
+ This sequence does not take into account the configuration of the
+ camera module, which should be made before to configure and enable
+ the DCMI to capture images.
+
+ (#) Program the required configuration through following parameters:
+ horizontal and vertical polarity, pixel clock polarity, Capture Rate,
+ Synchronization Mode, code of the frame delimiter and data width
+ using HAL_DCMI_Init() function.
+
+ (#) Configure the selected DMA stream to transfer Data from DCMI DR
+ register to the destination memory buffer.
+
+ (#) Program the required configuration through following parameters:
+ DCMI mode, destination memory Buffer address and the data length
+ and enable capture using HAL_DCMI_Start_DMA() function.
+
+ (#) Optionally, configure and Enable the CROP feature to select a rectangular
+ window from the received image using HAL_DCMI_ConfigCrop()
+ and HAL_DCMI_EnableCrop() functions
+
+ (#) The capture can be stopped using HAL_DCMI_Stop() function.
+
+ (#) To control DCMI state you can use the function HAL_DCMI_GetState().
+
+ *** DCMI HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in DCMI HAL driver.
+
+ (+) __HAL_DCMI_ENABLE: Enable the DCMI peripheral.
+ (+) __HAL_DCMI_DISABLE: Disable the DCMI peripheral.
+ (+) __HAL_DCMI_GET_FLAG: Get the DCMI pending flags.
+ (+) __HAL_DCMI_CLEAR_FLAG: Clear the DCMI pending flags.
+ (+) __HAL_DCMI_ENABLE_IT: Enable the specified DCMI interrupts.
+ (+) __HAL_DCMI_DISABLE_IT: Disable the specified DCMI interrupts.
+ (+) __HAL_DCMI_GET_IT_SOURCE: Check whether the specified DCMI interrupt has occurred or not.
+
+ [..]
+ (@) You can refer to the DCMI HAL driver header file for more useful macros
+
+ *** Callback registration ***
+ =============================
+
+ The compilation define USE_HAL_DCMI_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use functions @ref HAL_DCMI_RegisterCallback() to register a user callback.
+
+ Function @ref HAL_DCMI_RegisterCallback() allows to register following callbacks:
+ (+) FrameEventCallback : callback for DCMI Frame Event.
+ (+) VsyncEventCallback : callback for DCMI Vsync Event.
+ (+) LineEventCallback : callback for DCMI Line Event.
+ (+) ErrorCallback : callback for DCMI error detection.
+ (+) MspInitCallback : callback for DCMI MspInit.
+ (+) MspDeInitCallback : callback for DCMI MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_DCMI_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function.
+ @ref HAL_DCMI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the callback ID.
+ This function allows to reset following callbacks:
+ (+) FrameEventCallback : callback for DCMI Frame Event.
+ (+) VsyncEventCallback : callback for DCMI Vsync Event.
+ (+) LineEventCallback : callback for DCMI Line Event.
+ (+) ErrorCallback : callback for DCMI error.
+ (+) MspInitCallback : callback for DCMI MspInit.
+ (+) MspDeInitCallback : callback for DCMI MspDeInit.
+
+ By default, after the @ref HAL_DCMI_Init and if the state is HAL_DCMI_STATE_RESET
+ all callbacks are reset to the corresponding legacy weak (surcharged) functions:
+ examples @ref FrameEventCallback(), @ref HAL_DCMI_ErrorCallback().
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_DCMI_Init
+ and @ref HAL_DCMI_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_DCMI_Init and @ref HAL_DCMI_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_DCMI_RegisterCallback before calling @ref HAL_DCMI_DeInit
+ or @ref HAL_DCMI_Init function.
+
+ When the compilation define USE_HAL_DCMI_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+#ifdef HAL_DCMI_MODULE_ENABLED
+#if defined (DCMI)
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+/** @defgroup DCMI DCMI
+ * @brief DCMI HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup DCMI_Private_Constants DCMI Private Constants
+ * @{
+ */
+
+/** @defgroup DCMI_Stop_TimeOut DCMI Stop Time Out
+ * @{
+ */
+#define HAL_TIMEOUT_DCMI_STOP ((uint32_t)1000) /* Set timeout to 1s */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup DCMI_Private_Functions DCMI Private Functions
+ * @{
+ */
+static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma);
+static void DCMI_DMAError(DMA_HandleTypeDef *hdma);
+
+/**
+ * @}
+ */
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup DCMI_Exported_Functions DCMI Exported Functions
+ * @{
+ */
+
+/** @defgroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the DCMI
+ (+) De-initialize the DCMI
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the DCMI according to the specified
+ * parameters in the DCMI_InitTypeDef and create the associated handle.
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
+{
+ /* Check the DCMI peripheral state */
+ if (hdcmi == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check function parameters */
+ assert_param(IS_DCMI_ALL_INSTANCE(hdcmi->Instance));
+ assert_param(IS_DCMI_PCKPOLARITY(hdcmi->Init.PCKPolarity));
+ assert_param(IS_DCMI_VSPOLARITY(hdcmi->Init.VSPolarity));
+ assert_param(IS_DCMI_HSPOLARITY(hdcmi->Init.HSPolarity));
+ assert_param(IS_DCMI_SYNCHRO(hdcmi->Init.SynchroMode));
+ assert_param(IS_DCMI_CAPTURE_RATE(hdcmi->Init.CaptureRate));
+ assert_param(IS_DCMI_EXTENDED_DATA(hdcmi->Init.ExtendedDataMode));
+ assert_param(IS_DCMI_MODE_JPEG(hdcmi->Init.JPEGMode));
+
+ assert_param(IS_DCMI_BYTE_SELECT_MODE(hdcmi->Init.ByteSelectMode));
+ assert_param(IS_DCMI_BYTE_SELECT_START(hdcmi->Init.ByteSelectStart));
+ assert_param(IS_DCMI_LINE_SELECT_MODE(hdcmi->Init.LineSelectMode));
+ assert_param(IS_DCMI_LINE_SELECT_START(hdcmi->Init.LineSelectStart));
+
+ if (hdcmi->State == HAL_DCMI_STATE_RESET)
+ {
+ /* Init the DCMI Callback settings */
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+ /* Reset callback pointers to the weak predefined callbacks */
+ hdcmi->FrameEventCallback = HAL_DCMI_FrameEventCallback; /* Legacy weak FrameEventCallback */
+ hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback; /* Legacy weak VsyncEventCallback */
+ hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback; /* Legacy weak LineEventCallback */
+ hdcmi->ErrorCallback = HAL_DCMI_ErrorCallback; /* Legacy weak ErrorCallback */
+
+ if (hdcmi->MspInitCallback == NULL)
+ {
+ /* Legacy weak MspInit Callback */
+ hdcmi->MspInitCallback = HAL_DCMI_MspInit;
+ }
+ /* Initialize the low level hardware (MSP) */
+ hdcmi->MspInitCallback(hdcmi);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_DCMI_MspInit(hdcmi);
+#endif /* (USE_HAL_DCMI_REGISTER_CALLBACKS) */
+ }
+
+ /* Change the DCMI state */
+ hdcmi->State = HAL_DCMI_STATE_BUSY;
+
+ if (hdcmi->Init.ExtendedDataMode != DCMI_EXTEND_DATA_8B)
+ {
+ /* Byte select mode must be programmed to the reset value if the extended mode
+ is not set to 8-bit data capture on every pixel clock */
+ hdcmi->Init.ByteSelectMode = DCMI_BSM_ALL;
+ }
+ /* Configures the HS, VS, DE and PC polarity */
+ hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_EDM_0 | \
+ DCMI_CR_EDM_1 | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG | \
+ DCMI_CR_ESS | DCMI_CR_BSM_0 | DCMI_CR_BSM_1 | DCMI_CR_OEBS | \
+ DCMI_CR_LSM | DCMI_CR_OELS);
+
+ hdcmi->Instance->CR |= (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate | \
+ hdcmi->Init.VSPolarity | hdcmi->Init.HSPolarity | \
+ hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode | \
+ hdcmi->Init.JPEGMode | hdcmi->Init.ByteSelectMode | \
+ hdcmi->Init.ByteSelectStart | hdcmi->Init.LineSelectMode | \
+ hdcmi->Init.LineSelectStart);
+
+ if (hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED)
+ {
+ hdcmi->Instance->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode) | \
+ ((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << DCMI_ESCR_LSC_Pos) | \
+ ((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << DCMI_ESCR_LEC_Pos) | \
+ ((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << DCMI_ESCR_FEC_Pos));
+
+ }
+
+ /* Enable the Line, Vsync, Error and Overrun interrupts */
+ __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR);
+
+ /* Update error code */
+ hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
+
+ /* Initialize the DCMI state*/
+ hdcmi->State = HAL_DCMI_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deinitializes the DCMI peripheral registers to their default reset
+ * values.
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @retval HAL status
+ */
+
+HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi)
+{
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+ if (hdcmi->MspDeInitCallback == NULL)
+ {
+ hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit;
+ }
+ /* De-Initialize the low level hardware (MSP) */
+ hdcmi->MspDeInitCallback(hdcmi);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+ HAL_DCMI_MspDeInit(hdcmi);
+#endif /* (USE_HAL_DCMI_REGISTER_CALLBACKS) */
+
+ /* Update error code */
+ hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
+
+ /* Initialize the DCMI state*/
+ hdcmi->State = HAL_DCMI_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdcmi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the DCMI MSP.
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @retval None
+ */
+__weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef *hdcmi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdcmi);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DCMI_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the DCMI MSP.
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @retval None
+ */
+__weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef *hdcmi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdcmi);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DCMI_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+/** @defgroup DCMI_Exported_Functions_Group2 IO operation functions
+ * @brief IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure destination address and data length and
+ Enables DCMI DMA request and enables DCMI capture
+ (+) Stop the DCMI capture.
+ (+) Handles DCMI interrupt request.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables DCMI DMA request and enables DCMI capture
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @param DCMI_Mode DCMI capture mode snapshot or continuous grab.
+ * @param pData The destination memory Buffer address (LCD Frame buffer).
+ * @param Length The length of capture to be transferred.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef *hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)
+{
+ uint32_t tmp_length = Length;
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t cllr_offset;
+ uint32_t tmp1;
+ uint32_t tmp2;
+
+ /* Check function parameters */
+ assert_param(IS_DCMI_CAPTURE_MODE(DCMI_Mode));
+
+ /* Process Locked */
+ __HAL_LOCK(hdcmi);
+
+ /* Lock the DCMI peripheral state */
+ hdcmi->State = HAL_DCMI_STATE_BUSY;
+
+ /* Enable DCMI by setting DCMIEN bit */
+ __HAL_DCMI_ENABLE(hdcmi);
+
+ /* Configure the DCMI Mode */
+ hdcmi->Instance->CR &= ~(DCMI_CR_CM);
+ hdcmi->Instance->CR |= (uint32_t)(DCMI_Mode);
+
+ /* Set the DMA memory0 conversion complete callback */
+ hdcmi->DMA_Handle->XferCpltCallback = DCMI_DMAXferCplt;
+
+ /* Set the DMA error callback */
+ hdcmi->DMA_Handle->XferErrorCallback = DCMI_DMAError;
+
+ /* Set the dma abort callback */
+ hdcmi->DMA_Handle->XferAbortCallback = NULL;
+
+ /* Reset transfer counters value */
+ hdcmi->XferCount = 0;
+ hdcmi->XferTransferNumber = 0;
+ hdcmi->XferSize = 0;
+ hdcmi->pBuffPtr = 0;
+
+ /* Length should be converted to number of bytes */
+ tmp_length = tmp_length * 4U;
+
+ if (tmp_length <= 0xFFFFU)
+ {
+ /* Continuoues Mode */
+ /* Enable the DMA Stream */
+ if ((hdcmi->DMA_Handle->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if ((hdcmi->DMA_Handle->LinkedListQueue != 0U) && (hdcmi->DMA_Handle->LinkedListQueue->Head != 0U))
+ {
+ /* Set Source , Destination , Length for DMA Xfer */
+
+ /* Set DMA data size */
+ hdcmi->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = tmp_length;
+ /* Set DMA source address */
+ hdcmi->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = \
+ (uint32_t)&hdcmi->Instance->DR;
+ /* Set DMA destination address */
+ hdcmi->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
+
+ status = HAL_DMAEx_List_Start_IT(hdcmi->DMA_Handle);
+ }
+ else
+ {
+ /* Set Error Code */
+ hdcmi->ErrorCode = HAL_DCMI_ERROR_DMA;
+ /* Change DCMI state */
+ hdcmi->State = HAL_DCMI_STATE_READY;
+ /* Release Lock */
+ __HAL_UNLOCK(hdcmi);
+ /* Return function status */
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, tmp_length);
+ }
+ }
+ else /* DCMI_DOUBLE_BUFFER Mode */
+ {
+ /* Double buffering is used through 2 Nodes
+ Calculate the elementary size to be transferred by each node */
+
+ /* Initialize transfer parameters */
+ hdcmi->XferCount = 1;
+ hdcmi->XferSize = tmp_length;
+ hdcmi->pBuffPtr = pData;
+
+ /* Get the number of buffer */
+ while (hdcmi->XferSize > 0xFFFFU)
+ {
+ hdcmi->XferSize = (hdcmi->XferSize / 2U);
+ hdcmi->XferCount = hdcmi->XferCount * 2U;
+ }
+
+ /* Update DCMI counter and transfer number*/
+ hdcmi->XferCount = (hdcmi->XferCount - 1U);
+ hdcmi->XferTransferNumber = hdcmi->XferCount;
+
+ if ((hdcmi->DMA_Handle->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if ((hdcmi->DMA_Handle->LinkedListQueue != 0U) && (hdcmi->DMA_Handle->LinkedListQueue->Head != 0U))
+ {
+ /* Update first node */
+
+ /* Set DMA Data size */
+ hdcmi->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hdcmi->XferSize ;
+
+ /* Set DMA Source address */
+ hdcmi->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = \
+ (uint32_t)&hdcmi->Instance->DR;
+
+ /* Set DMA Destination address */
+ hdcmi->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
+
+ /* Get CLLR offset */
+ cllr_offset = (hdcmi->DMA_Handle->LinkedListQueue->Head->NodeInfo & NODE_CLLR_IDX) >> 8U;
+
+ /* Update second node */
+ if (hdcmi->DMA_Handle->LinkedListQueue->Head->LinkRegisters[cllr_offset] != 0U)
+ {
+ tmp1 = (uint32_t)hdcmi->DMA_Handle->LinkedListQueue->Head ;
+ tmp2 = hdcmi->DMA_Handle->LinkedListQueue->Head->LinkRegisters[cllr_offset];
+ /* Update second node */
+
+ /* Set DMA Data size */
+ ((DMA_NodeTypeDef *)((tmp1 & DMA_CLBAR_LBA) + \
+ (tmp2 & DMA_CLLR_LA)))->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hdcmi->XferSize;
+
+ /* Set DMA Source address */
+ ((DMA_NodeTypeDef *)((tmp1 & DMA_CLBAR_LBA) + \
+ (tmp2 & DMA_CLLR_LA)))->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = \
+ (uint32_t)&hdcmi->Instance->DR;
+
+ /* Set DMA Destination address */
+ ((DMA_NodeTypeDef *)((tmp1 & DMA_CLBAR_LBA) + \
+ (tmp2 & DMA_CLLR_LA)))->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = \
+ (uint32_t)pData + hdcmi->XferSize;
+
+ if (HAL_DMAEx_List_Start_IT(hdcmi->DMA_Handle) != HAL_OK)
+ {
+ /* Set Error Code */
+ hdcmi->ErrorCode = HAL_DCMI_ERROR_DMA;
+ /* Change DCMI state */
+ hdcmi->State = HAL_DCMI_STATE_READY;
+ /* Release Lock */
+ __HAL_UNLOCK(hdcmi);
+ /* Return function status */
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Set Error Code */
+ hdcmi->ErrorCode = HAL_DCMI_ERROR_DMA;
+ /* Change DCMI state */
+ hdcmi->State = HAL_DCMI_STATE_READY;
+ /* Release Lock */
+ __HAL_UNLOCK(hdcmi);
+ /* Return function status */
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Set Error Code */
+ hdcmi->ErrorCode = HAL_DCMI_ERROR_DMA;
+ /* Change DCMI state */
+ hdcmi->State = HAL_DCMI_STATE_READY;
+ /* Release Lock */
+ __HAL_UNLOCK(hdcmi);
+ /* Return function status */
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Set Error Code */
+ hdcmi->ErrorCode = HAL_DCMI_ERROR_DMA;
+ /* Change DCMI state */
+ hdcmi->State = HAL_DCMI_STATE_READY;
+ /* Release Lock */
+ __HAL_UNLOCK(hdcmi);
+ /* Return function status */
+ status = HAL_ERROR;
+ }
+ }
+ if (status == HAL_OK)
+ {
+ /* Enable Capture */
+ hdcmi->Instance->CR |= DCMI_CR_CAPTURE;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdcmi);
+ }
+ else
+ {
+ /* Set Error Code */
+ hdcmi->ErrorCode = HAL_DCMI_ERROR_DMA;
+ /* Change DCMI state */
+ hdcmi->State = HAL_DCMI_STATE_READY;
+ /* Release Lock */
+ __HAL_UNLOCK(hdcmi);
+ /* Return function status */
+ status = HAL_ERROR;
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Disable DCMI DMA request and Disable DCMI capture
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef *hdcmi)
+{
+ uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock / 8U / 1000U);
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hdcmi);
+
+ /* Lock the DCMI peripheral state */
+ hdcmi->State = HAL_DCMI_STATE_BUSY;
+
+ /* Disable Capture */
+ hdcmi->Instance->CR &= ~(DCMI_CR_CAPTURE);
+
+ /* Check if the DCMI capture effectively disabled */
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ /* Update error code */
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;
+
+ status = HAL_TIMEOUT;
+ break;
+ }
+ } while ((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U);
+
+ /* Disable the DCMI */
+ __HAL_DCMI_DISABLE(hdcmi);
+
+ /* Disable the DMA */
+ (void)HAL_DMA_Abort(hdcmi->DMA_Handle);
+
+ /* Update error code */
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_NONE;
+
+ /* Change DCMI state */
+ hdcmi->State = HAL_DCMI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdcmi);
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Suspend DCMI capture
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef *hdcmi)
+{
+ uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock / 8U / 1000U);
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hdcmi);
+
+ if (hdcmi->State == HAL_DCMI_STATE_BUSY)
+ {
+ /* Change DCMI state */
+ hdcmi->State = HAL_DCMI_STATE_SUSPENDED;
+
+ /* Disable Capture */
+ hdcmi->Instance->CR &= ~(DCMI_CR_CAPTURE);
+
+ /* Check if the DCMI capture effectively disabled */
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ /* Update error code */
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;
+
+ /* Change DCMI state */
+ hdcmi->State = HAL_DCMI_STATE_READY;
+
+ status = HAL_TIMEOUT;
+ break;
+ }
+ } while ((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U);
+ }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdcmi);
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Resume DCMI capture
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef *hdcmi)
+{
+ /* Process locked */
+ __HAL_LOCK(hdcmi);
+
+ if (hdcmi->State == HAL_DCMI_STATE_SUSPENDED)
+ {
+ /* Change DCMI state */
+ hdcmi->State = HAL_DCMI_STATE_BUSY;
+
+ /* Enable Capture */
+ hdcmi->Instance->CR |= DCMI_CR_CAPTURE;
+ }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdcmi);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Handles DCMI interrupt request.
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for the DCMI.
+ * @retval None
+ */
+void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
+{
+ uint32_t isr_value = READ_REG(hdcmi->Instance->MISR);
+
+ /* Synchronization error interrupt management *******************************/
+ if ((isr_value & DCMI_FLAG_ERRRI) == DCMI_FLAG_ERRRI)
+ {
+ /* Clear the Synchronization error flag */
+ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_ERRRI);
+
+ /* Update error code */
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_SYNC;
+
+ /* Change DCMI state */
+ hdcmi->State = HAL_DCMI_STATE_ERROR;
+
+ /* Set the synchronization error callback */
+ hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError;
+
+ /* Abort the DMA Transfer */
+ if (HAL_DMA_Abort_IT(hdcmi->DMA_Handle) != HAL_OK)
+ {
+ DCMI_DMAError(hdcmi->DMA_Handle);
+ }
+ }
+ /* Overflow interrupt management ********************************************/
+ if ((isr_value & DCMI_FLAG_OVRRI) == DCMI_FLAG_OVRRI)
+ {
+ /* Clear the Overflow flag */
+ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_OVRRI);
+
+ /* Update error code */
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_OVR;
+
+ /* Change DCMI state */
+ hdcmi->State = HAL_DCMI_STATE_ERROR;
+
+ /* Set the overflow callback */
+ hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError;
+
+ /* Abort the DMA Transfer */
+ if (HAL_DMA_Abort_IT(hdcmi->DMA_Handle) != HAL_OK)
+ {
+ DCMI_DMAError(hdcmi->DMA_Handle);
+ }
+ }
+ /* Line Interrupt management ************************************************/
+ if ((isr_value & DCMI_FLAG_LINERI) == DCMI_FLAG_LINERI)
+ {
+ /* Clear the Line interrupt flag */
+ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_LINERI);
+
+ /* Line interrupt Callback */
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+ /*Call registered DCMI line event callback*/
+ hdcmi->LineEventCallback(hdcmi);
+#else
+ HAL_DCMI_LineEventCallback(hdcmi);
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
+ }
+ /* VSYNC interrupt management ***********************************************/
+ if ((isr_value & DCMI_FLAG_VSYNCRI) == DCMI_FLAG_VSYNCRI)
+ {
+ /* Clear the VSYNC flag */
+ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_VSYNCRI);
+
+ /* VSYNC Callback */
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+ /*Call registered DCMI vsync event callback*/
+ hdcmi->VsyncEventCallback(hdcmi);
+#else
+ HAL_DCMI_VsyncEventCallback(hdcmi);
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
+ }
+ /* FRAME interrupt management ***********************************************/
+ if ((isr_value & DCMI_FLAG_FRAMERI) == DCMI_FLAG_FRAMERI)
+ {
+ /* When snapshot mode, disable Vsync, Error and Overrun interrupts */
+ if ((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)
+ {
+ /* Disable the Line, Vsync, Error and Overrun interrupts */
+ __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR);
+ }
+
+ /* Disable the Frame interrupt */
+ __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_FRAME);
+
+ /* Clear the End of Frame flag */
+ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_FRAMERI);
+
+ /* Frame Callback */
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+ /*Call registered DCMI frame event callback*/
+ hdcmi->FrameEventCallback(hdcmi);
+#else
+ HAL_DCMI_FrameEventCallback(hdcmi);
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief Error DCMI callback.
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @retval None
+ */
+__weak void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdcmi);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DCMI_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Line Event callback.
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @retval None
+ */
+__weak void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdcmi);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DCMI_LineEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief VSYNC Event callback.
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @retval None
+ */
+__weak void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdcmi);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DCMI_VsyncEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Frame Event callback.
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @retval None
+ */
+__weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdcmi);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DCMI_FrameEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+[..] This section provides functions allowing to:
+ (+) Configure the CROP feature.
+ (+) Enable/Disable the CROP feature.
+ (+) Set embedded synchronization delimiters unmasks.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the DCMI CROP coordinate.
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @param YSize DCMI Line number
+ * @param XSize DCMI Pixel per line
+ * @param X0 DCMI window X offset
+ * @param Y0 DCMI window Y offset
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize,
+ uint32_t YSize)
+{
+ /* Process Locked */
+ __HAL_LOCK(hdcmi);
+
+ /* Lock the DCMI peripheral state */
+ hdcmi->State = HAL_DCMI_STATE_BUSY;
+
+ /* Check the parameters */
+ assert_param(IS_DCMI_WINDOW_COORDINATE(X0));
+ assert_param(IS_DCMI_WINDOW_HEIGHT(Y0));
+ assert_param(IS_DCMI_WINDOW_COORDINATE(XSize));
+ assert_param(IS_DCMI_WINDOW_COORDINATE(YSize));
+
+ /* Configure CROP */
+ hdcmi->Instance->CWSIZER = (XSize | (YSize << DCMI_CWSIZE_VLINE_Pos));
+ hdcmi->Instance->CWSTRTR = (X0 | (Y0 << DCMI_CWSTRT_VST_Pos));
+
+ /* Initialize the DCMI state*/
+ hdcmi->State = HAL_DCMI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdcmi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the Crop feature.
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi)
+{
+ /* Process Locked */
+ __HAL_LOCK(hdcmi);
+
+ /* Lock the DCMI peripheral state */
+ hdcmi->State = HAL_DCMI_STATE_BUSY;
+
+ /* Disable DCMI Crop feature */
+ hdcmi->Instance->CR &= ~(uint32_t)DCMI_CR_CROP;
+
+ /* Change the DCMI state*/
+ hdcmi->State = HAL_DCMI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdcmi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable the Crop feature.
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi)
+{
+ /* Process Locked */
+ __HAL_LOCK(hdcmi);
+
+ /* Lock the DCMI peripheral state */
+ hdcmi->State = HAL_DCMI_STATE_BUSY;
+
+ /* Enable DCMI Crop feature */
+ hdcmi->Instance->CR |= (uint32_t)DCMI_CR_CROP;
+
+ /* Change the DCMI state*/
+ hdcmi->State = HAL_DCMI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdcmi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set embedded synchronization delimiters unmasks.
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @param SyncUnmask pointer to a DCMI_SyncUnmaskTypeDef structure that contains
+ * the embedded synchronization delimiters unmasks.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask)
+{
+ /* Process Locked */
+ __HAL_LOCK(hdcmi);
+
+ /* Lock the DCMI peripheral state */
+ hdcmi->State = HAL_DCMI_STATE_BUSY;
+
+ /* Write DCMI embedded synchronization unmask register */
+ hdcmi->Instance->ESUR = (((uint32_t)SyncUnmask->FrameStartUnmask) | \
+ ((uint32_t)SyncUnmask->LineStartUnmask << DCMI_ESUR_LSU_Pos) | \
+ ((uint32_t)SyncUnmask->LineEndUnmask << DCMI_ESUR_LEU_Pos) | \
+ ((uint32_t)SyncUnmask->FrameEndUnmask << DCMI_ESUR_FEU_Pos));
+
+ /* Change the DCMI state*/
+ hdcmi->State = HAL_DCMI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdcmi);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Check the DCMI state.
+ (+) Get the specific DCMI error flag.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the DCMI state
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @retval HAL state
+ */
+HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi)
+{
+ return hdcmi->State;
+}
+
+/**
+ * @brief Return the DCMI error code
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @retval DCMI Error Code
+ */
+uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi)
+{
+ return hdcmi->ErrorCode;
+}
+
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User DCMI Callback
+ * To be used instead of the weak predefined callback
+ * @param hdcmi DCMI handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_DCMI_LINE_EVENT_CB_ID Line Event callback ID
+ * @arg @ref HAL_DCMI_FRAME_EVENT_CB_ID Frame Event callback ID
+ * @arg @ref HAL_DCMI_VSYNC_EVENT_CB_ID Vsync Event callback ID
+ * @arg @ref HAL_DCMI_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_DCMI_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_DCMI_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID,
+ pDCMI_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* update the error code */
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ if (hdcmi->State == HAL_DCMI_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DCMI_FRAME_EVENT_CB_ID :
+ hdcmi->FrameEventCallback = pCallback;
+ break;
+
+ case HAL_DCMI_VSYNC_EVENT_CB_ID :
+ hdcmi->VsyncEventCallback = pCallback;
+ break;
+
+ case HAL_DCMI_LINE_EVENT_CB_ID :
+ hdcmi->LineEventCallback = pCallback;
+ break;
+
+ case HAL_DCMI_ERROR_CB_ID :
+ hdcmi->ErrorCallback = pCallback;
+ break;
+
+ case HAL_DCMI_MSPINIT_CB_ID :
+ hdcmi->MspInitCallback = pCallback;
+ break;
+
+ case HAL_DCMI_MSPDEINIT_CB_ID :
+ hdcmi->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hdcmi->State == HAL_DCMI_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DCMI_MSPINIT_CB_ID :
+ hdcmi->MspInitCallback = pCallback;
+ break;
+
+ case HAL_DCMI_MSPDEINIT_CB_ID :
+ hdcmi->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* update the error code */
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update the error code */
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Unregister a DCMI Callback
+ * DCMI callabck is redirected to the weak predefined callback
+ * @param hdcmi DCMI handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_DCMI_LINE_EVENT_CB_ID Line Event callback ID
+ * @arg @ref HAL_DCMI_FRAME_EVENT_CB_ID Frame Event callback ID
+ * @arg @ref HAL_DCMI_VSYNC_EVENT_CB_ID Vsync Event callback ID
+ * @arg @ref HAL_DCMI_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_DCMI_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_DCMI_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (hdcmi->State == HAL_DCMI_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DCMI_FRAME_EVENT_CB_ID :
+ hdcmi->FrameEventCallback = HAL_DCMI_FrameEventCallback; /* Legacy weak FrameEventCallback */
+ break;
+
+ case HAL_DCMI_VSYNC_EVENT_CB_ID :
+ hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback; /* Legacy weak VsyncEventCallback */
+ break;
+
+ case HAL_DCMI_LINE_EVENT_CB_ID :
+ hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback; /* Legacy weak LineEventCallback */
+ break;
+
+ case HAL_DCMI_ERROR_CB_ID :
+ hdcmi->ErrorCallback = HAL_DCMI_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_DCMI_MSPINIT_CB_ID :
+ hdcmi->MspInitCallback = HAL_DCMI_MspInit;
+ break;
+
+ case HAL_DCMI_MSPDEINIT_CB_ID :
+ hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit;
+ break;
+
+ default :
+ /* update the error code */
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hdcmi->State == HAL_DCMI_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DCMI_MSPINIT_CB_ID :
+ hdcmi->MspInitCallback = HAL_DCMI_MspInit;
+ break;
+
+ case HAL_DCMI_MSPDEINIT_CB_ID :
+ hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit;
+ break;
+
+ default :
+ /* update the error code */
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update the error code */
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DCMI_Private_Functions DCMI Private Functions
+ * @{
+ */
+/**
+ * @brief DMA conversion complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma)
+{
+
+ DCMI_HandleTypeDef *hdcmi = (DCMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ uint32_t tmp1;
+ uint32_t tmp2;
+ DMA_NodeTypeDef *pnode;
+ uint32_t pbuff;
+ uint32_t transfernumber;
+ uint32_t transfercount;
+ uint32_t transfersize ;
+
+ /* Update Nodes destinations */
+ if (hdcmi->XferSize != 0U)
+ {
+ pbuff = hdcmi->pBuffPtr;
+ transfernumber = hdcmi->XferTransferNumber;
+ transfercount = hdcmi->XferCount;
+ transfersize = hdcmi->XferSize;
+
+ tmp1 = hdcmi->DMA_Handle->Instance->CLLR & DMA_CLLR_LA;
+ tmp2 = hdcmi->DMA_Handle->Instance->CLBAR & DMA_CLBAR_LBA;
+ pnode = (DMA_NodeTypeDef *)(uint32_t)(tmp1 | tmp2);
+
+ if (hdcmi->XferCount > 1U)
+ {
+ pnode->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = pbuff + ((transfernumber - transfercount + 2U) * transfersize);
+ hdcmi->XferCount--;
+ }
+
+ else if (hdcmi->XferCount == 1U)
+ {
+ pnode->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = hdcmi->pBuffPtr;
+ hdcmi->XferCount--;
+ }
+ else
+ {
+ pnode->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = hdcmi->pBuffPtr + hdcmi->XferSize;
+
+ /* When Continuous mode, re-set dcmi XferCount */
+ if ((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_CONTINUOUS)
+ {
+ hdcmi->XferCount = hdcmi->XferTransferNumber ;
+ }
+ /* When snapshot mode, set dcmi state to ready */
+ else
+ {
+ hdcmi->State = HAL_DCMI_STATE_READY;
+ }
+
+ __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME);
+ }
+ }
+ else /* Snapshot Mode */
+ {
+ /* Enable the Frame interrupt */
+ __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME);
+
+ /* When snapshot mode, set dcmi state to ready */
+ if ((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)
+ {
+ hdcmi->State = HAL_DCMI_STATE_READY;
+ }
+ }
+}
+
+/**
+ * @brief DMA error callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void DCMI_DMAError(DMA_HandleTypeDef *hdma)
+{
+ DCMI_HandleTypeDef *hdcmi = (DCMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ if (hdcmi->DMA_Handle->ErrorCode != HAL_DMA_ERROR_ULE)
+ {
+ /* Initialize the DCMI state*/
+ hdcmi->State = HAL_DCMI_STATE_READY;
+
+ /* Set DCMI Error Code */
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_DMA;
+ }
+
+ /* DCMI error Callback */
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+ /*Call registered DCMI error callback*/
+ hdcmi->ErrorCallback(hdcmi);
+#else
+ HAL_DCMI_ErrorCallback(hdcmi);
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
+
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* DCMI */
+#endif /* HAL_DCMI_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma.c
new file mode 100644
index 00000000..9b5f5ed5
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma.c
@@ -0,0 +1,1695 @@
+/**
+ **********************************************************************************************************************
+ * @file stm32u5xx_hal_dma.c
+ * @author MCD Application Team
+ * @brief This file provides firmware functions to manage the following functionalities of the Direct Memory Access
+ * (DMA) peripheral:
+ * + Initialization/De-Initialization Functions
+ * + I/O Operation Functions
+ * + State and Errors Functions
+ * + DMA Attributes Functions
+ *
+ **********************************************************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ **********************************************************************************************************************
+ @verbatim
+ ======================================================================================================================
+ ############### How to use this driver ###############
+ ======================================================================================================================
+ [..]
+ DMA transfer modes are divided to 2 major categories :
+ (+) Normal transfers (legacy)
+ (+) Linked-list transfers
+
+ [..]
+ Normal transfers mode is initialized via the standard module and linked-list mode is configured via the extended
+ module.
+
+ [..]
+ Additionally to linked-list capability, all advanced DMA features are managed and configured via the extended
+ module as extensions to normal mode.
+ Advanced features are :
+ (+) Repeated block feature.
+ (+) Trigger feature.
+ (+) Data handling feature.
+
+ [..]
+ DMA Legacy circular transfer, is replaced by circular linked-list configuration.
+
+
+ *** Initialization and De-Initialization ***
+ ============================================
+ [..]
+ For a given channel, enable and configure the peripheral to be connected to the DMA Channel (except for internal
+ SRAM/FLASH memories: no initialization is necessary) please refer to Reference manual for connection between
+ peripherals and DMA requests.
+
+ [..]
+ For a given channel, use HAL_DMA_Init function to program the required configuration for normal transfer through
+ the following parameters:
+
+ (+) Request : Specifies the DMA channel request
+ Request parameters :
+ (++) can be a value of @ref DMA_Request_Selection
+
+ (+) BlkHWRequest : Specifies the Block hardware request mode for DMA channel
+ (++) can be a value of @ref DMA_Block_Request
+
+ (+) Direction : Specifies the transfer direction for DMA channel
+ (++) can be a value of @ref DMA_Transfer_Direction
+
+ (+) SrcInc : Specifies the source increment mode for the DMA channel
+ (++) can be a value of @ref DMA_Source_Increment_Mode
+
+ (+) DestInc : Specifies the destination increment mode for the DMA channel
+ (++) can be a value of @ref DMA_Destination_Increment_Mode
+
+ (+) SrcDataWidth : Specifies the source data width for the DMA channel
+ (++) can be a value of @ref DMA_Source_Data_Width
+
+ (+) DestDataWidth : Specifies the destination data width for the DMA channel
+ (++) can be a value of @ref DMA_Destination_Data_Width
+
+ (+) Priority : Specifies the priority for the DMA channel
+ (++) can be a value of @ref DMA_Priority_Level
+
+ (+) SrcBurstLength : Specifies the source burst length (number of beats) for the DMA channel
+ (++) can be a value of between 1 and 64
+
+ (+) DestBurstLength : Specifies the destination burst length (number of beats) for the DMA channel
+ (++) can be a value of between 1 and 64
+
+ (+) TransferAllocatedPort : Specifies the source and destination allocated ports
+ (++) can be a value of @ref DMA_Transfer_Allocated_Port
+
+ (+) TransferEventMode : Specifies the transfer event mode for the DMA channel
+ (++) can be a value of @ref DMA_Transfer_Event_Mode
+
+ (+) Mode : Specifies the transfer mode for the DMA channel
+ (++) can be a value of @ref DMA_Transfer_Mode
+
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Use HAL_DMA_Start() to start a DMA normal transfer after the configuration of source address, destination
+ address and the size of data to be transferred.
+
+ (+) Use HAL_DMA_PollForTransfer() to poll for selected transfer level. In this case a fixed Timeout can be
+ configured by User depending on his application.
+ Transfer level can be :
+ (++) HAL_DMA_HALF_TRANSFER
+ (++) HAL_DMA_FULL_TRANSFER
+ For circular transfer, this API returns an HAL_ERROR with HAL_DMA_ERROR_NOT_SUPPORTED error code.
+
+ (+) Use HAL_DMA_Abort() function to abort any ongoing DMA transfer in blocking mode.
+ This API returns HAL_ERROR when there is no ongoing transfer or timeout is reached when disabling the DMA
+ channel. (This API should not be called from an interrupt service routine)
+
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
+
+ (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
+
+ (+) Use HAL_DMA_RegisterCallback() function to register user callbacks from the following list :
+ (++) XferCpltCallback : transfer complete callback.
+ (++) XferHalfCpltCallback : half transfer complete callback.
+ (++) XferErrorCallback : transfer error callback.
+ (++) XferAbortCallback : transfer abort complete callback.
+ (++) XferSuspendCallback : transfer suspend complete callback.
+
+ (+) Use HAL_DMA_Start_IT() to start the DMA transfer after the enable of DMA interrupts and the configuration
+ of source address,destination address and the size of data to be transferred.
+
+ (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() interrupt subroutine to handle any DMA interrupt.
+
+ (+) Use HAL_DMA_Abort_IT() function to abort any on-going DMA transfer in non-blocking mode.
+ This API will suspend immediately the DMA channel execution. When the transfer is effectively suspended,
+ an interrupt is generated and HAL_DMA_IRQHandler() will reset the channel and execute the callback
+ XferAbortCallback. (This API could be called from an interrupt service routine)
+
+
+ *** State and errors ***
+ ========================
+ [..]
+ (+) Use HAL_DMA_GetState() function to get the DMA state.
+ (+) Use HAL_DMA_GetError() function to get the DMA error code.
+
+
+ *** Security and privilege attributes ***
+ =========================================
+ [..]
+ (+) Use HAL_DMA_ConfigChannelAttributes() function to configure DMA channel security and privilege attributes.
+ (++) Security : at channel level, at source level and at destination level.
+ (++) Privilege : at channel level.
+ (+) Use HAL_DMA_GetConfigChannelAttributes() function to get the DMA channel attributes.
+ (+) Use HAL_DMA_LockChannelAttributes() function to lock the DMA channel security and privilege attributes
+ configuration. This API is called once after each system boot.
+ When this API is called, HAL_DMA_ConfigChannelAttributes() API cannot be used anymore.
+ (+) Use HAL_DMA_GetLockChannelAttributes() function to get the attributes lock status.
+
+
+ *** DMA HAL driver macros list ***
+ ==================================
+ [..]
+ Below the list of most used macros in DMA HAL driver.
+
+ (+) __HAL_DMA_ENABLE : Enable the specified DMA Channel.
+ (+) __HAL_DMA_DISABLE : Disable the specified DMA Channel.
+ (+) __HAL_DMA_GET_FLAG : Get the DMA Channel pending flags.
+ (+) __HAL_DMA_CLEAR_FLAG : Clear the DMA Channel pending flags.
+ (+) __HAL_DMA_ENABLE_IT : Enable the specified DMA Channel interrupts.
+ (+) __HAL_DMA_DISABLE_IT : Disable the specified DMA Channel interrupts.
+ (+) __HAL_DMA_GET_IT_SOURCE : Check whether the specified DMA Channel interrupt has occurred or not.
+
+ [..]
+ (@) You can refer to the header file of the DMA HAL driver for more useful macros.
+
+ @endverbatim
+ **********************************************************************************************************************
+ */
+
+/* Includes ----------------------------------------------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup DMA DMA
+ * @brief DMA HAL module driver
+ * @{
+ */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+
+/* Private typedef ---------------------------------------------------------------------------------------------------*/
+/* Private constants -------------------------------------------------------------------------------------------------*/
+/* Private macro -----------------------------------------------------------------------------------------------------*/
+/* Private variables -------------------------------------------------------------------------------------------------*/
+/* Private function prototypes ---------------------------------------------------------------------------------------*/
+static void DMA_SetConfig(DMA_HandleTypeDef const *const hdma,
+ uint32_t SrcAddress,
+ uint32_t DstAddress,
+ uint32_t SrcDataSize);
+static void DMA_Init(DMA_HandleTypeDef const *const hdma);
+
+/* Exported functions ------------------------------------------------------------------------------------------------*/
+
+/** @addtogroup DMA_Exported_Functions DMA Exported Functions
+ * @{
+ */
+
+/** @addtogroup DMA_Exported_Functions_Group1
+ *
+@verbatim
+ ======================================================================================================================
+ ############### Initialization and de-initialization functions ###############
+ ======================================================================================================================
+ [..]
+ This section provides functions allowing to initialize and de-initialize the DMA channel in normal mode.
+
+ [..]
+ (+) The HAL_DMA_Init() function follows the DMA channel configuration procedures as described in reference manual.
+ (+) The HAL_DMA_DeInit() function allows to de-initialize the DMA channel.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the DMA channel in normal mode according to the specified parameters in the DMA_InitTypeDef and
+ * create the associated handle.
+ * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+ * specified DMA Channel.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma)
+{
+ /* Get tick number */
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Check the DMA peripheral handle parameter */
+ if (hdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+ assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
+ if ((hdma->Init.Direction == DMA_MEMORY_TO_PERIPH) || (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY))
+ {
+ assert_param(IS_DMA_REQUEST(hdma->Init.Request));
+ }
+ assert_param(IS_DMA_BLOCK_HW_REQUEST(hdma->Init.BlkHWRequest));
+ assert_param(IS_DMA_SOURCE_INC(hdma->Init.SrcInc));
+ assert_param(IS_DMA_DESTINATION_INC(hdma->Init.DestInc));
+ assert_param(IS_DMA_SOURCE_DATA_WIDTH(hdma->Init.SrcDataWidth));
+ assert_param(IS_DMA_DESTINATION_DATA_WIDTH(hdma->Init.DestDataWidth));
+ assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
+ assert_param(IS_DMA_TCEM_EVENT_MODE(hdma->Init.TransferEventMode));
+ assert_param(IS_DMA_MODE(hdma->Init.Mode));
+ /* Check DMA channel instance */
+ if (IS_GPDMA_INSTANCE(hdma->Instance) != 0U)
+ {
+ assert_param(IS_DMA_BURST_LENGTH(hdma->Init.SrcBurstLength));
+ assert_param(IS_DMA_BURST_LENGTH(hdma->Init.DestBurstLength));
+ assert_param(IS_DMA_TRANSFER_ALLOCATED_PORT(hdma->Init.TransferAllocatedPort));
+ }
+
+ /* Allocate lock resource */
+ __HAL_UNLOCK(hdma);
+
+ /* Update the DMA channel state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ /* Disable the DMA channel */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Check if the DMA channel is effectively disabled */
+ while ((hdma->Instance->CCR & DMA_CCR_EN) != 0U)
+ {
+ /* Check for the Timeout */
+ if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
+ {
+ /* Update the DMA channel error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+
+ /* Update the DMA channel state */
+ hdma->State = HAL_DMA_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Initialize the DMA channel registers */
+ DMA_Init(hdma);
+
+ /* Update DMA channel operation mode */
+ hdma->Mode = hdma->Init.Mode;
+
+ /* Update the DMA channel error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Update the DMA channel state */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitialize the DMA channel when it is configured in normal mode.
+ * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+ * specified DMA Channel.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma)
+{
+ DMA_TypeDef *p_dma_instance;
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Check the DMA peripheral handle parameter */
+ if (hdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+
+ /* Get DMA instance */
+ p_dma_instance = GET_DMA_INSTANCE(hdma);
+
+ /* Disable the selected DMA Channel */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Check if the DMA channel is effectively disabled */
+ while ((hdma->Instance->CCR & DMA_CCR_EN) != 0U)
+ {
+ /* Check for the Timeout */
+ if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
+ {
+ /* Update the DMA channel error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+
+ /* Update the DMA channel state */
+ hdma->State = HAL_DMA_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Reset DMA Channel registers */
+ hdma->Instance->CLBAR = 0U;
+ hdma->Instance->CCR = 0U;
+ hdma->Instance->CTR1 = 0U;
+ hdma->Instance->CTR2 = 0U;
+ hdma->Instance->CBR1 = 0U;
+ hdma->Instance->CSAR = 0U;
+ hdma->Instance->CDAR = 0U;
+ hdma->Instance->CLLR = 0U;
+
+ /* Reset 2D Addressing registers */
+ if (IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) != 0U)
+ {
+ hdma->Instance->CTR3 = 0U;
+ hdma->Instance->CBR2 = 0U;
+ }
+
+ /* Clear privilege attribute */
+ CLEAR_BIT(p_dma_instance->PRIVCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU)));
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ /* Clear secure attribute */
+ CLEAR_BIT(p_dma_instance->SECCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU)));
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+ /* Clear all flags */
+ __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP |
+ DMA_FLAG_TO));
+
+ /* Clean all callbacks */
+ hdma->XferCpltCallback = NULL;
+ hdma->XferHalfCpltCallback = NULL;
+ hdma->XferErrorCallback = NULL;
+ hdma->XferAbortCallback = NULL;
+ hdma->XferSuspendCallback = NULL;
+
+ /* Clean DMA queue */
+ hdma->LinkedListQueue = NULL;
+
+ /* Clean DMA parent */
+ if (hdma->Parent != NULL)
+ {
+ hdma->Parent = NULL;
+ }
+
+ /* Update DMA channel operation mode */
+ hdma->Mode = DMA_NORMAL;
+
+ /* Update the DMA channel error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Update the DMA channel state */
+ hdma->State = HAL_DMA_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Exported_Functions_Group2
+ *
+@verbatim
+ ======================================================================================================================
+ ############### IO operation functions ###############
+ ======================================================================================================================
+ [..]
+ This section provides functions allowing to :
+ (+) Configure the source, destination address and data size and Start DMA transfer in normal mode
+ (+) Abort DMA transfer
+ (+) Poll for transfer complete
+ (+) Handle DMA interrupt request
+ (+) Register and Unregister DMA callbacks
+
+ [..]
+ (+) The HAL_DMA_Start() function allows to start the DMA channel transfer in normal mode (Blocking mode).
+ (+) The HAL_DMA_Start_IT() function allows to start the DMA channel transfer in normal mode (Non-blocking mode).
+ (+) The HAL_DMA_Abort() function allows to abort any on-going transfer (Blocking mode).
+ (+) The HAL_DMA_Abort_IT() function allows to abort any on-going transfer (Non-blocking mode).
+ (+) The HAL_DMA_PollForTransfer() function allows to poll on half transfer and transfer complete (Blocking mode).
+ This API cannot be used for circular transfers.
+ (+) The HAL_DMA_IRQHandler() function allows to handle any DMA channel interrupt (Non-blocking mode).
+ (+) The HAL_DMA_RegisterCallback() and HAL_DMA_UnRegisterCallback() functions allow respectively to register and
+ unregister user customized callbacks.
+ User callbacks are called under HAL_DMA_IRQHandler().
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start the DMA channel transfer in normal mode (Blocking mode).
+ * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for
+ * the specified DMA Channel.
+ * @param SrcAddress : The source data address.
+ * @param DstAddress : The destination data address.
+ * @param SrcDataSize : The length of data to be transferred from source to destination in bytes.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *const hdma,
+ uint32_t SrcAddress,
+ uint32_t DstAddress,
+ uint32_t SrcDataSize)
+{
+ /* Check the DMA peripheral handle parameter */
+ if (hdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DMA_BLOCK_SIZE(SrcDataSize));
+
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ /* Check DMA channel state */
+ if (hdma->State == HAL_DMA_STATE_READY)
+ {
+ /* Update the DMA channel state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ /* Update the DMA channel error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Configure the source address, destination address, the data size and clear flags */
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, SrcDataSize);
+
+ /* Enable DMA channel */
+ __HAL_DMA_ENABLE(hdma);
+ }
+ else
+ {
+ /* Update the DMA channel error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the DMA channel transfer in normal mode with interrupts enabled (Non-blocking mode).
+ * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+ * specified DMA Channel.
+ * @param SrcAddress : The source data address.
+ * @param DstAddress : The destination data address.
+ * @param SrcDataSize : The length of data to be transferred from source to destination in bytes.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *const hdma,
+ uint32_t SrcAddress,
+ uint32_t DstAddress,
+ uint32_t SrcDataSize)
+{
+ /* Check the DMA peripheral handle parameter */
+ if (hdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DMA_BLOCK_SIZE(SrcDataSize));
+
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ /* Check DMA channel state */
+ if (hdma->State == HAL_DMA_STATE_READY)
+ {
+ /* Update the DMA channel state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ /* Update the DMA channel error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Configure the source address, destination address, the data size and clear flags */
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, SrcDataSize);
+
+ /* Enable common interrupts: Transfer Complete and Transfer Errors ITs */
+ __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_DTE | DMA_IT_ULE | DMA_IT_USE | DMA_IT_TO));
+
+ /* Check half transfer complete callback */
+ if (hdma->XferHalfCpltCallback != NULL)
+ {
+ /* If Half Transfer complete callback is set, enable the corresponding IT */
+ __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
+ }
+
+ /* Check Half suspend callback */
+ if (hdma->XferSuspendCallback != NULL)
+ {
+ /* If Transfer suspend callback is set, enable the corresponding IT */
+ __HAL_DMA_ENABLE_IT(hdma, DMA_IT_SUSP);
+ }
+
+ /* Enable DMA channel */
+ __HAL_DMA_ENABLE(hdma);
+ }
+ else
+ {
+ /* Update the DMA channel error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort any on-going DMA channel transfer (Blocking mode).
+ * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+ * specified DMA Channel.
+ * @note After suspending a DMA channel, a wait until the DMA channel is effectively stopped is added. If a channel
+ * is suspended while a data transfer is on-going, the current data will be transferred and the channel will be
+ * effectively suspended only after the transfer of any on-going data is finished.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *const hdma)
+{
+ /* Get tick number */
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Check the DMA peripheral handle parameter */
+ if (hdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check DMA channel state */
+ if (hdma->State != HAL_DMA_STATE_BUSY)
+ {
+ /* Update the DMA channel error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Suspend the channel */
+ hdma->Instance->CCR |= DMA_CCR_SUSP;
+
+ /* Update the DMA channel state */
+ hdma->State = HAL_DMA_STATE_SUSPEND;
+
+ /* Check if the DMA Channel is suspended */
+ while ((hdma->Instance->CSR & DMA_CSR_SUSPF) == 0U)
+ {
+ /* Check for the Timeout */
+ if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
+ {
+ /* Update the DMA channel error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
+
+ /* Update the DMA channel state */
+ hdma->State = HAL_DMA_STATE_ERROR;
+
+ /* Check DMA channel transfer mode */
+ if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ /* Update the linked-list queue state */
+ hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Reset the channel */
+ hdma->Instance->CCR |= DMA_CCR_RESET;
+
+ /* Update the DMA channel state */
+ hdma->State = HAL_DMA_STATE_ABORT;
+
+ /* Clear all status flags */
+ __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP |
+ DMA_FLAG_TO));
+
+ /* Update the DMA channel state */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ /* Check DMA channel transfer mode */
+ if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ /* Update the linked-list queue state */
+ hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
+
+ /* Clear remaining data size to ensure loading linked-list from memory next start */
+ hdma->Instance->CBR1 = 0U;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort any on-going DMA channel transfer in interrupt mode (Non-blocking mode).
+ * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+ * specified DMA Channel.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *const hdma)
+{
+ /* Check the DMA peripheral handle parameter */
+ if (hdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check DMA channel state */
+ if (hdma->State != HAL_DMA_STATE_BUSY)
+ {
+ /* Update the DMA channel error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Update the DMA channel state */
+ hdma->State = HAL_DMA_STATE_ABORT;
+
+ /* Suspend the channel and activate suspend interrupt */
+ hdma->Instance->CCR |= (DMA_CCR_SUSP | DMA_CCR_SUSPIE);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Polling for transfer status (Blocking mode).
+ * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+ * specified DMA Channel.
+ * @param CompleteLevel : Specifies the DMA level complete.
+ * @param Timeout : Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *const hdma,
+ HAL_DMA_LevelCompleteTypeDef CompleteLevel,
+ uint32_t Timeout)
+{
+ /* Get tick number */
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t level_flag;
+ uint32_t tmp_csr;
+
+ /* Check the DMA peripheral handle parameter */
+ if (hdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DMA_LEVEL_COMPLETE(CompleteLevel));
+
+ /* Check DMA channel state */
+ if (hdma->State != HAL_DMA_STATE_BUSY)
+ {
+ /* Update the DMA channel error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_ERROR;
+ }
+
+ /* Polling mode is not supported in circular mode */
+ if ((hdma->Mode & DMA_LINKEDLIST_CIRCULAR) == DMA_LINKEDLIST_CIRCULAR)
+ {
+ /* Update the DMA channel error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+
+ return HAL_ERROR;
+ }
+
+ /* Get the level transfer complete flag */
+ level_flag = ((CompleteLevel == HAL_DMA_FULL_TRANSFER) ? DMA_FLAG_IDLE : DMA_FLAG_HT);
+
+ /* Get DMA channel status */
+ tmp_csr = hdma->Instance->CSR;
+
+ while ((tmp_csr & level_flag) == 0U)
+ {
+ /* Check for the timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ /* Update the DMA channel error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
+
+ /*
+ If timeout, abort the current transfer.
+ Note that the Abort function will
+ - Clear all transfer flags.
+ - Unlock.
+ - Set the State.
+ */
+ (void)HAL_DMA_Abort(hdma);
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Get a newer CSR register value */
+ tmp_csr = hdma->Instance->CSR;
+ }
+
+ /* Check trigger overrun flag */
+ if ((tmp_csr & DMA_FLAG_TO) != 0U)
+ {
+ /* Update the DMA channel error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_TO;
+
+ /* Clear the error flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_TO);
+ }
+
+ /* Check error flags */
+ if ((tmp_csr & (DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE)) != 0U)
+ {
+ /* Check the data transfer error flag */
+ if ((tmp_csr & DMA_FLAG_DTE) != 0U)
+ {
+ /* Update the DMA channel error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_DTE;
+
+ /* Clear the error flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_DTE);
+ }
+
+ /* Check the update link error flag */
+ if ((tmp_csr & DMA_FLAG_ULE) != 0U)
+ {
+ /* Update the DMA channel error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_ULE;
+
+ /* Clear the error flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_ULE);
+ }
+
+ /* Check the user setting error flag */
+ if ((tmp_csr & DMA_FLAG_USE) != 0U)
+ {
+ /* Update the DMA channel error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_USE;
+
+ /* Clear the error flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_USE);
+ }
+
+ /* Reset the channel */
+ hdma->Instance->CCR |= DMA_CCR_RESET;
+
+ /* Update the DMA channel state */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ /* Check DMA channel transfer mode */
+ if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ /* Update the linked-list queue state */
+ hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_ERROR;
+ }
+
+ /* Clear the transfer level flag */
+ if (CompleteLevel == HAL_DMA_HALF_TRANSFER)
+ {
+ /* Clear the Half Transfer flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_HT);
+ }
+ else if (CompleteLevel == HAL_DMA_FULL_TRANSFER)
+ {
+ /* Clear the transfer flags */
+ __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT));
+
+ /* Update the DMA channel state */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ /* Check DMA channel transfer mode */
+ if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ /* Update the linked-list queue state */
+ hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle DMA interrupt request (Non-blocking mode).
+ * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+ * specified DMA Channel.
+ * @retval None.
+ */
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma)
+{
+ DMA_TypeDef *p_dma_instance = GET_DMA_INSTANCE(hdma);
+ uint32_t global_it_flag = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU);
+
+ /* Global Interrupt Flag management *********************************************************************************/
+ if (IS_DMA_GLOBAL_ACTIVE_FLAG(p_dma_instance, global_it_flag) == 0U)
+ {
+ return; /* the global interrupt flag for the current channel is down , nothing to do */
+ }
+
+ /* Data Transfer Error Interrupt management *************************************************************************/
+ if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_DTE) != 0U))
+ {
+ /* Check if interrupt source is enabled */
+ if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DTE) != 0U)
+ {
+ /* Clear the transfer error flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_DTE);
+
+ /* Update the DMA channel error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_DTE;
+ }
+ }
+
+ /* Update Linked-list Error Interrupt management ********************************************************************/
+ if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_ULE) != 0U))
+ {
+ /* Check if interrupt source is enabled */
+ if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_ULE) != 0U)
+ {
+ /* Clear the update linked-list error flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_ULE);
+
+ /* Update the DMA channel error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_ULE;
+ }
+ }
+
+ /* User Setting Error Interrupt management **************************************************************************/
+ if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_USE) != 0U))
+ {
+ /* Check if interrupt source is enabled */
+ if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_USE) != 0U)
+ {
+ /* Clear the user setting error flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_USE);
+
+ /* Update the DMA channel error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_USE;
+ }
+ }
+
+ /* Trigger Overrun Interrupt management *****************************************************************************/
+ if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_TO) != 0U))
+ {
+ /* Check if interrupt source is enabled */
+ if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TO) != 0U)
+ {
+ /* Clear the trigger overrun flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_TO);
+
+ /* Update the DMA channel error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_TO;
+ }
+ }
+
+ /* Half Transfer Complete Interrupt management **********************************************************************/
+ if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_HT) != 0U))
+ {
+ /* Check if interrupt source is enabled */
+ if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U)
+ {
+ /* Clear the half transfer flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_HT);
+
+ /* Check half transfer complete callback */
+ if (hdma->XferHalfCpltCallback != NULL)
+ {
+ /* Half transfer callback */
+ hdma->XferHalfCpltCallback(hdma);
+ }
+ }
+ }
+
+ /* Suspend Transfer Interrupt management ****************************************************************************/
+ if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_SUSP) != 0U))
+ {
+ /* Check if interrupt source is enabled */
+ if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_SUSP) != 0U)
+ {
+ /* Clear the block transfer complete flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_SUSP);
+
+ /* Check DMA channel state */
+ if (hdma->State == HAL_DMA_STATE_ABORT)
+ {
+ /* Disable the suspend transfer interrupt */
+ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_SUSP);
+
+ /* Reset the channel internal state and reset the FIFO */
+ hdma->Instance->CCR |= DMA_CCR_RESET;
+
+ if ((hdma->Instance->CCR & DMA_CCR_EN) != 0U)
+ {
+ /* Update the DMA channel state */
+ hdma->State = HAL_DMA_STATE_ERROR;
+ }
+ else
+ {
+ /* Update the DMA channel state */
+ hdma->State = HAL_DMA_STATE_READY;
+ }
+
+ /* Check DMA channel transfer mode */
+ if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ /* Update the linked-list queue state */
+ hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ /* Check transfer abort callback */
+ if (hdma->XferAbortCallback != NULL)
+ {
+ /* Transfer abort callback */
+ hdma->XferAbortCallback(hdma);
+ }
+
+ return;
+ }
+ else
+ {
+ /* Update the DMA channel state */
+ hdma->State = HAL_DMA_STATE_SUSPEND;
+
+ /* Check transfer suspend callback */
+ if (hdma->XferSuspendCallback != NULL)
+ {
+ /* Transfer suspend callback */
+ hdma->XferSuspendCallback(hdma);
+ }
+ }
+ }
+ }
+
+ /* Transfer Complete Interrupt management ***************************************************************************/
+ if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_TC) != 0U))
+ {
+ /* Check if interrupt source is enabled */
+ if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U)
+ {
+ /* Check DMA channel transfer mode */
+ if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ /* If linked-list transfer */
+ if (hdma->Instance->CLLR == 0U)
+ {
+ if (hdma->Instance->CBR1 == 0U)
+ {
+ /* Update the DMA channel state */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ /* Update the linked-list queue state */
+ hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
+ }
+ }
+ }
+ else
+ {
+ /* If normal transfer */
+ if (hdma->Instance->CBR1 == 0U)
+ {
+ /* Update the DMA channel state */
+ hdma->State = HAL_DMA_STATE_READY;
+ }
+ }
+
+ /* Clear TC and HT transfer flags */
+ __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT));
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ /* Check transfer complete callback */
+ if (hdma->XferCpltCallback != NULL)
+ {
+ /* Channel Transfer Complete callback */
+ hdma->XferCpltCallback(hdma);
+ }
+ }
+ }
+
+ /* Manage error case ************************************************************************************************/
+ if (hdma->ErrorCode != HAL_DMA_ERROR_NONE)
+ {
+ /* Reset the channel internal state and reset the FIFO */
+ hdma->Instance->CCR |= DMA_CCR_RESET;
+
+ if ((hdma->Instance->CCR & DMA_CCR_EN) != 0U)
+ {
+ /* Update the DMA channel state */
+ hdma->State = HAL_DMA_STATE_ERROR;
+ }
+ else
+ {
+ /* Update the DMA channel state */
+ hdma->State = HAL_DMA_STATE_READY;
+ }
+
+ /* Check DMA channel transfer mode */
+ if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ /* Update the linked-list queue state */
+ hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ /* Check transfer error callback */
+ if (hdma->XferErrorCallback != NULL)
+ {
+ /* Transfer error callback */
+ hdma->XferErrorCallback(hdma);
+ }
+ }
+}
+
+/**
+ * @brief Register callback according to specified ID.
+ * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+ * specified DMA Channel.
+ * @param CallbackID : User Callback identifier which could be a value of HAL_DMA_CallbackIDTypeDef enumeration.
+ * @param pCallback : Pointer to private callback function.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *const hdma,
+ HAL_DMA_CallbackIDTypeDef CallbackID,
+ void (*const pCallback)(DMA_HandleTypeDef *const _hdma))
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the DMA peripheral handle parameter */
+ if (hdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ /* Check DMA channel state */
+ if (hdma->State == HAL_DMA_STATE_READY)
+ {
+ /* Check callback ID */
+ switch (CallbackID)
+ {
+ case HAL_DMA_XFER_CPLT_CB_ID:
+ {
+ /* Register transfer complete callback */
+ hdma->XferCpltCallback = pCallback;
+ break;
+ }
+
+ case HAL_DMA_XFER_HALFCPLT_CB_ID:
+ {
+ /* Register half transfer callback */
+ hdma->XferHalfCpltCallback = pCallback;
+ break;
+ }
+
+ case HAL_DMA_XFER_ERROR_CB_ID:
+ {
+ /* Register transfer error callback */
+ hdma->XferErrorCallback = pCallback;
+ break;
+ }
+
+ case HAL_DMA_XFER_ABORT_CB_ID:
+ {
+ /* Register abort callback */
+ hdma->XferAbortCallback = pCallback;
+ break;
+ }
+
+ case HAL_DMA_XFER_SUSPEND_CB_ID:
+ {
+ /* Register suspend callback */
+ hdma->XferSuspendCallback = pCallback;
+ break;
+ }
+
+ default:
+ {
+ /* Update error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ }
+ else
+ {
+ /* Update error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdma);
+
+ return status;
+}
+
+/**
+ * @brief Unregister callback according to specified ID.
+ * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+ * specified DMA Channel.
+ * @param CallbackID : User Callback identifier which could be a value of HAL_DMA_CallbackIDTypeDef enum.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *const hdma,
+ HAL_DMA_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the DMA peripheral handle parameter */
+ if (hdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ /* Check DMA channel state */
+ if (hdma->State == HAL_DMA_STATE_READY)
+ {
+ /* Check callback ID */
+ switch (CallbackID)
+ {
+ case HAL_DMA_XFER_CPLT_CB_ID:
+ {
+ /* UnRegister transfer complete callback */
+ hdma->XferCpltCallback = NULL;
+ break;
+ }
+
+ case HAL_DMA_XFER_HALFCPLT_CB_ID:
+ {
+ /* UnRegister half transfer callback */
+ hdma->XferHalfCpltCallback = NULL;
+ break;
+ }
+
+ case HAL_DMA_XFER_ERROR_CB_ID:
+ {
+ /* UnRegister transfer error callback */
+ hdma->XferErrorCallback = NULL;
+ break;
+ }
+
+ case HAL_DMA_XFER_ABORT_CB_ID:
+ {
+ /* UnRegister abort callback */
+ hdma->XferAbortCallback = NULL;
+ break;
+ }
+
+ case HAL_DMA_XFER_SUSPEND_CB_ID:
+ {
+ /* UnRegister suspend callback */
+ hdma->XferSuspendCallback = NULL;
+ break;
+ }
+
+ case HAL_DMA_XFER_ALL_CB_ID:
+ {
+ /* UnRegister all available callbacks */
+ hdma->XferCpltCallback = NULL;
+ hdma->XferHalfCpltCallback = NULL;
+ hdma->XferErrorCallback = NULL;
+ hdma->XferAbortCallback = NULL;
+ hdma->XferSuspendCallback = NULL;
+ break;
+ }
+
+ default:
+ {
+ /* Update error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ }
+ else
+ {
+ /* Update error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdma);
+
+ return status;
+}
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Exported_Functions_Group3
+ *
+@verbatim
+ ======================================================================================================================
+ ############### State and Errors functions ###############
+ ======================================================================================================================
+ [..]
+ This section provides functions allowing to :
+ (+) Check the DMA state
+ (+) Get error code
+
+ [..]
+ (+) The HAL_DMA_GetState() function allows to get the DMA channel state.
+ (+) The HAL_DMA_DeInit() function allows to get the DMA channel error code.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the DMA channel state.
+ * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+ * specified DMA Channel.
+ * @retval DMA state.
+ */
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef const *const hdma)
+{
+ /* Return the DMA channel state */
+ return hdma->State;
+}
+
+/**
+ * @brief Return the DMA channel error code.
+ * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+ * specified DMA Channel.
+ * @retval DMA Error Code.
+ */
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef const *const hdma)
+{
+ /* Return the DMA channel error code */
+ return hdma->ErrorCode;
+}
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Exported_Functions_Group4
+ *
+@verbatim
+ ======================================================================================================================
+ ############### DMA Attributes functions ###############
+ ======================================================================================================================
+ [..]
+ This section provides functions allowing to :
+ (+) Configure DMA channel secure and privilege attributes.
+ (+) Get DMA channel secure and privilege attributes.
+ (+) Lock DMA channel secure and privilege attributes configuration.
+ (+) Check whether DMA channel secure and privilege attributes configuration is locked or not.
+
+ [..]
+ (+) The HAL_DMA_ConfigChannelAttributes() function allows to configure DMA channel security and privilege
+ attributes.
+ (+) The HAL_DMA_GetConfigChannelAttributes() function allows to get DMA channel security and privilege attributes
+ configuration.
+ (+) The HAL_DMA_LockChannelAttributes() function allows to lock the DMA channel security and privilege attributes.
+ (+) The HAL_DMA_GetLockChannelAttributes() function allows to get the DMA channel security and privilege
+ attributes lock status.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the DMA channel security and privilege attribute(s).
+ * @note These attributes cannot be modified when the corresponding lock state is enabled.
+ * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for
+ * the specified DMA Channel.
+ * @param ChannelAttributes : Specifies the DMA channel secure/privilege attributes.
+ * This parameter can be a one or a combination of @ref DMA_Channel_Attributes.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *const hdma, uint32_t ChannelAttributes)
+{
+ DMA_TypeDef *p_dma_instance;
+ uint32_t channel_idx;
+
+ /* Check the DMA peripheral handle parameter */
+ if (hdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DMA_ATTRIBUTES(ChannelAttributes));
+
+ /* Get DMA instance */
+ p_dma_instance = GET_DMA_INSTANCE(hdma);
+
+ /* Get channel index */
+ channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU);
+
+ /* Check DMA channel privilege attribute management */
+ if ((ChannelAttributes & DMA_CHANNEL_ATTR_PRIV_MASK) == DMA_CHANNEL_ATTR_PRIV_MASK)
+ {
+ /* Configure DMA channel privilege attribute */
+ if ((ChannelAttributes & DMA_CHANNEL_PRIV) == DMA_CHANNEL_PRIV)
+ {
+ p_dma_instance->PRIVCFGR |= channel_idx;
+ }
+ else
+ {
+ p_dma_instance->PRIVCFGR &= (~channel_idx);
+ }
+ }
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ /* Check DMA channel security attribute management */
+ if ((ChannelAttributes & DMA_CHANNEL_ATTR_SEC_MASK) == DMA_CHANNEL_ATTR_SEC_MASK)
+ {
+ /* Configure DMA channel security attribute */
+ if ((ChannelAttributes & DMA_CHANNEL_SEC) == DMA_CHANNEL_SEC)
+ {
+ p_dma_instance->SECCFGR |= channel_idx;
+ }
+ else
+ {
+ p_dma_instance->SECCFGR &= (~channel_idx);
+ }
+ }
+
+ /* Channel source security attribute management */
+ if ((ChannelAttributes & DMA_CHANNEL_ATTR_SEC_SRC_MASK) == DMA_CHANNEL_ATTR_SEC_SRC_MASK)
+ {
+ /* Configure DMA channel source security attribute */
+ if ((ChannelAttributes & DMA_CHANNEL_SRC_SEC) == DMA_CHANNEL_SRC_SEC)
+ {
+ hdma->Instance->CTR1 |= DMA_CTR1_SSEC;
+ }
+ else
+ {
+ hdma->Instance->CTR1 &= (~DMA_CTR1_SSEC);
+ }
+ }
+
+ /* Channel destination security attribute management */
+ if ((ChannelAttributes & DMA_CHANNEL_ATTR_SEC_DEST_MASK) == DMA_CHANNEL_ATTR_SEC_DEST_MASK)
+ {
+ /* Configure DMA channel destination security attribute */
+ if ((ChannelAttributes & DMA_CHANNEL_DEST_SEC) == DMA_CHANNEL_DEST_SEC)
+ {
+ hdma->Instance->CTR1 |= DMA_CTR1_DSEC;
+ }
+ else
+ {
+ hdma->Instance->CTR1 &= (~DMA_CTR1_DSEC);
+ }
+ }
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get the DMA channel security and privilege attributes.
+ * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information
+ * for the specified DMA Channel.
+ * @param pChannelAttributes : Pointer to the returned attributes.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *const hdma,
+ uint32_t *const pChannelAttributes)
+{
+ DMA_TypeDef *p_dma_instance;
+ uint32_t attributes;
+ uint32_t channel_idx;
+
+ /* Check the DMA peripheral handle and channel attributes parameters */
+ if ((hdma == NULL) || (pChannelAttributes == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Get DMA instance */
+ p_dma_instance = GET_DMA_INSTANCE(hdma);
+
+ /* Get channel index */
+ channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU);
+
+ /* Get DMA channel privilege attribute */
+ attributes = ((p_dma_instance->PRIVCFGR & channel_idx) == 0U) ? DMA_CHANNEL_NPRIV : DMA_CHANNEL_PRIV;
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ /* Get DMA channel security attribute */
+ attributes |= ((p_dma_instance->SECCFGR & channel_idx) == 0U) ? DMA_CHANNEL_NSEC : DMA_CHANNEL_SEC;
+
+ /* Get DMA channel source security attribute */
+ attributes |= ((hdma->Instance->CTR1 & DMA_CTR1_SSEC) == 0U) ? DMA_CHANNEL_SRC_NSEC : DMA_CHANNEL_SRC_SEC;
+
+ /* Get DMA channel destination security attribute */
+ attributes |= ((hdma->Instance->CTR1 & DMA_CTR1_DSEC) == 0U) ? DMA_CHANNEL_DEST_NSEC : DMA_CHANNEL_DEST_SEC;
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+ /* return value */
+ *pChannelAttributes = attributes;
+
+ return HAL_OK;
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ * @brief Lock the DMA channel security and privilege attribute(s).
+ * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+ * specified DMA Channel.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const hdma)
+{
+ DMA_TypeDef *p_dma_instance;
+ uint32_t channel_idx;
+
+ /* Check the DMA peripheral handle parameter */
+ if (hdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Get DMA instance */
+ p_dma_instance = GET_DMA_INSTANCE(hdma);
+
+ /* Get channel index */
+ channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU);
+
+ /* Lock the DMA channel privilege and security attributes */
+ p_dma_instance->RCFGLOCKR |= channel_idx;
+
+ return HAL_OK;
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/**
+ * @brief Get the security and privilege attribute lock state of a DMA channel.
+ * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+ * specified DMA Channel.
+ * @param pLockState : Pointer to lock state (returned value can be DMA_CHANNEL_ATTRIBUTE_UNLOCKED or
+ * DMA_CHANNEL_ATTRIBUTE_LOCKED).
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *const hdma, uint32_t *const pLockState)
+{
+ DMA_TypeDef *p_dma_instance;
+ uint32_t channel_idx;
+
+ /* Check the DMA peripheral handle and lock state parameters */
+ if ((hdma == NULL) || (pLockState == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Get DMA instance */
+ p_dma_instance = GET_DMA_INSTANCE(hdma);
+
+ /* Get channel index */
+ channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU);
+
+ /* Get channel lock attribute state */
+ *pLockState = ((p_dma_instance->RCFGLOCKR & channel_idx) == 0U) ? DMA_CHANNEL_ATTRIBUTE_UNLOCKED : \
+ DMA_CHANNEL_ATTRIBUTE_LOCKED;
+
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private functions -------------------------------------------------------------------------------------------------*/
+/** @defgroup DMA_Private_Functions DMA Private Functions
+ * @brief DMA Private Functions
+ * @{
+ */
+
+/**
+ * @brief Set the DMA channel normal transfer parameters.
+ * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+ * specified DMA Channel.
+ * @param SrcAddress : The source data address.
+ * @param DstAddress : The destination data address.
+ * @param SrcDataSize : The length of data to be transferred from source to destination in bytes.
+ * @retval None.
+ */
+static void DMA_SetConfig(DMA_HandleTypeDef const *const hdma,
+ uint32_t SrcAddress,
+ uint32_t DstAddress,
+ uint32_t SrcDataSize)
+{
+ /* Configure the DMA channel data size */
+ MODIFY_REG(hdma->Instance->CBR1, DMA_CBR1_BNDT, (SrcDataSize & DMA_CBR1_BNDT));
+
+ /* Clear all interrupt flags */
+ __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP |
+ DMA_FLAG_TO);
+
+ /* Configure DMA channel source address */
+ hdma->Instance->CSAR = SrcAddress;
+
+ /* Configure DMA channel destination address */
+ hdma->Instance->CDAR = DstAddress;
+}
+
+/**
+ * @brief Initialize the DMA channel in normal mode according to the specified parameters in the DMA_InitTypeDef.
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+ * specified DMA Channel.
+ * @retval None.
+ */
+static void DMA_Init(DMA_HandleTypeDef const *const hdma)
+{
+ uint32_t tmpreg;
+
+ /* Prepare DMA Channel Control Register (CCR) value *****************************************************************/
+ tmpreg = hdma->Init.Priority;
+
+ /* Write DMA Channel Control Register (CCR) */
+ MODIFY_REG(hdma->Instance->CCR, DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM, tmpreg);
+
+
+ /* Prepare DMA Channel Transfer Register (CTR1) value ***************************************************************/
+ tmpreg = hdma->Init.DestInc | hdma->Init.DestDataWidth | hdma->Init.SrcInc | hdma->Init.SrcDataWidth;
+
+ /* Add parameters specific to GPDMA */
+ if (IS_GPDMA_INSTANCE(hdma->Instance) != 0U)
+ {
+ tmpreg |= (hdma->Init.TransferAllocatedPort |
+ (((hdma->Init.DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1) |
+ (((hdma->Init.SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1));
+ }
+
+ /* Write DMA Channel Transfer Register 1 (CTR1) */
+ MODIFY_REG(hdma->Instance->CTR1, ~(DMA_CTR1_SSEC | DMA_CTR1_DSEC), tmpreg);
+
+ /* Prepare DMA Channel Transfer Register 2 (CTR2) value *************************************************************/
+ tmpreg = hdma->Init.BlkHWRequest | (hdma->Init.Request & DMA_CTR2_REQSEL) | hdma->Init.TransferEventMode;
+
+ /* Memory to Peripheral Transfer */
+ if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+ {
+ if (IS_GPDMA_INSTANCE(hdma->Instance) != 0U)
+ {
+ tmpreg |= DMA_CTR2_DREQ;
+ }
+ }
+ /* Memory to Memory Transfer */
+ else if ((hdma->Init.Direction) == DMA_MEMORY_TO_MEMORY)
+ {
+ tmpreg |= DMA_CTR2_SWREQ;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Write DMA Channel Transfer Register 2 (CTR2) */
+ MODIFY_REG(hdma->Instance->CTR2, (DMA_CTR2_TCEM | DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGSEL | DMA_CTR2_TRIGM |
+ DMA_CTR2_BREQ | DMA_CTR2_DREQ | DMA_CTR2_SWREQ | DMA_CTR2_REQSEL), tmpreg);
+
+
+ /* Write DMA Channel Block Register 1 (CBR1) ************************************************************************/
+ WRITE_REG(hdma->Instance->CBR1, 0U);
+
+
+ /* If 2D Addressing is supported by current channel */
+ if (IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) != 0U)
+ {
+ /* Write DMA Channel Transfer Register 3 (CTR3) *******************************************************************/
+ WRITE_REG(hdma->Instance->CTR3, 0U);
+
+
+ /* Write DMA Channel Block Register 2 (CBR2) **********************************************************************/
+ WRITE_REG(hdma->Instance->CBR2, 0U);
+ }
+
+
+ /* Write DMA Channel linked-list address register (CLLR) ************************************************************/
+ WRITE_REG(hdma->Instance->CLLR, 0U);
+}
+/**
+ * @}
+ */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma2d.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma2d.c
new file mode 100644
index 00000000..b47cc6e2
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma2d.c
@@ -0,0 +1,2176 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_dma2d.c
+ * @author MCD Application Team
+ * @brief DMA2D HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the DMA2D peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State and Errors functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Program the required configuration through the following parameters:
+ the transfer mode, the output color mode and the output offset using
+ HAL_DMA2D_Init() function.
+
+ (#) Program the required configuration through the following parameters:
+ the input color mode, the input color, the input alpha value, the alpha mode,
+ the red/blue swap mode, the inverted alpha mode and the input offset using
+ HAL_DMA2D_ConfigLayer() function for foreground or/and background layer.
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (#) Configure pdata parameter (explained hereafter), destination and data length
+ and enable the transfer using HAL_DMA2D_Start().
+ (#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage
+ user can specify the value of timeout according to his end application.
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (#) Configure pdata parameter, destination and data length and enable
+ the transfer using HAL_DMA2D_Start_IT().
+ (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine.
+ (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can
+ add his own function by customization of function pointer XferCpltCallback (member
+ of DMA2D handle structure).
+ (#) In case of error, the HAL_DMA2D_IRQHandler() function calls the callback
+ XferErrorCallback.
+
+ -@- In Register-to-Memory transfer mode, pdata parameter is the register
+ color, in Memory-to-memory or Memory-to-Memory with pixel format
+ conversion pdata is the source address.
+
+ -@- Configure the foreground source address, the background source address,
+ the destination and data length then Enable the transfer using
+ HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()
+ in interrupt mode.
+
+ -@- HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions
+ are used if the memory to memory with blending transfer mode is selected.
+
+ (#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling
+ mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode.
+
+ (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent().
+
+ (#) Optionally, configure the dead time value in the AHB clock cycle inserted between two
+ consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime()
+ and enable/disable the functionality with the APIs HAL_DMA2D_EnableDeadTime() or
+ HAL_DMA2D_DisableDeadTime().
+
+ (#) The transfer can be suspended, resumed and aborted using the following
+ functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().
+
+ (#) The CLUT loading can be suspended, resumed and aborted using the following
+ functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(),
+ HAL_DMA2D_CLUTLoading_Abort().
+
+ (#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState().
+
+ (#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError().
+
+ *** DMA2D HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in DMA2D HAL driver :
+
+ (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.
+ (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.
+ (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.
+ (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.
+ (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
+ (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not.
+
+ *** Callback registration ***
+ ===================================
+ [..]
+ (#) The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use function @ref HAL_DMA2D_RegisterCallback() to register a user callback.
+
+ (#) Function @ref HAL_DMA2D_RegisterCallback() allows to register following callbacks:
+ (+) XferCpltCallback : callback for transfer complete.
+ (+) XferErrorCallback : callback for transfer error.
+ (+) LineEventCallback : callback for line event.
+ (+) CLUTLoadingCpltCallback : callback for CLUT loading completion.
+ (+) MspInitCallback : DMA2D MspInit.
+ (+) MspDeInitCallback : DMA2D MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ (#) Use function @ref HAL_DMA2D_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function.
+ @ref HAL_DMA2D_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) XferCpltCallback : callback for transfer complete.
+ (+) XferErrorCallback : callback for transfer error.
+ (+) LineEventCallback : callback for line event.
+ (+) CLUTLoadingCpltCallback : callback for CLUT loading completion.
+ (+) MspInitCallback : DMA2D MspInit.
+ (+) MspDeInitCallback : DMA2D MspDeInit.
+
+ (#) By default, after the @ref HAL_DMA2D_Init and if the state is HAL_DMA2D_STATE_RESET
+ all callbacks are reset to the corresponding legacy weak (surcharged) functions:
+ examples @ref HAL_DMA2D_LineEventCallback(), @ref HAL_DMA2D_CLUTLoadingCpltCallback()
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_DMA2D_Init
+ and @ref HAL_DMA2D_DeInit only when these callbacks are null (not registered beforehand)
+ If not, MspInit or MspDeInit are not null, the @ref HAL_DMA2D_Init and @ref HAL_DMA2D_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+ Exception as well for Transfer Completion and Transfer Error callbacks that are not defined
+ as weak (surcharged) functions. They must be defined by the user to be resorted to.
+
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_DMA2D_RegisterCallback before calling @ref HAL_DMA2D_DeInit
+ or @ref HAL_DMA2D_Init function.
+
+ When The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
+ [..]
+ (@) You can refer to the DMA2D HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+#if defined (DMA2D)
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup DMA2D DMA2D
+ * @brief DMA2D HAL module driver
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup DMA2D_Private_Constants DMA2D Private Constants
+ * @{
+ */
+
+/** @defgroup DMA2D_TimeOut DMA2D Time Out
+ * @{
+ */
+#define DMA2D_TIMEOUT_ABORT (1000U) /*!< 1s */
+#define DMA2D_TIMEOUT_SUSPEND (1000U) /*!< 1s */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup DMA2D_Private_Functions DMA2D Private Functions
+ * @{
+ */
+static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
+ uint32_t Height);
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions
+ * @{
+ */
+
+/** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the DMA2D
+ (+) De-initialize the DMA2D
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the DMA2D according to the specified
+ * parameters in the DMA2D_InitTypeDef and create the associated handle.
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
+{
+ /* Check the DMA2D peripheral state */
+ if (hdma2d == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance));
+ assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode));
+ assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode));
+ assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));
+ assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->Init.AlphaInverted));
+ assert_param(IS_DMA2D_RB_SWAP(hdma2d->Init.RedBlueSwap));
+ assert_param(IS_DMA2D_LOM_MODE(hdma2d->Init.LineOffsetMode));
+ assert_param(IS_DMA2D_BYTES_SWAP(hdma2d->Init.BytesSwap));
+
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+ if (hdma2d->State == HAL_DMA2D_STATE_RESET)
+ {
+ /* Reset Callback pointers in HAL_DMA2D_STATE_RESET only */
+ hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback;
+ hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback;
+ if (hdma2d->MspInitCallback == NULL)
+ {
+ hdma2d->MspInitCallback = HAL_DMA2D_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hdma2d->MspInitCallback(hdma2d);
+ }
+#else
+ if (hdma2d->State == HAL_DMA2D_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hdma2d->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware */
+ HAL_DMA2D_MspInit(hdma2d);
+ }
+#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
+
+ /* Change DMA2D peripheral state */
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+ /* DMA2D CR register configuration -------------------------------------------*/
+ MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE | DMA2D_CR_LOM, hdma2d->Init.Mode | hdma2d->Init.LineOffsetMode);
+
+ /* DMA2D OPFCCR register configuration ---------------------------------------*/
+ MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM | DMA2D_OPFCCR_SB,
+ hdma2d->Init.ColorMode | hdma2d->Init.BytesSwap);
+
+ /* DMA2D OOR register configuration ------------------------------------------*/
+ MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
+ /* DMA2D OPFCCR AI and RBS fields setting (Output Alpha Inversion)*/
+ MODIFY_REG(hdma2d->Instance->OPFCCR, (DMA2D_OPFCCR_AI | DMA2D_OPFCCR_RBS),
+ ((hdma2d->Init.AlphaInverted << DMA2D_OPFCCR_AI_Pos) | \
+ (hdma2d->Init.RedBlueSwap << DMA2D_OPFCCR_RBS_Pos)));
+
+
+ /* Update error code */
+ hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
+
+ /* Initialize the DMA2D state*/
+ hdma2d->State = HAL_DMA2D_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deinitializes the DMA2D peripheral registers to their default reset
+ * values.
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @retval None
+ */
+
+HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
+{
+
+ /* Check the DMA2D peripheral state */
+ if (hdma2d == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Before aborting any DMA2D transfer or CLUT loading, check
+ first whether or not DMA2D clock is enabled */
+ if (__HAL_RCC_DMA2D_IS_CLK_ENABLED())
+ {
+ /* Abort DMA2D transfer if any */
+ if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)
+ {
+ if (HAL_DMA2D_Abort(hdma2d) != HAL_OK)
+ {
+ /* Issue when aborting DMA2D transfer */
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Abort background CLUT loading if any */
+ if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
+ {
+ if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0U) != HAL_OK)
+ {
+ /* Issue when aborting background CLUT loading */
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Abort foreground CLUT loading if any */
+ if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
+ {
+ if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1U) != HAL_OK)
+ {
+ /* Issue when aborting foreground CLUT loading */
+ return HAL_ERROR;
+ }
+ }
+ }
+ }
+ }
+
+ /* Reset DMA2D control registers*/
+ hdma2d->Instance->CR = 0U;
+ hdma2d->Instance->IFCR = 0x3FU;
+ hdma2d->Instance->FGOR = 0U;
+ hdma2d->Instance->BGOR = 0U;
+ hdma2d->Instance->FGPFCCR = 0U;
+ hdma2d->Instance->BGPFCCR = 0U;
+ hdma2d->Instance->OPFCCR = 0U;
+
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+
+ if (hdma2d->MspDeInitCallback == NULL)
+ {
+ hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit;
+ }
+
+ /* DeInit the low level hardware */
+ hdma2d->MspDeInitCallback(hdma2d);
+
+#else
+ /* Carry on with de-initialization of low level hardware */
+ HAL_DMA2D_MspDeInit(hdma2d);
+#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
+
+ /* Update error code */
+ hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
+
+ /* Initialize the DMA2D state*/
+ hdma2d->State = HAL_DMA2D_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdma2d);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the DMA2D MSP.
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @retval None
+ */
+__weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdma2d);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_DMA2D_MspInit can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief DeInitializes the DMA2D MSP.
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @retval None
+ */
+__weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdma2d);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_DMA2D_MspDeInit can be implemented in the user file.
+ */
+}
+
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User DMA2D Callback
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hdma2d DMA2D handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_DMA2D_TRANSFERCOMPLETE_CB_ID DMA2D transfer complete Callback ID
+ * @arg @ref HAL_DMA2D_TRANSFERERROR_CB_ID DMA2D transfer error Callback ID
+ * @arg @ref HAL_DMA2D_LINEEVENT_CB_ID DMA2D line event Callback ID
+ * @arg @ref HAL_DMA2D_CLUTLOADINGCPLT_CB_ID DMA2D CLUT loading completion Callback ID
+ * @arg @ref HAL_DMA2D_MSPINIT_CB_ID DMA2D MspInit callback ID
+ * @arg @ref HAL_DMA2D_MSPDEINIT_CB_ID DMA2D MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID,
+ pDMA2D_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hdma2d);
+
+ if (HAL_DMA2D_STATE_READY == hdma2d->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID :
+ hdma2d->XferCpltCallback = pCallback;
+ break;
+
+ case HAL_DMA2D_TRANSFERERROR_CB_ID :
+ hdma2d->XferErrorCallback = pCallback;
+ break;
+
+ case HAL_DMA2D_LINEEVENT_CB_ID :
+ hdma2d->LineEventCallback = pCallback;
+ break;
+
+ case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID :
+ hdma2d->CLUTLoadingCpltCallback = pCallback;
+ break;
+
+ case HAL_DMA2D_MSPINIT_CB_ID :
+ hdma2d->MspInitCallback = pCallback;
+ break;
+
+ case HAL_DMA2D_MSPDEINIT_CB_ID :
+ hdma2d->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_DMA2D_STATE_RESET == hdma2d->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DMA2D_MSPINIT_CB_ID :
+ hdma2d->MspInitCallback = pCallback;
+ break;
+
+ case HAL_DMA2D_MSPDEINIT_CB_ID :
+ hdma2d->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdma2d);
+ return status;
+}
+
+/**
+ * @brief Unregister a DMA2D Callback
+ * DMA2D Callback is redirected to the weak (surcharged) predefined callback
+ * @param hdma2d DMA2D handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_DMA2D_TRANSFERCOMPLETE_CB_ID DMA2D transfer complete Callback ID
+ * @arg @ref HAL_DMA2D_TRANSFERERROR_CB_ID DMA2D transfer error Callback ID
+ * @arg @ref HAL_DMA2D_LINEEVENT_CB_ID DMA2D line event Callback ID
+ * @arg @ref HAL_DMA2D_CLUTLOADINGCPLT_CB_ID DMA2D CLUT loading completion Callback ID
+ * @arg @ref HAL_DMA2D_MSPINIT_CB_ID DMA2D MspInit callback ID
+ * @arg @ref HAL_DMA2D_MSPDEINIT_CB_ID DMA2D MspDeInit callback ID
+ * @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hdma2d);
+
+ if (HAL_DMA2D_STATE_READY == hdma2d->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID :
+ hdma2d->XferCpltCallback = NULL;
+ break;
+
+ case HAL_DMA2D_TRANSFERERROR_CB_ID :
+ hdma2d->XferErrorCallback = NULL;
+ break;
+
+ case HAL_DMA2D_LINEEVENT_CB_ID :
+ hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback;
+ break;
+
+ case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID :
+ hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback;
+ break;
+
+ case HAL_DMA2D_MSPINIT_CB_ID :
+ hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
+ break;
+
+ case HAL_DMA2D_MSPDEINIT_CB_ID :
+ hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_DMA2D_STATE_RESET == hdma2d->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DMA2D_MSPINIT_CB_ID :
+ hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
+ break;
+
+ case HAL_DMA2D_MSPDEINIT_CB_ID :
+ hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdma2d);
+ return status;
+}
+#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions
+ * @brief IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure the pdata, destination address and data size then
+ start the DMA2D transfer.
+ (+) Configure the source for foreground and background, destination address
+ and data size then start a MultiBuffer DMA2D transfer.
+ (+) Configure the pdata, destination address and data size then
+ start the DMA2D transfer with interrupt.
+ (+) Configure the source for foreground and background, destination address
+ and data size then start a MultiBuffer DMA2D transfer with interrupt.
+ (+) Abort DMA2D transfer.
+ (+) Suspend DMA2D transfer.
+ (+) Resume DMA2D transfer.
+ (+) Enable CLUT transfer.
+ (+) Configure CLUT loading then start transfer in polling mode.
+ (+) Configure CLUT loading then start transfer in interrupt mode.
+ (+) Abort DMA2D CLUT loading.
+ (+) Suspend DMA2D CLUT loading.
+ (+) Resume DMA2D CLUT loading.
+ (+) Poll for transfer complete.
+ (+) handle DMA2D interrupt request.
+ (+) Transfer watermark callback.
+ (+) CLUT Transfer Complete callback.
+
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start the DMA2D Transfer.
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @param pdata Configure the source memory Buffer address if
+ * Memory-to-Memory or Memory-to-Memory with pixel format
+ * conversion mode is selected, or configure
+ * the color value if Register-to-Memory mode is selected.
+ * @param DstAddress The destination memory Buffer address.
+ * @param Width The width of data to be transferred from source
+ * to destination (expressed in number of pixels per line).
+ * @param Height The height of data to be transferred from source to destination (expressed in number of lines).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
+ uint32_t Height)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA2D_LINE(Height));
+ assert_param(IS_DMA2D_PIXEL(Width));
+
+ /* Process locked */
+ __HAL_LOCK(hdma2d);
+
+ /* Change DMA2D peripheral state */
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+ /* Configure the source, destination address and the data size */
+ DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
+
+ /* Enable the Peripheral */
+ __HAL_DMA2D_ENABLE(hdma2d);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Start the DMA2D Transfer with interrupt enabled.
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @param pdata Configure the source memory Buffer address if
+ * the Memory-to-Memory or Memory-to-Memory with pixel format
+ * conversion mode is selected, or configure
+ * the color value if Register-to-Memory mode is selected.
+ * @param DstAddress The destination memory Buffer address.
+ * @param Width The width of data to be transferred from source
+ * to destination (expressed in number of pixels per line).
+ * @param Height The height of data to be transferred from source to destination (expressed in number of lines).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
+ uint32_t Height)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA2D_LINE(Height));
+ assert_param(IS_DMA2D_PIXEL(Width));
+
+ /* Process locked */
+ __HAL_LOCK(hdma2d);
+
+ /* Change DMA2D peripheral state */
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+ /* Configure the source, destination address and the data size */
+ DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
+
+ /* Enable the transfer complete, transfer error and configuration error interrupts */
+ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE);
+
+ /* Enable the Peripheral */
+ __HAL_DMA2D_ENABLE(hdma2d);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Start the multi-source DMA2D Transfer.
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @param SrcAddress1 The source memory Buffer address for the foreground layer.
+ * @param SrcAddress2 The source memory Buffer address for the background layer.
+ * @param DstAddress The destination memory Buffer address.
+ * @param Width The width of data to be transferred from source
+ * to destination (expressed in number of pixels per line).
+ * @param Height The height of data to be transferred from source to destination (expressed in number of lines).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
+ uint32_t DstAddress, uint32_t Width, uint32_t Height)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA2D_LINE(Height));
+ assert_param(IS_DMA2D_PIXEL(Width));
+
+ /* Process locked */
+ __HAL_LOCK(hdma2d);
+
+ /* Change DMA2D peripheral state */
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+ if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG)
+ {
+ /*blending & fixed FG*/
+ WRITE_REG(hdma2d->Instance->FGCOLR, SrcAddress1);
+ /* Configure the source, destination address and the data size */
+ DMA2D_SetConfig(hdma2d, SrcAddress2, DstAddress, Width, Height);
+ }
+ else if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_BG)
+ {
+ /*blending & fixed BG*/
+ WRITE_REG(hdma2d->Instance->BGCOLR, SrcAddress2);
+ /* Configure the source, destination address and the data size */
+ DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
+ }
+ else
+ {
+ /* Configure DMA2D Stream source2 address */
+ WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
+
+ /* Configure the source, destination address and the data size */
+ DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_DMA2D_ENABLE(hdma2d);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Start the multi-source DMA2D Transfer with interrupt enabled.
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @param SrcAddress1 The source memory Buffer address for the foreground layer.
+ * @param SrcAddress2 The source memory Buffer address for the background layer.
+ * @param DstAddress The destination memory Buffer address.
+ * @param Width The width of data to be transferred from source
+ * to destination (expressed in number of pixels per line).
+ * @param Height The height of data to be transferred from source to destination (expressed in number of lines).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
+ uint32_t DstAddress, uint32_t Width, uint32_t Height)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA2D_LINE(Height));
+ assert_param(IS_DMA2D_PIXEL(Width));
+
+ /* Process locked */
+ __HAL_LOCK(hdma2d);
+
+ /* Change DMA2D peripheral state */
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+ if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG)
+ {
+ /*blending & fixed FG*/
+ WRITE_REG(hdma2d->Instance->FGCOLR, SrcAddress1);
+ /* Configure the source, destination address and the data size */
+ DMA2D_SetConfig(hdma2d, SrcAddress2, DstAddress, Width, Height);
+ }
+ else if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_BG)
+ {
+ /*blending & fixed BG*/
+ WRITE_REG(hdma2d->Instance->BGCOLR, SrcAddress2);
+ /* Configure the source, destination address and the data size */
+ DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
+ }
+ else
+ {
+ WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
+
+ /* Configure the source, destination address and the data size */
+ DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
+ }
+
+ /* Enable the transfer complete, transfer error and configuration error interrupts */
+ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE);
+
+ /* Enable the Peripheral */
+ __HAL_DMA2D_ENABLE(hdma2d);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort the DMA2D Transfer.
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
+{
+ uint32_t tickstart;
+
+ /* Abort the DMA2D transfer */
+ /* START bit is reset to make sure not to set it again, in the event the HW clears it
+ between the register read and the register write by the CPU (writing 0 has no
+ effect on START bitvalue) */
+ MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check if the DMA2D is effectively disabled */
+ while ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_ABORT)
+ {
+ /* Update error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
+
+ /* Change the DMA2D state */
+ hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma2d);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */
+ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE);
+
+ /* Change the DMA2D state*/
+ hdma2d->State = HAL_DMA2D_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma2d);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Suspend the DMA2D Transfer.
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
+{
+ uint32_t tickstart;
+
+ /* Suspend the DMA2D transfer */
+ /* START bit is reset to make sure not to set it again, in the event the HW clears it
+ between the register read and the register write by the CPU (writing 0 has no
+ effect on START bitvalue). */
+ MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check if the DMA2D is effectively suspended */
+ while ((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == DMA2D_CR_START)
+ {
+ if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_SUSPEND)
+ {
+ /* Update error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
+
+ /* Change the DMA2D state */
+ hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
+ if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
+ {
+ hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
+ }
+ else
+ {
+ /* Make sure SUSP bit is cleared since it is meaningless
+ when no transfer is on-going */
+ CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resume the DMA2D Transfer.
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
+{
+ /* Check the SUSP and START bits */
+ if ((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START))
+ {
+ /* Ongoing transfer is suspended: change the DMA2D state before resuming */
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+ }
+
+ /* Resume the DMA2D transfer */
+ /* START bit is reset to make sure not to set it again, in the event the HW clears it
+ between the register read and the register write by the CPU (writing 0 has no
+ effect on START bitvalue). */
+ CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP | DMA2D_CR_START));
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Enable the DMA2D CLUT Transfer.
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @param LayerIdx DMA2D Layer index.
+ * This parameter can be one of the following values:
+ * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA2D_LAYER(LayerIdx));
+
+ /* Process locked */
+ __HAL_LOCK(hdma2d);
+
+ /* Change DMA2D peripheral state */
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+ if (LayerIdx == DMA2D_BACKGROUND_LAYER)
+ {
+ /* Enable the background CLUT loading */
+ SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
+ }
+ else
+ {
+ /* Enable the foreground CLUT loading */
+ SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Start DMA2D CLUT Loading.
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
+ * the configuration information for the color look up table.
+ * @param LayerIdx DMA2D Layer index.
+ * This parameter can be one of the following values:
+ * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA2D_LAYER(LayerIdx));
+ assert_param(IS_DMA2D_CLUT_CM(CLUTCfg->CLUTColorMode));
+ assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg->Size));
+
+ /* Process locked */
+ __HAL_LOCK(hdma2d);
+
+ /* Change DMA2D peripheral state */
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+ /* Configure the CLUT of the background DMA2D layer */
+ if (LayerIdx == DMA2D_BACKGROUND_LAYER)
+ {
+ /* Write background CLUT memory address */
+ WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg->pCLUT);
+
+ /* Write background CLUT size and CLUT color mode */
+ MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
+ ((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
+
+ /* Enable the CLUT loading for the background */
+ SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
+ }
+ /* Configure the CLUT of the foreground DMA2D layer */
+ else
+ {
+ /* Write foreground CLUT memory address */
+ WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg->pCLUT);
+
+ /* Write foreground CLUT size and CLUT color mode */
+ MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
+ ((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
+
+ /* Enable the CLUT loading for the foreground */
+ SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Start DMA2D CLUT Loading with interrupt enabled.
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
+ * the configuration information for the color look up table.
+ * @param LayerIdx DMA2D Layer index.
+ * This parameter can be one of the following values:
+ * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg,
+ uint32_t LayerIdx)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA2D_LAYER(LayerIdx));
+ assert_param(IS_DMA2D_CLUT_CM(CLUTCfg->CLUTColorMode));
+ assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg->Size));
+
+ /* Process locked */
+ __HAL_LOCK(hdma2d);
+
+ /* Change DMA2D peripheral state */
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+ /* Configure the CLUT of the background DMA2D layer */
+ if (LayerIdx == DMA2D_BACKGROUND_LAYER)
+ {
+ /* Write background CLUT memory address */
+ WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg->pCLUT);
+
+ /* Write background CLUT size and CLUT color mode */
+ MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
+ ((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
+
+ /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
+ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
+
+ /* Enable the CLUT loading for the background */
+ SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
+ }
+ /* Configure the CLUT of the foreground DMA2D layer */
+ else
+ {
+ /* Write foreground CLUT memory address */
+ WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg->pCLUT);
+
+ /* Write foreground CLUT size and CLUT color mode */
+ MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
+ ((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
+
+ /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
+ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
+
+ /* Enable the CLUT loading for the foreground */
+ SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Start DMA2D CLUT Loading.
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
+ * the configuration information for the color look up table.
+ * @param LayerIdx DMA2D Layer index.
+ * This parameter can be one of the following values:
+ * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
+ * @note API obsolete and maintained for compatibility with legacy. User is
+ * invited to resort to HAL_DMA2D_CLUTStartLoad() instead to benefit from
+ * code compactness, code size and improved heap usage.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA2D_LAYER(LayerIdx));
+ assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
+ assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
+
+ /* Process locked */
+ __HAL_LOCK(hdma2d);
+
+ /* Change DMA2D peripheral state */
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+ /* Configure the CLUT of the background DMA2D layer */
+ if (LayerIdx == DMA2D_BACKGROUND_LAYER)
+ {
+ /* Write background CLUT memory address */
+ WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
+
+ /* Write background CLUT size and CLUT color mode */
+ MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
+ ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
+
+ /* Enable the CLUT loading for the background */
+ SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
+ }
+ /* Configure the CLUT of the foreground DMA2D layer */
+ else
+ {
+ /* Write foreground CLUT memory address */
+ WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
+
+ /* Write foreground CLUT size and CLUT color mode */
+ MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
+ ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
+
+ /* Enable the CLUT loading for the foreground */
+ SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Start DMA2D CLUT Loading with interrupt enabled.
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
+ * the configuration information for the color look up table.
+ * @param LayerIdx DMA2D Layer index.
+ * This parameter can be one of the following values:
+ * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
+ * @note API obsolete and maintained for compatibility with legacy. User is
+ * invited to resort to HAL_DMA2D_CLUTStartLoad_IT() instead to benefit
+ * from code compactness, code size and improved heap usage.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA2D_LAYER(LayerIdx));
+ assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
+ assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
+
+ /* Process locked */
+ __HAL_LOCK(hdma2d);
+
+ /* Change DMA2D peripheral state */
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+ /* Configure the CLUT of the background DMA2D layer */
+ if (LayerIdx == DMA2D_BACKGROUND_LAYER)
+ {
+ /* Write background CLUT memory address */
+ WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
+
+ /* Write background CLUT size and CLUT color mode */
+ MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
+ ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
+
+ /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
+ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
+
+ /* Enable the CLUT loading for the background */
+ SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
+ }
+ /* Configure the CLUT of the foreground DMA2D layer */
+ else
+ {
+ /* Write foreground CLUT memory address */
+ WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
+
+ /* Write foreground CLUT size and CLUT color mode */
+ MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
+ ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
+
+ /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
+ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
+
+ /* Enable the CLUT loading for the foreground */
+ SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort the DMA2D CLUT loading.
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @param LayerIdx DMA2D Layer index.
+ * This parameter can be one of the following values:
+ * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
+{
+ uint32_t tickstart;
+ const __IO uint32_t *reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
+
+ /* Abort the CLUT loading */
+ SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT);
+
+ /* If foreground CLUT loading is considered, update local variables */
+ if (LayerIdx == DMA2D_FOREGROUND_LAYER)
+ {
+ reg = &(hdma2d->Instance->FGPFCCR);
+ }
+
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check if the CLUT loading is aborted */
+ while ((*reg & DMA2D_BGPFCCR_START) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_ABORT)
+ {
+ /* Update error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
+
+ /* Change the DMA2D state */
+ hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma2d);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */
+ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
+
+ /* Change the DMA2D state*/
+ hdma2d->State = HAL_DMA2D_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma2d);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Suspend the DMA2D CLUT loading.
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @param LayerIdx DMA2D Layer index.
+ * This parameter can be one of the following values:
+ * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
+{
+ uint32_t tickstart;
+ uint32_t loadsuspended;
+ const __IO uint32_t *reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
+
+ /* Suspend the CLUT loading */
+ SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
+
+ /* If foreground CLUT loading is considered, update local variables */
+ if (LayerIdx == DMA2D_FOREGROUND_LAYER)
+ {
+ reg = &(hdma2d->Instance->FGPFCCR);
+ }
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check if the CLUT loading is suspended */
+ /* 1st condition: Suspend Check */
+ loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) ? 1UL : 0UL;
+ /* 2nd condition: Not Start Check */
+ loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START) ? 1UL : 0UL;
+ while (loadsuspended == 0UL)
+ {
+ if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_SUSPEND)
+ {
+ /* Update error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
+
+ /* Change the DMA2D state */
+ hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
+
+ return HAL_TIMEOUT;
+ }
+ /* 1st condition: Suspend Check */
+ loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) ? 1UL : 0UL;
+ /* 2nd condition: Not Start Check */
+ loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START) ? 1UL : 0UL;
+ }
+
+ /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
+ if ((*reg & DMA2D_BGPFCCR_START) != 0U)
+ {
+ hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
+ }
+ else
+ {
+ /* Make sure SUSP bit is cleared since it is meaningless
+ when no transfer is on-going */
+ CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resume the DMA2D CLUT loading.
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @param LayerIdx DMA2D Layer index.
+ * This parameter can be one of the following values:
+ * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
+{
+ /* Check the SUSP and START bits for background or foreground CLUT loading */
+ if (LayerIdx == DMA2D_BACKGROUND_LAYER)
+ {
+ /* Background CLUT loading suspension check */
+ if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
+ {
+ if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
+ {
+ /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+ }
+ }
+ }
+ else
+ {
+ /* Foreground CLUT loading suspension check */
+ if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
+ {
+ if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
+ {
+ /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+ }
+ }
+ }
+
+ /* Resume the CLUT loading */
+ CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
+
+ return HAL_OK;
+}
+
+
+/**
+
+ * @brief Polling for transfer complete or CLUT loading.
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
+{
+ uint32_t tickstart;
+ uint32_t layer_start;
+ __IO uint32_t isrflags = 0x0U;
+
+ /* Polling for DMA2D transfer */
+ if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while (__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U)
+ {
+ isrflags = READ_REG(hdma2d->Instance->ISR);
+ if ((isrflags & (DMA2D_FLAG_CE | DMA2D_FLAG_TE)) != 0U)
+ {
+ if ((isrflags & DMA2D_FLAG_CE) != 0U)
+ {
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
+ }
+ if ((isrflags & DMA2D_FLAG_TE) != 0U)
+ {
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
+ }
+ /* Clear the transfer and configuration error flags */
+ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE);
+
+ /* Change DMA2D state */
+ hdma2d->State = HAL_DMA2D_STATE_ERROR;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma2d);
+
+ return HAL_ERROR;
+ }
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ /* Update error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
+
+ /* Change the DMA2D state */
+ hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma2d);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ /* Polling for CLUT loading (foreground or background) */
+ layer_start = hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START;
+ layer_start |= hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START;
+ if (layer_start != 0U)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while (__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U)
+ {
+ isrflags = READ_REG(hdma2d->Instance->ISR);
+ if ((isrflags & (DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE)) != 0U)
+ {
+ if ((isrflags & DMA2D_FLAG_CAE) != 0U)
+ {
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
+ }
+ if ((isrflags & DMA2D_FLAG_CE) != 0U)
+ {
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
+ }
+ if ((isrflags & DMA2D_FLAG_TE) != 0U)
+ {
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
+ }
+ /* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */
+ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
+
+ /* Change DMA2D state */
+ hdma2d->State = HAL_DMA2D_STATE_ERROR;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma2d);
+
+ return HAL_ERROR;
+ }
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ /* Update error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
+
+ /* Change the DMA2D state */
+ hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma2d);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Clear the transfer complete and CLUT loading flags */
+ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC | DMA2D_FLAG_CTC);
+
+ /* Change DMA2D state */
+ hdma2d->State = HAL_DMA2D_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma2d);
+
+ return HAL_OK;
+}
+/**
+ * @brief Handle DMA2D interrupt request.
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @retval HAL status
+ */
+void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
+{
+ uint32_t isrflags = READ_REG(hdma2d->Instance->ISR);
+ uint32_t crflags = READ_REG(hdma2d->Instance->CR);
+
+ /* Transfer Error Interrupt management ***************************************/
+ if ((isrflags & DMA2D_FLAG_TE) != 0U)
+ {
+ if ((crflags & DMA2D_IT_TE) != 0U)
+ {
+ /* Disable the transfer Error interrupt */
+ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);
+
+ /* Update error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
+
+ /* Clear the transfer error flag */
+ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
+
+ /* Change DMA2D state */
+ hdma2d->State = HAL_DMA2D_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma2d);
+
+ if (hdma2d->XferErrorCallback != NULL)
+ {
+ /* Transfer error Callback */
+ hdma2d->XferErrorCallback(hdma2d);
+ }
+ }
+ }
+ /* Configuration Error Interrupt management **********************************/
+ if ((isrflags & DMA2D_FLAG_CE) != 0U)
+ {
+ if ((crflags & DMA2D_IT_CE) != 0U)
+ {
+ /* Disable the Configuration Error interrupt */
+ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
+
+ /* Clear the Configuration error flag */
+ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
+
+ /* Update error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
+
+ /* Change DMA2D state */
+ hdma2d->State = HAL_DMA2D_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma2d);
+
+ if (hdma2d->XferErrorCallback != NULL)
+ {
+ /* Transfer error Callback */
+ hdma2d->XferErrorCallback(hdma2d);
+ }
+ }
+ }
+ /* CLUT access Error Interrupt management ***********************************/
+ if ((isrflags & DMA2D_FLAG_CAE) != 0U)
+ {
+ if ((crflags & DMA2D_IT_CAE) != 0U)
+ {
+ /* Disable the CLUT access error interrupt */
+ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);
+
+ /* Clear the CLUT access error flag */
+ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
+
+ /* Update error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
+
+ /* Change DMA2D state */
+ hdma2d->State = HAL_DMA2D_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma2d);
+
+ if (hdma2d->XferErrorCallback != NULL)
+ {
+ /* Transfer error Callback */
+ hdma2d->XferErrorCallback(hdma2d);
+ }
+ }
+ }
+ /* Transfer watermark Interrupt management **********************************/
+ if ((isrflags & DMA2D_FLAG_TW) != 0U)
+ {
+ if ((crflags & DMA2D_IT_TW) != 0U)
+ {
+ /* Disable the transfer watermark interrupt */
+ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);
+
+ /* Clear the transfer watermark flag */
+ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);
+
+ /* Transfer watermark Callback */
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+ hdma2d->LineEventCallback(hdma2d);
+#else
+ HAL_DMA2D_LineEventCallback(hdma2d);
+#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
+
+ }
+ }
+ /* Transfer Complete Interrupt management ************************************/
+ if ((isrflags & DMA2D_FLAG_TC) != 0U)
+ {
+ if ((crflags & DMA2D_IT_TC) != 0U)
+ {
+ /* Disable the transfer complete interrupt */
+ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
+
+ /* Clear the transfer complete flag */
+ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
+
+ /* Update error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
+
+ /* Change DMA2D state */
+ hdma2d->State = HAL_DMA2D_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma2d);
+
+ if (hdma2d->XferCpltCallback != NULL)
+ {
+ /* Transfer complete Callback */
+ hdma2d->XferCpltCallback(hdma2d);
+ }
+ }
+ }
+ /* CLUT Transfer Complete Interrupt management ******************************/
+ if ((isrflags & DMA2D_FLAG_CTC) != 0U)
+ {
+ if ((crflags & DMA2D_IT_CTC) != 0U)
+ {
+ /* Disable the CLUT transfer complete interrupt */
+ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);
+
+ /* Clear the CLUT transfer complete flag */
+ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);
+
+ /* Update error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
+
+ /* Change DMA2D state */
+ hdma2d->State = HAL_DMA2D_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma2d);
+
+ /* CLUT Transfer complete Callback */
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+ hdma2d->CLUTLoadingCpltCallback(hdma2d);
+#else
+ HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d);
+#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
+ }
+ }
+
+}
+
+/**
+ * @brief Transfer watermark callback.
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @retval None
+ */
+__weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdma2d);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_DMA2D_LineEventCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief CLUT Transfer Complete callback.
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @retval None
+ */
+__weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdma2d);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure the DMA2D foreground or background layer parameters.
+ (+) Configure the DMA2D CLUT transfer.
+ (+) Configure the line watermark
+ (+) Configure the dead time value.
+ (+) Enable or disable the dead time value functionality.
+
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the DMA2D Layer according to the specified
+ * parameters in the DMA2D_HandleTypeDef.
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @param LayerIdx DMA2D Layer index.
+ * This parameter can be one of the following values:
+ * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
+{
+ DMA2D_LayerCfgTypeDef *pLayerCfg;
+ uint32_t regMask;
+ uint32_t regValue;
+
+ /* Check the parameters */
+ assert_param(IS_DMA2D_LAYER(LayerIdx));
+ assert_param(IS_DMA2D_OFFSET(hdma2d->LayerCfg[LayerIdx].InputOffset));
+ if (hdma2d->Init.Mode != DMA2D_R2M)
+ {
+ assert_param(IS_DMA2D_INPUT_COLOR_MODE(hdma2d->LayerCfg[LayerIdx].InputColorMode));
+ if (hdma2d->Init.Mode != DMA2D_M2M)
+ {
+ assert_param(IS_DMA2D_ALPHA_MODE(hdma2d->LayerCfg[LayerIdx].AlphaMode));
+ }
+ }
+ assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->LayerCfg[LayerIdx].AlphaInverted));
+ assert_param(IS_DMA2D_RB_SWAP(hdma2d->LayerCfg[LayerIdx].RedBlueSwap));
+
+ /* Process locked */
+ __HAL_LOCK(hdma2d);
+
+ /* Change DMA2D peripheral state */
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+ pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
+
+ /* Prepare the value to be written to the BGPFCCR or FGPFCCR register */
+ regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos) | \
+ (pLayerCfg->AlphaInverted << DMA2D_BGPFCCR_AI_Pos) | (pLayerCfg->RedBlueSwap << DMA2D_BGPFCCR_RBS_Pos);
+ regMask = (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_RBS);
+
+
+ if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
+ {
+ regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);
+ }
+ else
+ {
+ regValue |= (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos);
+ }
+
+ /* Configure the background DMA2D layer */
+ if (LayerIdx == DMA2D_BACKGROUND_LAYER)
+ {
+ /* Write DMA2D BGPFCCR register */
+ MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue);
+
+ /* DMA2D BGOR register configuration -------------------------------------*/
+ WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);
+
+ /* DMA2D BGCOLR register configuration -------------------------------------*/
+ if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
+ {
+ WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE | DMA2D_BGCOLR_GREEN | \
+ DMA2D_BGCOLR_RED));
+ }
+ }
+ /* Configure the foreground DMA2D layer */
+ else
+ {
+
+
+ /* Write DMA2D FGPFCCR register */
+ MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);
+
+ /* DMA2D FGOR register configuration -------------------------------------*/
+ WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);
+
+ /* DMA2D FGCOLR register configuration -------------------------------------*/
+ if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
+ {
+ WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE | DMA2D_FGCOLR_GREEN | \
+ DMA2D_FGCOLR_RED));
+ }
+ }
+ /* Initialize the DMA2D state*/
+ hdma2d->State = HAL_DMA2D_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma2d);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the DMA2D CLUT Transfer.
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
+ * the configuration information for the color look up table.
+ * @param LayerIdx DMA2D Layer index.
+ * This parameter can be one of the following values:
+ * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
+ * @note API obsolete and maintained for compatibility with legacy. User is invited
+ * to resort to HAL_DMA2D_CLUTStartLoad() instead to benefit from code compactness,
+ * code size and improved heap usage.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA2D_LAYER(LayerIdx));
+ assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
+ assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
+
+ /* Process locked */
+ __HAL_LOCK(hdma2d);
+
+ /* Change DMA2D peripheral state */
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+ /* Configure the CLUT of the background DMA2D layer */
+ if (LayerIdx == DMA2D_BACKGROUND_LAYER)
+ {
+ /* Write background CLUT memory address */
+ WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
+
+ /* Write background CLUT size and CLUT color mode */
+ MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
+ ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
+ }
+ /* Configure the CLUT of the foreground DMA2D layer */
+ else
+ {
+ /* Write foreground CLUT memory address */
+ WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
+
+ /* Write foreground CLUT size and CLUT color mode */
+ MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
+ ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
+ }
+
+ /* Set the DMA2D state to Ready*/
+ hdma2d->State = HAL_DMA2D_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma2d);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Configure the line watermark.
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @param Line Line Watermark configuration (maximum 16-bit long value expected).
+ * @note HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt.
+ * @note The transfer watermark interrupt is disabled once it has occurred.
+ * @retval HAL status
+ */
+
+HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
+{
+ /* Check the parameters */
+ if (Line > DMA2D_LWR_LW)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process locked */
+ __HAL_LOCK(hdma2d);
+
+ /* Change DMA2D peripheral state */
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+ /* Sets the Line watermark configuration */
+ WRITE_REG(hdma2d->Instance->LWR, Line);
+
+ /* Enable the Line interrupt */
+ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW);
+
+ /* Initialize the DMA2D state*/
+ hdma2d->State = HAL_DMA2D_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma2d);
+
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief Enable DMA2D dead time feature.
+ * @param hdma2d DMA2D handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d)
+{
+ /* Process Locked */
+ __HAL_LOCK(hdma2d);
+
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+ /* Set DMA2D_AMTCR EN bit */
+ SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
+
+ hdma2d->State = HAL_DMA2D_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma2d);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable DMA2D dead time feature.
+ * @param hdma2d DMA2D handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d)
+{
+ /* Process Locked */
+ __HAL_LOCK(hdma2d);
+
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+ /* Clear DMA2D_AMTCR EN bit */
+ CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
+
+ hdma2d->State = HAL_DMA2D_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma2d);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure dead time.
+ * @note The dead time value represents the guaranteed minimum number of cycles between
+ * two consecutive transactions on the AHB bus.
+ * @param hdma2d DMA2D handle.
+ * @param DeadTime dead time value.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)
+{
+ /* Process Locked */
+ __HAL_LOCK(hdma2d);
+
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+ /* Set DMA2D_AMTCR DT field */
+ MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_AMTCR_DT_Pos));
+
+ hdma2d->State = HAL_DMA2D_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma2d);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to:
+ (+) Get the DMA2D state
+ (+) Get the DMA2D error code
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the DMA2D state
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @retval HAL state
+ */
+HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)
+{
+ return hdma2d->State;
+}
+
+/**
+ * @brief Return the DMA2D error code
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for DMA2D.
+ * @retval DMA2D Error Code
+ */
+uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)
+{
+ return hdma2d->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA2D_Private_Functions DMA2D Private Functions
+ * @{
+ */
+
+/**
+ * @brief Set the DMA2D transfer parameters.
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA2D.
+ * @param pdata The source memory Buffer address
+ * @param DstAddress The destination memory Buffer address
+ * @param Width The width of data to be transferred from source to destination.
+ * @param Height The height of data to be transferred from source to destination.
+ * @retval HAL status
+ */
+static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
+ uint32_t Height)
+{
+ uint32_t tmp;
+ uint32_t tmp1;
+ uint32_t tmp2;
+ uint32_t tmp3;
+ uint32_t tmp4;
+
+ /* Configure DMA2D data size */
+ MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL | DMA2D_NLR_PL), (Height | (Width << DMA2D_NLR_PL_Pos)));
+
+ /* Configure DMA2D destination address */
+ WRITE_REG(hdma2d->Instance->OMAR, DstAddress);
+
+ /* Register to memory DMA2D mode selected */
+ if (hdma2d->Init.Mode == DMA2D_R2M)
+ {
+ tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
+ tmp2 = pdata & DMA2D_OCOLR_RED_1;
+ tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
+ tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
+
+ /* Prepare the value to be written to the OCOLR register according to the color mode */
+ if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888)
+ {
+ tmp = (tmp3 | tmp2 | tmp1 | tmp4);
+ }
+ else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888)
+ {
+ tmp = (tmp3 | tmp2 | tmp4);
+ }
+ else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565)
+ {
+ tmp2 = (tmp2 >> 19U);
+ tmp3 = (tmp3 >> 10U);
+ tmp4 = (tmp4 >> 3U);
+ tmp = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4);
+ }
+ else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)
+ {
+ tmp1 = (tmp1 >> 31U);
+ tmp2 = (tmp2 >> 19U);
+ tmp3 = (tmp3 >> 11U);
+ tmp4 = (tmp4 >> 3U);
+ tmp = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4);
+ }
+ else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */
+ {
+ tmp1 = (tmp1 >> 28U);
+ tmp2 = (tmp2 >> 20U);
+ tmp3 = (tmp3 >> 12U);
+ tmp4 = (tmp4 >> 4U);
+ tmp = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4);
+ }
+ /* Write to DMA2D OCOLR register */
+ WRITE_REG(hdma2d->Instance->OCOLR, tmp);
+ }
+ else if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG) /*M2M_blending with fixed color FG DMA2D Mode selected*/
+ {
+ WRITE_REG(hdma2d->Instance->BGMAR, pdata);
+ }
+ else /* M2M, M2M_PFC,M2M_Blending or M2M_blending with fixed color BG DMA2D Mode */
+ {
+ /* Configure DMA2D source address */
+ WRITE_REG(hdma2d->Instance->FGMAR, pdata);
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* DMA2D */
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma_ex.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma_ex.c
new file mode 100644
index 00000000..0b3c5c2f
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma_ex.c
@@ -0,0 +1,4695 @@
+/**
+ **********************************************************************************************************************
+ * @file stm32u5xx_hal_dma_ex.c
+ * @author MCD Application Team
+ * @brief DMA Extension HAL module driver
+ * This file provides firmware functions to manage the following functionalities of the DMA extension
+ * peripheral:
+ * + Linked-List Initialization and De-Initialization Functions
+ * + Linked-List I/O Operation Functions
+ * + Linked-List Management Functions
+ * + Data Handling, Repeated Block and Trigger Configuration Functions
+ * + Suspend and Resume Operation Functions
+ * + FIFO Status Function
+ *
+ **********************************************************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ **********************************************************************************************************************
+ @verbatim
+ ======================================================================================================================
+ ############### How to use this driver ###############
+ ======================================================================================================================
+ [..]
+ Alternatively to the normal programming mode, a DMA channel can be programmed by a list of transfers, known as
+ linked-list (list of Node items). Each node is defined by its data structure.
+ Each node specifies a standalone DMA channel.
+ When enabled, the DMA channel fetch the first linked-list node from SRAM (known as head node). When executed, the
+ next linked list node will be fetched and executed. This operation is repeated until the end of the whole
+ linked-list queue. Optionally, the linked-list can be linear where the last linked-list queue node is not linked
+ to another queue node or circular where the last linked-list node is linked to any linked-list queue node.
+
+ (+) Linear linked-list:
+ The DMA channel fetch and execute all DMA linked-list queue from first node (head node) to last node
+ (tail node) ones. When the last node is completed, the DMA channel remains in idle state and another
+ transfer can be lunched.
+
+ (+) Circular linked-list:
+ The DMA channel fetch and execute all DMA linked-list queue from first node (head node) to last node (tail
+ node). When last node is executed, the DMA channel fetches the first circular node another time and repeat
+ the same sequence in an infinite loop (Circular transfer). To stop the DMA channel, an abort operation is
+ required. This linked-list mode replaces the legacy circular transfers.
+
+ [..]
+ In order to reduce linked-list queue executing time and power consumption, the DMA channel supports executing the
+ dynamic linked-list format. In fact, the DMA supports the execution of 2 types of linked-list formats : static and
+ dynamic.
+
+ (+) Static linked-list:
+ The static linked-list format refers to the full linked-list node where all DMA channel parameters are
+ fetched and executed independently of the redundancy of information.
+
+ (+) Dynamic linked-list:
+ The dynamic linked-list format refer to the customized linked-list node where only DMA channel necessary
+ parameters are fetched and executed (Example: data size = 20 on previous node, and data size = 20 on the
+ current node => No need to update it).
+
+ For linked-list transfers, the DMA channel can execute the linked-list queue node by node. This feature is named
+ link step mode. When activated, enabling the DMA channel first time allows to fetch the head node from memory
+ then it stops. Then, another DMA channel enable is needed to execute the node. After that, keeping enabling the
+ DMA channel is needed to execute each node until the end of linked-list queue. When the linked-list queue is
+ circular, enabling the DMA channel in an infinite loop is required to keep the DMA channel running. This feature
+ is useful for debug purpose or asynchronously executing queue nodes.
+
+ [..]
+ Each DMA channel transfer (normal or linked-list), is highly configurable according to DMA channel instance
+ integrated in devices. These configuration can be :
+
+ (+) Repeated block configuration :
+ If the feature is supported, the DMA channel can performs a repeated block transfers. Named also 2
+ dimension addressing transfers, this feature can transfer n iteration of programmed block transfer (Block
+ transfer is the legacy data size). Additional to the repeat count of a block, DMA channel addresses can
+ jump after at burst and block level. The jump length is a programmable parameter defined by DMA user.
+ (++) Jump at burst level :
+ The DMA channel keep an empty area, between each 2 consecutive bursts transmitted.
+ (++) Jump at block level :
+ The DMA channel keep an empty area, between each 2 consecutive blocks transmitted.
+
+ (+) Trigger :
+ The DMA channel transfers can be conditioned by hardware signals edges (rising or falling) named hardware
+ triggers. Trigger condition can be applied at :
+ (++) Single/Burst level :
+ Each single/burst data transmission is conditioned by a signal trigger hit.
+ (++) Block level :
+ Each block data transmission is conditioned by a signal trigger hit.
+ (++) Repeated block level :
+ Each repeated block data transmission is conditioned by a signal trigger hit.
+ (++) Node level :
+ Each node execution is conditioned by a signal trigger hit.
+ The DMA channel can report a trigger overrun when detects more than 2 trigger signal edges before
+ executing the current transfer.
+
+ (+) Data handling :
+ The data handling feature is a FIFO capability that can be :
+ (++) Padding pattern :
+ Padding selected pattern (zero padding or sign extension) when the source data width is smaller
+ than the destination data width at single level.
+ (++) Truncation :
+ Truncate section from the source data single when the source data width is bigger than the
+ destination data width.
+ (++) Pack/Unpack :
+ Pack a set of data when source data width is smaller than the destination data width.
+ Unpack a set of data when source data width is bigger than the destination data width.
+ (++) Exchange :
+ Exchange data at byte and half-word on the destination and at byte level on the source.
+
+ [..]
+ Each DMA channel transfer (normal or linked-list) when it is active, can be suspended and resumed at run time
+ application. When trying to suspend an ongoing transfer, the DMA channel isn't suspended instantly but complete
+ the current ongoing single/burst then it stops.
+ When the DMA channel is suspended, the current transfer can be resumed instantly.
+
+ [..]
+ The DMA channel that supports FIFO, can report in real time the number of beats remains on destination (Output)
+ FIFO level.
+
+ *** Linked-List Initialization and De-Initialization operation ***
+ ==================================================================
+ [..]
+ Differently from normal transfers, DMA channel initialization and de-initialization need less parameters as the
+ remaining transfer parameters are defined by linked-list nodes.
+
+ (+) Use HAL_DMAEx_List_Init() to initialize a DMA channel in linked-list mode according to programmed fields.
+ When called, the DMA channel will be ready to execute linked-list queues.
+
+ (+) Use HAL_DMAEx_List_DeInit() to de-initialize a DMA channel in linked-list mode.
+ When called, the DMA channel will be in reset. It is mandatory to reinitialize it for next transfer.
+
+ *** Linked-List I/O Operation ***
+ =================================
+ [..]
+ (+) Use HAL_DMAEx_List_Start() to start a DMA transfer in linked-list mode after the configuration of
+ linked-list queue base address and offset in polling mode (Blocking mode).
+
+ (+) Use HAL_DMAEx_List_Start_IT() to start a DMA transfer in linked-list mode after the configuration of
+ linked-list queue base address and offset in interrupt mode (Non-blocking mode).
+
+ *** Linked-List Management ***
+ ==============================
+ [..]
+ The linked-list management is a software processing independently of DMA channel hardware. It allows to reset,
+ build, create, insert, remove, replace, circularize, convert both nodes and queue in order to perform DMA
+ channel transfers in linked-list mode.
+ Linked-list APIs and types are adapted to reduce memory footprint.
+
+ *** Linked-list nodes building ***
+ [..]
+ At node level, the operations that can be done are building a new linked-list node or get a linked-list node
+ information from a built node. The linked-list nodes have two forms according to 2 dimensions addressing
+ capability. The linear addressing nodes contains the information of all DMA channel features except the 2
+ dimension addressing features and the 2 dimensions addressing nodes contain the information of all available
+ features.
+
+ (+) Use HAL_DMAEx_List_BuildNode() to build the DMA linked-list node according to the specified parameters.
+ Build operation allow to convert the specified parameter in values known by the DMA channel and place them
+ in memory.
+ Placing DMA linked-list in SRAM must be done in accordance to product specification to ensure that the
+ link access port can access to the specified SRAM.
+
+ (+) Use HAL_DMAEx_List_GetNodeConfig() to get the specified configuration parameter on building node.
+ This API can be used when need to change few parameter to build new node.
+
+ *** Inserting nodes to linked-list queue ***
+ [..]
+ In order to build a sequence of DMA transaction with different configuration, we need to insert built node at
+ linked-list queue (node present an elementary DMA transaction) in linked-list queue on any position to have the
+ full flexibility of ordering nodes or extend the sequence of queue transactions.
+
+ (+) Use HAL_DMAEx_List_InsertNode() to insert new built node in any queue position of linked-list queue
+ according to selecting previous node. When calling this API with previous node parameter is NULL, the
+ inserted node will be placed at the head of the linked-list queue.
+ (++) This API must be used after HAL_DMAEx_List_BuildNode() otherwise an error will be returned.
+ (++) This API must be called for static queues format.
+ (++) This API shall be avoided when adding new node at the head or the tail of queue (overhead of
+ footprint and performance : use HAL_DMAEx_List_InsertNode_Head() or HAL_DMAEx_List_InsertNode_Tail()
+ instead).
+
+ (+) Use HAL_DMAEx_List_InsertNode_Head() to insert new built node at the head of linked-list queue. The head
+ node will not be overwritten but will be the second queue node.
+ (++) This API must be used after HAL_DMAEx_List_BuildNode() otherwise an error will be returned.
+ (++) This API must be called for static queues format.
+
+ (+) Use HAL_DMAEx_List_InsertNode_Tail() to insert new built node at the tail of linked-list queue. The tail
+ node will not be overwritten but will be the penultimate queue node.
+ (++) This API must be used after HAL_DMAEx_List_BuildNode() otherwise an error will be returned.
+ (++) This API must be called for static queues format.
+
+ *** Removing nodes from linked-list queue ***
+ [..]
+ There is some cases when removing a node from linked-list queue is needed (need to remove an elementary DMA
+ transaction). Removing node allows to unlink a node from DMA linked-list queue (NOT DELETED), so the removed node
+ can be reused for another queue or to be added to the same queue without need to rebuild it in next step.
+
+ (+) Use HAL_DMAEx_List_RemoveNode() to remove any yet built and inserted node from linked-list queue according
+ to selected node.
+ (++) This API must be called for static queues format.
+ (++) This API shall be avoided when removing the head or the tail of linked-list queue (overhead of
+ footprint and performance : use HAL_DMAEx_List_RemoveNode_Head() or HAL_DMAEx_List_RemoveNode_Tail()
+ instead).
+
+ (+) Use HAL_DMAEx_List_RemoveNode_Head() to remove the head node from linked-list queue.
+ (++) This API must be called for static queues format.
+
+ (+) Use HAL_DMAEx_List_RemoveNode_Tail() to remove the tail node from linked-list queue.
+ (++) This API must be called for static queues format.
+
+ *** Replacing nodes on linked-list queue ***
+ [..]
+ There is some cases when replacing a node from linked-list queue is needed (need to replace an elementary DMA
+ transfer, by another one that have not the same configuration). Replacing node allows to unlink the node to be
+ replaced from DMA linked-list queue (NOT DELETED) and link instead a new node. So the replaced node can be reused
+ for another queue or to be added to the same queue without need to rebuild it in next step and the new node cannot
+ be reused except when remove it or replaced in next step.
+
+ (+) Use HAL_DMAEx_List_ReplaceNode() to replace any yet built and inserted node on linked-list queue according
+ to selected node.
+ (++) This API must be called for static queues format.
+ (++) This API shall be avoided when replacing the head or the tail linked-list queue (overhead of
+ footprint and performance : use HAL_DMAEx_List_ReplaceNode_Head() or
+ HAL_DMAEx_List_ReplaceNode_Tail() instead).
+
+ (+) Use HAL_DMAEx_List_ReplaceNode_Head() to replace the head node of linked-list queue.
+ (++) This API must be called for static queues format.
+
+ (+) Use HAL_DMAEx_List_ReplaceNode_Tail() to replace the tail node from linked-list queue.
+ (++) This API must be called for static queues format.
+
+ *** Reset linked-list queue ***
+ [..]
+ After finishing using a linked-list queue, it can be reset and cleared and it's content nodes will be
+ unlinked (NOT DELETED) and reused on another queue.
+
+ (+) Use HAL_DMAEx_List_ResetQ() to reset a linked-list queue and unlink all it's content nodes.
+ (++) This API must be called for ready state queues.
+ (++) This API must be called for static queues format.
+
+ *** Inserting linked-list queue ***
+ [..]
+ To ensure the flexibility of building linked-list queue by their targeted functionalities (Example: 3 nodes for
+ action 1 and 5 nodes for action 2), it is possible to build a queue for action 1 that contains action 1 nodes and
+ a queue for action 2 that contains action 2 nodes then concatenating the 2 queues. So, there are some cases where
+ the management of linked-list at queue granularity is needed.
+
+ (+) Use HAL_DMAEx_List_InsertQ() to insert source linked-list queue to a destination linked-list queue
+ according to selecting previous node.
+ (++) This API must be called for static queues format.
+ (++) This API shall be avoided when inserting source linked-list queue at the head or the tail of
+ destination queue (overhead of footprint and performance : use HAL_DMAEx_List_InsertQ_Head() or
+ HAL_DMAEx_List_InsertQ_Tail() instead).
+
+ (+) Use HAL_DMAEx_List_InsertQ_Head() to insert a source linked-list queue at the head of linked-list
+ destination queue.
+ (++) This API must be called for static queues format.
+
+ (+) Use HAL_DMAEx_List_InsertQ_Tail() to insert a source linked-list queue at the tail of linked-list
+ destination queue.
+ (++) This API must be called for static queues format.
+
+ *** Circularizing linked-list queue ***
+ [..]
+ In order to perform tasks in infinite loop with DMA channel, it is possible to circularize the linked-list queues.
+ Circularizing queue allows to link last linked-list queue node to any previous node of the same queue (This node
+ is named first circular queue). When the first circular node is the head node, all linked-list queue nodes will be
+ executed in infinite loop. When the first circular node is not the head nodes, all precedent nodes are executed
+ once and all remaining nodes are executed in an infinite loop.
+
+ (+) Use HAL_DMAEx_List_SetCircularModeConfig() to circularize the linked-list queue according to first
+ circular node selected.
+ (++) This API must be called for static queues format.
+ (++) This API shall be avoided when first circular node is the head linked-list queue node (overhead of
+ footprint and performance : use HAL_DMAEx_List_SetCircularMode() instead).
+
+ (+) Use HAL_DMAEx_List_SetCircularMode() to circularize the linked-list queue with linking last queue node
+ with first queue node.
+ (++) This API must be called for static queues format.
+
+ (+) Use HAL_DMAEx_List_ClearCircularMode() to clear any linked-list queue circular configuration.
+ (++) This API must be called for static queues format.
+
+
+ *** Converting linked-list queue ***
+ [..]
+ To have the best DMA channel linked-list queue execution, it is recommended to convert yet build linked-list queue
+ to dynamic format (Static is the default format). When linked-list queue becomes dynamic, all queue nodes are
+ optimized and only changed parameters will be updated between nodes. So, the DMA will fetch only changes
+ parameters instead of the whole node.
+
+ (+) Use HAL_DMAEx_List_ConvertQToDynamic() to convert a linked-list queue to dynamic format.
+ (++) This API must be called for ready state queues.
+ (++) This API must be called for static queues format.
+ (++) This API must be called as the last API before starting the DMA channel in linked-list mode.
+
+ (+) Use HAL_DMAEx_List_ConvertQToStatic() to convert a linked-list queue to static format.
+ (++) This API must be called for ready state queues.
+ (++) This API must be called for dynamic queues format.
+ (++) This API must be called as the first API after the full execution of linked-list queue when the
+ execution mode is linear (not circular) if it is dynamic and a linked-list queue management is
+ needed.
+ (++) This API must be called as the first API after the aborting the execution of the current linked-list
+ queue when the execution mode is linear (not circular) if it is dynamic and a linked-list queue
+ management is needed.
+
+ [..]
+ When converting a circular queue to dynamic format and when the first circular node is the last queue node, it is
+ recommended to duplicate the last circular node in order to ensure the full optimization when calling
+ HAL_DMAEx_List_ConvertQToDynamic() API. In this case, updated information are only addresses which allow to reduce
+ 4 words of update for linear nodes per node execution and 6 words update for 2 dimensions addressing nodes per
+ node execution.
+
+
+ *** Linking linked-list queue to DMA channel ***
+ [..]
+ In order to have the possibility of the creation of an infinity queues (limited by available memory size), the
+ building of linked-list queue is fully independent from DMA channels. It is possible to build all needed queues if
+ their size is less then available memory at startup time, then linking each time when needed a linked-list queue
+ to an idle DMA channel.
+
+ (+) Use HAL_DMAEx_List_LinkQ() to link a ready linked-list queue to ready DMA channel.
+ (++) This API supports the two format of linked-list (Static and dynamic).
+ (++) This API must be called for ready state queues and DMA channels.
+
+ (+) Use HAL_DMAEx_List_ConvertQToStatic() to unlink a ready linked-list queue to ready DMA channel.
+ (++) This API supports the two format of linked-list (Static and dynamic).
+ (++) This API must be called for ready state queues and DMA channels.
+
+ *** User sequence ***
+ [..]
+ To use cleanly the DMA linked-list library, ensure to apply the following call sequences :
+
+ (+) Linear transfer :
+ Linked-list queue building
+ (++) HAL_DMAEx_List_BuildNode()
+ (++) HAL_DMAEx_List_InsertNode_Tail()
+ .
+ .
+ .
+ (++) HAL_DMAEx_List_BuildNode()
+ (++) HAL_DMAEx_List_InsertNode_Tail()
+ (++) HAL_DMAEx_List_ConvertQToDynamic()
+ Linked-list queue execution
+ (++) HAL_DMAEx_List_Init()
+ (++) HAL_DMAEx_List_LinkQ()
+ (++) HAL_DMAEx_List_Start() / HAL_DMAEx_List_Start_IT()
+ (++) HAL_DMAEx_List_UnLinkQ()
+ (++) HAL_DMAEx_List_DeInit()
+
+ (+) Circular transfer :
+ Linked-list queue building
+ (++) HAL_DMAEx_List_BuildNode()
+ (++) HAL_DMAEx_List_InsertNode_Tail()
+ .
+ .
+ .
+ (++) HAL_DMAEx_List_BuildNode()
+ (++) HAL_DMAEx_List_InsertNode_Tail()
+ (++) HAL_DMAEx_List_SetCircularModeConfig() / HAL_DMAEx_List_SetCircularMode()
+ (++) HAL_DMAEx_List_ConvertQToDynamic()
+ Linked-list queue execution
+ (++) HAL_DMAEx_List_Init()
+ (++) HAL_DMAEx_List_LinkQ()
+ (++) HAL_DMAEx_List_Start() / HAL_DMAEx_List_Start_IT()
+ (++) HAL_DMA_Abort() / HAL_DMA_Abort_IT()
+ (++) HAL_DMAEx_List_UnLinkQ()
+ (++) HAL_DMAEx_List_DeInit()
+
+
+ *** Data Handling ***
+ =====================
+ [..]
+ In order to avoid some CPU data processing in several cases, the DMA channel provides some features related to
+ FIFO capabilities titled data handling.
+ (++) Padding pattern
+ Padding selected patter (zero padding or sign extension) when the source data width is smaller than
+ the destination data width at single level.
+ Zero padding (Source : 0xABAB ------> Destination : 0xABAB0000)
+ Sign bit extension (Source : 0x0ABA ------> Destination : 0x00000ABA)
+ (Source : 0xFABA ------> Destination : 0xFFFFFABA)
+ (++) Truncation :
+ Truncate section from the source data single when the source data width is bigger than the
+ destination data width.
+ Left truncation (Source : 0xABABCDCD ------> Destination : 0xCDCD)
+ Right truncation (Source : 0xABABCDCD ------> Destination : 0xABAB)
+ (++) Pack/Unpack :
+ Pack a set of data when source data width is smaller than the destination data width.
+ Unpack a set of data when source data width is bigger than the destination data width.
+ Pack (Source : 0xAB, 0xCD ------> Destination : 0xABCD)
+ UnPack (Source : 0xABCD ------> Destination : 0xAB, 0xCD)
+ (++) Exchange :
+ Exchange data at byte and half-word on the destination and at byte level on the source.
+ Source byte exchange (Source : 0xAB12CD34 ------> Destination : 0xABCD1234)
+ Destination byte exchange (Source : 0xAB12CD34 ------> Destination : 0x12AB34CD)
+ Destination half-word exchange (Source : 0xAB12CD34 ------> Destination : 0xCD34AB12)
+
+ (+) Use HAL_DMAEx_ConfigDataHandling() to configure data handling features. Previous elementary explained
+ can be combined according to application needs.
+ (++) This API is complementary of normal transfers.
+ (++) This API must not be called for linked-list transfers as data handling information are configured at
+ node level.
+ (++) This API must be called only for DMA channel that supports data handling feature.
+
+ *** User sequence ***
+ [..]
+ To configure cleanly the DMA channel data handling, ensure to apply the following call sequence :
+
+ (+) Linear transfer :
+ (++) HAL_DMA_Init()
+ (++) HAL_DMAEx_ConfigDataHandling()
+ (++) HAL_DMA_Start()
+
+ *** Repeated Block ***
+ ======================
+ [..]
+ When available, this feature is used when the data size is higher then 65535 bytes (Maximum block size) or for
+ scattering / gathering data.
+ (++) Gather data
+ Source Destination
+ 0xAA 0xAA
+ 0xBB 0xAA
+ 0xAA ==> 0xAA
+ 0xCC
+ 0xAA
+ (++) Scatter data
+ Source Destination
+ 0xAA 0xAA
+ 0xAA 0xBB
+ 0xAA ==> 0xAA
+ 0xBB
+ 0xAA
+
+ (+) Use HAL_DMAEx_ConfigRepeatBlock() to configure data repeated block feature. Jump addresses and
+ incrementing or decrementing on source and destination can be combined to have the need application
+ behavior.
+ (++) This API is complementary of normal transfers.
+ (++) This API must not be called for linked-list transfers as repeated block information are configured at
+ node level.
+ (++) This API must be called only for DMA channel that supports repeated block feature.
+
+ *** User sequence ***
+ [..]
+ To configure cleanly the DMA channel repeated block, ensure to apply the following call sequence :
+
+ (+) Linear transfer :
+ (++) HAL_DMA_Init()
+ (++) HAL_DMAEx_ConfigRepeatBlock()
+ (++) HAL_DMA_Start()
+
+ *** Trigger Configuration ***
+ =============================
+ [..]
+ When application needs that DMA transfers are conditioned by internal or external events, the trigger feature can
+ do that. Trigger signals are a set of device signal that are linked to DMA trigger inputs that allows to start the
+ DMA transfers.
+ To setup a trigger transfers, three DMA channel parameters are needed:
+
+ (+) Trigger mode
+ This parameter specifies the trig level.
+ (++) Block level
+ (++) Repeated block level
+ (++) Node level
+ (++) Single / Burst level
+
+ (+) Trigger polarity
+ This parameter specifies the DMA trigger sensitivity (Rising or falling).
+
+ (+) Trigger selection
+ This parameter specifies the DMA trigger hardware signal.
+
+ (+) Use HAL_DMAEx_ConfigTrigger() to configure trigger feature.
+ (++) This API is complementary to normal transfers APIs.
+ (++) This API must not be called for linked-list transfers as trigger information are configured at
+ node level.
+
+ *** User sequence ***
+ [..]
+ To configure cleanly the DMA channel trigger, ensure to apply the following call sequence :
+ (+) Linear transfer :
+ (++) HAL_DMA_Init()
+ (++) HAL_DMAEx_ConfigTrigger()
+ (++) HAL_DMA_Start()
+
+ *** Suspend and resume operation ***
+ ====================================
+ [..]
+ There are several cases when needs to suspend a DMA current transfer (Example: liberate bandwidth for more
+ priority DMA channel transfer). Suspending DMA channel (same as abort) is available in polling (blocking mode) and
+ interrupt (non-blocking mode) modes. When suspended, a DMA channel can be instantly resumed.
+
+ (+) Use HAL_DMAEx_Suspend() to suspend an ongoing DMA channel transfer in polling mode (Blocking mode).
+
+ (+) Use HAL_DMAEx_Suspend_IT() to suspend an ongoing DMA channel transfer in interrupt mode (Non-blocking
+ mode).
+
+ (+) Use HAL_DMAEx_Resume() to resume a suspended DMA channel transfer execution.
+
+ *** FIFO status ***
+ ===================
+ [..]
+ In several cases, the information of FIFO level is useful to inform at application level how to process remaining
+ data. When not empty, the DMA channel FIFO cannot be flashed only by reset.
+
+ (+) Use HAL_DMAEx_GetFifoLevel() to get the DMA channel FIFO level (available beats in FIFO).
+
+ @endverbatim
+ **********************************************************************************************************************
+ */
+
+/* Includes ----------------------------------------------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup DMAEx DMAEx
+ * @brief DMA Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+
+/* Private types -----------------------------------------------------------------------------------------------------*/
+/* Private variables -------------------------------------------------------------------------------------------------*/
+/* Private Constants -------------------------------------------------------------------------------------------------*/
+/* Private macros ----------------------------------------------------------------------------------------------------*/
+/* Private function prototypes ---------------------------------------------------------------------------------------*/
+static void DMA_List_Init(DMA_HandleTypeDef const *const hdma);
+static void DMA_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig,
+ DMA_NodeTypeDef *const pNode);
+static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig,
+ DMA_NodeTypeDef const *const pNode);
+static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1,
+ DMA_NodeTypeDef const *const pNode2,
+ DMA_NodeTypeDef const *const pNode3);
+static uint32_t DMA_List_CheckNodesTypes(DMA_NodeTypeDef const *const pNode1,
+ DMA_NodeTypeDef const *const pNode2,
+ DMA_NodeTypeDef const *const pNode3);
+static void DMA_List_GetCLLRNodeInfo(DMA_NodeTypeDef const *const pNode,
+ uint32_t *const cllr_mask,
+ uint32_t *const cllr_offset);
+static uint32_t DMA_List_FindNode(DMA_QListTypeDef const *const pQList,
+ DMA_NodeTypeDef const *const pNode,
+ DMA_NodeInQInfoTypeDef *const NodeInfo);
+static void DMA_List_ResetQueueNodes(DMA_QListTypeDef const *const pQList,
+ DMA_NodeInQInfoTypeDef const *const NodeInfo);
+static void DMA_List_FillNode(DMA_NodeTypeDef const *const pSrcNode,
+ DMA_NodeTypeDef *const pDestNode);
+static void DMA_List_ConvertNodeToDynamic(uint32_t ContextNodeAddr,
+ uint32_t CurrentNodeAddr,
+ uint32_t RegisterNumber);
+static void DMA_List_ConvertNodeToStatic(uint32_t ContextNodeAddr,
+ uint32_t CurrentNodeAddr,
+ uint32_t RegisterNumber);
+static void DMA_List_UpdateDynamicQueueNodesCLLR(DMA_QListTypeDef const *const pQList,
+ uint32_t LastNode_IsCircular);
+static void DMA_List_UpdateStaticQueueNodesCLLR(DMA_QListTypeDef const *const pQList,
+ uint32_t operation);
+static void DMA_List_FormatNode(DMA_NodeTypeDef *const pNode,
+ uint32_t RegisterIdx,
+ uint32_t RegisterNumber,
+ uint32_t Format);
+static void DMA_List_ClearUnusedFields(DMA_NodeTypeDef *const pNode,
+ uint32_t FirstUnusedField);
+static void DMA_List_CleanQueue(DMA_QListTypeDef *const pQList);
+
+/* Exported functions ------------------------------------------------------------------------------------------------*/
+
+/** @addtogroup DMAEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DMAEx_Exported_Functions_Group1
+ *
+@verbatim
+ ======================================================================================================================
+ ############### Linked-List Initialization and De-Initialization Functions ###############
+ ======================================================================================================================
+ [..]
+ This section provides functions allowing to initialize and de-initialize the DMA channel in linked-list mode.
+ [..]
+ (+) The HAL_DMAEx_List_Init() function follows the DMA channel linked-list mode configuration procedures as
+ described in reference manual.
+ (+) The HAL_DMAEx_List_DeInit() function allows to de-initialize the DMA channel in linked-list mode.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the DMA channel in linked-list mode according to the specified parameters in the
+ * DMA_InitLinkedListTypeDef and create the associated handle.
+ * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+ * specified DMA Channel.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMAEx_List_Init(DMA_HandleTypeDef *const hdma)
+{
+ /* Get tick number */
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Check the DMA channel handle parameter */
+ if (hdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+ assert_param(IS_DMA_PRIORITY(hdma->InitLinkedList.Priority));
+ assert_param(IS_DMA_LINK_STEP_MODE(hdma->InitLinkedList.LinkStepMode));
+ assert_param(IS_DMA_TCEM_LINKEDLIST_EVENT_MODE(hdma->InitLinkedList.TransferEventMode));
+ assert_param(IS_DMA_LINKEDLIST_MODE(hdma->InitLinkedList.LinkedListMode));
+ /* Check DMA channel instance */
+ if (IS_GPDMA_INSTANCE(hdma->Instance) != 0U)
+ {
+ assert_param(IS_DMA_LINK_ALLOCATED_PORT(hdma->InitLinkedList.LinkAllocatedPort));
+ }
+
+ /* Allocate lock resource */
+ __HAL_UNLOCK(hdma);
+
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ /* Disable the DMA channel */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Check if the DMA channel is effectively disabled */
+ while ((hdma->Instance->CCR & DMA_CCR_EN) != 0U)
+ {
+ /* Check for the Timeout */
+ if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
+ {
+ /* Update error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Initialize the DMA channel registers */
+ DMA_List_Init(hdma);
+
+ /* Update DMA channel operation mode */
+ hdma->Mode = hdma->InitLinkedList.LinkedListMode;
+
+ /* Update the DMA channel error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Update the DMA channel state */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitialize the DMA channel when it is configured in linked-list mode.
+ * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+ * specified DMA Channel.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma)
+{
+ /* Get DMA instance */
+ DMA_TypeDef *p_dma_instance;
+ /* Get tick number */
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Check the DMA peripheral handle parameter */
+ if (hdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+
+ /* Get DMA instance */
+ p_dma_instance = GET_DMA_INSTANCE(hdma);
+
+ /* Disable the selected DMA Channel */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Check if the DMA channel is effectively disabled */
+ while ((hdma->Instance->CCR & DMA_CCR_EN) != 0U)
+ {
+ /* Check for the Timeout */
+ if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
+ {
+ /* Update error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Reset DMA Channel registers */
+ hdma->Instance->CCR = 0U;
+ hdma->Instance->CLBAR = 0U;
+ hdma->Instance->CTR1 = 0U;
+ hdma->Instance->CTR2 = 0U;
+ hdma->Instance->CBR1 = 0U;
+ hdma->Instance->CSAR = 0U;
+ hdma->Instance->CDAR = 0U;
+ hdma->Instance->CLLR = 0U;
+
+ /* Reset 2D Addressing registers */
+ if (IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) != 0U)
+ {
+ hdma->Instance->CTR3 = 0U;
+ hdma->Instance->CBR2 = 0U;
+ }
+
+ /* Clear privilege attribute */
+ CLEAR_BIT(p_dma_instance->PRIVCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU)));
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ /* Clear secure attribute */
+ CLEAR_BIT(p_dma_instance->SECCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU)));
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+ /* Clear all flags */
+ __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP |
+ DMA_FLAG_TO));
+
+ /* Clean all callbacks */
+ hdma->XferCpltCallback = NULL;
+ hdma->XferHalfCpltCallback = NULL;
+ hdma->XferErrorCallback = NULL;
+ hdma->XferAbortCallback = NULL;
+ hdma->XferSuspendCallback = NULL;
+
+ /* Check the linked-list queue */
+ if(hdma->LinkedListQueue != NULL)
+ {
+ /* Update the queue state and error code */
+ hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
+ hdma->LinkedListQueue->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Clean DMA queue */
+ hdma->LinkedListQueue = NULL;
+ }
+
+ /* Clean DMA parent */
+ if (hdma->Parent != NULL)
+ {
+ hdma->Parent = NULL;
+ }
+
+ /* Update DMA channel operation mode */
+ hdma->Mode = DMA_NORMAL;
+
+ /* Update the DMA channel error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Update the DMA channel state */
+ hdma->State = HAL_DMA_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/** @addtogroup DMAEx_Exported_Functions_Group2
+ *
+@verbatim
+ ======================================================================================================================
+ ############### Linked-List I/O Operation Functions ###############
+ ======================================================================================================================
+ [..]
+ This section provides functions allowing to :
+ (+) Configure to start DMA transfer in linked-list mode.
+
+ [..]
+ (+) The HAL_DMAEx_List_Start() function allows to start the DMA channel transfer in linked-list mode (Blocking
+ mode).
+ (+) The HAL_DMAEx_List_Start_IT() function allows to start the DMA channel transfer in linked-list mode
+ (Non-blocking mode).
+ (++) It is mandatory to register a linked-list queue to be executed by a DMA channel before starting
+ transfer otherwise a HAL_ERROR will be returned.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start the DMA channel transfer in linked-list mode (Blocking mode).
+ * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+ * specified DMA Channel.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMAEx_List_Start(DMA_HandleTypeDef *const hdma)
+{
+ HAL_DMA_StateTypeDef dma_state;
+ uint32_t ccr_value;
+ uint32_t cllr_mask;
+
+ /* Check the DMA peripheral handle and the linked-list queue parameters */
+ if ((hdma == NULL) || (hdma->LinkedListQueue == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check DMA channel state */
+ dma_state = hdma->State;
+ ccr_value = hdma->Instance->CCR & DMA_CCR_LSM;
+ if ((dma_state == HAL_DMA_STATE_READY) || ((dma_state == HAL_DMA_STATE_BUSY) && (ccr_value != 0U)))
+ {
+ /* Check DMA channel state is ready */
+ if (hdma->State == HAL_DMA_STATE_READY)
+ {
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ /* Update the DMA channel and the queue states */
+ hdma->State = HAL_DMA_STATE_BUSY;
+ hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+ /* Update the DMA channel and the queue error codes */
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+ hdma->LinkedListQueue->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Get CLLR register mask and offset */
+ DMA_List_GetCLLRNodeInfo(hdma->LinkedListQueue->Head, &cllr_mask, NULL);
+
+ /* Update DMA registers for linked-list transfer */
+ hdma->Instance->CLBAR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLBAR_LBA);
+ hdma->Instance->CLLR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLLR_LA) | cllr_mask;
+ }
+
+ /* Enable DMA channel */
+ __HAL_DMA_ENABLE(hdma);
+ }
+ else
+ {
+ /* Update the DMA channel error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the DMA channel transfer in linked-list mode with interrupts enabled (Non-blocking mode).
+ * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+ * specified DMA Channel.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMAEx_List_Start_IT(DMA_HandleTypeDef *const hdma)
+{
+ HAL_DMA_StateTypeDef dma_state;
+ uint32_t ccr_value;
+ uint32_t cllr_mask;
+
+ /* Check the DMA peripheral handle and the linked-list queue parameters */
+ if ((hdma == NULL) || (hdma->LinkedListQueue == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check DMA channel state */
+ dma_state = hdma->State;
+ ccr_value = hdma->Instance->CCR & DMA_CCR_LSM;
+ if ((dma_state == HAL_DMA_STATE_READY) || ((dma_state == HAL_DMA_STATE_BUSY) && (ccr_value != 0U)))
+ {
+ /* Check DMA channel state is ready */
+ if (hdma->State == HAL_DMA_STATE_READY)
+ {
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ /* Update the DMA channel and the queue states */
+ hdma->State = HAL_DMA_STATE_BUSY;
+ hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+ /* Update the DMA channel and the queue error codes */
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+ hdma->LinkedListQueue->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Enable common interrupts: Transfer Complete and Transfer Errors ITs */
+ __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_DTE | DMA_IT_ULE | DMA_IT_USE | DMA_IT_TO));
+
+ /* Check half transfer complete callback */
+ if (hdma->XferHalfCpltCallback != NULL)
+ {
+ /* If half transfer complete callback is set, enable the corresponding IT */
+ __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
+ }
+
+ /* Check suspend callback */
+ if (hdma->XferSuspendCallback != NULL)
+ {
+ /* If transfer suspend callback is set, enable the corresponding IT */
+ __HAL_DMA_ENABLE_IT(hdma, DMA_IT_SUSP);
+ }
+
+ /* Get CLLR register mask and offset */
+ DMA_List_GetCLLRNodeInfo(hdma->LinkedListQueue->Head, &cllr_mask, NULL);
+
+ /* Update DMA registers for linked-list transfer */
+ hdma->Instance->CLBAR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLBAR_LBA);
+ hdma->Instance->CLLR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLLR_LA) | cllr_mask;
+ }
+
+ /* Enable DMA channel */
+ __HAL_DMA_ENABLE(hdma);
+ }
+ else
+ {
+ /* Change the error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/** @addtogroup DMAEx_Exported_Functions_Group3
+ *
+@verbatim
+ ======================================================================================================================
+ ############### Linked-List Management Functions ###############
+ ======================================================================================================================
+ [..]
+ This section provides functions allowing to :
+ (+) Build linked-list node.
+ (+) Get linked-list node configuration.
+ (+) Insert node to linked-list queue in any queue position.
+ (+) Remove any node from linked-list queue.
+ (+) Replace any node from linked-list queue.
+ (+) Reset linked-list queue.
+ (+) Insert linked-list queue in any queue position.
+ (+) Set circular mode configuration to linked-list queue.
+ (+) Clear circular mode configuration from linked-list queue.
+ (+) Convert static linked-list queue to dynamic format.
+ (+) Convert dynamic linked-list queue to static format.
+ (+) Link linked-list queue to DMA channel.
+ (+) Unlink linked-list queue from DMA channel.
+
+ [..]
+ (+) The HAL_DMAEx_List_BuildNode() function allows to build linked-list node.
+ Node type can be :
+ (++) 2 dimensions addressing node.
+ (++) Linear addressing node.
+
+ (+) The HAL_DMAEx_List_GetNodeConfig() function allows to get the linked-list node configuration from built node.
+
+ (+) The HAL_DMAEx_List_InsertNode() function allows to insert built linked-list node to static linked-list queue
+ according to selected position.
+
+ (+) The HAL_DMAEx_List_InsertNode_Head() and HAL_DMAEx_List_InsertNode_Tail() functions allow to insert built
+ linked-list node to the head (respectively the tail) of static linked-list queue.
+
+ (+) The HAL_DMAEx_List_RemoveNode() function allows to remove selected built linked-list node from static
+ linked-list queue.
+
+ (+) The HAL_DMAEx_List_RemoveNode_Head() and HAL_DMAEx_List_RemoveNode_Tail() functions allow to remove the head
+ (respectively the tail) built linked-list node from static linked-list queue.
+
+ (+) The HAL_DMAEx_List_ReplaceNode() function allows to replace selected built linked-list node from static
+ linked-list queue.
+
+ (+) The HAL_DMAEx_List_ReplaceNode_Head() and HAL_DMAEx_List_ReplaceNode_Tail() functions allow to replace the
+ head (respectively the tail) built linked-list node of static linked-list queue.
+
+ (+) The HAL_DMAEx_List_ResetQ() function allows to reset static linked-list queue and unlink all built linked-list
+ nodes.
+
+ (+) The HAL_DMAEx_List_InsertQ() function allows to insert static linked-list source queue to static linked-list
+ destination queue according to selected position.
+
+ (+) The HAL_DMAEx_List_InsertQ_Head() and HAL_DMAEx_List_InsertQ_Tail() functions allow to insert static
+ linked-list source queue to the head (respectively the tail) of static linked-list destination queue.
+
+ (+) The HAL_DMAEx_List_SetCircularModeConfig() function allows to link the last static linked-list queue node to
+ the selected first circular node.
+
+ (+) The HAL_DMAEx_List_SetCircularMode() function allows to link the last static linked-list queue node to the
+ first static linked-list queue node.
+
+ (+) The HAL_DMAEx_List_ClearCircularMode() function allows to unlink the last static linked-list queue node from
+ any first circular node position.
+
+ (+) The HAL_DMAEx_List_ConvertQToDynamic() function allows to convert the static linked-list queue to dynamic
+ format. (Optimized queue execution)
+
+ (+) The HAL_DMAEx_List_ConvertQToStatic() function allows to convert the dynamic linked-list queue to static
+ format. (Not optimized queue execution)
+
+ (+) The HAL_DMAEx_List_LinkQ() function allows to link the (Dynamic / Static) linked-list queue to DMA channel to
+ be executed.
+
+ (+) The HAL_DMAEx_List_UnLinkQ() function allows to unlink the (Dynamic / Static) linked-list queue from DMA
+ channel when execution is completed.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Build a DMA channel node according to the specified parameters in the DMA_NodeConfTypeDef.
+ * @param pNodeConfig : Pointer to a DMA_NodeConfTypeDef structure that contains the configuration information for the
+ * specified DMA linked-list Node.
+ * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers
+ * configurations.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig,
+ DMA_NodeTypeDef *const pNode)
+{
+ /* Check the node configuration and physical node parameters */
+ if ((pNodeConfig == NULL) || (pNode == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check node type parameter */
+ assert_param(IS_DMA_NODE_TYPE(pNodeConfig->NodeType));
+
+ /* Check DMA channel basic transfer parameters */
+ assert_param(IS_DMA_SOURCE_INC(pNodeConfig->Init.SrcInc));
+ assert_param(IS_DMA_DESTINATION_INC(pNodeConfig->Init.DestInc));
+ assert_param(IS_DMA_SOURCE_DATA_WIDTH(pNodeConfig->Init.SrcDataWidth));
+ assert_param(IS_DMA_DESTINATION_DATA_WIDTH(pNodeConfig->Init.DestDataWidth));
+ assert_param(IS_DMA_DATA_ALIGNMENT(pNodeConfig->DataHandlingConfig.DataAlignment));
+ assert_param(IS_DMA_REQUEST(pNodeConfig->Init.Request));
+ assert_param(IS_DMA_DIRECTION(pNodeConfig->Init.Direction));
+ assert_param(IS_DMA_TCEM_EVENT_MODE(pNodeConfig->Init.TransferEventMode));
+ assert_param(IS_DMA_BLOCK_HW_REQUEST(pNodeConfig->Init.BlkHWRequest));
+
+ /* Check DMA channel parameters */
+ if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_GPDMA) == DMA_CHANNEL_TYPE_GPDMA)
+ {
+ assert_param(IS_DMA_BURST_LENGTH(pNodeConfig->Init.SrcBurstLength));
+ assert_param(IS_DMA_BURST_LENGTH(pNodeConfig->Init.DestBurstLength));
+ assert_param(IS_DMA_DATA_EXCHANGE(pNodeConfig->DataHandlingConfig.DataExchange));
+ assert_param(IS_DMA_TRANSFER_ALLOCATED_PORT(pNodeConfig->Init.TransferAllocatedPort));
+ }
+
+ /* Check DMA channel trigger parameters */
+ assert_param(IS_DMA_TRIGGER_POLARITY(pNodeConfig->TriggerConfig.TriggerPolarity));
+ if (pNodeConfig->TriggerConfig.TriggerPolarity != DMA_TRIG_POLARITY_MASKED)
+ {
+ assert_param(IS_DMA_TRIGGER_MODE(pNodeConfig->TriggerConfig.TriggerMode));
+ assert_param(IS_DMA_TRIGGER_SELECTION(pNodeConfig->TriggerConfig.TriggerSelection));
+ }
+
+ /* Check DMA channel repeated block parameters */
+ if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR)
+ {
+ assert_param(IS_DMA_REPEAT_COUNT(pNodeConfig->RepeatBlockConfig.RepeatCount));
+ assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.SrcAddrOffset));
+ assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.DestAddrOffset));
+ assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset));
+ assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset));
+ assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.SrcAddrOffset));
+ assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.DestAddrOffset));
+ assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset));
+ assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset));
+ }
+
+ /* Check DMA channel security and privilege attributes parameters */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ assert_param(IS_DMA_ATTRIBUTES(pNodeConfig->SrcSecure));
+ assert_param(IS_DMA_ATTRIBUTES(pNodeConfig->DestSecure));
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+ /* Build the DMA channel node */
+ DMA_List_BuildNode(pNodeConfig, pNode);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get a DMA channel node configuration.
+ * @param pNodeConfig : Pointer to a DMA_NodeConfTypeDef structure that contains the configuration information for the
+ * specified DMA linked-list Node.
+ * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers
+ * configurations.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMAEx_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig,
+ DMA_NodeTypeDef const *const pNode)
+{
+ /* Check the node configuration and physical node parameters */
+ if ((pNodeConfig == NULL) || (pNode == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Get the DMA channel node configuration */
+ DMA_List_GetNodeConfig(pNodeConfig, pNode);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Insert new node in any queue position of linked-list queue according to selecting previous node.
+ * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
+ * @param pPrevNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list previous node registers
+ * configurations.
+ * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers
+ * configurations.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMAEx_List_InsertNode(DMA_QListTypeDef *const pQList,
+ DMA_NodeTypeDef *const pPrevNode,
+ DMA_NodeTypeDef *const pNewNode)
+{
+ uint32_t cllr_mask;
+ uint32_t cllr_offset;
+ DMA_NodeInQInfoTypeDef node_info;
+
+ /* Check the queue and the new node parameters */
+ if ((pQList == NULL) || (pNewNode == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check queue type */
+ if (pQList->Type == QUEUE_TYPE_DYNAMIC)
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+ return HAL_ERROR;
+ }
+
+ /* Check nodes base addresses */
+ if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pPrevNode, pNewNode) != 0U)
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
+
+ return HAL_ERROR;
+ }
+
+ /* Check nodes types compatibility */
+ if (DMA_List_CheckNodesTypes(pQList->Head, pPrevNode, pNewNode) != 0U)
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+ return HAL_ERROR;
+ }
+
+ /* Update the queue state */
+ pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Get CLLR register mask and offset */
+ DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset);
+
+ /* Empty queue */
+ if (pQList->Head == NULL)
+ {
+ /* Add only new node to queue */
+ if (pPrevNode == NULL)
+ {
+ pQList->Head = pNewNode;
+ pQList->NodeNumber = 1U;
+ }
+ /* Add previous node then new node to queue */
+ else
+ {
+ pQList->Head = pPrevNode;
+ pPrevNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask;
+ pQList->NodeNumber = 2U;
+ }
+ }
+ /* Not empty queue */
+ else
+ {
+ /* Add new node at the head of queue */
+ if (pPrevNode == NULL)
+ {
+ pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->Head & DMA_CLLR_LA) | cllr_mask;
+ pQList->Head = pNewNode;
+ }
+ /* Add new node according to selected position */
+ else
+ {
+ /* Find node and get its position in selected queue */
+ node_info.cllr_offset = cllr_offset;
+ if (DMA_List_FindNode(pQList, pPrevNode, &node_info) == 0U)
+ {
+ /* Selected node is the last queue node */
+ if (node_info.currentnode_pos == pQList->NodeNumber)
+ {
+ /* Check if queue is circular */
+ if (pQList->FirstCircularNode != NULL)
+ {
+ pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->FirstCircularNode & DMA_CLLR_LA) | cllr_mask;
+ }
+
+ pPrevNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask;
+ }
+ /* Selected node is not the last queue node */
+ else
+ {
+ pNewNode->LinkRegisters[cllr_offset] = pPrevNode->LinkRegisters[cllr_offset];
+ pPrevNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask;
+ }
+ }
+ else
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND;
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Increment queue node number */
+ pQList->NodeNumber++;
+ }
+
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Update the queue state */
+ pQList->State = HAL_DMA_QUEUE_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Insert new node at the head of linked-list queue.
+ * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
+ * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers
+ * configurations.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Head(DMA_QListTypeDef *const pQList,
+ DMA_NodeTypeDef *const pNewNode)
+{
+ uint32_t cllr_mask;
+ uint32_t cllr_offset;
+
+ /* Check the queue and the new node parameters */
+ if ((pQList == NULL) || (pNewNode == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check queue type */
+ if (pQList->Type == QUEUE_TYPE_DYNAMIC)
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+ return HAL_ERROR;
+ }
+
+ /* Check nodes base addresses */
+ if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U)
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
+
+ return HAL_ERROR;
+ }
+
+ /* Check nodes types compatibility */
+ if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U)
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+ return HAL_ERROR;
+ }
+
+ /* Update the queue state */
+ pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Empty queue */
+ if (pQList->Head == NULL)
+ {
+ pQList->Head = pNewNode;
+ }
+ /* Not empty queue */
+ else
+ {
+ /* Get CLLR register mask and offset */
+ DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset);
+
+ pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->Head & DMA_CLLR_LA) | cllr_mask;
+ pQList->Head = pNewNode;
+ }
+
+ /* Increment queue node number */
+ pQList->NodeNumber++;
+
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Update the queue state */
+ pQList->State = HAL_DMA_QUEUE_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Insert new node at the tail of linked-list queue.
+ * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
+ * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers
+ * configurations.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Tail(DMA_QListTypeDef *const pQList,
+ DMA_NodeTypeDef *const pNewNode)
+{
+ uint32_t cllr_mask;
+ uint32_t cllr_offset;
+ DMA_NodeInQInfoTypeDef node_info;
+
+ /* Check the queue and the new node parameters */
+ if ((pQList == NULL) || (pNewNode == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check queue type */
+ if (pQList->Type == QUEUE_TYPE_DYNAMIC)
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+ return HAL_ERROR;
+ }
+
+ /* Check nodes base addresses */
+ if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U)
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
+
+ return HAL_ERROR;
+ }
+
+ /* Check nodes types compatibility */
+ if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U)
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+ return HAL_ERROR;
+ }
+
+ /* Empty queue */
+ if (pQList->Head == NULL)
+ {
+ pQList->Head = pNewNode;
+ }
+ /* Not empty queue */
+ else
+ {
+ /* Get CLLR register mask and offset */
+ DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset);
+
+ /* Find node and get its position in selected queue */
+ node_info.cllr_offset = cllr_offset;
+ (void)DMA_List_FindNode(pQList, NULL, &node_info);
+
+ /* Check if queue is circular */
+ if (pQList->FirstCircularNode != NULL)
+ {
+ pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->FirstCircularNode & DMA_CLLR_LA) | cllr_mask;
+ }
+
+ ((DMA_NodeTypeDef *)node_info.currentnode_addr)->LinkRegisters[cllr_offset] =
+ ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask;
+ }
+
+ /* Increment queue node number */
+ pQList->NodeNumber++;
+
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Update the queue state */
+ pQList->State = HAL_DMA_QUEUE_STATE_READY;
+
+ /* Prevent MISRA-C2012-Rule-2.2_b */
+ UNUSED(node_info);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Remove node from any linked-list queue position.
+ * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
+ * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list previous node registers
+ * configurations.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode(DMA_QListTypeDef *const pQList,
+ DMA_NodeTypeDef *const pNode)
+{
+ uint32_t previousnode_addr;
+ uint32_t cllr_offset;
+ DMA_NodeInQInfoTypeDef node_info;
+
+ /* Check the queue and the node parameters */
+ if ((pQList == NULL) || (pNode == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the queue */
+ if (pQList->Head == NULL)
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
+
+ return HAL_ERROR;
+ }
+
+ /* Check queue type */
+ if (pQList->Type == QUEUE_TYPE_DYNAMIC)
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+ return HAL_ERROR;
+ }
+
+ /* Update the queue state */
+ pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Get CLLR register mask and offset */
+ DMA_List_GetCLLRNodeInfo(pNode, NULL, &cllr_offset);
+
+ /* Find node and get its position in selected queue */
+ node_info.cllr_offset = cllr_offset;
+ if (DMA_List_FindNode(pQList, pNode, &node_info) == 0U)
+ {
+ /* Removed node is the head node */
+ if (node_info.currentnode_pos == 1U)
+ {
+ /* Check if first circular node queue is the first node */
+ if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)node_info.currentnode_addr))
+ {
+ /* Find last queue node */
+ (void)DMA_List_FindNode(pQList, NULL, &node_info);
+
+ /* Clear last node link */
+ ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U;
+
+ /* Clear first circular node */
+ pQList->FirstCircularNode = NULL;
+ }
+
+ /* Update the queue head node */
+ pQList->Head = (DMA_NodeTypeDef *)(((uint32_t)pQList->Head & DMA_CLBAR_LBA) +
+ (pNode->LinkRegisters[cllr_offset] & DMA_CLLR_LA));
+ /* Unlink node to be removed */
+ pNode->LinkRegisters[cllr_offset] = 0U;
+ }
+ /* Removed node is the last node */
+ else if (node_info.currentnode_pos == pQList->NodeNumber)
+ {
+ /* Clear CLLR for previous node */
+ ((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] = 0U;
+
+ /* Clear CLLR for last node */
+ ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U;
+
+ /* Clear first circular node */
+ pQList->FirstCircularNode = NULL;
+ }
+ /* Removed node is in the middle */
+ else
+ {
+ /* Store previous node address to be updated later */
+ previousnode_addr = node_info.previousnode_addr;
+
+ /* Check if first circular node queue is the current node */
+ if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)node_info.currentnode_addr))
+ {
+ /* Find last queue node */
+ (void)DMA_List_FindNode(pQList, NULL, &node_info);
+
+ /* Clear last node link */
+ ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U;
+
+ /* Clear first circular node */
+ pQList->FirstCircularNode = NULL;
+ }
+
+ /* Link previous node */
+ ((DMA_NodeTypeDef *)(previousnode_addr))->LinkRegisters[cllr_offset] = pNode->LinkRegisters[cllr_offset];
+
+ /* Unlink node to be removed */
+ pNode->LinkRegisters[cllr_offset] = 0U;
+ }
+
+ /* Decrement node number */
+ pQList->NodeNumber--;
+ }
+ else
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND;
+
+ return HAL_ERROR;
+ }
+
+ /* Check if queue is empty */
+ if (pQList->NodeNumber == 0U)
+ {
+ /* Clean empty queue parameter */
+ DMA_List_CleanQueue(pQList);
+ }
+ else
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Update the queue state */
+ pQList->State = HAL_DMA_QUEUE_STATE_READY;
+ }
+
+ /* Prevent MISRA-C2012-Rule-2.2_b */
+ UNUSED(node_info);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Remove the head node from linked-list queue.
+ * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Head(DMA_QListTypeDef *const pQList)
+{
+ uint32_t cllr_offset;
+ uint32_t current_addr;
+ DMA_NodeInQInfoTypeDef node_info;
+
+ /* Check the queue parameter */
+ if (pQList == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the queue */
+ if (pQList->Head == NULL)
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
+
+ return HAL_ERROR;
+ }
+
+ /* Check queue type */
+ if (pQList->Type == QUEUE_TYPE_DYNAMIC)
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+ return HAL_ERROR;
+ }
+
+ /* Update the queue state */
+ pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Get CLLR register mask and offset */
+ DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset);
+
+ /* Queue contains only one node */
+ if (pQList->NodeNumber == 1U)
+ {
+ pQList->Head->LinkRegisters[cllr_offset] = 0U;
+ pQList->FirstCircularNode = 0U;
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+ }
+ /* Queue contains more then one node */
+ else
+ {
+ /* Check if first circular node queue is the first node */
+ if (pQList->FirstCircularNode == pQList->Head)
+ {
+ /* Find last queue node */
+ node_info.cllr_offset = cllr_offset;
+ (void)DMA_List_FindNode(pQList, NULL, &node_info);
+
+ /* Clear last node link */
+ ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U;
+
+ /* Clear first circular node */
+ pQList->FirstCircularNode = NULL;
+ }
+
+ current_addr = pQList->Head->LinkRegisters[cllr_offset] & DMA_CLLR_LA;
+ pQList->Head->LinkRegisters[cllr_offset] = 0U;
+ pQList->Head = ((DMA_NodeTypeDef *)(current_addr + ((uint32_t)pQList->Head & DMA_CLBAR_LBA)));
+ }
+
+ /* Decrement node number */
+ pQList->NodeNumber--;
+
+ /* Check if queue is empty */
+ if (pQList->NodeNumber == 0U)
+ {
+ /* Clean empty queue parameter */
+ DMA_List_CleanQueue(pQList);
+ }
+ else
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Update the queue state */
+ pQList->State = HAL_DMA_QUEUE_STATE_READY;
+ }
+
+ /* Prevent MISRA-C2012-Rule-2.2_b */
+ UNUSED(node_info);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Remove the tail node from linked-list queue.
+ * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Tail(DMA_QListTypeDef *const pQList)
+{
+ uint32_t cllr_offset;
+ DMA_NodeInQInfoTypeDef node_info;
+
+ /* Check the queue parameter */
+ if (pQList == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the queue */
+ if (pQList->Head == NULL)
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
+
+ return HAL_ERROR;
+ }
+
+ /* Check queue type */
+ if (pQList->Type == QUEUE_TYPE_DYNAMIC)
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+ return HAL_ERROR;
+ }
+
+ /* Update the queue state */
+ pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Get CLLR register mask and offset */
+ DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset);
+
+ /* Queue contains only one node */
+ if (pQList->NodeNumber == 1U)
+ {
+ pQList->Head->LinkRegisters[cllr_offset] = 0U;
+ pQList->FirstCircularNode = 0U;
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+ }
+ /* Queue contains more then one node */
+ else
+ {
+ /* Find node and get its position in selected queue */
+ node_info.cllr_offset = cllr_offset;
+ (void)DMA_List_FindNode(pQList, NULL, &node_info);
+
+ /* Clear CLLR for previous node */
+ ((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] = 0U;
+
+ /* Clear CLLR for last node */
+ ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U;
+
+ /* Clear first circular node */
+ pQList->FirstCircularNode = NULL;
+ }
+
+ /* Decrement node number */
+ pQList->NodeNumber--;
+
+ /* Check if queue is empty */
+ if (pQList->NodeNumber == 0U)
+ {
+ /* Clean empty queue parameter */
+ DMA_List_CleanQueue(pQList);
+ }
+ else
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Update the queue state */
+ pQList->State = HAL_DMA_QUEUE_STATE_READY;
+ }
+
+ /* Prevent MISRA-C2012-Rule-2.2_b */
+ UNUSED(node_info);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Replace node in linked-list queue.
+ * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
+ * @param pOldNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list old node registers
+ * configurations.
+ * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers
+ * configurations.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode(DMA_QListTypeDef *const pQList,
+ DMA_NodeTypeDef *const pOldNode,
+ DMA_NodeTypeDef *const pNewNode)
+{
+ uint32_t cllr_mask;
+ uint32_t cllr_offset;
+ DMA_NodeInQInfoTypeDef node_info;
+
+ /* Check the queue and the nodes parameters */
+ if ((pQList == NULL) || (pOldNode == NULL) || (pNewNode == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the queue */
+ if (pQList->Head == NULL)
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
+
+ return HAL_ERROR;
+ }
+
+ /* Check queue type */
+ if (pQList->Type == QUEUE_TYPE_DYNAMIC)
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+ return HAL_ERROR;
+ }
+
+ /* Check nodes base addresses */
+ if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pOldNode, pNewNode) != 0U)
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
+
+ return HAL_ERROR;
+ }
+
+ /* Check nodes types compatibility */
+ if (DMA_List_CheckNodesTypes(pQList->Head, pOldNode, pNewNode) != 0U)
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+ return HAL_ERROR;
+ }
+
+ /* Update the queue state */
+ pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Get CLLR register mask and offset */
+ DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset);
+
+ /* Find node and get its position in selected queue */
+ node_info.cllr_offset = cllr_offset;
+ if (DMA_List_FindNode(pQList, pOldNode, &node_info) == 0U)
+ {
+ /* Replaced node is the head node */
+ if (node_info.currentnode_pos == 1U)
+ {
+ pNewNode->LinkRegisters[cllr_offset] =
+ ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset];
+ pQList->Head = pNewNode;
+ ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U;
+
+ /* Check if first circular node queue is the first node */
+ if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)node_info.currentnode_addr))
+ {
+ /* Find last queue node */
+ (void)DMA_List_FindNode(pQList, NULL, &node_info);
+
+ /* Clear last node link */
+ ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] =
+ ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask;
+
+ /* Set new node as first circular node */
+ pQList->FirstCircularNode = pNewNode;
+ }
+ }
+ /* Replaced node is the last */
+ else if (node_info.currentnode_pos == pQList->NodeNumber)
+ {
+ ((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] =
+ ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask;
+ ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U;
+
+ /* Check if first circular node queue is the last node */
+ if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)(node_info.currentnode_addr)))
+ {
+ /* Link first circular node to new node */
+ pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask;
+
+ /* Set new node as first circular node */
+ pQList->FirstCircularNode = pNewNode;
+ }
+ /* Check if first circular node queue is not the last node */
+ else if (pQList->FirstCircularNode != NULL)
+ {
+ /* Link first circular node to new node */
+ pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->FirstCircularNode & DMA_CLLR_LA) | cllr_mask;
+ }
+ else
+ {
+ /* Prevent MISRA-C2012-Rule-15.7 */
+ }
+ }
+ /* Replaced node is in the middle */
+ else
+ {
+ ((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] =
+ ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask;
+ pNewNode->LinkRegisters[cllr_offset] =
+ ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset];
+ ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U;
+
+ /* Check if first circular node queue is the current node */
+ if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)(node_info.currentnode_addr)))
+ {
+ /* Find last node and get its position in selected queue */
+ (void)DMA_List_FindNode(pQList, NULL, &node_info);
+
+ /* Link last queue node to new node */
+ ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] =
+ ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask;
+
+ /* Set new node as first circular node */
+ pQList->FirstCircularNode = pNewNode;
+ }
+ }
+ }
+ else
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND;
+
+ return HAL_ERROR;
+ }
+
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Update the queue state */
+ pQList->State = HAL_DMA_QUEUE_STATE_READY;
+
+ /* Prevent MISRA-C2012-Rule-2.2_b */
+ UNUSED(node_info);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Replace the head node of linked-list queue.
+ * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
+ * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers
+ * configurations.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Head(DMA_QListTypeDef *const pQList,
+ DMA_NodeTypeDef *const pNewNode)
+{
+ uint32_t cllr_offset;
+ uint32_t cllr_mask;
+ DMA_NodeInQInfoTypeDef node_info;
+
+ /* Check the queue and the new node parameters */
+ if ((pQList == NULL) || (pNewNode == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the queue */
+ if (pQList->Head == NULL)
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
+
+ return HAL_ERROR;
+ }
+
+ /* Check queue type */
+ if (pQList->Type == QUEUE_TYPE_DYNAMIC)
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+ return HAL_ERROR;
+ }
+
+ /* Check nodes base addresses */
+ if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U)
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
+
+ return HAL_ERROR;
+ }
+
+ /* Check nodes types compatibility */
+ if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U)
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+ return HAL_ERROR;
+ }
+
+ /* Update the queue state */
+ pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Get CLLR register mask and offset */
+ DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset);
+
+ /* Check if first circular node queue is the first node */
+ if (pQList->FirstCircularNode == pQList->Head)
+ {
+ /* Find last queue node */
+ node_info.cllr_offset = cllr_offset;
+ (void)DMA_List_FindNode(pQList, NULL, &node_info);
+
+ /* Clear last node link */
+ ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] =
+ ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask;
+
+ /* Set new node as first circular node */
+ pQList->FirstCircularNode = pNewNode;
+ }
+
+ /* Replace head node */
+ pNewNode->LinkRegisters[cllr_offset] = pQList->Head->LinkRegisters[cllr_offset];
+ pQList->Head->LinkRegisters[cllr_offset] = 0U;
+ pQList->Head = pNewNode;
+
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Update the queue state */
+ pQList->State = HAL_DMA_QUEUE_STATE_READY;
+
+ /* Prevent MISRA-C2012-Rule-2.2_b */
+ UNUSED(node_info);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Replace the tail node of linked-list queue.
+ * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
+ * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers
+ * configurations.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Tail(DMA_QListTypeDef *const pQList,
+ DMA_NodeTypeDef *const pNewNode)
+{
+ uint32_t cllr_mask;
+ uint32_t cllr_offset;
+ DMA_NodeInQInfoTypeDef node_info;
+
+ /* Check the queue and the new node parameters */
+ if ((pQList == NULL) || (pNewNode == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the queue */
+ if (pQList->Head == NULL)
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
+
+ return HAL_ERROR;
+ }
+
+ /* Check queue type */
+ if (pQList->Type == QUEUE_TYPE_DYNAMIC)
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+ return HAL_ERROR;
+ }
+
+ /* Update the queue state */
+ pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Get CLLR register mask and offset */
+ DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset);
+
+ /* Find last node and get its position in selected queue */
+ node_info.cllr_offset = cllr_offset;
+ (void)DMA_List_FindNode(pQList, NULL, &node_info);
+
+ /* Link previous node to new node */
+ ((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] =
+ ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask;
+
+ /* Clear CLLR for current node */
+ ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U;
+
+ /* Check if first circular node queue is the last node */
+ if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)(node_info.currentnode_addr)))
+ {
+ /* Link first circular node to new node */
+ pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask;
+
+ /* Set new node as first circular node */
+ pQList->FirstCircularNode = pNewNode;
+ }
+ /* Check if first circular node queue is not the last node */
+ else if (pQList->FirstCircularNode != NULL)
+ {
+ /* Link first circular node to new node */
+ pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->FirstCircularNode & DMA_CLLR_LA) | cllr_mask;
+ }
+ else
+ {
+ /* Prevent MISRA-C2012-Rule-15.7 */
+ }
+
+ /* Check if queue contains one node */
+ if (pQList->NodeNumber == 1U)
+ {
+ pQList->Head = pNewNode;
+ }
+
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Update the queue state */
+ pQList->State = HAL_DMA_QUEUE_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Reset the linked-list queue and unlink queue nodes.
+ * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMAEx_List_ResetQ(DMA_QListTypeDef *const pQList)
+{
+ uint32_t cllr_offset;
+ DMA_NodeInQInfoTypeDef node_info;
+
+ /* Check the queue parameter */
+ if (pQList == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check queue state */
+ if (pQList->State == HAL_DMA_QUEUE_STATE_BUSY)
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_BUSY;
+
+ return HAL_ERROR;
+ }
+
+ /* Check queue type */
+ if (pQList->Type == QUEUE_TYPE_DYNAMIC)
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+ return HAL_ERROR;
+ }
+
+ /* Update the queue state */
+ pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Check the queue */
+ if (pQList->Head != NULL)
+ {
+ /* Get CLLR register mask and offset */
+ DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset);
+
+ /* Reset selected queue nodes */
+ node_info.cllr_offset = cllr_offset;
+ DMA_List_ResetQueueNodes(pQList, &node_info);
+ }
+
+ /* Reset head node address */
+ pQList->Head = NULL;
+
+ /* Reset node number */
+ pQList->NodeNumber = 0U;
+
+ /* Reset first circular node */
+ pQList->FirstCircularNode = NULL;
+
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Update the queue state */
+ pQList->State = HAL_DMA_QUEUE_STATE_RESET;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Insert a source linked-list queue to a destination linked-list queue according to selecting previous node.
+ * @param pSrcQList : Pointer to a DMA_QListTypeDef structure that contains source queue information.
+ * @param pPrevNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list previous node registers
+ * configurations.
+ * @param pDestQList : Pointer to a DMA_QListTypeDef structure that contains destination queue information.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMAEx_List_InsertQ(DMA_QListTypeDef *const pSrcQList,
+ DMA_NodeTypeDef const *const pPrevNode,
+ DMA_QListTypeDef *const pDestQList)
+{
+ uint32_t cllr_mask;
+ uint32_t cllr_offset;
+ DMA_NodeInQInfoTypeDef src_q_node_info;
+ DMA_NodeInQInfoTypeDef dest_q_node_info;
+
+ /* Check the source and destination queues and the previous node parameters */
+ if ((pSrcQList == NULL) || (pDestQList == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the source queue */
+ if (pSrcQList->Head == NULL)
+ {
+ /* Update the queue error code */
+ pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
+
+ return HAL_ERROR;
+ }
+
+ /* Check the source queue type */
+ if (pSrcQList->Type == QUEUE_TYPE_DYNAMIC)
+ {
+ /* Update the queue error code */
+ pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+ return HAL_ERROR;
+ }
+
+ /* Check the destination queue type */
+ if (pDestQList->Type == QUEUE_TYPE_DYNAMIC)
+ {
+ /* Update the queue error code */
+ pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+ return HAL_ERROR;
+ }
+
+ /* Check the source queue circularity */
+ if (pSrcQList->FirstCircularNode != NULL)
+ {
+ /* Update the source queue error code */
+ pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+ return HAL_ERROR;
+ }
+
+ /* Check nodes base addresses */
+ if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pPrevNode, pDestQList->Head) != 0U)
+ {
+ /* Update the source queue error code */
+ pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
+
+ /* Update the destination queue error code */
+ pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
+
+ return HAL_ERROR;
+ }
+
+ /* Check nodes types compatibility */
+ if (DMA_List_CheckNodesTypes(pSrcQList->Head, pPrevNode, pDestQList->Head) != 0U)
+ {
+ /* Update the source queue error code */
+ pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+ /* Update the destination queue error code */
+ pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+ return HAL_ERROR;
+ }
+
+ /* Update the source queue state */
+ pSrcQList->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+ /* Update the source queue error code */
+ pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Update the destination queue state */
+ pDestQList->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+ /* Update the destination queue error code */
+ pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Get CLLR register mask and offset */
+ DMA_List_GetCLLRNodeInfo(pSrcQList->Head, &cllr_mask, &cllr_offset);
+
+ /* Empty destination queue */
+ if (pDestQList->Head == NULL)
+ {
+ pDestQList->Head = pSrcQList->Head;
+ pDestQList->NodeNumber = pSrcQList->NodeNumber;
+ }
+ /* Not empty destination queue */
+ else
+ {
+ /* Previous node is empty */
+ if (pPrevNode == NULL)
+ {
+ /* Find node and get its position in selected queue */
+ src_q_node_info.cllr_offset = cllr_offset;
+ (void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info);
+
+ /* Check if first circular node queue is the first node */
+ if (pDestQList->FirstCircularNode == pDestQList->Head)
+ {
+ /* Find node and get its position in selected queue */
+ dest_q_node_info.cllr_offset = cllr_offset;
+ (void)DMA_List_FindNode(pDestQList, NULL, &dest_q_node_info);
+
+ /* Link destination queue tail node to new first circular node */
+ ((DMA_NodeTypeDef *)dest_q_node_info.currentnode_addr)->LinkRegisters[cllr_offset] =
+ ((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask;
+
+ /* Set the head node of source queue as the first circular node */
+ pDestQList->FirstCircularNode = pSrcQList->Head;
+ }
+
+ /* Link the last node of source queue to the fist node of destination queue */
+ ((DMA_NodeTypeDef *)(src_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] =
+ ((uint32_t)pDestQList->Head & DMA_CLLR_LA) | cllr_mask;
+ pDestQList->Head = pSrcQList->Head;
+ pDestQList->NodeNumber += pSrcQList->NodeNumber;
+ }
+ /* Previous node is not empty */
+ else
+ {
+ /* Find node and get its position in selected queue */
+ dest_q_node_info.cllr_offset = cllr_offset;
+ if (DMA_List_FindNode(pDestQList, pPrevNode, &dest_q_node_info) == 0U)
+ {
+ /* Selected node is the last destination queue node */
+ if (dest_q_node_info.currentnode_pos == pDestQList->NodeNumber)
+ {
+ /* Link the first node of source queue to the last node of destination queue */
+ ((DMA_NodeTypeDef *)(dest_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] =
+ ((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask;
+ pDestQList->NodeNumber += pSrcQList->NodeNumber;
+
+ /* Check if first circular node queue is not empty */
+ if (pDestQList->FirstCircularNode != NULL)
+ {
+ /* Find node and get its position in selected queue */
+ src_q_node_info.cllr_offset = cllr_offset;
+ (void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info);
+
+ /* Find first circular node */
+ (void)DMA_List_FindNode(pDestQList, pDestQList->FirstCircularNode, &dest_q_node_info);
+
+ /* Link last source queue node to first destination queue */
+ ((DMA_NodeTypeDef *)src_q_node_info.currentnode_addr)->LinkRegisters[cllr_offset] =
+ (dest_q_node_info.currentnode_addr & DMA_CLLR_LA) | cllr_mask;
+ }
+ }
+ /* Selected node is not the last destination queue node */
+ else
+ {
+ /* Link the first node of source queue to the previous node of destination queue */
+ ((DMA_NodeTypeDef *)(dest_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] =
+ ((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask;
+
+ /* Find node and get its position in selected queue */
+ src_q_node_info.cllr_offset = cllr_offset;
+ (void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info);
+
+ /* Link the last node of source queue to the next node of destination queue */
+ ((DMA_NodeTypeDef *)(src_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] =
+ (dest_q_node_info.nextnode_addr & DMA_CLLR_LA) | cllr_mask;
+
+ /* Update queues counter */
+ pDestQList->NodeNumber += pSrcQList->NodeNumber;
+ }
+ }
+ else
+ {
+ /* Update the destination queue error code */
+ pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND;
+
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Clean the source queue variable as it is obsolete */
+ DMA_List_CleanQueue(pSrcQList);
+
+ /* Update the destination queue error code */
+ pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Update the destination queue state */
+ pDestQList->State = HAL_DMA_QUEUE_STATE_READY;
+
+ /* Prevent MISRA-C2012-Rule-2.2_b */
+ UNUSED(src_q_node_info);
+ UNUSED(dest_q_node_info);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Insert a source linked-list queue at the head of destination queue.
+ * @param pSrcQList : Pointer to a DMA_QListTypeDef structure that contains source queue information.
+ * @param pDestQList : Pointer to a DMA_QListTypeDef structure that contains destination queue information.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Head(DMA_QListTypeDef *const pSrcQList,
+ DMA_QListTypeDef *const pDestQList)
+{
+ uint32_t cllr_mask;
+ uint32_t cllr_offset;
+ DMA_NodeInQInfoTypeDef src_q_node_info;
+ DMA_NodeInQInfoTypeDef dest_q_node_info;
+
+ /* Check the source and destination queues and the previous node parameters */
+ if ((pSrcQList == NULL) || (pDestQList == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the source queue */
+ if (pSrcQList->Head == NULL)
+ {
+ /* Update the queue error code */
+ pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
+
+ return HAL_ERROR;
+ }
+
+ /* Check the source queue type */
+ if (pSrcQList->Type == QUEUE_TYPE_DYNAMIC)
+ {
+ /* Update the queue error code */
+ pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+ return HAL_ERROR;
+ }
+
+ /* Check the destination queue type */
+ if (pDestQList->Type == QUEUE_TYPE_DYNAMIC)
+ {
+ /* Update the queue error code */
+ pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+ return HAL_ERROR;
+ }
+
+ /* Check nodes base addresses */
+ if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pDestQList->Head, NULL) != 0U)
+ {
+ /* Update the source queue error code */
+ pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
+
+ /* Update the destination queue error code */
+ pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
+
+ return HAL_ERROR;
+ }
+
+ /* Check nodes types compatibility */
+ if (DMA_List_CheckNodesTypes(pSrcQList->Head, pDestQList->Head, NULL) != 0U)
+ {
+ /* Update the source queue error code */
+ pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+ /* Update the destination queue error code */
+ pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+ return HAL_ERROR;
+ }
+
+ /* Update the source queue state */
+ pSrcQList->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+ /* Update the source queue error code */
+ pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Update the destination queue state */
+ pDestQList->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+ /* Update the destination queue error code */
+ pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Get CLLR register mask and offset */
+ DMA_List_GetCLLRNodeInfo(pSrcQList->Head, &cllr_mask, &cllr_offset);
+
+ /* Empty destination queue */
+ if (pDestQList->Head == NULL)
+ {
+ pDestQList->Head = pSrcQList->Head;
+ pDestQList->NodeNumber = pSrcQList->NodeNumber;
+ }
+ /* Not empty destination queue */
+ else
+ {
+ /* Find node and get its position in selected queue */
+ src_q_node_info.cllr_offset = cllr_offset;
+ (void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info);
+
+ /* Check if first circular node queue is the first node */
+ if (pDestQList->FirstCircularNode == pDestQList->Head)
+ {
+ /* Find node and get its position in selected queue */
+ dest_q_node_info.cllr_offset = cllr_offset;
+ (void)DMA_List_FindNode(pDestQList, NULL, &dest_q_node_info);
+
+ /* Link destination queue tail node to new first circular node */
+ ((DMA_NodeTypeDef *)dest_q_node_info.currentnode_addr)->LinkRegisters[cllr_offset] =
+ ((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask;
+
+ /* Set the head node of source queue as the first circular node */
+ pDestQList->FirstCircularNode = pSrcQList->Head;
+ }
+
+ /* Link the last node of source queue to the fist node of destination queue */
+ ((DMA_NodeTypeDef *)(src_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] =
+ ((uint32_t)pDestQList->Head & DMA_CLLR_LA) | cllr_mask;
+ pDestQList->Head = pSrcQList->Head;
+ pDestQList->NodeNumber += pSrcQList->NodeNumber;
+ }
+
+ /* Clean the source queue variable as it is obsolete */
+ DMA_List_CleanQueue(pSrcQList);
+
+ /* Update the destination queue error code */
+ pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Update the destination queue state */
+ pDestQList->State = HAL_DMA_QUEUE_STATE_READY;
+
+ /* Prevent MISRA-C2012-Rule-2.2_b */
+ UNUSED(src_q_node_info);
+ UNUSED(dest_q_node_info);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Insert a source linked-list queue at the tail of destination queue.
+ * @param pSrcQList : Pointer to a DMA_QListTypeDef structure that contains source queue information.
+ * @param pDestQList : Pointer to a DMA_QListTypeDef structure that contains destination queue information.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Tail(DMA_QListTypeDef *const pSrcQList,
+ DMA_QListTypeDef *const pDestQList)
+{
+ uint32_t cllr_mask;
+ uint32_t cllr_offset;
+ DMA_NodeInQInfoTypeDef src_q_node_info;
+ DMA_NodeInQInfoTypeDef dest_q_node_info;
+
+ /* Check the source and destination queues and the previous node parameters */
+ if ((pSrcQList == NULL) || (pDestQList == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the source queue */
+ if (pSrcQList->Head == NULL)
+ {
+ /* Update the queue error code */
+ pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
+
+ return HAL_ERROR;
+ }
+
+ /* Check the source queue type */
+ if (pSrcQList->Type == QUEUE_TYPE_DYNAMIC)
+ {
+ /* Update the queue error code */
+ pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+ return HAL_ERROR;
+ }
+
+ /* Check the destination queue type */
+ if (pDestQList->Type == QUEUE_TYPE_DYNAMIC)
+ {
+ /* Update the queue error code */
+ pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+ return HAL_ERROR;
+ }
+
+ /* Check nodes base addresses */
+ if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pDestQList->Head, NULL) != 0U)
+ {
+ /* Update the source queue error code */
+ pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
+
+ /* Update the destination queue error code */
+ pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
+
+ return HAL_ERROR;
+ }
+
+ /* Check nodes types compatibility */
+ if (DMA_List_CheckNodesTypes(pSrcQList->Head, pDestQList->Head, NULL) != 0U)
+ {
+ /* Update the source queue error code */
+ pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+ /* Update the destination queue error code */
+ pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+ return HAL_ERROR;
+ }
+
+ /* Update the source queue state */
+ pSrcQList->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+ /* Update the source queue error code */
+ pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Update the destination queue state */
+ pDestQList->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+ /* Update the destination queue error code */
+ pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Get CLLR register mask and offset */
+ DMA_List_GetCLLRNodeInfo(pSrcQList->Head, &cllr_mask, &cllr_offset);
+
+ /* Empty destination queue */
+ if (pDestQList->Head == NULL)
+ {
+ pDestQList->Head = pSrcQList->Head;
+ pDestQList->NodeNumber = pSrcQList->NodeNumber;
+ }
+ /* Not empty destination queue */
+ else
+ {
+ /* Find node and get its position in selected queue */
+ dest_q_node_info.cllr_offset = cllr_offset;
+ (void)DMA_List_FindNode(pDestQList, NULL, &dest_q_node_info);
+
+ /* Update source queue last node CLLR to link it with destination first node */
+ ((DMA_NodeTypeDef *)(dest_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] =
+ ((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask;
+ pDestQList->NodeNumber += pSrcQList->NodeNumber;
+
+ /* Check if first circular node queue is not empty */
+ if (pDestQList->FirstCircularNode != NULL)
+ {
+ /* Find node and get its position in selected queue */
+ src_q_node_info.cllr_offset = cllr_offset;
+ (void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info);
+
+ /* Find first circular node */
+ (void)DMA_List_FindNode(pDestQList, pDestQList->FirstCircularNode, &dest_q_node_info);
+
+ /* Link last source queue node to first destination queue */
+ ((DMA_NodeTypeDef *)src_q_node_info.currentnode_addr)->LinkRegisters[cllr_offset] =
+ (dest_q_node_info.currentnode_addr & DMA_CLLR_LA) | cllr_mask;
+ }
+ }
+
+ /* Clean the source queue variable as it is obsolete */
+ DMA_List_CleanQueue(pSrcQList);
+
+ /* Update the destination queue error code */
+ pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Update the destination queue state */
+ pDestQList->State = HAL_DMA_QUEUE_STATE_READY;
+
+ /* Prevent MISRA-C2012-Rule-2.2_b */
+ UNUSED(src_q_node_info);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set circular mode configuration for linked-list queue.
+ * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
+ * @param pFirstCircularNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list first circular node
+ * registers configurations.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMAEx_List_SetCircularModeConfig(DMA_QListTypeDef *const pQList,
+ DMA_NodeTypeDef *const pFirstCircularNode)
+{
+ uint32_t cllr_mask;
+ uint32_t cllr_offset;
+ DMA_NodeInQInfoTypeDef node_info;
+
+ /* Check the queue and the first circular node parameters */
+ if ((pQList == NULL) || (pFirstCircularNode == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the queue */
+ if (pQList->Head == NULL)
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
+
+ return HAL_ERROR;
+ }
+
+ /* Check queue circular mode */
+ if (pQList->FirstCircularNode != NULL)
+ {
+ if (pQList->FirstCircularNode == pFirstCircularNode)
+ {
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Check queue type */
+ if (pQList->Type == QUEUE_TYPE_DYNAMIC)
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+ return HAL_ERROR;
+ }
+
+ /* Update the queue state */
+ pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Get CLLR register mask and offset */
+ DMA_List_GetCLLRNodeInfo(pFirstCircularNode, &cllr_mask, &cllr_offset);
+
+ /* Find the first circular node and get its position in selected queue */
+ node_info.cllr_offset = cllr_offset;
+ if (DMA_List_FindNode(pQList, pFirstCircularNode, &node_info) == 0U)
+ {
+ /* Find the last queue node and get its position in selected queue */
+ (void)DMA_List_FindNode(pQList, NULL, &node_info);
+
+ /* Set circular mode */
+ ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] =
+ ((uint32_t)pFirstCircularNode & DMA_CLLR_LA) | cllr_mask;
+
+ /* Update first circular node in queue */
+ pQList->FirstCircularNode = pFirstCircularNode;
+ }
+ else
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND;
+
+ return HAL_ERROR;
+ }
+
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Update the queue state */
+ pQList->State = HAL_DMA_QUEUE_STATE_READY;
+
+ /* Prevent MISRA-C2012-Rule-2.2_b */
+ UNUSED(node_info);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set circular mode for linked-list queue.
+ * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMAEx_List_SetCircularMode(DMA_QListTypeDef *const pQList)
+{
+ uint32_t cllr_mask;
+ uint32_t cllr_offset;
+ DMA_NodeInQInfoTypeDef node_info;
+
+ /* Check the queue parameter */
+ if (pQList == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the queue */
+ if (pQList->Head == NULL)
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
+
+ return HAL_ERROR;
+ }
+
+ /* Check queue circular mode */
+ if (pQList->FirstCircularNode != NULL)
+ {
+ if (pQList->FirstCircularNode == pQList->Head)
+ {
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Check queue type */
+ if (pQList->Type == QUEUE_TYPE_DYNAMIC)
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+ return HAL_ERROR;
+ }
+
+ /* Update the queue state */
+ pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Get CLLR register mask and offset */
+ DMA_List_GetCLLRNodeInfo(pQList->Head, &cllr_mask, &cllr_offset);
+
+ /* Find the last queue node and get its position in selected queue */
+ node_info.cllr_offset = cllr_offset;
+ (void)DMA_List_FindNode(pQList, NULL, &node_info);
+
+ /* Set circular mode */
+ ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] =
+ ((uint32_t)pQList->Head & DMA_CLLR_LA) | cllr_mask;
+
+ /* Update linked-list circular state */
+ pQList->FirstCircularNode = pQList->Head;
+
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Update the queue state */
+ pQList->State = HAL_DMA_QUEUE_STATE_READY;
+
+ /* Prevent MISRA-C2012-Rule-2.2_b */
+ UNUSED(node_info);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Clear circular mode for linked-list queue.
+ * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMAEx_List_ClearCircularMode(DMA_QListTypeDef *const pQList)
+{
+ uint32_t cllr_offset;
+ DMA_NodeInQInfoTypeDef node_info;
+
+ /* Check the queue parameter */
+ if (pQList == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the queue */
+ if (pQList->Head == NULL)
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
+
+ return HAL_ERROR;
+ }
+
+ /* Check queue circular mode */
+ if (pQList->FirstCircularNode == NULL)
+ {
+ return HAL_OK;
+ }
+
+ /* Check queue type */
+ if (pQList->Type == QUEUE_TYPE_DYNAMIC)
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+ return HAL_ERROR;
+ }
+
+ /* Update the queue state */
+ pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Get CLLR register offset */
+ DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset);
+
+ /* Find the last queue node and get its position in selected queue */
+ node_info.cllr_offset = cllr_offset;
+ (void)DMA_List_FindNode(pQList, NULL, &node_info);
+
+ /* Clear circular mode */
+ ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U;
+
+ /* Update linked-list circular configuration */
+ pQList->FirstCircularNode = NULL;
+
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Update the queue state */
+ pQList->State = HAL_DMA_QUEUE_STATE_READY;
+
+ /* Prevent MISRA-C2012-Rule-2.2_b */
+ UNUSED(node_info);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Convert a linked-list queue to dynamic (Optimized DMA queue execution).
+ * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToDynamic(DMA_QListTypeDef *const pQList)
+{
+ uint32_t cllr_offset;
+ uint32_t currentnode_addr;
+ DMA_NodeTypeDef context_node;
+ DMA_NodeInQInfoTypeDef node_info;
+
+ /* Check the queue parameter */
+ if (pQList == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the queue */
+ if (pQList->Head == NULL)
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
+
+ return HAL_ERROR;
+ }
+
+ /* Check if queue is dynamic */
+ if (pQList->Type == QUEUE_TYPE_DYNAMIC)
+ {
+ return HAL_OK;
+ }
+
+ /* Update the queue state */
+ pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Get CLLR register mask and offset */
+ DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset);
+
+ /* Check queue circularity */
+ if (pQList->FirstCircularNode != 0U)
+ {
+ /* Find the last queue node and get its position in selected queue */
+ node_info.cllr_offset = cllr_offset;
+ (void)DMA_List_FindNode(pQList, NULL, &node_info);
+ }
+
+ /* Set current node address */
+ currentnode_addr = (uint32_t)pQList->Head;
+
+ /* Store register value */
+ DMA_List_FillNode(pQList->Head, &context_node);
+
+ /* Convert all nodes to dyncamic (Bypass head node) */
+ for (uint32_t node_count = 1U; node_count < pQList->NodeNumber; node_count++)
+ {
+ /* Update node address */
+ MODIFY_REG(currentnode_addr, DMA_CLLR_LA, (context_node.LinkRegisters[cllr_offset] & DMA_CLLR_LA));
+
+ /* Bypass the first circular node when first circular node isn't the last queue node */
+ if (((uint32_t)pQList->FirstCircularNode != 0U) &&
+ ((uint32_t)pQList->FirstCircularNode != node_info.currentnode_addr) &&
+ ((uint32_t)pQList->FirstCircularNode == currentnode_addr))
+ {
+ /* Copy first circular node to context node */
+ DMA_List_FillNode(pQList->FirstCircularNode, &context_node);
+ }
+ else
+ {
+ /* Convert current node to dynamic */
+ DMA_List_ConvertNodeToDynamic((uint32_t)&context_node, currentnode_addr, (cllr_offset + 1U));
+ }
+ }
+
+ /* Check if first circular node is the last node queue */
+ if (((uint32_t)pQList->FirstCircularNode != 0U) &&
+ ((uint32_t)pQList->FirstCircularNode != node_info.currentnode_addr))
+ {
+ /* Update all queue nodes CLLR */
+ DMA_List_UpdateDynamicQueueNodesCLLR(pQList, LASTNODE_ISNOT_CIRCULAR);
+ }
+ else
+ {
+ /* Update all queue nodes CLLR */
+ DMA_List_UpdateDynamicQueueNodesCLLR(pQList, LASTNODE_IS_CIRCULAR);
+ }
+
+ /* Set queue type */
+ pQList->Type = QUEUE_TYPE_DYNAMIC;
+
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Update the queue state */
+ pQList->State = HAL_DMA_QUEUE_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Convert a linked-list queue to static (Not optimized DMA queue execution).
+ * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToStatic(DMA_QListTypeDef *const pQList)
+{
+ uint32_t cllr_offset;
+ uint32_t currentnode_addr;
+ DMA_NodeTypeDef context_node;
+
+ /* Check the queue parameter */
+ if (pQList == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the queue */
+ if (pQList->Head == NULL)
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
+
+ return HAL_ERROR;
+ }
+
+ /* Check if queue is static */
+ if (pQList->Type == QUEUE_TYPE_STATIC)
+ {
+ return HAL_OK;
+ }
+
+ /* Set current node address */
+ currentnode_addr = (uint32_t)pQList->Head;
+
+ /* Update the queue state */
+ pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Get CLLR register mask and offset */
+ DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset);
+
+ /* Set all CLLR queue nodes to their default positions */
+ DMA_List_UpdateStaticQueueNodesCLLR(pQList, UPDATE_CLLR_POSITION);
+
+ /* Convert all nodes to static (Bypass head node) */
+ for (uint32_t node_count = 1U; node_count < pQList->NodeNumber; node_count++)
+ {
+ /* Update context node register values */
+ DMA_List_FillNode((DMA_NodeTypeDef *)currentnode_addr, &context_node);
+
+ /* Update node address */
+ MODIFY_REG(currentnode_addr, DMA_CLLR_LA, (context_node.LinkRegisters[cllr_offset] & DMA_CLLR_LA));
+
+ /* Convert current node to static */
+ DMA_List_ConvertNodeToStatic((uint32_t)&context_node, currentnode_addr, (cllr_offset + 1U));
+ }
+
+ /* Set all CLLR queue nodes to their default values */
+ DMA_List_UpdateStaticQueueNodesCLLR(pQList, UPDATE_CLLR_VALUE);
+
+ /* Set queue type */
+ pQList->Type = QUEUE_TYPE_STATIC;
+
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Update the queue state */
+ pQList->State = HAL_DMA_QUEUE_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Link linked-list queue to a DMA channel.
+ * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+ * specified DMA Channel.
+ * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMAEx_List_LinkQ(DMA_HandleTypeDef *const hdma,
+ DMA_QListTypeDef *const pQList)
+{
+ HAL_DMA_StateTypeDef state;
+
+ /* Check the DMA channel handle and the queue parameters */
+ if ((hdma == NULL) || (pQList == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Get DMA state */
+ state = hdma->State;
+
+ /* Check DMA channel state */
+ if ((hdma->State == HAL_DMA_STATE_BUSY) || (state == HAL_DMA_STATE_SUSPEND))
+ {
+ /* Update the DMA channel error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_ERROR;
+ }
+
+ /* Check queue state */
+ if (pQList->State == HAL_DMA_QUEUE_STATE_BUSY)
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_BUSY;
+
+ return HAL_ERROR;
+ }
+
+ /* Check linearity compatibility */
+ if ((IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) == 0U) &&
+ ((pQList->Head->NodeInfo & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR))
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_UNSUPPORTED;
+
+ return HAL_ERROR;
+ }
+
+ /* Check circularity compatibility */
+ if (hdma->Mode == DMA_LINKEDLIST_CIRCULAR)
+ {
+ /* Check first circular node */
+ if (pQList->FirstCircularNode == NULL)
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Check first circular node */
+ if (pQList->FirstCircularNode != NULL)
+ {
+ /* Update the queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Register queue to DMA handle */
+ hdma->LinkedListQueue = pQList;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Unlink linked-list queue from a DMA channel.
+ * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+ * specified DMA Channel.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMAEx_List_UnLinkQ(DMA_HandleTypeDef *const hdma)
+{
+ HAL_DMA_StateTypeDef state;
+
+ /* Check the DMA channel parameter */
+ if (hdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Get DMA state */
+ state = hdma->State;
+
+ /* Check DMA channel state */
+ if ((hdma->State == HAL_DMA_STATE_BUSY) || (state == HAL_DMA_STATE_SUSPEND))
+ {
+ /* Update the DMA channel error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_ERROR;
+ }
+
+ /* Clear queue information from DMA channel handle */
+ hdma->LinkedListQueue = NULL;
+
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/** @addtogroup DMAEx_Exported_Functions_Group4
+ *
+@verbatim
+ ======================================================================================================================
+ ############### Data handling, repeated block and trigger configuration functions ###############
+ ======================================================================================================================
+ [..]
+ This section provides functions allowing to :
+ (+) Configure DMA channel data handling.
+ (+) Configure DMA channel repeated block.
+ (+) Configure DMA channel trigger.
+
+ [..]
+ (+) The HAL_DMAEx_ConfigDataHandling() function allows to configure DMA channel data handling.
+ (++) GPDMA data handling : byte-based reordering, packing/unpacking, padding/truncation, sign extension
+ and left/right alignment.
+ (++) LPDMA data handling : byte-based padding/truncation, sign extension and left/right alignment.
+
+ (+) The HAL_DMAEx_ConfigTrigger() function allows to configure DMA channel HW triggers.
+
+ (+) The HAL_DMAEx_ConfigRepeatBlock() function allows to configure DMA channel repeated block.
+ (++) This feature is available only for channel that supports 2 dimensions addressing capability.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the DMA channel data handling according to the specified parameters in the
+ * DMA_DataHandlingConfTypeDef.
+ * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information
+ * for the specified DMA Channel.
+ * @param pConfigDataHandling : Pointer to a DMA_DataHandlingConfTypeDef structure that contains the data handling
+ * configuration.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMAEx_ConfigDataHandling(DMA_HandleTypeDef *const hdma,
+ DMA_DataHandlingConfTypeDef const *const pConfigDataHandling)
+{
+ /* Check the DMA peripheral handle and data handling parameters */
+ if ((hdma == NULL) || (pConfigDataHandling == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DMA_DATA_ALIGNMENT(pConfigDataHandling->DataAlignment));
+ assert_param(IS_DMA_DATA_EXCHANGE(pConfigDataHandling->DataExchange));
+
+ /* Check DMA channel state */
+ if (hdma->State == HAL_DMA_STATE_READY)
+ {
+ MODIFY_REG(hdma->Instance->CTR1, (DMA_CTR1_DHX | DMA_CTR1_DBX | DMA_CTR1_SBX | DMA_CTR1_PAM),
+ (pConfigDataHandling->DataAlignment | pConfigDataHandling->DataExchange));
+ }
+ else
+ {
+ /* Update the DMA channel error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the DMA channel trigger according to the specified parameters in the DMA_TriggerConfTypeDef.
+ * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for
+ * the specified DMA Channel.
+ * @param pConfigTrigger : Pointer to a DMA_TriggerConfTypeDef structure that contains the trigger configuration.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMAEx_ConfigTrigger(DMA_HandleTypeDef *const hdma,
+ DMA_TriggerConfTypeDef const *const pConfigTrigger)
+{
+ /* Check the DMA peripheral handle and trigger parameters */
+ if ((hdma == NULL) || (pConfigTrigger == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+ assert_param(IS_DMA_TRIGGER_POLARITY(pConfigTrigger->TriggerPolarity));
+ assert_param(IS_DMA_TRIGGER_MODE(pConfigTrigger->TriggerMode));
+ assert_param(IS_DMA_TRIGGER_SELECTION(pConfigTrigger->TriggerSelection));
+
+ /* Check DMA channel state */
+ if (hdma->State == HAL_DMA_STATE_READY)
+ {
+ MODIFY_REG(hdma->Instance->CTR2, (DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGSEL | DMA_CTR2_TRIGM),
+ (pConfigTrigger->TriggerPolarity | pConfigTrigger->TriggerMode |
+ (pConfigTrigger->TriggerSelection << DMA_CTR2_TRIGSEL_Pos)));
+ }
+ else
+ {
+ /* Update the DMA channel error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the DMA channel repeated block according to the specified parameters in the
+ * DMA_RepeatBlockConfTypeDef.
+ * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information
+ * for the specified DMA Channel.
+ * @param pConfigRepeatBlock : Pointer to a DMA_RepeatBlockConfTypeDef structure that contains the repeated block
+ * configuration.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMAEx_ConfigRepeatBlock(DMA_HandleTypeDef *const hdma,
+ DMA_RepeatBlockConfTypeDef const *const pConfigRepeatBlock)
+{
+ uint32_t tmpreg1;
+ uint32_t tmpreg2;
+
+ /* Check the DMA peripheral handle and repeated block parameters */
+ if ((hdma == NULL) || (pConfigRepeatBlock == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check parameters */
+ assert_param(IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance));
+ assert_param(IS_DMA_REPEAT_COUNT(pConfigRepeatBlock->RepeatCount));
+ assert_param(IS_DMA_BURST_ADDR_OFFSET(pConfigRepeatBlock->SrcAddrOffset));
+ assert_param(IS_DMA_BURST_ADDR_OFFSET(pConfigRepeatBlock->DestAddrOffset));
+ assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pConfigRepeatBlock->BlkSrcAddrOffset));
+ assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pConfigRepeatBlock->BlkDestAddrOffset));
+
+ /* Check DMA channel state */
+ if (hdma->State == HAL_DMA_STATE_READY)
+ {
+ /* Store repeat block count */
+ tmpreg1 = ((pConfigRepeatBlock->RepeatCount - 1U) << DMA_CBR1_BRC_Pos);
+
+ /* Check the sign of single/burst destination address offset value */
+ if (pConfigRepeatBlock->DestAddrOffset < 0)
+ {
+ /* Store single/burst destination address offset configuration (signed case) */
+ tmpreg1 |= DMA_CBR1_DDEC;
+ tmpreg2 = (uint32_t)(- pConfigRepeatBlock->DestAddrOffset);
+ tmpreg2 = tmpreg2 << DMA_CTR3_DAO_Pos;
+ }
+ else
+ {
+ /* Store single/burst destination address offset configuration (unsigned case) */
+ tmpreg2 = ((uint32_t)pConfigRepeatBlock->DestAddrOffset << DMA_CTR3_DAO_Pos);
+ }
+
+ /* Check the sign of single/burst source address offset value */
+ if (pConfigRepeatBlock->SrcAddrOffset < 0)
+ {
+ /* Store single/burst source address offset configuration (signed case) */
+ tmpreg1 |= DMA_CBR1_SDEC;
+ tmpreg2 |= (uint32_t)(- pConfigRepeatBlock->SrcAddrOffset);
+ }
+ else
+ {
+ /* Store single/burst source address offset configuration (unsigned case) */
+ tmpreg2 |= (uint32_t)pConfigRepeatBlock->SrcAddrOffset;
+ }
+
+ /* Write DMA Channel Transfer Register 3 (CTR3) */
+ WRITE_REG(hdma->Instance->CTR3, tmpreg2);
+
+ /* Check the sign of block destination address offset value */
+ if (pConfigRepeatBlock->BlkDestAddrOffset < 0)
+ {
+ /* Store block destination address offset configuration (signed case) */
+ tmpreg1 |= DMA_CBR1_BRDDEC;
+ tmpreg2 = (uint32_t)(- pConfigRepeatBlock->BlkDestAddrOffset);
+ tmpreg2 = tmpreg2 << DMA_CBR2_BRDAO_Pos;
+ }
+ else
+ {
+ /* Store block destination address offset configuration (unsigned case) */
+ tmpreg2 = ((uint32_t)pConfigRepeatBlock->BlkDestAddrOffset << DMA_CBR2_BRDAO_Pos);
+ }
+
+ /* Check the sign of block source address offset value */
+ if (pConfigRepeatBlock->BlkSrcAddrOffset < 0)
+ {
+ /* Store block source address offset configuration (signed case) */
+ tmpreg1 |= DMA_CBR1_BRSDEC;
+ tmpreg2 |= (uint32_t)(- pConfigRepeatBlock->BlkSrcAddrOffset);
+ }
+ else
+ {
+ /* Store block source address offset configuration (unsigned case) */
+ tmpreg2 |= (uint32_t)pConfigRepeatBlock->BlkSrcAddrOffset;
+ }
+
+ /* Write DMA Channel block register 2 (CBR2) */
+ WRITE_REG(hdma->Instance->CBR2, tmpreg2);
+
+ /* Write DMA Channel block register 1 (CBR1) */
+ WRITE_REG(hdma->Instance->CBR1, tmpreg1);
+ }
+ else
+ {
+ /* Update the DMA channel error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/** @addtogroup DMAEx_Exported_Functions_Group5
+ *
+@verbatim
+ ======================================================================================================================
+ ############### Suspend and resume operation functions ###############
+ ======================================================================================================================
+ [..]
+ This section provides functions allowing to :
+ (+) Suspend any ongoing DMA channel transfer.
+ (+) Resume any suspended DMA channel transfer.
+
+ [..]
+ (+) The HAL_DMAEx_Suspend() function allows to suspend any ongoing DMA channel transfer in polling mode (Blocking
+ mode).
+
+ (+) The HAL_DMAEx_Suspend_IT() function allows to suspend any ongoing DMA channel transfer in interrupt mode
+ (Non-blocking mode).
+
+ (+) The HAL_DMAEx_Resume() function allows to resume any suspended DMA channel transfer.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Suspend any ongoing DMA channel transfer in polling mode (Blocking mode).
+ * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+ * specified DMA channel.
+ * @note After suspending a DMA channel, a check for wait until the DMA channel is effectively suspended is added. If
+ * a channel is suspended while a data transfer is ongoing, the current data will be transferred and the
+ * channel will be effectively suspended only after the transfer of this single/burst data is finished.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMAEx_Suspend(DMA_HandleTypeDef *const hdma)
+{
+ /* Get tick number */
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Check the DMA peripheral handle */
+ if (hdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check DMA channel state */
+ if (hdma->State != HAL_DMA_STATE_BUSY)
+ {
+ /* Update the DMA channel error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Suspend the channel */
+ hdma->Instance->CCR |= DMA_CCR_SUSP;
+
+ /* Check if the DMA channel is suspended */
+ while ((hdma->Instance->CSR & DMA_CSR_SUSPF) != 0U)
+ {
+ /* Check for the timeout */
+ if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
+ {
+ /* Update the DMA channel error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
+
+ /* Update the DMA channel state */
+ hdma->State = HAL_DMA_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_ERROR;
+ }
+
+ /* Update the DMA channel state */
+ hdma->State = HAL_DMA_STATE_SUSPEND;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Suspend any ongoing DMA channel transfer in polling mode (Non-blocking mode).
+ * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+ * specified DMA Channel.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMAEx_Suspend_IT(DMA_HandleTypeDef *const hdma)
+{
+ /* Check the DMA peripheral handle parameter */
+ if (hdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check DMA channel state */
+ if (hdma->State != HAL_DMA_STATE_BUSY)
+ {
+ /* Update the DMA channel error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Suspend the DMA channel and activate suspend interrupt */
+ hdma->Instance->CCR |= (DMA_CCR_SUSP | DMA_CCR_SUSPIE);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resume any suspended DMA channel transfer.
+ * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+ * specified DMA Channel.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DMAEx_Resume(DMA_HandleTypeDef *const hdma)
+{
+ /* Check the DMA peripheral handle parameter */
+ if (hdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check DMA channel state */
+ if (hdma->State != HAL_DMA_STATE_SUSPEND)
+ {
+ /* Update the DMA channel error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Resume the DMA channel */
+ hdma->Instance->CCR &= (~DMA_CCR_SUSP);
+
+ /* Clear the suspend flag */
+ hdma->Instance->CFCR |= DMA_CFCR_SUSPF;
+
+ /* Update the DMA channel state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+ }
+
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/** @addtogroup DMAEx_Exported_Functions_Group6
+ *
+@verbatim
+ ======================================================================================================================
+ ############### Fifo status function ###############
+ ======================================================================================================================
+ [..]
+ This section provides function allowing to get DMA channel FIFO level.
+
+ [..]
+ (+) The HAL_DMAEx_GetFifoLevel() function allows to return the number of available write beats in the FIFO, in
+ units of the programmed destination data.
+ (++) This API is available only for DMA channels that supports FIFO.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Get and returns the DMA channel FIFO level.
+ * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+ * specified DMA Channel.
+ * @retval Returns the number of available beats in FIFO.
+ */
+uint32_t HAL_DMAEx_GetFifoLevel(DMA_HandleTypeDef const *const hdma)
+{
+ return ((hdma->Instance->CSR & DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos);
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions -------------------------------------------------------------------------------------------------*/
+/** @defgroup DMAEx_Private_Functions DMAEx Private Functions
+ * @brief DMAEx Private Functions
+ * @{
+ */
+
+/**
+ * @brief Initialize the DMA handle according to the specified parameters in the DMA_InitTypeDef.
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+ * specified DMA Channel.
+ * @retval None.
+ */
+static void DMA_List_Init(DMA_HandleTypeDef const *const hdma)
+{
+ uint32_t tmpreg;
+
+ /* Prepare DMA Channel Control Register (CCR) value */
+ tmpreg = hdma->InitLinkedList.Priority | hdma->InitLinkedList.LinkStepMode | hdma->InitLinkedList.LinkAllocatedPort;
+
+ /* Write DMA Channel Control Register (CCR) */
+ MODIFY_REG(hdma->Instance->CCR, DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM, tmpreg);
+
+ /* Write DMA Channel Control Register (CTR1) */
+ WRITE_REG(hdma->Instance->CTR1, 0U);
+
+ /* Write DMA Channel Control Register (CTR2) */
+ WRITE_REG(hdma->Instance->CTR2, hdma->InitLinkedList.TransferEventMode);
+
+ /* Write DMA Channel Control Register (CBR1) */
+ WRITE_REG(hdma->Instance->CBR1, 0U);
+
+ /* Write DMA Channel Control Register (CSAR) */
+ WRITE_REG(hdma->Instance->CSAR, 0U);
+
+ /* Write DMA Channel Control Register (CDAR) */
+ WRITE_REG(hdma->Instance->CDAR, 0U);
+
+ /* If 2D Addressing is supported by current channel */
+ if (IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) != 0U)
+ {
+ /* Write DMA Channel Control Register (CTR3) */
+ WRITE_REG(hdma->Instance->CTR3, 0U);
+
+ /* Write DMA Channel Control Register (CBR2) */
+ WRITE_REG(hdma->Instance->CBR2, 0U);
+ }
+
+ /* Write DMA Channel linked-list address register (CLLR) */
+ WRITE_REG(hdma->Instance->CLLR, 0U);
+}
+
+/**
+ * @brief Build a DMA channel node according to the specified parameters in the DMA_NodeConfTypeDef.
+ * @param pNodeConfig : Pointer to a DMA_NodeConfTypeDef structure that contains the configuration information for the
+ * specified DMA linked-list Node.
+ * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers
+ * configurations.
+ * @retval None.
+ */
+static void DMA_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig,
+ DMA_NodeTypeDef *const pNode)
+{
+ int32_t blockoffset;
+
+ /* Update CTR1 register value ***************************************************************************************/
+ /* Prepare DMA channel transfer register (CTR1) value */
+ pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] = pNodeConfig->Init.DestInc |
+ pNodeConfig->Init.DestDataWidth |
+ pNodeConfig->DataHandlingConfig.DataAlignment |
+ pNodeConfig->Init.SrcInc |
+ pNodeConfig->Init.SrcDataWidth;
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ /* set source channel security attribute */
+ if (pNodeConfig->SrcSecure == DMA_CHANNEL_SRC_SEC)
+ {
+ pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= DMA_CTR1_SSEC;
+ }
+
+ /* set destination channel security attribute */
+ if (pNodeConfig->DestSecure == DMA_CHANNEL_DEST_SEC)
+ {
+ pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= DMA_CTR1_DSEC;
+ }
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+ /* Add parameters related to DMA configuration */
+ if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_GPDMA) == DMA_CHANNEL_TYPE_GPDMA)
+ {
+ /* Prepare DMA channel transfer register (CTR1) value */
+ pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |=
+ (pNodeConfig->Init.TransferAllocatedPort | pNodeConfig->DataHandlingConfig.DataExchange |
+ (((pNodeConfig->Init.DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1) |
+ (((pNodeConfig->Init.SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1));
+ }
+ /*********************************************************************************** CTR1 register value is updated */
+
+
+ /* Update CTR2 register value ***************************************************************************************/
+ /* Prepare DMA channel transfer register 2 (CTR2) value */
+ pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] = pNodeConfig->Init.TransferEventMode |
+ (pNodeConfig->Init.Request & (DMA_CTR2_REQSEL | DMA_CTR2_SWREQ));
+
+ /* Check for memory to peripheral transfer */
+ if ((pNodeConfig->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+ {
+ /* Check for GPDMA */
+ if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_GPDMA) == DMA_CHANNEL_TYPE_GPDMA)
+ {
+ pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] |= DMA_CTR2_DREQ;
+ }
+ }
+ /* Memory to memory transfer */
+ else if ((pNodeConfig->Init.Direction) == DMA_MEMORY_TO_MEMORY)
+ {
+ pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] |= DMA_CTR2_SWREQ;
+ }
+ else
+ {
+ /* Prevent MISRA-C2012-Rule-15.7 */
+ }
+
+ /* Check if trigger feature is active */
+ if (pNodeConfig->TriggerConfig.TriggerPolarity != DMA_TRIG_POLARITY_MASKED)
+ {
+ /* Prepare DMA channel transfer register 2 (CTR2) value */
+ pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] |=
+ pNodeConfig->TriggerConfig.TriggerMode | pNodeConfig->TriggerConfig.TriggerPolarity |
+ ((pNodeConfig->TriggerConfig.TriggerSelection << DMA_CTR2_TRIGSEL_Pos) & DMA_CTR2_TRIGSEL);
+ }
+ /*********************************************************************************** CTR2 register value is updated */
+
+
+ /* Update CBR1 register value ***************************************************************************************/
+ /* Prepare DMA channel block register 1 (CBR1) value */
+ pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = (pNodeConfig->DataSize & DMA_CBR1_BNDT);
+
+ /* If 2D addressing is supported by the selected DMA channel */
+ if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR)
+ {
+ /* Set the new CBR1 Register value */
+ pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] |=
+ (((pNodeConfig->RepeatBlockConfig.RepeatCount - 1U) << DMA_CBR1_BRC_Pos) & DMA_CBR1_BRC);
+
+ /* If the source address offset is negative, set SDEC bit */
+ if (pNodeConfig->RepeatBlockConfig.SrcAddrOffset < 0)
+ {
+ pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] |= DMA_CBR1_SDEC;
+ }
+ else
+ {
+ pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] &= (~DMA_CBR1_SDEC);
+ }
+
+ /* If the destination address offset is negative, set DDEC bit */
+ if (pNodeConfig->RepeatBlockConfig.DestAddrOffset < 0)
+ {
+ pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] |= DMA_CBR1_DDEC;
+ }
+ else
+ {
+ pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] &= (~DMA_CBR1_DDEC);
+ }
+
+ /* If the repeated block source address offset is negative, set BRSEC bit */
+ if (pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset < 0)
+ {
+ pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] |= DMA_CBR1_BRSDEC;
+ }
+ else
+ {
+ pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] &= (~DMA_CBR1_BRSDEC);
+ }
+
+ /* if the repeated block destination address offset is negative, set BRDEC bit */
+ if (pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset < 0)
+ {
+ pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] |= DMA_CBR1_BRDDEC;
+ }
+ else
+ {
+ pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] &= (~DMA_CBR1_BRDDEC);
+ }
+ }
+ /*********************************************************************************** CBR1 register value is updated */
+
+
+ /* Update CSAR register value ***************************************************************************************/
+ pNode->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = pNodeConfig->SrcAddress;
+ /*********************************************************************************** CSAR register value is updated */
+
+
+ /* Update CDAR register value ***************************************************************************************/
+ pNode->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = pNodeConfig->DstAddress;
+ /*********************************************************************************** CDAR register value is updated */
+
+
+ /* Check if the selected channel is 2D addressing */
+ if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR)
+ {
+ /* Update CTR3 register value *************************************************************************************/
+ /* Write new CTR3 Register value : source address offset */
+ if (pNodeConfig->RepeatBlockConfig.SrcAddrOffset < 0)
+ {
+ blockoffset = (- pNodeConfig->RepeatBlockConfig.SrcAddrOffset);
+ pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] = ((uint32_t)blockoffset & DMA_CTR3_SAO);
+ }
+ else
+ {
+ pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] =
+ ((uint32_t)pNodeConfig->RepeatBlockConfig.SrcAddrOffset & DMA_CTR3_SAO);
+ }
+
+ /* Write new CTR3 Register value : destination address offset */
+ if (pNodeConfig->RepeatBlockConfig.DestAddrOffset < 0)
+ {
+ blockoffset = (- pNodeConfig->RepeatBlockConfig.DestAddrOffset);
+ pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] |= (((uint32_t)blockoffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO);
+ }
+ else
+ {
+ pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] |=
+ (((uint32_t)pNodeConfig->RepeatBlockConfig.DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO);
+ }
+ /********************************************************************************* CTR3 register value is updated */
+
+
+ /* Update CBR2 register value *************************************************************************************/
+ /* Write new CBR2 Register value : repeated block source address offset */
+ if (pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset < 0)
+ {
+ blockoffset = (- pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset);
+ pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] = ((uint32_t)blockoffset & DMA_CBR2_BRSAO);
+ }
+ else
+ {
+ pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] =
+ ((uint32_t)pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset & DMA_CBR2_BRSAO);
+ }
+
+ /* Write new CBR2 Register value : repeated block destination address offset */
+ if (pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset < 0)
+ {
+ blockoffset = (- pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset);
+ pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] |=
+ (((uint32_t)blockoffset & DMA_CBR2_BRSAO) << DMA_CBR2_BRDAO_Pos);
+ }
+ else
+ {
+ pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] |=
+ (((uint32_t)pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO);
+ }
+ /********************************************************************************* CBR2 register value is updated */
+ }
+
+
+ /* Update node information value ************************************************************************************/
+ /* Set node information */
+ pNode->NodeInfo = pNodeConfig->NodeType;
+ if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR)
+ {
+ pNode->NodeInfo |= (NODE_CLLR_2D_DEFAULT_OFFSET << NODE_CLLR_IDX_POS);
+ }
+ else
+ {
+ pNode->NodeInfo |= (NODE_CLLR_LINEAR_DEFAULT_OFFSET << NODE_CLLR_IDX_POS);
+ }
+ /******************************************************************************** Node information value is updated */
+}
+
+/**
+ * @brief Get a DMA channel node configuration.
+ * @param pNodeConfig : Pointer to a DMA_NodeConfTypeDef structure that contains the configuration information for the
+ * specified DMA linked-list Node.
+ * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers
+ * configurations.
+ * @retval None.
+ */
+static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig,
+ DMA_NodeTypeDef const *const pNode)
+{
+ uint16_t offset;
+
+ /* Get node information *********************************************************************************************/
+ pNodeConfig->NodeType = (pNode->NodeInfo & NODE_TYPE_MASK);
+ /*************************************************************************************** Node type value is updated */
+
+
+ /* Get CTR1 fields values *******************************************************************************************/
+ pNodeConfig->Init.SrcInc = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_SINC;
+ pNodeConfig->Init.DestInc = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DINC;
+ pNodeConfig->Init.SrcDataWidth = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_SDW_LOG2;
+ pNodeConfig->Init.DestDataWidth = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2;
+ pNodeConfig->Init.SrcBurstLength = ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] &
+ DMA_CTR1_SBL_1) >> DMA_CTR1_SBL_1_Pos) + 1U;
+ pNodeConfig->Init.DestBurstLength = ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] &
+ DMA_CTR1_DBL_1) >> DMA_CTR1_DBL_1_Pos) + 1U;
+ pNodeConfig->Init.TransferAllocatedPort = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] &
+ (DMA_CTR1_SAP | DMA_CTR1_DAP);
+ pNodeConfig->DataHandlingConfig.DataExchange = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] &
+ (DMA_CTR1_SBX | DMA_CTR1_DBX | DMA_CTR1_DHX);
+ pNodeConfig->DataHandlingConfig.DataAlignment = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_PAM;
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ if ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_SSEC) != 0U)
+ {
+ pNodeConfig->SrcSecure = DMA_CHANNEL_SRC_SEC;
+ }
+ else
+ {
+ pNodeConfig->SrcSecure = DMA_CHANNEL_SRC_NSEC;
+ }
+
+ if ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DSEC) != 0U)
+ {
+ pNodeConfig->DestSecure = DMA_CHANNEL_DEST_SEC;
+ }
+ else
+ {
+ pNodeConfig->DestSecure = DMA_CHANNEL_DEST_NSEC;
+ }
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+ /*********************************************************************************** CTR1 fields values are updated */
+
+
+ /* Get CTR2 fields values *******************************************************************************************/
+ if ((pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_SWREQ) != 0U)
+ {
+ pNodeConfig->Init.Request = DMA_REQUEST_SW;
+ pNodeConfig->Init.Direction = DMA_MEMORY_TO_MEMORY;
+ }
+ else
+ {
+ pNodeConfig->Init.Request = pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_REQSEL;
+
+ if ((pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_DREQ) != 0U)
+ {
+ pNodeConfig->Init.Direction = DMA_MEMORY_TO_PERIPH;
+ }
+ else
+ {
+ pNodeConfig->Init.Direction = DMA_PERIPH_TO_MEMORY;
+ }
+ }
+
+ pNodeConfig->Init.BlkHWRequest = (pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_BREQ);
+ pNodeConfig->TriggerConfig.TriggerMode = pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_TRIGM;
+ pNodeConfig->TriggerConfig.TriggerPolarity = pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_TRIGPOL;
+ pNodeConfig->TriggerConfig.TriggerSelection = (pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] &
+ DMA_CTR2_TRIGSEL) >> DMA_CTR2_TRIGSEL_Pos;
+ pNodeConfig->Init.TransferEventMode = pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_TCEM;
+ /*********************************************************************************** CTR2 fields values are updated */
+
+
+ /* Get CBR1 fields **************************************************************************************************/
+ pNodeConfig->DataSize = pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_BNDT;
+
+ if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR)
+ {
+ pNodeConfig->RepeatBlockConfig.RepeatCount =
+ ((pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_BRC) >> DMA_CBR1_BRC_Pos) + 1U;
+ }
+ else
+ {
+ pNodeConfig->RepeatBlockConfig.RepeatCount = 1U;
+ }
+ /*********************************************************************************** CBR1 fields values are updated */
+
+
+ /* Get CSAR field ***************************************************************************************************/
+ pNodeConfig->SrcAddress = pNode->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET];
+ /************************************************************************************** CSAR field value is updated */
+
+
+ /* Get CDAR field ***************************************************************************************************/
+ pNodeConfig->DstAddress = pNode->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET];
+ /************************************************************************************** CDAR field value is updated */
+
+ /* Check if the selected channel is 2D addressing */
+ if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR)
+ {
+ /* Get CTR3 field *************************************************************************************************/
+ offset = (uint16_t)(pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] & DMA_CTR3_SAO);
+ pNodeConfig->RepeatBlockConfig.SrcAddrOffset = (int32_t)offset;
+
+ offset = (uint16_t)((pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] & DMA_CTR3_DAO) >> DMA_CTR3_DAO_Pos);
+ pNodeConfig->RepeatBlockConfig.DestAddrOffset = (int32_t)offset;
+
+ if ((pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_SDEC) != 0U)
+ {
+ pNodeConfig->RepeatBlockConfig.SrcAddrOffset *= (-1);
+ }
+
+ if ((pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_DDEC) != 0U)
+ {
+ pNodeConfig->RepeatBlockConfig.DestAddrOffset *= (-1);
+ }
+ /************************************************************************************ CTR3 field value is updated */
+
+
+ /* Get CBR2 fields ************************************************************************************************/
+ offset = (uint16_t)(pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] & DMA_CBR2_BRSAO);
+ pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset = (int32_t)offset;
+
+ offset = (uint16_t)((pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] & DMA_CBR2_BRDAO) >> DMA_CBR2_BRDAO_Pos);
+ pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset = (int32_t)offset;
+
+ if ((pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_BRSDEC) != 0U)
+ {
+ pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset *= (-1);
+ }
+
+ if ((pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_BRDDEC) != 0U)
+ {
+ pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset *= (-1);
+ }
+ /************************************************************************************ CBR2 field value is updated */
+ }
+ else
+ {
+ /* Get CTR3 field *************************************************************************************************/
+ pNodeConfig->RepeatBlockConfig.SrcAddrOffset = 0;
+ pNodeConfig->RepeatBlockConfig.DestAddrOffset = 0;
+ /************************************************************************************ CTR3 field value is updated */
+
+
+ /* Get CBR2 fields ************************************************************************************************/
+ pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset = 0;
+ pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset = 0;
+ /************************************************************************************ CBR2 field value is updated */
+ }
+}
+
+/**
+ * @brief Check nodes base addresses compatibility.
+ * @param pNode1 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 1 registers configurations.
+ * @param pNode2 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 2 registers configurations.
+ * @param pNode3 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 3 registers configurations.
+ * @retval Return 0 when nodes addresses are compatible, 1 otherwise.
+ */
+static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1,
+ DMA_NodeTypeDef const *const pNode2,
+ DMA_NodeTypeDef const *const pNode3)
+{
+ uint32_t temp = (((uint32_t)pNode1 | (uint32_t)pNode2 | (uint32_t)pNode3) & DMA_CLBAR_LBA);
+ uint32_t ref = 0U;
+
+ /* Check node 1 address */
+ if ((uint32_t)pNode1 != 0U)
+ {
+ ref = (uint32_t)pNode1;
+ }
+ /* Check node 2 address */
+ else if ((uint32_t)pNode2 != 0U)
+ {
+ ref = (uint32_t)pNode2;
+ }
+ /* Check node 3 address */
+ else if ((uint32_t)pNode3 != 0U)
+ {
+ ref = (uint32_t)pNode3;
+ }
+ else
+ {
+ /* Prevent MISRA-C2012-Rule-15.7 */
+ }
+
+ /* Check addresses compatibility */
+ if (temp != ((uint32_t)ref & DMA_CLBAR_LBA))
+ {
+ return 1U;
+ }
+
+ return 0U;
+}
+
+/**
+ * @brief Check nodes types compatibility.
+ * @param pNode1 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 1 registers configurations.
+ * @param pNode2 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 2 registers configurations.
+ * @param pNode3 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 3 registers configurations.
+ * @retval Return 0 when nodes types are compatible, otherwise nodes types are not compatible.
+ */
+static uint32_t DMA_List_CheckNodesTypes(DMA_NodeTypeDef const *const pNode1,
+ DMA_NodeTypeDef const *const pNode2,
+ DMA_NodeTypeDef const *const pNode3)
+{
+ uint32_t ref = 0U;
+
+ /* Check node 1 parameter */
+ if (pNode1 != NULL)
+ {
+ ref = pNode1->NodeInfo & NODE_TYPE_MASK;
+ }
+ /* Check node 2 parameter */
+ else if (pNode2 != NULL)
+ {
+ ref = pNode2->NodeInfo & NODE_TYPE_MASK;
+ }
+ /* Check node 3 parameter */
+ else if (pNode3 != NULL)
+ {
+ ref = pNode3->NodeInfo & NODE_TYPE_MASK;
+ }
+ else
+ {
+ /* Prevent MISRA-C2012-Rule-15.7 */
+ }
+
+ /* Check node 2 parameter */
+ if (pNode2 != NULL)
+ {
+ /* Check node type compatibility */
+ if (ref != (pNode2->NodeInfo & NODE_TYPE_MASK))
+ {
+ return 2U;
+ }
+ }
+
+ /* Check node 3 parameter */
+ if (pNode3 != NULL)
+ {
+ /* Check node type compatibility */
+ if (ref != (pNode3->NodeInfo & NODE_TYPE_MASK))
+ {
+ return 3U;
+ }
+ }
+
+ return 0U;
+}
+
+/**
+ * @brief Check nodes types compatibility.
+ * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers
+ * configurations.
+ * @param cllr_mask : Pointer to CLLR register mask value.
+ * @param cllr_offset : Pointer to CLLR register offset value.
+ * @retval None.
+ */
+static void DMA_List_GetCLLRNodeInfo(DMA_NodeTypeDef const *const pNode,
+ uint32_t *const cllr_mask,
+ uint32_t *const cllr_offset)
+{
+ /* Check node type */
+ if ((pNode->NodeInfo & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR)
+ {
+ /* Update CLLR register mask value */
+ if (cllr_mask != NULL)
+ {
+ *cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 |
+ DMA_CLLR_UB2 | DMA_CLLR_ULL;
+ }
+
+ /* Update CLLR register offset */
+ if (cllr_offset != NULL)
+ {
+ *cllr_offset = NODE_CLLR_2D_DEFAULT_OFFSET;
+ }
+ }
+ /* Update CLLR and register number for linear addressing node */
+ else
+ {
+ /* Update CLLR register mask value */
+ if (cllr_mask != NULL)
+ {
+ *cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_ULL;
+ }
+
+ /* Update CLLR register offset */
+ if (cllr_offset != NULL)
+ {
+ *cllr_offset = NODE_CLLR_LINEAR_DEFAULT_OFFSET;
+ }
+ }
+}
+
+/**
+ * @brief Find node in queue.
+ * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
+ * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers configurations.
+ * @param NodeInfo : Pointer to a DMA_NodeInQInfoTypeDef structure that contains node linked to queue information.
+ * @retval Return 0 when node is found in selected queue, otherwise node is not found.
+ */
+static uint32_t DMA_List_FindNode(DMA_QListTypeDef const *const pQList,
+ DMA_NodeTypeDef const *const pNode,
+ DMA_NodeInQInfoTypeDef *const NodeInfo)
+{
+ uint32_t node_idx = 0U;
+ uint32_t currentnode_address = 0U;
+ uint32_t previousnode_address = 0U;
+ uint32_t cllr_offset = NodeInfo->cllr_offset;
+
+ /* Find last node in queue */
+ if (pNode == NULL)
+ {
+ /* Check that previous node is linked to the selected queue */
+ while (node_idx < pQList->NodeNumber)
+ {
+ /* Get head node address */
+ if (node_idx == 0U)
+ {
+ currentnode_address = (uint32_t)pQList->Head & DMA_CLLR_LA;
+ }
+ /* Calculate nodes addresses */
+ else
+ {
+ previousnode_address = currentnode_address;
+ currentnode_address =
+ ((DMA_NodeTypeDef *)(currentnode_address +
+ ((uint32_t)pQList->Head & DMA_CLBAR_LBA)))->LinkRegisters[cllr_offset] & DMA_CLLR_LA;
+ }
+
+ /* Increment node index */
+ node_idx++;
+ }
+ }
+ /* Find selected node node in queue */
+ else
+ {
+ /* Check that previous node is linked to the selected queue */
+ while ((node_idx < pQList->NodeNumber) && (currentnode_address != ((uint32_t)pNode & DMA_CLLR_LA)))
+ {
+ /* Get head node address */
+ if (node_idx == 0U)
+ {
+ currentnode_address = (uint32_t)pQList->Head & DMA_CLLR_LA;
+ }
+ /* Calculate nodes addresses */
+ else
+ {
+ previousnode_address = currentnode_address;
+ currentnode_address =
+ ((DMA_NodeTypeDef *)(currentnode_address +
+ ((uint32_t)pQList->Head & DMA_CLBAR_LBA)))->LinkRegisters[cllr_offset] & DMA_CLLR_LA;
+ }
+
+ /* Increment node index */
+ node_idx++;
+ }
+ }
+
+ /* Check stored address */
+ if (pNode != NULL)
+ {
+ if (currentnode_address != ((uint32_t)pNode & DMA_CLLR_LA))
+ {
+ return 1U;
+ }
+ }
+
+ /* Update current node position */
+ NodeInfo->currentnode_pos = node_idx;
+
+ /* Update previous node address */
+ NodeInfo->previousnode_addr = previousnode_address | ((uint32_t)pQList->Head & DMA_CLBAR_LBA);
+
+ /* Update current node address */
+ NodeInfo->currentnode_addr = currentnode_address | ((uint32_t)pQList->Head & DMA_CLBAR_LBA);
+
+ /* Update next node address */
+ if (((DMA_NodeTypeDef *)NodeInfo->currentnode_addr)->LinkRegisters[cllr_offset] != 0U)
+ {
+ NodeInfo->nextnode_addr = (((DMA_NodeTypeDef *)NodeInfo->currentnode_addr)->LinkRegisters[cllr_offset] &
+ DMA_CLLR_LA) | ((uint32_t)pQList->Head & DMA_CLBAR_LBA);
+ }
+
+ return 0U;
+}
+
+/**
+ * @brief Reset queue nodes.
+ * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
+ * @param NodeInfo : Pointer to a DMA_NodeInQInfoTypeDef structure that contains node linked to queue information.
+ * @retval None.
+ */
+static void DMA_List_ResetQueueNodes(DMA_QListTypeDef const *const pQList,
+ DMA_NodeInQInfoTypeDef const *const NodeInfo)
+{
+ uint32_t node_idx = 0U;
+ uint32_t currentnode_address = 0U;
+ uint32_t previousnode_address;
+ uint32_t cllr_offset = NodeInfo->cllr_offset;
+
+ /* Check that previous node is linked to the selected queue */
+ while (node_idx < pQList->NodeNumber)
+ {
+ /* Get head node address */
+ if (node_idx == 0U)
+ {
+ previousnode_address = (uint32_t)pQList->Head & DMA_CLLR_LA;
+ currentnode_address = (pQList->Head->LinkRegisters[cllr_offset] & DMA_CLLR_LA);
+ }
+ /* Calculate nodes addresses */
+ else
+ {
+ previousnode_address = currentnode_address;
+ currentnode_address =
+ ((DMA_NodeTypeDef *)(currentnode_address +
+ ((uint32_t)pQList->Head & DMA_CLBAR_LBA)))->LinkRegisters[cllr_offset] & DMA_CLLR_LA;
+ }
+
+ /* Reset node */
+ ((DMA_NodeTypeDef *)(previousnode_address +
+ ((uint32_t)pQList->Head & DMA_CLBAR_LBA)))->LinkRegisters[cllr_offset] = 0U;
+
+ /* Increment node index */
+ node_idx++;
+ }
+}
+
+/**
+ * @brief Fill source node registers values by destination nodes registers values.
+ * @param pSrcNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list source node registers
+ * configurations.
+ * @param pDestNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list destination node registers
+ * configurations.
+ * @retval None.
+ */
+static void DMA_List_FillNode(DMA_NodeTypeDef const *const pSrcNode,
+ DMA_NodeTypeDef *const pDestNode)
+{
+ /* Repeat for all register nodes */
+ for (uint32_t reg_idx = 0U; reg_idx < NODE_CLLR_IDX_POS; reg_idx++)
+ {
+ pDestNode->LinkRegisters[reg_idx] = pSrcNode->LinkRegisters[reg_idx];
+ }
+
+ /* Fill node information */
+ pDestNode->NodeInfo = pSrcNode->NodeInfo;
+}
+
+/**
+ * @brief Convert node to dynamic.
+ * @param ContextNodeAddr : The context node address.
+ * @param CurrentNodeAddr : The current node address to be converted.
+ * @param RegisterNumber : The register number to be converted.
+ * @retval None.
+ */
+static void DMA_List_ConvertNodeToDynamic(uint32_t ContextNodeAddr,
+ uint32_t CurrentNodeAddr,
+ uint32_t RegisterNumber)
+{
+ uint32_t currentnode_reg_counter = 0U;
+ uint32_t contextnode_reg_counter = 0U;
+ uint32_t cllr_idx = RegisterNumber - 1U;
+ DMA_NodeTypeDef *context_node = (DMA_NodeTypeDef *)ContextNodeAddr;
+ DMA_NodeTypeDef *current_node = (DMA_NodeTypeDef *)CurrentNodeAddr;
+ uint32_t update_link[NODE_CLLR_IDX_POS] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA,
+ DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL
+ };
+
+ /* Update ULL position according to register number */
+ update_link[cllr_idx] = update_link[NODE_CLLR_IDX_POS - 1U];
+
+ /* Repeat for all node registers */
+ while (contextnode_reg_counter != RegisterNumber)
+ {
+ /* Check if register values are equal (exception for CSAR, CDAR and CLLR registers) */
+ if ((context_node->LinkRegisters[contextnode_reg_counter] ==
+ current_node->LinkRegisters[currentnode_reg_counter]) &&
+ (contextnode_reg_counter != NODE_CSAR_DEFAULT_OFFSET) &&
+ (contextnode_reg_counter != NODE_CDAR_DEFAULT_OFFSET) &&
+ (contextnode_reg_counter != (RegisterNumber - 1U)))
+ {
+ /* Format the node according to unused registers */
+ DMA_List_FormatNode(current_node, currentnode_reg_counter, RegisterNumber, NODE_DYNAMIC_FORMAT);
+
+ /* Update CLLR index */
+ cllr_idx --;
+
+ /* Update CLLR fields */
+ current_node->LinkRegisters[cllr_idx] &= ~update_link[contextnode_reg_counter];
+ }
+ else
+ {
+ /* Update context node register fields with new values */
+ context_node->LinkRegisters[contextnode_reg_counter] = current_node->LinkRegisters[currentnode_reg_counter];
+
+ /* Update CLLR fields */
+ current_node->LinkRegisters[cllr_idx] |= update_link[contextnode_reg_counter];
+
+ /* Increment current node number register counter */
+ currentnode_reg_counter++;
+ }
+
+ /* Increment context node number register counter */
+ contextnode_reg_counter++;
+ }
+
+ /* Update node information */
+ MODIFY_REG(current_node->NodeInfo, NODE_CLLR_IDX, ((currentnode_reg_counter - 1U) << NODE_CLLR_IDX_POS));
+
+ /* Clear unused node fields */
+ DMA_List_ClearUnusedFields(current_node, currentnode_reg_counter);
+}
+
+/**
+ * @brief Convert node to static.
+ * @param ContextNodeAddr : The context node address.
+ * @param CurrentNodeAddr : The current node address to be converted.
+ * @param RegisterNumber : The register number to be converted.
+ * @retval None.
+ */
+static void DMA_List_ConvertNodeToStatic(uint32_t ContextNodeAddr,
+ uint32_t CurrentNodeAddr,
+ uint32_t RegisterNumber)
+{
+ uint32_t contextnode_reg_counter = 0U;
+ uint32_t cllr_idx;
+ uint32_t cllr_mask;
+ DMA_NodeTypeDef *context_node = (DMA_NodeTypeDef *)ContextNodeAddr;
+ DMA_NodeTypeDef *current_node = (DMA_NodeTypeDef *)CurrentNodeAddr;
+ uint32_t update_link[NODE_CLLR_IDX_POS] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA,
+ DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL
+ };
+
+ /* Update ULL position according to register number */
+ update_link[RegisterNumber - 1U] = update_link[NODE_CLLR_IDX_POS - 1U];
+
+ /* Get context node CLLR information */
+ cllr_idx = (context_node->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS;
+ cllr_mask = context_node->LinkRegisters[cllr_idx];
+
+ /* Repeat for all node registers */
+ while (contextnode_reg_counter != RegisterNumber)
+ {
+ /* Check if node field is dynamic */
+ if ((cllr_mask & update_link[contextnode_reg_counter]) == 0U)
+ {
+ /* Format the node according to unused registers */
+ DMA_List_FormatNode(current_node, contextnode_reg_counter, RegisterNumber, NODE_STATIC_FORMAT);
+
+ /* Update node field */
+ current_node->LinkRegisters[contextnode_reg_counter] = context_node->LinkRegisters[contextnode_reg_counter];
+ }
+
+ /* Increment context node number register counter */
+ contextnode_reg_counter++;
+ }
+
+ /* Update node information */
+ MODIFY_REG(current_node->NodeInfo, NODE_CLLR_IDX, ((RegisterNumber - 1U) << NODE_CLLR_IDX_POS));
+}
+
+/**
+ * @brief Format the node according to unused registers.
+ * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers
+ * configurations.
+ * @param RegisterIdx : The first register index to be formatted.
+ * @param RegisterNumber : The number of node registers.
+ * @param Format : The format type.
+ * @retval None.
+ */
+static void DMA_List_FormatNode(DMA_NodeTypeDef *const pNode,
+ uint32_t RegisterIdx,
+ uint32_t RegisterNumber,
+ uint32_t Format)
+{
+ if (Format == NODE_DYNAMIC_FORMAT)
+ {
+ /* Repeat for all registers to be formatted */
+ for (uint32_t reg_idx = RegisterIdx; reg_idx < (RegisterNumber - 1U); reg_idx++)
+ {
+ pNode->LinkRegisters[reg_idx] = pNode->LinkRegisters[reg_idx + 1U];
+ }
+ }
+ else
+ {
+ /* Repeat for all registers to be formatted */
+ for (uint32_t reg_idx = (RegisterNumber - 2U); reg_idx > RegisterIdx; reg_idx--)
+ {
+ pNode->LinkRegisters[reg_idx] = pNode->LinkRegisters[reg_idx - 1U];
+ }
+ }
+}
+
+/**
+ * @brief Clear unused register fields.
+ * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers
+ * configurations.
+ * @param FirstUnusedField : The first unused field to be cleared.
+ * @retval None.
+ */
+static void DMA_List_ClearUnusedFields(DMA_NodeTypeDef *const pNode,
+ uint32_t FirstUnusedField)
+{
+ /* Repeat for all unused fields */
+ for (uint32_t reg_idx = FirstUnusedField; reg_idx < NODE_CLLR_IDX_POS; reg_idx++)
+ {
+ pNode->LinkRegisters[reg_idx] = 0U;
+ }
+}
+
+/**
+ * @brief Update CLLR for all dynamic queue nodes.
+ * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
+ * @param LastNode_IsCircular : The first circular node is the last queue node or not.
+ * @retval None.
+ */
+static void DMA_List_UpdateDynamicQueueNodesCLLR(DMA_QListTypeDef const *const pQList,
+ uint32_t LastNode_IsCircular)
+{
+ uint32_t previous_cllr_offset;
+ uint32_t current_cllr_offset = 0U;
+ uint32_t previousnode_addr;
+ uint32_t currentnode_addr = (uint32_t)pQList->Head;
+ uint32_t cllr_mask;
+ uint32_t node_idx = 0U;
+
+ /* Repeat for all register nodes */
+ while (node_idx < pQList->NodeNumber)
+ {
+ /* Get head node address */
+ if (node_idx == 0U)
+ {
+ /* Get current node information */
+ current_cllr_offset = (((DMA_NodeTypeDef *)currentnode_addr)->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS;
+ }
+ /* Calculate nodes addresses */
+ else
+ {
+ /* Get previous node information */
+ previousnode_addr = currentnode_addr;
+ previous_cllr_offset = current_cllr_offset;
+
+ /* Get current node information */
+ currentnode_addr = (((DMA_NodeTypeDef *)(previousnode_addr))->LinkRegisters[previous_cllr_offset] & DMA_CLLR_LA) +
+ ((uint32_t)pQList->Head & DMA_CLBAR_LBA);
+ current_cllr_offset = (((DMA_NodeTypeDef *)currentnode_addr)->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS;
+
+ /* Calculate CLLR register value to be updated */
+ cllr_mask = (((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] & ~DMA_CLLR_LA) |
+ (((DMA_NodeTypeDef *)(previousnode_addr))->LinkRegisters[previous_cllr_offset] & DMA_CLLR_LA);
+
+ /* Set new CLLR value to previous node */
+ ((DMA_NodeTypeDef *)(previousnode_addr))->LinkRegisters[previous_cllr_offset] = cllr_mask;
+ }
+
+ /* Increment node index */
+ node_idx++;
+ }
+
+ /* Check queue circularity */
+ if (pQList->FirstCircularNode != 0U)
+ {
+ /* First circular queue is not last queue node */
+ if (LastNode_IsCircular == 0U)
+ {
+ /* Get CLLR node information */
+ DMA_List_GetCLLRNodeInfo(((DMA_NodeTypeDef *)currentnode_addr), &cllr_mask, NULL);
+
+ /* Update CLLR register for last circular node */
+ ((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] =
+ ((uint32_t)pQList->Head & DMA_CLLR_LA) | cllr_mask;
+ }
+ /* First circular queue is last queue node */
+ else
+ {
+ /* Disable CLLR updating */
+ ((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] &= ~DMA_CLLR_ULL;
+ }
+ }
+ else
+ {
+ /* Clear CLLR register for last node */
+ ((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] = 0U;
+ }
+}
+
+/**
+ * @brief Update CLLR for all static queue nodes.
+ * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
+ * @param operation : The operation type.
+ * @retval None.
+ */
+static void DMA_List_UpdateStaticQueueNodesCLLR(DMA_QListTypeDef const *const pQList,
+ uint32_t operation)
+{
+ uint32_t currentnode_addr = (uint32_t)pQList->Head;
+ uint32_t current_cllr_offset = ((uint32_t)pQList->Head->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS;
+ uint32_t cllr_default_offset;
+ uint32_t cllr_default_mask;
+ uint32_t cllr_mask;
+ uint32_t node_idx = 0U;
+
+ /* Get CLLR node information */
+ DMA_List_GetCLLRNodeInfo(pQList->Head, &cllr_default_mask, &cllr_default_offset);
+
+ /* Repeat for all register nodes (Bypass last queue node) */
+ while (node_idx < pQList->NodeNumber)
+ {
+ if (operation == UPDATE_CLLR_POSITION)
+ {
+ /* Get CLLR value */
+ cllr_mask = ((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset];
+ }
+ else
+ {
+ /* Calculate CLLR value */
+ cllr_mask = (((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] & DMA_CLLR_LA) |
+ cllr_default_mask;
+ }
+
+ /* Set new CLLR value to default position */
+ if ((node_idx == (pQList->NodeNumber - 1U)) && (pQList->FirstCircularNode == NULL))
+ {
+ ((DMA_NodeTypeDef *)(currentnode_addr))->LinkRegisters[cllr_default_offset] = 0U;
+ }
+ else
+ {
+ ((DMA_NodeTypeDef *)(currentnode_addr))->LinkRegisters[cllr_default_offset] = cllr_mask;
+ }
+
+ /* Update current node address with next node address */
+ currentnode_addr = (currentnode_addr & DMA_CLBAR_LBA) | (cllr_mask & DMA_CLLR_LA);
+
+ /* Update current CLLR offset with next CLLR offset */
+ current_cllr_offset = (((DMA_NodeTypeDef *)currentnode_addr)->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS;
+
+ /* Increment node index */
+ node_idx++;
+ }
+}
+
+/**
+ * @brief Clean linked-list queue variable.
+ * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
+ * @retval None.
+ */
+static void DMA_List_CleanQueue(DMA_QListTypeDef *const pQList)
+{
+ /* Clear head node */
+ pQList->Head = NULL;
+
+ /* Clear first circular queue node */
+ pQList->FirstCircularNode = NULL;
+
+ /* Reset node number */
+ pQList->NodeNumber = 0U;
+
+ /* Reset queue state */
+ pQList->State = HAL_DMA_QUEUE_STATE_RESET;
+
+ /* Reset queue error code */
+ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+ /* Reset queue type */
+ pQList->Type = QUEUE_TYPE_STATIC;
+}
+/**
+ * @}
+ */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_exti.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_exti.c
new file mode 100644
index 00000000..c1954d35
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_exti.c
@@ -0,0 +1,826 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_exti.c
+ * @author MCD Application Team
+ * @brief EXTI HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the General Purpose Input/Output (EXTI) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### EXTI Peripheral features #####
+ ==============================================================================
+ [..]
+ (+) Each Exti line can be configured within this driver.
+
+ (+) Exti line can be configured in 3 different modes
+ (++) Interrupt
+ (++) Event
+ (++) Both of them
+
+ (+) Configurable Exti lines can be configured with 3 different triggers
+ (++) Rising
+ (++) Falling
+ (++) Both of them
+
+ (+) When set in interrupt mode, configurable Exti lines have two diffenrents
+ interrupt pending registers which allow to distinguish which transition
+ occurs:
+ (++) Rising edge pending interrupt
+ (++) Falling
+
+ (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
+ be selected through multiplexer.
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+
+ (#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
+ (++) Choose the interrupt line number by setting "Line" member from
+ EXTI_ConfigTypeDef structure.
+ (++) Configure the interrupt and/or event mode using "Mode" member from
+ EXTI_ConfigTypeDef structure.
+ (++) For configurable lines, configure rising and/or falling trigger
+ "Trigger" member from EXTI_ConfigTypeDef structure.
+ (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
+ member from GPIO_InitTypeDef structure.
+
+ (#) Get current Exti configuration of a dedicated line using
+ HAL_EXTI_GetConfigLine().
+ (++) Provide exiting handle as parameter.
+ (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
+
+ (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
+ (++) Provide exiting handle as parameter.
+
+ (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
+ (++) Provide exiting handle as first parameter.
+ (++) Provide which callback will be registered using one value from
+ EXTI_CallbackIDTypeDef.
+ (++) Provide callback function pointer.
+
+ (#) Get interrupt pending bit using HAL_EXTI_GetPending().
+
+ (#) Clear interrupt pending bit using HAL_EXTI_GetPending().
+
+ (#) Generate software interrupt using HAL_EXTI_GenerateSWI().
+
+ @endverbatim
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup EXTI
+ * @{
+ */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines ------------------------------------------------------------*/
+/** @defgroup EXTI_Private_Constants EXTI Private Constants
+ * @{
+ */
+#define EXTI_MODE_OFFSET 0x04U /* byte offset between IMR/EMR registers */
+#define EXTI_CONFIG_OFFSET 0x08U /* byte offset between Rising/Falling configuration registers */
+#define EXTI_PRIVCFGR_OFFSET 0x04U /* byte offset between PRIVCFGR1/PRIVCFGR2 registers */
+#define EXTI_SECCFGR_OFFSET 0x04U /* byte offset between SECCFGR1/SECCFGR2 registers */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup EXTI_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup EXTI_Exported_Functions_Group1
+ * @brief Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Configuration functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set configuration of a dedicated Exti line.
+ * @param hexti Exti handle.
+ * @param pExtiConfig Pointer on EXTI configuration to be set.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
+{
+ __IO uint32_t *regaddr;
+ uint32_t regval;
+ uint32_t linepos;
+ uint32_t maskline;
+ uint32_t offset;
+
+ /* Check null pointer */
+ if ((hexti == NULL) || (pExtiConfig == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(pExtiConfig->Line));
+ assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
+
+ /* Assign line number to handle */
+ hexti->Line = pExtiConfig->Line;
+
+ /* compute line register offset and line mask */
+ offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+ linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
+ maskline = (1UL << linepos);
+
+ /* Configure triggers for configurable lines */
+ if ((pExtiConfig->Line & EXTI_CONFIG) != 0U)
+ {
+ assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
+
+ /* Configure rising trigger */
+ regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
+ regval = *regaddr;
+
+ /* Mask or set line */
+ if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0U)
+ {
+ regval |= maskline;
+ }
+ else
+ {
+ regval &= ~maskline;
+ }
+
+ /* Store rising trigger mode */
+ *regaddr = regval;
+
+ /* Configure falling trigger */
+ regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
+ regval = *regaddr;
+
+ /* Mask or set line */
+ if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0U)
+ {
+ regval |= maskline;
+ }
+ else
+ {
+ regval &= ~maskline;
+ }
+
+ /* Store falling trigger mode */
+ *regaddr = regval;
+
+ /* Configure gpio port selection in case of gpio exti line */
+ if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
+ {
+ assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
+ assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+ regval = EXTI->EXTICR[(linepos >> 2U) & 0x03UL];
+ regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U)));
+ regval |= (pExtiConfig->GPIOSel << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U)));
+ EXTI->EXTICR[(linepos >> 2U) & 0x03UL] = regval;
+ }
+ }
+
+ /* Configure interrupt mode : read current mode */
+ regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
+ regval = *regaddr;
+
+ /* Mask or set line */
+ if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0U)
+ {
+ regval |= maskline;
+ }
+ else
+ {
+ regval &= ~maskline;
+ }
+
+ /* Store interrupt mode */
+ *regaddr = regval;
+
+ /* Configure event mode : read current mode */
+ regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
+ regval = *regaddr;
+
+ /* Mask or set line */
+ if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0U)
+ {
+ regval |= maskline;
+ }
+ else
+ {
+ regval &= ~maskline;
+ }
+
+ /* Store event mode */
+ *regaddr = regval;
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Get configuration of a dedicated Exti line.
+ * @param hexti Exti handle.
+ * @param pExtiConfig Pointer on structure to store Exti configuration.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
+{
+ __IO uint32_t *regaddr;
+ uint32_t regval;
+ uint32_t linepos;
+ uint32_t maskline;
+ uint32_t offset;
+
+ /* Check null pointer */
+ if ((hexti == NULL) || (pExtiConfig == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameter */
+ assert_param(IS_EXTI_LINE(hexti->Line));
+
+ /* Store handle line number to configiguration structure */
+ pExtiConfig->Line = hexti->Line;
+
+ /* compute line register offset and line mask */
+ offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+ linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
+ maskline = (1UL << linepos);
+
+ /* 1] Get core mode : interrupt */
+ regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
+ regval = *regaddr;
+
+ /* Check if selected line is enable */
+ if ((regval & maskline) != 0U)
+ {
+ pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
+ }
+ else
+ {
+ pExtiConfig->Mode = EXTI_MODE_NONE;
+ }
+
+ /* Get event mode */
+ regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
+ regval = *regaddr;
+
+ /* Check if selected line is enable */
+ if ((regval & maskline) != 0U)
+ {
+ pExtiConfig->Mode |= EXTI_MODE_EVENT;
+ }
+
+ /* 2] Get trigger for configurable lines : rising */
+ if ((pExtiConfig->Line & EXTI_CONFIG) != 0U)
+ {
+ regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
+ regval = *regaddr;
+
+ /* Get default Trigger and GPIOSel configuration */
+ pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
+ pExtiConfig->GPIOSel = 0x00u;
+
+ /* Check if configuration of selected line is enable */
+ if ((regval & maskline) != 0U)
+ {
+ pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
+ }
+
+ /* Get falling configuration */
+ regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
+ regval = *regaddr;
+
+ /* Check if configuration of selected line is enable */
+ if ((regval & maskline) != 0U)
+ {
+ pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
+ }
+
+ /* Get Gpio port selection for gpio lines */
+ if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
+ {
+ assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+ regval = EXTI->EXTICR[(linepos >> 2U) & 0x03UL];
+ pExtiConfig->GPIOSel = ((regval << (EXTI_EXTICR1_EXTI1_Pos * (3U - (linepos & 0x03U)))) >> 24U);
+ }
+ }
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Clear whole configuration of a dedicated Exti line.
+ * @param hexti Exti handle.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
+{
+ __IO uint32_t *regaddr;
+ uint32_t regval;
+ uint32_t linepos;
+ uint32_t maskline;
+ uint32_t offset;
+
+ /* Check null pointer */
+ if (hexti == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameter */
+ assert_param(IS_EXTI_LINE(hexti->Line));
+
+ /* compute line register offset and line mask */
+ offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+ linepos = (hexti->Line & EXTI_PIN_MASK);
+ maskline = (1UL << linepos);
+
+ /* 1] Clear interrupt mode */
+ regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
+ regval = (*regaddr & ~maskline);
+ *regaddr = regval;
+
+ /* 2] Clear event mode */
+ regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
+ regval = (*regaddr & ~maskline);
+ *regaddr = regval;
+
+ /* 3] Clear triggers in case of configurable lines */
+ if ((hexti->Line & EXTI_CONFIG) != 0U)
+ {
+ regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
+ regval = (*regaddr & ~maskline);
+ *regaddr = regval;
+
+ regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
+ regval = (*regaddr & ~maskline);
+ *regaddr = regval;
+
+ /* Get Gpio port selection for gpio lines */
+ if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
+ {
+ assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+ regval = EXTI->EXTICR[(linepos >> 2U) & 0x03UL];
+ regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U)));
+ EXTI->EXTICR[(linepos >> 2U) & 0x03UL] = regval;
+ }
+ }
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Register callback for a dedicaated Exti line.
+ * @param hexti Exti handle.
+ * @param CallbackID User callback identifier.
+ * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
+ * @param pPendingCbfn function pointer to be stored as callback.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID,
+ void (*pPendingCbfn)(void))
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ switch (CallbackID)
+ {
+ case HAL_EXTI_COMMON_CB_ID:
+ hexti->RisingCallback = pPendingCbfn;
+ hexti->FallingCallback = pPendingCbfn;
+ break;
+
+ case HAL_EXTI_RISING_CB_ID:
+ hexti->RisingCallback = pPendingCbfn;
+ break;
+
+ case HAL_EXTI_FALLING_CB_ID:
+ hexti->FallingCallback = pPendingCbfn;
+ break;
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ return status;
+}
+
+
+/**
+ * @brief Store line number as handle private field.
+ * @param hexti Exti handle.
+ * @param ExtiLine Exti line number.
+ * This parameter can be from 0 to @ref EXTI_LINE_NB.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(ExtiLine));
+
+ /* Check null pointer */
+ if (hexti == NULL)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Store line number as handle private field */
+ hexti->Line = ExtiLine;
+
+ return HAL_OK;
+ }
+}
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Exported_Functions_Group2
+ * @brief EXTI IO functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Handle EXTI interrupt request.
+ * @param hexti Exti handle.
+ * @retval none.
+ */
+void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
+{
+ __IO uint32_t *regaddr;
+ uint32_t regval;
+ uint32_t maskline;
+ uint32_t offset;
+
+ /* Compute line register offset and line mask */
+ offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+ maskline = (1UL << (hexti->Line & EXTI_PIN_MASK));
+
+ /* Get rising edge pending bit */
+ regaddr = (__IO uint32_t *)(&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset));
+ regval = (*regaddr & maskline);
+
+ if (regval != 0U)
+ {
+ /* Clear pending bit */
+ *regaddr = maskline;
+
+ /* Call rising callback */
+ if (hexti->RisingCallback != NULL)
+ {
+ hexti->RisingCallback();
+ }
+ }
+
+ /* Get falling edge pending bit */
+ regaddr = (__IO uint32_t *)(&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset));
+ regval = (*regaddr & maskline);
+
+ if (regval != 0U)
+ {
+ /* Clear pending bit */
+ *regaddr = maskline;
+
+ /* Call rising callback */
+ if (hexti->FallingCallback != NULL)
+ {
+ hexti->FallingCallback();
+ }
+ }
+}
+
+
+/**
+ * @brief Get interrupt pending bit of a dedicated line.
+ * @param hexti Exti handle.
+ * @param Edge Specify which pending edge as to be checked.
+ * This parameter can be one of the following values:
+ * @arg @ref EXTI_TRIGGER_RISING
+ * @arg @ref EXTI_TRIGGER_FALLING
+ * @retval 1 if interrupt is pending else 0.
+ */
+uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
+{
+ __IO uint32_t *regaddr;
+ uint32_t regval;
+ uint32_t linepos;
+ uint32_t maskline;
+ uint32_t offset;
+
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(hexti->Line));
+ assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+ assert_param(IS_EXTI_PENDING_EDGE(Edge));
+
+ /* compute line register offset and line mask */
+ offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+ linepos = (hexti->Line & EXTI_PIN_MASK);
+ maskline = (1UL << linepos);
+
+ if (Edge != EXTI_TRIGGER_RISING)
+ {
+ /* Get falling edge pending bit */
+ regaddr = (__IO uint32_t *)(&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset));
+ }
+ else
+ {
+ /* Get rising edge pending bit */
+ regaddr = (__IO uint32_t *)(&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset));
+ }
+
+ /* return 1 if bit is set else 0 */
+ regval = ((*regaddr & maskline) >> linepos);
+ return regval;
+}
+
+
+/**
+ * @brief Clear interrupt pending bit of a dedicated line.
+ * @param hexti Exti handle.
+ * @param Edge Specify which pending edge as to be clear.
+ * This parameter can be one of the following values:
+ * @arg @ref EXTI_TRIGGER_RISING
+ * @arg @ref EXTI_TRIGGER_FALLING
+ * @retval None.
+ */
+void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
+{
+ __IO uint32_t *regaddr;
+ uint32_t maskline;
+ uint32_t offset;
+
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(hexti->Line));
+ assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+ assert_param(IS_EXTI_PENDING_EDGE(Edge));
+
+ /* compute line register offset and line mask */
+ offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+ maskline = (1UL << (hexti->Line & EXTI_PIN_MASK));
+
+ if (Edge != EXTI_TRIGGER_RISING)
+ {
+ /* Get falling edge pending register address */
+ regaddr = (__IO uint32_t *)(&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset));
+ }
+ else
+ {
+ /* Get falling edge pending register address */
+ regaddr = (__IO uint32_t *)(&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset));
+ }
+
+ /* Clear Pending bit */
+ *regaddr = maskline;
+}
+
+
+/**
+ * @brief Generate a software interrupt for a dedicated line.
+ * @param hexti Exti handle.
+ * @retval None.
+ */
+void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
+{
+ __IO uint32_t *regaddr;
+ uint32_t maskline;
+ uint32_t offset;
+
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(hexti->Line));
+ assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+
+ /* compute line register offset and line mask */
+ offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+ maskline = (1UL << (hexti->Line & EXTI_PIN_MASK));
+
+ regaddr = (__IO uint32_t *)(&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset));
+ *regaddr = maskline;
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Exported_Functions_Group3 EXTI line attributes management functions
+ * @brief EXTI attributes management functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### EXTI attributes functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the EXTI line attribute(s).
+ * @note Available attributes are to secure EXTI line and set EXT line as privileged.
+ * Default state is not secure and unprivileged access allowed.
+ * @note Secure and non-secure attributes can only be set from the secure
+ * state when the system implements the security (TZEN=1).
+ * @note Security and privilege attributes can be set independently.
+ * @param ExtiLine Exti line number.
+ * This parameter can be from 0 to @ref EXTI_LINE_NB.
+ * @param LineAttributes can be one or a combination of the following values:
+ * @arg @ref EXTI_LINE_PRIV Privileged-only access
+ * @arg @ref EXTI_LINE_NPRIV Privileged/Non-privileged access
+ * @arg @ref EXTI_LINE_SEC Secure-only access
+ * @arg @ref EXTI_LINE_NSEC Secure/Non-secure access
+ * @retval None
+ */
+void HAL_EXTI_ConfigLineAttributes(uint32_t ExtiLine, uint32_t LineAttributes)
+{
+ __IO uint32_t *regaddr;
+ uint32_t regval;
+ uint32_t linepos;
+ uint32_t maskline;
+ uint32_t offset;
+
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(ExtiLine));
+ assert_param(IS_EXTI_LINE_ATTRIBUTES(LineAttributes));
+
+ /* compute line register offset and line mask */
+ offset = ((ExtiLine & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+ linepos = (ExtiLine & EXTI_PIN_MASK);
+ maskline = (1UL << linepos);
+
+ /* Configure privilege or non-privilege attributes */
+ regaddr = (__IO uint32_t *)(&EXTI->PRIVCFGR1 + (EXTI_PRIVCFGR_OFFSET * offset));
+ regval = *regaddr;
+
+ /* Mask or set line */
+ if ((LineAttributes & EXTI_LINE_PRIV) == EXTI_LINE_PRIV)
+ {
+ regval |= maskline;
+ }
+ else if ((LineAttributes & EXTI_LINE_NPRIV) == EXTI_LINE_NPRIV)
+ {
+ regval &= ~maskline;
+ }
+ else
+ {
+ /* do nothing */
+ }
+
+ /* Store privilege or non-privilege attribute */
+ *regaddr = regval;
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+ /* Configure secure or non-secure attributes */
+ regaddr = (__IO uint32_t *)(&EXTI->SECCFGR1 + (EXTI_SECCFGR_OFFSET * offset));
+ regval = *regaddr;
+
+ /* Mask or set line */
+ if ((LineAttributes & EXTI_LINE_SEC) == EXTI_LINE_SEC)
+ {
+ regval |= maskline;
+ }
+ else if ((LineAttributes & EXTI_LINE_NSEC) == EXTI_LINE_NSEC)
+ {
+ regval &= ~maskline;
+ }
+ else
+ {
+ /* do nothing */
+ }
+
+ /* Store secure or non-secure attribute */
+ *regaddr = regval;
+
+#endif /* __ARM_FEATURE_CMSE */
+}
+
+/**
+ * @brief Get the EXTI line attribute(s).
+ * @note Secure and non-secure attributes are only available from secure state
+ * when the system implements the security (TZEN=1)
+ * @param ExtiLine Exti line number.
+ * This parameter can be from 0 to @ref EXTI_LINE_NB.
+ * @param pLineAttributes: pointer to return line attributes.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_GetConfigLineAttributes(uint32_t ExtiLine, uint32_t *pLineAttributes)
+{
+ __IO uint32_t *regaddr;
+ uint32_t linepos;
+ uint32_t maskline;
+ uint32_t offset;
+ uint32_t attributes;
+
+ /* Check null pointer */
+ if (pLineAttributes == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(ExtiLine));
+
+ /* Compute line register offset and line mask */
+ offset = ((ExtiLine & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+ linepos = (ExtiLine & EXTI_PIN_MASK);
+ maskline = (1UL << linepos);
+
+ /* Get privilege or non-privilege attribute */
+ regaddr = (__IO uint32_t *)(&EXTI->PRIVCFGR1 + (EXTI_PRIVCFGR_OFFSET * offset));
+
+ if ((*regaddr & maskline) != 0U)
+ {
+ attributes = EXTI_LINE_PRIV;
+ }
+ else
+ {
+ attributes = EXTI_LINE_NPRIV;
+ }
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+ /* Get secure or non-secure attribute */
+ regaddr = (__IO uint32_t *)(&EXTI->SECCFGR1 + (EXTI_SECCFGR_OFFSET * offset));
+
+ if ((*regaddr & maskline) != 0U)
+ {
+ attributes |= EXTI_LINE_SEC;
+ }
+ else
+ {
+ attributes |= EXTI_LINE_NSEC;
+ }
+
+#endif /* __ARM_FEATURE_CMSE */
+
+ /* return value */
+ *pLineAttributes = attributes;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_EXTI_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_fdcan.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_fdcan.c
new file mode 100644
index 00000000..7c0fc47c
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_fdcan.c
@@ -0,0 +1,3498 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_fdcan.c
+ * @author MCD Application Team
+ * @brief FDCAN HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Flexible DataRate Controller Area Network
+ * (FDCAN) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Configuration and Control functions
+ * + Peripheral State and Error functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Initialize the FDCAN peripheral using HAL_FDCAN_Init function.
+
+ (#) If needed , configure the reception filters and optional features using
+ the following configuration functions:
+ (++) HAL_FDCAN_ConfigFilter
+ (++) HAL_FDCAN_ConfigGlobalFilter
+ (++) HAL_FDCAN_ConfigExtendedIdMask
+ (++) HAL_FDCAN_ConfigRxFifoOverwrite
+ (++) HAL_FDCAN_ConfigRamWatchdog
+ (++) HAL_FDCAN_ConfigTimestampCounter
+ (++) HAL_FDCAN_EnableTimestampCounter
+ (++) HAL_FDCAN_DisableTimestampCounter
+ (++) HAL_FDCAN_ConfigTimeoutCounter
+ (++) HAL_FDCAN_EnableTimeoutCounter
+ (++) HAL_FDCAN_DisableTimeoutCounter
+ (++) HAL_FDCAN_ConfigTxDelayCompensation
+ (++) HAL_FDCAN_EnableTxDelayCompensation
+ (++) HAL_FDCAN_DisableTxDelayCompensation
+ (++) HAL_FDCAN_EnableISOMode
+ (++) HAL_FDCAN_DisableISOMode
+ (++) HAL_FDCAN_EnableEdgeFiltering
+ (++) HAL_FDCAN_DisableEdgeFiltering
+
+ (#) Start the FDCAN module using HAL_FDCAN_Start function. At this level
+ the node is active on the bus: it can send and receive messages.
+
+ (#) The following Tx control functions can only be called when the FDCAN
+ module is started:
+ (++) HAL_FDCAN_AddMessageToTxFifoQ
+ (++) HAL_FDCAN_AbortTxRequest
+
+ (#) After having submitted a Tx request in Tx Fifo or Queue, it is possible to
+ get Tx buffer location used to place the Tx request thanks to
+ HAL_FDCAN_GetLatestTxFifoQRequestBuffer API.
+ It is then possible to abort later on the corresponding Tx Request using
+ HAL_FDCAN_AbortTxRequest API.
+
+ (#) When a message is received into the FDCAN message RAM, it can be
+ retrieved using the HAL_FDCAN_GetRxMessage function.
+
+ (#) Calling the HAL_FDCAN_Stop function stops the FDCAN module by entering
+ it to initialization mode and re-enabling access to configuration
+ registers through the configuration functions listed here above.
+
+ (#) All other control functions can be called any time after initialization
+ phase, no matter if the FDCAN module is started or stopped.
+
+ *** Polling mode operation ***
+ ==============================
+ [..]
+ (#) Reception and transmission states can be monitored via the following
+ functions:
+ (++) HAL_FDCAN_IsTxBufferMessagePending
+ (++) HAL_FDCAN_GetRxFifoFillLevel
+ (++) HAL_FDCAN_GetTxFifoFreeLevel
+
+ *** Interrupt mode operation ***
+ ================================
+ [..]
+ (#) There are two interrupt lines: line 0 and 1.
+ By default, all interrupts are assigned to line 0. Interrupt lines
+ can be configured using HAL_FDCAN_ConfigInterruptLines function.
+
+ (#) Notifications are activated using HAL_FDCAN_ActivateNotification
+ function. Then, the process can be controlled through one of the
+ available user callbacks: HAL_FDCAN_xxxCallback.
+
+ *** Callback registration ***
+ =============================================
+
+ The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Function @ref HAL_FDCAN_RegisterCallback() or HAL_FDCAN_RegisterXXXCallback()
+ to register an interrupt callback.
+
+ Function @ref HAL_FDCAN_RegisterCallback() allows to register following callbacks:
+ (+) TxFifoEmptyCallback : Tx Fifo Empty Callback.
+ (+) HighPriorityMessageCallback : High Priority Message Callback.
+ (+) TimestampWraparoundCallback : Timestamp Wraparound Callback.
+ (+) TimeoutOccurredCallback : Timeout Occurred Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) MspInitCallback : FDCAN MspInit.
+ (+) MspDeInitCallback : FDCAN MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ For specific callbacks TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback,
+ TxBufferCompleteCallback, TxBufferAbortCallback and ErrorStatusCallback use dedicated
+ register callbacks : respectively @ref HAL_FDCAN_RegisterTxEventFifoCallback(),
+ @ref HAL_FDCAN_RegisterRxFifo0Callback(), @ref HAL_FDCAN_RegisterRxFifo1Callback(),
+ @ref HAL_FDCAN_RegisterTxBufferCompleteCallback(), @ref HAL_FDCAN_RegisterTxBufferAbortCallback()
+ and @ref HAL_FDCAN_RegisterErrorStatusCallback().
+
+ Use function @ref HAL_FDCAN_UnRegisterCallback() to reset a callback to the default
+ weak function.
+ @ref HAL_FDCAN_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TxFifoEmptyCallback : Tx Fifo Empty Callback.
+ (+) HighPriorityMessageCallback : High Priority Message Callback.
+ (+) TimestampWraparoundCallback : Timestamp Wraparound Callback.
+ (+) TimeoutOccurredCallback : Timeout Occurred Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) MspInitCallback : FDCAN MspInit.
+ (+) MspDeInitCallback : FDCAN MspDeInit.
+
+ For specific callbacks TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback,
+ TxBufferCompleteCallback and TxBufferAbortCallback, use dedicated
+ unregister callbacks : respectively @ref HAL_FDCAN_UnRegisterTxEventFifoCallback(),
+ @ref HAL_FDCAN_UnRegisterRxFifo0Callback(), @ref HAL_FDCAN_UnRegisterRxFifo1Callback(),
+ @ref HAL_FDCAN_UnRegisterTxBufferCompleteCallback(), @ref HAL_FDCAN_UnRegisterTxBufferAbortCallback()
+ and @ref HAL_FDCAN_UnRegisterErrorStatusCallback().
+
+ By default, after the @ref HAL_FDCAN_Init() and when the state is HAL_FDCAN_STATE_RESET,
+ all callbacks are set to the corresponding weak functions:
+ examples @ref HAL_FDCAN_ErrorCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak function in the @ref HAL_FDCAN_Init()/ @ref HAL_FDCAN_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ if not, MspInit or MspDeInit are not null, the @ref HAL_FDCAN_Init()/ @ref HAL_FDCAN_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in HAL_FDCAN_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_FDCAN_STATE_READY or HAL_FDCAN_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_FDCAN_RegisterCallback() before calling @ref HAL_FDCAN_DeInit()
+ or @ref HAL_FDCAN_Init() function.
+
+ When The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+#if defined(FDCAN1)
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup FDCAN FDCAN
+ * @brief FDCAN HAL module driver
+ * @{
+ */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup FDCAN_Private_Constants
+ * @{
+ */
+#define FDCAN_TIMEOUT_VALUE 10U
+
+#define FDCAN_TX_EVENT_FIFO_MASK (FDCAN_IR_TEFL | FDCAN_IR_TEFF | FDCAN_IR_TEFN)
+#define FDCAN_RX_FIFO0_MASK (FDCAN_IR_RF0L | FDCAN_IR_RF0F | FDCAN_IR_RF0N)
+#define FDCAN_RX_FIFO1_MASK (FDCAN_IR_RF1L | FDCAN_IR_RF1F | FDCAN_IR_RF1N)
+#define FDCAN_ERROR_MASK (FDCAN_IR_ELO | FDCAN_IR_WDI | FDCAN_IR_PEA | FDCAN_IR_PED | FDCAN_IR_ARA)
+#define FDCAN_ERROR_STATUS_MASK (FDCAN_IR_EP | FDCAN_IR_EW | FDCAN_IR_BO)
+
+#define FDCAN_ELEMENT_MASK_STDID ((uint32_t)0x1FFC0000U) /* Standard Identifier */
+#define FDCAN_ELEMENT_MASK_EXTID ((uint32_t)0x1FFFFFFFU) /* Extended Identifier */
+#define FDCAN_ELEMENT_MASK_RTR ((uint32_t)0x20000000U) /* Remote Transmission Request */
+#define FDCAN_ELEMENT_MASK_XTD ((uint32_t)0x40000000U) /* Extended Identifier */
+#define FDCAN_ELEMENT_MASK_ESI ((uint32_t)0x80000000U) /* Error State Indicator */
+#define FDCAN_ELEMENT_MASK_TS ((uint32_t)0x0000FFFFU) /* Timestamp */
+#define FDCAN_ELEMENT_MASK_DLC ((uint32_t)0x000F0000U) /* Data Length Code */
+#define FDCAN_ELEMENT_MASK_BRS ((uint32_t)0x00100000U) /* Bit Rate Switch */
+#define FDCAN_ELEMENT_MASK_FDF ((uint32_t)0x00200000U) /* FD Format */
+#define FDCAN_ELEMENT_MASK_EFC ((uint32_t)0x00800000U) /* Event FIFO Control */
+#define FDCAN_ELEMENT_MASK_MM ((uint32_t)0xFF000000U) /* Message Marker */
+#define FDCAN_ELEMENT_MASK_FIDX ((uint32_t)0x7F000000U) /* Filter Index */
+#define FDCAN_ELEMENT_MASK_ANMF ((uint32_t)0x80000000U) /* Accepted Non-matching Frame */
+#define FDCAN_ELEMENT_MASK_ET ((uint32_t)0x00C00000U) /* Event type */
+
+#define SRAMCAN_FLS_NBR (28U) /* Max. Filter List Standard Number */
+#define SRAMCAN_FLE_NBR ( 8U) /* Max. Filter List Extended Number */
+#define SRAMCAN_RF0_NBR ( 3U) /* RX FIFO 0 Elements Number */
+#define SRAMCAN_RF1_NBR ( 3U) /* RX FIFO 1 Elements Number */
+#define SRAMCAN_TEF_NBR ( 3U) /* TX Event FIFO Elements Number */
+#define SRAMCAN_TFQ_NBR ( 3U) /* TX FIFO/Queue Elements Number */
+
+#define SRAMCAN_FLS_SIZE ( 1U * 4U) /* Filter Standard Element Size in bytes */
+#define SRAMCAN_FLE_SIZE ( 2U * 4U) /* Filter Extended Element Size in bytes */
+#define SRAMCAN_RF0_SIZE (18U * 4U) /* RX FIFO 0 Elements Size in bytes */
+#define SRAMCAN_RF1_SIZE (18U * 4U) /* RX FIFO 1 Elements Size in bytes */
+#define SRAMCAN_TEF_SIZE ( 2U * 4U) /* TX Event FIFO Elements Size in bytes */
+#define SRAMCAN_TFQ_SIZE (18U * 4U) /* TX FIFO/Queue Elements Size in bytes */
+
+#define SRAMCAN_FLSSA ((uint32_t)0) /* Filter List Standard Start
+ Address */
+#define SRAMCAN_FLESA ((uint32_t)(SRAMCAN_FLSSA + (SRAMCAN_FLS_NBR * SRAMCAN_FLS_SIZE))) /* Filter List Extended Start
+ Address */
+#define SRAMCAN_RF0SA ((uint32_t)(SRAMCAN_FLESA + (SRAMCAN_FLE_NBR * SRAMCAN_FLE_SIZE))) /* Rx FIFO 0 Start Address */
+#define SRAMCAN_RF1SA ((uint32_t)(SRAMCAN_RF0SA + (SRAMCAN_RF0_NBR * SRAMCAN_RF0_SIZE))) /* Rx FIFO 1 Start Address */
+#define SRAMCAN_TEFSA ((uint32_t)(SRAMCAN_RF1SA + (SRAMCAN_RF1_NBR * SRAMCAN_RF1_SIZE))) /* Tx Event FIFO Start
+ Address */
+#define SRAMCAN_TFQSA ((uint32_t)(SRAMCAN_TEFSA + (SRAMCAN_TEF_NBR * SRAMCAN_TEF_SIZE))) /* Tx FIFO/Queue Start
+ Address */
+#define SRAMCAN_SIZE ((uint32_t)(SRAMCAN_TFQSA + (SRAMCAN_TFQ_NBR * SRAMCAN_TFQ_SIZE))) /* Message RAM size */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @addtogroup FDCAN_Private_Variables
+ * @{
+ */
+static const uint8_t DLCtoBytes[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64};
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+static void FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan);
+static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData,
+ uint32_t BufferIndex);
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup FDCAN_Exported_Functions FDCAN Exported Functions
+ * @{
+ */
+
+/** @defgroup FDCAN_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the FDCAN.
+ (+) De-initialize the FDCAN.
+ (+) Enter FDCAN peripheral in power down mode.
+ (+) Exit power down mode.
+ (+) Register callbacks.
+ (+) Unregister callbacks.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the FDCAN peripheral according to the specified
+ * parameters in the FDCAN_InitTypeDef structure.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan)
+{
+ uint32_t tickstart;
+
+ /* Check FDCAN handle */
+ if (hfdcan == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance));
+ assert_param(IS_FDCAN_CKDIV(hfdcan->Init.ClockDivider));
+ assert_param(IS_FDCAN_FRAME_FORMAT(hfdcan->Init.FrameFormat));
+ assert_param(IS_FDCAN_MODE(hfdcan->Init.Mode));
+ assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.AutoRetransmission));
+ assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.TransmitPause));
+ assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.ProtocolException));
+ assert_param(IS_FDCAN_NOMINAL_PRESCALER(hfdcan->Init.NominalPrescaler));
+ assert_param(IS_FDCAN_NOMINAL_SJW(hfdcan->Init.NominalSyncJumpWidth));
+ assert_param(IS_FDCAN_NOMINAL_TSEG1(hfdcan->Init.NominalTimeSeg1));
+ assert_param(IS_FDCAN_NOMINAL_TSEG2(hfdcan->Init.NominalTimeSeg2));
+ if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS)
+ {
+ assert_param(IS_FDCAN_DATA_PRESCALER(hfdcan->Init.DataPrescaler));
+ assert_param(IS_FDCAN_DATA_SJW(hfdcan->Init.DataSyncJumpWidth));
+ assert_param(IS_FDCAN_DATA_TSEG1(hfdcan->Init.DataTimeSeg1));
+ assert_param(IS_FDCAN_DATA_TSEG2(hfdcan->Init.DataTimeSeg2));
+ }
+ assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.StdFiltersNbr, SRAMCAN_FLS_NBR));
+ assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.ExtFiltersNbr, SRAMCAN_FLE_NBR));
+ assert_param(IS_FDCAN_TX_FIFO_QUEUE_MODE(hfdcan->Init.TxFifoQueueMode));
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+ if (hfdcan->State == HAL_FDCAN_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hfdcan->Lock = HAL_UNLOCKED;
+
+ /* Reset callbacks to legacy functions */
+ hfdcan->TxEventFifoCallback = HAL_FDCAN_TxEventFifoCallback; /* Legacy weak TxEventFifoCallback */
+ hfdcan->RxFifo0Callback = HAL_FDCAN_RxFifo0Callback; /* Legacy weak RxFifo0Callback */
+ hfdcan->RxFifo1Callback = HAL_FDCAN_RxFifo1Callback; /* Legacy weak RxFifo1Callback */
+ hfdcan->TxFifoEmptyCallback = HAL_FDCAN_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
+ hfdcan->TxBufferCompleteCallback = HAL_FDCAN_TxBufferCompleteCallback; /* Legacy weak
+ TxBufferCompleteCallback */
+ hfdcan->TxBufferAbortCallback = HAL_FDCAN_TxBufferAbortCallback; /* Legacy weak
+ TxBufferAbortCallback */
+ hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback; /* Legacy weak
+ HighPriorityMessageCallback */
+ hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback; /* Legacy weak
+ TimestampWraparoundCallback */
+ hfdcan->TimeoutOccurredCallback = HAL_FDCAN_TimeoutOccurredCallback; /* Legacy weak
+ TimeoutOccurredCallback */
+ hfdcan->ErrorCallback = HAL_FDCAN_ErrorCallback; /* Legacy weak ErrorCallback */
+ hfdcan->ErrorStatusCallback = HAL_FDCAN_ErrorStatusCallback; /* Legacy weak ErrorStatusCallback */
+
+ if (hfdcan->MspInitCallback == NULL)
+ {
+ hfdcan->MspInitCallback = HAL_FDCAN_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware: CLOCK, NVIC */
+ hfdcan->MspInitCallback(hfdcan);
+ }
+#else
+ if (hfdcan->State == HAL_FDCAN_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hfdcan->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware: CLOCK, NVIC */
+ HAL_FDCAN_MspInit(hfdcan);
+ }
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+ /* Exit from Sleep mode */
+ CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check Sleep mode acknowledge */
+ while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
+ {
+ if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Request initialisation */
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until the INIT bit into CCCR register is set */
+ while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U)
+ {
+ /* Check for the Timeout */
+ if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Enable configuration change */
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE);
+
+ /* Configure Clock divider */
+ FDCAN_CONFIG->CKDIV = hfdcan->Init.ClockDivider;
+
+ /* Set the no automatic retransmission */
+ if (hfdcan->Init.AutoRetransmission == ENABLE)
+ {
+ CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
+ }
+ else
+ {
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
+ }
+
+ /* Set the transmit pause feature */
+ if (hfdcan->Init.TransmitPause == ENABLE)
+ {
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
+ }
+ else
+ {
+ CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
+ }
+
+ /* Set the Protocol Exception Handling */
+ if (hfdcan->Init.ProtocolException == ENABLE)
+ {
+ CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
+ }
+ else
+ {
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
+ }
+
+ /* Set FDCAN Frame Format */
+ MODIFY_REG(hfdcan->Instance->CCCR, FDCAN_FRAME_FD_BRS, hfdcan->Init.FrameFormat);
+
+ /* Reset FDCAN Operation Mode */
+ CLEAR_BIT(hfdcan->Instance->CCCR, (FDCAN_CCCR_TEST | FDCAN_CCCR_MON | FDCAN_CCCR_ASM));
+ CLEAR_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK);
+
+ /* Set FDCAN Operating Mode:
+ | Normal | Restricted | Bus | Internal | External
+ | | Operation | Monitoring | LoopBack | LoopBack
+ CCCR.TEST | 0 | 0 | 0 | 1 | 1
+ CCCR.MON | 0 | 0 | 1 | 1 | 0
+ TEST.LBCK | 0 | 0 | 0 | 1 | 1
+ CCCR.ASM | 0 | 1 | 0 | 0 | 0
+ */
+ if (hfdcan->Init.Mode == FDCAN_MODE_RESTRICTED_OPERATION)
+ {
+ /* Enable Restricted Operation mode */
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM);
+ }
+ else if (hfdcan->Init.Mode != FDCAN_MODE_NORMAL)
+ {
+ if (hfdcan->Init.Mode != FDCAN_MODE_BUS_MONITORING)
+ {
+ /* Enable write access to TEST register */
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TEST);
+
+ /* Enable LoopBack mode */
+ SET_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK);
+
+ if (hfdcan->Init.Mode == FDCAN_MODE_INTERNAL_LOOPBACK)
+ {
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
+ }
+ }
+ else
+ {
+ /* Enable bus monitoring mode */
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
+ }
+ }
+ else
+ {
+ /* Nothing to do: normal mode */
+ }
+
+ /* Set the nominal bit timing register */
+ hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \
+ (((uint32_t)hfdcan->Init.NominalTimeSeg1 - 1U) << FDCAN_NBTP_NTSEG1_Pos) | \
+ (((uint32_t)hfdcan->Init.NominalTimeSeg2 - 1U) << FDCAN_NBTP_NTSEG2_Pos) | \
+ (((uint32_t)hfdcan->Init.NominalPrescaler - 1U) << FDCAN_NBTP_NBRP_Pos));
+
+ /* If FD operation with BRS is selected, set the data bit timing register */
+ if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS)
+ {
+ hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos) | \
+ (((uint32_t)hfdcan->Init.DataTimeSeg1 - 1U) << FDCAN_DBTP_DTSEG1_Pos) | \
+ (((uint32_t)hfdcan->Init.DataTimeSeg2 - 1U) << FDCAN_DBTP_DTSEG2_Pos) | \
+ (((uint32_t)hfdcan->Init.DataPrescaler - 1U) << FDCAN_DBTP_DBRP_Pos));
+ }
+
+ /* Select between Tx FIFO and Tx Queue operation modes */
+ SET_BIT(hfdcan->Instance->TXBC, hfdcan->Init.TxFifoQueueMode);
+
+ /* Calculate each RAM block address */
+ FDCAN_CalcultateRamBlockAddresses(hfdcan);
+
+ /* Initialize the Latest Tx request buffer index */
+ hfdcan->LatestTxFifoQRequest = 0U;
+
+ /* Initialize the error code */
+ hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
+
+ /* Initialize the FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Deinitializes the FDCAN peripheral registers to their default reset values.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan)
+{
+ /* Check FDCAN handle */
+ if (hfdcan == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance));
+
+ /* Stop the FDCAN module: return value is voluntary ignored */
+ (void)HAL_FDCAN_Stop(hfdcan);
+
+ /* Disable Interrupt lines */
+ CLEAR_BIT(hfdcan->Instance->ILE, (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1));
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+ if (hfdcan->MspDeInitCallback == NULL)
+ {
+ hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware: CLOCK, NVIC */
+ hfdcan->MspDeInitCallback(hfdcan);
+#else
+ /* DeInit the low level hardware: CLOCK, NVIC */
+ HAL_FDCAN_MspDeInit(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+ /* Reset the FDCAN ErrorCode */
+ hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_RESET;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the FDCAN MSP.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval None
+ */
+__weak void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the FDCAN MSP.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval None
+ */
+__weak void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Enter FDCAN peripheral in sleep mode.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan)
+{
+ uint32_t tickstart;
+
+ /* Request clock stop */
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until FDCAN is ready for power down */
+ while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Exit power down mode.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan)
+{
+ uint32_t tickstart;
+
+ /* Reset clock stop request */
+ CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until FDCAN exits sleep mode */
+ while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
+ {
+ if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Enter normal operation */
+ CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+/**
+ * @brief Register a FDCAN CallBack.
+ * To be used instead of the weak predefined callback
+ * @param hfdcan pointer to a FDCAN_HandleTypeDef structure that contains
+ * the configuration information for FDCAN module
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_FDCAN_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty callback ID
+ * @arg @ref HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID High priority message callback ID
+ * @arg @ref HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID Timestamp wraparound callback ID
+ * @arg @ref HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID Timeout occurred callback ID
+ * @arg @ref HAL_FDCAN_ERROR_CALLBACK_CB_ID Error callback ID
+ * @arg @ref HAL_FDCAN_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_FDCAN_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID,
+ void (* pCallback)(FDCAN_HandleTypeDef *_hFDCAN))
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_FDCAN_TX_FIFO_EMPTY_CB_ID :
+ hfdcan->TxFifoEmptyCallback = pCallback;
+ break;
+
+ case HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID :
+ hfdcan->HighPriorityMessageCallback = pCallback;
+ break;
+
+ case HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID :
+ hfdcan->TimestampWraparoundCallback = pCallback;
+ break;
+
+ case HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID :
+ hfdcan->TimeoutOccurredCallback = pCallback;
+ break;
+
+ case HAL_FDCAN_ERROR_CALLBACK_CB_ID :
+ hfdcan->ErrorCallback = pCallback;
+ break;
+
+ case HAL_FDCAN_MSPINIT_CB_ID :
+ hfdcan->MspInitCallback = pCallback;
+ break;
+
+ case HAL_FDCAN_MSPDEINIT_CB_ID :
+ hfdcan->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hfdcan->State == HAL_FDCAN_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_FDCAN_MSPINIT_CB_ID :
+ hfdcan->MspInitCallback = pCallback;
+ break;
+
+ case HAL_FDCAN_MSPDEINIT_CB_ID :
+ hfdcan->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Unregister a FDCAN CallBack.
+ * FDCAN callback is redirected to the weak predefined callback
+ * @param hfdcan pointer to a FDCAN_HandleTypeDef structure that contains
+ * the configuration information for FDCAN module
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_FDCAN_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty callback ID
+ * @arg @ref HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID High priority message callback ID
+ * @arg @ref HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID Timestamp wraparound callback ID
+ * @arg @ref HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID Timeout occurred callback ID
+ * @arg @ref HAL_FDCAN_ERROR_CALLBACK_CB_ID Error callback ID
+ * @arg @ref HAL_FDCAN_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_FDCAN_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_FDCAN_TX_FIFO_EMPTY_CB_ID :
+ hfdcan->TxFifoEmptyCallback = HAL_FDCAN_TxFifoEmptyCallback;
+ break;
+
+ case HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID :
+ hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback;
+ break;
+
+ case HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID :
+ hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback;
+ break;
+
+ case HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID :
+ hfdcan->TimeoutOccurredCallback = HAL_FDCAN_TimeoutOccurredCallback;
+ break;
+
+ case HAL_FDCAN_ERROR_CALLBACK_CB_ID :
+ hfdcan->ErrorCallback = HAL_FDCAN_ErrorCallback;
+ break;
+
+ case HAL_FDCAN_MSPINIT_CB_ID :
+ hfdcan->MspInitCallback = HAL_FDCAN_MspInit;
+ break;
+
+ case HAL_FDCAN_MSPDEINIT_CB_ID :
+ hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hfdcan->State == HAL_FDCAN_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_FDCAN_MSPINIT_CB_ID :
+ hfdcan->MspInitCallback = HAL_FDCAN_MspInit;
+ break;
+
+ case HAL_FDCAN_MSPDEINIT_CB_ID :
+ hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Register Tx Event Fifo FDCAN Callback
+ * To be used instead of the weak HAL_FDCAN_TxEventFifoCallback() predefined callback
+ * @param hfdcan FDCAN handle
+ * @param pCallback pointer to the Tx Event Fifo Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan,
+ pFDCAN_TxEventFifoCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ hfdcan->TxEventFifoCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief UnRegister the Tx Event Fifo FDCAN Callback
+ * Tx Event Fifo FDCAN Callback is redirected to the weak HAL_FDCAN_TxEventFifoCallback() predefined callback
+ * @param hfdcan FDCAN handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ hfdcan->TxEventFifoCallback = HAL_FDCAN_TxEventFifoCallback; /* Legacy weak TxEventFifoCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Register Rx Fifo 0 FDCAN Callback
+ * To be used instead of the weak HAL_FDCAN_RxFifo0Callback() predefined callback
+ * @param hfdcan FDCAN handle
+ * @param pCallback pointer to the Rx Fifo 0 Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan,
+ pFDCAN_RxFifo0CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ hfdcan->RxFifo0Callback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief UnRegister the Rx Fifo 0 FDCAN Callback
+ * Rx Fifo 0 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo0Callback() predefined callback
+ * @param hfdcan FDCAN handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ hfdcan->RxFifo0Callback = HAL_FDCAN_RxFifo0Callback; /* Legacy weak RxFifo0Callback */
+ }
+ else
+ {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Register Rx Fifo 1 FDCAN Callback
+ * To be used instead of the weak HAL_FDCAN_RxFifo1Callback() predefined callback
+ * @param hfdcan FDCAN handle
+ * @param pCallback pointer to the Rx Fifo 1 Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan,
+ pFDCAN_RxFifo1CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ hfdcan->RxFifo1Callback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief UnRegister the Rx Fifo 1 FDCAN Callback
+ * Rx Fifo 1 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo1Callback() predefined callback
+ * @param hfdcan FDCAN handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ hfdcan->RxFifo1Callback = HAL_FDCAN_RxFifo1Callback; /* Legacy weak RxFifo1Callback */
+ }
+ else
+ {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Register Tx Buffer Complete FDCAN Callback
+ * To be used instead of the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback
+ * @param hfdcan FDCAN handle
+ * @param pCallback pointer to the Tx Buffer Complete Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan,
+ pFDCAN_TxBufferCompleteCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ hfdcan->TxBufferCompleteCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief UnRegister the Tx Buffer Complete FDCAN Callback
+ * Tx Buffer Complete FDCAN Callback is redirected to
+ * the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback
+ * @param hfdcan FDCAN handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ hfdcan->TxBufferCompleteCallback = HAL_FDCAN_TxBufferCompleteCallback; /* Legacy weak TxBufferCompleteCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Register Tx Buffer Abort FDCAN Callback
+ * To be used instead of the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback
+ * @param hfdcan FDCAN handle
+ * @param pCallback pointer to the Tx Buffer Abort Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan,
+ pFDCAN_TxBufferAbortCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ hfdcan->TxBufferAbortCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief UnRegister the Tx Buffer Abort FDCAN Callback
+ * Tx Buffer Abort FDCAN Callback is redirected to
+ * the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback
+ * @param hfdcan FDCAN handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ hfdcan->TxBufferAbortCallback = HAL_FDCAN_TxBufferAbortCallback; /* Legacy weak TxBufferAbortCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Register Error Status FDCAN Callback
+ * To be used instead of the weak HAL_FDCAN_ErrorStatusCallback() predefined callback
+ * @param hfdcan FDCAN handle
+ * @param pCallback pointer to the Error Status Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan,
+ pFDCAN_ErrorStatusCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ hfdcan->ErrorStatusCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief UnRegister the Error Status FDCAN Callback
+ * Error Status FDCAN Callback is redirected to the weak HAL_FDCAN_ErrorStatusCallback() predefined callback
+ * @param hfdcan FDCAN handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ hfdcan->ErrorStatusCallback = HAL_FDCAN_ErrorStatusCallback; /* Legacy weak ErrorStatusCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Exported_Functions_Group2 Configuration functions
+ * @brief FDCAN Configuration functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Configuration functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) HAL_FDCAN_ConfigFilter : Configure the FDCAN reception filters
+ (+) HAL_FDCAN_ConfigGlobalFilter : Configure the FDCAN global filter
+ (+) HAL_FDCAN_ConfigExtendedIdMask : Configure the extended ID mask
+ (+) HAL_FDCAN_ConfigRxFifoOverwrite : Configure the Rx FIFO operation mode
+ (+) HAL_FDCAN_ConfigRamWatchdog : Configure the RAM watchdog
+ (+) HAL_FDCAN_ConfigTimestampCounter : Configure the timestamp counter
+ (+) HAL_FDCAN_EnableTimestampCounter : Enable the timestamp counter
+ (+) HAL_FDCAN_DisableTimestampCounter : Disable the timestamp counter
+ (+) HAL_FDCAN_GetTimestampCounter : Get the timestamp counter value
+ (+) HAL_FDCAN_ResetTimestampCounter : Reset the timestamp counter to zero
+ (+) HAL_FDCAN_ConfigTimeoutCounter : Configure the timeout counter
+ (+) HAL_FDCAN_EnableTimeoutCounter : Enable the timeout counter
+ (+) HAL_FDCAN_DisableTimeoutCounter : Disable the timeout counter
+ (+) HAL_FDCAN_GetTimeoutCounter : Get the timeout counter value
+ (+) HAL_FDCAN_ResetTimeoutCounter : Reset the timeout counter to its start value
+ (+) HAL_FDCAN_ConfigTxDelayCompensation : Configure the transmitter delay compensation
+ (+) HAL_FDCAN_EnableTxDelayCompensation : Enable the transmitter delay compensation
+ (+) HAL_FDCAN_DisableTxDelayCompensation : Disable the transmitter delay compensation
+ (+) HAL_FDCAN_EnableISOMode : Enable ISO 11898-1 protocol mode
+ (+) HAL_FDCAN_DisableISOMode : Disable ISO 11898-1 protocol mode
+ (+) HAL_FDCAN_EnableEdgeFiltering : Enable edge filtering during bus integration
+ (+) HAL_FDCAN_DisableEdgeFiltering : Disable edge filtering during bus integration
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the FDCAN reception filter according to the specified
+ * parameters in the FDCAN_FilterTypeDef structure.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param sFilterConfig pointer to an FDCAN_FilterTypeDef structure that
+ * contains the filter configuration information
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig)
+{
+ uint32_t FilterElementW1;
+ uint32_t FilterElementW2;
+ uint32_t *FilterAddress;
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+ if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+ {
+ /* Check function parameters */
+ assert_param(IS_FDCAN_ID_TYPE(sFilterConfig->IdType));
+ assert_param(IS_FDCAN_FILTER_CFG(sFilterConfig->FilterConfig));
+
+ if (sFilterConfig->IdType == FDCAN_STANDARD_ID)
+ {
+ /* Check function parameters */
+ assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.StdFiltersNbr - 1U)));
+ assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x7FFU));
+ assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x7FFU));
+ assert_param(IS_FDCAN_STD_FILTER_TYPE(sFilterConfig->FilterType));
+
+ /* Build filter element */
+ FilterElementW1 = ((sFilterConfig->FilterType << 30U) |
+ (sFilterConfig->FilterConfig << 27U) |
+ (sFilterConfig->FilterID1 << 16U) |
+ sFilterConfig->FilterID2);
+
+ /* Calculate filter address */
+ FilterAddress = (uint32_t *)(hfdcan->msgRam.StandardFilterSA + (sFilterConfig->FilterIndex * SRAMCAN_FLS_SIZE));
+
+ /* Write filter element to the message RAM */
+ *FilterAddress = FilterElementW1;
+ }
+ else /* sFilterConfig->IdType == FDCAN_EXTENDED_ID */
+ {
+ /* Check function parameters */
+ assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.ExtFiltersNbr - 1U)));
+ assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x1FFFFFFFU));
+ assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x1FFFFFFFU));
+ assert_param(IS_FDCAN_EXT_FILTER_TYPE(sFilterConfig->FilterType));
+
+ /* Build first word of filter element */
+ FilterElementW1 = ((sFilterConfig->FilterConfig << 29U) | sFilterConfig->FilterID1);
+
+ /* Build second word of filter element */
+ FilterElementW2 = ((sFilterConfig->FilterType << 30U) | sFilterConfig->FilterID2);
+
+ /* Calculate filter address */
+ FilterAddress = (uint32_t *)(hfdcan->msgRam.ExtendedFilterSA + (sFilterConfig->FilterIndex * SRAMCAN_FLE_SIZE));
+
+ /* Write filter element to the message RAM */
+ *FilterAddress = FilterElementW1;
+ FilterAddress++;
+ *FilterAddress = FilterElementW2;
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configure the FDCAN global filter.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param NonMatchingStd Defines how received messages with 11-bit IDs that
+ * do not match any element of the filter list are treated.
+ * This parameter can be a value of @arg FDCAN_Non_Matching_Frames.
+ * @param NonMatchingExt Defines how received messages with 29-bit IDs that
+ * do not match any element of the filter list are treated.
+ * This parameter can be a value of @arg FDCAN_Non_Matching_Frames.
+ * @param RejectRemoteStd Filter or reject all the remote 11-bit IDs frames.
+ * This parameter can be a value of @arg FDCAN_Reject_Remote_Frames.
+ * @param RejectRemoteExt Filter or reject all the remote 29-bit IDs frames.
+ * This parameter can be a value of @arg FDCAN_Reject_Remote_Frames.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan,
+ uint32_t NonMatchingStd,
+ uint32_t NonMatchingExt,
+ uint32_t RejectRemoteStd,
+ uint32_t RejectRemoteExt)
+{
+ /* Check function parameters */
+ assert_param(IS_FDCAN_NON_MATCHING(NonMatchingStd));
+ assert_param(IS_FDCAN_NON_MATCHING(NonMatchingExt));
+ assert_param(IS_FDCAN_REJECT_REMOTE(RejectRemoteStd));
+ assert_param(IS_FDCAN_REJECT_REMOTE(RejectRemoteExt));
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ /* Configure global filter */
+ MODIFY_REG(hfdcan->Instance->RXGFC, (FDCAN_RXGFC_ANFS |
+ FDCAN_RXGFC_ANFE |
+ FDCAN_RXGFC_RRFS |
+ FDCAN_RXGFC_RRFE),
+ ((NonMatchingStd << FDCAN_RXGFC_ANFS_Pos) |
+ (NonMatchingExt << FDCAN_RXGFC_ANFE_Pos) |
+ (RejectRemoteStd << FDCAN_RXGFC_RRFS_Pos) |
+ (RejectRemoteExt << FDCAN_RXGFC_RRFE_Pos)));
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configure the extended ID mask.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param Mask Extended ID Mask.
+ This parameter must be a number between 0 and 0x1FFFFFFF
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask)
+{
+ /* Check function parameters */
+ assert_param(IS_FDCAN_MAX_VALUE(Mask, 0x1FFFFFFFU));
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ /* Configure the extended ID mask */
+ hfdcan->Instance->XIDAM = Mask;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configure the Rx FIFO operation mode.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param RxFifo Rx FIFO.
+ * This parameter can be one of the following values:
+ * @arg FDCAN_RX_FIFO0: Rx FIFO 0
+ * @arg FDCAN_RX_FIFO1: Rx FIFO 1
+ * @param OperationMode operation mode.
+ * This parameter can be a value of @arg FDCAN_Rx_FIFO_operation_mode.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode)
+{
+ /* Check function parameters */
+ assert_param(IS_FDCAN_RX_FIFO(RxFifo));
+ assert_param(IS_FDCAN_RX_FIFO_MODE(OperationMode));
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ if (RxFifo == FDCAN_RX_FIFO0)
+ {
+ /* Select FIFO 0 Operation Mode */
+ MODIFY_REG(hfdcan->Instance->RXGFC, FDCAN_RXGFC_F0OM, (OperationMode << FDCAN_RXGFC_F0OM_Pos));
+ }
+ else /* RxFifo == FDCAN_RX_FIFO1 */
+ {
+ /* Select FIFO 1 Operation Mode */
+ MODIFY_REG(hfdcan->Instance->RXGFC, FDCAN_RXGFC_F1OM, (OperationMode << FDCAN_RXGFC_F1OM_Pos));
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configure the RAM watchdog.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param CounterStartValue Start value of the Message RAM Watchdog Counter,
+ * This parameter must be a number between 0x00 and 0xFF,
+ * with the reset value of 0x00 the counter is disabled.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue)
+{
+ /* Check function parameters */
+ assert_param(IS_FDCAN_MAX_VALUE(CounterStartValue, 0xFFU));
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ /* Configure the RAM watchdog counter start value */
+ MODIFY_REG(hfdcan->Instance->RWD, FDCAN_RWD_WDC, CounterStartValue);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configure the timestamp counter.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param TimestampPrescaler Timestamp Counter Prescaler.
+ * This parameter can be a value of @arg FDCAN_Timestamp_Prescaler.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler)
+{
+ /* Check function parameters */
+ assert_param(IS_FDCAN_TIMESTAMP_PRESCALER(TimestampPrescaler));
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ /* Configure prescaler */
+ MODIFY_REG(hfdcan->Instance->TSCC, FDCAN_TSCC_TCP, TimestampPrescaler);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Enable the timestamp counter.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param TimestampOperation Timestamp counter operation.
+ * This parameter can be a value of @arg FDCAN_Timestamp.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation)
+{
+ /* Check function parameters */
+ assert_param(IS_FDCAN_TIMESTAMP(TimestampOperation));
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ /* Enable timestamp counter */
+ MODIFY_REG(hfdcan->Instance->TSCC, FDCAN_TSCC_TSS, TimestampOperation);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Disable the timestamp counter.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ /* Disable timestamp counter */
+ CLEAR_BIT(hfdcan->Instance->TSCC, FDCAN_TSCC_TSS);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Get the timestamp counter value.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval Timestamp counter value
+ */
+uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+ return (uint16_t)(hfdcan->Instance->TSCV);
+}
+
+/**
+ * @brief Reset the timestamp counter to zero.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+ if ((hfdcan->Instance->TSCC & FDCAN_TSCC_TSS) != FDCAN_TIMESTAMP_EXTERNAL)
+ {
+ /* Reset timestamp counter.
+ Actually any write operation to TSCV clears the counter */
+ CLEAR_REG(hfdcan->Instance->TSCV);
+ }
+ else
+ {
+ /* Update error code.
+ Unable to reset external counter */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+ return HAL_ERROR;
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the timeout counter.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param TimeoutOperation Timeout counter operation.
+ * This parameter can be a value of @arg FDCAN_Timeout_Operation.
+ * @param TimeoutPeriod Start value of the timeout down-counter.
+ * This parameter must be a number between 0x0000 and 0xFFFF
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation,
+ uint32_t TimeoutPeriod)
+{
+ /* Check function parameters */
+ assert_param(IS_FDCAN_TIMEOUT(TimeoutOperation));
+ assert_param(IS_FDCAN_MAX_VALUE(TimeoutPeriod, 0xFFFFU));
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ /* Select timeout operation and configure period */
+ MODIFY_REG(hfdcan->Instance->TOCC,
+ (FDCAN_TOCC_TOS | FDCAN_TOCC_TOP), (TimeoutOperation | (TimeoutPeriod << FDCAN_TOCC_TOP_Pos)));
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Enable the timeout counter.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ /* Enable timeout counter */
+ SET_BIT(hfdcan->Instance->TOCC, FDCAN_TOCC_ETOC);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Disable the timeout counter.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ /* Disable timeout counter */
+ CLEAR_BIT(hfdcan->Instance->TOCC, FDCAN_TOCC_ETOC);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Get the timeout counter value.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval Timeout counter value
+ */
+uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+ return (uint16_t)(hfdcan->Instance->TOCV);
+}
+
+/**
+ * @brief Reset the timeout counter to its start value.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+ if ((hfdcan->Instance->TOCC & FDCAN_TOCC_TOS) == FDCAN_TIMEOUT_CONTINUOUS)
+ {
+ /* Reset timeout counter to start value */
+ CLEAR_REG(hfdcan->Instance->TOCV);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code.
+ Unable to reset counter: controlled only by FIFO empty state */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configure the transmitter delay compensation.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param TdcOffset Transmitter Delay Compensation Offset.
+ * This parameter must be a number between 0x00 and 0x7F.
+ * @param TdcFilter Transmitter Delay Compensation Filter Window Length.
+ * This parameter must be a number between 0x00 and 0x7F.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset,
+ uint32_t TdcFilter)
+{
+ /* Check function parameters */
+ assert_param(IS_FDCAN_MAX_VALUE(TdcOffset, 0x7FU));
+ assert_param(IS_FDCAN_MAX_VALUE(TdcFilter, 0x7FU));
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ /* Configure TDC offset and filter window */
+ hfdcan->Instance->TDCR = ((TdcFilter << FDCAN_TDCR_TDCF_Pos) | (TdcOffset << FDCAN_TDCR_TDCO_Pos));
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Enable the transmitter delay compensation.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan)
+{
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ /* Enable transmitter delay compensation */
+ SET_BIT(hfdcan->Instance->DBTP, FDCAN_DBTP_TDC);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Disable the transmitter delay compensation.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan)
+{
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ /* Disable transmitter delay compensation */
+ CLEAR_BIT(hfdcan->Instance->DBTP, FDCAN_DBTP_TDC);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Enable ISO 11898-1 protocol mode.
+ * CAN FD frame format is according to ISO 11898-1 standard.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan)
+{
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ /* Disable Non ISO protocol mode */
+ CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_NISO);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Disable ISO 11898-1 protocol mode.
+ * CAN FD frame format is according to Bosch CAN FD specification V1.0.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan)
+{
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ /* Enable Non ISO protocol mode */
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_NISO);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Enable edge filtering during bus integration.
+ * Two consecutive dominant tq are required to detect an edge for hard synchronization.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan)
+{
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ /* Enable edge filtering */
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_EFBI);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Disable edge filtering during bus integration.
+ * One dominant tq is required to detect an edge for hard synchronization.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan)
+{
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ /* Disable edge filtering */
+ CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_EFBI);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Exported_Functions_Group3 Control functions
+ * @brief Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Control functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) HAL_FDCAN_Start : Start the FDCAN module
+ (+) HAL_FDCAN_Stop : Stop the FDCAN module and enable access to configuration registers
+ (+) HAL_FDCAN_AddMessageToTxFifoQ : Add a message to the Tx FIFO/Queue and activate the corresponding
+ transmission request
+ (+) HAL_FDCAN_GetLatestTxFifoQRequestBuffer : Get Tx buffer index of latest Tx FIFO/Queue request
+ (+) HAL_FDCAN_AbortTxRequest : Abort transmission request
+ (+) HAL_FDCAN_GetRxMessage : Get an FDCAN frame from the Rx FIFO zone into the message RAM
+ (+) HAL_FDCAN_GetTxEvent : Get an FDCAN Tx event from the Tx Event FIFO zone
+ into the message RAM
+ (+) HAL_FDCAN_GetHighPriorityMessageStatus : Get high priority message status
+ (+) HAL_FDCAN_GetProtocolStatus : Get protocol status
+ (+) HAL_FDCAN_GetErrorCounters : Get error counter values
+ (+) HAL_FDCAN_IsTxBufferMessagePending : Check if a transmission request is pending
+ on the selected Tx buffer
+ (+) HAL_FDCAN_GetRxFifoFillLevel : Return Rx FIFO fill level
+ (+) HAL_FDCAN_GetTxFifoFreeLevel : Return Tx FIFO free level
+ (+) HAL_FDCAN_IsRestrictedOperationMode : Check if the FDCAN peripheral entered Restricted Operation Mode
+ (+) HAL_FDCAN_ExitRestrictedOperationMode : Exit Restricted Operation Mode
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start the FDCAN module.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan)
+{
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ /* Change FDCAN peripheral state */
+ hfdcan->State = HAL_FDCAN_STATE_BUSY;
+
+ /* Request leave initialisation */
+ CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
+
+ /* Reset the FDCAN ErrorCode */
+ hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Stop the FDCAN module and enable access to configuration registers.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan)
+{
+ uint32_t Counter = 0U;
+
+ if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
+ {
+ /* Request initialisation */
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
+
+ /* Wait until the INIT bit into CCCR register is set */
+ while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U)
+ {
+ /* Check for the Timeout */
+ if (Counter > FDCAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+
+ /* Increment counter */
+ Counter++;
+ }
+
+ /* Reset counter */
+ Counter = 0U;
+
+ /* Exit from Sleep mode */
+ CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
+
+ /* Wait until FDCAN exits sleep mode */
+ while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
+ {
+ /* Check for the Timeout */
+ if (Counter > FDCAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+
+ /* Increment counter */
+ Counter++;
+ }
+
+ /* Enable configuration change */
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE);
+
+ /* Reset Latest Tx FIFO/Queue Request Buffer Index */
+ hfdcan->LatestTxFifoQRequest = 0U;
+
+ /* Change FDCAN peripheral state */
+ hfdcan->State = HAL_FDCAN_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Add a message to the Tx FIFO/Queue and activate the corresponding transmission request
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure.
+ * @param pTxData pointer to a buffer containing the payload of the Tx frame.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader,
+ uint8_t *pTxData)
+{
+ uint32_t PutIndex;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_ID_TYPE(pTxHeader->IdType));
+ if (pTxHeader->IdType == FDCAN_STANDARD_ID)
+ {
+ assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x7FFU));
+ }
+ else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
+ {
+ assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x1FFFFFFFU));
+ }
+ assert_param(IS_FDCAN_FRAME_TYPE(pTxHeader->TxFrameType));
+ assert_param(IS_FDCAN_DLC(pTxHeader->DataLength));
+ assert_param(IS_FDCAN_ESI(pTxHeader->ErrorStateIndicator));
+ assert_param(IS_FDCAN_BRS(pTxHeader->BitRateSwitch));
+ assert_param(IS_FDCAN_FDF(pTxHeader->FDFormat));
+ assert_param(IS_FDCAN_EFC(pTxHeader->TxEventFifoControl));
+ assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->MessageMarker, 0xFFU));
+
+ if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
+ {
+ /* Check that the Tx FIFO/Queue is not full */
+ if ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQF) != 0U)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_FULL;
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Retrieve the Tx FIFO PutIndex */
+ PutIndex = ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQPI) >> FDCAN_TXFQS_TFQPI_Pos);
+
+ /* Add the message to the Tx FIFO/Queue */
+ FDCAN_CopyMessageToRAM(hfdcan, pTxHeader, pTxData, PutIndex);
+
+ /* Activate the corresponding transmission request */
+ hfdcan->Instance->TXBAR = ((uint32_t)1 << PutIndex);
+
+ /* Store the Latest Tx FIFO/Queue Request Buffer Index */
+ hfdcan->LatestTxFifoQRequest = ((uint32_t)1 << PutIndex);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Get Tx buffer index of latest Tx FIFO/Queue request
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval Tx buffer index of last Tx FIFO/Queue request
+ * - Any value of @arg FDCAN_Tx_location if Tx request has been submitted.
+ * - 0 if no Tx FIFO/Queue request have been submitted.
+ */
+uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan)
+{
+ /* Return Last Tx FIFO/Queue Request Buffer */
+ return hfdcan->LatestTxFifoQRequest;
+}
+
+/**
+ * @brief Abort transmission request
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param BufferIndex buffer index.
+ * This parameter can be any combination of @arg FDCAN_Tx_location.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
+{
+ /* Check function parameters */
+ assert_param(IS_FDCAN_TX_LOCATION_LIST(BufferIndex));
+
+ if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
+ {
+ /* Add cancellation request */
+ hfdcan->Instance->TXBCR = BufferIndex;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Get an FDCAN frame from the Rx FIFO zone into the message RAM.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param RxLocation Location of the received message to be read.
+ * This parameter can be a value of @arg FDCAN_Rx_location.
+ * @param pRxHeader pointer to a FDCAN_RxHeaderTypeDef structure.
+ * @param pRxData pointer to a buffer where the payload of the Rx frame will be stored.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation,
+ FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData)
+{
+ uint32_t *RxAddress;
+ uint8_t *pData;
+ uint32_t ByteCounter;
+ uint32_t GetIndex;
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_RX_FIFO(RxLocation));
+
+ if (state == HAL_FDCAN_STATE_BUSY)
+ {
+ if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */
+ {
+ /* Check that the Rx FIFO 0 is not empty */
+ if ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL) == 0U)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Calculate Rx FIFO 0 element address */
+ GetIndex = ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos);
+ RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO0SA + (GetIndex * SRAMCAN_RF0_SIZE));
+ }
+ }
+ else /* Rx element is assigned to the Rx FIFO 1 */
+ {
+ /* Check that the Rx FIFO 1 is not empty */
+ if ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL) == 0U)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Calculate Rx FIFO 1 element address */
+ GetIndex = ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos);
+ RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO1SA + (GetIndex * SRAMCAN_RF1_SIZE));
+ }
+ }
+
+ /* Retrieve IdType */
+ pRxHeader->IdType = *RxAddress & FDCAN_ELEMENT_MASK_XTD;
+
+ /* Retrieve Identifier */
+ if (pRxHeader->IdType == FDCAN_STANDARD_ID) /* Standard ID element */
+ {
+ pRxHeader->Identifier = ((*RxAddress & FDCAN_ELEMENT_MASK_STDID) >> 18U);
+ }
+ else /* Extended ID element */
+ {
+ pRxHeader->Identifier = (*RxAddress & FDCAN_ELEMENT_MASK_EXTID);
+ }
+
+ /* Retrieve RxFrameType */
+ pRxHeader->RxFrameType = (*RxAddress & FDCAN_ELEMENT_MASK_RTR);
+
+ /* Retrieve ErrorStateIndicator */
+ pRxHeader->ErrorStateIndicator = (*RxAddress & FDCAN_ELEMENT_MASK_ESI);
+
+ /* Increment RxAddress pointer to second word of Rx FIFO element */
+ RxAddress++;
+
+ /* Retrieve RxTimestamp */
+ pRxHeader->RxTimestamp = (*RxAddress & FDCAN_ELEMENT_MASK_TS);
+
+ /* Retrieve DataLength */
+ pRxHeader->DataLength = (*RxAddress & FDCAN_ELEMENT_MASK_DLC);
+
+ /* Retrieve BitRateSwitch */
+ pRxHeader->BitRateSwitch = (*RxAddress & FDCAN_ELEMENT_MASK_BRS);
+
+ /* Retrieve FDFormat */
+ pRxHeader->FDFormat = (*RxAddress & FDCAN_ELEMENT_MASK_FDF);
+
+ /* Retrieve FilterIndex */
+ pRxHeader->FilterIndex = ((*RxAddress & FDCAN_ELEMENT_MASK_FIDX) >> 24U);
+
+ /* Retrieve NonMatchingFrame */
+ pRxHeader->IsFilterMatchingFrame = ((*RxAddress & FDCAN_ELEMENT_MASK_ANMF) >> 31U);
+
+ /* Increment RxAddress pointer to payload of Rx FIFO element */
+ RxAddress++;
+
+ /* Retrieve Rx payload */
+ pData = (uint8_t *)RxAddress;
+ for (ByteCounter = 0; ByteCounter < DLCtoBytes[pRxHeader->DataLength >> 16U]; ByteCounter++)
+ {
+ pRxData[ByteCounter] = pData[ByteCounter];
+ }
+
+ if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */
+ {
+ /* Acknowledge the Rx FIFO 0 that the oldest element is read so that it increments the GetIndex */
+ hfdcan->Instance->RXF0A = GetIndex;
+ }
+ else /* Rx element is assigned to the Rx FIFO 1 */
+ {
+ /* Acknowledge the Rx FIFO 1 that the oldest element is read so that it increments the GetIndex */
+ hfdcan->Instance->RXF1A = GetIndex;
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param pTxEvent pointer to a FDCAN_TxEventFifoTypeDef structure.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent)
+{
+ uint32_t *TxEventAddress;
+ uint32_t GetIndex;
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+ if (state == HAL_FDCAN_STATE_BUSY)
+ {
+ /* Check that the Tx event FIFO is not empty */
+ if ((hfdcan->Instance->TXEFS & FDCAN_TXEFS_EFFL) == 0U)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
+
+ return HAL_ERROR;
+ }
+
+ /* Calculate Tx event FIFO element address */
+ GetIndex = ((hfdcan->Instance->TXEFS & FDCAN_TXEFS_EFGI) >> FDCAN_TXEFS_EFGI_Pos);
+ TxEventAddress = (uint32_t *)(hfdcan->msgRam.TxEventFIFOSA + (GetIndex * SRAMCAN_TEF_SIZE));
+
+ /* Retrieve IdType */
+ pTxEvent->IdType = *TxEventAddress & FDCAN_ELEMENT_MASK_XTD;
+
+ /* Retrieve Identifier */
+ if (pTxEvent->IdType == FDCAN_STANDARD_ID) /* Standard ID element */
+ {
+ pTxEvent->Identifier = ((*TxEventAddress & FDCAN_ELEMENT_MASK_STDID) >> 18U);
+ }
+ else /* Extended ID element */
+ {
+ pTxEvent->Identifier = (*TxEventAddress & FDCAN_ELEMENT_MASK_EXTID);
+ }
+
+ /* Retrieve TxFrameType */
+ pTxEvent->TxFrameType = (*TxEventAddress & FDCAN_ELEMENT_MASK_RTR);
+
+ /* Retrieve ErrorStateIndicator */
+ pTxEvent->ErrorStateIndicator = (*TxEventAddress & FDCAN_ELEMENT_MASK_ESI);
+
+ /* Increment TxEventAddress pointer to second word of Tx Event FIFO element */
+ TxEventAddress++;
+
+ /* Retrieve TxTimestamp */
+ pTxEvent->TxTimestamp = (*TxEventAddress & FDCAN_ELEMENT_MASK_TS);
+
+ /* Retrieve DataLength */
+ pTxEvent->DataLength = (*TxEventAddress & FDCAN_ELEMENT_MASK_DLC);
+
+ /* Retrieve BitRateSwitch */
+ pTxEvent->BitRateSwitch = (*TxEventAddress & FDCAN_ELEMENT_MASK_BRS);
+
+ /* Retrieve FDFormat */
+ pTxEvent->FDFormat = (*TxEventAddress & FDCAN_ELEMENT_MASK_FDF);
+
+ /* Retrieve EventType */
+ pTxEvent->EventType = (*TxEventAddress & FDCAN_ELEMENT_MASK_ET);
+
+ /* Retrieve MessageMarker */
+ pTxEvent->MessageMarker = ((*TxEventAddress & FDCAN_ELEMENT_MASK_MM) >> 24U);
+
+ /* Acknowledge the Tx Event FIFO that the oldest element is read so that it increments the GetIndex */
+ hfdcan->Instance->TXEFA = GetIndex;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Get high priority message status.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param HpMsgStatus pointer to an FDCAN_HpMsgStatusTypeDef structure.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan,
+ FDCAN_HpMsgStatusTypeDef *HpMsgStatus)
+{
+ HpMsgStatus->FilterList = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FLST) >> FDCAN_HPMS_FLST_Pos);
+ HpMsgStatus->FilterIndex = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FIDX) >> FDCAN_HPMS_FIDX_Pos);
+ HpMsgStatus->MessageStorage = (hfdcan->Instance->HPMS & FDCAN_HPMS_MSI);
+ HpMsgStatus->MessageIndex = (hfdcan->Instance->HPMS & FDCAN_HPMS_BIDX);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Get protocol status.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param ProtocolStatus pointer to an FDCAN_ProtocolStatusTypeDef structure.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus)
+{
+ uint32_t StatusReg;
+
+ /* Read the protocol status register */
+ StatusReg = READ_REG(hfdcan->Instance->PSR);
+
+ /* Fill the protocol status structure */
+ ProtocolStatus->LastErrorCode = (StatusReg & FDCAN_PSR_LEC);
+ ProtocolStatus->DataLastErrorCode = ((StatusReg & FDCAN_PSR_DLEC) >> FDCAN_PSR_DLEC_Pos);
+ ProtocolStatus->Activity = (StatusReg & FDCAN_PSR_ACT);
+ ProtocolStatus->ErrorPassive = ((StatusReg & FDCAN_PSR_EP) >> FDCAN_PSR_EP_Pos);
+ ProtocolStatus->Warning = ((StatusReg & FDCAN_PSR_EW) >> FDCAN_PSR_EW_Pos);
+ ProtocolStatus->BusOff = ((StatusReg & FDCAN_PSR_BO) >> FDCAN_PSR_BO_Pos);
+ ProtocolStatus->RxESIflag = ((StatusReg & FDCAN_PSR_RESI) >> FDCAN_PSR_RESI_Pos);
+ ProtocolStatus->RxBRSflag = ((StatusReg & FDCAN_PSR_RBRS) >> FDCAN_PSR_RBRS_Pos);
+ ProtocolStatus->RxFDFflag = ((StatusReg & FDCAN_PSR_REDL) >> FDCAN_PSR_REDL_Pos);
+ ProtocolStatus->ProtocolException = ((StatusReg & FDCAN_PSR_PXE) >> FDCAN_PSR_PXE_Pos);
+ ProtocolStatus->TDCvalue = ((StatusReg & FDCAN_PSR_TDCV) >> FDCAN_PSR_TDCV_Pos);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Get error counter values.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param ErrorCounters pointer to an FDCAN_ErrorCountersTypeDef structure.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters)
+{
+ uint32_t CountersReg;
+
+ /* Read the error counters register */
+ CountersReg = READ_REG(hfdcan->Instance->ECR);
+
+ /* Fill the error counters structure */
+ ErrorCounters->TxErrorCnt = ((CountersReg & FDCAN_ECR_TEC) >> FDCAN_ECR_TEC_Pos);
+ ErrorCounters->RxErrorCnt = ((CountersReg & FDCAN_ECR_REC) >> FDCAN_ECR_REC_Pos);
+ ErrorCounters->RxErrorPassive = ((CountersReg & FDCAN_ECR_RP) >> FDCAN_ECR_RP_Pos);
+ ErrorCounters->ErrorLogging = ((CountersReg & FDCAN_ECR_CEL) >> FDCAN_ECR_CEL_Pos);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Check if a transmission request is pending on the selected Tx buffer.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param TxBufferIndex Tx buffer index.
+ * This parameter can be any combination of @arg FDCAN_Tx_location.
+ * @retval Status
+ * - 0 : No pending transmission request on TxBufferIndex list
+ * - 1 : Pending transmission request on TxBufferIndex.
+ */
+uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex)
+{
+ /* Check function parameters */
+ assert_param(IS_FDCAN_TX_LOCATION_LIST(TxBufferIndex));
+
+ /* Check pending transmission request on the selected buffer */
+ if ((hfdcan->Instance->TXBRP & TxBufferIndex) == 0U)
+ {
+ return 0;
+ }
+ return 1;
+}
+
+/**
+ * @brief Return Rx FIFO fill level.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param RxFifo Rx FIFO.
+ * This parameter can be one of the following values:
+ * @arg FDCAN_RX_FIFO0: Rx FIFO 0
+ * @arg FDCAN_RX_FIFO1: Rx FIFO 1
+ * @retval Rx FIFO fill level.
+ */
+uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo)
+{
+ uint32_t FillLevel;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_RX_FIFO(RxFifo));
+
+ if (RxFifo == FDCAN_RX_FIFO0)
+ {
+ FillLevel = hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL;
+ }
+ else /* RxFifo == FDCAN_RX_FIFO1 */
+ {
+ FillLevel = hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL;
+ }
+
+ /* Return Rx FIFO fill level */
+ return FillLevel;
+}
+
+/**
+ * @brief Return Tx FIFO free level: number of consecutive free Tx FIFO
+ * elements starting from Tx FIFO GetIndex.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval Tx FIFO free level.
+ */
+uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan)
+{
+ uint32_t FreeLevel;
+
+ FreeLevel = hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFFL;
+
+ /* Return Tx FIFO free level */
+ return FreeLevel;
+}
+
+/**
+ * @brief Check if the FDCAN peripheral entered Restricted Operation Mode.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval Status
+ * - 0 : Normal FDCAN operation.
+ * - 1 : Restricted Operation Mode active.
+ */
+uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan)
+{
+ uint32_t OperationMode;
+
+ /* Get Operation Mode */
+ OperationMode = ((hfdcan->Instance->CCCR & FDCAN_CCCR_ASM) >> FDCAN_CCCR_ASM_Pos);
+
+ return OperationMode;
+}
+
+/**
+ * @brief Exit Restricted Operation Mode.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan)
+{
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+ if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+ {
+ /* Exit Restricted Operation mode */
+ CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Exported_Functions_Group4 Interrupts management
+ * @brief Interrupts management
+ *
+@verbatim
+ ==============================================================================
+ ##### Interrupts management #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) HAL_FDCAN_ConfigInterruptLines : Assign interrupts to either Interrupt line 0 or 1
+ (+) HAL_FDCAN_ActivateNotification : Enable interrupts
+ (+) HAL_FDCAN_DeactivateNotification : Disable interrupts
+ (+) HAL_FDCAN_IRQHandler : Handles FDCAN interrupt request
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Assign interrupts to either Interrupt line 0 or 1.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param ITList indicates which interrupts group will be assigned to the selected interrupt line.
+ * This parameter can be any combination of @arg FDCAN_Interrupts_Group.
+ * @param InterruptLine Interrupt line.
+ * This parameter can be a value of @arg FDCAN_Interrupt_Line.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine)
+{
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_IT_GROUP(ITList));
+ assert_param(IS_FDCAN_IT_LINE(InterruptLine));
+
+ if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+ {
+ /* Assign list of interrupts to the selected line */
+ if (InterruptLine == FDCAN_INTERRUPT_LINE0)
+ {
+ CLEAR_BIT(hfdcan->Instance->ILS, ITList);
+ }
+ else /* InterruptLine == FDCAN_INTERRUPT_LINE1 */
+ {
+ SET_BIT(hfdcan->Instance->ILS, ITList);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Enable interrupts.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param ActiveITs indicates which interrupts will be enabled.
+ * This parameter can be any combination of @arg FDCAN_Interrupts.
+ * @param BufferIndexes Tx Buffer Indexes.
+ * This parameter can be any combination of @arg FDCAN_Tx_location.
+ * This parameter is ignored if ActiveITs does not include one of the following:
+ * - FDCAN_IT_TX_COMPLETE
+ * - FDCAN_IT_TX_ABORT_COMPLETE
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs,
+ uint32_t BufferIndexes)
+{
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+ uint32_t ITs_lines_selection;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_IT(ActiveITs));
+ if ((ActiveITs & (FDCAN_IT_TX_COMPLETE | FDCAN_IT_TX_ABORT_COMPLETE)) != 0U)
+ {
+ assert_param(IS_FDCAN_TX_LOCATION_LIST(BufferIndexes));
+ }
+
+ if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+ {
+ /* Get interrupts line selection */
+ ITs_lines_selection = hfdcan->Instance->ILS;
+
+ /* Enable Interrupt lines */
+ if ((((ActiveITs & FDCAN_IT_LIST_RX_FIFO0) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0) == 0U)) || \
+ (((ActiveITs & FDCAN_IT_LIST_RX_FIFO1) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1) == 0U)) || \
+ (((ActiveITs & FDCAN_IT_LIST_SMSG) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG) == 0U)) || \
+ (((ActiveITs & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR) == 0U)) || \
+ (((ActiveITs & FDCAN_IT_LIST_MISC) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC) == 0U)) || \
+ (((ActiveITs & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) == 0U)) || \
+ (((ActiveITs & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) == 0U)))
+ {
+ /* Enable Interrupt line 0 */
+ SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
+ }
+ if ((((ActiveITs & FDCAN_IT_LIST_RX_FIFO0) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0) != 0U)) || \
+ (((ActiveITs & FDCAN_IT_LIST_RX_FIFO1) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1) != 0U)) || \
+ (((ActiveITs & FDCAN_IT_LIST_SMSG) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG) != 0U)) || \
+ (((ActiveITs & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR) != 0U)) || \
+ (((ActiveITs & FDCAN_IT_LIST_MISC) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC) != 0U)) || \
+ (((ActiveITs & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) != 0U)) || \
+ (((ActiveITs & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) != 0U)))
+ {
+ /* Enable Interrupt line 1 */
+ SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
+ }
+
+ if ((ActiveITs & FDCAN_IT_TX_COMPLETE) != 0U)
+ {
+ /* Enable Tx Buffer Transmission Interrupt to set TC flag in IR register,
+ but interrupt will only occur if TC is enabled in IE register */
+ SET_BIT(hfdcan->Instance->TXBTIE, BufferIndexes);
+ }
+
+ if ((ActiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U)
+ {
+ /* Enable Tx Buffer Cancellation Finished Interrupt to set TCF flag in IR register,
+ but interrupt will only occur if TCF is enabled in IE register */
+ SET_BIT(hfdcan->Instance->TXBCIE, BufferIndexes);
+ }
+
+ /* Enable the selected interrupts */
+ __HAL_FDCAN_ENABLE_IT(hfdcan, ActiveITs);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Disable interrupts.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param InactiveITs indicates which interrupts will be disabled.
+ * This parameter can be any combination of @arg FDCAN_Interrupts.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs)
+{
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+ uint32_t ITs_enabled;
+ uint32_t ITs_lines_selection;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_IT(InactiveITs));
+
+ if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+ {
+ /* Disable the selected interrupts */
+ __HAL_FDCAN_DISABLE_IT(hfdcan, InactiveITs);
+
+ if ((InactiveITs & FDCAN_IT_TX_COMPLETE) != 0U)
+ {
+ /* Disable Tx Buffer Transmission Interrupts */
+ CLEAR_REG(hfdcan->Instance->TXBTIE);
+ }
+
+ if ((InactiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U)
+ {
+ /* Disable Tx Buffer Cancellation Finished Interrupt */
+ CLEAR_REG(hfdcan->Instance->TXBCIE);
+ }
+
+ /* Get interrupts enabled and interrupts line selection */
+ ITs_enabled = hfdcan->Instance->IE;
+ ITs_lines_selection = hfdcan->Instance->ILS;
+
+ /* Check if some interrupts are still enabled on interrupt line 0 */
+ if ((((ITs_enabled & FDCAN_IT_LIST_RX_FIFO0) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0) == 0U)) || \
+ (((ITs_enabled & FDCAN_IT_LIST_RX_FIFO1) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1) == 0U)) || \
+ (((ITs_enabled & FDCAN_IT_LIST_SMSG) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG) == 0U)) || \
+ (((ITs_enabled & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR) == 0U)) || \
+ (((ITs_enabled & FDCAN_IT_LIST_MISC) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC) == 0U)) || \
+ (((ITs_enabled & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) == 0U)) || \
+ (((ITs_enabled & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) == 0U)))
+ {
+ /* Do nothing */
+ }
+ else /* no more interrupts enabled on interrupt line 0 */
+ {
+ /* Disable interrupt line 0 */
+ CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
+ }
+
+ /* Check if some interrupts are still enabled on interrupt line 1 */
+ if ((((ITs_enabled & FDCAN_IT_LIST_RX_FIFO0) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0) != 0U)) || \
+ (((ITs_enabled & FDCAN_IT_LIST_RX_FIFO1) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1) != 0U)) || \
+ (((ITs_enabled & FDCAN_IT_LIST_SMSG) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG) != 0U)) || \
+ (((ITs_enabled & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR) != 0U)) || \
+ (((ITs_enabled & FDCAN_IT_LIST_MISC) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC) != 0U)) || \
+ (((ITs_enabled & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) != 0U)) || \
+ (((ITs_enabled & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) != 0U)))
+ {
+ /* Do nothing */
+ }
+ else /* no more interrupts enabled on interrupt line 1 */
+ {
+ /* Disable interrupt line 1 */
+ CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Handles FDCAN interrupt request.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
+{
+ uint32_t TxEventFifoITs;
+ uint32_t RxFifo0ITs;
+ uint32_t RxFifo1ITs;
+ uint32_t Errors;
+ uint32_t ErrorStatusITs;
+ uint32_t TransmittedBuffers;
+ uint32_t AbortedBuffers;
+
+ TxEventFifoITs = hfdcan->Instance->IR & FDCAN_TX_EVENT_FIFO_MASK;
+ TxEventFifoITs &= hfdcan->Instance->IE;
+ RxFifo0ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO0_MASK;
+ RxFifo0ITs &= hfdcan->Instance->IE;
+ RxFifo1ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO1_MASK;
+ RxFifo1ITs &= hfdcan->Instance->IE;
+ Errors = hfdcan->Instance->IR & FDCAN_ERROR_MASK;
+ Errors &= hfdcan->Instance->IE;
+ ErrorStatusITs = hfdcan->Instance->IR & FDCAN_ERROR_STATUS_MASK;
+ ErrorStatusITs &= hfdcan->Instance->IE;
+
+ /* High Priority Message interrupt management *******************************/
+ if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG) != 0U)
+ {
+ if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RX_HIGH_PRIORITY_MSG) != 0U)
+ {
+ /* Clear the High Priority Message flag */
+ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hfdcan->HighPriorityMessageCallback(hfdcan);
+#else
+ /* High Priority Message Callback */
+ HAL_FDCAN_HighPriorityMessageCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* Transmission Abort interrupt management **********************************/
+ if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE) != 0U)
+ {
+ if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_ABORT_COMPLETE) != 0U)
+ {
+ /* List of aborted monitored buffers */
+ AbortedBuffers = hfdcan->Instance->TXBCF;
+ AbortedBuffers &= hfdcan->Instance->TXBCIE;
+
+ /* Clear the Transmission Cancellation flag */
+ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hfdcan->TxBufferAbortCallback(hfdcan, AbortedBuffers);
+#else
+ /* Transmission Cancellation Callback */
+ HAL_FDCAN_TxBufferAbortCallback(hfdcan, AbortedBuffers);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* Tx event FIFO interrupts management **************************************/
+ if (TxEventFifoITs != 0U)
+ {
+ /* Clear the Tx Event FIFO flags */
+ __HAL_FDCAN_CLEAR_FLAG(hfdcan, TxEventFifoITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hfdcan->TxEventFifoCallback(hfdcan, TxEventFifoITs);
+#else
+ /* Tx Event FIFO Callback */
+ HAL_FDCAN_TxEventFifoCallback(hfdcan, TxEventFifoITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+ }
+
+ /* Rx FIFO 0 interrupts management ******************************************/
+ if (RxFifo0ITs != 0U)
+ {
+ /* Clear the Rx FIFO 0 flags */
+ __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo0ITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hfdcan->RxFifo0Callback(hfdcan, RxFifo0ITs);
+#else
+ /* Rx FIFO 0 Callback */
+ HAL_FDCAN_RxFifo0Callback(hfdcan, RxFifo0ITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+ }
+
+ /* Rx FIFO 1 interrupts management ******************************************/
+ if (RxFifo1ITs != 0U)
+ {
+ /* Clear the Rx FIFO 1 flags */
+ __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo1ITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hfdcan->RxFifo1Callback(hfdcan, RxFifo1ITs);
+#else
+ /* Rx FIFO 1 Callback */
+ HAL_FDCAN_RxFifo1Callback(hfdcan, RxFifo1ITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+ }
+
+ /* Tx FIFO empty interrupt management ***************************************/
+ if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY) != 0U)
+ {
+ if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_FIFO_EMPTY) != 0U)
+ {
+ /* Clear the Tx FIFO empty flag */
+ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hfdcan->TxFifoEmptyCallback(hfdcan);
+#else
+ /* Tx FIFO empty Callback */
+ HAL_FDCAN_TxFifoEmptyCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* Transmission Complete interrupt management *******************************/
+ if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE) != 0U)
+ {
+ if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_COMPLETE) != 0U)
+ {
+ /* List of transmitted monitored buffers */
+ TransmittedBuffers = hfdcan->Instance->TXBTO;
+ TransmittedBuffers &= hfdcan->Instance->TXBTIE;
+
+ /* Clear the Transmission Complete flag */
+ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hfdcan->TxBufferCompleteCallback(hfdcan, TransmittedBuffers);
+#else
+ /* Transmission Complete Callback */
+ HAL_FDCAN_TxBufferCompleteCallback(hfdcan, TransmittedBuffers);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* Timestamp Wraparound interrupt management ********************************/
+ if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND) != 0U)
+ {
+ if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TIMESTAMP_WRAPAROUND) != 0U)
+ {
+ /* Clear the Timestamp Wraparound flag */
+ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hfdcan->TimestampWraparoundCallback(hfdcan);
+#else
+ /* Timestamp Wraparound Callback */
+ HAL_FDCAN_TimestampWraparoundCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* Timeout Occurred interrupt management ************************************/
+ if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED) != 0U)
+ {
+ if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TIMEOUT_OCCURRED) != 0U)
+ {
+ /* Clear the Timeout Occurred flag */
+ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hfdcan->TimeoutOccurredCallback(hfdcan);
+#else
+ /* Timeout Occurred Callback */
+ HAL_FDCAN_TimeoutOccurredCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* Message RAM access failure interrupt management **************************/
+ if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE) != 0U)
+ {
+ if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RAM_ACCESS_FAILURE) != 0U)
+ {
+ /* Clear the Message RAM access failure flag */
+ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE);
+
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_RAM_ACCESS;
+ }
+ }
+
+ /* Error Status interrupts management ***************************************/
+ if (ErrorStatusITs != 0U)
+ {
+ /* Clear the Error flags */
+ __HAL_FDCAN_CLEAR_FLAG(hfdcan, ErrorStatusITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hfdcan->ErrorStatusCallback(hfdcan, ErrorStatusITs);
+#else
+ /* Error Status Callback */
+ HAL_FDCAN_ErrorStatusCallback(hfdcan, ErrorStatusITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+ }
+
+ /* Error interrupts management **********************************************/
+ if (Errors != 0U)
+ {
+ /* Clear the Error flags */
+ __HAL_FDCAN_CLEAR_FLAG(hfdcan, Errors);
+
+ /* Update error code */
+ hfdcan->ErrorCode |= Errors;
+ }
+
+ if (hfdcan->ErrorCode != HAL_FDCAN_ERROR_NONE)
+ {
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hfdcan->ErrorCallback(hfdcan);
+#else
+ /* Error Callback */
+ HAL_FDCAN_ErrorCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Exported_Functions_Group5 Callback functions
+ * @brief FDCAN Callback functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Callback functions #####
+ ==============================================================================
+ [..]
+ This subsection provides the following callback functions:
+ (+) HAL_FDCAN_TxEventFifoCallback
+ (+) HAL_FDCAN_RxFifo0Callback
+ (+) HAL_FDCAN_RxFifo1Callback
+ (+) HAL_FDCAN_TxFifoEmptyCallback
+ (+) HAL_FDCAN_TxBufferCompleteCallback
+ (+) HAL_FDCAN_TxBufferAbortCallback
+ (+) HAL_FDCAN_HighPriorityMessageCallback
+ (+) HAL_FDCAN_TimestampWraparoundCallback
+ (+) HAL_FDCAN_TimeoutOccurredCallback
+ (+) HAL_FDCAN_ErrorCallback
+ (+) HAL_FDCAN_ErrorStatusCallback
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Tx Event callback.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param TxEventFifoITs indicates which Tx Event FIFO interrupts are signalled.
+ * This parameter can be any combination of @arg FDCAN_Tx_Event_Fifo_Interrupts.
+ * @retval None
+ */
+__weak void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+ UNUSED(TxEventFifoITs);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_TxEventFifoCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx FIFO 0 callback.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param RxFifo0ITs indicates which Rx FIFO 0 interrupts are signalled.
+ * This parameter can be any combination of @arg FDCAN_Rx_Fifo0_Interrupts.
+ * @retval None
+ */
+__weak void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+ UNUSED(RxFifo0ITs);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_RxFifo0Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx FIFO 1 callback.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param RxFifo1ITs indicates which Rx FIFO 1 interrupts are signalled.
+ * This parameter can be any combination of @arg FDCAN_Rx_Fifo1_Interrupts.
+ * @retval None
+ */
+__weak void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+ UNUSED(RxFifo1ITs);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_RxFifo1Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx FIFO Empty callback.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval None
+ */
+__weak void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_TxFifoEmptyCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Transmission Complete callback.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param BufferIndexes Indexes of the transmitted buffers.
+ * This parameter can be any combination of @arg FDCAN_Tx_location.
+ * @retval None
+ */
+__weak void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+ UNUSED(BufferIndexes);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_TxBufferCompleteCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Transmission Cancellation callback.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param BufferIndexes Indexes of the aborted buffers.
+ * This parameter can be any combination of @arg FDCAN_Tx_location.
+ * @retval None
+ */
+__weak void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+ UNUSED(BufferIndexes);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_TxBufferAbortCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Timestamp Wraparound callback.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval None
+ */
+__weak void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_TimestampWraparoundCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Timeout Occurred callback.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval None
+ */
+__weak void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_TimeoutOccurredCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief High Priority Message callback.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval None
+ */
+__weak void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_HighPriorityMessageCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Error callback.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval None
+ */
+__weak void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Error status callback.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param ErrorStatusITs indicates which Error Status interrupts are signaled.
+ * This parameter can be any combination of @arg FDCAN_Error_Status_Interrupts.
+ * @retval None
+ */
+__weak void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+ UNUSED(ErrorStatusITs);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_ErrorStatusCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Exported_Functions_Group6 Peripheral State functions
+ * @brief FDCAN Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection provides functions allowing to :
+ (+) HAL_FDCAN_GetState() : Return the FDCAN state.
+ (+) HAL_FDCAN_GetError() : Return the FDCAN error code if any.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Return the FDCAN state
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL state
+ */
+HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan)
+{
+ /* Return FDCAN state */
+ return hfdcan->State;
+}
+
+/**
+ * @brief Return the FDCAN error code
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval FDCAN Error Code
+ */
+uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan)
+{
+ /* Return FDCAN error code */
+ return hfdcan->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Private_Functions FDCAN Private Functions
+ * @{
+ */
+
+/**
+ * @brief Calculate each RAM block start address and size
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval none
+ */
+static void FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan)
+{
+ uint32_t RAMcounter;
+ uint32_t SramCanInstanceBase = SRAMCAN_BASE;
+
+ /* Standard filter list start address */
+ hfdcan->msgRam.StandardFilterSA = SramCanInstanceBase + SRAMCAN_FLSSA;
+
+ /* Standard filter elements number */
+ MODIFY_REG(hfdcan->Instance->RXGFC, FDCAN_RXGFC_LSS, (hfdcan->Init.StdFiltersNbr << FDCAN_RXGFC_LSS_Pos));
+
+ /* Extended filter list start address */
+ hfdcan->msgRam.ExtendedFilterSA = SramCanInstanceBase + SRAMCAN_FLESA;
+
+ /* Extended filter elements number */
+ MODIFY_REG(hfdcan->Instance->RXGFC, FDCAN_RXGFC_LSE, (hfdcan->Init.ExtFiltersNbr << FDCAN_RXGFC_LSE_Pos));
+
+ /* Rx FIFO 0 start address */
+ hfdcan->msgRam.RxFIFO0SA = SramCanInstanceBase + SRAMCAN_RF0SA;
+
+ /* Rx FIFO 1 start address */
+ hfdcan->msgRam.RxFIFO1SA = SramCanInstanceBase + SRAMCAN_RF1SA;
+
+ /* Tx event FIFO start address */
+ hfdcan->msgRam.TxEventFIFOSA = SramCanInstanceBase + SRAMCAN_TEFSA;
+
+ /* Tx FIFO/queue start address */
+ hfdcan->msgRam.TxFIFOQSA = SramCanInstanceBase + SRAMCAN_TFQSA;
+
+ /* Flush the allocated Message RAM area */
+ for (RAMcounter = SramCanInstanceBase; RAMcounter < (SramCanInstanceBase + SRAMCAN_SIZE); RAMcounter += 4U)
+ {
+ *(uint32_t *)(RAMcounter) = 0x00000000U;
+ }
+}
+
+/**
+ * @brief Copy Tx message to the message RAM.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure.
+ * @param pTxData pointer to a buffer containing the payload of the Tx frame.
+ * @param BufferIndex index of the buffer to be configured.
+ * @retval none
+ */
+static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData,
+ uint32_t BufferIndex)
+{
+ uint32_t TxElementW1;
+ uint32_t TxElementW2;
+ uint32_t *TxAddress;
+ uint32_t ByteCounter;
+
+ /* Build first word of Tx header element */
+ if (pTxHeader->IdType == FDCAN_STANDARD_ID)
+ {
+ TxElementW1 = (pTxHeader->ErrorStateIndicator |
+ FDCAN_STANDARD_ID |
+ pTxHeader->TxFrameType |
+ (pTxHeader->Identifier << 18U));
+ }
+ else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
+ {
+ TxElementW1 = (pTxHeader->ErrorStateIndicator |
+ FDCAN_EXTENDED_ID |
+ pTxHeader->TxFrameType |
+ pTxHeader->Identifier);
+ }
+
+ /* Build second word of Tx header element */
+ TxElementW2 = ((pTxHeader->MessageMarker << 24U) |
+ pTxHeader->TxEventFifoControl |
+ pTxHeader->FDFormat |
+ pTxHeader->BitRateSwitch |
+ pTxHeader->DataLength);
+
+ /* Calculate Tx element address */
+ TxAddress = (uint32_t *)(hfdcan->msgRam.TxFIFOQSA + (BufferIndex * SRAMCAN_TFQ_SIZE));
+
+ /* Write Tx element header to the message RAM */
+ *TxAddress = TxElementW1;
+ TxAddress++;
+ *TxAddress = TxElementW2;
+ TxAddress++;
+
+ /* Write Tx payload to the message RAM */
+ for (ByteCounter = 0; ByteCounter < DLCtoBytes[pTxHeader->DataLength >> 16U]; ByteCounter += 4U)
+ {
+ *TxAddress = (((uint32_t)pTxData[ByteCounter + 3U] << 24U) |
+ ((uint32_t)pTxData[ByteCounter + 2U] << 16U) |
+ ((uint32_t)pTxData[ByteCounter + 1U] << 8U) |
+ (uint32_t)pTxData[ByteCounter]);
+ TxAddress++;
+ }
+}
+
+/**
+ * @}
+ */
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* FDCAN1 */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_flash.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_flash.c
new file mode 100644
index 00000000..4e4bf160
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_flash.c
@@ -0,0 +1,774 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_flash.c
+ * @author MCD Application Team
+ * @brief FLASH HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the internal FLASH memory:
+ * + Program operations functions
+ * + Memory Control functions
+ * + Peripheral Errors functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### FLASH peripheral features #####
+ ==============================================================================
+
+ [..] The Flash memory interface manages CPU AHB C-Bus accesses to the Flash memory.
+ It implements the erase and program Flash memory operations and the read
+ and write protection mechanisms.
+
+ [..] The Flash memory interface implements the TrustZone security features (TZ) supported
+ by ARM Cortex-M33 core (CM33).
+
+ [..] The FLASH main features are:
+ (+) Flash memory read operations
+ (+) Flash memory program/erase operations
+ (+) Read / write protections
+ (+) Option bytes programming
+ (+) TrustZone aware
+ (+) Watermark-based area protection including the secure hide area
+ (+) Block-based page protection
+ (+) Error code correction (ECC) : Data in flash are 137-bits word
+ (9 bits added per quad-word)
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This driver provides functions and macros to configure and program the FLASH
+ memory of all STM32U5xx devices.
+
+ (#) Flash Memory IO Programming functions:
+ (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
+ HAL_FLASH_Lock() functions
+ (++) Program functions: quad-words and burst program (8 quad-words)
+ (++) There are two modes of programming :
+ (+++) Polling mode using HAL_FLASH_Program() function
+ (+++) Interrupt mode using HAL_FLASH_Program_IT() function
+
+ (#) Interrupts and flags management functions :
+ (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
+ (++) Callback functions are called when the flash operations are finished :
+ HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise
+ HAL_FLASH_OperationErrorCallback()
+ (++) Get error flag status by calling HAL_GetError()
+
+ (#) Option bytes management functions :
+ (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and
+ HAL_FLASH_OB_Lock() functions
+ (++) Launch the reload of the option bytes using HAL_FLASH_Launch() function.
+ In this case, a reset is generated
+
+ [..]
+ In addition to these functions, this driver includes a set of macros allowing
+ to handle the following operations:
+ (+) Set the latency
+ (+) Enable/Disable the Flash power-down during low-power run and sleep modes
+ (+) Enable/Disable the Flash interrupts
+ (+) Monitor the Flash flags status
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup FLASH FLASH
+ * @brief FLASH HAL module driver
+ * @{
+ */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Variables FLASH Private Variables
+ * @{
+ */
+/**
+ * @brief Variable used for Program/Erase sectors under interruption
+ */
+FLASH_ProcessTypeDef pFlash = {.Lock = HAL_UNLOCKED, \
+ .ErrorCode = HAL_FLASH_ERROR_NONE, \
+ .ProcedureOnGoing = 0U, \
+ .Address = 0U, \
+ .Bank = FLASH_BANK_1, \
+ .Page = 0U, \
+ .NbPagesToErase = 0U
+ };
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup FLASH_Private_Functions FLASH Private Functions
+ * @{
+ */
+static void FLASH_Program_QuadWord(uint32_t Address, uint32_t DataAddress);
+static void FLASH_Program_Burst(uint32_t Address, uint32_t DataAddress);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
+ * @{
+ */
+
+/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
+ * @brief Programming operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Programming operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the FLASH
+ program operations.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Program a quad-word or a burst of 8 quad-words at a specified address.
+ * @param TypeProgram Indicate the way to program at a specified address.
+ * This parameter can be a value of @ref FLASH_Type_Program
+ * @param Address specifies the address to be programmed.
+ * This parameter shall be aligned to the Flash word (128 bits)
+ * @param DataAddress specifies the address of data to be programmed.
+ * This parameter shall be 32-bit aligned
+ *
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t DataAddress)
+{
+ HAL_StatusTypeDef status;
+ __IO uint32_t *reg_cr;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Reset error code */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
+
+ if (status == HAL_OK)
+ {
+ /* Set current operation type */
+ pFlash.ProcedureOnGoing = TypeProgram;
+
+ /* Access to SECCR or NSCR depends on operation type */
+ reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR);
+
+ if ((TypeProgram & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEPROGRAM_QUADWORD)
+ {
+ /* Program a quad-word (128-bit) at a specified address */
+ FLASH_Program_QuadWord(Address, DataAddress);
+ }
+ else
+ {
+ /* Program a burst of 8 quad-words at a specified address */
+ FLASH_Program_Burst(Address, DataAddress);
+ }
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
+
+ /* If the program operation is completed, disable the PG (and BWR Bit in Burst programming mode) */
+ CLEAR_BIT((*reg_cr), (TypeProgram & ~(FLASH_NON_SECURE_MASK)));
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+
+ /* return status */
+ return status;
+}
+
+/**
+ * @brief Program a quad-word or a burst of 8 quad-words at a specified address with interrupt enabled.
+ * @param TypeProgram Indicate the way to program at a specified address.
+ * This parameter can be a value of @ref FLASH_Type_Program
+ * @param Address specifies the address to be programmed.
+ * This parameter shall be aligned to the Flash word (128 bits)
+ * @param DataAddress specifies the address of data to be programmed.
+ * This parameter shall be 32-bit aligned
+ *
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t DataAddress)
+{
+ HAL_StatusTypeDef status;
+ __IO uint32_t *reg_cr;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Reset error code */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
+
+ if (status != HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+ }
+ else
+ {
+ /* Set internal variables used by the IRQ handler */
+ pFlash.ProcedureOnGoing = TypeProgram;
+ pFlash.Address = Address;
+
+ /* Access to SECCR or NSCR depends on operation type */
+ reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR);
+
+ /* Enable End of Operation and Error interrupts */
+ (*reg_cr) |= (FLASH_IT_EOP | FLASH_IT_OPERR);
+
+ if ((TypeProgram & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEPROGRAM_QUADWORD)
+ {
+ /* Program a quad-word (128-bit) at a specified address */
+ FLASH_Program_QuadWord(Address, DataAddress);
+ }
+ else
+ {
+ /* Program a burst of 8 quad-words at a specified address */
+ FLASH_Program_Burst(Address, DataAddress);
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Handle FLASH interrupt request.
+ * @retval None
+ */
+void HAL_FLASH_IRQHandler(void)
+{
+ uint32_t param = 0U;
+ uint32_t error;
+ __IO uint32_t *reg_cr;
+ __IO uint32_t *reg_sr;
+
+ /* Access to CR and SR registers depends on operation type */
+ reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR);
+ reg_sr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECSR) : &(FLASH_NS->NSSR);
+
+ /* Save Flash errors */
+ error = (*reg_sr) & FLASH_FLAG_SR_ERRORS;
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ error |= (FLASH->NSSR & FLASH_FLAG_OPTWERR);
+#endif /* __ARM_FEATURE_CMSE */
+
+ /* Set parameter of the callback */
+ if ((pFlash.ProcedureOnGoing & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEERASE_PAGES)
+ {
+ param = pFlash.Page;
+ }
+ else if ((pFlash.ProcedureOnGoing & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEERASE_MASSERASE)
+ {
+ param = pFlash.Bank;
+ }
+ else if ((pFlash.ProcedureOnGoing & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEPROGRAM_QUADWORD)
+ {
+ param = pFlash.Address;
+ }
+ else if ((pFlash.ProcedureOnGoing & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEPROGRAM_BURST)
+ {
+ param = pFlash.Address;
+ }
+ else
+ {
+ /* Empty statement (to be compliant MISRA 15.7) */
+ }
+
+ /* Clear operation bit on the on-going procedure */
+ CLEAR_BIT((*reg_cr), (pFlash.ProcedureOnGoing & ~(FLASH_NON_SECURE_MASK)));
+
+ /* Check FLASH operation error flags */
+ if (error != 0U)
+ {
+ /* Save the error code */
+ pFlash.ErrorCode |= error;
+
+ /* Clear error programming flags */
+ (*reg_sr) = error;
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ if ((error & FLASH_FLAG_OPTWERR) != 0U)
+ {
+ FLASH->NSSR = FLASH_FLAG_OPTWERR;
+ }
+#endif /* __ARM_FEATURE_CMSE */
+
+ /* Stop the procedure ongoing */
+ pFlash.ProcedureOnGoing = 0U;
+
+ /* FLASH error interrupt user callback */
+ HAL_FLASH_OperationErrorCallback(param);
+ }
+
+ /* Check FLASH End of Operation flag */
+ if (((*reg_sr) & FLASH_FLAG_EOP) != 0U)
+ {
+ /* Clear FLASH End of Operation pending bit */
+ (*reg_sr) = FLASH_FLAG_EOP;
+
+ if ((pFlash.ProcedureOnGoing & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEERASE_PAGES)
+ {
+ /* Nb of pages to erase can be decreased */
+ pFlash.NbPagesToErase--;
+
+ /* Check if there are still pages to erase */
+ if (pFlash.NbPagesToErase != 0U)
+ {
+ /* Increment page number */
+ pFlash.Page++;
+ FLASH_PageErase(pFlash.Page, pFlash.Bank);
+ }
+ else
+ {
+ /* No more pages to Erase */
+ pFlash.ProcedureOnGoing = 0U;
+ param = 0xFFFFFFFFU;
+ }
+ }
+ else
+ {
+ /*Clear the procedure ongoing*/
+ pFlash.ProcedureOnGoing = 0U;
+ }
+
+ /* FLASH EOP interrupt user callback */
+ HAL_FLASH_EndOfOperationCallback(param);
+ }
+
+ if (pFlash.ProcedureOnGoing == 0U)
+ {
+ /* Disable End of Operation and Error interrupts */
+ (*reg_cr) &= ~(FLASH_IT_EOP | FLASH_IT_OPERR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+ }
+}
+
+/**
+ * @brief FLASH end of operation interrupt callback.
+ * @param ReturnValue The value saved in this parameter depends on the ongoing procedure
+ * Mass Erase: Bank number which has been requested to erase
+ * Page Erase: Page which has been erased
+ * (if 0xFFFFFFFF, it means that all the selected pages have been erased)
+ * Program: Address which was selected for data program
+ * @retval None
+ */
+__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(ReturnValue);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief FLASH operation error interrupt callback.
+ * @param ReturnValue The value saved in this parameter depends on the ongoing procedure
+ * Mass Erase: Bank number which has been requested to erase
+ * Page Erase: Page number which returned an error
+ * Program: Address which was selected for data program
+ * @retval None
+ */
+__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(ReturnValue);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_FLASH_OperationErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
+ * @brief Management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the FLASH
+ memory operations.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Unlock the FLASH control register access.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Unlock(void)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (READ_BIT(FLASH->NSCR, FLASH_NSCR_LOCK) != 0U)
+ {
+ /* Authorize the FLASH Registers access */
+ WRITE_REG(FLASH->NSKEYR, FLASH_KEY1);
+ WRITE_REG(FLASH->NSKEYR, FLASH_KEY2);
+
+ /* verify Flash is unlocked */
+ if (READ_BIT(FLASH->NSCR, FLASH_NSCR_LOCK) != 0U)
+ {
+ status = HAL_ERROR;
+ }
+ }
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ if (status == HAL_OK)
+ {
+ if (READ_BIT(FLASH->SECCR, FLASH_SECCR_LOCK) != 0U)
+ {
+ /* Authorize the FLASH Registers access */
+ WRITE_REG(FLASH->SECKEYR, FLASH_KEY1);
+ WRITE_REG(FLASH->SECKEYR, FLASH_KEY2);
+
+ /* verify Flash is unlocked */
+ if (READ_BIT(FLASH->SECCR, FLASH_SECCR_LOCK) != 0U)
+ {
+ status = HAL_ERROR;
+ }
+ }
+ }
+#endif /* __ARM_FEATURE_CMSE */
+
+ return status;
+}
+
+/**
+ * @brief Lock the FLASH control register access.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Lock(void)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Set the LOCK Bit to lock the FLASH Registers access */
+ SET_BIT(FLASH->NSCR, FLASH_NSCR_LOCK);
+
+ /* verify Flash is locked */
+ if (READ_BIT(FLASH->NSCR, FLASH_NSCR_LOCK) != 0U)
+ {
+ status = HAL_OK;
+ }
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ if (status == HAL_OK)
+ {
+ SET_BIT(FLASH->SECCR, FLASH_SECCR_LOCK);
+
+ /* verify Flash is locked */
+ if (READ_BIT(FLASH->SECCR, FLASH_SECCR_LOCK) != 0U)
+ {
+ status = HAL_OK;
+ }
+ }
+#endif /* __ARM_FEATURE_CMSE */
+
+ return status;
+}
+
+/**
+ * @brief Unlock the FLASH Option Bytes Registers access.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
+{
+ if (READ_BIT(FLASH->NSCR, FLASH_NSCR_OPTLOCK) != 0U)
+ {
+ /* Authorizes the Option Byte register programming */
+ WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
+ WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
+
+ /* Verify that the Option Bytes are unlocked */
+ if (READ_BIT(FLASH->NSCR, FLASH_NSCR_OPTLOCK) != 0U)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Lock the FLASH Option Bytes Registers access.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
+{
+ /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
+ SET_BIT(FLASH->NSCR, FLASH_NSCR_OPTLOCK);
+
+ /* Verify that the Option Bytes are locked */
+ if (READ_BIT(FLASH->NSCR, FLASH_NSCR_OPTLOCK) != 0U)
+ {
+ return HAL_OK;
+ }
+
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Launch the option byte loading.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
+{
+ /* Set the bit to force the option byte reloading */
+ SET_BIT(FLASH->NSCR, FLASH_NSCR_OBL_LAUNCH);
+
+ /* We should not reach here : Option byte launch generates Option byte reset
+ so return error */
+ return HAL_ERROR;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief Peripheral Errors functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time Errors of the FLASH peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Get the specific FLASH error flag.
+ * @retval FLASH_ErrorCode The returned value can be:
+ * @arg HAL_FLASH_ERROR_NONE: No error set
+ * @arg HAL_FLASH_ERROR_OP: FLASH Operation error
+ * @arg HAL_FLASH_ERROR_PROG: FLASH Programming error
+ * @arg HAL_FLASH_ERROR_WRP: FLASH Write protection error
+ * @arg HAL_FLASH_ERROR_PGA: FLASH Programming alignment error
+ * @arg HAL_FLASH_ERROR_SIZ: FLASH Size error
+ * @arg HAL_FLASH_ERROR_PGS: FLASH Programming sequence error
+ * @arg HAL_FLASH_ERROR_OPTW: FLASH Option modification error
+ */
+uint32_t HAL_FLASH_GetError(void)
+{
+ return pFlash.ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @addtogroup FLASH_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Wait for a FLASH operation to complete.
+ * @param Timeout maximum flash operation timeout
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
+{
+ /* Wait for the FLASH operation to complete by polling on BUSY and WDW flags to be reset.
+ Even if the FLASH operation fails, the BUSY & WDW flags will be reset, and an error flag will be set */
+
+ uint32_t timeout = HAL_GetTick() + Timeout;
+ uint32_t error;
+ __IO uint32_t *reg_sr;
+
+ /* Access to SECSR or NSSR registers depends on operation type */
+ reg_sr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECSR) : &(FLASH_NS->NSSR);
+
+ while (((*reg_sr) & (FLASH_FLAG_BSY | FLASH_FLAG_WDW)) != 0U)
+ {
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (HAL_GetTick() >= timeout)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Check FLASH operation error flags */
+ error = ((*reg_sr) & FLASH_FLAG_SR_ERRORS);
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ error |= (FLASH->NSSR & FLASH_FLAG_OPTWERR);
+#endif /* __ARM_FEATURE_CMSE */
+
+ if (error != 0U)
+ {
+ /*Save the error code*/
+ pFlash.ErrorCode |= error;
+
+ /* Clear error programming flags */
+ (*reg_sr) = error;
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ if ((error & FLASH_FLAG_OPTWERR) != 0U)
+ {
+ FLASH->NSSR = FLASH_FLAG_OPTWERR;
+ }
+#endif /* __ARM_FEATURE_CMSE */
+
+ return HAL_ERROR;
+ }
+
+ /* Check FLASH End of Operation flag */
+ if (((*reg_sr) & FLASH_FLAG_EOP) != 0U)
+ {
+ /* Clear FLASH End of Operation pending bit */
+ (*reg_sr) = FLASH_FLAG_EOP;
+ }
+
+ /* If there is no error flag set */
+ return HAL_OK;
+}
+
+/**
+ * @brief Program a quad-word (128-bit) at a specified address.
+ * @param Address specifies the address to be programmed.
+ * @param DataAddress specifies the address of data to be programmed.
+ * @retval None
+ */
+static void FLASH_Program_QuadWord(uint32_t Address, uint32_t DataAddress)
+{
+ uint8_t index = 4;
+ uint32_t *dest_addr = (uint32_t *)Address;
+ uint32_t *src_addr = (uint32_t *)DataAddress;
+ uint32_t primask_bit;
+ __IO uint32_t *reg_cr;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
+
+ /* Access to SECCR or NSCR registers depends on operation type */
+ reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR);
+
+ /* Set PG bit */
+ SET_BIT((*reg_cr), FLASH_NSCR_PG);
+
+ /* Enter critical section: Disable interrupts to avoid any interruption during the loop */
+ primask_bit = __get_PRIMASK();
+ __disable_irq();
+
+ /* Program the quad-word */
+ do
+ {
+ *dest_addr = *src_addr;
+ dest_addr++;
+ src_addr++;
+ index--;
+ } while (index != 0U);
+
+ /* Exit critical section: restore previous priority mask */
+ __set_PRIMASK(primask_bit);
+}
+
+/**
+ * @brief Program a burst of 8x quad-words at a specified address.
+ * @param Address: specifies the address to be programmed.
+ * @param DataAddress: specifies the address where the data are stored.
+ * @retval None
+ */
+static void FLASH_Program_Burst(uint32_t Address, uint32_t DataAddress)
+{
+ uint8_t burst_index = FLASH_NB_WORDS_IN_BURST;
+ uint32_t *dest_addr = (uint32_t *)Address;
+ uint32_t *src_addr = (uint32_t *)DataAddress;
+ uint32_t primask_bit;
+ __IO uint32_t *reg_cr;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_MAIN_MEM_ADDRESS(Address));
+
+ /* Access to SECCR or NSCR registers depends on operation type */
+ reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR);
+
+ /* Set PG and BWR bits */
+ SET_BIT((*reg_cr), (FLASH_NSCR_PG | FLASH_NSCR_BWR));
+
+ /* Enter critical section: Disable interrupts to avoid any interruption during the loop */
+ primask_bit = __get_PRIMASK();
+ __disable_irq();
+
+ /* Program the burst */
+ do
+ {
+ *dest_addr = *src_addr;
+ dest_addr++;
+ src_addr++;
+ burst_index--;
+ } while (burst_index != 0U);
+
+ /* Exit critical section: restore previous priority mask */
+ __set_PRIMASK(primask_bit);
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_flash_ex.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_flash_ex.c
new file mode 100644
index 00000000..bb61832d
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_flash_ex.c
@@ -0,0 +1,1698 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_flash_ex.c
+ * @author MCD Application Team
+ * @brief Extended FLASH HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the FLASH extended peripheral:
+ * + Extended programming operations functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### Flash Extended features #####
+ ==============================================================================
+
+ [..] Comparing to other previous devices, the FLASH interface for STM32U5xx
+ devices contains the following additional features
+
+ (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
+ capability (RWW)
+ (+) Dual bank memory organization
+ (+) Watermark-based secure area including the secure hide areas
+ (+) Block-based secure pages
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..] This driver provides functions to configure and program the FLASH memory
+ of all STM32U5xx devices. It includes:
+ (#) Flash Memory Erase functions:
+ (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
+ HAL_FLASH_Lock() functions
+ (++) Erase function: page Erase and Bank/Mass Erase
+ (++) There are two modes of erase :
+ (+++) Polling Mode using HAL_FLASHEx_Erase()
+ (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
+
+ (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to:
+ (++) Configure the write protection for each area
+ (++) Set the Read protection Level
+ (++) Program the user Option Bytes
+ (++) Configure the watermark security for each area including the secure hide areas
+ (++) Configure the boot lock (BOOT_LOCK)
+ (++) Configure the Boot addresses
+
+ (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to:
+ (++) Get the value of a write protection area
+ (++) Know if the read protection is activated
+ (++) Get the value of the user Option Bytes
+ (++) Get the configuration of a watermark security area including the secure hide areas
+ (++) Get the boot lock (BOOT_LOCK) configuration
+ (++) Get the value of a boot address
+
+ (#) Block-based secure / privilege area configuration function: Use HAL_FLASHEx_ConfigBBAttributes()
+ (++) Bit-field allowing to secure or un-secure each page
+ (++) Bit-field allowing to privilege or un-privilege each page
+
+ (#) Get the block-based secure / privilege area configuration function: Use HAL_FLASHEx_GetBBSec()
+ (++) Return the configuration of the block-based security and privilege for all the pages
+
+ (#) Activation of the secure hide area function: Use HAL_FLASHEx_EnableSecHideProtection()
+ (++) Deny the access to the secure hide area
+
+ (#) Privilege mode configuration function: Use HAL_FLASHEx_ConfigPrivMode()
+ (++) FLASH register can be protected against non-privilege accesses
+
+ (#) Get the privilege mode configuration function: Use HAL_FLASHEx_GetPrivMode()
+ (++) Return if the FLASH registers are protected against non-privilege accesses
+
+ (#) Security inversion configuration function: Use HAL_FLASHEx_ConfigSecInversion()
+ (++) FLASH secure state can be override
+
+ (#) Get the security inversion configuration function: Use HAL_FLASHEx_GetSecInversion()
+ (++) Return if FLASH secure state is override
+
+ (#) Enable bank low-power mode function: Use HAL_FLASHEx_EnablePowerDown()
+ (++) Enable low-power mode for Flash Bank 1 and/or Bank 2
+
+ (#) Enable low-power read mode function: Use HAL_FLASHEx_ConfigLowPowerRead()
+ (++) Enable low-power read mode for Flash memory
+
+ (#) Get the low-power read mode configuration function: Use HAL_FLASHEx_GetLowPowerRead()
+ (++) Return if FLASH is in low-power read mode or normal read mode
+
+ (#) Get Flash operation function: Use HAL_FLASHEx_GetOperation()
+ (++) Return information about the on-going Flash operation. After a
+ system reset, return information about the interrupted Flash operation, if any.
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup FLASHEx FLASHEx
+ * @brief FLASH Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
+ * @{
+ */
+static void FLASH_MassErase(uint32_t Banks);
+static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRPEndOffset,
+ FunctionalState WRPLock);
+static void FLASH_OB_RDPConfig(uint32_t RDPLevel);
+static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig);
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+static void FLASH_OB_WMSECConfig(uint32_t WMSecConfig, uint32_t WMSecStartPage, uint32_t WMSecEndPage,
+ uint32_t WMHDPEndPage);
+static void FLASH_OB_BootLockConfig(uint32_t BootLockConfig);
+#endif /* __ARM_FEATURE_CMSE */
+static void FLASH_OB_BootAddrConfig(uint32_t BootAddrConfig, uint32_t BootAddr);
+static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRPEndOffset,
+ FunctionalState *WRPLock);
+static uint32_t FLASH_OB_GetRDP(void);
+static uint32_t FLASH_OB_GetUser(void);
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+static void FLASH_OB_GetWMSEC(uint32_t *WMSecConfig, uint32_t *WMSecStartPage, uint32_t *WMSecEndPage,
+ uint32_t *WMHDPEndPage);
+static uint32_t FLASH_OB_GetBootLock(void);
+#endif /* __ARM_FEATURE_CMSE */
+static void FLASH_OB_GetBootAddr(uint32_t BootAddrConfig, uint32_t *BootAddr);
+static void FLASH_OB_RDPKeyConfig(uint32_t RDPKeyType, uint32_t RDPKey1, uint32_t RDPKey2);
+/**
+ * @}
+ */
+
+/* Exported functions -------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
+ * @{
+ */
+
+/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
+ * @brief Extended IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended programming operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the Extended FLASH
+ programming operations Operations.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Perform a mass erase or erase the specified FLASH memory pages.
+ * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
+ * contains the configuration information for the erasing.
+ *
+ * @param[out] PageError pointer to variable that contains the configuration
+ * information on faulty page in case of error (0xFFFFFFFF means that all
+ * the pages have been correctly erased).
+ *
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
+{
+ HAL_StatusTypeDef status;
+ uint32_t page_index;
+ __IO uint32_t *reg_cr;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Reset error code */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
+
+ if (status == HAL_OK)
+ {
+ /* Current operation type */
+ pFlash.ProcedureOnGoing = pEraseInit->TypeErase;
+
+ /* Access to SECCR or NSCR depends on operation type */
+ reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH->NSCR);
+
+ if ((pEraseInit->TypeErase & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEERASE_MASSERASE)
+ {
+ /* Mass erase to be done */
+ FLASH_MassErase(pEraseInit->Banks);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
+ }
+ else
+ {
+ /*Initialization of PageError variable*/
+ *PageError = 0xFFFFFFFFU;
+
+ for (page_index = pEraseInit->Page; page_index < (pEraseInit->Page + pEraseInit->NbPages); page_index++)
+ {
+ FLASH_PageErase(page_index, pEraseInit->Banks);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
+
+ if (status != HAL_OK)
+ {
+ /* In case of error, stop erase procedure and return the faulty page */
+ *PageError = page_index;
+ break;
+ }
+ }
+ }
+
+ /* If the erase operation is completed, disable the associated bits */
+ CLEAR_BIT((*reg_cr), (pEraseInit->TypeErase) & (~(FLASH_NON_SECURE_MASK)));
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+
+ return status;
+}
+
+/**
+ * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.
+ * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
+ * contains the configuration information for the erasing.
+ *
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
+{
+ HAL_StatusTypeDef status;
+ __IO uint32_t *reg_cr;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Reset error code */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
+
+ if (status != HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+ }
+ else
+ {
+ /* Set internal variables used by the IRQ handler */
+ pFlash.ProcedureOnGoing = pEraseInit->TypeErase;
+ pFlash.Bank = pEraseInit->Banks;
+
+ /* Access to SECCR or NSCR depends on operation type */
+ reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH->NSCR);
+
+ /* Enable End of Operation and Error interrupts */
+ (*reg_cr) |= (FLASH_IT_EOP | FLASH_IT_OPERR);
+
+ if ((pEraseInit->TypeErase & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEERASE_MASSERASE)
+ {
+ /* Mass erase to be done */
+ FLASH_MassErase(pEraseInit->Banks);
+ }
+ else
+ {
+ /* Erase by page to be done */
+ pFlash.NbPagesToErase = pEraseInit->NbPages;
+ pFlash.Page = pEraseInit->Page;
+
+ /* Erase first page and wait for IT */
+ FLASH_PageErase(pEraseInit->Page, pEraseInit->Banks);
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Program Option bytes.
+ * @param pOBInit pointer to an FLASH_OBInitStruct structure that
+ * contains the configuration information for the programming.
+ *
+ * @note To configure any option bytes, the option lock bit OPTLOCK must be
+ * cleared with the call of HAL_FLASH_OB_Unlock() function.
+ * @note New option bytes configuration will be taken into account in two cases:
+ * - after an option bytes launch through the call of HAL_FLASH_OB_Launch()
+ * - after a power reset (BOR reset or exit from Standby/Shutdown modes)
+ *
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check the parameters */
+ assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Reset error code */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
+
+ if (status == HAL_OK)
+ {
+ /* Write protection configuration */
+ if ((pOBInit->OptionType & OPTIONBYTE_WRP) != 0U)
+ {
+ /* Configure of Write protection on the selected area */
+ FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset, pOBInit->WRPLock);
+ }
+
+ /* Read protection configuration */
+ if ((pOBInit->OptionType & OPTIONBYTE_RDP) != 0U)
+ {
+ /* Configure the Read protection level */
+ FLASH_OB_RDPConfig(pOBInit->RDPLevel);
+ }
+
+ /* Read protection key configuration */
+ if ((pOBInit->OptionType & OPTIONBYTE_RDPKEY) != 0U)
+ {
+ /* Configure the Read protection key */
+ FLASH_OB_RDPKeyConfig(pOBInit->RDPKeyType, pOBInit->RDPKey1, pOBInit->RDPKey2);
+ }
+
+ /* User Configuration */
+ if ((pOBInit->OptionType & OPTIONBYTE_USER) != 0U)
+ {
+ /* Configure the user option bytes */
+ FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig);
+ }
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ /* Watermark secure configuration */
+ if ((pOBInit->OptionType & OPTIONBYTE_WMSEC) != 0U)
+ {
+ /* Configure the watermark-based secure area */
+ FLASH_OB_WMSECConfig(pOBInit->WMSecConfig, pOBInit->WMSecStartPage, pOBInit->WMSecEndPage,
+ pOBInit->WMHDPEndPage);
+ }
+
+ /* Unique boot entry point configuration */
+ if ((pOBInit->OptionType & OPTIONBYTE_BOOT_LOCK) != 0U)
+ {
+ /* Configure the unique boot entry point */
+ FLASH_OB_BootLockConfig(pOBInit->BootLock);
+ }
+#endif /* __ARM_FEATURE_CMSE */
+
+ /* Boot address configuration */
+ if ((pOBInit->OptionType & OPTIONBYTE_BOOTADDR) != 0U)
+ {
+ /* Configure the boot address */
+ FLASH_OB_BootAddrConfig(pOBInit->BootAddrConfig, pOBInit->BootAddr);
+ }
+
+ /* Set OPTSTRT Bit */
+ SET_BIT(FLASH->NSCR, FLASH_NSCR_OPTSTRT);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+
+ return status;
+}
+
+/**
+ * @brief Get the Option bytes configuration.
+ * @param pOBInit pointer to an FLASH_OBInitStruct structure that contains the
+ * configuration information.
+ * @note The fields pOBInit->WRPArea, pOBInit->WMSecConfig and pOBInit->BootAddrConfig
+ * should indicate which area/address is requested for the WRP, WM Security or
+ * Boot Address, else no information will be returned
+ *
+ * @retval None
+ */
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
+{
+ pOBInit->OptionType = (OPTIONBYTE_RDP | OPTIONBYTE_USER);
+
+ if ((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB) ||
+ (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAB))
+ {
+ pOBInit->OptionType |= OPTIONBYTE_WRP;
+ /* Get write protection on the selected area */
+ FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset), &(pOBInit->WRPLock));
+ }
+
+ /* Get Read protection level */
+ pOBInit->RDPLevel = FLASH_OB_GetRDP();
+
+ /* Get the user option bytes */
+ pOBInit->USERConfig = FLASH_OB_GetUser();
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ /* Get the configuration of the watermark secure area for the selected area */
+ if ((pOBInit->WMSecConfig == OB_WMSEC_AREA1) || (pOBInit->WMSecConfig == OB_WMSEC_AREA2))
+ {
+ pOBInit->OptionType |= OPTIONBYTE_WMSEC;
+ FLASH_OB_GetWMSEC(&(pOBInit->WMSecConfig), &(pOBInit->WMSecStartPage), &(pOBInit->WMSecEndPage),
+ &(pOBInit->WMHDPEndPage));
+ }
+
+ pOBInit->OptionType |= OPTIONBYTE_BOOT_LOCK;
+
+ /* Get the configuration of the unique boot entry point */
+ pOBInit->BootLock = FLASH_OB_GetBootLock();
+#endif /* __ARM_FEATURE_CMSE */
+
+ /* Get the value of the selected boot address */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ if ((pOBInit->BootAddrConfig == OB_BOOTADDR_NS0) || (pOBInit->BootAddrConfig == OB_BOOTADDR_NS1) ||
+ (pOBInit->BootAddrConfig == OB_BOOTADDR_SEC0))
+#else
+ if ((pOBInit->BootAddrConfig == OB_BOOTADDR_NS0) || (pOBInit->BootAddrConfig == OB_BOOTADDR_NS1))
+#endif /* __ARM_FEATURE_CMSE */
+ {
+ pOBInit->OptionType |= OPTIONBYTE_BOOTADDR;
+ FLASH_OB_GetBootAddr(pOBInit->BootAddrConfig, &(pOBInit->BootAddr));
+ }
+}
+
+/**
+ * @brief Configure the block-based secure area.
+ *
+ * @param pBBAttributes pointer to an FLASH_BBAttributesTypeDef structure that
+ * contains the configuration information for the programming.
+ *
+ * @note The field pBBAttributes->Bank should indicate which area is requested
+ * for the block-based attributes.
+ * @note The field pBBAttributes->BBAttributesType should indicate which
+ * block-base attribute type is requested: Secure or Privilege.
+ *
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASHEx_ConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes)
+{
+ HAL_StatusTypeDef status;
+ uint8_t index;
+ __IO uint32_t *reg;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_BANK_EXCLUSIVE(pBBAttributes->Bank));
+ assert_param(IS_FLASH_BB_EXCLUSIVE(pBBAttributes->BBAttributesType));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
+
+ if (status == HAL_OK)
+ {
+ /* Set the first Block-Based register to write */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ if (pBBAttributes->BBAttributesType == FLASH_BB_SEC)
+ {
+ if (pBBAttributes->Bank == FLASH_BANK_1)
+ {
+ reg = &(FLASH->SECBB1R1);
+ }
+ else
+ {
+ reg = &(FLASH->SECBB2R1);
+ }
+ }
+ else
+#endif /* __ARM_FEATURE_CMSE */
+ {
+ if (pBBAttributes->Bank == FLASH_BANK_1)
+ {
+ reg = &(FLASH->PRIVBB1R1);
+ }
+ else
+ {
+ reg = &(FLASH->PRIVBB2R1);
+ }
+ }
+
+ /* Modify the register values and check that new attributes are taken in account */
+ for (index = 0; index < FLASH_BLOCKBASED_NB_REG; index++)
+ {
+ *reg = pBBAttributes->BBAttributes_array[index];
+ if ((*reg) != pBBAttributes->BBAttributes_array[index])
+ {
+ status = HAL_ERROR;
+ }
+ reg++;
+ }
+
+ /* ISB instruction is called to be sure next instructions are performed with correct attributes */
+ __ISB();
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+
+ return status;
+}
+
+/**
+ * @brief Return the block-based attributes.
+ *
+ * @param pBBAttributes [in/out] pointer to an FLASH_BBAttributesTypeDef structure
+ * that contains the configuration information.
+ * @note The field pBBAttributes->Bank should indicate which area is requested
+ * for the block-based attributes.
+ * @note The field pBBAttributes->BBAttributesType should indicate which
+ * block-base attribute type is requested: Secure or Privilege.
+ *
+ * @retval None
+ */
+void HAL_FLASHEx_GetConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes)
+{
+ uint8_t index;
+ __IO uint32_t *reg;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_BANK_EXCLUSIVE(pBBAttributes->Bank));
+ assert_param(IS_FLASH_BB_EXCLUSIVE(pBBAttributes->BBAttributesType));
+
+ /* Set the first Block-Based register to read */
+ if (pBBAttributes->BBAttributesType == FLASH_BB_SEC)
+ {
+ if (pBBAttributes->Bank == FLASH_BANK_1)
+ {
+ reg = &(FLASH->SECBB1R1);
+ }
+ else
+ {
+ reg = &(FLASH->SECBB2R1);
+ }
+ }
+ else
+ {
+ if (pBBAttributes->Bank == FLASH_BANK_1)
+ {
+ reg = &(FLASH->PRIVBB1R1);
+ }
+ else
+ {
+ reg = &(FLASH->PRIVBB2R1);
+ }
+ }
+
+ /* Read the register values */
+ for (index = 0; index < FLASH_BLOCKBASED_NB_REG; index++)
+ {
+ pBBAttributes->BBAttributes_array[index] = (*reg);
+ reg++;
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ * @brief Activation of the protection of the secure hide area.
+ *
+ * @param Banks indicate the bank concerned by the activation
+ * This parameter can be one of the following values:
+ * @arg FLASH_BANK_1: Bank1 to be protected
+ * @arg FLASH_BANK_2: Bank2 to be protected
+ * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be protected
+ *
+ * @retval None
+ */
+void HAL_FLASHEx_EnableSecHideProtection(uint32_t Banks)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_BANK(Banks));
+
+ if ((Banks & FLASH_BANK_1) != 0U)
+ {
+ SET_BIT(FLASH->SECHDPCR, FLASH_SECHDPCR_HDP1_ACCDIS);
+ }
+
+ if ((Banks & FLASH_BANK_2) != 0U)
+ {
+ SET_BIT(FLASH->SECHDPCR, FLASH_SECHDPCR_HDP2_ACCDIS);
+ }
+}
+#endif /* __ARM_FEATURE_CMSE */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASHEx_Exported_Functions_Group2 FLASHEx Exported Functions Group2
+ * @{
+ */
+
+/**
+ * @brief Configuration of the privilege attribute.
+ *
+ * @param PrivMode indicate privilege mode configuration
+ * This parameter can be one of the following values:
+ * @arg FLASH_SPRIV_GRANTED: access to secure Flash registers is granted to privileged
+ * or unprivileged access
+ * @arg FLASH_SPRIV_DENIED: access to secure Flash registers is denied
+ * to unprivileged access
+ * @arg FLASH_NSPRIV_GRANTED: access to non-secure Flash registers is granted to privileged
+ * or unprivileged access
+ * @arg FLASH_NSPRIV_DENIED: access to non-secure Flash registers is denied
+ * to unprivilege access
+ *
+ * @retval None
+ */
+void HAL_FLASHEx_ConfigPrivMode(uint32_t PrivMode)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_CFGPRIVMODE(PrivMode));
+
+ MODIFY_REG(FLASH->PRIVCFGR, (FLASH_PRIVCFGR_SPRIV | FLASH_PRIVCFGR_NSPRIV), PrivMode);
+}
+
+/**
+ * @brief Return the value of the privilege attribute.
+ *
+ * @retval It indicates the privilege mode configuration.
+ * This return value can be one of the following values:
+ * @arg FLASH_SPRIV_GRANTED: access to secure Flash registers is granted to privileged
+ * or unprivileged access
+ * @arg FLASH_SPRIV_DENIED: access to secure Flash registers is denied
+ * to unprivileged access
+ * @arg FLASH_NSPRIV_GRANTED: access to non-secure Flash registers is granted to privileged
+ * or unprivileged access
+ * @arg FLASH_NSPRIV_DENIED: access to Flash registers is denied
+ * to unprivilege accessP
+ */
+uint32_t HAL_FLASHEx_GetPrivMode(void)
+{
+ return (FLASH->PRIVCFGR & (FLASH_PRIVCFGR_SPRIV | FLASH_PRIVCFGR_NSPRIV));
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ * @brief Configuration of the security inversion.
+ *
+ * @param SecInvState indicate the flash security state configuration
+ * This parameter can be one of the following values:
+ * @arg FLASH_SEC_INV_DISABLE: Security state of Flash is not inverted
+ * @arg FLASH_SEC_INV_ENABLE: Security state of Flash is inverted
+ *
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASHEx_ConfigSecInversion(uint32_t SecInvState)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_CFGSECINV(SecInvState));
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
+
+ if (status == HAL_OK)
+ {
+ MODIFY_REG(FLASH->SECCR, FLASH_SECCR_INV, SecInvState);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+
+ return status;
+}
+
+/**
+ * @brief Return the value of the security inversion.
+ *
+ * @retval It indicates the flash security state configuration
+ * This return value can be one of the following values:
+ * @arg FLASH_SEC_INV_DISABLE: Security state of Flash is not inverted
+ * @arg FLASH_SEC_INV_ENABLE: Security state of Flash is inverted
+ */
+uint32_t HAL_FLASHEx_GetSecInversion(void)
+{
+ return (FLASH->SECCR & FLASH_SECCR_INV);
+}
+#endif /* __ARM_FEATURE_CMSE */
+
+/**
+ * @brief Enable the Power-down Mode for Flash Banks
+ * @param Banks indicate which bank to put in power-down mode
+ * This parameter can be one of the following values:
+ * @arg FLASH_BANK_1: Flash Bank 1
+ * @arg FLASH_BANK_2: Flash Bank 2
+ * @arg FLASH_BANK_BOTH: Flash Bank 1 and Bank 2
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASHEx_EnablePowerDown(uint32_t Banks)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tickstart;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_BANK(Banks));
+
+ /* Request power-down mode for Bank 1 */
+ if ((Banks & FLASH_BANK_1) != 0U)
+ {
+ /* Check PD1 and PDREQ1 bits (Bank 1 is not in power-down mode and not being
+ already under power-down request) */
+ if ((FLASH->NSSR & FLASH_NSSR_PD1) != 0U)
+ {
+ status = HAL_ERROR;
+ }
+ else if ((FLASH->ACR & FLASH_ACR_PDREQ1) != 0U)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Unlock PDREQ1 bit */
+ WRITE_REG(FLASH->PDKEY1R, FLASH_PDKEY1_1);
+ WRITE_REG(FLASH->PDKEY1R, FLASH_PDKEY1_2);
+
+ /* Set PDREQ1 in FLASH_ACR register */
+ SET_BIT(FLASH->ACR, FLASH_ACR_PDREQ1);
+
+ /* Check PD1 bit */
+ tickstart = HAL_GetTick();
+ while (((FLASH->NSSR & FLASH_NSSR_PD1) != FLASH_NSSR_PD1))
+ {
+ if ((HAL_GetTick() - tickstart) > FLASH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Request power-down mode for Bank 2 */
+ if ((Banks & FLASH_BANK_2) != 0U)
+ {
+ /* Check PD2 and PDREQ2 bits (Bank 2 is not in power-down mode and not being
+ already under power-down request) */
+ if ((FLASH->NSSR & FLASH_NSSR_PD2) != 0U)
+ {
+ status = HAL_ERROR;
+ }
+ else if ((FLASH->ACR & FLASH_ACR_PDREQ2) != 0U)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Unlock PDREQ2 bit */
+ WRITE_REG(FLASH->PDKEY2R, FLASH_PDKEY2_1);
+ WRITE_REG(FLASH->PDKEY2R, FLASH_PDKEY2_2);
+
+ /* Set PDREQ2 in FLASH_ACR register */
+ SET_BIT(FLASH->ACR, FLASH_ACR_PDREQ2);
+
+ /* Check PD2 bit */
+ tickstart = HAL_GetTick();
+ while (((FLASH->NSSR & FLASH_NSSR_PD2) != FLASH_NSSR_PD2))
+ {
+ if ((HAL_GetTick() - tickstart) > FLASH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Configuration of the Low-Power read Mode.
+ *
+ * @param ConfigLPM indicate the Low-Power read Mode configuration.
+ * This parameter can be one of the following values:
+ * @arg FLASH_LPM_ENABLE: Flash is in low-power read mode
+ * @arg FLASH_LPM_DISABLE: Flash is in normal read mode
+ *
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASHEx_ConfigLowPowerRead(uint32_t ConfigLPM)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_CFGLPM(ConfigLPM));
+
+ /* Set LPM Bit in FLASH_ACR register */
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LPM, ConfigLPM);
+
+ /* Check that low power read mode has been activated */
+ if (READ_BIT(FLASH->ACR, FLASH_ACR_LPM) != ConfigLPM)
+ {
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Return the value of the Low-Power read Mode.
+ *
+ * @retval It indicates the flash low-power read mode configuration
+ * This return value can be one of the following values:
+ * @arg FLASH_LPM_ENABLE: Flash is in low-power read mode
+ * @arg FLASH_LPM_DISABLE: Flash is in normal read mode
+ */
+uint32_t HAL_FLASHEx_GetLowPowerRead(void)
+{
+ return (FLASH->ACR & FLASH_ACR_LPM);
+}
+
+/**
+ * @brief Return the on-going Flash Operation. After a system reset, return
+ * the interrupted Flash operation, if any.
+ * @param pFlashOperation [out] pointer to a FLASH_OperationTypeDef structure
+ * that contains the Flash operation information.
+ *
+ * @retval None
+ */
+void HAL_FLASHEx_GetOperation(FLASH_OperationTypeDef *pFlashOperation)
+{
+ uint32_t opsr_reg = FLASH->OPSR;
+
+ /* Get Flash operation Type */
+ pFlashOperation->OperationType = opsr_reg & FLASH_OPSR_CODE_OP;
+
+ /* Get Flash operation memory */
+ pFlashOperation->FlashArea = opsr_reg & (FLASH_OPSR_SYSF_OP | FLASH_OPSR_BK_OP);
+
+ /* Get Flash operation address */
+ pFlashOperation->Address = opsr_reg & FLASH_OPSR_ADDR_OP;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @addtogroup FLASHEx_Private_Functions
+ * @{
+ */
+/**
+ * @brief Mass erase of FLASH memory.
+ * @param Banks Banks to be erased
+ * This parameter can be one of the following values:
+ * @arg FLASH_BANK_1: Bank1 to be erased
+ * @arg FLASH_BANK_2: Bank2 to be erased
+ * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
+ * @retval None
+ */
+static void FLASH_MassErase(uint32_t Banks)
+{
+ __IO uint32_t *reg_cr;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_BANK(Banks));
+
+ /* Access to SECCR or NSCR registers depends on operation type */
+ reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR);
+
+ /* Set the Mass Erase Bit for the bank 1 and proceed to erase */
+ if ((Banks & FLASH_BANK_1) != 0U)
+ {
+ SET_BIT((*reg_cr), FLASH_NSCR_MER1 | FLASH_NSCR_STRT);
+ }
+
+ /* Set the Mass Erase Bit for the bank 2 and proceed to erase */
+ if ((Banks & FLASH_BANK_2) != 0U)
+ {
+ SET_BIT((*reg_cr), FLASH_NSCR_MER2 | FLASH_NSCR_STRT);
+ }
+}
+
+/**
+ * @brief Erase the specified FLASH memory page.
+ * @param Page FLASH page to erase
+ * This parameter must be a value between 0 and (max number of pages in the bank - 1)
+ * @param Banks Bank(s) where the page will be erased
+ * This parameter can be one of the following values:
+ * @arg FLASH_BANK_1: Page in bank 1 to be erased
+ * @arg FLASH_BANK_2: Page in bank 2 to be erased
+ * @retval None
+ */
+void FLASH_PageErase(uint32_t Page, uint32_t Banks)
+{
+ __IO uint32_t *reg_cr;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_PAGE(Page));
+ assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks));
+
+ /* Access to SECCR or NSCR registers depends on operation type */
+ reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR);
+
+ if ((Banks & FLASH_BANK_1) != 0U)
+ {
+ CLEAR_BIT((*reg_cr), FLASH_NSCR_BKER);
+ }
+ else
+ {
+ SET_BIT((*reg_cr), FLASH_NSCR_BKER);
+ }
+
+ /* Proceed to erase the page */
+ MODIFY_REG((*reg_cr), (FLASH_NSCR_PNB | FLASH_NSCR_PER | FLASH_NSCR_STRT), \
+ ((Page << FLASH_NSCR_PNB_Pos) | FLASH_NSCR_PER | FLASH_NSCR_STRT));
+}
+
+/**
+ * @brief Configure the write protection of the desired pages.
+ *
+ * @note When the memory read protection level is selected (RDP level = 1),
+ * it is not possible to program or erase Flash memory if the CPU debug
+ * features are connected (JTAG or single wire) or boot code is being
+ * executed from RAM or System flash, even if WRP is not activated.
+ * @note To configure the WRP options, the option lock bit OPTLOCK must be
+ * cleared with the call of the HAL_FLASH_OB_Unlock() function.
+ * @note To validate the WRP options, the option bytes must be reloaded
+ * through the call of the HAL_FLASH_OB_Launch() function.
+ *
+ * @param WRPArea specifies the area to be configured.
+ * This parameter can be one of the following values:
+ * @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A
+ * @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B
+ * @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A
+ * @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B
+ *
+ * @param WRPStartOffset specifies the start page of the write protected area
+ * This parameter can be page number between 0 and (max number of pages in the bank - 1)
+ *
+ * @param WRPEndOffset specifies the end page of the write protected area
+ * This parameter can be page number between WRPStartOffset and (max number of pages in the bank - 1)
+ *
+ * @param WRPLock enables the lock of the write protected area
+ * This parameter can be set to ENABLE or DISABLE
+ *
+ * @retval None
+ */
+static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRPEndOffset,
+ FunctionalState WRPLock)
+{
+ /* Check the parameters */
+ assert_param(IS_OB_WRPAREA(WRPArea));
+ assert_param(IS_FLASH_PAGE(WRPStartOffset));
+ assert_param(IS_FLASH_PAGE(WRPEndOffset));
+ assert_param(IS_FUNCTIONAL_STATE(WRPLock));
+
+ /* Configure the write protected area */
+ if (WRPArea == OB_WRPAREA_BANK1_AREAA)
+ {
+ FLASH->WRP1AR = (((uint32_t)(~WRPLock) << FLASH_WRP1AR_UNLOCK_Pos) | \
+ (WRPEndOffset << FLASH_WRP1AR_WRP1A_PEND_Pos) | \
+ WRPStartOffset);
+ }
+ else if (WRPArea == OB_WRPAREA_BANK1_AREAB)
+ {
+ FLASH->WRP1BR = (((uint32_t)(~WRPLock) << FLASH_WRP1BR_UNLOCK_Pos) | \
+ (WRPEndOffset << FLASH_WRP1BR_WRP1B_PEND_Pos) | \
+ WRPStartOffset);
+ }
+ else if (WRPArea == OB_WRPAREA_BANK2_AREAA)
+ {
+ FLASH->WRP2AR = (((uint32_t)(~WRPLock) << FLASH_WRP2AR_UNLOCK_Pos) | \
+ (WRPEndOffset << FLASH_WRP2AR_WRP2A_PEND_Pos) | \
+ WRPStartOffset);
+ }
+ else if (WRPArea == OB_WRPAREA_BANK2_AREAB)
+ {
+ FLASH->WRP2BR = (((uint32_t)(~WRPLock) << FLASH_WRP2BR_UNLOCK_Pos) | \
+ (WRPEndOffset << FLASH_WRP2BR_WRP2B_PEND_Pos) | \
+ WRPStartOffset);
+ }
+ else
+ {
+ /* Empty statement (to be compliant MISRA 15.7) */
+ }
+}
+
+/**
+ * @brief Set the read protection level.
+ *
+ * @note To configure the RDP level, the option lock bit OPTLOCK must be
+ * cleared with the call of the HAL_FLASH_OB_Unlock() function.
+ * @note To validate the RDP level, the option bytes must be reloaded
+ * through the call of the HAL_FLASH_OB_Launch() function.
+ * @note !!! Warning : When enabling OB_RDP level 2 it's no more possible
+ * to go back to other levels !!!
+ *
+ * @param RDPLevel specifies the read protection level.
+ * This parameter can be one of the following values:
+ * @arg OB_RDP_LEVEL_0: No protection
+ * @arg OB_RDP_LEVEL_0_5: No debug access to secure area
+ * @arg OB_RDP_LEVEL_1: Read protection of the memory
+ * @arg OB_RDP_LEVEL_2: Full chip protection
+ *
+ * @retval None
+ */
+static void FLASH_OB_RDPConfig(uint32_t RDPLevel)
+{
+ /* Check the parameters */
+ assert_param(IS_OB_RDP_LEVEL(RDPLevel));
+
+ /* Configure the RDP level in the option bytes register */
+ MODIFY_REG(FLASH->OPTR, FLASH_OPTR_RDP, RDPLevel);
+}
+
+/**
+ * @brief Set the read protection key.
+ * @param RDPKeyType specifies the read protection key type.
+ * This parameter can be one of the following values:
+ * @arg OB_RDP_KEY_OEM1: OEM1 key
+ * @arg OB_RDP_KEY_OEM2: OEM2 key
+ * @param RDPKey1 specifies the RDP key 1.
+ * @param RDPKey2 specifies the RDP key 2.
+ * @retval None
+ */
+static void FLASH_OB_RDPKeyConfig(uint32_t RDPKeyType, uint32_t RDPKey1, uint32_t RDPKey2)
+{
+ /* Check the parameters */
+ assert_param(IS_OB_RDP_KEY_TYPE(RDPKeyType));
+
+ /* Configure the RDP OEM key */
+ if (RDPKeyType == OB_RDP_KEY_OEM1)
+ {
+ WRITE_REG(FLASH->OEM1KEYR1, RDPKey1);
+ WRITE_REG(FLASH->OEM1KEYR2, RDPKey2);
+ }
+ else
+ {
+ WRITE_REG(FLASH->OEM2KEYR1, RDPKey1);
+ WRITE_REG(FLASH->OEM2KEYR2, RDPKey2);
+ }
+}
+
+/**
+ * @brief Program the FLASH User Option Byte.
+ *
+ * @note To configure the user option bytes, the option lock bit OPTLOCK must
+ * be cleared with the call of the HAL_FLASH_OB_Unlock() function.
+ * @note To validate the user option bytes, the option bytes must be reloaded
+ * through the call of the HAL_FLASH_OB_Launch() function.
+ * @param UserType: The FLASH User Option Bytes to be modified.
+ * This parameter can be a combination of @ref FLASH_OB_USER_Type
+ * @param UserConfig The selected User Option Bytes values.
+ * This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,
+ * @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
+ * @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM134_RST,
+ * @ref FLASH_OB_USER_IWDG_SW, @ref FLASH_OB_USER_IWDG_STOP,
+ * @ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_WWDG_SW,
+ * @ref OB_USER_SWAP_BANK, @ref FLASH_OB_USER_DUALBANK,
+ * @ref FLASH_OB_USER_BKPRAM_RST, @ref FLASH_OB_USER_SRAM3_ECC,
+ * @ref FLASH_OB_USER_SRAM2_ECC, @ref FLASH_OB_USER_SRAM2_RST,
+ * @ref FLASH_OB_USER_nSWBOOT0, @ref FLASH_OB_USER_nBOOT0,
+ * @ref FLASH_OB_USER_PA15_PUPEN, @ref FLASH_OB_USER_IO_VDD_HSLV,
+ * @ref FLASH_OB_USER_IO_VDDIO2_HSLV and @ref OB_USER_TZEN
+ * @retval None
+ */
+static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)
+{
+ uint32_t optr_reg_val = 0;
+ uint32_t optr_reg_mask = 0;
+
+ /* Check the parameters */
+ assert_param(IS_OB_USER_TYPE(UserType));
+
+ if ((UserType & OB_USER_BOR_LEV) != 0U)
+ {
+ /* BOR level option byte should be modified */
+ assert_param(IS_OB_USER_BOR_LEVEL(UserConfig & FLASH_OPTR_BOR_LEV));
+
+ /* Set value and mask for BOR level option byte */
+ optr_reg_val |= (UserConfig & FLASH_OPTR_BOR_LEV);
+ optr_reg_mask |= FLASH_OPTR_BOR_LEV;
+ }
+
+ if ((UserType & OB_USER_NRST_STOP) != 0U)
+ {
+ /* nRST_STOP option byte should be modified */
+ assert_param(IS_OB_USER_STOP(UserConfig & FLASH_OPTR_nRST_STOP));
+
+ /* Set value and mask for nRST_STOP option byte */
+ optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STOP);
+ optr_reg_mask |= FLASH_OPTR_nRST_STOP;
+ }
+
+ if ((UserType & OB_USER_NRST_STDBY) != 0U)
+ {
+ /* nRST_STDBY option byte should be modified */
+ assert_param(IS_OB_USER_STANDBY(UserConfig & FLASH_OPTR_nRST_STDBY));
+
+ /* Set value and mask for nRST_STDBY option byte */
+ optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STDBY);
+ optr_reg_mask |= FLASH_OPTR_nRST_STDBY;
+ }
+
+ if ((UserType & OB_USER_NRST_SHDW) != 0U)
+ {
+ /* nRST_SHDW option byte should be modified */
+ assert_param(IS_OB_USER_SHUTDOWN(UserConfig & FLASH_OPTR_nRST_SHDW));
+
+ /* Set value and mask for nRST_SHDW option byte */
+ optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_SHDW);
+ optr_reg_mask |= FLASH_OPTR_nRST_SHDW;
+ }
+
+ if ((UserType & OB_USER_SRAM134_RST) != 0U)
+ {
+ /* SRAM134_RST option byte should be modified */
+ assert_param(IS_OB_USER_SRAM134_RST(UserConfig & FLASH_OPTR_SRAM134_RST));
+
+ /* Set value and mask for SRAM134_RST option byte */
+ optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM134_RST);
+ optr_reg_mask |= FLASH_OPTR_SRAM134_RST;
+ }
+
+ if ((UserType & OB_USER_IWDG_SW) != 0U)
+ {
+ /* IWDG_SW option byte should be modified */
+ assert_param(IS_OB_USER_IWDG(UserConfig & FLASH_OPTR_IWDG_SW));
+
+ /* Set value and mask for IWDG_SW option byte */
+ optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_SW);
+ optr_reg_mask |= FLASH_OPTR_IWDG_SW;
+ }
+
+ if ((UserType & OB_USER_IWDG_STOP) != 0U)
+ {
+ /* IWDG_STOP option byte should be modified */
+ assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTR_IWDG_STOP));
+
+ /* Set value and mask for IWDG_STOP option byte */
+ optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STOP);
+ optr_reg_mask |= FLASH_OPTR_IWDG_STOP;
+ }
+
+ if ((UserType & OB_USER_IWDG_STDBY) != 0U)
+ {
+ /* IWDG_STDBY option byte should be modified */
+ assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTR_IWDG_STDBY));
+
+ /* Set value and mask for IWDG_STDBY option byte */
+ optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STDBY);
+ optr_reg_mask |= FLASH_OPTR_IWDG_STDBY;
+ }
+
+ if ((UserType & OB_USER_WWDG_SW) != 0U)
+ {
+ /* WWDG_SW option byte should be modified */
+ assert_param(IS_OB_USER_WWDG(UserConfig & FLASH_OPTR_WWDG_SW));
+
+ /* Set value and mask for WWDG_SW option byte */
+ optr_reg_val |= (UserConfig & FLASH_OPTR_WWDG_SW);
+ optr_reg_mask |= FLASH_OPTR_WWDG_SW;
+ }
+
+ if ((UserType & OB_USER_SWAP_BANK) != 0U)
+ {
+ /* SWAP_BANK option byte should be modified */
+ assert_param(IS_OB_USER_SWAP_BANK(UserConfig & FLASH_OPTR_SWAP_BANK));
+
+ /* Set value and mask for SWAP_BANK option byte */
+ optr_reg_val |= (UserConfig & FLASH_OPTR_SWAP_BANK);
+ optr_reg_mask |= FLASH_OPTR_SWAP_BANK;
+ }
+
+ if ((UserType & OB_USER_DUALBANK) != 0U)
+ {
+ /* DUALBANK option byte should be modified */
+ assert_param(IS_OB_USER_DUALBANK(UserConfig & FLASH_OPTR_DUALBANK));
+
+ /* Set value and mask for DUALBANK option byte */
+ optr_reg_val |= (UserConfig & FLASH_OPTR_DUALBANK);
+ optr_reg_mask |= FLASH_OPTR_DUALBANK;
+ }
+
+ if ((UserType & OB_USER_BKPRAM_ECC) != 0U)
+ {
+ /* BKPRAM_ECC option byte should be modified */
+ assert_param(IS_OB_USER_BKPRAM_ECC(UserConfig & FLASH_OPTR_BKPRAM_ECC));
+
+ /* Set value and mask for BKPRAM_ECC option byte */
+ optr_reg_val |= (UserConfig & FLASH_OPTR_BKPRAM_ECC);
+ optr_reg_mask |= FLASH_OPTR_BKPRAM_ECC;
+ }
+
+ if ((UserType & OB_USER_SRAM3_ECC) != 0U)
+ {
+ /* SRAM3_ECC option byte should be modified */
+ assert_param(IS_OB_USER_SRAM3_ECC(UserConfig & FLASH_OPTR_SRAM3_ECC));
+
+ /* Set value and mask for SRAM3_ECC option byte */
+ optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM3_ECC);
+ optr_reg_mask |= FLASH_OPTR_SRAM3_ECC;
+ }
+
+ if ((UserType & OB_USER_SRAM2_ECC) != 0U)
+ {
+ /* SRAM2_ECC option byte should be modified */
+ assert_param(IS_OB_USER_SRAM2_ECC(UserConfig & FLASH_OPTR_SRAM2_ECC));
+
+ /* Set value and mask for SRAM2_ECC option byte */
+ optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_ECC);
+ optr_reg_mask |= FLASH_OPTR_SRAM2_ECC;
+ }
+
+ if ((UserType & OB_USER_SRAM2_RST) != 0U)
+ {
+ /* SRAM2_RST option byte should be modified */
+ assert_param(IS_OB_USER_SRAM2_RST(UserConfig & FLASH_OPTR_SRAM2_RST));
+
+ /* Set value and mask for SRAM2_RST option byte */
+ optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_RST);
+ optr_reg_mask |= FLASH_OPTR_SRAM2_RST;
+ }
+
+ if ((UserType & OB_USER_NSWBOOT0) != 0U)
+ {
+ /* nSWBOOT0 option byte should be modified */
+ assert_param(IS_OB_USER_SWBOOT0(UserConfig & FLASH_OPTR_nSWBOOT0));
+
+ /* Set value and mask for nSWBOOT0 option byte */
+ optr_reg_val |= (UserConfig & FLASH_OPTR_nSWBOOT0);
+ optr_reg_mask |= FLASH_OPTR_nSWBOOT0;
+ }
+
+ if ((UserType & OB_USER_NBOOT0) != 0U)
+ {
+ /* nBOOT0 option byte should be modified */
+ assert_param(IS_OB_USER_BOOT0(UserConfig & FLASH_OPTR_nBOOT0));
+
+ /* Set value and mask for nBOOT0 option byte */
+ optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT0);
+ optr_reg_mask |= FLASH_OPTR_nBOOT0;
+ }
+
+ if ((UserType & OB_USER_PA15_PUPEN) != 0U)
+ {
+ /* PA15_PUPEN option byte should be modified */
+ assert_param(IS_OB_USER_PA15_PUPEN(UserConfig & FLASH_OPTR_PA15_PUPEN));
+
+ /* Set value and mask for nBOOT0 option byte */
+ optr_reg_val |= (UserConfig & FLASH_OPTR_PA15_PUPEN);
+ optr_reg_mask |= FLASH_OPTR_PA15_PUPEN;
+ }
+
+ if ((UserType & OB_USER_IO_VDD_HSLV) != 0U)
+ {
+ /* IO_VDD_HSLV option byte should be modified */
+ assert_param(IS_OB_USER_IO_VDD_HSLV(UserConfig & FLASH_OPTR_IO_VDD_HSLV));
+
+ /* Set value and mask for IO_VDD_HSLV option byte */
+ optr_reg_val |= (UserConfig & FLASH_OPTR_IO_VDD_HSLV);
+ optr_reg_mask |= FLASH_OPTR_IO_VDD_HSLV;
+ }
+
+ if ((UserType & OB_USER_IO_VDDIO2_HSLV) != 0U)
+ {
+ /* IO_VDDIO2_HSLV option byte should be modified */
+ assert_param(IS_OB_USER_IO_VDDIO2_HSLV(UserConfig & FLASH_OPTR_IO_VDDIO2_HSLV));
+
+ /* Set value and mask for IO_VDDIO2_HSLV option byte */
+ optr_reg_val |= (UserConfig & FLASH_OPTR_IO_VDDIO2_HSLV);
+ optr_reg_mask |= FLASH_OPTR_IO_VDDIO2_HSLV;
+ }
+
+ if ((UserType & OB_USER_TZEN) != 0U)
+ {
+ /* TZEN option byte should be modified */
+ assert_param(IS_OB_USER_TZEN(UserConfig & FLASH_OPTR_TZEN));
+
+ /* Set value and mask for TZEN option byte */
+ optr_reg_val |= (UserConfig & FLASH_OPTR_TZEN);
+ optr_reg_mask |= FLASH_OPTR_TZEN;
+ }
+
+ /* Configure the option bytes register */
+ MODIFY_REG(FLASH->OPTR, optr_reg_mask, optr_reg_val);
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ * @brief Configure the watermarked-based secure area.
+ *
+ * @param WMSecConfig specifies the area to be configured.
+ * This parameter can be a combination of the following values:
+ * @arg OB_WMSEC_AREA1 or @arg OB_WMSEC_AREA2: Select Flash Secure Area 1 or Area 2
+ * @arg OB_WMSEC_SECURE_AREA_CONFIG: configure Flash Secure Area
+ * @arg OB_WMSEC_HDP_AREA_CONFIG: configure Flash secure hide Area
+ * @arg OB_WMSEC_HDP_AREA_ENABLE: enable secure hide Area in Secure Area
+ * @arg OB_WMSEC_HDP_AREA_DISABLE: disable secure hide Area in Secure Area
+ *
+ * @param WMSecStartPage specifies the start page of the secure area
+ * This parameter can be page number between 0 and (max number of pages in the bank - 1)
+ *
+ * @param WMSecEndPage specifies the end page of the secure area
+ * This parameter can be page number between WMSecStartPage and (max number of pages in the bank - 1)
+ *
+ * @param WMHDPEndPage specifies the end page of the secure hide area
+ * This parameter can be a page number between WMSecStartPage and WMSecEndPage
+ *
+ * @retval None
+ */
+static void FLASH_OB_WMSECConfig(uint32_t WMSecConfig, uint32_t WMSecStartPage, uint32_t WMSecEndPage,
+ uint32_t WMHDPEndPage)
+{
+ uint32_t tmp_secwm1 = 0U;
+ uint32_t tmp_secwm2 = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_OB_WMSEC_CONFIG(WMSecConfig));
+ assert_param(IS_OB_WMSEC_AREA_EXCLUSIVE(WMSecConfig & 0x3U));
+ assert_param(IS_FLASH_PAGE(WMSecStartPage));
+ assert_param(IS_FLASH_PAGE(WMSecEndPage));
+ assert_param(IS_FLASH_PAGE(WMHDPEndPage));
+
+ /* Read SECWM registers */
+ if ((WMSecConfig & OB_WMSEC_AREA1) != 0U)
+ {
+ tmp_secwm1 = FLASH->SECWM1R1;
+ tmp_secwm2 = FLASH->SECWM1R2;
+ }
+ else if ((WMSecConfig & OB_WMSEC_AREA2) != 0U)
+ {
+ tmp_secwm1 = FLASH->SECWM2R1;
+ tmp_secwm2 = FLASH->SECWM2R2;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Configure Secure Area */
+ if ((WMSecConfig & OB_WMSEC_SECURE_AREA_CONFIG) != 0U)
+ {
+ tmp_secwm1 = ((WMSecEndPage << FLASH_SECWM1R1_SECWM1_PEND_Pos) | WMSecStartPage);
+ }
+
+ /* Configure Secure Hide Area */
+ if ((WMSecConfig & OB_WMSEC_HDP_AREA_CONFIG) != 0U)
+ {
+ tmp_secwm2 &= (~FLASH_SECWM1R2_HDP1_PEND);
+ tmp_secwm2 |= (WMHDPEndPage << FLASH_SECWM1R2_HDP1_PEND_Pos);
+ }
+
+ /* Enable Secure Hide Area */
+ if ((WMSecConfig & OB_WMSEC_HDP_AREA_ENABLE) != 0U)
+ {
+ tmp_secwm2 |= FLASH_SECWM1R2_HDP1EN;
+ }
+
+ /* Disable Secure Hide Area */
+ if ((WMSecConfig & OB_WMSEC_HDP_AREA_DISABLE) != 0U)
+ {
+ tmp_secwm2 &= (~FLASH_SECWM1R2_HDP1EN);
+ }
+
+ /* Write SECWM registers */
+ if ((WMSecConfig & OB_WMSEC_AREA1) != 0U)
+ {
+ FLASH->SECWM1R1 = tmp_secwm1;
+ FLASH->SECWM1R2 = tmp_secwm2;
+ }
+ else if ((WMSecConfig & OB_WMSEC_AREA2) != 0U)
+ {
+ FLASH->SECWM2R1 = tmp_secwm1;
+ FLASH->SECWM2R2 = tmp_secwm2;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+}
+
+/**
+ * @brief Configure the boot lock.
+ *
+ * @param BootLockConfig specifies the activation of the BOOT_LOCK.
+ * This parameter can be one of the following values:
+ * @arg OB_BOOT_LOCK_DISABLE: Boot Lock mode deactivated
+ * @arg OB_BOOT_LOCK_ENABLE: Boot Lock mode activated
+ *
+ * @retval None
+ */
+static void FLASH_OB_BootLockConfig(uint32_t BootLockConfig)
+{
+ /* Check the parameters */
+ assert_param(IS_OB_BOOT_LOCK(BootLockConfig));
+
+ /* Configure the option bytes register */
+ MODIFY_REG(FLASH->SECBOOTADD0R, FLASH_SECBOOTADD0R_BOOT_LOCK, BootLockConfig);
+}
+#endif /* __ARM_FEATURE_CMSE */
+
+/**
+ * @brief Configure the boot address.
+ *
+ * @param BootAddrConfig specifies the area to be configured.
+ * This parameter can be one of the following values:
+ * @arg OB_BOOTADDR_NS0: Non-secure boot address 0
+ * @arg OB_BOOTADDR_NS1: Non-secure boot address 1
+ * @arg OB_BOOTADDR_SEC0: Secure boot address 0
+ *
+ * @param BootAddr: specifies the address used for the boot
+ * This parameter can be page number between 0 and 0xFFFFFF00
+ *
+ * @retval None
+ */
+static void FLASH_OB_BootAddrConfig(uint32_t BootAddrConfig, uint32_t BootAddr)
+{
+ /* Check the parameters */
+ assert_param(IS_OB_BOOTADDR_CONFIG(BootAddrConfig));
+
+ if (BootAddrConfig == OB_BOOTADDR_NS0)
+ {
+ FLASH->NSBOOTADD0R = BootAddr;
+ }
+ else if (BootAddrConfig == OB_BOOTADDR_NS1)
+ {
+ FLASH->NSBOOTADD1R = BootAddr;
+ }
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ else if (BootAddrConfig == OB_BOOTADDR_SEC0)
+ {
+ MODIFY_REG(FLASH->SECBOOTADD0R, FLASH_SECBOOTADD0R_SECBOOTADD0, BootAddr);
+ }
+#endif /* __ARM_FEATURE_CMSE */
+ else
+ {
+ /* Empty statement (to be compliant MISRA 15.7) */
+ }
+}
+
+/**
+ * @brief Return the FLASH Write Protection Option Bytes value.
+ *
+ * @param[in] WRPArea specifies the area to be returned.
+ * This parameter can be one of the following values:
+ * @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A
+ * @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B
+ * @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A
+ * @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B
+ *
+ * @param[out] WRPStartOffset specifies the address where to copied the start page
+ * of the write protected area
+ *
+ * @param[out] WRPEndOffset specifies the address where to copied the end page of
+ * the write protected area
+ *
+ * @param[out] WRPLock specifies the lock status of the write protected area.
+ * The returned value can be ENABLE or DISABLE
+ *
+ * @retval None
+ */
+static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRPEndOffset,
+ FunctionalState *WRPLock)
+{
+ /* Get the configuration of the write protected area */
+ if (WRPArea == OB_WRPAREA_BANK1_AREAA)
+ {
+ *WRPStartOffset = READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_PSTRT);
+ *WRPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_PEND) >> FLASH_WRP1AR_WRP1A_PEND_Pos);
+ *WRPLock = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_UNLOCK) != 0U) ? DISABLE : ENABLE;
+ }
+ else if (WRPArea == OB_WRPAREA_BANK1_AREAB)
+ {
+ *WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_PSTRT);
+ *WRPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_PEND) >> FLASH_WRP1BR_WRP1B_PEND_Pos);
+ *WRPLock = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_UNLOCK) != 0U) ? DISABLE : ENABLE;
+ }
+ else if (WRPArea == OB_WRPAREA_BANK2_AREAA)
+ {
+ *WRPStartOffset = READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_PSTRT);
+ *WRPEndOffset = (READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_PEND) >> FLASH_WRP2AR_WRP2A_PEND_Pos);
+ *WRPLock = (READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_UNLOCK) != 0U) ? DISABLE : ENABLE;
+ }
+ else if (WRPArea == OB_WRPAREA_BANK2_AREAB)
+ {
+ *WRPStartOffset = READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_PSTRT);
+ *WRPEndOffset = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_PEND) >> FLASH_WRP2BR_WRP2B_PEND_Pos);
+ *WRPLock = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_UNLOCK) != 0U) ? DISABLE : ENABLE;
+ }
+ else
+ {
+ /* Empty statement (to be compliant MISRA 15.7) */
+ }
+}
+
+/**
+ * @brief Return the FLASH Read Protection level.
+ * @retval FLASH ReadOut Protection Level.
+ * This return value can be one of the following values:
+ * @arg OB_RDP_LEVEL_0: No protection
+ * @arg OB_RDP_LEVEL_0_5: No debug access to secure area
+ * @arg OB_RDP_LEVEL_1: Read protection of the memory
+ * @arg OB_RDP_LEVEL_2: Full chip protection
+ */
+static uint32_t FLASH_OB_GetRDP(void)
+{
+ uint32_t rdp_level = READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP);
+
+ if ((rdp_level != OB_RDP_LEVEL_0) && (rdp_level != OB_RDP_LEVEL_0_5) && (rdp_level != OB_RDP_LEVEL_2))
+ {
+ return (OB_RDP_LEVEL_1);
+ }
+ else
+ {
+ return rdp_level;
+ }
+}
+
+/**
+ * @brief Return the FLASH User Option Byte value.
+ * @retval The FLASH User Option Bytes values.
+ * The return value can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,
+ * @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
+ * @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM134_RST,
+ * @ref FLASH_OB_USER_IWDG_SW, @ref FLASH_OB_USER_IWDG_STOP,
+ * @ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_WWDG_SW,
+ * @ref OB_USER_SWAP_BANK, @ref FLASH_OB_USER_DUALBANK,
+ * @ref FLASH_OB_USER_BKPRAM_RST, @ref FLASH_OB_USER_SRAM3_ECC,
+ * @ref FLASH_OB_USER_SRAM2_ECC, @ref FLASH_OB_USER_SRAM2_RST,
+ * @ref FLASH_OB_USER_nSWBOOT0, @ref FLASH_OB_USER_nBOOT0,
+ * @ref FLASH_OB_USER_PA15_PUPEN, @ref FLASH_OB_USER_IO_VDD_HSLV,
+ * @ref FLASH_OB_USER_IO_VDDIO2_HSLV and @ref OB_USER_TZEN
+ */
+static uint32_t FLASH_OB_GetUser(void)
+{
+ uint32_t user_config = READ_REG(FLASH->OPTR);
+ CLEAR_BIT(user_config, FLASH_OPTR_RDP);
+
+ return user_config;
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ * @brief Return the watermarked-based secure area configuration.
+ *
+ * @param WMSecConfig [in/out] specifies the area to be returned.
+ * This parameter can be one of the following values:
+ * @arg OB_WMSEC_AREA1: select Flash Secure Area 1
+ * @arg OB_WMSEC_AREA2: select Flash Secure Area 2
+ * When return from the function, this parameter will be a combinaison of the following values:
+ * @arg OB_WMSEC_AREAA or @arg OB_WMSEC_AREAB: selected Flash Secure Area A or Area B
+ * @arg OB_WMSEC_HDP_AREA_ENABLE: Secure Hide Area in Secure Area enabled
+ * @arg OB_WMSEC_HDP_AREA_DISABLE: Secure Hide Area in Secure Area disabled
+ *
+ * @param WMSecStartPage [out] specifies the start page of the secure area
+ *
+ * @param WMSecEndPage [out] specifies the end page of the secure area
+ *
+ * @param WMHDPEndPage [out] specifies the end page of the secure hide area
+ *
+ *
+ * @retval None
+ */
+static void FLASH_OB_GetWMSEC(uint32_t *WMSecConfig, uint32_t *WMSecStartPage, uint32_t *WMSecEndPage,
+ uint32_t *WMHDPEndPage)
+{
+ uint32_t tmp_secwm1 = 0U;
+ uint32_t tmp_secwm2 = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_OB_WMSEC_CONFIG(*WMSecConfig));
+ assert_param(IS_FLASH_BANK_EXCLUSIVE((*WMSecConfig) & 0x3U));
+
+ /* Read SECWM registers */
+ if (((*WMSecConfig) & OB_WMSEC_AREA1) != 0U)
+ {
+ tmp_secwm1 = FLASH->SECWM1R1;
+ tmp_secwm2 = FLASH->SECWM1R2;
+ }
+ else if (((*WMSecConfig) & OB_WMSEC_AREA2) != 0U)
+ {
+ tmp_secwm1 = FLASH->SECWM2R1;
+ tmp_secwm2 = FLASH->SECWM2R2;
+ }
+ else
+ {
+ /* Empty statement (to be compliant MISRA 15.7) */
+ }
+
+ /* Configuration of secure area */
+ *WMSecStartPage = (tmp_secwm1 & FLASH_SECWM1R1_SECWM1_PSTRT);
+ *WMSecEndPage = ((tmp_secwm1 & FLASH_SECWM1R1_SECWM1_PEND) >> FLASH_SECWM1R1_SECWM1_PEND_Pos);
+
+ /* Configuration of secure hide area */
+ *WMHDPEndPage = ((tmp_secwm2 & FLASH_SECWM1R2_HDP1_PEND) >> FLASH_SECWM1R2_HDP1_PEND_Pos);
+
+ if ((tmp_secwm2 & FLASH_SECWM1R2_HDP1EN) == 0U)
+ {
+ *WMSecConfig = ((*WMSecConfig) | OB_WMSEC_HDP_AREA_DISABLE);
+ }
+ else
+ {
+ *WMSecConfig = ((*WMSecConfig) | OB_WMSEC_HDP_AREA_ENABLE);
+ }
+
+}
+
+/**
+ * @brief Return the boot lock configuration.
+ *
+ * @retval Value of Boot Lock configuration.
+ * It can be one of the following values:
+ * @arg OB_BOOT_LOCK_DISABLE: Boot Lock mode deactivated
+ * @arg OB_BOOT_LOCK_ENABLE: Boot Lock mode activated
+ */
+static uint32_t FLASH_OB_GetBootLock(void)
+{
+ return (FLASH->SECBOOTADD0R & FLASH_SECBOOTADD0R_BOOT_LOCK);
+}
+#endif /* __ARM_FEATURE_CMSE */
+
+/**
+ * @brief Return the boot address.
+ *
+ * @param[in] BootAddrConfig specifies the area to be returned.
+ * This parameter can be one of the following values:
+ * @arg OB_BOOTADDR_NS0: Non-secure boot address 0
+ * @arg OB_BOOTADDR_NS1: Non-secure boot address 1
+ * @arg OB_BOOTADDR_SEC0: Secure boot address 0
+ *
+ * @param[out] BootAddr specifies the boot address value
+ *
+ * @retval None
+ */
+static void FLASH_OB_GetBootAddr(uint32_t BootAddrConfig, uint32_t *BootAddr)
+{
+ if (BootAddrConfig == OB_BOOTADDR_NS0)
+ {
+ *BootAddr = (FLASH->NSBOOTADD0R & FLASH_NSBOOTADD0R_NSBOOTADD0);
+ }
+ else if (BootAddrConfig == OB_BOOTADDR_NS1)
+ {
+ *BootAddr = (FLASH->NSBOOTADD1R & FLASH_NSBOOTADD1R_NSBOOTADD1);
+ }
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ else if (BootAddrConfig == OB_BOOTADDR_SEC0)
+ {
+ *BootAddr = (FLASH->SECBOOTADD0R & FLASH_SECBOOTADD0R_SECBOOTADD0);
+ }
+#endif /* __ARM_FEATURE_CMSE */
+ else
+ {
+ /* Empty statement (to be compliant MISRA 15.7) */
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_fmac.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_fmac.c
new file mode 100644
index 00000000..b5fde295
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_fmac.c
@@ -0,0 +1,2740 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_fmac.c
+ * @author MCD Application Team
+ * @brief FMAC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the FMAC peripheral:
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ * + Callback functions
+ * + IRQ handler management
+ * + Peripheral State and Error functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ *
+ * @verbatim
+================================================================================
+ ##### How to use this driver #####
+================================================================================
+ [..]
+ The FMAC HAL driver can be used as follows:
+
+ (#) Initialize the FMAC low level resources by implementing the @ref HAL_FMAC_MspInit():
+ (++) Enable the FMAC interface clock using @ref __HAL_RCC_FMAC_CLK_ENABLE().
+ (++) In case of using interrupts (e.g. access configured as FMAC_BUFFER_ACCESS_IT):
+ (+++) Configure the FMAC interrupt priority using @ref HAL_NVIC_SetPriority().
+ (+++) Enable the FMAC IRQ handler using @ref HAL_NVIC_EnableIRQ().
+ (+++) In FMAC IRQ handler, call @ref HAL_FMAC_IRQHandler().
+ (++) In case of using DMA to control data transfer (e.g. access configured
+ as FMAC_BUFFER_ACCESS_DMA):
+ (+++) Enable the DMA interface clock using @ref __HAL_RCC_DMA1_CLK_ENABLE()
+ or @ref __HAL_RCC_DMA2_CLK_ENABLE() depending on the used DMA instance.
+ (+++) Enable the DMAMUX1 interface clock using @ref __HAL_RCC_DMAMUX1_CLK_ENABLE().
+ (+++) If the initialization of the internal buffers (coefficients, input,
+ output) is done via DMA, configure and enable one DMA channel for
+ managing data transfer from memory to memory (preload channel).
+ (+++) If the input buffer is accessed via DMA, configure and enable one
+ DMA channel for managing data transfer from memory to peripheral
+ (input channel).
+ (+++) If the output buffer is accessed via DMA, configure and enable
+ one DMA channel for managing data transfer from peripheral to
+ memory (output channel).
+ (+++) Associate the initialized DMA handle(s) to the FMAC DMA handle(s)
+ using @ref __HAL_LINKDMA().
+ (+++) Configure the priority and enable the NVIC for the transfer complete
+ interrupt on the enabled DMA channel(s) using @ref HAL_NVIC_SetPriority()
+ and @ref HAL_NVIC_EnableIRQ().
+
+ (#) Initialize the FMAC HAL using @ref HAL_FMAC_Init(). This function
+ resorts to @ref HAL_FMAC_MspInit() for low-level initialization.
+
+ (#) Configure the FMAC processing (filter) using @ref HAL_FMAC_FilterConfig()
+ or @ref HAL_FMAC_FilterConfig_DMA().
+ This function:
+ (++) Defines the memory area within the FMAC internal memory
+ (input, coefficients, output) and the associated threshold (input, output).
+ (++) Configures the filter and its parameters:
+ (+++) Finite Impulse Response (FIR) filter (also known as convolution).
+ (+++) Infinite Impulse Response (IIR) filter (direct form 1).
+ (++) Choose the way to access to the input and output buffers: none, polling,
+ DMA, IT. "none" means the input and/or output data will be handled by
+ another IP (ADC, DAC, etc.).
+ (++) Enable the error interruptions in the input access and/or the output
+ access is done through IT/DMA. If an error occurs, the interruption
+ will be triggered in loop. In order to recover, the user will have
+ to reset the IP with the sequence @ref HAL_FMAC_DeInit / @ref HAL_FMAC_Init.
+ Optionally, he can also disable the interrupt using @ref __HAL_FMAC_DISABLE_IT;
+ the error status will be kept, but no more interrupt will be triggered.
+ (++) Write the provided coefficients into the internal memory using polling
+ mode ( @ref HAL_FMAC_FilterConfig() ) or DMA ( @ref HAL_FMAC_FilterConfig_DMA() ).
+ In the DMA case, @ref HAL_FMAC_FilterConfigCallback() is called when
+ the handling is over.
+
+ (#) Optionally, the user can enable the error interruption related to
+ saturation by calling @ref __HAL_FMAC_ENABLE_IT. This helps in debugging the
+ filter. If a saturation occurs, the interruption will be triggered in loop.
+ In order to recover, the user will have to:
+ (++) Disable the interruption by calling @ref __HAL_FMAC_DISABLE_IT if
+ the user wishes to continue all the same.
+ (++) Reset the IP with the sequence @ref HAL_FMAC_DeInit / @ref HAL_FMAC_Init.
+
+ (#) Optionally, preload input (FIR, IIR) and output (IIR) data using
+ @ref HAL_FMAC_FilterPreload() or @ref HAL_FMAC_FilterPreload_DMA().
+ In the DMA case, @ref HAL_FMAC_FilterPreloadCallback() is called when
+ the handling is over.
+ This step is optional as the filter can be started without preloaded
+ data.
+
+ (#) Start the FMAC processing (filter) using @ref HAL_FMAC_FilterStart().
+ This function also configures the output buffer that will be filled from
+ the circular internal output buffer. The function returns immediately
+ without updating the provided buffer. The IP processing will be active until
+ @ref HAL_FMAC_FilterStop() is called.
+
+ (#) If the input internal buffer is accessed via DMA, @ref HAL_FMAC_HalfGetDataCallback()
+ will be called to indicate that half of the input buffer has been handled.
+
+ (#) If the input internal buffer is accessed via DMA or interrupt, @ref HAL_FMAC_GetDataCallback()
+ will be called to require new input data. It will be provided through
+ @ref HAL_FMAC_AppendFilterData() if the DMA isn't in circular mode.
+
+ (#) If the output internal buffer is accessed via DMA, @ref HAL_FMAC_HalfOutputDataReadyCallback()
+ will be called to indicate that half of the output buffer has been handled.
+
+ (#) If the output internal buffer is accessed via DMA or interrupt,
+ @ref HAL_FMAC_OutputDataReadyCallback() will be called to require a new output
+ buffer. It will be provided through @ref HAL_FMAC_ConfigFilterOutputBuffer()
+ if the DMA isn't in circular mode.
+
+ (#) In all modes except none, provide new input data to be processed via @ref HAL_FMAC_AppendFilterData().
+ This function should only be called once the previous input data has been handled
+ (the preloaded input data isn't concerned).
+
+ (#) In all modes except none, provide a new output buffer to be filled via
+ @ref HAL_FMAC_ConfigFilterOutputBuffer(). This function should only be called once the previous
+ user's output buffer has been filled.
+
+ (#) In polling mode, handle the input and output data using @ref HAL_FMAC_PollFilterData().
+ This function:
+ (++) Write the user's input data (provided via @ref HAL_FMAC_AppendFilterData())
+ into the FMAC input memory area.
+ (++) Read the FMAC output memory area and write it into the user's output buffer.
+ It will return either when:
+ (++) the user's output buffer is filled.
+ (++) the user's input buffer has been handled.
+ The unused data (unread input data or free output data) will not be saved.
+ The user will have to use the updated input and output sizes to keep track
+ of them.
+
+ (#) Stop the FMAC processing (filter) using @ref HAL_FMAC_FilterStop().
+
+ (#) Call @ref HAL_FMAC_DeInit() to de-initialize the FMAC peripheral. This function
+ resorts to @ref HAL_FMAC_MspDeInit() for low-level de-initialization.
+
+ ##### Callback registration #####
+ ==================================
+
+ [..]
+ The compilation define USE_HAL_FMAC_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ [..]
+ Use Function @ref HAL_FMAC_RegisterCallback() to register a user callback.
+ Function @ref HAL_FMAC_RegisterCallback() allows to register following callbacks:
+ (+) ErrorCallback : Error Callback.
+ (+) HalfGetDataCallback : Get Half Data Callback.
+ (+) GetDataCallback : Get Data Callback.
+ (+) HalfOutputDataReadyCallback : Half Output Data Ready Callback.
+ (+) OutputDataReadyCallback : Output Data Ready Callback.
+ (+) FilterConfigCallback : Filter Configuration Callback.
+ (+) FilterPreloadCallback : Filter Preload Callback.
+ (+) MspInitCallback : FMAC MspInit.
+ (+) MspDeInitCallback : FMAC MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ [..]
+ Use function @ref HAL_FMAC_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function.
+ @ref HAL_FMAC_UnRegisterCallback() takes as parameters the HAL peripheral handle
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) ErrorCallback : Error Callback.
+ (+) HalfGetDataCallback : Get Half Data Callback.
+ (+) GetDataCallback : Get Data Callback.
+ (+) HalfOutputDataReadyCallback : Half Output Data Ready Callback.
+ (+) OutputDataReadyCallback : Output Data Ready Callback.
+ (+) FilterConfigCallback : Filter Configuration Callback.
+ (+) FilterPreloadCallback : Filter Preload Callback.
+ (+) MspInitCallback : FMAC MspInit.
+ (+) MspDeInitCallback : FMAC MspDeInit.
+
+ [..]
+ By default, after the @ref HAL_FMAC_Init() and when the state is HAL_FMAC_STATE_RESET
+ all callbacks are set to the corresponding weak (surcharged) functions:
+ examples @ref GetDataCallback(), @ref OutputDataReadyCallback().
+ Exception done for MspInit and MspDeInit functions that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_FMAC_Init()
+ and @ref HAL_FMAC_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_FMAC_Init() and @ref HAL_FMAC_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+ [..]
+ Callbacks can be registered/unregistered in HAL_FMAC_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_FMAC_STATE_READY or HAL_FMAC_STATE_RESET state, thus registered (user)
+ MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_FMAC_RegisterCallback() before calling @ref HAL_FMAC_DeInit()
+ or @ref HAL_FMAC_Init() function.
+
+ [..]
+ When the compilation define USE_HAL_FMAC_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available
+ and weak (surcharged) callbacks are used.
+
+
+ @endverbatim
+ *
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+#if defined(FMAC)
+#ifdef HAL_FMAC_MODULE_ENABLED
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup FMAC FMAC
+ * @brief FMAC HAL driver module
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup FMAC_Private_Constants FMAC Private Constants
+ * @{
+ */
+
+#define MAX_FILTER_DATA_SIZE_TO_HANDLE ((uint16_t) 0xFFU)
+#define MAX_PRELOAD_INDEX 0xFFU
+#define PRELOAD_ACCESS_DMA 0x00U
+#define PRELOAD_ACCESS_POLLING 0x01U
+#define POLLING_DISABLED 0U
+#define POLLING_ENABLED 1U
+#define POLLING_NOT_STOPPED 0U
+#define POLLING_STOPPED 1U
+/* FMAC polling-based communications time-out value */
+#define HAL_FMAC_TIMEOUT_VALUE 1000U
+/* FMAC reset time-out value */
+#define HAL_FMAC_RESET_TIMEOUT_VALUE 500U
+/* DMA Read Requests Enable */
+#define FMAC_DMA_REN FMAC_CR_DMAREN
+/* DMA Write Channel Enable */
+#define FMAC_DMA_WEN FMAC_CR_DMAWEN
+/* FMAC Execution Enable */
+#define FMAC_START FMAC_PARAM_START
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FMAC_Private_Macros FMAC Private Macros
+ * @{
+ */
+
+/**
+ * @brief Get the X1 memory area size.
+ * @param __HANDLE__ FMAC handle.
+ * @retval X1_BUF_SIZE
+ */
+#define FMAC_GET_X1_SIZE(__HANDLE__) \
+ ((((__HANDLE__)->Instance->X1BUFCFG) & (FMAC_X1BUFCFG_X1_BUF_SIZE)) >> (FMAC_X1BUFCFG_X1_BUF_SIZE_Pos))
+
+/**
+ * @brief Get the X1 watermark.
+ * @param __HANDLE__ FMAC handle.
+ * @retval FULL_WM
+ */
+#define FMAC_GET_X1_FULL_WM(__HANDLE__) \
+ (((__HANDLE__)->Instance->X1BUFCFG) & (FMAC_X1BUFCFG_FULL_WM))
+
+/**
+ * @brief Get the X2 memory area size.
+ * @param __HANDLE__ FMAC handle.
+ * @retval X2_BUF_SIZE
+ */
+#define FMAC_GET_X2_SIZE(__HANDLE__) \
+ ((((__HANDLE__)->Instance->X2BUFCFG) & (FMAC_X2BUFCFG_X2_BUF_SIZE)) >> (FMAC_X2BUFCFG_X2_BUF_SIZE_Pos))
+
+/**
+ * @brief Get the Y memory area size.
+ * @param __HANDLE__ FMAC handle.
+ * @retval Y_BUF_SIZE
+ */
+#define FMAC_GET_Y_SIZE(__HANDLE__) \
+ ((((__HANDLE__)->Instance->YBUFCFG) & (FMAC_YBUFCFG_Y_BUF_SIZE)) >> (FMAC_YBUFCFG_Y_BUF_SIZE_Pos))
+
+/**
+ * @brief Get the Y watermark.
+ * @param __HANDLE__ FMAC handle.
+ * @retval EMPTY_WM
+ */
+#define FMAC_GET_Y_EMPTY_WM(__HANDLE__) \
+ (((__HANDLE__)->Instance->YBUFCFG) & (FMAC_YBUFCFG_EMPTY_WM))
+
+/**
+ * @brief Get the start bit state.
+ * @param __HANDLE__ FMAC handle.
+ * @retval START
+ */
+#define FMAC_GET_START_BIT(__HANDLE__) \
+ ((((__HANDLE__)->Instance->PARAM) & (FMAC_PARAM_START)) >> (FMAC_PARAM_START_Pos))
+
+/**
+ * @brief Get the threshold matching the watermark.
+ * @param __WM__ Watermark value.
+ * @retval THRESHOLD
+ */
+#define FMAC_GET_THRESHOLD_FROM_WM(__WM__) (((__WM__) == FMAC_THRESHOLD_1)? 1U: \
+ ((__WM__) == FMAC_THRESHOLD_2)? 2U: \
+ ((__WM__) == FMAC_THRESHOLD_4)? 4U:8U)
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Global variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+static HAL_StatusTypeDef FMAC_Reset(FMAC_HandleTypeDef *hfmac);
+static void FMAC_ResetDataPointers(FMAC_HandleTypeDef *hfmac);
+static void FMAC_ResetOutputStateAndDataPointers(FMAC_HandleTypeDef *hfmac);
+static void FMAC_ResetInputStateAndDataPointers(FMAC_HandleTypeDef *hfmac);
+static HAL_StatusTypeDef FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig,
+ uint8_t PreloadAccess);
+static HAL_StatusTypeDef FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
+ int16_t *pOutput, uint8_t OutputSize, uint8_t PreloadAccess);
+static void FMAC_WritePreloadDataIncrementPtr(FMAC_HandleTypeDef *hfmac, int16_t **ppData, uint8_t Size);
+static HAL_StatusTypeDef FMAC_WaitOnStartUntilTimeout(FMAC_HandleTypeDef *hfmac, uint32_t Tickstart, uint32_t Timeout);
+static HAL_StatusTypeDef FMAC_AppendFilterDataUpdateState(FMAC_HandleTypeDef *hfmac, int16_t *pInput,
+ uint16_t *pInputSize);
+static HAL_StatusTypeDef FMAC_ConfigFilterOutputBufferUpdateState(FMAC_HandleTypeDef *hfmac, int16_t *pOutput,
+ uint16_t *pOutputSize);
+static void FMAC_WriteDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSizeToWrite);
+static void FMAC_ReadDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSizeToRead);
+static void FMAC_DMAHalfGetData(DMA_HandleTypeDef *hdma);
+static void FMAC_DMAGetData(DMA_HandleTypeDef *hdma);
+static void FMAC_DMAHalfOutputDataReady(DMA_HandleTypeDef *hdma);
+static void FMAC_DMAOutputDataReady(DMA_HandleTypeDef *hdma);
+static void FMAC_DMAFilterConfig(DMA_HandleTypeDef *hdma);
+static void FMAC_DMAFilterPreload(DMA_HandleTypeDef *hdma);
+static void FMAC_DMAError(DMA_HandleTypeDef *hdma);
+
+/* Functions Definition ------------------------------------------------------*/
+
+/** @defgroup FMAC_Exported_Functions FMAC Exported Functions
+ * @{
+ */
+
+/** @defgroup FMAC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the FMAC peripheral and the associated handle
+ (+) DeInitialize the FMAC peripheral
+ (+) Initialize the FMAC MSP (MCU Specific Package)
+ (+) De-Initialize the FMAC MSP
+ (+) Register a User FMAC Callback
+ (+) Unregister a FMAC CallBack
+
+ [..]
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the FMAC peripheral and the associated handle.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure.
+ * @retval HAL_StatusTypeDef HAL status
+ */
+HAL_StatusTypeDef HAL_FMAC_Init(FMAC_HandleTypeDef *hfmac)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check the FMAC handle allocation */
+ if (hfmac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the instance */
+ assert_param(IS_FMAC_ALL_INSTANCE(hfmac->Instance));
+
+ if (hfmac->State == HAL_FMAC_STATE_RESET)
+ {
+ /* Initialize lock resource */
+ hfmac->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+ /* Register the default callback functions */
+ hfmac->ErrorCallback = HAL_FMAC_ErrorCallback;
+ hfmac->HalfGetDataCallback = HAL_FMAC_HalfGetDataCallback;
+ hfmac->GetDataCallback = HAL_FMAC_GetDataCallback;
+ hfmac->HalfOutputDataReadyCallback = HAL_FMAC_HalfOutputDataReadyCallback;
+ hfmac->OutputDataReadyCallback = HAL_FMAC_OutputDataReadyCallback;
+ hfmac->FilterConfigCallback = HAL_FMAC_FilterConfigCallback;
+ hfmac->FilterPreloadCallback = HAL_FMAC_FilterPreloadCallback;
+
+ if (hfmac->MspInitCallback == NULL)
+ {
+ hfmac->MspInitCallback = HAL_FMAC_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hfmac->MspInitCallback(hfmac);
+#else
+ /* Init the low level hardware */
+ HAL_FMAC_MspInit(hfmac);
+#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
+ }
+
+ /* Reset pInput and pOutput */
+ hfmac->FilterParam = 0U;
+ FMAC_ResetDataPointers(hfmac);
+
+ /* Reset FMAC unit (internal pointers) */
+ if (FMAC_Reset(hfmac) == HAL_ERROR)
+ {
+ /* Update FMAC error code and FMAC peripheral state */
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_RESET;
+ hfmac->State = HAL_FMAC_STATE_TIMEOUT;
+
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Update FMAC error code and FMAC peripheral state */
+ hfmac->ErrorCode = HAL_FMAC_ERROR_NONE;
+ hfmac->State = HAL_FMAC_STATE_READY;
+
+ status = HAL_OK;
+ }
+
+ __HAL_UNLOCK(hfmac);
+
+ return status;
+}
+
+/**
+ * @brief De-initialize the FMAC peripheral.
+ * @param hfmac pointer to a FMAC structure.
+ * @retval HAL_StatusTypeDef HAL status
+ */
+HAL_StatusTypeDef HAL_FMAC_DeInit(FMAC_HandleTypeDef *hfmac)
+{
+ /* Check the FMAC handle allocation */
+ if (hfmac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_FMAC_ALL_INSTANCE(hfmac->Instance));
+
+ /* Change FMAC peripheral state */
+ hfmac->State = HAL_FMAC_STATE_BUSY;
+
+ /* Set FMAC error code to none */
+ hfmac->ErrorCode = HAL_FMAC_ERROR_NONE;
+
+ /* Reset pInput and pOutput */
+ hfmac->FilterParam = 0U;
+ FMAC_ResetDataPointers(hfmac);
+
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+ if (hfmac->MspDeInitCallback == NULL)
+ {
+ hfmac->MspDeInitCallback = HAL_FMAC_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ hfmac->MspDeInitCallback(hfmac);
+#else
+ /* DeInit the low level hardware: CLOCK, NVIC, DMA */
+ HAL_FMAC_MspDeInit(hfmac);
+#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
+
+ /* Change FMAC peripheral state */
+ hfmac->State = HAL_FMAC_STATE_RESET;
+
+ /* Always release Lock in case of de-initialization */
+ __HAL_UNLOCK(hfmac);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the FMAC MSP.
+ * @param hfmac FMAC handle.
+ * @retval None
+ */
+__weak void HAL_FMAC_MspInit(FMAC_HandleTypeDef *hfmac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfmac);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_FMAC_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief De-initialize the FMAC MSP.
+ * @param hfmac FMAC handle.
+ * @retval None
+ */
+__weak void HAL_FMAC_MspDeInit(FMAC_HandleTypeDef *hfmac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfmac);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_FMAC_MspDeInit can be implemented in the user file
+ */
+}
+
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User FMAC Callback.
+ * @note The User FMAC Callback is to be used instead of the weak predefined callback.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @param CallbackID ID of the callback to be registered.
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_FMAC_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_FMAC_HALF_GET_DATA_CB_ID Get Half Data Callback ID
+ * @arg @ref HAL_FMAC_GET_DATA_CB_ID Get Data Callback ID
+ * @arg @ref HAL_FMAC_HALF_OUTPUT_DATA_READY_CB_ID Half Output Data Ready Callback ID
+ * @arg @ref HAL_FMAC_OUTPUT_DATA_READY_CB_ID Output Data Ready Callback ID
+ * @arg @ref HAL_FMAC_FILTER_CONFIG_CB_ID Filter Configuration Callback ID
+ * @arg @ref HAL_FMAC_FILTER_PRELOAD_CB_ID Filter Preload Callback ID
+ * @arg @ref HAL_FMAC_MSPINIT_CB_ID FMAC MspInit ID
+ * @arg @ref HAL_FMAC_MSPDEINIT_CB_ID FMAC MspDeInit ID
+ * @param pCallback pointer to the Callback function.
+ * @retval HAL_StatusTypeDef HAL status
+ */
+HAL_StatusTypeDef HAL_FMAC_RegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_CallbackIDTypeDef CallbackID,
+ pFMAC_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the FMAC handle allocation */
+ if (hfmac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ __HAL_LOCK(hfmac);
+
+ if (hfmac->State == HAL_FMAC_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_FMAC_ERROR_CB_ID :
+ hfmac->ErrorCallback = pCallback;
+ break;
+
+ case HAL_FMAC_HALF_GET_DATA_CB_ID :
+ hfmac->HalfGetDataCallback = pCallback;
+ break;
+
+ case HAL_FMAC_GET_DATA_CB_ID :
+ hfmac->GetDataCallback = pCallback;
+ break;
+
+ case HAL_FMAC_HALF_OUTPUT_DATA_READY_CB_ID :
+ hfmac->HalfOutputDataReadyCallback = pCallback;
+ break;
+
+ case HAL_FMAC_OUTPUT_DATA_READY_CB_ID :
+ hfmac->OutputDataReadyCallback = pCallback;
+ break;
+
+ case HAL_FMAC_FILTER_CONFIG_CB_ID :
+ hfmac->FilterConfigCallback = pCallback;
+ break;
+
+ case HAL_FMAC_FILTER_PRELOAD_CB_ID :
+ hfmac->FilterPreloadCallback = pCallback;
+ break;
+
+ case HAL_FMAC_MSPINIT_CB_ID :
+ hfmac->MspInitCallback = pCallback;
+ break;
+
+ case HAL_FMAC_MSPDEINIT_CB_ID :
+ hfmac->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hfmac->State == HAL_FMAC_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_FMAC_MSPINIT_CB_ID :
+ hfmac->MspInitCallback = pCallback;
+ break;
+
+ case HAL_FMAC_MSPDEINIT_CB_ID :
+ hfmac->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ __HAL_UNLOCK(hfmac);
+
+ return status;
+}
+
+/**
+ * @brief Unregister a FMAC CallBack.
+ * @note The FMAC callback is redirected to the weak predefined callback.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module
+ * @param CallbackID ID of the callback to be unregistered.
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_FMAC_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_FMAC_HALF_GET_DATA_CB_ID Get Half Data Callback ID
+ * @arg @ref HAL_FMAC_GET_DATA_CB_ID Get Data Callback ID
+ * @arg @ref HAL_FMAC_HALF_OUTPUT_DATA_READY_CB_ID Half Output Data Ready Callback ID
+ * @arg @ref HAL_FMAC_OUTPUT_DATA_READY_CB_ID Output Data Ready Callback ID
+ * @arg @ref HAL_FMAC_FILTER_CONFIG_CB_ID Filter Configuration Callback ID
+ * @arg @ref HAL_FMAC_FILTER_PRELOAD_CB_ID Filter Preload Callback ID
+ * @arg @ref HAL_FMAC_MSPINIT_CB_ID FMAC MspInit ID
+ * @arg @ref HAL_FMAC_MSPDEINIT_CB_ID FMAC MspDeInit ID
+ * @retval HAL_StatusTypeDef HAL status
+ */
+HAL_StatusTypeDef HAL_FMAC_UnRegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the FMAC handle allocation */
+ if (hfmac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ __HAL_LOCK(hfmac);
+
+ if (hfmac->State == HAL_FMAC_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_FMAC_ERROR_CB_ID :
+ hfmac->ErrorCallback = HAL_FMAC_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_FMAC_HALF_GET_DATA_CB_ID :
+ hfmac->HalfGetDataCallback = HAL_FMAC_HalfGetDataCallback; /* Legacy weak HalfGetDataCallback */
+ break;
+
+ case HAL_FMAC_GET_DATA_CB_ID :
+ hfmac->GetDataCallback = HAL_FMAC_GetDataCallback; /* Legacy weak GetDataCallback */
+ break;
+
+ case HAL_FMAC_HALF_OUTPUT_DATA_READY_CB_ID :
+ hfmac->HalfOutputDataReadyCallback = HAL_FMAC_HalfOutputDataReadyCallback; /* Legacy weak
+ HalfOutputDataReadyCallback */
+ break;
+
+ case HAL_FMAC_OUTPUT_DATA_READY_CB_ID :
+ hfmac->OutputDataReadyCallback = HAL_FMAC_OutputDataReadyCallback; /* Legacy weak
+ OutputDataReadyCallback */
+ break;
+
+ case HAL_FMAC_FILTER_CONFIG_CB_ID :
+ hfmac->FilterConfigCallback = HAL_FMAC_FilterConfigCallback; /* Legacy weak
+ FilterConfigCallback */
+ break;
+
+ case HAL_FMAC_FILTER_PRELOAD_CB_ID :
+ hfmac->FilterPreloadCallback = HAL_FMAC_FilterPreloadCallback; /* Legacy weak FilterPreloadCallba */
+ break;
+
+ case HAL_FMAC_MSPINIT_CB_ID :
+ hfmac->MspInitCallback = HAL_FMAC_MspInit; /* Legacy weak MspInitCallback */
+ break;
+
+ case HAL_FMAC_MSPDEINIT_CB_ID :
+ hfmac->MspDeInitCallback = HAL_FMAC_MspDeInit; /* Legacy weak MspDeInitCallback */
+ break;
+
+ default :
+ /* Update the error code */
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hfmac->State == HAL_FMAC_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_FMAC_MSPINIT_CB_ID :
+ hfmac->MspInitCallback = HAL_FMAC_MspInit;
+ break;
+
+ case HAL_FMAC_MSPDEINIT_CB_ID :
+ hfmac->MspDeInitCallback = HAL_FMAC_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ __HAL_UNLOCK(hfmac);
+
+ return status;
+}
+#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_Exported_Functions_Group2 Peripheral Control functions
+ * @brief Control functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure the FMAC peripheral: memory area, filter type and parameters,
+ way to access to the input and output memory area (none, polling, IT, DMA).
+ (+) Start the FMAC processing (filter).
+ (+) Handle the input data that will be provided into FMAC.
+ (+) Handle the output data provided by FMAC.
+ (+) Stop the FMAC processing (filter).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the FMAC filter.
+ * @note The configuration is done according to the parameters
+ * specified in the FMAC_FilterConfigTypeDef structure.
+ * The provided data will be loaded using polling mode.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @param pConfig pointer to a FMAC_FilterConfigTypeDef structure that
+ * contains the FMAC configuration information.
+ * @retval HAL_StatusTypeDef HAL status
+ */
+HAL_StatusTypeDef HAL_FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig)
+{
+ return (FMAC_FilterConfig(hfmac, pConfig, PRELOAD_ACCESS_POLLING));
+}
+
+/**
+ * @brief Configure the FMAC filter.
+ * @note The configuration is done according to the parameters
+ * specified in the FMAC_FilterConfigTypeDef structure.
+ * The provided data will be loaded using DMA.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @param pConfig pointer to a FMAC_FilterConfigTypeDef structure that
+ * contains the FMAC configuration information.
+ * @retval HAL_StatusTypeDef HAL status
+ */
+HAL_StatusTypeDef HAL_FMAC_FilterConfig_DMA(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig)
+{
+ return (FMAC_FilterConfig(hfmac, pConfig, PRELOAD_ACCESS_DMA));
+}
+
+/**
+ * @brief Preload the input (FIR, IIR) and output data (IIR) of the FMAC filter.
+ * @note The set(s) of data will be used by FMAC as soon as @ref HAL_FMAC_FilterStart is called.
+ * The provided data will be loaded using polling mode.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @param pInput Preloading of the first elements of the input buffer (X1).
+ * If not needed (no data available when starting), it should be set to NULL.
+ * @param InputSize Size of the input vector.
+ * As pInput is used for preloading data, it cannot be bigger than the input memory area.
+ * @param pOutput [IIR] Preloading of the first elements of the output vector (Y).
+ * If not needed, it should be set to NULL.
+ * @param OutputSize Size of the output vector.
+ * As pOutput is used for preloading data, it cannot be bigger than the output memory area.
+ * @note The input and the output buffers can be filled by calling several times @ref HAL_FMAC_FilterPreload
+ * (each call filling partly the buffers). In case of overflow (too much data provided through
+ * all these calls), an error will be returned.
+ * @retval HAL_StatusTypeDef HAL status
+ */
+HAL_StatusTypeDef HAL_FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
+ int16_t *pOutput, uint8_t OutputSize)
+{
+ return (FMAC_FilterPreload(hfmac, pInput, InputSize, pOutput, OutputSize, PRELOAD_ACCESS_POLLING));
+}
+
+/**
+ * @brief Preload the input (FIR, IIR) and output data (IIR) of the FMAC filter.
+ * @note The set(s) of data will be used by FMAC as soon as @ref HAL_FMAC_FilterStart is called.
+ * The provided data will be loaded using DMA.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @param pInput Preloading of the first elements of the input buffer (X1).
+ * If not needed (no data available when starting), it should be set to NULL.
+ * @param InputSize Size of the input vector.
+ * As pInput is used for preloading data, it cannot be bigger than the input memory area.
+ * @param pOutput [IIR] Preloading of the first elements of the output vector (Y).
+ * If not needed, it should be set to NULL.
+ * @param OutputSize Size of the output vector.
+ * As pOutput is used for preloading data, it cannot be bigger than the output memory area.
+ * @note The input and the output buffers can be filled by calling several times @ref HAL_FMAC_FilterPreload
+ * (each call filling partly the buffers). In case of overflow (too much data provided through
+ * all these calls), an error will be returned.
+ * @retval HAL_StatusTypeDef HAL status
+ */
+HAL_StatusTypeDef HAL_FMAC_FilterPreload_DMA(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
+ int16_t *pOutput, uint8_t OutputSize)
+{
+ return (FMAC_FilterPreload(hfmac, pInput, InputSize, pOutput, OutputSize, PRELOAD_ACCESS_DMA));
+}
+
+
+/**
+ * @brief Start the FMAC processing according to the existing FMAC configuration.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @param pOutput pointer to buffer where output data of FMAC processing will be stored
+ * in the next steps.
+ * If it is set to NULL, the output will not be read and it will be up to
+ * an external IP to empty the output buffer.
+ * @param pOutputSize pointer to the size of the output buffer. The number of read data will be written here.
+ * @retval HAL_StatusTypeDef HAL status
+ */
+HAL_StatusTypeDef HAL_FMAC_FilterStart(FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize)
+{
+ uint32_t tmpcr = 0U;
+ HAL_StatusTypeDef status;
+
+ /* Check the START bit state */
+ if (FMAC_GET_START_BIT(hfmac) != 0U)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check that a valid configuration was done previously */
+ if (hfmac->FilterParam == 0U)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check handle state is ready */
+ if (hfmac->State == HAL_FMAC_STATE_READY)
+ {
+ /* Change the FMAC state */
+ hfmac->State = HAL_FMAC_STATE_BUSY;
+
+ /* CR: Configure the input access (error interruptions enabled only for IT or DMA) */
+ if (hfmac->InputAccess == FMAC_BUFFER_ACCESS_DMA)
+ {
+ tmpcr |= FMAC_DMA_WEN;
+ }
+ else if (hfmac->InputAccess == FMAC_BUFFER_ACCESS_IT)
+ {
+ tmpcr |= FMAC_IT_WIEN;
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+ /* CR: Configure the output access (error interruptions enabled only for IT or DMA) */
+ if (hfmac->OutputAccess == FMAC_BUFFER_ACCESS_DMA)
+ {
+ tmpcr |= FMAC_DMA_REN;
+ }
+ else if (hfmac->OutputAccess == FMAC_BUFFER_ACCESS_IT)
+ {
+ tmpcr |= FMAC_IT_RIEN;
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+ /* CR: Write the configuration */
+ MODIFY_REG(hfmac->Instance->CR, \
+ FMAC_IT_RIEN | FMAC_IT_WIEN | FMAC_DMA_REN | FMAC_CR_DMAWEN, \
+ tmpcr);
+
+ /* Register the new output buffer */
+ status = FMAC_ConfigFilterOutputBufferUpdateState(hfmac, pOutput, pOutputSize);
+
+ if (status == HAL_OK)
+ {
+ /* PARAM: Start the filter ( this can generate interrupts before the end of the HAL_FMAC_FilterStart ) */
+ WRITE_REG(hfmac->Instance->PARAM, (uint32_t)(hfmac->FilterParam));
+ }
+
+ /* Reset the busy flag (do not overwrite the possible write and read flag) */
+ hfmac->State = HAL_FMAC_STATE_READY;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Provide a new input buffer that will be loaded into the FMAC input memory area.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @param pInput New input vector (additional input data).
+ * @param pInputSize Size of the input vector (if all the data can't be
+ * written, it will be updated with the number of data read from FMAC).
+ * @retval HAL_StatusTypeDef HAL status
+ */
+HAL_StatusTypeDef HAL_FMAC_AppendFilterData(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint16_t *pInputSize)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check the function parameters */
+ if ((pInput == NULL) || (pInputSize == NULL))
+ {
+ return HAL_ERROR;
+ }
+ if (*pInputSize == 0U)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the START bit state */
+ if (FMAC_GET_START_BIT(hfmac) == 0U)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the FMAC configuration */
+ if (hfmac->InputAccess == FMAC_BUFFER_ACCESS_NONE)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check whether the previous input vector has been handled */
+ if ((hfmac->pInputSize != NULL) && (hfmac->InputCurrentSize < * (hfmac->pInputSize)))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check that FMAC was initialized and that no writing is already ongoing */
+ if (hfmac->WrState == HAL_FMAC_STATE_READY)
+ {
+ /* Register the new input buffer */
+ status = FMAC_AppendFilterDataUpdateState(hfmac, pInput, pInputSize);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Provide a new output buffer to be filled with the data computed by FMAC unit.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @param pOutput New output vector.
+ * @param pOutputSize Size of the output vector (if the vector can't
+ * be entirely filled, pOutputSize will be updated with the number
+ * of data read from FMAC).
+ * @retval HAL_StatusTypeDef HAL status
+ */
+HAL_StatusTypeDef HAL_FMAC_ConfigFilterOutputBuffer(FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check the function parameters */
+ if ((pOutput == NULL) || (pOutputSize == NULL))
+ {
+ return HAL_ERROR;
+ }
+ if (*pOutputSize == 0U)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the START bit state */
+ if (FMAC_GET_START_BIT(hfmac) == 0U)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the FMAC configuration */
+ if (hfmac->OutputAccess == FMAC_BUFFER_ACCESS_NONE)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check whether the previous output vector has been handled */
+ if ((hfmac->pOutputSize != NULL) && (hfmac->OutputCurrentSize < * (hfmac->pOutputSize)))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check that FMAC was initialized and that not reading is already ongoing */
+ if (hfmac->RdState == HAL_FMAC_STATE_READY)
+ {
+ /* Register the new output buffer */
+ status = FMAC_ConfigFilterOutputBufferUpdateState(hfmac, pOutput, pOutputSize);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Handle the input and/or output data in polling mode
+ * @note This function writes the previously provided user's input data and
+ * fills the previously provided user's output buffer,
+ * according to the existing FMAC configuration (polling mode only).
+ * The function returns when the input data has been handled or
+ * when the output data is filled. The possible unused data isn't
+ * kept. It will be up to the user to handle it. The previously
+ * provided pInputSize and pOutputSize will be used to indicate to the
+ * size of the read/written data to the user.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @param Timeout timeout value.
+ * @retval HAL_StatusTypeDef HAL status
+ */
+HAL_StatusTypeDef HAL_FMAC_PollFilterData(FMAC_HandleTypeDef *hfmac, uint32_t Timeout)
+{
+ uint32_t tickstart;
+ uint8_t inpolling;
+ uint8_t inpollingover = POLLING_NOT_STOPPED;
+ uint8_t outpolling;
+ uint8_t outpollingover = POLLING_NOT_STOPPED;
+ HAL_StatusTypeDef status;
+
+ /* Check the START bit state */
+ if (FMAC_GET_START_BIT(hfmac) == 0U)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the configuration */
+
+ /* Get the input and output mode (if no buffer was previously provided, nothing will be read/written) */
+ if ((hfmac->InputAccess == FMAC_BUFFER_ACCESS_POLLING) && (hfmac->pInput != NULL))
+ {
+ inpolling = POLLING_ENABLED;
+ }
+ else
+ {
+ inpolling = POLLING_DISABLED;
+ }
+ if ((hfmac->OutputAccess == FMAC_BUFFER_ACCESS_POLLING) && (hfmac->pOutput != NULL))
+ {
+ outpolling = POLLING_ENABLED;
+ }
+ else
+ {
+ outpolling = POLLING_DISABLED;
+ }
+
+ /* Check the configuration */
+ if ((inpolling == POLLING_DISABLED) && (outpolling == POLLING_DISABLED))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check handle state is ready */
+ if (hfmac->State == HAL_FMAC_STATE_READY)
+ {
+ /* Change the FMAC state */
+ hfmac->State = HAL_FMAC_STATE_BUSY;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Loop on reading and writing until timeout */
+ while ((HAL_GetTick() - tickstart) < Timeout)
+ {
+ /* X1: Check the mode: polling or none */
+ if (inpolling != POLLING_DISABLED)
+ {
+ FMAC_WriteDataIncrementPtr(hfmac, MAX_FILTER_DATA_SIZE_TO_HANDLE);
+ if (hfmac->InputCurrentSize == *(hfmac->pInputSize))
+ {
+ inpollingover = POLLING_STOPPED;
+ }
+ }
+
+ /* Y: Check the mode: polling or none */
+ if (outpolling != POLLING_DISABLED)
+ {
+ FMAC_ReadDataIncrementPtr(hfmac, MAX_FILTER_DATA_SIZE_TO_HANDLE);
+ if (hfmac->OutputCurrentSize == *(hfmac->pOutputSize))
+ {
+ outpollingover = POLLING_STOPPED;
+ }
+ }
+
+ /* Exit if there isn't data to handle anymore on one side or another */
+ if ((inpollingover != POLLING_NOT_STOPPED) || (outpollingover != POLLING_NOT_STOPPED))
+ {
+ break;
+ }
+ }
+
+ /* Change the FMAC state; update the input and output sizes; reset the indexes */
+ if (inpolling != POLLING_DISABLED)
+ {
+ (*(hfmac->pInputSize)) = hfmac->InputCurrentSize;
+ FMAC_ResetInputStateAndDataPointers(hfmac);
+ }
+ if (outpolling != POLLING_DISABLED)
+ {
+ (*(hfmac->pOutputSize)) = hfmac->OutputCurrentSize;
+ FMAC_ResetOutputStateAndDataPointers(hfmac);
+ }
+
+ /* Reset the busy flag (do not overwrite the possible write and read flag) */
+ hfmac->State = HAL_FMAC_STATE_READY;
+
+ if ((HAL_GetTick() - tickstart) >= Timeout)
+ {
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
+ status = HAL_ERROR;
+ }
+ else
+ {
+ status = HAL_OK;
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Stop the FMAC processing.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @retval HAL_StatusTypeDef HAL status
+ */
+HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check handle state is ready */
+ if (hfmac->State == HAL_FMAC_STATE_READY)
+ {
+ /* Change the FMAC state */
+ hfmac->State = HAL_FMAC_STATE_BUSY;
+
+ /* Set the START bit to 0 (stop the previously configured filter) */
+ CLEAR_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START);
+
+ /* Disable the interrupts in order to avoid crossing cases */
+ CLEAR_BIT(hfmac->Instance->CR, FMAC_DMA_REN | FMAC_DMA_WEN | FMAC_IT_RIEN | FMAC_IT_WIEN);
+
+ /* In case of IT, update the sizes */
+ if ((hfmac->InputAccess == FMAC_BUFFER_ACCESS_IT) && (hfmac->pInput != NULL))
+ {
+ (*(hfmac->pInputSize)) = hfmac->InputCurrentSize;
+ }
+ if ((hfmac->OutputAccess == FMAC_BUFFER_ACCESS_IT) && (hfmac->pOutput != NULL))
+ {
+ (*(hfmac->pOutputSize)) = hfmac->OutputCurrentSize;
+ }
+
+ /* Reset FMAC unit (internal pointers) */
+ if (FMAC_Reset(hfmac) == HAL_ERROR)
+ {
+ /* Update FMAC error code and FMAC peripheral state */
+ hfmac->ErrorCode = HAL_FMAC_ERROR_RESET;
+ hfmac->State = HAL_FMAC_STATE_TIMEOUT;
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Reset the data pointers */
+ FMAC_ResetDataPointers(hfmac);
+
+ status = HAL_OK;
+ }
+
+ /* Reset the busy flag */
+ hfmac->State = HAL_FMAC_STATE_READY;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_Exported_Functions_Group3 Callback functions
+ * @brief Callback functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Callback functions #####
+ ==============================================================================
+ [..] This section provides Interruption and DMA callback functions:
+ (+) DMA or Interrupt: the user's input data is half written (DMA only)
+ or completely written.
+ (+) DMA or Interrupt: the user's output buffer is half filled (DMA only)
+ or completely filled.
+ (+) DMA or Interrupt: error handling.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief FMAC error callback.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @retval None
+ */
+__weak void HAL_FMAC_ErrorCallback(FMAC_HandleTypeDef *hfmac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfmac);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_FMAC_ErrorCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief FMAC get half data callback.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @retval None
+ */
+__weak void HAL_FMAC_HalfGetDataCallback(FMAC_HandleTypeDef *hfmac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfmac);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_FMAC_HalfGetDataCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief FMAC get data callback.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @retval None
+ */
+__weak void HAL_FMAC_GetDataCallback(FMAC_HandleTypeDef *hfmac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfmac);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_FMAC_GetDataCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief FMAC half output data ready callback.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @retval None
+ */
+__weak void HAL_FMAC_HalfOutputDataReadyCallback(FMAC_HandleTypeDef *hfmac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfmac);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_FMAC_HalfOutputDataReadyCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief FMAC output data ready callback.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @retval None
+ */
+__weak void HAL_FMAC_OutputDataReadyCallback(FMAC_HandleTypeDef *hfmac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfmac);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_FMAC_OutputDataReadyCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief FMAC filter configuration callback.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @retval None
+ */
+__weak void HAL_FMAC_FilterConfigCallback(FMAC_HandleTypeDef *hfmac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfmac);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_FMAC_FilterConfigCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief FMAC filter preload callback.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @retval None
+ */
+__weak void HAL_FMAC_FilterPreloadCallback(FMAC_HandleTypeDef *hfmac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfmac);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_FMAC_FilterPreloadCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_Exported_Functions_Group4 IRQ handler management
+ * @brief IRQ handler.
+ *
+@verbatim
+ ==============================================================================
+ ##### IRQ handler management #####
+ ==============================================================================
+[..] This section provides IRQ handler function.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Handle FMAC interrupt request.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @retval None
+ */
+void HAL_FMAC_IRQHandler(FMAC_HandleTypeDef *hfmac)
+{
+ uint32_t itsource;
+
+ /* Check if the read interrupt is enabled and if Y buffer empty flag isn't set */
+ itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_RIEN);
+ if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_YEMPTY) == 0U) && (itsource != 0U))
+ {
+ /* Read some data if possible (Y size is used as a pseudo timeout in order
+ to not get stuck too long under IT if FMAC keeps on processing input
+ data reloaded via DMA for instance). */
+ if (hfmac->pOutput != NULL)
+ {
+ FMAC_ReadDataIncrementPtr(hfmac, (uint16_t)FMAC_GET_Y_SIZE(hfmac));
+ }
+
+ /* Indicate that data is ready to be read */
+ if ((hfmac->pOutput == NULL) || (hfmac->OutputCurrentSize == *(hfmac->pOutputSize)))
+ {
+ /* Reset the pointers to indicate new data will be needed */
+ FMAC_ResetOutputStateAndDataPointers(hfmac);
+
+ /* Call the output data ready callback */
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+ hfmac->OutputDataReadyCallback(hfmac);
+#else
+ HAL_FMAC_OutputDataReadyCallback(hfmac);
+#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* Check if the write interrupt is enabled and if X1 buffer full flag isn't set */
+ itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_WIEN);
+ if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_X1FULL) == 0U) && (itsource != 0U))
+ {
+ /* Write some data if possible (X1 size is used as a pseudo timeout in order
+ to not get stuck too long under IT if FMAC keep on processing input
+ data whereas its output emptied via DMA for instance). */
+ if (hfmac->pInput != NULL)
+ {
+ FMAC_WriteDataIncrementPtr(hfmac, (uint16_t)FMAC_GET_X1_SIZE(hfmac));
+ }
+
+ /* Indicate that new data will be needed */
+ if ((hfmac->pInput == NULL) || (hfmac->InputCurrentSize == *(hfmac->pInputSize)))
+ {
+ /* Reset the pointers to indicate new data will be needed */
+ FMAC_ResetInputStateAndDataPointers(hfmac);
+
+ /* Call the get data callback */
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+ hfmac->GetDataCallback(hfmac);
+#else
+ HAL_FMAC_GetDataCallback(hfmac);
+#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* Check if the overflow error interrupt is enabled and if overflow error flag is raised */
+ itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_OVFLIEN);
+ if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_OVFL) != 0U) && (itsource != 0U))
+ {
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_OVFL;
+ }
+
+ /* Check if the underflow error interrupt is enabled and if underflow error flag is raised */
+ itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_UNFLIEN);
+ if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_UNFL) != 0U) && (itsource != 0U))
+ {
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_UNFL;
+ }
+
+ /* Check if the saturation error interrupt is enabled and if saturation error flag is raised */
+ itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_SATIEN);
+ if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_SAT) != 0U) && (itsource != 0U))
+ {
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_SAT;
+ }
+
+ /* Call the error callback if an error occurred */
+ if (hfmac->ErrorCode != HAL_FMAC_ERROR_NONE)
+ {
+ /* Call the error callback */
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+ hfmac->ErrorCallback(hfmac);
+#else
+ HAL_FMAC_ErrorCallback(hfmac);
+#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_Exported_Functions_Group5 Peripheral State and Error functions
+ * @brief Peripheral State and Error functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Error functions #####
+ ==============================================================================
+ [..] This subsection provides functions allowing to
+ (+) Check the FMAC state
+ (+) Get error code
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the FMAC state.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @retval HAL_FMAC_StateTypeDef FMAC state
+ */
+HAL_FMAC_StateTypeDef HAL_FMAC_GetState(FMAC_HandleTypeDef *hfmac)
+{
+ /* Return FMAC state */
+ return hfmac->State;
+}
+
+/**
+ * @brief Return the FMAC peripheral error.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @note The returned error is a bit-map combination of possible errors.
+ * @retval uint32_t Error bit-map based on @ref FMAC_Error_Code
+ */
+uint32_t HAL_FMAC_GetError(FMAC_HandleTypeDef *hfmac)
+{
+ /* Return FMAC error code */
+ return hfmac->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_Private_Functions FMAC Private Functions
+ * @{
+ */
+
+/**
+ ==============================================================================
+ ##### FMAC Private Functions #####
+ ==============================================================================
+ */
+/**
+ * @brief Perform a reset of the FMAC unit.
+ * @param hfmac FMAC handle.
+ * @retval HAL_StatusTypeDef HAL status
+ */
+static HAL_StatusTypeDef FMAC_Reset(FMAC_HandleTypeDef *hfmac)
+{
+ uint32_t tickstart;
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ /* Perform the reset */
+ SET_BIT(hfmac->Instance->CR, FMAC_CR_RESET);
+
+ /* Wait until flag is reset */
+ while (READ_BIT(hfmac->Instance->CR, FMAC_CR_RESET) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > HAL_FMAC_RESET_TIMEOUT_VALUE)
+ {
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
+ return HAL_ERROR;
+ }
+ }
+
+ hfmac->ErrorCode = HAL_FMAC_ERROR_NONE;
+ return HAL_OK;
+}
+
+/**
+ * @brief Reset the data pointers of the FMAC unit.
+ * @param hfmac FMAC handle.
+ * @retval None
+ */
+static void FMAC_ResetDataPointers(FMAC_HandleTypeDef *hfmac)
+{
+ FMAC_ResetInputStateAndDataPointers(hfmac);
+ FMAC_ResetOutputStateAndDataPointers(hfmac);
+}
+
+/**
+ * @brief Reset the input data pointers of the FMAC unit.
+ * @param hfmac FMAC handle.
+ * @retval None
+ */
+static void FMAC_ResetInputStateAndDataPointers(FMAC_HandleTypeDef *hfmac)
+{
+ hfmac->pInput = NULL;
+ hfmac->pInputSize = NULL;
+ hfmac->InputCurrentSize = 0U;
+ hfmac->WrState = HAL_FMAC_STATE_READY;
+}
+
+/**
+ * @brief Reset the output data pointers of the FMAC unit.
+ * @param hfmac FMAC handle.
+ * @retval None
+ */
+static void FMAC_ResetOutputStateAndDataPointers(FMAC_HandleTypeDef *hfmac)
+{
+ hfmac->pOutput = NULL;
+ hfmac->pOutputSize = NULL;
+ hfmac->OutputCurrentSize = 0U;
+ hfmac->RdState = HAL_FMAC_STATE_READY;
+}
+
+/**
+ * @brief Configure the FMAC filter.
+ * @note The configuration is done according to the parameters
+ * specified in the FMAC_FilterConfigTypeDef structure.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @param pConfig pointer to a FMAC_FilterConfigTypeDef structure that
+ * contains the FMAC configuration information.
+ * @param PreloadAccess access mode used for the preload (polling or DMA).
+ * @retval HAL_StatusTypeDef HAL status
+ */
+static HAL_StatusTypeDef FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig,
+ uint8_t PreloadAccess)
+{
+ uint32_t tickstart;
+ uint32_t tmpcr;
+ HAL_StatusTypeDef status;
+#if defined(USE_FULL_ASSERT)
+ uint32_t x2size;
+#endif /* USE_FULL_ASSERT */
+
+ /* Check the parameters */
+ assert_param(IS_FMAC_THRESHOLD(pConfig->InputThreshold));
+ assert_param(IS_FMAC_THRESHOLD(pConfig->OutputThreshold));
+ assert_param(IS_FMAC_BUFFER_ACCESS(pConfig->InputAccess));
+ assert_param(IS_FMAC_BUFFER_ACCESS(pConfig->OutputAccess));
+ assert_param(IS_FMAC_CLIP_STATE(pConfig->Clip));
+ assert_param(IS_FMAC_FILTER_FUNCTION(pConfig->Filter));
+ assert_param(IS_FMAC_PARAM_P(pConfig->Filter, pConfig->P));
+ assert_param(IS_FMAC_PARAM_Q(pConfig->Filter, pConfig->Q));
+ assert_param(IS_FMAC_PARAM_R(pConfig->Filter, pConfig->R));
+
+ /* Check the START bit state */
+ if (FMAC_GET_START_BIT(hfmac) != 0U)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check handle state is ready */
+ if (hfmac->State != HAL_FMAC_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Change the FMAC state */
+ hfmac->State = HAL_FMAC_STATE_BUSY;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Indicate that there is no valid configuration done */
+ hfmac->FilterParam = 0U;
+
+ /* FMAC_X1BUFCFG: Configure the input buffer within the internal memory if required */
+ if (pConfig->InputBufferSize != 0U)
+ {
+ MODIFY_REG(hfmac->Instance->X1BUFCFG, \
+ (FMAC_X1BUFCFG_X1_BASE | FMAC_X1BUFCFG_X1_BUF_SIZE), \
+ (((((uint32_t)(pConfig->InputBaseAddress)) << FMAC_X1BUFCFG_X1_BASE_Pos) & FMAC_X1BUFCFG_X1_BASE) | \
+ ((((uint32_t)(pConfig->InputBufferSize)) << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) & \
+ FMAC_X1BUFCFG_X1_BUF_SIZE)));
+ }
+
+ /* FMAC_X1BUFCFG: Configure the input threshold if valid when compared to the configured X1 size */
+ if (pConfig->InputThreshold != FMAC_THRESHOLD_NO_VALUE)
+ {
+ /* Check the parameter */
+ assert_param(IS_FMAC_THRESHOLD_APPLICABLE(FMAC_GET_X1_SIZE(hfmac), pConfig->InputThreshold, pConfig->InputAccess));
+
+ MODIFY_REG(hfmac->Instance->X1BUFCFG, \
+ FMAC_X1BUFCFG_FULL_WM, \
+ ((pConfig->InputThreshold) & FMAC_X1BUFCFG_FULL_WM));
+ }
+
+ /* FMAC_X2BUFCFG: Configure the coefficient buffer within the internal memory */
+ if (pConfig->CoeffBufferSize != 0U)
+ {
+ MODIFY_REG(hfmac->Instance->X2BUFCFG, \
+ (FMAC_X2BUFCFG_X2_BASE | FMAC_X2BUFCFG_X2_BUF_SIZE), \
+ (((((uint32_t)(pConfig->CoeffBaseAddress)) << FMAC_X2BUFCFG_X2_BASE_Pos) & FMAC_X2BUFCFG_X2_BASE) | \
+ ((((uint32_t)(pConfig->CoeffBufferSize)) << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) &\
+ FMAC_X2BUFCFG_X2_BUF_SIZE)));
+ }
+
+ /* FMAC_YBUFCFG: Configure the output buffer within the internal memory if required */
+ if (pConfig->OutputBufferSize != 0U)
+ {
+ MODIFY_REG(hfmac->Instance->YBUFCFG, \
+ (FMAC_YBUFCFG_Y_BASE | FMAC_YBUFCFG_Y_BUF_SIZE), \
+ (((((uint32_t)(pConfig->OutputBaseAddress)) << FMAC_YBUFCFG_Y_BASE_Pos) & FMAC_YBUFCFG_Y_BASE) | \
+ ((((uint32_t)(pConfig->OutputBufferSize)) << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) & FMAC_YBUFCFG_Y_BUF_SIZE)));
+ }
+
+ /* FMAC_YBUFCFG: Configure the output threshold if valid when compared to the configured Y size */
+ if (pConfig->OutputThreshold != FMAC_THRESHOLD_NO_VALUE)
+ {
+ /* Check the parameter */
+ assert_param(IS_FMAC_THRESHOLD_APPLICABLE(FMAC_GET_Y_SIZE(hfmac), pConfig->OutputThreshold, pConfig->OutputAccess));
+
+ MODIFY_REG(hfmac->Instance->YBUFCFG, \
+ FMAC_YBUFCFG_EMPTY_WM, \
+ ((pConfig->OutputThreshold) & FMAC_YBUFCFG_EMPTY_WM));
+ }
+
+ /* FMAC_CR: Configure the clip feature */
+ tmpcr = pConfig->Clip & FMAC_CR_CLIPEN;
+
+ /* FMAC_CR: If IT or DMA will be used, enable error interrupts.
+ * Being more a debugging feature, FMAC_CR_SATIEN isn't enabled by default. */
+ if ((pConfig->InputAccess == FMAC_BUFFER_ACCESS_DMA) || (pConfig->InputAccess == FMAC_BUFFER_ACCESS_IT) ||
+ (pConfig->OutputAccess == FMAC_BUFFER_ACCESS_DMA) || (pConfig->OutputAccess == FMAC_BUFFER_ACCESS_IT))
+ {
+ tmpcr |= FMAC_IT_UNFLIEN | FMAC_IT_OVFLIEN;
+ }
+
+ /* FMAC_CR: write the value */
+ WRITE_REG(hfmac->Instance->CR, tmpcr);
+
+ /* Save the input/output accesses in order to configure RIEN, WIEN, DMAREN and DMAWEN during filter start */
+ hfmac->InputAccess = pConfig->InputAccess;
+ hfmac->OutputAccess = pConfig->OutputAccess;
+
+ /* Check whether the configured X2 is big enough for the filter */
+#if defined(USE_FULL_ASSERT)
+ x2size = FMAC_GET_X2_SIZE(hfmac);
+#endif /* USE_FULL_ASSERT */
+ assert_param(((pConfig->Filter == FMAC_FUNC_CONVO_FIR) && (x2size >= pConfig->P)) || \
+ ((pConfig->Filter == FMAC_FUNC_IIR_DIRECT_FORM_1) && \
+ (x2size >= ((uint32_t)pConfig->P + (uint32_t)pConfig->Q))));
+
+ /* Build the PARAM value that will be used when starting the filter */
+ hfmac->FilterParam = (FMAC_PARAM_START | pConfig->Filter | \
+ ((((uint32_t)(pConfig->P)) << FMAC_PARAM_P_Pos) & FMAC_PARAM_P) | \
+ ((((uint32_t)(pConfig->Q)) << FMAC_PARAM_Q_Pos) & FMAC_PARAM_Q) | \
+ ((((uint32_t)(pConfig->R)) << FMAC_PARAM_R_Pos) & FMAC_PARAM_R));
+
+ /* Initialize the coefficient buffer if required (pCoeffA for FIR only) */
+ if ((pConfig->pCoeffB != NULL) && (pConfig->CoeffBSize != 0U))
+ {
+ /* FIR/IIR: The provided coefficients should match X2 size */
+ assert_param(((uint32_t)pConfig->CoeffASize + (uint32_t)pConfig->CoeffBSize) <= x2size);
+ /* FIR/IIR: The size of pCoeffB should match the parameter P */
+ assert_param(pConfig->CoeffBSize >= pConfig->P);
+ /* pCoeffA should be provided for IIR but not for FIR */
+ /* IIR : if pCoeffB is provided, pCoeffA should also be there */
+ /* IIR: The size of pCoeffA should match the parameter Q */
+ assert_param(((pConfig->Filter == FMAC_FUNC_CONVO_FIR) &&
+ (pConfig->pCoeffA == NULL) && (pConfig->CoeffASize == 0U)) ||
+ ((pConfig->Filter == FMAC_FUNC_IIR_DIRECT_FORM_1) &&
+ (pConfig->pCoeffA != NULL) && (pConfig->CoeffASize != 0U) &&
+ (pConfig->CoeffASize >= pConfig->Q)));
+
+ /* Write number of values to be loaded, the data load function and start the operation */
+ WRITE_REG(hfmac->Instance->PARAM, \
+ (((uint32_t)(pConfig->CoeffBSize) << FMAC_PARAM_P_Pos) | \
+ ((uint32_t)(pConfig->CoeffASize) << FMAC_PARAM_Q_Pos) | \
+ FMAC_FUNC_LOAD_X2 | FMAC_PARAM_START));
+
+ if (PreloadAccess == PRELOAD_ACCESS_POLLING)
+ {
+ /* Load the buffer into the internal memory */
+ FMAC_WritePreloadDataIncrementPtr(hfmac, &(pConfig->pCoeffB), pConfig->CoeffBSize);
+
+ /* Load pCoeffA if needed */
+ if ((pConfig->pCoeffA != NULL) && (pConfig->CoeffASize != 0U))
+ {
+ /* Load the buffer into the internal memory */
+ FMAC_WritePreloadDataIncrementPtr(hfmac, &(pConfig->pCoeffA), pConfig->CoeffASize);
+ }
+
+ /* Wait for the end of the writing */
+ if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK)
+ {
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
+ hfmac->State = HAL_FMAC_STATE_TIMEOUT;
+ return HAL_ERROR;
+ }
+
+ /* Change the FMAC state */
+ hfmac->State = HAL_FMAC_STATE_READY;
+ }
+ else
+ {
+ hfmac->pInput = pConfig->pCoeffA;
+ hfmac->InputCurrentSize = pConfig->CoeffASize;
+
+ /* Set the FMAC DMA transfer complete callback */
+ hfmac->hdmaPreload->XferHalfCpltCallback = NULL;
+ hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterConfig;
+ /* Set the DMA error callback */
+ hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError;
+
+ /* Enable the DMA stream managing FMAC preload data write */
+ if ((hfmac->hdmaPreload->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if ((hfmac->hdmaPreload->LinkedListQueue != NULL) && (hfmac->hdmaPreload->LinkedListQueue->Head != NULL))
+ {
+ /* Enable the DMA channel */
+ hfmac->hdmaPreload->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] =
+ (uint32_t)(2UL * pConfig->CoeffBSize); /* Set DMA data size */
+ hfmac->hdmaPreload->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
+ (uint32_t)pConfig->pCoeffB; /* Set DMA source address */
+ hfmac->hdmaPreload->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
+ (uint32_t)&hfmac->Instance->WDATA; /* Set DMA destination address */
+
+ status = HAL_DMAEx_List_Start_IT(hfmac->hdmaPreload);
+ }
+ else
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pConfig->pCoeffB, \
+ (uint32_t)&hfmac->Instance->WDATA, (uint32_t)(2UL * pConfig->CoeffBSize));
+ }
+
+ if (status != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ }
+ }
+ else
+ {
+ /* Change the FMAC state */
+ hfmac->State = HAL_FMAC_STATE_READY;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Preload the input (FIR, IIR) and output data (IIR) of the FMAC filter.
+ * @note The set(s) of data will be used by FMAC as soon as @ref HAL_FMAC_FilterStart is called.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @param pInput Preloading of the first elements of the input buffer (X1).
+ * If not needed (no data available when starting), it should be set to NULL.
+ * @param InputSize Size of the input vector.
+ * As pInput is used for preloading data, it cannot be bigger than the input memory area.
+ * @param pOutput [IIR] Preloading of the first elements of the output vector (Y).
+ * If not needed, it should be set to NULL.
+ * @param OutputSize Size of the output vector.
+ * As pOutput is used for preloading data, it cannot be bigger than the output memory area.
+ * @param PreloadAccess access mode used for the preload (polling or DMA).
+ * @note The input and the output buffers can be filled by calling several times @ref HAL_FMAC_FilterPreload
+ * (each call filling partly the buffers). In case of overflow (too much data provided through
+ * all these calls), an error will be returned.
+ * @retval HAL_StatusTypeDef HAL status
+ */
+static HAL_StatusTypeDef FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
+ int16_t *pOutput, uint8_t OutputSize, uint8_t PreloadAccess)
+{
+ uint32_t tickstart;
+ HAL_StatusTypeDef status;
+
+ /* Check the START bit state */
+ if (FMAC_GET_START_BIT(hfmac) != 0U)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check that a valid configuration was done previously */
+ if (hfmac->FilterParam == 0U)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the preload input buffers isn't too big */
+ if ((InputSize > FMAC_GET_X1_SIZE(hfmac)) && (pInput != NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the preload output buffer isn't too big */
+ if ((OutputSize > FMAC_GET_Y_SIZE(hfmac)) && (pOutput != NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check handle state is ready */
+ if (hfmac->State != HAL_FMAC_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Change the FMAC state */
+ hfmac->State = HAL_FMAC_STATE_BUSY;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Preload the input buffer if required */
+ if ((pInput != NULL) && (InputSize != 0U))
+ {
+ /* Write number of values to be loaded, the data load function and start the operation */
+ WRITE_REG(hfmac->Instance->PARAM, \
+ (((uint32_t)InputSize << FMAC_PARAM_P_Pos) | FMAC_FUNC_LOAD_X1 | FMAC_PARAM_START));
+
+ if (PreloadAccess == PRELOAD_ACCESS_POLLING)
+ {
+ /* Load the buffer into the internal memory */
+ FMAC_WritePreloadDataIncrementPtr(hfmac, &pInput, InputSize);
+
+ /* Wait for the end of the writing */
+ if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK)
+ {
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
+ hfmac->State = HAL_FMAC_STATE_TIMEOUT;
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ hfmac->pInput = pOutput;
+ hfmac->InputCurrentSize = OutputSize;
+
+ /* Set the FMAC DMA transfer complete callback */
+ hfmac->hdmaPreload->XferHalfCpltCallback = NULL;
+ hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterPreload;
+ /* Set the DMA error callback */
+ hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError;
+
+ /* Enable the DMA stream managing FMAC preload data write */
+ if ((hfmac->hdmaPreload->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if ((hfmac->hdmaPreload->LinkedListQueue != NULL) && (hfmac->hdmaPreload->LinkedListQueue->Head != NULL))
+ {
+ /* Enable the DMA channel */
+ hfmac->hdmaPreload->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] =
+ (uint32_t)(2UL * InputSize); /* Set DMA data size */
+ hfmac->hdmaPreload->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
+ (uint32_t)pInput; /* Set DMA source address */
+ hfmac->hdmaPreload->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
+ (uint32_t)&hfmac->Instance->WDATA; /* Set DMA destination address */
+
+ status = HAL_DMAEx_List_Start_IT(hfmac->hdmaPreload);
+ }
+ else
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pInput, \
+ (uint32_t)&hfmac->Instance->WDATA, (uint32_t)(2UL * InputSize));
+ }
+
+ if (status != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Preload the output buffer if required */
+ if ((pOutput != NULL) && (OutputSize != 0U))
+ {
+ /* Write number of values to be loaded, the data load function and start the operation */
+ WRITE_REG(hfmac->Instance->PARAM, \
+ (((uint32_t)OutputSize << FMAC_PARAM_P_Pos) | FMAC_FUNC_LOAD_Y | FMAC_PARAM_START));
+
+ if (PreloadAccess == PRELOAD_ACCESS_POLLING)
+ {
+ /* Load the buffer into the internal memory */
+ FMAC_WritePreloadDataIncrementPtr(hfmac, &pOutput, OutputSize);
+
+ /* Wait for the end of the writing */
+ if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK)
+ {
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
+ hfmac->State = HAL_FMAC_STATE_TIMEOUT;
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ hfmac->pInput = NULL;
+ hfmac->InputCurrentSize = 0U;
+
+ /* Set the FMAC DMA transfer complete callback */
+ hfmac->hdmaPreload->XferHalfCpltCallback = NULL;
+ hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterPreload;
+ /* Set the DMA error callback */
+ hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError;
+
+ /* Enable the DMA stream managing FMAC preload data write */
+ if ((hfmac->hdmaPreload->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if ((hfmac->hdmaPreload->LinkedListQueue != NULL) && (hfmac->hdmaPreload->LinkedListQueue->Head != NULL))
+ {
+ /* Enable the DMA channel */
+ hfmac->hdmaPreload->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] =
+ (uint32_t)(2UL * OutputSize); /* Set DMA data size */
+ hfmac->hdmaPreload->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
+ (uint32_t)pOutput; /* Set DMA source address */
+ hfmac->hdmaPreload->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
+ (uint32_t)&hfmac->Instance->WDATA; /* Set DMA destination address */
+
+ status = HAL_DMAEx_List_Start_IT(hfmac->hdmaPreload);
+ }
+ else
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pOutput, \
+ (uint32_t)&hfmac->Instance->WDATA, (uint32_t)(2UL * OutputSize));
+ }
+
+ if (status != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Update the error codes */
+ if (__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_OVFL))
+ {
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_OVFL;
+ }
+ if (__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_UNFL))
+ {
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_UNFL;
+ }
+ if (__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_SAT))
+ {
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_SAT;
+ }
+
+ /* Change the FMAC state */
+ hfmac->State = HAL_FMAC_STATE_READY;
+
+ /* Return function status */
+ if (hfmac->ErrorCode == HAL_FMAC_ERROR_NONE)
+ {
+ status = HAL_OK;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ return status;
+}
+
+/**
+ * @brief Write data into FMAC internal memory through WDATA and increment input buffer pointer.
+ * @note This function is only used with preload functions.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @param ppData pointer to pointer to the data buffer.
+ * @param Size size of the data buffer.
+ * @retval None
+ */
+static void FMAC_WritePreloadDataIncrementPtr(FMAC_HandleTypeDef *hfmac, int16_t **ppData, uint8_t Size)
+{
+ uint8_t index;
+
+ /* Load the buffer into the internal memory */
+ for (index = Size; index > 0U; index--)
+ {
+ WRITE_REG(hfmac->Instance->WDATA, (((uint32_t)(*(*ppData))) & FMAC_WDATA_WDATA));
+ (*ppData)++;
+ }
+}
+
+/**
+ * @brief Handle FMAC Function Timeout.
+ * @param hfmac FMAC handle.
+ * @param Tickstart Tick start value.
+ * @param Timeout Timeout duration.
+ * @retval HAL_StatusTypeDef HAL status
+ */
+static HAL_StatusTypeDef FMAC_WaitOnStartUntilTimeout(FMAC_HandleTypeDef *hfmac, uint32_t Tickstart, uint32_t Timeout)
+{
+ /* Wait until flag changes */
+ while (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0U)
+ {
+ if ((HAL_GetTick() - Tickstart) > Timeout)
+ {
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
+
+ return HAL_ERROR;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Register the new input buffer, update DMA configuration if needed and change the FMAC state.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @param pInput New input vector (additional input data).
+ * @param pInputSize Size of the input vector (if all the data can't be
+ * written, it will be updated with the number of data read from FMAC).
+ * @retval HAL_StatusTypeDef HAL status
+ */
+static HAL_StatusTypeDef FMAC_AppendFilterDataUpdateState(FMAC_HandleTypeDef *hfmac, int16_t *pInput,
+ uint16_t *pInputSize)
+{
+ HAL_StatusTypeDef status;
+ /* Change the FMAC state */
+ hfmac->WrState = HAL_FMAC_STATE_BUSY_WR;
+
+ /* Reset the current size */
+ hfmac->InputCurrentSize = 0U;
+
+ /* Handle the pointer depending on the input access */
+ if (hfmac->InputAccess == FMAC_BUFFER_ACCESS_DMA)
+ {
+ hfmac->pInput = NULL;
+ hfmac->pInputSize = NULL;
+
+ /* Set the FMAC DMA transfer complete callback */
+ hfmac->hdmaIn->XferHalfCpltCallback = FMAC_DMAHalfGetData;
+ hfmac->hdmaIn->XferCpltCallback = FMAC_DMAGetData;
+ /* Set the DMA error callback */
+ hfmac->hdmaIn->XferErrorCallback = FMAC_DMAError;
+
+ /* Enable the DMA stream managing FMAC input data write */
+ if ((hfmac->hdmaIn->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if ((hfmac->hdmaIn->LinkedListQueue != NULL) && (hfmac->hdmaIn->LinkedListQueue->Head != NULL))
+ {
+ /* Enable the DMA channel */
+ hfmac->hdmaIn->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] =
+ (uint32_t)(2UL * (*pInputSize)); /* Set DMA data size */
+ hfmac->hdmaIn->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
+ (uint32_t)pInput; /* Set DMA source address */
+ hfmac->hdmaIn->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
+ (uint32_t)&hfmac->Instance->WDATA;/* Set DMA destination address */
+
+ status = HAL_DMAEx_List_Start_IT(hfmac->hdmaIn);
+ }
+ else
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_DMA_Start_IT(hfmac->hdmaIn, (uint32_t)pInput, \
+ (uint32_t)&hfmac->Instance->WDATA, (uint32_t)(2UL * (*pInputSize)));
+ }
+
+ if (status != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Update the input data information (polling, IT) */
+ hfmac->pInput = pInput;
+ hfmac->pInputSize = pInputSize;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Register the new output buffer, update DMA configuration if needed and change the FMAC state.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @param pOutput New output vector.
+ * @param pOutputSize Size of the output vector (if the vector can't
+ * be entirely filled, pOutputSize will be updated with the number
+ * of data read from FMAC).
+ * @retval HAL_StatusTypeDef HAL status
+ */
+static HAL_StatusTypeDef FMAC_ConfigFilterOutputBufferUpdateState(FMAC_HandleTypeDef *hfmac, int16_t *pOutput,
+ uint16_t *pOutputSize)
+{
+ HAL_StatusTypeDef status;
+ /* Reset the current size */
+ hfmac->OutputCurrentSize = 0U;
+
+ /* Check whether a valid pointer was provided */
+ if ((pOutput == NULL) || (pOutputSize == NULL) || (*pOutputSize == 0U))
+ {
+ /* The user will have to provide a valid configuration later */
+ hfmac->pOutput = NULL;
+ hfmac->pOutputSize = NULL;
+ hfmac->RdState = HAL_FMAC_STATE_READY;
+ }
+ /* Handle the pointer depending on the input access */
+ else if (hfmac->OutputAccess == FMAC_BUFFER_ACCESS_DMA)
+ {
+ hfmac->pOutput = NULL;
+ hfmac->pOutputSize = NULL;
+ hfmac->RdState = HAL_FMAC_STATE_BUSY_RD;
+
+ /* Set the FMAC DMA transfer complete callback */
+ hfmac->hdmaOut->XferHalfCpltCallback = FMAC_DMAHalfOutputDataReady;
+ hfmac->hdmaOut->XferCpltCallback = FMAC_DMAOutputDataReady;
+ /* Set the DMA error callback */
+ hfmac->hdmaOut->XferErrorCallback = FMAC_DMAError;
+
+ /* Enable the DMA stream managing FMAC output data read */
+ if ((hfmac->hdmaOut->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if ((hfmac->hdmaOut->LinkedListQueue != NULL) && (hfmac->hdmaOut->LinkedListQueue->Head != NULL))
+ {
+ /* Enable the DMA channel */
+ hfmac->hdmaOut->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] =
+ (uint32_t)(4UL * (*pOutputSize)); /* Set DMA data size */
+ hfmac->hdmaOut->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
+ (uint32_t)&hfmac->Instance->RDATA;/* Set DMA source address */
+ hfmac->hdmaOut->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
+ (uint32_t)pOutput; /* Set DMA destination address */
+
+ status = HAL_DMAEx_List_Start_IT(hfmac->hdmaOut);
+ }
+ else
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_DMA_Start_IT(hfmac->hdmaOut, (uint32_t)&hfmac->Instance->RDATA, \
+ (uint32_t)pOutput, (uint32_t)(4UL * (*pOutputSize)));
+ }
+
+ if (status != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ }
+ else if (hfmac->OutputAccess == FMAC_BUFFER_ACCESS_NONE)
+ {
+ hfmac->pOutput = NULL;
+ hfmac->pOutputSize = NULL;
+ hfmac->RdState = HAL_FMAC_STATE_READY;
+ }
+ else
+ {
+ /* Update the output data information (polling, IT) */
+ hfmac->pOutput = pOutput;
+ hfmac->pOutputSize = pOutputSize;
+ hfmac->RdState = HAL_FMAC_STATE_BUSY_RD;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read available output data until Y EMPTY is set.
+ * @param hfmac FMAC handle.
+ * @param MaxSizeToRead Maximum number of data to read (this serves as a timeout
+ * if FMAC continuously writes into the output buffer).
+ * @retval None
+ */
+static void FMAC_ReadDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSizeToRead)
+{
+ uint16_t maxsize;
+ uint16_t threshold;
+ uint32_t tmpvalue;
+
+ /* Check if there is data to read */
+ if (READ_BIT(hfmac->Instance->SR, FMAC_SR_YEMPTY) != 0U)
+ {
+ return;
+ }
+
+ /* Get the maximum index (no wait allowed, no overstepping of the output buffer) */
+ if ((hfmac->OutputCurrentSize + MaxSizeToRead) > *(hfmac->pOutputSize))
+ {
+ maxsize = *(hfmac->pOutputSize);
+ }
+ else
+ {
+ maxsize = hfmac->OutputCurrentSize + MaxSizeToRead;
+ }
+
+ /* Read until there is no more room or no more data */
+ do
+ {
+ /* If there is no more room, return */
+ if (!(hfmac->OutputCurrentSize < maxsize))
+ {
+ return;
+ }
+
+ /* Read the available data */
+ tmpvalue = ((READ_REG(hfmac->Instance->RDATA))& FMAC_RDATA_RDATA);
+ *(hfmac->pOutput) = (int16_t)tmpvalue;
+ hfmac->pOutput++;
+ hfmac->OutputCurrentSize++;
+ } while (READ_BIT(hfmac->Instance->SR, FMAC_SR_YEMPTY) == 0U);
+
+ /* Y buffer empty flag has just be raised, read the threshold */
+ threshold = (uint16_t)FMAC_GET_THRESHOLD_FROM_WM(FMAC_GET_Y_EMPTY_WM(hfmac)) - 1U;
+
+ /* Update the maximum size if needed (limited data available) */
+ if ((hfmac->OutputCurrentSize + threshold) < maxsize)
+ {
+ maxsize = hfmac->OutputCurrentSize + threshold;
+ }
+
+ /* Read the available data */
+ while (hfmac->OutputCurrentSize < maxsize)
+ {
+ tmpvalue = ((READ_REG(hfmac->Instance->RDATA))& FMAC_RDATA_RDATA);
+ *(hfmac->pOutput) = (int16_t)tmpvalue;
+ hfmac->pOutput++;
+ hfmac->OutputCurrentSize++;
+ }
+}
+
+/**
+ * @brief Write available input data until X1 FULL is set.
+ * @param hfmac FMAC handle.
+ * @param MaxSizeToWrite Maximum number of data to write (this serves as a timeout
+ * if FMAC continuously empties the input buffer).
+ * @retval None
+ */
+static void FMAC_WriteDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSizeToWrite)
+{
+ uint16_t maxsize;
+ uint16_t threshold;
+
+ /* Check if there is room in FMAC */
+ if (READ_BIT(hfmac->Instance->SR, FMAC_SR_X1FULL) != 0U)
+ {
+ return;
+ }
+
+ /* Get the maximum index (no wait allowed, no overstepping of the output buffer) */
+ if ((hfmac->InputCurrentSize + MaxSizeToWrite) > *(hfmac->pInputSize))
+ {
+ maxsize = *(hfmac->pInputSize);
+ }
+ else
+ {
+ maxsize = hfmac->InputCurrentSize + MaxSizeToWrite;
+ }
+
+ /* Write until there is no more room or no more data */
+ do
+ {
+ /* If there is no more room, return */
+ if (!(hfmac->InputCurrentSize < maxsize))
+ {
+ return;
+ }
+
+ /* Write the available data */
+ WRITE_REG(hfmac->Instance->WDATA, (((uint32_t)(*(hfmac->pInput))) & FMAC_WDATA_WDATA));
+ hfmac->pInput++;
+ hfmac->InputCurrentSize++;
+ } while (READ_BIT(hfmac->Instance->SR, FMAC_SR_X1FULL) == 0U);
+
+ /* X1 buffer full flag has just be raised, read the threshold */
+ threshold = (uint16_t)FMAC_GET_THRESHOLD_FROM_WM(FMAC_GET_X1_FULL_WM(hfmac)) - 1U;
+
+ /* Update the maximum size if needed (limited data available) */
+ if ((hfmac->InputCurrentSize + threshold) < maxsize)
+ {
+ maxsize = hfmac->InputCurrentSize + threshold;
+ }
+
+ /* Write the available data */
+ while (hfmac->InputCurrentSize < maxsize)
+ {
+ WRITE_REG(hfmac->Instance->WDATA, (((uint32_t)(*(hfmac->pInput))) & FMAC_WDATA_WDATA));
+ hfmac->pInput++;
+ hfmac->InputCurrentSize++;
+ }
+}
+
+/**
+ * @brief DMA FMAC Input Data process half complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void FMAC_DMAHalfGetData(DMA_HandleTypeDef *hdma)
+{
+ FMAC_HandleTypeDef *hfmac = (FMAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Call half get data callback */
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+ hfmac->HalfGetDataCallback(hfmac);
+#else
+ HAL_FMAC_HalfGetDataCallback(hfmac);
+#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA FMAC Input Data process complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void FMAC_DMAGetData(DMA_HandleTypeDef *hdma)
+{
+ FMAC_HandleTypeDef *hfmac = (FMAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Reset the pointers to indicate new data will be needed */
+ FMAC_ResetInputStateAndDataPointers(hfmac);
+
+ /* Call get data callback */
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+ hfmac->GetDataCallback(hfmac);
+#else
+ HAL_FMAC_GetDataCallback(hfmac);
+#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA FMAC Output Data process half complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void FMAC_DMAHalfOutputDataReady(DMA_HandleTypeDef *hdma)
+{
+ FMAC_HandleTypeDef *hfmac = (FMAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Call half output data ready callback */
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+ hfmac->HalfOutputDataReadyCallback(hfmac);
+#else
+ HAL_FMAC_HalfOutputDataReadyCallback(hfmac);
+#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA FMAC Output Data process complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void FMAC_DMAOutputDataReady(DMA_HandleTypeDef *hdma)
+{
+ FMAC_HandleTypeDef *hfmac = (FMAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Reset the pointers to indicate new data will be needed */
+ FMAC_ResetOutputStateAndDataPointers(hfmac);
+
+ /* Call output data ready callback */
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+ hfmac->OutputDataReadyCallback(hfmac);
+#else
+ HAL_FMAC_OutputDataReadyCallback(hfmac);
+#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA FMAC Filter Configuration process complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void FMAC_DMAFilterConfig(DMA_HandleTypeDef *hdma)
+{
+ HAL_StatusTypeDef status;
+ uint8_t index;
+
+ FMAC_HandleTypeDef *hfmac = (FMAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* If needed, write CoeffA and exit */
+ if (hfmac->pInput != NULL)
+ {
+ /* Set the FMAC DMA transfer complete callback */
+ hfmac->hdmaPreload->XferHalfCpltCallback = NULL;
+ hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterConfig;
+ /* Set the DMA error callback */
+ hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError;
+
+ /* Enable the DMA stream managing FMAC preload data write */
+ if ((hfmac->hdmaPreload->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if ((hfmac->hdmaPreload->LinkedListQueue != NULL) && (hfmac->hdmaPreload->LinkedListQueue->Head != NULL))
+ {
+ /* Enable the DMA channel */
+ hfmac->hdmaPreload->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] =
+ (uint32_t)(2UL * hfmac->InputCurrentSize);/* Set DMA data size */
+ hfmac->hdmaPreload->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
+ (uint32_t)hfmac->pInput; /* Set DMA source address */
+ hfmac->hdmaPreload->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
+ (uint32_t)&hfmac->Instance->WDATA; /* Set DMA destination address */
+
+ status = HAL_DMAEx_List_Start_IT(hfmac->hdmaPreload);
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)hfmac->pInput, \
+ (uint32_t)&hfmac->Instance->WDATA, (uint32_t)(2UL * hfmac->InputCurrentSize));
+ }
+
+ if (status == HAL_OK)
+ {
+ hfmac->pInput = NULL;
+ hfmac->InputCurrentSize = 0U;
+ return;
+ }
+
+ /* If not exited, there was an error: set FMAC handle state to error */
+ hfmac->State = HAL_FMAC_STATE_ERROR;
+ }
+ else
+ {
+ /* Wait for the end of the writing */
+ for (index = 0U; index < MAX_PRELOAD_INDEX; index++)
+ {
+ if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) == 0U)
+ {
+ break;
+ }
+ }
+
+ /* If 'START' is still set, there was a timeout: set FMAC handle state to timeout */
+ if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0U)
+ {
+ hfmac->State = HAL_FMAC_STATE_TIMEOUT;
+ }
+ else
+ {
+ /* Change the FMAC state */
+ hfmac->State = HAL_FMAC_STATE_READY;
+
+ /* Call output data ready callback */
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+ hfmac->FilterConfigCallback(hfmac);
+#else
+ HAL_FMAC_FilterConfigCallback(hfmac);
+#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
+ return;
+ }
+ }
+
+ /* If not exited, there was an error: set FMAC handle error code to DMA error */
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_DMA;
+
+ /* Call user callback */
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+ hfmac->ErrorCallback(hfmac);
+#else
+ HAL_FMAC_ErrorCallback(hfmac);
+#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
+
+}
+
+/**
+ * @brief DMA FMAC Filter Configuration process complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void FMAC_DMAFilterPreload(DMA_HandleTypeDef *hdma)
+{
+ HAL_StatusTypeDef status;
+ uint8_t index;
+
+ FMAC_HandleTypeDef *hfmac = (FMAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Wait for the end of the X1 writing */
+ for (index = 0U; index < MAX_PRELOAD_INDEX; index++)
+ {
+ if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) == 0U)
+ {
+ break;
+ }
+ }
+
+ /* If 'START' is still set, there was an error: set FMAC handle state to error */
+ if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0U)
+ {
+ hfmac->State = HAL_FMAC_STATE_TIMEOUT;
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
+ }
+ /* If needed, preload Y buffer */
+ else if ((hfmac->pInput != NULL) && (hfmac->InputCurrentSize != 0U))
+ {
+ /* Write number of values to be loaded, the data load function and start the operation */
+ WRITE_REG(hfmac->Instance->PARAM, \
+ (((uint32_t)(hfmac->InputCurrentSize) << FMAC_PARAM_P_Pos) | FMAC_FUNC_LOAD_Y | FMAC_PARAM_START));
+
+ /* Set the FMAC DMA transfer complete callback */
+ hfmac->hdmaPreload->XferHalfCpltCallback = NULL;
+ hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterPreload;
+ /* Set the DMA error callback */
+ hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError;
+
+ /* Enable the DMA stream managing FMAC preload data write */
+ if ((hfmac->hdmaPreload->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if ((hfmac->hdmaPreload->LinkedListQueue != NULL) && (hfmac->hdmaPreload->LinkedListQueue->Head != NULL))
+ {
+ /* Enable the DMA channel */
+ hfmac->hdmaPreload->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] =
+ (uint32_t)(2UL * hfmac->InputCurrentSize);/* Set DMA data size */
+ hfmac->hdmaPreload->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
+ (uint32_t)hfmac->pInput; /* Set DMA source address */
+ hfmac->hdmaPreload->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
+ (uint32_t)&hfmac->Instance->WDATA; /* Set DMA destination address */
+
+ status = HAL_DMAEx_List_Start_IT(hfmac->hdmaPreload);
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)hfmac->pInput, \
+ (uint32_t)&hfmac->Instance->WDATA, (uint32_t)(2UL * hfmac->InputCurrentSize));
+ }
+
+ if (status == HAL_OK)
+ {
+ hfmac->pInput = NULL;
+ hfmac->InputCurrentSize = 0U;
+ return;
+ }
+
+ /* If not exited, there was an error */
+ hfmac->ErrorCode = HAL_FMAC_ERROR_DMA;
+ hfmac->State = HAL_FMAC_STATE_ERROR;
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+ if (hfmac->ErrorCode == HAL_FMAC_ERROR_NONE)
+ {
+ /* Change the FMAC state */
+ hfmac->State = HAL_FMAC_STATE_READY;
+
+ /* Call output data ready callback */
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+ hfmac->FilterPreloadCallback(hfmac);
+#else
+ HAL_FMAC_FilterPreloadCallback(hfmac);
+#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Call user callback */
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+ hfmac->ErrorCallback(hfmac);
+#else
+ HAL_FMAC_ErrorCallback(hfmac);
+#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
+ }
+}
+
+
+/**
+ * @brief DMA FMAC communication error callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void FMAC_DMAError(DMA_HandleTypeDef *hdma)
+{
+ FMAC_HandleTypeDef *hfmac = (FMAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Set FMAC handle state to error */
+ hfmac->State = HAL_FMAC_STATE_ERROR;
+
+ /* Set FMAC handle error code to DMA error */
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_DMA;
+
+ /* Call user callback */
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+ hfmac->ErrorCallback(hfmac);
+#else
+ HAL_FMAC_ErrorCallback(hfmac);
+#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
+}
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_FMAC_MODULE_ENABLED */
+#endif /* FMAC */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gpio.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gpio.c
new file mode 100644
index 00000000..3402acdb
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gpio.c
@@ -0,0 +1,957 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_gpio.c
+ * @author MCD Application Team
+ * @brief GPIO HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the General Purpose Input/Output (GPIO) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### GPIO Peripheral features #####
+ ==============================================================================
+ [..]
+ (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
+ configured by software in several modes:
+ (++) Input mode
+ (++) Analog mode
+ (++) Output mode
+ (++) Alternate function mode
+ (++) External interrupt/event lines
+
+ (+) During and just after reset, the alternate functions and external interrupt
+ lines are not active and the I/O ports are configured in input floating mode.
+
+ (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
+ activated or not.
+
+ (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
+ type and the IO speed can be selected depending on the VDD value.
+
+ (+) The microcontroller IO pins are connected to onboard peripherals/modules through a
+ multiplexer that allows only one peripheral alternate function (AF) connected
+ to an IO pin at a time. In this way, there can be no conflict between peripherals
+ sharing the same IO pin.
+
+ (+) All ports have external interrupt/event capability. To use external interrupt
+ lines, the port must be configured in input mode. All available GPIO pins are
+ connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
+
+ (+) The external interrupt/event controller consists of up to 39 edge detectors
+ (16 lines are connected to GPIO) for generating event/interrupt requests (each
+ input line can be independently configured to select the type (interrupt or event)
+ and the corresponding trigger event (rising or falling or both). Each line can
+ also be masked independently.
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
+
+ (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
+ (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
+ (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
+ structure.
+ (++) In case of Output or alternate function mode selection: the speed is
+ configured through "Speed" member from GPIO_InitTypeDef structure.
+ (++) In alternate mode is selection, the alternate function connected to the IO
+ is configured through "Alternate" member from GPIO_InitTypeDef structure.
+ (++) Analog mode is required when a pin is to be used as ADC channel
+ or DAC output.
+ (++) In case of external interrupt/event selection the "Mode" member from
+ GPIO_InitTypeDef structure select the type (interrupt or event) and
+ the corresponding trigger event (rising or falling or both).
+
+ (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
+ mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
+ HAL_NVIC_EnableIRQ().
+
+ (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
+
+ (#) To set/reset the level of a pin configured in output mode use
+ HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
+
+ (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
+
+ (#) During and just after reset, the alternate functions are not
+ active and the GPIO pins are configured in input floating mode (except JTAG
+ pins).
+
+ (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
+ (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
+ priority over the GPIO function.
+
+ (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
+ general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
+ The HSE has priority over the GPIO function.
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup GPIO
+ * @{
+ */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup GPIO_Private_Defines GPIO Private Defines
+ * @{
+ */
+#define GPIO_MODE (0x00000003U)
+#define EXTI_MODE (0x10000000U)
+#define GPIO_MODE_IT (0x00010000U)
+#define GPIO_MODE_EVT (0x00020000U)
+#define RISING_EDGE (0x00100000U)
+#define FALLING_EDGE (0x00200000U)
+#define GPIO_OUTPUT_TYPE (0x00000010U)
+#define GPIO_NUMBER (16U)
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup GPIO_Private_Variables GPIO Private Variables
+ * @{
+ */
+
+/* LPGPIO Mapping */
+static const LPGPIO_MapTypeDef LPGPIO_Map[GPIO_NUMBER] =
+{
+ /* LPGPIO Pins Port Pin */
+ /* Pin 0:*/ {GPIOA, 1},
+ /* Pin 1:*/ {GPIOA, 3},
+ /* Pin 2:*/ {GPIOA, 6},
+ /* Pin 3:*/ {GPIOB, 1},
+ /* Pin 4:*/ {GPIOB, 10},
+ /* Pin 5:*/ {GPIOC, 2},
+ /* Pin 6:*/ {GPIOD, 13},
+ /* Pin 7:*/ {GPIOD, 2},
+ /* Pin 8:*/ {GPIOC, 10},
+ /* Pin 9:*/ {GPIOB, 0},
+ /* Pin 10:*/ {GPIOC, 12},
+ /* Pin 11:*/ {GPIOB, 3},
+ /* Pin 12:*/ {GPIOB, 4},
+ /* Pin 13:*/ {GPIOE, 0},
+ /* Pin 14:*/ {GPIOE, 2},
+ /* Pin 15:*/ {GPIOE, 3},
+};
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup GPIO_Exported_Functions
+ * @{
+ */
+
+/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the GPIOx/LPGPIOx peripheral according to the specified parameters in the pGPIO_Init.
+ * @note If GPIOx/LPGPIOx peripheral pin is used in EXTI_MODE and the pin is secure in case
+ * the system implements the security (TZEN=1), it is up to the secure application to
+ * insure that the corresponding EXTI line is set secure.
+ * @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the corresponding
+ * peripheral for STM32U5 family
+ * @param pGPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
+ * the configuration information for the specified GPIO peripheral.
+ * @retval None
+ */
+void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init)
+{
+ uint32_t tmp;
+ uint32_t iocurrent;
+ uint32_t pin_position;
+ uint32_t position = 0U;
+ GPIO_TypeDef *p_gpio;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_PIN(pGPIO_Init->Pin));
+ assert_param(IS_GPIO_MODE(pGPIO_Init->Mode));
+
+ /* Save GPIO port address */
+ p_gpio = GPIOx;
+
+ /* Configure the port pins */
+ while (((pGPIO_Init->Pin) >> position) != 0U)
+ {
+ /* Get current io position */
+ iocurrent = (pGPIO_Init->Pin) & (1UL << position);
+
+ /* Save Pin Position */
+ pin_position = position;
+
+ if (iocurrent != 0U)
+ {
+ /*--------------------- GPIO Mode Configuration ------------------------*/
+ /* In case of Alternate function mode selection */
+ if (GPIOx == LPGPIO1)
+ {
+ /* MODER configuration */
+ tmp = GPIOx->MODER;
+ tmp &= ~(LPGPIO_MODER_MOD0 << position);
+ tmp |= ((pGPIO_Init->Mode & GPIO_MODE_OUTPUT_PP) << position);
+ GPIOx->MODER = tmp;
+
+ /* Save GPIO Port and pin index */
+ p_gpio = LPGPIO_Map[position].GPIO_PORT;
+ pin_position = LPGPIO_Map[position].Pin_Pos;
+
+ /* Configure Alternate function mapped with the current IO */
+ tmp = p_gpio->AFR[(pin_position) >> 3U];
+ tmp &= ~(0x0FUL << (((pin_position) & 0x07U) * 4U));
+ tmp |= ((GPIO_AF11_LPGPIO & 0x0FUL) << (((pin_position) & 0x07U) * 4U));
+ p_gpio->AFR[(pin_position) >> 3U] = tmp;
+
+ /* Configure IO Direction mode (Alternate) */
+ tmp = p_gpio->MODER;
+ tmp &= ~(GPIO_MODER_MODE0 << (pin_position * 2U));
+ tmp |= ((GPIO_MODE_AF_PP & 0x0FUL) << (pin_position * 2U));
+ p_gpio->MODER = tmp;
+ }
+ else if ((pGPIO_Init->Mode == GPIO_MODE_AF_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_OD))
+ {
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_AF(pGPIO_Init->Alternate));
+
+ /* Configure Alternate function mapped with the current IO */
+ tmp = GPIOx->AFR[position >> 3U];
+ tmp &= ~(0x0FUL << ((position & 0x07U) * 4U));
+ tmp |= ((pGPIO_Init->Alternate & 0x0FUL) << ((position & 0x07U) * 4U));
+ GPIOx->AFR[position >> 3U] = tmp;
+
+ /* Configure IO Direction mode (Alternate) */
+ tmp = p_gpio->MODER;
+ tmp &= ~(GPIO_MODER_MODE0 << (pin_position * 2U));
+ tmp |= ((pGPIO_Init->Mode & GPIO_MODE) << (pin_position * 2U));
+ p_gpio->MODER = tmp;
+ }
+ else
+ {
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+
+ /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+ tmp = p_gpio->MODER;
+ tmp &= ~(GPIO_MODER_MODE0 << (pin_position * 2U));
+ tmp |= ((pGPIO_Init->Mode & GPIO_MODE) << (pin_position * 2U));
+ p_gpio->MODER = tmp;
+ }
+
+ /* In case of Output or Alternate function mode selection */
+ if ((pGPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_PP) ||
+ (pGPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (pGPIO_Init->Mode == GPIO_MODE_AF_OD))
+ {
+ /* Check the Speed parameter */
+ assert_param(IS_GPIO_SPEED(pGPIO_Init->Speed));
+
+ /* Configure the IO Speed */
+ tmp = p_gpio->OSPEEDR;
+ tmp &= ~(GPIO_OSPEEDR_OSPEED0 << (pin_position * 2U));
+ tmp |= (pGPIO_Init->Speed << (pin_position * 2U));
+ p_gpio->OSPEEDR = tmp;
+
+ /* Configure the IO Output Type */
+ tmp = p_gpio->OTYPER;
+ tmp &= ~(GPIO_OTYPER_OT0 << pin_position);
+ tmp |= (((pGPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << pin_position);
+ p_gpio->OTYPER = tmp;
+ }
+
+ if (pGPIO_Init->Mode != GPIO_MODE_ANALOG)
+ {
+ /* Check the Pull parameters */
+ assert_param(IS_GPIO_PULL(pGPIO_Init->Pull));
+
+ /* Activate the Pull-up or Pull down resistor for the current IO */
+ tmp = p_gpio->PUPDR;
+ tmp &= ~(GPIO_PUPDR_PUPD0 << (pin_position * 2U));
+ tmp |= ((pGPIO_Init->Pull) << (pin_position * 2U));
+ p_gpio->PUPDR = tmp;
+ }
+
+ /*--------------------- EXTI Mode Configuration ------------------------*/
+ /* Configure the External Interrupt or event for the current IO */
+ if ((pGPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
+ {
+ tmp = EXTI->EXTICR[position >> 2U];
+ tmp &= ~((0x0FUL) << (8U * (position & 0x03U)));
+ tmp |= (GPIO_GET_INDEX(GPIOx) << (8U * (position & 0x03U)));
+ EXTI->EXTICR[position >> 2U] = tmp;
+
+ /* Clear EXTI line configuration */
+ tmp = EXTI->IMR1;
+ tmp &= ~((uint32_t)iocurrent);
+ if ((pGPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
+ {
+ tmp |= iocurrent;
+ }
+ EXTI->IMR1 = tmp;
+
+ tmp = EXTI->EMR1;
+ tmp &= ~((uint32_t)iocurrent);
+ if ((pGPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
+ {
+ tmp |= iocurrent;
+ }
+ EXTI->EMR1 = tmp;
+
+ /* Clear Rising Falling edge configuration */
+ tmp = EXTI->RTSR1;
+ tmp &= ~((uint32_t)iocurrent);
+ if ((pGPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
+ {
+ tmp |= iocurrent;
+ }
+ EXTI->RTSR1 = tmp;
+
+ tmp = EXTI->FTSR1;
+ tmp &= ~((uint32_t)iocurrent);
+ if ((pGPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
+ {
+ tmp |= iocurrent;
+ }
+ EXTI->FTSR1 = tmp;
+ }
+ }
+ position++;
+ }
+}
+
+/**
+ * @brief De-initialize the GPIOx peripheral registers to their default reset values.
+ * @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding
+ * peripheral for STM32U5 family
+ * @param GPIO_Pin: specifies the port bit to be written.
+ * This parameter can be one of GPIO_PIN_x where x can be (0..15).
+ * @retval None
+ */
+void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
+{
+ uint32_t tmp;
+ uint32_t iocurrent;
+ uint32_t pin_position;
+ uint32_t position = 0U;
+ GPIO_TypeDef *p_gpio;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ /* Save GPIO port address */
+ p_gpio = GPIOx;
+
+ /* Configure the port pins */
+ while ((GPIO_Pin >> position) != 0U)
+ {
+ /* Get current io position */
+ iocurrent = (GPIO_Pin) & (1UL << position);
+
+ /*Save Pin Position */
+ pin_position = position;
+
+ if (iocurrent != 0U)
+ {
+ /* In case of LPGPIO port selected */
+ if (GPIOx == LPGPIO1)
+ {
+ /* Configure LP/IO in Input Mode */
+ p_gpio = LPGPIO_Map[pin_position].GPIO_PORT;
+ pin_position = LPGPIO_Map[position].Pin_Pos;
+ LPGPIO1->MODER &= ~(1U << pin_position);
+ }
+ else
+ {
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+
+ /*------------------------- EXTI Mode Configuration --------------------*/
+ /* Clear the External Interrupt or Event for the current IO */
+ tmp = EXTI->EXTICR[position >> 2U];
+ tmp &= ((0x0FUL) << (8U * (position & 0x03U)));
+ if (tmp == (GPIO_GET_INDEX(GPIOx) << (8U * (position & 0x03U))))
+ {
+ /* Clear EXTI line configuration */
+ EXTI->IMR1 &= ~(iocurrent);
+ EXTI->EMR1 &= ~(iocurrent);
+
+ /* Clear Rising Falling edge configuration */
+ EXTI->RTSR1 &= ~(iocurrent);
+ EXTI->FTSR1 &= ~(iocurrent);
+
+ tmp = (0x0FUL) << (8U * (position & 0x03U));
+ EXTI->EXTICR[position >> 2U] &= ~tmp;
+ }
+ }
+
+ /*------------------------- GPIO Mode Configuration --------------------*/
+ /* Configure IO in Analog Mode */
+ p_gpio->MODER |= (GPIO_MODER_MODE0 << (pin_position * 2U));
+
+ /* Configure the default Alternate Function in current IO */
+ p_gpio->AFR[pin_position >> 3U] &= ~(0x0FUL << ((pin_position & 0x07U) * 4U));
+
+ /* Configure the default value for IO Speed */
+ p_gpio->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (pin_position * 2U));
+
+ /* Configure the default value IO Output Type */
+ p_gpio->OTYPER &= ~(GPIO_OTYPER_OT0 << pin_position);
+
+ /* Deactivate the Pull-up and Pull-down resistor for the current IO */
+ p_gpio->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (pin_position * 2U));
+ }
+
+ position++;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Exported_Functions_Group2
+ * @brief GPIO/LPGPIO Read, Write, Toggle, Lock and EXTI management functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Read the specified input port pin.
+ * @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding
+ * peripheral for STM32U5 family
+ * @param GPIO_Pin: specifies the port bit to read.
+ * This parameter can be GPIO_PIN_x where x can be (0..15).
+ * @retval The input port pin value.
+ */
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+ GPIO_PinState bitstatus;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ if ((GPIOx->IDR & GPIO_Pin) != 0U)
+ {
+ bitstatus = GPIO_PIN_SET;
+ }
+ else
+ {
+ bitstatus = GPIO_PIN_RESET;
+ }
+
+ return bitstatus;
+}
+
+/**
+ * @brief Set or clear the selected data port bit.
+ * @note This function uses GPIOx_BSRR/LPGPIOx_BSRR and GPIOx_BRR/LPGPIOx_BRR registers to allow atomic read/modify
+ * accesses. In this way, there is no risk of an IRQ occurring between
+ * the read and the modify access.
+ * @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding
+ * peripheral for STM32U5 family
+ * @param GPIO_Pin: specifies the port bit to be written.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ * @param PinState: specifies the value to be written to the selected bit.
+ * This parameter can be one of the GPIO_PinState enum values:
+ * @arg GPIO_PIN_RESET: to clear the port pin
+ * @arg GPIO_PIN_SET: to set the port pin
+ * @retval None
+ */
+void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+ assert_param(IS_GPIO_PIN_ACTION(PinState));
+
+ if (PinState != GPIO_PIN_RESET)
+ {
+ GPIOx->BSRR = (uint32_t)GPIO_Pin;
+ }
+ else
+ {
+ GPIOx->BRR = (uint32_t)GPIO_Pin;
+ }
+}
+
+/**
+ * @brief Toggle the specified GPIO pin.
+ * @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding
+ * peripheral for STM32U5 family
+ * @param GPIO_Pin specifies the pin to be toggled.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ * @retval None
+ */
+void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+ uint32_t odr;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ /* get current Output Data Register value */
+ odr = GPIOx->ODR;
+
+ /* Set selected pins that were at low level, and reset ones that were high */
+ GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
+}
+
+/**
+ * @brief Lock GPIO Pins configuration registers.
+ * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
+ * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
+ * @note The configuration of the locked GPIO pins can no longer be modified
+ * until the next reset.
+ * @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding
+ * peripheral for STM32U5 family
+ * @param GPIO_Pin: specifies the port bits to be locked.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+ uint32_t iocurrent;
+ uint32_t pin_locked;
+ uint32_t pin_position;
+ uint32_t position = 0U;
+ GPIO_TypeDef *p_gpio;
+ __IO uint32_t tmp = GPIO_LCKR_LCKK;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ /* Save GPIO port address */
+ p_gpio = GPIOx;
+
+ /* Configure the port pins */
+ while ((GPIO_Pin >> position) != 0U)
+ {
+ /* Get current io position */
+ iocurrent = GPIO_Pin & (1UL << position);
+
+ if (iocurrent != 0U)
+ {
+
+ /* In case of LPGPIO Port */
+ if (GPIOx == LPGPIO1)
+ {
+ /* Save GPIO Port and pin index */
+ p_gpio = LPGPIO_Map[position].GPIO_PORT;
+ pin_position = (1UL << (LPGPIO_Map[position].Pin_Pos));
+
+ /* Save gpio pin locked */
+ pin_locked = p_gpio->LCKR;
+
+ /* Apply lock key write sequence */
+ tmp |= (pin_locked | pin_position);
+ }
+ else
+ {
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+
+ /* Save GPIO Pin pos*/
+ pin_position = (1UL << position);
+
+ /* Save gpio pin locked */
+ pin_locked = p_gpio->LCKR;
+
+ /* Apply lock key write sequence */
+ tmp |= (pin_locked | pin_position);
+ }
+
+ /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+ p_gpio->LCKR = tmp;
+ /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
+ p_gpio->LCKR = pin_position;
+ /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+ p_gpio->LCKR = tmp;
+ /* Read LCKK register. This read is mandatory to complete key lock sequence */
+ tmp = p_gpio->LCKR;
+
+ /* read again in order to confirm lock is active */
+ if ((p_gpio->LCKR & GPIO_LCKR_LCKK) != GPIO_LCKR_LCKK)
+ {
+ return HAL_ERROR;
+ }
+ }
+ position++;
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable speed optimization for several pin of dedicated port.
+ * @note Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding
+ * datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must
+ * be kept at reset value.
+ * @note It must be used only if the I/O supply voltage is below 2.7 V.
+ * @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding
+ * peripheral for STM32U5 family
+ * @param GPIO_Pin: specifies the port bit to be written.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ * @retval None
+ */
+void HAL_GPIO_EnableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+ uint32_t iocurrent;
+ uint32_t pin_position;
+ uint32_t position = 0U;
+ GPIO_TypeDef *p_gpio;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ /* Save GPIO port address */
+ p_gpio = GPIOx;
+
+ /* Configure the port pins */
+ while ((GPIO_Pin >> position) != 0U)
+ {
+ /* Get current io position */
+ iocurrent = GPIO_Pin & (1UL << position);
+
+ if (iocurrent != 0U)
+ {
+ /* In case of LPGPIO Port */
+ if (GPIOx == LPGPIO1)
+ {
+ /* Get GPIO pin position */
+ position = POSITION_VAL(GPIO_Pin);
+
+ /* Save GPIO Port and pin index */
+ p_gpio = LPGPIO_Map[position].GPIO_PORT;
+ pin_position = (1UL << (LPGPIO_Map[position].Pin_Pos));
+ }
+ else
+ {
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+
+ /* Save GPIO pin pos */
+ pin_position = (1UL << position);
+ }
+ /* Set HSLVR gpio pin */
+ SET_BIT(p_gpio->HSLVR, pin_position);
+ }
+ position++;
+ }
+}
+
+/**
+ * @brief Disable speed optimization for several pin of dedicated port.
+ * @note Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding
+ * datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must
+ * be kept at reset value.
+ * @note It must be used only if the I/O supply voltage is below 2.7 V.
+ * @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding
+ * peripheral for STM32U5 family
+ * @param GPIO_Pin: specifies the port bit to be written.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ * @retval None
+ */
+void HAL_GPIO_DisableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+ uint32_t iocurrent;
+ uint32_t pin_position;
+ uint32_t position = 0U;
+ GPIO_TypeDef *p_gpio;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ /* Save GPIO port address */
+ p_gpio = GPIOx;
+
+ /* Configure the port pins */
+ while ((GPIO_Pin >> position) != 0U)
+ {
+ /* Get current io position */
+ iocurrent = GPIO_Pin & (1UL << position);
+
+ if (iocurrent != 0U)
+ {
+ /* In case of LPGPIO Port */
+ if (GPIOx == LPGPIO1)
+ {
+ /* Get GPIO pin position */
+ position = POSITION_VAL(GPIO_Pin);
+
+ /* Save GPIO Port and pin index */
+ p_gpio = LPGPIO_Map[position].GPIO_PORT;
+ pin_position = (1UL << (LPGPIO_Map[position].Pin_Pos));
+ }
+ else
+ {
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+
+ /* Save GPIO pin pos */
+ pin_position = (1UL << position);
+ }
+ /* Clear HSLVR gpio pin */
+ CLEAR_BIT(p_gpio->HSLVR, pin_position);
+ }
+ position++;
+ }
+}
+
+/**
+ * @brief Handle EXTI interrupt request.
+ * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
+ * @retval None
+ */
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
+{
+ /* EXTI line interrupt detected */
+ if (__HAL_GPIO_EXTI_GET_RISING_IT(GPIO_Pin) != 0U)
+ {
+ __HAL_GPIO_EXTI_CLEAR_RISING_IT(GPIO_Pin);
+ HAL_GPIO_EXTI_Rising_Callback(GPIO_Pin);
+ }
+
+ if (__HAL_GPIO_EXTI_GET_FALLING_IT(GPIO_Pin) != 0U)
+ {
+ __HAL_GPIO_EXTI_CLEAR_FALLING_IT(GPIO_Pin);
+ HAL_GPIO_EXTI_Falling_Callback(GPIO_Pin);
+ }
+}
+
+/**
+ * @brief EXTI line rising detection callback.
+ * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
+ * @retval None
+ */
+__weak void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(GPIO_Pin);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_GPIO_EXTI_Rising_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief EXTI line falling detection callback.
+ * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
+ * @retval None
+ */
+__weak void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(GPIO_Pin);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_GPIO_EXTI_Falling_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/** @defgroup GPIO_Exported_Functions_Group3 IO attributes management functions
+ * @brief GPIO attributes management functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### IO attributes functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the GPIO pins attributes.
+ * @note Available attributes are to secure GPIO pin(s), so this function is
+ * only available in secure
+ * @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding
+ * peripheral for STM32U5 family
+ * @param GPIO_Pin: specifies the pin(s) to configure the secure attribute
+ * @param PinAttributes: specifies the pin(s) to be set in secure mode, other being set non secured.
+ * @retval None
+ */
+void HAL_GPIO_ConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t PinAttributes)
+{
+ uint32_t iocurrent;
+ uint32_t pin_position;
+ uint32_t position = 0U;
+ GPIO_TypeDef *p_gpio;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+ assert_param(IS_GPIO_PIN_ATTRIBUTES(PinAttributes));
+
+ /* Save GPIO port address */
+ p_gpio = GPIOx;
+
+ /* Configure the port pins */
+ while ((GPIO_Pin >> position) != 0U)
+ {
+ /* Get current io position */
+ iocurrent = GPIO_Pin & (1UL << position);
+
+ /* Save pin position */
+ pin_position = position;
+
+ if (iocurrent != 0U)
+ {
+ /* In case of LPGPIO Port */
+ if (GPIOx == LPGPIO1)
+ {
+ /* Save GPIO Port and pin index */
+ p_gpio = LPGPIO_Map[position].GPIO_PORT;
+ pin_position = LPGPIO_Map[position].Pin_Pos;
+ }
+ else
+ {
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+ }
+
+ /* Configure the IO secure attribute */
+ MODIFY_REG(p_gpio->SECCFGR, (GPIO_SECCFGR_SEC0 << pin_position), (PinAttributes << pin_position));
+ }
+ position++;
+ }
+}
+
+/**
+ * @brief Get the GPIO pins attributes.
+ * @note Available attributes are to secure GPIO pin(s), so this function is
+ * only available in secure
+ * @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding
+ * peripheral for STM32U5 family
+ * @param GPIO_Pin: specifies the single pin to get the secure attribute from
+ * @param pPinAttributes: pointer to return the pin attributes.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t *pPinAttributes)
+{
+ uint32_t iocurrent;
+ uint32_t pin_position;
+ uint32_t position = 0U;
+ GPIO_TypeDef *p_gpio;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin) && (GPIO_Pin != GPIO_PIN_ALL));
+
+ /* Check null pointer */
+ if (pPinAttributes == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Get secure attribute of the port pin */
+ while ((GPIO_Pin >> position) != 0U)
+ {
+ /* Get current io position */
+ iocurrent = GPIO_Pin & (1UL << position);
+
+ if (iocurrent != 0U)
+ {
+ /* In case of LPGPIO Port */
+ if (GPIOx == LPGPIO1)
+ {
+ /* Save GPIO Port and pin index */
+ p_gpio = LPGPIO_Map[position].GPIO_PORT;
+ pin_position = LPGPIO_Map[position].Pin_Pos;
+ }
+ else
+ {
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+
+ /* Save GPIO port address */
+ p_gpio = GPIOx;
+
+ pin_position = (1UL << position);
+ }
+
+ /* Get the IO secure attribute */
+ if ((p_gpio->SECCFGR & (GPIO_SECCFGR_SEC0 << pin_position)) != 0U)
+ {
+ *pPinAttributes = GPIO_PIN_SEC;
+ }
+ else
+ {
+ *pPinAttributes = GPIO_PIN_NSEC;
+ }
+
+ break;
+ }
+ position++;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+#endif /* __ARM_FEATURE_CMSE */
+
+
+/**
+ * @}
+ */
+
+#endif /* HAL_GPIO_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gtzc.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gtzc.c
new file mode 100644
index 00000000..37491777
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gtzc.c
@@ -0,0 +1,1927 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_gtzc.c
+ * @author MCD Application Team
+ * @brief GTZC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of GTZC peripheral:
+ * + TZSC Initialization and Configuration functions
+ * + TZSC-MPCWM Initialization and Configuration functions
+ * + MPCBB Initialization and Configuration functions
+ * + TZSC, TZSC-MPCWM and MPCBB Lock functions
+ * + TZIC Initialization and Configuration functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### GTZC main features #####
+ ==============================================================================
+ [..]
+ (+) Global TrustZone Controller (GTZC) composed of three sub-blocks:
+ (++) TZSC: TrustZone security controller
+ This sub-block defines the secure/privileged state of master and slave
+ peripherals. It also controls the secure/privileged state of subregions
+ for the watermark memory peripheral controller (MPCWM).
+ (++) MPCBB: Block-Based memory protection controller
+ This sub-block defines the secure/privileged state of all blocks
+ (512-byte pages) of the associated SRAM.
+ (++) TZIC: TrustZone illegal access controller
+ This sub-block gathers all illegal access events in the system and
+ generates a secure interrupt towards NVIC.
+
+ (+) These sub-blocks are used to configure TrustZone system security in
+ a product having bus agents with programmable-security and privileged
+ attributes (securable) such as:
+ (++) on-chip RAM with programmable secure and/or privilege blocks (pages)
+ (++) AHB and APB peripherals with programmable security and/or privilege access
+ (++) AHB master granted as secure and/or privilege
+ (++) off-chip memories with secure and/or privilege areas
+
+ [..]
+ (+) TZIC accessible only with secure privileged transactions.
+ (+) Secure and non-secure access supported for privileged and unprivileged
+ part of TZSC and MPCBB
+ (+) Set of registers to define product security settings:
+ (++) Secure and privilege blocks for internal memories
+ (++) Secure and privilege regions for external memories
+ (++) Secure and privileged access mode for securable peripherals
+
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The GTZC HAL driver can be used as follows:
+
+ (#) Configure or get back securable peripherals attributes using
+ HAL_GTZC_TZSC_ConfigPeriphAttributes() / HAL_GTZC_TZSC_GetConfigPeriphAttributes()
+
+ (#) Configure or get back MPCWM memories attributes using
+ HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes() / HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes()
+
+ (#) Lock TZSC sub-block or get lock status using HAL_GTZC_TZSC_Lock() /
+ HAL_GTZC_TZSC_GetLock()
+
+ (#) Configure or get back MPCBB memories complete configuration using
+ HAL_GTZC_MPCBB_ConfigMem() / HAL_GTZC_MPCBB_GetConfigMem()
+
+ (#) Configure or get back MPCBB memories attributes using
+ HAL_GTZC_MPCBB_ConfigMemAttributes() / HAL_GTZC_MPCBB_GetConfigMemAttributes()
+
+ (#) Lock MPCBB configuration or get lock status using HAL_GTZC_MPCBB_Lock() /
+ HAL_GTZC_MPCBB_GetLock()
+
+ (#) Lock MPCBB super-blocks or get lock status using HAL_GTZC_MPCBB_LockConfig() /
+ HAL_GTZC_MPCBB_GetLockConfig()
+
+ (#) Illegal access detection can be configured through TZIC sub-block using
+ following functions: HAL_GTZC_TZIC_DisableIT() / HAL_GTZC_TZIC_EnableIT()
+
+ (#) Illegal access flags can be retrieved through HAL_GTZC_TZIC_GetFlag() and
+ HAL_GTZC_TZIC_ClearFlag() functions
+
+ (#) Illegal access interrupt service routines are served by HAL_GTZC_IRQHandler()
+ and user can add his own code using HAL_GTZC_TZIC_Callback()
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup GTZC GTZC
+ * @brief GTZC HAL module driver
+ * @{
+ */
+
+#ifdef HAL_GTZC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+
+/** @defgroup GTZC_Private_Constants GTZC Private Constants
+ * @{
+ */
+
+/* Definitions for TZSC_MPCWM */
+#define TZSC_MPCWM1_MEM_SIZE 0x10000000U /* 256MB max size */
+#define TZSC_MPCWM2_MEM_SIZE 0x10000000U /* 256MB max size */
+#define TZSC_MPCWM3_MEM_SIZE 0x10000000U /* 256MB max size */
+#define TZSC_MPCWM4_MEM_SIZE 0x00000800U /* 2KB max size */
+#define TZSC_MPCWM5_MEM_SIZE 0x10000000U /* 256MB max size */
+
+/* Definitions for GTZC TZSC & TZIC ALL register values */
+/* TZSC1 / TZIC1 instances */
+#define TZSC1_SECCFGR1_ALL (0x001FFFFFUL)
+#define TZSC1_SECCFGR2_ALL (0x000001FFUL)
+#define TZSC1_SECCFGR3_ALL (0x007FFFFFUL)
+
+#define TZSC1_PRIVCFGR1_ALL (0x001FFFFFUL)
+#define TZSC1_PRIVCFGR2_ALL (0x000001FFUL)
+#define TZSC1_PRIVCFGR3_ALL (0x007FFFFFUL)
+
+#define TZIC1_IER1_ALL (0x001FFFFFUL)
+#define TZIC1_IER2_ALL (0x000001FFUL)
+#define TZIC1_IER3_ALL (0x007FFFFFUL)
+#define TZIC1_IER4_ALL (0x3F0FC01FUL)
+
+#define TZIC1_FCR1_ALL (0x001FFFFFUL)
+#define TZIC1_FCR2_ALL (0x000001FFUL)
+#define TZIC1_FCR3_ALL (0x007FFFFFUL)
+#define TZIC1_FCR4_ALL (0x3F0FC01FUL)
+
+/* TZSC2 / TZIC2 instances */
+#define TZSC2_SECCFGR1_ALL (0x00001BFFUL)
+
+#define TZSC2_PRIVCFGR1_ALL (0x00001BFFUL)
+
+#define TZIC2_IER1_ALL (0x00001BFFUL)
+#define TZIC2_IER2_ALL (0x0300C07FUL)
+
+#define TZIC2_FCR1_ALL (0x00001BFFUL)
+#define TZIC2_FCR2_ALL (0x0300C07FUL)
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup GTZC_Private_Macros GTZC Private Macros
+ * @{
+ */
+
+#define IS_ADDRESS_IN(mem, address)\
+ ( ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \
+ && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_NS(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) \
+ || ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \
+ && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_S(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) )
+
+#define IS_ADDRESS_IN_S(mem, address)\
+ ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \
+ && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_S(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) )
+
+#define IS_ADDRESS_IN_NS(mem, address)\
+ ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \
+ && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_NS(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) )
+
+#define GTZC_BASE_ADDRESS(mem)\
+ ( mem ## _BASE )
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup GTZC_Exported_Functions GTZC Exported Functions
+ * @{
+ */
+
+/** @defgroup GTZC_Exported_Functions_Group1 TZSC Configuration functions
+ * @brief TZSC Configuration functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### TZSC Configuration functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to configure TZSC
+ TZSC: TrustZone Security Controller
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure TZSC on a single peripheral or on all peripherals.
+ * @note Secure and non-secure attributes can only be set from the secure
+ * state when the system implements the security (TZEN=1).
+ * @note Privilege and non-privilege attributes can only be set from the
+ * privilege state when TZEN=0 or TZEN=1
+ * @note Security and privilege attributes can be set independently.
+ * @note Default state is non-secure and unprivileged access allowed.
+ * @param PeriphId Peripheral identifier
+ * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
+ * Use GTZC_PERIPH_ALL to select all peripherals.
+ * @param PeriphAttributes Peripheral attributes, see @ref GTZC_TZSC_PeriphAttributes.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId,
+ uint32_t PeriphAttributes)
+{
+ uint32_t register_address;
+
+ /* check entry parameters */
+ if ((PeriphAttributes > (GTZC_TZSC_PERIPH_SEC | GTZC_TZSC_PERIPH_PRIV))
+ || (HAL_GTZC_TZSC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZSC_PERIPH_NUMBER)
+ || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
+ && (HAL_GTZC_TZSC_GET_ARRAY_INDEX(PeriphId) != 0U)))
+ {
+ return HAL_ERROR;
+ }
+
+ if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
+ {
+ /* special case where same attributes are applied to all peripherals */
+
+#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ /* secure configuration */
+ if ((PeriphAttributes & GTZC_TZSC_PERIPH_SEC) == GTZC_TZSC_PERIPH_SEC)
+ {
+ SET_BIT(GTZC_TZSC1->SECCFGR1, TZSC1_SECCFGR1_ALL);
+ SET_BIT(GTZC_TZSC1->SECCFGR2, TZSC1_SECCFGR2_ALL);
+ SET_BIT(GTZC_TZSC1->SECCFGR3, TZSC1_SECCFGR3_ALL);
+ SET_BIT(GTZC_TZSC2->SECCFGR1, TZSC2_SECCFGR1_ALL);
+ }
+ else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NSEC) == GTZC_TZSC_PERIPH_NSEC)
+ {
+ CLEAR_BIT(GTZC_TZSC1->SECCFGR1, TZSC1_SECCFGR1_ALL);
+ CLEAR_BIT(GTZC_TZSC1->SECCFGR2, TZSC1_SECCFGR2_ALL);
+ CLEAR_BIT(GTZC_TZSC1->SECCFGR3, TZSC1_SECCFGR3_ALL);
+ CLEAR_BIT(GTZC_TZSC2->SECCFGR1, TZSC2_SECCFGR1_ALL);
+ }
+ else
+ {
+ /* do nothing */
+ }
+#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+ /* privilege configuration */
+ if ((PeriphAttributes & GTZC_TZSC_PERIPH_PRIV) == GTZC_TZSC_PERIPH_PRIV)
+ {
+ SET_BIT(GTZC_TZSC1->PRIVCFGR1, TZSC1_PRIVCFGR1_ALL);
+ SET_BIT(GTZC_TZSC1->PRIVCFGR2, TZSC1_PRIVCFGR2_ALL);
+ SET_BIT(GTZC_TZSC1->PRIVCFGR3, TZSC1_PRIVCFGR3_ALL);
+ SET_BIT(GTZC_TZSC2->PRIVCFGR1, TZSC2_PRIVCFGR1_ALL);
+ }
+ else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NPRIV) == GTZC_TZSC_PERIPH_NPRIV)
+ {
+ CLEAR_BIT(GTZC_TZSC1->PRIVCFGR1, TZSC1_PRIVCFGR1_ALL);
+ CLEAR_BIT(GTZC_TZSC1->PRIVCFGR2, TZSC1_PRIVCFGR2_ALL);
+ CLEAR_BIT(GTZC_TZSC1->PRIVCFGR3, TZSC1_PRIVCFGR3_ALL);
+ CLEAR_BIT(GTZC_TZSC2->PRIVCFGR1, TZSC2_PRIVCFGR1_ALL);
+ }
+ else
+ {
+ /* do nothing */
+ }
+ }
+ else
+ {
+ /* common case where only one peripheral is configured */
+
+#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ /* secure configuration */
+ register_address = (uint32_t) &(HAL_GTZC_TZSC_GET_INSTANCE(PeriphId)->SECCFGR1)
+ + (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId));
+ if ((PeriphAttributes & GTZC_TZSC_PERIPH_SEC) == GTZC_TZSC_PERIPH_SEC)
+ {
+ SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
+ }
+ else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NSEC) == GTZC_TZSC_PERIPH_NSEC)
+ {
+ CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
+ }
+ else
+ {
+ /* do nothing */
+ }
+#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+ /* privilege configuration */
+ register_address = (uint32_t) &(HAL_GTZC_TZSC_GET_INSTANCE(PeriphId)->PRIVCFGR1)
+ + (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId));
+ if ((PeriphAttributes & GTZC_TZSC_PERIPH_PRIV) == GTZC_TZSC_PERIPH_PRIV)
+ {
+ SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
+ }
+ else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NPRIV) == GTZC_TZSC_PERIPH_NPRIV)
+ {
+ CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
+ }
+ else
+ {
+ /* do nothing */
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Get TZSC configuration on a single peripheral or on all peripherals.
+ * @param PeriphId Peripheral identifier.
+ * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
+ * Use GTZC_PERIPH_ALL to select all peripherals.
+ * @param PeriphAttributes Peripheral attribute pointer.
+ * This parameter can be a value of @ref GTZC_TZSC_PeriphAttributes.
+ * If PeriphId target a single peripheral, pointer on a single element.
+ * If all peripherals selected (GTZC_PERIPH_ALL), pointer to an array of
+ * GTZC_TZSC_PERIPH_NUMBER elements is to be provided.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId,
+ uint32_t *PeriphAttributes)
+{
+ uint32_t i;
+ uint32_t reg_value;
+ uint32_t register_address;
+
+ /* check entry parameters */
+ if ((PeriphAttributes == NULL)
+ || (HAL_GTZC_TZSC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZSC_PERIPH_NUMBER)
+ || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
+ && (HAL_GTZC_TZSC_GET_ARRAY_INDEX(PeriphId) != 0U)))
+ {
+ return HAL_ERROR;
+ }
+
+ if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
+ {
+ /* get secure configuration: read each register and deploy each bit value
+ * of corresponding index in the destination array
+ */
+ reg_value = READ_REG(GTZC_TZSC1->SECCFGR1);
+ for (i = 0U; i < 32U; i++)
+ {
+ if (((reg_value & (1UL << i)) >> i) != 0U)
+ {
+ PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC;
+ }
+ else
+ {
+ PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC;
+ }
+ }
+
+ reg_value = READ_REG(GTZC_TZSC1->SECCFGR2);
+ for (i = 32U; i < 64U; i++)
+ {
+ if (((reg_value & (1UL << (i - 32U))) >> (i - 32U)) != 0U)
+ {
+ PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC;
+ }
+ else
+ {
+ PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC;
+ }
+ }
+
+ reg_value = READ_REG(GTZC_TZSC1->SECCFGR3);
+ for (i = 64U; i < 96U; i++)
+ {
+ if (((reg_value & (1UL << (i - 64U))) >> (i - 64U)) != 0U)
+ {
+ PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC;
+ }
+ else
+ {
+ PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC;
+ }
+ }
+
+ reg_value = READ_REG(GTZC_TZSC2->SECCFGR1);
+ for (i = 96U; i < GTZC_TZSC_PERIPH_NUMBER; i++)
+ {
+ if (((reg_value & (1UL << (i - 96U))) >> (i - 96U)) != 0U)
+ {
+ PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC;
+ }
+ else
+ {
+ PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC;
+ }
+ }
+
+ /* get privilege configuration: read each register and deploy each bit value
+ * of corresponding index in the destination array
+ */
+ reg_value = READ_REG(GTZC_TZSC1->PRIVCFGR1);
+ for (i = 0U; i < 32U; i++)
+ {
+ if (((reg_value & (1UL << i)) >> i) != 0U)
+ {
+ PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV;
+ }
+ else
+ {
+ PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV;
+ }
+ }
+
+ reg_value = READ_REG(GTZC_TZSC1->PRIVCFGR2);
+ for (i = 32U; i < 64U; i++)
+ {
+ if (((reg_value & (1UL << (i - 32U))) >> (i - 32U)) != 0U)
+ {
+ PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV;
+ }
+ else
+ {
+ PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV;
+ }
+ }
+
+ reg_value = READ_REG(GTZC_TZSC1->PRIVCFGR3);
+ for (i = 64U; i < 96U; i++)
+ {
+ if (((reg_value & (1UL << (i - 64U))) >> (i - 64U)) != 0U)
+ {
+ PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV;
+ }
+ else
+ {
+ PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV;
+ }
+ }
+
+ reg_value = READ_REG(GTZC_TZSC2->PRIVCFGR1);
+ for (i = 96U; i < GTZC_TZSC_PERIPH_NUMBER; i++)
+ {
+ if (((reg_value & (1UL << (i - 96U))) >> (i - 96U)) != 0U)
+ {
+ PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV;
+ }
+ else
+ {
+ PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV;
+ }
+ }
+ }
+ else
+ {
+ /* common case where only one peripheral is configured */
+
+ /* secure configuration */
+ register_address = (uint32_t) &(HAL_GTZC_TZSC_GET_INSTANCE(PeriphId)->SECCFGR1)
+ + (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId));
+
+ if (((READ_BIT(*(__IO uint32_t *)register_address,
+ 1UL << GTZC_GET_PERIPH_POS(PeriphId))) >> GTZC_GET_PERIPH_POS(PeriphId))
+ != 0U)
+ {
+ *PeriphAttributes = GTZC_TZSC_PERIPH_SEC;
+ }
+ else
+ {
+ *PeriphAttributes = GTZC_TZSC_PERIPH_NSEC;
+ }
+
+ /* privilege configuration */
+ register_address = (uint32_t) &(HAL_GTZC_TZSC_GET_INSTANCE(PeriphId)->PRIVCFGR1)
+ + (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId));
+ if (((READ_BIT(*(__IO uint32_t *)register_address,
+ 1UL << GTZC_GET_PERIPH_POS(PeriphId))) >> GTZC_GET_PERIPH_POS(PeriphId))
+ != 0U)
+ {
+ *PeriphAttributes |= GTZC_TZSC_PERIPH_PRIV;
+ }
+ else
+ {
+ *PeriphAttributes |= GTZC_TZSC_PERIPH_NPRIV;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/** @defgroup GTZC_Exported_Functions_Group2 MPCWM Configuration functions
+ * @brief MPCWM Configuration functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### MPCWM Configuration functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to configure MPCWM
+ MPCWM is Memory Protection Controller WaterMark
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure a TZSC-MPCWM area.
+ * @param MemBaseAddress WM identifier.
+ * @param pMPCWM_Desc TZSC-MPCWM descriptor pointer.
+ * The structure description is available in @ref GTZC_Exported_Types.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(
+ uint32_t MemBaseAddress,
+ MPCWM_ConfigTypeDef *pMPCWM_Desc)
+{
+ uint32_t register_address;
+ uint32_t reg_value;
+ uint32_t size;
+ /* granularity value depends on selected memory */
+ uint32_t granularity = (MemBaseAddress == BKPSRAM_BASE) ? \
+ GTZC_TZSC_MPCWM_GRANULARITY_2 : GTZC_TZSC_MPCWM_GRANULARITY_1;
+
+ /* check entry parameters */
+ if ((pMPCWM_Desc->AreaId > GTZC_TZSC_MPCWM_ID2)
+ || (((MemBaseAddress == FMC_BANK3) || (MemBaseAddress == BKPSRAM_BASE))
+ && (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2))
+ || ((pMPCWM_Desc->Offset % granularity) != 0U)
+ || ((pMPCWM_Desc->Length % granularity) != 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* check descriptor content vs. memory capacity */
+ switch (MemBaseAddress)
+ {
+ case OCTOSPI1_BASE:
+ size = TZSC_MPCWM1_MEM_SIZE;
+ if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1)
+ {
+ register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM1AR);
+ }
+ else
+ {
+ /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2
+ * (Parameter already checked)
+ */
+ register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM1BR);
+ }
+ break;
+ case FMC_BANK1:
+ size = TZSC_MPCWM1_MEM_SIZE;
+ if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1)
+ {
+ register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM2AR);
+ }
+ else
+ {
+ /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2
+ * (Parameter already checked)
+ */
+ register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM2BR);
+ }
+ break;
+ case FMC_BANK3:
+ /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1
+ * (Parameter already checked)
+ */
+ size = TZSC_MPCWM3_MEM_SIZE;
+ register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM3AR);
+ break;
+ case BKPSRAM_BASE:
+ /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1
+ * (Parameter already checked)
+ */
+ size = TZSC_MPCWM4_MEM_SIZE;
+ register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM4AR);
+ break;
+ case OCTOSPI2_BASE:
+ size = TZSC_MPCWM5_MEM_SIZE;
+ if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1)
+ {
+ register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM5AR);
+ }
+ else
+ {
+ /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2
+ * (Parameter already checked)
+ */
+ register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM5BR);
+ }
+ break;
+ default:
+ return HAL_ERROR;
+ break;
+ }
+
+ if ((pMPCWM_Desc->Offset > size)
+ || ((pMPCWM_Desc->Offset
+ + pMPCWM_Desc->Length)
+ > size))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Write watermark start and length value */
+ reg_value = ((pMPCWM_Desc->Offset / granularity)
+ << GTZC_TZSC_MPCWMR_SUBZ_START_Pos) & GTZC_TZSC_MPCWMR_SUBZ_START_Msk;
+ reg_value |= ((pMPCWM_Desc->Length / granularity)
+ << GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) & GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk;
+ MODIFY_REG(*(__IO uint32_t *)register_address, GTZC_TZSC_MPCWMR_SUBZ_START_Msk | \
+ GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk, reg_value);
+
+ /* Write watermark configuration value */
+ reg_value = (pMPCWM_Desc->Attribute << GTZC_TZSC_MPCWM_CFGR_SEC_Pos) | \
+ pMPCWM_Desc->Lock | \
+ pMPCWM_Desc->AreaStatus;
+ MODIFY_REG(*(__IO uint32_t *)(register_address - 4U), (GTZC_TZSC_MPCWM_CFGR_PRIV | GTZC_TZSC_MPCWM_CFGR_SEC | \
+ GTZC_TZSC_MPCWM_CFGR_SRLOCK | GTZC_TZSC_MPCWM_CFGR_SREN), \
+ reg_value);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get a TZSC-MPCWM area configuration.
+ * @param MemBaseAddress WM identifier.
+ * @param pMPCWM_Desc pointer to a TZSC-MPCWM descriptor.
+ * The structure description is available in @ref GTZC_Exported_Types.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(
+ uint32_t MemBaseAddress,
+ MPCWM_ConfigTypeDef *pMPCWM_Desc)
+{
+ uint32_t register_address;
+ uint32_t reg_value;
+ uint32_t granularity = (MemBaseAddress == BKPSRAM_BASE) ? \
+ GTZC_TZSC_MPCWM_GRANULARITY_2 : GTZC_TZSC_MPCWM_GRANULARITY_1;
+
+ /* firstly take care of the first area, present on all MPCWM sub-blocks */
+ switch (MemBaseAddress)
+ {
+ case OCTOSPI1_BASE:
+ register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM1AR);
+ break;
+ case FMC_BANK1:
+ register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM2AR);
+ break;
+ case FMC_BANK3:
+ register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM3AR);
+ break;
+ case BKPSRAM_BASE:
+ register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM4AR);
+ break;
+ case OCTOSPI2_BASE:
+ register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM5AR);
+ break;
+ default:
+ return HAL_ERROR;
+ break;
+ }
+
+ /* read register and update the descriptor for first area*/
+ reg_value = READ_REG(*(__IO uint32_t *)register_address);
+ pMPCWM_Desc[0].AreaId = GTZC_TZSC_MPCWM_ID1;
+ pMPCWM_Desc[0].Offset = ((reg_value & GTZC_TZSC_MPCWMR_SUBZ_START_Msk)
+ >> GTZC_TZSC_MPCWMR_SUBZ_START_Pos) * granularity;
+ pMPCWM_Desc[0].Length = ((reg_value & GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk)
+ >> GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) * granularity;
+
+ /* read configuration register and update the descriptor for first area*/
+ reg_value = READ_REG(*(__IO uint32_t *)(register_address - 4U));
+ pMPCWM_Desc[0].Attribute = (reg_value & (GTZC_TZSC_MPCWM_CFGR_PRIV | \
+ GTZC_TZSC_MPCWM_CFGR_SEC)) >> GTZC_TZSC_MPCWM_CFGR_SEC_Pos;
+ pMPCWM_Desc[0].Lock = reg_value & GTZC_TZSC_MPCWM_CFGR_SRLOCK;
+ pMPCWM_Desc[0].AreaStatus = reg_value & GTZC_TZSC_MPCWM_CFGR_SREN;
+
+ if ((MemBaseAddress != FMC_BANK3) && (MemBaseAddress != BKPSRAM_BASE))
+ {
+ /* Here MemBaseAddress = OCTOSPI1_BASE, OCTOSPI2_BASE
+ * or FMC_BANK1 (already checked)
+ * Now take care of the second area, present on these sub-blocks
+ */
+ switch (MemBaseAddress)
+ {
+ case OCTOSPI1_BASE:
+ register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM1BR);
+ break;
+ case FMC_BANK1:
+ register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM2BR);
+ break;
+ case OCTOSPI2_BASE:
+ register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM5BR);
+ break;
+ default:
+ return HAL_ERROR;
+ break;
+ }
+
+ /* read register and update the descriptor for second area*/
+ reg_value = READ_REG(*(__IO uint32_t *)register_address);
+ pMPCWM_Desc[1].AreaId = GTZC_TZSC_MPCWM_ID2;
+ pMPCWM_Desc[1].Offset = ((reg_value & GTZC_TZSC_MPCWMR_SUBZ_START_Msk)
+ >> GTZC_TZSC_MPCWMR_SUBZ_START_Pos) * granularity;
+ pMPCWM_Desc[1].Length = ((reg_value & GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk)
+ >> GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) * granularity;
+
+ /* read configuration register and update the descriptor for second area*/
+ reg_value = READ_REG(*(__IO uint32_t *)(register_address - 4U));
+ pMPCWM_Desc[1].Attribute = reg_value & (GTZC_TZSC_MPCWM_CFGR_PRIV | \
+ GTZC_TZSC_MPCWM_CFGR_SEC);
+ pMPCWM_Desc[1].Lock = reg_value & GTZC_TZSC_MPCWM_CFGR_SRLOCK;
+ pMPCWM_Desc[1].AreaStatus = reg_value & GTZC_TZSC_MPCWM_CFGR_SREN;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup GTZC_Exported_Functions_Group3 TZSC Lock functions
+ * @brief TZSC Lock functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### TZSC Lock functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to manage the TZSC (TrustZone
+ Security Controller) lock. It includes lock enable, and current value read.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Lock TZSC configuration.
+ * @note This function locks the configuration of TZSC_SECCFGRx and TZSC_PRIVCFGRx
+ * registers until next reset
+ * @param TZSC_Instance TZSC sub-block instance.
+ */
+void HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSC_Instance)
+{
+ SET_BIT(TZSC_Instance->CR, GTZC_TZSC_CR_LCK_Msk);
+}
+
+/**
+ * @brief Get TZSC configuration lock state.
+ * @param TZSC_Instance TZSC sub-block instance.
+ * @retval Lock State (GTZC_TZSC_LOCK_OFF or GTZC_TZSC_LOCK_ON)
+ */
+uint32_t HAL_GTZC_TZSC_GetLock(GTZC_TZSC_TypeDef *TZSC_Instance)
+{
+ return READ_BIT(TZSC_Instance->CR, GTZC_TZSC_CR_LCK_Msk);
+}
+
+/**
+ * @}
+ */
+#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/** @defgroup GTZC_Exported_Functions_Group4 MPCBB Configuration functions
+ * @brief MPCBB Configuration functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### MPCBB Configuration functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to configure MPCBB
+ MPCBB is Memory Protection Controller Block Base
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set a complete MPCBB configuration on the SRAM passed as parameter.
+ * @param MemBaseAddress MPCBB identifier.
+ * @param pMPCBB_desc pointer to MPCBB descriptor.
+ * The structure description is available in @ref GTZC_Exported_Types.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress,
+ MPCBB_ConfigTypeDef *pMPCBB_desc)
+{
+ GTZC_MPCBB_TypeDef *mpcbb_ptr;
+ uint32_t mem_size;
+ uint32_t size_in_superblocks;
+ uint32_t i;
+
+ /* check entry parameters */
+ if ((!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
+ && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
+ && !(IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
+ && !(IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress)))
+ || ((pMPCBB_desc->SecureRWIllegalMode
+ != GTZC_MPCBB_SRWILADIS_ENABLE)
+ && (pMPCBB_desc->SecureRWIllegalMode
+ != GTZC_MPCBB_SRWILADIS_DISABLE))
+ || ((pMPCBB_desc->InvertSecureState
+ != GTZC_MPCBB_INVSECSTATE_NOT_INVERTED)
+ && (pMPCBB_desc->InvertSecureState
+ != GTZC_MPCBB_INVSECSTATE_INVERTED)))
+ {
+ return HAL_ERROR;
+ }
+
+ if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
+ {
+ mpcbb_ptr = GTZC_MPCBB1;
+ mem_size = GTZC_MEM_SIZE(SRAM1);
+ }
+ else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
+ {
+ mpcbb_ptr = GTZC_MPCBB2;
+ mem_size = GTZC_MEM_SIZE(SRAM2);
+ }
+ else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
+ {
+ mpcbb_ptr = GTZC_MPCBB3;
+ mem_size = GTZC_MEM_SIZE(SRAM3);
+ }
+ else
+ {
+ /* Here MemBaseAddress is inside SRAM4 (parameter already checked) */
+ mpcbb_ptr = GTZC_MPCBB4;
+ mem_size = GTZC_MEM_SIZE(SRAM4);
+ }
+
+ /* translate mem_size in number of super-blocks */
+ size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE);
+
+ /* write PRIVCFGR register information */
+ for (i = 0U; i < size_in_superblocks; i++)
+ {
+ WRITE_REG(mpcbb_ptr->PRIVCFGR[i],
+ pMPCBB_desc->AttributeConfig.MPCBB_PrivConfig_array[i]);
+ }
+
+#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ uint32_t size_mask;
+ uint32_t reg_value;
+
+ /* write SECCFGR register information */
+ for (i = 0U; i < size_in_superblocks; i++)
+ {
+ WRITE_REG(mpcbb_ptr->SECCFGR[i],
+ pMPCBB_desc->AttributeConfig.MPCBB_SecConfig_array[i]);
+ }
+
+#if defined (GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk)
+ if (size_in_superblocks >= 32U)
+ {
+ size_mask = 0xFFFFFFFFU;
+ MODIFY_REG(mpcbb_ptr->CFGLOCKR2, 0x000FFFFFUL, pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[1]);
+ }
+ else
+#endif /* GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk */
+ {
+ size_mask = (1UL << size_in_superblocks) - 1U;
+ }
+ /* limitation: code not portable with memory > 512K */
+ MODIFY_REG(mpcbb_ptr->CFGLOCKR1, size_mask, pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0]);
+
+ /* write InvertSecureState and SecureRWIllegalMode properties */
+ reg_value = pMPCBB_desc->InvertSecureState;
+ reg_value |= pMPCBB_desc->SecureRWIllegalMode;
+
+ /* write configuration and lock register information */
+ MODIFY_REG(mpcbb_ptr->CR,
+ GTZC_MPCBB_CR_INVSECSTATE_Msk | GTZC_MPCBB_CR_SRWILADIS_Msk, reg_value);
+#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get a complete MPCBB configuration on the SRAM passed as parameter.
+ * @param MemBaseAddress MPCBB identifier.
+ * @param pMPCBB_desc pointer to a MPCBB descriptor.
+ * The structure description is available in @ref GTZC_Exported_Types.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress,
+ MPCBB_ConfigTypeDef *pMPCBB_desc)
+{
+ GTZC_MPCBB_TypeDef *mpcbb_ptr;
+ uint32_t mem_size;
+ uint32_t size_in_superblocks;
+ uint32_t i;
+
+ /* check entry parameters */
+ if (!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
+ && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
+ && !(IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
+ && !(IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress)))
+ {
+ return HAL_ERROR;
+ }
+
+ /* read InvertSecureState and SecureRWIllegalMode properties */
+ /* assume their Position/Mask is identical for all sub-blocks */
+ if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
+ {
+ mpcbb_ptr = GTZC_MPCBB1;
+ mem_size = GTZC_MEM_SIZE(SRAM1);
+ }
+ else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
+ {
+ mpcbb_ptr = GTZC_MPCBB2;
+ mem_size = GTZC_MEM_SIZE(SRAM2);
+ }
+ else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
+ {
+ mpcbb_ptr = GTZC_MPCBB3;
+ mem_size = GTZC_MEM_SIZE(SRAM3);
+ }
+ else
+ {
+ mpcbb_ptr = GTZC_MPCBB4;
+ mem_size = GTZC_MEM_SIZE(SRAM4);
+ }
+
+ /* translate mem_size in number of super-blocks */
+ size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE);
+
+#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ uint32_t reg_value;
+ uint32_t size_mask;
+
+ /* read configuration and lock register information */
+ reg_value = READ_REG(mpcbb_ptr->CR);
+ pMPCBB_desc->InvertSecureState = (reg_value & GTZC_MPCBB_CR_INVSECSTATE_Msk);
+ pMPCBB_desc->SecureRWIllegalMode = (reg_value & GTZC_MPCBB_CR_SRWILADIS_Msk);
+ if (size_in_superblocks == 32U)
+ {
+ size_mask = 0xFFFFFFFFU;
+ }
+ else
+ {
+ size_mask = (1UL << size_in_superblocks) - 1U;
+ }
+ /* limitation: code not portable with memory > 512K */
+ pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0] = READ_REG(mpcbb_ptr->CFGLOCKR1)
+ & size_mask;
+#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+ /* read SECCFGR / PRIVCFGR registers information */
+ for (i = 0U; i < size_in_superblocks; i++)
+ {
+ pMPCBB_desc->AttributeConfig.MPCBB_SecConfig_array[i] = mpcbb_ptr->SECCFGR[i];
+ pMPCBB_desc->AttributeConfig.MPCBB_PrivConfig_array[i] = mpcbb_ptr->PRIVCFGR[i];
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set a MPCBB attribute configuration on the SRAM passed as parameter
+ * for a number of blocks.
+ * @param MemAddress MPCBB identifier, and start block to configure
+ * (must be 512 Bytes aligned).
+ * @param NbBlocks Number of blocks to configure
+ * (Block size is 512 Bytes).
+ * @param pMemAttributes pointer to an array (containing "NbBlocks" elements),
+ * with each element must be GTZC_MCPBB_BLOCK_NSEC or GTZC_MCPBB_BLOCK_SEC,
+ * and GTZC_MCPBB_BLOCK_NPRIV or GTZC_MCPBB_BLOCK_PRIV.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress,
+ uint32_t NbBlocks,
+ uint32_t *pMemAttributes)
+{
+ GTZC_MPCBB_TypeDef *mpcbb_ptr;
+ uint32_t base_address;
+ uint32_t end_address;
+ uint32_t block_start;
+ uint32_t offset_reg_start;
+ uint32_t offset_bit_start;
+ uint32_t i;
+ uint32_t do_attr_change;
+
+ /* firstly check that MemAddress is well 512 Bytes aligned */
+ if ((MemAddress % GTZC_MPCBB_BLOCK_SIZE) != 0U)
+ {
+ return HAL_ERROR;
+ }
+
+ /* check entry parameters and deduce physical base address */
+ end_address = MemAddress + (NbBlocks * GTZC_MPCBB_BLOCK_SIZE) - 1U;
+ if (((IS_ADDRESS_IN_NS(SRAM1, MemAddress))
+ && (IS_ADDRESS_IN_NS(SRAM1, end_address))) != 0U)
+ {
+ mpcbb_ptr = GTZC_MPCBB1;
+ base_address = SRAM1_BASE_NS;
+ }
+ else if (((IS_ADDRESS_IN_S(SRAM1, MemAddress))
+ && (IS_ADDRESS_IN_S(SRAM1, end_address))) != 0U)
+ {
+ mpcbb_ptr = GTZC_MPCBB1;
+ base_address = SRAM1_BASE_S;
+ }
+ else if (((IS_ADDRESS_IN_NS(SRAM2, MemAddress))
+ && (IS_ADDRESS_IN_NS(SRAM2, end_address))) != 0U)
+ {
+ mpcbb_ptr = GTZC_MPCBB2;
+ base_address = SRAM2_BASE_NS;
+ }
+ else if (((IS_ADDRESS_IN_S(SRAM2, MemAddress))
+ && (IS_ADDRESS_IN_S(SRAM2, end_address))) != 0U)
+ {
+ mpcbb_ptr = GTZC_MPCBB2;
+ base_address = SRAM2_BASE_S;
+ }
+ else if (((IS_ADDRESS_IN_NS(SRAM3, MemAddress))
+ && (IS_ADDRESS_IN_NS(SRAM3, end_address))) != 0U)
+ {
+ mpcbb_ptr = GTZC_MPCBB3;
+ base_address = SRAM3_BASE_NS;
+ }
+ else if (((IS_ADDRESS_IN_S(SRAM3, MemAddress))
+ && (IS_ADDRESS_IN_S(SRAM3, end_address))) != 0U)
+ {
+ mpcbb_ptr = GTZC_MPCBB3;
+ base_address = SRAM3_BASE_S;
+ }
+ else if (((IS_ADDRESS_IN_NS(SRAM4, MemAddress))
+ && (IS_ADDRESS_IN_NS(SRAM4, end_address))) != 0U)
+ {
+ mpcbb_ptr = GTZC_MPCBB4;
+ base_address = SRAM4_BASE_NS;
+ }
+ else if (((IS_ADDRESS_IN_S(SRAM4, MemAddress))
+ && (IS_ADDRESS_IN_S(SRAM4, end_address))) != 0U)
+ {
+ mpcbb_ptr = GTZC_MPCBB4;
+ base_address = SRAM4_BASE_S;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ /* get start coordinates of the configuration */
+ block_start = (MemAddress - base_address) / GTZC_MPCBB_BLOCK_SIZE;
+ offset_reg_start = block_start / 32U;
+ offset_bit_start = block_start % 32U;
+
+ for (i = 0U; i < NbBlocks; i++)
+ {
+ /* Indicate change done for protection attributes */
+ do_attr_change = 0U;
+
+#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ /* secure configuration */
+ if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_SEC) == GTZC_MCPBB_BLOCK_SEC)
+ {
+ SET_BIT(mpcbb_ptr->SECCFGR[offset_reg_start],
+ 1UL << (offset_bit_start % 32U));
+ do_attr_change = 1U;
+ }
+ else if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_NSEC) == GTZC_MCPBB_BLOCK_NSEC)
+ {
+ CLEAR_BIT(mpcbb_ptr->SECCFGR[offset_reg_start],
+ 1UL << (offset_bit_start % 32U));
+ do_attr_change = 1U;
+ }
+ else
+ {
+ /* nothing to do */
+ }
+#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+ /* privilege configuration */
+ if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_PRIV) == GTZC_MCPBB_BLOCK_PRIV)
+ {
+ SET_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start],
+ 1UL << (offset_bit_start % 32U));
+ }
+ else if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_NPRIV) == GTZC_MCPBB_BLOCK_NPRIV)
+ {
+ CLEAR_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start],
+ 1UL << (offset_bit_start % 32U));
+ }
+ else
+ {
+ /* if no change is done for security and privilege attributes: break the loop */
+ if (do_attr_change == 0U)
+ {
+ break;
+ }
+ }
+
+ offset_bit_start++;
+ if (offset_bit_start == 32U)
+ {
+ offset_bit_start = 0U;
+ offset_reg_start++;
+ }
+ }
+
+ /* an unexpected value in pMemAttributes array leads to error status */
+ if (i != NbBlocks)
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get a MPCBB attribute configuration on the SRAM passed as parameter
+ * for a number of blocks.
+ * @param MemAddress MPCBB identifier, and start block to get configuration
+ * (must be 512 Bytes aligned).
+ * @param NbBlocks Number of blocks to get configuration.
+ * @param pMemAttributes pointer to an array (containing "NbBlocks" elements),
+ * with each element will be GTZC_MCPBB_BLOCK_NSEC or GTZC_MCPBB_BLOCK_SEC,
+ * and GTZC_MCPBB_BLOCK_NPRIV or GTZC_MCPBB_BLOCK_PRIV.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress,
+ uint32_t NbBlocks,
+ uint32_t *pMemAttributes)
+{
+ GTZC_MPCBB_TypeDef *mpcbb_ptr;
+ uint32_t base_address;
+ uint32_t end_address;
+ uint32_t block_start;
+ uint32_t offset_reg_start;
+ uint32_t offset_bit_start;
+ uint32_t i;
+
+ /* firstly check that MemAddress is well 512 Bytes aligned */
+ if ((MemAddress % GTZC_MPCBB_BLOCK_SIZE) != 0U)
+ {
+ return HAL_ERROR;
+ }
+
+ /* check entry parameters and deduce physical base address */
+ end_address = MemAddress + (NbBlocks * GTZC_MPCBB_BLOCK_SIZE) - 1U;
+ if ((IS_ADDRESS_IN_NS(SRAM1, MemAddress))
+ && (IS_ADDRESS_IN_NS(SRAM1, end_address)))
+ {
+ mpcbb_ptr = GTZC_MPCBB1_NS;
+ base_address = SRAM1_BASE_NS;
+ }
+ else if ((IS_ADDRESS_IN_S(SRAM1, MemAddress))
+ && (IS_ADDRESS_IN_S(SRAM1, end_address)))
+ {
+ mpcbb_ptr = GTZC_MPCBB1_S;
+ base_address = SRAM1_BASE_S;
+ }
+ else if ((IS_ADDRESS_IN_NS(SRAM2, MemAddress))
+ && (IS_ADDRESS_IN_NS(SRAM2, end_address)))
+ {
+ mpcbb_ptr = GTZC_MPCBB2_NS;
+ base_address = SRAM2_BASE_NS;
+ }
+ else if ((IS_ADDRESS_IN_S(SRAM2, MemAddress))
+ && (IS_ADDRESS_IN_S(SRAM2, end_address)))
+ {
+ mpcbb_ptr = GTZC_MPCBB2_S;
+ base_address = SRAM2_BASE_S;
+ }
+ else if ((IS_ADDRESS_IN_NS(SRAM3, MemAddress))
+ && (IS_ADDRESS_IN_NS(SRAM3, end_address)))
+ {
+ mpcbb_ptr = GTZC_MPCBB3_NS;
+ base_address = SRAM3_BASE_NS;
+ }
+ else if ((IS_ADDRESS_IN_S(SRAM3, MemAddress))
+ && (IS_ADDRESS_IN_S(SRAM3, end_address)))
+ {
+ mpcbb_ptr = GTZC_MPCBB3_S;
+ base_address = SRAM3_BASE_S;
+ }
+ else if ((IS_ADDRESS_IN_NS(SRAM4, MemAddress))
+ && (IS_ADDRESS_IN_NS(SRAM4, end_address)))
+ {
+ mpcbb_ptr = GTZC_MPCBB4_NS;
+ base_address = SRAM4_BASE_NS;
+ }
+ else if ((IS_ADDRESS_IN_S(SRAM4, MemAddress))
+ && (IS_ADDRESS_IN_S(SRAM4, end_address)))
+ {
+ mpcbb_ptr = GTZC_MPCBB4_S;
+ base_address = SRAM4_BASE_S;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ /* get start coordinates of the configuration */
+ block_start = (MemAddress - base_address) / GTZC_MPCBB_BLOCK_SIZE;
+ offset_reg_start = block_start / 32U;
+ offset_bit_start = block_start % 32U;
+
+ for (i = 0U; i < NbBlocks; i++)
+ {
+ pMemAttributes[i] = (READ_BIT(mpcbb_ptr->SECCFGR[offset_reg_start],
+ 1UL << (offset_bit_start % 32U))
+ >> (offset_bit_start % 32U)) | GTZC_ATTR_SEC_MASK;
+ pMemAttributes[i] |= (READ_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start],
+ 1UL << (offset_bit_start % 32U))
+ >> (offset_bit_start % 32U)) | GTZC_ATTR_PRIV_MASK;
+
+ offset_bit_start++;
+ if (offset_bit_start == 32U)
+ {
+ offset_bit_start = 0U;
+ offset_reg_start++;
+ }
+ }
+
+ return HAL_OK;
+}
+
+#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ * @brief Lock MPCBB super-blocks on the SRAM passed as parameter.
+ * @param MemAddress MPCBB start-address of super-block to configure
+ * (must be 16KBytes aligned).
+ * @param NbSuperBlocks Number of super-blocks to configure.
+ * @param pLockAttributes pointer to an array (containing "NbSuperBlocks" elements),
+ * with for each element:
+ * value 0 super-block is unlocked, value 1 super-block is locked
+ * (corresponds to GTZC_MCPBB_SUPERBLOCK_UNLOCKED and
+ * GTZC_MCPBB_SUPERBLOCK_LOCKED values).
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress,
+ uint32_t NbSuperBlocks,
+ uint32_t *pLockAttributes)
+{
+ __IO uint32_t *reg_mpcbb;
+ uint32_t base_address;
+ uint32_t superblock_start;
+ uint32_t offset_bit_start;
+ uint32_t i;
+
+ /* firstly check that MemAddress is well 16KBytes aligned */
+ if ((MemAddress % GTZC_MPCBB_SUPERBLOCK_SIZE) != 0U)
+ {
+ return HAL_ERROR;
+ }
+
+ /* check entry parameters */
+ if ((IS_ADDRESS_IN(SRAM1, MemAddress))
+ && (IS_ADDRESS_IN(SRAM1, (MemAddress
+ + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
+ - 1U))))
+ {
+ base_address = GTZC_BASE_ADDRESS(SRAM1);
+ /* limitation: code not portable with memory > 512K */
+ reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB1_S->CFGLOCKR1;
+ }
+ else if ((IS_ADDRESS_IN(SRAM2, MemAddress))
+ && (IS_ADDRESS_IN(SRAM2, (MemAddress
+ + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
+ - 1U))))
+ {
+ base_address = GTZC_BASE_ADDRESS(SRAM2);
+ /* limitation: code not portable with memory > 512K */
+ reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB2_S->CFGLOCKR1;
+ }
+ else if ((IS_ADDRESS_IN(SRAM3, MemAddress))
+ && (IS_ADDRESS_IN(SRAM3, (MemAddress
+ + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
+ - 1U))))
+ {
+ base_address = GTZC_BASE_ADDRESS(SRAM3);
+ /* limitation: code not portable with memory > 512K */
+ reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB3_S->CFGLOCKR1;
+ }
+
+ else if ((IS_ADDRESS_IN(SRAM4, MemAddress))
+ && (IS_ADDRESS_IN(SRAM4, (MemAddress
+ + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
+ - 1U))))
+ {
+ base_address = GTZC_BASE_ADDRESS(SRAM4);
+ /* limitation: code not portable with memory > 512K */
+ reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB4_S->CFGLOCKR1;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ /* get start coordinates of the configuration */
+ superblock_start = (MemAddress - base_address) / GTZC_MPCBB_SUPERBLOCK_SIZE;
+ offset_bit_start = superblock_start % 32U;
+
+ for (i = 0U; i < NbSuperBlocks; i++)
+ {
+ if (pLockAttributes[i] == GTZC_MCPBB_SUPERBLOCK_LOCKED)
+ {
+ SET_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U));
+ }
+ else if (pLockAttributes[i] == GTZC_MCPBB_SUPERBLOCK_UNLOCKED)
+ {
+ CLEAR_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U));
+ }
+ else
+ {
+ break;
+ }
+
+ offset_bit_start++;
+ }
+
+ /* an unexpected value in pLockAttributes array leads to an error status */
+ if (i != NbSuperBlocks)
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get MPCBB super-blocks lock configuration on the SRAM passed as parameter.
+ * @param MemAddress MPCBB start-address of super-block to get configuration
+ * (must be 16KBytes aligned).
+ * @param NbSuperBlocks Number of super-blocks to get configuration.
+ * @param pLockAttributes pointer to an array (containing "NbSuperBlocks" elements),
+ * with for each element:
+ * value 0 super-block is unlocked, value 1 super-block is locked
+ * (corresponds to GTZC_MCPBB_SUPERBLOCK_UNLOCKED and
+ * GTZC_MCPBB_SUPERBLOCK_LOCKED values).
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress,
+ uint32_t NbSuperBlocks,
+ uint32_t *pLockAttributes)
+{
+ uint32_t reg_mpcbb;
+ uint32_t base_address;
+ uint32_t superblock_start;
+ uint32_t offset_bit_start;
+ uint32_t i;
+
+ /* firstly check that MemAddress is well 16KBytes aligned */
+ if ((MemAddress % GTZC_MPCBB_SUPERBLOCK_SIZE) != 0U)
+ {
+ return HAL_ERROR;
+ }
+
+ /* check entry parameters */
+ if ((IS_ADDRESS_IN(SRAM1, MemAddress))
+ && (IS_ADDRESS_IN(SRAM1, (MemAddress
+ + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
+ - 1U))))
+ {
+ base_address = GTZC_BASE_ADDRESS(SRAM1);
+ /* limitation: code not portable with memory > 512K */
+ reg_mpcbb = GTZC_MPCBB1_S->CFGLOCKR1;
+ }
+ else if ((IS_ADDRESS_IN(SRAM2, MemAddress))
+ && (IS_ADDRESS_IN(SRAM2, (MemAddress
+ + (NbSuperBlocks
+ * GTZC_MPCBB_SUPERBLOCK_SIZE)
+ - 1U))))
+ {
+ base_address = GTZC_BASE_ADDRESS(SRAM2);
+ /* limitation: code not portable with memory > 512K */
+ reg_mpcbb = GTZC_MPCBB2_S->CFGLOCKR1;
+ }
+ else if ((IS_ADDRESS_IN(SRAM3, MemAddress))
+ && (IS_ADDRESS_IN(SRAM3, (MemAddress
+ + (NbSuperBlocks
+ * GTZC_MPCBB_SUPERBLOCK_SIZE)
+ - 1U))))
+ {
+ base_address = GTZC_BASE_ADDRESS(SRAM3);
+ /* limitation: code not portable with memory > 512K */
+ reg_mpcbb = GTZC_MPCBB3_S->CFGLOCKR1;
+ }
+ else if ((IS_ADDRESS_IN(SRAM4, MemAddress))
+ && (IS_ADDRESS_IN(SRAM4, (MemAddress
+ + (NbSuperBlocks
+ * GTZC_MPCBB_SUPERBLOCK_SIZE)
+ - 1U))))
+ {
+ base_address = GTZC_BASE_ADDRESS(SRAM4);
+ /* limitation: code not portable with memory > 512K */
+ reg_mpcbb = GTZC_MPCBB4_S->CFGLOCKR1;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ /* get start coordinates of the configuration */
+ superblock_start = (MemAddress - base_address) / GTZC_MPCBB_SUPERBLOCK_SIZE;
+ offset_bit_start = superblock_start % 32U;
+
+ for (i = 0U; i < NbSuperBlocks; i++)
+ {
+ pLockAttributes[i] = (reg_mpcbb & (1UL << (offset_bit_start % 32U)))
+ >> (offset_bit_start % 32U);
+ offset_bit_start++;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Lock a MPCBB configuration on the SRAM base address passed as parameter.
+ * @note This functions locks the control register of the MPCBB until next reset.
+ * @param MemBaseAddress MPCBB identifier.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress)
+{
+ /* check entry parameters */
+ if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
+ {
+ SET_BIT(GTZC_MPCBB1_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
+ }
+ else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
+ {
+ SET_BIT(GTZC_MPCBB2_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
+ }
+ else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
+ {
+ SET_BIT(GTZC_MPCBB3_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
+ }
+ else if (IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress))
+ {
+ SET_BIT(GTZC_MPCBB4_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get MPCBB configuration lock state on the SRAM base address passed as parameter.
+ * @param MemBaseAddress MPCBB identifier.
+ * @param pLockState pointer to Lock State (GTZC_MCPBB_LOCK_OFF or GTZC_MCPBB_LOCK_ON).
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress,
+ uint32_t *pLockState)
+{
+ /* check entry parameters */
+ if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
+ {
+ *pLockState = READ_BIT(GTZC_MPCBB1_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
+ }
+ else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
+ {
+ *pLockState = READ_BIT(GTZC_MPCBB2_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
+ }
+ else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
+ {
+ *pLockState = READ_BIT(GTZC_MPCBB3_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
+ }
+ else if (IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress))
+ {
+ *pLockState = READ_BIT(GTZC_MPCBB4_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup GTZC_Exported_Functions_Group5 TZIC Configuration and Control functions
+ * @brief TZIC Configuration and Control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### TZIC Configuration and Control functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to configure and control TZIC
+ TZIC is Trust Zone Interrupt Controller
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Disable the interrupt associated to a single TZIC peripheral or on all peripherals.
+ * @param PeriphId Peripheral identifier.
+ * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
+ * Use GTZC_PERIPH_ALL to select all peripherals.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId)
+{
+ uint32_t register_address;
+
+ /* check entry parameters */
+ if ((HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
+ || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
+ && (HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) != 0U)))
+ {
+ return HAL_ERROR;
+ }
+
+ if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
+ {
+ /* same configuration is applied to all peripherals */
+ WRITE_REG(GTZC_TZIC1->IER1, 0U);
+ WRITE_REG(GTZC_TZIC1->IER2, 0U);
+ WRITE_REG(GTZC_TZIC1->IER3, 0U);
+ WRITE_REG(GTZC_TZIC1->IER4, 0U);
+ WRITE_REG(GTZC_TZIC2->IER1, 0U);
+ WRITE_REG(GTZC_TZIC2->IER2, 0U);
+ }
+ else
+ {
+ /* common case where only one peripheral is configured */
+ register_address = (uint32_t) &(HAL_GTZC_TZIC_GET_INSTANCE(PeriphId)->IER1)
+ + (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId));
+ CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable the interrupt associated to a single TZIC peripheral or on all peripherals.
+ * @param PeriphId Peripheral identifier.
+ * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
+ * Use GTZC_PERIPH_ALL to select all peripherals.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId)
+{
+ uint32_t register_address;
+
+ /* check entry parameters */
+ if ((HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
+ || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
+ && (HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) != 0U)))
+ {
+ return HAL_ERROR;
+ }
+
+ if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
+ {
+ /* same configuration is applied to all peripherals */
+ WRITE_REG(GTZC_TZIC1->IER1, TZIC1_IER1_ALL);
+ WRITE_REG(GTZC_TZIC1->IER2, TZIC1_IER2_ALL);
+ WRITE_REG(GTZC_TZIC1->IER3, TZIC1_IER3_ALL);
+ WRITE_REG(GTZC_TZIC1->IER4, TZIC1_IER4_ALL);
+ WRITE_REG(GTZC_TZIC2->IER1, TZIC2_IER1_ALL);
+ WRITE_REG(GTZC_TZIC2->IER2, TZIC2_IER2_ALL);
+ }
+ else
+ {
+ /* common case where only one peripheral is configured */
+ register_address = (uint32_t) &(HAL_GTZC_TZIC_GET_INSTANCE(PeriphId)->IER1)
+ + (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId));
+ SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get TZIC flag on a single TZIC peripheral or on all peripherals.
+ * @param PeriphId Peripheral identifier.
+ * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
+ * Use GTZC_PERIPH_ALL to select all peripherals.
+ * @param pFlag Pointer to the flags.
+ * If PeriphId target a single peripheral, pointer on a single element.
+ * If all peripherals selected (GTZC_PERIPH_ALL), pointer to an array
+ * of GTZC_TZIC_PERIPH_NUMBER elements.
+ * Element content is either GTZC_TZIC_NO_ILA_EVENT
+ * or GTZC_TZSC_ILA_EVENT_PENDING.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *pFlag)
+{
+ uint32_t i;
+ uint32_t reg_value;
+ uint32_t register_address;
+
+ /* check entry parameters */
+ if ((HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
+ || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
+ && (HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) != 0U)))
+ {
+ return HAL_ERROR;
+ }
+
+ if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
+ {
+ /* special case where it is applied to all peripherals */
+ reg_value = READ_REG(GTZC_TZIC1->SR1);
+ for (i = 0U; i < 32U; i++)
+ {
+ pFlag[i] = (reg_value & (1UL << i)) >> i;
+ }
+
+ reg_value = READ_REG(GTZC_TZIC1->SR2);
+ for (i = 32U; i < 64U; i++)
+ {
+ pFlag[i] = (reg_value & (1UL << (i - 32U))) >> (i - 32U);
+ }
+
+ reg_value = READ_REG(GTZC_TZIC1->SR3);
+ for (i = 64; i < 96U; i++)
+ {
+ pFlag[i] = (reg_value & (1UL << (i - 64U))) >> (i - 64U);
+ }
+
+ reg_value = READ_REG(GTZC_TZIC1->SR4);
+ for (i = 96U; i < 128U; i++)
+ {
+ pFlag[i] = (reg_value & (1UL << (i - 96U))) >> (i - 96U);
+ }
+
+ reg_value = READ_REG(GTZC_TZIC2->SR1);
+ for (i = 128U; i < 160U; i++)
+ {
+ pFlag[i] = (reg_value & (1UL << (i - 128U))) >> (i - 128U);
+ }
+
+ reg_value = READ_REG(GTZC_TZIC2->SR2);
+ for (i = 160U; i < GTZC_TZIC_PERIPH_NUMBER; i++)
+ {
+ pFlag[i] = (reg_value & (1UL << (i - 160U))) >> (i - 160U);
+ }
+ }
+ else
+ {
+ /* common case where only one peripheral is concerned */
+ register_address = (uint32_t) &(HAL_GTZC_TZIC_GET_INSTANCE(PeriphId)->SR1)
+ + (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId));
+ *pFlag = READ_BIT(*(__IO uint32_t *)register_address,
+ 1UL << GTZC_GET_PERIPH_POS(PeriphId)) >> GTZC_GET_PERIPH_POS(PeriphId);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Clear TZIC flag on a single TZIC peripheral or on all peripherals.
+ * @param PeriphId Peripheral identifier.
+ * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
+ * Use GTZC_PERIPH_ALL to select all peripherals.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId)
+{
+ uint32_t register_address;
+
+ /* check entry parameters */
+ if ((HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
+ || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
+ && (HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) != 0U)))
+ {
+ return HAL_ERROR;
+ }
+
+ if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
+ {
+ /* same configuration is applied to all peripherals */
+ WRITE_REG(GTZC_TZIC1->FCR1, TZIC1_FCR1_ALL);
+ WRITE_REG(GTZC_TZIC1->FCR2, TZIC1_FCR2_ALL);
+ WRITE_REG(GTZC_TZIC1->FCR3, TZIC1_FCR3_ALL);
+ WRITE_REG(GTZC_TZIC1->FCR4, TZIC1_FCR4_ALL);
+ WRITE_REG(GTZC_TZIC2->FCR1, TZIC2_FCR1_ALL);
+ WRITE_REG(GTZC_TZIC2->FCR2, TZIC2_FCR2_ALL);
+ }
+ else
+ {
+ /* common case where only one peripheral is configured */
+ register_address = (uint32_t) &(HAL_GTZC_TZIC_GET_INSTANCE(PeriphId)->FCR1)
+ + (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId));
+ SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup GTZC_Exported_Functions_Group6 IRQ related functions
+ * @brief IRQ related functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### TZIC IRQ Handler and Callback functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to treat ISR and provide user callback
+ @endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function handles GTZC TZIC interrupt request.
+ * @retval None.
+ */
+void HAL_GTZC_IRQHandler(void)
+{
+ uint32_t position;
+ uint32_t flag;
+ uint32_t ier_itsources;
+ uint32_t sr_flags;
+
+ /*********************************************************************/
+ /****************************** TZIC1 ******************************/
+ /*********************************************************************/
+
+ /* Get current IT Flags and IT sources value on 1st register of TZIC1 */
+ ier_itsources = READ_REG(GTZC_TZIC1_S->IER1);
+ sr_flags = READ_REG(GTZC_TZIC1_S->SR1);
+
+ /* Get Mask interrupt and then clear them */
+ flag = ier_itsources & sr_flags;
+ if (flag != 0U)
+ {
+ WRITE_REG(GTZC_TZIC1_S->FCR1, flag);
+
+ /* Loop on flag to check, which ones have been raised */
+ position = 0U;
+ while ((flag >> position) != 0U)
+ {
+ if ((flag & (1UL << position)) != 0U)
+ {
+ HAL_GTZC_TZIC_Callback(GTZC1_PERIPH_REG1 | position);
+ }
+
+ /* Position bit to be updated */
+ position++;
+ }
+ }
+
+ /* Get current IT Flags and IT sources value on 2nd register of TZIC1 */
+ ier_itsources = READ_REG(GTZC_TZIC1_S->IER2);
+ sr_flags = READ_REG(GTZC_TZIC1_S->SR2);
+
+ /* Get Mask interrupt and then clear them */
+ flag = ier_itsources & sr_flags;
+ if (flag != 0U)
+ {
+ WRITE_REG(GTZC_TZIC1_S->FCR2, flag);
+
+ /* Loop on flag to check, which ones have been raised */
+ position = 0U;
+ while ((flag >> position) != 0U)
+ {
+ if ((flag & (1UL << position)) != 0U)
+ {
+ HAL_GTZC_TZIC_Callback(GTZC1_PERIPH_REG2 | position);
+ }
+
+ /* Position bit to be updated */
+ position++;
+ }
+ }
+
+ /* Get current IT Flags and IT sources value on 3rd register of TZIC1 */
+ ier_itsources = READ_REG(GTZC_TZIC1_S->IER3);
+ sr_flags = READ_REG(GTZC_TZIC1_S->SR3);
+
+ /* Get Mask interrupt and then clear them */
+ flag = ier_itsources & sr_flags;
+ if (flag != 0U)
+ {
+ WRITE_REG(GTZC_TZIC1_S->FCR3, flag);
+
+ /* Loop on flag to check, which ones have been raised */
+ position = 0U;
+ while ((flag >> position) != 0U)
+ {
+ if ((flag & (1UL << position)) != 0U)
+ {
+ HAL_GTZC_TZIC_Callback(GTZC1_PERIPH_REG3 | position);
+ }
+
+ /* Position bit to be updated */
+ position++;
+ }
+ }
+
+ /* Get current IT Flags and IT sources value on 4th register of TZIC1 */
+ ier_itsources = READ_REG(GTZC_TZIC1_S->IER4);
+ sr_flags = READ_REG(GTZC_TZIC1_S->SR4);
+
+ /* Get Mask interrupt and then clear them */
+ flag = ier_itsources & sr_flags;
+ if (flag != 0U)
+ {
+ WRITE_REG(GTZC_TZIC1_S->FCR4, flag);
+
+ /* Loop on flag to check, which ones have been raised */
+ position = 0U;
+ while ((flag >> position) != 0U)
+ {
+ if ((flag & (1UL << position)) != 0U)
+ {
+ HAL_GTZC_TZIC_Callback(GTZC1_PERIPH_REG4 | position);
+ }
+
+ /* Position bit to be updated */
+ position++;
+ }
+ }
+
+ /*********************************************************************/
+ /****************************** TZIC2 ******************************/
+ /*********************************************************************/
+
+ /* Get current IT Flags and IT sources value on 1st register of TZIC2 */
+ ier_itsources = READ_REG(GTZC_TZIC2_S->IER1);
+ sr_flags = READ_REG(GTZC_TZIC2_S->SR1);
+
+ /* Get Mask interrupt and then clear them */
+ flag = ier_itsources & sr_flags;
+ if (flag != 0U)
+ {
+ WRITE_REG(GTZC_TZIC2_S->FCR1, flag);
+
+ /* Loop on flag to check, which ones have been raised */
+ position = 0U;
+ while ((flag >> position) != 0U)
+ {
+ if ((flag & (1UL << position)) != 0U)
+ {
+ HAL_GTZC_TZIC_Callback(GTZC2_PERIPH_REG1 | position);
+ }
+
+ /* Position bit to be updated */
+ position++;
+ }
+ }
+
+ /* Get current IT Flags and IT sources value on 2nd register of TZIC2 */
+ ier_itsources = READ_REG(GTZC_TZIC2_S->IER2);
+ sr_flags = READ_REG(GTZC_TZIC2_S->SR2);
+
+ /* Get Mask interrupt and then clear them */
+ flag = ier_itsources & sr_flags;
+ if (flag != 0U)
+ {
+ WRITE_REG(GTZC_TZIC2_S->FCR2, flag);
+
+ /* Loop on flag to check, which ones have been raised */
+ position = 0U;
+ while ((flag >> position) != 0U)
+ {
+ if ((flag & (1UL << position)) != 0U)
+ {
+ HAL_GTZC_TZIC_Callback(GTZC2_PERIPH_REG2 | position);
+ }
+
+ /* Position bit to be updated */
+ position++;
+ }
+ }
+}
+
+/**
+ * @brief GTZC TZIC sub-block interrupt callback.
+ * @param PeriphId Peripheral identifier triggering the illegal access.
+ * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId
+ * @retval None.
+ */
+__weak void HAL_GTZC_TZIC_Callback(uint32_t PeriphId)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(PeriphId);
+
+ /* NOTE: This function should not be modified. When the callback is needed,
+ * the HAL_GTZC_TZIC_Callback is to be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/**
+ * @}
+ */
+
+#endif /*HAL_GTZC_MODULE_ENABLED*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hash.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hash.c
new file mode 100644
index 00000000..e37ae59f
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hash.c
@@ -0,0 +1,3558 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_hash.c
+ * @author MCD Application Team
+ * @brief HASH HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the HASH peripheral:
+ * + Initialization and de-initialization methods
+ * + HASH or HMAC processing in polling mode
+ * + HASH or HMAC processing in interrupt mode
+ * + HASH or HMAC processing in DMA mode
+ * + Peripheral State methods
+ * + HASH or HMAC processing suspension/resumption
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ The HASH HAL driver can be used as follows:
+
+ (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():
+ (##) Enable the HASH interface clock using __HASH_CLK_ENABLE()
+ (##) When resorting to interrupt-based APIs (e.g. HAL_HASH_xxx_Start_IT())
+ (+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()
+ (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()
+ (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler() API
+ (##) When resorting to DMA-based APIs (e.g. HAL_HASH_xxx_Start_DMA())
+ (+++) Enable the DMAx interface clock using
+ __DMAx_CLK_ENABLE()
+ (+++) Configure and enable one DMA channel to manage data transfer from
+ memory to peripheral (input channel). Managing data transfer from
+ peripheral to memory can be performed only using CPU.
+ (+++) Associate the initialized DMA handle to the HASH DMA handle
+ using __HAL_LINKDMA()
+ (+++) Configure the priority and enable the NVIC for the transfer complete
+ interrupt on the DMA channel: use
+ HAL_NVIC_SetPriority() and
+ HAL_NVIC_EnableIRQ()
+
+ (#)Initialize the HASH HAL using HAL_HASH_Init(). This function:
+ (##) resorts to HAL_HASH_MspInit() for low-level initialization,
+ (##) configures the data type: 1-bit, 8-bit, 16-bit or 32-bit.
+
+ (#)Three processing schemes are available:
+ (##) Polling mode: processing APIs are blocking functions
+ i.e. they process the data and wait till the digest computation is finished,
+ e.g. HAL_HASH_xxx_Start() for HASH or HAL_HMAC_xxx_Start() for HMAC
+ (##) Interrupt mode: processing APIs are not blocking functions
+ i.e. they process the data under interrupt,
+ e.g. HAL_HASH_xxx_Start_IT() for HASH or HAL_HMAC_xxx_Start_IT() for HMAC
+ (##) DMA mode: processing APIs are not blocking functions and the CPU is
+ not used for data transfer i.e. the data transfer is ensured by DMA,
+ e.g. HAL_HASH_xxx_Start_DMA() for HASH or HAL_HMAC_xxx_Start_DMA()
+ for HMAC. Note that in DMA mode, a call to HAL_HASH_xxx_Finish()
+ is then required to retrieve the digest.
+
+ (#)When the processing function is called after HAL_HASH_Init(), the HASH peripheral is
+ initialized and processes the buffer fed in input. When the input data have all been
+ fed to the Peripheral, the digest computation can start.
+
+ (#)Multi-buffer processing is possible in polling, interrupt and DMA modes.
+ (##) In polling mode, only multi-buffer HASH processing is possible.
+ API HAL_HASH_xxx_Accumulate() must be called for each input buffer, except for the last one.
+ User must resort to HAL_HASH_xxx_Accumulate_End() to enter the last one and retrieve as
+ well the computed digest.
+
+ (##) In interrupt mode, API HAL_HASH_xxx_Accumulate_IT() must be called for each input buffer,
+ except for the last one.
+ User must resort to HAL_HASH_xxx_Accumulate_End_IT() to enter the last one and retrieve as
+ well the computed digest.
+
+ (##) In DMA mode, multi-buffer HASH and HMAC processing are possible.
+ (+++) HASH processing: once initialization is done, MDMAT bit must be set
+ through __HAL_HASH_SET_MDMAT() macro.
+ From that point, each buffer can be fed to the Peripheral through HAL_HASH_xxx_Start_DMA() API.
+ Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
+ macro then wrap-up the HASH processing in feeding the last input buffer through the
+ same API HAL_HASH_xxx_Start_DMA(). The digest can then be retrieved with a call to
+ API HAL_HASH_xxx_Finish().
+ (+++) HMAC processing (requires to resort to extended functions):
+ after initialization, the key and the first input buffer are entered
+ in the Peripheral with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
+ starts step 2.
+ The following buffers are next entered with the API HAL_HMACEx_xxx_Step2_DMA(). At this
+ point, the HMAC processing is still carrying out step 2.
+ Then, step 2 for the last input buffer and step 3 are carried out by a single call
+ to HAL_HMACEx_xxx_Step2_3_DMA().
+
+ The digest can finally be retrieved with a call to API HAL_HASH_xxx_Finish().
+
+
+ (#)Context swapping.
+ (##) Two APIs are available to suspend HASH or HMAC processing:
+ (+++) HAL_HASH_SwFeed_ProcessSuspend() when data are entered by software (polling or IT mode),
+ (+++) HAL_HASH_DMAFeed_ProcessSuspend() when data are entered by DMA.
+
+ (##) When HASH or HMAC processing is suspended, HAL_HASH_ContextSaving() allows
+ to save in memory the Peripheral context. This context can be restored afterwards
+ to resume the HASH processing thanks to HAL_HASH_ContextRestoring().
+
+ (##) Once the HASH Peripheral has been restored to the same configuration as that at suspension
+ time, processing can be restarted with the same API call (same API, same handle,
+ same parameters) as done before the suspension. Relevant parameters to restart at
+ the proper location are internally saved in the HASH handle.
+
+ (#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.
+
+ *** Remarks on message length ***
+ ===================================
+ [..]
+ (#) HAL in interruption mode (interruptions driven)
+
+ (##)Due to HASH peripheral hardware design, the peripheral interruption is triggered every 64 bytes.
+ This is why, for driver implementation simplicity’s sake, user is requested to enter a message the
+ length of which is a multiple of 4 bytes.
+
+ (##) When the message length (in bytes) is not a multiple of words, a specific field exists in HASH_STR
+ to specify which bits to discard at the end of the complete message to process only the message bits
+ and not extra bits.
+
+ (##) If user needs to perform a hash computation of a large input buffer that is spread around various places
+ in memory and where each piece of this input buffer is not necessarily a multiple of 4 bytes in size, it becomes
+ necessary to use a temporary buffer to format the data accordingly before feeding them to the Peripheral.
+ It is advised to the user to
+ (+++) achieve the first formatting operation by software then enter the data
+ (+++) while the Peripheral is processing the first input set, carry out the second formatting
+ operation by software, to be ready when DINIS occurs.
+ (+++) repeat step 2 until the whole message is processed.
+
+ [..]
+ (#) HAL in DMA mode
+
+ (##) Again, due to hardware design, the DMA transfer to feed the data can only be done on a word-basis.
+ The same field described above in HASH_STR is used to specify which bits to discard at the end of the
+ DMA transfer to process only the message bits and not extra bits. Due to hardware implementation,
+ this is possible only at the end of the complete message. When several DMA transfers are needed to
+ enter the message, this is not applicable at the end of the intermediary transfers.
+
+ (##) Similarly to the interruption-driven mode, it is suggested to the user to format the consecutive
+ chunks of data by software while the DMA transfer and processing is on-going for the first parts of
+ the message. Due to the 32-bit alignment required for the DMA transfer, it is underlined that the
+ software formatting operation is more complex than in the IT mode.
+
+ *** Callback registration ***
+ ===================================
+ [..]
+ (#) The compilation define USE_HAL_HASH_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use function @ref HAL_HASH_RegisterCallback() to register a user callback.
+
+ (#) Function @ref HAL_HASH_RegisterCallback() allows to register following callbacks:
+ (+) InCpltCallback : callback for input completion.
+ (+) DgstCpltCallback : callback for digest computation completion.
+ (+) ErrorCallback : callback for error.
+ (+) MspInitCallback : HASH MspInit.
+ (+) MspDeInitCallback : HASH MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ (#) Use function @ref HAL_HASH_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function.
+ @ref HAL_HASH_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) InCpltCallback : callback for input completion.
+ (+) DgstCpltCallback : callback for digest computation completion.
+ (+) ErrorCallback : callback for error.
+ (+) MspInitCallback : HASH MspInit.
+ (+) MspDeInitCallback : HASH MspDeInit.
+
+ (#) By default, after the @ref HAL_HASH_Init and if the state is HAL_HASH_STATE_RESET
+ all callbacks are reset to the corresponding legacy weak (surcharged) functions:
+ examples @ref HAL_HASH_InCpltCallback(), @ref HAL_HASH_DgstCpltCallback()
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_HASH_Init
+ and @ref HAL_HASH_DeInit only when these callbacks are null (not registered beforehand)
+ If not, MspInit or MspDeInit are not null, the @ref HAL_HASH_Init and @ref HAL_HASH_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_HASH_RegisterCallback before calling @ref HAL_HASH_DeInit
+ or @ref HAL_HASH_Init function.
+
+ When The compilation define USE_HAL_HASH_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+#if defined (HASH)
+
+/** @defgroup HASH HASH
+ * @brief HASH HAL module driver.
+ * @{
+ */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup HASH_Private_Constants HASH Private Constants
+ * @{
+ */
+
+/** @defgroup HASH_Digest_Calculation_Status HASH Digest Calculation Status
+ * @{
+ */
+#define HASH_DIGEST_CALCULATION_NOT_STARTED ((uint32_t)0x00000000U) /*!< DCAL not set after input data written in DIN register */
+#define HASH_DIGEST_CALCULATION_STARTED ((uint32_t)0x00000001U) /*!< DCAL set after input data written in DIN register */
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Number_Of_CSR_Registers HASH Number of Context Swap Registers
+ * @{
+ */
+#define HASH_NUMBER_OF_CSR_REGISTERS 54U /*!< Number of Context Swap Registers */
+/**
+ * @}
+ */
+
+/** @defgroup HASH_TimeOut_Value HASH TimeOut Value
+ * @{
+ */
+#define HASH_TIMEOUTVALUE 1000U /*!< Time-out value */
+/**
+ * @}
+ */
+
+/** @defgroup HASH_DMA_Suspension_Words_Limit HASH DMA suspension words limit
+ * @{
+ */
+#define HASH_DMA_SUSPENSION_WORDS_LIMIT 20U /*!< Number of words below which DMA suspension is aborted */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup HASH_Private_Functions HASH Private Functions
+ * @{
+ */
+static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma);
+static void HASH_DMAError(DMA_HandleTypeDef *hdma);
+static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size);
+static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status,
+ uint32_t Timeout);
+static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash);
+static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash);
+static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Exported_Functions HASH Exported Functions
+ * @{
+ */
+
+/** @defgroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization, configuration and call-back functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the HASH according to the specified parameters
+ in the HASH_InitTypeDef and create the associated handle
+ (+) DeInitialize the HASH peripheral
+ (+) Initialize the HASH MCU Specific Package (MSP)
+ (+) DeInitialize the HASH MSP
+
+ [..] This section provides as well call back functions definitions for user
+ code to manage:
+ (+) Input data transfer to Peripheral completion
+ (+) Calculated digest retrieval completion
+ (+) Error management
+
+
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the HASH according to the specified parameters in the
+ HASH_HandleTypeDef and create the associated handle.
+ * @note Only MDMAT and DATATYPE bits of HASH Peripheral are set by HAL_HASH_Init(),
+ * other configuration bits are set by HASH or HMAC processing APIs.
+ * @note MDMAT bit is systematically reset by HAL_HASH_Init(). To set it for
+ * multi-buffer HASH processing, user needs to resort to
+ * __HAL_HASH_SET_MDMAT() macro. For HMAC multi-buffer processing, the
+ * relevant APIs manage themselves the MDMAT bit.
+ * @param hhash HASH handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
+{
+ /* Check the hash handle allocation */
+ if (hhash == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_HASH_DATATYPE(hhash->Init.DataType));
+
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+ if (hhash->State == HAL_HASH_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hhash->Lock = HAL_UNLOCKED;
+
+ /* Reset Callback pointers in HAL_HASH_STATE_RESET only */
+ hhash->InCpltCallback = HAL_HASH_InCpltCallback; /* Legacy weak (surcharged) input completion callback */
+ hhash->DgstCpltCallback = HAL_HASH_DgstCpltCallback; /* Legacy weak (surcharged) digest computation
+ completion callback */
+ hhash->ErrorCallback = HAL_HASH_ErrorCallback; /* Legacy weak (surcharged) error callback */
+ if (hhash->MspInitCallback == NULL)
+ {
+ hhash->MspInitCallback = HAL_HASH_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hhash->MspInitCallback(hhash);
+ }
+#else
+ if (hhash->State == HAL_HASH_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hhash->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware */
+ HAL_HASH_MspInit(hhash);
+ }
+#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Reset HashInCount, HashITCounter, HashBuffSize and NbWordsAlreadyPushed */
+ hhash->HashInCount = 0;
+ hhash->HashBuffSize = 0;
+ hhash->HashITCounter = 0;
+ hhash->NbWordsAlreadyPushed = 0;
+ /* Reset digest calculation bridle (MDMAT bit control) */
+ hhash->DigestCalculationDisable = RESET;
+ /* Set phase to READY */
+ hhash->Phase = HAL_HASH_PHASE_READY;
+ /* Reset suspension request flag */
+ hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE;
+
+ /* Set the data type bit */
+ MODIFY_REG(HASH->CR, HASH_CR_DATATYPE, hhash->Init.DataType);
+ /* Reset MDMAT bit */
+ __HAL_HASH_RESET_MDMAT();
+ /* Reset HASH handle status */
+ hhash->Status = HAL_OK;
+
+ /* Set the HASH state to Ready */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Initialise the error code */
+ hhash->ErrorCode = HAL_HASH_ERROR_NONE;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitialize the HASH peripheral.
+ * @param hhash HASH handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)
+{
+ /* Check the HASH handle allocation */
+ if (hhash == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Set the default HASH phase */
+ hhash->Phase = HAL_HASH_PHASE_READY;
+
+ /* Reset HashInCount, HashITCounter and HashBuffSize */
+ hhash->HashInCount = 0;
+ hhash->HashBuffSize = 0;
+ hhash->HashITCounter = 0;
+ /* Reset digest calculation bridle (MDMAT bit control) */
+ hhash->DigestCalculationDisable = RESET;
+
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+ if (hhash->MspDeInitCallback == NULL)
+ {
+ hhash->MspDeInitCallback = HAL_HASH_MspDeInit;
+ }
+
+ /* DeInit the low level hardware */
+ hhash->MspDeInitCallback(hhash);
+#else
+ /* DeInit the low level hardware: CLOCK, NVIC */
+ HAL_HASH_MspDeInit(hhash);
+#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
+
+
+ /* Reset HASH handle status */
+ hhash->Status = HAL_OK;
+
+ /* Set the HASH state to Ready */
+ hhash->State = HAL_HASH_STATE_RESET;
+
+ /* Initialise the error code */
+ hhash->ErrorCode = HAL_HASH_ERROR_NONE;
+
+ /* Reset multi buffers accumulation flag */
+ hhash->Accumulation = 0U;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the HASH MSP.
+ * @param hhash HASH handle.
+ * @retval None
+ */
+__weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhash);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ HAL_HASH_MspInit() can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief DeInitialize the HASH MSP.
+ * @param hhash HASH handle.
+ * @retval None
+ */
+__weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhash);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ HAL_HASH_MspDeInit() can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Input data transfer complete call back.
+ * @note HAL_HASH_InCpltCallback() is called when the complete input message
+ * has been fed to the Peripheral. This API is invoked only when input data are
+ * entered under interruption or through DMA.
+ * @note In case of HASH or HMAC multi-buffer DMA feeding case (MDMAT bit set),
+ * HAL_HASH_InCpltCallback() is called at the end of each buffer feeding
+ * to the Peripheral.
+ * @param hhash HASH handle.
+ * @retval None
+ */
+__weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhash);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ HAL_HASH_InCpltCallback() can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Digest computation complete call back.
+ * @note HAL_HASH_DgstCpltCallback() is used under interruption, is not
+ * relevant with DMA.
+ * @param hhash HASH handle.
+ * @retval None
+ */
+__weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhash);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ HAL_HASH_DgstCpltCallback() can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Error callback.
+ * @note Code user can resort to hhash->Status (HAL_ERROR, HAL_TIMEOUT,...)
+ * to retrieve the error type.
+ * @param hhash HASH handle.
+ * @retval None
+ */
+__weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhash);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ HAL_HASH_ErrorCallback() can be implemented in the user file.
+ */
+}
+
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User HASH Callback
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hhash HASH handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_HASH_INPUTCPLT_CB_ID HASH input completion Callback ID
+ * @arg @ref HAL_HASH_DGSTCPLT_CB_ID HASH digest computation completion Callback ID
+ * @arg @ref HAL_HASH_ERROR_CB_ID HASH error Callback ID
+ * @arg @ref HAL_HASH_MSPINIT_CB_ID HASH MspInit callback ID
+ * @arg @ref HAL_HASH_MSPDEINIT_CB_ID HASH MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID,
+ pHASH_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hhash);
+
+ if (HAL_HASH_STATE_READY == hhash->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_HASH_INPUTCPLT_CB_ID :
+ hhash->InCpltCallback = pCallback;
+ break;
+
+ case HAL_HASH_DGSTCPLT_CB_ID :
+ hhash->DgstCpltCallback = pCallback;
+ break;
+
+ case HAL_HASH_ERROR_CB_ID :
+ hhash->ErrorCallback = pCallback;
+ break;
+
+ case HAL_HASH_MSPINIT_CB_ID :
+ hhash->MspInitCallback = pCallback;
+ break;
+
+ case HAL_HASH_MSPDEINIT_CB_ID :
+ hhash->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_HASH_STATE_RESET == hhash->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_HASH_MSPINIT_CB_ID :
+ hhash->MspInitCallback = pCallback;
+ break;
+
+ case HAL_HASH_MSPDEINIT_CB_ID :
+ hhash->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hhash);
+ return status;
+}
+
+/**
+ * @brief Unregister a HASH Callback
+ * HASH Callback is redirected to the weak (surcharged) predefined callback
+ * @param hhash HASH handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_HASH_INPUTCPLT_CB_ID HASH input completion Callback ID
+ * @arg @ref HAL_HASH_DGSTCPLT_CB_ID HASH digest computation completion Callback ID
+ * @arg @ref HAL_HASH_ERROR_CB_ID HASH error Callback ID
+ * @arg @ref HAL_HASH_MSPINIT_CB_ID HASH MspInit callback ID
+ * @arg @ref HAL_HASH_MSPDEINIT_CB_ID HASH MspDeInit callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hhash);
+
+ if (HAL_HASH_STATE_READY == hhash->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_HASH_INPUTCPLT_CB_ID :
+ hhash->InCpltCallback = HAL_HASH_InCpltCallback; /* Legacy weak (surcharged) input completion callback */
+ break;
+
+ case HAL_HASH_DGSTCPLT_CB_ID :
+ hhash->DgstCpltCallback = HAL_HASH_DgstCpltCallback; /* Legacy weak (surcharged) digest computation
+ completion callback */
+ break;
+
+ case HAL_HASH_ERROR_CB_ID :
+ hhash->ErrorCallback = HAL_HASH_ErrorCallback; /* Legacy weak (surcharged) error callback */
+ break;
+
+ case HAL_HASH_MSPINIT_CB_ID :
+ hhash->MspInitCallback = HAL_HASH_MspInit; /* Legacy weak (surcharged) Msp Init */
+ break;
+
+ case HAL_HASH_MSPDEINIT_CB_ID :
+ hhash->MspDeInitCallback = HAL_HASH_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_HASH_STATE_RESET == hhash->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_HASH_MSPINIT_CB_ID :
+ hhash->MspInitCallback = HAL_HASH_MspInit; /* Legacy weak (surcharged) Msp Init */
+ break;
+
+ case HAL_HASH_MSPDEINIT_CB_ID :
+ hhash->MspDeInitCallback = HAL_HASH_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hhash);
+ return status;
+}
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode
+ * @brief HASH processing functions using polling mode.
+ *
+@verbatim
+ ===============================================================================
+ ##### Polling mode HASH processing functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in polling mode
+ the hash value using one of the following algorithms:
+ (+) MD5
+ (++) HAL_HASH_MD5_Start()
+ (++) HAL_HASH_MD5_Accmlt()
+ (++) HAL_HASH_MD5_Accmlt_End()
+ (+) SHA1
+ (++) HAL_HASH_SHA1_Start()
+ (++) HAL_HASH_SHA1_Accmlt()
+ (++) HAL_HASH_SHA1_Accmlt_End()
+
+ [..] For a single buffer to be hashed, user can resort to HAL_HASH_xxx_Start().
+
+ [..] In case of multi-buffer HASH processing (a single digest is computed while
+ several buffers are fed to the Peripheral), the user can resort to successive calls
+ to HAL_HASH_xxx_Accumulate() and wrap-up the digest computation by a call
+ to HAL_HASH_xxx_Accumulate_End().
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the HASH peripheral in MD5 mode, next process pInBuffer then
+ * read the computed digest.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
+ * @param Timeout Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout)
+{
+ return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5);
+}
+
+/**
+ * @brief If not already done, initialize the HASH peripheral in MD5 mode then
+ * processes pInBuffer.
+ * @note Consecutive calls to HAL_HASH_MD5_Accmlt() can be used to feed
+ * several input buffers back-to-back to the Peripheral that will yield a single
+ * HASH signature once all buffers have been entered. Wrap-up of input
+ * buffers feeding and retrieval of digest is done by a call to
+ * HAL_HASH_MD5_Accmlt_End().
+ * @note Field hhash->Phase of HASH handle is tested to check whether or not
+ * the Peripheral has already been initialized.
+ * @note Digest is not retrieved by this API, user must resort to HAL_HASH_MD5_Accmlt_End()
+ * to read it, feeding at the same time the last input buffer to the Peripheral.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted. Only HAL_HASH_MD5_Accmlt_End() is able
+ * to manage the ending buffer with a length in bytes not a multiple of 4.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes, must be a multiple of 4.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
+}
+
+/**
+ * @brief End computation of a single HASH signature after several calls to HAL_HASH_MD5_Accmlt() API.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
+ * @param Timeout Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout)
+{
+ return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5);
+}
+
+/**
+ * @brief Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then
+ * read the computed digest.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
+ * @param Timeout Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout)
+{
+ return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1);
+}
+
+/**
+ * @brief If not already done, initialize the HASH peripheral in SHA1 mode then
+ * processes pInBuffer.
+ * @note Consecutive calls to HAL_HASH_SHA1_Accmlt() can be used to feed
+ * several input buffers back-to-back to the Peripheral that will yield a single
+ * HASH signature once all buffers have been entered. Wrap-up of input
+ * buffers feeding and retrieval of digest is done by a call to
+ * HAL_HASH_SHA1_Accmlt_End().
+ * @note Field hhash->Phase of HASH handle is tested to check whether or not
+ * the Peripheral has already been initialized.
+ * @note Digest is not retrieved by this API, user must resort to HAL_HASH_SHA1_Accmlt_End()
+ * to read it, feeding at the same time the last input buffer to the Peripheral.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted. Only HAL_HASH_SHA1_Accmlt_End() is able
+ * to manage the ending buffer with a length in bytes not a multiple of 4.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes, must be a multiple of 4.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
+}
+
+/**
+ * @brief End computation of a single HASH signature after several calls to HAL_HASH_SHA1_Accmlt() API.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
+ * @param Timeout Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout)
+{
+ return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Exported_Functions_Group3 HASH processing functions in interrupt mode
+ * @brief HASH processing functions using interrupt mode.
+ *
+@verbatim
+ ===============================================================================
+ ##### Interruption mode HASH processing functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in interrupt mode
+ the hash value using one of the following algorithms:
+ (+) MD5
+ (++) HAL_HASH_MD5_Start_IT()
+ (++) HAL_HASH_MD5_Accmlt_IT()
+ (++) HAL_HASH_MD5_Accmlt_End_IT()
+ (+) SHA1
+ (++) HAL_HASH_SHA1_Start_IT()
+ (++) HAL_HASH_SHA1_Accmlt_IT()
+ (++) HAL_HASH_SHA1_Accmlt_End_IT()
+
+ [..] API HAL_HASH_IRQHandler() manages each HASH interruption.
+
+ [..] Note that HAL_HASH_IRQHandler() manages as well HASH Peripheral interruptions when in
+ HMAC processing mode.
+
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the HASH peripheral in MD5 mode, next process pInBuffer then
+ * read the computed digest in interruption mode.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer)
+{
+ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5);
+}
+
+/**
+ * @brief If not already done, initialize the HASH peripheral in MD5 mode then
+ * processes pInBuffer in interruption mode.
+ * @note Consecutive calls to HAL_HASH_MD5_Accmlt_IT() can be used to feed
+ * several input buffers back-to-back to the Peripheral that will yield a single
+ * HASH signature once all buffers have been entered. Wrap-up of input
+ * buffers feeding and retrieval of digest is done by a call to
+ * HAL_HASH_MD5_Accmlt_End_IT().
+ * @note Field hhash->Phase of HASH handle is tested to check whether or not
+ * the Peripheral has already been initialized.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted. Only HAL_HASH_MD5_Accmlt_End_IT() is able
+ * to manage the ending buffer with a length in bytes not a multiple of 4.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes, must be a multiple of 4.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
+}
+
+/**
+ * @brief End computation of a single HASH signature after several calls to HAL_HASH_MD5_Accmlt_IT() API.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer)
+{
+ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5);
+}
+
+/**
+ * @brief Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then
+ * read the computed digest in interruption mode.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer)
+{
+ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1);
+}
+
+
+/**
+ * @brief If not already done, initialize the HASH peripheral in SHA1 mode then
+ * processes pInBuffer in interruption mode.
+ * @note Consecutive calls to HAL_HASH_SHA1_Accmlt_IT() can be used to feed
+ * several input buffers back-to-back to the Peripheral that will yield a single
+ * HASH signature once all buffers have been entered. Wrap-up of input
+ * buffers feeding and retrieval of digest is done by a call to
+ * HAL_HASH_SHA1_Accmlt_End_IT().
+ * @note Field hhash->Phase of HASH handle is tested to check whether or not
+ * the Peripheral has already been initialized.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted. Only HAL_HASH_SHA1_Accmlt_End_IT() is able
+ * to manage the ending buffer with a length in bytes not a multiple of 4.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes, must be a multiple of 4.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
+}
+
+/**
+ * @brief End computation of a single HASH signature after several calls to HAL_HASH_SHA1_Accmlt_IT() API.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer)
+{
+ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1);
+}
+
+/**
+ * @brief Handle HASH interrupt request.
+ * @param hhash HASH handle.
+ * @note HAL_HASH_IRQHandler() handles interrupts in HMAC processing as well.
+ * @note In case of error reported during the HASH interruption processing,
+ * HAL_HASH_ErrorCallback() API is called so that user code can
+ * manage the error. The error type is available in hhash->Status field.
+ * @retval None
+ */
+void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash)
+{
+ hhash->Status = HASH_IT(hhash);
+ if (hhash->Status != HAL_OK)
+ {
+ hhash->ErrorCode |= HAL_HASH_ERROR_IT;
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+ hhash->ErrorCallback(hhash);
+#else
+ HAL_HASH_ErrorCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+ /* After error handling by code user, reset HASH handle HAL status */
+ hhash->Status = HAL_OK;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Exported_Functions_Group4 HASH processing functions in DMA mode
+ * @brief HASH processing functions using DMA mode.
+ *
+@verbatim
+ ===============================================================================
+ ##### DMA mode HASH processing functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in DMA mode
+ the hash value using one of the following algorithms:
+ (+) MD5
+ (++) HAL_HASH_MD5_Start_DMA()
+ (++) HAL_HASH_MD5_Finish()
+ (+) SHA1
+ (++) HAL_HASH_SHA1_Start_DMA()
+ (++) HAL_HASH_SHA1_Finish()
+
+ [..] When resorting to DMA mode to enter the data in the Peripheral, user must resort
+ to HAL_HASH_xxx_Start_DMA() then read the resulting digest with
+ HAL_HASH_xxx_Finish().
+ [..] In case of multi-buffer HASH processing, MDMAT bit must first be set before
+ the successive calls to HAL_HASH_xxx_Start_DMA(). Then, MDMAT bit needs to be
+ reset before the last call to HAL_HASH_xxx_Start_DMA(). Digest is finally
+ retrieved thanks to HAL_HASH_xxx_Finish().
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the HASH peripheral in MD5 mode then initiate a DMA transfer
+ * to feed the input buffer to the Peripheral.
+ * @note Once the DMA transfer is finished, HAL_HASH_MD5_Finish() API must
+ * be called to retrieve the computed digest.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
+}
+
+/**
+ * @brief Return the computed digest in MD5 mode.
+ * @note The API waits for DCIS to be set then reads the computed digest.
+ * @note HAL_HASH_MD5_Finish() can be used as well to retrieve the digest in
+ * HMAC MD5 mode.
+ * @param hhash HASH handle.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
+ * @param Timeout Timeout value.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
+{
+ return HASH_Finish(hhash, pOutBuffer, Timeout);
+}
+
+/**
+ * @brief Initialize the HASH peripheral in SHA1 mode then initiate a DMA transfer
+ * to feed the input buffer to the Peripheral.
+ * @note Once the DMA transfer is finished, HAL_HASH_SHA1_Finish() API must
+ * be called to retrieve the computed digest.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
+}
+
+
+/**
+ * @brief Return the computed digest in SHA1 mode.
+ * @note The API waits for DCIS to be set then reads the computed digest.
+ * @note HAL_HASH_SHA1_Finish() can be used as well to retrieve the digest in
+ * HMAC SHA1 mode.
+ * @param hhash HASH handle.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
+ * @param Timeout Timeout value.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
+{
+ return HASH_Finish(hhash, pOutBuffer, Timeout);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Exported_Functions_Group5 HMAC processing functions in polling mode
+ * @brief HMAC processing functions using polling mode.
+ *
+@verbatim
+ ===============================================================================
+ ##### Polling mode HMAC processing functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in polling mode
+ the HMAC value using one of the following algorithms:
+ (+) MD5
+ (++) HAL_HMAC_MD5_Start()
+ (+) SHA1
+ (++) HAL_HMAC_SHA1_Start()
+
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then
+ * read the computed digest.
+ * @note Digest is available in pOutBuffer.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
+ * @param Timeout Timeout value.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout)
+{
+ return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5);
+}
+
+/**
+ * @brief Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then
+ * read the computed digest.
+ * @note Digest is available in pOutBuffer.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
+ * @param Timeout Timeout value.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout)
+{
+ return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1);
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HASH_Exported_Functions_Group6 HMAC processing functions in interrupt mode
+ * @brief HMAC processing functions using interrupt mode.
+ *
+@verbatim
+ ===============================================================================
+ ##### Interrupt mode HMAC processing functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in interrupt mode
+ the HMAC value using one of the following algorithms:
+ (+) MD5
+ (++) HAL_HMAC_MD5_Start_IT()
+ (+) SHA1
+ (++) HAL_HMAC_SHA1_Start_IT()
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then
+ * read the computed digest in interrupt mode.
+ * @note Digest is available in pOutBuffer.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer)
+{
+ return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5);
+}
+
+/**
+ * @brief Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then
+ * read the computed digest in interrupt mode.
+ * @note Digest is available in pOutBuffer.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer)
+{
+ return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1);
+}
+
+/**
+ * @}
+ */
+
+
+
+/** @defgroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode
+ * @brief HMAC processing functions using DMA modes.
+ *
+@verbatim
+ ===============================================================================
+ ##### DMA mode HMAC processing functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in DMA mode
+ the HMAC value using one of the following algorithms:
+ (+) MD5
+ (++) HAL_HMAC_MD5_Start_DMA()
+ (+) SHA1
+ (++) HAL_HMAC_SHA1_Start_DMA()
+
+ [..] When resorting to DMA mode to enter the data in the Peripheral for HMAC processing,
+ user must resort to HAL_HMAC_xxx_Start_DMA() then read the resulting digest
+ with HAL_HASH_xxx_Finish().
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Initialize the HASH peripheral in HMAC MD5 mode then initiate the required
+ * DMA transfers to feed the key and the input buffer to the Peripheral.
+ * @note Once the DMA transfers are finished (indicated by hhash->State set back
+ * to HAL_HASH_STATE_READY), HAL_HASH_MD5_Finish() API must be called to retrieve
+ * the computed digest.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note If MDMAT bit is set before calling this function (multi-buffer
+ * HASH processing case), the input buffer size (in bytes) must be
+ * a multiple of 4 otherwise, the HASH digest computation is corrupted.
+ * For the processing of the last buffer of the thread, MDMAT bit must
+ * be reset and the buffer length (in bytes) doesn't have to be a
+ * multiple of 4.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
+}
+
+
+/**
+ * @brief Initialize the HASH peripheral in HMAC SHA1 mode then initiate the required
+ * DMA transfers to feed the key and the input buffer to the Peripheral.
+ * @note Once the DMA transfers are finished (indicated by hhash->State set back
+ * to HAL_HASH_STATE_READY), HAL_HASH_SHA1_Finish() API must be called to retrieve
+ * the computed digest.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note If MDMAT bit is set before calling this function (multi-buffer
+ * HASH processing case), the input buffer size (in bytes) must be
+ * a multiple of 4 otherwise, the HASH digest computation is corrupted.
+ * For the processing of the last buffer of the thread, MDMAT bit must
+ * be reset and the buffer length (in bytes) doesn't have to be a
+ * multiple of 4.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Exported_Functions_Group8 Peripheral states functions
+ * @brief Peripheral State functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State methods #####
+ ===============================================================================
+ [..]
+ This section permits to get in run-time the state and the peripheral handle
+ status of the peripheral:
+ (+) HAL_HASH_GetState()
+ (+) HAL_HASH_GetStatus()
+
+ [..]
+ Additionally, this subsection provides functions allowing to save and restore
+ the HASH or HMAC processing context in case of calculation suspension:
+ (+) HAL_HASH_ContextSaving()
+ (+) HAL_HASH_ContextRestoring()
+
+ [..]
+ This subsection provides functions allowing to suspend the HASH processing
+ (+) when input are fed to the Peripheral by software
+ (++) HAL_HASH_SwFeed_ProcessSuspend()
+ (+) when input are fed to the Peripheral by DMA
+ (++) HAL_HASH_DMAFeed_ProcessSuspend()
+
+
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the HASH handle state.
+ * @note The API yields the current state of the handle (BUSY, READY,...).
+ * @param hhash HASH handle.
+ * @retval HAL HASH state
+ */
+HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
+{
+ return hhash->State;
+}
+
+
+/**
+ * @brief Return the HASH HAL status.
+ * @note The API yields the HAL status of the handle: it is the result of the
+ * latest HASH processing and allows to report any issue (e.g. HAL_TIMEOUT).
+ * @param hhash HASH handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash)
+{
+ return hhash->Status;
+}
+
+/**
+ * @brief Save the HASH context in case of processing suspension.
+ * @param hhash HASH handle.
+ * @param pMemBuffer pointer to the memory buffer where the HASH context
+ * is saved.
+ * @note The IMR, STR, CR then all the CSR registers are saved
+ * in that order. Only the r/w bits are read to be restored later on.
+ * @note By default, all the context swap registers (there are
+ * HASH_NUMBER_OF_CSR_REGISTERS of those) are saved.
+ * @note pMemBuffer points to a buffer allocated by the user. The buffer size
+ * must be at least (HASH_NUMBER_OF_CSR_REGISTERS + 3) * 4 uint8 long.
+ * @retval None
+ */
+void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer)
+{
+ uint32_t mem_ptr = (uint32_t)pMemBuffer;
+ uint32_t csr_ptr = (uint32_t)HASH->CSR;
+ uint32_t i;
+
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhash);
+
+ /* Save IMR register content */
+ *(uint32_t *)(mem_ptr) = READ_BIT(HASH->IMR, HASH_IT_DINI | HASH_IT_DCI);
+ mem_ptr += 4U;
+ /* Save STR register content */
+ *(uint32_t *)(mem_ptr) = READ_BIT(HASH->STR, HASH_STR_NBLW);
+ mem_ptr += 4U;
+ /* Save CR register content */
+ *(uint32_t *)(mem_ptr) = READ_BIT(HASH->CR, HASH_CR_DMAE | HASH_CR_DATATYPE | HASH_CR_MODE | HASH_CR_ALGO |
+ HASH_CR_LKEY | HASH_CR_MDMAT);
+ mem_ptr += 4U;
+ /* By default, save all CSRs registers */
+ for (i = HASH_NUMBER_OF_CSR_REGISTERS; i > 0U; i--)
+ {
+ *(uint32_t *)(mem_ptr) = *(uint32_t *)(csr_ptr);
+ mem_ptr += 4U;
+ csr_ptr += 4U;
+ }
+}
+
+
+/**
+ * @brief Restore the HASH context in case of processing resumption.
+ * @param hhash HASH handle.
+ * @param pMemBuffer pointer to the memory buffer where the HASH context
+ * is stored.
+ * @note The IMR, STR, CR then all the CSR registers are restored
+ * in that order. Only the r/w bits are restored.
+ * @note By default, all the context swap registers (HASH_NUMBER_OF_CSR_REGISTERS
+ * of those) are restored (all of them have been saved by default
+ * beforehand).
+ * @retval None
+ */
+void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer)
+{
+ uint32_t mem_ptr = (uint32_t)pMemBuffer;
+ uint32_t csr_ptr = (uint32_t)HASH->CSR;
+ uint32_t i;
+
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhash);
+
+ /* Restore IMR register content */
+ WRITE_REG(HASH->IMR, (*(uint32_t *)(mem_ptr)));
+ mem_ptr += 4U;
+ /* Restore STR register content */
+ WRITE_REG(HASH->STR, (*(uint32_t *)(mem_ptr)));
+ mem_ptr += 4U;
+ /* Restore CR register content */
+ WRITE_REG(HASH->CR, (*(uint32_t *)(mem_ptr)));
+ mem_ptr += 4U;
+
+ /* Reset the HASH processor before restoring the Context
+ Swap Registers (CSR) */
+ __HAL_HASH_INIT();
+
+ /* By default, restore all CSR registers */
+ for (i = HASH_NUMBER_OF_CSR_REGISTERS; i > 0U; i--)
+ {
+ WRITE_REG((*(uint32_t *)(csr_ptr)), (*(uint32_t *)(mem_ptr)));
+ mem_ptr += 4U;
+ csr_ptr += 4U;
+ }
+}
+
+
+/**
+ * @brief Initiate HASH processing suspension when in polling or interruption mode.
+ * @param hhash HASH handle.
+ * @note Set the handle field SuspendRequest to the appropriate value so that
+ * the on-going HASH processing is suspended as soon as the required
+ * conditions are met. Note that the actual suspension is carried out
+ * by the functions HASH_WriteData() in polling mode and HASH_IT() in
+ * interruption mode.
+ * @retval None
+ */
+void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash)
+{
+ /* Set Handle Suspend Request field */
+ hhash->SuspendRequest = HAL_HASH_SUSPEND;
+}
+
+/**
+ * @brief Suspend the HASH processing when in DMA mode.
+ * @param hhash HASH handle.
+ * @note When suspension attempt occurs at the very end of a DMA transfer and
+ * all the data have already been entered in the Peripheral, hhash->State is
+ * set to HAL_HASH_STATE_READY and the API returns HAL_ERROR. It is
+ * recommended to wrap-up the processing in reading the digest as usual.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash)
+{
+ uint32_t tmp_remaining_DMATransferSize_inWords;
+ uint32_t tmp_initial_DMATransferSize_inWords;
+
+ if (hhash->State == HAL_HASH_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+
+ /* Make sure there is enough time to suspend the processing */
+ /* DMA3 used, DMA_CBR1_BNDT in bytes*/
+ tmp_remaining_DMATransferSize_inWords = ((((DMA_Channel_TypeDef *)hhash->hdmain->Instance)->CBR1) \
+ & DMA_CBR1_BNDT) / 4U;
+
+ if (tmp_remaining_DMATransferSize_inWords <= HASH_DMA_SUSPENSION_WORDS_LIMIT)
+ {
+ /* No suspension attempted since almost to the end of the transferred data. */
+ /* Best option for user code is to wrap up low priority message hashing */
+ return HAL_ERROR;
+ }
+ /* Clear the DMAE bit to disable the DMA interface */
+ CLEAR_BIT(HASH->CR, HASH_CR_DMAE);
+
+ /* Wait until the last DMA transfer is complete (DMAS = 0 in the HASH_SR register) */
+ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DMAS, SET, HASH_TIMEOUTVALUE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* At this point, DMA interface is disabled and no transfer is on-going */
+ /* Retrieve from the DMA handle how many words remain to be written */
+ /* DMA3 used, DMA_CBR1_BNDT in bytes, DMA_CSR_FIFOL in words */
+ tmp_remaining_DMATransferSize_inWords = ((((DMA_Channel_TypeDef *)hhash->hdmain->Instance)->CBR1) \
+ & DMA_CBR1_BNDT) / 4U;
+ tmp_remaining_DMATransferSize_inWords += ((((DMA_Channel_TypeDef *)hhash->hdmain->Instance)->CSR) \
+ & DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos;
+
+ /* Disable DMA channel */
+ /* Note that the Abort function will
+ - Clear the transfer error flags
+ - Unlock
+ - Set the State
+ */
+ if (HAL_DMA_Abort(hhash->hdmain) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS) != RESET)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Wait until the hash processor is ready (no block is being processed), that is wait for DINIS=1 in HASH_SR */
+ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DINIS, RESET, HASH_TIMEOUTVALUE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if (tmp_remaining_DMATransferSize_inWords == 0U)
+ {
+ /* All the DMA transfer is actually done. Suspension occurred at the very end
+ of the transfer. Either the digest computation is about to start (HASH case)
+ or processing is about to move from one step to another (HMAC case).
+ In both cases, the processing can't be suspended at this point. It is
+ safer to
+ - retrieve the low priority block digest before starting the high
+ priority block processing (HASH case)
+ - re-attempt a new suspension (HMAC case)
+ */
+ return HAL_ERROR;
+ }
+ else
+ {
+
+ /* Compute how many words were supposed to be transferred by DMA */
+ tmp_initial_DMATransferSize_inWords = (((hhash->HashInCount % 4U) != 0U) ? \
+ ((hhash->HashInCount + 3U) / 4U) : (hhash->HashInCount / 4U));
+ /* Accordingly, update the input pointer that points at the next word to be
+ transferred to the Peripheral by DMA */
+ hhash->pHashInBuffPtr += 4U * (tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) ;
+
+ /* And store in HashInCount the remaining size to transfer (in bytes) */
+ hhash->HashInCount = 4U * tmp_remaining_DMATransferSize_inWords;
+
+ }
+
+ /* Set State as suspended */
+ hhash->State = HAL_HASH_STATE_SUSPENDED;
+
+ return HAL_OK;
+
+ }
+}
+
+/**
+ * @brief Return the HASH handle error code.
+ * @param hhash pointer to a HASH_HandleTypeDef structure.
+ * @retval HASH Error Code
+ */
+uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash)
+{
+ /* Return HASH Error Code */
+ return hhash->ErrorCode;
+}
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Private_Functions HASH Private Functions
+ * @{
+ */
+
+/**
+ * @brief DMA HASH Input Data transfer completion callback.
+ * @param hdma DMA handle.
+ * @note In case of HMAC processing, HASH_DMAXferCplt() initiates
+ * the next DMA transfer for the following HMAC step.
+ * @retval None
+ */
+static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma)
+{
+ HASH_HandleTypeDef *hhash = (HASH_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ uint32_t inputaddr;
+ uint32_t buffersize;
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (hhash->State != HAL_HASH_STATE_SUSPENDED)
+ {
+
+ /* Disable the DMA transfer */
+ CLEAR_BIT(HASH->CR, HASH_CR_DMAE);
+
+ if (READ_BIT(HASH->CR, HASH_CR_MODE) == 0U)
+ {
+ /* If no HMAC processing, input data transfer is now over */
+
+ /* Change the HASH state to ready */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Call Input data transfer complete call back */
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+ hhash->InCpltCallback(hhash);
+#else
+ HAL_HASH_InCpltCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+
+ }
+ else
+ {
+ /* HMAC processing: depending on the current HMAC step and whether or
+ not multi-buffer processing is on-going, the next step is initiated
+ and MDMAT bit is set. */
+
+
+ if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)
+ {
+ /* This is the end of HMAC processing */
+
+ /* Change the HASH state to ready */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Call Input data transfer complete call back
+ (note that the last DMA transfer was that of the key
+ for the outer HASH operation). */
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+ hhash->InCpltCallback(hhash);
+#else
+ HAL_HASH_InCpltCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+
+ return;
+ }
+ else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1)
+ {
+ inputaddr = (uint32_t)hhash->pHashMsgBuffPtr; /* DMA transfer start address */
+ buffersize = hhash->HashBuffSize; /* DMA transfer size (in bytes) */
+ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2; /* Move phase from Step 1 to Step 2 */
+
+ /* In case of suspension request, save the new starting parameters */
+ hhash->HashInCount = hhash->HashBuffSize; /* Initial DMA transfer size (in bytes) */
+ hhash->pHashInBuffPtr = hhash->pHashMsgBuffPtr ; /* DMA transfer start address */
+
+ hhash->NbWordsAlreadyPushed = 0U; /* Reset number of words already pushed */
+ /* Check whether or not digest calculation must be disabled (in case of multi-buffer HMAC processing) */
+ if (hhash->DigestCalculationDisable != RESET)
+ {
+ /* Digest calculation is disabled: Step 2 must start with MDMAT bit set,
+ no digest calculation will be triggered at the end of the input buffer feeding to the Peripheral */
+ __HAL_HASH_SET_MDMAT();
+ }
+ }
+ else /*case (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)*/
+ {
+ if (hhash->DigestCalculationDisable != RESET)
+ {
+ /* No automatic move to Step 3 as a new message buffer will be fed to the Peripheral
+ (case of multi-buffer HMAC processing):
+ DCAL must not be set.
+ Phase remains in Step 2, MDMAT remains set at this point.
+ Change the HASH state to ready and call Input data transfer complete call back. */
+ hhash->State = HAL_HASH_STATE_READY;
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+ hhash->InCpltCallback(hhash);
+#else
+ HAL_HASH_InCpltCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+ return ;
+ }
+ else
+ {
+ /* Digest calculation is not disabled (case of single buffer input or last buffer
+ of multi-buffer HMAC processing) */
+ inputaddr = (uint32_t)hhash->Init.pKey; /* DMA transfer start address */
+ buffersize = hhash->Init.KeySize; /* DMA transfer size (in bytes) */
+ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3; /* Move phase from Step 2 to Step 3 */
+ /* In case of suspension request, save the new starting parameters */
+ hhash->HashInCount = hhash->Init.KeySize; /* Initial size for second DMA transfer (input data) */
+ hhash->pHashInBuffPtr = hhash->Init.pKey ; /* address passed to DMA, now entering data message */
+
+ hhash->NbWordsAlreadyPushed = 0U; /* Reset number of words already pushed */
+ }
+ }
+
+ /* Configure the Number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(buffersize);
+
+ /* Set the HASH DMA transfer completion call back */
+ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
+
+ /* Enable the DMA In DMA channel */
+ if ((hhash->hdmain->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if ((hhash->hdmain->LinkedListQueue != NULL) && (hhash->hdmain->LinkedListQueue->Head != NULL))
+ {
+ /* Set DMA data size */
+ hhash->hdmain->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET]\
+ = (((buffersize % 4U) != 0U) ? (buffersize + (4U - (buffersize % 4U))) : (buffersize));
+ /* Set DMA source address */
+ hhash->hdmain->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = inputaddr;
+ /* Set DMA destination address */
+ hhash->hdmain->LinkedListQueue->Head->\
+ LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&HASH->DIN;
+
+ status = HAL_DMAEx_List_Start_IT(hhash->hdmain);
+ }
+ else
+ {
+ /* Update HASH state machine to error */
+ hhash->State = HAL_HASH_STATE_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, \
+ (((buffersize % 4U) != 0U) ? (buffersize + (4U - (buffersize % 4U))) : (buffersize)));
+ }
+
+ if (status != HAL_OK)
+ {
+ /* Update HASH state machine to error */
+ hhash->State = HAL_HASH_STATE_ERROR;
+ }
+
+ /* Enable DMA requests */
+ SET_BIT(HASH->CR, HASH_CR_DMAE);
+
+ /* Return function status */
+ if (status != HAL_OK)
+ {
+ /* Update HASH state machine to error */
+ hhash->State = HAL_HASH_STATE_ERROR;
+ }
+ else
+ {
+ /* Change HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+ }
+ }
+ }
+
+ return;
+}
+
+/**
+ * @brief DMA HASH communication error callback.
+ * @param hdma DMA handle.
+ * @note HASH_DMAError() callback invokes HAL_HASH_ErrorCallback() that
+ * can contain user code to manage the error.
+ * @retval None
+ */
+static void HASH_DMAError(DMA_HandleTypeDef *hdma)
+{
+ HASH_HandleTypeDef *hhash = (HASH_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ if (hhash->State != HAL_HASH_STATE_SUSPENDED)
+ {
+ hhash->ErrorCode |= HAL_HASH_ERROR_DMA;
+ /* Set HASH state to ready to prevent any blocking issue in user code
+ present in HAL_HASH_ErrorCallback() */
+ hhash->State = HAL_HASH_STATE_READY;
+ /* Set HASH handle status to error */
+ hhash->Status = HAL_ERROR;
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+ hhash->ErrorCallback(hhash);
+#else
+ HAL_HASH_ErrorCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+ /* After error handling by code user, reset HASH handle HAL status */
+ hhash->Status = HAL_OK;
+
+ }
+}
+
+/**
+ * @brief Feed the input buffer to the HASH Peripheral.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to input buffer.
+ * @param Size the size of input buffer in bytes.
+ * @note HASH_WriteData() regularly reads hhash->SuspendRequest to check whether
+ * or not the HASH processing must be suspended. If this is the case, the
+ * processing is suspended when possible and the Peripheral feeding point reached at
+ * suspension time is stored in the handle for resumption later on.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ uint32_t buffercounter;
+ __IO uint32_t inputaddr = (uint32_t) pInBuffer;
+
+ for (buffercounter = 0U; buffercounter < Size; buffercounter += 4U)
+ {
+ /* Write input data 4 bytes at a time */
+ HASH->DIN = *(uint32_t *)inputaddr;
+ inputaddr += 4U;
+
+ /* If the suspension flag has been raised and if the processing is not about
+ to end, suspend processing */
+ if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter + 4U) < Size))
+ {
+ /* wait for flag BUSY not set before Wait for DINIS = 1*/
+ if (buffercounter >= 64U)
+ {
+ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Wait for DINIS = 1, which occurs when 16 32-bit locations are free
+ in the input buffer */
+ if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
+ {
+ /* Reset SuspendRequest */
+ hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE;
+
+ /* Depending whether the key or the input data were fed to the Peripheral, the feeding point
+ reached at suspension time is not saved in the same handle fields */
+ if ((hhash->Phase == HAL_HASH_PHASE_PROCESS) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2))
+ {
+ /* Save current reading and writing locations of Input and Output buffers */
+ hhash->pHashInBuffPtr = (uint8_t *)inputaddr;
+ /* Save the number of bytes that remain to be processed at this point */
+ hhash->HashInCount = Size - (buffercounter + 4U);
+ }
+ else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
+ {
+ /* Save current reading and writing locations of Input and Output buffers */
+ hhash->pHashKeyBuffPtr = (uint8_t *)inputaddr;
+ /* Save the number of bytes that remain to be processed at this point */
+ hhash->HashKeyCount = Size - (buffercounter + 4U);
+ }
+ else
+ {
+ /* Unexpected phase: unlock process and report error */
+ hhash->State = HAL_HASH_STATE_READY;
+ __HAL_UNLOCK(hhash);
+ return HAL_ERROR;
+ }
+
+ /* Set the HASH state to Suspended and exit to stop entering data */
+ hhash->State = HAL_HASH_STATE_SUSPENDED;
+
+ return HAL_OK;
+ } /* if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS)) */
+ } /* if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter+4) < Size)) */
+ } /* for(buffercounter = 0; buffercounter < Size; buffercounter+=4) */
+
+ /* At this point, all the data have been entered to the Peripheral: exit */
+ return HAL_OK;
+}
+
+/**
+ * @brief Retrieve the message digest.
+ * @param pMsgDigest pointer to the computed digest.
+ * @param Size message digest size in bytes.
+ * @retval None
+ */
+static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
+{
+ uint32_t msgdigest = (uint32_t)pMsgDigest;
+
+ switch (Size)
+ {
+ /* Read the message digest */
+ case 16: /* MD5 */
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[0]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[1]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[2]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[3]);
+ break;
+ case 20: /* SHA1 */
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[0]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[1]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[2]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[3]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[4]);
+ break;
+ case 28: /* SHA224 */
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[0]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[1]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[2]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[3]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[4]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
+ break;
+ case 32: /* SHA256 */
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[0]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[1]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[2]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[3]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[4]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[7]);
+ break;
+ default:
+ break;
+ }
+}
+
+
+
+/**
+ * @brief Handle HASH processing Timeout.
+ * @param hhash HASH handle.
+ * @param Flag specifies the HASH flag to check.
+ * @param Status the Flag status (SET or RESET).
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status,
+ uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Wait until flag is set */
+ if (Status == RESET)
+ {
+ while (__HAL_HASH_GET_FLAG(Flag) == RESET)
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ /* Set State to Ready to be able to restart later on */
+ hhash->State = HAL_HASH_STATE_READY;
+ /* Store time out issue in handle status */
+ hhash->Status = HAL_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ while (__HAL_HASH_GET_FLAG(Flag) != RESET)
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ /* Set State to Ready to be able to restart later on */
+ hhash->State = HAL_HASH_STATE_READY;
+ /* Store time out issue in handle status */
+ hhash->Status = HAL_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+
+/**
+ * @brief HASH processing in interruption mode.
+ * @param hhash HASH handle.
+ * @note HASH_IT() regularly reads hhash->SuspendRequest to check whether
+ * or not the HASH processing must be suspended. If this is the case, the
+ * processing is suspended when possible and the Peripheral feeding point reached at
+ * suspension time is stored in the handle for resumption later on.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash)
+{
+ if (hhash->State == HAL_HASH_STATE_BUSY)
+ {
+ /* ITCounter must not be equal to 0 at this point. Report an error if this is the case. */
+ if (hhash->HashITCounter == 0U)
+ {
+ /* Disable Interrupts */
+ __HAL_HASH_DISABLE_IT(HASH_IT_DINI | HASH_IT_DCI);
+ /* HASH state set back to Ready to prevent any issue in user code
+ present in HAL_HASH_ErrorCallback() */
+ hhash->State = HAL_HASH_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if (hhash->HashITCounter == 1U)
+ {
+ /* This is the first call to HASH_IT, the first input data are about to be
+ entered in the Peripheral. A specific processing is carried out at this point to
+ start-up the processing. */
+ hhash->HashITCounter = 2U;
+ }
+ else
+ {
+ /* Cruise speed reached, HashITCounter remains equal to 3 until the end of
+ the HASH processing or the end of the current step for HMAC processing. */
+ hhash->HashITCounter = 3U;
+ }
+
+ /* If digest is ready */
+ if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
+ {
+ /* Read the digest */
+ HASH_GetDigest(hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH());
+
+ /* Disable Interrupts */
+ __HAL_HASH_DISABLE_IT(HASH_IT_DINI | HASH_IT_DCI);
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+ /* Reset HASH state machine */
+ hhash->Phase = HAL_HASH_PHASE_READY;
+ /* Call digest computation complete call back */
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+ hhash->DgstCpltCallback(hhash);
+#else
+ HAL_HASH_DgstCpltCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+
+ return HAL_OK;
+ }
+
+ /* If Peripheral ready to accept new data */
+ if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
+ {
+
+ /* If the suspension flag has been raised and if the processing is not about
+ to end, suspend processing */
+ if ((hhash->HashInCount != 0U) && (hhash->SuspendRequest == HAL_HASH_SUSPEND))
+ {
+ /* Disable Interrupts */
+ __HAL_HASH_DISABLE_IT(HASH_IT_DINI | HASH_IT_DCI);
+
+ /* Reset SuspendRequest */
+ hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE;
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_SUSPENDED;
+
+ return HAL_OK;
+ }
+
+ /* Enter input data in the Peripheral through HASH_Write_Block_Data() call and
+ check whether the digest calculation has been triggered */
+ if (HASH_Write_Block_Data(hhash) == HASH_DIGEST_CALCULATION_STARTED)
+ {
+ /* Call Input data transfer complete call back
+ (called at the end of each step for HMAC) */
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+ hhash->InCpltCallback(hhash);
+#else
+ HAL_HASH_InCpltCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+
+ if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1)
+ {
+ /* Wait until Peripheral is not busy anymore */
+ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
+ {
+ /* Disable Interrupts */
+ __HAL_HASH_DISABLE_IT(HASH_IT_DINI | HASH_IT_DCI);
+ return HAL_TIMEOUT;
+ }
+ /* Initialization start for HMAC STEP 2 */
+ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2; /* Move phase from Step 1 to Step 2 */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->HashBuffSize); /* Set NBLW for the input message */
+ hhash->HashInCount = hhash->HashBuffSize; /* Set the input data size (in bytes) */
+ hhash->pHashInBuffPtr = hhash->pHashMsgBuffPtr; /* Set the input data address */
+ hhash->HashITCounter = 1; /* Set ITCounter to 1 to indicate the start
+ of a new phase */
+ __HAL_HASH_ENABLE_IT(HASH_IT_DINI); /* Enable IT (was disabled in HASH_Write_Block_Data) */
+ }
+ else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
+ {
+ /* Wait until Peripheral is not busy anymore */
+ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
+ {
+ /* Disable Interrupts */
+ __HAL_HASH_DISABLE_IT(HASH_IT_DINI | HASH_IT_DCI);
+ return HAL_TIMEOUT;
+ }
+ /* Initialization start for HMAC STEP 3 */
+ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3; /* Move phase from Step 2 to Step 3 */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); /* Set NBLW for the key */
+ hhash->HashInCount = hhash->Init.KeySize; /* Set the key size (in bytes) */
+ hhash->pHashInBuffPtr = hhash->Init.pKey; /* Set the key address */
+ hhash->HashITCounter = 1; /* Set ITCounter to 1 to indicate the start
+ of a new phase */
+ __HAL_HASH_ENABLE_IT(HASH_IT_DINI); /* Enable IT (was disabled in HASH_Write_Block_Data) */
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ } /* if (HASH_Write_Block_Data(hhash) == HASH_DIGEST_CALCULATION_STARTED) */
+ } /* if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))*/
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+/**
+ * @brief Write a block of data in HASH Peripheral in interruption mode.
+ * @param hhash HASH handle.
+ * @note HASH_Write_Block_Data() is called under interruption by HASH_IT().
+ * @retval HAL status
+ */
+static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash)
+{
+ uint32_t inputaddr;
+ uint32_t buffercounter;
+ uint32_t inputcounter;
+ uint32_t ret = HASH_DIGEST_CALCULATION_NOT_STARTED;
+
+ /* If there are more than 64 bytes remaining to be entered */
+ if (hhash->HashInCount > 64U)
+ {
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+ /* Write the Input block in the Data IN register
+ (16 32-bit words, or 64 bytes are entered) */
+ for (buffercounter = 0U; buffercounter < 64U; buffercounter += 4U)
+ {
+ HASH->DIN = *(uint32_t *)inputaddr;
+ inputaddr += 4U;
+ }
+ /* If this is the start of input data entering, an additional word
+ must be entered to start up the HASH processing */
+ if (hhash->HashITCounter == 2U)
+ {
+ HASH->DIN = *(uint32_t *)inputaddr;
+ if (hhash->HashInCount >= 68U)
+ {
+ /* There are still data waiting to be entered in the Peripheral.
+ Decrement buffer counter and set pointer to the proper
+ memory location for the next data entering round. */
+ hhash->HashInCount -= 68U;
+ hhash->pHashInBuffPtr += 68U;
+ }
+ else
+ {
+ /* All the input buffer has been fed to the HW. */
+ hhash->HashInCount = 0U;
+ }
+ }
+ else
+ {
+ /* 64 bytes have been entered and there are still some remaining:
+ Decrement buffer counter and set pointer to the proper
+ memory location for the next data entering round.*/
+ hhash->HashInCount -= 64U;
+ hhash->pHashInBuffPtr += 64U;
+ }
+ }
+ else
+ {
+ /* 64 or less bytes remain to be entered. This is the last
+ data entering round. */
+
+ /* Get the buffer address */
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+ /* Get the buffer counter */
+ inputcounter = hhash->HashInCount;
+ /* Disable Interrupts */
+ __HAL_HASH_DISABLE_IT(HASH_IT_DINI);
+
+ /* Write the Input block in the Data IN register */
+ for (buffercounter = 0U; buffercounter < ((inputcounter + 3U) / 4U); buffercounter++)
+ {
+ HASH->DIN = *(uint32_t *)inputaddr;
+ inputaddr += 4U;
+ }
+
+ if (hhash->Accumulation == 1U)
+ {
+ /* Field accumulation is set, API only feeds data to the Peripheral and under interruption.
+ The digest computation will be started when the last buffer data are entered. */
+
+ /* Reset multi buffers accumulation flag */
+ hhash->Accumulation = 0U;
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+ /* Call Input data transfer complete call back */
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+ hhash->InCpltCallback(hhash);
+#else
+ HAL_HASH_InCpltCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Start the Digest calculation */
+ __HAL_HASH_START_DIGEST();
+ /* Return indication that digest calculation has started:
+ this return value triggers the call to Input data transfer
+ complete call back as well as the proper transition from
+ one step to another in HMAC mode. */
+ ret = HASH_DIGEST_CALCULATION_STARTED;
+ }
+ /* Reset buffer counter */
+ hhash->HashInCount = 0;
+ }
+
+ /* Return whether or digest calculation has started */
+ return ret;
+}
+
+/**
+ * @brief HMAC processing in polling mode.
+ * @param hhash HASH handle.
+ * @param Timeout Timeout value.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout)
+{
+ /* Ensure first that Phase is correct */
+ if ((hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_1) && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_2)
+ && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_3))
+ {
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Process Unlock */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+
+ /* HMAC Step 1 processing */
+ if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1)
+ {
+ /************************** STEP 1 ******************************************/
+ /* Configure the Number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+
+ /* Write input buffer in Data register */
+ hhash->Status = HASH_WriteData(hhash, hhash->pHashKeyBuffPtr, hhash->HashKeyCount);
+ if (hhash->Status != HAL_OK)
+ {
+ return hhash->Status;
+ }
+
+ /* Check whether or not key entering process has been suspended */
+ if (hhash->State == HAL_HASH_STATE_SUSPENDED)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Stop right there and return function status */
+ return HAL_OK;
+ }
+
+ /* No processing suspension at this point: set DCAL bit. */
+ __HAL_HASH_START_DIGEST();
+
+ /* Wait for BUSY flag to be cleared */
+ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Move from Step 1 to Step 2 */
+ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2;
+
+ }
+
+ /* HMAC Step 2 processing.
+ After phase check, HMAC_Processing() may
+ - directly start up from this point in resumption case
+ if the same Step 2 processing was suspended previously
+ - or fall through from the Step 1 processing carried out hereabove */
+ if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
+ {
+ /************************** STEP 2 ******************************************/
+ /* Configure the Number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->HashBuffSize);
+
+ /* Write input buffer in Data register */
+ hhash->Status = HASH_WriteData(hhash, hhash->pHashInBuffPtr, hhash->HashInCount);
+ if (hhash->Status != HAL_OK)
+ {
+ return hhash->Status;
+ }
+
+ /* Check whether or not data entering process has been suspended */
+ if (hhash->State == HAL_HASH_STATE_SUSPENDED)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Stop right there and return function status */
+ return HAL_OK;
+ }
+
+ /* No processing suspension at this point: set DCAL bit. */
+ __HAL_HASH_START_DIGEST();
+
+ /* Wait for BUSY flag to be cleared */
+ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Move from Step 2 to Step 3 */
+ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3;
+ /* In case Step 1 phase was suspended then resumed,
+ set again Key input buffers and size before moving to
+ next step */
+ hhash->pHashKeyBuffPtr = hhash->Init.pKey;
+ hhash->HashKeyCount = hhash->Init.KeySize;
+ }
+
+
+ /* HMAC Step 3 processing.
+ After phase check, HMAC_Processing() may
+ - directly start up from this point in resumption case
+ if the same Step 3 processing was suspended previously
+ - or fall through from the Step 2 processing carried out hereabove */
+ if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)
+ {
+ /************************** STEP 3 ******************************************/
+ /* Configure the Number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+
+ /* Write input buffer in Data register */
+ hhash->Status = HASH_WriteData(hhash, hhash->pHashKeyBuffPtr, hhash->HashKeyCount);
+ if (hhash->Status != HAL_OK)
+ {
+ return hhash->Status;
+ }
+
+ /* Check whether or not key entering process has been suspended */
+ if (hhash->State == HAL_HASH_STATE_SUSPENDED)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Stop right there and return function status */
+ return HAL_OK;
+ }
+
+ /* No processing suspension at this point: start the Digest calculation. */
+ __HAL_HASH_START_DIGEST();
+
+ /* Wait for DCIS flag to be set */
+ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Read the message digest */
+ HASH_GetDigest(hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH());
+
+ /* Reset HASH state machine */
+ hhash->Phase = HAL_HASH_PHASE_READY;
+ }
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Process Unlock */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Initialize the HASH peripheral, next process pInBuffer then
+ * read the computed digest.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest.
+ * @param Timeout Timeout value.
+ * @param Algorithm HASH algorithm.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout, uint32_t Algorithm)
+{
+ uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */
+ uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
+
+
+ /* Initiate HASH processing in case of start or resumption */
+ if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+ {
+ /* Check input parameters */
+ if ((pInBuffer == NULL) || (pOutBuffer == NULL))
+ {
+ hhash->State = HAL_HASH_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Check if initialization phase has not been already performed */
+ if (hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, Algorithm | HASH_CR_INIT);
+
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
+
+ /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as
+ input parameters of HASH_WriteData() */
+ pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */
+ Size_tmp = Size; /* Size_tmp contains the input data size in bytes */
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+ }
+ else if (hhash->Phase == HAL_HASH_PHASE_PROCESS)
+ {
+ /* if the Peripheral has already been initialized, two cases are possible */
+
+ /* Process resumption time ... */
+ if (hhash->State == HAL_HASH_STATE_SUSPENDED)
+ {
+ /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set
+ to the API input parameters but to those saved beforehand by HASH_WriteData()
+ when the processing was suspended */
+ pInBuffer_tmp = hhash->pHashInBuffPtr;
+ Size_tmp = hhash->HashInCount;
+ }
+ /* ... or multi-buffer HASH processing end */
+ else
+ {
+ /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as
+ input parameters of HASH_WriteData() */
+ pInBuffer_tmp = pInBuffer;
+ Size_tmp = Size;
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
+ }
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+ }
+ else
+ {
+ /* Phase error */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+
+
+ /* Write input buffer in Data register */
+ hhash->Status = HASH_WriteData(hhash, pInBuffer_tmp, Size_tmp);
+ if (hhash->Status != HAL_OK)
+ {
+ return hhash->Status;
+ }
+
+ /* If the process has not been suspended, carry on to digest calculation */
+ if (hhash->State != HAL_HASH_STATE_SUSPENDED)
+ {
+ /* Start the Digest calculation */
+ __HAL_HASH_START_DIGEST();
+
+ /* Wait for DCIS flag to be set */
+ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Read the message digest */
+ HASH_GetDigest(pOutBuffer, HASH_DIGEST_LENGTH());
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Reset HASH state machine */
+ hhash->Phase = HAL_HASH_PHASE_READY;
+
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+/**
+ * @brief If not already done, initialize the HASH peripheral then
+ * processes pInBuffer.
+ * @note Field hhash->Phase of HASH handle is tested to check whether or not
+ * the Peripheral has already been initialized.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes, must be a multiple of 4.
+ * @param Algorithm HASH algorithm.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
+{
+ uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */
+ uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
+
+ /* Make sure the input buffer size (in bytes) is a multiple of 4 */
+ if ((Size % 4U) != 0U)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Initiate HASH processing in case of start or resumption */
+ if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+ {
+ /* Check input parameters */
+ if ((pInBuffer == NULL) || (Size == 0U))
+ {
+ hhash->State = HAL_HASH_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* If resuming the HASH processing */
+ if (hhash->State == HAL_HASH_STATE_SUSPENDED)
+ {
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set
+ to the API input parameters but to those saved beforehand by HASH_WriteData()
+ when the processing was suspended */
+ pInBuffer_tmp = hhash->pHashInBuffPtr; /* pInBuffer_tmp is set to the input data address */
+ Size_tmp = hhash->HashInCount; /* Size_tmp contains the input data size in bytes */
+
+ }
+ else
+ {
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as
+ input parameters of HASH_WriteData() */
+ pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */
+ Size_tmp = Size; /* Size_tmp contains the input data size in bytes */
+
+ /* Check if initialization phase has already be performed */
+ if (hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, Algorithm | HASH_CR_INIT);
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ }
+
+ /* Write input buffer in Data register */
+ hhash->Status = HASH_WriteData(hhash, pInBuffer_tmp, Size_tmp);
+ if (hhash->Status != HAL_OK)
+ {
+ return hhash->Status;
+ }
+
+ /* If the process has not been suspended, move the state to Ready */
+ if (hhash->State != HAL_HASH_STATE_SUSPENDED)
+ {
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+
+
+}
+
+
+/**
+ * @brief If not already done, initialize the HASH peripheral then
+ * processes pInBuffer in interruption mode.
+ * @note Field hhash->Phase of HASH handle is tested to check whether or not
+ * the Peripheral has already been initialized.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes, must be a multiple of 4.
+ * @param Algorithm HASH algorithm.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
+{
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
+ __IO uint32_t inputaddr = (uint32_t) pInBuffer;
+ uint32_t SizeVar = Size;
+
+ /* Make sure the input buffer size (in bytes) is a multiple of 4 */
+ if ((Size % 4U) != 0U)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Initiate HASH processing in case of start or resumption */
+ if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+ {
+ /* Check input parameters */
+ if ((pInBuffer == NULL) || (Size == 0U))
+ {
+ hhash->State = HAL_HASH_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* If resuming the HASH processing */
+ if (hhash->State == HAL_HASH_STATE_SUSPENDED)
+ {
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+ }
+ else
+ {
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Check if initialization phase has already be performed */
+ if (hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, Algorithm | HASH_CR_INIT);
+ hhash->HashITCounter = 1;
+ }
+ else
+ {
+ hhash->HashITCounter = 3; /* 'cruise-speed' reached during a previous buffer processing */
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* If DINIS is equal to 0 (for example if an incomplete block has been previously
+ fed to the Peripheral), the DINIE interruption won't be triggered when DINIE is set.
+ Therefore, first words are manually entered until DINIS raises, or until there
+ is not more data to enter. */
+ while ((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) && (SizeVar > 0U))
+ {
+
+ /* Write input data 4 bytes at a time */
+ HASH->DIN = *(uint32_t *)inputaddr;
+ inputaddr += 4U;
+ SizeVar -= 4U;
+ }
+
+ /* If DINIS is still not set or if all the data have been fed, stop here */
+ if ((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) || (SizeVar == 0U))
+ {
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Process Unlock */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+
+ /* otherwise, carry on in interrupt-mode */
+ hhash->HashInCount = SizeVar; /* Counter used to keep track of number of data
+ to be fed to the Peripheral */
+ hhash->pHashInBuffPtr = (uint8_t *)inputaddr; /* Points at data which will be fed to the Peripheral at
+ the next interruption */
+ /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain
+ the information describing where the HASH process is stopped.
+ These variables are used later on to resume the HASH processing at the
+ correct location. */
+
+ }
+
+ /* Set multi buffers accumulation flag */
+ hhash->Accumulation = 1U;
+
+ /* Process Unlock */
+ __HAL_UNLOCK(hhash);
+
+ /* Enable Data Input interrupt */
+ __HAL_HASH_ENABLE_IT(HASH_IT_DINI);
+
+ /* Return function status */
+ return HAL_OK;
+
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+
+}
+
+
+
+/**
+ * @brief Initialize the HASH peripheral, next process pInBuffer then
+ * read the computed digest in interruption mode.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest.
+ * @param Algorithm HASH algorithm.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Algorithm)
+{
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
+ __IO uint32_t inputaddr = (uint32_t) pInBuffer;
+ uint32_t polling_step = 0U;
+ uint32_t initialization_skipped = 0U;
+ uint32_t SizeVar = Size;
+
+ /* If State is ready or suspended, start or resume IT-based HASH processing */
+ if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+ {
+ /* Check input parameters */
+ if ((pInBuffer == NULL) || (Size == 0U) || (pOutBuffer == NULL))
+ {
+ hhash->State = HAL_HASH_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Initialize IT counter */
+ hhash->HashITCounter = 1;
+
+ /* Check if initialization phase has already be performed */
+ if (hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, Algorithm | HASH_CR_INIT);
+
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(SizeVar);
+
+
+ hhash->HashInCount = SizeVar; /* Counter used to keep track of number of data
+ to be fed to the Peripheral */
+ hhash->pHashInBuffPtr = pInBuffer; /* Points at data which will be fed to the Peripheral at
+ the next interruption */
+ /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain
+ the information describing where the HASH process is stopped.
+ These variables are used later on to resume the HASH processing at the
+ correct location. */
+
+ hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */
+ }
+ else
+ {
+ initialization_skipped = 1; /* info user later on in case of multi-buffer */
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* If DINIS is equal to 0 (for example if an incomplete block has been previously
+ fed to the Peripheral), the DINIE interruption won't be triggered when DINIE is set.
+ Therefore, first words are manually entered until DINIS raises. */
+ while ((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) && (SizeVar > 3U))
+ {
+ polling_step = 1U; /* note that some words are entered before enabling the interrupt */
+
+ /* Write input data 4 bytes at a time */
+ HASH->DIN = *(uint32_t *)inputaddr;
+ inputaddr += 4U;
+ SizeVar -= 4U;
+ }
+
+ if (polling_step == 1U)
+ {
+ if (SizeVar == 0U)
+ {
+ /* If all the data have been entered at this point, it only remains to
+ read the digest */
+ hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */
+
+ /* Start the Digest calculation */
+ __HAL_HASH_START_DIGEST();
+ /* Process Unlock */
+ __HAL_UNLOCK(hhash);
+
+ /* Enable Interrupts */
+ __HAL_HASH_ENABLE_IT(HASH_IT_DCI);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
+ {
+ /* It remains data to enter and the Peripheral is ready to trigger DINIE,
+ carry on as usual.
+ Update HashInCount and pHashInBuffPtr accordingly. */
+ hhash->HashInCount = SizeVar;
+ hhash->pHashInBuffPtr = (uint8_t *)inputaddr;
+ __HAL_HASH_SET_NBVALIDBITS(
+ SizeVar); /* Update the configuration of the number of valid bits in last word of the message */
+ hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */
+ if (initialization_skipped == 1U)
+ {
+ hhash->HashITCounter = 3; /* 'cruise-speed' reached during a previous buffer processing */
+ }
+ }
+ else
+ {
+ /* DINIS is not set but it remains a few data to enter (not enough for a full word).
+ Manually enter the last bytes before enabling DCIE. */
+ __HAL_HASH_SET_NBVALIDBITS(SizeVar);
+ HASH->DIN = *(uint32_t *)inputaddr;
+
+ /* Start the Digest calculation */
+ hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */
+ __HAL_HASH_START_DIGEST();
+ /* Process Unlock */
+ __HAL_UNLOCK(hhash);
+
+ /* Enable Interrupts */
+ __HAL_HASH_ENABLE_IT(HASH_IT_DCI);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ } /* if (polling_step == 1) */
+
+
+ /* Process Unlock */
+ __HAL_UNLOCK(hhash);
+
+ /* Enable Interrupts */
+ __HAL_HASH_ENABLE_IT(HASH_IT_DINI | HASH_IT_DCI);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+
+}
+
+
+/**
+ * @brief Initialize the HASH peripheral then initiate a DMA transfer
+ * to feed the input buffer to the Peripheral.
+ * @note If MDMAT bit is set before calling this function (multi-buffer
+ * HASH processing case), the input buffer size (in bytes) must be
+ * a multiple of 4 otherwise, the HASH digest computation is corrupted.
+ * For the processing of the last buffer of the thread, MDMAT bit must
+ * be reset and the buffer length (in bytes) doesn't have to be a
+ * multiple of 4.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param Algorithm HASH algorithm.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
+{
+ uint32_t inputaddr;
+ uint32_t inputSize;
+ HAL_StatusTypeDef status ;
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
+
+
+ /* Make sure the input buffer size (in bytes) is a multiple of 4 when MDMAT bit is set
+ (case of multi-buffer HASH processing) */
+ assert_param(IS_HASH_DMA_MULTIBUFFER_SIZE(Size));
+
+ /* If State is ready or suspended, start or resume polling-based HASH processing */
+ if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+ {
+ /* Check input parameters */
+ if ((pInBuffer == NULL) || (Size == 0U) ||
+ /* Check phase coherency. Phase must be
+ either READY (fresh start)
+ or PROCESS (multi-buffer HASH management) */
+ ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HASH_PROCESSING(hhash)))))
+ {
+ hhash->State = HAL_HASH_STATE_READY;
+ return HAL_ERROR;
+ }
+
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* If not a resumption case */
+ if (hhash->State == HAL_HASH_STATE_READY)
+ {
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed.
+ If Phase is already set to HAL_HASH_PHASE_PROCESS, this means the
+ API is processing a new input data message in case of multi-buffer HASH
+ computation. */
+ if (hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, Algorithm | HASH_CR_INIT);
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+ }
+
+ /* Configure the Number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
+
+ inputaddr = (uint32_t)pInBuffer; /* DMA transfer start address */
+ inputSize = Size; /* DMA transfer size (in bytes) */
+
+ /* In case of suspension request, save the starting parameters */
+ hhash->pHashInBuffPtr = pInBuffer; /* DMA transfer start address */
+ hhash->HashInCount = Size; /* DMA transfer size (in bytes) */
+
+ }
+ /* If resumption case */
+ else
+ {
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Resumption case, inputaddr and inputSize are not set to the API input parameters
+ but to those saved beforehand by HAL_HASH_DMAFeed_ProcessSuspend() when the
+ processing was suspended */
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr; /* DMA transfer start address */
+ inputSize = hhash->HashInCount; /* DMA transfer size (in bytes) */
+
+ }
+
+ /* Set the HASH DMA transfer complete callback */
+ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
+ /* Set the DMA error callback */
+ hhash->hdmain->XferErrorCallback = HASH_DMAError;
+
+ /* Store number of words already pushed to manage proper DMA processing suspension */
+ hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED();
+
+ /* Enable the DMA In DMA channel */
+ if ((hhash->hdmain->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if ((hhash->hdmain->LinkedListQueue != NULL) && (hhash->hdmain->LinkedListQueue->Head != NULL))
+ {
+ /* Enable the DMA channel */
+ hhash->hdmain->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET]\
+ = (((inputSize % 4U) != 0U) ? (inputSize + (4U - (inputSize % 4U))) : (inputSize)); /* Set DMA data size */
+ hhash->hdmain->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET]\
+ = inputaddr; /* Set DMA source address */
+ hhash->hdmain->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET]\
+ = (uint32_t)&HASH->DIN; /* Set DMA destination address */
+
+ status = HAL_DMAEx_List_Start_IT(hhash->hdmain);
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, \
+ (((inputSize % 4U) != 0U) ? (inputSize + (4U - (inputSize % 4U))) : (inputSize)));
+ }
+
+ if (status != HAL_OK)
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Enable DMA requests */
+ SET_BIT(HASH->CR, HASH_CR_DMAE);
+
+ /* Process Unlock */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ if (status != HAL_OK)
+ {
+ /* Update HASH state machine to error */
+ hhash->State = HAL_HASH_STATE_ERROR;
+ }
+
+ return status;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Return the computed digest.
+ * @note The API waits for DCIS to be set then reads the computed digest.
+ * @param hhash HASH handle.
+ * @param pOutBuffer pointer to the computed digest.
+ * @param Timeout Timeout value.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
+{
+
+ if (hhash->State == HAL_HASH_STATE_READY)
+ {
+ /* Check parameter */
+ if (pOutBuffer == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state to busy */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Wait for DCIS flag to be set */
+ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Read the message digest */
+ HASH_GetDigest(pOutBuffer, HASH_DIGEST_LENGTH());
+
+ /* Change the HASH state to ready */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Reset HASH state machine */
+ hhash->Phase = HAL_HASH_PHASE_READY;
+
+ /* Process UnLock */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+
+}
+
+
+/**
+ * @brief Initialize the HASH peripheral in HMAC mode, next process pInBuffer then
+ * read the computed digest.
+ * @note Digest is available in pOutBuffer.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest.
+ * @param Timeout Timeout value.
+ * @param Algorithm HASH algorithm.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout, uint32_t Algorithm)
+{
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
+
+ /* If State is ready or suspended, start or resume polling-based HASH processing */
+ if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+ {
+ /* Check input parameters */
+ if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U)
+ || (pOutBuffer == NULL))
+ {
+ hhash->State = HAL_HASH_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Check if initialization phase has already be performed */
+ if (hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */
+ if (hhash->Init.KeySize > 64U)
+ {
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT,
+ Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
+ }
+ else
+ {
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT,
+ Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+ }
+ /* Set the phase to Step 1 */
+ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
+ /* Resort to hhash internal fields to feed the Peripheral.
+ Parameters will be updated in case of suspension to contain the proper
+ information at resumption time. */
+ hhash->pHashOutBuffPtr = pOutBuffer; /* Output digest address */
+ hhash->pHashInBuffPtr = pInBuffer; /* Input data address, HMAC_Processing input
+ parameter for Step 2 */
+ hhash->HashInCount = Size; /* Input data size, HMAC_Processing input
+ parameter for Step 2 */
+ hhash->HashBuffSize = Size; /* Store the input buffer size for the whole HMAC process*/
+ hhash->pHashKeyBuffPtr = hhash->Init.pKey; /* Key address, HMAC_Processing input parameter for Step
+ 1 and Step 3 */
+ hhash->HashKeyCount = hhash->Init.KeySize; /* Key size, HMAC_Processing input parameter for Step 1
+ and Step 3 */
+ }
+
+ /* Carry out HMAC processing */
+ return HMAC_Processing(hhash, Timeout);
+
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+
+/**
+ * @brief Initialize the HASH peripheral in HMAC mode, next process pInBuffer then
+ * read the computed digest in interruption mode.
+ * @note Digest is available in pOutBuffer.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest.
+ * @param Algorithm HASH algorithm.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Algorithm)
+{
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
+
+ /* If State is ready or suspended, start or resume IT-based HASH processing */
+ if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+ {
+ /* Check input parameters */
+ if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U)
+ || (pOutBuffer == NULL))
+ {
+ hhash->State = HAL_HASH_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Initialize IT counter */
+ hhash->HashITCounter = 1;
+
+ /* Check if initialization phase has already be performed */
+ if (hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */
+ if (hhash->Init.KeySize > 64U)
+ {
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT,
+ Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
+ }
+ else
+ {
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT,
+ Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+ }
+
+ /* Resort to hhash internal fields hhash->pHashInBuffPtr and hhash->HashInCount
+ to feed the Peripheral whatever the HMAC step.
+ Lines below are set to start HMAC Step 1 processing where key is entered first. */
+ hhash->HashInCount = hhash->Init.KeySize; /* Key size */
+ hhash->pHashInBuffPtr = hhash->Init.pKey ; /* Key address */
+
+ /* Store input and output parameters in handle fields to manage steps transition
+ or possible HMAC suspension/resumption */
+ hhash->pHashKeyBuffPtr = hhash->Init.pKey; /* Key address */
+ hhash->pHashMsgBuffPtr = pInBuffer; /* Input message address */
+ hhash->HashBuffSize = Size; /* Input message size (in bytes) */
+ hhash->pHashOutBuffPtr = pOutBuffer; /* Output digest address */
+
+ /* Configure the number of valid bits in last word of the key */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+
+ /* Set the phase to Step 1 */
+ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
+ }
+ else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
+ {
+ /* Restart IT-based HASH processing after Step 1 or Step 3 suspension */
+
+ }
+ else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
+ {
+ /* Restart IT-based HASH processing after Step 2 suspension */
+
+ }
+ else
+ {
+ /* Error report as phase incorrect */
+ /* Process Unlock */
+ __HAL_UNLOCK(hhash);
+ hhash->State = HAL_HASH_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Process Unlock */
+ __HAL_UNLOCK(hhash);
+
+ /* Enable Interrupts */
+ __HAL_HASH_ENABLE_IT(HASH_IT_DINI | HASH_IT_DCI);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+
+}
+
+
+
+/**
+ * @brief Initialize the HASH peripheral in HMAC mode then initiate the required
+ * DMA transfers to feed the key and the input buffer to the Peripheral.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note In case of multi-buffer HMAC processing, the input buffer size (in bytes) must
+ * be a multiple of 4 otherwise, the HASH digest computation is corrupted.
+ * Only the length of the last buffer of the thread doesn't have to be a
+ * multiple of 4.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param Algorithm HASH algorithm.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
+{
+ uint32_t inputaddr;
+ uint32_t inputSize;
+ HAL_StatusTypeDef status ;
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
+ /* Make sure the input buffer size (in bytes) is a multiple of 4 when digest calculation
+ is disabled (multi-buffer HMAC processing, MDMAT bit to be set) */
+ assert_param(IS_HMAC_DMA_MULTIBUFFER_SIZE(hhash, Size));
+ /* If State is ready or suspended, start or resume DMA-based HASH processing */
+ if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+ {
+ /* Check input parameters */
+ if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) ||
+ /* Check phase coherency. Phase must be
+ either READY (fresh start)
+ or one of HMAC PROCESS steps (multi-buffer HASH management) */
+ ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HMAC_PROCESSING(hhash)))))
+ {
+ hhash->State = HAL_HASH_STATE_READY;
+ return HAL_ERROR;
+ }
+
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* If not a case of resumption after suspension */
+ if (hhash->State == HAL_HASH_STATE_READY)
+ {
+ /* Check whether or not initialization phase has already be performed */
+ if (hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+ /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits.
+ At the same time, ensure MDMAT bit is cleared. */
+ if (hhash->Init.KeySize > 64U)
+ {
+ MODIFY_REG(HASH->CR, HASH_CR_MDMAT | HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT,
+ Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
+ }
+ else
+ {
+ MODIFY_REG(HASH->CR, HASH_CR_MDMAT | HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT,
+ Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+ }
+ /* Store input aparameters in handle fields to manage steps transition
+ or possible HMAC suspension/resumption */
+ hhash->HashInCount = hhash->Init.KeySize; /* Initial size for first DMA transfer (key size) */
+ hhash->pHashKeyBuffPtr = hhash->Init.pKey; /* Key address */
+ hhash->pHashInBuffPtr = hhash->Init.pKey ; /* First address passed to DMA (key address at Step 1) */
+ hhash->pHashMsgBuffPtr = pInBuffer; /* Input data address */
+ hhash->HashBuffSize = Size; /* input data size (in bytes) */
+
+ /* Set DMA input parameters */
+ inputaddr = (uint32_t)(hhash->Init.pKey); /* Address passed to DMA (start by entering Key message) */
+ inputSize = hhash->Init.KeySize; /* Size for first DMA transfer (in bytes) */
+
+ /* Configure the number of valid bits in last word of the key */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+
+ /* Set the phase to Step 1 */
+ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
+
+ }
+ else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
+ {
+ /* Process a new input data message in case of multi-buffer HMAC processing
+ (this is not a resumption case) */
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Save input parameters to be able to manage possible suspension/resumption */
+ hhash->HashInCount = Size; /* Input message address */
+ hhash->pHashInBuffPtr = pInBuffer; /* Input message size in bytes */
+
+ /* Set DMA input parameters */
+ inputaddr = (uint32_t)pInBuffer; /* Input message address */
+ inputSize = Size; /* Input message size in bytes */
+
+ if (hhash->DigestCalculationDisable == RESET)
+ {
+ /* This means this is the last buffer of the multi-buffer sequence: DCAL needs to be set. */
+ __HAL_HASH_RESET_MDMAT();
+ __HAL_HASH_SET_NBVALIDBITS(inputSize);
+ }
+ }
+ else
+ {
+ /* Phase not aligned with handle READY state */
+ __HAL_UNLOCK(hhash);
+ /* Return function status */
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Resumption case (phase may be Step 1, 2 or 3) */
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Set DMA input parameters at resumption location;
+ inputaddr and inputSize are not set to the API input parameters
+ but to those saved beforehand by HAL_HASH_DMAFeed_ProcessSuspend() when the
+ processing was suspended. */
+ inputaddr = (uint32_t)(hhash->pHashInBuffPtr); /* Input message address */
+ inputSize = hhash->HashInCount; /* Input message size in bytes */
+ }
+
+
+ /* Set the HASH DMA transfer complete callback */
+ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
+ /* Set the DMA error callback */
+ hhash->hdmain->XferErrorCallback = HASH_DMAError;
+
+ /* Store number of words already pushed to manage proper DMA processing suspension */
+ hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED();
+
+ /* Enable the DMA In DMA channel */
+ if ((hhash->hdmain->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if ((hhash->hdmain->LinkedListQueue != NULL) && (hhash->hdmain->LinkedListQueue->Head != NULL))
+ {
+ /* Enable the DMA channel */
+ hhash->hdmain->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET]\
+ = (((inputSize % 4U) != 0U) ? (inputSize + (4U - (inputSize % 4U))) : (inputSize)); /* Set DMA data size */
+ hhash->hdmain->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET]\
+ = inputaddr; /* Set DMA source address */
+ hhash->hdmain->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET]\
+ = (uint32_t)&HASH->DIN; /* Set DMA destination address */
+
+ status = HAL_DMAEx_List_Start_IT(hhash->hdmain);
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, \
+ (((inputSize % 4U) != 0U) ? (inputSize + (4U - (inputSize % 4U))) : (inputSize)));
+ }
+
+ if (status != HAL_OK)
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ /* Enable DMA requests */
+ SET_BIT(HASH->CR, HASH_CR_DMAE);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ if (status != HAL_OK)
+ {
+ /* Update HASH state machine to error */
+ hhash->State = HAL_HASH_STATE_ERROR;
+ }
+
+ /* Return function status */
+ return status;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @}
+ */
+
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+#endif /* HASH*/
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hash_ex.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hash_ex.c
new file mode 100644
index 00000000..8215c154
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hash_ex.c
@@ -0,0 +1,1039 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_hash_ex.c
+ * @author MCD Application Team
+ * @brief Extended HASH HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the HASH peripheral for SHA-224 and SHA-256
+ * algorithms:
+ * + HASH or HMAC processing in polling mode
+ * + HASH or HMAC processing in interrupt mode
+ * + HASH or HMAC processing in DMA mode
+ * Additionally, this file provides functions to manage HMAC
+ * multi-buffer DMA-based processing for MD-5, SHA-1, SHA-224
+ * and SHA-256.
+ *
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ===============================================================================
+ ##### HASH peripheral extended features #####
+ ===============================================================================
+ [..]
+ The SHA-224 and SHA-256 HASH and HMAC processing can be carried out exactly
+ the same way as for SHA-1 or MD-5 algorithms.
+ (#) Three modes are available.
+ (##) Polling mode: processing APIs are blocking functions
+ i.e. they process the data and wait till the digest computation is finished,
+ e.g. HAL_HASHEx_xxx_Start()
+ (##) Interrupt mode: processing APIs are not blocking functions
+ i.e. they process the data under interrupt,
+ e.g. HAL_HASHEx_xxx_Start_IT()
+ (##) DMA mode: processing APIs are not blocking functions and the CPU is
+ not used for data transfer i.e. the data transfer is ensured by DMA,
+ e.g. HAL_HASHEx_xxx_Start_DMA(). Note that in DMA mode, a call to
+ HAL_HASHEx_xxx_Finish() is then required to retrieve the digest.
+
+ (#)Multi-buffer processing is possible in polling, interrupt and DMA modes.
+ (##) In polling mode, only multi-buffer HASH processing is possible.
+ API HAL_HASHEx_xxx_Accumulate() must be called for each input buffer, except for the last one.
+ User must resort to HAL_HASHEx_xxx_Accumulate_End() to enter the last one and retrieve as
+ well the computed digest.
+
+ (##) In interrupt mode, API HAL_HASHEx_xxx_Accumulate_IT() must be called for each input buffer,
+ except for the last one.
+ User must resort to HAL_HASHEx_xxx_Accumulate_End_IT() to enter the last one and retrieve as
+ well the computed digest.
+
+ (##) In DMA mode, multi-buffer HASH and HMAC processing are possible.
+
+ (+++) HASH processing: once initialization is done, MDMAT bit must be set through
+ __HAL_HASH_SET_MDMAT() macro.
+ From that point, each buffer can be fed to the Peripheral through HAL_HASHEx_xxx_Start_DMA() API.
+ Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
+ macro then wrap-up the HASH processing in feeding the last input buffer through the
+ same API HAL_HASHEx_xxx_Start_DMA(). The digest can then be retrieved with a call to
+ API HAL_HASHEx_xxx_Finish().
+
+ (+++) HMAC processing (MD-5, SHA-1, SHA-224 and SHA-256 must all resort to
+ extended functions): after initialization, the key and the first input buffer are entered
+ in the Peripheral with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
+ starts step 2.
+ The following buffers are next entered with the API HAL_HMACEx_xxx_Step2_DMA(). At this
+ point, the HMAC processing is still carrying out step 2.
+ Then, step 2 for the last input buffer and step 3 are carried out by a single call
+ to HAL_HMACEx_xxx_Step2_3_DMA().
+
+ The digest can finally be retrieved with a call to API HAL_HASH_xxx_Finish() for
+ MD-5 and SHA-1, to HAL_HASHEx_xxx_Finish() for SHA-224 and SHA-256.
+
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+
+
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+#if defined (HASH)
+
+/** @defgroup HASHEx HASHEx
+ * @brief HASH HAL extended module driver.
+ * @{
+ */
+#ifdef HAL_HASH_MODULE_ENABLED
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+
+/** @defgroup HASHEx_Exported_Functions HASH Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode
+ * @brief HASH extended processing functions using polling mode.
+ *
+@verbatim
+ ===============================================================================
+ ##### Polling mode HASH extended processing functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in polling mode
+ the hash value using one of the following algorithms:
+ (+) SHA224
+ (++) HAL_HASHEx_SHA224_Start()
+ (++) HAL_HASHEx_SHA224_Accmlt()
+ (++) HAL_HASHEx_SHA224_Accmlt_End()
+ (+) SHA256
+ (++) HAL_HASHEx_SHA256_Start()
+ (++) HAL_HASHEx_SHA256_Accmlt()
+ (++) HAL_HASHEx_SHA256_Accmlt_End()
+
+ [..] For a single buffer to be hashed, user can resort to HAL_HASH_xxx_Start().
+
+ [..] In case of multi-buffer HASH processing (a single digest is computed while
+ several buffers are fed to the Peripheral), the user can resort to successive calls
+ to HAL_HASHEx_xxx_Accumulate() and wrap-up the digest computation by a call
+ to HAL_HASHEx_xxx_Accumulate_End().
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then
+ * read the computed digest.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
+ * @param Timeout Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout)
+{
+ return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
+}
+
+/**
+ * @brief If not already done, initialize the HASH peripheral in SHA224 mode then
+ * processes pInBuffer.
+ * @note Consecutive calls to HAL_HASHEx_SHA224_Accmlt() can be used to feed
+ * several input buffers back-to-back to the Peripheral that will yield a single
+ * HASH signature once all buffers have been entered. Wrap-up of input
+ * buffers feeding and retrieval of digest is done by a call to
+ * HAL_HASHEx_SHA224_Accmlt_End().
+ * @note Field hhash->Phase of HASH handle is tested to check whether or not
+ * the Peripheral has already been initialized.
+ * @note Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA224_Accmlt_End()
+ * to read it, feeding at the same time the last input buffer to the Peripheral.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted. Only HAL_HASHEx_SHA224_Accmlt_End() is able
+ * to manage the ending buffer with a length in bytes not a multiple of 4.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes, must be a multiple of 4.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
+}
+
+/**
+ * @brief End computation of a single HASH signature after several calls to HAL_HASHEx_SHA224_Accmlt() API.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
+ * @param Timeout Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout)
+{
+ return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
+}
+
+/**
+ * @brief Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then
+ * read the computed digest.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
+ * @param Timeout Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout)
+{
+ return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
+}
+
+/**
+ * @brief If not already done, initialize the HASH peripheral in SHA256 mode then
+ * processes pInBuffer.
+ * @note Consecutive calls to HAL_HASHEx_SHA256_Accmlt() can be used to feed
+ * several input buffers back-to-back to the Peripheral that will yield a single
+ * HASH signature once all buffers have been entered. Wrap-up of input
+ * buffers feeding and retrieval of digest is done by a call to
+ * HAL_HASHEx_SHA256_Accmlt_End().
+ * @note Field hhash->Phase of HASH handle is tested to check whether or not
+ * the Peripheral has already been initialized.
+ * @note Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA256_Accmlt_End()
+ * to read it, feeding at the same time the last input buffer to the Peripheral.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted. Only HAL_HASHEx_SHA256_Accmlt_End() is able
+ * to manage the ending buffer with a length in bytes not a multiple of 4.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes, must be a multiple of 4.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
+}
+
+/**
+ * @brief End computation of a single HASH signature after several calls to HAL_HASHEx_SHA256_Accmlt() API.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
+ * @param Timeout Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout)
+{
+ return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode
+ * @brief HASH extended processing functions using interrupt mode.
+ *
+@verbatim
+ ===============================================================================
+ ##### Interruption mode HASH extended processing functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in interrupt mode
+ the hash value using one of the following algorithms:
+ (+) SHA224
+ (++) HAL_HASHEx_SHA224_Start_IT()
+ (++) HAL_HASHEx_SHA224_Accmlt_IT()
+ (++) HAL_HASHEx_SHA224_Accmlt_End_IT()
+ (+) SHA256
+ (++) HAL_HASHEx_SHA256_Start_IT()
+ (++) HAL_HASHEx_SHA256_Accmlt_IT()
+ (++) HAL_HASHEx_SHA256_Accmlt_End_IT()
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then
+ * read the computed digest in interruption mode.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer)
+{
+ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224);
+}
+
+/**
+ * @brief If not already done, initialize the HASH peripheral in SHA224 mode then
+ * processes pInBuffer in interruption mode.
+ * @note Consecutive calls to HAL_HASHEx_SHA224_Accmlt_IT() can be used to feed
+ * several input buffers back-to-back to the Peripheral that will yield a single
+ * HASH signature once all buffers have been entered. Wrap-up of input
+ * buffers feeding and retrieval of digest is done by a call to
+ * HAL_HASHEx_SHA224_Accmlt_End_IT().
+ * @note Field hhash->Phase of HASH handle is tested to check whether or not
+ * the Peripheral has already been initialized.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted. Only HAL_HASHEx_SHA224_Accmlt_End_IT() is able
+ * to manage the ending buffer with a length in bytes not a multiple of 4.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes, must be a multiple of 4.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
+}
+
+/**
+ * @brief End computation of a single HASH signature after several calls to HAL_HASHEx_SHA224_Accmlt_IT() API.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer)
+{
+ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224);
+}
+
+/**
+ * @brief Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then
+ * read the computed digest in interruption mode.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer)
+{
+ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256);
+}
+
+/**
+ * @brief If not already done, initialize the HASH peripheral in SHA256 mode then
+ * processes pInBuffer in interruption mode.
+ * @note Consecutive calls to HAL_HASHEx_SHA256_Accmlt_IT() can be used to feed
+ * several input buffers back-to-back to the Peripheral that will yield a single
+ * HASH signature once all buffers have been entered. Wrap-up of input
+ * buffers feeding and retrieval of digest is done by a call to
+ * HAL_HASHEx_SHA256_Accmlt_End_IT().
+ * @note Field hhash->Phase of HASH handle is tested to check whether or not
+ * the Peripheral has already been initialized.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted. Only HAL_HASHEx_SHA256_Accmlt_End_IT() is able
+ * to manage the ending buffer with a length in bytes not a multiple of 4.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes, must be a multiple of 4.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
+}
+
+/**
+ * @brief End computation of a single HASH signature after several calls to HAL_HASHEx_SHA256_Accmlt_IT() API.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer)
+{
+ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode
+ * @brief HASH extended processing functions using DMA mode.
+ *
+@verbatim
+ ===============================================================================
+ ##### DMA mode HASH extended processing functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in DMA mode
+ the hash value using one of the following algorithms:
+ (+) SHA224
+ (++) HAL_HASHEx_SHA224_Start_DMA()
+ (++) HAL_HASHEx_SHA224_Finish()
+ (+) SHA256
+ (++) HAL_HASHEx_SHA256_Start_DMA()
+ (++) HAL_HASHEx_SHA256_Finish()
+
+ [..] When resorting to DMA mode to enter the data in the Peripheral, user must resort
+ to HAL_HASHEx_xxx_Start_DMA() then read the resulting digest with
+ HAL_HASHEx_xxx_Finish().
+
+ [..] In case of multi-buffer HASH processing, MDMAT bit must first be set before
+ the successive calls to HAL_HASHEx_xxx_Start_DMA(). Then, MDMAT bit needs to be
+ reset before the last call to HAL_HASHEx_xxx_Start_DMA(). Digest is finally
+ retrieved thanks to HAL_HASHEx_xxx_Finish().
+
+@endverbatim
+ * @{
+ */
+
+
+
+
+/**
+ * @brief Initialize the HASH peripheral in SHA224 mode then initiate a DMA transfer
+ * to feed the input buffer to the Peripheral.
+ * @note Once the DMA transfer is finished, HAL_HASHEx_SHA224_Finish() API must
+ * be called to retrieve the computed digest.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
+}
+
+/**
+ * @brief Return the computed digest in SHA224 mode.
+ * @note The API waits for DCIS to be set then reads the computed digest.
+ * @note HAL_HASHEx_SHA224_Finish() can be used as well to retrieve the digest in
+ * HMAC SHA224 mode.
+ * @param hhash HASH handle.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
+ * @param Timeout Timeout value.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
+{
+ return HASH_Finish(hhash, pOutBuffer, Timeout);
+}
+
+/**
+ * @brief Initialize the HASH peripheral in SHA256 mode then initiate a DMA transfer
+ * to feed the input buffer to the Peripheral.
+ * @note Once the DMA transfer is finished, HAL_HASHEx_SHA256_Finish() API must
+ * be called to retrieve the computed digest.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
+}
+
+/**
+ * @brief Return the computed digest in SHA256 mode.
+ * @note The API waits for DCIS to be set then reads the computed digest.
+ * @note HAL_HASHEx_SHA256_Finish() can be used as well to retrieve the digest in
+ * HMAC SHA256 mode.
+ * @param hhash HASH handle.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
+ * @param Timeout Timeout value.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
+{
+ return HASH_Finish(hhash, pOutBuffer, Timeout);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode
+ * @brief HMAC extended processing functions using polling mode.
+ *
+@verbatim
+ ===============================================================================
+ ##### Polling mode HMAC extended processing functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in polling mode
+ the HMAC value using one of the following algorithms:
+ (+) SHA224
+ (++) HAL_HMACEx_SHA224_Start()
+ (+) SHA256
+ (++) HAL_HMACEx_SHA256_Start()
+
+@endverbatim
+ * @{
+ */
+
+
+
+/**
+ * @brief Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then
+ * read the computed digest.
+ * @note Digest is available in pOutBuffer.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
+ * @param Timeout Timeout value.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout)
+{
+ return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
+}
+
+/**
+ * @brief Initialize the HASH peripheral in HMAC SHA256 mode, next process pInBuffer then
+ * read the computed digest.
+ * @note Digest is available in pOutBuffer.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
+ * @param Timeout Timeout value.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout)
+{
+ return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode
+ * @brief HMAC extended processing functions using interruption mode.
+ *
+@verbatim
+ ===============================================================================
+ ##### Interrupt mode HMAC extended processing functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in interrupt mode
+ the HMAC value using one of the following algorithms:
+ (+) SHA224
+ (++) HAL_HMACEx_SHA224_Start_IT()
+ (+) SHA256
+ (++) HAL_HMACEx_SHA256_Start_IT()
+
+@endverbatim
+ * @{
+ */
+
+
+
+/**
+ * @brief Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then
+ * read the computed digest in interrupt mode.
+ * @note Digest is available in pOutBuffer.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer)
+{
+ return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224);
+}
+
+/**
+ * @brief Initialize the HASH peripheral in HMAC SHA256 mode, next process pInBuffer then
+ * read the computed digest in interrupt mode.
+ * @note Digest is available in pOutBuffer.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer)
+{
+ return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256);
+}
+
+
+
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode
+ * @brief HMAC extended processing functions using DMA mode.
+ *
+@verbatim
+ ===============================================================================
+ ##### DMA mode HMAC extended processing functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in DMA mode
+ the HMAC value using one of the following algorithms:
+ (+) SHA224
+ (++) HAL_HMACEx_SHA224_Start_DMA()
+ (+) SHA256
+ (++) HAL_HMACEx_SHA256_Start_DMA()
+
+ [..] When resorting to DMA mode to enter the data in the Peripheral for HMAC processing,
+ user must resort to HAL_HMACEx_xxx_Start_DMA() then read the resulting digest
+ with HAL_HASHEx_xxx_Finish().
+
+
+@endverbatim
+ * @{
+ */
+
+
+
+/**
+ * @brief Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required
+ * DMA transfers to feed the key and the input buffer to the Peripheral.
+ * @note Once the DMA transfers are finished (indicated by hhash->State set back
+ * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA224_Finish() API must be called to retrieve
+ * the computed digest.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note If MDMAT bit is set before calling this function (multi-buffer
+ * HASH processing case), the input buffer size (in bytes) must be
+ * a multiple of 4 otherwise, the HASH digest computation is corrupted.
+ * For the processing of the last buffer of the thread, MDMAT bit must
+ * be reset and the buffer length (in bytes) doesn't have to be a
+ * multiple of 4.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
+}
+
+/**
+ * @brief Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required
+ * DMA transfers to feed the key and the input buffer to the Peripheral.
+ * @note Once the DMA transfers are finished (indicated by hhash->State set back
+ * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
+ * the computed digest.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note If MDMAT bit is set before calling this function (multi-buffer
+ * HASH processing case), the input buffer size (in bytes) must be
+ * a multiple of 4 otherwise, the HASH digest computation is corrupted.
+ * For the processing of the last buffer of the thread, MDMAT bit must
+ * be reset and the buffer length (in bytes) doesn't have to be a
+ * multiple of 4.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup HASHEx_Exported_Functions_Group7 Multi-buffer HMAC extended processing functions in DMA mode
+ * @brief HMAC extended processing functions in multi-buffer DMA mode.
+ *
+@verbatim
+ ===============================================================================
+ ##### Multi-buffer DMA mode HMAC extended processing functions #####
+ ===============================================================================
+ [..] This section provides functions to manage HMAC multi-buffer
+ DMA-based processing for MD5, SHA1, SHA224 and SHA256 algorithms.
+ (+) MD5
+ (++) HAL_HMACEx_MD5_Step1_2_DMA()
+ (++) HAL_HMACEx_MD5_Step2_DMA()
+ (++) HAL_HMACEx_MD5_Step2_3_DMA()
+ (+) SHA1
+ (++) HAL_HMACEx_SHA1_Step1_2_DMA()
+ (++) HAL_HMACEx_SHA1_Step2_DMA()
+ (++) HAL_HMACEx_SHA1_Step2_3_DMA()
+
+ (+) SHA256
+ (++) HAL_HMACEx_SHA224_Step1_2_DMA()
+ (++) HAL_HMACEx_SHA224_Step2_DMA()
+ (++) HAL_HMACEx_SHA224_Step2_3_DMA()
+ (+) SHA256
+ (++) HAL_HMACEx_SHA256_Step1_2_DMA()
+ (++) HAL_HMACEx_SHA256_Step2_DMA()
+ (++) HAL_HMACEx_SHA256_Step2_3_DMA()
+
+ [..] User must first start-up the multi-buffer DMA-based HMAC computation in
+ calling HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
+ intiates step 2 with the first input buffer.
+
+ [..] The following buffers are next fed to the Peripheral with a call to the API
+ HAL_HMACEx_xxx_Step2_DMA(). There may be several consecutive calls
+ to this API.
+
+ [..] Multi-buffer DMA-based HMAC computation is wrapped up by a call to
+ HAL_HMACEx_xxx_Step2_3_DMA(). This finishes step 2 in feeding the last input
+ buffer to the Peripheral then carries out step 3.
+
+ [..] Digest is retrieved by a call to HAL_HASH_xxx_Finish() for MD-5 or
+ SHA-1, to HAL_HASHEx_xxx_Finish() for SHA-224 or SHA-256.
+
+ [..] If only two buffers need to be consecutively processed, a call to
+ HAL_HMACEx_xxx_Step1_2_DMA() followed by a call to HAL_HMACEx_xxx_Step2_3_DMA()
+ is sufficient.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief MD5 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
+ * @note Step 1 consists in writing the inner hash function key in the Peripheral,
+ * step 2 consists in writing the message text.
+ * @note The API carries out the HMAC step 1 then starts step 2 with
+ * the first buffer entered to the Peripheral. DCAL bit is not automatically set after
+ * the message buffer feeding, allowing other messages DMA transfers to occur.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (message buffer).
+ * @param Size length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ hhash->DigestCalculationDisable = SET;
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
+}
+
+/**
+ * @brief MD5 HMAC step 2 in multi-buffer DMA mode.
+ * @note Step 2 consists in writing the message text in the Peripheral.
+ * @note The API carries on the HMAC step 2, applied to the buffer entered as input
+ * parameter. DCAL bit is not automatically set after the message buffer feeding,
+ * allowing other messages DMA transfers to occur.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (message buffer).
+ * @param Size length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ if (hhash->DigestCalculationDisable != SET)
+ {
+ return HAL_ERROR;
+ }
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
+}
+
+/**
+ * @brief MD5 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
+ * @note Step 2 consists in writing the message text in the Peripheral,
+ * step 3 consists in writing the outer hash function key.
+ * @note The API wraps up the HMAC step 2 in processing the buffer entered as input
+ * parameter (the input buffer must be the last one of the multi-buffer thread)
+ * then carries out HMAC step 3.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note Once the DMA transfers are finished (indicated by hhash->State set back
+ * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
+ * the computed digest.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (message buffer).
+ * @param Size length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ hhash->DigestCalculationDisable = RESET;
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
+}
+
+
+/**
+ * @brief SHA1 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
+ * @note Step 1 consists in writing the inner hash function key in the Peripheral,
+ * step 2 consists in writing the message text.
+ * @note The API carries out the HMAC step 1 then starts step 2 with
+ * the first buffer entered to the Peripheral. DCAL bit is not automatically set after
+ * the message buffer feeding, allowing other messages DMA transfers to occur.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (message buffer).
+ * @param Size length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ hhash->DigestCalculationDisable = SET;
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
+}
+
+/**
+ * @brief SHA1 HMAC step 2 in multi-buffer DMA mode.
+ * @note Step 2 consists in writing the message text in the Peripheral.
+ * @note The API carries on the HMAC step 2, applied to the buffer entered as input
+ * parameter. DCAL bit is not automatically set after the message buffer feeding,
+ * allowing other messages DMA transfers to occur.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (message buffer).
+ * @param Size length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ if (hhash->DigestCalculationDisable != SET)
+ {
+ return HAL_ERROR;
+ }
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
+}
+
+/**
+ * @brief SHA1 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
+ * @note Step 2 consists in writing the message text in the Peripheral,
+ * step 3 consists in writing the outer hash function key.
+ * @note The API wraps up the HMAC step 2 in processing the buffer entered as input
+ * parameter (the input buffer must be the last one of the multi-buffer thread)
+ * then carries out HMAC step 3.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note Once the DMA transfers are finished (indicated by hhash->State set back
+ * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
+ * the computed digest.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (message buffer).
+ * @param Size length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ hhash->DigestCalculationDisable = RESET;
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
+}
+
+/**
+ * @brief SHA224 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
+ * @note Step 1 consists in writing the inner hash function key in the Peripheral,
+ * step 2 consists in writing the message text.
+ * @note The API carries out the HMAC step 1 then starts step 2 with
+ * the first buffer entered to the Peripheral. DCAL bit is not automatically set after
+ * the message buffer feeding, allowing other messages DMA transfers to occur.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (message buffer).
+ * @param Size length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ hhash->DigestCalculationDisable = SET;
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
+}
+
+/**
+ * @brief SHA224 HMAC step 2 in multi-buffer DMA mode.
+ * @note Step 2 consists in writing the message text in the Peripheral.
+ * @note The API carries on the HMAC step 2, applied to the buffer entered as input
+ * parameter. DCAL bit is not automatically set after the message buffer feeding,
+ * allowing other messages DMA transfers to occur.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (message buffer).
+ * @param Size length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ if (hhash->DigestCalculationDisable != SET)
+ {
+ return HAL_ERROR;
+ }
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
+}
+
+/**
+ * @brief SHA224 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
+ * @note Step 2 consists in writing the message text in the Peripheral,
+ * step 3 consists in writing the outer hash function key.
+ * @note The API wraps up the HMAC step 2 in processing the buffer entered as input
+ * parameter (the input buffer must be the last one of the multi-buffer thread)
+ * then carries out HMAC step 3.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note Once the DMA transfers are finished (indicated by hhash->State set back
+ * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
+ * the computed digest.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (message buffer).
+ * @param Size length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ hhash->DigestCalculationDisable = RESET;
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
+}
+
+/**
+ * @brief SHA256 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
+ * @note Step 1 consists in writing the inner hash function key in the Peripheral,
+ * step 2 consists in writing the message text.
+ * @note The API carries out the HMAC step 1 then starts step 2 with
+ * the first buffer entered to the Peripheral. DCAL bit is not automatically set after
+ * the message buffer feeding, allowing other messages DMA transfers to occur.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (message buffer).
+ * @param Size length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ hhash->DigestCalculationDisable = SET;
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
+}
+
+/**
+ * @brief SHA256 HMAC step 2 in multi-buffer DMA mode.
+ * @note Step 2 consists in writing the message text in the Peripheral.
+ * @note The API carries on the HMAC step 2, applied to the buffer entered as input
+ * parameter. DCAL bit is not automatically set after the message buffer feeding,
+ * allowing other messages DMA transfers to occur.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (message buffer).
+ * @param Size length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ if (hhash->DigestCalculationDisable != SET)
+ {
+ return HAL_ERROR;
+ }
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
+}
+
+/**
+ * @brief SHA256 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
+ * @note Step 2 consists in writing the message text in the Peripheral,
+ * step 3 consists in writing the outer hash function key.
+ * @note The API wraps up the HMAC step 2 in processing the buffer entered as input
+ * parameter (the input buffer must be the last one of the multi-buffer thread)
+ * then carries out HMAC step 3.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note Once the DMA transfers are finished (indicated by hhash->State set back
+ * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
+ * the computed digest.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (message buffer).
+ * @param Size length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ hhash->DigestCalculationDisable = RESET;
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
+}
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+#endif /* HASH*/
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hcd.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hcd.c
new file mode 100644
index 00000000..162c44b7
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hcd.c
@@ -0,0 +1,1737 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_hcd.c
+ * @author MCD Application Team
+ * @brief HCD HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the USB Peripheral Controller:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#)Declare a HCD_HandleTypeDef handle structure, for example:
+ HCD_HandleTypeDef hhcd;
+
+ (#)Fill parameters of Init structure in HCD handle
+
+ (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...)
+
+ (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API:
+ (##) Enable the HCD/USB Low Level interface clock using the following macros
+ (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
+ (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)
+
+ (##) Initialize the related GPIO clocks
+ (##) Configure HCD pin-out
+ (##) Configure HCD NVIC interrupt
+
+ (#)Associate the Upper USB Host stack to the HAL HCD Driver:
+ (##) hhcd.pData = phost;
+
+ (#)Enable HCD transmission and reception:
+ (##) HAL_HCD_Start();
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+
+/** @defgroup HCD HCD
+ * @brief HCD HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup HCD_Private_Functions HCD Private Functions
+ * @{
+ */
+static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd);
+static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup HCD_Exported_Functions HCD Exported Functions
+ * @{
+ */
+
+/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the host driver.
+ * @param hhcd HCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
+{
+#if defined (STM32U575xx) || defined (STM32U585xx)
+ USB_OTG_GlobalTypeDef *USBx;
+#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
+
+ /* Check the HCD handle allocation */
+ if (hhcd == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance));
+
+#if defined (STM32U575xx) || defined (STM32U585xx)
+ USBx = hhcd->Instance;
+#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
+
+ if (hhcd->State == HAL_HCD_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hhcd->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+ hhcd->SOFCallback = HAL_HCD_SOF_Callback;
+ hhcd->ConnectCallback = HAL_HCD_Connect_Callback;
+ hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback;
+ hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback;
+ hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback;
+ hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback;
+
+ if (hhcd->MspInitCallback == NULL)
+ {
+ hhcd->MspInitCallback = HAL_HCD_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hhcd->MspInitCallback(hhcd);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+ HAL_HCD_MspInit(hhcd);
+#endif /* (USE_HAL_HCD_REGISTER_CALLBACKS) */
+ }
+
+ hhcd->State = HAL_HCD_STATE_BUSY;
+#if defined (STM32U575xx) || defined (STM32U585xx)
+ /* Disable DMA mode for FS instance */
+ if ((USBx->CID & (0x1U << 8)) == 0U)
+ {
+ hhcd->Init.dma_enable = 0U;
+ }
+#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
+ /* Disable the Interrupts */
+ __HAL_HCD_DISABLE(hhcd);
+
+ /* Init the Core (common init.) */
+ (void)USB_CoreInit(hhcd->Instance, hhcd->Init);
+
+ /* Force Host Mode*/
+ (void)USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE);
+
+ /* Init Host */
+ (void)USB_HostInit(hhcd->Instance, hhcd->Init);
+
+ hhcd->State = HAL_HCD_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize a host channel.
+ * @param hhcd HCD handle
+ * @param ch_num Channel number.
+ * This parameter can be a value from 1 to 15
+ * @param epnum Endpoint number.
+ * This parameter can be a value from 1 to 15
+ * @param dev_address Current device address
+ * This parameter can be a value from 0 to 255
+ * @param speed Current device speed.
+ * This parameter can be one of these values:
+ * HCD_DEVICE_SPEED_HIGH: High speed mode,
+ * HCD_DEVICE_SPEED_FULL: Full speed mode,
+ * HCD_DEVICE_SPEED_LOW: Low speed mode
+ * @param ep_type Endpoint Type.
+ * This parameter can be one of these values:
+ * EP_TYPE_CTRL: Control type,
+ * EP_TYPE_ISOC: Isochronous type,
+ * EP_TYPE_BULK: Bulk type,
+ * EP_TYPE_INTR: Interrupt type
+ * @param mps Max Packet Size.
+ * This parameter can be a value from 0 to32K
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
+ uint8_t ch_num,
+ uint8_t epnum,
+ uint8_t dev_address,
+ uint8_t speed,
+ uint8_t ep_type,
+ uint16_t mps)
+{
+ HAL_StatusTypeDef status;
+
+ __HAL_LOCK(hhcd);
+ hhcd->hc[ch_num].do_ping = 0U;
+ hhcd->hc[ch_num].dev_addr = dev_address;
+ hhcd->hc[ch_num].max_packet = mps;
+ hhcd->hc[ch_num].ch_num = ch_num;
+ hhcd->hc[ch_num].ep_type = ep_type;
+ hhcd->hc[ch_num].ep_num = epnum & 0x7FU;
+
+ if ((epnum & 0x80U) == 0x80U)
+ {
+ hhcd->hc[ch_num].ep_is_in = 1U;
+ }
+ else
+ {
+ hhcd->hc[ch_num].ep_is_in = 0U;
+ }
+
+ hhcd->hc[ch_num].speed = speed;
+
+ status = USB_HC_Init(hhcd->Instance,
+ ch_num,
+ epnum,
+ dev_address,
+ speed,
+ ep_type,
+ mps);
+ __HAL_UNLOCK(hhcd);
+
+ return status;
+}
+
+/**
+ * @brief Halt a host channel.
+ * @param hhcd HCD handle
+ * @param ch_num Channel number.
+ * This parameter can be a value from 1 to 15
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ __HAL_LOCK(hhcd);
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+ __HAL_UNLOCK(hhcd);
+
+ return status;
+}
+
+/**
+ * @brief DeInitialize the host driver.
+ * @param hhcd HCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd)
+{
+ /* Check the HCD handle allocation */
+ if (hhcd == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ hhcd->State = HAL_HCD_STATE_BUSY;
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+ if (hhcd->MspDeInitCallback == NULL)
+ {
+ hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware */
+ hhcd->MspDeInitCallback(hhcd);
+#else
+ /* DeInit the low level hardware: CLOCK, NVIC.*/
+ HAL_HCD_MspDeInit(hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+
+ __HAL_HCD_DISABLE(hhcd);
+
+ hhcd->State = HAL_HCD_STATE_RESET;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the HCD MSP.
+ * @param hhcd HCD handle
+ * @retval None
+ */
+__weak void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhcd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HCD_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the HCD MSP.
+ * @param hhcd HCD handle
+ * @retval None
+ */
+__weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhcd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HCD_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HCD_Exported_Functions_Group2 Input and Output operation functions
+ * @brief HCD IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to manage the USB Host Data
+ Transfer
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Submit a new URB for processing.
+ * @param hhcd HCD handle
+ * @param ch_num Channel number.
+ * This parameter can be a value from 1 to 15
+ * @param direction Channel number.
+ * This parameter can be one of these values:
+ * 0 : Output / 1 : Input
+ * @param ep_type Endpoint Type.
+ * This parameter can be one of these values:
+ * EP_TYPE_CTRL: Control type/
+ * EP_TYPE_ISOC: Isochronous type/
+ * EP_TYPE_BULK: Bulk type/
+ * EP_TYPE_INTR: Interrupt type/
+ * @param token Endpoint Type.
+ * This parameter can be one of these values:
+ * 0: HC_PID_SETUP / 1: HC_PID_DATA1
+ * @param pbuff pointer to URB data
+ * @param length Length of URB data
+ * @param do_ping activate do ping protocol (for high speed only).
+ * This parameter can be one of these values:
+ * 0 : do ping inactive / 1 : do ping active
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
+ uint8_t ch_num,
+ uint8_t direction,
+ uint8_t ep_type,
+ uint8_t token,
+ uint8_t *pbuff,
+ uint16_t length,
+ uint8_t do_ping)
+{
+ hhcd->hc[ch_num].ep_is_in = direction;
+ hhcd->hc[ch_num].ep_type = ep_type;
+
+ if (token == 0U)
+ {
+ hhcd->hc[ch_num].data_pid = HC_PID_SETUP;
+ hhcd->hc[ch_num].do_ping = do_ping;
+ }
+ else
+ {
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+ }
+
+ /* Manage Data Toggle */
+ switch (ep_type)
+ {
+ case EP_TYPE_CTRL:
+ if ((token == 1U) && (direction == 0U)) /*send data */
+ {
+ if (length == 0U)
+ {
+ /* For Status OUT stage, Length==0, Status Out PID = 1 */
+ hhcd->hc[ch_num].toggle_out = 1U;
+ }
+
+ /* Set the Data Toggle bit as per the Flag */
+ if (hhcd->hc[ch_num].toggle_out == 0U)
+ {
+ /* Put the PID 0 */
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ }
+ else
+ {
+ /* Put the PID 1 */
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+ }
+ }
+ break;
+
+ case EP_TYPE_BULK:
+ if (direction == 0U)
+ {
+ /* Set the Data Toggle bit as per the Flag */
+ if (hhcd->hc[ch_num].toggle_out == 0U)
+ {
+ /* Put the PID 0 */
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ }
+ else
+ {
+ /* Put the PID 1 */
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+ }
+ }
+ else
+ {
+ if (hhcd->hc[ch_num].toggle_in == 0U)
+ {
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ }
+ else
+ {
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+ }
+ }
+
+ break;
+ case EP_TYPE_INTR:
+ if (direction == 0U)
+ {
+ /* Set the Data Toggle bit as per the Flag */
+ if (hhcd->hc[ch_num].toggle_out == 0U)
+ {
+ /* Put the PID 0 */
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ }
+ else
+ {
+ /* Put the PID 1 */
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+ }
+ }
+ else
+ {
+ if (hhcd->hc[ch_num].toggle_in == 0U)
+ {
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ }
+ else
+ {
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+ }
+ }
+ break;
+
+ case EP_TYPE_ISOC:
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ break;
+
+ default:
+ break;
+ }
+
+ hhcd->hc[ch_num].xfer_buff = pbuff;
+ hhcd->hc[ch_num].xfer_len = length;
+ hhcd->hc[ch_num].urb_state = URB_IDLE;
+ hhcd->hc[ch_num].xfer_count = 0U;
+ hhcd->hc[ch_num].ch_num = ch_num;
+ hhcd->hc[ch_num].state = HC_IDLE;
+
+ return USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[ch_num], (uint8_t)hhcd->Init.dma_enable);
+}
+
+/**
+ * @brief Handle HCD interrupt request.
+ * @param hhcd HCD handle
+ * @retval None
+ */
+void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
+{
+ USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t i;
+ uint32_t interrupt;
+
+ /* Ensure that we are in device mode */
+ if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST)
+ {
+ /* Avoid spurious interrupt */
+ if (__HAL_HCD_IS_INVALID_INTERRUPT(hhcd))
+ {
+ return;
+ }
+
+ if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
+ {
+ /* Incorrect mode, acknowledge the interrupt */
+ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
+ }
+
+ if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR))
+ {
+ /* Incorrect mode, acknowledge the interrupt */
+ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR);
+ }
+
+ if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE))
+ {
+ /* Incorrect mode, acknowledge the interrupt */
+ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE);
+ }
+
+ if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS))
+ {
+ /* Incorrect mode, acknowledge the interrupt */
+ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS);
+ }
+
+ /* Handle Host Disconnect Interrupts */
+ if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT))
+ {
+ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT);
+
+ if ((USBx_HPRT0 & USB_OTG_HPRT_PCSTS) == 0U)
+ {
+ /* Flush USB Fifo */
+ (void)USB_FlushTxFifo(USBx, 0x10U);
+ (void)USB_FlushRxFifo(USBx);
+
+ /* Restore FS Clock */
+ (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ);
+
+ /* Handle Host Port Disconnect Interrupt */
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+ hhcd->DisconnectCallback(hhcd);
+#else
+ HAL_HCD_Disconnect_Callback(hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* Handle Host Port Interrupts */
+ if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT))
+ {
+ HCD_Port_IRQHandler(hhcd);
+ }
+
+ /* Handle Host SOF Interrupt */
+ if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF))
+ {
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+ hhcd->SOFCallback(hhcd);
+#else
+ HAL_HCD_SOF_Callback(hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+
+ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF);
+ }
+
+ /* Handle Rx Queue Level Interrupts */
+ if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U)
+ {
+ USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+
+ HCD_RXQLVL_IRQHandler(hhcd);
+
+ USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+ }
+
+ /* Handle Host channel Interrupt */
+ if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))
+ {
+ interrupt = USB_HC_ReadInterrupt(hhcd->Instance);
+ for (i = 0U; i < hhcd->Init.Host_channels; i++)
+ {
+ if ((interrupt & (1UL << (i & 0xFU))) != 0U)
+ {
+ if ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_EPDIR) == USB_OTG_HCCHAR_EPDIR)
+ {
+ HCD_HC_IN_IRQHandler(hhcd, (uint8_t)i);
+ }
+ else
+ {
+ HCD_HC_OUT_IRQHandler(hhcd, (uint8_t)i);
+ }
+ }
+ }
+ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT);
+ }
+ }
+}
+
+
+/**
+ * @brief SOF callback.
+ * @param hhcd HCD handle
+ * @retval None
+ */
+__weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhcd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HCD_SOF_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Connection Event callback.
+ * @param hhcd HCD handle
+ * @retval None
+ */
+__weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhcd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HCD_Connect_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Disconnection Event callback.
+ * @param hhcd HCD handle
+ * @retval None
+ */
+__weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhcd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HCD_Disconnect_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Port Enabled Event callback.
+ * @param hhcd HCD handle
+ * @retval None
+ */
+__weak void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhcd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HCD_Disconnect_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Port Disabled Event callback.
+ * @param hhcd HCD handle
+ * @retval None
+ */
+__weak void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhcd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HCD_Disconnect_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Notify URB state change callback.
+ * @param hhcd HCD handle
+ * @param chnum Channel number.
+ * This parameter can be a value from 1 to 15
+ * @param urb_state:
+ * This parameter can be one of these values:
+ * URB_IDLE/
+ * URB_DONE/
+ * URB_NOTREADY/
+ * URB_NYET/
+ * URB_ERROR/
+ * URB_STALL/
+ * @retval None
+ */
+__weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhcd);
+ UNUSED(chnum);
+ UNUSED(urb_state);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file
+ */
+}
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+/**
+ * @brief Register a User USB HCD Callback
+ * To be used instead of the weak predefined callback
+ * @param hhcd USB HCD handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID
+ * @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID
+ * @arg @ref HAL_HCD_DISCONNECT_CB_ID OTG HCD Disconnect callback ID
+ * @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enable callback ID
+ * @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disable callback ID
+ * @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID
+ * @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd,
+ HAL_HCD_CallbackIDTypeDef CallbackID,
+ pHCD_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hhcd);
+
+ if (hhcd->State == HAL_HCD_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_HCD_SOF_CB_ID :
+ hhcd->SOFCallback = pCallback;
+ break;
+
+ case HAL_HCD_CONNECT_CB_ID :
+ hhcd->ConnectCallback = pCallback;
+ break;
+
+ case HAL_HCD_DISCONNECT_CB_ID :
+ hhcd->DisconnectCallback = pCallback;
+ break;
+
+ case HAL_HCD_PORT_ENABLED_CB_ID :
+ hhcd->PortEnabledCallback = pCallback;
+ break;
+
+ case HAL_HCD_PORT_DISABLED_CB_ID :
+ hhcd->PortDisabledCallback = pCallback;
+ break;
+
+ case HAL_HCD_MSPINIT_CB_ID :
+ hhcd->MspInitCallback = pCallback;
+ break;
+
+ case HAL_HCD_MSPDEINIT_CB_ID :
+ hhcd->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hhcd->State == HAL_HCD_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_HCD_MSPINIT_CB_ID :
+ hhcd->MspInitCallback = pCallback;
+ break;
+
+ case HAL_HCD_MSPDEINIT_CB_ID :
+ hhcd->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hhcd);
+ return status;
+}
+
+/**
+ * @brief Unregister an USB HCD Callback
+ * USB HCD callback is redirected to the weak predefined callback
+ * @param hhcd USB HCD handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID
+ * @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID
+ * @arg @ref HAL_HCD_DISCONNECT_CB_ID OTG HCD Disconnect callback ID
+ * @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enabled callback ID
+ * @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disabled callback ID
+ * @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID
+ * @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hhcd);
+
+ /* Setup Legacy weak Callbacks */
+ if (hhcd->State == HAL_HCD_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_HCD_SOF_CB_ID :
+ hhcd->SOFCallback = HAL_HCD_SOF_Callback;
+ break;
+
+ case HAL_HCD_CONNECT_CB_ID :
+ hhcd->ConnectCallback = HAL_HCD_Connect_Callback;
+ break;
+
+ case HAL_HCD_DISCONNECT_CB_ID :
+ hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback;
+ break;
+
+ case HAL_HCD_PORT_ENABLED_CB_ID :
+ hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback;
+ break;
+
+ case HAL_HCD_PORT_DISABLED_CB_ID :
+ hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback;
+ break;
+
+ case HAL_HCD_MSPINIT_CB_ID :
+ hhcd->MspInitCallback = HAL_HCD_MspInit;
+ break;
+
+ case HAL_HCD_MSPDEINIT_CB_ID :
+ hhcd->MspDeInitCallback = HAL_HCD_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hhcd->State == HAL_HCD_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_HCD_MSPINIT_CB_ID :
+ hhcd->MspInitCallback = HAL_HCD_MspInit;
+ break;
+
+ case HAL_HCD_MSPDEINIT_CB_ID :
+ hhcd->MspDeInitCallback = HAL_HCD_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hhcd);
+ return status;
+}
+
+/**
+ * @brief Register USB HCD Host Channel Notify URB Change Callback
+ * To be used instead of the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback
+ * @param hhcd HCD handle
+ * @param pCallback pointer to the USB HCD Host Channel Notify URB Change Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd,
+ pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hhcd);
+
+ if (hhcd->State == HAL_HCD_STATE_READY)
+ {
+ hhcd->HC_NotifyURBChangeCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hhcd);
+
+ return status;
+}
+
+/**
+ * @brief Unregister the USB HCD Host Channel Notify URB Change Callback
+ * USB HCD Host Channel Notify URB Change Callback is redirected
+ * to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback
+ * @param hhcd HCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hhcd);
+
+ if (hhcd->State == HAL_HCD_STATE_READY)
+ {
+ hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback; /* Legacy weak DataOutStageCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hhcd);
+
+ return status;
+}
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the HCD data
+ transfers.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start the host driver.
+ * @param hhcd HCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)
+{
+ __HAL_LOCK(hhcd);
+ /* Enable port power */
+ (void)USB_DriveVbus(hhcd->Instance, 1U);
+
+ /* Enable global interrupt */
+ __HAL_HCD_ENABLE(hhcd);
+ __HAL_UNLOCK(hhcd);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the host driver.
+ * @param hhcd HCD handle
+ * @retval HAL status
+ */
+
+HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd)
+{
+ __HAL_LOCK(hhcd);
+ (void)USB_StopHost(hhcd->Instance);
+ __HAL_UNLOCK(hhcd);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Reset the host port.
+ * @param hhcd HCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
+{
+ return (USB_ResetPort(hhcd->Instance));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the HCD handle state.
+ * @param hhcd HCD handle
+ * @retval HAL state
+ */
+HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd)
+{
+ return hhcd->State;
+}
+
+/**
+ * @brief Return URB state for a channel.
+ * @param hhcd HCD handle
+ * @param chnum Channel number.
+ * This parameter can be a value from 1 to 15
+ * @retval URB state.
+ * This parameter can be one of these values:
+ * URB_IDLE/
+ * URB_DONE/
+ * URB_NOTREADY/
+ * URB_NYET/
+ * URB_ERROR/
+ * URB_STALL
+ */
+HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
+{
+ return hhcd->hc[chnum].urb_state;
+}
+
+
+/**
+ * @brief Return the last host transfer size.
+ * @param hhcd HCD handle
+ * @param chnum Channel number.
+ * This parameter can be a value from 1 to 15
+ * @retval last transfer size in byte
+ */
+uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum)
+{
+ return hhcd->hc[chnum].xfer_count;
+}
+
+/**
+ * @brief Return the Host Channel state.
+ * @param hhcd HCD handle
+ * @param chnum Channel number.
+ * This parameter can be a value from 1 to 15
+ * @retval Host channel state
+ * This parameter can be one of these values:
+ * HC_IDLE/
+ * HC_XFRC/
+ * HC_HALTED/
+ * HC_NYET/
+ * HC_NAK/
+ * HC_STALL/
+ * HC_XACTERR/
+ * HC_BBLERR/
+ * HC_DATATGLERR
+ */
+HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
+{
+ return hhcd->hc[chnum].state;
+}
+
+/**
+ * @brief Return the current Host frame number.
+ * @param hhcd HCD handle
+ * @retval Current Host frame number
+ */
+uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd)
+{
+ return (USB_GetCurrentFrame(hhcd->Instance));
+}
+
+/**
+ * @brief Return the Host enumeration speed.
+ * @param hhcd HCD handle
+ * @retval Enumeration speed
+ */
+uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
+{
+ return (USB_GetHostSpeed(hhcd->Instance));
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup HCD_Private_Functions
+ * @{
+ */
+/**
+ * @brief Handle Host Channel IN interrupt requests.
+ * @param hhcd HCD handle
+ * @param chnum Channel number.
+ * This parameter can be a value from 1 to 15
+ * @retval none
+ */
+static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
+{
+ USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t ch_num = (uint32_t)chnum;
+
+ uint32_t tmpreg;
+
+ if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR)
+ {
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR);
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ }
+ else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_BBERR) == USB_OTG_HCINT_BBERR)
+ {
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_BBERR);
+ hhcd->hc[ch_num].state = HC_BBLERR;
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+ }
+ else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK)
+ {
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK);
+ }
+ else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL)
+ {
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ hhcd->hc[ch_num].state = HC_STALL;
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL);
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+ }
+ else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR)
+ {
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ hhcd->hc[ch_num].state = HC_DATATGLERR;
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR);
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+ }
+ else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR)
+ {
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ hhcd->hc[ch_num].state = HC_XACTERR;
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR);
+ }
+ else
+ {
+ /* ... */
+ }
+
+ if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR)
+ {
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR);
+ }
+ else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC)
+ {
+ if (hhcd->Init.dma_enable != 0U)
+ {
+ hhcd->hc[ch_num].xfer_count = hhcd->hc[ch_num].XferSize - \
+ (USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);
+ }
+
+ hhcd->hc[ch_num].state = HC_XFRC;
+ hhcd->hc[ch_num].ErrCnt = 0U;
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC);
+
+ if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) ||
+ (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK))
+ {
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
+ }
+ else if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR)
+ {
+ USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
+ hhcd->hc[ch_num].urb_state = URB_DONE;
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+ hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+#else
+ HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+ }
+ else if (hhcd->hc[ch_num].ep_type == EP_TYPE_ISOC)
+ {
+ hhcd->hc[ch_num].urb_state = URB_DONE;
+ hhcd->hc[ch_num].toggle_in ^= 1U;
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+ hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+#else
+ HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* ... */
+ }
+
+ if (hhcd->Init.dma_enable == 1U)
+ {
+ if (((hhcd->hc[ch_num].XferSize / hhcd->hc[ch_num].max_packet) & 1U) != 0U)
+ {
+ hhcd->hc[ch_num].toggle_in ^= 1U;
+ }
+ }
+ else
+ {
+ hhcd->hc[ch_num].toggle_in ^= 1U;
+ }
+ }
+ else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH)
+ {
+ __HAL_HCD_MASK_HALT_HC_INT(ch_num);
+
+ if (hhcd->hc[ch_num].state == HC_XFRC)
+ {
+ hhcd->hc[ch_num].urb_state = URB_DONE;
+ }
+ else if (hhcd->hc[ch_num].state == HC_STALL)
+ {
+ hhcd->hc[ch_num].urb_state = URB_STALL;
+ }
+ else if ((hhcd->hc[ch_num].state == HC_XACTERR) ||
+ (hhcd->hc[ch_num].state == HC_DATATGLERR))
+ {
+ hhcd->hc[ch_num].ErrCnt++;
+ if (hhcd->hc[ch_num].ErrCnt > 2U)
+ {
+ hhcd->hc[ch_num].ErrCnt = 0U;
+ hhcd->hc[ch_num].urb_state = URB_ERROR;
+ }
+ else
+ {
+ hhcd->hc[ch_num].urb_state = URB_NOTREADY;
+
+ /* re-activate the channel */
+ tmpreg = USBx_HC(ch_num)->HCCHAR;
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+ tmpreg |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(ch_num)->HCCHAR = tmpreg;
+ }
+ }
+ else if (hhcd->hc[ch_num].state == HC_NAK)
+ {
+ hhcd->hc[ch_num].urb_state = URB_NOTREADY;
+
+ /* re-activate the channel */
+ tmpreg = USBx_HC(ch_num)->HCCHAR;
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+ tmpreg |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(ch_num)->HCCHAR = tmpreg;
+ }
+ else if (hhcd->hc[ch_num].state == HC_BBLERR)
+ {
+ hhcd->hc[ch_num].ErrCnt++;
+ hhcd->hc[ch_num].urb_state = URB_ERROR;
+ }
+ else
+ {
+ /* ... */
+ }
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH);
+ HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+ }
+ else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK)
+ {
+ if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR)
+ {
+ hhcd->hc[ch_num].ErrCnt = 0U;
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+ }
+ else if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) ||
+ (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK))
+ {
+ hhcd->hc[ch_num].ErrCnt = 0U;
+
+ if (hhcd->Init.dma_enable == 0U)
+ {
+ hhcd->hc[ch_num].state = HC_NAK;
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+ }
+ }
+ else
+ {
+ /* ... */
+ }
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
+ }
+ else
+ {
+ /* ... */
+ }
+}
+
+/**
+ * @brief Handle Host Channel OUT interrupt requests.
+ * @param hhcd HCD handle
+ * @param chnum Channel number.
+ * This parameter can be a value from 1 to 15
+ * @retval none
+ */
+static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
+{
+ USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t ch_num = (uint32_t)chnum;
+ uint32_t tmpreg;
+ uint32_t num_packets;
+
+ if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR)
+ {
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR);
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ }
+ else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK)
+ {
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK);
+
+ if (hhcd->hc[ch_num].do_ping == 1U)
+ {
+ hhcd->hc[ch_num].do_ping = 0U;
+ hhcd->hc[ch_num].urb_state = URB_NOTREADY;
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+ }
+ }
+ else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR)
+ {
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR);
+ }
+ else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC)
+ {
+ hhcd->hc[ch_num].ErrCnt = 0U;
+
+ /* transaction completed with NYET state, update do ping state */
+ if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET)
+ {
+ hhcd->hc[ch_num].do_ping = 1U;
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET);
+ }
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC);
+ hhcd->hc[ch_num].state = HC_XFRC;
+ }
+ else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET)
+ {
+ hhcd->hc[ch_num].state = HC_NYET;
+ hhcd->hc[ch_num].do_ping = 1U;
+ hhcd->hc[ch_num].ErrCnt = 0U;
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET);
+ }
+ else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL)
+ {
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL);
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+ hhcd->hc[ch_num].state = HC_STALL;
+ }
+ else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK)
+ {
+ hhcd->hc[ch_num].ErrCnt = 0U;
+ hhcd->hc[ch_num].state = HC_NAK;
+
+ if (hhcd->hc[ch_num].do_ping == 0U)
+ {
+ if (hhcd->hc[ch_num].speed == HCD_DEVICE_SPEED_HIGH)
+ {
+ hhcd->hc[ch_num].do_ping = 1U;
+ }
+ }
+
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
+ }
+ else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR)
+ {
+ if (hhcd->Init.dma_enable == 0U)
+ {
+ hhcd->hc[ch_num].state = HC_XACTERR;
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+ }
+ else
+ {
+ hhcd->hc[ch_num].ErrCnt++;
+ if (hhcd->hc[ch_num].ErrCnt > 2U)
+ {
+ hhcd->hc[ch_num].ErrCnt = 0U;
+ hhcd->hc[ch_num].urb_state = URB_ERROR;
+ HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num,
+ hhcd->hc[ch_num].urb_state);
+ }
+ else
+ {
+ hhcd->hc[ch_num].urb_state = URB_NOTREADY;
+ }
+ }
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR);
+ }
+ else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR)
+ {
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR);
+ hhcd->hc[ch_num].state = HC_DATATGLERR;
+ }
+ else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH)
+ {
+ __HAL_HCD_MASK_HALT_HC_INT(ch_num);
+
+ if (hhcd->hc[ch_num].state == HC_XFRC)
+ {
+ hhcd->hc[ch_num].urb_state = URB_DONE;
+ if ((hhcd->hc[ch_num].ep_type == EP_TYPE_BULK) ||
+ (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR))
+ {
+ if (hhcd->Init.dma_enable == 0U)
+ {
+ hhcd->hc[ch_num].toggle_out ^= 1U;
+ }
+
+ if ((hhcd->Init.dma_enable == 1U) && (hhcd->hc[ch_num].xfer_len > 0U))
+ {
+ num_packets = (hhcd->hc[ch_num].xfer_len + hhcd->hc[ch_num].max_packet - 1U) / hhcd->hc[ch_num].max_packet;
+
+ if ((num_packets & 1U) != 0U)
+ {
+ hhcd->hc[ch_num].toggle_out ^= 1U;
+ }
+ }
+ }
+ }
+ else if (hhcd->hc[ch_num].state == HC_NAK)
+ {
+ hhcd->hc[ch_num].urb_state = URB_NOTREADY;
+ }
+ else if (hhcd->hc[ch_num].state == HC_NYET)
+ {
+ hhcd->hc[ch_num].urb_state = URB_NOTREADY;
+ }
+ else if (hhcd->hc[ch_num].state == HC_STALL)
+ {
+ hhcd->hc[ch_num].urb_state = URB_STALL;
+ }
+ else if ((hhcd->hc[ch_num].state == HC_XACTERR) ||
+ (hhcd->hc[ch_num].state == HC_DATATGLERR))
+ {
+ hhcd->hc[ch_num].ErrCnt++;
+ if (hhcd->hc[ch_num].ErrCnt > 2U)
+ {
+ hhcd->hc[ch_num].ErrCnt = 0U;
+ hhcd->hc[ch_num].urb_state = URB_ERROR;
+ }
+ else
+ {
+ hhcd->hc[ch_num].urb_state = URB_NOTREADY;
+
+ /* re-activate the channel */
+ tmpreg = USBx_HC(ch_num)->HCCHAR;
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+ tmpreg |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(ch_num)->HCCHAR = tmpreg;
+ }
+ }
+ else
+ {
+ /* ... */
+ }
+
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH);
+ HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+ }
+ else
+ {
+ /* ... */
+ }
+}
+
+/**
+ * @brief Handle Rx Queue Level interrupt requests.
+ * @param hhcd HCD handle
+ * @retval none
+ */
+static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd)
+{
+ USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t pktsts;
+ uint32_t pktcnt;
+ uint32_t GrxstspReg;
+ uint32_t xferSizePktCnt;
+ uint32_t tmpreg;
+ uint32_t ch_num;
+
+ GrxstspReg = hhcd->Instance->GRXSTSP;
+ ch_num = GrxstspReg & USB_OTG_GRXSTSP_EPNUM;
+ pktsts = (GrxstspReg & USB_OTG_GRXSTSP_PKTSTS) >> 17;
+ pktcnt = (GrxstspReg & USB_OTG_GRXSTSP_BCNT) >> 4;
+
+ switch (pktsts)
+ {
+ case GRXSTS_PKTSTS_IN:
+ /* Read the data into the host buffer. */
+ if ((pktcnt > 0U) && (hhcd->hc[ch_num].xfer_buff != (void *)0))
+ {
+ if ((hhcd->hc[ch_num].xfer_count + pktcnt) <= hhcd->hc[ch_num].xfer_len)
+ {
+ (void)USB_ReadPacket(hhcd->Instance,
+ hhcd->hc[ch_num].xfer_buff, (uint16_t)pktcnt);
+
+ /* manage multiple Xfer */
+ hhcd->hc[ch_num].xfer_buff += pktcnt;
+ hhcd->hc[ch_num].xfer_count += pktcnt;
+
+ /* get transfer size packet count */
+ xferSizePktCnt = (USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) >> 19;
+
+ if ((hhcd->hc[ch_num].max_packet == pktcnt) && (xferSizePktCnt > 0U))
+ {
+ /* re-activate the channel when more packets are expected */
+ tmpreg = USBx_HC(ch_num)->HCCHAR;
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+ tmpreg |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(ch_num)->HCCHAR = tmpreg;
+ hhcd->hc[ch_num].toggle_in ^= 1U;
+ }
+ }
+ else
+ {
+ hhcd->hc[ch_num].urb_state = URB_ERROR;
+ }
+ }
+ break;
+
+ case GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
+ break;
+
+ case GRXSTS_PKTSTS_IN_XFER_COMP:
+ case GRXSTS_PKTSTS_CH_HALTED:
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Handle Host Port interrupt requests.
+ * @param hhcd HCD handle
+ * @retval None
+ */
+static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd)
+{
+ USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ __IO uint32_t hprt0;
+ __IO uint32_t hprt0_dup;
+
+ /* Handle Host Port Interrupts */
+ hprt0 = USBx_HPRT0;
+ hprt0_dup = USBx_HPRT0;
+
+ hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \
+ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
+
+ /* Check whether Port Connect detected */
+ if ((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET)
+ {
+ if ((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS)
+ {
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+ hhcd->ConnectCallback(hhcd);
+#else
+ HAL_HCD_Connect_Callback(hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+ }
+ hprt0_dup |= USB_OTG_HPRT_PCDET;
+ }
+
+ /* Check whether Port Enable Changed */
+ if ((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG)
+ {
+ hprt0_dup |= USB_OTG_HPRT_PENCHNG;
+
+ if ((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA)
+ {
+ if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY)
+ {
+ if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17))
+ {
+ (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_6_MHZ);
+ }
+ else
+ {
+ (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ);
+ }
+ }
+ else
+ {
+ if (hhcd->Init.speed == HCD_SPEED_FULL)
+ {
+ USBx_HOST->HFIR = 60000U;
+ }
+ }
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+ hhcd->PortEnabledCallback(hhcd);
+#else
+ HAL_HCD_PortEnabled_Callback(hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+
+ }
+ else
+ {
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+ hhcd->PortDisabledCallback(hhcd);
+#else
+ HAL_HCD_PortDisabled_Callback(hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* Check for an overcurrent */
+ if ((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG)
+ {
+ hprt0_dup |= USB_OTG_HPRT_POCCHNG;
+ }
+
+ /* Clear Port Interrupts */
+ USBx_HPRT0 = hprt0_dup;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c.c
new file mode 100644
index 00000000..43312d3e
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c.c
@@ -0,0 +1,7186 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_i2c.c
+ * @author MCD Application Team
+ * @brief I2C HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Inter Integrated Circuit (I2C) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State and Errors functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The I2C HAL driver can be used as follows:
+
+ (#) Declare a I2C_HandleTypeDef handle structure, for example:
+ I2C_HandleTypeDef hi2c;
+
+ (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API:
+ (##) Enable the I2Cx interface clock
+ (##) I2C pins configuration
+ (+++) Enable the clock for the I2C GPIOs
+ (+++) Configure I2C pins as alternate function open-drain
+ (##) NVIC configuration if you need to use interrupt process
+ (+++) Configure the I2Cx interrupt priority
+ (+++) Enable the NVIC I2C IRQ Channel
+ (##) DMA Configuration if you need to use DMA process
+ (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
+ (+++) Enable the DMAx interface clock using
+ (+++) Configure the DMA handle parameters
+ (+++) Configure the DMA Tx or Rx channel
+ (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
+ the DMA Tx or Rx channel
+
+ (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
+ Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
+
+ (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware
+ (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit(&hi2c) API.
+
+ (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady()
+
+ (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit()
+ (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive()
+ (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit()
+ (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive()
+
+ *** Polling mode IO MEM operation ***
+ =====================================
+ [..]
+ (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write()
+ (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read()
+
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT()
+ (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
+ (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT()
+ (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
+ (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT()
+ (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
+ (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT()
+ (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
+ (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+ (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
+ (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
+ (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
+ This action will inform Master to generate a Stop condition to discard the communication.
+
+
+ *** Interrupt mode or DMA mode IO sequential operation ***
+ ==========================================================
+ [..]
+ (@) These interfaces allow to manage a sequential transfer with a repeated start condition
+ when a direction change during transfer
+ [..]
+ (+) A specific option field manage the different steps of a sequential transfer
+ (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
+ (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential
+ mode
+ (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
+ and data to transfer without a final stop condition
+ (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start
+ condition, address and data to transfer without a final stop condition, an then permit
+ a call the same master sequential interface several times
+ (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT()
+ or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA())
+ (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
+ and with new data to transfer if the direction change or manage only the new data to
+ transfer
+ if no direction change and without a final stop condition in both cases
+ (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
+ and with new data to transfer if the direction change or manage only the new data to
+ transfer
+ if no direction change and with a final stop condition in both cases
+ (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition
+ after several call of the same master sequential
+ interface several times (link with option I2C_FIRST_AND_NEXT_FRAME).
+ Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT
+ (option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
+ or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
+ or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
+ or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).
+ Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence
+ permit to call the opposite interface Receive or Transmit without stopping
+ the communication and so generate a restart condition.
+ (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after
+ each call of the same master sequential
+ interface.
+ Usage can, transfer several bytes one by one with a restart with slave address between
+ each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
+ or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
+ or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
+ or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME).
+ Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic
+ generation of STOP condition.
+
+ (+) Different sequential I2C interfaces are listed below:
+ (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using
+ @ref HAL_I2C_Master_Seq_Transmit_IT() or using @ref HAL_I2C_Master_Seq_Transmit_DMA()
+ (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
+ (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using
+ @ref HAL_I2C_Master_Seq_Receive_IT() or using @ref HAL_I2C_Master_Seq_Receive_DMA()
+ (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
+ (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
+ (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
+ (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT()
+ @ref HAL_I2C_DisableListen_IT()
+ (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can
+ add his own code to check the Address Match Code and the transmission direction request by master
+ (Write/Read).
+ (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback()
+ (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using
+ @ref HAL_I2C_Slave_Seq_Transmit_IT()
+ or using @ref HAL_I2C_Slave_Seq_Transmit_DMA()
+ (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
+ (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using
+ @ref HAL_I2C_Slave_Seq_Receive_IT()
+ or using @ref HAL_I2C_Slave_Seq_Receive_DMA()
+ (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
+ (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+ (++) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
+ This action will inform Master to generate a Stop condition to discard the communication.
+
+ *** Interrupt mode IO MEM operation ***
+ =======================================
+ [..]
+ (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
+ @ref HAL_I2C_Mem_Write_IT()
+ (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()
+ (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
+ @ref HAL_I2C_Mem_Read_IT()
+ (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()
+ (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
+ @ref HAL_I2C_Master_Transmit_DMA()
+ (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
+ (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
+ @ref HAL_I2C_Master_Receive_DMA()
+ (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
+ (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
+ @ref HAL_I2C_Slave_Transmit_DMA()
+ (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
+ (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
+ @ref HAL_I2C_Slave_Receive_DMA()
+ (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
+ (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+ (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
+ (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
+ (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
+ This action will inform Master to generate a Stop condition to discard the communication.
+
+ *** DMA mode IO MEM operation ***
+ =================================
+ [..]
+ (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
+ @ref HAL_I2C_Mem_Write_DMA()
+ (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()
+ (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
+ @ref HAL_I2C_Mem_Read_DMA()
+ (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()
+ (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+
+
+ *** I2C HAL driver macros list ***
+ ==================================
+ [..]
+ Below the list of most used macros in I2C HAL driver.
+
+ (+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral
+ (+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral
+ (+) @ref __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
+ (+) @ref __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
+ (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
+ (+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
+ (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
+
+ *** Callback registration ***
+ =============================================
+ [..]
+ The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback()
+ to register an interrupt callback.
+ [..]
+ Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks:
+ (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+ (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+ (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
+ (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
+ (+) ListenCpltCallback : callback for end of listen mode.
+ (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
+ (+) MemRxCpltCallback : callback for Memory reception end of transfer.
+ (+) ErrorCallback : callback for error detection.
+ (+) AbortCpltCallback : callback for abort completion process.
+ (+) MspInitCallback : callback for Msp Init.
+ (+) MspDeInitCallback : callback for Msp DeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+ [..]
+ For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback().
+ [..]
+ Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default
+ weak function.
+ @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+ (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+ (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
+ (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
+ (+) ListenCpltCallback : callback for end of listen mode.
+ (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
+ (+) MemRxCpltCallback : callback for Memory reception end of transfer.
+ (+) ErrorCallback : callback for error detection.
+ (+) AbortCpltCallback : callback for abort completion process.
+ (+) MspInitCallback : callback for Msp Init.
+ (+) MspDeInitCallback : callback for Msp DeInit.
+ [..]
+ For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback().
+ [..]
+ By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+ [..]
+ Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
+ Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ Then, the user first registers the MspInit/MspDeInit user callbacks
+ using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit()
+ or @ref HAL_I2C_Init() function.
+ [..]
+ When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
+ [..]
+ (@) You can refer to the I2C HAL driver header file for more useful macros
+
+ @endverbatim
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup I2C I2C
+ * @brief I2C HAL module driver
+ * @{
+ */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup I2C_Private_Define I2C Private Define
+ * @{
+ */
+#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */
+#define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */
+#define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */
+#define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */
+#define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */
+#define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */
+#define I2C_TIMEOUT_TC (25U) /*!< 25 ms */
+#define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */
+#define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */
+#define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */
+
+#define MAX_NBYTE_SIZE 255U
+#define SLAVE_ADDR_SHIFT 7U
+#define SLAVE_ADDR_MSK 0x06U
+
+/* Private define for @ref PreviousState usage */
+/*!< Mask State define, keep only RX and TX bits */
+#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \
+ (uint32_t)HAL_I2C_STATE_BUSY_RX) & \
+ (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY))))
+/*!< Default Value */
+#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
+/*!< Master Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
+ (uint32_t)HAL_I2C_MODE_MASTER))
+/*!< Master Busy RX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
+ (uint32_t)HAL_I2C_MODE_MASTER))
+/*!< Slave Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
+ (uint32_t)HAL_I2C_MODE_SLAVE))
+/*!< Slave Busy RX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
+ (uint32_t)HAL_I2C_MODE_SLAVE))
+/*!< Memory Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
+ (uint32_t)HAL_I2C_MODE_MEM))
+/*!< Memory Busy RX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
+ (uint32_t)HAL_I2C_MODE_MEM))
+
+
+/* Private define to centralize the enable/disable of Interrupts */
+#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */
+#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */
+#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /* Bit field can be combinated with @ref I2C_XFER_TX_IT
+ and @ref I2C_XFER_RX_IT */
+
+#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /* Bit definition to manage addition of global Error
+ and NACK treatment */
+#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /* Bit definition to manage only STOP evenement */
+#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /* Bit definition to manage only Reload of NBYTE */
+
+/* Private define Sequential Transfer Options default/reset value */
+#define I2C_NO_OPTION_FRAME (0xFFFF0000U)
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/** @defgroup I2C_Private_Functions I2C Private Functions
+ * @{
+ */
+/* Private functions to handle DMA transfer */
+static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMAError(DMA_HandleTypeDef *hdma);
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
+
+/* Private functions to handle IT transfer */
+static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
+static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c);
+static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
+
+/* Private functions to handle IT transfer */
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
+
+/* Private functions for I2C transfer IRQ handler */
+static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+
+/* Private functions to handle flags during polling transfer */
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
+ uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+
+/* Private functions to centralize the enable/disable of Interrupts */
+static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
+static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
+
+/* Private function to treat different error callback */
+static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c);
+
+/* Private function to flush TXDR register */
+static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
+
+/* Private function to handle start, restart or stop a transfer */
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
+ uint32_t Request);
+
+/* Private function to Convert Specific options */
+static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Functions I2C Exported Functions
+ * @{
+ */
+
+/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ deinitialize the I2Cx peripheral:
+
+ (+) User must Implement HAL_I2C_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+ (+) Call the function HAL_I2C_Init() to configure the selected device with
+ the selected configuration:
+ (++) Clock Timing
+ (++) Own Address 1
+ (++) Addressing mode (Master, Slave)
+ (++) Dual Addressing mode
+ (++) Own Address 2
+ (++) Own Address 2 Mask
+ (++) General call mode
+ (++) Nostretch mode
+
+ (+) Call the function HAL_I2C_DeInit() to restore the default configuration
+ of the selected I2Cx peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the I2C according to the specified parameters
+ * in the I2C_InitTypeDef and initialize the associated handle.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
+{
+ /* Check the I2C handle allocation */
+ if (hi2c == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+ assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
+ assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
+ assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
+ assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
+ assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
+ assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
+ assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
+
+ if (hi2c->State == HAL_I2C_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hi2c->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ /* Init the I2C Callback settings */
+ hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+ hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+ hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
+ hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
+ hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
+ hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
+ hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
+ hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
+ hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
+
+ if (hi2c->MspInitCallback == NULL)
+ {
+ hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ hi2c->MspInitCallback(hi2c);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ HAL_I2C_MspInit(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+
+ /* Disable the selected I2C peripheral */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
+ /* Configure I2Cx: Frequency range */
+ hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
+
+ /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
+ /* Disable Own Address1 before set the Own Address1 configuration */
+ hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
+
+ /* Configure I2Cx: Own Address1 and ack own address1 mode */
+ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
+ {
+ hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
+ }
+ else /* I2C_ADDRESSINGMODE_10BIT */
+ {
+ hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
+ }
+
+ /*---------------------------- I2Cx CR2 Configuration ----------------------*/
+ /* Configure I2Cx: Addressing Master mode */
+ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+ {
+ hi2c->Instance->CR2 = (I2C_CR2_ADD10);
+ }
+ /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
+ hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
+
+ /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
+ /* Disable Own Address2 before set the Own Address2 configuration */
+ hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
+
+ /* Configure I2Cx: Dual mode and Own Address2 */
+ hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));
+
+ /*---------------------------- I2Cx CR1 Configuration ----------------------*/
+ /* Configure I2Cx: Generalcall and NoStretch mode */
+ hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
+
+ /* Enable the selected I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitialize the I2C peripheral.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
+{
+ /* Check the I2C handle allocation */
+ if (hi2c == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+
+ /* Disable the I2C Peripheral Clock */
+ __HAL_I2C_DISABLE(hi2c);
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ if (hi2c->MspDeInitCallback == NULL)
+ {
+ hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ hi2c->MspDeInitCallback(hi2c);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_I2C_MspDeInit(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ hi2c->State = HAL_I2C_STATE_RESET;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the I2C MSP.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the I2C MSP.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_MspDeInit could be implemented in the user file
+ */
+}
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User I2C Callback
+ * To be used instead of the weak predefined callback
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+ * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+ * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+ * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+ * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+ * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
+ * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
+ * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
+ * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
+ pI2C_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hi2c);
+
+ if (HAL_I2C_STATE_READY == hi2c->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
+ hi2c->MasterTxCpltCallback = pCallback;
+ break;
+
+ case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
+ hi2c->MasterRxCpltCallback = pCallback;
+ break;
+
+ case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
+ hi2c->SlaveTxCpltCallback = pCallback;
+ break;
+
+ case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
+ hi2c->SlaveRxCpltCallback = pCallback;
+ break;
+
+ case HAL_I2C_LISTEN_COMPLETE_CB_ID :
+ hi2c->ListenCpltCallback = pCallback;
+ break;
+
+ case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
+ hi2c->MemTxCpltCallback = pCallback;
+ break;
+
+ case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
+ hi2c->MemRxCpltCallback = pCallback;
+ break;
+
+ case HAL_I2C_ERROR_CB_ID :
+ hi2c->ErrorCallback = pCallback;
+ break;
+
+ case HAL_I2C_ABORT_CB_ID :
+ hi2c->AbortCpltCallback = pCallback;
+ break;
+
+ case HAL_I2C_MSPINIT_CB_ID :
+ hi2c->MspInitCallback = pCallback;
+ break;
+
+ case HAL_I2C_MSPDEINIT_CB_ID :
+ hi2c->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_I2C_STATE_RESET == hi2c->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_I2C_MSPINIT_CB_ID :
+ hi2c->MspInitCallback = pCallback;
+ break;
+
+ case HAL_I2C_MSPDEINIT_CB_ID :
+ hi2c->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2c);
+ return status;
+}
+
+/**
+ * @brief Unregister an I2C Callback
+ * I2C callback is redirected to the weak predefined callback
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+ * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+ * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+ * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+ * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+ * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
+ * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
+ * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
+ * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hi2c);
+
+ if (HAL_I2C_STATE_READY == hi2c->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
+ hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+ break;
+
+ case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
+ hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+ break;
+
+ case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
+ hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
+ break;
+
+ case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
+ hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
+ break;
+
+ case HAL_I2C_LISTEN_COMPLETE_CB_ID :
+ hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
+ break;
+
+ case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
+ hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
+ break;
+
+ case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
+ hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
+ break;
+
+ case HAL_I2C_ERROR_CB_ID :
+ hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_I2C_ABORT_CB_ID :
+ hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ break;
+
+ case HAL_I2C_MSPINIT_CB_ID :
+ hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_I2C_MSPDEINIT_CB_ID :
+ hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_I2C_STATE_RESET == hi2c->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_I2C_MSPINIT_CB_ID :
+ hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_I2C_MSPDEINIT_CB_ID :
+ hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2c);
+ return status;
+}
+
+/**
+ * @brief Register the Slave Address Match I2C Callback
+ * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pCallback pointer to the Address Match Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hi2c);
+
+ if (HAL_I2C_STATE_READY == hi2c->State)
+ {
+ hi2c->AddrCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2c);
+ return status;
+}
+
+/**
+ * @brief UnRegister the Slave Address Match I2C Callback
+ * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hi2c);
+
+ if (HAL_I2C_STATE_READY == hi2c->State)
+ {
+ hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2c);
+ return status;
+}
+
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the I2C data
+ transfers.
+
+ (#) There are two modes of transfer:
+ (++) Blocking mode : The communication is performed in the polling mode.
+ The status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode : The communication is performed using Interrupts
+ or DMA. These functions return the status of the transfer startup.
+ The end of the data processing will be indicated through the
+ dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+
+ (#) Blocking mode functions are :
+ (++) HAL_I2C_Master_Transmit()
+ (++) HAL_I2C_Master_Receive()
+ (++) HAL_I2C_Slave_Transmit()
+ (++) HAL_I2C_Slave_Receive()
+ (++) HAL_I2C_Mem_Write()
+ (++) HAL_I2C_Mem_Read()
+ (++) HAL_I2C_IsDeviceReady()
+
+ (#) No-Blocking mode functions with Interrupt are :
+ (++) HAL_I2C_Master_Transmit_IT()
+ (++) HAL_I2C_Master_Receive_IT()
+ (++) HAL_I2C_Slave_Transmit_IT()
+ (++) HAL_I2C_Slave_Receive_IT()
+ (++) HAL_I2C_Mem_Write_IT()
+ (++) HAL_I2C_Mem_Read_IT()
+ (++) HAL_I2C_Master_Seq_Transmit_IT()
+ (++) HAL_I2C_Master_Seq_Receive_IT()
+ (++) HAL_I2C_Slave_Seq_Transmit_IT()
+ (++) HAL_I2C_Slave_Seq_Receive_IT()
+ (++) HAL_I2C_EnableListen_IT()
+ (++) HAL_I2C_DisableListen_IT()
+ (++) HAL_I2C_Master_Abort_IT()
+
+ (#) No-Blocking mode functions with DMA are :
+ (++) HAL_I2C_Master_Transmit_DMA()
+ (++) HAL_I2C_Master_Receive_DMA()
+ (++) HAL_I2C_Slave_Transmit_DMA()
+ (++) HAL_I2C_Slave_Receive_DMA()
+ (++) HAL_I2C_Mem_Write_DMA()
+ (++) HAL_I2C_Mem_Read_DMA()
+ (++) HAL_I2C_Master_Seq_Transmit_DMA()
+ (++) HAL_I2C_Master_Seq_Receive_DMA()
+ (++) HAL_I2C_Slave_Seq_Transmit_DMA()
+ (++) HAL_I2C_Slave_Seq_Receive_DMA()
+
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (++) HAL_I2C_MasterTxCpltCallback()
+ (++) HAL_I2C_MasterRxCpltCallback()
+ (++) HAL_I2C_SlaveTxCpltCallback()
+ (++) HAL_I2C_SlaveRxCpltCallback()
+ (++) HAL_I2C_MemTxCpltCallback()
+ (++) HAL_I2C_MemRxCpltCallback()
+ (++) HAL_I2C_AddrCallback()
+ (++) HAL_I2C_ListenCpltCallback()
+ (++) HAL_I2C_ErrorCallback()
+ (++) HAL_I2C_AbortCpltCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmits in master mode an amount of data in blocking mode.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferISR = NULL;
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
+ }
+
+ while (hi2c->XferCount > 0U)
+ {
+ /* Wait until TXIS flag is set */
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ hi2c->XferCount--;
+ hi2c->XferSize--;
+
+ if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+ {
+ /* Wait until TCR flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ }
+ }
+ }
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is set */
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receives in master mode an amount of data in blocking mode.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferISR = NULL;
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+ }
+
+ while (hi2c->XferCount > 0U)
+ {
+ /* Wait until RXNE flag is set */
+ if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Read data from RXDR */
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+
+ if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+ {
+ /* Wait until TCR flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ }
+ }
+ }
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is set */
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmits in slave mode an amount of data in blocking mode.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferISR = NULL;
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Wait until ADDR flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_ERROR;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+ /* If 10bit addressing mode is selected */
+ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+ {
+ /* Wait until ADDR flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_ERROR;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+ }
+
+ /* Wait until DIR flag is set Transmitter mode */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_ERROR;
+ }
+
+ while (hi2c->XferCount > 0U)
+ {
+ /* Wait until TXIS flag is set */
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_ERROR;
+ }
+
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ hi2c->XferCount--;
+ }
+
+ /* Wait until STOP flag is set */
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Normal use case for Transmitter mode */
+ /* A NACK is generated to confirm the end of transfer */
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Clear STOP flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Wait until BUSY flag is reset */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_ERROR;
+ }
+
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in slave mode an amount of data in blocking mode
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferISR = NULL;
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Wait until ADDR flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_ERROR;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+ /* Wait until DIR flag is reset Receiver mode */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_ERROR;
+ }
+
+ while (hi2c->XferCount > 0U)
+ {
+ /* Wait until RXNE flag is set */
+ if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ /* Store Last receive data if any */
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+ {
+ /* Read data from RXDR */
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ hi2c->XferCount--;
+ }
+
+ return HAL_ERROR;
+ }
+
+ /* Read data from RXDR */
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ hi2c->XferCount--;
+ }
+
+ /* Wait until STOP flag is set */
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_ERROR;
+ }
+
+ /* Clear STOP flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Wait until BUSY flag is reset */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_ERROR;
+ }
+
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size)
+{
+ uint32_t xfermode;
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Master_ISR_IT;
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = I2C_AUTOEND_MODE;
+ }
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+ /* Check if the Autonomous mode is enabled */
+ if ((hi2c->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN)
+ {
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_NO_START_WRITE);
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size)
+{
+ uint32_t xfermode;
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Master_ISR_IT;
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = I2C_AUTOEND_MODE;
+ }
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+ /* Check if the Autonomous mode is enabled */
+ if ((hi2c->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN)
+ {
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_NO_START_READ);
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Slave_ISR_IT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Slave_ISR_IT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in master mode an amount of data in non-blocking mode with DMA
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size)
+{
+ uint32_t xfermode;
+ HAL_StatusTypeDef dmaxferstatus;
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Master_ISR_DMA;
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = I2C_AUTOEND_MODE;
+ }
+
+ if (hi2c->XferSize > 0U)
+ {
+ if (hi2c->hdmatx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if (hi2c->hdmatx->LinkedListQueue != NULL)
+ {
+ /* Set DMA data size */
+ hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
+
+ /* Set DMA source address */
+ hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
+
+ /* Set DMA destination address */
+ hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \
+ = (uint32_t)&hi2c->Instance->TXDR;
+
+ dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
+ hi2c->XferSize);
+ }
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ /* Check if the Autonomous mode is enabled */
+ if ((hi2c->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN)
+ {
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_NO_START_WRITE);
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
+ }
+
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Update Transfer ISR function pointer */
+ hi2c->XferISR = I2C_Master_ISR_IT;
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and generate START condition */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in master mode an amount of data in non-blocking mode with DMA
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size)
+{
+ uint32_t xfermode;
+ HAL_StatusTypeDef dmaxferstatus;
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Master_ISR_DMA;
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = I2C_AUTOEND_MODE;
+ }
+
+ if (hi2c->XferSize > 0U)
+ {
+ if (hi2c->hdmarx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if (hi2c->hdmarx->LinkedListQueue != NULL)
+ {
+ /* Set DMA data size */
+ hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
+
+ /* Set DMA source address */
+ hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \
+ = (uint32_t)&hi2c->Instance->RXDR;
+
+ /* Set DMA destination address */
+ hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
+
+ dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
+ hi2c->XferSize);
+ }
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Send Slave Address */
+ /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ /* Check if the Autonomous mode is enabled */
+ if ((hi2c->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN)
+ {
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_NO_START_READ);
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+ }
+
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Update Transfer ISR function pointer */
+ hi2c->XferISR = I2C_Master_ISR_IT;
+
+ /* Send Slave Address */
+ /* Set NBYTES to read and generate START condition */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef dmaxferstatus;
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Slave_ISR_DMA;
+
+ if (hi2c->hdmatx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if (hi2c->hdmatx->LinkedListQueue != NULL)
+ {
+ /* Set DMA data size */
+ hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
+
+ /* Set DMA source address */
+ hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
+
+ /* Set DMA destination address */
+ hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \
+ = (uint32_t)&hi2c->Instance->TXDR;
+
+ dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
+ hi2c->XferSize);
+ }
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, STOP, NACK, ADDR interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef dmaxferstatus;
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Slave_ISR_DMA;
+
+ if (hi2c->hdmarx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if (hi2c->hdmarx->LinkedListQueue != NULL)
+ {
+ /* Set DMA data size */
+ hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
+
+ /* Set DMA source address */
+ hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \
+ = (uint32_t)&hi2c->Instance->RXDR;
+
+ /* Set DMA destination address */
+ hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
+
+ dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
+ hi2c->XferSize);
+ }
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, STOP, NACK, ADDR interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @brief Write an amount of data in blocking mode to a specific memory address
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferISR = NULL;
+
+ /* Send Slave Address and Memory Address */
+ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ }
+
+ do
+ {
+ /* Wait until TXIS flag is set */
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ hi2c->XferCount--;
+ hi2c->XferSize--;
+
+ if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+ {
+ /* Wait until TCR flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ }
+ }
+
+ } while (hi2c->XferCount > 0U);
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Read an amount of data in blocking mode from a specific memory address
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferISR = NULL;
+
+ /* Send Slave Address and Memory Address */
+ if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+ }
+
+ do
+ {
+ /* Wait until RXNE flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Read data from RXDR */
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+
+ if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+ {
+ /* Wait until TCR flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ }
+ }
+ } while (hi2c->XferCount > 0U);
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ uint32_t tickstart;
+ uint32_t xfermode;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Master_ISR_IT;
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = I2C_AUTOEND_MODE;
+ }
+
+ /* Send Slave Address and Memory Address */
+ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ uint32_t tickstart;
+ uint32_t xfermode;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Master_ISR_IT;
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = I2C_AUTOEND_MODE;
+ }
+
+ /* Send Slave Address and Memory Address */
+ if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ uint32_t tickstart;
+ uint32_t xfermode;
+ HAL_StatusTypeDef dmaxferstatus;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Master_ISR_DMA;
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = I2C_AUTOEND_MODE;
+ }
+
+ /* Send Slave Address and Memory Address */
+ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+
+
+ if (hi2c->hdmatx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if (hi2c->hdmatx->LinkedListQueue != NULL)
+ {
+ /* Set DMA data size */
+ hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
+
+ /* Set DMA source address */
+ hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
+
+ /* Set DMA destination address */
+ hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \
+ = (uint32_t)&hi2c->Instance->TXDR;
+
+ dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
+ hi2c->XferSize);
+ }
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be read
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ uint32_t tickstart;
+ uint32_t xfermode;
+ HAL_StatusTypeDef dmaxferstatus;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Master_ISR_DMA;
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = I2C_AUTOEND_MODE;
+ }
+
+ /* Send Slave Address and Memory Address */
+ if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+
+ if (hi2c->hdmarx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if (hi2c->hdmarx->LinkedListQueue != NULL)
+ {
+ /* Set DMA data size */
+ hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
+
+ /* Set DMA source address */
+ hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \
+ = (uint32_t)&hi2c->Instance->RXDR;
+
+ /* Set DMA destination address */
+ hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
+
+ dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
+ hi2c->XferSize);
+ }
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Checks if target device is ready for communication.
+ * @note This function is used with Memory devices
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param Trials Number of trials
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ __IO uint32_t I2C_Trials = 0UL;
+
+ FlagStatus tmp1;
+ FlagStatus tmp2;
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ do
+ {
+ /* Generate Start */
+ hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is set or a NACK flag is set*/
+ tickstart = HAL_GetTick();
+
+ tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
+ tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+
+ while ((tmp1 == RESET) && (tmp2 == RESET))
+ {
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ }
+
+ tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
+ tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+ }
+
+ /* Check if the NACKF flag has not been set */
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
+ {
+ /* Wait until STOPF flag is reset */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Device is ready */
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Wait until STOPF flag is reset */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Clear STOP Flag, auto generated with autoend*/
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+ }
+
+ /* Check if the maximum allowed number of trials has been reached */
+ if (I2C_Trials == Trials)
+ {
+ /* Generate Stop */
+ hi2c->Instance->CR2 |= I2C_CR2_STOP;
+
+ /* Wait until STOPF flag is reset */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+ }
+
+ /* Increment Trials */
+ I2C_Trials++;
+ } while (I2C_Trials < Trials);
+
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions)
+{
+ uint32_t xfermode;
+ uint32_t xferrequest = I2C_GENERATE_START_WRITE;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = XferOptions;
+ hi2c->XferISR = I2C_Master_ISR_IT;
+
+ /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = hi2c->XferOptions;
+ }
+
+ /* If transfer direction not change and there is no request to start another frame,
+ do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+ if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ {
+ xferrequest = I2C_NO_STARTSTOP;
+ }
+ else
+ {
+ /* Convert OTHER_xxx XferOptions if any */
+ I2C_ConvertOtherXferOptions(hi2c);
+
+ /* Update xfermode accordingly if no reload is necessary */
+ if (hi2c->XferCount <= MAX_NBYTE_SIZE)
+ {
+ xfermode = hi2c->XferOptions;
+ }
+ }
+
+ /* Send Slave Address and set NBYTES to write */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions)
+{
+ uint32_t xfermode;
+ uint32_t xferrequest = I2C_GENERATE_START_WRITE;
+ HAL_StatusTypeDef dmaxferstatus;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = XferOptions;
+ hi2c->XferISR = I2C_Master_ISR_DMA;
+
+ /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = hi2c->XferOptions;
+ }
+
+ /* If transfer direction not change and there is no request to start another frame,
+ do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+ if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ {
+ xferrequest = I2C_NO_STARTSTOP;
+ }
+ else
+ {
+ /* Convert OTHER_xxx XferOptions if any */
+ I2C_ConvertOtherXferOptions(hi2c);
+
+ /* Update xfermode accordingly if no reload is necessary */
+ if (hi2c->XferCount <= MAX_NBYTE_SIZE)
+ {
+ xfermode = hi2c->XferOptions;
+ }
+ }
+
+ if (hi2c->XferSize > 0U)
+ {
+ if (hi2c->hdmatx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if (hi2c->hdmatx->LinkedListQueue != NULL)
+ {
+ /* Set DMA data size */
+ hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
+
+ /* Set DMA source address */
+ hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
+
+ /* Set DMA destination address */
+ hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \
+ = (uint32_t)&hi2c->Instance->TXDR;
+
+ dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
+ hi2c->XferSize);
+ }
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Send Slave Address and set NBYTES to write */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Update Transfer ISR function pointer */
+ hi2c->XferISR = I2C_Master_ISR_IT;
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and generate START condition */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions)
+{
+ uint32_t xfermode;
+ uint32_t xferrequest = I2C_GENERATE_START_READ;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = XferOptions;
+ hi2c->XferISR = I2C_Master_ISR_IT;
+
+ /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = hi2c->XferOptions;
+ }
+
+ /* If transfer direction not change and there is no request to start another frame,
+ do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+ if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ {
+ xferrequest = I2C_NO_STARTSTOP;
+ }
+ else
+ {
+ /* Convert OTHER_xxx XferOptions if any */
+ I2C_ConvertOtherXferOptions(hi2c);
+
+ /* Update xfermode accordingly if no reload is necessary */
+ if (hi2c->XferCount <= MAX_NBYTE_SIZE)
+ {
+ xfermode = hi2c->XferOptions;
+ }
+ }
+
+ /* Send Slave Address and set NBYTES to read */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions)
+{
+ uint32_t xfermode;
+ uint32_t xferrequest = I2C_GENERATE_START_READ;
+ HAL_StatusTypeDef dmaxferstatus;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = XferOptions;
+ hi2c->XferISR = I2C_Master_ISR_DMA;
+
+ /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = hi2c->XferOptions;
+ }
+
+ /* If transfer direction not change and there is no request to start another frame,
+ do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+ if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ {
+ xferrequest = I2C_NO_STARTSTOP;
+ }
+ else
+ {
+ /* Convert OTHER_xxx XferOptions if any */
+ I2C_ConvertOtherXferOptions(hi2c);
+
+ /* Update xfermode accordingly if no reload is necessary */
+ if (hi2c->XferCount <= MAX_NBYTE_SIZE)
+ {
+ xfermode = hi2c->XferOptions;
+ }
+ }
+
+ if (hi2c->XferSize > 0U)
+ {
+ if (hi2c->hdmarx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if (hi2c->hdmarx->LinkedListQueue != NULL)
+ {
+ /* Set DMA data size */
+ hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
+
+ /* Set DMA source address */
+ hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \
+ = (uint32_t)&hi2c->Instance->RXDR;
+
+ /* Set DMA destination address */
+ hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
+
+ dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
+ }
+ else
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
+ hi2c->XferSize);
+ }
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Send Slave Address and set NBYTES to read */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Update Transfer ISR function pointer */
+ hi2c->XferISR = I2C_Master_ISR_IT;
+
+ /* Send Slave Address */
+ /* Set NBYTES to read and generate START condition */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+ /* and then toggle the HAL slave RX state to TX state */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+ {
+ /* Disable associated Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+ /* Abort DMA Xfer if any */
+ if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+ {
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+ if (hi2c->hdmarx != NULL)
+ {
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+ }
+ }
+ }
+ }
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = XferOptions;
+ hi2c->XferISR = I2C_Slave_ISR_IT;
+
+ if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+ {
+ /* Clear ADDR flag after prepare the transfer parameters */
+ /* This action will generate an acknowledge to the Master */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* REnable ADDR interrupt */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions)
+{
+ HAL_StatusTypeDef dmaxferstatus;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+
+ /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+ /* and then toggle the HAL slave RX state to TX state */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+ {
+ /* Disable associated Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+ if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+ {
+ /* Abort DMA Xfer if any */
+ if (hi2c->hdmarx != NULL)
+ {
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+ }
+ }
+ }
+ }
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+ {
+ if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+ {
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+ /* Abort DMA Xfer if any */
+ if (hi2c->hdmatx != NULL)
+ {
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+ }
+ }
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = XferOptions;
+ hi2c->XferISR = I2C_Slave_ISR_DMA;
+
+ if (hi2c->hdmatx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if (hi2c->hdmatx->LinkedListQueue != NULL)
+ {
+ /* Set DMA data size */
+ hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
+
+ /* Set DMA source address */
+ hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
+
+ /* Set DMA destination address */
+ hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \
+ = (uint32_t)&hi2c->Instance->TXDR;
+
+ dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
+ hi2c->XferSize);
+ }
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Reset XferSize */
+ hi2c->XferSize = 0;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+ {
+ /* Clear ADDR flag after prepare the transfer parameters */
+ /* This action will generate an acknowledge to the Master */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, STOP, NACK, ADDR interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+ /* and then toggle the HAL slave TX state to RX state */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+ {
+ /* Disable associated Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+ if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+ {
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+ /* Abort DMA Xfer if any */
+ if (hi2c->hdmatx != NULL)
+ {
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+ }
+ }
+ }
+ }
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = XferOptions;
+ hi2c->XferISR = I2C_Slave_ISR_IT;
+
+ if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
+ {
+ /* Clear ADDR flag after prepare the transfer parameters */
+ /* This action will generate an acknowledge to the Master */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* REnable ADDR interrupt */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions)
+{
+ HAL_StatusTypeDef dmaxferstatus;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+ /* and then toggle the HAL slave TX state to RX state */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+ {
+ /* Disable associated Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+ if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+ {
+ /* Abort DMA Xfer if any */
+ if (hi2c->hdmatx != NULL)
+ {
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+ }
+ }
+ }
+ }
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+ {
+ if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+ {
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+ /* Abort DMA Xfer if any */
+ if (hi2c->hdmarx != NULL)
+ {
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+ }
+ }
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = XferOptions;
+ hi2c->XferISR = I2C_Slave_ISR_DMA;
+
+ if (hi2c->hdmarx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if (hi2c->hdmarx->LinkedListQueue != NULL)
+ {
+ /* Set DMA data size */
+ hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
+
+ /* Set DMA source address */
+ hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \
+ = (uint32_t)&hi2c->Instance->RXDR;
+
+ /* Set DMA destination address */
+ hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
+
+ dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
+ hi2c->XferSize);
+ }
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Reset XferSize */
+ hi2c->XferSize = 0;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
+ {
+ /* Clear ADDR flag after prepare the transfer parameters */
+ /* This action will generate an acknowledge to the Master */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* REnable ADDR interrupt */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Enable the Address listen mode with Interrupt.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
+{
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->XferISR = I2C_Slave_ISR_IT;
+
+ /* Enable the Address Match interrupt */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Disable the Address listen mode with Interrupt.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
+{
+ /* Declaration of tmp to prevent undefined behavior of volatile usage */
+ uint32_t tmp;
+
+ /* Disable Address listen mode only if a transfer is not ongoing */
+ if (hi2c->State == HAL_I2C_STATE_LISTEN)
+ {
+ tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
+ hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->XferISR = NULL;
+
+ /* Disable the Address Match interrupt */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Abort a master I2C IT or DMA process communication with Interrupt.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
+{
+ if (hi2c->Mode == HAL_I2C_MODE_MASTER)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Disable Interrupts and Store Previous state */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+ }
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ }
+ else
+ {
+ /* Do nothing */
+ }
+
+ /* Set State at HAL_I2C_STATE_ABORT */
+ hi2c->State = HAL_I2C_STATE_ABORT;
+
+ /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
+ /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
+ I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Wrong usage of abort function */
+ /* This function should be used only in case of abort monitored by master device */
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+
+/**
+ * @brief This function handles I2C event interrupt request.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
+{
+ /* Get current IT Flags and IT sources value */
+ uint32_t itflags = READ_REG(hi2c->Instance->ISR);
+ uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+
+ /* I2C events treatment -------------------------------------*/
+ if (hi2c->XferISR != NULL)
+ {
+ hi2c->XferISR(hi2c, itflags, itsources);
+ }
+}
+
+/**
+ * @brief This function handles I2C error interrupt request.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
+{
+ uint32_t itflags = READ_REG(hi2c->Instance->ISR);
+ uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+ uint32_t tmperror;
+
+ /* I2C Bus error interrupt occurred ------------------------------------*/
+ if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
+
+ /* Clear BERR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
+ }
+
+ /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
+ if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
+
+ /* Clear OVR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
+ }
+
+ /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
+ if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
+
+ /* Clear ARLO flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
+ }
+
+ /* Store current volatile hi2c->ErrorCode, misra rule */
+ tmperror = hi2c->ErrorCode;
+
+ /* Call the Error Callback in case of Error detected */
+ if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)
+ {
+ I2C_ITError(hi2c, tmperror);
+ }
+}
+
+/**
+ * @brief Master Tx Transfer completed callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Master Rx Transfer completed callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
+ */
+}
+
+/** @brief Slave Tx Transfer completed callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Slave Rx Transfer completed callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Slave Address Match callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
+ * @param AddrMatchCode Address Match Code
+ * @retval None
+ */
+__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+ UNUSED(TransferDirection);
+ UNUSED(AddrMatchCode);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_AddrCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Listen Complete callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_ListenCpltCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Memory Tx Transfer completed callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_MemTxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Memory Rx Transfer completed callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_MemRxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C error callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C abort callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_AbortCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
+ * @brief Peripheral State, Mode and Error functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State, Mode and Error functions #####
+ ===============================================================================
+ [..]
+ This subsection permit to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the I2C handle state.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL state
+ */
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
+{
+ /* Return I2C handle state */
+ return hi2c->State;
+}
+
+/**
+ * @brief Returns the I2C Master, Slave, Memory or no mode.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
+ * @retval HAL mode
+ */
+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
+{
+ return hi2c->Mode;
+}
+
+/**
+ * @brief Return the I2C error code.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval I2C Error Code
+ */
+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
+{
+ return hi2c->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param ITFlags Interrupt flags to handle.
+ * @param ITSources Interrupt sources enabled.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+{
+ uint16_t devaddress;
+ uint32_t tmpITFlags = ITFlags;
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Set corresponding Error Code */
+ /* No need to generate STOP, it is automatically done */
+ /* Error callback will be send during stop flag treatment */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+ }
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+ {
+ /* Remove RXNE flag on temporary variable as read done */
+ tmpITFlags &= ~I2C_FLAG_RXNE;
+
+ /* Read data from RXDR */
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+ {
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ {
+ if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+ {
+ devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+ {
+ I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ }
+ }
+ }
+ else
+ {
+ /* Call TxCpltCallback() if no stop mode is set */
+ if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+ {
+ /* Call I2C Master Sequential complete process */
+ I2C_ITMasterSeqCplt(hi2c);
+ }
+ else
+ {
+ /* Wrong size Status regarding TCR flag event */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+ }
+ }
+ }
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ {
+ if (hi2c->XferCount == 0U)
+ {
+ if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+ {
+ /* Generate a stop condition in case of no transfer option */
+ if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
+ {
+ /* Generate Stop */
+ hi2c->Instance->CR2 |= I2C_CR2_STOP;
+ }
+ else
+ {
+ /* Call I2C Master Sequential complete process */
+ I2C_ITMasterSeqCplt(hi2c);
+ }
+ }
+ }
+ else
+ {
+ /* Wrong size Status regarding TC flag event */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ {
+ /* Call I2C Master complete process */
+ I2C_ITMasterCplt(hi2c, tmpITFlags);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param ITFlags Interrupt flags to handle.
+ * @param ITSources Interrupt sources enabled.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+{
+ uint32_t tmpoptions = hi2c->XferOptions;
+ uint32_t tmpITFlags = ITFlags;
+
+ /* Process locked */
+ __HAL_LOCK(hi2c);
+
+ /* Check if STOPF is set */
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ {
+ /* Call I2C Slave complete process */
+ I2C_ITSlaveCplt(hi2c, tmpITFlags);
+ }
+
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ {
+ /* Check that I2C transfer finished */
+ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+ /* Mean XferCount == 0*/
+ /* So clear Flag NACKF only */
+ if (hi2c->XferCount == 0U)
+ {
+ if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
+ /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+ Warning[Pa134]: left and right operands are identical */
+ {
+ /* Call I2C Listen complete process */
+ I2C_ITListenCplt(hi2c, tmpITFlags);
+ }
+ else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
+ /* Last Byte is Transmitted */
+ /* Call I2C Slave Sequential complete process */
+ I2C_ITSlaveSeqCplt(hi2c);
+ }
+ else
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ }
+ }
+ else
+ {
+ /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+ if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, hi2c->ErrorCode);
+ }
+ }
+ }
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+ {
+ if (hi2c->XferCount > 0U)
+ {
+ /* Read data from RXDR */
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+
+ if ((hi2c->XferCount == 0U) && \
+ (tmpoptions != I2C_NO_OPTION_FRAME))
+ {
+ /* Call I2C Slave Sequential complete process */
+ I2C_ITSlaveSeqCplt(hi2c);
+ }
+ }
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
+ {
+ I2C_ITAddrCplt(hi2c, tmpITFlags);
+ }
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+ {
+ /* Write data to TXDR only if XferCount not reach "0" */
+ /* A TXIS flag can be set, during STOP treatment */
+ /* Check if all Data have already been sent */
+ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
+ if (hi2c->XferCount > 0U)
+ {
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ hi2c->XferCount--;
+ hi2c->XferSize--;
+ }
+ else
+ {
+ if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
+ {
+ /* Last Byte is Transmitted */
+ /* Call I2C Slave Sequential complete process */
+ I2C_ITSlaveSeqCplt(hi2c);
+ }
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param ITFlags Interrupt flags to handle.
+ * @param ITSources Interrupt sources enabled.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+{
+ uint16_t devaddress;
+ uint32_t xfermode;
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Set corresponding Error Code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+ /* No need to generate STOP, it is automatically done */
+ /* But enable STOP interrupt, to treat it */
+ /* Error callback will be send during stop flag treatment */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+ }
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ {
+ /* Disable TC interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
+
+ if (hi2c->XferCount != 0U)
+ {
+ /* Recover Slave address */
+ devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
+
+ /* Prepare the new XferSize to transfer */
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+ {
+ xfermode = hi2c->XferOptions;
+ }
+ else
+ {
+ xfermode = I2C_AUTOEND_MODE;
+ }
+ }
+
+ /* Set the new XferSize in Nbytes register */
+ I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Enable DMA Request */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ }
+ }
+ else
+ {
+ /* Call TxCpltCallback() if no stop mode is set */
+ if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+ {
+ /* Call I2C Master Sequential complete process */
+ I2C_ITMasterSeqCplt(hi2c);
+ }
+ else
+ {
+ /* Wrong size Status regarding TCR flag event */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+ }
+ }
+ }
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ {
+ if (hi2c->XferCount == 0U)
+ {
+ if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+ {
+ /* Generate a stop condition in case of no transfer option */
+ if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
+ {
+ /* Generate Stop */
+ hi2c->Instance->CR2 |= I2C_CR2_STOP;
+ }
+ else
+ {
+ /* Call I2C Master Sequential complete process */
+ I2C_ITMasterSeqCplt(hi2c);
+ }
+ }
+ }
+ else
+ {
+ /* Wrong size Status regarding TC flag event */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+ }
+ }
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ {
+ /* Call I2C Master complete process */
+ I2C_ITMasterCplt(hi2c, ITFlags);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param ITFlags Interrupt flags to handle.
+ * @param ITSources Interrupt sources enabled.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+{
+ uint32_t tmpoptions = hi2c->XferOptions;
+ uint32_t treatdmanack = 0U;
+ HAL_I2C_StateTypeDef tmpstate;
+
+ /* Process locked */
+ __HAL_LOCK(hi2c);
+
+ /* Check if STOPF is set */
+ if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ {
+ /* Call I2C Slave complete process */
+ I2C_ITSlaveCplt(hi2c, ITFlags);
+ }
+
+ if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ {
+ /* Check that I2C transfer finished */
+ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+ /* Mean XferCount == 0 */
+ /* So clear Flag NACKF only */
+ if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
+ {
+ /* Split check of hdmarx, for MISRA compliance */
+ if (hi2c->hdmarx != NULL)
+ {
+ if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
+ {
+ if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U)
+ {
+ treatdmanack = 1U;
+ }
+ }
+ }
+
+ /* Split check of hdmatx, for MISRA compliance */
+ if (hi2c->hdmatx != NULL)
+ {
+ if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
+ {
+ if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U)
+ {
+ treatdmanack = 1U;
+ }
+ }
+ }
+
+ if (treatdmanack == 1U)
+ {
+ if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
+ /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+ Warning[Pa134]: left and right operands are identical */
+ {
+ /* Call I2C Listen complete process */
+ I2C_ITListenCplt(hi2c, ITFlags);
+ }
+ else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
+ /* Last Byte is Transmitted */
+ /* Call I2C Slave Sequential complete process */
+ I2C_ITSlaveSeqCplt(hi2c);
+ }
+ else
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ }
+ }
+ else
+ {
+ /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+ /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
+ tmpstate = hi2c->State;
+
+ if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
+ {
+ if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
+ {
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+ }
+ else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+ {
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+ }
+ else
+ {
+ /* Do nothing */
+ }
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, hi2c->ErrorCode);
+ }
+ }
+ }
+ else
+ {
+ /* Only Clear NACK Flag, no DMA treatment is pending */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ }
+ }
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
+ {
+ I2C_ITAddrCplt(hi2c, ITFlags);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Master sends target device address followed by internal memory address for write request.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param Timeout Timeout duration
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
+{
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
+
+ /* Wait until TXIS flag is set */
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* If Memory address size is 8Bit */
+ if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
+ {
+ /* Send Memory Address */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+ }
+ /* If Memory address size is 16Bit */
+ else
+ {
+ /* Send MSB of Memory Address */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+ /* Wait until TXIS flag is set */
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Send LSB of Memory Address */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+ }
+
+ /* Wait until TCR flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Master sends target device address followed by internal memory address for read request.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param Timeout Timeout duration
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
+{
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
+
+ /* Wait until TXIS flag is set */
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* If Memory address size is 8Bit */
+ if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
+ {
+ /* Send Memory Address */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+ }
+ /* If Memory address size is 16Bit */
+ else
+ {
+ /* Send MSB of Memory Address */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+ /* Wait until TXIS flag is set */
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Send LSB of Memory Address */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+ }
+
+ /* Wait until TC flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief I2C Address complete process callback.
+ * @param hi2c I2C handle.
+ * @param ITFlags Interrupt flags to handle.
+ * @retval None
+ */
+static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+ uint8_t transferdirection;
+ uint16_t slaveaddrcode;
+ uint16_t ownadd1code;
+ uint16_t ownadd2code;
+
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(ITFlags);
+
+ /* In case of Listen state, need to inform upper layer of address match code event */
+ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+ {
+ transferdirection = I2C_GET_DIR(hi2c);
+ slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c);
+ ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c);
+ ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c);
+
+ /* If 10bits addressing mode is selected */
+ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+ {
+ if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK))
+ {
+ slaveaddrcode = ownadd1code;
+ hi2c->AddrEventCount++;
+ if (hi2c->AddrEventCount == 2U)
+ {
+ /* Reset Address Event counter */
+ hi2c->AddrEventCount = 0U;
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call Slave Addr callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#else
+ HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+ }
+ else
+ {
+ slaveaddrcode = ownadd2code;
+
+ /* Disable ADDR Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call Slave Addr callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#else
+ HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+ }
+ /* else 7 bits addressing mode is selected */
+ else
+ {
+ /* Disable ADDR Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call Slave Addr callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#else
+ HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+ }
+ /* Else clear address flag only */
+ else
+ {
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ }
+}
+
+/**
+ * @brief I2C Master sequential complete process.
+ * @param hi2c I2C handle.
+ * @retval None
+ */
+static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
+{
+ /* Reset I2C handle mode */
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* No Generate Stop, to permit restart mode */
+ /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+ hi2c->XferISR = NULL;
+
+ /* Disable Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->MasterTxCpltCallback(hi2c);
+#else
+ HAL_I2C_MasterTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+ /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
+ else
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ hi2c->XferISR = NULL;
+
+ /* Disable Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->MasterRxCpltCallback(hi2c);
+#else
+ HAL_I2C_MasterRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief I2C Slave sequential complete process.
+ * @param hi2c I2C handle.
+ * @retval None
+ */
+static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
+{
+ uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
+
+ /* Reset I2C handle mode */
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* If a DMA is ongoing, Update handle size context */
+ if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
+ {
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+ }
+ else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
+ {
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ /* Do nothing */
+ }
+
+ if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+ {
+ /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+
+ /* Disable Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->SlaveTxCpltCallback(hi2c);
+#else
+ HAL_I2C_SlaveTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+ {
+ /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+
+ /* Disable Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->SlaveRxCpltCallback(hi2c);
+#else
+ HAL_I2C_SlaveRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+}
+
+/**
+ * @brief I2C Master complete process.
+ * @param hi2c I2C handle.
+ * @param ITFlags Interrupt flags to handle.
+ * @retval None
+ */
+static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+ uint32_t tmperror;
+ uint32_t tmpITFlags = ITFlags;
+ __IO uint32_t tmp;
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Disable Interrupts and Store Previous state */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+ }
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ }
+ else
+ {
+ /* Do nothing */
+ }
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ /* Reset handle parameters */
+ hi2c->XferISR = NULL;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+
+ if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Set acknowledge error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+
+ /* Fetch Last receive data if any */
+ if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
+ {
+ /* Read data from RXDR */
+ tmp = (uint8_t)hi2c->Instance->RXDR;
+
+ UNUSED(tmp);
+ }
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
+ /* Store current volatile hi2c->ErrorCode, misra rule */
+ tmperror = hi2c->ErrorCode;
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE))
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, hi2c->ErrorCode);
+ }
+ /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
+
+ if (hi2c->Mode == HAL_I2C_MODE_MEM)
+ {
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->MemTxCpltCallback(hi2c);
+#else
+ HAL_I2C_MemTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->MasterTxCpltCallback(hi2c);
+#else
+ HAL_I2C_MasterTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+ }
+ /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
+
+ if (hi2c->Mode == HAL_I2C_MODE_MEM)
+ {
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->MemRxCpltCallback(hi2c);
+#else
+ HAL_I2C_MemRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->MasterRxCpltCallback(hi2c);
+#else
+ HAL_I2C_MasterRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+}
+
+/**
+ * @brief I2C Slave complete process.
+ * @param hi2c I2C handle.
+ * @param ITFlags Interrupt flags to handle.
+ * @retval None
+ */
+static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+ uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
+ uint32_t tmpITFlags = ITFlags;
+ HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Disable Interrupts and Store Previous state */
+ if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+ }
+ else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+ }
+ else
+ {
+ /* Do nothing */
+ }
+
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
+ /* If a DMA is ongoing, Update handle size context */
+ if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
+ {
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+ if (hi2c->hdmatx != NULL)
+ {
+ hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx);
+ }
+ }
+ else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
+ {
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+ if (hi2c->hdmarx != NULL)
+ {
+ hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx);
+ }
+ }
+ else
+ {
+ /* Do nothing */
+ }
+
+ /* Store Last receive data if any */
+ if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)
+ {
+ /* Remove RXNE flag on temporary variable as read done */
+ tmpITFlags &= ~I2C_FLAG_RXNE;
+
+ /* Read data from RXDR */
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ if ((hi2c->XferSize > 0U))
+ {
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+ }
+
+ /* All data are not transferred, so set error code accordingly */
+ if (hi2c->XferCount != 0U)
+ {
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->XferISR = NULL;
+
+ if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, hi2c->ErrorCode);
+
+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+ if (hi2c->State == HAL_I2C_STATE_LISTEN)
+ {
+ /* Call I2C Listen complete process */
+ I2C_ITListenCplt(hi2c, tmpITFlags);
+ }
+ }
+ else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+ {
+ /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */
+ I2C_ITSlaveSeqCplt(hi2c);
+
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->ListenCpltCallback(hi2c);
+#else
+ HAL_I2C_ListenCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->SlaveRxCpltCallback(hi2c);
+#else
+ HAL_I2C_SlaveRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->SlaveTxCpltCallback(hi2c);
+#else
+ HAL_I2C_SlaveTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief I2C Listen complete process.
+ * @param hi2c I2C handle.
+ * @param ITFlags Interrupt flags to handle.
+ * @retval None
+ */
+static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+ /* Reset handle parameters */
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->XferISR = NULL;
+
+ /* Store Last receive data if any */
+ if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)
+ {
+ /* Read data from RXDR */
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ if ((hi2c->XferSize > 0U))
+ {
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+ }
+
+ /* Disable all Interrupts*/
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->ListenCpltCallback(hi2c);
+#else
+ HAL_I2C_ListenCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief I2C interrupts error process.
+ * @param hi2c I2C handle.
+ * @param ErrorCode Error code to handle.
+ * @retval None
+ */
+static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
+{
+ HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+ uint32_t tmppreviousstate;
+
+ /* Reset handle parameters */
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferCount = 0U;
+
+ /* Set new error code */
+ hi2c->ErrorCode |= ErrorCode;
+
+ /* Disable Interrupts */
+ if ((tmpstate == HAL_I2C_STATE_LISTEN) ||
+ (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
+ (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+ {
+ /* Disable all interrupts, except interrupts related to LISTEN state */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+
+ /* keep HAL_I2C_STATE_LISTEN if set */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->XferISR = I2C_Slave_ISR_IT;
+ }
+ else
+ {
+ /* Disable all interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+
+ /* If state is an abort treatment on going, don't change state */
+ /* This change will be do later */
+ if (hi2c->State != HAL_I2C_STATE_ABORT)
+ {
+ /* Set HAL_I2C_STATE_READY */
+ hi2c->State = HAL_I2C_STATE_READY;
+ }
+ hi2c->XferISR = NULL;
+ }
+
+ /* Abort DMA TX transfer if any */
+ tmppreviousstate = hi2c->PreviousState;
+ if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
+ (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
+ {
+ if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+ {
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+ }
+
+ if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
+ {
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+ }
+ }
+ else
+ {
+ I2C_TreatErrorCallback(hi2c);
+ }
+ }
+ /* Abort DMA RX transfer if any */
+ else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \
+ (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
+ {
+ if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+ {
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+ }
+
+ if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
+ {
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+ {
+ /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
+ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+ }
+ }
+ else
+ {
+ I2C_TreatErrorCallback(hi2c);
+ }
+ }
+ else
+ {
+ I2C_TreatErrorCallback(hi2c);
+ }
+}
+
+/**
+ * @brief I2C Error callback treatment.
+ * @param hi2c I2C handle.
+ * @retval None
+ */
+static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
+{
+ if (hi2c->State == HAL_I2C_STATE_ABORT)
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->AbortCpltCallback(hi2c);
+#else
+ HAL_I2C_AbortCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->ErrorCallback(hi2c);
+#else
+ HAL_I2C_ErrorCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief I2C Tx data register flush process.
+ * @param hi2c I2C handle.
+ * @retval None
+ */
+static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
+{
+ /* If a pending TXIS flag is set */
+ /* Write a dummy data in TXDR to clear it */
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
+ {
+ hi2c->Instance->TXDR = 0x00U;
+ }
+
+ /* Flush TX register if not empty */
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
+ {
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
+ }
+}
+
+/**
+ * @brief DMA I2C master transmit process complete callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ HAL_StatusTypeDef dmaxferstatus = HAL_OK;
+ /* Derogation MISRAC2012-Rule-11.5 */
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+ /* If last transfer, enable STOP interrupt */
+ if (hi2c->XferCount == 0U)
+ {
+ /* Enable STOP interrupt */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+ }
+ /* else prepare a new DMA transfer and enable TCReload interrupt */
+ else
+ {
+ /* Update Buffer pointer */
+ hi2c->pBuffPtr += hi2c->XferSize;
+
+ /* Set the XferSize to transfer */
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ }
+
+ /* Enable the DMA channel */
+ if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if (hi2c->hdmatx->LinkedListQueue != NULL)
+ {
+ /* Set DMA data size */
+ hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
+
+ /* Set DMA source address */
+ hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hi2c->pBuffPtr;
+
+ /* Set DMA destination address */
+ hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hi2c->Instance->TXDR;
+
+ dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
+ }
+ else
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+ }
+ }
+ else
+ {
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
+ hi2c->XferSize);
+ }
+
+ if (dmaxferstatus != HAL_OK)
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+ }
+ else
+ {
+ /* Enable TC interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
+ }
+ }
+}
+
+/**
+ * @brief DMA I2C slave transmit process complete callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Derogation MISRAC2012-Rule-11.5 */
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+ uint32_t tmpoptions = hi2c->XferOptions;
+
+ if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
+ {
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+ /* Last Byte is Transmitted */
+ /* Call I2C Slave Sequential complete process */
+ I2C_ITSlaveSeqCplt(hi2c);
+ }
+ else
+ {
+ /* No specific action, Master fully manage the generation of STOP condition */
+ /* Mean that this generation can arrive at any time, at the end or during DMA process */
+ /* So STOP condition should be manage through Interrupt treatment */
+ }
+}
+
+/**
+ * @brief DMA I2C master receive process complete callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ HAL_StatusTypeDef dmaxferstatus = HAL_OK;
+ /* Derogation MISRAC2012-Rule-11.5 */
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+ /* If last transfer, enable STOP interrupt */
+ if (hi2c->XferCount == 0U)
+ {
+ /* Enable STOP interrupt */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+ }
+ /* else prepare a new DMA transfer and enable TCReload interrupt */
+ else
+ {
+ /* Update Buffer pointer */
+ hi2c->pBuffPtr += hi2c->XferSize;
+
+ /* Set the XferSize to transfer */
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ }
+
+ /* Enable the DMA channel */
+ if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if (hi2c->hdmarx->LinkedListQueue != NULL)
+ {
+ /* Set DMA data size */
+ hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
+
+ /* Set DMA source address */
+ hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hi2c->Instance->RXDR;
+
+ /* Set DMA destination address */
+ hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hi2c->pBuffPtr;
+
+ dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
+ }
+ else
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+ }
+ }
+ else
+ {
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr,
+ hi2c->XferSize);
+ }
+
+ if (dmaxferstatus != HAL_OK)
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+ }
+ else
+ {
+ /* Enable TC interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
+ }
+ }
+}
+
+/**
+ * @brief DMA I2C slave receive process complete callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Derogation MISRAC2012-Rule-11.5 */
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+ uint32_t tmpoptions = hi2c->XferOptions;
+
+ if ((__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) && \
+ (tmpoptions != I2C_NO_OPTION_FRAME))
+ {
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+ /* Call I2C Slave Sequential complete process */
+ I2C_ITSlaveSeqCplt(hi2c);
+ }
+ else
+ {
+ /* No specific action, Master fully manage the generation of STOP condition */
+ /* Mean that this generation can arrive at any time, at the end or during DMA process */
+ /* So STOP condition should be manage through Interrupt treatment */
+ }
+}
+
+/**
+ * @brief DMA I2C communication error callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void I2C_DMAError(DMA_HandleTypeDef *hdma)
+{
+ /* Derogation MISRAC2012-Rule-11.5 */
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+
+ /* Disable Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+}
+
+/**
+ * @brief DMA I2C communication abort callback
+ * (To be called at end of DMA Abort procedure).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
+{
+ /* Derogation MISRAC2012-Rule-11.5 */
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+
+ /* Reset AbortCpltCallback */
+ if (hi2c->hdmatx != NULL)
+ {
+ hi2c->hdmatx->XferAbortCallback = NULL;
+ }
+ if (hi2c->hdmarx != NULL)
+ {
+ hi2c->hdmarx->XferAbortCallback = NULL;
+ }
+
+ I2C_TreatErrorCallback(hi2c);
+}
+
+/**
+ * @brief This function handles I2C Communication Timeout.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param Flag Specifies the I2C flag to check.
+ * @param Status The new Flag status (SET or RESET).
+ * @param Timeout Timeout duration
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
+ uint32_t Timeout, uint32_t Tickstart)
+{
+ while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param Timeout Timeout duration
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
+ {
+ /* Check if an error is detected */
+ if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param Timeout Timeout duration
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+ {
+ /* Check if an error is detected */
+ if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check for the Timeout */
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param Timeout Timeout duration
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
+ {
+ /* Check if an error is detected */
+ if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check if a STOPF is detected */
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
+ {
+ /* Check if an RXNE is pending */
+ /* Store Last receive data if any */
+ if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))
+ {
+ /* Return HAL_OK */
+ /* The Reading of data from RXDR will be done in caller function */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Check for the Timeout */
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles errors detection during an I2C Communication.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param Timeout Timeout duration
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t itflag = hi2c->Instance->ISR;
+ uint32_t error_code = 0;
+
+ if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF))
+ {
+ /* In case of Soft End condition, generate the STOP condition */
+ if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+ {
+ /* Generate Stop */
+ hi2c->Instance->CR2 |= I2C_CR2_STOP;
+ }
+
+ /* Wait until STOP Flag is set or timeout occurred */
+ /* AutoEnd should be initiate after AF */
+ while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+ {
+ error_code |= HAL_I2C_ERROR_TIMEOUT;
+
+ status = HAL_ERROR;
+ }
+ }
+ }
+
+ /* In case STOP Flag is detected, clear it */
+ if (status == HAL_OK)
+ {
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+ }
+
+ /* Clear NACKF Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ error_code |= HAL_I2C_ERROR_AF;
+
+ status = HAL_ERROR;
+ }
+
+ /* Refresh Content of Status register */
+ itflag = hi2c->Instance->ISR;
+
+ /* Then verify if an additionnal errors occurs */
+ /* Check if a Bus error occurred */
+ if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR))
+ {
+ error_code |= HAL_I2C_ERROR_BERR;
+
+ /* Clear BERR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
+
+ status = HAL_ERROR;
+ }
+
+ /* Check if an Over-Run/Under-Run error occurred */
+ if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR))
+ {
+ error_code |= HAL_I2C_ERROR_OVR;
+
+ /* Clear OVR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
+
+ status = HAL_ERROR;
+ }
+
+ /* Check if an Arbitration Loss error occurred */
+ if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO))
+ {
+ error_code |= HAL_I2C_ERROR_ARLO;
+
+ /* Clear ARLO flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
+
+ status = HAL_ERROR;
+ }
+
+ if (status != HAL_OK)
+ {
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ hi2c->ErrorCode |= error_code;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
+ * @param hi2c I2C handle.
+ * @param DevAddress Specifies the slave address to be programmed.
+ * @param Size Specifies the number of bytes to be programmed.
+ * This parameter must be a value between 0 and 255.
+ * @param Mode New state of the I2C START condition generation.
+ * This parameter can be one of the following values:
+ * @arg @ref I2C_RELOAD_MODE Enable Reload mode .
+ * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
+ * @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
+ * @param Request New state of the I2C START condition generation.
+ * This parameter can be one of the following values:
+ * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
+ * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
+ * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
+ * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
+ * @retval None
+ */
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
+ uint32_t Request)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+ assert_param(IS_TRANSFER_MODE(Mode));
+ assert_param(IS_TRANSFER_REQUEST(Request));
+
+ /* update CR2 register */
+ MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
+ (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
+ I2C_CR2_START | I2C_CR2_STOP)), \
+ (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
+ (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
+ (uint32_t)Mode | (uint32_t)Request));
+}
+
+/**
+ * @brief Manage the enabling of Interrupts.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
+ * @retval None
+ */
+static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
+{
+ uint32_t tmpisr = 0U;
+
+ if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \
+ (hi2c->XferISR == I2C_Slave_ISR_DMA))
+ {
+ if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+ {
+ /* Enable ERR, STOP, NACK and ADDR interrupts */
+ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+ }
+
+ if (InterruptRequest == I2C_XFER_ERROR_IT)
+ {
+ /* Enable ERR and NACK interrupts */
+ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
+ }
+
+ if (InterruptRequest == I2C_XFER_CPLT_IT)
+ {
+ /* Enable STOP interrupts */
+ tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
+ }
+
+ if (InterruptRequest == I2C_XFER_RELOAD_IT)
+ {
+ /* Enable TC interrupts */
+ tmpisr |= I2C_IT_TCI;
+ }
+ }
+ else
+ {
+ if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+ {
+ /* Enable ERR, STOP, NACK, and ADDR interrupts */
+ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+ }
+
+ if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+ {
+ /* Enable ERR, TC, STOP, NACK and RXI interrupts */
+ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
+ }
+
+ if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+ {
+ /* Enable ERR, TC, STOP, NACK and TXI interrupts */
+ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
+ }
+
+ if (InterruptRequest == I2C_XFER_CPLT_IT)
+ {
+ /* Enable STOP interrupts */
+ tmpisr |= I2C_IT_STOPI;
+ }
+ }
+
+ /* Enable interrupts only at the end */
+ /* to avoid the risk of I2C interrupt handle execution before */
+ /* all interrupts requested done */
+ __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
+}
+
+/**
+ * @brief Manage the disabling of Interrupts.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
+ * @retval None
+ */
+static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
+{
+ uint32_t tmpisr = 0U;
+
+ if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+ {
+ /* Disable TC and TXI interrupts */
+ tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
+
+ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
+ {
+ /* Disable NACK and STOP interrupts */
+ tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+ }
+ }
+
+ if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+ {
+ /* Disable TC and RXI interrupts */
+ tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
+
+ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
+ {
+ /* Disable NACK and STOP interrupts */
+ tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+ }
+ }
+
+ if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+ {
+ /* Disable ADDR, NACK and STOP interrupts */
+ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+ }
+
+ if (InterruptRequest == I2C_XFER_ERROR_IT)
+ {
+ /* Enable ERR and NACK interrupts */
+ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
+ }
+
+ if (InterruptRequest == I2C_XFER_CPLT_IT)
+ {
+ /* Enable STOP interrupts */
+ tmpisr |= I2C_IT_STOPI;
+ }
+
+ if (InterruptRequest == I2C_XFER_RELOAD_IT)
+ {
+ /* Enable TC interrupts */
+ tmpisr |= I2C_IT_TCI;
+ }
+
+ /* Disable interrupts only at the end */
+ /* to avoid a breaking situation like at "t" time */
+ /* all disable interrupts request are not done */
+ __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
+}
+
+/**
+ * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
+ * @param hi2c I2C handle.
+ * @retval None
+ */
+static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
+{
+ /* if user set XferOptions to I2C_OTHER_FRAME */
+ /* it request implicitly to generate a restart condition */
+ /* set XferOptions to I2C_FIRST_FRAME */
+ if (hi2c->XferOptions == I2C_OTHER_FRAME)
+ {
+ hi2c->XferOptions = I2C_FIRST_FRAME;
+ }
+ /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
+ /* it request implicitly to generate a restart condition */
+ /* then generate a stop condition at the end of transfer */
+ /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */
+ else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
+ {
+ hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_I2C_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c_ex.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c_ex.c
new file mode 100644
index 00000000..bb18de81
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c_ex.c
@@ -0,0 +1,498 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_i2c_ex.c
+ * @author MCD Application Team
+ * @brief I2C Extended HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of I2C Extended peripheral:
+ * + I2C Extended Filter Mode Functions
+ * + I2C Extended WakeUp Mode Functions
+ * + I2C I2C Extended FastModePlus Functions
+ * + I2C I2C Extended Autonomous Mode Functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### I2C peripheral Extended features #####
+ ==============================================================================
+
+ [..] Comparing to other previous devices, the I2C interface for STM32U5xx
+ devices contains the following additional features
+
+ (+) Possibility to disable or enable Analog Noise Filter
+ (+) Use of a configured Digital Noise Filter
+ (+) Disable or enable wakeup from Stop mode(s)
+ (+) Disable or enable Fast Mode Plus
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..] This driver provides functions to configure Noise Filter and Wake Up Feature
+ (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
+ (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
+ (#) Configure the enable or disable of I2C Wake Up Mode using the functions :
+ (++) HAL_I2CEx_EnableWakeUp()
+ (++) HAL_I2CEx_DisableWakeUp()
+ (#) Configure the enable or disable of fast mode plus driving capability using the functions :
+ (++) HAL_I2CEx_ConfigFastModePlus()
+ (#) Set or get or clear the autonomous mode configuration using these functions :
+ (++) HAL_I2CEx_SetConfigAutonomousMode()
+ (++) HAL_I2CEx_GetConfigAutonomousMode()
+ (++) HAL_I2CEx_ClearConfigAutonomousMode()
+ @endverbatim
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup I2CEx I2CEx
+ * @brief I2C Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup I2CEx_Exported_Functions_Group1 I2C Extended Filter Mode Functions
+ * @brief I2C Extended Filter Mode Functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended Noise Filters functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure Noise Filters
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure I2C Analog noise filter.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2Cx peripheral.
+ * @param AnalogFilter New state of the Analog filter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+ assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+
+ /* Disable the selected I2C peripheral */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /* Reset I2Cx ANOFF bit */
+ hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
+
+ /* Set analog filter bit*/
+ hi2c->Instance->CR1 |= AnalogFilter;
+
+ __HAL_I2C_ENABLE(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Configure I2C Digital noise filter.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2Cx peripheral.
+ * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
+{
+ uint32_t tmpreg;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+ assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+
+ /* Disable the selected I2C peripheral */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /* Get the old register value */
+ tmpreg = hi2c->Instance->CR1;
+
+ /* Reset I2Cx DNF bits [11:8] */
+ tmpreg &= ~(I2C_CR1_DNF);
+
+ /* Set I2Cx DNF coefficient */
+ tmpreg |= DigitalFilter << 8U;
+
+ /* Store the new register value */
+ hi2c->Instance->CR1 = tmpreg;
+
+ __HAL_I2C_ENABLE(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2CEx_Exported_Functions_Group2 I2C Extended WakeUp Mode Functions
+ * @brief I2C Extended WakeUp Mode Functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended WakeUp Mode functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure Wake Up Feature
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable I2C wakeup from Stop mode(s).
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2Cx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+
+ /* Disable the selected I2C peripheral */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /* Enable wakeup from stop mode */
+ hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
+
+ __HAL_I2C_ENABLE(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Disable I2C wakeup from Stop mode(s).
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2Cx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+
+ /* Disable the selected I2C peripheral */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /* Enable wakeup from stop mode */
+ hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
+
+ __HAL_I2C_ENABLE(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2CEx_Exported_Functions_Group3 I2C Extended FastModePlus Functions
+ * @brief I2C Extended FastModePlus Functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended FastModePlus functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure Fast Mode Plus
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure I2C Fast Mode Plus.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2Cx peripheral.
+ * @param FastModePlus New state of the Fast Mode Plus.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2CEx_ConfigFastModePlus(I2C_HandleTypeDef *hi2c, uint32_t FastModePlus)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+ assert_param(IS_I2C_FASTMODEPLUS(FastModePlus));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+
+ /* Disable the selected I2C peripheral */
+ __HAL_I2C_DISABLE(hi2c);
+
+ if (FastModePlus == I2C_FASTMODEPLUS_ENABLE)
+ {
+ /* Set I2Cx FMP bit */
+ hi2c->Instance->CR1 |= (I2C_CR1_FMP);
+ }
+ else
+ {
+ /* Reset I2Cx FMP bit */
+ hi2c->Instance->CR1 &= ~(I2C_CR1_FMP);
+ }
+
+ __HAL_I2C_ENABLE(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2CEx_Exported_Functions_Group4 I2C Extended Autonomous Mode Functions
+ * @brief I2C Extended Autonomous Mode Functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended Autonomous Mode functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure Autonomous Mode
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set Autonomous Mode configuration
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2Cx peripheral.
+ * @param sConfig Pointer to a I2C_AutonomousModeConfTypeDef structure that contains
+ * the configuration information of the autonomous mode for the specified I2Cx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2CEx_SetConfigAutonomousMode(I2C_HandleTypeDef *hi2c, I2C_AutonomousModeConfTypeDef *sConfig)
+{
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_TRIG_SOURCE(hi2c->Instance, sConfig->TriggerSelection));
+
+ assert_param(IS_I2C_AUTO_MODE_TRG_POL(sConfig->TriggerPolarity));
+
+ /* Disable the selected I2C peripheral to be able to configure AUTOCR */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /* I2Cx AUTOCR Configuration */
+ WRITE_REG(hi2c->Instance->AUTOCR, (sConfig->TriggerState | ((sConfig->TriggerSelection) & I2C_AUTOCR_TRIGSEL_Msk) |
+ sConfig->TriggerPolarity));
+
+ /* Enable the selected I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Get Autonomous Mode configuration
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2Cx peripheral.
+ * @param sConfig Pointer to a I2C_AutonomousModeConfTypeDef structure that contains
+ * the configuration information of the autonomous mode for the specified I2Cx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2CEx_GetConfigAutonomousMode(I2C_HandleTypeDef *hi2c, I2C_AutonomousModeConfTypeDef *sConfig)
+{
+ uint32_t autocr_tmp;
+
+ autocr_tmp = hi2c->Instance->AUTOCR;
+
+ sConfig->TriggerState = (autocr_tmp & I2C_AUTOCR_TRIGEN);
+ if (IS_I2C_GRP2_INSTANCE(hi2c->Instance))
+ {
+ sConfig->TriggerSelection = ((autocr_tmp & I2C_AUTOCR_TRIGSEL) | I2C_TRIG_GRP2);
+ }
+ else
+ {
+ sConfig->TriggerSelection = ((autocr_tmp & I2C_AUTOCR_TRIGSEL) | I2C_TRIG_GRP1);
+ }
+ sConfig->TriggerPolarity = (autocr_tmp & I2C_AUTOCR_TRIGPOL);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Clear Autonomous Mode configuration
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2Cx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2CEx_ClearConfigAutonomousMode(I2C_HandleTypeDef *hi2c)
+{
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+
+ /* Disable the selected I2C peripheral to be able to clear AUTOCR */
+ __HAL_I2C_DISABLE(hi2c);
+
+ CLEAR_REG(hi2c->Instance->AUTOCR);
+
+ /* Enable the selected I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_I2C_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_icache.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_icache.c
new file mode 100644
index 00000000..ce41ead3
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_icache.c
@@ -0,0 +1,641 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_icache.c
+ * @author MCD Application Team
+ * @brief ICACHE HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Instruction Cache (ICACHE).
+ * + Initialization and Configuration
+ * + Invalidate functions
+ * + Monitoring management
+ * + Memory address remap management
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### ICACHE main features #####
+ ==============================================================================
+ [..]
+ The Instruction Cache (ICACHE) is introduced on C-AHB code bus of
+ Cortex-M33 processor to improve performance when fetching instruction
+ and data from both internal and external memories. It allows close to
+ zero wait states performance.
+
+ (+) The ICACHE provides two performance counters (Hit and Miss),
+ cache invalidate maintenance operation, error management and TrustZone
+ security support.
+
+ (+) The ICACHE provides additionnaly the possibility to remap input address
+ falling into up to four memory regions (used to remap aliased code in
+ external memories to the internal Code region, for execution)
+
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ The ICACHE HAL driver can be used as follows:
+
+ (#) Enable and disable the Instruction Cache with respectively
+ @ref HAL_ICACHE_Enable() and @ref HAL_ICACHE_Disable()
+
+ (#) Configure the Instruction Cache mode with @ref HAL_ICACHE_ConfigAssociativityMode()
+
+ (#) Initiate the cache maintenance invalidation procedure with either
+ @ref HAL_ICACHE_Invalidate() (blocking mode) or @ref HAL_ICACHE_Invalidate_IT()
+ (interrupt mode). When interrupt mode is used, the callback function
+ @ref HAL_ICACHE_InvalidateCompleteCallback() is called when the invalidate
+ procedure is complete. The function @ref HAL_ICACHE_WaitForInvalidateComplete()
+ may be called to wait for the end of the invalidate procedure automatically
+ initiated when disabling the Instruction Cache with @ref HAL_ICACHE_Disable().
+ The cache operation is bypassed during the invalidation procedure.
+
+ (#) Use the performance monitoring counters for Hit and Miss with the following
+ functions: @ref HAL_ICACHE_Monitor_Start(), @ref HAL_ICACHE_Monitor_Stop(),
+ @ref HAL_ICACHE_Monitor_Reset(), @ref HAL_ICACHE_Monitor_GetHitValue() and
+ @ref HAL_ICACHE_Monitor_GetMissValue()
+
+ (#) Enable and disable up to four regions to remap input address from external
+ memories to the internal Code region for execution with
+ @ref HAL_ICACHE_EnableRemapRegion() and @ref HAL_ICACHE_DisableRemapRegion()
+
+ @endverbatim
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup ICACHE ICACHE
+ * @brief HAL ICACHE module driver
+ * @{
+ */
+#ifdef HAL_ICACHE_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup ICACHE_Private_Constants ICACHE Private Constants
+ * @{
+ */
+#define ICACHE_INVALIDATE_TIMEOUT_VALUE 1U /* 1ms */
+#define ICACHE_DISABLE_TIMEOUT_VALUE 1U /* 1ms */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup ICACHE_Private_Macros ICACHE Private Macros
+ * @{
+ */
+
+#define IS_ICACHE_ASSOCIATIVITY_MODE(__MODE__) (((__MODE__) == ICACHE_1WAY) || \
+ ((__MODE__) == ICACHE_2WAYS))
+
+#define IS_ICACHE_MONITOR_TYPE(__TYPE__) (((__TYPE__) == ICACHE_MONITOR_HIT_MISS) || \
+ ((__TYPE__) == ICACHE_MONITOR_HIT) || \
+ ((__TYPE__) == ICACHE_MONITOR_MISS))
+
+#define IS_ICACHE_REGION_NUMBER(__NUMBER__) ((__NUMBER__) < 4U)
+
+#define IS_ICACHE_REGION_SIZE(__SIZE__) (((__SIZE__) == ICACHE_REGIONSIZE_2MB) || \
+ ((__SIZE__) == ICACHE_REGIONSIZE_4MB) || \
+ ((__SIZE__) == ICACHE_REGIONSIZE_8MB) || \
+ ((__SIZE__) == ICACHE_REGIONSIZE_16MB) || \
+ ((__SIZE__) == ICACHE_REGIONSIZE_32MB) || \
+ ((__SIZE__) == ICACHE_REGIONSIZE_64MB) || \
+ ((__SIZE__) == ICACHE_REGIONSIZE_128MB))
+
+#define IS_ICACHE_REGION_TRAFFIC_ROUTE(__TRAFFICROUTE__) (((__TRAFFICROUTE__) == ICACHE_MASTER1_PORT) || \
+ ((__TRAFFICROUTE__) == ICACHE_MASTER2_PORT))
+
+#define IS_ICACHE_REGION_OUTPUT_BURST_TYPE(__OUTPUTBURSTTYPE_) (((__OUTPUTBURSTTYPE_) == ICACHE_OUTPUT_BURST_WRAP) || \
+ ((__OUTPUTBURSTTYPE_) == ICACHE_OUTPUT_BURST_INCR))
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup ICACHE_Exported_Functions ICACHE Exported Functions
+ * @{
+ */
+
+/** @defgroup ICACHE_Exported_Functions_Group1 Initialization and control functions
+ * @brief Initialization and control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### Initialization and control functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to initialize and control the
+ Instruction Cache (mode, invalidate procedure, performance counters).
+ @endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the Instruction Cache cache associativity mode selection.
+ * @param AssociativityMode Associativity mode selection
+ * This parameter can be one of the following values:
+ * @arg ICACHE_1WAY 1-way cache (direct mapped cache)
+ * @arg ICACHE_2WAYS 2-ways set associative cache (default)
+ * @retval HAL status (HAL_OK/HAL_ERROR)
+ */
+HAL_StatusTypeDef HAL_ICACHE_ConfigAssociativityMode(uint32_t AssociativityMode)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ICACHE_ASSOCIATIVITY_MODE(AssociativityMode));
+
+ /* Check cache is not enabled */
+ if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ MODIFY_REG(ICACHE->CR, ICACHE_CR_WAYSEL, AssociativityMode);
+ }
+
+ return status;
+}
+
+/**
+ * @brief DeInitialize the Instruction Cache.
+ * @retval HAL status (HAL_OK/HAL_TIMEOUT)
+ */
+HAL_StatusTypeDef HAL_ICACHE_DeInit(void)
+{
+ HAL_StatusTypeDef status;
+
+ /* Disable cache with reset value for 2-ways set associative mode */
+ WRITE_REG(ICACHE->CR, ICACHE_CR_WAYSEL);
+
+ /* Stop monitor and reset monitor values */
+ (void)HAL_ICACHE_Monitor_Stop(ICACHE_MONITOR_HIT_MISS);
+ (void)HAL_ICACHE_Monitor_Reset(ICACHE_MONITOR_HIT_MISS);
+
+ /* No remapped regions */
+ (void)HAL_ICACHE_DisableRemapRegion(ICACHE_REGION_0);
+ (void)HAL_ICACHE_DisableRemapRegion(ICACHE_REGION_1);
+ (void)HAL_ICACHE_DisableRemapRegion(ICACHE_REGION_2);
+ (void)HAL_ICACHE_DisableRemapRegion(ICACHE_REGION_3);
+
+ /* Wait for end of invalidate cache procedure */
+ status = HAL_ICACHE_WaitForInvalidateComplete();
+
+ /* Clear any pending flags */
+ WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF | ICACHE_FCR_CERRF);
+
+ return status;
+}
+
+/**
+ * @brief Enable the Instruction Cache.
+ * @note This function always returns HAL_OK even if there is any ongoing
+ * cache operation. The Instruction Cache is bypassed until the
+ * cache operation completes.
+ * @retval HAL status (HAL_OK)
+ */
+HAL_StatusTypeDef HAL_ICACHE_Enable(void)
+{
+ SET_BIT(ICACHE->CR, ICACHE_CR_EN);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the Instruction Cache.
+ * @note This function waits for the cache being disabled but
+ * not for the end of the automatic cache invalidation procedure.
+ * @retval HAL status (HAL_OK/HAL_TIMEOUT)
+ */
+HAL_StatusTypeDef HAL_ICACHE_Disable(void)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tickstart;
+
+ /* Reset BSYENDF before to disable the instruction cache */
+ /* that starts a cache invalidation procedure */
+ CLEAR_BIT(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
+
+ CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait for instruction cache being disabled */
+ while (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > ICACHE_DISABLE_TIMEOUT_VALUE)
+ {
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U)
+ {
+ status = HAL_TIMEOUT;
+ break;
+ }
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Invalidate the Instruction Cache.
+ * @note This function waits for the end of cache invalidation procedure
+ * and clears the associated BSYENDF flag.
+ * @retval HAL status (HAL_OK/HAL_ERROR/HAL_TIMEOUT)
+ */
+HAL_StatusTypeDef HAL_ICACHE_Invalidate(void)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check no ongoing operation */
+ if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Make sure BSYENDF is reset before to start cache invalidation */
+ CLEAR_BIT(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
+
+ /* Launch cache invalidation */
+ SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV);
+
+ status = HAL_ICACHE_WaitForInvalidateComplete();
+ }
+
+ return status;
+}
+
+/**
+ * @brief Invalidate the Instruction Cache with interrupt.
+ * @note This function launches cache invalidation and returns.
+ * User application shall resort to interrupt generation to check
+ * the end of the cache invalidation with the BSYENDF flag and the
+ * HAL_ICACHE_InvalidateCompleteCallback() callback.
+ * @retval HAL status (HAL_OK/HAL_ERROR)
+ */
+HAL_StatusTypeDef HAL_ICACHE_Invalidate_IT(void)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check no ongoing operation */
+ if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Make sure BSYENDF is reset */
+ WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
+
+ /* Enable end of cache invalidation interrupt */
+ SET_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);
+
+ /* Launch cache invalidation */
+ SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Wait for the end of the Instruction Cache invalidate procedure.
+ * @note This function checks and clears the BSYENDF flag when set.
+ * @retval HAL status (HAL_OK/HAL_TIMEOUT)
+ */
+HAL_StatusTypeDef HAL_ICACHE_WaitForInvalidateComplete(void)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tickstart;
+
+ /* Check if ongoing invalidation operation */
+ if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait for end of cache invalidation */
+ while (READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > ICACHE_INVALIDATE_TIMEOUT_VALUE)
+ {
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == 0U)
+ {
+ status = HAL_TIMEOUT;
+ break;
+ }
+ }
+ }
+ }
+
+ /* Clear BSYENDF */
+ WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
+
+ return status;
+}
+
+
+/**
+ * @brief Start the Instruction Cache performance monitoring.
+ * @param MonitorType Monitoring type
+ * This parameter can be one of the following values:
+ * @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring
+ * @arg ICACHE_MONITOR_HIT Hit monitoring
+ * @arg ICACHE_MONITOR_MISS Miss monitoring
+ * @retval HAL status (HAL_OK)
+ */
+HAL_StatusTypeDef HAL_ICACHE_Monitor_Start(uint32_t MonitorType)
+{
+ /* Check the parameters */
+ assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType));
+
+ SET_BIT(ICACHE->CR, MonitorType);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the Instruction Cache performance monitoring.
+ * @note Stopping the monitoring does not reset the values.
+ * @param MonitorType Monitoring type
+ * This parameter can be one of the following values:
+ * @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring
+ * @arg ICACHE_MONITOR_HIT Hit monitoring
+ * @arg ICACHE_MONITOR_MISS Miss monitoring
+ * @retval HAL status (HAL_OK)
+ */
+HAL_StatusTypeDef HAL_ICACHE_Monitor_Stop(uint32_t MonitorType)
+{
+ /* Check the parameters */
+ assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType));
+
+ CLEAR_BIT(ICACHE->CR, MonitorType);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Reset the Instruction Cache performance monitoring values.
+ * @param MonitorType Monitoring type
+ * This parameter can be one of the following values:
+ * @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring
+ * @arg ICACHE_MONITOR_HIT Hit monitoring
+ * @arg ICACHE_MONITOR_MISS Miss monitoring
+ * @retval HAL status (HAL_OK)
+ */
+HAL_StatusTypeDef HAL_ICACHE_Monitor_Reset(uint32_t MonitorType)
+{
+ /* Check the parameters */
+ assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType));
+
+ /* Force/Release reset */
+ SET_BIT(ICACHE->CR, (MonitorType << 2U));
+ CLEAR_BIT(ICACHE->CR, (MonitorType << 2U));
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get the Instruction Cache performance Hit monitoring value.
+ * @note Upon reaching the 32-bit maximum value, monitor does not wrap.
+ * @retval Hit monitoring value
+ */
+uint32_t HAL_ICACHE_Monitor_GetHitValue(void)
+{
+ return (ICACHE->HMONR);
+}
+
+/**
+ * @brief Get the Instruction Cache performance Miss monitoring value.
+ * @note Upon reaching the 32-bit maximum value, monitor does not wrap.
+ * @retval Miss monitoring value
+ */
+uint32_t HAL_ICACHE_Monitor_GetMissValue(void)
+{
+ return (ICACHE->MMONR);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ICACHE_Exported_Functions_Group2 IRQ and callback functions
+ * @brief IRQ and callback functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### IRQ and callback functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to handle ICACHE global interrupt
+ and the associated callback functions.
+ @endverbatim
+ * @{
+ */
+
+/**
+ * @brief Handle the Instruction Cache interrupt request.
+ * @note This function should be called under the ICACHE_IRQHandler().
+ * @note This function respectively disables the interrupt and clears the
+ * flag of any pending flag before calling the associated user callback.
+ * @retval None
+ */
+void HAL_ICACHE_IRQHandler(void)
+{
+ /* Get current interrupt flags and interrupt sources value */
+ uint32_t itflags = READ_REG(ICACHE->SR);
+ uint32_t itsources = READ_REG(ICACHE->IER);
+
+ /* Check Instruction cache Error interrupt flag */
+ if (((itflags & itsources) & ICACHE_FLAG_ERROR) != 0U)
+ {
+ /* Disable error interrupt */
+ CLEAR_BIT(ICACHE->IER, ICACHE_IER_ERRIE);
+
+ /* Clear ICACHE error pending flag */
+ WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF);
+
+ /* Instruction cache error interrupt user callback */
+ HAL_ICACHE_ErrorCallback();
+ }
+
+ /* Check Instruction cache BusyEnd interrupt flag */
+ if (((itflags & itsources) & ICACHE_FLAG_BUSYEND) != 0U)
+ {
+ /* Disable end of cache invalidation interrupt */
+ CLEAR_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);
+
+ /* Clear ICACHE busyend pending flag */
+ WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
+
+ /* Instruction cache busyend interrupt user callback */
+ HAL_ICACHE_InvalidateCompleteCallback();
+ }
+}
+
+/**
+ * @brief Cache invalidation complete callback.
+ */
+__weak void HAL_ICACHE_InvalidateCompleteCallback(void)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_ICACHE_InvalidateCompleteCallback() should be implemented in the user file
+ */
+}
+
+/**
+ * @brief Error callback.
+ */
+__weak void HAL_ICACHE_ErrorCallback(void)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_ICACHE_ErrorCallback() should be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ICACHE_Exported_Functions_Group3 Memory remapped regions functions
+ * @brief Memory remapped regions functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### Memory remapped regions functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to manage the remapping of
+ external memories to internal Code for execution.
+ @endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure and enable a region for memory remapping.
+ * @note The Instruction Cache and the region must be disabled.
+ * @param Region Region number
+ This parameter can be a value of @arg @ref ICACHE_Region
+ * @param pRegionConfig Pointer to structure of ICACHE region configuration parameters
+ * @retval HAL status (HAL_OK/HAL_ERROR)
+ */
+HAL_StatusTypeDef HAL_ICACHE_EnableRemapRegion(uint32_t Region, const ICACHE_RegionConfigTypeDef *const pRegionConfig)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ __IO uint32_t *p_reg;
+ uint32_t value;
+
+ /* Check the parameters */
+ assert_param(IS_ICACHE_REGION_NUMBER(Region));
+ assert_param(IS_ICACHE_REGION_SIZE(pRegionConfig->Size));
+ assert_param(IS_ICACHE_REGION_TRAFFIC_ROUTE(pRegionConfig->TrafficRoute));
+ assert_param(IS_ICACHE_REGION_OUTPUT_BURST_TYPE(pRegionConfig->OutputBurstType));
+
+ /* Check cache is not enabled */
+ if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Get region control register address */
+ p_reg = &(ICACHE->CRR0) + (1U * Region);
+
+ /* Check region is not already enabled */
+ if ((*p_reg & ICACHE_CRRx_REN) != 0U)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Region 2MB: BaseAddress size 8 bits, RemapAddress size 11 bits */
+ /* Region 4MB: BaseAddress size 7 bits, RemapAddress size 10 bits */
+ /* Region 8MB: BaseAddress size 6 bits, RemapAddress size 9 bits */
+ /* Region 16MB: BaseAddress size 5 bits, RemapAddress size 8 bits */
+ /* Region 32MB: BaseAddress size 4 bits, RemapAddress size 7 bits */
+ /* Region 64MB: BaseAddress size 3 bits, RemapAddress size 6 bits */
+ /* Region 128MB: BaseAddress size 2 bits, RemapAddress size 5 bits */
+ value = ((pRegionConfig->BaseAddress & 0x1FFFFFFFU) >> 21U) & \
+ (0xFFU & ~(pRegionConfig->Size - 1U));
+ value |= ((pRegionConfig->RemapAddress >> 5U) & \
+ ((uint32_t)(0x7FFU & ~(pRegionConfig->Size - 1U)) << ICACHE_CRRx_REMAPADDR_Pos));
+ value |= (pRegionConfig->Size << ICACHE_CRRx_RSIZE_Pos) | pRegionConfig->TrafficRoute | \
+ pRegionConfig->OutputBurstType;
+ *p_reg = (value | ICACHE_CRRx_REN);
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Disable the memory remapping for a predefined region.
+ * @param Region Region number
+ This parameter can be a value of @arg @ref ICACHE_Region
+ * @retval HAL status (HAL_OK/HAL_ERROR)
+ */
+HAL_StatusTypeDef HAL_ICACHE_DisableRemapRegion(uint32_t Region)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ __IO uint32_t *p_reg;
+
+ /* Check the parameters */
+ assert_param(IS_ICACHE_REGION_NUMBER(Region));
+
+ /* Check cache is not enabled */
+ if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Get region control register address */
+ p_reg = &(ICACHE->CRR0) + (1U * Region);
+
+ *p_reg &= ~ICACHE_CRRx_REN;
+ }
+
+ return status;
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_ICACHE_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_irda.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_irda.c
new file mode 100644
index 00000000..4acfd023
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_irda.c
@@ -0,0 +1,2975 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_irda.c
+ * @author MCD Application Team
+ * @brief IRDA HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the IrDA (Infrared Data Association) Peripheral
+ * (IRDA)
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State and Errors functions
+ * + Peripheral Control functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The IRDA HAL driver can be used as follows:
+
+ (#) Declare a IRDA_HandleTypeDef handle structure (eg. IRDA_HandleTypeDef hirda).
+ (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API
+ in setting the associated USART or UART in IRDA mode:
+ (++) Enable the USARTx/UARTx interface clock.
+ (++) USARTx/UARTx pins configuration:
+ (+++) Enable the clock for the USARTx/UARTx GPIOs.
+ (+++) Configure these USARTx/UARTx pins (TX as alternate function pull-up, RX as alternate function Input).
+ (++) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
+ and HAL_IRDA_Receive_IT() APIs):
+ (+++) Configure the USARTx/UARTx interrupt priority.
+ (+++) Enable the NVIC USARTx/UARTx IRQ handle.
+ (+++) The specific IRDA interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
+
+ (++) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
+ and HAL_IRDA_Receive_DMA() APIs):
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx channel.
+ (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer
+ complete interrupt on the DMA Tx/Rx channel.
+
+ (#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter),
+ the normal or low power mode and the clock prescaler in the hirda handle Init structure.
+
+ (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
+ (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customized HAL_IRDA_MspInit() API.
+
+ -@@- The specific IRDA interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
+
+ (#) Three operation modes are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
+ (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Send an amount of data in non-blocking mode using HAL_IRDA_Transmit_IT()
+ (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
+ (+) Receive an amount of data in non-blocking mode using HAL_IRDA_Receive_IT()
+ (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
+ (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Send an amount of data in non-blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
+ (+) At transmission half of transfer HAL_IRDA_TxHalfCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback()
+ (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
+ (+) Receive an amount of data in non-blocking mode (DMA) using HAL_IRDA_Receive_DMA()
+ (+) At reception half of transfer HAL_IRDA_RxHalfCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback()
+ (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
+ (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
+
+ *** IRDA HAL driver macros list ***
+ ====================================
+ [..]
+ Below the list of most used macros in IRDA HAL driver.
+
+ (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
+ (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
+ (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not
+ (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag
+ (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt
+ (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt
+ (+) __HAL_IRDA_GET_IT_SOURCE: Check whether or not the specified IRDA interrupt is enabled
+
+ [..]
+ (@) You can refer to the IRDA HAL driver header file for more useful macros
+
+ ##### Callback registration #####
+ ==================================
+
+ [..]
+ The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ [..]
+ Use Function @ref HAL_IRDA_RegisterCallback() to register a user callback.
+ Function @ref HAL_IRDA_RegisterCallback() allows to register following callbacks:
+ (+) TxHalfCpltCallback : Tx Half Complete Callback.
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxHalfCpltCallback : Rx Half Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+ (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
+ (+) MspInitCallback : IRDA MspInit.
+ (+) MspDeInitCallback : IRDA MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ [..]
+ Use function @ref HAL_IRDA_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function.
+ @ref HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TxHalfCpltCallback : Tx Half Complete Callback.
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxHalfCpltCallback : Rx Half Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+ (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
+ (+) MspInitCallback : IRDA MspInit.
+ (+) MspDeInitCallback : IRDA MspDeInit.
+
+ [..]
+ By default, after the @ref HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET
+ all callbacks are set to the corresponding weak (surcharged) functions:
+ examples @ref HAL_IRDA_TxCpltCallback(), @ref HAL_IRDA_RxHalfCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_IRDA_Init()
+ and @ref HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_IRDA_Init() and @ref HAL_IRDA_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+ [..]
+ Callbacks can be registered/unregistered in HAL_IRDA_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_IRDA_STATE_READY or HAL_IRDA_STATE_RESET state, thus registered (user)
+ MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_IRDA_RegisterCallback() before calling @ref HAL_IRDA_DeInit()
+ or @ref HAL_IRDA_Init() function.
+
+ [..]
+ When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available
+ and weak (surcharged) callbacks are used.
+
+ @endverbatim
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup IRDA IRDA
+ * @brief HAL IRDA module driver
+ * @{
+ */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup IRDA_Private_Constants IRDA Private Constants
+ * @{
+ */
+#define IRDA_TEACK_REACK_TIMEOUT 1000U /*!< IRDA TX or RX enable acknowledge time-out value */
+
+#define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE \
+ | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */
+
+#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */
+
+#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup IRDA_Private_Macros IRDA Private Macros
+ * @{
+ */
+/** @brief BRR division operation to set BRR register in 16-bit oversampling mode.
+ * @param __PCLK__ IRDA clock source.
+ * @param __BAUD__ Baud rate set by the user.
+ * @param __PRESCALER__ IRDA clock prescaler value.
+ * @retval Division result
+ */
+#define IRDA_DIV_SAMPLING16(__PCLK__, __BAUD__, __PRESCALER__) ((((__PCLK__)/IRDAPrescTable[(__PRESCALER__)])\
+ + ((__BAUD__)/2U)) / (__BAUD__))
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup IRDA_Private_Functions
+ * @{
+ */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status,
+ uint32_t Tickstart, uint32_t Timeout);
+static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);
+static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
+static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
+static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
+static void IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup IRDA_Exported_Functions IRDA Exported Functions
+ * @{
+ */
+
+/** @defgroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and Configuration functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USARTx
+ in asynchronous IRDA mode.
+ (+) For the asynchronous mode only these parameters can be configured:
+ (++) Baud Rate
+ (++) Word Length
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ (++) Power mode
+ (++) Prescaler setting
+ (++) Receiver/transmitter modes
+
+ [..]
+ The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures
+ (details for the procedures are available in reference manual).
+
+@endverbatim
+
+ Depending on the frame length defined by the M1 and M0 bits (7-bit,
+ 8-bit or 9-bit), the possible IRDA frame formats are listed in the
+ following table.
+
+ Table 1. IRDA frame format.
+ +-----------------------------------------------------------------------+
+ | M1 bit | M0 bit | PCE bit | IRDA frame |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 0 | | SB | 8 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 0 | | SB | 9 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 0 | | SB | 7 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
+ +-----------------------------------------------------------------------+
+
+ * @{
+ */
+
+/**
+ * @brief Initialize the IRDA mode according to the specified
+ * parameters in the IRDA_InitTypeDef and initialize the associated handle.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
+{
+ /* Check the IRDA handle allocation */
+ if (hirda == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the USART/UART associated to the IRDA handle */
+ assert_param(IS_IRDA_INSTANCE(hirda->Instance));
+
+ if (hirda->gState == HAL_IRDA_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hirda->Lock = HAL_UNLOCKED;
+
+#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
+ IRDA_InitCallbacksToDefault(hirda);
+
+ if (hirda->MspInitCallback == NULL)
+ {
+ hirda->MspInitCallback = HAL_IRDA_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hirda->MspInitCallback(hirda);
+#else
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_IRDA_MspInit(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+ }
+
+ hirda->gState = HAL_IRDA_STATE_BUSY;
+
+ /* Disable the Peripheral to update the configuration registers */
+ __HAL_IRDA_DISABLE(hirda);
+
+ /* Set the IRDA Communication parameters */
+ if (IRDA_SetConfig(hirda) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ /* In IRDA mode, the following bits must be kept cleared:
+ - LINEN, STOP and CLKEN bits in the USART_CR2 register,
+ - SCEN and HDSEL bits in the USART_CR3 register.*/
+ CLEAR_BIT(hirda->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
+ CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
+
+ /* set the UART/USART in IRDA mode */
+ hirda->Instance->CR3 |= USART_CR3_IREN;
+
+ /* Enable the Peripheral */
+ __HAL_IRDA_ENABLE(hirda);
+
+ /* TEACK and/or REACK to check before moving hirda->gState and hirda->RxState to Ready */
+ return (IRDA_CheckIdleState(hirda));
+}
+
+/**
+ * @brief DeInitialize the IRDA peripheral.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
+{
+ /* Check the IRDA handle allocation */
+ if (hirda == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the USART/UART associated to the IRDA handle */
+ assert_param(IS_IRDA_INSTANCE(hirda->Instance));
+
+ hirda->gState = HAL_IRDA_STATE_BUSY;
+
+ /* DeInit the low level hardware */
+#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
+ if (hirda->MspDeInitCallback == NULL)
+ {
+ hirda->MspDeInitCallback = HAL_IRDA_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ hirda->MspDeInitCallback(hirda);
+#else
+ HAL_IRDA_MspDeInit(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+ /* Disable the Peripheral */
+ __HAL_IRDA_DISABLE(hirda);
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->gState = HAL_IRDA_STATE_RESET;
+ hirda->RxState = HAL_IRDA_STATE_RESET;
+
+ /* Process Unlock */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the IRDA MSP.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_IRDA_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the IRDA MSP.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_IRDA_MspDeInit can be implemented in the user file
+ */
+}
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User IRDA Callback
+ * To be used instead of the weak predefined callback
+ * @param hirda irda handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+ * @arg @ref HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+ * @arg @ref HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_IRDA_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+ * @arg @ref HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+ * @arg @ref HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID,
+ pIRDA_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hirda);
+
+ if (hirda->gState == HAL_IRDA_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_IRDA_TX_HALFCOMPLETE_CB_ID :
+ hirda->TxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_IRDA_TX_COMPLETE_CB_ID :
+ hirda->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_IRDA_RX_HALFCOMPLETE_CB_ID :
+ hirda->RxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_IRDA_RX_COMPLETE_CB_ID :
+ hirda->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_IRDA_ERROR_CB_ID :
+ hirda->ErrorCallback = pCallback;
+ break;
+
+ case HAL_IRDA_ABORT_COMPLETE_CB_ID :
+ hirda->AbortCpltCallback = pCallback;
+ break;
+
+ case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID :
+ hirda->AbortTransmitCpltCallback = pCallback;
+ break;
+
+ case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID :
+ hirda->AbortReceiveCpltCallback = pCallback;
+ break;
+
+ case HAL_IRDA_MSPINIT_CB_ID :
+ hirda->MspInitCallback = pCallback;
+ break;
+
+ case HAL_IRDA_MSPDEINIT_CB_ID :
+ hirda->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hirda->gState == HAL_IRDA_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_IRDA_MSPINIT_CB_ID :
+ hirda->MspInitCallback = pCallback;
+ break;
+
+ case HAL_IRDA_MSPDEINIT_CB_ID :
+ hirda->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hirda);
+
+ return status;
+}
+
+/**
+ * @brief Unregister an IRDA callback
+ * IRDA callback is redirected to the weak predefined callback
+ * @param hirda irda handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+ * @arg @ref HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+ * @arg @ref HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_IRDA_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+ * @arg @ref HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+ * @arg @ref HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hirda);
+
+ if (HAL_IRDA_STATE_READY == hirda->gState)
+ {
+ switch (CallbackID)
+ {
+ case HAL_IRDA_TX_HALFCOMPLETE_CB_ID :
+ hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ break;
+
+ case HAL_IRDA_TX_COMPLETE_CB_ID :
+ hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ break;
+
+ case HAL_IRDA_RX_HALFCOMPLETE_CB_ID :
+ hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ break;
+
+ case HAL_IRDA_RX_COMPLETE_CB_ID :
+ hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ break;
+
+ case HAL_IRDA_ERROR_CB_ID :
+ hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_IRDA_ABORT_COMPLETE_CB_ID :
+ hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ break;
+
+ case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID :
+ hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak
+ AbortTransmitCpltCallback */
+ break;
+
+ case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID :
+ hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak
+ AbortReceiveCpltCallback */
+ break;
+
+ case HAL_IRDA_MSPINIT_CB_ID :
+ hirda->MspInitCallback = HAL_IRDA_MspInit; /* Legacy weak MspInitCallback */
+ break;
+
+ case HAL_IRDA_MSPDEINIT_CB_ID :
+ hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; /* Legacy weak MspDeInitCallback */
+ break;
+
+ default :
+ /* Update the error code */
+ hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_IRDA_STATE_RESET == hirda->gState)
+ {
+ switch (CallbackID)
+ {
+ case HAL_IRDA_MSPINIT_CB_ID :
+ hirda->MspInitCallback = HAL_IRDA_MspInit;
+ break;
+
+ case HAL_IRDA_MSPDEINIT_CB_ID :
+ hirda->MspDeInitCallback = HAL_IRDA_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hirda);
+
+ return status;
+}
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions
+ * @brief IRDA Transmit and Receive functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the IRDA data transfers.
+
+ [..]
+ IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
+ on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
+ is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
+ While receiving data, transmission should be avoided as the data to be transmitted
+ could be corrupted.
+
+ [..]
+ (#) There are two modes of transfer:
+ (++) Blocking mode: the communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) Non-Blocking mode: the communication is performed using Interrupts
+ or DMA, these API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
+ will be executed respectively at the end of the Transmit or Receive process
+ The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
+
+ (#) Blocking mode APIs are :
+ (++) HAL_IRDA_Transmit()
+ (++) HAL_IRDA_Receive()
+
+ (#) Non Blocking mode APIs with Interrupt are :
+ (++) HAL_IRDA_Transmit_IT()
+ (++) HAL_IRDA_Receive_IT()
+ (++) HAL_IRDA_IRQHandler()
+
+ (#) Non Blocking mode functions with DMA are :
+ (++) HAL_IRDA_Transmit_DMA()
+ (++) HAL_IRDA_Receive_DMA()
+ (++) HAL_IRDA_DMAPause()
+ (++) HAL_IRDA_DMAResume()
+ (++) HAL_IRDA_DMAStop()
+
+ (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode:
+ (++) HAL_IRDA_TxHalfCpltCallback()
+ (++) HAL_IRDA_TxCpltCallback()
+ (++) HAL_IRDA_RxHalfCpltCallback()
+ (++) HAL_IRDA_RxCpltCallback()
+ (++) HAL_IRDA_ErrorCallback()
+
+ (#) Non-Blocking mode transfers could be aborted using Abort API's :
+ (++) HAL_IRDA_Abort()
+ (++) HAL_IRDA_AbortTransmit()
+ (++) HAL_IRDA_AbortReceive()
+ (++) HAL_IRDA_Abort_IT()
+ (++) HAL_IRDA_AbortTransmit_IT()
+ (++) HAL_IRDA_AbortReceive_IT()
+
+ (#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
+ (++) HAL_IRDA_AbortCpltCallback()
+ (++) HAL_IRDA_AbortTransmitCpltCallback()
+ (++) HAL_IRDA_AbortReceiveCpltCallback()
+
+ (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+ Errors are handled as follows :
+ (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error
+ in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user
+ to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
+ Transfer is kept ongoing on IRDA side.
+ If user wants to abort it, Abort services should be called by user.
+ (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type, and
+ HAL_IRDA_ErrorCallback() user callback is executed.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Send an amount of data in blocking mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
+ * @param Timeout Specify timeout value.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint8_t *pdata8bits;
+ uint16_t *pdata16bits;
+ uint32_t tickstart;
+
+ /* Check that a Tx process is not already ongoing */
+ if (hirda->gState == HAL_IRDA_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->gState = HAL_IRDA_STATE_BUSY_TX;
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ hirda->TxXferSize = Size;
+ hirda->TxXferCount = Size;
+
+ /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ {
+ pdata8bits = NULL;
+ pdata16bits = (uint16_t *) pData; /* Derogation R.11.3 */
+ }
+ else
+ {
+ pdata8bits = pData;
+ pdata16bits = NULL;
+ }
+
+ while (hirda->TxXferCount > 0U)
+ {
+ hirda->TxXferCount--;
+
+ if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if (pdata8bits == NULL)
+ {
+ hirda->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
+ pdata16bits++;
+ }
+ else
+ {
+ hirda->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
+ pdata8bits++;
+ }
+ }
+
+ if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* At end of Tx process, restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
+ * @param Timeout Specify timeout value.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint8_t *pdata8bits;
+ uint16_t *pdata16bits;
+ uint16_t uhMask;
+ uint32_t tickstart;
+
+ /* Check that a Rx process is not already ongoing */
+ if (hirda->RxState == HAL_IRDA_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ hirda->RxXferSize = Size;
+ hirda->RxXferCount = Size;
+
+ /* Computation of the mask to apply to RDR register
+ of the UART associated to the IRDA */
+ IRDA_MASK_COMPUTATION(hirda);
+ uhMask = hirda->Mask;
+
+ /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ {
+ pdata8bits = NULL;
+ pdata16bits = (uint16_t *) pData; /* Derogation R.11.3 */
+ }
+ else
+ {
+ pdata8bits = pData;
+ pdata16bits = NULL;
+ }
+
+ /* Check data remaining to be received */
+ while (hirda->RxXferCount > 0U)
+ {
+ hirda->RxXferCount--;
+
+ if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if (pdata8bits == NULL)
+ {
+ *pdata16bits = (uint16_t)(hirda->Instance->RDR & uhMask);
+ pdata16bits++;
+ }
+ else
+ {
+ *pdata8bits = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
+ pdata8bits++;
+ }
+ }
+
+ /* At end of Rx process, restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in interrupt mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Tx process is not already ongoing */
+ if (hirda->gState == HAL_IRDA_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->pTxBuffPtr = pData;
+ hirda->TxXferSize = Size;
+ hirda->TxXferCount = Size;
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->gState = HAL_IRDA_STATE_BUSY_TX;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ /* Enable the IRDA Transmit Data Register Empty Interrupt */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in interrupt mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Rx process is not already ongoing */
+ if (hirda->RxState == HAL_IRDA_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->pRxBuffPtr = pData;
+ hirda->RxXferSize = Size;
+ hirda->RxXferCount = Size;
+
+ /* Computation of the mask to apply to the RDR register
+ of the UART associated to the IRDA */
+ IRDA_MASK_COMPUTATION(hirda);
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ /* Enable the IRDA Parity Error and Data Register not empty Interrupts */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+
+ /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in DMA mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef status;
+ uint16_t nbByte = Size;
+
+ /* Check that a Tx process is not already ongoing */
+ if (hirda->gState == HAL_IRDA_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->pTxBuffPtr = pData;
+ hirda->TxXferSize = Size;
+ hirda->TxXferCount = Size;
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->gState = HAL_IRDA_STATE_BUSY_TX;
+
+ /* Set the IRDA DMA transfer complete callback */
+ hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
+
+ /* Set the IRDA DMA half transfer complete callback */
+ hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
+
+ /* Set the DMA error callback */
+ hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
+
+ /* Set the DMA abort callback */
+ hirda->hdmatx->XferAbortCallback = NULL;
+
+ /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
+ should be aligned on a u16 frontier, so nbByte should be equal to Size multiplied by 2 */
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ {
+ nbByte = Size * 2U;
+ }
+
+ /* Check linked list mode */
+ if ((hirda->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if ((hirda->hdmatx->LinkedListQueue != NULL) && (hirda->hdmatx->LinkedListQueue->Head != NULL))
+ {
+ /* Set DMA data size */
+ hirda->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte;
+
+ /* Set DMA source address */
+ hirda->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
+ (uint32_t)hirda->pTxBuffPtr;
+
+ /* Set DMA destination address */
+ hirda->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
+ (uint32_t)&hirda->Instance->TDR;
+
+ /* Enable the IRDA transmit DMA channel */
+ status = HAL_DMAEx_List_Start_IT(hirda->hdmatx);
+ }
+ else
+ {
+ /* Update status */
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Enable the IRDA transmit DMA channel */
+ status = HAL_DMA_Start_IT(hirda->hdmatx, (uint32_t)hirda->pTxBuffPtr, (uint32_t)&hirda->Instance->TDR, nbByte);
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Clear the TC flag in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_TCF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the USART CR3 register */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Set error code to DMA */
+ hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ /* Restore hirda->gState to ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in DMA mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
+ * @note When the IRDA parity is enabled (PCE = 1), the received data contains
+ * the parity bit (MSB position).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef status;
+ uint16_t nbByte = Size;
+
+ /* Check that a Rx process is not already ongoing */
+ if (hirda->RxState == HAL_IRDA_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->pRxBuffPtr = pData;
+ hirda->RxXferSize = Size;
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
+
+ /* Set the IRDA DMA transfer complete callback */
+ hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
+
+ /* Set the IRDA DMA half transfer complete callback */
+ hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
+
+ /* Set the DMA error callback */
+ hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
+
+ /* Set the DMA abort callback */
+ hirda->hdmarx->XferAbortCallback = NULL;
+
+ /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
+ should be aligned on a u16 frontier, so nbByte should be equal to Size multiplied by 2 */
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ {
+ nbByte = Size * 2U;
+ }
+
+ /* Check linked list mode */
+ if ((hirda->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if ((hirda->hdmarx->LinkedListQueue != NULL) && (hirda->hdmarx->LinkedListQueue->Head != NULL))
+ {
+ /* Set DMA data size */
+ hirda->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte;
+
+ /* Set DMA source address */
+ hirda->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
+ (uint32_t)&hirda->Instance->RDR;
+
+ /* Set DMA destination address */
+ hirda->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hirda->pRxBuffPtr;
+
+ /* Enable the DMA channel */
+ status = HAL_DMAEx_List_Start_IT(hirda->hdmarx);
+ }
+ else
+ {
+ /* Update status */
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Enable the DMA channel */
+ status = HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, (uint32_t)hirda->pRxBuffPtr, nbByte);
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ /* Enable the UART Parity Error Interrupt */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the USART CR3 register */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Set error code to DMA */
+ hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ /* Restore hirda->RxState to ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+/**
+ * @brief Pause the DMA Transfer.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
+{
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
+ {
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable the IRDA DMA Tx request */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+ }
+ }
+ if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
+ {
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the IRDA DMA Rx request */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resume the DMA Transfer.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
+{
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
+ {
+ /* Enable the IRDA DMA Tx request */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+ }
+ if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
+ {
+ /* Clear the Overrun flag before resuming the Rx transfer*/
+ __HAL_IRDA_CLEAR_OREFLAG(hirda);
+
+ /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+ SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the IRDA DMA Rx request */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the DMA Transfer.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
+{
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() /
+ HAL_IRDA_TxHalfCpltCallback / HAL_IRDA_RxHalfCpltCallback:
+ indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
+ interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
+ the stream and the corresponding call back is executed. */
+
+ /* Stop IRDA DMA Tx request if ongoing */
+ if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
+ {
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the IRDA DMA Tx channel */
+ if (hirda->hdmatx != NULL)
+ {
+ if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ IRDA_EndTxTransfer(hirda);
+ }
+ }
+
+ /* Stop IRDA DMA Rx request if ongoing */
+ if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
+ {
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel */
+ if (hirda->hdmarx != NULL)
+ {
+ if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ IRDA_EndRxTransfer(hirda);
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (blocking mode).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable IRDA Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | \
+ USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the IRDA DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if (hirda->hdmatx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hirda->hdmatx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Disable the IRDA DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if (hirda->hdmarx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hirda->hdmarx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Reset Tx and Rx transfer counters */
+ hirda->TxXferCount = 0U;
+ hirda->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+ /* Restore hirda->gState and hirda->RxState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Reset Handle ErrorCode to No Error */
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (blocking mode).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable IRDA Interrupts (Tx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+
+ /* Disable the IRDA DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if (hirda->hdmatx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hirda->hdmatx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Reset Tx transfer counter */
+ hirda->TxXferCount = 0U;
+
+ /* Restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (blocking mode).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable IRDA Interrupts (Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the IRDA DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if (hirda->hdmarx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hirda->hdmarx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Reset Rx transfer counter */
+ hirda->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+ /* Restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (Interrupt mode).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable IRDA Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
+{
+ uint32_t abortcplt = 1U;
+
+ /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | \
+ USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised
+ before any call to DMA Abort functions */
+ /* DMA Tx Handle is valid */
+ if (hirda->hdmatx != NULL)
+ {
+ /* Set DMA Abort Complete callback if IRDA DMA Tx request if enabled.
+ Otherwise, set it to NULL */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ hirda->hdmatx->XferAbortCallback = IRDA_DMATxAbortCallback;
+ }
+ else
+ {
+ hirda->hdmatx->XferAbortCallback = NULL;
+ }
+ }
+ /* DMA Rx Handle is valid */
+ if (hirda->hdmarx != NULL)
+ {
+ /* Set DMA Abort Complete callback if IRDA DMA Rx request if enabled.
+ Otherwise, set it to NULL */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ hirda->hdmarx->XferAbortCallback = IRDA_DMARxAbortCallback;
+ }
+ else
+ {
+ hirda->hdmarx->XferAbortCallback = NULL;
+ }
+ }
+
+ /* Disable the IRDA DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable DMA Tx at UART level */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if (hirda->hdmatx != NULL)
+ {
+ /* IRDA Tx DMA Abort callback has already been initialised :
+ will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
+ {
+ hirda->hdmatx->XferAbortCallback = NULL;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* Disable the IRDA DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if (hirda->hdmarx != NULL)
+ {
+ /* IRDA Rx DMA Abort callback has already been initialised :
+ will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+ {
+ hirda->hdmarx->XferAbortCallback = NULL;
+ abortcplt = 1U;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+ if (abortcplt == 1U)
+ {
+ /* Reset Tx and Rx transfer counters */
+ hirda->TxXferCount = 0U;
+ hirda->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+ /* Restore hirda->gState and hirda->RxState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ hirda->AbortCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort complete callback */
+ HAL_IRDA_AbortCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (Interrupt mode).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable IRDA Interrupts (Tx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+
+ /* Disable the IRDA DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if (hirda->hdmatx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback :
+ will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+ hirda->hdmatx->XferAbortCallback = IRDA_DMATxOnlyAbortCallback;
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
+ {
+ /* Call Directly hirda->hdmatx->XferAbortCallback function in case of error */
+ hirda->hdmatx->XferAbortCallback(hirda->hdmatx);
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ hirda->TxXferCount = 0U;
+
+ /* Restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ hirda->AbortTransmitCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
+ HAL_IRDA_AbortTransmitCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ hirda->TxXferCount = 0U;
+
+ /* Restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ hirda->AbortTransmitCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
+ HAL_IRDA_AbortTransmitCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (Interrupt mode).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable IRDA Interrupts (Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the IRDA DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if (hirda->hdmarx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback :
+ will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+ hirda->hdmarx->XferAbortCallback = IRDA_DMARxOnlyAbortCallback;
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+ {
+ /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
+ hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ hirda->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+ /* Restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ hirda->AbortReceiveCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
+ HAL_IRDA_AbortReceiveCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ hirda->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+ /* Restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ hirda->AbortReceiveCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
+ HAL_IRDA_AbortReceiveCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle IRDA interrupt request.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
+{
+ uint32_t isrflags = READ_REG(hirda->Instance->ISR);
+ uint32_t cr1its = READ_REG(hirda->Instance->CR1);
+ uint32_t cr3its;
+ uint32_t errorflags;
+ uint32_t errorcode;
+
+ /* If no error occurs */
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
+ if (errorflags == 0U)
+ {
+ /* IRDA in mode Receiver ---------------------------------------------------*/
+ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) && ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U))
+ {
+ IRDA_Receive_IT(hirda);
+ return;
+ }
+ }
+
+ /* If some errors occur */
+ cr3its = READ_REG(hirda->Instance->CR3);
+ if ((errorflags != 0U)
+ && (((cr3its & USART_CR3_EIE) != 0U)
+ || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U)))
+ {
+ /* IRDA parity error interrupt occurred -------------------------------------*/
+ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+ {
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF);
+
+ hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
+ }
+
+ /* IRDA frame error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF);
+
+ hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
+ }
+
+ /* IRDA noise error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF);
+
+ hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
+ }
+
+ /* IRDA Over-Run interrupt occurred -----------------------------------------*/
+ if (((isrflags & USART_ISR_ORE) != 0U) &&
+ (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || ((cr3its & USART_CR3_EIE) != 0U)))
+ {
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);
+
+ hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
+ }
+
+ /* Call IRDA Error Call back function if need be --------------------------*/
+ if (hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
+ {
+ /* IRDA in mode Receiver ---------------------------------------------------*/
+ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) && ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U))
+ {
+ IRDA_Receive_IT(hirda);
+ }
+
+ /* If Overrun error occurs, or if any error occurs in DMA mode reception,
+ consider error as blocking */
+ errorcode = hirda->ErrorCode;
+ if ((HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) ||
+ ((errorcode & HAL_IRDA_ERROR_ORE) != 0U))
+ {
+ /* Blocking error : transfer is aborted
+ Set the IRDA state ready to be able to start again the process,
+ Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+ IRDA_EndRxTransfer(hirda);
+
+ /* Disable the IRDA DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel */
+ if (hirda->hdmarx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback :
+ will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */
+ hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError;
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+ {
+ /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
+ hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
+ }
+ }
+ else
+ {
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hirda->ErrorCallback(hirda);
+#else
+ /* Call legacy weak user error callback */
+ HAL_IRDA_ErrorCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+ }
+ }
+ else
+ {
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hirda->ErrorCallback(hirda);
+#else
+ /* Call legacy weak user error callback */
+ HAL_IRDA_ErrorCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+ }
+ }
+ else
+ {
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hirda->ErrorCallback(hirda);
+#else
+ /* Call legacy weak user error callback */
+ HAL_IRDA_ErrorCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ }
+ }
+ return;
+
+ } /* End if some error occurs */
+
+ /* IRDA in mode Transmitter ------------------------------------------------*/
+ if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) && ((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U))
+ {
+ IRDA_Transmit_IT(hirda);
+ return;
+ }
+
+ /* IRDA in mode Transmitter (transmission end) -----------------------------*/
+ if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
+ {
+ IRDA_EndTransmit_IT(hirda);
+ return;
+ }
+
+}
+
+/**
+ * @brief Tx Transfer completed callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_TxCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Tx Half Transfer completed callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval None
+ */
+__weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_RxCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Rx Half Transfer complete callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief IRDA error callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_ErrorCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief IRDA Abort Complete callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_AbortCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief IRDA Abort Complete callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_AbortTransmitCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief IRDA Abort Receive Complete callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_AbortReceiveCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
+ * @brief IRDA State and Errors functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Error functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to return the State of IrDA
+ communication process and also return Peripheral Errors occurred during communication process
+ (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state
+ of the IRDA peripheral handle.
+ (+) HAL_IRDA_GetError() checks in run-time errors that could occur during
+ communication.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the IRDA handle state.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL state
+ */
+HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
+{
+ /* Return IRDA handle state */
+ uint32_t temp1;
+ uint32_t temp2;
+ temp1 = (uint32_t)hirda->gState;
+ temp2 = (uint32_t)hirda->RxState;
+
+ return (HAL_IRDA_StateTypeDef)(temp1 | temp2);
+}
+
+/**
+ * @brief Return the IRDA handle error code.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval IRDA Error Code
+ */
+uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
+{
+ return hirda->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Private_Functions IRDA Private Functions
+ * @{
+ */
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Initialize the callbacks to their default values.
+ * @param hirda IRDA handle.
+ * @retval none
+ */
+void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda)
+{
+ /* Init the IRDA Callback settings */
+ hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */
+ hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+ hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
+
+}
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+
+/**
+ * @brief Configure the IRDA peripheral.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
+{
+ uint32_t tmpreg;
+ IRDA_ClockSourceTypeDef clocksource;
+ HAL_StatusTypeDef ret = HAL_OK;
+ static const uint16_t IRDAPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
+ uint32_t pclk;
+
+ /* Check the communication parameters */
+ assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
+ assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
+ assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
+ assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode));
+ assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler));
+ assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode));
+ assert_param(IS_IRDA_CLOCKPRESCALER(hirda->Init.ClockPrescaler));
+
+ /*-------------------------- USART CR1 Configuration -----------------------*/
+ /* Configure the IRDA Word Length, Parity and transfer Mode:
+ Set the M bits according to hirda->Init.WordLength value
+ Set PCE and PS bits according to hirda->Init.Parity value
+ Set TE and RE bits according to hirda->Init.Mode value */
+ tmpreg = (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode ;
+
+ MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg);
+
+ /*-------------------------- USART CR3 Configuration -----------------------*/
+ MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode);
+
+ /*--------------------- USART clock PRESC Configuration ----------------*/
+ /* Configure
+ * - IRDA Clock Prescaler: set PRESCALER according to hirda->Init.ClockPrescaler value */
+ MODIFY_REG(hirda->Instance->PRESC, USART_PRESC_PRESCALER, hirda->Init.ClockPrescaler);
+
+ /*-------------------------- USART GTPR Configuration ----------------------*/
+ MODIFY_REG(hirda->Instance->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)hirda->Init.Prescaler);
+
+ /*-------------------------- USART BRR Configuration -----------------------*/
+ IRDA_GETCLOCKSOURCE(hirda, clocksource);
+ tmpreg = 0U;
+ switch (clocksource)
+ {
+ case IRDA_CLOCKSOURCE_PCLK1:
+ pclk = HAL_RCC_GetPCLK1Freq();
+ tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
+ break;
+ case IRDA_CLOCKSOURCE_PCLK2:
+ pclk = HAL_RCC_GetPCLK2Freq();
+ tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
+ break;
+ case IRDA_CLOCKSOURCE_HSI:
+ tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
+ break;
+ case IRDA_CLOCKSOURCE_SYSCLK:
+ pclk = HAL_RCC_GetSysClockFreq();
+ tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
+ break;
+ case IRDA_CLOCKSOURCE_LSE:
+ tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
+ break;
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+
+ /* USARTDIV must be greater than or equal to 0d16 */
+ if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX))
+ {
+ hirda->Instance->BRR = tmpreg;
+ }
+ else
+ {
+ ret = HAL_ERROR;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Check the IRDA Idle State.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
+{
+ uint32_t tickstart;
+
+ /* Initialize the IRDA ErrorCode */
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ /* Check if the Transmitter is enabled */
+ if ((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ {
+ /* Wait until TEACK flag is set */
+ if (IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Check if the Receiver is enabled */
+ if ((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+ {
+ /* Wait until REACK flag is set */
+ if (IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Initialize the IRDA state*/
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle IRDA Communication Timeout.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param Flag Specifies the IRDA flag to check.
+ * @param Status Flag status (SET or RESET)
+ * @param Tickstart Tick start value
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status,
+ uint32_t Tickstart, uint32_t Timeout)
+{
+ /* Wait until flag is set */
+ while ((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
+ interrupts for the interrupt process */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+
+/**
+ * @brief End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+
+ /* At end of Tx process, restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+}
+
+
+/**
+ * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* At end of Rx process, restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+}
+
+
+/**
+ * @brief DMA IRDA transmit process complete callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
+
+ /* DMA Normal mode */
+ if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR)
+ {
+ hirda->TxXferCount = 0U;
+
+ /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+ in the IRDA CR3 register */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Enable the IRDA Transmit Complete Interrupt */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
+ }
+ /* DMA Circular mode */
+ else
+ {
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx complete callback */
+ hirda->TxCpltCallback(hirda);
+#else
+ /* Call legacy weak Tx complete callback */
+ HAL_IRDA_TxCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+ }
+
+}
+
+/**
+ * @brief DMA IRDA transmit process half complete callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Half complete callback */
+ hirda->TxHalfCpltCallback(hirda);
+#else
+ /* Call legacy weak Tx complete callback */
+ HAL_IRDA_TxHalfCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+}
+
+/**
+ * @brief DMA IRDA receive process complete callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
+
+ /* DMA Normal mode */
+ if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR)
+ {
+ hirda->RxXferCount = 0U;
+
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+ in the IRDA CR3 register */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* At end of Rx process, restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+ }
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx complete callback */
+ hirda->RxCpltCallback(hirda);
+#else
+ /* Call legacy weak Rx complete callback */
+ HAL_IRDA_RxCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA IRDA receive process half complete callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Half complete callback*/
+ hirda->RxHalfCpltCallback(hirda);
+#else
+ /* Call legacy weak Rx Half complete callback */
+ HAL_IRDA_RxHalfCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+}
+
+/**
+ * @brief DMA IRDA communication error callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
+
+ /* Stop IRDA DMA Tx request if ongoing */
+ if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
+ {
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ hirda->TxXferCount = 0U;
+ IRDA_EndTxTransfer(hirda);
+ }
+ }
+
+ /* Stop IRDA DMA Rx request if ongoing */
+ if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
+ {
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ hirda->RxXferCount = 0U;
+ IRDA_EndRxTransfer(hirda);
+ }
+ }
+
+ hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hirda->ErrorCallback(hirda);
+#else
+ /* Call legacy weak user error callback */
+ HAL_IRDA_ErrorCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+}
+
+/**
+ * @brief DMA IRDA communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
+ hirda->RxXferCount = 0U;
+ hirda->TxXferCount = 0U;
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hirda->ErrorCallback(hirda);
+#else
+ /* Call legacy weak user error callback */
+ HAL_IRDA_ErrorCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+}
+
+/**
+ * @brief DMA IRDA Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
+
+ hirda->hdmatx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if (hirda->hdmarx != NULL)
+ {
+ if (hirda->hdmarx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ hirda->TxXferCount = 0U;
+ hirda->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+ /* Restore hirda->gState and hirda->RxState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ hirda->AbortCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort complete callback */
+ HAL_IRDA_AbortCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+}
+
+
+/**
+ * @brief DMA IRDA Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
+
+ hirda->hdmarx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if (hirda->hdmatx != NULL)
+ {
+ if (hirda->hdmatx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ hirda->TxXferCount = 0U;
+ hirda->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+ /* Restore hirda->gState and hirda->RxState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ hirda->AbortCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort complete callback */
+ HAL_IRDA_AbortCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+}
+
+
+/**
+ * @brief DMA IRDA Tx communication abort callback, when initiated by user by a call to
+ * HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer)
+ * (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+ * and leads to user Tx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
+
+ hirda->TxXferCount = 0U;
+
+ /* Restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ hirda->AbortTransmitCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
+ HAL_IRDA_AbortTransmitCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+}
+
+/**
+ * @brief DMA IRDA Rx communication abort callback, when initiated by user by a call to
+ * HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer)
+ * (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+ * and leads to user Rx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ hirda->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+ /* Restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ hirda->AbortReceiveCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
+ HAL_IRDA_AbortReceiveCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+}
+
+/**
+ * @brief Send an amount of data in interrupt mode.
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_IRDA_Transmit_IT().
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
+{
+ uint16_t *tmp;
+
+ /* Check that a Tx process is ongoing */
+ if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
+ {
+ if (hirda->TxXferCount == 0U)
+ {
+ /* Disable the IRDA Transmit Data Register Empty Interrupt */
+ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+
+ /* Enable the IRDA Transmit Complete Interrupt */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
+ }
+ else
+ {
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ {
+ tmp = (uint16_t *) hirda->pTxBuffPtr; /* Derogation R.11.3 */
+ hirda->Instance->TDR = (uint16_t)(*tmp & 0x01FFU);
+ hirda->pTxBuffPtr += 2U;
+ }
+ else
+ {
+ hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr & 0xFFU);
+ hirda->pTxBuffPtr++;
+ }
+ hirda->TxXferCount--;
+ }
+ }
+}
+
+/**
+ * @brief Wrap up transmission in non-blocking mode.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable the IRDA Transmit Complete Interrupt */
+ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
+
+ /* Tx process is ended, restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx complete callback */
+ hirda->TxCpltCallback(hirda);
+#else
+ /* Call legacy weak Tx complete callback */
+ HAL_IRDA_TxCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+}
+
+/**
+ * @brief Receive an amount of data in interrupt mode.
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_IRDA_Receive_IT()
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+static void IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
+{
+ uint16_t *tmp;
+ uint16_t uhMask = hirda->Mask;
+ uint16_t uhdata;
+
+ /* Check that a Rx process is ongoing */
+ if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
+ {
+ uhdata = (uint16_t) READ_REG(hirda->Instance->RDR);
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ {
+ tmp = (uint16_t *) hirda->pRxBuffPtr; /* Derogation R.11.3 */
+ *tmp = (uint16_t)(uhdata & uhMask);
+ hirda->pRxBuffPtr += 2U;
+ }
+ else
+ {
+ *hirda->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
+ hirda->pRxBuffPtr++;
+ }
+
+ hirda->RxXferCount--;
+ if (hirda->RxXferCount == 0U)
+ {
+ /* Disable the IRDA Parity Error Interrupt and RXNE interrupt */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+
+ /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Rx process is completed, restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx complete callback */
+ hirda->RxCpltCallback(hirda);
+#else
+ /* Call legacy weak Rx complete callback */
+ HAL_IRDA_RxCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+ }
+ }
+ else
+ {
+ /* Clear RXNE interrupt flag */
+ __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST);
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_IRDA_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_iwdg.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_iwdg.c
new file mode 100644
index 00000000..25ec1e12
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_iwdg.c
@@ -0,0 +1,474 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_iwdg.c
+ * @author MCD Application Team
+ * @brief IWDG HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Independent Watchdog (IWDG) peripheral:
+ * + Initialization and Start functions
+ * + IO operation functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### IWDG Generic features #####
+ ==============================================================================
+ [..]
+ (+) The IWDG can be started by either software or hardware (configurable
+ through option byte).
+
+ (+) The IWDG is clocked by the Low-Speed Internal clock (LSI) and thus stays
+ active even if the main clock fails.
+
+ (+) Once the IWDG is started, the LSI is forced ON and both cannot be
+ disabled. The counter starts counting down from the reset value (0xFFF).
+ When it reaches the end of count value (0x000) a reset signal is
+ generated (IWDG reset).
+
+ (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
+ the IWDG_RLR value is reloaded into the counter and the watchdog reset
+ is prevented.
+
+ (+) The IWDG is implemented in the VDD voltage domain that is still functional
+ in STOP and STANDBY mode (IWDG reset can wake up the CPU from STANDBY).
+ IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
+ reset occurs.
+
+ (+) Debug mode: When the microcontroller enters debug mode (core halted),
+ the IWDG counter either continues to work normally or stops, depending
+ on DBG_IWDG_STOP configuration bit in DBG module, accessible through
+ __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros.
+
+ [..] Min-max timeout value @32KHz (LSI): ~125us / ~131.04s
+ The IWDG timeout may vary due to LSI clock frequency dispersion.
+ STM32U5xx devices provide the capability to measure the LSI clock
+ frequency (LSI clock is internally connected to TIM16 CH1 input capture).
+ The measured value can be used to have an IWDG timeout with an
+ acceptable accuracy.
+
+ [..] Default timeout value (necessary for IWDG_SR status register update):
+ Constant LSI_VALUE is defined based on the nominal LSI clock frequency.
+ This frequency being subject to variations as mentioned above, the
+ default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT
+ below) may become too short or too long.
+ In such cases, this default timeout value can be tuned by redefining
+ the constant LSI_VALUE at user-application level (based, for instance,
+ on the measured LSI clock frequency as explained above).
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Register callback to treat Iwdg interrupt and MspInit using HAL_IWDG_RegisterCallback().
+ (++) Provide exiting handle as first parameter.
+ (++) Provide which callback will be registered using one value from
+ HAL_IWDG_CallbackIDTypeDef.
+ (++) Provide callback function pointer.
+
+ (#) Use IWDG using HAL_IWDG_Init() function to :
+ (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
+ clock is forced ON and IWDG counter starts counting down.
+ (++) Enable write access to configuration registers:
+ IWDG_PR, IWDG_RLR, IWDG_WINR and EWCR.
+ (++) Configure the IWDG prescaler and counter reload value. This reload
+ value will be loaded in the IWDG counter each time the watchdog is
+ reloaded, then the IWDG will start counting down from this value.
+ (++) Depending on window parameter:
+ (+++) If Window Init parameter is same as Window register value,
+ nothing more is done but reload counter value in order to exit
+ function with exact time base.
+ (+++) Else modify Window register. This will automatically reload
+ watchdog counter.
+ (++) Depending on Early Wakeup Interrupt parameter:
+ (+++) If EWI is set to disable, comparator is set to 0, interrupt is
+ disable & flag is clear.
+ (+++) Else modify EWCR register, setting comparator value, enable
+ interrupt & clear flag.
+ (++) Wait for status flags to be reset.
+
+ (#) Then the application program must refresh the IWDG counter at regular
+ intervals during normal operation to prevent an MCU reset, using
+ HAL_IWDG_Refresh() function.
+
+ *** IWDG HAL driver macros list ***
+ ====================================
+ [..]
+ Below the list of most used macros in IWDG HAL driver:
+ (+) __HAL_IWDG_START: Enable the IWDG peripheral
+ (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
+ the reload register
+
+ @endverbatim
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+/** @addtogroup IWDG
+ * @brief IWDG HAL module driver.
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup IWDG_Private_Defines IWDG Private Defines
+ * @{
+ */
+/* Status register needs up to 5 LSI clock periods divided by the clock
+ prescaler to be updated. The number of LSI clock periods is upper-rounded to
+ 6 for the timeout value calculation.
+ The timeout value is also calculated using the highest prescaler (256) and
+ the LSI_VALUE constant. The value of this constant can be changed by the user
+ to take into account possible LSI clock period variations.
+ The timeout value is multiplied by 1000 to be converted in milliseconds. */
+#define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_VALUE)
+#define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_EWU | IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU)
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup IWDG_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup IWDG_Exported_Functions_Group1
+ * @brief Initialization and Start functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Start functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the IWDG according to the specified parameters in the
+ IWDG_InitTypeDef of associated handle.
+ (+) Manage Window option.
+ (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
+ is reloaded in order to exit function with correct time base.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the IWDG according to the specified parameters in the
+ * IWDG_InitTypeDef and start watchdog. Before exiting function,
+ * watchdog is refreshed in order to have correct time base.
+ * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified IWDG module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
+{
+ uint32_t tickstart;
+
+ /* Check the IWDG handle allocation */
+ if (hiwdg == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
+ assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
+ assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
+ assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
+ assert_param(IS_IWDG_EWI(hiwdg->Init.EWI));
+
+#if (USE_HAL_IWDG_REGISTER_CALLBACKS == 1)
+ /* Reset Callback pointers */
+ if (hiwdg->EwiCallback == NULL)
+ {
+ hiwdg->EwiCallback = HAL_IWDG_EarlyWakeupCallback;
+ }
+ if (hiwdg->MspInitCallback == NULL)
+ {
+ hiwdg->MspInitCallback = HAL_IWDG_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hiwdg->MspInitCallback(hiwdg);
+#else
+ /* Init the low level hardware */
+ HAL_IWDG_MspInit(hiwdg);
+#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */
+
+ /* Enable IWDG. LSI is turned on automatically */
+ __HAL_IWDG_START(hiwdg);
+
+ /* Enable write access to IWDG_PR, IWDG_RLR, IWDG_WINR and EWCR registers by writing
+ 0x5555 in KR */
+ IWDG_ENABLE_WRITE_ACCESS(hiwdg);
+
+ /* Write to IWDG registers the Prescaler & Reload values to work with */
+ hiwdg->Instance->PR = hiwdg->Init.Prescaler;
+ hiwdg->Instance->RLR = hiwdg->Init.Reload;
+
+ if (hiwdg->Init.EWI == IWDG_EWI_DISABLE)
+ {
+ /* EWI comparator value different from 0,
+ * Disable the early wakeup interrupt
+ * acknowledge the early wakeup interrupt in any cases. it clears the EWIF flag in SR register
+ * Set Watchdog Early Wakeup Comparator to 0x00
+ */
+ hiwdg->Instance->EWCR = IWDG_EWCR_EWIC;
+ }
+ else
+ {
+ /* EWI comparator value different from 0,
+ * Enable the early wakeup interrupt
+ * acknowledge the early wakeup interrupt in any cases. it clears the EWIF flag in SR register
+ * Set Watchdog Early Wakeup Comparator value
+ */
+ hiwdg->Instance->EWCR = IWDG_EWCR_EWIE | IWDG_EWCR_EWIC | hiwdg->Init.EWI;
+ }
+
+ /* Check pending flag, if previous update not done, return timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait for register to be updated */
+ while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
+ {
+ if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
+ {
+ if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* If window parameter is different than current value, modify window
+ register */
+ if (hiwdg->Instance->WINR != hiwdg->Init.Window)
+ {
+ /* Write to IWDG WINR the IWDG_Window value to compare with. In any case,
+ even if window feature is disabled, Watchdog will be reloaded by writing
+ windows register */
+ hiwdg->Instance->WINR = hiwdg->Init.Window;
+ }
+ else
+ {
+ /* Reload IWDG counter with value defined in the reload register */
+ __HAL_IWDG_RELOAD_COUNTER(hiwdg);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Initialize the IWDG MSP.
+ * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified IWDG module.
+ * @note When rewriting this function in user file, mechanism may be added
+ * to avoid multiple initialize when HAL_IWDG_Init function is called
+ * again to change parameters.
+ * @retval None
+ */
+__weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hiwdg);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_IWDG_MspInit could be implemented in the user file
+ */
+}
+
+
+#if (USE_HAL_IWDG_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User IWDG Callback
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hiwdg IWDG handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_IWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
+ * @arg @ref HAL_IWDG_MSPINIT_CB_ID MspInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_IWDG_RegisterCallback(IWDG_HandleTypeDef *hiwdg, HAL_IWDG_CallbackIDTypeDef CallbackID,
+ pIWDG_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ switch (CallbackID)
+ {
+ case HAL_IWDG_EWI_CB_ID:
+ hiwdg->EwiCallback = pCallback;
+ break;
+ case HAL_IWDG_MSPINIT_CB_ID:
+ hiwdg->MspInitCallback = pCallback;
+ break;
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+ }
+
+ return status;
+}
+
+
+/**
+ * @brief Unregister a IWDG Callback
+ * IWDG Callback is redirected to the weak (surcharged) predefined callback
+ * @param hiwdg IWDG handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_IWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
+ * @arg @ref HAL_IWDG_MSPINIT_CB_ID MspInit callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_IWDG_UnRegisterCallback(IWDG_HandleTypeDef *hiwdg, HAL_IWDG_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ switch (CallbackID)
+ {
+ case HAL_IWDG_EWI_CB_ID:
+ hiwdg->EwiCallback = HAL_IWDG_EarlyWakeupCallback;
+ break;
+ case HAL_IWDG_MSPINIT_CB_ID:
+ hiwdg->MspInitCallback = HAL_IWDG_MspInit;
+ break;
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ return status;
+}
+#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */
+
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup IWDG_Exported_Functions_Group2
+ * @brief IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Refresh the IWDG.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Refresh the IWDG.
+ * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified IWDG module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
+{
+ /* Reload IWDG counter with value defined in the reload register */
+ __HAL_IWDG_RELOAD_COUNTER(hiwdg);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Handle IWDG interrupt request.
+ * @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations
+ * or data logging must be performed before the actual reset is generated.
+ * The EWI interrupt is enabled by calling HAL_IWDG_Init function with
+ * EWIMode set to IWDG_EWI_ENABLE.
+ * When the downcounter reaches the value 0x40, and EWI interrupt is
+ * generated and the corresponding Interrupt Service Routine (ISR) can
+ * be used to trigger specific actions (such as communications or data
+ * logging), before resetting the device.
+ * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified IWDG module.
+ * @retval None
+ */
+void HAL_IWDG_IRQHandler(IWDG_HandleTypeDef *hiwdg)
+{
+ /* Check if IWDG Early Wakeup Interrupt occurred */
+ if ((hiwdg->Instance->SR & IWDG_SR_EWIF) != 0x00u)
+ {
+ /* Clear the IWDG Early Wakeup flag */
+ hiwdg->Instance->EWCR |= IWDG_EWCR_EWIC;
+
+#if (USE_HAL_IWDG_REGISTER_CALLBACKS == 1)
+ /* Early Wakeup registered callback */
+ hiwdg->EwiCallback(hiwdg);
+#else
+ /* Early Wakeup callback */
+ HAL_IWDG_EarlyWakeupCallback(hiwdg);
+#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */
+ }
+}
+
+
+/**
+ * @brief IWDG Early Wakeup callback.
+ * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified IWDG module.
+ * @retval None
+ */
+__weak void HAL_IWDG_EarlyWakeupCallback(IWDG_HandleTypeDef *hiwdg)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hiwdg);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_IWDG_EarlyWakeupCallback could be implemented in the user file
+ */
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_IWDG_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_lptim.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_lptim.c
new file mode 100644
index 00000000..749d5d26
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_lptim.c
@@ -0,0 +1,3783 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_lptim.c
+ * @author MCD Application Team
+ * @brief LPTIM HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Low Power Timer (LPTIM) peripheral:
+ * + Initialization and de-initialization functions.
+ * + Start/Stop operation functions in polling mode.
+ * + Start/Stop operation functions in interrupt mode.
+ * + Reading operation functions.
+ * + Peripheral State functions.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The LPTIM HAL driver can be used as follows:
+
+ (#)Initialize the LPTIM low level resources by implementing the
+ HAL_LPTIM_MspInit():
+ (++) Enable the LPTIM interface clock using __HAL_RCC_LPTIMx_CLK_ENABLE().
+ (++) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):
+ (+++) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().
+ (+++) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().
+ (+++) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().
+
+ (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function
+ configures mainly:
+ (++) The instance: LPTIM1, LPTIM2, LPTIM3 or LPTIM4.
+ (++) Clock: the counter clock.
+ (+++) Source : it can be either the ULPTIM input (IN1) or one of
+ the internal clock; (APB, LSE, LSI or MSI).
+ (+++) Prescaler: select the clock divider.
+ (++) UltraLowPowerClock : To be used only if the ULPTIM is selected
+ as counter clock source.
+ (+++) Polarity: polarity of the active edge for the counter unit
+ if the ULPTIM input is selected.
+ (+++) SampleTime: clock sampling time to configure the clock glitch
+ filter.
+ (++) Trigger: How the counter start.
+ (+++) Source: trigger can be software or one of the hardware triggers.
+ (+++) ActiveEdge : only for hardware trigger.
+ (+++) SampleTime : trigger sampling time to configure the trigger
+ glitch filter.
+ (++) OutputPolarity : 2 opposite polarities are possible.
+ (++) UpdateMode: specifies whether the update of the autoreload and
+ the compare values is done immediately or after the end of current
+ period.
+ (++) Input1Source: Source selected for input1 (GPIO or comparator output).
+ (++) Input2Source: Source selected for input2 (GPIO or comparator output).
+ Input2 is used only for encoder feature so is used only for LPTIM1 instance.
+
+ (#)Six modes are available:
+
+ (++) PWM Mode: To generate a PWM signal with specified period and pulse,
+ call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption
+ mode.
+
+ (++) One Pulse Mode: To generate pulse with specified width in response
+ to a stimulus, call HAL_LPTIM_OnePulse_Start() or
+ HAL_LPTIM_OnePulse_Start_IT() for interruption mode.
+
+ (++) Set once Mode: In this mode, the output changes the level (from
+ low level to high level if the output polarity is configured high, else
+ the opposite) when a compare match occurs. To start this mode, call
+ HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for
+ interruption mode.
+
+ (++) Encoder Mode: To use the encoder interface call
+ HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for
+ interruption mode. Only available for LPTIM1 instance.
+
+ (++) Time out Mode: an active edge on one selected trigger input rests
+ the counter. The first trigger event will start the timer, any
+ successive trigger event will reset the counter and the timer will
+ restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or
+ HAL_LPTIM_TimeOut_Start_IT() for interruption mode.
+
+ (++) Counter Mode: counter can be used to count external events on
+ the LPTIM Input1 or it can be used to count internal clock cycles.
+ To start this mode, call HAL_LPTIM_Counter_Start() or
+ HAL_LPTIM_Counter_Start_IT() for interruption mode.
+
+
+ (#) User can stop any process by calling the corresponding API:
+ HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is
+ already started in interruption mode.
+
+ (#) De-initialize the LPTIM peripheral using HAL_LPTIM_DeInit().
+
+ *** Callback registration ***
+ =============================================
+ [..]
+ The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ [..]
+ Use Function @ref HAL_LPTIM_RegisterCallback() to register a callback.
+ @ref HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle,
+ the Callback ID and a pointer to the user callback function.
+ [..]
+ Use function @ref HAL_LPTIM_UnRegisterCallback() to reset a callback to the
+ default weak function.
+ @ref HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ [..]
+ These functions allow to register/unregister following callbacks:
+
+ (+) MspInitCallback : LPTIM Base Msp Init Callback.
+ (+) MspDeInitCallback : LPTIM Base Msp DeInit Callback.
+ (+) CompareMatchCallback : Compare match Callback.
+ (+) AutoReloadMatchCallback : Auto-reload match Callback.
+ (+) TriggerCallback : External trigger event detection Callback.
+ (+) CompareWriteCallback : Compare register write complete Callback.
+ (+) AutoReloadWriteCallback : Auto-reload register write complete Callback.
+ (+) DirectionUpCallback : Up-counting direction change Callback.
+ (+) DirectionDownCallback : Down-counting direction change Callback.
+ (+) UpdateEventCallback : Update event detection Callback.
+ (+) RepCounterWriteCallback : Repetition counter register write complete Callback.
+
+ [..]
+ By default, after the Init and when the state is HAL_LPTIM_STATE_RESET
+ all interrupt callbacks are set to the corresponding weak functions:
+ examples @ref HAL_LPTIM_TriggerCallback(), @ref HAL_LPTIM_CompareMatchCallback().
+
+ [..]
+ Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
+ functionalities in the Init/DeInit only when these callbacks are null
+ (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init/DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ [..]
+ Callbacks can be registered/unregistered in HAL_LPTIM_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_LPTIM_RegisterCallback() before calling DeInit or Init function.
+
+ [..]
+ When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup LPTIM LPTIM
+ * @brief LPTIM HAL module driver.
+ * @{
+ */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+
+#if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3) || defined (LPTIM4)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup LPTIM_Private_Constants
+ * @{
+ */
+#define TIMEOUT 1000UL /* Timeout is 1s */
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static HAL_StatusTypeDef LPTIM_OC1_SetConfig(LPTIM_HandleTypeDef *hlptim, LPTIM_OC_ConfigTypeDef *sConfig);
+static HAL_StatusTypeDef LPTIM_OC2_SetConfig(LPTIM_HandleTypeDef *hlptim, LPTIM_OC_ConfigTypeDef *sConfig);
+static void LPTIM_IC1_SetConfig(LPTIM_HandleTypeDef *hlptim, LPTIM_IC_ConfigTypeDef *sConfig);
+static void LPTIM_IC2_SetConfig(LPTIM_HandleTypeDef *hlptim, LPTIM_IC_ConfigTypeDef *sConfig);
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag);
+void LPTIM_DMAError(DMA_HandleTypeDef *hdma);
+void LPTIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
+void LPTIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
+void LPTIM_DMAUpdateEventCplt(DMA_HandleTypeDef *hdma);
+void LPTIM_DMAUpdateEventHalfCplt(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef LPTIM_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t src, uint32_t dst,
+ uint32_t length);
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
+ * @{
+ */
+
+/** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the LPTIM according to the specified parameters in the
+ LPTIM_InitTypeDef and initialize the associated handle.
+ (+) DeInitialize the LPTIM peripheral.
+ (+) Initialize the LPTIM MSP.
+ (+) DeInitialize the LPTIM MSP.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the LPTIM according to the specified parameters in the
+ * LPTIM_InitTypeDef and initialize the associated handle.
+ * @param hlptim LPTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
+{
+ uint32_t tmpcfgr;
+
+ /* Check the LPTIM handle allocation */
+ if (hlptim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+ assert_param(IS_LPTIM_PERIOD(hlptim->Init.Period));
+
+ assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
+ assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
+ if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
+ || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
+ {
+ assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
+ assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
+ }
+ assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));
+ if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
+ {
+ assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
+ assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
+ }
+ assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
+ assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource));
+ assert_param(IS_LPTIM_REPETITION(hlptim->Init.RepetitionCounter));
+
+ if (hlptim->State == HAL_LPTIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hlptim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy weak callbacks */
+ LPTIM_ResetCallback(hlptim);
+
+ if (hlptim->MspInitCallback == NULL)
+ {
+ hlptim->MspInitCallback = HAL_LPTIM_MspInit;
+ }
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ hlptim->MspInitCallback(hlptim);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ HAL_LPTIM_MspInit(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+ }
+
+ /* Change the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_REPOK);
+
+ /* Set the repetition counter */
+ __HAL_LPTIM_REPETITIONCOUNTER_SET(hlptim, hlptim->Init.RepetitionCounter);
+
+ /* Wait for the completion of the write operation to the LPTIM_RCR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_REPOK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
+ /* Set LPTIM Period */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, hlptim->Init.Period);
+
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* Get the LPTIMx CFGR value */
+ tmpcfgr = hlptim->Instance->CFGR;
+
+ if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
+ || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
+ {
+ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
+ }
+ if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
+ {
+ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
+ }
+
+ /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
+ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
+ LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE));
+
+ /* Set initialization parameters */
+ tmpcfgr |= (hlptim->Init.Clock.Source |
+ hlptim->Init.Clock.Prescaler |
+ hlptim->Init.UpdateMode |
+ hlptim->Init.CounterSource);
+
+ /* Glitch filters for internal triggers and external inputs are configured
+ * only if an internal clock source is provided to the LPTIM
+ */
+ if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
+ {
+ tmpcfgr |= (hlptim->Init.Trigger.SampleTime |
+ hlptim->Init.UltraLowPowerClock.SampleTime);
+ }
+
+ /* Configure LPTIM external clock polarity and digital filter */
+ if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
+ || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
+ {
+ tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |
+ hlptim->Init.UltraLowPowerClock.SampleTime);
+ }
+
+ /* Configure LPTIM external trigger */
+ if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
+ {
+ /* Enable External trigger and set the trigger source */
+ tmpcfgr |= (hlptim->Init.Trigger.Source |
+ hlptim->Init.Trigger.ActiveEdge |
+ hlptim->Init.Trigger.SampleTime);
+ }
+
+ /* Write to LPTIMx CFGR */
+ hlptim->Instance->CFGR = tmpcfgr;
+
+ /* Configure LPTIM input sources */
+ if ((hlptim->Instance == LPTIM1) || (hlptim->Instance == LPTIM2))
+ {
+ /* Check LPTIM Input1 and Input2 sources */
+ assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source));
+ assert_param(IS_LPTIM_INPUT2_SOURCE(hlptim->Instance, hlptim->Init.Input2Source));
+
+ /* Configure LPTIM Input1 and Input2 sources */
+ hlptim->Instance->CFGR2 = (hlptim->Init.Input1Source | hlptim->Init.Input2Source);
+ }
+ else
+ {
+ if ((hlptim->Instance == LPTIM3) || (hlptim->Instance == LPTIM4))
+ {
+ /* Check LPTIM3 Input1 source */
+ assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source));
+
+ /* Configure LPTIM3 Input1 source */
+ hlptim->Instance->CFGR2 = hlptim->Init.Input1Source;
+ }
+ }
+
+ /* Initialize the LPTIM channels state */
+ LPTIM_CHANNEL_STATE_SET_ALL(hlptim, HAL_LPTIM_CHANNEL_STATE_READY);
+
+ /* Change the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitialize the LPTIM peripheral.
+ * @param hlptim LPTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the LPTIM handle allocation */
+ if (hlptim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Change the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ if (hlptim->Instance != LPTIM4)
+ {
+ hlptim->Instance->CCMR1 = 0;
+ }
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK);
+
+ __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_1, 0);
+ /* Wait for the completion of the write operation to the LPTIM_CCR1 register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if (hlptim->Instance != LPTIM4)
+ {
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP2OK);
+
+ __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_2, 0);
+ /* Wait for the completion of the write operation to the LPTIM_CCR2 register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP2OK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, 0);
+
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable the LPTIM Peripheral Clock */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ hlptim->Instance->CFGR = 0;
+ hlptim->Instance->CFGR2 = 0;
+
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ if (hlptim->MspDeInitCallback == NULL)
+ {
+ hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
+ }
+
+ /* DeInit the low level hardware: CLOCK, NVIC.*/
+ hlptim->MspDeInitCallback(hlptim);
+#else
+ /* DeInit the low level hardware: CLOCK, NVIC.*/
+ HAL_LPTIM_MspDeInit(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+
+ /* Change the LPTIM channels state */
+ LPTIM_CHANNEL_STATE_SET_ALL(hlptim, HAL_LPTIM_CHANNEL_STATE_RESET);
+
+ /* Change the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hlptim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the LPTIM MSP.
+ * @param hlptim LPTIM handle
+ * @retval None
+ */
+__weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hlptim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_LPTIM_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize LPTIM MSP.
+ * @param hlptim LPTIM handle
+ * @retval None
+ */
+__weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hlptim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_LPTIM_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions
+ * @brief Start-Stop operation functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### LPTIM Start Stop operation functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start the PWM mode.
+ (+) Stop the PWM mode.
+ (+) Start the One pulse mode.
+ (+) Stop the One pulse mode.
+ (+) Start the Set once mode.
+ (+) Stop the Set once mode.
+ (+) Start the Encoder mode.
+ (+) Stop the Encoder mode.
+ (+) Start the Timeout mode.
+ (+) Stop the Timeout mode.
+ (+) Start the Counter mode.
+ (+) Stop the Counter mode.
+
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start the LPTIM PWM generation.
+ * @param hlptim LPTIM handle
+ * @param Channel LPTIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
+ * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
+
+ if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance))
+ {
+ if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+ /* Set the LPTIM channel state */
+ LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
+ }
+ else
+ {
+ /* Check the LPTIM state */
+ if (hlptim->State != HAL_LPTIM_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+ }
+
+ /* Reset WAVE bit to set PWM mode */
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Enable LPTIM signal on the corresponding output pin */
+ __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
+
+ /* Start timer in continuous mode */
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the LPTIM PWM generation.
+ * @param hlptim LPTIM handle
+ * @param Channel LPTIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
+ * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
+
+ /* Set the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+ /* Disable LPTIM signal from the corresponding output pin */
+ __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance))
+ {
+ /* Set the LPTIM channel state */
+ LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
+ }
+ else
+ {
+ /* Set the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_READY;
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Start the LPTIM PWM generation in interrupt mode.
+ * @param hlptim LPTIM handle
+ * @param Channel LPTIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
+ * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
+
+ if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance))
+ {
+ if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+ /* Set the LPTIM channel state */
+ LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
+ }
+ else
+ {
+ /* Check the LPTIM state */
+ if (hlptim->State != HAL_LPTIM_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM state */
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+ }
+
+ /* Reset WAVE bit to set PWM mode */
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
+
+ switch (Channel)
+ {
+ case LPTIM_CHANNEL_1:
+ /* Enable interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
+ LPTIM_IT_UPDATE);
+ break;
+ case LPTIM_CHANNEL_2:
+ /* Enable interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
+ LPTIM_IT_UPDATE);
+ break;
+ default:
+ break;
+ }
+
+ /* Wait for the completion of the write operation to the LPTIM_DIER register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* If external trigger source is used, then enable external trigger interrupt */
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ {
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
+
+ /* Enable external trigger interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
+
+ /* Wait for the completion of the write operation to the LPTIM_DIER register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
+
+ /* Start timer in continuous mode */
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the LPTIM PWM generation in interrupt mode.
+ * @param hlptim LPTIM handle
+ * @param Channel LPTIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
+ * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
+
+ /* Set the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+ /* Disable LPTIM signal from the corresponding output pin */
+ __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
+
+ switch (Channel)
+ {
+ case LPTIM_CHANNEL_1:
+ /* Disable interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
+ LPTIM_IT_UPDATE);
+ break;
+ case LPTIM_CHANNEL_2:
+ /* Disable interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
+ LPTIM_IT_UPDATE);
+ break;
+ default:
+ break;
+ }
+
+ /* Wait for the completion of the write operation to the LPTIM_DIER register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* If external trigger source is used, then enable external trigger interrupt */
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ {
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
+
+ /* Enable external trigger interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
+
+ /* Wait for the completion of the write operation to the LPTIM_DIER register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance))
+ {
+ /* Set the LPTIM channel state */
+ LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
+ }
+ else
+ {
+ /* Set the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_READY;
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Start the LPTIM PWM generation in DMA mode.
+ * @param hlptim LPTIM handle
+ * @param Channel LPTIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
+ * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
+ * @param pData The destination Buffer address
+ * @param Length The length of data to be transferred from LPTIM peripheral to memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Start_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel, uint32_t *pData,
+ uint32_t Length)
+{
+ DMA_HandleTypeDef *hdma;
+
+ /* Check the parameters */
+ assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
+
+ if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance))
+ {
+ if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+ /* Set the LPTIM channel state */
+ LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
+ }
+ else
+ {
+ /* Check the LPTIM state */
+ if (hlptim->State != HAL_LPTIM_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM state */
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+ }
+
+ /* Reset WAVE bit to set PWM mode */
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Enable update event DMA request */
+ __HAL_LPTIM_ENABLE_DMA(hlptim, LPTIM_DMA_UPDATE);
+
+ /* Wait for the completion of the write operation to the LPTIM_DIER register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ switch (Channel)
+ {
+ case LPTIM_CHANNEL_1:
+ /* Set the DMA update event callbacks */
+ hlptim->hdma[LPTIM_DMA_ID_CC1]->XferCpltCallback = LPTIM_DMAUpdateEventCplt;
+ hlptim->hdma[LPTIM_DMA_ID_CC1]->XferHalfCpltCallback = LPTIM_DMAUpdateEventHalfCplt;
+
+ /* Set the DMA error callback */
+ hlptim->hdma[LPTIM_DMA_ID_CC1]->XferErrorCallback = LPTIM_DMAError;
+
+ /* Enable the DMA Channel */
+ hdma = hlptim->hdma[LPTIM_DMA_ID_CC1];
+ if (LPTIM_DMA_Start_IT(hdma, (uint32_t)pData, (uint32_t)&hlptim->Instance->CCR1, Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ break;
+ case LPTIM_CHANNEL_2:
+ /* Set the DMA update event callbacks */
+ hlptim->hdma[LPTIM_DMA_ID_CC2]->XferCpltCallback = LPTIM_DMAUpdateEventCplt;
+ hlptim->hdma[LPTIM_DMA_ID_CC2]->XferHalfCpltCallback = LPTIM_DMAUpdateEventHalfCplt;
+
+ /* Set the DMA error callback */
+ hlptim->hdma[LPTIM_DMA_ID_CC2]->XferErrorCallback = LPTIM_DMAError;
+
+ /* Enable the DMA Channel */
+ hdma = hlptim->hdma[LPTIM_DMA_ID_CC2];
+ if (LPTIM_DMA_Start_IT(hdma, (uint32_t)pData, (uint32_t)&hlptim->Instance->CCR2, Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Enable LPTIM signal on the corresponding output pin */
+ __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
+
+ /* Start timer in continuous mode */
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the LPTIM PWM generation in DMA mode.
+ * @param hlptim LPTIM handle
+ * @param Channel LPTIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
+ * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
+
+ /* Set the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+ /* Disable update event DMA request */
+ __HAL_LPTIM_DISABLE_DMA(hlptim, LPTIM_DMA_UPDATE);
+
+ switch (Channel)
+ {
+ case LPTIM_CHANNEL_1:
+ /* Disable update event DMA request */
+ (void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC1]);
+ break;
+ case LPTIM_CHANNEL_2:
+ /* Disable update event DMA request */
+ (void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC2]);
+ break;
+ default:
+ break;
+ }
+
+ /* Disable LPTIM signal from the corresponding output pin */
+ __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance))
+ {
+ /* Set the LPTIM channel state */
+ LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
+ }
+ else
+ {
+ /* Set the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_READY;
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Start the LPTIM One pulse generation.
+ * @param hlptim LPTIM handle
+ * @param Channel LPTIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
+ * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
+
+ if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance))
+ {
+ if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+ /* Set the LPTIM channel state */
+ LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
+ }
+ else
+ {
+ /* Check the LPTIM state */
+ if (hlptim->State != HAL_LPTIM_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM state */
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+ }
+
+ /* Reset WAVE bit to set one pulse mode */
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Enable LPTIM signal on the corresponding output pin */
+ __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
+
+ /* Start timer in single (one shot) mode */
+ __HAL_LPTIM_START_SINGLE(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the LPTIM One pulse generation.
+ * @param hlptim LPTIM handle
+ * @param Channel LPTIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
+ * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
+
+ /* Set the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+ /* Disable LPTIM signal on the corresponding output pin */
+ __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance))
+ {
+ /* Set the LPTIM channel state */
+ LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
+ }
+ else
+ {
+ /* Set the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_READY;
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Start the LPTIM One pulse generation in interrupt mode.
+ * @param hlptim LPTIM handle
+ * @param Channel LPTIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
+ * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
+
+ if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance))
+ {
+ if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+ /* Set the LPTIM channel state */
+ LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
+ }
+ else
+ {
+ /* Check the LPTIM state */
+ if (hlptim->State != HAL_LPTIM_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM state */
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+ }
+
+ /* Reset WAVE bit to set one pulse mode */
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
+
+ switch (Channel)
+ {
+ case LPTIM_CHANNEL_1:
+ /* Enable interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
+ LPTIM_IT_UPDATE);
+ break;
+ case LPTIM_CHANNEL_2:
+ /* Enable interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
+ LPTIM_IT_UPDATE);
+ break;
+ default:
+ break;
+ }
+
+ /* Wait for the completion of the write operation to the LPTIM_DIER register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* If external trigger source is used, then enable external trigger interrupt */
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ {
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
+ /* Enable external trigger interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
+ /* Wait for the completion of the write operation to the LPTIM_DIER register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Enable LPTIM signal on the corresponding output pin */
+ __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
+
+ /* Start timer in single (one shot) mode */
+ __HAL_LPTIM_START_SINGLE(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the LPTIM One pulse generation in interrupt mode.
+ * @param hlptim LPTIM handle
+ * @param Channel LPTIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
+ * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
+
+ /* Set the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+ /* Disable LPTIM signal on the corresponding output pin */
+ __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
+
+ switch (Channel)
+ {
+ case LPTIM_CHANNEL_1:
+ /* Disable interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
+ LPTIM_IT_UPDATE);
+ break;
+ case LPTIM_CHANNEL_2:
+ /* Disable interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
+ LPTIM_IT_UPDATE);
+ break;
+ default:
+ break;
+ }
+
+ /* Wait for the completion of the write operation to the LPTIM_DIER register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* If external trigger source is used, then enable external trigger interrupt */
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ {
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
+ /* Enable external trigger interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
+ /* Wait for the completion of the write operation to the LPTIM_DIER register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance))
+ {
+ /* Set the LPTIM channel state */
+ LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
+ }
+ else
+ {
+ /* Set the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_READY;
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Start the LPTIM in Set once mode.
+ * @param hlptim LPTIM handle
+ * @param Channel LPTIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
+ * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
+
+ if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance))
+ {
+ if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+ /* Set the LPTIM channel state */
+ LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
+ }
+ else
+ {
+ /* Check the LPTIM state */
+ if (hlptim->State != HAL_LPTIM_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM state */
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+ }
+
+ /* Set WAVE bit to enable the set once mode */
+ hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Enable LPTIM signal on the corresponding output pin */
+ __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
+
+ /* Start timer in single (one shot) mode */
+ __HAL_LPTIM_START_SINGLE(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the LPTIM Set once mode.
+ * @param hlptim LPTIM handle
+ * @param Channel LPTIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
+ * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
+
+ /* Set the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+ /* Disable LPTIM signal on the corresponding output pin */
+ __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance))
+ {
+ /* Set the LPTIM channel state */
+ LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
+ }
+ else
+ {
+ /* Set the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_READY;
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Start the LPTIM Set once mode in interrupt mode.
+ * @param hlptim LPTIM handle
+ * @param Channel LPTIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
+ * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
+
+ if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance))
+ {
+ if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+ /* Set the LPTIM channel state */
+ LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
+ }
+ else
+ {
+ /* Check the LPTIM state */
+ if (hlptim->State != HAL_LPTIM_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM state */
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+ }
+
+ /* Set WAVE bit to enable the set once mode */
+ hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
+
+ switch (Channel)
+ {
+ case LPTIM_CHANNEL_1:
+ /* Enable interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_UPDATE);
+ break;
+ case LPTIM_CHANNEL_2:
+ /* Enable interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_UPDATE);
+ break;
+ default:
+ break;
+ }
+
+ /* Wait for the completion of the write operation to the LPTIM_DIER register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* If external trigger source is used, then enable external trigger interrupt */
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ {
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
+ /* Enable external trigger interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
+ /* Wait for the completion of the write operation to the LPTIM_DIER register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Enable LPTIM signal on the corresponding output pin */
+ __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
+
+ /* Start timer in single (one shot) mode */
+ __HAL_LPTIM_START_SINGLE(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the LPTIM Set once mode in interrupt mode.
+ * @param hlptim LPTIM handle
+ * @param Channel LPTIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
+ * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
+
+ /* Set the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+ /* Disable LPTIM signal on the corresponding output pin */
+ __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
+
+ switch (Channel)
+ {
+ case LPTIM_CHANNEL_1:
+ /* Disable interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM);
+ break;
+ case LPTIM_CHANNEL_2:
+ /* Disable interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM);
+ break;
+ default:
+ break;
+ }
+
+ /* Wait for the completion of the write operation to the LPTIM_DIER register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* If external trigger source is used, then enable external trigger interrupt */
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ {
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
+ /* Enable external trigger interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
+
+ /* Wait for the completion of the write operation to the LPTIM_DIER register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance))
+ {
+ /* Set the LPTIM channel state */
+ LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
+ }
+ else
+ {
+ /* Set the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_READY;
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Start the Encoder interface.
+ * @param hlptim LPTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim)
+{
+ uint32_t tmpcfgr;
+
+ /* Check the parameters */
+ assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
+ assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
+ assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
+ assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
+
+ /* Set the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+ /* Get the LPTIMx CFGR value */
+ tmpcfgr = hlptim->Instance->CFGR;
+
+ /* Clear CKPOL bits */
+ tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
+
+ /* Set Input polarity */
+ tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity;
+
+ /* Write to LPTIMx CFGR */
+ hlptim->Instance->CFGR = tmpcfgr;
+
+ /* Set ENC bit to enable the encoder interface */
+ hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Start timer in continuous mode */
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the Encoder interface.
+ * @param hlptim LPTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
+
+ /* Set the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* Reset ENC bit to disable the encoder interface */
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
+
+ /* Change the TIM state*/
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Start the Encoder interface in interrupt mode.
+ * @param hlptim LPTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim)
+{
+ uint32_t tmpcfgr;
+
+ /* Check the parameters */
+ assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
+ assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
+ assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
+ assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
+
+ /* Set the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+ /* Configure edge sensitivity for encoder mode */
+ /* Get the LPTIMx CFGR value */
+ tmpcfgr = hlptim->Instance->CFGR;
+
+ /* Clear CKPOL bits */
+ tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
+
+ /* Set Input polarity */
+ tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity;
+
+ /* Write to LPTIMx CFGR */
+ hlptim->Instance->CFGR = tmpcfgr;
+
+ /* Set ENC bit to enable the encoder interface */
+ hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
+
+ /* Enable "switch to up/down direction" interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP | LPTIM_IT_DOWN);
+
+ /* Wait for the completion of the write operation to the LPTIM_DIER register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+
+ /* Start timer in continuous mode */
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the Encoder interface in interrupt mode.
+ * @param hlptim LPTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
+
+ /* Set the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* Reset ENC bit to disable the encoder interface */
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
+
+ /* Disable "switch to down/up direction" interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP | LPTIM_IT_DOWN);
+
+ /* Wait for the completion of the write operation to the LPTIM_DIER register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Start the Timeout function.
+ * @note The first trigger event will start the timer, any successive
+ * trigger event will reset the counter and the timer restarts.
+ * @param hlptim LPTIM handle
+ * @param Timeout Specifies the TimeOut value to reset the counter.
+ * This parameter must be a value between 0x0000 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Timeout)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+ assert_param(IS_LPTIM_PULSE(Timeout));
+
+ /* Set the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+ /* Set TIMOUT bit to enable the timeout function */
+ hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK);
+
+ /* Load the Timeout value in the compare register */
+ __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_1, Timeout);
+
+ /* Wait for the completion of the write operation to the LPTIM_CCR1 register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Start timer in continuous mode */
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the Timeout function.
+ * @param hlptim LPTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+ /* Set the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* Reset TIMOUT bit to enable the timeout function */
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
+
+ /* Change the TIM state*/
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Start the Timeout function in interrupt mode.
+ * @note The first trigger event will start the timer, any successive
+ * trigger event will reset the counter and the timer restarts.
+ * @param hlptim LPTIM handle
+ * @param Timeout Specifies the TimeOut value to reset the counter.
+ * This parameter must be a value between 0x0000 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Timeout)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+ assert_param(IS_LPTIM_PULSE(Timeout));
+
+ /* Set the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+ /* Set TIMOUT bit to enable the timeout function */
+ hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
+
+ /* Enable Compare match CH1 interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CC1);
+
+ /* Wait for the completion of the write operation to the LPTIM_DIER register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK);
+
+ /* Load the Timeout value in the compare register */
+ __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_1, Timeout);
+
+ /* Wait for the completion of the write operation to the LPTIM_CCR1 register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Start timer in continuous mode */
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the Timeout function in interrupt mode.
+ * @param hlptim LPTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+ /* Set the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* Reset TIMOUT bit to enable the timeout function */
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
+
+ /* Disable Compare match CH1 interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CC1);
+
+ /* Wait for the completion of the write operation to the LPTIM_DIER register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Start the Counter mode.
+ * @param hlptim LPTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+ /* Set the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+ /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
+ if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM)
+ && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
+ {
+ /* Check if clock is prescaled */
+ assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
+ /* Set clock prescaler to 0 */
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
+ }
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Start timer in continuous mode */
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the Counter mode.
+ * @param hlptim LPTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+ /* Set the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Start the Counter mode in interrupt mode.
+ * @param hlptim LPTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+ /* Set the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+ /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
+ if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM)
+ && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
+ {
+ /* Check if clock is prescaled */
+ assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
+ /* Set clock prescaler to 0 */
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
+ }
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
+
+ /* Enable interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK | LPTIM_IT_UPDATE);
+
+ /* Wait for the completion of the write operation to the LPTIM_DIER register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Start timer in continuous mode */
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the Counter mode in interrupt mode.
+ * @param hlptim LPTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+ /* Set the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
+
+ /* Disable interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK | LPTIM_IT_UPDATE);
+
+ /* Wait for the completion of the write operation to the LPTIM_DIER register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the LPTIM Input Capture measurement.
+ * @param hlptim LPTIM Input Capture handle
+ * @param Channel LPTIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_IC_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
+{
+ assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance));
+ assert_param(IS_LPTIM_CHANNELS(hlptim->Instance, Channel));
+
+ if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance))
+ {
+ if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+ /* Set the LPTIM channel state */
+ LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
+ }
+ else
+ {
+ /* Check the LPTIM state */
+ if (hlptim->State != HAL_LPTIM_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM state */
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+ }
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Start timer in continuous mode */
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+ /* Enable capture */
+ __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the LPTIM Input Capture measurement.
+ * @param hlptim LPTIM Input Capture handle
+ * @param Channel LPTIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_IC_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
+{
+ assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance));
+ assert_param(IS_LPTIM_CHANNELS(hlptim->Instance, Channel));
+
+ /* Disable capture */
+ __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* Set the LPTIM channel state */
+ LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the LPTIM Input Capture measurement in interrupt mode.
+ * @param hlptim LPTIM Input Capture handle
+ * @param Channel LPTIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_IC_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
+{
+ assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance));
+ assert_param(IS_LPTIM_CHANNELS(hlptim->Instance, Channel));
+
+ if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance))
+ {
+ if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+ /* Set the LPTIM channel state */
+ LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
+ }
+ else
+ {
+ /* Check the LPTIM state */
+ if (hlptim->State != HAL_LPTIM_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM state */
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+ }
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ switch (Channel)
+ {
+ case LPTIM_CHANNEL_1:
+ /* Enable Capture/Compare 1 interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CC1);
+ break;
+ case LPTIM_CHANNEL_2:
+ /* Disable Capture/Compare 2 interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CC2);
+ break;
+ default:
+ break;
+ }
+
+ /* Wait for the completion of the write operation to the LPTIM_DIER register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Start timer in continuous mode */
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+ /* Enable capture */
+ __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the LPTIM Input Capture measurement in interrupt mode.
+ * @param hlptim LPTIM Input Capture handle
+ * @param Channel LPTIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_IC_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
+{
+ assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance));
+ assert_param(IS_LPTIM_CHANNELS(hlptim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case LPTIM_CHANNEL_1:
+ /* Disable Capture/Compare 1 interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CC1);
+ break;
+ case LPTIM_CHANNEL_2:
+ /* Disable Capture/Compare 2 interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CC2);
+ break;
+ default:
+ return HAL_ERROR;
+ break;
+ }
+ /* Disable capture */
+ __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* Set the LPTIM channel state */
+ LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the LPTIM Input Capture measurement in DMA mode.
+ * @param hlptim LPTIM Input Capture handle
+ * @param Channel LPTIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
+ * @param pData The destination Buffer address
+ * @param Length The length of data to be transferred from LPTIM peripheral to memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_IC_Start_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel, uint32_t *pData,
+ uint32_t Length)
+{
+ DMA_HandleTypeDef *hdma;
+
+ assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance));
+ assert_param(IS_LPTIM_CHANNELS(hlptim->Instance, Channel));
+
+ if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance))
+ {
+ if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+ /* Set the LPTIM channel state */
+ LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
+ }
+ else
+ {
+ /* Check the LPTIM state */
+ if (hlptim->State != HAL_LPTIM_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM state */
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+ }
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ switch (Channel)
+ {
+ case LPTIM_CHANNEL_1:
+ /* Set the DMA capture callbacks */
+ hlptim->hdma[LPTIM_DMA_ID_CC1]->XferCpltCallback = LPTIM_DMACaptureCplt;
+ hlptim->hdma[LPTIM_DMA_ID_CC1]->XferHalfCpltCallback = LPTIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ hlptim->hdma[LPTIM_DMA_ID_CC1]->XferErrorCallback = LPTIM_DMAError;
+
+ /* Enable the DMA Channel */
+ hdma = hlptim->hdma[LPTIM_DMA_ID_CC1];
+ if (LPTIM_DMA_Start_IT(hdma, (uint32_t)&hlptim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+
+ /* Enable Capture/Compare 1 DMA request */
+ __HAL_LPTIM_ENABLE_DMA(hlptim, LPTIM_DMA_CC1);
+ break;
+
+ case LPTIM_CHANNEL_2:
+ /* Set the DMA capture callbacks */
+ hlptim->hdma[LPTIM_DMA_ID_CC2]->XferCpltCallback = LPTIM_DMACaptureCplt;
+ hlptim->hdma[LPTIM_DMA_ID_CC2]->XferHalfCpltCallback = LPTIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ hlptim->hdma[LPTIM_DMA_ID_CC2]->XferErrorCallback = LPTIM_DMAError;
+
+ /* Enable the DMA Channel */
+ hdma = hlptim->hdma[LPTIM_DMA_ID_CC2];
+ if (LPTIM_DMA_Start_IT(hdma, (uint32_t)&hlptim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+
+ /* Enable Capture/Compare 2 DMA request */
+ __HAL_LPTIM_ENABLE_DMA(hlptim, LPTIM_DMA_CC2);
+ break;
+
+ default:
+ break;
+ }
+
+ /* Wait for the completion of the write operation to the LPTIM_DIER register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Start timer in continuous mode */
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+ /* Enable capture */
+ __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the LPTIM Input Capture measurement in DMA mode.
+ * @param hlptim LPTIM Input Capture handle
+ * @param Channel LPTIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_IC_Stop_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
+{
+ assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance));
+ assert_param(IS_LPTIM_CHANNELS(hlptim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case LPTIM_CHANNEL_1:
+ /* Disable Capture/Compare 1 DMA request */
+ __HAL_LPTIM_DISABLE_DMA(hlptim, LPTIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC1]);
+ break;
+
+ case LPTIM_CHANNEL_2:
+ /* Disable Capture/Compare 2 DMA request */
+ __HAL_LPTIM_DISABLE_DMA(hlptim, LPTIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC2]);
+ break;
+ default:
+ return HAL_ERROR;
+ break;
+ }
+
+ /* Disable capture */
+ __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* Set the LPTIM channel state */
+ LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
+
+ /* Return function status */
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions
+ * @brief Read operation functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### LPTIM Read operation functions #####
+ ==============================================================================
+[..] This section provides LPTIM Reading functions.
+ (+) Read the counter value.
+ (+) Read the period (Auto-reload) value.
+ (+) Read the pulse (Compare)value.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the current counter value.
+ * @param hlptim LPTIM handle
+ * @retval Counter value.
+ */
+uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+ return (hlptim->Instance->CNT);
+}
+
+/**
+ * @brief Return the current Autoreload (Period) value.
+ * @param hlptim LPTIM handle
+ * @retval Autoreload value.
+ */
+uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+ return (hlptim->Instance->ARR);
+}
+
+/**
+ * @brief Return the current Compare (Pulse) value.
+ * @param hlptim LPTIM handle
+ * @param Channel LPTIM Channel to be selected
+ * This parameter can be one of the following values:
+ * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
+ * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
+ * @retval Compare value.
+ */
+uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
+{
+ uint32_t tmpccr;
+
+ /* Check the parameters */
+ assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case LPTIM_CHANNEL_1:
+ tmpccr = hlptim->Instance->CCR1;
+ break;
+ case LPTIM_CHANNEL_2:
+ tmpccr = hlptim->Instance->CCR2;
+ break;
+ default:
+ tmpccr = 0;
+ break;
+ }
+ return tmpccr;
+}
+
+/**
+ * @}
+ */
+/** @defgroup LPTIM_Exported_Functions_Group5 LPTIM Config function
+ * @brief Config channel
+ *
+@verbatim
+ ==============================================================================
+ ##### LPTIM Config function #####
+ ==============================================================================
+[..] This section provides LPTIM Config function.
+ (+) Configure channel: Output Compare mode, Period, Polarity.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief
+ * @param hlptim LPTIM handle
+ * @param sConfig The output configuration structure
+ * @param Channel LPTIM Channel to be configured
+ * This parameter can be one of the following values:
+ * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
+ * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_OC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, LPTIM_OC_ConfigTypeDef *sConfig,
+ uint32_t Channel)
+{
+ HAL_StatusTypeDef status;
+ /* Check the parameters */
+ assert_param(IS_LPTIM_CHANNELS(hlptim->Instance, Channel));
+ assert_param(IS_LPTIM_OC_POLARITY(sConfig->OCPolarity));
+ assert_param(IS_LPTIM_PULSE(sConfig->Pulse));
+
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+ switch (Channel)
+ {
+ case LPTIM_CHANNEL_1:
+ {
+ /* Check the parameters */
+ assert_param(IS_LPTIM_CC1_INSTANCE(hlptim->Instance));
+
+ /* Configure the LPTIM Channel 1 in Output Compare */
+ status = LPTIM_OC1_SetConfig(hlptim, sConfig);
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ break;
+ }
+ case LPTIM_CHANNEL_2:
+ {
+ /* Check the parameters */
+ assert_param(IS_LPTIM_CC2_INSTANCE(hlptim->Instance));
+
+ /* Configure the LPTIM Channel 2 in Output Compare */
+ status = LPTIM_OC2_SetConfig(hlptim, sConfig);
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ break;
+ }
+ default:
+ break;
+ }
+
+ /* Change the LPTIM state*/
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief
+ * @param hlptim LPTIM handle
+ * @param sConfig The input configuration structure
+ * @param Channel LPTIM Channel to be configured
+ * This parameter can be one of the following values:
+ * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
+ * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_IC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, LPTIM_IC_ConfigTypeDef *sConfig,
+ uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_CHANNELS(hlptim->Instance, Channel));
+ assert_param(IS_LPTIM_IC_PRESCALER(sConfig->ICPrescaler));
+ assert_param(IS_LPTIM_IC_POLARITY(sConfig->ICPolarity));
+ assert_param(IS_LPTIM_IC_FILTER(sConfig->ICFilter));
+
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+ switch (Channel)
+ {
+ case LPTIM_CHANNEL_1:
+ {
+ /* Check the parameters */
+ assert_param(IS_LPTIM_CC1_INSTANCE(hlptim->Instance));
+ assert_param(IS_LPTIM_IC1_SOURCE(hlptim->Instance, sConfig->ICInputSource));
+
+ /* Configure the LPTIM Channel 1 in Input Capture */
+ LPTIM_IC1_SetConfig(hlptim, sConfig);
+ break;
+ }
+ case LPTIM_CHANNEL_2:
+ {
+ /* Check the parameters */
+ assert_param(IS_LPTIM_CC2_INSTANCE(hlptim->Instance));
+ assert_param(IS_LPTIM_IC2_SOURCE(hlptim->Instance, sConfig->ICInputSource));
+
+ /* Configure the LPTIM Channel 2 in Input Capture */
+ LPTIM_IC2_SetConfig(hlptim, sConfig);
+ break;
+ }
+ default:
+ break;
+ }
+
+ /* Change the LPTIM state*/
+ hlptim->State = HAL_LPTIM_STATE_READY;
+ /* Return function status */
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler and callbacks
+ * @brief LPTIM IRQ handler.
+ *
+@verbatim
+ ==============================================================================
+ ##### LPTIM IRQ handler and callbacks #####
+ ==============================================================================
+[..] This section provides LPTIM IRQ handler and callback functions called within
+ the IRQ handler:
+ (+) LPTIM interrupt request handler
+ (+) Compare match Callback
+ (+) Auto-reload match Callback
+ (+) External trigger event detection Callback
+ (+) Compare register write complete Callback
+ (+) Auto-reload register write complete Callback
+ (+) Up-counting direction change Callback
+ (+) Down-counting direction change Callback
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Handle LPTIM interrupt request.
+ * @param hlptim LPTIM handle
+ * @retval None
+ */
+void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Capture Compare 1 interrupt */
+ if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC1) != RESET)
+ {
+ if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC1) != RESET)
+ {
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC1);
+ hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
+
+ /* Input capture event */
+ if ((hlptim->Instance->CCMR1 & LPTIM_CCMR1_CC1SEL) != 0x00U)
+ {
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ hlptim->IC_CaptureCallback(hlptim);
+#else
+ HAL_LPTIM_IC_CaptureCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+ }
+ /* Output compare event */
+ else
+ {
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ hlptim->CompareMatchCallback(hlptim);
+#else
+ HAL_LPTIM_CompareMatchCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+ }
+ hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+
+ /* Capture Compare 2 interrupt */
+ if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC2) != RESET)
+ {
+ if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC2) != RESET)
+ {
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC2);
+ hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
+
+ /* Input capture event */
+ if ((hlptim->Instance->CCMR1 & LPTIM_CCMR1_CC2SEL) != 0x00U)
+ {
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ hlptim->IC_CaptureCallback(hlptim);
+#else
+ HAL_LPTIM_IC_CaptureCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+ }
+ /* Output compare event */
+ else
+ {
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ hlptim->CompareMatchCallback(hlptim);
+#else
+ HAL_LPTIM_CompareMatchCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+ }
+ hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+
+ /* Over Capture 1 interrupt */
+ if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC1O) != RESET)
+ {
+ if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC1O) != RESET)
+ {
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC1O);
+ hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
+
+ /* Over capture event */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ hlptim->IC_OverCaptureCallback(hlptim);
+#else
+ HAL_LPTIM_IC_OverCaptureCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+ hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+
+ /* Over Capture 2 interrupt */
+ if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC2O) != RESET)
+ {
+ if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC2O) != RESET)
+ {
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC2O);
+ hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
+
+ /* Over capture event */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ hlptim->IC_OverCaptureCallback(hlptim);
+#else
+ HAL_LPTIM_IC_OverCaptureCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+ hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+
+ /* Autoreload match interrupt */
+ if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET)
+ {
+ if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) != RESET)
+ {
+ /* Clear Autoreload match flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM);
+
+ /* Autoreload match Callback */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ hlptim->AutoReloadMatchCallback(hlptim);
+#else
+ HAL_LPTIM_AutoReloadMatchCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* Trigger detected interrupt */
+ if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET)
+ {
+ if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) != RESET)
+ {
+ /* Clear Trigger detected flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG);
+
+ /* Trigger detected callback */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ hlptim->TriggerCallback(hlptim);
+#else
+ HAL_LPTIM_TriggerCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* Compare write interrupt */
+ if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMP1OK) != RESET)
+ {
+ if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMP1OK) != RESET)
+ {
+ /* Clear Compare write flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK);
+ hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
+ /* Compare write Callback */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ hlptim->CompareWriteCallback(hlptim);
+#else
+ HAL_LPTIM_CompareWriteCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* Compare write interrupt */
+ if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMP2OK) != RESET)
+ {
+ if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMP2OK) != RESET)
+ {
+ /* Clear Compare write flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP2OK);
+ hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
+ /* Compare write Callback */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ hlptim->CompareWriteCallback(hlptim);
+#else
+ HAL_LPTIM_CompareWriteCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* Autoreload write interrupt */
+ if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET)
+ {
+ if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) != RESET)
+ {
+ /* Clear Autoreload write flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
+ /* Autoreload write Callback */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ hlptim->AutoReloadWriteCallback(hlptim);
+#else
+ HAL_LPTIM_AutoReloadWriteCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* Direction counter changed from Down to Up interrupt */
+ if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET)
+ {
+ if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) != RESET)
+ {
+ /* Clear Direction counter changed from Down to Up flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP);
+
+ /* Direction counter changed from Down to Up Callback */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ hlptim->DirectionUpCallback(hlptim);
+#else
+ HAL_LPTIM_DirectionUpCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* Direction counter changed from Up to Down interrupt */
+ if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET)
+ {
+ if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) != RESET)
+ {
+ /* Clear Direction counter changed from Up to Down flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN);
+
+ /* Direction counter changed from Up to Down Callback */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ hlptim->DirectionDownCallback(hlptim);
+#else
+ HAL_LPTIM_DirectionDownCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* Repetition counter underflowed (or contains zero) and the LPTIM counter
+ overflowed */
+ if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UPDATE) != RESET)
+ {
+ if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UPDATE) != RESET)
+ {
+ /* Clear update event flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UPDATE);
+
+ /* Update event Callback */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ hlptim->UpdateEventCallback(hlptim);
+#else
+ HAL_LPTIM_UpdateEventCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* Successful APB bus write to repetition counter register */
+ if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_REPOK) != RESET)
+ {
+ if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_REPOK) != RESET)
+ {
+ /* Clear successful APB bus write to repetition counter flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_REPOK);
+
+ /* Successful APB bus write to repetition counter Callback */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ hlptim->RepCounterWriteCallback(hlptim);
+#else
+ HAL_LPTIM_RepCounterWriteCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+ }
+ }
+}
+
+/**
+ * @brief Compare match callback in non-blocking mode.
+ * @param hlptim LPTIM handle
+ * @retval None
+ */
+__weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hlptim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_LPTIM_CompareMatchCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Autoreload match callback in non-blocking mode.
+ * @param hlptim LPTIM handle
+ * @retval None
+ */
+__weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hlptim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Trigger detected callback in non-blocking mode.
+ * @param hlptim LPTIM handle
+ * @retval None
+ */
+__weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hlptim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_LPTIM_TriggerCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Compare write callback in non-blocking mode.
+ * @param hlptim LPTIM handle
+ * @retval None
+ */
+__weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hlptim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_LPTIM_CompareWriteCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Autoreload write callback in non-blocking mode.
+ * @param hlptim LPTIM handle
+ * @retval None
+ */
+__weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hlptim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Direction counter changed from Down to Up callback in non-blocking mode.
+ * @param hlptim LPTIM handle
+ * @retval None
+ */
+__weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hlptim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_LPTIM_DirectionUpCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Direction counter changed from Up to Down callback in non-blocking mode.
+ * @param hlptim LPTIM handle
+ * @retval None
+ */
+__weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hlptim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_LPTIM_DirectionDownCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Repetition counter underflowed (or contains zero) and LPTIM counter overflowed callback in non-blocking mode.
+ * @param hlptim LPTIM handle
+ * @retval None
+ */
+__weak void HAL_LPTIM_UpdateEventCallback(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hlptim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_LPTIM_UpdateEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Successful APB bus write to repetition counter register callback in non-blocking mode.
+ * @param hlptim LPTIM handle
+ * @retval None
+ */
+__weak void HAL_LPTIM_RepCounterWriteCallback(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hlptim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_LPTIM_RepCounterWriteCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Input Capture callback in non-blocking mode
+ * @param hlptim LPTIM handle
+ * @retval None
+ */
+__weak void HAL_LPTIM_IC_CaptureCallback(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hlptim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_LPTIM_IC_CaptureCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Over Capture callback in non-blocking mode
+ * @param hlptim LPTIM handle
+ * @retval None
+ */
+__weak void HAL_LPTIM_IC_OverCaptureCallback(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hlptim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_LPTIM_IC_OverCaptureCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Input Capture half complete callback in non-blocking mode
+ * @param hlptim LPTIM IC handle
+ * @retval None
+ */
+__weak void HAL_LPTIM_IC_CaptureHalfCpltCallback(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hlptim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_LPTIM_IC_CaptureHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Update event half complete callback in non-blocking mode
+ * @param hlptim LPTIM handle
+ * @retval None
+ */
+__weak void HAL_LPTIM_UpdateEventHalfCpltCallback(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hlptim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_LPTIM_UpdateEventHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Error callback in non-blocking mode
+ * @param hlptim LPTIM handle
+ * @retval None
+ */
+__weak void HAL_LPTIM_ErrorCallback(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hlptim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_LPTIM_ErrorCallback could be implemented in the user file
+ */
+}
+
+
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User LPTIM callback to be used instead of the weak predefined callback
+ * @param hlptim LPTIM handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID
+ * @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID
+ * @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID
+ * @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
+ * @arg @ref HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID
+ * @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID
+ * @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
+ * @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID
+ * @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID
+ * @arg @ref HAL_LPTIM_UPDATE_EVENT_CB_ID Update event detection Callback ID
+ * @arg @ref HAL_LPTIM_REP_COUNTER_WRITE_CB_ID Repetition counter register write complete Callback ID
+ * @arg @ref HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID Update event Half detection Callback ID
+ * @arg @ref HAL_LPTIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+ * @arg @ref HAL_LPTIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
+ * @arg @ref HAL_LPTIM_OVER_CAPTURE_CB_ID Over Capture Callback ID
+ * @arg @ref HAL_LPTIM_ERROR_CB_ID Error Callback ID
+ * @param pCallback pointer to the callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim,
+ HAL_LPTIM_CallbackIDTypeDef CallbackID,
+ pLPTIM_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hlptim);
+
+ if (hlptim->State == HAL_LPTIM_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_LPTIM_MSPINIT_CB_ID :
+ hlptim->MspInitCallback = pCallback;
+ break;
+
+ case HAL_LPTIM_MSPDEINIT_CB_ID :
+ hlptim->MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_LPTIM_COMPARE_MATCH_CB_ID :
+ hlptim->CompareMatchCallback = pCallback;
+ break;
+
+ case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID :
+ hlptim->AutoReloadMatchCallback = pCallback;
+ break;
+
+ case HAL_LPTIM_TRIGGER_CB_ID :
+ hlptim->TriggerCallback = pCallback;
+ break;
+
+ case HAL_LPTIM_COMPARE_WRITE_CB_ID :
+ hlptim->CompareWriteCallback = pCallback;
+ break;
+
+ case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID :
+ hlptim->AutoReloadWriteCallback = pCallback;
+ break;
+
+ case HAL_LPTIM_DIRECTION_UP_CB_ID :
+ hlptim->DirectionUpCallback = pCallback;
+ break;
+
+ case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
+ hlptim->DirectionDownCallback = pCallback;
+ break;
+
+ case HAL_LPTIM_UPDATE_EVENT_CB_ID :
+ hlptim->UpdateEventCallback = pCallback;
+ break;
+
+ case HAL_LPTIM_REP_COUNTER_WRITE_CB_ID :
+ hlptim->RepCounterWriteCallback = pCallback;
+ break;
+
+ case HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID :
+ hlptim->UpdateEventHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_LPTIM_IC_CAPTURE_CB_ID :
+ hlptim->IC_CaptureCallback = pCallback;
+ break;
+
+ case HAL_LPTIM_IC_CAPTURE_HALF_CB_ID :
+ hlptim->IC_CaptureHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_LPTIM_OVER_CAPTURE_CB_ID :
+ hlptim->IC_OverCaptureCallback = pCallback;
+ break;
+
+ case HAL_LPTIM_ERROR_CB_ID :
+ hlptim->ErrorCallback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hlptim->State == HAL_LPTIM_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_LPTIM_MSPINIT_CB_ID :
+ hlptim->MspInitCallback = pCallback;
+ break;
+
+ case HAL_LPTIM_MSPDEINIT_CB_ID :
+ hlptim->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hlptim);
+
+ return status;
+}
+
+/**
+ * @brief Unregister a LPTIM callback
+ * LLPTIM callback is redirected to the weak predefined callback
+ * @param hlptim LPTIM handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID
+ * @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID
+ * @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID
+ * @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
+ * @arg @ref HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID
+ * @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID
+ * @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
+ * @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID
+ * @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID
+ * @arg @ref HAL_LPTIM_UPDATE_EVENT_CB_ID Update event detection Callback ID
+ * @arg @ref HAL_LPTIM_REP_COUNTER_WRITE_CB_ID Repetition counter register write complete Callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim,
+ HAL_LPTIM_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hlptim);
+
+ if (hlptim->State == HAL_LPTIM_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_LPTIM_MSPINIT_CB_ID :
+ /* Legacy weak MspInit Callback */
+ hlptim->MspInitCallback = HAL_LPTIM_MspInit;
+ break;
+
+ case HAL_LPTIM_MSPDEINIT_CB_ID :
+ /* Legacy weak Msp DeInit Callback */
+ hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
+ break;
+
+ case HAL_LPTIM_COMPARE_MATCH_CB_ID :
+ /* Legacy weak Compare match Callback */
+ hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback;
+ break;
+
+ case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID :
+ /* Legacy weak Auto-reload match Callback */
+ hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback;
+ break;
+
+ case HAL_LPTIM_TRIGGER_CB_ID :
+ /* Legacy weak External trigger event detection Callback */
+ hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback;
+ break;
+
+ case HAL_LPTIM_COMPARE_WRITE_CB_ID :
+ /* Legacy weak Compare register write complete Callback */
+ hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback;
+ break;
+
+ case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID :
+ /* Legacy weak Auto-reload register write complete Callback */
+ hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback;
+ break;
+
+ case HAL_LPTIM_DIRECTION_UP_CB_ID :
+ /* Legacy weak Up-counting direction change Callback */
+ hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback;
+ break;
+
+ case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
+ /* Legacy weak Down-counting direction change Callback */
+ hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback;
+ break;
+
+ case HAL_LPTIM_UPDATE_EVENT_CB_ID :
+ /* Legacy weak Update event detection Callback */
+ hlptim->UpdateEventCallback = HAL_LPTIM_UpdateEventCallback;
+ break;
+
+ case HAL_LPTIM_REP_COUNTER_WRITE_CB_ID :
+ /* Legacy weak Repetition counter register write complete Callback */
+ hlptim->RepCounterWriteCallback = HAL_LPTIM_RepCounterWriteCallback;
+ break;
+
+ case HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID :
+ /* Legacy weak Update event half complete detection Callback */
+ hlptim->UpdateEventHalfCpltCallback = HAL_LPTIM_UpdateEventHalfCpltCallback;
+ break;
+
+ case HAL_LPTIM_IC_CAPTURE_CB_ID :
+ /* Legacy weak IC Capture Callback */
+ hlptim->IC_CaptureCallback = HAL_LPTIM_IC_CaptureCallback;
+ break;
+
+ case HAL_LPTIM_IC_CAPTURE_HALF_CB_ID :
+ /* Legacy weak IC Capture half complete Callback */
+ hlptim->IC_CaptureHalfCpltCallback = HAL_LPTIM_IC_CaptureHalfCpltCallback;
+ break;
+
+ case HAL_LPTIM_OVER_CAPTURE_CB_ID :
+ /* Legacy weak IC over capture Callback */
+ hlptim->IC_OverCaptureCallback = HAL_LPTIM_IC_OverCaptureCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hlptim->State == HAL_LPTIM_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_LPTIM_MSPINIT_CB_ID :
+ /* Legacy weak MspInit Callback */
+ hlptim->MspInitCallback = HAL_LPTIM_MspInit;
+ break;
+
+ case HAL_LPTIM_MSPDEINIT_CB_ID :
+ /* Legacy weak Msp DeInit Callback */
+ hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hlptim);
+
+ return status;
+}
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Group5 Peripheral State functions
+ * @brief Peripheral State functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the LPTIM handle state.
+ * @param hlptim LPTIM handle
+ * @retval HAL state
+ */
+HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Return LPTIM handle state */
+ return hlptim->State;
+}
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
+ * @{
+ */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Reset interrupt callbacks to the legacy weak callbacks.
+ * @param lptim pointer to a LPTIM_HandleTypeDef structure that contains
+ * the configuration information for LPTIM module.
+ * @retval None
+ */
+static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim)
+{
+ /* Reset the LPTIM callback to the legacy weak callbacks */
+ lptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback;
+ lptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback;
+ lptim->TriggerCallback = HAL_LPTIM_TriggerCallback;
+ lptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback;
+ lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback;
+ lptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback;
+ lptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback;
+ lptim->UpdateEventCallback = HAL_LPTIM_UpdateEventCallback;
+ lptim->RepCounterWriteCallback = HAL_LPTIM_RepCounterWriteCallback;
+ lptim->UpdateEventHalfCpltCallback = HAL_LPTIM_UpdateEventHalfCpltCallback;
+ lptim->IC_CaptureCallback = HAL_LPTIM_IC_CaptureCallback;
+ lptim->IC_CaptureHalfCpltCallback = HAL_LPTIM_IC_CaptureHalfCpltCallback;
+ lptim->IC_OverCaptureCallback = HAL_LPTIM_IC_OverCaptureCallback;
+ lptim->ErrorCallback = HAL_LPTIM_ErrorCallback;
+}
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+
+/**
+ * @brief LPTimer Wait for flag set
+ * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
+ * the configuration information for LPTIM module.
+ * @param flag The lptim flag
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag)
+{
+ HAL_StatusTypeDef result = HAL_OK;
+ uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL);
+ do
+ {
+ count--;
+ if (count == 0UL)
+ {
+ result = HAL_TIMEOUT;
+ }
+ } while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
+
+ return result;
+}
+
+/**
+ * @brief LPTIM DMA error callback
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void LPTIM_DMAError(DMA_HandleTypeDef *hdma)
+{
+ LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ hlptim->ErrorCallback(hlptim);
+#else
+ HAL_LPTIM_ErrorCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief LPTIM DMA Capture complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void LPTIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
+{
+ LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
+ if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC1])
+ {
+ hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
+ }
+ else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC2])
+ {
+ hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ hlptim->IC_CaptureCallback(hlptim);
+#else
+ HAL_LPTIM_IC_CaptureCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+
+ hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief LPTIM DMA Capture half complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void LPTIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
+ if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC1])
+ {
+ hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
+ }
+ else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC2])
+ {
+ hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ hlptim->IC_CaptureHalfCpltCallback(hlptim);
+#else
+ HAL_LPTIM_IC_CaptureHalfCpltCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+
+ hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief LPTIM DMA Update event complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void LPTIM_DMAUpdateEventCplt(DMA_HandleTypeDef *hdma)
+{
+ LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
+ if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC1])
+ {
+ hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
+ }
+ else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC2])
+ {
+ hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ hlptim->UpdateEventCallback(hlptim);
+#else
+ HAL_LPTIM_UpdateEventCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+
+ hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief LPTIM DMA Capture half complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void LPTIM_DMAUpdateEventHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
+ if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC1])
+ {
+ hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
+ }
+ else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC2])
+ {
+ hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ hlptim->UpdateEventHalfCpltCallback(hlptim);
+#else
+ HAL_LPTIM_UpdateEventHalfCpltCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+
+ hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
+}
+/**
+ * @brief LPTimer Output Compare 1 configuration
+ * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
+ * the configuration information for LPTIM module.
+ * @param sConfig The output configuration structure
+ * @retval None
+ */
+static HAL_StatusTypeDef LPTIM_OC1_SetConfig(LPTIM_HandleTypeDef *hlptim, LPTIM_OC_ConfigTypeDef *sConfig)
+{
+ uint32_t tmpccmr1;
+ uint32_t tmpcfgr;
+
+ tmpccmr1 = hlptim->Instance->CCMR1;
+ tmpccmr1 &= ~(LPTIM_CCMR1_CC1P_Msk | LPTIM_CCMR1_CC1SEL_Msk);
+
+ if (hlptim->Instance == LPTIM4)
+ {
+ tmpcfgr = hlptim->Instance->CFGR;
+ tmpcfgr &= ~LPTIM_CFGR_WAVPOL_Msk;
+ tmpcfgr |= sConfig->OCPolarity << LPTIM_CFGR_WAVPOL_Pos;
+
+ /* Write to CFGR register */
+ hlptim->Instance->CFGR = tmpcfgr;
+ }
+ else
+ {
+ tmpccmr1 |= sConfig->OCPolarity << LPTIM_CCMR1_CC1P_Pos;
+ }
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK);
+
+ /* Write to CCR1 register */
+ __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_1, sConfig->Pulse);
+
+ /* Wait for the completion of the write operation to the LPTIM_CCR1 register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* Write to CCMR1 register */
+ hlptim->Instance->CCMR1 = tmpccmr1;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief LPTimer Output Compare 2 configuration
+ * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
+ * the configuration information for LPTIM module.
+ * @param sConfig The output configuration structure
+ * @retval None
+ */
+static HAL_StatusTypeDef LPTIM_OC2_SetConfig(LPTIM_HandleTypeDef *hlptim, LPTIM_OC_ConfigTypeDef *sConfig)
+{
+ uint32_t tmpccmr1;
+
+ tmpccmr1 = hlptim->Instance->CCMR1;
+ tmpccmr1 &= ~(LPTIM_CCMR1_CC2P_Msk | LPTIM_CCMR1_CC2SEL_Msk);
+ tmpccmr1 |= sConfig->OCPolarity << LPTIM_CCMR1_CC2P_Pos;
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP2OK);
+
+ /* Write to CCR2 register */
+ __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_2, sConfig->Pulse);
+
+ /* Wait for the completion of the write operation to the LPTIM_CCR2 register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP2OK) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* Write to CCMR1 register */
+ hlptim->Instance->CCMR1 = tmpccmr1;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief LPTimer Input Capture 1 configuration
+ * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
+ * the configuration information for LPTIM module.
+ * @param sConfig The input configuration structure
+ * @retval None
+ */
+static void LPTIM_IC1_SetConfig(LPTIM_HandleTypeDef *hlptim, LPTIM_IC_ConfigTypeDef *sConfig)
+{
+ uint32_t tmpccmr1;
+ uint32_t tmpcfgr2;
+
+ tmpccmr1 = hlptim->Instance->CCMR1;
+ tmpccmr1 &= ~(LPTIM_CCMR1_IC1PSC_Msk | LPTIM_CCMR1_CC1P_Msk | LPTIM_CCMR1_IC1F_Msk);
+ tmpccmr1 |= sConfig->ICPrescaler |
+ sConfig->ICPolarity |
+ sConfig->ICFilter |
+ LPTIM_CCMR1_CC1SEL;
+
+ tmpcfgr2 = hlptim->Instance->CFGR2;
+ tmpcfgr2 &= ~(LPTIM_CFGR2_IC1SEL_Msk);
+ tmpcfgr2 |= sConfig->ICInputSource;
+
+ /* Write to CCMR1 register */
+ hlptim->Instance->CCMR1 = tmpccmr1;
+
+ /* Write to CFGR2 register */
+ hlptim->Instance->CFGR2 = tmpcfgr2;
+}
+
+/**
+ * @brief LPTimer Input Capture 2 configuration
+ * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
+ * the configuration information for LPTIM module.
+ * @param sConfig The input configuration structure
+ * @retval None
+ */
+static void LPTIM_IC2_SetConfig(LPTIM_HandleTypeDef *hlptim, LPTIM_IC_ConfigTypeDef *sConfig)
+{
+ uint32_t tmpccmr1;
+ uint32_t tmpcfgr2;
+
+ tmpccmr1 = hlptim->Instance->CCMR1;
+ tmpccmr1 &= ~(LPTIM_CCMR1_IC2PSC_Msk | LPTIM_CCMR1_CC2P_Msk | LPTIM_CCMR1_IC2F_Msk);
+ tmpccmr1 |= (sConfig->ICPrescaler << (LPTIM_CCMR1_IC2PSC_Pos - LPTIM_CCMR1_IC1PSC_Pos)) |
+ (sConfig->ICPolarity << (LPTIM_CCMR1_CC2P_Pos - LPTIM_CCMR1_CC1P_Pos)) |
+ (sConfig->ICFilter << (LPTIM_CCMR1_IC2F_Pos - LPTIM_CCMR1_IC1F_Pos)) |
+ LPTIM_CCMR1_CC2SEL;
+
+ tmpcfgr2 = hlptim->Instance->CFGR2;
+ tmpcfgr2 &= ~(LPTIM_CFGR2_IC2SEL_Msk);
+ tmpcfgr2 |= sConfig->ICInputSource;
+
+ /* Write to CCMR1 register */
+ hlptim->Instance->CCMR1 = tmpccmr1;
+
+ /* Write to CFGR2 register */
+ hlptim->Instance->CFGR2 = tmpcfgr2;
+}
+
+/**
+ * @brief Start the DMA data transfer.
+ * @param hdma DMA handle
+ * @param src The source memory Buffer address.
+ * @param dst The destination memory Buffer address.
+ * @param length The size of a source block transfer in byte.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef LPTIM_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t src, uint32_t dst,
+ uint32_t length)
+{
+ HAL_StatusTypeDef status;
+
+ /* Enable the DMA channel */
+ if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if ((hdma->LinkedListQueue != 0U) && (hdma->LinkedListQueue->Head != 0U))
+ {
+ /* Enable the DMA channel */
+ hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = length;
+ hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)src;
+ hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)dst;
+
+ status = HAL_DMAEx_List_Start_IT(hdma);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_DMA_Start_IT(hdma, src, dst, length);
+ }
+
+ return status;
+}
+/**
+ * @}
+ */
+#endif /* LPTIM1 || LPTIM2 || LPTIM3 || LPTIM4 */
+
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mdf.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mdf.c
new file mode 100644
index 00000000..e1a085e9
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mdf.c
@@ -0,0 +1,3582 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_mdf.c
+ * @author MCD Application Team
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Multi-function Digital Filter (MDF)
+ * peripheral:
+ * + Initialization and de-initialization
+ * + Acquisition
+ * + Clock absence detection
+ * + Short circuit detection
+ * + Out-off limit detection
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ *** Initialization and de-initialization ***
+ ============================================
+ [..]
+ (#) User has first to initialize MDF or ADF instance.
+ (#) As prerequisite, fill in the HAL_MDF_MspInit() :
+ (++) Enable MDFz or ADFz clock interface with __HAL_RCC_MDFz_CLK_ENABLE()
+ or __HAL_RCC_ADFz_CLK_ENABLE().
+ (++) Enable the clocks for the used GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
+ (++) Configure these pins in alternate mode using HAL_GPIO_Init().
+ (++) If interrupt mode is used, enable and configure MDFz_FLTx or ADFz
+ interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
+ (++) If DMA mode is used, initialize and configure DMA.
+ (#) Configure the common parameters (only for first MDF or ADF instance init),
+ serial interface parameters and filter bitstream selection by calling
+ HAL_MDF_Init() function.
+
+ [..]
+ (#) User can de-initialize MDF or ADF instance with HAL_MDF_DeInit() function.
+
+ *** Acquisition ***
+ ===================
+ [..]
+ (#) Configure filter parameters and start acquisition using HAL_MDF_AcqStart(),
+ HAL_MDF_AcqStart_IT() or HAL_MDF_AcqStart_DMA().
+ (#) In polling mode :
+ (++) Use HAL_MDF_PollForAcq() to detect the end of acquisition.
+ Use HAL_MDF_GetAcqValue to get acquisition value.
+ (++) Only for MDF instance, use HAL_MDF_PollForSnapshotAcq() to detect
+ the end of snapshot acquisition.
+ Use HAL_MDF_GetSnapshotAcqValue to get snapshot acquisition value.
+ (++) Only for ADF instance, use HAL_MDF_PollForSndLvl() to detect and get
+ new sound level value and ambient noise value.
+ (++) Only for ADF instance, use HAL_MDF_PollForSad() to detect sound activity.
+ (#) In interrupt mode :
+ (++) HAL_MDF_AcqCpltCallback() will be called at the end of acquisition.
+ Use HAL_MDF_GetAcqValue to get acquisition value or use
+ HAL_MDF_GetSnapshotAcqValue to get snapshot acquisition value.
+ (++) Only for ADF instance, HAL_MDF_SndLvlCallback() will be called when new
+ sound level and ambient noise values are available.
+ (++) Only for ADF instance, HAL_MDF_SadCallback() will be called when
+ sound activity detection occurs.
+ (++) HAL_MDF_ErrorCallback() will be called if overflow, filter overrun or
+ saturation occurs.
+ Use HAL_MDF_GetErrorCode() to get the corresponding error.
+ (#) In DMA mode :
+ (++) HAL_MDF_AcqHalfCpltCallback() and HAL_MDF_AcqCpltCallback() will be called
+ respectively at the half acquisition and at the acquisition complete.
+ (++) Only for ADF instance, HAL_MDF_SndLvlCallback() will be called when new
+ sound level and ambient noise values are available.
+ (++) Only for ADF instance, HAL_MDF_SadCallback() will be called when
+ sound activity detection occurs.
+ (++) HAL_MDF_ErrorCallback() will be called if overflow, filter overrun,
+ saturation or DMA error occurs.
+ Use HAL_MDF_GetErrorCode() to get the corresponding error.
+ (#) Use HAL_MDF_GenerateTrgo() to generate pulse on TRGO signal.
+ (#) During acquisition, use HAL_MDF_SetDelay() and HAL_MDF_GetDelay() to respectively
+ set and get the delay on data source.
+ (#) During acquisition, use HAL_MDF_SetGain() and HAL_MDF_GetGain() to respectively
+ set and get the filter gain.
+ (#) During acquisition, use HAL_MDF_SetOffset() and HAL_MDF_GetOffset() to respectively
+ set and get the filter offset error compensation.
+ (#) During acquisition, only for MDF instance, use HAL_MDF_SetOffset() and HAL_MDF_GetOffset()
+ to respectively set and get the filter offset error compensation.
+ (#) Stop acquisition using HAL_MDF_AcqStop(), HAL_MDF_AcqStop_IT() or HAL_MDF_AcqStop_DMA().
+
+ *** Clock absence detection ***
+ ===============================
+ [..]
+ (#) Clock absence detection is always enabled so no need to start clock absence detection
+ in polling mode.
+ Use HAL_MDF_CkabStart_IT() to start clock absence detection in interrupt mode.
+ (#) In polling mode, use HAL_MDF_PollForCkab() to detect the clock absence.
+ (#) In interrupt mode, HAL_MDF_ErrorCallback() will be called if clock absence detection
+ occurs.
+ Use HAL_MDF_GetErrorCode() to get the corresponding error.
+ (#) Stop clock absence detection in interrupt mode using HAL_MDF_CkabStop_IT().
+
+ *** Short circuit detection ***
+ ===============================
+ [..]
+ (#) Only for MDF instance, start short circuit detection using HAL_MDF_ScdStart()
+ or HAL_MDF_ScdStart_IT().
+ (#) In polling mode, use HAL_MDF_PollForScd() to detect short circuit.
+ (#) In interrupt mode, HAL_MDF_ErrorCallback() will be called if short circuit detection
+ occurs.
+ Use HAL_MDF_GetErrorCode() to get the corresponding error.
+ (#) Stop short circuit detection using HAL_MDF_ScdStop() or HAL_MDF_ScdStop_IT().
+
+ *** Out-off limit detection ***
+ ===============================
+ [..]
+ (#) Only for MDF instance, start out-off limit detection using HAL_MDF_OldStart()
+ or HAL_MDF_OldStart_IT().
+ (#) In polling mode, use HAL_MDF_PollForOld() to detect out-off limit and to get threshold
+ information.
+ (#) In interrupt mode, HAL_MDF_OldCallback() will be called if out-off limit detection occurs.
+ (#) Stop out-off limit detection using HAL_MDF_OldStop() or HAL_MDF_OldStop_IT().
+
+ *** generic functions ***
+ =========================
+ [..]
+ (#) HAL_MDF_IRQHandler will be called when MDF or ADF interrupt occurs.
+ (#) HAL_MDF_ErrorCallback will be called when MDF or ADF error occurs.
+ (#) Use HAL_MDF_GetState() to get the current MDF or ADF instance state.
+ (#) Use HAL_MDF_GetErrorCode() to get the current MDF or ADF instance error code.
+
+ *** Callback registration ***
+ =============================
+ [..]
+ The compilation define USE_HAL_MDF_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use functions HAL_MDF_RegisterCallback(), HAL_MDF_RegisterOldCallback()
+ or HAL_MDF_RegisterSndLvlCallback() to register a user callback.
+
+ [..]
+ Function HAL_MDF_RegisterCallback() allows to register following callbacks :
+ (+) AcqCpltCallback : Acquisition complete callback.
+ (+) AcqHalfCpltCallback : Acquisition half complete callback.
+ (+) SadCallback : Sound activity detection callback (only for ADF instance).
+ (+) ErrorCallback : Error callback.
+ (+) MspInitCallback : MSP init callback.
+ (+) MspDeInitCallback : MSP de-init callback.
+ [..]
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ [..]
+ For MDF instance and for specific out-off limit detection callback use dedicated
+ register callback :
+ HAL_MDF_RegisterOldCallback().
+
+ [..]
+ For ADF instance and for specific sound level callback use dedicated register callback :
+ HAL_MDF_RegisterSndLvlCallback().
+
+ [..]
+ Use function HAL_MDF_UnRegisterCallback() to reset a callback to the default weak function.
+
+ [..]
+ HAL_MDF_UnRegisterCallback() takes as parameters the HAL peripheral handle and the Callback ID.
+ [..]
+ This function allows to reset following callbacks :
+ (+) AcqCpltCallback : Acquisition complete callback.
+ (+) AcqHalfCpltCallback : Acquisition half complete callback.
+ (+) SadCallback : Sound activity detection callback (only for ADF instance).
+ (+) ErrorCallback : Error callback.
+ (+) MspInitCallback : MSP init callback.
+ (+) MspDeInitCallback : MSP de-init callback.
+
+ [..]
+ For MDF instance and for specific out-off limit detection callback use dedicated
+ unregister callback :
+ HAL_MDF_UnRegisterOldCallback().
+
+ [..]
+ For ADF instance and for specific sound level callback use dedicated unregister callback :
+ HAL_MDF_UnRegisterSndLvlCallback().
+
+ [..]
+ By default, after the call of init function and if the state is RESET
+ all callbacks are reset to the corresponding legacy weak functions :
+ examples HAL_MDF_AcqCpltCallback(), HAL_MDF_ErrorCallback().
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak functions in the init and de-init only when these
+ callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the init and de-init keep and use
+ the user MspInit/MspDeInit callbacks (registered beforehand).
+
+ [..]
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the init/de-init.
+ In that case first register the MspInit/MspDeInit user callbacks using
+ HAL_MDF_RegisterCallback() before calling init or de-init function.
+
+ [..]
+ When the compilation define USE_HAL_MDF_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak callbacks are used.
+
+ @endverbatim
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup MDF MDF
+ * @brief MDF HAL module driver
+ * @{
+ */
+
+#ifdef HAL_MDF_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/** @defgroup MDF_Private_Typedefs MDF Private Typedefs
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private define ------------------------------------------------------------*/
+/** @defgroup MDF_Private_Constants MDF Private Constants
+ * @{
+ */
+#define MDF_INSTANCE_NUMBER 7U /* 6 instances for MDF1 and 1 instance for ADF1 */
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup MDF_Private_Variables MDF Private Variables
+ * @{
+ */
+static uint32_t v_mdf1InstanceCounter = 0U;
+static uint32_t v_adf1InstanceCounter = 0U;
+static MDF_HandleTypeDef *a_mdfHandle[MDF_INSTANCE_NUMBER] = {NULL};
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup MDF_Private_Functions MDF Private Functions
+ * @{
+ */
+static uint32_t MDF_GetHandleNumberFromInstance(const MDF_Filter_TypeDef *const pInstance);
+static void MDF_AcqStart(MDF_HandleTypeDef *const hmdf, const MDF_FilterConfigTypeDef *const pFilterConfig);
+static void MDF_DmaXferCpltCallback(DMA_HandleTypeDef *hdma);
+static void MDF_DmaXferHalfCpltCallback(DMA_HandleTypeDef *hdma);
+static void MDF_DmaErrorCallback(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup MDF_Exported_Functions MDF Exported Functions
+ * @{
+ */
+
+/** @defgroup MDF_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and de-initialization functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to :
+ (+) Initialize the MDF or ADF instance.
+ (+) De-initialize the MDF or ADF instance.
+ (+) Register and unregister callbacks.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the MDF instance according to the specified parameters
+ * in the MDF_InitTypeDef structure and initialize the associated handle.
+ * @param hmdf MDF handle.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_MDF_Init(MDF_HandleTypeDef *hmdf)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check MDF handle */
+ if (hmdf == NULL)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check parameters */
+ assert_param(IS_MDF_ALL_INSTANCE(hmdf->Instance));
+ assert_param(IS_MDF_FILTER_BITSTREAM(hmdf->Init.FilterBistream));
+ assert_param(IS_FUNCTIONAL_STATE(hmdf->Init.SerialInterface.Activation));
+
+ /* Check that instance has not been already initialized */
+ if (a_mdfHandle[MDF_GetHandleNumberFromInstance(hmdf->Instance)] != NULL)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+ /* Reset callback pointers to the weak predefined callbacks */
+ if (IS_ADF_INSTANCE(hmdf->Instance))
+ {
+ hmdf->OldCallback = NULL;
+ hmdf->SndLvCallback = HAL_MDF_SndLvlCallback;
+ hmdf->SadCallback = HAL_MDF_SadCallback;
+ }
+ else /* MDF instance */
+ {
+ hmdf->OldCallback = HAL_MDF_OldCallback;
+ hmdf->SndLvCallback = NULL;
+ hmdf->SadCallback = NULL;
+ }
+ hmdf->AcqCpltCallback = HAL_MDF_AcqCpltCallback;
+ hmdf->AcqHalfCpltCallback = HAL_MDF_AcqHalfCpltCallback;
+ hmdf->ErrorCallback = HAL_MDF_ErrorCallback;
+
+ /* Call MDF MSP init function */
+ if (hmdf->MspInitCallback == NULL)
+ {
+ hmdf->MspInitCallback = HAL_MDF_MspInit;
+ }
+ hmdf->MspInitCallback(hmdf);
+#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
+ /* Call MDF MSP init function */
+ HAL_MDF_MspInit(hmdf);
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+
+ /* Configure common parameters only for first MDF or ADF instance */
+ if (((v_mdf1InstanceCounter == 0U) && IS_MDF_INSTANCE(hmdf->Instance)) ||
+ ((v_adf1InstanceCounter == 0U) && IS_ADF_INSTANCE(hmdf->Instance)))
+ {
+ MDF_TypeDef *mdfBase;
+ /* Get MDF base according instance */
+ mdfBase = (IS_ADF_INSTANCE(hmdf->Instance)) ? ADF1 : MDF1;
+
+ /* Check clock generator status */
+ if ((mdfBase->CKGCR & MDF_CKGCR_CCKACTIVE) != 0U)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Configure number of interleaved filters for MDF instance */
+ if (IS_MDF_INSTANCE(hmdf->Instance))
+ {
+ assert_param(IS_MDF_INTERLEAVED_FILTERS(hmdf->Init.CommonParam.InterleavedFilters));
+ mdfBase->GCR &= ~(MDF_GCR_ILVNB);
+ mdfBase->GCR |= (hmdf->Init.CommonParam.InterleavedFilters << MDF_GCR_ILVNB_Pos);
+ }
+
+ /* Configure processing clock divider, output clock divider,
+ output clock pins and output clock generation trigger */
+ assert_param(IS_MDF_PROC_CLOCK_DIVIDER(hmdf->Init.CommonParam.ProcClockDivider));
+ assert_param(IS_FUNCTIONAL_STATE(hmdf->Init.CommonParam.OutputClock.Activation));
+ mdfBase->CKGCR = 0U;
+ mdfBase->CKGCR |= ((hmdf->Init.CommonParam.ProcClockDivider - 1U) << MDF_CKGCR_PROCDIV_Pos);
+ if (hmdf->Init.CommonParam.OutputClock.Activation == ENABLE)
+ {
+ assert_param(IS_MDF_OUTPUT_CLOCK_PINS(hmdf->Init.CommonParam.OutputClock.Pins));
+ assert_param(IS_MDF_OUTPUT_CLOCK_DIVIDER(hmdf->Init.CommonParam.OutputClock.Divider));
+ assert_param(IS_FUNCTIONAL_STATE(hmdf->Init.CommonParam.OutputClock.Trigger.Activation));
+ mdfBase->CKGCR |= (((hmdf->Init.CommonParam.OutputClock.Divider - 1U) << MDF_CKGCR_CCKDIV_Pos) |
+ hmdf->Init.CommonParam.OutputClock.Pins |
+ (hmdf->Init.CommonParam.OutputClock.Pins >> 4U));
+ if (hmdf->Init.CommonParam.OutputClock.Trigger.Activation == ENABLE)
+ {
+ if (IS_MDF_INSTANCE(hmdf->Instance))
+ {
+ assert_param(IS_MDF_OUTPUT_CLOCK_TRIGGER_SOURCE(hmdf->Init.CommonParam.OutputClock.Trigger.Source));
+ }
+ else /* ADF instance */
+ {
+ assert_param(IS_ADF_OUTPUT_CLOCK_TRIGGER_SOURCE(hmdf->Init.CommonParam.OutputClock.Trigger.Source));
+ }
+ assert_param(IS_MDF_OUTPUT_CLOCK_TRIGGER_EDGE(hmdf->Init.CommonParam.OutputClock.Trigger.Edge));
+ mdfBase->CKGCR |= (hmdf->Init.CommonParam.OutputClock.Trigger.Source |
+ hmdf->Init.CommonParam.OutputClock.Trigger.Edge |
+ MDF_CKGCR_CKGMOD);
+ }
+ }
+
+ /* Activate clock generator */
+ mdfBase->CKGCR |= MDF_CKGCR_CKDEN;
+ }
+ }
+
+ /* Configure serial interface */
+ if ((status == HAL_OK) && (hmdf->Init.SerialInterface.Activation == ENABLE))
+ {
+ /* Check serial interface status */
+ if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFACTIVE) != 0U)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Configure mode, clock source and threshold */
+ assert_param(IS_MDF_SITF_MODE(hmdf->Init.SerialInterface.Mode));
+ assert_param(IS_MDF_SITF_CLOCK_SOURCE(hmdf->Init.SerialInterface.ClockSource));
+ assert_param(IS_MDF_SITF_THRESHOLD(hmdf->Init.SerialInterface.Threshold));
+ hmdf->Instance->SITFCR = 0U;
+ hmdf->Instance->SITFCR |= ((hmdf->Init.SerialInterface.Threshold << MDF_SITFCR_STH_Pos) |
+ hmdf->Init.SerialInterface.Mode | hmdf->Init.SerialInterface.ClockSource);
+
+ /* Activate serial interface */
+ hmdf->Instance->SITFCR |= MDF_SITFCR_SITFEN;
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Configure filter bitstream */
+ hmdf->Instance->BSMXCR &= ~(MDF_BSMXCR_BSSEL);
+ hmdf->Instance->BSMXCR |= hmdf->Init.FilterBistream;
+
+ /* Update instance counter and table */
+ if (IS_ADF_INSTANCE(hmdf->Instance))
+ {
+ v_adf1InstanceCounter++;
+ }
+ else /* MDF instance */
+ {
+ v_mdf1InstanceCounter++;
+ }
+ a_mdfHandle[MDF_GetHandleNumberFromInstance(hmdf->Instance)] = hmdf;
+
+ /* Update error code and state */
+ hmdf->ErrorCode = MDF_ERROR_NONE;
+ hmdf->State = HAL_MDF_STATE_READY;
+ }
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief De-initialize the MDF instance.
+ * @param hmdf MDF handle.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_MDF_DeInit(MDF_HandleTypeDef *hmdf)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check MDF handle */
+ if (hmdf == NULL)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check parameters */
+ assert_param(IS_MDF_ALL_INSTANCE(hmdf->Instance));
+
+ /* Check that instance has not been already deinitialized */
+ if (a_mdfHandle[MDF_GetHandleNumberFromInstance(hmdf->Instance)] == NULL)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ if (IS_MDF_INSTANCE(hmdf->Instance))
+ {
+ /* Disable short circuit detector if needed */
+ if ((hmdf->Instance->SCDCR & MDF_SCDCR_SCDACTIVE) != 0U)
+ {
+ hmdf->Instance->SCDCR &= ~(MDF_SCDCR_SCDEN);
+ }
+
+ /* Disable out-off limit detector if needed */
+ if ((hmdf->Instance->OLDCR & MDF_OLDCR_OLDACTIVE) != 0U)
+ {
+ hmdf->Instance->OLDCR &= ~(MDF_OLDCR_OLDEN);
+ }
+ }
+
+ /* Disable sound activity detector if needed */
+ if (IS_ADF_INSTANCE(hmdf->Instance))
+ {
+ if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) != 0U)
+ {
+ hmdf->Instance->SADCR &= ~(MDF_SADCR_SADEN);
+ }
+ }
+
+ /* Disable filter if needed */
+ if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) != 0U)
+ {
+ hmdf->Instance->DFLTCR &= ~(MDF_DFLTCR_DFLTEN);
+ }
+
+ /* Disable serial interface if needed */
+ if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFACTIVE) != 0U)
+ {
+ hmdf->Instance->SITFCR &= ~(MDF_SITFCR_SITFEN);
+ }
+
+ /* Disable all interrupts and clear all pending flags */
+ hmdf->Instance->DFLTIER = 0U;
+ hmdf->Instance->DFLTISR = 0xFFFFFFFFU;
+
+ /* Disable clock generator only for last MDF or ADF instance deinitialization */
+ if (((v_mdf1InstanceCounter == 1U) && IS_MDF_INSTANCE(hmdf->Instance)) ||
+ ((v_adf1InstanceCounter == 1U) && IS_ADF_INSTANCE(hmdf->Instance)))
+ {
+ MDF_TypeDef *p_mdf_base;
+ /* Get MDF base according instance */
+ p_mdf_base = (IS_ADF_INSTANCE(hmdf->Instance)) ? ADF1 : MDF1;
+
+ /* Disable clock generator */
+ p_mdf_base->CKGCR &= ~(MDF_CKGCR_CKDEN);
+ }
+
+ /* Call MDF MSP deinit function */
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+ if (hmdf->MspDeInitCallback == NULL)
+ {
+ hmdf->MspDeInitCallback = HAL_MDF_MspDeInit;
+ }
+ hmdf->MspDeInitCallback(hmdf);
+#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
+ HAL_MDF_MspDeInit(hmdf);
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+
+ /* Update instance counter and table */
+ if (IS_ADF_INSTANCE(hmdf->Instance))
+ {
+ v_adf1InstanceCounter--;
+ }
+ else /* MDF instance */
+ {
+ v_mdf1InstanceCounter--;
+ }
+ a_mdfHandle[MDF_GetHandleNumberFromInstance(hmdf->Instance)] = (MDF_HandleTypeDef *) NULL;
+
+ /* Update state */
+ hmdf->State = HAL_MDF_STATE_RESET;
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Initialize the MDF instance MSP.
+ * @param hmdf MDF handle.
+ * @retval None.
+ */
+__weak void HAL_MDF_MspInit(MDF_HandleTypeDef *hmdf)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hmdf);
+
+ /* NOTE : This function should not be modified, when the function is needed,
+ the HAL_MDF_MspInit could be implemented in the user file */
+}
+
+/**
+ * @brief De-initialize the MDF instance MSP.
+ * @param hmdf MDF handle.
+ * @retval None.
+ */
+__weak void HAL_MDF_MspDeInit(MDF_HandleTypeDef *hmdf)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hmdf);
+
+ /* NOTE : This function should not be modified, when the function is needed,
+ the HAL_MDF_MspDeInit could be implemented in the user file */
+}
+
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a user MDF callback to be used instead of the weak predefined callback.
+ * @param hmdf MDF handle.
+ * @param CallbackID ID of the callback to be registered.
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_MDF_ACQ_COMPLETE_CB_ID acquisition complete callback ID.
+ * @arg @ref HAL_MDF_ACQ_HALFCOMPLETE_CB_ID acquisition half complete callback ID.
+ * @arg @ref HAL_MDF_SAD_CB_ID sound activity detector callback ID (only for ADF instance).
+ * @arg @ref HAL_MDF_ERROR_CB_ID error callback ID.
+ * @arg @ref HAL_MDF_MSPINIT_CB_ID MSP init callback ID.
+ * @arg @ref HAL_MDF_MSPDEINIT_CB_ID MSP de-init callback ID.
+ * @param pCallback pointer to the callback function.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_MDF_RegisterCallback(MDF_HandleTypeDef *hmdf,
+ HAL_MDF_CallbackIDTypeDef CallbackID,
+ pMDF_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ if (pCallback == NULL)
+ {
+ /* Update error code and status */
+ hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK;
+ status = HAL_ERROR;
+ }
+ else
+ {
+ if (hmdf->State == HAL_MDF_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_MDF_ACQ_COMPLETE_CB_ID :
+ hmdf->AcqCpltCallback = pCallback;
+ break;
+ case HAL_MDF_ACQ_HALFCOMPLETE_CB_ID :
+ hmdf->AcqHalfCpltCallback = pCallback;
+ break;
+ case HAL_MDF_SAD_CB_ID :
+ hmdf->SadCallback = pCallback;
+ break;
+ case HAL_MDF_ERROR_CB_ID :
+ hmdf->ErrorCallback = pCallback;
+ break;
+ case HAL_MDF_MSPINIT_CB_ID :
+ hmdf->MspInitCallback = pCallback;
+ break;
+ case HAL_MDF_MSPDEINIT_CB_ID :
+ hmdf->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* Update error code and status */
+ hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK;
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hmdf->State == HAL_MDF_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_MDF_MSPINIT_CB_ID :
+ hmdf->MspInitCallback = pCallback;
+ break;
+ case HAL_MDF_MSPDEINIT_CB_ID :
+ hmdf->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* Update error code and status */
+ hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK;
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update error code and status */
+ hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK;
+ status = HAL_ERROR;
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Unregister a user MDF callback.
+ * MDF callback is redirected to the weak predefined callback.
+ * @param hmdf MDF handle.
+ * @param CallbackID ID of the callback to be unregistered.
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_MDF_ACQ_COMPLETE_CB_ID acquisition complete callback ID.
+ * @arg @ref HAL_MDF_ACQ_HALFCOMPLETE_CB_ID acquisition half complete callback ID.
+ * @arg @ref HAL_MDF_SAD_CB_ID sound activity detector callback ID (only for ADF instance).
+ * @arg @ref HAL_MDF_ERROR_CB_ID error callback ID.
+ * @arg @ref HAL_MDF_MSPINIT_CB_ID MSP init callback ID.
+ * @arg @ref HAL_MDF_MSPDEINIT_CB_ID MSP de-init callback ID.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_MDF_UnRegisterCallback(MDF_HandleTypeDef *hmdf,
+ HAL_MDF_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (hmdf->State == HAL_MDF_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_MDF_ACQ_COMPLETE_CB_ID :
+ hmdf->AcqCpltCallback = HAL_MDF_AcqCpltCallback;
+ break;
+ case HAL_MDF_ACQ_HALFCOMPLETE_CB_ID :
+ hmdf->AcqHalfCpltCallback = HAL_MDF_AcqHalfCpltCallback;
+ break;
+ case HAL_MDF_SAD_CB_ID :
+ hmdf->SadCallback = HAL_MDF_SadCallback;
+ break;
+ case HAL_MDF_ERROR_CB_ID :
+ hmdf->ErrorCallback = HAL_MDF_ErrorCallback;
+ break;
+ case HAL_MDF_MSPINIT_CB_ID :
+ hmdf->MspInitCallback = HAL_MDF_MspInit;
+ break;
+ case HAL_MDF_MSPDEINIT_CB_ID :
+ hmdf->MspDeInitCallback = HAL_MDF_MspDeInit;
+ break;
+ default :
+ /* Update error code and status */
+ hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK;
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hmdf->State == HAL_MDF_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_MDF_MSPINIT_CB_ID :
+ hmdf->MspInitCallback = HAL_MDF_MspInit;
+ break;
+ case HAL_MDF_MSPDEINIT_CB_ID :
+ hmdf->MspDeInitCallback = HAL_MDF_MspDeInit;
+ break;
+ default :
+ /* Update error code and status */
+ hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK;
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update error code and status */
+ hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK;
+ status = HAL_ERROR;
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Register specific MDF out-off limit detector callback
+ * to be used instead of the weak predefined callback.
+ * @param hmdf MDF handle.
+ * @param pCallback pointer to the out-off limit detector callback function.
+ * @retval HAL status.
+ * @note This function must not be used with ADF instance.
+ */
+HAL_StatusTypeDef HAL_MDF_RegisterOldCallback(MDF_HandleTypeDef *hmdf,
+ pMDF_OldCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ if (pCallback == NULL)
+ {
+ /* Update error code and status */
+ hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK;
+ status = HAL_ERROR;
+ }
+ else
+ {
+ if (hmdf->State == HAL_MDF_STATE_READY)
+ {
+ hmdf->OldCallback = pCallback;
+ }
+ else
+ {
+ /* Update error code and status */
+ hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK;
+ status = HAL_ERROR;
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Unregister the specific MDF out-off limit detector callback.
+ * MDF out-off limit detector callback is redirected to the weak predefined callback.
+ * @param hmdf MDF handle.
+ * @retval HAL status.
+ * @note This function must not be used with ADF instance.
+ */
+HAL_StatusTypeDef HAL_MDF_UnRegisterOldCallback(MDF_HandleTypeDef *hmdf)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (hmdf->State == HAL_MDF_STATE_READY)
+ {
+ hmdf->OldCallback = HAL_MDF_OldCallback;
+ }
+ else
+ {
+ /* Update error code and status */
+ hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK;
+ status = HAL_ERROR;
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Register specific MDF sound level callback
+ * to be used instead of the weak predefined callback.
+ * @param hmdf MDF handle.
+ * @param pCallback pointer to the sound level callback function.
+ * @retval HAL status.
+ * @note This function must not be used with MDF instance.
+ */
+HAL_StatusTypeDef HAL_MDF_RegisterSndLvlCallback(MDF_HandleTypeDef *hmdf,
+ pMDF_SndLvlCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ if (pCallback == NULL)
+ {
+ /* Update error code and status */
+ hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK;
+ status = HAL_ERROR;
+ }
+ else
+ {
+ if (hmdf->State == HAL_MDF_STATE_READY)
+ {
+ hmdf->SndLvCallback = pCallback;
+ }
+ else
+ {
+ /* Update error code and status */
+ hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK;
+ status = HAL_ERROR;
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Unregister the specific MDF sound level callback.
+ * MDF sound level callback is redirected to the weak predefined callback.
+ * @param hmdf MDF handle.
+ * @retval HAL status.
+ * @note This function must not be used with MDF instance.
+ */
+HAL_StatusTypeDef HAL_MDF_UnRegisterSndLvlCallback(MDF_HandleTypeDef *hmdf)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (hmdf->State == HAL_MDF_STATE_READY)
+ {
+ hmdf->SndLvCallback = HAL_MDF_SndLvlCallback;
+ }
+ else
+ {
+ /* Update error code and status */
+ hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK;
+ status = HAL_ERROR;
+ }
+
+ /* Return function status */
+ return status;
+}
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup MDF_Exported_Functions_Group2 Acquisition functions
+ * @brief Acquisition functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Acquisition functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to :
+ (+) Start and stop acquisition in polling, interrupt or DMA mode.
+ (+) Wait and get acquisition values.
+ (+) Generate pulse on TRGO signal.
+ (+) Modify and get some filter parameters during acquisition.
+ (+) Wait and get sound level values for ADF instance.
+ (+) Detect sound activity for ADF instance.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function allows to start acquisition in polling mode.
+ * @param hmdf MDF handle.
+ * @param pFilterConfig Filter configuration parameters.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_MDF_AcqStart(MDF_HandleTypeDef *hmdf, MDF_FilterConfigTypeDef *pFilterConfig)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ if (pFilterConfig == NULL)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ if (IS_ADF_INSTANCE(hmdf->Instance))
+ {
+ assert_param(IS_ADF_ACQUISITION_MODE(pFilterConfig->AcquisitionMode));
+ assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->SoundActivity.Activation));
+ }
+ else
+ {
+ assert_param(IS_MDF_ACQUISITION_MODE(pFilterConfig->AcquisitionMode));
+ }
+ if ((IS_ADF_INSTANCE(hmdf->Instance)) && (pFilterConfig->SoundActivity.Activation == ENABLE) &&
+ ((pFilterConfig->AcquisitionMode == MDF_MODE_ASYNC_SINGLE) ||
+ (pFilterConfig->AcquisitionMode == MDF_MODE_SYNC_SINGLE) ||
+ (pFilterConfig->AcquisitionMode == MDF_MODE_WINDOW_CONT)))
+ {
+ status = HAL_ERROR;
+ }
+ /* Check state */
+ else if (hmdf->State != HAL_MDF_STATE_READY)
+ {
+ status = HAL_ERROR;
+ }
+ /* Check filter status */
+ else if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) != 0U)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* For ADF instance, check SAD status */
+ if (IS_ADF_INSTANCE(hmdf->Instance))
+ {
+ if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) != 0U)
+ {
+ status = HAL_ERROR;
+ }
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ /* For MDF instance, check OLD status and main filter order */
+ assert_param(IS_MDF_CIC_MODE(pFilterConfig->CicMode));
+ if (IS_MDF_INSTANCE(hmdf->Instance))
+ {
+ if (((hmdf->Instance->OLDCR & MDF_OLDCR_OLDACTIVE) != 0U) && (pFilterConfig->CicMode >= MDF_ONE_FILTER_SINC4))
+ {
+ status = HAL_ERROR;
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Configure filter and start acquisition */
+ hmdf->Instance->DFLTCR = 0U;
+ MDF_AcqStart(hmdf, pFilterConfig);
+ }
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to poll for available acquisition value.
+ * @param hmdf MDF handle.
+ * @param Timeout Timeout value in milliseconds.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_MDF_PollForAcq(MDF_HandleTypeDef *hmdf, uint32_t Timeout)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check state */
+ if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Wait for available acquisition value */
+ while (((hmdf->Instance->DFLTISR & MDF_DFLTISR_RXNEF) != MDF_DFLTISR_RXNEF) && (status == HAL_OK))
+ {
+ /* Check the timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ status = HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Check if data overflow, saturation or reshape filter occurs */
+ uint32_t error_flags = (hmdf->Instance->DFLTISR & (MDF_DFLTISR_DOVRF | MDF_DFLTISR_SATF | MDF_DFLTISR_RFOVRF));
+ if (error_flags != 0U)
+ {
+ /* Update error code */
+ if ((error_flags & MDF_DFLTISR_DOVRF) == MDF_DFLTISR_DOVRF)
+ {
+ hmdf->ErrorCode |= MDF_ERROR_ACQUISITION_OVERFLOW;
+ }
+ if ((error_flags & MDF_DFLTISR_SATF) == MDF_DFLTISR_SATF)
+ {
+ hmdf->ErrorCode |= MDF_ERROR_SATURATION;
+ }
+ if ((error_flags & MDF_DFLTISR_RFOVRF) == MDF_DFLTISR_RFOVRF)
+ {
+ hmdf->ErrorCode |= MDF_ERROR_RSF_OVERRUN;
+ }
+
+ /* Clear corresponding flags */
+ hmdf->Instance->DFLTISR |= error_flags;
+
+ /* Call error callback */
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+ hmdf->ErrorCallback(hmdf);
+#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
+ HAL_MDF_ErrorCallback(hmdf);
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Update state only in asynchronous single shot mode */
+ if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_ACQMOD) == MDF_MODE_ASYNC_SINGLE)
+ {
+ hmdf->State = HAL_MDF_STATE_READY;
+ }
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to poll for available snapshot acquisition value.
+ * @param hmdf MDF handle.
+ * @param Timeout Timeout value in milliseconds.
+ * @retval HAL status.
+ * @note This function must not be used with ADF instance.
+ */
+HAL_StatusTypeDef HAL_MDF_PollForSnapshotAcq(MDF_HandleTypeDef *hmdf, uint32_t Timeout)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check state */
+ if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Wait for available snapshot acquisition value */
+ while (((hmdf->Instance->DFLTISR & MDF_DFLTISR_SSDRF) != MDF_DFLTISR_SSDRF) && (status == HAL_OK))
+ {
+ /* Check the timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ status = HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Check if snapshot overrun, saturation or reshape filter occurs */
+ uint32_t error_flags = (hmdf->Instance->DFLTISR & (MDF_DFLTISR_SSOVRF | MDF_DFLTISR_SATF | MDF_DFLTISR_RFOVRF));
+ if (error_flags != 0U)
+ {
+ /* Update error code */
+ if ((error_flags & MDF_DFLTISR_SSOVRF) == MDF_DFLTISR_SSOVRF)
+ {
+ hmdf->ErrorCode |= MDF_ERROR_ACQUISITION_OVERFLOW;
+ }
+ if ((error_flags & MDF_DFLTISR_SATF) == MDF_DFLTISR_SATF)
+ {
+ hmdf->ErrorCode |= MDF_ERROR_SATURATION;
+ }
+ if ((error_flags & MDF_DFLTISR_RFOVRF) == MDF_DFLTISR_RFOVRF)
+ {
+ hmdf->ErrorCode |= MDF_ERROR_RSF_OVERRUN;
+ }
+
+ /* Clear corresponding flags */
+ hmdf->Instance->DFLTISR |= error_flags;
+
+ /* Call error callback */
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+ hmdf->ErrorCallback(hmdf);
+#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
+ HAL_MDF_ErrorCallback(hmdf);
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to get acquisition value.
+ * @param hmdf MDF handle.
+ * @param pValue Acquisition value on 24 MSB.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_MDF_GetAcqValue(MDF_HandleTypeDef *hmdf, int32_t *pValue)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ if (pValue == NULL)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check state */
+ if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+ {
+ if (hmdf->State != HAL_MDF_STATE_READY)
+ {
+ status = HAL_ERROR;
+ }
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Get acquisition value */
+ *pValue = (int32_t) hmdf->Instance->DFLTDR;
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to get snapshot acquisition value.
+ * @param hmdf MDF handle.
+ * @param pSnapshotParam Snapshot parameters.
+ * @retval HAL status.
+ * @note This function must not be used with ADF instance.
+ */
+HAL_StatusTypeDef HAL_MDF_GetSnapshotAcqValue(MDF_HandleTypeDef *hmdf, MDF_SnapshotParamTypeDef *pSnapshotParam)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ if (pSnapshotParam == NULL)
+ {
+ status = HAL_ERROR;
+ }
+ /* Check state */
+ else if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ uint32_t snpsdr_value;
+
+ /* Read value of snapshot data register */
+ snpsdr_value = hmdf->Instance->SNPSDR;
+
+ /* Clear snapshot data ready flag */
+ hmdf->Instance->DFLTISR |= MDF_DFLTISR_SSDRF;
+
+ /* Store value of decimation counter in snapshot parameter structure */
+ pSnapshotParam->DecimationCounter = (snpsdr_value & MDF_SNPSDR_MCICDC);
+
+ /* Check snapshot format */
+ if ((hmdf->Instance->DFLTCR & MDF_SNAPSHOT_16BITS) == MDF_SNAPSHOT_16BITS)
+ {
+ /* Store value of integrator counter in snapshot parameter structure */
+ pSnapshotParam->IntegratorCounter = ((snpsdr_value & MDF_SNPSDR_EXTSDR) >> MDF_SNPSDR_EXTSDR_Pos);
+
+ /* Store snapshot acquisition value (16MSB) in snapshot parameter structure */
+ snpsdr_value &= 0xFFFF0000U;
+ pSnapshotParam->Value = (int32_t) snpsdr_value;
+ }
+ else
+ {
+ /* Store snapshot acquisition value (23MSB) in snapshot parameter structure */
+ snpsdr_value &= 0xFFFFFE00U;
+ pSnapshotParam->Value = (int32_t) snpsdr_value;
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to stop acquisition in polling mode.
+ * @param hmdf MDF handle.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_MDF_AcqStop(MDF_HandleTypeDef *hmdf)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check state */
+ if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+ {
+ /* Check if state is ready and filter active */
+ if (hmdf->State == HAL_MDF_STATE_READY)
+ {
+ if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) != MDF_DFLTCR_DFLTACTIVE)
+ {
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Disable sound activity detector if needed for ADF instance */
+ if (IS_ADF_INSTANCE(hmdf->Instance))
+ {
+ if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) != 0U)
+ {
+ hmdf->Instance->SADCR &= ~(MDF_SADCR_SADEN);
+ }
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Disable filter */
+ hmdf->Instance->DFLTCR &= ~(MDF_DFLTCR_DFLTEN);
+
+ /* Clear all potential pending flags */
+ if (IS_ADF_INSTANCE(hmdf->Instance))
+ {
+ hmdf->Instance->DFLTISR |= (MDF_DFLTISR_DOVRF | MDF_DFLTISR_SATF | MDF_DFLTISR_RFOVRF |
+ MDF_DFLTISR_SDDETF | MDF_DFLTISR_SDLVLF);
+ }
+ else
+ {
+ hmdf->Instance->DFLTISR |= (MDF_DFLTISR_DOVRF | MDF_DFLTISR_SSDRF | MDF_DFLTISR_SSOVRF |
+ MDF_DFLTISR_SATF | MDF_DFLTISR_RFOVRF);
+ }
+
+ /* Update state */
+ hmdf->State = HAL_MDF_STATE_READY;
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to start acquisition in interrupt mode.
+ * @param hmdf MDF handle.
+ * @param pFilterConfig Filter configuration parameters.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_MDF_AcqStart_IT(MDF_HandleTypeDef *hmdf, MDF_FilterConfigTypeDef *pFilterConfig)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ if (pFilterConfig == NULL)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ if (IS_ADF_INSTANCE(hmdf->Instance))
+ {
+ assert_param(IS_ADF_ACQUISITION_MODE(pFilterConfig->AcquisitionMode));
+ assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->SoundActivity.Activation));
+ }
+ else
+ {
+ assert_param(IS_MDF_ACQUISITION_MODE(pFilterConfig->AcquisitionMode));
+ }
+ if ((IS_ADF_INSTANCE(hmdf->Instance)) && (pFilterConfig->SoundActivity.Activation == ENABLE) &&
+ ((pFilterConfig->AcquisitionMode == MDF_MODE_ASYNC_SINGLE) ||
+ (pFilterConfig->AcquisitionMode == MDF_MODE_SYNC_SINGLE) ||
+ (pFilterConfig->AcquisitionMode == MDF_MODE_WINDOW_CONT)))
+ {
+ status = HAL_ERROR;
+ }
+ /* Check state */
+ else if (hmdf->State != HAL_MDF_STATE_READY)
+ {
+ status = HAL_ERROR;
+ }
+ /* Check filter status */
+ else if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) != 0U)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* For ADF instance, check SAD status */
+ if (IS_ADF_INSTANCE(hmdf->Instance))
+ {
+ if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) != 0U)
+ {
+ status = HAL_ERROR;
+ }
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ /* For MDF instance, check OLD status and main filter order */
+ assert_param(IS_MDF_CIC_MODE(pFilterConfig->CicMode));
+ if (IS_MDF_INSTANCE(hmdf->Instance))
+ {
+ if (((hmdf->Instance->OLDCR & MDF_OLDCR_OLDACTIVE) != 0U) && (pFilterConfig->CicMode >= MDF_ONE_FILTER_SINC4))
+ {
+ status = HAL_ERROR;
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ if (pFilterConfig->AcquisitionMode == MDF_MODE_SYNC_SNAPSHOT)
+ {
+ /* Enable snapshot overrun and data ready interrupts */
+ hmdf->Instance->DFLTIER |= (MDF_DFLTIER_SSOVRIE | MDF_DFLTIER_SSDRIE);
+ }
+ else
+ {
+ if ((IS_MDF_INSTANCE(hmdf->Instance)) || (pFilterConfig->SoundActivity.Activation == DISABLE) ||
+ (pFilterConfig->SoundActivity.DataMemoryTransfer != MDF_SAD_NO_MEMORY_TRANSFER))
+ {
+ /* Enable data overflow and fifo threshold interrupts */
+ hmdf->Instance->DFLTIER |= (MDF_DFLTIER_DOVRIE | MDF_DFLTIER_FTHIE);
+ }
+ }
+
+ if (pFilterConfig->ReshapeFilter.Activation == ENABLE)
+ {
+ /* Enable reshape filter overrun interrupt */
+ hmdf->Instance->DFLTIER |= MDF_DFLTIER_RFOVRIE;
+ }
+
+ /* Enable saturation interrupt */
+ hmdf->Instance->DFLTIER |= MDF_DFLTIER_SATIE;
+
+ if ((IS_ADF_INSTANCE(hmdf->Instance)) && (pFilterConfig->SoundActivity.Activation == ENABLE))
+ {
+ /* Enable sound level value ready and sound activity detection interrupts */
+ assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->SoundActivity.SoundLevelInterrupt));
+ hmdf->Instance->DFLTIER |= (pFilterConfig->SoundActivity.SoundLevelInterrupt == ENABLE) ?
+ (MDF_DFLTIER_SDLVLIE | MDF_DFLTIER_SDDETIE) :
+ MDF_DFLTIER_SDDETIE;
+ }
+
+ /* Configure filter and start acquisition */
+ hmdf->Instance->DFLTCR = 0U;
+ MDF_AcqStart(hmdf, pFilterConfig);
+ }
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to stop acquisition in interrupt mode.
+ * @param hmdf MDF handle.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_MDF_AcqStop_IT(MDF_HandleTypeDef *hmdf)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check state */
+ if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+ {
+ /* Check if state is ready and filter active */
+ if (hmdf->State == HAL_MDF_STATE_READY)
+ {
+ if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) != MDF_DFLTCR_DFLTACTIVE)
+ {
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Disable sound activity detector if needed for ADF instance */
+ if (IS_ADF_INSTANCE(hmdf->Instance))
+ {
+ if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) != 0U)
+ {
+ hmdf->Instance->SADCR &= ~(MDF_SADCR_SADEN);
+ }
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Disable filter */
+ hmdf->Instance->DFLTCR &= ~(MDF_DFLTCR_DFLTEN);
+
+ /* Disable interrupts and clear all potential pending flags */
+ if (IS_ADF_INSTANCE(hmdf->Instance))
+ {
+ hmdf->Instance->DFLTIER &= ~(MDF_DFLTIER_FTHIE | MDF_DFLTIER_DOVRIE | MDF_DFLTIER_SATIE |
+ MDF_DFLTIER_RFOVRIE | MDF_DFLTIER_SDDETIE | MDF_DFLTIER_SDLVLIE);
+ hmdf->Instance->DFLTISR |= (MDF_DFLTISR_DOVRF | MDF_DFLTISR_SATF | MDF_DFLTISR_RFOVRF |
+ MDF_DFLTISR_SDDETF | MDF_DFLTISR_SDLVLF);
+ }
+ else
+ {
+ hmdf->Instance->DFLTIER &= ~(MDF_DFLTIER_FTHIE | MDF_DFLTIER_DOVRIE | MDF_DFLTIER_SSDRIE |
+ MDF_DFLTIER_SSOVRIE | MDF_DFLTIER_SATIE | MDF_DFLTIER_RFOVRIE);
+ hmdf->Instance->DFLTISR |= (MDF_DFLTISR_DOVRF | MDF_DFLTISR_SSDRF | MDF_DFLTISR_SSOVRF |
+ MDF_DFLTISR_SATF | MDF_DFLTISR_RFOVRF);
+ }
+
+ /* Update state */
+ hmdf->State = HAL_MDF_STATE_READY;
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to start acquisition in DMA mode.
+ * @param hmdf MDF handle.
+ * @param pFilterConfig Filter configuration parameters.
+ * @param pDmaConfig DMA configuration parameters.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_MDF_AcqStart_DMA(MDF_HandleTypeDef *hmdf, MDF_FilterConfigTypeDef *pFilterConfig,
+ MDF_DmaConfigTypeDef *pDmaConfig)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ if ((pFilterConfig == NULL) || (pDmaConfig == NULL))
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ assert_param(IS_FUNCTIONAL_STATE(pDmaConfig->MsbOnly));
+ if (IS_ADF_INSTANCE(hmdf->Instance))
+ {
+ assert_param(IS_ADF_ACQUISITION_MODE(pFilterConfig->AcquisitionMode));
+ assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->SoundActivity.Activation));
+ }
+ else
+ {
+ assert_param(IS_MDF_ACQUISITION_MODE(pFilterConfig->AcquisitionMode));
+ }
+ if ((IS_ADF_INSTANCE(hmdf->Instance)) && (pFilterConfig->SoundActivity.Activation == ENABLE) &&
+ ((pFilterConfig->AcquisitionMode == MDF_MODE_ASYNC_SINGLE) ||
+ (pFilterConfig->AcquisitionMode == MDF_MODE_SYNC_SINGLE) ||
+ (pFilterConfig->AcquisitionMode == MDF_MODE_WINDOW_CONT)))
+ {
+ status = HAL_ERROR;
+ }
+ else if (pFilterConfig->AcquisitionMode == MDF_MODE_SYNC_SNAPSHOT)
+ {
+ status = HAL_ERROR;
+ }
+ /* Check state */
+ else if (hmdf->State != HAL_MDF_STATE_READY)
+ {
+ status = HAL_ERROR;
+ }
+ /* Check filter status */
+ else if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) != 0U)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* For ADF instance, check SAD status */
+ if (IS_ADF_INSTANCE(hmdf->Instance))
+ {
+ if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) != 0U)
+ {
+ status = HAL_ERROR;
+ }
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ /* For MDF instance, check OLD status and main filter order */
+ assert_param(IS_MDF_CIC_MODE(pFilterConfig->CicMode));
+ if (IS_MDF_INSTANCE(hmdf->Instance))
+ {
+ if (((hmdf->Instance->OLDCR & MDF_OLDCR_OLDACTIVE) != 0U) && (pFilterConfig->CicMode >= MDF_ONE_FILTER_SINC4))
+ {
+ status = HAL_ERROR;
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ uint32_t SrcAddress;
+
+ if (pFilterConfig->ReshapeFilter.Activation == ENABLE)
+ {
+ /* Enable reshape filter overrun interrupt */
+ hmdf->Instance->DFLTIER |= MDF_DFLTIER_RFOVRIE;
+ }
+
+ /* Enable saturation interrupt */
+ hmdf->Instance->DFLTIER |= MDF_DFLTIER_SATIE;
+
+ if ((IS_ADF_INSTANCE(hmdf->Instance)) && (pFilterConfig->SoundActivity.Activation == ENABLE))
+ {
+ /* Enable sound level value ready and sound activity detection interrupts */
+ assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->SoundActivity.SoundLevelInterrupt));
+ hmdf->Instance->DFLTIER |= (pFilterConfig->SoundActivity.SoundLevelInterrupt == ENABLE) ?
+ (MDF_DFLTIER_SDLVLIE | MDF_DFLTIER_SDDETIE) :
+ MDF_DFLTIER_SDDETIE;
+ }
+
+ /* Enable MDF DMA requests */
+ hmdf->Instance->DFLTCR = MDF_DFLTCR_DMAEN;
+
+ /* Start DMA transfer */
+ hmdf->hdma->XferCpltCallback = MDF_DmaXferCpltCallback;
+ hmdf->hdma->XferHalfCpltCallback = MDF_DmaXferHalfCpltCallback;
+ hmdf->hdma->XferErrorCallback = MDF_DmaErrorCallback;
+ SrcAddress = (pDmaConfig->MsbOnly == ENABLE) ? (((uint32_t) &hmdf->Instance->DFLTDR) + 2U) :
+ (uint32_t) &hmdf->Instance->DFLTDR;
+ if ((hmdf->hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if (hmdf->hdma->LinkedListQueue != NULL)
+ {
+ hmdf->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = pDmaConfig->DataLength;
+ hmdf->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = SrcAddress;
+ hmdf->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = pDmaConfig->Address;
+
+ status = HAL_DMAEx_List_Start_IT(hmdf->hdma);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_DMA_Start_IT(hmdf->hdma, SrcAddress, pDmaConfig->Address, pDmaConfig->DataLength);
+ }
+ if (status != HAL_OK)
+ {
+ /* Update state */
+ hmdf->State = HAL_MDF_STATE_ERROR;
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Configure filter and start acquisition */
+ MDF_AcqStart(hmdf, pFilterConfig);
+ }
+ }
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to stop acquisition in DMA mode.
+ * @param hmdf MDF handle.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_MDF_AcqStop_DMA(MDF_HandleTypeDef *hmdf)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check if state is ready and filter active */
+ if (hmdf->State == HAL_MDF_STATE_READY)
+ {
+ if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) != MDF_DFLTCR_DFLTACTIVE)
+ {
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Check state */
+ if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Stop the DMA transfer */
+ if (HAL_DMA_Abort(hmdf->hdma) != HAL_OK)
+ {
+ /* Update state */
+ hmdf->State = HAL_MDF_STATE_ERROR;
+ status = HAL_ERROR;
+ }
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Disable sound activity detector if needed for ADF instance */
+ if (IS_ADF_INSTANCE(hmdf->Instance))
+ {
+ if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) != 0U)
+ {
+ hmdf->Instance->SADCR &= ~(MDF_SADCR_SADEN);
+ }
+ }
+
+ /* Disable filter */
+ hmdf->Instance->DFLTCR &= ~(MDF_DFLTCR_DFLTEN);
+
+ /* Disable interrupts and clear all potential pending flags */
+ if (IS_ADF_INSTANCE(hmdf->Instance))
+ {
+ hmdf->Instance->DFLTIER &= ~(MDF_DFLTIER_SATIE | MDF_DFLTIER_RFOVRIE | MDF_DFLTIER_SDDETIE |
+ MDF_DFLTIER_SDLVLIE);
+ hmdf->Instance->DFLTISR |= (MDF_DFLTISR_SATF | MDF_DFLTISR_RFOVRF | MDF_DFLTISR_SDDETF |
+ MDF_DFLTISR_SDLVLF);
+ }
+ else
+ {
+ hmdf->Instance->DFLTIER &= ~(MDF_DFLTIER_SATIE | MDF_DFLTIER_RFOVRIE);
+ hmdf->Instance->DFLTISR |= (MDF_DFLTISR_SATF | MDF_DFLTISR_RFOVRF);
+ }
+
+ /* Disable MDF DMA requests */
+ hmdf->Instance->DFLTCR &= ~(MDF_DFLTCR_DMAEN);
+
+ /* Update state */
+ hmdf->State = HAL_MDF_STATE_READY;
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to generate pulse on TRGO signal.
+ * @param hmdf MDF handle.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_MDF_GenerateTrgo(MDF_HandleTypeDef *hmdf)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check state */
+ if (hmdf->State != HAL_MDF_STATE_READY)
+ {
+ if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+ {
+ status = HAL_ERROR;
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ MDF_TypeDef *p_mdf_base;
+
+ /* Get MDF base according instance */
+ p_mdf_base = (IS_ADF_INSTANCE(hmdf->Instance)) ? ADF1 : MDF1;
+
+ /* Check if trigger output control is already active */
+ if ((p_mdf_base->GCR & MDF_GCR_TRGO) == MDF_GCR_TRGO)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Generate pulse on trigger output control signal */
+ p_mdf_base->GCR |= MDF_GCR_TRGO;
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to set delay to apply on data source in number of samples.
+ * @param hmdf MDF handle.
+ * @param Delay Delay to apply on data source in number of samples.
+ * This parameter must be a number between Min_Data = 0 and Max_Data = 127.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_MDF_SetDelay(MDF_HandleTypeDef *hmdf, uint32_t Delay)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_MDF_DELAY(Delay));
+
+ /* Check state */
+ if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check if bitstream delay is already active */
+ if ((hmdf->Instance->DLYCR & MDF_DLYCR_SKPBF) == MDF_DLYCR_SKPBF)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Configure bitstream delay */
+ hmdf->Instance->DLYCR |= Delay;
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to get current delay applied on data source in number of samples.
+ * @param hmdf MDF handle.
+ * @param pDelay Current delay applied on data source in number of samples.
+ * This value is between Min_Data = 0 and Max_Data = 127.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_MDF_GetDelay(MDF_HandleTypeDef *hmdf, uint32_t *pDelay)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ if (pDelay == NULL)
+ {
+ status = HAL_ERROR;
+ }
+ /* Check state */
+ else if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Get current bitstream delay */
+ *pDelay = (hmdf->Instance->DLYCR & MDF_DLYCR_SKPDLY);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to set filter gain.
+ * @param hmdf MDF handle.
+ * @param Gain Filter gain in step of around 3db (from -48db to 72dB).
+ * This parameter must be a number between Min_Data = -16 and Max_Data = 24.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_MDF_SetGain(MDF_HandleTypeDef *hmdf, int32_t Gain)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_MDF_GAIN(Gain));
+
+ /* Check state */
+ if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ uint32_t register_gain_value;
+ uint32_t tmp_register;
+
+ if (Gain < 0)
+ {
+ int32_t adjust_gain;
+
+ /* adjust gain value to set on register for negative value (offset of -16) */
+ adjust_gain = Gain - 16;
+ register_gain_value = ((uint32_t) adjust_gain & 0x3FU);
+ }
+ else
+ {
+ /* for positive value, no offset to apply */
+ register_gain_value = (uint32_t) Gain;
+ }
+ /* Set gain */
+ tmp_register = (hmdf->Instance->DFLTCICR & ~(MDF_DFLTCICR_SCALE));
+ hmdf->Instance->DFLTCICR = (tmp_register | (register_gain_value << MDF_DFLTCICR_SCALE_Pos));
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to get filter gain.
+ * @param hmdf MDF handle.
+ * @param pGain Filter gain in step of around 3db (from -48db to 72dB).
+ * This parameter is between Min_Data = -16 and Max_Data = 24.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_MDF_GetGain(MDF_HandleTypeDef *hmdf, int32_t *pGain)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ if (pGain == NULL)
+ {
+ status = HAL_ERROR;
+ }
+ /* Check state */
+ else if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ uint32_t register_gain_value;
+
+ /* Get current gain */
+ register_gain_value = ((hmdf->Instance->DFLTCICR & MDF_DFLTCICR_SCALE) >> MDF_DFLTCICR_SCALE_Pos);
+ if (register_gain_value > 31U)
+ {
+ /* adjust gain value to set on register for negative value (offset of +16) */
+ register_gain_value |= 0xFFFFFFC0U;
+ *pGain = (int32_t) register_gain_value + 16;
+ }
+ else
+ {
+ /* for positive value, no offset to apply */
+ *pGain = (int32_t) register_gain_value;
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to set filter offset error compensation.
+ * @param hmdf MDF handle.
+ * @param Offset Filter offset error compensation.
+ * This parameter must be a number between Min_Data = -33554432 and Max_Data = 33554431.
+ * @retval HAL status.
+ * @note This function must not be used with ADF instance.
+ */
+HAL_StatusTypeDef HAL_MDF_SetOffset(MDF_HandleTypeDef *hmdf, int32_t Offset)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_MDF_INSTANCE(hmdf->Instance));
+ assert_param(IS_MDF_OFFSET(Offset));
+
+ /* Check state */
+ if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Set offset */
+ hmdf->Instance->OECCR = (uint32_t) Offset;
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to get filter offset error compensation.
+ * @param hmdf MDF handle.
+ * @param pOffset Filter offset error compensation.
+ * This value is between Min_Data = -33554432 and Max_Data = 33554431.
+ * @retval HAL status.
+ * @note This function must not be used with ADF instance.
+ */
+HAL_StatusTypeDef HAL_MDF_GetOffset(MDF_HandleTypeDef *hmdf, int32_t *pOffset)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_MDF_INSTANCE(hmdf->Instance));
+ if (pOffset == NULL)
+ {
+ status = HAL_ERROR;
+ }
+ /* Check state */
+ else if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ uint32_t register_offset_value;
+
+ /* Get current offset */
+ register_offset_value = hmdf->Instance->OECCR;
+ if (register_offset_value > 33554431U)
+ {
+ /* Negative value */
+ register_offset_value |= 0xFC000000U;
+ *pOffset = (int32_t) register_offset_value;
+ }
+ else
+ {
+ /* Positive value */
+ *pOffset = (int32_t) register_offset_value;
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to poll for sound level data.
+ * @param hmdf MDF handle.
+ * @param Timeout Timeout value in milliseconds.
+ * @param pSoundLevel Sound level.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 32767.
+ * @param pAmbientNoise Ambient noise.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 32767.
+ * @retval HAL status.
+ * @note This function must not be used with MDF instance.
+ */
+HAL_StatusTypeDef HAL_MDF_PollForSndLvl(MDF_HandleTypeDef *hmdf, uint32_t Timeout, uint32_t *pSoundLevel,
+ uint32_t *pAmbientNoise)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_ADF_INSTANCE(hmdf->Instance));
+ if ((pSoundLevel == NULL) || (pAmbientNoise == NULL))
+ {
+ status = HAL_ERROR;
+ }
+ /* Check state */
+ else if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+ {
+ status = HAL_ERROR;
+ }
+ /* Check SAD status */
+ else if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) == 0U)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Wait for available sound level data */
+ while (((hmdf->Instance->DFLTISR & MDF_DFLTISR_SDLVLF) != MDF_DFLTISR_SDLVLF) && (status == HAL_OK))
+ {
+ /* Check the timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ status = HAL_TIMEOUT;
+ }
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Get sound level */
+ *pSoundLevel = hmdf->Instance->SADSDLVR;
+
+ /* Get ambient noise */
+ *pAmbientNoise = hmdf->Instance->SADANLVR;
+
+ /* Clear sound level ready flag */
+ hmdf->Instance->DFLTISR |= MDF_DFLTISR_SDLVLF;
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to poll for sound activity detection.
+ * @param hmdf MDF handle.
+ * @param Timeout Timeout value in milliseconds.
+ * @retval HAL status.
+ * @note This function must not be used with MDF instance.
+ */
+HAL_StatusTypeDef HAL_MDF_PollForSad(MDF_HandleTypeDef *hmdf, uint32_t Timeout)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_ADF_INSTANCE(hmdf->Instance));
+
+ /* Check state */
+ if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+ {
+ status = HAL_ERROR;
+ }
+ /* Check SAD status */
+ else if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) == 0U)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Wait for sound activity detection */
+ while (((hmdf->Instance->DFLTISR & MDF_DFLTISR_SDDETF) != MDF_DFLTISR_SDDETF) && (status == HAL_OK))
+ {
+ /* Check the timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ status = HAL_TIMEOUT;
+ }
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Clear sound activity detection flag */
+ hmdf->Instance->DFLTISR |= MDF_DFLTISR_SDDETF;
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief MDF acquisition complete callback.
+ * @param hmdf MDF handle.
+ * @retval None.
+ */
+__weak void HAL_MDF_AcqCpltCallback(MDF_HandleTypeDef *hmdf)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hmdf);
+
+ /* NOTE : This function should not be modified, when the function is needed,
+ the HAL_MDF_AcqCpltCallback could be implemented in the user file */
+}
+
+/**
+ * @brief MDF acquisition half complete callback.
+ * @param hmdf MDF handle.
+ * @retval None.
+ */
+__weak void HAL_MDF_AcqHalfCpltCallback(MDF_HandleTypeDef *hmdf)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hmdf);
+
+ /* NOTE : This function should not be modified, when the function is needed,
+ the HAL_MDF_AcqHalfCpltCallback could be implemented in the user file */
+}
+
+/**
+ * @brief MDF sound level callback.
+ * @param hmdf MDF handle.
+ * @param SoundLevel Sound level value computed by sound activity detector.
+ * This parameter can be a value between Min_Data = 0 and Max_Data = 32767.
+ * @param AmbientNoise Ambient noise value computed by sound activity detector.
+ * This parameter can be a value between Min_Data = 0 and Max_Data = 32767.
+ * @retval None.
+ */
+__weak void HAL_MDF_SndLvlCallback(MDF_HandleTypeDef *hmdf, uint32_t SoundLevel, uint32_t AmbientNoise)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hmdf);
+ UNUSED(SoundLevel);
+ UNUSED(AmbientNoise);
+
+ /* NOTE : This function should not be modified, when the function is needed,
+ the HAL_MDF_SndLvlCallback could be implemented in the user file */
+}
+
+/**
+ * @brief MDF sound activity detector callback.
+ * @param hmdf MDF handle.
+ * @retval None.
+ */
+__weak void HAL_MDF_SadCallback(MDF_HandleTypeDef *hmdf)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hmdf);
+
+ /* NOTE : This function should not be modified, when the function is needed,
+ the HAL_MDF_SadCallback could be implemented in the user file */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup MDF_Exported_Functions_Group3 Clock absence detection functions
+ * @brief Clock absence detection functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Clock absence detection functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to :
+ (+) Start and stop clock absence detection in interrupt mode.
+ (+) Detect clock absence.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function allows to poll for the clock absence detection.
+ * @param hmdf MDF handle.
+ * @param Timeout Timeout value in milliseconds.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_MDF_PollForCkab(MDF_HandleTypeDef *hmdf, uint32_t Timeout)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check state */
+ if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+ {
+ if (hmdf->State != HAL_MDF_STATE_READY)
+ {
+ status = HAL_ERROR;
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Check serial interface status and mode */
+ if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFACTIVE) == 0U)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFMOD) != MDF_SITF_NORMAL_SPI_MODE)
+ {
+ status = HAL_ERROR;
+ }
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Wait for clock absence detection */
+ while (((hmdf->Instance->DFLTISR & MDF_DFLTISR_CKABF) != MDF_DFLTISR_CKABF) && (status == HAL_OK))
+ {
+ /* Check the timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ status = HAL_TIMEOUT;
+ }
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Clear clock absence detection flag */
+ hmdf->Instance->DFLTISR |= MDF_DFLTISR_CKABF;
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to start clock absence detection in interrupt mode.
+ * @param hmdf MDF handle.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_MDF_CkabStart_IT(MDF_HandleTypeDef *hmdf)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check state */
+ if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+ {
+ if (hmdf->State != HAL_MDF_STATE_READY)
+ {
+ status = HAL_ERROR;
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Check serial interface status and mode */
+ if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFACTIVE) == 0U)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFMOD) != MDF_SITF_NORMAL_SPI_MODE)
+ {
+ status = HAL_ERROR;
+ }
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Clear clock absence detection flag */
+ hmdf->Instance->DFLTISR |= MDF_DFLTISR_CKABF;
+
+ /* Check clock absence detection flag */
+ if ((hmdf->Instance->DFLTISR & MDF_DFLTISR_CKABF) == MDF_DFLTISR_CKABF)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Enable clock absence detection interrupt */
+ hmdf->Instance->DFLTIER |= MDF_DFLTIER_CKABIE;
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to stop clock absence detection in interrupt mode.
+ * @param hmdf MDF handle.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_MDF_CkabStop_IT(MDF_HandleTypeDef *hmdf)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check state */
+ if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+ {
+ if (hmdf->State != HAL_MDF_STATE_READY)
+ {
+ status = HAL_ERROR;
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Check serial interface status and mode */
+ if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFACTIVE) == 0U)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFMOD) != MDF_SITF_NORMAL_SPI_MODE)
+ {
+ status = HAL_ERROR;
+ }
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Disable clock absence detection interrupt */
+ hmdf->Instance->DFLTIER &= ~(MDF_DFLTIER_CKABIE);
+
+ /* Clear potential pending clock absence detection flag */
+ hmdf->Instance->DFLTISR |= MDF_DFLTISR_CKABF;
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup MDF_Exported_Functions_Group4 Short circuit detection functions
+ * @brief Short circuit detection functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Short circuit detection functions #####
+ ==============================================================================
+ [..] This section provides functions available only for MDF instance
+ allowing to :
+ (+) Start and stop short circuit detection in polling and interrupt mode.
+ (+) Detect short circuit.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function allows to start short-circuit detection in polling mode.
+ * @param hmdf MDF handle.
+ * @param pScdConfig Short-circuit detector configuration parameters.
+ * @retval HAL status.
+ * @note This function must not be used with ADF instance.
+ */
+HAL_StatusTypeDef HAL_MDF_ScdStart(MDF_HandleTypeDef *hmdf, MDF_ScdConfigTypeDef *pScdConfig)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ if (pScdConfig == NULL)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ assert_param(IS_MDF_INSTANCE(hmdf->Instance));
+ assert_param(IS_MDF_SCD_THRESHOLD(pScdConfig->Threshold));
+ assert_param(IS_MDF_BREAK_SIGNAL(pScdConfig->BreakSignal));
+
+ /* Check state */
+ if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+ {
+ if (hmdf->State != HAL_MDF_STATE_READY)
+ {
+ status = HAL_ERROR;
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Check short-circuit detector status */
+ if ((hmdf->Instance->SCDCR & MDF_SCDCR_SCDACTIVE) == MDF_SCDCR_SCDACTIVE)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Configure threshold and break signal */
+ hmdf->Instance->SCDCR = (((pScdConfig->Threshold - 1U) << MDF_SCDCR_SCDT_Pos) |
+ (pScdConfig->BreakSignal << MDF_SCDCR_BKSCD_Pos));
+
+ /* Enable short-circuit detector */
+ hmdf->Instance->SCDCR |= MDF_SCDCR_SCDEN;
+ }
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to poll for the short-circuit detection.
+ * @param hmdf MDF handle.
+ * @param Timeout Timeout value in milliseconds.
+ * @retval HAL status.
+ * @note This function must not be used with ADF instance.
+ */
+HAL_StatusTypeDef HAL_MDF_PollForScd(MDF_HandleTypeDef *hmdf, uint32_t Timeout)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_MDF_INSTANCE(hmdf->Instance));
+
+ /* Check state */
+ if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+ {
+ if (hmdf->State != HAL_MDF_STATE_READY)
+ {
+ status = HAL_ERROR;
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Check short-circuit detector status */
+ if ((hmdf->Instance->SCDCR & MDF_SCDCR_SCDACTIVE) != MDF_SCDCR_SCDACTIVE)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Wait for short-circuit detection */
+ while (((hmdf->Instance->DFLTISR & MDF_DFLTISR_SCDF) != MDF_DFLTISR_SCDF) && (status == HAL_OK))
+ {
+ /* Check the timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ status = HAL_TIMEOUT;
+ }
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Clear short-circuit detection flag */
+ hmdf->Instance->DFLTISR |= MDF_DFLTISR_SCDF;
+ }
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to stop short-circuit detection in polling mode.
+ * @param hmdf MDF handle.
+ * @retval HAL status.
+ * @note This function must not be used with ADF instance.
+ */
+HAL_StatusTypeDef HAL_MDF_ScdStop(MDF_HandleTypeDef *hmdf)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_MDF_INSTANCE(hmdf->Instance));
+
+ /* Check state */
+ if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+ {
+ if (hmdf->State != HAL_MDF_STATE_READY)
+ {
+ status = HAL_ERROR;
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Check short-circuit detector status */
+ if ((hmdf->Instance->SCDCR & MDF_SCDCR_SCDACTIVE) != MDF_SCDCR_SCDACTIVE)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Disable short-circuit detection */
+ hmdf->Instance->SCDCR &= ~(MDF_SCDCR_SCDEN);
+
+ /* Clear potential pending short-circuit detection flag */
+ hmdf->Instance->DFLTISR |= MDF_DFLTISR_SCDF;
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to start short-circuit detection in interrupt mode.
+ * @param hmdf MDF handle.
+ * @param pScdConfig Short-circuit detector configuration parameters.
+ * @retval HAL status.
+ * @note This function must not be used with ADF instance.
+ */
+HAL_StatusTypeDef HAL_MDF_ScdStart_IT(MDF_HandleTypeDef *hmdf, MDF_ScdConfigTypeDef *pScdConfig)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ if (pScdConfig == NULL)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ assert_param(IS_MDF_INSTANCE(hmdf->Instance));
+ assert_param(IS_MDF_SCD_THRESHOLD(pScdConfig->Threshold));
+ assert_param(IS_MDF_BREAK_SIGNAL(pScdConfig->BreakSignal));
+
+ /* Check state */
+ if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+ {
+ if (hmdf->State != HAL_MDF_STATE_READY)
+ {
+ status = HAL_ERROR;
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Check short-circuit detector status */
+ if ((hmdf->Instance->SCDCR & MDF_SCDCR_SCDACTIVE) == MDF_SCDCR_SCDACTIVE)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Configure threshold and break signal */
+ hmdf->Instance->SCDCR = (((pScdConfig->Threshold - 1U) << MDF_SCDCR_SCDT_Pos) |
+ (pScdConfig->BreakSignal << MDF_SCDCR_BKSCD_Pos));
+
+ /* Enable short-circuit detector interrupt */
+ hmdf->Instance->DFLTIER |= MDF_DFLTIER_SCDIE;
+
+ /* Enable short-circuit detector */
+ hmdf->Instance->SCDCR |= MDF_SCDCR_SCDEN;
+ }
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to stop short-circuit detection in interrupt mode.
+ * @param hmdf MDF handle.
+ * @retval HAL status.
+ * @note This function must not be used with ADF instance.
+ */
+HAL_StatusTypeDef HAL_MDF_ScdStop_IT(MDF_HandleTypeDef *hmdf)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_MDF_INSTANCE(hmdf->Instance));
+
+ /* Check state */
+ if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+ {
+ if (hmdf->State != HAL_MDF_STATE_READY)
+ {
+ status = HAL_ERROR;
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Check short-circuit detector status */
+ if ((hmdf->Instance->SCDCR & MDF_SCDCR_SCDACTIVE) != MDF_SCDCR_SCDACTIVE)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Disable short-circuit detection */
+ hmdf->Instance->SCDCR &= ~(MDF_SCDCR_SCDEN);
+
+ /* Disable short-circuit detection interrupt */
+ hmdf->Instance->DFLTIER &= ~(MDF_DFLTIER_SCDIE);
+
+ /* Clear potential pending short-circuit detection flag */
+ hmdf->Instance->DFLTISR |= MDF_DFLTISR_SCDF;
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup MDF_Exported_Functions_Group5 Out-off limit detection functions
+ * @brief Out-off limit detection functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Out-off limit detection functions #####
+ ==============================================================================
+ [..] This section provides functions available only for MDF instance
+ allowing to :
+ (+) Start and stop out-off limit detection in polling and interrupt mode.
+ (+) Detect short circuit and get threshold information.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function allows to start out-off limit detection in polling mode.
+ * @param hmdf MDF handle.
+ * @param pOldConfig Out-off limit detector configuration parameters.
+ * @retval HAL status.
+ * @note This function must not be used with ADF instance.
+ */
+HAL_StatusTypeDef HAL_MDF_OldStart(MDF_HandleTypeDef *hmdf, MDF_OldConfigTypeDef *pOldConfig)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ if (pOldConfig == NULL)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ assert_param(IS_MDF_INSTANCE(hmdf->Instance));
+ assert_param(IS_MDF_OLD_CIC_MODE(pOldConfig->OldCicMode));
+ assert_param(IS_MDF_OLD_DECIMATION_RATIO(pOldConfig->OldDecimationRatio));
+ assert_param(IS_MDF_OLD_THRESHOLD(pOldConfig->HighThreshold));
+ assert_param(IS_MDF_OLD_THRESHOLD(pOldConfig->LowThreshold));
+ assert_param(IS_MDF_OLD_EVENT_CONFIG(pOldConfig->OldEventConfig));
+ assert_param(IS_MDF_BREAK_SIGNAL(pOldConfig->BreakSignal));
+ if (pOldConfig->LowThreshold >= pOldConfig->HighThreshold)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check state */
+ if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+ {
+ if (hmdf->State != HAL_MDF_STATE_READY)
+ {
+ status = HAL_ERROR;
+ }
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Check out-off limit detector status */
+ if ((hmdf->Instance->OLDCR & MDF_OLDCR_OLDACTIVE) == MDF_OLDCR_OLDACTIVE)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check filter status */
+ if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) == MDF_DFLTCR_DFLTACTIVE)
+ {
+ /* Check main filter order */
+ if ((hmdf->Instance->DFLTCICR & MDF_DFLTCICR_CICMOD) >= MDF_ONE_FILTER_SINC4)
+ {
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Reset main filter order */
+ hmdf->Instance->DFLTCICR &= ~(MDF_DFLTCICR_CICMOD);
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Configure OLD CIC mode, decimation ratio, event and break signal */
+ hmdf->Instance->OLDCR = (pOldConfig->OldCicMode | pOldConfig->OldEventConfig |
+ ((pOldConfig->OldDecimationRatio - 1U) << MDF_OLDCR_ACICD_Pos) |
+ (pOldConfig->BreakSignal << MDF_OLDCR_BKOLD_Pos));
+
+ /* Configure low and high thresholds */
+ hmdf->Instance->OLDTHLR = (uint32_t) pOldConfig->LowThreshold;
+ hmdf->Instance->OLDTHHR = (uint32_t) pOldConfig->HighThreshold;
+
+ /* Enable out-off limit detector */
+ hmdf->Instance->OLDCR |= MDF_OLDCR_OLDEN;
+ }
+ }
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to poll for the out-off limit detection.
+ * @param hmdf MDF handle.
+ * @param Timeout Timeout value in milliseconds.
+ * @param pThresholdInfo Threshold information of out-off limit detection.
+ * This parameter can be a value of @ref MDF_OldThresholdInfo.
+ * @retval HAL status.
+ * @note This function must not be used with ADF instance.
+ */
+HAL_StatusTypeDef HAL_MDF_PollForOld(MDF_HandleTypeDef *hmdf, uint32_t Timeout, uint32_t *pThresholdInfo)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_MDF_INSTANCE(hmdf->Instance));
+ if (pThresholdInfo == NULL)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check state */
+ if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+ {
+ if (hmdf->State != HAL_MDF_STATE_READY)
+ {
+ status = HAL_ERROR;
+ }
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Check out-off limit detector status */
+ if ((hmdf->Instance->OLDCR & MDF_OLDCR_OLDACTIVE) != MDF_OLDCR_OLDACTIVE)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Wait for out-off limit detection */
+ while (((hmdf->Instance->DFLTISR & MDF_DFLTISR_OLDF) != MDF_DFLTISR_OLDF) && (status == HAL_OK))
+ {
+ /* Check the timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ status = HAL_TIMEOUT;
+ }
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Get threshold information */
+ if ((hmdf->Instance->DFLTISR & (MDF_DFLTISR_THLF | MDF_DFLTISR_THHF)) == 0U)
+ {
+ *pThresholdInfo = MDF_OLD_IN_THRESHOLDS;
+ }
+ else if ((hmdf->Instance->DFLTISR & MDF_DFLTISR_THLF) == MDF_DFLTISR_THLF)
+ {
+ *pThresholdInfo = MDF_OLD_LOW_THRESHOLD;
+ }
+ else
+ {
+ *pThresholdInfo = MDF_OLD_HIGH_THRESHOLD;
+ }
+
+ /* Clear out-off limit detection flags */
+ hmdf->Instance->DFLTISR |= MDF_DFLTISR_OLDF;
+ }
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to stop out-off limit detection in polling mode.
+ * @param hmdf MDF handle.
+ * @retval HAL status.
+ * @note This function must not be used with ADF instance.
+ */
+HAL_StatusTypeDef HAL_MDF_OldStop(MDF_HandleTypeDef *hmdf)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_MDF_INSTANCE(hmdf->Instance));
+
+ /* Check state */
+ if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+ {
+ if (hmdf->State != HAL_MDF_STATE_READY)
+ {
+ status = HAL_ERROR;
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Check out-off limit detector status */
+ if ((hmdf->Instance->OLDCR & MDF_OLDCR_OLDACTIVE) != MDF_OLDCR_OLDACTIVE)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Disable out-off limit detection */
+ hmdf->Instance->OLDCR &= ~(MDF_OLDCR_OLDEN);
+
+ /* Clear potential pending out-off limit detection flags */
+ hmdf->Instance->DFLTISR |= MDF_DFLTISR_OLDF;
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to start out-off limit detection in interrupt mode.
+ * @param hmdf MDF handle.
+ * @param pOldConfig Out-off limit detector configuration parameters.
+ * @retval HAL status.
+ * @note This function must not be used with ADF instance.
+ */
+HAL_StatusTypeDef HAL_MDF_OldStart_IT(MDF_HandleTypeDef *hmdf, MDF_OldConfigTypeDef *pOldConfig)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ if (pOldConfig == NULL)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ assert_param(IS_MDF_INSTANCE(hmdf->Instance));
+ assert_param(IS_MDF_OLD_CIC_MODE(pOldConfig->OldCicMode));
+ assert_param(IS_MDF_OLD_DECIMATION_RATIO(pOldConfig->OldDecimationRatio));
+ assert_param(IS_MDF_OLD_THRESHOLD(pOldConfig->HighThreshold));
+ assert_param(IS_MDF_OLD_THRESHOLD(pOldConfig->LowThreshold));
+ assert_param(IS_MDF_OLD_EVENT_CONFIG(pOldConfig->OldEventConfig));
+ assert_param(IS_MDF_BREAK_SIGNAL(pOldConfig->BreakSignal));
+ if (pOldConfig->LowThreshold >= pOldConfig->HighThreshold)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check state */
+ if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+ {
+ if (hmdf->State != HAL_MDF_STATE_READY)
+ {
+ status = HAL_ERROR;
+ }
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Check out-off limit detector status */
+ if ((hmdf->Instance->OLDCR & MDF_OLDCR_OLDACTIVE) == MDF_OLDCR_OLDACTIVE)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check filter status */
+ if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) == MDF_DFLTCR_DFLTACTIVE)
+ {
+ /* Check main filter order */
+ if ((hmdf->Instance->DFLTCICR & MDF_DFLTCICR_CICMOD) >= MDF_ONE_FILTER_SINC4)
+ {
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Reset main filter order */
+ hmdf->Instance->DFLTCICR &= ~(MDF_DFLTCICR_CICMOD);
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Configure OLD CIC mode, decimation ratio, event and break signal */
+ hmdf->Instance->OLDCR = (pOldConfig->OldCicMode | pOldConfig->OldEventConfig |
+ ((pOldConfig->OldDecimationRatio - 1U) << MDF_OLDCR_ACICD_Pos) |
+ (pOldConfig->BreakSignal << MDF_OLDCR_BKOLD_Pos));
+
+ /* Configure low and high thresholds */
+ hmdf->Instance->OLDTHLR = (uint32_t) pOldConfig->LowThreshold;
+ hmdf->Instance->OLDTHHR = (uint32_t) pOldConfig->HighThreshold;
+
+ /* Enable out-off limit detector interrupt */
+ hmdf->Instance->DFLTIER |= MDF_DFLTIER_OLDIE;
+
+ /* Enable out-off limit detector */
+ hmdf->Instance->OLDCR |= MDF_OLDCR_OLDEN;
+ }
+ }
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to stop out-off limit detection in interrupt mode.
+ * @param hmdf MDF handle.
+ * @retval HAL status.
+ * @note This function must not be used with ADF instance.
+ */
+HAL_StatusTypeDef HAL_MDF_OldStop_IT(MDF_HandleTypeDef *hmdf)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_MDF_INSTANCE(hmdf->Instance));
+
+ /* Check state */
+ if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+ {
+ if (hmdf->State != HAL_MDF_STATE_READY)
+ {
+ status = HAL_ERROR;
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Check out-off limit detector status */
+ if ((hmdf->Instance->OLDCR & MDF_OLDCR_OLDACTIVE) != MDF_OLDCR_OLDACTIVE)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Disable out-off limit detection */
+ hmdf->Instance->OLDCR &= ~(MDF_OLDCR_OLDEN);
+
+ /* Disable out-off limit detector interrupt */
+ hmdf->Instance->DFLTIER &= ~(MDF_DFLTIER_OLDIE);
+
+ /* Clear potential pending out-off limit detection flags */
+ hmdf->Instance->DFLTISR |= MDF_DFLTISR_OLDF;
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief MDF out-off limit detector callback.
+ * @param hmdf MDF handle.
+ * @param ThresholdInfo Threshold information of out-off limit detection.
+ * This parameter can be a value of @ref MDF_OldThresholdInfo.
+ * @retval None.
+ */
+__weak void HAL_MDF_OldCallback(MDF_HandleTypeDef *hmdf, uint32_t ThresholdInfo)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hmdf);
+ UNUSED(ThresholdInfo);
+
+ /* NOTE : This function should not be modified, when the function is needed,
+ the HAL_MDF_OldCallback could be implemented in the user file */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup MDF_Exported_Functions_Group6 Generic functions
+ * @brief Generic functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Generic functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to :
+ (+) Handle MDF interrupt.
+ (+) Inform user that error occurs.
+ (+) Get the current MDF instance state.
+ (+) Get the current MDF instance error code.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function handles the MDF interrupts.
+ * @param hmdf MDF handle.
+ * @retval None.
+ */
+void HAL_MDF_IRQHandler(MDF_HandleTypeDef *hmdf)
+{
+ uint32_t tmp_reg1;
+ uint32_t tmp_reg2;
+ uint32_t interrupts;
+
+ /* Read current flags and interrupts and determine which ones occur */
+ tmp_reg1 = hmdf->Instance->DFLTIER;
+ tmp_reg2 = hmdf->Instance->DFLTISR;
+ interrupts = (tmp_reg1 & tmp_reg2);
+
+ /* Check if data overflow occurs */
+ if ((interrupts & MDF_DFLTISR_DOVRF) == MDF_DFLTISR_DOVRF)
+ {
+ /* Clear data overflow flag */
+ hmdf->Instance->DFLTISR |= MDF_DFLTISR_DOVRF;
+
+ /* Update error code */
+ hmdf->ErrorCode |= MDF_ERROR_ACQUISITION_OVERFLOW;
+
+ /* Call error callback */
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+ hmdf->ErrorCallback(hmdf);
+#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
+ HAL_MDF_ErrorCallback(hmdf);
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+ }
+ /* Check if snapshot overrun occurs */
+ else if ((interrupts & MDF_DFLTISR_SSOVRF) == MDF_DFLTISR_SSOVRF)
+ {
+ /* Clear snapshot overrun flag */
+ hmdf->Instance->DFLTISR |= MDF_DFLTISR_SSOVRF;
+
+ /* Update error code */
+ hmdf->ErrorCode |= MDF_ERROR_ACQUISITION_OVERFLOW;
+
+ /* Call error callback */
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+ hmdf->ErrorCallback(hmdf);
+#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
+ HAL_MDF_ErrorCallback(hmdf);
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+ }
+ /* Check if RXFIFO threshold occurs */
+ else if ((interrupts & MDF_DFLTISR_FTHF) == MDF_DFLTISR_FTHF)
+ {
+ /* Call acquisition complete callback */
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+ hmdf->AcqCpltCallback(hmdf);
+#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
+ HAL_MDF_AcqCpltCallback(hmdf);
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+
+ /* Update state only in asynchronous single shot mode */
+ if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_ACQMOD) == MDF_MODE_ASYNC_SINGLE)
+ {
+ hmdf->State = HAL_MDF_STATE_READY;
+ }
+ }
+ /* Check if snapshot data ready occurs */
+ else if ((interrupts & MDF_DFLTISR_SSDRF) == MDF_DFLTISR_SSDRF)
+ {
+ /* Clear snapshot data ready flag */
+ hmdf->Instance->DFLTISR |= MDF_DFLTISR_SSDRF;
+
+ /* Call acquisition complete callback */
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+ hmdf->AcqCpltCallback(hmdf);
+#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
+ HAL_MDF_AcqCpltCallback(hmdf);
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+ }
+ /* Check if reshape filter overrun occurs */
+ else if ((interrupts & MDF_DFLTISR_RFOVRF) == MDF_DFLTISR_RFOVRF)
+ {
+ /* Clear reshape filter overrun flag */
+ hmdf->Instance->DFLTISR |= MDF_DFLTISR_RFOVRF;
+
+ /* Update error code */
+ hmdf->ErrorCode |= MDF_ERROR_RSF_OVERRUN;
+
+ /* Call error callback */
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+ hmdf->ErrorCallback(hmdf);
+#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
+ HAL_MDF_ErrorCallback(hmdf);
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+ }
+ /* Check if clock absence detection occurs */
+ else if ((interrupts & MDF_DFLTISR_CKABF) == MDF_DFLTISR_CKABF)
+ {
+ /* Clear clock absence detection flag */
+ hmdf->Instance->DFLTISR |= MDF_DFLTISR_CKABF;
+
+ /* Update error code */
+ hmdf->ErrorCode |= MDF_ERROR_CLOCK_ABSENCE;
+
+ /* Call error callback */
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+ hmdf->ErrorCallback(hmdf);
+#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
+ HAL_MDF_ErrorCallback(hmdf);
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+ }
+ /* Check if saturation occurs */
+ else if ((interrupts & MDF_DFLTISR_SATF) == MDF_DFLTISR_SATF)
+ {
+ /* Clear saturation flag */
+ hmdf->Instance->DFLTISR |= MDF_DFLTISR_SATF;
+
+ /* Update error code */
+ hmdf->ErrorCode |= MDF_ERROR_SATURATION;
+
+ /* Call error callback */
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+ hmdf->ErrorCallback(hmdf);
+#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
+ HAL_MDF_ErrorCallback(hmdf);
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+ }
+ /* Check if short-circuit detection occurs */
+ else if ((interrupts & MDF_DFLTISR_SCDF) == MDF_DFLTISR_SCDF)
+ {
+ /* Clear short-circuit detection flag */
+ hmdf->Instance->DFLTISR |= MDF_DFLTISR_SCDF;
+
+ /* Update error code */
+ hmdf->ErrorCode |= MDF_ERROR_SHORT_CIRCUIT;
+
+ /* Call error callback */
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+ hmdf->ErrorCallback(hmdf);
+#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
+ HAL_MDF_ErrorCallback(hmdf);
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+ }
+ /* Check if out-off limit detection occurs */
+ else if ((interrupts & MDF_DFLTISR_OLDF) == MDF_DFLTISR_OLDF)
+ {
+ uint32_t threshold_info;
+
+ /* Get threshold information */
+ if ((hmdf->Instance->DFLTISR & (MDF_DFLTISR_THLF | MDF_DFLTISR_THHF)) == 0U)
+ {
+ threshold_info = MDF_OLD_IN_THRESHOLDS;
+ }
+ else if ((hmdf->Instance->DFLTISR & MDF_DFLTISR_THLF) == MDF_DFLTISR_THLF)
+ {
+ threshold_info = MDF_OLD_LOW_THRESHOLD;
+ }
+ else
+ {
+ threshold_info = MDF_OLD_HIGH_THRESHOLD;
+ }
+
+ /* Clear out-off limit detection flag */
+ hmdf->Instance->DFLTISR |= MDF_DFLTISR_OLDF;
+
+ /* Update error code */
+ hmdf->ErrorCode |= MDF_ERROR_OUT_OFF_LIMIT;
+
+ /* Call out-off limit detection callback */
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+ hmdf->OldCallback(hmdf, threshold_info);
+#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
+ HAL_MDF_OldCallback(hmdf, threshold_info);
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+ }
+ /* Check if sound activity detection occurs */
+ else if ((interrupts & MDF_DFLTISR_SDDETF) == MDF_DFLTISR_SDDETF)
+ {
+ /* Clear sound activity detection flag */
+ hmdf->Instance->DFLTISR |= MDF_DFLTISR_SDDETF;
+
+ /* Call sound activity detection callback */
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+ hmdf->SadCallback(hmdf);
+#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
+ HAL_MDF_SadCallback(hmdf);
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Check if sound level ready occurs */
+ if ((interrupts & MDF_DFLTISR_SDLVLF) == MDF_DFLTISR_SDLVLF)
+ {
+ uint32_t sound_level;
+ uint32_t ambient_noise;
+
+ /* Get sound level */
+ sound_level = hmdf->Instance->SADSDLVR;
+
+ /* Get ambient noise */
+ ambient_noise = hmdf->Instance->SADANLVR;
+
+ /* Clear sound level ready flag */
+ hmdf->Instance->DFLTISR |= MDF_DFLTISR_SDLVLF;
+
+ /* Call sound level callback */
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+ hmdf->SndLvCallback(hmdf, sound_level, ambient_noise);
+#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
+ HAL_MDF_SndLvlCallback(hmdf, sound_level, ambient_noise);
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+ }
+ }
+}
+
+/**
+ * @brief MDF error callback.
+ * @param hmdf MDF handle.
+ * @retval None.
+ */
+__weak void HAL_MDF_ErrorCallback(MDF_HandleTypeDef *hmdf)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hmdf);
+
+ /* NOTE : This function should not be modified, when the function is needed,
+ the HAL_MDF_ErrorCallback could be implemented in the user file */
+}
+
+/**
+ * @brief This function allows to get the current MDF state.
+ * @param hmdf MDF handle.
+ * @retval MDF state.
+ */
+HAL_MDF_StateTypeDef HAL_MDF_GetState(MDF_HandleTypeDef *hmdf)
+{
+ /* Return MDF state */
+ return hmdf->State;
+}
+
+/**
+ * @brief This function allows to get the current MDF error.
+ * @param hmdf MDF handle.
+ * @retval MDF error code.
+ */
+uint32_t HAL_MDF_GetError(MDF_HandleTypeDef *hmdf)
+{
+ /* Return MDF error code */
+ return hmdf->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup MDF_Private_Functions
+ * @brief Private functions
+ * @{
+ */
+
+/**
+ * @brief This function allows to get the handle number from instance.
+ * @param pInstance MDF instance.
+ * @retval Instance number.
+ */
+static uint32_t MDF_GetHandleNumberFromInstance(const MDF_Filter_TypeDef *const pInstance)
+{
+ uint32_t handle_number;
+
+ /* Get handle number from instance */
+ if (pInstance == MDF1_Filter0)
+ {
+ handle_number = 0U;
+ }
+ else if (pInstance == MDF1_Filter1)
+ {
+ handle_number = 1U;
+ }
+ else if (pInstance == MDF1_Filter2)
+ {
+ handle_number = 2U;
+ }
+ else if (pInstance == MDF1_Filter3)
+ {
+ handle_number = 3U;
+ }
+ else if (pInstance == MDF1_Filter4)
+ {
+ handle_number = 4U;
+ }
+ else if (pInstance == MDF1_Filter5)
+ {
+ handle_number = 5U;
+ }
+ else /* ADF1_Filter0 */
+ {
+ handle_number = 6U;
+ }
+
+ return handle_number;
+}
+
+/**
+ * @brief This function allows to configure filter and start acquisition.
+ * @param hmdf MDF handle.
+ * @param pFilterConfig Filter configuration parameters.
+ * @retval None.
+ */
+static void MDF_AcqStart(MDF_HandleTypeDef *const hmdf, const MDF_FilterConfigTypeDef *const pFilterConfig)
+{
+ uint32_t register_gain_value;
+
+ /* Configure acquisition mode, discard samples, trigger and fifo threshold */
+ assert_param(IS_MDF_DISCARD_SAMPLES(pFilterConfig->DiscardSamples));
+ assert_param(IS_MDF_FIFO_THRESHOLD(pFilterConfig->FifoThreshold));
+ if ((pFilterConfig->AcquisitionMode == MDF_MODE_ASYNC_CONT) ||
+ (pFilterConfig->AcquisitionMode == MDF_MODE_ASYNC_SINGLE))
+ {
+ /* Trigger parameters are not used */
+ hmdf->Instance->DFLTCR |= (pFilterConfig->AcquisitionMode | pFilterConfig->FifoThreshold |
+ (pFilterConfig->DiscardSamples << MDF_DFLTCR_NBDIS_Pos));
+ }
+ else
+ {
+ /* Trigger parameters are used */
+ if (IS_ADF_INSTANCE(hmdf->Instance))
+ {
+ assert_param(IS_ADF_TRIGGER_SOURCE(pFilterConfig->Trigger.Source));
+ }
+ else
+ {
+ assert_param(IS_MDF_TRIGGER_SOURCE(pFilterConfig->Trigger.Source));
+ }
+ assert_param(IS_MDF_TRIGGER_EDGE(pFilterConfig->Trigger.Edge));
+ hmdf->Instance->DFLTCR |= (pFilterConfig->AcquisitionMode | pFilterConfig->FifoThreshold |
+ pFilterConfig->Trigger.Source | pFilterConfig->Trigger.Edge |
+ (pFilterConfig->DiscardSamples << MDF_DFLTCR_NBDIS_Pos));
+ }
+
+ /* Configure if needed snapshot format only for MDF instance */
+ if (IS_MDF_INSTANCE(hmdf->Instance) && (pFilterConfig->AcquisitionMode == MDF_MODE_SYNC_SNAPSHOT))
+ {
+ assert_param(IS_MDF_SNAPSHOT_FORMAT(pFilterConfig->SnapshotFormat));
+ hmdf->Instance->DFLTCR |= pFilterConfig->SnapshotFormat;
+ }
+
+ /* Configure data source, CIC mode, decimation ratio and gain */
+ if (IS_ADF_INSTANCE(hmdf->Instance))
+ {
+ assert_param(IS_ADF_DATA_SOURCE(pFilterConfig->DataSource));
+ assert_param(IS_ADF_CIC_MODE(pFilterConfig->CicMode));
+ }
+ else
+ {
+ assert_param(IS_MDF_DATA_SOURCE(pFilterConfig->DataSource));
+ }
+ assert_param(IS_MDF_DECIMATION_RATIO(pFilterConfig->DecimationRatio));
+ assert_param(IS_MDF_GAIN(pFilterConfig->Gain));
+ if (pFilterConfig->Gain < 0)
+ {
+ int32_t adjust_gain;
+
+ /* adjust gain value to set on register for negative value (offset of -16) */
+ adjust_gain = pFilterConfig->Gain - 16;
+ register_gain_value = ((uint32_t) adjust_gain & 0x3FU);
+ }
+ else
+ {
+ /* for positive value, no offset to apply */
+ register_gain_value = (uint32_t) pFilterConfig->Gain;
+ }
+ hmdf->Instance->DFLTCICR = (pFilterConfig->DataSource | pFilterConfig->CicMode |
+ ((pFilterConfig->DecimationRatio - 1U) << MDF_DFLTCICR_MCICD_Pos) |
+ (register_gain_value << MDF_DFLTCICR_SCALE_Pos));
+
+ /* Configure bitstream delay */
+ assert_param(IS_MDF_DELAY(pFilterConfig->Delay));
+ hmdf->Instance->DLYCR = pFilterConfig->Delay;
+
+ /* Configure offset compensation only for MDF instance */
+ if (IS_MDF_INSTANCE(hmdf->Instance))
+ {
+ assert_param(IS_MDF_OFFSET(pFilterConfig->Offset));
+ hmdf->Instance->OECCR = (uint32_t) pFilterConfig->Offset;
+ }
+
+ /* Configure reshape filter */
+ assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->ReshapeFilter.Activation));
+ hmdf->Instance->DFLTRSFR = 0U;
+ if (pFilterConfig->ReshapeFilter.Activation == ENABLE)
+ {
+ /* Configure reshape filter decimation ratio */
+ assert_param(IS_MDF_RSF_DECIMATION_RATIO(pFilterConfig->ReshapeFilter.DecimationRatio));
+ hmdf->Instance->DFLTRSFR |= pFilterConfig->ReshapeFilter.DecimationRatio;
+ }
+ else
+ {
+ /* Bypass reshape filter */
+ hmdf->Instance->DFLTRSFR |= MDF_DFLTRSFR_RSFLTBYP;
+ }
+
+ /* Configure high-pass filter */
+ assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->HighPassFilter.Activation));
+ if (pFilterConfig->HighPassFilter.Activation == ENABLE)
+ {
+ /* Configure high-pass filter cut-off frequency */
+ assert_param(IS_MDF_HPF_CUTOFF_FREQ(pFilterConfig->HighPassFilter.CutOffFrequency));
+ hmdf->Instance->DFLTRSFR |= pFilterConfig->HighPassFilter.CutOffFrequency;
+ }
+ else
+ {
+ /* Bypass high-pass filter */
+ hmdf->Instance->DFLTRSFR |= MDF_DFLTRSFR_HPFBYP;
+ }
+
+ /* Configure integrator only for MDF instance */
+ if (IS_MDF_INSTANCE(hmdf->Instance))
+ {
+ assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->Integrator.Activation));
+ if (pFilterConfig->Integrator.Activation == ENABLE)
+ {
+ /* Configure integrator value and output division */
+ assert_param(IS_MDF_INTEGRATOR_VALUE(pFilterConfig->Integrator.Value));
+ assert_param(IS_MDF_INTEGRATOR_OUTPUT_DIV(pFilterConfig->Integrator.OutputDivision));
+ hmdf->Instance->DFLTINTR = (((pFilterConfig->Integrator.Value - 1U) << MDF_DFLTINTR_INTVAL_Pos) |
+ pFilterConfig->Integrator.OutputDivision);
+ }
+ else
+ {
+ /* Bypass integrator */
+ hmdf->Instance->DFLTINTR = 0U;
+ }
+ }
+
+ if (IS_ADF_INSTANCE(hmdf->Instance))
+ {
+ assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->SoundActivity.Activation));
+ if (pFilterConfig->SoundActivity.Activation == ENABLE)
+ {
+ /* Configure SAD mode, frame size, hysteresis, sound trigger event
+ and data memory transfer only for ADF instance */
+ assert_param(IS_MDF_SAD_MODE(pFilterConfig->SoundActivity.Mode));
+ assert_param(IS_MDF_SAD_FRAME_SIZE(pFilterConfig->SoundActivity.FrameSize));
+ if (pFilterConfig->SoundActivity.Mode != MDF_SAD_AMBIENT_NOISE_DETECTOR)
+ {
+ assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->SoundActivity.Hysteresis));
+ }
+ assert_param(IS_MDF_SAD_SOUND_TRIGGER(pFilterConfig->SoundActivity.SoundTriggerEvent));
+ assert_param(IS_MDF_SAD_DATA_MEMORY_TRANSFER(pFilterConfig->SoundActivity.DataMemoryTransfer));
+ if ((pFilterConfig->SoundActivity.Mode != MDF_SAD_AMBIENT_NOISE_DETECTOR) &&
+ (pFilterConfig->SoundActivity.Hysteresis == ENABLE))
+ {
+ hmdf->Instance->SADCR = (pFilterConfig->SoundActivity.Mode | pFilterConfig->SoundActivity.FrameSize |
+ MDF_SADCR_HYSTEN | pFilterConfig->SoundActivity.SoundTriggerEvent |
+ pFilterConfig->SoundActivity.DataMemoryTransfer);
+ }
+ else
+ {
+ hmdf->Instance->SADCR = (pFilterConfig->SoundActivity.Mode | pFilterConfig->SoundActivity.FrameSize |
+ pFilterConfig->SoundActivity.SoundTriggerEvent |
+ pFilterConfig->SoundActivity.DataMemoryTransfer);
+ }
+
+ /* Configure SAD minimum noise level, hangover window, learning frames,
+ ambient noise slope control and signal noise threshold only for ADF instance */
+ assert_param(IS_MDF_SAD_MIN_NOISE_LEVEL(pFilterConfig->SoundActivity.MinNoiseLevel));
+ assert_param(IS_MDF_SAD_HANGOVER_WINDOW(pFilterConfig->SoundActivity.HangoverWindow));
+ assert_param(IS_MDF_SAD_LEARNING_FRAMES(pFilterConfig->SoundActivity.LearningFrames));
+ assert_param(IS_MDF_SAD_SIGNAL_NOISE_THRESHOLD(pFilterConfig->SoundActivity.SignalNoiseThreshold));
+ if (pFilterConfig->SoundActivity.Mode != MDF_SAD_SOUND_DETECTOR)
+ {
+ assert_param(IS_MDF_SAD_AMBIENT_NOISE_SLOPE(pFilterConfig->SoundActivity.AmbientNoiseSlope));
+ hmdf->Instance->SADCFGR = ((pFilterConfig->SoundActivity.MinNoiseLevel << MDF_SADCFGR_ANMIN_Pos) |
+ pFilterConfig->SoundActivity.HangoverWindow |
+ pFilterConfig->SoundActivity.LearningFrames |
+ (pFilterConfig->SoundActivity.AmbientNoiseSlope << MDF_SADCFGR_ANSLP_Pos) |
+ pFilterConfig->SoundActivity.SignalNoiseThreshold);
+ }
+ else
+ {
+ hmdf->Instance->SADCFGR = ((pFilterConfig->SoundActivity.MinNoiseLevel << MDF_SADCFGR_ANMIN_Pos) |
+ pFilterConfig->SoundActivity.HangoverWindow |
+ pFilterConfig->SoundActivity.LearningFrames |
+ pFilterConfig->SoundActivity.SignalNoiseThreshold);
+ }
+ }
+ else
+ {
+ /* SAD is not used */
+ hmdf->Instance->SADCR = 0U;
+ hmdf->Instance->SADCFGR = 0U;
+ }
+ }
+
+ /* Update instance state */
+ hmdf->State = HAL_MDF_STATE_ACQUISITION;
+
+ /* Enable sound activity detector if needed only for ADF instance */
+ if ((IS_ADF_INSTANCE(hmdf->Instance)) && (pFilterConfig->SoundActivity.Activation == ENABLE))
+ {
+ hmdf->Instance->SADCR |= MDF_SADCR_SADEN;
+ }
+
+ /* Enable filter */
+ hmdf->Instance->DFLTCR |= MDF_DFLTCR_DFLTEN;
+}
+
+/**
+ * @brief This function handles DMA transfer complete callback.
+ * @param hdma DMA handle.
+ * @retval None.
+ */
+static void MDF_DmaXferCpltCallback(DMA_HandleTypeDef *hdma)
+{
+ MDF_HandleTypeDef *hmdf = (MDF_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Check if DMA in circular mode */
+ if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR)
+ {
+ hmdf->State = HAL_MDF_STATE_READY;
+ }
+
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+ hmdf->AcqCpltCallback(hmdf);
+#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
+ HAL_MDF_AcqCpltCallback(hmdf);
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief This function handles DMA half transfer complete callback.
+ * @param hdma DMA handle.
+ * @retval None.
+ */
+static void MDF_DmaXferHalfCpltCallback(DMA_HandleTypeDef *hdma)
+{
+ MDF_HandleTypeDef *hmdf = (MDF_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+ hmdf->AcqHalfCpltCallback(hmdf);
+#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
+ HAL_MDF_AcqHalfCpltCallback(hmdf);
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief This function handles DMA error callback.
+ * @param hdma DMA handle.
+ * @retval None.
+ */
+static void MDF_DmaErrorCallback(DMA_HandleTypeDef *hdma)
+{
+ MDF_HandleTypeDef *hmdf = (MDF_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Update error code */
+ hmdf->ErrorCode |= MDF_ERROR_DMA;
+
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+ hmdf->ErrorCallback(hmdf);
+#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
+ HAL_MDF_ErrorCallback(hmdf);
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_MDF_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mmc.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mmc.c
new file mode 100644
index 00000000..faa2b709
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mmc.c
@@ -0,0 +1,3864 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_mmc.c
+ * @author MCD Application Team
+ * @brief MMC card HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Secure Digital (MMC) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + MMC card Control functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This driver implements a high level communication layer for read and write from/to
+ this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by
+ the user in HAL_MMC_MspInit() function (MSP layer).
+ Basically, the MSP layer configuration should be the same as we provide in the
+ examples.
+ You can easily tailor this configuration according to hardware resources.
+
+ [..]
+ This driver is a generic layered driver for SDMMC memories which uses the HAL
+ SDMMC driver functions to interface with MMC and eMMC cards devices.
+ It is used as follows:
+
+ (#)Initialize the SDMMC low level resources by implement the HAL_MMC_MspInit() API:
+ (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE();
+ (##) SDMMC pins configuration for MMC card
+ (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
+ (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()
+ and according to your pin assignment;
+ (##) NVIC configuration if you need to use interrupt process (HAL_MMC_ReadBlocks_IT()
+ and HAL_MMC_WriteBlocks_IT() APIs).
+ (+++) Configure the SDMMC interrupt priorities using function HAL_NVIC_SetPriority();
+ (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ()
+ (+++) SDMMC interrupts are managed using the macros __HAL_MMC_ENABLE_IT()
+ and __HAL_MMC_DISABLE_IT() inside the communication process.
+ (+++) SDMMC interrupts pending bits are managed using the macros __HAL_MMC_GET_IT()
+ and __HAL_MMC_CLEAR_IT()
+ (##) No general propose DMA Configuration is needed, an Internal DMA for SDMMC Peripheral are used.
+
+ (#) At this stage, you can perform MMC read/write/erase operations after MMC card initialization
+
+
+ *** MMC Card Initialization and configuration ***
+ ================================================
+ [..]
+ To initialize the MMC Card, use the HAL_MMC_Init() function. It Initializes
+ SDMMC Peripheral (STM32 side) and the MMC Card, and put it into StandBy State (Ready for data transfer).
+ This function provide the following operations:
+
+ (#) Initialize the SDMMC peripheral interface with defaullt configuration.
+ The initialization process is done at 400KHz. You can change or adapt
+ this frequency by adjusting the "ClockDiv" field.
+ The MMC Card frequency (SDMMC_CK) is computed as follows:
+
+ SDMMC_CK = SDMMCCLK / (2 * ClockDiv)
+
+ In initialization mode and according to the MMC Card standard,
+ make sure that the SDMMC_CK frequency doesn't exceed 400KHz.
+
+ This phase of initialization is done through SDMMC_Init() and
+ SDMMC_PowerState_ON() SDMMC low level APIs.
+
+ (#) Initialize the MMC card. The API used is HAL_MMC_InitCard().
+ This phase allows the card initialization and identification
+ and check the MMC Card type (Standard Capacity or High Capacity)
+ The initialization flow is compatible with MMC standard.
+
+ This API (HAL_MMC_InitCard()) could be used also to reinitialize the card in case
+ of plug-off plug-in.
+
+ (#) Configure the MMC Card Data transfer frequency. By Default, the card transfer
+ frequency by adjusting the "ClockDiv" field.
+ In transfer mode and according to the MMC Card standard, make sure that the
+ SDMMC_CK frequency doesn't exceed 25MHz and 100MHz in High-speed mode switch.
+
+ (#) Select the corresponding MMC Card according to the address read with the step 2.
+
+ (#) Configure the MMC Card in wide bus mode: 4-bits data.
+
+ *** MMC Card Read operation ***
+ ==============================
+ [..]
+ (+) You can read from MMC card in polling mode by using function HAL_MMC_ReadBlocks().
+ This function support only 512-bytes block length (the block size should be
+ chosen as 512 bytes).
+ You can choose either one block read operation or multiple block read operation
+ by adjusting the "NumberOfBlocks" parameter.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_MMC_GetCardState() function for MMC card state.
+
+ (+) You can read from MMC card in DMA mode by using function HAL_MMC_ReadBlocks_DMA().
+ This function support only 512-bytes block length (the block size should be
+ chosen as 512 bytes).
+ You can choose either one block read operation or multiple block read operation
+ by adjusting the "NumberOfBlocks" parameter.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_MMC_GetCardState() function for MMC card state.
+ You could also check the DMA transfer process through the MMC Rx interrupt event.
+
+ (+) You can read from MMC card in Interrupt mode by using function HAL_MMC_ReadBlocks_IT().
+ This function allows the read of 512 bytes blocks.
+ You can choose either one block read operation or multiple block read operation
+ by adjusting the "NumberOfBlocks" parameter.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_MMC_GetCardState() function for MMC card state.
+ You could also check the IT transfer process through the MMC Rx interrupt event.
+
+ *** MMC Card Write operation ***
+ ===============================
+ [..]
+ (+) You can write to MMC card in polling mode by using function HAL_MMC_WriteBlocks().
+ This function support only 512-bytes block length (the block size should be
+ chosen as 512 bytes).
+ You can choose either one block read operation or multiple block read operation
+ by adjusting the "NumberOfBlocks" parameter.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_MMC_GetCardState() function for MMC card state.
+
+ (+) You can write to MMC card in DMA mode by using function HAL_MMC_WriteBlocks_DMA().
+ This function support only 512-bytes block length (the block size should be
+ chosen as 512 byte).
+ You can choose either one block read operation or multiple block read operation
+ by adjusting the "NumberOfBlocks" parameter.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_MMC_GetCardState() function for MMC card state.
+ You could also check the DMA transfer process through the MMC Tx interrupt event.
+
+ (+) You can write to MMC card in Interrupt mode by using function HAL_MMC_WriteBlocks_IT().
+ This function allows the read of 512 bytes blocks.
+ You can choose either one block read operation or multiple block read operation
+ by adjusting the "NumberOfBlocks" parameter.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_MMC_GetCardState() function for MMC card state.
+ You could also check the IT transfer process through the MMC Tx interrupt event.
+
+ *** MMC card information ***
+ ===========================
+ [..]
+ (+) To get MMC card information, you can use the function HAL_MMC_GetCardInfo().
+ It returns useful information about the MMC card such as block size, card type,
+ block number ...
+
+ *** MMC card CSD register ***
+ ============================
+ [..]
+ (+) The HAL_MMC_GetCardCSD() API allows to get the parameters of the CSD register.
+ Some of the CSD parameters are useful for card initialization and identification.
+
+ *** MMC card CID register ***
+ ============================
+ [..]
+ (+) The HAL_MMC_GetCardCID() API allows to get the parameters of the CID register.
+ Some of the CID parameters are useful for card initialization and identification.
+
+ *** MMC HAL driver macros list ***
+ ==================================
+ [..]
+ Below the list of most used macros in MMC HAL driver.
+
+ (+) __HAL_MMC_ENABLE_IT: Enable the MMC device interrupt
+ (+) __HAL_MMC_DISABLE_IT: Disable the MMC device interrupt
+ (+) __HAL_MMC_GET_FLAG:Check whether the specified MMC flag is set or not
+ (+) __HAL_MMC_CLEAR_FLAG: Clear the MMC's pending flags
+
+ [..]
+ (@) You can refer to the MMC HAL driver header file for more useful macros
+
+ *** Callback registration ***
+ =============================================
+ [..]
+ The compilation define USE_HAL_MMC_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ Use Functions @ref HAL_MMC_RegisterCallback() to register a user callback,
+ it allows to register following callbacks:
+ (+) TxCpltCallback : callback when a transmission transfer is completed.
+ (+) RxCpltCallback : callback when a reception transfer is completed.
+ (+) ErrorCallback : callback when error occurs.
+ (+) AbortCpltCallback : callback when abort is completed.
+ (+) Read_DMALnkLstBufCpltCallback : callback when the DMA reception of linked list node buffer is completed.
+ (+) Write_DMALnkLstBufCpltCallback : callback when the DMA transmission of linked list node buffer is completed.
+ (+) MspInitCallback : MMC MspInit.
+ (+) MspDeInitCallback : MMC MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_MMC_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function. It allows to reset following callbacks:
+ (+) TxCpltCallback : callback when a transmission transfer is completed.
+ (+) RxCpltCallback : callback when a reception transfer is completed.
+ (+) ErrorCallback : callback when error occurs.
+ (+) AbortCpltCallback : callback when abort is completed.
+ (+) Read_DMADblBuf0CpltCallback : callback when the DMA reception of first buffer is completed.
+ (+) Read_DMADblBuf1CpltCallback : callback when the DMA reception of second buffer is completed.
+ (+) Write_DMADblBuf0CpltCallback : callback when the DMA transmission of first buffer is completed.
+ (+) Write_DMADblBuf1CpltCallback : callback when the DMA transmission of second buffer is completed.
+ (+) MspInitCallback : MMC MspInit.
+ (+) MspDeInitCallback : MMC MspDeInit.
+ This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+ By default, after the @ref HAL_MMC_Init and if the state is HAL_MMC_STATE_RESET
+ all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_MMC_Init
+ and @ref HAL_MMC_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_MMC_Init and @ref HAL_MMC_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_MMC_RegisterCallback before calling @ref HAL_MMC_DeInit
+ or @ref HAL_MMC_Init function.
+
+ When The compilation define USE_HAL_MMC_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
+ @endverbatim
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup MMC MMC
+ * @brief MMC HAL module driver
+ * @{
+ */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup MMC_Private_Defines
+ * @{
+ */
+#if defined (VDD_VALUE) && (VDD_VALUE <= 1950U)
+#define MMC_VOLTAGE_RANGE MMC_LOW_VOLTAGE_RANGE
+
+#define MMC_EXT_CSD_PWR_CL_26_INDEX 201
+#define MMC_EXT_CSD_PWR_CL_52_INDEX 200
+#define MMC_EXT_CSD_PWR_CL_DDR_52_INDEX 238
+
+#define MMC_EXT_CSD_PWR_CL_26_POS 8
+#define MMC_EXT_CSD_PWR_CL_52_POS 0
+#define MMC_EXT_CSD_PWR_CL_DDR_52_POS 16
+#else
+#define MMC_VOLTAGE_RANGE MMC_HIGH_VOLTAGE_RANGE
+
+#define MMC_EXT_CSD_PWR_CL_26_INDEX 203
+#define MMC_EXT_CSD_PWR_CL_52_INDEX 202
+#define MMC_EXT_CSD_PWR_CL_DDR_52_INDEX 239
+
+#define MMC_EXT_CSD_PWR_CL_26_POS 24
+#define MMC_EXT_CSD_PWR_CL_52_POS 16
+#define MMC_EXT_CSD_PWR_CL_DDR_52_POS 24
+#endif /* (VDD_VALUE) && (VDD_VALUE <= 1950U)*/
+
+/* Frequencies used in the driver for clock divider calculation */
+#define MMC_INIT_FREQ 400000U /* Initialization phase : 400 kHz max */
+#define MMC_HIGH_SPEED_FREQ 52000000U /* High speed phase : 52 MHz max */
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup MMC_Private_Functions MMC Private Functions
+ * @{
+ */
+static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc);
+static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc);
+static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus);
+static void MMC_PowerOFF(MMC_HandleTypeDef *hmmc);
+static void MMC_Write_IT(MMC_HandleTypeDef *hmmc);
+static void MMC_Read_IT(MMC_HandleTypeDef *hmmc);
+static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state);
+static uint32_t MMC_DDR_Mode(MMC_HandleTypeDef *hmmc, FunctionalState state);
+static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex,
+ uint32_t Timeout);
+static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide, uint32_t Speed);
+
+/**
+ * @}
+ */
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup MMC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup MMC_Exported_Functions_Group1
+ * @brief Initialization and de-initialization functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to initialize/de-initialize the MMC
+ card device to be ready for use.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the MMC according to the specified parameters in the
+ MMC_HandleTypeDef and create the associated handle.
+ * @param hmmc: Pointer to the MMC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc)
+{
+ /* Check the MMC handle allocation */
+ if (hmmc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SDMMC_ALL_INSTANCE(hmmc->Instance));
+ assert_param(IS_SDMMC_CLOCK_EDGE(hmmc->Init.ClockEdge));
+ assert_param(IS_SDMMC_CLOCK_POWER_SAVE(hmmc->Init.ClockPowerSave));
+ assert_param(IS_SDMMC_BUS_WIDE(hmmc->Init.BusWide));
+ assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hmmc->Init.HardwareFlowControl));
+ assert_param(IS_SDMMC_CLKDIV(hmmc->Init.ClockDiv));
+
+ if (hmmc->State == HAL_MMC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hmmc->Lock = HAL_UNLOCKED;
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+ /* Reset Callback pointers in HAL_MMC_STATE_RESET only */
+ hmmc->TxCpltCallback = HAL_MMC_TxCpltCallback;
+ hmmc->RxCpltCallback = HAL_MMC_RxCpltCallback;
+ hmmc->ErrorCallback = HAL_MMC_ErrorCallback;
+ hmmc->AbortCpltCallback = HAL_MMC_AbortCallback;
+ hmmc->Read_DMALnkLstBufCpltCallback = HAL_MMCEx_Read_DMALnkLstBufCpltCallback;
+ hmmc->Write_DMALnkLstBufCpltCallback = HAL_MMCEx_Write_DMALnkLstBufCpltCallback;
+
+ if (hmmc->MspInitCallback == NULL)
+ {
+ hmmc->MspInitCallback = HAL_MMC_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hmmc->MspInitCallback(hmmc);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ HAL_MMC_MspInit(hmmc);
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+ }
+
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Initialize the Card parameters */
+ if (HAL_MMC_InitCard(hmmc) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Initialize the error code */
+ hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Initialize the MMC operation */
+ hmmc->Context = MMC_CONTEXT_NONE;
+
+ /* Initialize the MMC state */
+ hmmc->State = HAL_MMC_STATE_READY;
+
+ /* Configure bus width */
+ if (hmmc->Init.BusWide != SDMMC_BUS_WIDE_1B)
+ {
+ if (HAL_MMC_ConfigWideBusOperation(hmmc, hmmc->Init.BusWide) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the MMC Card.
+ * @param hmmc: Pointer to MMC handle
+ * @note This function initializes the MMC card. It could be used when a card
+ re-initialization is needed.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc)
+{
+ uint32_t errorstate;
+ MMC_InitTypeDef Init;
+ uint32_t sdmmc_clk;
+
+ /* Default SDMMC peripheral configuration for MMC card initialization */
+ Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING;
+ Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE;
+ Init.BusWide = SDMMC_BUS_WIDE_1B;
+ Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
+
+ /* Init Clock should be less or equal to 400Khz*/
+ sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC);
+ if (sdmmc_clk == 0U)
+ {
+ hmmc->State = HAL_MMC_STATE_READY;
+ hmmc->ErrorCode = SDMMC_ERROR_INVALID_PARAMETER;
+ return HAL_ERROR;
+ }
+ Init.ClockDiv = sdmmc_clk / (2U * MMC_INIT_FREQ);
+
+#if (USE_SD_TRANSCEIVER != 0U)
+ Init.TranceiverPresent = SDMMC_TRANSCEIVER_NOT_PRESENT;
+#endif /* USE_SD_TRANSCEIVER */
+
+ /* Initialize SDMMC peripheral interface with default configuration */
+ (void)SDMMC_Init(hmmc->Instance, Init);
+
+ /* Set Power State to ON */
+ (void)SDMMC_PowerState_ON(hmmc->Instance);
+
+ /* wait 74 Cycles: required power up waiting time before starting
+ the MMC initialization sequence */
+ sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv);
+ HAL_Delay(1U + (74U * 1000U / (sdmmc_clk)));
+
+ /* Identify card operating voltage */
+ errorstate = MMC_PowerON(hmmc);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->State = HAL_MMC_STATE_READY;
+ hmmc->ErrorCode |= errorstate;
+ return HAL_ERROR;
+ }
+
+ /* Card initialization */
+ errorstate = MMC_InitCard(hmmc);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->State = HAL_MMC_STATE_READY;
+ hmmc->ErrorCode |= errorstate;
+ return HAL_ERROR;
+ }
+
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief De-Initializes the MMC card.
+ * @param hmmc: Pointer to MMC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc)
+{
+ /* Check the MMC handle allocation */
+ if (hmmc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SDMMC_ALL_INSTANCE(hmmc->Instance));
+
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Set MMC power state to off */
+ MMC_PowerOFF(hmmc);
+
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+ if (hmmc->MspDeInitCallback == NULL)
+ {
+ hmmc->MspDeInitCallback = HAL_MMC_MspDeInit;
+ }
+
+ /* DeInit the low level hardware */
+ hmmc->MspDeInitCallback(hmmc);
+#else
+ /* De-Initialize the MSP layer */
+ HAL_MMC_MspDeInit(hmmc);
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+
+ hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+ hmmc->State = HAL_MMC_STATE_RESET;
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Initializes the MMC MSP.
+ * @param hmmc: Pointer to MMC handle
+ * @retval None
+ */
+__weak void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hmmc);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_MMC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief De-Initialize MMC MSP.
+ * @param hmmc: Pointer to MMC handle
+ * @retval None
+ */
+__weak void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hmmc);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_MMC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup MMC_Exported_Functions_Group2
+ * @brief Data transfer functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the data
+ transfer from/to MMC card.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Reads block(s) from a specified address in a card. The Data transfer
+ * is managed by polling mode.
+ * @note This API should be followed by a check on the card state through
+ * HAL_MMC_GetCardState().
+ * @param hmmc: Pointer to MMC handle
+ * @param pData: pointer to the buffer that will contain the received data
+ * @param BlockAdd: Block Address from where data is to be read
+ * @param NumberOfBlocks: Number of MMC blocks to read
+ * @param Timeout: Specify timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks, uint32_t Timeout)
+{
+ SDMMC_DataInitTypeDef config;
+ uint32_t errorstate;
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t count;
+ uint32_t data;
+ uint32_t dataremaining;
+ uint32_t add = BlockAdd;
+ uint8_t *tempbuff = pData;
+
+ if (NULL == pData)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if (hmmc->State == HAL_MMC_STATE_READY)
+ {
+ hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+
+ if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
+ if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+ {
+ if ((NumberOfBlocks % 8U) != 0U)
+ {
+ /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR;
+ return HAL_ERROR;
+ }
+
+ if ((BlockAdd % 8U) != 0U)
+ {
+ /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
+ return HAL_ERROR;
+ }
+ }
+
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Initialize data control register */
+ hmmc->Instance->DCTRL = 0U;
+
+ if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
+ {
+ add *= 512U;
+ }
+
+ /* Configure the MMC DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE;
+ config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
+ config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDMMC_DPSM_DISABLE;
+ (void)SDMMC_ConfigData(hmmc->Instance, &config);
+ __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
+
+ /* Read block(s) in polling mode */
+ if (NumberOfBlocks > 1U)
+ {
+ hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK;
+
+ /* Read Multi Block command */
+ errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add);
+ }
+ else
+ {
+ hmmc->Context = MMC_CONTEXT_READ_SINGLE_BLOCK;
+
+ /* Read Single Block command */
+ errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add);
+ }
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Poll on SDMMC flags */
+ dataremaining = config.DataLength;
+ while (!__HAL_MMC_GET_FLAG(hmmc,
+ SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+ {
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U))
+ {
+ /* Read data from SDMMC Rx FIFO */
+ for (count = 0U; count < 8U; count++)
+ {
+ data = SDMMC_ReadFIFO(hmmc->Instance);
+ *tempbuff = (uint8_t)(data & 0xFFU);
+ tempbuff++;
+ *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
+ tempbuff++;
+ *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
+ tempbuff++;
+ *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
+ tempbuff++;
+ }
+ dataremaining -= 32U;
+ }
+
+ if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_TIMEOUT;
+ }
+ }
+ __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
+
+ /* Send stop transmission command in case of multiblock read */
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
+ {
+ /* Send stop transmission command */
+ errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ }
+
+ /* Get error state */
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+
+ hmmc->State = HAL_MMC_STATE_READY;
+
+ return HAL_OK;
+ }
+ else
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY;
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Allows to write block(s) to a specified address in a card. The Data
+ * transfer is managed by polling mode.
+ * @note This API should be followed by a check on the card state through
+ * HAL_MMC_GetCardState().
+ * @param hmmc: Pointer to MMC handle
+ * @param pData: pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd: Block Address where data will be written
+ * @param NumberOfBlocks: Number of MMC blocks to write
+ * @param Timeout: Specify timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks, uint32_t Timeout)
+{
+ SDMMC_DataInitTypeDef config;
+ uint32_t errorstate;
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t count;
+ uint32_t data;
+ uint32_t dataremaining;
+ uint32_t add = BlockAdd;
+ uint8_t *tempbuff = pData;
+
+ if (NULL == pData)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if (hmmc->State == HAL_MMC_STATE_READY)
+ {
+ hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+
+ if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
+ if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+ {
+ if ((NumberOfBlocks % 8U) != 0U)
+ {
+ /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR;
+ return HAL_ERROR;
+ }
+
+ if ((BlockAdd % 8U) != 0U)
+ {
+ /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
+ return HAL_ERROR;
+ }
+ }
+
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Initialize data control register */
+ hmmc->Instance->DCTRL = 0U;
+
+ if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
+ {
+ add *= 512U;
+ }
+
+ /* Configure the MMC DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE;
+ config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;
+ config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDMMC_DPSM_DISABLE;
+ (void)SDMMC_ConfigData(hmmc->Instance, &config);
+ __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
+
+ /* Write Blocks in Polling mode */
+ if (NumberOfBlocks > 1U)
+ {
+ hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK;
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add);
+ }
+ else
+ {
+ hmmc->Context = MMC_CONTEXT_WRITE_SINGLE_BLOCK;
+
+ /* Write Single Block command */
+ errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add);
+ }
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Write block(s) in polling mode */
+ dataremaining = config.DataLength;
+ while (!__HAL_MMC_GET_FLAG(hmmc,
+ SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+ {
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U))
+ {
+ /* Write data to SDMMC Tx FIFO */
+ for (count = 0U; count < 8U; count++)
+ {
+ data = (uint32_t)(*tempbuff);
+ tempbuff++;
+ data |= ((uint32_t)(*tempbuff) << 8U);
+ tempbuff++;
+ data |= ((uint32_t)(*tempbuff) << 16U);
+ tempbuff++;
+ data |= ((uint32_t)(*tempbuff) << 24U);
+ tempbuff++;
+ (void)SDMMC_WriteFIFO(hmmc->Instance, &data);
+ }
+ dataremaining -= 32U;
+ }
+
+ if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_TIMEOUT;
+ }
+ }
+ __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
+
+ /* Send stop transmission command in case of multiblock write */
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
+ {
+ /* Send stop transmission command */
+ errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ }
+
+ /* Get error state */
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+
+ hmmc->State = HAL_MMC_STATE_READY;
+
+ return HAL_OK;
+ }
+ else
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY;
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Reads block(s) from a specified address in a card. The Data transfer
+ * is managed in interrupt mode.
+ * @note This API should be followed by a check on the card state through
+ * HAL_MMC_GetCardState().
+ * @note You could also check the IT transfer process through the MMC Rx
+ * interrupt event.
+ * @param hmmc: Pointer to MMC handle
+ * @param pData: Pointer to the buffer that will contain the received data
+ * @param BlockAdd: Block Address from where data is to be read
+ * @param NumberOfBlocks: Number of blocks to read.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData,
+ uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+ SDMMC_DataInitTypeDef config;
+ uint32_t errorstate;
+ uint32_t add = BlockAdd;
+
+ if (NULL == pData)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if (hmmc->State == HAL_MMC_STATE_READY)
+ {
+ hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+
+ if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
+ if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+ {
+ if ((NumberOfBlocks % 8U) != 0U)
+ {
+ /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR;
+ return HAL_ERROR;
+ }
+
+ if ((BlockAdd % 8U) != 0U)
+ {
+ /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
+ return HAL_ERROR;
+ }
+ }
+
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Initialize data control register */
+ hmmc->Instance->DCTRL = 0U;
+
+ hmmc->pRxBuffPtr = pData;
+ hmmc->RxXferSize = MMC_BLOCKSIZE * NumberOfBlocks;
+
+ if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
+ {
+ add *= 512U;
+ }
+
+ /* Configure the MMC DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
+ config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
+ config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDMMC_DPSM_DISABLE;
+ (void)SDMMC_ConfigData(hmmc->Instance, &config);
+ __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
+
+ /* Read Blocks in IT mode */
+ if (NumberOfBlocks > 1U)
+ {
+ hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_IT);
+
+ /* Read Multi Block command */
+ errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add);
+ }
+ else
+ {
+ hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_IT);
+
+ /* Read Single Block command */
+ errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add);
+ }
+
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND |
+ SDMMC_FLAG_RXFIFOHF));
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Writes block(s) to a specified address in a card. The Data transfer
+ * is managed in interrupt mode.
+ * @note This API should be followed by a check on the card state through
+ * HAL_MMC_GetCardState().
+ * @note You could also check the IT transfer process through the MMC Tx
+ * interrupt event.
+ * @param hmmc: Pointer to MMC handle
+ * @param pData: Pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd: Block Address where data will be written
+ * @param NumberOfBlocks: Number of blocks to write
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData,
+ uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+ SDMMC_DataInitTypeDef config;
+ uint32_t errorstate;
+ uint32_t add = BlockAdd;
+
+ if (NULL == pData)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if (hmmc->State == HAL_MMC_STATE_READY)
+ {
+ hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+
+ if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
+ if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+ {
+ if ((NumberOfBlocks % 8U) != 0U)
+ {
+ /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR;
+ return HAL_ERROR;
+ }
+
+ if ((BlockAdd % 8U) != 0U)
+ {
+ /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
+ return HAL_ERROR;
+ }
+ }
+
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Initialize data control register */
+ hmmc->Instance->DCTRL = 0U;
+
+ hmmc->pTxBuffPtr = pData;
+ hmmc->TxXferSize = MMC_BLOCKSIZE * NumberOfBlocks;
+
+ if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
+ {
+ add *= 512U;
+ }
+
+ /* Configure the MMC DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
+ config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;
+ config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDMMC_DPSM_DISABLE;
+ (void)SDMMC_ConfigData(hmmc->Instance, &config);
+
+ __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
+
+ /* Write Blocks in Polling mode */
+ if (NumberOfBlocks > 1U)
+ {
+ hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_IT);
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add);
+ }
+ else
+ {
+ hmmc->Context = (MMC_CONTEXT_WRITE_SINGLE_BLOCK | MMC_CONTEXT_IT);
+
+ /* Write Single Block command */
+ errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add);
+ }
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Enable transfer interrupts */
+ __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND |
+ SDMMC_FLAG_TXFIFOHE));
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Reads block(s) from a specified address in a card. The Data transfer
+ * is managed by DMA mode.
+ * @note This API should be followed by a check on the card state through
+ * HAL_MMC_GetCardState().
+ * @note You could also check the DMA transfer process through the MMC Rx
+ * interrupt event.
+ * @param hmmc: Pointer MMC handle
+ * @param pData: Pointer to the buffer that will contain the received data
+ * @param BlockAdd: Block Address from where data is to be read
+ * @param NumberOfBlocks: Number of blocks to read.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData,
+ uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+ SDMMC_DataInitTypeDef config;
+ uint32_t errorstate;
+ uint32_t add = BlockAdd;
+
+ if (NULL == pData)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if (hmmc->State == HAL_MMC_STATE_READY)
+ {
+ hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
+ if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+ {
+ if ((NumberOfBlocks % 8U) != 0U)
+ {
+ /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR;
+ return HAL_ERROR;
+ }
+
+ if ((BlockAdd % 8U) != 0U)
+ {
+ /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
+ return HAL_ERROR;
+ }
+ }
+
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Initialize data control register */
+ hmmc->Instance->DCTRL = 0U;
+
+ hmmc->pRxBuffPtr = pData;
+ hmmc->RxXferSize = MMC_BLOCKSIZE * NumberOfBlocks;
+
+ if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
+ {
+ add *= 512U;
+ }
+
+ /* Configure the MMC DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
+ config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
+ config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDMMC_DPSM_DISABLE;
+ (void)SDMMC_ConfigData(hmmc->Instance, &config);
+
+ __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
+ hmmc->Instance->IDMABASER = (uint32_t) pData ;
+ hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
+
+ /* Read Blocks in DMA mode */
+ if (NumberOfBlocks > 1U)
+ {
+ hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
+
+ /* Read Multi Block command */
+ errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add);
+ }
+ else
+ {
+ hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_DMA);
+
+ /* Read Single Block command */
+ errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add);
+ }
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode = errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Enable transfer interrupts */
+ __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND));
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Writes block(s) to a specified address in a card. The Data transfer
+ * is managed by DMA mode.
+ * @note This API should be followed by a check on the card state through
+ * HAL_MMC_GetCardState().
+ * @note You could also check the DMA transfer process through the MMC Tx
+ * interrupt event.
+ * @param hmmc: Pointer to MMC handle
+ * @param pData: Pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd: Block Address where data will be written
+ * @param NumberOfBlocks: Number of blocks to write
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData,
+ uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+ SDMMC_DataInitTypeDef config;
+ uint32_t errorstate;
+ uint32_t add = BlockAdd;
+
+ if (NULL == pData)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if (hmmc->State == HAL_MMC_STATE_READY)
+ {
+ hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+
+ if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
+ if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+ {
+ if ((NumberOfBlocks % 8U) != 0U)
+ {
+ /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR;
+ return HAL_ERROR;
+ }
+
+ if ((BlockAdd % 8U) != 0U)
+ {
+ /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
+ return HAL_ERROR;
+ }
+ }
+
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Initialize data control register */
+ hmmc->Instance->DCTRL = 0U;
+
+ hmmc->pTxBuffPtr = pData;
+ hmmc->TxXferSize = MMC_BLOCKSIZE * NumberOfBlocks;
+
+ if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
+ {
+ add *= 512U;
+ }
+
+ /* Configure the MMC DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
+ config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;
+ config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDMMC_DPSM_DISABLE;
+ (void)SDMMC_ConfigData(hmmc->Instance, &config);
+
+ __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
+
+ hmmc->Instance->IDMABASER = (uint32_t) pData ;
+ hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
+
+ /* Write Blocks in Polling mode */
+ if (NumberOfBlocks > 1U)
+ {
+ hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add);
+ }
+ else
+ {
+ hmmc->Context = (MMC_CONTEXT_WRITE_SINGLE_BLOCK | MMC_CONTEXT_DMA);
+
+ /* Write Single Block command */
+ errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add);
+ }
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Enable transfer interrupts */
+ __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND));
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Erases the specified memory area of the given MMC card.
+ * @note This API should be followed by a check on the card state through
+ * HAL_MMC_GetCardState().
+ * @param hmmc: Pointer to MMC handle
+ * @param BlockStartAdd: Start Block address
+ * @param BlockEndAdd: End Block address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
+{
+ uint32_t errorstate;
+ uint32_t start_add = BlockStartAdd;
+ uint32_t end_add = BlockEndAdd;
+
+ if (hmmc->State == HAL_MMC_STATE_READY)
+ {
+ hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+
+ if (end_add < start_add)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if (end_add > (hmmc->MmcCard.LogBlockNbr))
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
+ if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+ {
+ if (((start_add % 8U) != 0U) || ((end_add % 8U) != 0U))
+ {
+ /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
+ return HAL_ERROR;
+ }
+ }
+
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Check if the card command class supports erase command */
+ if (((hmmc->MmcCard.Class) & SDMMC_CCCC_ERASE) == 0U)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ if ((SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_LOCK_UNLOCK_FAILED;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
+ {
+ start_add *= 512U;
+ end_add *= 512U;
+ }
+
+ /* Send CMD35 MMC_ERASE_GRP_START with argument as addr */
+ errorstate = SDMMC_CmdEraseStartAdd(hmmc->Instance, start_add);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Send CMD36 MMC_ERASE_GRP_END with argument as addr */
+ errorstate = SDMMC_CmdEraseEndAdd(hmmc->Instance, end_add);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Send CMD38 ERASE */
+ errorstate = SDMMC_CmdErase(hmmc->Instance, 0UL);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ hmmc->State = HAL_MMC_STATE_READY;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief This function handles MMC card interrupt request.
+ * @param hmmc: Pointer to MMC handle
+ * @retval None
+ */
+void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
+{
+ uint32_t errorstate;
+ uint32_t context = hmmc->Context;
+
+ /* Check for SDMMC interrupt flags */
+ if ((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & MMC_CONTEXT_IT) != 0U))
+ {
+ MMC_Read_IT(hmmc);
+ }
+
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) != RESET)
+ {
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_DATAEND);
+
+ __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+ SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE | \
+ SDMMC_IT_RXFIFOHF);
+
+ __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_IDMABTC);
+ __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
+
+ if ((context & MMC_CONTEXT_DMA) != 0U)
+ {
+ hmmc->Instance->DLEN = 0;
+ hmmc->Instance->DCTRL = 0;
+ hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA ;
+
+ /* Stop Transfer for Write Multi blocks or Read Multi blocks */
+ if (((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+ {
+ errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->ErrorCode |= errorstate;
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+ hmmc->ErrorCallback(hmmc);
+#else
+ HAL_MMC_ErrorCallback(hmmc);
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+
+ hmmc->State = HAL_MMC_STATE_READY;
+ if (((context & MMC_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+ {
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+ hmmc->TxCpltCallback(hmmc);
+#else
+ HAL_MMC_TxCpltCallback(hmmc);
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+ }
+ if (((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
+ {
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+ hmmc->RxCpltCallback(hmmc);
+#else
+ HAL_MMC_RxCpltCallback(hmmc);
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+ }
+ }
+ else if ((context & MMC_CONTEXT_IT) != 0U)
+ {
+ /* Stop Transfer for Write Multi blocks or Read Multi blocks */
+ if (((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+ {
+ errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->ErrorCode |= errorstate;
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+ hmmc->ErrorCallback(hmmc);
+#else
+ HAL_MMC_ErrorCallback(hmmc);
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+
+ hmmc->State = HAL_MMC_STATE_READY;
+ if (((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
+ {
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+ hmmc->RxCpltCallback(hmmc);
+#else
+ HAL_MMC_RxCpltCallback(hmmc);
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+ }
+ else
+ {
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+ hmmc->TxCpltCallback(hmmc);
+#else
+ HAL_MMC_TxCpltCallback(hmmc);
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+
+ else if ((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & MMC_CONTEXT_IT) != 0U))
+ {
+ MMC_Write_IT(hmmc);
+ }
+
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL |
+ SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | SDMMC_FLAG_TXUNDERR) != RESET)
+ {
+ /* Set Error code */
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DCRCFAIL) != RESET)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
+ }
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DTIMEOUT) != RESET)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
+ }
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_RXOVERR) != RESET)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
+ }
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_TXUNDERR) != RESET)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN;
+ }
+
+ /* Clear All flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+
+ /* Disable all interrupts */
+ __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+ SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR);
+
+ __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
+ hmmc->Instance->DCTRL |= SDMMC_DCTRL_FIFORST;
+ hmmc->Instance->CMD |= SDMMC_CMD_CMDSTOP;
+ hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance);
+ hmmc->Instance->CMD &= ~(SDMMC_CMD_CMDSTOP);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_DABORT);
+
+ if ((context & MMC_CONTEXT_IT) != 0U)
+ {
+ /* Set the MMC state to ready to be able to start again the process */
+ hmmc->State = HAL_MMC_STATE_READY;
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+ hmmc->ErrorCallback(hmmc);
+#else
+ HAL_MMC_ErrorCallback(hmmc);
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+ }
+ else if ((context & MMC_CONTEXT_DMA) != 0U)
+ {
+ if (hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
+ {
+ /* Disable Internal DMA */
+ __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_IDMABTC);
+ hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
+
+ /* Set the MMC state to ready to be able to start again the process */
+ hmmc->State = HAL_MMC_STATE_READY;
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+ hmmc->ErrorCallback(hmmc);
+#else
+ HAL_MMC_ErrorCallback(hmmc);
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_IDMABTC) != RESET)
+ {
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_IT_IDMABTC);
+
+ if ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
+ {
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+ hmmc->Write_DMALnkLstBufCpltCallback(hmmc);
+#else
+ HAL_MMCEx_Write_DMALnkLstBufCpltCallback(hmmc);
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+ }
+ else /* MMC_CONTEXT_READ_MULTIPLE_BLOCK */
+ {
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+ hmmc->Read_DMALnkLstBufCpltCallback(hmmc);
+#else
+ HAL_MMCEx_Read_DMALnkLstBufCpltCallback(hmmc);
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+ }
+ }
+
+ else
+ {
+ /* Nothing to do */
+ }
+}
+
+/**
+ * @brief return the MMC state
+ * @param hmmc: Pointer to mmc handle
+ * @retval HAL state
+ */
+HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc)
+{
+ return hmmc->State;
+}
+
+/**
+ * @brief Return the MMC error code
+ * @param hmmc : Pointer to a MMC_HandleTypeDef structure that contains
+ * the configuration information.
+ * @retval MMC Error Code
+ */
+uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc)
+{
+ return hmmc->ErrorCode;
+}
+
+/**
+ * @brief Tx Transfer completed callbacks
+ * @param hmmc: Pointer to MMC handle
+ * @retval None
+ */
+__weak void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hmmc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_MMC_TxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callbacks
+ * @param hmmc: Pointer MMC handle
+ * @retval None
+ */
+__weak void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hmmc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_MMC_RxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief MMC error callbacks
+ * @param hmmc: Pointer MMC handle
+ * @retval None
+ */
+__weak void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hmmc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_MMC_ErrorCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief MMC Abort callbacks
+ * @param hmmc: Pointer MMC handle
+ * @retval None
+ */
+__weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hmmc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_MMC_AbortCallback can be implemented in the user file
+ */
+}
+
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+/**
+ * @brief Register a User MMC Callback
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hmmc : MMC handle
+ * @param CallbackId : ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_MMC_TX_CPLT_CB_ID MMC Tx Complete Callback ID
+ * @arg @ref HAL_MMC_RX_CPLT_CB_ID MMC Rx Complete Callback ID
+ * @arg @ref HAL_MMC_ERROR_CB_ID MMC Error Callback ID
+ * @arg @ref HAL_MMC_ABORT_CB_ID MMC Abort Callback ID
+ * @arg @ref HAL_MMC_READ_DMA_LNKLST_BUF_CPLT_CB_ID MMC DMA Rx Linked List Node buffer Callback ID
+ * @arg @ref HAL_MMC_WRITE_DMA_LNKLST_BUF_CPLT_CB_ID MMC DMA Tx Linked List Node buffer Callback ID
+ * @arg @ref HAL_MMC_MSP_INIT_CB_ID MMC MspInit Callback ID
+ * @arg @ref HAL_MMC_MSP_DEINIT_CB_ID MMC MspDeInit Callback ID
+ * @param pCallback : pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId,
+ pMMC_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hmmc);
+
+ if (hmmc->State == HAL_MMC_STATE_READY)
+ {
+ switch (CallbackId)
+ {
+ case HAL_MMC_TX_CPLT_CB_ID :
+ hmmc->TxCpltCallback = pCallback;
+ break;
+ case HAL_MMC_RX_CPLT_CB_ID :
+ hmmc->RxCpltCallback = pCallback;
+ break;
+ case HAL_MMC_ERROR_CB_ID :
+ hmmc->ErrorCallback = pCallback;
+ break;
+ case HAL_MMC_ABORT_CB_ID :
+ hmmc->AbortCpltCallback = pCallback;
+ break;
+ case HAL_MMC_READ_DMA_LNKLST_BUF_CPLT_CB_ID :
+ hmmc->Read_DMALnkLstBufCpltCallback = pCallback;
+ break;
+ case HAL_MMC_WRITE_DMA_LNKLST_BUF_CPLT_CB_ID :
+ hmmc->Write_DMALnkLstBufCpltCallback = pCallback;
+ break;
+ case HAL_MMC_MSP_INIT_CB_ID :
+ hmmc->MspInitCallback = pCallback;
+ break;
+ case HAL_MMC_MSP_DEINIT_CB_ID :
+ hmmc->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* Update the error code */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hmmc->State == HAL_MMC_STATE_RESET)
+ {
+ switch (CallbackId)
+ {
+ case HAL_MMC_MSP_INIT_CB_ID :
+ hmmc->MspInitCallback = pCallback;
+ break;
+ case HAL_MMC_MSP_DEINIT_CB_ID :
+ hmmc->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* Update the error code */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hmmc);
+ return status;
+}
+
+/**
+ * @brief Unregister a User MMC Callback
+ * MMC Callback is redirected to the weak (surcharged) predefined callback
+ * @param hmmc : MMC handle
+ * @param CallbackId : ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_MMC_TX_CPLT_CB_ID MMC Tx Complete Callback ID
+ * @arg @ref HAL_MMC_RX_CPLT_CB_ID MMC Rx Complete Callback ID
+ * @arg @ref HAL_MMC_ERROR_CB_ID MMC Error Callback ID
+ * @arg @ref HAL_MMC_ABORT_CB_ID MMC Abort Callback ID
+ * @arg @ref HAL_MMC_READ_DMA_LNKLST_BUF_CPLT_CB_ID MMC DMA Rx Linked List Node buffer Callback ID
+ * @arg @ref HAL_MMC_WRITE_DMA_LNKLST_BUF_CPLT_CB_ID MMC DMA Tx Linked List Node buffer Callback ID
+ * @arg @ref HAL_MMC_MSP_INIT_CB_ID MMC MspInit Callback ID
+ * @arg @ref HAL_MMC_MSP_DEINIT_CB_ID MMC MspDeInit Callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hmmc);
+
+ if (hmmc->State == HAL_MMC_STATE_READY)
+ {
+ switch (CallbackId)
+ {
+ case HAL_MMC_TX_CPLT_CB_ID :
+ hmmc->TxCpltCallback = HAL_MMC_TxCpltCallback;
+ break;
+ case HAL_MMC_RX_CPLT_CB_ID :
+ hmmc->RxCpltCallback = HAL_MMC_RxCpltCallback;
+ break;
+ case HAL_MMC_ERROR_CB_ID :
+ hmmc->ErrorCallback = HAL_MMC_ErrorCallback;
+ break;
+ case HAL_MMC_ABORT_CB_ID :
+ hmmc->AbortCpltCallback = HAL_MMC_AbortCallback;
+ break;
+ case HAL_MMC_READ_DMA_LNKLST_BUF_CPLT_CB_ID :
+ hmmc->Read_DMALnkLstBufCpltCallback = HAL_MMCEx_Read_DMALnkLstBufCpltCallback;
+ break;
+ case HAL_MMC_WRITE_DMA_LNKLST_BUF_CPLT_CB_ID :
+ hmmc->Write_DMALnkLstBufCpltCallback = HAL_MMCEx_Write_DMALnkLstBufCpltCallback;
+ break;
+ case HAL_MMC_MSP_INIT_CB_ID :
+ hmmc->MspInitCallback = HAL_MMC_MspInit;
+ break;
+ case HAL_MMC_MSP_DEINIT_CB_ID :
+ hmmc->MspDeInitCallback = HAL_MMC_MspDeInit;
+ break;
+ default :
+ /* Update the error code */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hmmc->State == HAL_MMC_STATE_RESET)
+ {
+ switch (CallbackId)
+ {
+ case HAL_MMC_MSP_INIT_CB_ID :
+ hmmc->MspInitCallback = HAL_MMC_MspInit;
+ break;
+ case HAL_MMC_MSP_DEINIT_CB_ID :
+ hmmc->MspDeInitCallback = HAL_MMC_MspDeInit;
+ break;
+ default :
+ /* Update the error code */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hmmc);
+ return status;
+}
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @addtogroup MMC_Exported_Functions_Group3
+ * @brief management functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the MMC card
+ operations and get the related information
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns information the information of the card which are stored on
+ * the CID register.
+ * @param hmmc: Pointer to MMC handle
+ * @param pCID: Pointer to a HAL_MMC_CIDTypedef structure that
+ * contains all CID register parameters
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID)
+{
+ pCID->ManufacturerID = (uint8_t)((hmmc->CID[0] & 0xFF000000U) >> 24U);
+
+ pCID->OEM_AppliID = (uint16_t)((hmmc->CID[0] & 0x00FFFF00U) >> 8U);
+
+ pCID->ProdName1 = (((hmmc->CID[0] & 0x000000FFU) << 24U) | ((hmmc->CID[1] & 0xFFFFFF00U) >> 8U));
+
+ pCID->ProdName2 = (uint8_t)(hmmc->CID[1] & 0x000000FFU);
+
+ pCID->ProdRev = (uint8_t)((hmmc->CID[2] & 0xFF000000U) >> 24U);
+
+ pCID->ProdSN = (((hmmc->CID[2] & 0x00FFFFFFU) << 8U) | ((hmmc->CID[3] & 0xFF000000U) >> 24U));
+
+ pCID->Reserved1 = (uint8_t)((hmmc->CID[3] & 0x00F00000U) >> 20U);
+
+ pCID->ManufactDate = (uint16_t)((hmmc->CID[3] & 0x000FFF00U) >> 8U);
+
+ pCID->CID_CRC = (uint8_t)((hmmc->CID[3] & 0x000000FEU) >> 1U);
+
+ pCID->Reserved2 = 1U;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Returns information the information of the card which are stored on
+ * the CSD register.
+ * @param hmmc: Pointer to MMC handle
+ * @param pCSD: Pointer to a HAL_MMC_CardCSDTypeDef structure that
+ * contains all CSD register parameters
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD)
+{
+ uint32_t block_nbr = 0;
+
+ pCSD->CSDStruct = (uint8_t)((hmmc->CSD[0] & 0xC0000000U) >> 30U);
+
+ pCSD->SysSpecVersion = (uint8_t)((hmmc->CSD[0] & 0x3C000000U) >> 26U);
+
+ pCSD->Reserved1 = (uint8_t)((hmmc->CSD[0] & 0x03000000U) >> 24U);
+
+ pCSD->TAAC = (uint8_t)((hmmc->CSD[0] & 0x00FF0000U) >> 16U);
+
+ pCSD->NSAC = (uint8_t)((hmmc->CSD[0] & 0x0000FF00U) >> 8U);
+
+ pCSD->MaxBusClkFrec = (uint8_t)(hmmc->CSD[0] & 0x000000FFU);
+
+ pCSD->CardComdClasses = (uint16_t)((hmmc->CSD[1] & 0xFFF00000U) >> 20U);
+
+ pCSD->RdBlockLen = (uint8_t)((hmmc->CSD[1] & 0x000F0000U) >> 16U);
+
+ pCSD->PartBlockRead = (uint8_t)((hmmc->CSD[1] & 0x00008000U) >> 15U);
+
+ pCSD->WrBlockMisalign = (uint8_t)((hmmc->CSD[1] & 0x00004000U) >> 14U);
+
+ pCSD->RdBlockMisalign = (uint8_t)((hmmc->CSD[1] & 0x00002000U) >> 13U);
+
+ pCSD->DSRImpl = (uint8_t)((hmmc->CSD[1] & 0x00001000U) >> 12U);
+
+ pCSD->Reserved2 = 0U; /*!< Reserved */
+
+ if (MMC_ReadExtCSD(hmmc, &block_nbr, 212, 0x0FFFFFFFU) != HAL_OK) /* Field SEC_COUNT [215:212] */
+ {
+ return HAL_ERROR;
+ }
+
+ if (hmmc->MmcCard.CardType == MMC_LOW_CAPACITY_CARD)
+ {
+ pCSD->DeviceSize = (((hmmc->CSD[1] & 0x000003FFU) << 2U) | ((hmmc->CSD[2] & 0xC0000000U) >> 30U));
+
+ pCSD->MaxRdCurrentVDDMin = (uint8_t)((hmmc->CSD[2] & 0x38000000U) >> 27U);
+
+ pCSD->MaxRdCurrentVDDMax = (uint8_t)((hmmc->CSD[2] & 0x07000000U) >> 24U);
+
+ pCSD->MaxWrCurrentVDDMin = (uint8_t)((hmmc->CSD[2] & 0x00E00000U) >> 21U);
+
+ pCSD->MaxWrCurrentVDDMax = (uint8_t)((hmmc->CSD[2] & 0x001C0000U) >> 18U);
+
+ pCSD->DeviceSizeMul = (uint8_t)((hmmc->CSD[2] & 0x00038000U) >> 15U);
+
+ hmmc->MmcCard.BlockNbr = (pCSD->DeviceSize + 1U) ;
+ hmmc->MmcCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U));
+ hmmc->MmcCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU));
+
+ hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / 512U);
+ hmmc->MmcCard.LogBlockSize = 512U;
+ }
+ else if (hmmc->MmcCard.CardType == MMC_HIGH_CAPACITY_CARD)
+ {
+ hmmc->MmcCard.BlockNbr = block_nbr;
+ hmmc->MmcCard.LogBlockNbr = hmmc->MmcCard.BlockNbr;
+ hmmc->MmcCard.BlockSize = 512U;
+ hmmc->MmcCard.LogBlockSize = hmmc->MmcCard.BlockSize;
+ }
+ else
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_UNSUPPORTED_FEATURE;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ pCSD->EraseGrSize = (uint8_t)((hmmc->CSD[2] & 0x00004000U) >> 14U);
+
+ pCSD->EraseGrMul = (uint8_t)((hmmc->CSD[2] & 0x00003F80U) >> 7U);
+
+ pCSD->WrProtectGrSize = (uint8_t)(hmmc->CSD[2] & 0x0000007FU);
+
+ pCSD->WrProtectGrEnable = (uint8_t)((hmmc->CSD[3] & 0x80000000U) >> 31U);
+
+ pCSD->ManDeflECC = (uint8_t)((hmmc->CSD[3] & 0x60000000U) >> 29U);
+
+ pCSD->WrSpeedFact = (uint8_t)((hmmc->CSD[3] & 0x1C000000U) >> 26U);
+
+ pCSD->MaxWrBlockLen = (uint8_t)((hmmc->CSD[3] & 0x03C00000U) >> 22U);
+
+ pCSD->WriteBlockPaPartial = (uint8_t)((hmmc->CSD[3] & 0x00200000U) >> 21U);
+
+ pCSD->Reserved3 = 0;
+
+ pCSD->ContentProtectAppli = (uint8_t)((hmmc->CSD[3] & 0x00010000U) >> 16U);
+
+ pCSD->FileFormatGroup = (uint8_t)((hmmc->CSD[3] & 0x00008000U) >> 15U);
+
+ pCSD->CopyFlag = (uint8_t)((hmmc->CSD[3] & 0x00004000U) >> 14U);
+
+ pCSD->PermWrProtect = (uint8_t)((hmmc->CSD[3] & 0x00002000U) >> 13U);
+
+ pCSD->TempWrProtect = (uint8_t)((hmmc->CSD[3] & 0x00001000U) >> 12U);
+
+ pCSD->FileFormat = (uint8_t)((hmmc->CSD[3] & 0x00000C00U) >> 10U);
+
+ pCSD->ECC = (uint8_t)((hmmc->CSD[3] & 0x00000300U) >> 8U);
+
+ pCSD->CSD_CRC = (uint8_t)((hmmc->CSD[3] & 0x000000FEU) >> 1U);
+
+ pCSD->Reserved4 = 1;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Gets the MMC card info.
+ * @param hmmc: Pointer to MMC handle
+ * @param pCardInfo: Pointer to the HAL_MMC_CardInfoTypeDef structure that
+ * will contain the MMC card status information
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo)
+{
+ pCardInfo->CardType = (uint32_t)(hmmc->MmcCard.CardType);
+ pCardInfo->Class = (uint32_t)(hmmc->MmcCard.Class);
+ pCardInfo->RelCardAdd = (uint32_t)(hmmc->MmcCard.RelCardAdd);
+ pCardInfo->BlockNbr = (uint32_t)(hmmc->MmcCard.BlockNbr);
+ pCardInfo->BlockSize = (uint32_t)(hmmc->MmcCard.BlockSize);
+ pCardInfo->LogBlockNbr = (uint32_t)(hmmc->MmcCard.LogBlockNbr);
+ pCardInfo->LogBlockSize = (uint32_t)(hmmc->MmcCard.LogBlockSize);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Returns information the information of the card which are stored on
+ * the Extended CSD register.
+ * @param hmmc Pointer to MMC handle
+ * @param pExtCSD Pointer to a memory area (512 bytes) that contains all
+ * Extended CSD register parameters
+ * @param Timeout Specify timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtCSD, uint32_t Timeout)
+{
+ SDMMC_DataInitTypeDef config;
+ uint32_t errorstate;
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t count;
+ uint32_t *tmp_buf;
+
+ if (NULL == pExtCSD)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if (hmmc->State == HAL_MMC_STATE_READY)
+ {
+ hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Initialize data control register */
+ hmmc->Instance->DCTRL = 0;
+
+ /* Initiaize the destination pointer */
+ tmp_buf = pExtCSD;
+
+ /* Configure the MMC DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = 512U;
+ config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
+ config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDMMC_DPSM_DISABLE;
+ (void)SDMMC_ConfigData(hmmc->Instance, &config);
+ __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
+
+ /* Send ExtCSD Read command to Card */
+ errorstate = SDMMC_CmdSendEXTCSD(hmmc->Instance, 0);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Poll on SDMMC flags */
+ while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR |
+ SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+ {
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF))
+ {
+ /* Read data from SDMMC Rx FIFO */
+ for (count = 0U; count < 8U; count++)
+ {
+ *tmp_buf = SDMMC_ReadFIFO(hmmc->Instance);
+ tmp_buf++;
+ }
+ }
+
+ if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_TIMEOUT;
+ }
+ }
+
+ __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
+
+ /* Get error state */
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+ hmmc->State = HAL_MMC_STATE_READY;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables wide bus operation for the requested card if supported by
+ * card.
+ * @param hmmc: Pointer to MMC handle
+ * @param WideMode: Specifies the MMC card wide bus mode
+ * This parameter can be one of the following values:
+ * @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer
+ * @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer
+ * @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode)
+{
+ uint32_t count;
+ SDMMC_InitTypeDef Init;
+ uint32_t errorstate;
+ uint32_t response = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_SDMMC_BUS_WIDE(WideMode));
+
+ /* Change State */
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Check and update the power class if needed */
+ if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) != 0U)
+ {
+ if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) != 0U)
+ {
+ errorstate = MMC_PwrClassUpdate(hmmc, WideMode, SDMMC_SPEED_MODE_DDR);
+ }
+ else
+ {
+ errorstate = MMC_PwrClassUpdate(hmmc, WideMode, SDMMC_SPEED_MODE_HIGH);
+ }
+ }
+ else
+ {
+ errorstate = MMC_PwrClassUpdate(hmmc, WideMode, SDMMC_SPEED_MODE_DEFAULT);
+ }
+
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ if (WideMode == SDMMC_BUS_WIDE_8B)
+ {
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U);
+ }
+ else if (WideMode == SDMMC_BUS_WIDE_4B)
+ {
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U);
+ }
+ else if (WideMode == SDMMC_BUS_WIDE_1B)
+ {
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70000U);
+ }
+ else
+ {
+ /* WideMode is not a valid argument*/
+ errorstate = HAL_MMC_ERROR_PARAM;
+ }
+
+ /* Check for switch error and violation of the trial number of sending CMD 13 */
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+ count = SDMMC_MAX_TRIAL;
+ do
+ {
+ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ break;
+ }
+
+ /* Get command response */
+ response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+ count--;
+ } while (((response & 0x100U) == 0U) && (count != 0U));
+
+ /* Check the status after the switch command execution */
+ if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
+ {
+ /* Check the bit SWITCH_ERROR of the device status */
+ if ((response & 0x80U) != 0U)
+ {
+ errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+ }
+ else
+ {
+ /* Configure the SDMMC peripheral */
+ Init = hmmc->Init;
+ Init.BusWide = WideMode;
+ (void)SDMMC_Init(hmmc->Instance, Init);
+ }
+ }
+ else if (count == 0U)
+ {
+ errorstate = SDMMC_ERROR_TIMEOUT;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ }
+
+ /* Change State */
+ hmmc->State = HAL_MMC_STATE_READY;
+
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the speed bus mode
+ * @param hmmc: Pointer to the MMC handle
+ * @param SpeedMode: Specifies the MMC card speed bus mode
+ * This parameter can be one of the following values:
+ * @arg SDMMC_SPEED_MODE_AUTO: Max speed mode supported by the card
+ * @arg SDMMC_SPEED_MODE_DEFAULT: Default Speed (MMC @ 26MHz)
+ * @arg SDMMC_SPEED_MODE_HIGH: High Speed (MMC @ 52 MHz)
+ * @arg SDMMC_SPEED_MODE_DDR: High Speed DDR (MMC DDR @ 52 MHz)
+ * @retval HAL status
+ */
+
+HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint32_t SpeedMode)
+{
+ uint32_t tickstart;
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t device_type;
+ uint32_t errorstate;
+
+ /* Check the parameters */
+ assert_param(IS_SDMMC_SPEED_MODE(SpeedMode));
+
+ /* Change State */
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Field DEVICE_TYPE [196 = 49*4] of Extended CSD register */
+ device_type = (hmmc->Ext_CSD[49] & 0x000000FFU);
+
+ switch (SpeedMode)
+ {
+ case SDMMC_SPEED_MODE_AUTO:
+ {
+ if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS) != 0U) && ((device_type & 0x04U) != 0U))
+ {
+ /* High Speed DDR mode allowed */
+ errorstate = MMC_HighSpeed(hmmc, ENABLE);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->ErrorCode |= errorstate;
+ }
+ else
+ {
+ if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_CLKDIV) != 0U)
+ {
+ /* DDR mode not supported with CLKDIV = 0 */
+ errorstate = MMC_DDR_Mode(hmmc, ENABLE);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->ErrorCode |= errorstate;
+ }
+ }
+ }
+ }
+ else if ((device_type & 0x02U) != 0U)
+ {
+ /* High Speed mode allowed */
+ errorstate = MMC_HighSpeed(hmmc, ENABLE);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->ErrorCode |= errorstate;
+ }
+ }
+ else
+ {
+ /* Nothing to do : keep current speed */
+ }
+ break;
+ }
+ case SDMMC_SPEED_MODE_DDR:
+ {
+ if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS) != 0U) && ((device_type & 0x04U) != 0U))
+ {
+ /* High Speed DDR mode allowed */
+ errorstate = MMC_HighSpeed(hmmc, ENABLE);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->ErrorCode |= errorstate;
+ }
+ else
+ {
+ if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_CLKDIV) != 0U)
+ {
+ /* DDR mode not supported with CLKDIV = 0 */
+ errorstate = MMC_DDR_Mode(hmmc, ENABLE);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->ErrorCode |= errorstate;
+ }
+ }
+ }
+ }
+ else
+ {
+ /* High Speed DDR mode not allowed */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_UNSUPPORTED_FEATURE;
+ status = HAL_ERROR;
+ }
+ break;
+ }
+ case SDMMC_SPEED_MODE_HIGH:
+ {
+ if ((device_type & 0x02U) != 0U)
+ {
+ /* High Speed mode allowed */
+ errorstate = MMC_HighSpeed(hmmc, ENABLE);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->ErrorCode |= errorstate;
+ }
+ }
+ else
+ {
+ /* High Speed mode not allowed */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_UNSUPPORTED_FEATURE;
+ status = HAL_ERROR;
+ }
+ break;
+ }
+ case SDMMC_SPEED_MODE_DEFAULT:
+ {
+ if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) != 0U)
+ {
+ /* High Speed DDR mode activated */
+ errorstate = MMC_DDR_Mode(hmmc, DISABLE);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->ErrorCode |= errorstate;
+ }
+ }
+ if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) != 0U)
+ {
+ /* High Speed mode activated */
+ errorstate = MMC_HighSpeed(hmmc, DISABLE);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->ErrorCode |= errorstate;
+ }
+ }
+ break;
+ }
+ default:
+ hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+ status = HAL_ERROR;
+ break;
+ }
+
+ /* Verify that MMC card is ready to use after Speed mode switch*/
+ tickstart = HAL_GetTick();
+ while ((HAL_MMC_GetCardState(hmmc) != HAL_MMC_CARD_TRANSFER))
+ {
+ if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+ {
+ hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Change State */
+ hmmc->State = HAL_MMC_STATE_READY;
+ return status;
+}
+
+/**
+ * @brief Gets the current mmc card data state.
+ * @param hmmc: pointer to MMC handle
+ * @retval Card state
+ */
+HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc)
+{
+ uint32_t cardstate;
+ uint32_t errorstate;
+ uint32_t resp1 = 0U;
+
+ errorstate = MMC_SendStatus(hmmc, &resp1);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->ErrorCode |= errorstate;
+ }
+
+ cardstate = ((resp1 >> 9U) & 0x0FU);
+
+ return (HAL_MMC_CardStateTypeDef)cardstate;
+}
+
+/**
+ * @brief Abort the current transfer and disable the MMC.
+ * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
+ * the configuration information for MMC module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc)
+{
+ HAL_MMC_CardStateTypeDef CardState;
+
+ /* DIsable All interrupts */
+ __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+ SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR);
+
+ /* Clear All flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+
+ /* If IDMA Context, disable Internal DMA */
+ hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
+
+ hmmc->State = HAL_MMC_STATE_READY;
+
+ /* Initialize the MMC operation */
+ hmmc->Context = MMC_CONTEXT_NONE;
+
+ CardState = HAL_MMC_GetCardState(hmmc);
+ if ((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
+ {
+ hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance);
+ }
+ if (hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
+ {
+ return HAL_ERROR;
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort the current transfer and disable the MMC (IT mode).
+ * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
+ * the configuration information for MMC module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc)
+{
+ HAL_MMC_CardStateTypeDef CardState;
+
+ /* DIsable All interrupts */
+ __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+ SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR);
+
+ /* If IDMA Context, disable Internal DMA */
+ hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
+
+ /* Clear All flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+
+ CardState = HAL_MMC_GetCardState(hmmc);
+ hmmc->State = HAL_MMC_STATE_READY;
+
+ if ((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
+ {
+ hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance);
+ }
+ if (hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+ hmmc->AbortCpltCallback(hmmc);
+#else
+ HAL_MMC_AbortCallback(hmmc);
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Perform specific commands sequence for the different type of erase.
+ * @note This API should be followed by a check on the card state through
+ * HAL_MMC_GetCardState().
+ * @param hmmc Pointer to MMC handle
+ * @param EraseType Specifies the type of erase to be performed
+ * This parameter can be one of the following values:
+ * @arg HAL_MMC_TRIM Erase the write blocks identified by CMD35 & 36
+ * @arg HAL_MMC_ERASE Erase the erase groups identified by CMD35 & 36
+ * @arg HAL_MMC_DISCARD Discard the write blocks identified by CMD35 & 36
+ * @arg HAL_MMC_SECURE_ERASE Perform a secure purge according SRT on the erase groups identified
+ * by CMD35 & 36
+ * @arg HAL_MMC_SECURE_TRIM_STEP1 Mark the write blocks identified by CMD35 & 36 for secure erase
+ * @arg HAL_MMC_SECURE_TRIM_STEP2 Perform a secure purge according SRT on the write blocks
+ * previously identified
+ * @param BlockStartAdd Start Block address
+ * @param BlockEndAdd End Block address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_EraseSequence(MMC_HandleTypeDef *hmmc, uint32_t EraseType,
+ uint32_t BlockStartAdd, uint32_t BlockEndAdd)
+{
+ uint32_t errorstate;
+ uint32_t start_add = BlockStartAdd;
+ uint32_t end_add = BlockEndAdd;
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Check the erase type value is correct */
+ assert_param(IS_MMC_ERASE_TYPE(EraseType));
+
+ /* Check the coherence between start and end address */
+ if (end_add < start_add)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ /* Check that the end address is not out of range of device memory */
+ if (end_add > (hmmc->MmcCard.LogBlockNbr))
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
+ if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+ {
+ if (((start_add % 8U) != 0U) || ((end_add % 8U) != 0U))
+ {
+ /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
+ return HAL_ERROR;
+ }
+ }
+
+ /* Check if the card command class supports erase command */
+ if (((hmmc->MmcCard.Class) & SDMMC_CCCC_ERASE) == 0U)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
+ return HAL_ERROR;
+ }
+
+ /* Check the state of the driver */
+ if (hmmc->State == HAL_MMC_STATE_READY)
+ {
+ /* Change State */
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Check that the card is not locked */
+ if ((SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_LOCK_UNLOCK_FAILED;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* In case of low capacity card, the address is not block number but bytes */
+ if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
+ {
+ start_add *= 512U;
+ end_add *= 512U;
+ }
+
+ /* Send CMD35 MMC_ERASE_GRP_START with start address as argument */
+ errorstate = SDMMC_CmdEraseStartAdd(hmmc->Instance, start_add);
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* Send CMD36 MMC_ERASE_GRP_END with end address as argument */
+ errorstate = SDMMC_CmdEraseEndAdd(hmmc->Instance, end_add);
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* Send CMD38 ERASE with erase type as argument */
+ errorstate = SDMMC_CmdErase(hmmc->Instance, EraseType);
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ if ((EraseType == HAL_MMC_SECURE_ERASE) || (EraseType == HAL_MMC_SECURE_TRIM_STEP2))
+ {
+ /* Wait that the device is ready by checking the D0 line */
+ while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE))
+ {
+ if ((HAL_GetTick() - tickstart) >= SDMMC_MAXERASETIMEOUT)
+ {
+ errorstate = HAL_MMC_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear the flag corresponding to end D0 bus line */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END);
+ }
+ }
+ }
+ }
+
+ /* Change State */
+ hmmc->State = HAL_MMC_STATE_READY;
+
+ /* Manage errors */
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+
+ if (errorstate != HAL_MMC_ERROR_TIMEOUT)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ else
+ {
+ return HAL_OK;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Perform sanitize operation on the device.
+ * @note This API should be followed by a check on the card state through
+ * HAL_MMC_GetCardState().
+ * @param hmmc Pointer to MMC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_Sanitize(MMC_HandleTypeDef *hmmc)
+{
+ uint32_t errorstate;
+ uint32_t response = 0U;
+ uint32_t count;
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Check the state of the driver */
+ if (hmmc->State == HAL_MMC_STATE_READY)
+ {
+ /* Change State */
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Index : 165 - Value : 0x01 */
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03A50100U);
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* Wait that the device is ready by checking the D0 line */
+ while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE))
+ {
+ if ((HAL_GetTick() - tickstart) >= SDMMC_MAXERASETIMEOUT)
+ {
+ errorstate = HAL_MMC_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear the flag corresponding to end D0 bus line */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END);
+
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+ count = SDMMC_MAX_TRIAL;
+ do
+ {
+ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ break;
+ }
+
+ /* Get command response */
+ response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+ count--;
+ } while (((response & 0x100U) == 0U) && (count != 0U));
+
+ /* Check the status after the switch command execution */
+ if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
+ {
+ /* Check the bit SWITCH_ERROR of the device status */
+ if ((response & 0x80U) != 0U)
+ {
+ errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+ }
+ }
+ else if (count == 0U)
+ {
+ errorstate = SDMMC_ERROR_TIMEOUT;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ }
+
+ /* Change State */
+ hmmc->State = HAL_MMC_STATE_READY;
+
+ /* Manage errors */
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+
+ if (errorstate != HAL_MMC_ERROR_TIMEOUT)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ else
+ {
+ return HAL_OK;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Configure the Secure Removal Type (SRT) in the Extended CSD register.
+ * @note This API should be followed by a check on the card state through
+ * HAL_MMC_GetCardState().
+ * @param hmmc Pointer to MMC handle
+ * @param SRTMode Specifies the type of erase to be performed
+ * This parameter can be one of the following values:
+ * @arg HAL_MMC_SRT_ERASE Information removed by an erase
+ * @arg HAL_MMC_SRT_WRITE_CHAR_ERASE Information removed by an overwriting with a character
+ * followed by an erase
+ * @arg HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM Information removed by an overwriting with a character,
+ * its complement then a random character
+ * @arg HAL_MMC_SRT_VENDOR_DEFINED Information removed using a vendor defined
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_ConfigSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t SRTMode)
+{
+ uint32_t srt;
+ uint32_t errorstate;
+ uint32_t response = 0U;
+ uint32_t count;
+
+ /* Check the erase type value is correct */
+ assert_param(IS_MMC_SRT_TYPE(SRTMode));
+
+ /* Check the state of the driver */
+ if (hmmc->State == HAL_MMC_STATE_READY)
+ {
+ /* Get the supported values by the device */
+ if (HAL_MMC_GetSupportedSecRemovalType(hmmc, &srt) == HAL_OK)
+ {
+ /* Change State */
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Check the value passed as parameter is supported by the device */
+ if ((SRTMode & srt) != 0U)
+ {
+ /* Index : 16 - Value : SRTMode */
+ srt |= ((POSITION_VAL(SRTMode)) << 4U);
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03100000U | (srt << 8U)));
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+ count = SDMMC_MAX_TRIAL;
+ do
+ {
+ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ break;
+ }
+
+ /* Get command response */
+ response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+ count--;
+ } while (((response & 0x100U) == 0U) && (count != 0U));
+
+ /* Check the status after the switch command execution */
+ if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
+ {
+ /* Check the bit SWITCH_ERROR of the device status */
+ if ((response & 0x80U) != 0U)
+ {
+ errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+ }
+ }
+ else if (count == 0U)
+ {
+ errorstate = SDMMC_ERROR_TIMEOUT;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ }
+ else
+ {
+ errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
+ }
+
+ /* Change State */
+ hmmc->State = HAL_MMC_STATE_READY;
+ }
+ else
+ {
+ errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+ }
+
+ /* Manage errors */
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_OK;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Gets the supported values of the the Secure Removal Type (SRT).
+ * @param hmmc pointer to MMC handle
+ * @param SupportedSRT pointer for supported SRT value
+ * This parameter is a bit field of the following values:
+ * @arg HAL_MMC_SRT_ERASE Information removed by an erase
+ * @arg HAL_MMC_SRT_WRITE_CHAR_ERASE Information removed by an overwriting with a character followed
+ * by an erase
+ * @arg HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM Information removed by an overwriting with a character,
+ * its complement then a random character
+ * @arg HAL_MMC_SRT_VENDOR_DEFINED Information removed using a vendor defined
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_GetSupportedSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t *SupportedSRT)
+{
+ /* Check the state of the driver */
+ if (hmmc->State == HAL_MMC_STATE_READY)
+ {
+ /* Change State */
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Read field SECURE_REMOVAL_TYPE [16 = 4*4] of the Extended CSD register */
+ *SupportedSRT = (hmmc->Ext_CSD[4] & 0x0000000FU); /* Bits [3:0] of field 16 */
+
+ /* Change State */
+ hmmc->State = HAL_MMC_STATE_READY;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private function ----------------------------------------------------------*/
+/** @addtogroup MMC_Private_Functions
+ * @{
+ */
+
+
+/**
+ * @brief Initializes the mmc card.
+ * @param hmmc: Pointer to MMC handle
+ * @retval MMC Card error state
+ */
+static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc)
+{
+ HAL_MMC_CardCSDTypeDef CSD;
+ uint32_t errorstate;
+ uint16_t mmc_rca = 2U;
+ MMC_InitTypeDef Init;
+
+ /* Check the power State */
+ if (SDMMC_GetPowerState(hmmc->Instance) == 0U)
+ {
+ /* Power off */
+ return HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
+ }
+
+ /* Send CMD2 ALL_SEND_CID */
+ errorstate = SDMMC_CmdSendCID(hmmc->Instance);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ return errorstate;
+ }
+ else
+ {
+ /* Get Card identification number data */
+ hmmc->CID[0U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+ hmmc->CID[1U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2);
+ hmmc->CID[2U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP3);
+ hmmc->CID[3U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP4);
+ }
+
+ /* Send CMD3 SET_REL_ADDR with RCA = 2 (should be greater than 1) */
+ /* MMC Card publishes its RCA. */
+ errorstate = SDMMC_CmdSetRelAddMmc(hmmc->Instance, mmc_rca);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ return errorstate;
+ }
+
+ /* Get the MMC card RCA */
+ hmmc->MmcCard.RelCardAdd = mmc_rca;
+
+ /* Send CMD9 SEND_CSD with argument as card's RCA */
+ errorstate = SDMMC_CmdSendCSD(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U));
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ return errorstate;
+ }
+ else
+ {
+ /* Get Card Specific Data */
+ hmmc->CSD[0U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+ hmmc->CSD[1U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2);
+ hmmc->CSD[2U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP3);
+ hmmc->CSD[3U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP4);
+ }
+
+ /* Get the Card Class */
+ hmmc->MmcCard.Class = (SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2) >> 20U);
+
+ /* Select the Card */
+ errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ return errorstate;
+ }
+
+ /* Get CSD parameters */
+ if (HAL_MMC_GetCardCSD(hmmc, &CSD) != HAL_OK)
+ {
+ return hmmc->ErrorCode;
+ }
+
+ /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->ErrorCode |= errorstate;
+ }
+
+
+ /* Get Extended CSD parameters */
+ if (HAL_MMC_GetCardExtCSD(hmmc, hmmc->Ext_CSD, SDMMC_DATATIMEOUT) != HAL_OK)
+ {
+ return hmmc->ErrorCode;
+ }
+
+ /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->ErrorCode |= errorstate;
+ }
+
+ /* Configure the SDMMC peripheral */
+ Init = hmmc->Init;
+ Init.BusWide = SDMMC_BUS_WIDE_1B;
+ (void)SDMMC_Init(hmmc->Instance, Init);
+
+ /* All cards are initialized */
+ return HAL_MMC_ERROR_NONE;
+}
+
+/**
+ * @brief Enquires cards about their operating voltage and configures clock
+ * controls and stores MMC information that will be needed in future
+ * in the MMC handle.
+ * @param hmmc: Pointer to MMC handle
+ * @retval error state
+ */
+static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc)
+{
+ __IO uint32_t count = 0U;
+ uint32_t response = 0U;
+ uint32_t validvoltage = 0U;
+ uint32_t errorstate;
+
+ /* CMD0: GO_IDLE_STATE */
+ errorstate = SDMMC_CmdGoIdleState(hmmc->Instance);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ return errorstate;
+ }
+
+ while (validvoltage == 0U)
+ {
+ if (count++ == SDMMC_MAX_VOLT_TRIAL)
+ {
+ return HAL_MMC_ERROR_INVALID_VOLTRANGE;
+ }
+
+ /* SEND CMD1 APP_CMD with voltage range as argument */
+ errorstate = SDMMC_CmdOpCondition(hmmc->Instance, MMC_VOLTAGE_RANGE);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ return HAL_MMC_ERROR_UNSUPPORTED_FEATURE;
+ }
+
+ /* Get command response */
+ response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+
+ /* Get operating voltage*/
+ validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);
+ }
+
+ /* When power routine is finished and command returns valid voltage */
+ if (((response & (0xFF000000U)) >> 24) == 0xC0U)
+ {
+ hmmc->MmcCard.CardType = MMC_HIGH_CAPACITY_CARD;
+ }
+ else
+ {
+ hmmc->MmcCard.CardType = MMC_LOW_CAPACITY_CARD;
+ }
+
+ return HAL_MMC_ERROR_NONE;
+}
+
+/**
+ * @brief Turns the SDMMC output signals off.
+ * @param hmmc: Pointer to MMC handle
+ * @retval None
+ */
+static void MMC_PowerOFF(MMC_HandleTypeDef *hmmc)
+{
+ /* Set Power State to OFF */
+ (void)SDMMC_PowerState_OFF(hmmc->Instance);
+}
+
+/**
+ * @brief Returns the current card's status.
+ * @param hmmc: Pointer to MMC handle
+ * @param pCardStatus: pointer to the buffer that will contain the MMC card
+ * status (Card Status register)
+ * @retval error state
+ */
+static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus)
+{
+ uint32_t errorstate;
+
+ if (pCardStatus == NULL)
+ {
+ return HAL_MMC_ERROR_PARAM;
+ }
+
+ /* Send Status command */
+ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U));
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ return errorstate;
+ }
+
+ /* Get MMC card status */
+ *pCardStatus = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+
+ return HAL_MMC_ERROR_NONE;
+}
+
+/**
+ * @brief Reads extended CSD register to get the sectors number of the device
+ * @param hmmc: Pointer to MMC handle
+ * @param pFieldData: Pointer to the read buffer
+ * @param FieldIndex: Index of the field to be read
+ * @param Timeout: Specify timeout value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData,
+ uint16_t FieldIndex, uint32_t Timeout)
+{
+ SDMMC_DataInitTypeDef config;
+ uint32_t errorstate;
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t count;
+ uint32_t i = 0;
+ uint32_t tmp_data;
+
+ hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+
+ /* Initialize data control register */
+ hmmc->Instance->DCTRL = 0;
+
+ /* Configure the MMC DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = 512U;
+ config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
+ config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDMMC_DPSM_ENABLE;
+ (void)SDMMC_ConfigData(hmmc->Instance, &config);
+
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdSendEXTCSD(hmmc->Instance, 0);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Poll on SDMMC flags */
+ while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+ {
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF))
+ {
+ /* Read data from SDMMC Rx FIFO */
+ for (count = 0U; count < 8U; count++)
+ {
+ tmp_data = SDMMC_ReadFIFO(hmmc->Instance);
+ /* eg : SEC_COUNT : FieldIndex = 212 => i+count = 53 */
+ /* DEVICE_TYPE : FieldIndex = 196 => i+count = 49 */
+ if ((i + count) == ((uint32_t)FieldIndex / 4U))
+ {
+ *pFieldData = tmp_data;
+ }
+ }
+ i += 8U;
+ }
+
+ if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Get error state */
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16));
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->ErrorCode |= errorstate;
+ }
+
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+
+ hmmc->State = HAL_MMC_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Wrap up reading in non-blocking mode.
+ * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
+ * the configuration information.
+ * @retval None
+ */
+static void MMC_Read_IT(MMC_HandleTypeDef *hmmc)
+{
+ uint32_t count;
+ uint32_t data;
+ uint8_t *tmp;
+
+ tmp = hmmc->pRxBuffPtr;
+
+ if (hmmc->RxXferSize >= 32U)
+ {
+ /* Read data from SDMMC Rx FIFO */
+ for (count = 0U; count < 8U; count++)
+ {
+ data = SDMMC_ReadFIFO(hmmc->Instance);
+ *tmp = (uint8_t)(data & 0xFFU);
+ tmp++;
+ *tmp = (uint8_t)((data >> 8U) & 0xFFU);
+ tmp++;
+ *tmp = (uint8_t)((data >> 16U) & 0xFFU);
+ tmp++;
+ *tmp = (uint8_t)((data >> 24U) & 0xFFU);
+ tmp++;
+ }
+
+ hmmc->pRxBuffPtr = tmp;
+ hmmc->RxXferSize -= 32U;
+ }
+}
+
+/**
+ * @brief Wrap up writing in non-blocking mode.
+ * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
+ * the configuration information.
+ * @retval None
+ */
+static void MMC_Write_IT(MMC_HandleTypeDef *hmmc)
+{
+ uint32_t count;
+ uint32_t data;
+ uint8_t *tmp;
+
+ tmp = hmmc->pTxBuffPtr;
+
+ if (hmmc->TxXferSize >= 32U)
+ {
+ /* Write data to SDMMC Tx FIFO */
+ for (count = 0U; count < 8U; count++)
+ {
+ data = (uint32_t)(*tmp);
+ tmp++;
+ data |= ((uint32_t)(*tmp) << 8U);
+ tmp++;
+ data |= ((uint32_t)(*tmp) << 16U);
+ tmp++;
+ data |= ((uint32_t)(*tmp) << 24U);
+ tmp++;
+ (void)SDMMC_WriteFIFO(hmmc->Instance, &data);
+ }
+
+ hmmc->pTxBuffPtr = tmp;
+ hmmc->TxXferSize -= 32U;
+ }
+}
+
+/**
+ * @brief Switches the MMC card to high speed mode.
+ * @param hmmc: MMC handle
+ * @param state: State of high speed mode
+ * @retval MMC Card error state
+ */
+static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state)
+{
+ uint32_t errorstate = HAL_MMC_ERROR_NONE;
+ uint32_t response = 0U;
+ uint32_t count;
+ uint32_t sdmmc_clk;
+ SDMMC_InitTypeDef Init;
+
+ if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) != 0U) && (state == DISABLE))
+ {
+ errorstate = MMC_PwrClassUpdate(hmmc, (hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS), SDMMC_SPEED_MODE_DEFAULT);
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* Index : 185 - Value : 0 */
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B90000U);
+ }
+ }
+
+ if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) == 0U) && (state != DISABLE))
+ {
+ errorstate = MMC_PwrClassUpdate(hmmc, (hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS), SDMMC_SPEED_MODE_HIGH);
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* Index : 185 - Value : 1 */
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B90100U);
+ }
+ }
+
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+ count = SDMMC_MAX_TRIAL;
+ do
+ {
+ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ break;
+ }
+
+ /* Get command response */
+ response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+ count--;
+ } while (((response & 0x100U) == 0U) && (count != 0U));
+
+ /* Check the status after the switch command execution */
+ if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
+ {
+ /* Check the bit SWITCH_ERROR of the device status */
+ if ((response & 0x80U) != 0U)
+ {
+ errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
+ }
+ else
+ {
+ /* Configure high speed */
+ Init.ClockEdge = hmmc->Init.ClockEdge;
+ Init.ClockPowerSave = hmmc->Init.ClockPowerSave;
+ Init.BusWide = (hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS);
+ Init.HardwareFlowControl = hmmc->Init.HardwareFlowControl;
+
+ if (state == DISABLE)
+ {
+ Init.ClockDiv = hmmc->Init.ClockDiv;
+ (void)SDMMC_Init(hmmc->Instance, Init);
+
+ CLEAR_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED);
+ }
+ else
+ {
+ /* High Speed Clock should be less or equal to 52MHz*/
+ sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC);
+ if (sdmmc_clk == 0U)
+ {
+ errorstate = SDMMC_ERROR_INVALID_PARAMETER;
+ }
+ else
+ {
+ Init.ClockDiv = sdmmc_clk / (2U * MMC_HIGH_SPEED_FREQ);
+ (void)SDMMC_Init(hmmc->Instance, Init);
+
+ SET_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED);
+ }
+ }
+ }
+ }
+ else if (count == 0U)
+ {
+ errorstate = SDMMC_ERROR_TIMEOUT;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+
+ return errorstate;
+}
+
+/**
+ * @brief Switches the MMC card to Double Data Rate (DDR) mode.
+ * @param hmmc: MMC handle
+ * @param state: State of DDR mode
+ * @retval MMC Card error state
+ */
+static uint32_t MMC_DDR_Mode(MMC_HandleTypeDef *hmmc, FunctionalState state)
+{
+ uint32_t errorstate = HAL_MMC_ERROR_NONE;
+ uint32_t response = 0U;
+ uint32_t count;
+
+ if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) != 0U) && (state == DISABLE))
+ {
+ if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS_0) != 0U)
+ {
+ errorstate = MMC_PwrClassUpdate(hmmc, SDMMC_BUS_WIDE_4B, SDMMC_SPEED_MODE_HIGH);
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* Index : 183 - Value : 1 */
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U);
+ }
+ }
+ else
+ {
+ errorstate = MMC_PwrClassUpdate(hmmc, SDMMC_BUS_WIDE_8B, SDMMC_SPEED_MODE_HIGH);
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* Index : 183 - Value : 2 */
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U);
+ }
+ }
+ }
+
+ if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U) && (state != DISABLE))
+ {
+ if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS_0) != 0U)
+ {
+ errorstate = MMC_PwrClassUpdate(hmmc, SDMMC_BUS_WIDE_4B, SDMMC_SPEED_MODE_DDR);
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* Index : 183 - Value : 5 */
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70500U);
+ }
+ }
+ else
+ {
+ errorstate = MMC_PwrClassUpdate(hmmc, SDMMC_BUS_WIDE_8B, SDMMC_SPEED_MODE_DDR);
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* Index : 183 - Value : 6 */
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70600U);
+ }
+ }
+ }
+
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+ count = SDMMC_MAX_TRIAL;
+ do
+ {
+ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ break;
+ }
+
+ /* Get command response */
+ response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+ count--;
+ } while (((response & 0x100U) == 0U) && (count != 0U));
+
+ /* Check the status after the switch command execution */
+ if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
+ {
+ /* Check the bit SWITCH_ERROR of the device status */
+ if ((response & 0x80U) != 0U)
+ {
+ errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
+ }
+ else
+ {
+ /* Configure DDR mode */
+ if (state == DISABLE)
+ {
+ CLEAR_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_DDR);
+ }
+ else
+ {
+ SET_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_DDR);
+ }
+ }
+ }
+ else if (count == 0U)
+ {
+ errorstate = SDMMC_ERROR_TIMEOUT;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+
+ return errorstate;
+}
+
+/**
+ * @brief Update the power class of the device.
+ * @param hmmc MMC handle
+ * @param Wide Wide of MMC bus
+ * @param Speed Speed of the MMC bus
+ * @retval MMC Card error state
+ */
+static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide, uint32_t Speed)
+{
+ uint32_t count;
+ uint32_t response = 0U;
+ uint32_t errorstate = HAL_MMC_ERROR_NONE;
+ uint32_t power_class;
+ uint32_t supported_pwr_class;
+
+ if ((Wide == SDMMC_BUS_WIDE_8B) || (Wide == SDMMC_BUS_WIDE_4B))
+ {
+ power_class = 0U; /* Default value after power-on or software reset */
+
+ /* Read the PowerClass field of the Extended CSD register */
+ if (MMC_ReadExtCSD(hmmc, &power_class, 187, SDMMC_DATATIMEOUT) != HAL_OK) /* Field POWER_CLASS [187] */
+ {
+ errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+ }
+ else
+ {
+ power_class = ((power_class >> 24U) & 0x000000FFU);
+ }
+
+ /* Get the supported PowerClass field of the Extended CSD register */
+ if (Speed == SDMMC_SPEED_MODE_DDR)
+ {
+ /* Field PWR_CL_DDR_52_xxx [238 or 239] */
+ supported_pwr_class = ((hmmc->Ext_CSD[(MMC_EXT_CSD_PWR_CL_DDR_52_INDEX / 4)] >> MMC_EXT_CSD_PWR_CL_DDR_52_POS) &
+ 0x000000FFU);
+ }
+ else if (Speed == SDMMC_SPEED_MODE_HIGH)
+ {
+ /* Field PWR_CL_52_xxx [200 or 202] */
+ supported_pwr_class = ((hmmc->Ext_CSD[(MMC_EXT_CSD_PWR_CL_52_INDEX / 4)] >> MMC_EXT_CSD_PWR_CL_52_POS) &
+ 0x000000FFU);
+ }
+ else
+ {
+ /* Field PWR_CL_26_xxx [201 or 203] */
+ supported_pwr_class = ((hmmc->Ext_CSD[(MMC_EXT_CSD_PWR_CL_26_INDEX / 4)] >> MMC_EXT_CSD_PWR_CL_26_POS) &
+ 0x000000FFU);
+ }
+
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ if (Wide == SDMMC_BUS_WIDE_8B)
+ {
+ /* Bit [7:4]: power class for 8-bits bus configuration - Bit [3:0]: power class for 4-bits bus configuration */
+ supported_pwr_class = (supported_pwr_class >> 4U);
+ }
+
+ if ((power_class & 0x0FU) != (supported_pwr_class & 0x0FU))
+ {
+ /* Need to change current power class */
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03BB0000U | ((supported_pwr_class & 0x0FU) << 8U)));
+
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+ count = SDMMC_MAX_TRIAL;
+ do
+ {
+ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ break;
+ }
+
+ /* Get command response */
+ response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+ count--;
+ } while (((response & 0x100U) == 0U) && (count != 0U));
+
+ /* Check the status after the switch command execution */
+ if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
+ {
+ /* Check the bit SWITCH_ERROR of the device status */
+ if ((response & 0x80U) != 0U)
+ {
+ errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
+ }
+ }
+ else if (count == 0U)
+ {
+ errorstate = SDMMC_ERROR_TIMEOUT;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ }
+ }
+ }
+
+ return errorstate;
+}
+
+/**
+ * @brief Read DMA Linked list node Transfer completed callbacks
+ * @param hmmc: MMC handle
+ * @retval None
+ */
+__weak void HAL_MMCEx_Read_DMALnkLstBufCpltCallback(MMC_HandleTypeDef *hmmc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hmmc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_MMCEx_Read_DMALnkLstBufCpltCallback can be implemented in the user file
+ */
+}
+/**
+ * @brief Read DMA Linked list node Transfer completed callbacks
+ * @param hmmc: MMC handle
+ * @retval None
+ */
+__weak void HAL_MMCEx_Write_DMALnkLstBufCpltCallback(MMC_HandleTypeDef *hmmc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hmmc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_MMCEx_Write_DMALnkLstBufCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mmc_ex.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mmc_ex.c
new file mode 100644
index 00000000..13a4338c
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mmc_ex.c
@@ -0,0 +1,445 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_mmc_ex.c
+ * @author MCD Application Team
+ * @brief MMC card Extended HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Secure Digital (MMC) peripheral:
+ * + Extended features functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The MMC Extension HAL driver can be used as follows:
+ (+) Configure Buffer0 and Buffer1 start address and Buffer size using HAL_MMCEx_ConfigDMAMultiBuffer() function.
+
+ (+) Start Read and Write for multibuffer mode using HAL_MMCEx_ReadBlocksDMAMultiBuffer() and
+ HAL_MMCEx_WriteBlocksDMAMultiBuffer() functions.
+
+ @endverbatim
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup MMCEx MMCEx
+ * @brief MMC Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup MMCEx_Exported_Functions
+ * @{
+ */
+
+
+
+/** @addtogroup MMCEx_Exported_Functions_Group1
+ * @brief Linked List management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Linked List management functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the needed functions.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Build Linked List node.
+ * @param pNode: Pointer to new node to add.
+ * @param pNodeConf: Pointer to configuration parameters for new node to add.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_BuildNode(MMC_DMALinkNodeTypeDef *pNode,
+ MMC_DMALinkNodeConfTypeDef *pNodeConf)
+{
+
+ if (SDMMC_DMALinkedList_BuildNode(pNode, pNodeConf) != SDMMC_ERROR_NONE)
+ {
+ return (HAL_ERROR);
+ }
+ else
+ {
+ return (HAL_OK);
+ }
+
+}
+/**
+ * @brief Insert Linked List node.
+ * @param pLinkedList: Pointer to the linkedlist that contains transfer nodes
+ * @param pPrevNode: Pointer to previous node.
+ * @param pNewNode: Pointer to new node to insert.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_InsertNode(MMC_DMALinkedListTypeDef *pLinkedList,
+ MMC_DMALinkNodeTypeDef *pPrevNode,
+ MMC_DMALinkNodeTypeDef *pNewNode)
+{
+
+ if (SDMMC_DMALinkedList_InsertNode(pLinkedList, pPrevNode, pNewNode) != SDMMC_ERROR_NONE)
+ {
+ return (HAL_ERROR);
+ }
+ else
+ {
+ return (HAL_OK);
+ }
+
+}
+/**
+ * @brief Remove Linked List node.
+ * @param pLinkedList: Pointer to the linkedlist that contains transfer nodes
+ * @param pNode: Pointer to node to remove.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_RemoveNode(MMC_DMALinkedListTypeDef *pLinkedList,
+ MMC_DMALinkNodeTypeDef *pNode)
+{
+
+ if (SDMMC_DMALinkedList_RemoveNode(pLinkedList, pNode) != SDMMC_ERROR_NONE)
+ {
+ return (HAL_ERROR);
+ }
+ else
+ {
+ return (HAL_OK);
+ }
+}
+
+/**
+ * @brief Lock Linked List node.
+ * @param pNode: Pointer to node to remove.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_LockNode(MMC_DMALinkNodeTypeDef *pNode)
+{
+
+ if (SDMMC_DMALinkedList_LockNode(pNode) != SDMMC_ERROR_NONE)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief Unlock Linked List node.
+ * @param pNode: Pointer to node to remove.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_UnlockNode(MMC_DMALinkNodeTypeDef *pNode)
+{
+
+ if (SDMMC_DMALinkedList_UnlockNode(pNode) != SDMMC_ERROR_NONE)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief Enable Circular mode for DMA Linked List mode.
+ * @param pLinkedList: Pointer to the linkedlist that contains transfer nodes
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_EnableCircularMode(MMC_DMALinkedListTypeDef *pLinkedList)
+{
+
+ if (SDMMC_DMALinkedList_EnableCircularMode(pLinkedList) != SDMMC_ERROR_NONE)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_OK;
+ }
+}
+/**
+ * @brief Disable Circular mode for DMA Linked List mode.
+ * @param pLinkedList: Pointer to the linkedlist that contains transfer nodes
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_DisableCircularMode(MMC_DMALinkedListTypeDef *pLinkedList)
+{
+
+ if (SDMMC_DMALinkedList_DisableCircularMode(pLinkedList) != SDMMC_ERROR_NONE)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_OK;
+ }
+}
+
+
+/**
+ * @brief Reads block(s) from a specified address in a card. The received Data will be stored in linked list buffers.
+ * linked list should be prepared before call this function .
+ * @param hmmc: MMC handle
+ * @param pLinkedList: pointer to first linked list node
+ * @param BlockAdd: Block Address from where data is to be read
+ * @param NumberOfBlocks: Total number of blocks to read
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_ReadBlocks(MMC_HandleTypeDef *hmmc, MMC_DMALinkedListTypeDef *pLinkedList,
+ uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+ SDMMC_DataInitTypeDef config;
+ uint32_t DmaBase0_reg;
+ uint32_t DmaBase1_reg;
+ uint32_t errorstate;
+ uint32_t add = BlockAdd;
+
+ if (hmmc->State == HAL_MMC_STATE_READY)
+ {
+ if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
+ if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+ {
+ if ((NumberOfBlocks % 8U) != 0U)
+ {
+ /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR;
+ return HAL_ERROR;
+ }
+
+ if ((BlockAdd % 8U) != 0U)
+ {
+ /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
+ return HAL_ERROR;
+ }
+ }
+
+ hmmc->Instance->IDMABASER = (uint32_t) pLinkedList->pHeadNode->IDMABASER;
+ hmmc->Instance->IDMABSIZE = (uint32_t) pLinkedList->pHeadNode->IDMABSIZE;
+ hmmc->Instance->IDMABAR = (uint32_t) pLinkedList->pHeadNode;
+ hmmc->Instance->IDMALAR = (uint32_t) SDMMC_IDMALAR_ABR | SDMMC_IDMALAR_ULS | SDMMC_IDMALAR_ULA |
+ sizeof(SDMMC_DMALinkNodeTypeDef) ; /* Initial configuration */
+
+ DmaBase0_reg = hmmc->Instance->IDMABASER;
+ DmaBase1_reg = hmmc->Instance->IDMABAR;
+
+ if ((hmmc->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U))
+ {
+ hmmc->ErrorCode = HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ /* Initialize data control register */
+ hmmc->Instance->DCTRL = 0;
+
+ hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
+ {
+ add *= 512U;
+ }
+
+ /* Configure the MMC DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
+ config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
+ config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDMMC_DPSM_DISABLE;
+ (void)SDMMC_ConfigData(hmmc->Instance, &config);
+
+ hmmc->Instance->DCTRL |= SDMMC_DCTRL_FIFORST;
+
+ __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
+
+ hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
+
+ /* Read Blocks in DMA mode */
+ hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
+
+ /* Read Multi Block command */
+ errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->State = HAL_MMC_STATE_READY;
+ hmmc->ErrorCode |= errorstate;
+ return HAL_ERROR;
+ }
+
+ __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND |
+ SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC));
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+
+}
+
+/**
+ * @brief Write block(s) to a specified address in a card. The transferred Data are stored linked list nodes buffers .
+ * linked list should be prepared before call this function .
+ * @param hmmc: MMC handle
+ * @param pLinkedList: pointer to first linked list node
+ * @param BlockAdd: Block Address from where data is to be read
+ * @param NumberOfBlocks: Total number of blocks to read
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_WriteBlocks(MMC_HandleTypeDef *hmmc, MMC_DMALinkedListTypeDef *pLinkedList,
+ uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+ SDMMC_DataInitTypeDef config;
+ uint32_t errorstate;
+ uint32_t DmaBase0_reg;
+ uint32_t DmaBase1_reg;
+ uint32_t add = BlockAdd;
+
+ if (hmmc->State == HAL_MMC_STATE_READY)
+ {
+ if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
+ if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+ {
+ if ((NumberOfBlocks % 8U) != 0U)
+ {
+ /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR;
+ return HAL_ERROR;
+ }
+
+ if ((BlockAdd % 8U) != 0U)
+ {
+ /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
+ return HAL_ERROR;
+ }
+ }
+
+ hmmc->Instance->IDMABASER = (uint32_t) pLinkedList->pHeadNode->IDMABASER;
+ hmmc->Instance->IDMABSIZE = (uint32_t) pLinkedList->pHeadNode->IDMABSIZE;
+
+ hmmc->Instance->IDMABAR = (uint32_t) pLinkedList->pHeadNode;
+ hmmc->Instance->IDMALAR = (uint32_t) SDMMC_IDMALAR_ABR | SDMMC_IDMALAR_ULS | SDMMC_IDMALAR_ULA |
+ sizeof(SDMMC_DMALinkNodeTypeDef) ; /* Initial configuration */
+
+ DmaBase0_reg = hmmc->Instance->IDMABASER;
+ DmaBase1_reg = hmmc->Instance->IDMABAR;
+
+ if ((hmmc->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U))
+ {
+ hmmc->ErrorCode = HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ /* Initialize data control register */
+ hmmc->Instance->DCTRL = 0;
+
+ hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
+ {
+ add *= 512U;
+ }
+
+ /* Configure the MMC DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
+ config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;
+ config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDMMC_DPSM_DISABLE;
+ (void)SDMMC_ConfigData(hmmc->Instance, &config);
+
+ __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
+
+ hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
+
+ /* Write Blocks in DMA mode */
+ hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->State = HAL_MMC_STATE_READY;
+ hmmc->ErrorCode |= errorstate;
+ return HAL_ERROR;
+ }
+
+ __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND |
+ SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC));
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_msp_template.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_msp_template.c
new file mode 100644
index 00000000..c4c59e53
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_msp_template.c
@@ -0,0 +1,101 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_msp_template.c
+ * @author MCD Application Team
+ * @brief HAL MSP module.
+ * This file template is located in the HAL folder and should be copied
+ * to the user folder.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup HAL_MSP HAL MSP module driver
+ * @brief HAL MSP module.
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup HAL_MSP_Private_Functions HAL MSP Private Functions
+ * @{
+ */
+
+/**
+ * @brief Initializes the Global MSP.
+ * @retval None
+ */
+void HAL_MspInit(void)
+{
+
+}
+
+/**
+ * @brief DeInitializes the Global MSP.
+ * @retval None
+ */
+void HAL_MspDeInit(void)
+{
+
+}
+
+/**
+ * @brief Initialize the PPP MSP.
+ * @retval None
+ */
+/*
+void HAL_PPP_MspInit(void)
+{
+}
+*/
+
+/**
+ * @brief DeInitialize the PPP MSP.
+ * @retval None
+ */
+/*
+void HAL_PPP_MspDeInit(void)
+{
+}
+*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_nand.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_nand.c
new file mode 100644
index 00000000..ccbad52f
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_nand.c
@@ -0,0 +1,2242 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_nand.c
+ * @author MCD Application Team
+ * @brief NAND HAL module driver.
+ * This file provides a generic firmware to drive NAND memories mounted
+ * as external device.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This driver is a generic layered driver which contains a set of APIs used to
+ control NAND flash memories. It uses the FMC layer functions to interface
+ with NAND devices. This driver is used as follows:
+
+ (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
+ with control and timing parameters for both common and attribute spaces.
+
+ (+) Read NAND flash memory maker and device IDs using the function
+ HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
+ structure declared by the function caller.
+
+ (+) Access NAND flash memory by read/write operations using the functions
+ HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(),
+ HAL_NAND_Write_Page_8b()/HAL_NAND_Write_SpareArea_8b(),
+ HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(),
+ HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b()
+ to read/write page(s)/spare area(s). These functions use specific device
+ information (Block, page size..) predefined by the user in the NAND_DeviceConfigTypeDef
+ structure. The read/write address information is contained by the Nand_Address_Typedef
+ structure passed as parameter.
+
+ (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
+
+ (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
+ The erase block address information is contained in the Nand_Address_Typedef
+ structure passed as parameter.
+
+ (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
+
+ (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
+ HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
+ feature or the function HAL_NAND_GetECC() to get the ECC correction code.
+
+ (+) You can monitor the NAND device HAL state by calling the function
+ HAL_NAND_GetState()
+
+ [..]
+ (@) This driver is a set of generic APIs which handle standard NAND flash operations.
+ If a NAND flash device contains different operations and/or implementations,
+ it should be implemented separately.
+
+ *** Callback registration ***
+ =============================================
+ [..]
+ The compilation define USE_HAL_NAND_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ Use Functions @ref HAL_NAND_RegisterCallback() to register a user callback,
+ it allows to register following callbacks:
+ (+) MspInitCallback : NAND MspInit.
+ (+) MspDeInitCallback : NAND MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_NAND_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function. It allows to reset following callbacks:
+ (+) MspInitCallback : NAND MspInit.
+ (+) MspDeInitCallback : NAND MspDeInit.
+ This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+ By default, after the @ref HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET
+ all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_NAND_Init
+ and @ref HAL_NAND_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_NAND_Init and @ref HAL_NAND_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_NAND_RegisterCallback before calling @ref HAL_NAND_DeInit
+ or @ref HAL_NAND_Init function.
+
+ When The compilation define USE_HAL_NAND_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+
+/** @defgroup NAND NAND
+ * @brief NAND HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private Constants ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup NAND_Exported_Functions NAND Exported Functions
+ * @{
+ */
+
+/** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### NAND Initialization and de-initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to initialize/de-initialize
+ the NAND memory
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Perform NAND memory Initialization sequence
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param ComSpace_Timing pointer to Common space timing structure
+ * @param AttSpace_Timing pointer to Attribute space timing structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing,
+ FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
+{
+ /* Check the NAND handle state */
+ if (hnand == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ if (hnand->State == HAL_NAND_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hnand->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+ if (hnand->MspInitCallback == NULL)
+ {
+ hnand->MspInitCallback = HAL_NAND_MspInit;
+ }
+ hnand->ItCallback = HAL_NAND_ITCallback;
+
+ /* Init the low level hardware */
+ hnand->MspInitCallback(hnand);
+#else
+ /* Initialize the low level hardware (MSP) */
+ HAL_NAND_MspInit(hnand);
+#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
+ }
+
+ /* Initialize NAND control Interface */
+ (void)FMC_NAND_Init(hnand->Instance, &(hnand->Init));
+
+ /* Initialize NAND common space timing Interface */
+ (void)FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
+
+ /* Initialize NAND attribute space timing Interface */
+ (void)FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
+
+ /* Enable the NAND device */
+ __FMC_NAND_ENABLE(hnand->Instance);
+
+ /* Enable FMC Peripheral */
+ __FMC_ENABLE();
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Perform NAND memory De-Initialization sequence
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
+{
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+ if (hnand->MspDeInitCallback == NULL)
+ {
+ hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
+ }
+
+ /* DeInit the low level hardware */
+ hnand->MspDeInitCallback(hnand);
+#else
+ /* Initialize the low level hardware (MSP) */
+ HAL_NAND_MspDeInit(hnand);
+#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
+
+ /* Configure the NAND registers with their reset values */
+ (void)FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
+
+ /* Reset the NAND controller state */
+ hnand->State = HAL_NAND_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief NAND MSP Init
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval None
+ */
+__weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hnand);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_NAND_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief NAND MSP DeInit
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval None
+ */
+__weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hnand);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_NAND_MspDeInit could be implemented in the user file
+ */
+}
+
+
+/**
+ * @brief This function handles NAND device interrupt request.
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval HAL status
+ */
+void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
+{
+ /* Check NAND interrupt Rising edge flag */
+ if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE))
+ {
+ /* NAND interrupt callback*/
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+ hnand->ItCallback(hnand);
+#else
+ HAL_NAND_ITCallback(hnand);
+#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
+
+ /* Clear NAND interrupt Rising edge pending bit */
+ __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_RISING_EDGE);
+ }
+
+ /* Check NAND interrupt Level flag */
+ if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL))
+ {
+ /* NAND interrupt callback*/
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+ hnand->ItCallback(hnand);
+#else
+ HAL_NAND_ITCallback(hnand);
+#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
+
+ /* Clear NAND interrupt Level pending bit */
+ __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_LEVEL);
+ }
+
+ /* Check NAND interrupt Falling edge flag */
+ if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE))
+ {
+ /* NAND interrupt callback*/
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+ hnand->ItCallback(hnand);
+#else
+ HAL_NAND_ITCallback(hnand);
+#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
+
+ /* Clear NAND interrupt Falling edge pending bit */
+ __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FALLING_EDGE);
+ }
+
+ /* Check NAND interrupt FIFO empty flag */
+ if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT))
+ {
+ /* NAND interrupt callback*/
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+ hnand->ItCallback(hnand);
+#else
+ HAL_NAND_ITCallback(hnand);
+#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
+
+ /* Clear NAND interrupt FIFO empty pending bit */
+ __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FEMPT);
+ }
+
+}
+
+/**
+ * @brief NAND interrupt feature callback
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval None
+ */
+__weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hnand);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_NAND_ITCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
+ * @brief Input Output and memory control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### NAND Input and Output functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to use and control the NAND
+ memory
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Read the NAND memory electronic signature
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pNAND_ID NAND ID structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
+{
+ __IO uint32_t data = 0;
+ __IO uint32_t data1 = 0;
+ uint32_t deviceaddress;
+
+ /* Check the NAND controller state */
+ if (hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (hnand->State == HAL_NAND_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Identify the device address */
+ deviceaddress = NAND_DEVICE;
+
+ /* Send Read ID command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ __DSB();
+
+ /* Read the electronic signature from NAND flash */
+ if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8)
+ {
+ data = *(__IO uint32_t *)deviceaddress;
+
+ /* Return the data read */
+ pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
+ pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data);
+ pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data);
+ pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data);
+ }
+ else
+ {
+ data = *(__IO uint32_t *)deviceaddress;
+ data1 = *((__IO uint32_t *)deviceaddress + 4);
+
+ /* Return the data read */
+ pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
+ pNAND_ID->Device_Id = ADDR_3RD_CYCLE(data);
+ pNAND_ID->Third_Id = ADDR_1ST_CYCLE(data1);
+ pNAND_ID->Fourth_Id = ADDR_3RD_CYCLE(data1);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief NAND memory reset
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
+{
+ uint32_t deviceaddress;
+
+ /* Check the NAND controller state */
+ if (hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (hnand->State == HAL_NAND_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Identify the device address */
+ deviceaddress = NAND_DEVICE;
+
+ /* Send NAND reset command */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF;
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+
+}
+
+/**
+ * @brief Configure the device: Enter the physical parameters of the device
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pDeviceConfig pointer to NAND_DeviceConfigTypeDef structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig)
+{
+ hnand->Config.PageSize = pDeviceConfig->PageSize;
+ hnand->Config.SpareAreaSize = pDeviceConfig->SpareAreaSize;
+ hnand->Config.BlockSize = pDeviceConfig->BlockSize;
+ hnand->Config.BlockNbr = pDeviceConfig->BlockNbr;
+ hnand->Config.PlaneSize = pDeviceConfig->PlaneSize;
+ hnand->Config.PlaneNbr = pDeviceConfig->PlaneNbr;
+ hnand->Config.ExtraCommandEnable = pDeviceConfig->ExtraCommandEnable;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read Page(s) from NAND memory block (8-bits addressing)
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to destination read buffer
+ * @param NumPageToRead number of pages to read from block
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
+ uint32_t NumPageToRead)
+{
+ uint32_t index;
+ uint32_t tickstart;
+ uint32_t deviceaddress;
+ uint32_t numpagesread = 0U;
+ uint32_t nandaddress;
+ uint32_t nbpages = NumPageToRead;
+ uint8_t *buff = pBuffer;
+
+ /* Check the NAND controller state */
+ if (hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (hnand->State == HAL_NAND_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Identify the device address */
+ deviceaddress = NAND_DEVICE;
+
+ /* NAND raw address calculation */
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+ /* Page(s) read loop */
+ while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ {
+ /* Send read page command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ __DSB();
+
+ /* Cards with page size <= 512 bytes */
+ if ((hnand->Config.PageSize) <= 512U)
+ {
+ if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ __DSB();
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ __DSB();
+ }
+ }
+ else /* (hnand->Config.PageSize) > 512 */
+ {
+ if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ __DSB();
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ __DSB();
+ }
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+ __DSB();
+
+
+ if (hnand->Config.ExtraCommandEnable == ENABLE)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Read status until NAND is ready */
+ while (HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
+ {
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_ERROR;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Go back to read mode */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
+ __DSB();
+ }
+
+ /* Get Data into Buffer */
+ for (index = 0U; index < hnand->Config.PageSize; index++)
+ {
+ *buff = *(uint8_t *)deviceaddress;
+ buff++;
+ }
+
+ /* Increment read pages number */
+ numpagesread++;
+
+ /* Decrement pages to read */
+ nbpages--;
+
+ /* Increment the NAND address */
+ nandaddress = (uint32_t)(nandaddress + 1U);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read Page(s) from NAND memory block (16-bits addressing)
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to destination read buffer. pBuffer should be 16bits aligned
+ * @param NumPageToRead number of pages to read from block
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
+ uint32_t NumPageToRead)
+{
+ uint32_t index;
+ uint32_t tickstart;
+ uint32_t deviceaddress;
+ uint32_t numpagesread = 0U;
+ uint32_t nandaddress;
+ uint32_t nbpages = NumPageToRead;
+ uint16_t *buff = pBuffer;
+
+ /* Check the NAND controller state */
+ if (hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (hnand->State == HAL_NAND_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Identify the device address */
+ deviceaddress = NAND_DEVICE;
+
+ /* NAND raw address calculation */
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+ /* Page(s) read loop */
+ while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ {
+ /* Send read page command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ __DSB();
+
+ /* Cards with page size <= 512 bytes */
+ if ((hnand->Config.PageSize) <= 512U)
+ {
+ if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ __DSB();
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ __DSB();
+ }
+ }
+ else /* (hnand->Config.PageSize) > 512 */
+ {
+ if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ __DSB();
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ __DSB();
+ }
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+ __DSB();
+
+ if (hnand->Config.ExtraCommandEnable == ENABLE)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Read status until NAND is ready */
+ while (HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
+ {
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_ERROR;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Go back to read mode */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
+ __DSB();
+ }
+
+ /* Calculate PageSize */
+ if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8)
+ {
+ hnand->Config.PageSize = hnand->Config.PageSize / 2U;
+ }
+ else
+ {
+ /* Do nothing */
+ /* Keep the same PageSize for FMC_NAND_MEM_BUS_WIDTH_16*/
+ }
+
+ /* Get Data into Buffer */
+ for (index = 0U; index < hnand->Config.PageSize; index++)
+ {
+ *buff = *(uint16_t *)deviceaddress;
+ buff++;
+ }
+
+ /* Increment read pages number */
+ numpagesread++;
+
+ /* Decrement pages to read */
+ nbpages--;
+
+ /* Increment the NAND address */
+ nandaddress = (uint32_t)(nandaddress + 1U);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Write Page(s) to NAND memory block (8-bits addressing)
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to source buffer to write
+ * @param NumPageToWrite number of pages to write to block
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
+ uint32_t NumPageToWrite)
+{
+ uint32_t index;
+ uint32_t tickstart;
+ uint32_t deviceaddress;
+ uint32_t numpageswritten = 0U;
+ uint32_t nandaddress;
+ uint32_t nbpages = NumPageToWrite;
+ uint8_t *buff = pBuffer;
+
+ /* Check the NAND controller state */
+ if (hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (hnand->State == HAL_NAND_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Identify the device address */
+ deviceaddress = NAND_DEVICE;
+
+ /* NAND raw address calculation */
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+ /* Page(s) write loop */
+ while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ {
+ /* Send write page command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+ __DSB();
+
+ /* Cards with page size <= 512 bytes */
+ if ((hnand->Config.PageSize) <= 512U)
+ {
+ if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ __DSB();
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ __DSB();
+ }
+ }
+ else /* (hnand->Config.PageSize) > 512 */
+ {
+ if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ __DSB();
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ __DSB();
+ }
+ }
+
+ /* Write data to memory */
+ for (index = 0U; index < hnand->Config.PageSize; index++)
+ {
+ *(__IO uint8_t *)deviceaddress = *buff;
+ buff++;
+ __DSB();
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+ __DSB();
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Read status until NAND is ready */
+ while (HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
+ {
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_ERROR;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Increment written pages number */
+ numpageswritten++;
+
+ /* Decrement pages to write */
+ nbpages--;
+
+ /* Increment the NAND address */
+ nandaddress = (uint32_t)(nandaddress + 1U);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Write Page(s) to NAND memory block (16-bits addressing)
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned
+ * @param NumPageToWrite number of pages to write to block
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
+ uint32_t NumPageToWrite)
+{
+ uint32_t index;
+ uint32_t tickstart;
+ uint32_t deviceaddress;
+ uint32_t numpageswritten = 0U;
+ uint32_t nandaddress;
+ uint32_t nbpages = NumPageToWrite;
+ uint16_t *buff = pBuffer;
+
+ /* Check the NAND controller state */
+ if (hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (hnand->State == HAL_NAND_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Identify the device address */
+ deviceaddress = NAND_DEVICE;
+
+ /* NAND raw address calculation */
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+ /* Page(s) write loop */
+ while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ {
+ /* Send write page command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+ __DSB();
+
+ /* Cards with page size <= 512 bytes */
+ if ((hnand->Config.PageSize) <= 512U)
+ {
+ if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ __DSB();
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ __DSB();
+ }
+ }
+ else /* (hnand->Config.PageSize) > 512 */
+ {
+ if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ __DSB();
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ __DSB();
+ }
+ }
+
+ /* Calculate PageSize */
+ if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8)
+ {
+ hnand->Config.PageSize = hnand->Config.PageSize / 2U;
+ }
+ else
+ {
+ /* Do nothing */
+ /* Keep the same PageSize for FMC_NAND_MEM_BUS_WIDTH_16*/
+ }
+
+ /* Write data to memory */
+ for (index = 0U; index < hnand->Config.PageSize; index++)
+ {
+ *(__IO uint16_t *)deviceaddress = *buff;
+ buff++;
+ __DSB();
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+ __DSB();
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Read status until NAND is ready */
+ while (HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
+ {
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_ERROR;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Increment written pages number */
+ numpageswritten++;
+
+ /* Decrement pages to write */
+ nbpages--;
+
+ /* Increment the NAND address */
+ nandaddress = (uint32_t)(nandaddress + 1U);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read Spare area(s) from NAND memory (8-bits addressing)
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to source buffer to write
+ * @param NumSpareAreaToRead Number of spare area to read
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
+ uint32_t NumSpareAreaToRead)
+{
+ uint32_t index;
+ uint32_t tickstart;
+ uint32_t deviceaddress;
+ uint32_t numsparearearead = 0U;
+ uint32_t nandaddress;
+ uint32_t columnaddress;
+ uint32_t nbspare = NumSpareAreaToRead;
+ uint8_t *buff = pBuffer;
+
+ /* Check the NAND controller state */
+ if (hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (hnand->State == HAL_NAND_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Identify the device address */
+ deviceaddress = NAND_DEVICE;
+
+ /* NAND raw address calculation */
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+ /* Column in page address */
+ columnaddress = COLUMN_ADDRESS(hnand);
+
+ /* Spare area(s) read loop */
+ while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ {
+ /* Cards with page size <= 512 bytes */
+ if ((hnand->Config.PageSize) <= 512U)
+ {
+ /* Send read spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
+ __DSB();
+
+ if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ __DSB();
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ __DSB();
+ }
+ }
+ else /* (hnand->Config.PageSize) > 512 */
+ {
+ /* Send read spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ __DSB();
+
+ if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ __DSB();
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ __DSB();
+ }
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+ __DSB();
+
+ if (hnand->Config.ExtraCommandEnable == ENABLE)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Read status until NAND is ready */
+ while (HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
+ {
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_ERROR;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Go back to read mode */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
+ __DSB();
+ }
+
+ /* Get Data into Buffer */
+ for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
+ {
+ *buff = *(uint8_t *)deviceaddress;
+ buff++;
+ }
+
+ /* Increment read spare areas number */
+ numsparearearead++;
+
+ /* Decrement spare areas to read */
+ nbspare--;
+
+ /* Increment the NAND address */
+ nandaddress = (uint32_t)(nandaddress + 1U);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read Spare area(s) from NAND memory (16-bits addressing)
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned.
+ * @param NumSpareAreaToRead Number of spare area to read
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+ uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
+{
+ uint32_t index;
+ uint32_t tickstart;
+ uint32_t deviceaddress;
+ uint32_t numsparearearead = 0U;
+ uint32_t nandaddress;
+ uint32_t columnaddress;
+ uint32_t nbspare = NumSpareAreaToRead;
+ uint16_t *buff = pBuffer;
+
+ /* Check the NAND controller state */
+ if (hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (hnand->State == HAL_NAND_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Identify the device address */
+ deviceaddress = NAND_DEVICE;
+
+ /* NAND raw address calculation */
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+ /* Column in page address */
+ columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand));
+
+ /* Spare area(s) read loop */
+ while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ {
+ /* Cards with page size <= 512 bytes */
+ if ((hnand->Config.PageSize) <= 512U)
+ {
+ /* Send read spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
+ __DSB();
+
+ if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ __DSB();
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ __DSB();
+ }
+ }
+ else /* (hnand->Config.PageSize) > 512 */
+ {
+ /* Send read spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ __DSB();
+
+ if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ __DSB();
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ __DSB();
+ }
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+ __DSB();
+
+ if (hnand->Config.ExtraCommandEnable == ENABLE)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Read status until NAND is ready */
+ while (HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
+ {
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_ERROR;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Go back to read mode */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
+ __DSB();
+ }
+
+ /* Get Data into Buffer */
+ for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
+ {
+ *buff = *(uint16_t *)deviceaddress;
+ buff++;
+ }
+
+ /* Increment read spare areas number */
+ numsparearearead++;
+
+ /* Decrement spare areas to read */
+ nbspare--;
+
+ /* Increment the NAND address */
+ nandaddress = (uint32_t)(nandaddress + 1U);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Write Spare area(s) to NAND memory (8-bits addressing)
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to source buffer to write
+ * @param NumSpareAreaTowrite number of spare areas to write to block
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+ uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
+{
+ uint32_t index;
+ uint32_t tickstart;
+ uint32_t deviceaddress;
+ uint32_t numspareareawritten = 0U;
+ uint32_t nandaddress;
+ uint32_t columnaddress;
+ uint32_t nbspare = NumSpareAreaTowrite;
+ uint8_t *buff = pBuffer;
+
+ /* Check the NAND controller state */
+ if (hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (hnand->State == HAL_NAND_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Identify the device address */
+ deviceaddress = NAND_DEVICE;
+
+ /* Page address calculation */
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+ /* Column in page address */
+ columnaddress = COLUMN_ADDRESS(hnand);
+
+ /* Spare area(s) write loop */
+ while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ {
+ /* Cards with page size <= 512 bytes */
+ if ((hnand->Config.PageSize) <= 512U)
+ {
+ /* Send write Spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+ __DSB();
+
+ if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ __DSB();
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ __DSB();
+ }
+ }
+ else /* (hnand->Config.PageSize) > 512 */
+ {
+ /* Send write Spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+ __DSB();
+
+ if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ __DSB();
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ __DSB();
+ }
+ }
+
+ /* Write data to memory */
+ for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
+ {
+ *(__IO uint8_t *)deviceaddress = *buff;
+ buff++;
+ __DSB();
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+ __DSB();
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Read status until NAND is ready */
+ while (HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
+ {
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_ERROR;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Increment written spare areas number */
+ numspareareawritten++;
+
+ /* Decrement spare areas to write */
+ nbspare--;
+
+ /* Increment the NAND address */
+ nandaddress = (uint32_t)(nandaddress + 1U);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Write Spare area(s) to NAND memory (16-bits addressing)
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned.
+ * @param NumSpareAreaTowrite number of spare areas to write to block
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+ uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
+{
+ uint32_t index;
+ uint32_t tickstart;
+ uint32_t deviceaddress;
+ uint32_t numspareareawritten = 0U;
+ uint32_t nandaddress;
+ uint32_t columnaddress;
+ uint32_t nbspare = NumSpareAreaTowrite;
+ uint16_t *buff = pBuffer;
+
+ /* Check the NAND controller state */
+ if (hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (hnand->State == HAL_NAND_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Identify the device address */
+ deviceaddress = NAND_DEVICE;
+
+ /* NAND raw address calculation */
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+ /* Column in page address */
+ columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand));
+
+ /* Spare area(s) write loop */
+ while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ {
+ /* Cards with page size <= 512 bytes */
+ if ((hnand->Config.PageSize) <= 512U)
+ {
+ /* Send write Spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+ __DSB();
+
+ if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ __DSB();
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ __DSB();
+ }
+ }
+ else /* (hnand->Config.PageSize) > 512 */
+ {
+ /* Send write Spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+ __DSB();
+
+ if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ __DSB();
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ __DSB();
+ }
+ }
+
+ /* Write data to memory */
+ for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
+ {
+ *(__IO uint16_t *)deviceaddress = *buff;
+ buff++;
+ __DSB();
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+ __DSB();
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Read status until NAND is ready */
+ while (HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
+ {
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_ERROR;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Increment written spare areas number */
+ numspareareawritten++;
+
+ /* Decrement spare areas to write */
+ nbspare--;
+
+ /* Increment the NAND address */
+ nandaddress = (uint32_t)(nandaddress + 1U);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief NAND memory Block erase
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress pointer to NAND address structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
+{
+ uint32_t deviceaddress;
+
+ /* Check the NAND controller state */
+ if (hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (hnand->State == HAL_NAND_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Identify the device address */
+ deviceaddress = NAND_DEVICE;
+
+ /* Send Erase block command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+ __DSB();
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1;
+ __DSB();
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Increment the NAND memory address
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress pointer to NAND address structure
+ * @retval The new status of the increment address operation. It can be:
+ * - NAND_VALID_ADDRESS: When the new address is valid address
+ * - NAND_INVALID_ADDRESS: When the new address is invalid address
+ */
+uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
+{
+ uint32_t status = NAND_VALID_ADDRESS;
+
+ /* Increment page address */
+ pAddress->Page++;
+
+ /* Check NAND address is valid */
+ if (pAddress->Page == hnand->Config.BlockSize)
+ {
+ pAddress->Page = 0;
+ pAddress->Block++;
+
+ if (pAddress->Block == hnand->Config.PlaneSize)
+ {
+ pAddress->Block = 0;
+ pAddress->Plane++;
+
+ if (pAddress->Plane == (hnand->Config.PlaneNbr))
+ {
+ status = NAND_INVALID_ADDRESS;
+ }
+ }
+ }
+
+ return (status);
+}
+
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User NAND Callback
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hnand : NAND handle
+ * @param CallbackId : ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_NAND_MSP_INIT_CB_ID NAND MspInit callback ID
+ * @arg @ref HAL_NAND_MSP_DEINIT_CB_ID NAND MspDeInit callback ID
+ * @arg @ref HAL_NAND_IT_CB_ID NAND IT callback ID
+ * @param pCallback : pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId,
+ pNAND_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hnand);
+
+ if (hnand->State == HAL_NAND_STATE_READY)
+ {
+ switch (CallbackId)
+ {
+ case HAL_NAND_MSP_INIT_CB_ID :
+ hnand->MspInitCallback = pCallback;
+ break;
+ case HAL_NAND_MSP_DEINIT_CB_ID :
+ hnand->MspDeInitCallback = pCallback;
+ break;
+ case HAL_NAND_IT_CB_ID :
+ hnand->ItCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hnand->State == HAL_NAND_STATE_RESET)
+ {
+ switch (CallbackId)
+ {
+ case HAL_NAND_MSP_INIT_CB_ID :
+ hnand->MspInitCallback = pCallback;
+ break;
+ case HAL_NAND_MSP_DEINIT_CB_ID :
+ hnand->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hnand);
+ return status;
+}
+
+/**
+ * @brief Unregister a User NAND Callback
+ * NAND Callback is redirected to the weak (surcharged) predefined callback
+ * @param hnand : NAND handle
+ * @param CallbackId : ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_NAND_MSP_INIT_CB_ID NAND MspInit callback ID
+ * @arg @ref HAL_NAND_MSP_DEINIT_CB_ID NAND MspDeInit callback ID
+ * @arg @ref HAL_NAND_IT_CB_ID NAND IT callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hnand);
+
+ if (hnand->State == HAL_NAND_STATE_READY)
+ {
+ switch (CallbackId)
+ {
+ case HAL_NAND_MSP_INIT_CB_ID :
+ hnand->MspInitCallback = HAL_NAND_MspInit;
+ break;
+ case HAL_NAND_MSP_DEINIT_CB_ID :
+ hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
+ break;
+ case HAL_NAND_IT_CB_ID :
+ hnand->ItCallback = HAL_NAND_ITCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hnand->State == HAL_NAND_STATE_RESET)
+ {
+ switch (CallbackId)
+ {
+ case HAL_NAND_MSP_INIT_CB_ID :
+ hnand->MspInitCallback = HAL_NAND_MspInit;
+ break;
+ case HAL_NAND_MSP_DEINIT_CB_ID :
+ hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hnand);
+ return status;
+}
+#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
+ * @brief management functions
+ *
+@verbatim
+ ==============================================================================
+ ##### NAND Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control dynamically
+ the NAND interface.
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Enables dynamically NAND ECC feature.
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
+{
+ /* Check the NAND controller state */
+ if (hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (hnand->State == HAL_NAND_STATE_READY)
+ {
+ /* Update the NAND state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Enable ECC feature */
+ (void)FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
+
+ /* Update the NAND state */
+ hnand->State = HAL_NAND_STATE_READY;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables dynamically FMC_NAND ECC feature.
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
+{
+ /* Check the NAND controller state */
+ if (hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (hnand->State == HAL_NAND_STATE_READY)
+ {
+ /* Update the NAND state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Disable ECC feature */
+ (void)FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
+
+ /* Update the NAND state */
+ hnand->State = HAL_NAND_STATE_READY;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables dynamically NAND ECC feature.
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param ECCval pointer to ECC value
+ * @param Timeout maximum timeout to wait
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check the NAND controller state */
+ if (hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (hnand->State == HAL_NAND_STATE_READY)
+ {
+ /* Update the NAND state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Get NAND ECC value */
+ status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
+
+ /* Update the NAND state */
+ hnand->State = HAL_NAND_STATE_READY;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### NAND State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the NAND controller
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the NAND state
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval HAL state
+ */
+HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
+{
+ return hnand->State;
+}
+
+/**
+ * @brief NAND memory read status
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval NAND status
+ */
+uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
+{
+ uint32_t data;
+ uint32_t deviceaddress;
+ UNUSED(hnand);
+
+ /* Identify the device address */
+ deviceaddress = NAND_DEVICE;
+
+ /* Send Read status operation command */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS;
+
+ /* Read status register data */
+ data = *(__IO uint8_t *)deviceaddress;
+
+ /* Return the status */
+ if ((data & NAND_ERROR) == NAND_ERROR)
+ {
+ return NAND_ERROR;
+ }
+ else if ((data & NAND_READY) == NAND_READY)
+ {
+ return NAND_READY;
+ }
+ else
+ {
+ return NAND_BUSY;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_nor.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_nor.c
new file mode 100644
index 00000000..8486db0d
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_nor.c
@@ -0,0 +1,1512 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_nor.c
+ * @author MCD Application Team
+ * @brief NOR HAL module driver.
+ * This file provides a generic firmware to drive NOR memories mounted
+ * as external device.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This driver is a generic layered driver which contains a set of APIs used to
+ control NOR flash memories. It uses the FMC layer functions to interface
+ with NOR devices. This driver is used as follows:
+
+ (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
+ with control and timing parameters for both normal and extended mode.
+
+ (+) Read NOR flash memory manufacturer code and device IDs using the function
+ HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
+ structure declared by the function caller.
+
+ (+) Access NOR flash memory by read/write data unit operations using the functions
+ HAL_NOR_Read(), HAL_NOR_Program().
+
+ (+) Perform NOR flash erase block/chip operations using the functions
+ HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
+
+ (+) Read the NOR flash CFI (common flash interface) IDs using the function
+ HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
+ structure declared by the function caller.
+
+ (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
+ HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
+
+ (+) You can monitor the NOR device HAL state by calling the function
+ HAL_NOR_GetState()
+ [..]
+ (@) This driver is a set of generic APIs which handle standard NOR flash operations.
+ If a NOR flash device contains different operations and/or implementations,
+ it should be implemented separately.
+
+ *** NOR HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in NOR HAL driver.
+
+ (+) NOR_WRITE : NOR memory write data to specified address
+
+ *** Callback registration ***
+ =============================================
+ [..]
+ The compilation define USE_HAL_NOR_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ Use Functions @ref HAL_NOR_RegisterCallback() to register a user callback,
+ it allows to register following callbacks:
+ (+) MspInitCallback : NOR MspInit.
+ (+) MspDeInitCallback : NOR MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_NOR_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function. It allows to reset following callbacks:
+ (+) MspInitCallback : NOR MspInit.
+ (+) MspDeInitCallback : NOR MspDeInit.
+ This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+ By default, after the @ref HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET
+ all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_NOR_Init
+ and @ref HAL_NOR_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_NOR_Init and @ref HAL_NOR_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_NOR_RegisterCallback before calling @ref HAL_NOR_DeInit
+ or @ref HAL_NOR_Init function.
+
+ When The compilation define USE_HAL_NOR_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+
+/** @defgroup NOR NOR
+ * @brief NOR driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup NOR_Private_Defines NOR Private Defines
+ * @{
+ */
+
+/* Constants to define address to set to write a command */
+#define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
+#define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
+#define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
+#define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
+#define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
+#define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
+#define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
+
+/* Constants to define data to program a command */
+#define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
+#define NOR_CMD_DATA_FIRST (uint16_t)0x00AA
+#define NOR_CMD_DATA_SECOND (uint16_t)0x0055
+#define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
+#define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
+#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
+#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
+#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
+#define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
+#define NOR_CMD_DATA_CFI (uint16_t)0x0098
+
+#define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
+#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
+#define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
+
+#define NOR_CMD_READ_ARRAY (uint16_t)0x00FF
+#define NOR_CMD_WORD_PROGRAM (uint16_t)0x0040
+#define NOR_CMD_BUFFERED_PROGRAM (uint16_t)0x00E8
+#define NOR_CMD_CONFIRM (uint16_t)0x00D0
+#define NOR_CMD_BLOCK_ERASE (uint16_t)0x0020
+#define NOR_CMD_BLOCK_UNLOCK (uint16_t)0x0060
+#define NOR_CMD_READ_STATUS_REG (uint16_t)0x0070
+#define NOR_CMD_CLEAR_STATUS_REG (uint16_t)0x0050
+
+/* Mask on NOR STATUS REGISTER */
+#define NOR_MASK_STATUS_DQ4 (uint16_t)0x0010
+#define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
+#define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
+#define NOR_MASK_STATUS_DQ7 (uint16_t)0x0080
+
+/* Address of the primary command set */
+#define NOR_ADDRESS_COMMAND_SET (uint16_t)0x0013
+
+/* Command set code assignment (defined in JEDEC JEP137B version may 2004) */
+#define NOR_INTEL_SHARP_EXT_COMMAND_SET (uint16_t)0x0001 /* Supported in this driver */
+#define NOR_AMD_FUJITSU_COMMAND_SET (uint16_t)0x0002 /* Supported in this driver */
+#define NOR_INTEL_STANDARD_COMMAND_SET (uint16_t)0x0003 /* Not Supported in this driver */
+#define NOR_AMD_FUJITSU_EXT_COMMAND_SET (uint16_t)0x0004 /* Not Supported in this driver */
+#define NOR_WINDBOND_STANDARD_COMMAND_SET (uint16_t)0x0006 /* Not Supported in this driver */
+#define NOR_MITSUBISHI_STANDARD_COMMAND_SET (uint16_t)0x0100 /* Not Supported in this driver */
+#define NOR_MITSUBISHI_EXT_COMMAND_SET (uint16_t)0x0101 /* Not Supported in this driver */
+#define NOR_PAGE_WRITE_COMMAND_SET (uint16_t)0x0102 /* Not Supported in this driver */
+#define NOR_INTEL_PERFORMANCE_COMMAND_SET (uint16_t)0x0200 /* Not Supported in this driver */
+#define NOR_INTEL_DATA_COMMAND_SET (uint16_t)0x0210 /* Not Supported in this driver */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup NOR_Private_Variables NOR Private Variables
+ * @{
+ */
+
+static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B;
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup NOR_Exported_Functions NOR Exported Functions
+ * @{
+ */
+
+/** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### NOR Initialization and de_initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to initialize/de-initialize
+ the NOR memory
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Perform the NOR memory Initialization sequence
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param Timing pointer to NOR control timing structure
+ * @param ExtTiming pointer to NOR extended mode timing structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing,
+ FMC_NORSRAM_TimingTypeDef *ExtTiming)
+{
+ uint32_t deviceaddress;
+
+ /* Check the NOR handle parameter */
+ if (hnor == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ if (hnor->State == HAL_NOR_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hnor->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+ if (hnor->MspInitCallback == NULL)
+ {
+ hnor->MspInitCallback = HAL_NOR_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hnor->MspInitCallback(hnor);
+#else
+ /* Initialize the low level hardware (MSP) */
+ HAL_NOR_MspInit(hnor);
+#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
+ }
+
+ /* Initialize NOR control Interface */
+ (void)FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
+
+ /* Initialize NOR timing Interface */
+ (void)FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
+
+ /* Initialize NOR extended mode timing Interface */
+ (void)FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
+
+ /* Enable the NORSRAM device */
+ __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
+
+ /* Initialize NOR Memory Data Width*/
+ if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8)
+ {
+ uwNORMemoryDataWidth = NOR_MEMORY_8B;
+ }
+ else
+ {
+ uwNORMemoryDataWidth = NOR_MEMORY_16B;
+ }
+
+ /* Enable FMC Peripheral */
+ __FMC_ENABLE();
+
+ /* Initialize the NOR controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Get the value of the command set */
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
+ hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET);
+
+ return HAL_NOR_ReturnToReadMode(hnor);
+}
+
+/**
+ * @brief Perform NOR memory De-Initialization sequence
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
+{
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+ if (hnor->MspDeInitCallback == NULL)
+ {
+ hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
+ }
+
+ /* DeInit the low level hardware */
+ hnor->MspDeInitCallback(hnor);
+#else
+ /* De-Initialize the low level hardware (MSP) */
+ HAL_NOR_MspDeInit(hnor);
+#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
+
+ /* Configure the NOR registers with their reset values */
+ (void)FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
+
+ /* Reset the NOR controller state */
+ hnor->State = HAL_NOR_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief NOR MSP Init
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @retval None
+ */
+__weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hnor);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_NOR_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief NOR MSP DeInit
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @retval None
+ */
+__weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hnor);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_NOR_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief NOR MSP Wait for Ready/Busy signal
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param Timeout Maximum timeout value
+ * @retval None
+ */
+__weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hnor);
+ UNUSED(Timeout);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_NOR_MspWait could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
+ * @brief Input Output and memory control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### NOR Input and Output functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to use and control the NOR memory
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Read NOR flash IDs
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param pNOR_ID pointer to NOR ID structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
+{
+ uint32_t deviceaddress;
+ HAL_NOR_StateTypeDef state;
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the NOR controller state */
+ state = hnor->State;
+ if (state == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Send read ID command */
+ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
+ }
+ else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+ {
+ NOR_WRITE(deviceaddress, NOR_CMD_DATA_AUTO_SELECT);
+ }
+ else
+ {
+ /* Primary command set not supported by the driver */
+ status = HAL_ERROR;
+ }
+
+ if (status != HAL_ERROR)
+ {
+ /* Read the NOR IDs */
+ pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
+ pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth,
+ DEVICE_CODE1_ADDR);
+ pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth,
+ DEVICE_CODE2_ADDR);
+ pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth,
+ DEVICE_CODE3_ADDR);
+ }
+
+ /* Check the NOR controller state */
+ hnor->State = state;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Returns the NOR memory to Read mode.
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
+{
+ uint32_t deviceaddress;
+ HAL_NOR_StateTypeDef state;
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the NOR controller state */
+ state = hnor->State;
+ if (state == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+ {
+ NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
+ }
+ else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+ {
+ NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY);
+ }
+ else
+ {
+ /* Primary command set not supported by the driver */
+ status = HAL_ERROR;
+ }
+
+ /* Check the NOR controller state */
+ hnor->State = state;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Read data from NOR memory
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param pAddress pointer to Device address
+ * @param pData pointer to read data
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
+{
+ uint32_t deviceaddress;
+ HAL_NOR_StateTypeDef state;
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the NOR controller state */
+ state = hnor->State;
+ if (state == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Send read data command */
+ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
+ }
+ else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+ {
+ NOR_WRITE(pAddress, NOR_CMD_READ_ARRAY);
+ }
+ else
+ {
+ /* Primary command set not supported by the driver */
+ status = HAL_ERROR;
+ }
+
+ if (status != HAL_ERROR)
+ {
+ /* Read the data */
+ *pData = (uint16_t)(*(__IO uint32_t *)pAddress);
+ }
+
+ /* Check the NOR controller state */
+ hnor->State = state;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Program data to NOR memory
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param pAddress Device address
+ * @param pData pointer to the data to write
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
+{
+ uint32_t deviceaddress;
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the NOR controller state */
+ if (hnor->State == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (hnor->State == HAL_NOR_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Send program data command */
+ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
+ }
+ else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+ {
+ NOR_WRITE(pAddress, NOR_CMD_WORD_PROGRAM);
+ }
+ else
+ {
+ /* Primary command set not supported by the driver */
+ status = HAL_ERROR;
+ }
+
+ if (status != HAL_ERROR)
+ {
+ /* Write the data */
+ NOR_WRITE(pAddress, *pData);
+ }
+
+ /* Check the NOR controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Reads a half-word buffer from the NOR memory.
+ * @param hnor pointer to the NOR handle
+ * @param uwAddress NOR memory internal address to read from.
+ * @param pData pointer to the buffer that receives the data read from the
+ * NOR memory.
+ * @param uwBufferSize number of Half word to read.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
+ uint32_t uwBufferSize)
+{
+ uint32_t deviceaddress;
+ uint32_t size = uwBufferSize;
+ uint32_t address = uwAddress;
+ uint16_t *data = pData;
+ HAL_NOR_StateTypeDef state;
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the NOR controller state */
+ state = hnor->State;
+ if (state == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Send read data command */
+ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
+ }
+ else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+ {
+ NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY);
+ }
+ else
+ {
+ /* Primary command set not supported by the driver */
+ status = HAL_ERROR;
+ }
+
+ if (status != HAL_ERROR)
+ {
+ /* Read buffer */
+ while (size > 0U)
+ {
+ *data = *(__IO uint16_t *)address;
+ data++;
+ address += 2U;
+ size--;
+ }
+ }
+
+ /* Check the NOR controller state */
+ hnor->State = state;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Writes a half-word buffer to the NOR memory. This function must be used
+ only with S29GL128P NOR memory.
+ * @param hnor pointer to the NOR handle
+ * @param uwAddress NOR memory internal start write address
+ * @param pData pointer to source data buffer.
+ * @param uwBufferSize Size of the buffer to write
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
+ uint32_t uwBufferSize)
+{
+ uint16_t *p_currentaddress;
+ const uint16_t *p_endaddress;
+ uint16_t *data = pData;
+ uint32_t deviceaddress;
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the NOR controller state */
+ if (hnor->State == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (hnor->State == HAL_NOR_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Initialize variables */
+ p_currentaddress = (uint16_t *)(deviceaddress + uwAddress);
+ p_endaddress = (uint16_t *)(deviceaddress + uwAddress + (2U * (uwBufferSize - 1U)));
+
+ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+ {
+ /* Issue unlock command sequence */
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+
+ /* Write Buffer Load Command */
+ NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
+ NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U));
+ }
+ else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+ {
+ /* Write Buffer Load Command */
+ NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_BUFFERED_PROGRAM);
+ NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U));
+ }
+ else
+ {
+ /* Primary command set not supported by the driver */
+ status = HAL_ERROR;
+ }
+
+ if (status != HAL_ERROR)
+ {
+ /* Load Data into NOR Buffer */
+ while (p_currentaddress <= p_endaddress)
+ {
+ NOR_WRITE(p_currentaddress, *data);
+
+ data++;
+ p_currentaddress ++;
+ }
+
+ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+ {
+ NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
+ }
+ else /* => hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET */
+ {
+ NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_CONFIRM);
+ }
+ }
+
+ /* Check the NOR controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return status;
+
+}
+
+/**
+ * @brief Erase the specified block of the NOR memory
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param BlockAddress Block to erase address
+ * @param Address Device address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
+{
+ uint32_t deviceaddress;
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the NOR controller state */
+ if (hnor->State == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (hnor->State == HAL_NOR_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Send block erase command sequence */
+ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
+ NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
+ NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
+ NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+ NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
+ }
+ else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+ {
+ NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_UNLOCK);
+ NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM);
+ NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_ERASE);
+ NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM);
+ }
+ else
+ {
+ /* Primary command set not supported by the driver */
+ status = HAL_ERROR;
+ }
+
+ /* Check the NOR memory status and update the controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return status;
+
+}
+
+/**
+ * @brief Erase the entire NOR chip.
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param Address Device address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
+{
+ uint32_t deviceaddress;
+ HAL_StatusTypeDef status = HAL_OK;
+ UNUSED(Address);
+
+ /* Check the NOR controller state */
+ if (hnor->State == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (hnor->State == HAL_NOR_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Send NOR chip erase command sequence */
+ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
+ NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
+ NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
+ NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
+ }
+ else
+ {
+ /* Primary command set not supported by the driver */
+ status = HAL_ERROR;
+ }
+
+ /* Check the NOR memory status and update the controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Read NOR flash CFI IDs
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param pNOR_CFI pointer to NOR CFI IDs structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
+{
+ uint32_t deviceaddress;
+ HAL_NOR_StateTypeDef state;
+
+ /* Check the NOR controller state */
+ state = hnor->State;
+ if (state == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Send read CFI query command */
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
+
+ /* read the NOR CFI information */
+ pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
+ pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
+ pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
+ pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
+
+ /* Check the NOR controller state */
+ hnor->State = state;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User NOR Callback
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hnor : NOR handle
+ * @param CallbackId : ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_NOR_MSP_INIT_CB_ID NOR MspInit callback ID
+ * @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID
+ * @param pCallback : pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId,
+ pNOR_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ HAL_NOR_StateTypeDef state;
+
+ if (pCallback == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hnor);
+
+ state = hnor->State;
+ if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
+ {
+ switch (CallbackId)
+ {
+ case HAL_NOR_MSP_INIT_CB_ID :
+ hnor->MspInitCallback = pCallback;
+ break;
+ case HAL_NOR_MSP_DEINIT_CB_ID :
+ hnor->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hnor);
+ return status;
+}
+
+/**
+ * @brief Unregister a User NOR Callback
+ * NOR Callback is redirected to the weak (surcharged) predefined callback
+ * @param hnor : NOR handle
+ * @param CallbackId : ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_NOR_MSP_INIT_CB_ID NOR MspInit callback ID
+ * @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ HAL_NOR_StateTypeDef state;
+
+ /* Process locked */
+ __HAL_LOCK(hnor);
+
+ state = hnor->State;
+ if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
+ {
+ switch (CallbackId)
+ {
+ case HAL_NOR_MSP_INIT_CB_ID :
+ hnor->MspInitCallback = HAL_NOR_MspInit;
+ break;
+ case HAL_NOR_MSP_DEINIT_CB_ID :
+ hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hnor);
+ return status;
+}
+#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
+
+/**
+ * @}
+ */
+
+/** @defgroup NOR_Exported_Functions_Group3 NOR Control functions
+ * @brief management functions
+ *
+@verbatim
+ ==============================================================================
+ ##### NOR Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control dynamically
+ the NOR interface.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables dynamically NOR write operation.
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
+{
+ /* Check the NOR controller state */
+ if (hnor->State == HAL_NOR_STATE_PROTECTED)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Enable write operation */
+ (void)FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables dynamically NOR write operation.
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
+{
+ /* Check the NOR controller state */
+ if (hnor->State == HAL_NOR_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Disable write operation */
+ (void)FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_PROTECTED;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup NOR_Exported_Functions_Group4 NOR State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### NOR State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the NOR controller
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the NOR controller state
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @retval NOR controller state
+ */
+HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
+{
+ return hnor->State;
+}
+
+/**
+ * @brief Returns the NOR operation status.
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param Address Device address
+ * @param Timeout NOR programming Timeout
+ * @retval NOR_Status The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
+ * or HAL_NOR_STATUS_TIMEOUT
+ */
+HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
+{
+ HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
+ uint16_t tmpsr1;
+ uint16_t tmpsr2;
+ uint32_t tickstart;
+
+ /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
+ HAL_NOR_MspWait(hnor, Timeout);
+
+ /* Get the NOR memory operation status -------------------------------------*/
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+ {
+ while ((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ status = HAL_NOR_STATUS_TIMEOUT;
+ }
+ }
+
+ /* Read NOR status register (DQ6 and DQ5) */
+ tmpsr1 = *(__IO uint16_t *)Address;
+ tmpsr2 = *(__IO uint16_t *)Address;
+
+ /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
+ if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6))
+ {
+ return HAL_NOR_STATUS_SUCCESS ;
+ }
+
+ if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
+ {
+ status = HAL_NOR_STATUS_ONGOING;
+ }
+
+ tmpsr1 = *(__IO uint16_t *)Address;
+ tmpsr2 = *(__IO uint16_t *)Address;
+
+ /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
+ if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6))
+ {
+ return HAL_NOR_STATUS_SUCCESS;
+ }
+ if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
+ {
+ return HAL_NOR_STATUS_ERROR;
+ }
+ }
+ }
+ else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+ {
+ do
+ {
+ NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
+ tmpsr2 = *(__IO uint16_t *)(Address);
+
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ return HAL_NOR_STATUS_TIMEOUT;
+ }
+ }
+ } while ((tmpsr2 & NOR_MASK_STATUS_DQ7) == 0U);
+
+ NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
+ tmpsr1 = *(__IO uint16_t *)(Address);
+ if ((tmpsr1 & (NOR_MASK_STATUS_DQ5 | NOR_MASK_STATUS_DQ4)) != 0U)
+ {
+ /* Clear the Status Register */
+ NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
+ status = HAL_NOR_STATUS_ERROR;
+ }
+ else
+ {
+ status = HAL_NOR_STATUS_SUCCESS;
+ }
+ }
+ else
+ {
+ /* Primary command set not supported by the driver */
+ status = HAL_NOR_STATUS_ERROR;
+ }
+
+ /* Return the operation status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_opamp.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_opamp.c
new file mode 100644
index 00000000..fb760979
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_opamp.c
@@ -0,0 +1,1183 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_opamp.c
+ * @author MCD Application Team
+ * @brief OPAMP HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the operational amplifier(s) peripheral:
+ * + OPAMP configuration
+ * + OPAMP calibration
+ * Thanks to
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ===============================================================================
+ ##### OPAMP Peripheral Features #####
+ ==============================================================================
+
+ [..] The device integrates 1 or 2 operational amplifiers OPAMP1 & OPAMP2
+
+ (#) The OPAMP(s) provide(s) several exclusive running modes.
+ (++) Standalone mode
+ (++) Programmable Gain Amplifier (PGA) mode (Resistor feedback output)
+ (++) Follower mode
+
+ (#) Each OPAMP(s) can be configured in normal and low power mode with different speeds.
+
+ (#) The OPAMP(s) provide(s) calibration capabilities.
+ (++) Calibration aims at correcting some offset for running mode.
+ (++) The OPAMP uses either factory calibration settings OR user defined
+ calibration (trimming) settings (i.e. trimming mode).
+ (++) The user defined settings can be figured out using self calibration
+ handled by HAL_OPAMP_SelfCalibrate, HAL_OPAMPEx_SelfCalibrateAll
+ (++) HAL_OPAMP_SelfCalibrate:
+ (+++) Runs automatically the calibration.
+ (+++) Enables the user trimming mode
+ (+++) Updates the init structure with trimming values with fresh calibration
+ results.
+ The user may store the calibration results for larger
+ (ex monitoring the trimming as a function of temperature for instance)
+ (+++) HAL_OPAMPEx_SelfCalibrateAll
+ runs calibration of all OPAMPs in parallel to save search time.
+
+ (#) Running mode: Standalone mode
+ (++) Gain is set externally (gain depends on external loads).
+ (++) Follower mode also possible externally by connecting the inverting input to
+ the output.
+
+ (#) Running mode: Follower mode
+ (++) No Inverting Input is connected.
+
+ (#) Running mode: Programmable Gain Amplifier (PGA) mode
+ (Resistor feedback output)
+ (++) The OPAMP(s) output(s) can be internally connected to resistor feedback
+ output.
+ (++) OPAMP gain is either 2, 4, 8 or 16.
+
+ (#) The OPAMPs inverting input can be selected according to the Reference Manual
+ "OPAMP function description" chapter.
+
+ (#) The OPAMPs non inverting input can be selected according to the Reference Manual
+ "OPAMP function description" chapter.
+
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+
+ *** Speed & power mode ***
+ ============================================
+ [..] To run in low power mode with different speed:
+
+ (#) Configure the OPAMP using HAL_OPAMP_Init() function:
+ (++) Select OPAMP_POWERMODE_LOWPOWER_NORMALSPEED
+ (++) Select OPAMP_POWERMODE_LOWPOWER_HIGHSPEED
+ (++) Select OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED
+ (++) Select OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED
+
+ *** Calibration ***
+ ============================================
+ [..] To run the OPAMP calibration self calibration:
+
+ (#) Start calibration using HAL_OPAMP_SelfCalibrate.
+ Store the calibration results.
+
+ *** Running mode ***
+ ============================================
+
+ [..] To use the OPAMP, perform the following steps:
+
+ (#) Fill in the HAL_OPAMP_MspInit() to
+ (++) Enable the OPAMP Peripheral clock using macro __HAL_RCC_OPAMP_CLK_ENABLE()
+ (++) Configure the OPAMP input and output in analog mode using
+ HAL_GPIO_Init() to map the OPAMP output to the GPIO pin.
+
+ (#) Registrate Callbacks
+ (++) The compilation define USE_HAL_OPAMP_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ (++) Use Functions @ref HAL_OPAMP_RegisterCallback() to register a user callback,
+ it allows to register following callbacks:
+ (+++) MspInitCallback : OPAMP MspInit.
+ (+++) MspDeInitCallback : OPAMP MspFeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ (++) Use function @ref HAL_OPAMP_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function. It allows to reset following callbacks:
+ (+++) MspInitCallback : OPAMP MspInit.
+ (+++) MspDeInitCallback : OPAMP MspdeInit.
+ (+++) All Callbacks
+
+ (#) Configure the OPAMP using HAL_OPAMP_Init() function:
+ (++) Select the mode
+ (++) Select the inverting input
+ (++) Select the non-inverting input
+ (++) If PGA mode is enabled, Select if inverting input is connected.
+ (++) Select either factory or user defined trimming mode.
+ (++) If the user-defined trimming mode is enabled, select PMOS & NMOS trimming values
+ (typically values set by HAL_OPAMP_SelfCalibrate function).
+
+ (#) Enable the OPAMP using HAL_OPAMP_Start() function.
+
+ (#) Disable the OPAMP using HAL_OPAMP_Stop() function.
+
+ (#) Lock the OPAMP in running mode using HAL_OPAMP_Lock() function.
+ Caution: On STM32U5, HAL OPAMP lock is software lock only (not
+ hardware lock as on some other STM32 devices)
+
+ (#) If needed, unlock the OPAMP using HAL_OPAMPEx_Unlock() function.
+
+ *** Running mode: change of configuration while OPAMP ON ***
+ ============================================
+ [..] To Re-configure OPAMP when OPAMP is ON (change on the fly)
+ (#) If needed, fill in the HAL_OPAMP_MspInit()
+ (++) This is the case for instance if you wish to use new OPAMP I/O
+
+ (#) Configure the OPAMP using HAL_OPAMP_Init() function:
+ (++) As in configure case, select first the parameters you wish to modify.
+
+ (#) Change from low power mode to normal power mode (& vice versa) requires
+ first HAL_OPAMP_DeInit() (force OPAMP OFF) and then HAL_OPAMP_Init().
+ In other words, of OPAMP is ON, HAL_OPAMP_Init can NOT change power mode
+ alone.
+
+ @endverbatim
+ ******************************************************************************
+
+ Table 1. OPAMPs inverting/non-inverting inputs for the STM32U5 devices:
+ +------------------------------------------------------------------------|
+ | | | OPAMP1 | OPAMP2 |
+ |-----------------|---------|----------------------|---------------------|
+ | Inverting Input | VM_SEL | | |
+ | | | IO0-> PA1 | IO0-> PA7 |
+ | | | LOW LEAKAGE IO (2) | LOW LEAKAGE IO (2) |
+ | | | Not connected | Not connected |
+ | (1) | | PGA mode only | PGA mode only |
+ |-----------------|---------|----------------------|---------------------|
+ | Non Inverting | VP_SEL | | |
+ | | | IO0-> PA0 (GPIO) | IO0-> PA6 (GPIO) |
+ | Input | | DAC1_OUT1 internal | DAC1_OUT2 internal |
+ +------------------------------------------------------------------------|
+ (1): NA in follower mode.
+ (2): Available on some package only (ex: BGA132 and BGA169).
+
+
+ Table 2. OPAMPs outputs for the STM32U5 devices:
+
+ +-------------------------------------------------------------------------------+
+ | | | OPAMP1 | OPAMP2 |
+ |-----------------|--------|-----------------------|----------------------------|
+ | Output | VOUT | - PA3 | - PB0 |
+ | | | - ADC1_IN8 if | - ADC1_IN15 & ADC4_IN18 if |
+ | | | connected internally | connected internally |
+ |-----------------|--------|-----------------------|----------------------------|
+
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup OPAMP OPAMP
+ * @brief OPAMP module driver
+ * @{
+ */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup OPAMP_Private_Constants
+ * @{
+ */
+
+/* CSR register reset value */
+#define OPAMP_CSR_RESET_VALUE ((uint32_t)0x00000000)
+
+#define OPAMP_CSR_RESET_BITS (OPAMP_CSR_OPAEN | OPAMP_CSR_OPALPM | OPAMP_CSR_OPAMODE |\
+ OPAMP_CSR_PGA_GAIN | OPAMP_CSR_VM_SEL | OPAMP_CSR_VP_SEL |\
+ OPAMP_CSR_CALON | OPAMP_CSR_USERTRIM | OPAMP_CSR_CALSEL |\
+ OPAMP_CSR_HSM)
+
+/* CSR Init masks */
+#define OPAMP_CSR_INIT_MASK_PGA (OPAMP_CSR_OPALPM | OPAMP_CSR_OPAMODE| OPAMP_CSR_PGA_GAIN |\
+ OPAMP_CSR_VM_SEL | OPAMP_CSR_VP_SEL | OPAMP_CSR_USERTRIM |\
+ OPAMP_CSR_HSM)
+
+#define OPAMP_CSR_INIT_MASK_FOLLOWER (OPAMP_CSR_OPALPM | OPAMP_CSR_OPAMODE| OPAMP_CSR_VP_SEL |\
+ OPAMP_CSR_USERTRIM | OPAMP_CSR_HSM)
+
+#define OPAMP_CSR_INIT_MASK_STANDALONE (OPAMP_CSR_OPALPM | OPAMP_CSR_OPAMODE| OPAMP_CSR_VP_SEL |\
+ OPAMP_CSR_VM_SEL | OPAMP_CSR_USERTRIM | OPAMP_CSR_HSM)
+
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup OPAMP_Exported_Functions OPAMP Exported Functions
+ * @{
+ */
+
+/** @defgroup OPAMP_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the OPAMP according to the specified
+ * parameters in the OPAMP_InitTypeDef and initialize the associated handle.
+ * @note If the selected opamp is locked, initialization can't be performed.
+ * To unlock the configuration, perform a system reset.
+ * @param hopamp: OPAMP handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t updateotrlpotr;
+
+ /* Check the OPAMP handle allocation and lock status */
+ /* Init not allowed if calibration is ongoing */
+ if (hopamp == NULL)
+ {
+ return HAL_ERROR;
+ }
+ else if (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)
+ {
+ return HAL_ERROR;
+ }
+ else if (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Check the parameter */
+ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
+
+ /* Set OPAMP parameters */
+ assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode));
+ assert_param(IS_OPAMP_FUNCTIONAL_NORMALMODE(hopamp->Init.Mode));
+ assert_param(IS_OPAMP_NONINVERTING_INPUT(hopamp->Init.NonInvertingInput));
+
+#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
+ if (hopamp->State == HAL_OPAMP_STATE_RESET)
+ {
+ if (hopamp->MspInitCallback == NULL)
+ {
+ hopamp->MspInitCallback = HAL_OPAMP_MspInit;
+ }
+ }
+#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
+
+ if ((hopamp->Init.Mode) == OPAMP_STANDALONE_MODE)
+ {
+ assert_param(IS_OPAMP_INVERTING_INPUT_STANDALONE(hopamp->Init.InvertingInput));
+ }
+
+ if ((hopamp->Init.Mode) == OPAMP_PGA_MODE)
+ {
+ assert_param(IS_OPAMP_INVERTING_INPUT_PGA(hopamp->Init.InvertingInput));
+ }
+
+ if ((hopamp->Init.Mode) == OPAMP_PGA_MODE)
+ {
+ assert_param(IS_OPAMP_PGA_GAIN(hopamp->Init.PgaGain));
+ }
+
+ assert_param(IS_OPAMP_TRIMMING(hopamp->Init.UserTrimming));
+ if ((hopamp->Init.UserTrimming) == OPAMP_TRIMMING_USER)
+ {
+ if ((hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED) || \
+ (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED))
+ {
+ assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueP));
+ assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueN));
+ }
+ else
+ {
+ assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValuePLowPower));
+ assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueNLowPower));
+ }
+ }
+
+ if (hopamp->State == HAL_OPAMP_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hopamp->Lock = HAL_UNLOCKED;
+ }
+
+#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
+ hopamp->MspInitCallback(hopamp);
+#else
+ /* Call MSP init function */
+ HAL_OPAMP_MspInit(hopamp);
+#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
+
+ /* Set operating mode */
+ CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALON);
+
+ if (hopamp->Init.Mode == OPAMP_PGA_MODE)
+ {
+ MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_INIT_MASK_PGA, \
+ hopamp->Init.PowerMode | \
+ hopamp->Init.Mode | \
+ hopamp->Init.PgaGain | \
+ hopamp->Init.InvertingInput | \
+ hopamp->Init.NonInvertingInput | \
+ hopamp->Init.UserTrimming);
+ }
+
+ if (hopamp->Init.Mode == OPAMP_FOLLOWER_MODE)
+ {
+ /* In Follower mode InvertingInput is Not Applicable */
+ MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_INIT_MASK_FOLLOWER, \
+ hopamp->Init.PowerMode | \
+ hopamp->Init.Mode | \
+ hopamp->Init.NonInvertingInput | \
+ hopamp->Init.UserTrimming);
+ }
+
+ if (hopamp->Init.Mode == OPAMP_STANDALONE_MODE)
+ {
+ MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_INIT_MASK_STANDALONE, \
+ hopamp->Init.PowerMode | \
+ hopamp->Init.Mode | \
+ hopamp->Init.InvertingInput | \
+ hopamp->Init.NonInvertingInput | \
+ hopamp->Init.UserTrimming);
+ }
+
+ if (hopamp->Init.UserTrimming == OPAMP_TRIMMING_USER)
+ {
+ /* Set power mode and associated calibration parameters */
+ if ((hopamp->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER_NORMALSPEED) && \
+ (hopamp->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER_HIGHSPEED))
+ {
+ /* OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED or OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED */
+ /* Set calibration mode (factory or user) and values for */
+ /* transistors differential pair high (PMOS) and low (NMOS) for */
+ /* normal mode. */
+ updateotrlpotr = (((hopamp->Init.TrimmingValueP) << (OPAMP_INPUT_NONINVERTING)) \
+ | (hopamp->Init.TrimmingValueN));
+ MODIFY_REG(hopamp->Instance->OTR, OPAMP_OTR_TRIMOFFSETN | OPAMP_OTR_TRIMOFFSETP, updateotrlpotr);
+ }
+ else
+ {
+ /* OPAMP_POWERMODE_LOWPOWER_HIGHSPEED or OPAMP_POWERMODE_LOWPOWER_NORMALSPEED */
+ /* transistors differential pair high (PMOS) and low (NMOS) for */
+ /* low power mode. */
+ updateotrlpotr = (((hopamp->Init.TrimmingValuePLowPower) << (OPAMP_INPUT_NONINVERTING)) \
+ | (hopamp->Init.TrimmingValueNLowPower));
+ MODIFY_REG(hopamp->Instance->LPOTR, OPAMP_OTR_TRIMOFFSETN | OPAMP_OTR_TRIMOFFSETP, updateotrlpotr);
+ }
+ }
+
+ /* Set the power supply range to high for performance purpose */
+ /* The OPAMP_CSR_OPARANGE is common configuration for all OPAMPs */
+ /* bit OPAMP_CSR_OPARANGE applies for both OPAMPs */
+ MODIFY_REG(OPAMP1->CSR, OPAMP_CSR_OPARANGE, OPAMP_CSR_OPARANGE);
+
+ /* Update the OPAMP state*/
+ if (hopamp->State == HAL_OPAMP_STATE_RESET)
+ {
+ /* From RESET state to READY State */
+ hopamp->State = HAL_OPAMP_STATE_READY;
+ }
+ /* else: remain in READY or BUSY state (no update) */
+ return status;
+ }
+}
+
+/**
+ * @brief DeInitialize the OPAMP peripheral.
+ * @note Deinitialization can be performed if the OPAMP configuration is locked.
+ * (the lock is SW in U5)
+ * @param hopamp: OPAMP handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_OPAMP_DeInit(OPAMP_HandleTypeDef *hopamp)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the OPAMP handle allocation */
+ /* DeInit not allowed if calibration is ongoing */
+ if (hopamp == NULL)
+ {
+ status = HAL_ERROR;
+ }
+ else if (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check the parameter */
+ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
+
+ /* Set OPAMP_CSR register to reset value */
+ /* Mind that OPAMP1_CSR_OPARANGE of CSR of OPAMP1 remains unchanged (applies to both OPAMPs) */
+ /* OPAMP shall be disabled first separately */
+ CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_OPAEN);
+ MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_RESET_BITS, OPAMP_CSR_RESET_VALUE);
+
+#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
+ if (hopamp->MspDeInitCallback == NULL)
+ {
+ hopamp->MspDeInitCallback = HAL_OPAMP_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ hopamp->MspDeInitCallback(hopamp);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK and NVIC */
+ HAL_OPAMP_MspDeInit(hopamp);
+#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
+ /* Update the OPAMP state*/
+ hopamp->State = HAL_OPAMP_STATE_RESET;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hopamp);
+ }
+ return status;
+}
+
+/**
+ * @brief Initialize the OPAMP MSP.
+ * @param hopamp: OPAMP handle
+ * @retval None
+ */
+__weak void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef *hopamp)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hopamp);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the function "HAL_OPAMP_MspInit()" must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief DeInitialize OPAMP MSP.
+ * @param hopamp: OPAMP handle
+ * @retval None
+ */
+__weak void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hopamp);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the function "HAL_OPAMP_MspDeInit()" must be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup OPAMP_Exported_Functions_Group2 IO operation functions
+ * @brief IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the OPAMP
+ start, stop and calibration actions.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start the OPAMP.
+ * @param hopamp: OPAMP handle
+ * @retval HAL status
+ */
+
+HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the OPAMP handle allocation */
+ /* Check if OPAMP locked */
+ if (hopamp == NULL)
+ {
+ status = HAL_ERROR;
+ }
+ else if (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check the parameter */
+ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
+
+ if (hopamp->State == HAL_OPAMP_STATE_READY)
+ {
+ /* Enable the selected opamp */
+ SET_BIT(hopamp->Instance->CSR, OPAMP_CSR_OPAEN);
+
+ /* Update the OPAMP state*/
+ /* From HAL_OPAMP_STATE_READY to HAL_OPAMP_STATE_BUSY */
+ hopamp->State = HAL_OPAMP_STATE_BUSY;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+
+ }
+ return status;
+}
+
+/**
+ * @brief Stop the OPAMP.
+ * @param hopamp: OPAMP handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the OPAMP handle allocation */
+ /* Check if OPAMP locked */
+ /* Check if OPAMP calibration ongoing */
+ if (hopamp == NULL)
+ {
+ status = HAL_ERROR;
+ }
+ else if (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)
+ {
+ status = HAL_ERROR;
+ }
+ else if (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check the parameter */
+ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
+
+ if (hopamp->State == HAL_OPAMP_STATE_BUSY)
+ {
+ /* Disable the selected opamp */
+ CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_OPAEN);
+
+ /* Update the OPAMP state*/
+ /* From HAL_OPAMP_STATE_BUSY to HAL_OPAMP_STATE_READY*/
+ hopamp->State = HAL_OPAMP_STATE_READY;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ }
+ return status;
+}
+
+/**
+ * @brief Run the self calibration of one OPAMP.
+ * @note Calibration is performed in the mode specified in OPAMP init
+ * structure (mode normal or low-power). To perform calibration for
+ * both modes, repeat this function twice after OPAMP init structure
+ * accordingly updated.
+ * @note Calibration runs about 10 ms.
+ * @param hopamp handle
+ * @retval Updated offset trimming values (PMOS & NMOS), user trimming is enabled
+ * @retval HAL status
+
+ */
+
+HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp)
+{
+
+ HAL_StatusTypeDef status = HAL_OK;
+
+ uint32_t trimmingvaluen;
+ uint32_t trimmingvaluep;
+ uint32_t delta;
+ uint32_t opampmode;
+
+ __IO uint32_t *tmp_opamp_reg_trimming; /* Selection of register of trimming depending on power mode: OTR or LPOTR */
+
+ /* Check the OPAMP handle allocation */
+ /* Check if OPAMP locked */
+ if (hopamp == NULL)
+ {
+ status = HAL_ERROR;
+ }
+ else if (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check if OPAMP in calibration mode and calibration not yet enable */
+ if (hopamp->State == HAL_OPAMP_STATE_READY)
+ {
+ /* Check the parameter */
+ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
+ assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode));
+
+ /* Save OPAMP mode as in */
+ /* the calibration is not working in PGA mode */
+ opampmode = READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_OPAMODE);
+
+ /* Use of standalone mode */
+ MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_OPAMODE, OPAMP_STANDALONE_MODE);
+
+ /* user trimming values are used for offset calibration */
+ SET_BIT(hopamp->Instance->CSR, OPAMP_CSR_USERTRIM);
+
+ /* Select trimming settings depending on power mode */
+ if ((hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED) || \
+ (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED))
+ {
+ tmp_opamp_reg_trimming = &hopamp->Instance->OTR;
+ }
+ else
+ {
+ tmp_opamp_reg_trimming = &hopamp->Instance->LPOTR;
+ }
+
+ /* Enable calibration */
+ SET_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALON);
+
+ /* 1st calibration - N */
+ CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALSEL);
+
+ /* Enable the selected opamp */
+ SET_BIT(hopamp->Instance->CSR, OPAMP_CSR_OPAEN);
+
+ /* Init trimming counter */
+ /* Medium value */
+ trimmingvaluen = 16U;
+ delta = 8U;
+
+ while (delta != 0U)
+ {
+ /* Set candidate trimming */
+ /* OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED or OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED */
+ MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen);
+
+ /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */
+ /* Offset trim time: during calibration, minimum time needed between */
+ /* two steps to have 1 mV accuracy */
+ HAL_Delay(OPAMP_TRIMMING_DELAY);
+
+ if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT) != 0U)
+ {
+ /* OPAMP_CSR_CALOUT is HIGH try higher trimming */
+ trimmingvaluen -= delta;
+ }
+ else
+ {
+ /* OPAMP_CSR_CALOUT is LOW try lower trimming */
+ trimmingvaluen += delta;
+ }
+ /* Divide range by 2 to continue dichotomy sweep */
+ delta >>= 1U;
+ }
+
+ /* Still need to check if right calibration is current value or one step below */
+ /* Indeed the first value that causes the OUTCAL bit to change from 0 to 1 */
+ /* Set candidate trimming */
+ MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen);
+
+ /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */
+ /* Offset trim time: during calibration, minimum time needed between */
+ /* two steps to have 1 mV accuracy */
+ HAL_Delay(OPAMP_TRIMMING_DELAY);
+
+ if ((READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT)) == 0U)
+ {
+ /* Trimming value is actually one value more */
+ trimmingvaluen++;
+ /* Set right trimming */
+ MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen);
+ }
+
+ /* 2nd calibration - P */
+ SET_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALSEL);
+
+ /* Init trimming counter */
+ /* Medium value */
+ trimmingvaluep = 16U;
+ delta = 8U;
+
+ while (delta != 0U)
+ {
+ /* Set candidate trimming */
+ /* OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED or OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED */
+ MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep << OPAMP_INPUT_NONINVERTING));
+
+ /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */
+ /* Offset trim time: during calibration, minimum time needed between */
+ /* two steps to have 1 mV accuracy */
+ HAL_Delay(OPAMP_TRIMMING_DELAY);
+
+ if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT) != 0U)
+ {
+ /* OPAMP_CSR_CALOUT is HIGH try higher trimming */
+ trimmingvaluep -= delta;
+ }
+ else
+ {
+ /* OPAMP_CSR_CALOUT is LOW try lower trimming */
+ trimmingvaluep += delta;
+ }
+
+ /* Divide range by 2 to continue dichotomy sweep */
+ delta >>= 1U;
+ }
+
+ /* Still need to check if right calibration is current value or one step below */
+ /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0 */
+ /* Set candidate trimming */
+ MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep << OPAMP_INPUT_NONINVERTING));
+
+ /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */
+ /* Offset trim time: during calibration, minimum time needed between */
+ /* two steps to have 1 mV accuracy */
+ HAL_Delay(OPAMP_TRIMMING_DELAY);
+
+ if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT) != 0U)
+ {
+ /* Trimming value is actually one value more */
+ trimmingvaluep++;
+ MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep << OPAMP_INPUT_NONINVERTING));
+ }
+
+ /* Disable the OPAMP */
+ CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_OPAEN);
+
+ /* Disable calibration & set normal mode (operating mode) */
+ CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALON);
+
+ /* Self calibration is successful */
+ /* Store calibration(user trimming) results in init structure. */
+
+ /* Set user trimming mode */
+ hopamp->Init.UserTrimming = OPAMP_TRIMMING_USER;
+
+ /* Affect calibration parameters depending on mode normal/low power */
+ if ((hopamp->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER_NORMALSPEED) && \
+ (hopamp->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER_HIGHSPEED))
+ {
+ /* Write calibration result N */
+ hopamp->Init.TrimmingValueN = trimmingvaluen;
+ /* Write calibration result P */
+ hopamp->Init.TrimmingValueP = trimmingvaluep;
+ }
+ else
+ {
+ /* Write calibration result N */
+ hopamp->Init.TrimmingValueNLowPower = trimmingvaluen;
+ /* Write calibration result P */
+ hopamp->Init.TrimmingValuePLowPower = trimmingvaluep;
+ }
+
+ /* Restore OPAMP mode after calibration */
+ MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_OPAMODE, opampmode);
+ }
+ else
+ {
+ /* OPAMP can not be calibrated from this mode */
+ status = HAL_ERROR;
+ }
+ }
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the OPAMP data
+ transfers.
+
+
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Lock the selected OPAMP configuration.
+ * @note On STM32U5, HAL OPAMP lock is software lock only (in
+ * contrast of hardware lock available on some other STM32
+ * devices).
+ * @param hopamp: OPAMP handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the OPAMP handle allocation */
+ /* Check if OPAMP locked */
+ /* OPAMP can be locked when enabled and running in normal mode */
+ /* It is meaningless otherwise */
+ if (hopamp == NULL)
+ {
+ status = HAL_ERROR;
+ }
+ else if (hopamp->State == HAL_OPAMP_STATE_BUSY)
+ {
+ /* Check the parameter */
+ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
+
+ /* OPAMP state changed to locked */
+ hopamp->State = HAL_OPAMP_STATE_BUSYLOCKED;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ return status;
+}
+
+/**
+ * @brief Return the OPAMP factory trimming value.
+ * @note On STM32U5 OPAMP, user can retrieve factory trimming if
+ * OPAMP has never been set to user trimming before.
+ * Therefore, this function must be called when OPAMP init
+ * parameter "UserTrimming" is set to trimming factory,
+ * and before OPAMP calibration (function
+ * "HAL_OPAMP_SelfCalibrate()").
+ * Otherwise, factory trimming value cannot be retrieved and
+ * error status is returned.
+ * @param hopamp : OPAMP handle
+ * @param trimmingoffset : Trimming offset (P or N)
+ * This parameter must be a value of @ref OPAMP_FactoryTrimming
+ * @note Calibration parameter retrieved is corresponding to the mode
+ * specified in OPAMP init structure (mode normal or low-power).
+ * To retrieve calibration parameters for both modes, repeat this
+ * function after OPAMP init structure accordingly updated.
+ * @retval Trimming value (P or N): range: 0->31
+ * or OPAMP_FACTORYTRIMMING_DUMMY if trimming value is not available
+ *
+ */
+
+HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset(OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset)
+{
+ HAL_OPAMP_TrimmingValueTypeDef trimmingvalue;
+ __IO uint32_t *tmp_opamp_reg_trimming; /* Selection of register of trimming depending on power mode: OTR or LPOTR */
+
+ /* Check the OPAMP handle allocation */
+ /* Value can be retrieved in HAL_OPAMP_STATE_READY state */
+ if (hopamp == NULL)
+ {
+ return OPAMP_FACTORYTRIMMING_DUMMY;
+ }
+
+ /* Check the OPAMP handle allocation */
+ /* Value can be retrieved in HAL_OPAMP_STATE_READY state */
+ if (hopamp->State == HAL_OPAMP_STATE_READY)
+ {
+ /* Check the parameter */
+ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
+ assert_param(IS_OPAMP_FACTORYTRIMMING(trimmingoffset));
+ assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode));
+
+ /* Check the trimming mode */
+ if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_USERTRIM) != 0U)
+ {
+ /* This function must called when OPAMP init parameter "UserTrimming" */
+ /* is set to trimming factory, and before OPAMP calibration (function */
+ /* "HAL_OPAMP_SelfCalibrate()"). */
+ /* Otherwise, factory trimming value cannot be retrieved and error */
+ /* status is returned. */
+ trimmingvalue = OPAMP_FACTORYTRIMMING_DUMMY;
+ }
+ else
+ {
+ /* Select trimming settings depending on power mode */
+ if ((hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED) || \
+ (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED))
+ {
+ tmp_opamp_reg_trimming = &OPAMP->OTR;
+ }
+ else
+ {
+ tmp_opamp_reg_trimming = &OPAMP->LPOTR;
+ }
+
+ /* Get factory trimming */
+ if (trimmingoffset == OPAMP_FACTORYTRIMMING_P)
+ {
+ /* OPAMP_FACTORYTRIMMING_P */
+ trimmingvalue = ((*tmp_opamp_reg_trimming) & OPAMP_OTR_TRIMOFFSETP) >> OPAMP_INPUT_NONINVERTING;
+ }
+ else
+ {
+ /* OPAMP_FACTORYTRIMMING_N */
+ trimmingvalue = (*tmp_opamp_reg_trimming) & OPAMP_OTR_TRIMOFFSETN;
+ }
+ }
+ }
+ else
+ {
+ return OPAMP_FACTORYTRIMMING_DUMMY;
+ }
+ return trimmingvalue;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup OPAMP_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the OPAMP handle state.
+ * @param hopamp : OPAMP handle
+ * @retval HAL state
+ */
+HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp)
+{
+ /* Check the OPAMP handle allocation */
+ if (hopamp == NULL)
+ {
+ return HAL_OPAMP_STATE_RESET;
+ }
+
+ /* Check the parameter */
+ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
+
+ /* Return OPAMP handle state */
+ return hopamp->State;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_Exported_Functions_Group5 Peripheral Callback functions
+ * @brief Peripheral Callback functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Callback functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral.
+
+@endverbatim
+ * @{
+ */
+
+#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User OPAMP Callback
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hopamp : OPAMP handle
+ * @param CallbackID : ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_OPAMP_MSP_INIT_CB_ID OPAMP MspInit callback ID
+ * @arg @ref HAL_OPAMP_MSP_DEINIT_CB_ID OPAMP MspDeInit callback ID
+ * @param pCallback : pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_OPAMP_RegisterCallback(OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackID,
+ pOPAMP_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hopamp);
+
+ if (hopamp->State == HAL_OPAMP_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_OPAMP_MSP_INIT_CB_ID :
+ hopamp->MspInitCallback = pCallback;
+ break;
+ case HAL_OPAMP_MSP_DEINIT_CB_ID :
+ hopamp->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hopamp->State == HAL_OPAMP_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_OPAMP_MSP_INIT_CB_ID :
+ hopamp->MspInitCallback = pCallback;
+ break;
+ case HAL_OPAMP_MSP_DEINIT_CB_ID :
+ hopamp->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hopamp);
+ return status;
+}
+
+/**
+ * @brief Unregister a User OPAMP Callback
+ * OPAMP Callback is redirected to the weak (surcharged) predefined callback
+ * @param hopamp : OPAMP handle
+ * @param CallbackID : ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_OPAMP_MSP_INIT_CB_ID OPAMP MSP Init Callback ID
+ * @arg @ref HAL_OPAMP_MSP_DEINIT_CB_ID OPAMP MSP DeInit Callback ID
+ * @arg @ref HAL_OPAMP_ALL_CB_ID OPAMP All Callbacks
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_OPAMP_UnRegisterCallback(OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hopamp);
+
+ if (hopamp->State == HAL_OPAMP_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_OPAMP_MSP_INIT_CB_ID :
+ hopamp->MspInitCallback = HAL_OPAMP_MspInit;
+ break;
+ case HAL_OPAMP_MSP_DEINIT_CB_ID :
+ hopamp->MspDeInitCallback = HAL_OPAMP_MspDeInit;
+ break;
+ case HAL_OPAMP_ALL_CB_ID :
+ hopamp->MspInitCallback = HAL_OPAMP_MspInit;
+ hopamp->MspDeInitCallback = HAL_OPAMP_MspDeInit;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hopamp->State == HAL_OPAMP_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_OPAMP_MSP_INIT_CB_ID :
+ hopamp->MspInitCallback = HAL_OPAMP_MspInit;
+ break;
+ case HAL_OPAMP_MSP_DEINIT_CB_ID :
+ hopamp->MspDeInitCallback = HAL_OPAMP_MspDeInit;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hopamp);
+ return status;
+}
+#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_OPAMP_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_opamp_ex.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_opamp_ex.c
new file mode 100644
index 00000000..6e34af03
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_opamp_ex.c
@@ -0,0 +1,435 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_opamp_ex.c
+ * @author MCD Application Team
+ * @brief Extended OPAMP HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the operational amplifier(s)(OPAMP1, OPAMP2 etc)
+ * peripheral:
+ * + Extended Initialization and de-initialization functions
+ * + Extended Peripheral Control functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup OPAMPEx OPAMPEx
+ * @brief OPAMP Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup OPAMP_Exported_Functions OPAMP Exported Functions
+ * @{
+ */
+
+/** @addtogroup OPAMPEx_Exported_Functions_Group1
+ * @brief Extended operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended IO operation functions #####
+ ===============================================================================
+ [..]
+ (+) OPAMP Self calibration.
+
+@endverbatim
+ * @{
+ */
+
+/* 2 OPAMPS available */
+/* 2 OPAMPS can be calibrated in parallel */
+
+/**
+ * @brief Run the self calibration of the 2 OPAMPs in parallel.
+ * @note Trimming values (PMOS & NMOS) are updated and user trimming is
+ * enabled is calibration is successful.
+ * @note Calibration is performed in the mode specified in OPAMP init
+ * structure (mode normal or low-power). To perform calibration for
+ * both modes, repeat this function twice after OPAMP init structure
+ * accordingly updated.
+ * @note Calibration runs about 10 ms (5 dichotomy steps, repeated for P
+ * and N transistors: 10 steps with 1 ms for each step).
+ * @param hopamp1 handle
+ * @param hopamp2 handle
+ * @retval HAL status
+ */
+
+HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ uint32_t trimmingvaluen1;
+ uint32_t trimmingvaluep1;
+ uint32_t trimmingvaluen2;
+ uint32_t trimmingvaluep2;
+
+ /* Selection of register of trimming depending on power mode: OTR or LPOTR */
+ __IO uint32_t *tmp_opamp1_reg_trimming;
+ __IO uint32_t *tmp_opamp2_reg_trimming;
+
+ uint32_t delta;
+ uint32_t opampmode1;
+ uint32_t opampmode2;
+
+ if ((hopamp1 == NULL) || (hopamp2 == NULL))
+ {
+ status = HAL_ERROR;
+ }
+ /* Check if OPAMP in calibration mode and calibration not yet enable */
+ else if (hopamp1->State != HAL_OPAMP_STATE_READY)
+ {
+ status = HAL_ERROR;
+ }
+ else if (hopamp2->State != HAL_OPAMP_STATE_READY)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check the parameter */
+ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp1->Instance));
+ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp2->Instance));
+
+ assert_param(IS_OPAMP_POWERMODE(hopamp1->Init.PowerMode));
+ assert_param(IS_OPAMP_POWERMODE(hopamp2->Init.PowerMode));
+
+ /* Save OPAMP mode as in */
+ /* the calibration is not working in PGA mode */
+ opampmode1 = READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_OPAMODE);
+ opampmode2 = READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_OPAMODE);
+
+ /* Use of standalone mode */
+ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_OPAMODE, OPAMP_STANDALONE_MODE);
+ MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_OPAMODE, OPAMP_STANDALONE_MODE);
+
+ /* user trimming values are used for offset calibration */
+ SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_USERTRIM);
+ SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_USERTRIM);
+
+ /* Select trimming settings depending on power mode */
+ if ((hopamp1->Init.PowerMode == OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED) || \
+ (hopamp1->Init.PowerMode == OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED))
+ {
+ tmp_opamp1_reg_trimming = &OPAMP1->OTR;
+ }
+ else
+ {
+ tmp_opamp1_reg_trimming = &OPAMP1->LPOTR;
+ }
+
+ if ((hopamp2->Init.PowerMode == OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED) || \
+ (hopamp2->Init.PowerMode == OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED))
+ {
+ tmp_opamp2_reg_trimming = &OPAMP2->OTR;
+ }
+ else
+ {
+ tmp_opamp2_reg_trimming = &OPAMP2->LPOTR;
+ }
+
+ /* Enable calibration */
+ SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALON);
+ SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALON);
+
+ /* 1st calibration - N */
+ CLEAR_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL);
+ CLEAR_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL);
+
+ /* Enable the selected opamp */
+ SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_OPAEN);
+ SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_OPAEN);
+
+ /* Init trimming counter */
+ /* Medium value */
+ trimmingvaluen1 = 16U;
+ trimmingvaluen2 = 16U;
+ delta = 8U;
+
+ while (delta != 0U)
+ {
+ /* Set candidate trimming */
+ /* OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED or OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED*/
+ MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen1);
+ MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen2);
+
+ /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */
+ /* Offset trim time: during calibration, minimum time needed between */
+ /* two steps to have 1 mV accuracy */
+ HAL_Delay(OPAMP_TRIMMING_DELAY);
+
+ if (READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALOUT) != 0U)
+ {
+ /* OPAMP_CSR_CALOUT is HIGH try lower trimming */
+ trimmingvaluen1 -= delta;
+ }
+ else
+ {
+ /* OPAMP_CSR_CALOUT is LOW try higher trimming */
+ trimmingvaluen1 += delta;
+ }
+
+ if (READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT) != 0U)
+ {
+ /* OPAMP_CSR_CALOUT is HIGH try lower trimming */
+ trimmingvaluen2 -= delta;
+ }
+ else
+ {
+ /* OPAMP_CSR_CALOUT is LOW try higher trimming */
+ trimmingvaluen2 += delta;
+ }
+ /* Divide range by 2 to continue dichotomy sweep */
+ delta >>= 1U;
+ }
+
+ /* Still need to check if right calibration is current value or one step below */
+ /* Indeed the first value that causes the OUTCAL bit to change from 0 to 1 */
+ /* Set candidate trimming */
+ MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen1);
+ MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen2);
+
+ /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */
+ /* Offset trim time: during calibration, minimum time needed between */
+ /* two steps to have 1 mV accuracy */
+ HAL_Delay(OPAMP_TRIMMING_DELAY);
+
+ if ((READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALOUT)) == 0U)
+ {
+ /* Trimming value is actually one value more */
+ trimmingvaluen1++;
+ MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen1);
+ }
+
+ if ((READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT)) == 0U)
+ {
+ /* Trimming value is actually one value more */
+ trimmingvaluen2++;
+ MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen2);
+ }
+
+ /* 2nd calibration - P */
+ SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL);
+ SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL);
+
+ /* Init trimming counter */
+ /* Medium value */
+ trimmingvaluep1 = 16U;
+ trimmingvaluep2 = 16U;
+ delta = 8U;
+
+ while (delta != 0U)
+ {
+ /* Set candidate trimming */
+ /* OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED or OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED*/
+ MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep1 << OPAMP_INPUT_NONINVERTING));
+ MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep2 << OPAMP_INPUT_NONINVERTING));
+
+ /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */
+ /* Offset trim time: during calibration, minimum time needed between */
+ /* two steps to have 1 mV accuracy */
+ HAL_Delay(OPAMP_TRIMMING_DELAY);
+
+ if (READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALOUT) != 0U)
+ {
+ /* OPAMP_CSR_CALOUT is HIGH try higher trimming */
+ trimmingvaluep1 -= delta;
+ }
+ else
+ {
+ /* OPAMP_CSR_CALOUT is HIGH try lower trimming */
+ trimmingvaluep1 += delta;
+ }
+
+ if (READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT) != 0U)
+ {
+ /* OPAMP_CSR_CALOUT is HIGH try higher trimming */
+ trimmingvaluep2 -= delta;
+ }
+ else
+ {
+ /* OPAMP_CSR_CALOUT is LOW try lower trimming */
+ trimmingvaluep2 += delta;
+ }
+ /* Divide range by 2 to continue dichotomy sweep */
+ delta >>= 1U;
+ }
+
+ /* Still need to check if right calibration is current value or one step below */
+ /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0 */
+ /* Set candidate trimming */
+ MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep1 << OPAMP_INPUT_NONINVERTING));
+ MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep2 << OPAMP_INPUT_NONINVERTING));
+
+ /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */
+ /* Offset trim time: during calibration, minimum time needed between */
+ /* two steps to have 1 mV accuracy */
+ HAL_Delay(OPAMP_TRIMMING_DELAY);
+
+ if (READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALOUT) != 0U)
+ {
+ /* Trimming value is actually one value more */
+ trimmingvaluep1++;
+ MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep1 << OPAMP_INPUT_NONINVERTING));
+ }
+
+ if (READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT) != 0U)
+ {
+ /* Trimming value is actually one value more */
+ trimmingvaluep2++;
+ MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep2 << OPAMP_INPUT_NONINVERTING));
+ }
+
+ /* Disable the OPAMPs */
+ CLEAR_BIT(hopamp1->Instance->CSR, OPAMP_CSR_OPAEN);
+ CLEAR_BIT(hopamp2->Instance->CSR, OPAMP_CSR_OPAEN);
+
+ /* Disable calibration & set normal mode (operating mode) */
+ CLEAR_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALON);
+ CLEAR_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALON);
+
+ /* Self calibration is successful */
+ /* Store calibration (user trimming) results in init structure. */
+
+ /* Set user trimming mode */
+ hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER;
+ hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER;
+
+ /* Affect calibration parameters depending on mode normal/low power */
+ if ((hopamp1->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER_NORMALSPEED) && \
+ (hopamp1->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER_HIGHSPEED))
+ {
+ /* Write calibration result N */
+ hopamp1->Init.TrimmingValueN = trimmingvaluen1;
+ /* Write calibration result P */
+ hopamp1->Init.TrimmingValueP = trimmingvaluep1;
+ }
+ else
+ {
+ /* Write calibration result N */
+ hopamp1->Init.TrimmingValueNLowPower = trimmingvaluen1;
+ /* Write calibration result P */
+ hopamp1->Init.TrimmingValuePLowPower = trimmingvaluep1;
+ }
+
+ if ((hopamp2->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER_NORMALSPEED) && \
+ (hopamp2->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER_HIGHSPEED))
+ {
+ /* Write calibration result N */
+ hopamp2->Init.TrimmingValueN = trimmingvaluen2;
+ /* Write calibration result P */
+ hopamp2->Init.TrimmingValueP = trimmingvaluep2;
+ }
+ else
+ {
+ /* Write calibration result N */
+ hopamp2->Init.TrimmingValueNLowPower = trimmingvaluen2;
+ /* Write calibration result P */
+ hopamp2->Init.TrimmingValuePLowPower = trimmingvaluep2;
+ }
+
+ /* Update OPAMP state */
+ hopamp1->State = HAL_OPAMP_STATE_READY;
+ hopamp2->State = HAL_OPAMP_STATE_READY;
+
+ /* Restore OPAMP mode after calibration */
+ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_OPAMODE, opampmode1);
+ MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_OPAMODE, opampmode2);
+ }
+ return status;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup OPAMPEx_Exported_Functions_Group2 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ (+) OPAMP unlock.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Unlock the selected OPAMP configuration.
+ * @note This function must be called only when OPAMP is in state "locked".
+ * @param hopamp: OPAMP handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef *hopamp)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the OPAMP handle allocation */
+ /* Check if OPAMP locked */
+ if (hopamp == NULL)
+ {
+ status = HAL_ERROR;
+ }
+ /* Check the OPAMP handle allocation */
+ /* Check if OPAMP locked */
+ else if (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)
+ {
+ /* Check the parameter */
+ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
+
+ /* OPAMP state changed to locked */
+ hopamp->State = HAL_OPAMP_STATE_BUSY;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_OPAMP_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_ospi.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_ospi.c
new file mode 100644
index 00000000..dc14ab5f
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_ospi.c
@@ -0,0 +1,3528 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_ospi.c
+ * @author MCD Application Team
+ * @brief OSPI HAL module driver.
+ This file provides firmware functions to manage the following
+ functionalities of the OctoSPI interface (OSPI).
+ + Initialization and de-initialization functions
+ + Hyperbus configuration
+ + Indirect functional mode management
+ + Memory-mapped functional mode management
+ + Auto-polling functional mode management
+ + Interrupts and flags management
+ + DMA channel configuration for indirect functional mode
+ + Errors management and abort functionality
+ + IO manager configuration
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ *** Initialization ***
+ ======================
+ [..]
+ As prerequisite, fill in the HAL_OSPI_MspInit() :
+ (+) Enable OctoSPI and OctoSPIM clocks interface with __HAL_RCC_OSPIx_CLK_ENABLE().
+ (+) Reset OctoSPI Peripheral with __HAL_RCC_OSPIx_FORCE_RESET() and __HAL_RCC_OSPIx_RELEASE_RESET().
+ (+) Enable the clocks for the OctoSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
+ (+) Configure these OctoSPI pins in alternate mode using HAL_GPIO_Init().
+ (+) If interrupt or DMA mode is used, enable and configure OctoSPI global
+ interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
+ (+) If DMA mode is used, enable the clocks for the OctoSPI DMA channel
+ with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
+ link it with OctoSPI handle using __HAL_LINKDMA(), enable and configure
+ DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
+ [..]
+ Configure the fifo threshold, the dual-quad mode, the memory type, the
+ device size, the CS high time, the free running clock, the clock mode,
+ the wrap size, the clock prescaler, the sample shifting, the hold delay
+ and the CS boundary using the HAL_OSPI_Init() function.
+ [..]
+ When using Hyperbus, configure the RW recovery time, the access time,
+ the write latency and the latency mode unsing the HAL_OSPI_HyperbusCfg()
+ function.
+
+ *** Indirect functional mode ***
+ ================================
+ [..]
+ In regular mode, configure the command sequence using the HAL_OSPI_Command()
+ or HAL_OSPI_Command_IT() functions :
+ (+) Instruction phase : the mode used and if present the size, the instruction
+ opcode and the DTR mode.
+ (+) Address phase : the mode used and if present the size, the address
+ value and the DTR mode.
+ (+) Alternate-bytes phase : the mode used and if present the size, the
+ alternate bytes values and the DTR mode.
+ (+) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
+ (+) Data phase : the mode used and if present the number of bytes and the DTR mode.
+ (+) Data strobe (DQS) mode : the activation (or not) of this mode
+ (+) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
+ (+) Flash identifier : in dual-quad mode, indicates which flash is concerned
+ (+) Operation type : always common configuration
+ [..]
+ In Hyperbus mode, configure the command sequence using the HAL_OSPI_HyperbusCmd()
+ function :
+ (+) Address space : indicate if the access will be done in register or memory
+ (+) Address size
+ (+) Number of data
+ (+) Data strobe (DQS) mode : the activation (or not) of this mode
+ [..]
+ If no data is required for the command (only for regular mode, not for
+ Hyperbus mode), it is sent directly to the memory :
+ (+) In polling mode, the output of the function is done when the transfer is complete.
+ (+) In interrupt mode, HAL_OSPI_CmdCpltCallback() will be called when the transfer is complete.
+ [..]
+ For the indirect write mode, use HAL_OSPI_Transmit(), HAL_OSPI_Transmit_DMA() or
+ HAL_OSPI_Transmit_IT() after the command configuration :
+ (+) In polling mode, the output of the function is done when the transfer is complete.
+ (+) In interrupt mode, HAL_OSPI_FifoThresholdCallback() will be called when the fifo threshold
+ is reached and HAL_OSPI_TxCpltCallback() will be called when the transfer is complete.
+ (+) In DMA mode, HAL_OSPI_TxHalfCpltCallback() will be called at the half transfer and
+ HAL_OSPI_TxCpltCallback() will be called when the transfer is complete.
+ [..]
+ For the indirect read mode, use HAL_OSPI_Receive(), HAL_OSPI_Receive_DMA() or
+ HAL_OSPI_Receive_IT() after the command configuration :
+ (+) In polling mode, the output of the function is done when the transfer is complete.
+ (+) In interrupt mode, HAL_OSPI_FifoThresholdCallback() will be called when the fifo threshold
+ is reached and HAL_OSPI_RxCpltCallback() will be called when the transfer is complete.
+ (+) In DMA mode, HAL_OSPI_RxHalfCpltCallback() will be called at the half transfer and
+ HAL_OSPI_RxCpltCallback() will be called when the transfer is complete.
+
+ *** Auto-polling functional mode ***
+ ====================================
+ [..]
+ Configure the command sequence by the same way than the indirect mode
+ [..]
+ Configure the auto-polling functional mode using the HAL_OSPI_AutoPolling()
+ or HAL_OSPI_AutoPolling_IT() functions :
+ (+) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
+ the polling interval and the automatic stop activation.
+ [..]
+ After the configuration :
+ (+) In polling mode, the output of the function is done when the status match is reached. The
+ automatic stop is activated to avoid an infinite loop.
+ (+) In interrupt mode, HAL_OSPI_StatusMatchCallback() will be called each time the status match is reached.
+
+ *** Memory-mapped functional mode ***
+ =====================================
+ [..]
+ Configure the command sequence by the same way than the indirect mode except
+ for the operation type in regular mode :
+ (+) Operation type equals to read configuration : the command configuration
+ applies to read access in memory-mapped mode
+ (+) Operation type equals to write configuration : the command configuration
+ applies to write access in memory-mapped mode
+ (+) Both read and write configuration should be performed before activating
+ memory-mapped mode
+ [..]
+ Configure the memory-mapped functional mode using the HAL_OSPI_MemoryMapped()
+ functions :
+ (+) The timeout activation and the timeout period.
+ [..]
+ After the configuration, the OctoSPI will be used as soon as an access on the AHB is done on
+ the address range. HAL_OSPI_TimeOutCallback() will be called when the timeout expires.
+
+ *** Errors management and abort functionality ***
+ =================================================
+ [..]
+ HAL_OSPI_GetError() function gives the error raised during the last operation.
+ [..]
+ HAL_OSPI_Abort() and HAL_OSPI_AbortIT() functions aborts any on-going operation and
+ flushes the fifo :
+ (+) In polling mode, the output of the function is done when the transfer
+ complete bit is set and the busy bit cleared.
+ (+) In interrupt mode, HAL_OSPI_AbortCpltCallback() will be called when
+ the transfer complete bit is set.
+
+ *** Control functions ***
+ =========================
+ [..]
+ HAL_OSPI_GetState() function gives the current state of the HAL OctoSPI driver.
+ [..]
+ HAL_OSPI_SetTimeout() function configures the timeout value used in the driver.
+ [..]
+ HAL_OSPI_SetFifoThreshold() function configures the threshold on the Fifo of the OSPI Peripheral.
+ [..]
+ HAL_OSPI_GetFifoThreshold() function gives the current of the Fifo's threshold
+
+ *** IO manager configuration functions ***
+ ==========================================
+ [..]
+ HAL_OSPIM_Config() function configures the IO manager for the OctoSPI instance.
+
+ *** Callback registration ***
+ =============================================
+ [..]
+ The compilation define USE_HAL_OSPI_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ [..]
+ Use function HAL_OSPI_RegisterCallback() to register a user callback,
+ it allows to register following callbacks:
+ (+) ErrorCallback : callback when error occurs.
+ (+) AbortCpltCallback : callback when abort is completed.
+ (+) FifoThresholdCallback : callback when the fifo threshold is reached.
+ (+) CmdCpltCallback : callback when a command without data is completed.
+ (+) RxCpltCallback : callback when a reception transfer is completed.
+ (+) TxCpltCallback : callback when a transmission transfer is completed.
+ (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.
+ (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.
+ (+) StatusMatchCallback : callback when a status match occurs.
+ (+) TimeOutCallback : callback when the timeout perioed expires.
+ (+) MspInitCallback : OSPI MspInit.
+ (+) MspDeInitCallback : OSPI MspDeInit.
+ [..]
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ [..]
+ Use function HAL_OSPI_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function. It allows to reset following callbacks:
+ (+) ErrorCallback : callback when error occurs.
+ (+) AbortCpltCallback : callback when abort is completed.
+ (+) FifoThresholdCallback : callback when the fifo threshold is reached.
+ (+) CmdCpltCallback : callback when a command without data is completed.
+ (+) RxCpltCallback : callback when a reception transfer is completed.
+ (+) TxCpltCallback : callback when a transmission transfer is completed.
+ (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.
+ (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.
+ (+) StatusMatchCallback : callback when a status match occurs.
+ (+) TimeOutCallback : callback when the timeout perioed expires.
+ (+) MspInitCallback : OSPI MspInit.
+ (+) MspDeInitCallback : OSPI MspDeInit.
+ [..]
+ This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+ [..]
+ By default, after the HAL_OSPI_Init() and if the state is HAL_OSPI_STATE_RESET
+ all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak (surcharged) functions in the HAL_OSPI_Init()
+ and HAL_OSPI_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_OSPI_Init() and HAL_OSPI_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ [..]
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using HAL_OSPI_RegisterCallback() before calling HAL_OSPI_DeInit()
+ or HAL_OSPI_Init() function.
+
+ [..]
+ When The compilation define USE_HAL_OSPI_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+#if defined(OCTOSPI) || defined(OCTOSPI1) || defined(OCTOSPI2)
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup OSPI OSPI
+ * @brief OSPI HAL module driver
+ * @{
+ */
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+
+/**
+ @cond 0
+ */
+/* Private typedef -----------------------------------------------------------*/
+
+/* Private define ------------------------------------------------------------*/
+#define OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000) /*!< Indirect write mode */
+#define OSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)OCTOSPI_CR_FMODE_0) /*!< Indirect read mode */
+#define OSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)OCTOSPI_CR_FMODE_1) /*!< Automatic polling mode */
+#define OSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)OCTOSPI_CR_FMODE) /*!< Memory-mapped mode */
+
+#define OSPI_CFG_STATE_MASK 0x00000004U
+#define OSPI_BUSY_STATE_MASK 0x00000008U
+
+#define OSPI_NB_INSTANCE 2U
+#define OSPI_IOM_NB_PORTS 2U
+#define OSPI_IOM_PORT_MASK 0x1U
+
+/* Private macro -------------------------------------------------------------*/
+#define IS_OSPI_FUNCTIONAL_MODE(MODE) (((MODE) == OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \
+ ((MODE) == OSPI_FUNCTIONAL_MODE_INDIRECT_READ) || \
+ ((MODE) == OSPI_FUNCTIONAL_MODE_AUTO_POLLING) || \
+ ((MODE) == OSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
+
+/* Private variables ---------------------------------------------------------*/
+
+/* Private function prototypes -----------------------------------------------*/
+static void OSPI_DMACplt(DMA_HandleTypeDef *hdma);
+static void OSPI_DMAHalfCplt(DMA_HandleTypeDef *hdma);
+static void OSPI_DMAError(DMA_HandleTypeDef *hdma);
+static void OSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hospi, uint32_t Flag, FlagStatus State,
+ uint32_t Tickstart, uint32_t Timeout);
+static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd);
+static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef *cfg);
+/**
+ @endcond
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup OSPI_Exported_Functions OSPI Exported Functions
+ * @{
+ */
+
+/** @defgroup OSPI_Exported_Functions_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to :
+ (+) Initialize the OctoSPI.
+ (+) De-initialize the OctoSPI.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the OSPI mode according to the specified parameters
+ * in the OSPI_InitTypeDef and initialize the associated handle.
+ * @param hospi : OSPI handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_OSPI_Init(OSPI_HandleTypeDef *hospi)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Check the OSPI handle allocation */
+ if (hospi == NULL)
+ {
+ status = HAL_ERROR;
+ /* No error code can be set set as the handler is null */
+ }
+ else
+ {
+ /* Check the parameters of the initialization structure */
+ assert_param(IS_OSPI_FIFO_THRESHOLD(hospi->Init.FifoThreshold));
+ assert_param(IS_OSPI_DUALQUAD_MODE(hospi->Init.DualQuad));
+ assert_param(IS_OSPI_MEMORY_TYPE(hospi->Init.MemoryType));
+ assert_param(IS_OSPI_DEVICE_SIZE(hospi->Init.DeviceSize));
+ assert_param(IS_OSPI_CS_HIGH_TIME(hospi->Init.ChipSelectHighTime));
+ assert_param(IS_OSPI_FREE_RUN_CLK(hospi->Init.FreeRunningClock));
+ assert_param(IS_OSPI_CLOCK_MODE(hospi->Init.ClockMode));
+ assert_param(IS_OSPI_WRAP_SIZE(hospi->Init.WrapSize));
+ assert_param(IS_OSPI_CLK_PRESCALER(hospi->Init.ClockPrescaler));
+ assert_param(IS_OSPI_SAMPLE_SHIFTING(hospi->Init.SampleShifting));
+ assert_param(IS_OSPI_DHQC(hospi->Init.DelayHoldQuarterCycle));
+ assert_param(IS_OSPI_CS_BOUNDARY(hospi->Init.ChipSelectBoundary));
+ assert_param(IS_OSPI_DLYBYP(hospi->Init.DelayBlockBypass));
+ assert_param(IS_OSPI_MAXTRAN(hospi->Init.MaxTran));
+
+ /* Initialize error code */
+ hospi->ErrorCode = HAL_OSPI_ERROR_NONE;
+
+ /* Check if the state is the reset state */
+ if (hospi->State == HAL_OSPI_STATE_RESET)
+ {
+#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
+ /* Reset Callback pointers in HAL_OSPI_STATE_RESET only */
+ hospi->ErrorCallback = HAL_OSPI_ErrorCallback;
+ hospi->AbortCpltCallback = HAL_OSPI_AbortCpltCallback;
+ hospi->FifoThresholdCallback = HAL_OSPI_FifoThresholdCallback;
+ hospi->CmdCpltCallback = HAL_OSPI_CmdCpltCallback;
+ hospi->RxCpltCallback = HAL_OSPI_RxCpltCallback;
+ hospi->TxCpltCallback = HAL_OSPI_TxCpltCallback;
+ hospi->RxHalfCpltCallback = HAL_OSPI_RxHalfCpltCallback;
+ hospi->TxHalfCpltCallback = HAL_OSPI_TxHalfCpltCallback;
+ hospi->StatusMatchCallback = HAL_OSPI_StatusMatchCallback;
+ hospi->TimeOutCallback = HAL_OSPI_TimeOutCallback;
+
+ if (hospi->MspInitCallback == NULL)
+ {
+ hospi->MspInitCallback = HAL_OSPI_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hospi->MspInitCallback(hospi);
+#else
+ /* Initialization of the low level hardware */
+ HAL_OSPI_MspInit(hospi);
+#endif /* defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
+
+ /* Configure the default timeout for the OSPI memory access */
+ (void)HAL_OSPI_SetTimeout(hospi, HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
+
+ /* Configure memory type, device size, chip select high time, delay block bypass,
+ free running clock, clock mode */
+ MODIFY_REG(hospi->Instance->DCR1,
+ (OCTOSPI_DCR1_MTYP | OCTOSPI_DCR1_DEVSIZE | OCTOSPI_DCR1_CSHT | OCTOSPI_DCR1_DLYBYP |
+ OCTOSPI_DCR1_FRCK | OCTOSPI_DCR1_CKMODE),
+ (hospi->Init.MemoryType | ((hospi->Init.DeviceSize - 1U) << OCTOSPI_DCR1_DEVSIZE_Pos) |
+ ((hospi->Init.ChipSelectHighTime - 1U) << OCTOSPI_DCR1_CSHT_Pos) |
+ hospi->Init.DelayBlockBypass | hospi->Init.ClockMode));
+
+ /* Configure wrap size */
+ MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_WRAPSIZE, hospi->Init.WrapSize);
+
+ /* Configure chip select boundary and maximum transfer */
+ hospi->Instance->DCR3 = ((hospi->Init.ChipSelectBoundary << OCTOSPI_DCR3_CSBOUND_Pos) |
+ (hospi->Init.MaxTran << OCTOSPI_DCR3_MAXTRAN_Pos));
+
+ /* Configure refresh */
+ hospi->Instance->DCR4 = hospi->Init.Refresh;
+
+ /* Configure FIFO threshold */
+ MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FTHRES, ((hospi->Init.FifoThreshold - 1U) << OCTOSPI_CR_FTHRES_Pos));
+
+ /* Wait till busy flag is reset */
+ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout);
+
+ if (status == HAL_OK)
+ {
+ /* Configure clock prescaler */
+ MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_PRESCALER,
+ ((hospi->Init.ClockPrescaler - 1U) << OCTOSPI_DCR2_PRESCALER_Pos));
+
+ /* Configure Dual Quad mode */
+ MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_DQM, hospi->Init.DualQuad);
+
+ /* Configure sample shifting and delay hold quarter cycle */
+ MODIFY_REG(hospi->Instance->TCR, (OCTOSPI_TCR_SSHIFT | OCTOSPI_TCR_DHQC),
+ (hospi->Init.SampleShifting | hospi->Init.DelayHoldQuarterCycle));
+
+ /* Enable OctoSPI */
+ __HAL_OSPI_ENABLE(hospi);
+
+ /* Enable free running clock if needed : must be done after OSPI enable */
+ if (hospi->Init.FreeRunningClock == HAL_OSPI_FREERUNCLK_ENABLE)
+ {
+ SET_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK);
+ }
+
+ /* Initialize the OSPI state */
+ if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)
+ {
+ hospi->State = HAL_OSPI_STATE_HYPERBUS_INIT;
+ }
+ else
+ {
+ hospi->State = HAL_OSPI_STATE_READY;
+ }
+ }
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Initialize the OSPI MSP.
+ * @param hospi : OSPI handle
+ * @retval None
+ */
+__weak void HAL_OSPI_MspInit(OSPI_HandleTypeDef *hospi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hospi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_OSPI_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief De-Initialize the OSPI peripheral.
+ * @param hospi : OSPI handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_OSPI_DeInit(OSPI_HandleTypeDef *hospi)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the OSPI handle allocation */
+ if (hospi == NULL)
+ {
+ status = HAL_ERROR;
+ /* No error code can be set set as the handler is null */
+ }
+ else
+ {
+ /* Disable OctoSPI */
+ __HAL_OSPI_DISABLE(hospi);
+
+ /* Disable free running clock if needed : must be done after OSPI disable */
+ CLEAR_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK);
+
+#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
+ if (hospi->MspDeInitCallback == NULL)
+ {
+ hospi->MspDeInitCallback = HAL_OSPI_MspDeInit;
+ }
+
+ /* DeInit the low level hardware */
+ hospi->MspDeInitCallback(hospi);
+#else
+ /* De-initialize the low-level hardware */
+ HAL_OSPI_MspDeInit(hospi);
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
+
+ /* Reset the driver state */
+ hospi->State = HAL_OSPI_STATE_RESET;
+ }
+
+ return status;
+}
+
+/**
+ * @brief DeInitialize the OSPI MSP.
+ * @param hospi : OSPI handle
+ * @retval None
+ */
+__weak void HAL_OSPI_MspDeInit(OSPI_HandleTypeDef *hospi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hospi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_OSPI_MspDeInit can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup OSPI_Exported_Functions_Group2 Input and Output operation functions
+ * @brief OSPI Transmit/Receive functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to :
+ (+) Handle the interrupts.
+ (+) Handle the command sequence (regular and Hyperbus).
+ (+) Handle the Hyperbus configuration.
+ (+) Transmit data in blocking, interrupt or DMA mode.
+ (+) Receive data in blocking, interrupt or DMA mode.
+ (+) Manage the auto-polling functional mode.
+ (+) Manage the memory-mapped functional mode.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Handle OSPI interrupt request.
+ * @param hospi : OSPI handle
+ * @retval None
+ */
+void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi)
+{
+ __IO uint32_t *data_reg = &hospi->Instance->DR;
+ uint32_t flag = hospi->Instance->SR;
+ uint32_t itsource = hospi->Instance->CR;
+ uint32_t currentstate = hospi->State;
+
+ /* OctoSPI fifo threshold interrupt occurred -------------------------------*/
+ if (((flag & HAL_OSPI_FLAG_FT) != 0U) && ((itsource & HAL_OSPI_IT_FT) != 0U))
+ {
+ if (currentstate == HAL_OSPI_STATE_BUSY_TX)
+ {
+ /* Write a data in the fifo */
+ *((__IO uint8_t *)data_reg) = *hospi->pBuffPtr;
+ hospi->pBuffPtr++;
+ hospi->XferCount--;
+ }
+ else if (currentstate == HAL_OSPI_STATE_BUSY_RX)
+ {
+ /* Read a data from the fifo */
+ *hospi->pBuffPtr = *((__IO uint8_t *)data_reg);
+ hospi->pBuffPtr++;
+ hospi->XferCount--;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ if (hospi->XferCount == 0U)
+ {
+ /* All data have been received or transmitted for the transfer */
+ /* Disable fifo threshold interrupt */
+ __HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_FT);
+ }
+
+ /* Fifo threshold callback */
+#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
+ hospi->FifoThresholdCallback(hospi);
+#else
+ HAL_OSPI_FifoThresholdCallback(hospi);
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/
+ }
+ /* OctoSPI transfer complete interrupt occurred ----------------------------*/
+ else if (((flag & HAL_OSPI_FLAG_TC) != 0U) && ((itsource & HAL_OSPI_IT_TC) != 0U))
+ {
+ if (currentstate == HAL_OSPI_STATE_BUSY_RX)
+ {
+ if ((hospi->XferCount > 0U) && ((flag & OCTOSPI_SR_FLEVEL) != 0U))
+ {
+ /* Read the last data received in the fifo */
+ *hospi->pBuffPtr = *((__IO uint8_t *)data_reg);
+ hospi->pBuffPtr++;
+ hospi->XferCount--;
+ }
+ else if (hospi->XferCount == 0U)
+ {
+ /* Clear flag */
+ hospi->Instance->FCR = HAL_OSPI_FLAG_TC;
+
+ /* Disable the interrupts */
+ __HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_FT | HAL_OSPI_IT_TE);
+
+ /* Update state */
+ hospi->State = HAL_OSPI_STATE_READY;
+
+ /* RX complete callback */
+#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
+ hospi->RxCpltCallback(hospi);
+#else
+ HAL_OSPI_RxCpltCallback(hospi);
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ else
+ {
+ /* Clear flag */
+ hospi->Instance->FCR = HAL_OSPI_FLAG_TC;
+
+ /* Disable the interrupts */
+ __HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_FT | HAL_OSPI_IT_TE);
+
+ /* Update state */
+ hospi->State = HAL_OSPI_STATE_READY;
+
+ if (currentstate == HAL_OSPI_STATE_BUSY_TX)
+ {
+ /* TX complete callback */
+#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
+ hospi->TxCpltCallback(hospi);
+#else
+ HAL_OSPI_TxCpltCallback(hospi);
+#endif /* defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
+ }
+ else if (currentstate == HAL_OSPI_STATE_BUSY_CMD)
+ {
+ /* Command complete callback */
+#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
+ hospi->CmdCpltCallback(hospi);
+#else
+ HAL_OSPI_CmdCpltCallback(hospi);
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
+ }
+ else if (currentstate == HAL_OSPI_STATE_ABORT)
+ {
+ if (hospi->ErrorCode == HAL_OSPI_ERROR_NONE)
+ {
+ /* Abort called by the user */
+ /* Abort complete callback */
+#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
+ hospi->AbortCpltCallback(hospi);
+#else
+ HAL_OSPI_AbortCpltCallback(hospi);
+#endif /* defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/
+ }
+ else
+ {
+ /* Abort due to an error (eg : DMA error) */
+ /* Error callback */
+#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
+ hospi->ErrorCallback(hospi);
+#else
+ HAL_OSPI_ErrorCallback(hospi);
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ }
+ /* OctoSPI status match interrupt occurred ---------------------------------*/
+ else if (((flag & HAL_OSPI_FLAG_SM) != 0U) && ((itsource & HAL_OSPI_IT_SM) != 0U))
+ {
+ /* Clear flag */
+ hospi->Instance->FCR = HAL_OSPI_FLAG_SM;
+
+ /* Check if automatic poll mode stop is activated */
+ if ((hospi->Instance->CR & OCTOSPI_CR_APMS) != 0U)
+ {
+ /* Disable the interrupts */
+ __HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_SM | HAL_OSPI_IT_TE);
+
+ /* Update state */
+ hospi->State = HAL_OSPI_STATE_READY;
+ }
+
+ /* Status match callback */
+#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
+ hospi->StatusMatchCallback(hospi);
+#else
+ HAL_OSPI_StatusMatchCallback(hospi);
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
+ }
+ /* OctoSPI transfer error interrupt occurred -------------------------------*/
+ else if (((flag & HAL_OSPI_FLAG_TE) != 0U) && ((itsource & HAL_OSPI_IT_TE) != 0U))
+ {
+ /* Clear flag */
+ hospi->Instance->FCR = HAL_OSPI_FLAG_TE;
+
+ /* Disable all interrupts */
+ __HAL_OSPI_DISABLE_IT(hospi, (HAL_OSPI_IT_TO | HAL_OSPI_IT_SM | HAL_OSPI_IT_FT | HAL_OSPI_IT_TC | HAL_OSPI_IT_TE));
+
+ /* Set error code */
+ hospi->ErrorCode = HAL_OSPI_ERROR_TRANSFER;
+
+ /* Check if the DMA is enabled */
+ if ((hospi->Instance->CR & OCTOSPI_CR_DMAEN) != 0U)
+ {
+ /* Disable the DMA transfer on the OctoSPI side */
+ CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN);
+
+ /* Disable the DMA transfer on the DMA side */
+ hospi->hdma->XferAbortCallback = OSPI_DMAAbortCplt;
+ if (HAL_DMA_Abort_IT(hospi->hdma) != HAL_OK)
+ {
+ /* Update state */
+ hospi->State = HAL_OSPI_STATE_READY;
+
+ /* Error callback */
+#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
+ hospi->ErrorCallback(hospi);
+#else
+ HAL_OSPI_ErrorCallback(hospi);
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/
+ }
+ }
+ else
+ {
+ /* Update state */
+ hospi->State = HAL_OSPI_STATE_READY;
+
+ /* Error callback */
+#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
+ hospi->ErrorCallback(hospi);
+#else
+ HAL_OSPI_ErrorCallback(hospi);
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
+ }
+ }
+ /* OctoSPI timeout interrupt occurred --------------------------------------*/
+ else if (((flag & HAL_OSPI_FLAG_TO) != 0U) && ((itsource & HAL_OSPI_IT_TO) != 0U))
+ {
+ /* Clear flag */
+ hospi->Instance->FCR = HAL_OSPI_FLAG_TO;
+
+ /* Timeout callback */
+#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
+ hospi->TimeOutCallback(hospi);
+#else
+ HAL_OSPI_TimeOutCallback(hospi);
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+}
+
+/**
+ * @brief Set the command configuration.
+ * @param hospi : OSPI handle
+ * @param cmd : structure that contains the command configuration information
+ * @param Timeout : Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout)
+{
+ HAL_StatusTypeDef status;
+ uint32_t state;
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Check the parameters of the command structure */
+ assert_param(IS_OSPI_OPERATION_TYPE(cmd->OperationType));
+
+ if (hospi->Init.DualQuad == HAL_OSPI_DUALQUAD_DISABLE)
+ {
+ assert_param(IS_OSPI_FLASH_ID(cmd->FlashId));
+ }
+
+ assert_param(IS_OSPI_INSTRUCTION_MODE(cmd->InstructionMode));
+ if (cmd->InstructionMode != HAL_OSPI_INSTRUCTION_NONE)
+ {
+ assert_param(IS_OSPI_INSTRUCTION_SIZE(cmd->InstructionSize));
+ assert_param(IS_OSPI_INSTRUCTION_DTR_MODE(cmd->InstructionDtrMode));
+ }
+
+ assert_param(IS_OSPI_ADDRESS_MODE(cmd->AddressMode));
+ if (cmd->AddressMode != HAL_OSPI_ADDRESS_NONE)
+ {
+ assert_param(IS_OSPI_ADDRESS_SIZE(cmd->AddressSize));
+ assert_param(IS_OSPI_ADDRESS_DTR_MODE(cmd->AddressDtrMode));
+ }
+
+ assert_param(IS_OSPI_ALT_BYTES_MODE(cmd->AlternateBytesMode));
+ if (cmd->AlternateBytesMode != HAL_OSPI_ALTERNATE_BYTES_NONE)
+ {
+ assert_param(IS_OSPI_ALT_BYTES_SIZE(cmd->AlternateBytesSize));
+ assert_param(IS_OSPI_ALT_BYTES_DTR_MODE(cmd->AlternateBytesDtrMode));
+ }
+
+ assert_param(IS_OSPI_DATA_MODE(cmd->DataMode));
+ if (cmd->DataMode != HAL_OSPI_DATA_NONE)
+ {
+ if (cmd->OperationType == HAL_OSPI_OPTYPE_COMMON_CFG)
+ {
+ assert_param(IS_OSPI_NUMBER_DATA(cmd->NbData));
+ }
+ assert_param(IS_OSPI_DATA_DTR_MODE(cmd->DataDtrMode));
+ assert_param(IS_OSPI_DUMMY_CYCLES(cmd->DummyCycles));
+ }
+
+ assert_param(IS_OSPI_DQS_MODE(cmd->DQSMode));
+ assert_param(IS_OSPI_SIOO_MODE(cmd->SIOOMode));
+
+ /* Check the state of the driver */
+ state = hospi->State;
+ if (((state == HAL_OSPI_STATE_READY) && (hospi->Init.MemoryType != HAL_OSPI_MEMTYPE_HYPERBUS)) ||
+ ((state == HAL_OSPI_STATE_READ_CMD_CFG) && ((cmd->OperationType == HAL_OSPI_OPTYPE_WRITE_CFG)
+ || (cmd->OperationType == HAL_OSPI_OPTYPE_WRAP_CFG))) ||
+ ((state == HAL_OSPI_STATE_WRITE_CMD_CFG) && ((cmd->OperationType == HAL_OSPI_OPTYPE_READ_CFG) ||
+ (cmd->OperationType == HAL_OSPI_OPTYPE_WRAP_CFG))))
+ {
+ /* Wait till busy flag is reset */
+ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout);
+
+ if (status == HAL_OK)
+ {
+ /* Initialize error code */
+ hospi->ErrorCode = HAL_OSPI_ERROR_NONE;
+
+ /* Configure the registers */
+ status = OSPI_ConfigCmd(hospi, cmd);
+
+ if (status == HAL_OK)
+ {
+ if (cmd->DataMode == HAL_OSPI_DATA_NONE)
+ {
+ /* When there is no data phase, the transfer start as soon as the configuration is done
+ so wait until TC flag is set to go back in idle state */
+ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_TC, SET, tickstart, Timeout);
+
+ __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC);
+ }
+ else
+ {
+ /* Update the state */
+ if (cmd->OperationType == HAL_OSPI_OPTYPE_COMMON_CFG)
+ {
+ hospi->State = HAL_OSPI_STATE_CMD_CFG;
+ }
+ else if (cmd->OperationType == HAL_OSPI_OPTYPE_READ_CFG)
+ {
+ if (hospi->State == HAL_OSPI_STATE_WRITE_CMD_CFG)
+ {
+ hospi->State = HAL_OSPI_STATE_CMD_CFG;
+ }
+ else
+ {
+ hospi->State = HAL_OSPI_STATE_READ_CMD_CFG;
+ }
+ }
+ else if (cmd->OperationType == HAL_OSPI_OPTYPE_WRITE_CFG)
+ {
+ if (hospi->State == HAL_OSPI_STATE_READ_CMD_CFG)
+ {
+ hospi->State = HAL_OSPI_STATE_CMD_CFG;
+ }
+ else
+ {
+ hospi->State = HAL_OSPI_STATE_WRITE_CMD_CFG;
+ }
+ }
+ else
+ {
+ /* Wrap configuration, no state change */
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Set the command configuration in interrupt mode.
+ * @param hospi : OSPI handle
+ * @param cmd : structure that contains the command configuration information
+ * @note This function is used only in Indirect Read or Write Modes
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_OSPI_Command_IT(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd)
+{
+ HAL_StatusTypeDef status;
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Check the parameters of the command structure */
+ assert_param(IS_OSPI_OPERATION_TYPE(cmd->OperationType));
+
+ if (hospi->Init.DualQuad == HAL_OSPI_DUALQUAD_DISABLE)
+ {
+ assert_param(IS_OSPI_FLASH_ID(cmd->FlashId));
+ }
+
+ assert_param(IS_OSPI_INSTRUCTION_MODE(cmd->InstructionMode));
+ if (cmd->InstructionMode != HAL_OSPI_INSTRUCTION_NONE)
+ {
+ assert_param(IS_OSPI_INSTRUCTION_SIZE(cmd->InstructionSize));
+ assert_param(IS_OSPI_INSTRUCTION_DTR_MODE(cmd->InstructionDtrMode));
+ }
+
+ assert_param(IS_OSPI_ADDRESS_MODE(cmd->AddressMode));
+ if (cmd->AddressMode != HAL_OSPI_ADDRESS_NONE)
+ {
+ assert_param(IS_OSPI_ADDRESS_SIZE(cmd->AddressSize));
+ assert_param(IS_OSPI_ADDRESS_DTR_MODE(cmd->AddressDtrMode));
+ }
+
+ assert_param(IS_OSPI_ALT_BYTES_MODE(cmd->AlternateBytesMode));
+ if (cmd->AlternateBytesMode != HAL_OSPI_ALTERNATE_BYTES_NONE)
+ {
+ assert_param(IS_OSPI_ALT_BYTES_SIZE(cmd->AlternateBytesSize));
+ assert_param(IS_OSPI_ALT_BYTES_DTR_MODE(cmd->AlternateBytesDtrMode));
+ }
+
+ assert_param(IS_OSPI_DATA_MODE(cmd->DataMode));
+ if (cmd->DataMode != HAL_OSPI_DATA_NONE)
+ {
+ assert_param(IS_OSPI_NUMBER_DATA(cmd->NbData));
+ assert_param(IS_OSPI_DATA_DTR_MODE(cmd->DataDtrMode));
+ assert_param(IS_OSPI_DUMMY_CYCLES(cmd->DummyCycles));
+ }
+
+ assert_param(IS_OSPI_DQS_MODE(cmd->DQSMode));
+ assert_param(IS_OSPI_SIOO_MODE(cmd->SIOOMode));
+
+ /* Check the state of the driver */
+ if ((hospi->State == HAL_OSPI_STATE_READY) && (cmd->OperationType == HAL_OSPI_OPTYPE_COMMON_CFG) &&
+ (cmd->DataMode == HAL_OSPI_DATA_NONE) && (hospi->Init.MemoryType != HAL_OSPI_MEMTYPE_HYPERBUS))
+ {
+ /* Wait till busy flag is reset */
+ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout);
+
+ if (status == HAL_OK)
+ {
+ /* Initialize error code */
+ hospi->ErrorCode = HAL_OSPI_ERROR_NONE;
+
+ /* Clear flags related to interrupt */
+ __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC);
+
+ /* Configure the registers */
+ status = OSPI_ConfigCmd(hospi, cmd);
+
+ if (status == HAL_OK)
+ {
+ /* Update the state */
+ hospi->State = HAL_OSPI_STATE_BUSY_CMD;
+
+ /* Enable the transfer complete and transfer error interrupts */
+ __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_TE);
+ }
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Configure the Hyperbus parameters.
+ * @param hospi : OSPI handle
+ * @param cfg : Structure containing the Hyperbus configuration
+ * @param Timeout : Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_OSPI_HyperbusCfg(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout)
+{
+ HAL_StatusTypeDef status;
+ uint32_t state;
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Check the parameters of the hyperbus configuration structure */
+ assert_param(IS_OSPI_RW_RECOVERY_TIME(cfg->RWRecoveryTime));
+ assert_param(IS_OSPI_ACCESS_TIME(cfg->AccessTime));
+ assert_param(IS_OSPI_WRITE_ZERO_LATENCY(cfg->WriteZeroLatency));
+ assert_param(IS_OSPI_LATENCY_MODE(cfg->LatencyMode));
+
+ /* Check the state of the driver */
+ state = hospi->State;
+ if ((state == HAL_OSPI_STATE_HYPERBUS_INIT) || (state == HAL_OSPI_STATE_READY))
+ {
+ /* Wait till busy flag is reset */
+ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout);
+
+ if (status == HAL_OK)
+ {
+ /* Configure Hyperbus configuration Latency register */
+ WRITE_REG(hospi->Instance->HLCR, ((cfg->RWRecoveryTime << OCTOSPI_HLCR_TRWR_Pos) |
+ (cfg->AccessTime << OCTOSPI_HLCR_TACC_Pos) |
+ cfg->WriteZeroLatency | cfg->LatencyMode));
+
+ /* Update the state */
+ hospi->State = HAL_OSPI_STATE_READY;
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Set the Hyperbus command configuration.
+ * @param hospi : OSPI handle
+ * @param cmd : Structure containing the Hyperbus command
+ * @param Timeout : Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_OSPI_HyperbusCmd(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCmdTypeDef *cmd, uint32_t Timeout)
+{
+ HAL_StatusTypeDef status;
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Check the parameters of the hyperbus command structure */
+ assert_param(IS_OSPI_ADDRESS_SPACE(cmd->AddressSpace));
+ assert_param(IS_OSPI_ADDRESS_SIZE(cmd->AddressSize));
+ assert_param(IS_OSPI_NUMBER_DATA(cmd->NbData));
+ assert_param(IS_OSPI_DQS_MODE(cmd->DQSMode));
+
+ /* Check the state of the driver */
+ if ((hospi->State == HAL_OSPI_STATE_READY) && (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS))
+ {
+ /* Wait till busy flag is reset */
+ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout);
+
+ if (status == HAL_OK)
+ {
+ /* Re-initialize the value of the functional mode */
+ MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, 0U);
+
+ /* Configure the address space in the DCR1 register */
+ MODIFY_REG(hospi->Instance->DCR1, OCTOSPI_DCR1_MTYP_0, cmd->AddressSpace);
+
+ /* Configure the CCR and WCCR registers with the address size and the following configuration :
+ - DQS signal enabled (used as RWDS)
+ - DTR mode enabled on address and data
+ - address and data on 8 lines */
+ WRITE_REG(hospi->Instance->CCR, (cmd->DQSMode | OCTOSPI_CCR_DDTR | OCTOSPI_CCR_DMODE_2 |
+ cmd->AddressSize | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADMODE_2));
+ WRITE_REG(hospi->Instance->WCCR, (cmd->DQSMode | OCTOSPI_WCCR_DDTR | OCTOSPI_WCCR_DMODE_2 |
+ cmd->AddressSize | OCTOSPI_WCCR_ADDTR | OCTOSPI_WCCR_ADMODE_2));
+
+ /* Configure the DLR register with the number of data */
+ WRITE_REG(hospi->Instance->DLR, (cmd->NbData - 1U));
+
+ /* Configure the AR register with the address value */
+ WRITE_REG(hospi->Instance->AR, cmd->Address);
+
+ /* Update the state */
+ hospi->State = HAL_OSPI_STATE_CMD_CFG;
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Transmit an amount of data in blocking mode.
+ * @param hospi : OSPI handle
+ * @param pData : pointer to data buffer
+ * @param Timeout : Timeout duration
+ * @note This function is used only in Indirect Write Mode
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout)
+{
+ HAL_StatusTypeDef status;
+ uint32_t tickstart = HAL_GetTick();
+ __IO uint32_t *data_reg = &hospi->Instance->DR;
+
+ /* Check the data pointer allocation */
+ if (pData == NULL)
+ {
+ status = HAL_ERROR;
+ hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
+ }
+ else
+ {
+ /* Check the state */
+ if (hospi->State == HAL_OSPI_STATE_CMD_CFG)
+ {
+ /* Configure counters and size */
+ hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1U;
+ hospi->XferSize = hospi->XferCount;
+ hospi->pBuffPtr = pData;
+
+ /* Configure CR register with functional mode as indirect write */
+ MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+
+ do
+ {
+ /* Wait till fifo threshold flag is set to send data */
+ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_FT, SET, tickstart, Timeout);
+
+ if (status != HAL_OK)
+ {
+ break;
+ }
+
+ *((__IO uint8_t *)data_reg) = *hospi->pBuffPtr;
+ hospi->pBuffPtr++;
+ hospi->XferCount--;
+ } while (hospi->XferCount > 0U);
+
+ if (status == HAL_OK)
+ {
+ /* Wait till transfer complete flag is set to go back in idle state */
+ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_TC, SET, tickstart, Timeout);
+
+ if (status == HAL_OK)
+ {
+ /* Clear transfer complete flag */
+ __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC);
+
+ /* Update state */
+ hospi->State = HAL_OSPI_STATE_READY;
+ }
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode.
+ * @param hospi : OSPI handle
+ * @param pData : pointer to data buffer
+ * @param Timeout : Timeout duration
+ * @note This function is used only in Indirect Read Mode
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout)
+{
+ HAL_StatusTypeDef status;
+ uint32_t tickstart = HAL_GetTick();
+ __IO uint32_t *data_reg = &hospi->Instance->DR;
+ uint32_t addr_reg = hospi->Instance->AR;
+ uint32_t ir_reg = hospi->Instance->IR;
+
+ /* Check the data pointer allocation */
+ if (pData == NULL)
+ {
+ status = HAL_ERROR;
+ hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
+ }
+ else
+ {
+ /* Check the state */
+ if (hospi->State == HAL_OSPI_STATE_CMD_CFG)
+ {
+ /* Configure counters and size */
+ hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1U;
+ hospi->XferSize = hospi->XferCount;
+ hospi->pBuffPtr = pData;
+
+ /* Configure CR register with functional mode as indirect read */
+ MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_READ);
+
+ /* Trig the transfer by re-writing address or instruction register */
+ if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)
+ {
+ WRITE_REG(hospi->Instance->AR, addr_reg);
+ }
+ else
+ {
+ if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE)
+ {
+ WRITE_REG(hospi->Instance->AR, addr_reg);
+ }
+ else
+ {
+ WRITE_REG(hospi->Instance->IR, ir_reg);
+ }
+ }
+
+ do
+ {
+ /* Wait till fifo threshold or transfer complete flags are set to read received data */
+ status = OSPI_WaitFlagStateUntilTimeout(hospi, (HAL_OSPI_FLAG_FT | HAL_OSPI_FLAG_TC), SET, tickstart, Timeout);
+
+ if (status != HAL_OK)
+ {
+ break;
+ }
+
+ *hospi->pBuffPtr = *((__IO uint8_t *)data_reg);
+ hospi->pBuffPtr++;
+ hospi->XferCount--;
+ } while (hospi->XferCount > 0U);
+
+ if (status == HAL_OK)
+ {
+ /* Wait till transfer complete flag is set to go back in idle state */
+ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_TC, SET, tickstart, Timeout);
+
+ if (status == HAL_OK)
+ {
+ /* Clear transfer complete flag */
+ __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC);
+
+ /* Update state */
+ hospi->State = HAL_OSPI_STATE_READY;
+ }
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Send an amount of data in non-blocking mode with interrupt.
+ * @param hospi : OSPI handle
+ * @param pData : pointer to data buffer
+ * @note This function is used only in Indirect Write Mode
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_OSPI_Transmit_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the data pointer allocation */
+ if (pData == NULL)
+ {
+ status = HAL_ERROR;
+ hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
+ }
+ else
+ {
+ /* Check the state */
+ if (hospi->State == HAL_OSPI_STATE_CMD_CFG)
+ {
+ /* Configure counters and size */
+ hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1U;
+ hospi->XferSize = hospi->XferCount;
+ hospi->pBuffPtr = pData;
+
+ /* Configure CR register with functional mode as indirect write */
+ MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+
+ /* Clear flags related to interrupt */
+ __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC);
+
+ /* Update the state */
+ hospi->State = HAL_OSPI_STATE_BUSY_TX;
+
+ /* Enable the transfer complete, fifo threshold and transfer error interrupts */
+ __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_FT | HAL_OSPI_IT_TE);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with interrupt.
+ * @param hospi : OSPI handle
+ * @param pData : pointer to data buffer
+ * @note This function is used only in Indirect Read Mode
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_OSPI_Receive_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t addr_reg = hospi->Instance->AR;
+ uint32_t ir_reg = hospi->Instance->IR;
+
+ /* Check the data pointer allocation */
+ if (pData == NULL)
+ {
+ status = HAL_ERROR;
+ hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
+ }
+ else
+ {
+ /* Check the state */
+ if (hospi->State == HAL_OSPI_STATE_CMD_CFG)
+ {
+ /* Configure counters and size */
+ hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1U;
+ hospi->XferSize = hospi->XferCount;
+ hospi->pBuffPtr = pData;
+
+ /* Configure CR register with functional mode as indirect read */
+ MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_READ);
+
+ /* Clear flags related to interrupt */
+ __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC);
+
+ /* Update the state */
+ hospi->State = HAL_OSPI_STATE_BUSY_RX;
+
+ /* Enable the transfer complete, fifo threshold and transfer error interrupts */
+ __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_FT | HAL_OSPI_IT_TE);
+
+ /* Trig the transfer by re-writing address or instruction register */
+ if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)
+ {
+ WRITE_REG(hospi->Instance->AR, addr_reg);
+ }
+ else
+ {
+ if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE)
+ {
+ WRITE_REG(hospi->Instance->AR, addr_reg);
+ }
+ else
+ {
+ WRITE_REG(hospi->Instance->IR, ir_reg);
+ }
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Send an amount of data in non-blocking mode with DMA.
+ * @param hospi : OSPI handle
+ * @param pData : pointer to data buffer
+ * @note This function is used only in Indirect Write Mode
+ * @note If DMA peripheral access is configured as halfword, the number
+ * of data and the fifo threshold should be aligned on halfword
+ * @note If DMA peripheral access is configured as word, the number
+ * of data and the fifo threshold should be aligned on word
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t data_size = hospi->Instance->DLR + 1U;
+ DMA_QListTypeDef *p_queue = {NULL};
+ uint32_t data_width = DMA_DEST_DATAWIDTH_BYTE;
+
+ /* Check the data pointer allocation */
+ if (pData == NULL)
+ {
+ status = HAL_ERROR;
+ hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
+ }
+ else
+ {
+ /* Check the state */
+ if (hospi->State == HAL_OSPI_STATE_CMD_CFG)
+ {
+ if ((hospi->hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ p_queue = hospi->hdma->LinkedListQueue;
+ if ((p_queue != NULL) && (p_queue->Head != NULL))
+ {
+ data_width = p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2;
+ }
+ else
+ {
+ /* Set Error Code */
+ hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
+
+ /* Return function status */
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ data_width = hospi->hdma->Init.DestDataWidth;
+ }
+ /* Configure counters and size */
+ if (data_width == DMA_DEST_DATAWIDTH_BYTE)
+ {
+ hospi->XferCount = data_size;
+ }
+ else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD)
+ {
+ if (((data_size % 2U) != 0U) || ((hospi->Init.FifoThreshold % 2U) != 0U))
+ {
+ /* The number of data or the fifo threshold is not aligned on halfword
+ => no transfer possible with DMA peripheral access configured as halfword */
+ hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
+ status = HAL_ERROR;
+ }
+ else
+ {
+ hospi->XferCount = data_size;
+ }
+ }
+ else if (data_width == DMA_DEST_DATAWIDTH_WORD)
+ {
+ if (((data_size % 4U) != 0U) || ((hospi->Init.FifoThreshold % 4U) != 0U))
+ {
+ /* The number of data or the fifo threshold is not aligned on word
+ => no transfer possible with DMA peripheral access configured as word */
+ hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
+ status = HAL_ERROR;
+ }
+ else
+ {
+ hospi->XferCount = data_size;
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ if (status == HAL_OK)
+ {
+ hospi->XferSize = hospi->XferCount;
+ hospi->pBuffPtr = pData;
+
+ /* Configure CR register with functional mode as indirect write */
+ MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+
+ /* Clear flags related to interrupt */
+ __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC);
+
+ /* Update the state */
+ hospi->State = HAL_OSPI_STATE_BUSY_TX;
+
+ /* Set the DMA transfer complete callback */
+ hospi->hdma->XferCpltCallback = OSPI_DMACplt;
+
+ /* Set the DMA Half transfer complete callback */
+ hospi->hdma->XferHalfCpltCallback = OSPI_DMAHalfCplt;
+
+ /* Set the DMA error callback */
+ hospi->hdma->XferErrorCallback = OSPI_DMAError;
+
+ /* Clear the DMA abort callback */
+ hospi->hdma->XferAbortCallback = NULL;
+
+ /* Enable the transmit DMA Channel */
+ if ((hospi->hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if (hospi->hdma->LinkedListQueue != NULL)
+ {
+ /* Enable the DMA channel */
+ MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET], \
+ (DMA_CTR1_SINC | DMA_CTR1_DINC), (DMA_SINC_INCREMENTED | DMA_DINC_FIXED));
+ MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET], \
+ DMA_CTR2_DREQ, DMA_MEMORY_TO_PERIPH);
+ /* Set DMA data size*/
+ p_queue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hospi->XferSize;
+ /* Set DMA source address */
+ p_queue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
+ /* Set DMA destination address */
+ p_queue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hospi->Instance->DR;
+ status = HAL_DMAEx_List_Start_IT(hospi->hdma);
+ }
+ else
+ {
+ /* Set Error Code */
+ hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
+
+ /* Change OSPI state */
+ hospi->State = HAL_OSPI_STATE_READY;
+
+ /* Return function status */
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Configure the direction of the DMA */
+ MODIFY_REG(hospi->hdma->Instance->CTR1, (DMA_CTR1_SINC | DMA_CTR1_DINC), \
+ (DMA_SINC_INCREMENTED | DMA_DINC_FIXED));
+ MODIFY_REG(hospi->hdma->Instance->CTR2, DMA_CTR2_DREQ, DMA_MEMORY_TO_PERIPH);
+
+ status = HAL_DMA_Start_IT(hospi->hdma, (uint32_t)pData, (uint32_t)&hospi->Instance->DR, hospi->XferSize);
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Enable the transfer error interrupt */
+ __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE);
+
+ /* Enable the DMA transfer by setting the DMAEN bit */
+ SET_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
+ hospi->State = HAL_OSPI_STATE_READY;
+ }
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with DMA.
+ * @param hospi : OSPI handle
+ * @param pData : pointer to data buffer.
+ * @note This function is used only in Indirect Read Mode
+ * @note If DMA peripheral access is configured as halfword, the number
+ * of data and the fifo threshold should be aligned on halfword
+ * @note If DMA peripheral access is configured as word, the number
+ * of data and the fifo threshold should be aligned on word
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t data_size = hospi->Instance->DLR + 1U;
+ uint32_t addr_reg = hospi->Instance->AR;
+ uint32_t ir_reg = hospi->Instance->IR;
+ DMA_QListTypeDef *p_queue = {NULL};
+ uint32_t data_width = DMA_DEST_DATAWIDTH_BYTE;
+ /* Check the data pointer allocation */
+ if (pData == NULL)
+ {
+ status = HAL_ERROR;
+ hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
+ }
+ else
+ {
+ /* Check the state */
+ if (hospi->State == HAL_OSPI_STATE_CMD_CFG)
+ {
+ if ((hospi->hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ p_queue = hospi->hdma->LinkedListQueue;
+ if ((p_queue != NULL) && (p_queue->Head != NULL))
+ {
+ data_width = p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2;
+ }
+ else
+ {
+ /* Set Error Code */
+ hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
+
+ /* Return function status */
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ data_width = hospi->hdma->Init.DestDataWidth;
+ }
+
+ /* Configure counters and size */
+ if (data_width == DMA_DEST_DATAWIDTH_BYTE)
+ {
+ hospi->XferCount = data_size;
+ }
+ else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD)
+ {
+ if (((data_size % 2U) != 0U) || ((hospi->Init.FifoThreshold % 2U) != 0U))
+ {
+ /* The number of data or the fifo threshold is not aligned on halfword
+ => no transfer possible with DMA peripheral access configured as halfword */
+ hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
+ status = HAL_ERROR;
+ }
+ else
+ {
+ hospi->XferCount = data_size;
+ }
+ }
+ else if (data_width == DMA_DEST_DATAWIDTH_WORD)
+ {
+ if (((data_size % 4U) != 0U) || ((hospi->Init.FifoThreshold % 4U) != 0U))
+ {
+ /* The number of data or the fifo threshold is not aligned on word
+ => no transfer possible with DMA peripheral access configured as word */
+ hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
+ status = HAL_ERROR;
+ }
+ else
+ {
+ hospi->XferCount = data_size;
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ if (status == HAL_OK)
+ {
+ hospi->XferSize = hospi->XferCount;
+ hospi->pBuffPtr = pData;
+
+ /* Configure CR register with functional mode as indirect read */
+ MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_READ);
+
+ /* Clear flags related to interrupt */
+ __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC);
+
+ /* Update the state */
+ hospi->State = HAL_OSPI_STATE_BUSY_RX;
+
+ /* Set the DMA transfer complete callback */
+ hospi->hdma->XferCpltCallback = OSPI_DMACplt;
+
+ /* Set the DMA Half transfer complete callback */
+ hospi->hdma->XferHalfCpltCallback = OSPI_DMAHalfCplt;
+
+ /* Set the DMA error callback */
+ hospi->hdma->XferErrorCallback = OSPI_DMAError;
+
+ /* Clear the DMA abort callback */
+ hospi->hdma->XferAbortCallback = NULL;
+
+ /* Enable the transmit DMA Channel */
+ if ((hospi->hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if (hospi->hdma->LinkedListQueue != NULL)
+ {
+ /* Enable the DMA channel */
+ MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET], \
+ (DMA_CTR1_SINC | DMA_CTR1_DINC), (DMA_SINC_FIXED | DMA_DINC_INCREMENTED));
+ MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET], \
+ DMA_CTR2_DREQ, DMA_PERIPH_TO_MEMORY);
+ /* Set DMA data size */
+ p_queue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hospi->XferSize;
+ /* Set DMA source address */
+ p_queue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hospi->Instance->DR;
+ /* Set DMA destination address */
+ p_queue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
+
+ status = HAL_DMAEx_List_Start_IT(hospi->hdma);
+ }
+ else
+ {
+ /* Set Error Code */
+ hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
+
+ /* Change OSPI state */
+ hospi->State = HAL_OSPI_STATE_READY;
+
+ /* Return function status */
+ status = HAL_ERROR;
+ }
+ }
+
+
+ else
+ {
+ /* Configure the direction of the DMA */
+ MODIFY_REG(hospi->hdma->Instance->CTR1, (DMA_CTR1_SINC | DMA_CTR1_DINC), \
+ (DMA_SINC_FIXED | DMA_DINC_INCREMENTED));
+ MODIFY_REG(hospi->hdma->Instance->CTR2, DMA_CTR2_DREQ, DMA_PERIPH_TO_MEMORY);
+
+ status = HAL_DMA_Start_IT(hospi->hdma, (uint32_t)&hospi->Instance->DR, (uint32_t)pData, hospi->XferSize);
+ }
+ if (status == HAL_OK)
+ {
+ /* Enable the transfer error interrupt */
+ __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE);
+
+ /* Trig the transfer by re-writing address or instruction register */
+ if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)
+ {
+ WRITE_REG(hospi->Instance->AR, addr_reg);
+ }
+ else
+ {
+ if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE)
+ {
+ WRITE_REG(hospi->Instance->AR, addr_reg);
+ }
+ else
+ {
+ WRITE_REG(hospi->Instance->IR, ir_reg);
+ }
+ }
+
+ /* Enable the DMA transfer by setting the DMAEN bit */
+ SET_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
+ hospi->State = HAL_OSPI_STATE_READY;
+ }
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Configure the OSPI Automatic Polling Mode in blocking mode.
+ * @param hospi : OSPI handle
+ * @param cfg : structure that contains the polling configuration information.
+ * @param Timeout : Timeout duration
+ * @note This function is used only in Automatic Polling Mode
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
+{
+ HAL_StatusTypeDef status;
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t addr_reg = hospi->Instance->AR;
+ uint32_t ir_reg = hospi->Instance->IR;
+#ifdef USE_FULL_ASSERT
+ uint32_t dlr_reg = hospi->Instance->DLR;
+#endif /* USE_FULL_ASSERT */
+
+ /* Check the parameters of the autopolling configuration structure */
+ assert_param(IS_OSPI_MATCH_MODE(cfg->MatchMode));
+ assert_param(IS_OSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
+ assert_param(IS_OSPI_INTERVAL(cfg->Interval));
+ assert_param(IS_OSPI_STATUS_BYTES_SIZE(dlr_reg + 1U));
+
+ /* Check the state */
+ if ((hospi->State == HAL_OSPI_STATE_CMD_CFG) && (cfg->AutomaticStop == HAL_OSPI_AUTOMATIC_STOP_ENABLE))
+ {
+ /* Wait till busy flag is reset */
+ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout);
+
+ if (status == HAL_OK)
+ {
+ /* Configure registers */
+ WRITE_REG(hospi->Instance->PSMAR, cfg->Match);
+ WRITE_REG(hospi->Instance->PSMKR, cfg->Mask);
+ WRITE_REG(hospi->Instance->PIR, cfg->Interval);
+ MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_PMM | OCTOSPI_CR_APMS | OCTOSPI_CR_FMODE),
+ (cfg->MatchMode | cfg->AutomaticStop | OSPI_FUNCTIONAL_MODE_AUTO_POLLING));
+
+ /* Trig the transfer by re-writing address or instruction register */
+ if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)
+ {
+ WRITE_REG(hospi->Instance->AR, addr_reg);
+ }
+ else
+ {
+ if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE)
+ {
+ WRITE_REG(hospi->Instance->AR, addr_reg);
+ }
+ else
+ {
+ WRITE_REG(hospi->Instance->IR, ir_reg);
+ }
+ }
+
+ /* Wait till status match flag is set to go back in idle state */
+ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_SM, SET, tickstart, Timeout);
+
+ if (status == HAL_OK)
+ {
+ /* Clear status match flag */
+ __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_SM);
+
+ /* Update state */
+ hospi->State = HAL_OSPI_STATE_READY;
+ }
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Configure the OSPI Automatic Polling Mode in non-blocking mode.
+ * @param hospi : OSPI handle
+ * @param cfg : structure that contains the polling configuration information.
+ * @note This function is used only in Automatic Polling Mode
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg)
+{
+ HAL_StatusTypeDef status;
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t addr_reg = hospi->Instance->AR;
+ uint32_t ir_reg = hospi->Instance->IR;
+#ifdef USE_FULL_ASSERT
+ uint32_t dlr_reg = hospi->Instance->DLR;
+#endif /* USE_FULL_ASSERT */
+
+ /* Check the parameters of the autopolling configuration structure */
+ assert_param(IS_OSPI_MATCH_MODE(cfg->MatchMode));
+ assert_param(IS_OSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
+ assert_param(IS_OSPI_INTERVAL(cfg->Interval));
+ assert_param(IS_OSPI_STATUS_BYTES_SIZE(dlr_reg + 1U));
+
+ /* Check the state */
+ if (hospi->State == HAL_OSPI_STATE_CMD_CFG)
+ {
+ /* Wait till busy flag is reset */
+ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout);
+
+ if (status == HAL_OK)
+ {
+ /* Configure registers */
+ WRITE_REG(hospi->Instance->PSMAR, cfg->Match);
+ WRITE_REG(hospi->Instance->PSMKR, cfg->Mask);
+ WRITE_REG(hospi->Instance->PIR, cfg->Interval);
+ MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_PMM | OCTOSPI_CR_APMS | OCTOSPI_CR_FMODE),
+ (cfg->MatchMode | cfg->AutomaticStop | OSPI_FUNCTIONAL_MODE_AUTO_POLLING));
+
+ /* Clear flags related to interrupt */
+ __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_SM);
+
+ /* Update state */
+ hospi->State = HAL_OSPI_STATE_BUSY_AUTO_POLLING;
+
+ /* Enable the status match and transfer error interrupts */
+ __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_SM | HAL_OSPI_IT_TE);
+
+ /* Trig the transfer by re-writing address or instruction register */
+ if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)
+ {
+ WRITE_REG(hospi->Instance->AR, addr_reg);
+ }
+ else
+ {
+ if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE)
+ {
+ WRITE_REG(hospi->Instance->AR, addr_reg);
+ }
+ else
+ {
+ WRITE_REG(hospi->Instance->IR, ir_reg);
+ }
+ }
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Configure the Memory Mapped mode.
+ * @param hospi : OSPI handle
+ * @param cfg : structure that contains the memory mapped configuration information.
+ * @note This function is used only in Memory mapped Mode
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_OSPI_MemoryMapped(OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg)
+{
+ HAL_StatusTypeDef status;
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Check the parameters of the memory-mapped configuration structure */
+ assert_param(IS_OSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
+
+ /* Check the state */
+ if (hospi->State == HAL_OSPI_STATE_CMD_CFG)
+ {
+ /* Wait till busy flag is reset */
+ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout);
+
+ if (status == HAL_OK)
+ {
+ /* Update state */
+ hospi->State = HAL_OSPI_STATE_BUSY_MEM_MAPPED;
+
+ if (cfg->TimeOutActivation == HAL_OSPI_TIMEOUT_COUNTER_ENABLE)
+ {
+ assert_param(IS_OSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
+
+ /* Configure register */
+ WRITE_REG(hospi->Instance->LPTR, cfg->TimeOutPeriod);
+
+ /* Clear flags related to interrupt */
+ __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TO);
+
+ /* Enable the timeout interrupt */
+ __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TO);
+ }
+
+ /* Configure CR register with functional mode as memory-mapped */
+ MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_TCEN | OCTOSPI_CR_FMODE),
+ (cfg->TimeOutActivation | OSPI_FUNCTIONAL_MODE_MEMORY_MAPPED));
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Transfer Error callback.
+ * @param hospi : OSPI handle
+ * @retval None
+ */
+__weak void HAL_OSPI_ErrorCallback(OSPI_HandleTypeDef *hospi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hospi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_OSPI_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Abort completed callback.
+ * @param hospi : OSPI handle
+ * @retval None
+ */
+__weak void HAL_OSPI_AbortCpltCallback(OSPI_HandleTypeDef *hospi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hospi);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_OSPI_AbortCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief FIFO Threshold callback.
+ * @param hospi : OSPI handle
+ * @retval None
+ */
+__weak void HAL_OSPI_FifoThresholdCallback(OSPI_HandleTypeDef *hospi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hospi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_OSPI_FIFOThresholdCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Command completed callback.
+ * @param hospi : OSPI handle
+ * @retval None
+ */
+__weak void HAL_OSPI_CmdCpltCallback(OSPI_HandleTypeDef *hospi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hospi);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_OSPI_CmdCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callback.
+ * @param hospi : OSPI handle
+ * @retval None
+ */
+__weak void HAL_OSPI_RxCpltCallback(OSPI_HandleTypeDef *hospi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hospi);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_OSPI_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx Transfer completed callback.
+ * @param hospi : OSPI handle
+ * @retval None
+ */
+__weak void HAL_OSPI_TxCpltCallback(OSPI_HandleTypeDef *hospi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hospi);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_OSPI_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Half Transfer completed callback.
+ * @param hospi : OSPI handle
+ * @retval None
+ */
+__weak void HAL_OSPI_RxHalfCpltCallback(OSPI_HandleTypeDef *hospi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hospi);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_OSPI_RxHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx Half Transfer completed callback.
+ * @param hospi : OSPI handle
+ * @retval None
+ */
+__weak void HAL_OSPI_TxHalfCpltCallback(OSPI_HandleTypeDef *hospi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hospi);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_OSPI_TxHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Status Match callback.
+ * @param hospi : OSPI handle
+ * @retval None
+ */
+__weak void HAL_OSPI_StatusMatchCallback(OSPI_HandleTypeDef *hospi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hospi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_OSPI_StatusMatchCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Timeout callback.
+ * @param hospi : OSPI handle
+ * @retval None
+ */
+__weak void HAL_OSPI_TimeOutCallback(OSPI_HandleTypeDef *hospi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hospi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_OSPI_TimeOutCallback could be implemented in the user file
+ */
+}
+
+#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
+/**
+ * @brief Register a User OSPI Callback
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hospi : OSPI handle
+ * @param CallbackID : ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_OSPI_ERROR_CB_ID OSPI Error Callback ID
+ * @arg @ref HAL_OSPI_ABORT_CB_ID OSPI Abort Callback ID
+ * @arg @ref HAL_OSPI_FIFO_THRESHOLD_CB_ID OSPI FIFO Threshold Callback ID
+ * @arg @ref HAL_OSPI_CMD_CPLT_CB_ID OSPI Command Complete Callback ID
+ * @arg @ref HAL_OSPI_RX_CPLT_CB_ID OSPI Rx Complete Callback ID
+ * @arg @ref HAL_OSPI_TX_CPLT_CB_ID OSPI Tx Complete Callback ID
+ * @arg @ref HAL_OSPI_RX_HALF_CPLT_CB_ID OSPI Rx Half Complete Callback ID
+ * @arg @ref HAL_OSPI_TX_HALF_CPLT_CB_ID OSPI Tx Half Complete Callback ID
+ * @arg @ref HAL_OSPI_STATUS_MATCH_CB_ID OSPI Status Match Callback ID
+ * @arg @ref HAL_OSPI_TIMEOUT_CB_ID OSPI Timeout Callback ID
+ * @arg @ref HAL_OSPI_MSP_INIT_CB_ID OSPI MspInit callback ID
+ * @arg @ref HAL_OSPI_MSP_DEINIT_CB_ID OSPI MspDeInit callback ID
+ * @param pCallback : pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_OSPI_RegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID,
+ pOSPI_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+
+ if (hospi->State == HAL_OSPI_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_OSPI_ERROR_CB_ID :
+ hospi->ErrorCallback = pCallback;
+ break;
+ case HAL_OSPI_ABORT_CB_ID :
+ hospi->AbortCpltCallback = pCallback;
+ break;
+ case HAL_OSPI_FIFO_THRESHOLD_CB_ID :
+ hospi->FifoThresholdCallback = pCallback;
+ break;
+ case HAL_OSPI_CMD_CPLT_CB_ID :
+ hospi->CmdCpltCallback = pCallback;
+ break;
+ case HAL_OSPI_RX_CPLT_CB_ID :
+ hospi->RxCpltCallback = pCallback;
+ break;
+ case HAL_OSPI_TX_CPLT_CB_ID :
+ hospi->TxCpltCallback = pCallback;
+ break;
+ case HAL_OSPI_RX_HALF_CPLT_CB_ID :
+ hospi->RxHalfCpltCallback = pCallback;
+ break;
+ case HAL_OSPI_TX_HALF_CPLT_CB_ID :
+ hospi->TxHalfCpltCallback = pCallback;
+ break;
+ case HAL_OSPI_STATUS_MATCH_CB_ID :
+ hospi->StatusMatchCallback = pCallback;
+ break;
+ case HAL_OSPI_TIMEOUT_CB_ID :
+ hospi->TimeOutCallback = pCallback;
+ break;
+ case HAL_OSPI_MSP_INIT_CB_ID :
+ hospi->MspInitCallback = pCallback;
+ break;
+ case HAL_OSPI_MSP_DEINIT_CB_ID :
+ hospi->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* Update the error code */
+ hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hospi->State == HAL_OSPI_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_OSPI_MSP_INIT_CB_ID :
+ hospi->MspInitCallback = pCallback;
+ break;
+ case HAL_OSPI_MSP_DEINIT_CB_ID :
+ hospi->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* Update the error code */
+ hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Unregister a User OSPI Callback
+ * OSPI Callback is redirected to the weak (surcharged) predefined callback
+ * @param hospi : OSPI handle
+ * @param CallbackID : ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_OSPI_ERROR_CB_ID OSPI Error Callback ID
+ * @arg @ref HAL_OSPI_ABORT_CB_ID OSPI Abort Callback ID
+ * @arg @ref HAL_OSPI_FIFO_THRESHOLD_CB_ID OSPI FIFO Threshold Callback ID
+ * @arg @ref HAL_OSPI_CMD_CPLT_CB_ID OSPI Command Complete Callback ID
+ * @arg @ref HAL_OSPI_RX_CPLT_CB_ID OSPI Rx Complete Callback ID
+ * @arg @ref HAL_OSPI_TX_CPLT_CB_ID OSPI Tx Complete Callback ID
+ * @arg @ref HAL_OSPI_RX_HALF_CPLT_CB_ID OSPI Rx Half Complete Callback ID
+ * @arg @ref HAL_OSPI_TX_HALF_CPLT_CB_ID OSPI Tx Half Complete Callback ID
+ * @arg @ref HAL_OSPI_STATUS_MATCH_CB_ID OSPI Status Match Callback ID
+ * @arg @ref HAL_OSPI_TIMEOUT_CB_ID OSPI Timeout Callback ID
+ * @arg @ref HAL_OSPI_MSP_INIT_CB_ID OSPI MspInit callback ID
+ * @arg @ref HAL_OSPI_MSP_DEINIT_CB_ID OSPI MspDeInit callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (hospi->State == HAL_OSPI_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_OSPI_ERROR_CB_ID :
+ hospi->ErrorCallback = HAL_OSPI_ErrorCallback;
+ break;
+ case HAL_OSPI_ABORT_CB_ID :
+ hospi->AbortCpltCallback = HAL_OSPI_AbortCpltCallback;
+ break;
+ case HAL_OSPI_FIFO_THRESHOLD_CB_ID :
+ hospi->FifoThresholdCallback = HAL_OSPI_FifoThresholdCallback;
+ break;
+ case HAL_OSPI_CMD_CPLT_CB_ID :
+ hospi->CmdCpltCallback = HAL_OSPI_CmdCpltCallback;
+ break;
+ case HAL_OSPI_RX_CPLT_CB_ID :
+ hospi->RxCpltCallback = HAL_OSPI_RxCpltCallback;
+ break;
+ case HAL_OSPI_TX_CPLT_CB_ID :
+ hospi->TxCpltCallback = HAL_OSPI_TxCpltCallback;
+ break;
+ case HAL_OSPI_RX_HALF_CPLT_CB_ID :
+ hospi->RxHalfCpltCallback = HAL_OSPI_RxHalfCpltCallback;
+ break;
+ case HAL_OSPI_TX_HALF_CPLT_CB_ID :
+ hospi->TxHalfCpltCallback = HAL_OSPI_TxHalfCpltCallback;
+ break;
+ case HAL_OSPI_STATUS_MATCH_CB_ID :
+ hospi->StatusMatchCallback = HAL_OSPI_StatusMatchCallback;
+ break;
+ case HAL_OSPI_TIMEOUT_CB_ID :
+ hospi->TimeOutCallback = HAL_OSPI_TimeOutCallback;
+ break;
+ case HAL_OSPI_MSP_INIT_CB_ID :
+ hospi->MspInitCallback = HAL_OSPI_MspInit;
+ break;
+ case HAL_OSPI_MSP_DEINIT_CB_ID :
+ hospi->MspDeInitCallback = HAL_OSPI_MspDeInit;
+ break;
+ default :
+ /* Update the error code */
+ hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hospi->State == HAL_OSPI_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_OSPI_MSP_INIT_CB_ID :
+ hospi->MspInitCallback = HAL_OSPI_MspInit;
+ break;
+ case HAL_OSPI_MSP_DEINIT_CB_ID :
+ hospi->MspDeInitCallback = HAL_OSPI_MspDeInit;
+ break;
+ default :
+ /* Update the error code */
+ hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+#endif /* defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
+
+/**
+ * @}
+ */
+
+/** @defgroup OSPI_Exported_Functions_Group3 Peripheral Control and State functions
+ * @brief OSPI control and State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control and State functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to :
+ (+) Check in run-time the state of the driver.
+ (+) Check the error code set during last operation.
+ (+) Abort any operation.
+ (+) Manage the Fifo threshold.
+ (+) Configure the timeout duration used in the driver.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Abort the current transmission.
+ * @param hospi : OSPI handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_OSPI_Abort(OSPI_HandleTypeDef *hospi)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t state;
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Check if the state is in one of the busy or configured states */
+ state = hospi->State;
+ if (((state & OSPI_BUSY_STATE_MASK) != 0U) || ((state & OSPI_CFG_STATE_MASK) != 0U))
+ {
+ /* Check if the DMA is enabled */
+ if ((hospi->Instance->CR & OCTOSPI_CR_DMAEN) != 0U)
+ {
+ /* Disable the DMA transfer on the OctoSPI side */
+ CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN);
+
+ /* Disable the DMA transfer on the DMA side */
+ status = HAL_DMA_Abort(hospi->hdma);
+ if (status != HAL_OK)
+ {
+ hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
+ }
+ }
+
+ if (__HAL_OSPI_GET_FLAG(hospi, HAL_OSPI_FLAG_BUSY) != RESET)
+ {
+ /* Perform an abort of the OctoSPI */
+ SET_BIT(hospi->Instance->CR, OCTOSPI_CR_ABORT);
+
+ /* Wait until the transfer complete flag is set to go back in idle state */
+ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_TC, SET, tickstart, hospi->Timeout);
+
+ if (status == HAL_OK)
+ {
+ /* Clear transfer complete flag */
+ __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC);
+
+ /* Wait until the busy flag is reset to go back in idle state */
+ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout);
+
+ if (status == HAL_OK)
+ {
+ /* Update state */
+ hospi->State = HAL_OSPI_STATE_READY;
+ }
+ }
+ }
+ else
+ {
+ /* Update state */
+ hospi->State = HAL_OSPI_STATE_READY;
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Abort the current transmission (non-blocking function)
+ * @param hospi : OSPI handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_OSPI_Abort_IT(OSPI_HandleTypeDef *hospi)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t state;
+
+ /* Check if the state is in one of the busy or configured states */
+ state = hospi->State;
+ if (((state & OSPI_BUSY_STATE_MASK) != 0U) || ((state & OSPI_CFG_STATE_MASK) != 0U))
+ {
+ /* Disable all interrupts */
+ __HAL_OSPI_DISABLE_IT(hospi, (HAL_OSPI_IT_TO | HAL_OSPI_IT_SM | HAL_OSPI_IT_FT | HAL_OSPI_IT_TC | HAL_OSPI_IT_TE));
+
+ /* Update state */
+ hospi->State = HAL_OSPI_STATE_ABORT;
+
+ /* Check if the DMA is enabled */
+ if ((hospi->Instance->CR & OCTOSPI_CR_DMAEN) != 0U)
+ {
+ /* Disable the DMA transfer on the OctoSPI side */
+ CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN);
+
+ /* Disable the DMA transfer on the DMA side */
+ hospi->hdma->XferAbortCallback = OSPI_DMAAbortCplt;
+ if (HAL_DMA_Abort_IT(hospi->hdma) != HAL_OK)
+ {
+ /* Update state */
+ hospi->State = HAL_OSPI_STATE_READY;
+
+ /* Abort callback */
+#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
+ hospi->AbortCpltCallback(hospi);
+#else
+ HAL_OSPI_AbortCpltCallback(hospi);
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/
+ }
+ }
+ else
+ {
+ if (__HAL_OSPI_GET_FLAG(hospi, HAL_OSPI_FLAG_BUSY) != RESET)
+ {
+ /* Clear transfer complete flag */
+ __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC);
+
+ /* Enable the transfer complete interrupts */
+ __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC);
+
+ /* Perform an abort of the OctoSPI */
+ SET_BIT(hospi->Instance->CR, OCTOSPI_CR_ABORT);
+ }
+ else
+ {
+ /* Update state */
+ hospi->State = HAL_OSPI_STATE_READY;
+
+ /* Abort callback */
+#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
+ hospi->AbortCpltCallback(hospi);
+#else
+ HAL_OSPI_AbortCpltCallback(hospi);
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
+ }
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/** @brief Set OSPI Fifo threshold.
+ * @param hospi : OSPI handle.
+ * @param Threshold : Threshold of the Fifo.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold(OSPI_HandleTypeDef *hospi, uint32_t Threshold)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the state */
+ if ((hospi->State & OSPI_BUSY_STATE_MASK) == 0U)
+ {
+ /* Synchronize initialization structure with the new fifo threshold value */
+ hospi->Init.FifoThreshold = Threshold;
+
+ /* Configure new fifo threshold */
+ MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FTHRES, ((hospi->Init.FifoThreshold - 1U) << OCTOSPI_CR_FTHRES_Pos));
+
+ }
+ else
+ {
+ status = HAL_ERROR;
+ hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/** @brief Get OSPI Fifo threshold.
+ * @param hospi : OSPI handle.
+ * @retval Fifo threshold
+ */
+uint32_t HAL_OSPI_GetFifoThreshold(OSPI_HandleTypeDef *hospi)
+{
+ return ((READ_BIT(hospi->Instance->CR, OCTOSPI_CR_FTHRES) >> OCTOSPI_CR_FTHRES_Pos) + 1U);
+}
+
+/** @brief Set OSPI timeout.
+ * @param hospi : OSPI handle.
+ * @param Timeout : Timeout for the memory access.
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_OSPI_SetTimeout(OSPI_HandleTypeDef *hospi, uint32_t Timeout)
+{
+ hospi->Timeout = Timeout;
+ return HAL_OK;
+}
+
+/**
+ * @brief Return the OSPI error code.
+ * @param hospi : OSPI handle
+ * @retval OSPI Error Code
+ */
+uint32_t HAL_OSPI_GetError(OSPI_HandleTypeDef *hospi)
+{
+ return hospi->ErrorCode;
+}
+
+/**
+ * @brief Return the OSPI handle state.
+ * @param hospi : OSPI handle
+ * @retval HAL state
+ */
+uint32_t HAL_OSPI_GetState(OSPI_HandleTypeDef *hospi)
+{
+ /* Return OSPI handle state */
+ return hospi->State;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup OSPI_Exported_Functions_Group4 IO Manager configuration function
+ * @brief OSPI IO Manager configuration function
+ *
+@verbatim
+ ===============================================================================
+ ##### IO Manager configuration function #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to :
+ (+) Configure the IO manager.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the OctoSPI IO manager.
+ * @param hospi : OSPI handle
+ * @param cfg : Configuration of the IO Manager for the instance
+ * @param Timeout : Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t instance;
+ uint8_t index;
+ uint8_t ospi_enabled = 0U;
+ uint8_t other_instance;
+ OSPIM_CfgTypeDef IOM_cfg[OSPI_NB_INSTANCE];
+
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(Timeout);
+
+ /* Check the parameters of the OctoSPI IO Manager configuration structure */
+ assert_param(IS_OSPIM_PORT(cfg->ClkPort));
+ assert_param(IS_OSPIM_DQS_PORT(cfg->DQSPort));
+ assert_param(IS_OSPIM_PORT(cfg->NCSPort));
+ assert_param(IS_OSPIM_IO_PORT(cfg->IOLowPort));
+ assert_param(IS_OSPIM_IO_PORT(cfg->IOHighPort));
+
+ if (hospi->Instance == OCTOSPI1)
+ {
+ instance = 0U;
+ other_instance = 1U;
+ }
+ else
+ {
+ instance = 1U;
+ other_instance = 0U;
+ }
+
+ /**************** Get current configuration of the instances ****************/
+ for (index = 0U; index < OSPI_NB_INSTANCE; index++)
+ {
+ if (OSPIM_GetConfig(index + 1U, &(IOM_cfg[index])) != HAL_OK)
+ {
+ status = HAL_ERROR;
+ hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ /********** Disable both OctoSPI to configure OctoSPI IO Manager **********/
+ if ((OCTOSPI1->CR & OCTOSPI_CR_EN) != 0U)
+ {
+ CLEAR_BIT(OCTOSPI1->CR, OCTOSPI_CR_EN);
+ ospi_enabled |= 0x1U;
+ }
+ if ((OCTOSPI2->CR & OCTOSPI_CR_EN) != 0U)
+ {
+ CLEAR_BIT(OCTOSPI2->CR, OCTOSPI_CR_EN);
+ ospi_enabled |= 0x2U;
+ }
+
+ /***************** Deactivation of previous configuration *****************/
+ CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].NCSPort - 1U)], OCTOSPIM_PCR_NCSEN);
+ if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) != 0U)
+ {
+ /* De-multiplexing should be performed */
+ CLEAR_BIT(OCTOSPIM->CR, OCTOSPIM_CR_MUXEN);
+
+ if (other_instance == 1U)
+ {
+ SET_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort - 1U)], OCTOSPIM_PCR_CLKSRC);
+ if (IOM_cfg[other_instance].DQSPort != 0U)
+ {
+ SET_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort - 1U)], OCTOSPIM_PCR_DQSSRC);
+ }
+ if (IOM_cfg[other_instance].IOLowPort != HAL_OSPIM_IOPORT_NONE)
+ {
+ SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort - 1U)& OSPI_IOM_PORT_MASK)],
+ OCTOSPIM_PCR_IOLSRC_1);
+ }
+ if (IOM_cfg[other_instance].IOHighPort != HAL_OSPIM_IOPORT_NONE)
+ {
+ SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort - 1U)& OSPI_IOM_PORT_MASK)],
+ OCTOSPIM_PCR_IOHSRC_1);
+ }
+ }
+ }
+ else
+ {
+ if (IOM_cfg[instance].ClkPort != 0U)
+ {
+ CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].ClkPort - 1U)], OCTOSPIM_PCR_CLKEN);
+ if (IOM_cfg[instance].DQSPort != 0U)
+ {
+ CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].DQSPort - 1U)], OCTOSPIM_PCR_DQSEN);
+ }
+ if (IOM_cfg[instance].IOLowPort != HAL_OSPIM_IOPORT_NONE)
+ {
+ CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOLowPort - 1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLEN);
+ }
+ if (IOM_cfg[instance].IOHighPort != HAL_OSPIM_IOPORT_NONE)
+ {
+ CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOHighPort - 1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHEN);
+ }
+ }
+ }
+
+ /********************* Deactivation of other instance *********************/
+ if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) || (cfg->DQSPort == IOM_cfg[other_instance].DQSPort) ||
+ (cfg->NCSPort == IOM_cfg[other_instance].NCSPort) || (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) ||
+ (cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort))
+ {
+ if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) &&
+ (cfg->DQSPort == IOM_cfg[other_instance].DQSPort) &&
+ (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) &&
+ (cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort))
+ {
+ /* Multiplexing should be performed */
+ SET_BIT(OCTOSPIM->CR, OCTOSPIM_CR_MUXEN);
+ }
+ else
+ {
+ CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort - 1U)], OCTOSPIM_PCR_CLKEN);
+ if (IOM_cfg[other_instance].DQSPort != 0U)
+ {
+ CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort - 1U)], OCTOSPIM_PCR_DQSEN);
+ }
+ CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].NCSPort - 1U)], OCTOSPIM_PCR_NCSEN);
+ if (IOM_cfg[other_instance].IOLowPort != HAL_OSPIM_IOPORT_NONE)
+ {
+ CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort - 1U)& OSPI_IOM_PORT_MASK)],
+ OCTOSPIM_PCR_IOLEN);
+ }
+ if (IOM_cfg[other_instance].IOHighPort != HAL_OSPIM_IOPORT_NONE)
+ {
+ CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort - 1U)& OSPI_IOM_PORT_MASK)],
+ OCTOSPIM_PCR_IOHEN);
+ }
+ }
+ }
+
+ /******************** Activation of new configuration *********************/
+ MODIFY_REG(OCTOSPIM->PCR[(cfg->NCSPort - 1U)], (OCTOSPIM_PCR_NCSEN | OCTOSPIM_PCR_NCSSRC),
+ (OCTOSPIM_PCR_NCSEN | (instance << OCTOSPIM_PCR_NCSSRC_Pos)));
+
+ if (((cfg->Req2AckTime) >= 1U) && ((cfg->Req2AckTime) <= 256U))
+ {
+ if ((cfg->Req2AckTime - 1U) > ((OCTOSPIM->CR & OCTOSPIM_CR_REQ2ACK_TIME) >> OCTOSPIM_CR_REQ2ACK_TIME_Pos))
+ {
+ MODIFY_REG(OCTOSPIM->CR, OCTOSPIM_CR_REQ2ACK_TIME, ((cfg->Req2AckTime - 1U) << OCTOSPIM_CR_REQ2ACK_TIME_Pos));
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+
+ if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) != 0U)
+ {
+ MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort - 1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), OCTOSPIM_PCR_CLKEN);
+ if (cfg->DQSPort != 0U)
+ {
+ MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort - 1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), OCTOSPIM_PCR_DQSEN);
+ }
+
+ if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U)
+ {
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort - 1U)& OSPI_IOM_PORT_MASK)],
+ (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), OCTOSPIM_PCR_IOLEN);
+ }
+ else if (cfg->IOLowPort != HAL_OSPIM_IOPORT_NONE)
+ {
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort - 1U)& OSPI_IOM_PORT_MASK)],
+ (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), OCTOSPIM_PCR_IOHEN);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U)
+ {
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort - 1U)& OSPI_IOM_PORT_MASK)],
+ (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0));
+ }
+ else if (cfg->IOHighPort != HAL_OSPIM_IOPORT_NONE)
+ {
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort - 1U)& OSPI_IOM_PORT_MASK)],
+ (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0));
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ else
+ {
+ MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort - 1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC),
+ (OCTOSPIM_PCR_CLKEN | (instance << OCTOSPIM_PCR_CLKSRC_Pos)));
+ if (cfg->DQSPort != 0U)
+ {
+ MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort - 1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC),
+ (OCTOSPIM_PCR_DQSEN | (instance << OCTOSPIM_PCR_DQSSRC_Pos)));
+ }
+
+ if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U)
+ {
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort - 1U)& OSPI_IOM_PORT_MASK)],
+ (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC),
+ (OCTOSPIM_PCR_IOLEN | (instance << (OCTOSPIM_PCR_IOLSRC_Pos + 1U))));
+ }
+ else if (cfg->IOLowPort != HAL_OSPIM_IOPORT_NONE)
+ {
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort - 1U)& OSPI_IOM_PORT_MASK)],
+ (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC),
+ (OCTOSPIM_PCR_IOHEN | (instance << (OCTOSPIM_PCR_IOHSRC_Pos + 1U))));
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U)
+ {
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort - 1U)& OSPI_IOM_PORT_MASK)],
+ (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC),
+ (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0 | (instance << (OCTOSPIM_PCR_IOLSRC_Pos + 1U))));
+ }
+ else if (cfg->IOHighPort != HAL_OSPIM_IOPORT_NONE)
+ {
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort - 1U)& OSPI_IOM_PORT_MASK)],
+ (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC),
+ (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0 | (instance << (OCTOSPIM_PCR_IOHSRC_Pos + 1U))));
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+
+ /******* Re-enable both OctoSPI after configure OctoSPI IO Manager ********/
+ if ((ospi_enabled & 0x1U) != 0U)
+ {
+ SET_BIT(OCTOSPI1->CR, OCTOSPI_CR_EN);
+ }
+ if ((ospi_enabled & 0x2U) != 0U)
+ {
+ SET_BIT(OCTOSPI2->CR, OCTOSPI_CR_EN);
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ @cond 0
+ */
+/**
+ * @brief DMA OSPI process complete callback.
+ * @param hdma : DMA handle
+ * @retval None
+ */
+static void OSPI_DMACplt(DMA_HandleTypeDef *hdma)
+{
+ OSPI_HandleTypeDef *hospi = (OSPI_HandleTypeDef *)(hdma->Parent);
+ hospi->XferCount = 0;
+
+ /* Disable the DMA transfer on the OctoSPI side */
+ CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN);
+
+ /* Disable the DMA channel */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Enable the OSPI transfer complete Interrupt */
+ __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC);
+}
+
+/**
+ * @brief DMA OSPI process half complete callback.
+ * @param hdma : DMA handle
+ * @retval None
+ */
+static void OSPI_DMAHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ OSPI_HandleTypeDef *hospi = (OSPI_HandleTypeDef *)(hdma->Parent);
+ hospi->XferCount = (hospi->XferCount >> 1);
+
+ if (hospi->State == HAL_OSPI_STATE_BUSY_RX)
+ {
+#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
+ hospi->RxHalfCpltCallback(hospi);
+#else
+ HAL_OSPI_RxHalfCpltCallback(hospi);
+#endif /*(USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
+ }
+ else
+ {
+#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
+ hospi->TxHalfCpltCallback(hospi);
+#else
+ HAL_OSPI_TxHalfCpltCallback(hospi);
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/
+ }
+}
+
+/**
+ * @brief DMA OSPI communication error callback.
+ * @param hdma : DMA handle
+ * @retval None
+ */
+static void OSPI_DMAError(DMA_HandleTypeDef *hdma)
+{
+ OSPI_HandleTypeDef *hospi = (OSPI_HandleTypeDef *)(hdma->Parent);
+ hospi->XferCount = 0;
+ hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
+
+ /* Disable the DMA transfer on the OctoSPI side */
+ CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN);
+
+ /* Abort the OctoSPI */
+ if (HAL_OSPI_Abort_IT(hospi) != HAL_OK)
+ {
+ /* Disable the interrupts */
+ __HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_FT | HAL_OSPI_IT_TE);
+
+ /* Update state */
+ hospi->State = HAL_OSPI_STATE_READY;
+
+ /* Error callback */
+#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
+ hospi->ErrorCallback(hospi);
+#else
+ HAL_OSPI_ErrorCallback(hospi);
+#endif /*(USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
+ }
+}
+
+/**
+ * @brief DMA OSPI abort complete callback.
+ * @param hdma : DMA handle
+ * @retval None
+ */
+static void OSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma)
+{
+ OSPI_HandleTypeDef *hospi = (OSPI_HandleTypeDef *)(hdma->Parent);
+ hospi->XferCount = 0;
+
+ /* Check the state */
+ if (hospi->State == HAL_OSPI_STATE_ABORT)
+ {
+ /* DMA abort called by OctoSPI abort */
+ if (__HAL_OSPI_GET_FLAG(hospi, HAL_OSPI_FLAG_BUSY) != RESET)
+ {
+ /* Clear transfer complete flag */
+ __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC);
+
+ /* Enable the transfer complete interrupts */
+ __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC);
+
+ /* Perform an abort of the OctoSPI */
+ SET_BIT(hospi->Instance->CR, OCTOSPI_CR_ABORT);
+ }
+ else
+ {
+ /* Update state */
+ hospi->State = HAL_OSPI_STATE_READY;
+
+ /* Abort callback */
+#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
+ hospi->AbortCpltCallback(hospi);
+#else
+ HAL_OSPI_AbortCpltCallback(hospi);
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
+ }
+ }
+ else
+ {
+ /* DMA abort called due to a transfer error interrupt */
+ /* Update state */
+ hospi->State = HAL_OSPI_STATE_READY;
+
+ /* Error callback */
+#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
+ hospi->ErrorCallback(hospi);
+#else
+ HAL_OSPI_ErrorCallback(hospi);
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/
+ }
+}
+
+/**
+ * @brief Wait for a flag state until timeout.
+ * @param hospi : OSPI handle
+ * @param Flag : Flag checked
+ * @param State : Value of the flag expected
+ * @param Timeout : Duration of the timeout
+ * @param Tickstart : Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hospi, uint32_t Flag,
+ FlagStatus State, uint32_t Tickstart, uint32_t Timeout)
+{
+ /* Wait until flag is in expected state */
+ while ((__HAL_OSPI_GET_FLAG(hospi, Flag)) != State)
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+ {
+ /* New check to avoid false timeout detection in case of preemption */
+ if ((hospi->Instance->SR & Flag) != (uint32_t)State)
+ {
+ hospi->State = HAL_OSPI_STATE_ERROR;
+ hospi->ErrorCode |= HAL_OSPI_ERROR_TIMEOUT;
+
+ return HAL_ERROR;
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the registers for the regular command mode.
+ * @param hospi : OSPI handle
+ * @param cmd : structure that contains the command configuration information
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ __IO uint32_t *ccr_reg;
+ __IO uint32_t *tcr_reg;
+ __IO uint32_t *ir_reg;
+ __IO uint32_t *abr_reg;
+
+ /* Re-initialize the value of the functional mode */
+ MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, 0U);
+
+ /* Configure the flash ID */
+ if (hospi->Init.DualQuad == HAL_OSPI_DUALQUAD_DISABLE)
+ {
+ MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FSEL, cmd->FlashId);
+ }
+
+ if (cmd->OperationType == HAL_OSPI_OPTYPE_WRITE_CFG)
+ {
+ ccr_reg = &(hospi->Instance->WCCR);
+ tcr_reg = &(hospi->Instance->WTCR);
+ ir_reg = &(hospi->Instance->WIR);
+ abr_reg = &(hospi->Instance->WABR);
+ }
+ else if (cmd->OperationType == HAL_OSPI_OPTYPE_WRAP_CFG)
+ {
+ ccr_reg = &(hospi->Instance->WPCCR);
+ tcr_reg = &(hospi->Instance->WPTCR);
+ ir_reg = &(hospi->Instance->WPIR);
+ abr_reg = &(hospi->Instance->WPABR);
+ }
+ else
+ {
+ ccr_reg = &(hospi->Instance->CCR);
+ tcr_reg = &(hospi->Instance->TCR);
+ ir_reg = &(hospi->Instance->IR);
+ abr_reg = &(hospi->Instance->ABR);
+ }
+
+ /* Configure the CCR register with DQS and SIOO modes */
+ *ccr_reg = (cmd->DQSMode | cmd->SIOOMode);
+
+ if (cmd->AlternateBytesMode != HAL_OSPI_ALTERNATE_BYTES_NONE)
+ {
+ /* Configure the ABR register with alternate bytes value */
+ *abr_reg = cmd->AlternateBytes;
+
+ /* Configure the CCR register with alternate bytes communication parameters */
+ MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_ABMODE | OCTOSPI_CCR_ABDTR | OCTOSPI_CCR_ABSIZE),
+ (cmd->AlternateBytesMode | cmd->AlternateBytesDtrMode | cmd->AlternateBytesSize));
+ }
+
+ /* Configure the TCR register with the number of dummy cycles */
+ MODIFY_REG((*tcr_reg), OCTOSPI_TCR_DCYC, cmd->DummyCycles);
+
+ if (cmd->DataMode != HAL_OSPI_DATA_NONE)
+ {
+ if (cmd->OperationType == HAL_OSPI_OPTYPE_COMMON_CFG)
+ {
+ /* Configure the DLR register with the number of data */
+ hospi->Instance->DLR = (cmd->NbData - 1U);
+ }
+ }
+
+ if (cmd->InstructionMode != HAL_OSPI_INSTRUCTION_NONE)
+ {
+ if (cmd->AddressMode != HAL_OSPI_ADDRESS_NONE)
+ {
+ if (cmd->DataMode != HAL_OSPI_DATA_NONE)
+ {
+ /* ---- Command with instruction, address and data ---- */
+
+ /* Configure the CCR register with all communication parameters */
+ MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE |
+ OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE |
+ OCTOSPI_CCR_DMODE | OCTOSPI_CCR_DDTR),
+ (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize |
+ cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize |
+ cmd->DataMode | cmd->DataDtrMode));
+ }
+ else
+ {
+ /* ---- Command with instruction and address ---- */
+
+ /* Configure the CCR register with all communication parameters */
+ MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE |
+ OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE),
+ (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize |
+ cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize));
+
+ /* The DHQC bit is linked with DDTR bit which should be activated */
+ if ((hospi->Init.DelayHoldQuarterCycle == HAL_OSPI_DHQC_ENABLE) &&
+ (cmd->InstructionDtrMode == HAL_OSPI_INSTRUCTION_DTR_ENABLE))
+ {
+ MODIFY_REG((*ccr_reg), OCTOSPI_CCR_DDTR, HAL_OSPI_DATA_DTR_ENABLE);
+ }
+ }
+
+ /* Configure the IR register with the instruction value */
+ *ir_reg = cmd->Instruction;
+
+ /* Configure the AR register with the address value */
+ hospi->Instance->AR = cmd->Address;
+ }
+ else
+ {
+ if (cmd->DataMode != HAL_OSPI_DATA_NONE)
+ {
+ /* ---- Command with instruction and data ---- */
+
+ /* Configure the CCR register with all communication parameters */
+ MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE |
+ OCTOSPI_CCR_DMODE | OCTOSPI_CCR_DDTR),
+ (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize |
+ cmd->DataMode | cmd->DataDtrMode));
+ }
+ else
+ {
+ /* ---- Command with only instruction ---- */
+
+ /* Configure the CCR register with all communication parameters */
+ MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE),
+ (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize));
+
+ /* The DHQC bit is linked with DDTR bit which should be activated */
+ if ((hospi->Init.DelayHoldQuarterCycle == HAL_OSPI_DHQC_ENABLE) &&
+ (cmd->InstructionDtrMode == HAL_OSPI_INSTRUCTION_DTR_ENABLE))
+ {
+ MODIFY_REG((*ccr_reg), OCTOSPI_CCR_DDTR, HAL_OSPI_DATA_DTR_ENABLE);
+ }
+ }
+
+ /* Configure the IR register with the instruction value */
+ *ir_reg = cmd->Instruction;
+
+ }
+ }
+ else
+ {
+ if (cmd->AddressMode != HAL_OSPI_ADDRESS_NONE)
+ {
+ if (cmd->DataMode != HAL_OSPI_DATA_NONE)
+ {
+ /* ---- Command with address and data ---- */
+
+ /* Configure the CCR register with all communication parameters */
+ MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE |
+ OCTOSPI_CCR_DMODE | OCTOSPI_CCR_DDTR),
+ (cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize |
+ cmd->DataMode | cmd->DataDtrMode));
+ }
+ else
+ {
+ /* ---- Command with only address ---- */
+
+ /* Configure the CCR register with all communication parameters */
+ MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE),
+ (cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize));
+ }
+
+ /* Configure the AR register with the instruction value */
+ hospi->Instance->AR = cmd->Address;
+ }
+ else
+ {
+ /* ---- Invalid command configuration (no instruction, no address) ---- */
+ status = HAL_ERROR;
+ hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Get the current IOM configuration for an OctoSPI instance.
+ * @param instance_nb : number of the instance
+ * @param cfg : configuration of the IO Manager for the instance
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef *cfg)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t reg;
+ uint32_t value = 0U;
+ uint32_t index;
+
+ if ((instance_nb == 0U) || (instance_nb > OSPI_NB_INSTANCE) || (cfg == NULL))
+ {
+ /* Invalid parameter -> error returned */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Initialize the structure */
+ cfg->ClkPort = 0U;
+ cfg->DQSPort = 0U;
+ cfg->NCSPort = 0U;
+ cfg->IOLowPort = 0U;
+ cfg->IOHighPort = 0U;
+
+ if (instance_nb == 2U)
+ {
+ if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) == 0U)
+ {
+ value = (OCTOSPIM_PCR_CLKSRC | OCTOSPIM_PCR_DQSSRC | OCTOSPIM_PCR_NCSSRC
+ | OCTOSPIM_PCR_IOLSRC_1 | OCTOSPIM_PCR_IOHSRC_1);
+ }
+ else
+ {
+ value = OCTOSPIM_PCR_NCSSRC;
+ }
+ }
+
+ /* Get the information about the instance */
+ for (index = 0U; index < OSPI_IOM_NB_PORTS; index ++)
+ {
+ reg = OCTOSPIM->PCR[index];
+
+ if ((reg & OCTOSPIM_PCR_CLKEN) != 0U)
+ {
+ /* The clock is enabled on this port */
+ if ((reg & OCTOSPIM_PCR_CLKSRC) == (value & OCTOSPIM_PCR_CLKSRC))
+ {
+ /* The clock correspond to the instance passed as parameter */
+ cfg->ClkPort = index + 1U;
+ }
+ }
+
+ if ((reg & OCTOSPIM_PCR_DQSEN) != 0U)
+ {
+ /* The DQS is enabled on this port */
+ if ((reg & OCTOSPIM_PCR_DQSSRC) == (value & OCTOSPIM_PCR_DQSSRC))
+ {
+ /* The DQS correspond to the instance passed as parameter */
+ cfg->DQSPort = index + 1U;
+ }
+ }
+
+ if ((reg & OCTOSPIM_PCR_NCSEN) != 0U)
+ {
+ /* The nCS is enabled on this port */
+ if ((reg & OCTOSPIM_PCR_NCSSRC) == (value & OCTOSPIM_PCR_NCSSRC))
+ {
+ /* The nCS correspond to the instance passed as parameter */
+ cfg->NCSPort = index + 1U;
+ }
+ }
+
+ if ((reg & OCTOSPIM_PCR_IOLEN) != 0U)
+ {
+ /* The IO Low is enabled on this port */
+ if ((reg & OCTOSPIM_PCR_IOLSRC_1) == (value & OCTOSPIM_PCR_IOLSRC_1))
+ {
+ /* The IO Low correspond to the instance passed as parameter */
+ if ((reg & OCTOSPIM_PCR_IOLSRC_0) == 0U)
+ {
+ cfg->IOLowPort = (OCTOSPIM_PCR_IOLEN | (index + 1U));
+ }
+ else
+ {
+ cfg->IOLowPort = (OCTOSPIM_PCR_IOHEN | (index + 1U));
+ }
+ }
+ }
+
+ if ((reg & OCTOSPIM_PCR_IOHEN) != 0U)
+ {
+ /* The IO High is enabled on this port */
+ if ((reg & OCTOSPIM_PCR_IOHSRC_1) == (value & OCTOSPIM_PCR_IOHSRC_1))
+ {
+ /* The IO High correspond to the instance passed as parameter */
+ if ((reg & OCTOSPIM_PCR_IOHSRC_0) == 0U)
+ {
+ cfg->IOHighPort = (OCTOSPIM_PCR_IOLEN | (index + 1U));
+ }
+ else
+ {
+ cfg->IOHighPort = (OCTOSPIM_PCR_IOHEN | (index + 1U));
+ }
+ }
+ }
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+
+/** @defgroup OSPI_Exported_Functions_Group5 Delay Block function
+ * @brief Delay block function
+ *
+@verbatim
+ ===============================================================================
+ ##### Delay Block function #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to :
+ (+) Configure the delay block.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set the Delay Block configuration.
+ * @param hospi : OSPI handle.
+ * @param pdlyb_cfg: Pointer to DLYB configuration structure.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_OSPI_DLYB_SetConfig(OSPI_HandleTypeDef *hospi, HAL_OSPI_DLYB_CfgTypeDef *pdlyb_cfg)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+ uint32_t tickstart;
+
+ /* Enable OCTOSPI Free Running Clock (mandatory) */
+ SET_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK);
+
+ if (hospi->Instance == OCTOSPI1)
+ {
+ /* Enable the DelayBlock */
+ LL_DLYB_Enable(DLYB_OCTOSPI1);
+
+ /* Set the Delay Block configuration */
+ LL_DLYB_SetDelay(DLYB_OCTOSPI1, pdlyb_cfg);
+ status = HAL_OK;
+ }
+
+ else if (hospi->Instance == OCTOSPI2)
+ {
+ /* Enable the DelayBlock */
+ LL_DLYB_Enable(DLYB_OCTOSPI2);
+
+ /* Set the Delay Block configuration */
+ LL_DLYB_SetDelay(DLYB_OCTOSPI2, pdlyb_cfg);
+ status = HAL_OK;
+ }
+
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Disable OCTOSPI */
+ __HAL_OSPI_DISABLE(hospi);
+
+ /* Wait till OSPI Disabled or if Time out is reached, exit */
+ tickstart = HAL_GetTick();
+ while (READ_BIT(hospi->Instance->CR, OCTOSPI_CR_EN) == (uint32_t)SET)
+ {
+ if ((HAL_GetTick() - tickstart) > hospi->Timeout)
+ {
+ hospi->State = HAL_OSPI_STATE_ERROR;
+ hospi->ErrorCode |= HAL_OSPI_ERROR_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Disable Free Running Clock */
+ CLEAR_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK);
+
+ /* Re-Enable OCTOSPI */
+ __HAL_OSPI_ENABLE(hospi);
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Get the Delay Block configuration.
+ * @param hospi : OSPI handle.
+ * @param pdlyb_cfg: Pointer to DLYB configuration structure.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_OSPI_DLYB_GetConfig(OSPI_HandleTypeDef *hospi, HAL_OSPI_DLYB_CfgTypeDef *pdlyb_cfg)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ if (hospi->Instance == OCTOSPI1)
+ {
+ LL_DLYB_GetDelay(DLYB_OCTOSPI1, pdlyb_cfg);
+ status = HAL_OK;
+ }
+ else if (hospi->Instance == OCTOSPI2)
+ {
+ LL_DLYB_GetDelay(DLYB_OCTOSPI2, pdlyb_cfg);
+ status = HAL_OK;
+ }
+
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Get the Delay line length value.
+ * @param hospi : OSPI handle.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_OSPI_DLYB_GetClockPeriod(OSPI_HandleTypeDef *hospi, HAL_OSPI_DLYB_CfgTypeDef *pdlyb_cfg)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+ uint32_t tickstart;
+
+ /* Enable OCTOSPI Free Running Clock (mandatory) */
+ SET_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK);
+
+ if (hospi->Instance == OCTOSPI1)
+ {
+ /* Enable the DelayBlock */
+ LL_DLYB_Enable(DLYB_OCTOSPI1);
+
+ /* try to detect Period */
+ if (LL_DLYB_GetClockPeriod(DLYB_OCTOSPI1, pdlyb_cfg) == (uint32_t)SUCCESS)
+ {
+ status = HAL_OK;
+ }
+
+ /* Disable the DelayBlock */
+ LL_DLYB_Enable(DLYB_OCTOSPI1);
+ }
+
+ else if (hospi->Instance == OCTOSPI2)
+ {
+ /* Enable the DelayBlock */
+ LL_DLYB_Enable(DLYB_OCTOSPI2);
+
+ /* try to detect Period */
+ if (LL_DLYB_GetClockPeriod(DLYB_OCTOSPI2, pdlyb_cfg) == (uint32_t)SUCCESS)
+ {
+ status = HAL_OK;
+ }
+
+ /* Disable the DelayBlock */
+ LL_DLYB_Enable(DLYB_OCTOSPI2);
+ }
+
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Disable OCTOSPI */
+ __HAL_OSPI_DISABLE(hospi);
+
+ /* Wait till OSPI Disabled or if Time out is reached, exit */
+ tickstart = HAL_GetTick();
+ while (READ_BIT(hospi->Instance->CR, OCTOSPI_CR_EN) == (uint32_t)SET)
+ {
+ if ((HAL_GetTick() - tickstart) > hospi->Timeout)
+ {
+ hospi->State = HAL_OSPI_STATE_ERROR;
+ hospi->ErrorCode |= HAL_OSPI_ERROR_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Disable Free Running Clock */
+ CLEAR_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK);
+
+ /* Re-Enable OCTOSPI */
+ __HAL_OSPI_ENABLE(hospi);
+
+ /* Return function status */
+ return status;
+}
+/**
+ @endcond
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_OSPI_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* OCTOSPI || OCTOSPI1 || OCTOSPI2 */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_otfdec.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_otfdec.c
new file mode 100644
index 00000000..56a27a61
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_otfdec.c
@@ -0,0 +1,1154 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_otfdec.c
+ * @author MCD Application Team
+ * @brief OTFDEC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the On-The-Fly Decryption/Encryption (OTFDEC)
+ * peripheral:
+ * + Initialization and de-initialization functions
+ * + Region setting/enable functions
+ * + Peripheral State functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The OTFDEC HAL driver can be used as follows:
+
+ (#) Declare an OTFDEC_HandleTypeDef handle structure (eg. OTFDEC_HandleTypeDef hotfdec).
+
+ (#) Initialize the OTFDEC low level resources by implementing the HAL_OTFDEC_MspInit() API:
+ (++) Enable the OTFDEC interface clock.
+ (++) NVIC configuration if interrupts are used
+ (+++) Configure the OTFDEC interrupt priority.
+ (+++) Enable the NVIC OTFDEC IRQ handle.
+
+ (#) Initialize the OTFDEC peripheral by calling the HAL_OTFDEC_Init() API.
+
+ (#) In the case of encryption, enable ciphering mode for the peripheral
+
+ (#) For each region,
+
+ (++) Configure the region deciphering mode by calling the HAL_OTFDEC_RegionSetMode() API.
+
+ (++) Write the region Key by calling the HAL_OTFDEC_RegionSetKey() API. If desired,
+ read the key CRC by calling HAL_OTFDEC_RegionGetKeyCRC() API and compare the
+ result with the theoretically expected CRC.
+
+ (++) Initialize the OTFDEC region config structure with the Nonce, protected
+ region start and end addresses and firmware version, and wrap-up the region
+ configuration by calling HAL_OTFDEC_RegionConfig() API.
+
+ (#) At this point, the OTFDEC region configuration is done and the deciphering
+ or enciphering enabled. The region can be deciphered on the fly after
+ having made sure the OctoSPI is configured in memory-mapped mode or data can
+ be enciphered by calling HAL_OTFDEC_Cipher() API.
+
+ [..]
+ (@) Warning: the OTFDEC en/deciphering is based on a different endianness compared
+ to the AES-CTR as implemented in the AES peripheral. E.g., if the OTFEC
+ resorts to the Key (B0, B1, B2, B3) where Bi are 32-bit longwords and B0
+ is the Least Significant Word, the AES has to be configured with the Key
+ (B3, B2, B1, B0) to report the same result (with the same swapping applied
+ to the Initialization Vector).
+
+ [..]
+
+ *** Callback registration ***
+ =============================================
+ [..]
+
+ The compilation flag USE_HAL_OTFDEC_REGISTER_CALLBACKS, when set to 1,
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions @ref HAL_OTFDEC_RegisterCallback()
+ to register an interrupt callback.
+ [..]
+
+ Function @ref HAL_OTFDEC_RegisterCallback() allows to register following callbacks:
+ (+) ErrorCallback : OTFDEC error callback
+ (+) MspInitCallback : OTFDEC Msp Init callback
+ (+) MspDeInitCallback : OTFDEC Msp DeInit callback
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+ [..]
+
+ Use function @ref HAL_OTFDEC_UnRegisterCallback to reset a callback to the default
+ weak function.
+ [..]
+
+ @ref HAL_OTFDEC_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) ErrorCallback : OTFDEC error callback
+ (+) MspInitCallback : OTFDEC Msp Init callback
+ (+) MspDeInitCallback : OTFDEC Msp DeInit callback
+ [..]
+
+ By default, after the @ref HAL_OTFDEC_Init() and when the state is @ref HAL_OTFDEC_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ example @ref HAL_OTFDEC_ErrorCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak functions in the @ref HAL_OTFDEC_Init()/ @ref HAL_OTFDEC_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ [..]
+
+ If MspInit or MspDeInit are not null, the @ref HAL_OTFDEC_Init()/ @ref HAL_OTFDEC_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+ [..]
+
+ Callbacks can be registered/unregistered in @ref HAL_OTFDEC_STATE_READY state only.
+ Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ in @ref HAL_OTFDEC_STATE_READY or @ref HAL_OTFDEC_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ [..]
+
+ Then, the user first registers the MspInit/MspDeInit user callbacks
+ using @ref HAL_OTFDEC_RegisterCallback() before calling @ref HAL_OTFDEC_DeInit()
+ or @ref HAL_OTFDEC_Init() function.
+ [..]
+
+ When the compilation flag USE_HAL_OTFDEC_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup OTFDEC OTFDEC
+ * @brief OTFDEC HAL module driver.
+ * @{
+ */
+
+
+#ifdef HAL_OTFDEC_MODULE_ENABLED
+
+#if defined(OTFDEC1)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup OTFDEC_Exported_Functions
+ * @{
+ */
+
+/** @defgroup OTFDEC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the OTFDEC peripheral and create the associated handle.
+ * @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
+ * the configuration information for OTFDEC module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_OTFDEC_Init(OTFDEC_HandleTypeDef *hotfdec)
+{
+ /* Check the OTFDEC handle allocation */
+ if (hotfdec == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
+
+ if (hotfdec->State == HAL_OTFDEC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ __HAL_UNLOCK(hotfdec);
+
+#if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)
+ /* Init the OTFDEC Callback settings */
+ hotfdec->ErrorCallback = HAL_OTFDEC_ErrorCallback; /* Legacy weak callback */
+
+ if (hotfdec->MspInitCallback == NULL)
+ {
+ hotfdec->MspInitCallback = HAL_OTFDEC_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware */
+ hotfdec->MspInitCallback(hotfdec);
+#else
+ /* Init the low level hardware */
+ HAL_OTFDEC_MspInit(hotfdec);
+#endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */
+ }
+
+ /* Change the OTFDEC state */
+ hotfdec->State = HAL_OTFDEC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitialize the OTFDEC peripheral.
+ * @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
+ * the configuration information for OTFDEC module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_OTFDEC_DeInit(OTFDEC_HandleTypeDef *hotfdec)
+{
+ /* Check the OTFDEC handle allocation */
+ if (hotfdec == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
+
+ /* Change the OTFDEC state */
+ hotfdec->State = HAL_OTFDEC_STATE_BUSY;
+
+#if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)
+ if (hotfdec->MspDeInitCallback == NULL)
+ {
+ hotfdec->MspDeInitCallback = HAL_OTFDEC_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware: CLOCK, NVIC */
+ hotfdec->MspDeInitCallback(hotfdec);
+#else
+ /* DeInit the low level hardware: CLOCK, NVIC */
+ HAL_OTFDEC_MspDeInit(hotfdec);
+#endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */
+
+ /* Change the OTFDEC state */
+ hotfdec->State = HAL_OTFDEC_STATE_RESET;
+
+ /* Reset OTFDEC error status */
+ hotfdec->ErrorCode = HAL_OTFDEC_ERROR_NONE;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hotfdec);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the OTFDEC MSP.
+ * @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
+ * the configuration information for OTFDEC module
+ * @retval None
+ */
+__weak void HAL_OTFDEC_MspInit(OTFDEC_HandleTypeDef *hotfdec)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hotfdec);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_OTFDEC_MspInit can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief DeInitialize OTFDEC MSP.
+ * @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
+ * the configuration information for OTFDEC module
+ * @retval None
+ */
+__weak void HAL_OTFDEC_MspDeInit(OTFDEC_HandleTypeDef *hotfdec)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hotfdec);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_OTFDEC_MspDeInit can be implemented in the user file.
+ */
+}
+
+#if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User OTFDEC Callback
+ * To be used instead of the weak predefined callback
+ * @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
+ * the configuration information for OTFDEC module
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_OTFDEC_ERROR_CB_ID OTFDEC error callback ID
+ * @arg @ref HAL_OTFDEC_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_OTFDEC_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_OTFDEC_RegisterCallback(OTFDEC_HandleTypeDef *hotfdec, HAL_OTFDEC_CallbackIDTypeDef CallbackID,
+ pOTFDEC_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hotfdec->ErrorCode |= HAL_OTFDEC_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ if (hotfdec->State == HAL_OTFDEC_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_OTFDEC_ERROR_CB_ID :
+ hotfdec->ErrorCallback = pCallback;
+ break;
+
+ case HAL_OTFDEC_MSPINIT_CB_ID :
+ hotfdec->MspInitCallback = pCallback;
+ break;
+
+ case HAL_OTFDEC_MSPDEINIT_CB_ID :
+ hotfdec->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hotfdec->ErrorCode |= HAL_OTFDEC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_OTFDEC_STATE_RESET == hotfdec->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_OTFDEC_MSPINIT_CB_ID :
+ hotfdec->MspInitCallback = pCallback;
+ break;
+
+ case HAL_OTFDEC_MSPDEINIT_CB_ID :
+ hotfdec->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hotfdec->ErrorCode |= HAL_OTFDEC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hotfdec->ErrorCode |= HAL_OTFDEC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Unregister a OTFDEC Callback
+ * OTFDEC callback is redirected to the weak predefined callback
+ * @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
+ * the configuration information for OTFDEC module
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_OTFDEC_ERROR_CB_ID OTFDEC error callback ID
+ * @arg @ref HAL_OTFDEC_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_OTFDEC_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_OTFDEC_UnRegisterCallback(OTFDEC_HandleTypeDef *hotfdec, HAL_OTFDEC_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (hotfdec->State == HAL_OTFDEC_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_OTFDEC_ERROR_CB_ID :
+ hotfdec->ErrorCallback = HAL_OTFDEC_ErrorCallback;
+ break;
+
+ case HAL_OTFDEC_MSPINIT_CB_ID :
+ hotfdec->MspInitCallback = HAL_OTFDEC_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_OTFDEC_MSPDEINIT_CB_ID :
+ hotfdec->MspDeInitCallback = HAL_OTFDEC_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hotfdec->ErrorCode |= HAL_OTFDEC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_OTFDEC_STATE_RESET == hotfdec->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_OTFDEC_MSPINIT_CB_ID :
+ hotfdec->MspInitCallback = HAL_OTFDEC_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_OTFDEC_MSPDEINIT_CB_ID :
+ hotfdec->MspDeInitCallback = HAL_OTFDEC_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hotfdec->ErrorCode |= HAL_OTFDEC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hotfdec->ErrorCode |= HAL_OTFDEC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+#endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup OTFDEC_Exported_Functions_Group2 OTFDEC IRQ handler management
+ * @brief OTFDEC IRQ handler.
+ *
+@verbatim
+ ==============================================================================
+ ##### OTFDEC IRQ handler management #####
+ ==============================================================================
+[..] This section provides OTFDEC IRQ handler function.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Handle OTFDEC interrupt request.
+ * @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
+ * the configuration information for OTFDEC module
+ * @retval None
+ */
+void HAL_OTFDEC_IRQHandler(OTFDEC_HandleTypeDef *hotfdec)
+{
+ uint32_t isr_reg;
+
+ isr_reg = READ_REG(hotfdec->Instance->ISR);
+ if ((isr_reg & OTFDEC_ISR_SEIF) == OTFDEC_ISR_SEIF)
+ {
+ SET_BIT(hotfdec->Instance->ICR, OTFDEC_ICR_SEIF);
+ hotfdec->ErrorCode |= HAL_OTFDEC_SECURITY_ERROR;
+ }
+ if ((isr_reg & OTFDEC_ISR_XONEIF) == OTFDEC_ISR_XONEIF)
+ {
+ SET_BIT(hotfdec->Instance->ICR, OTFDEC_ICR_XONEIF);
+ hotfdec->ErrorCode |= HAL_OTFDEC_EXECUTE_ERROR;
+ }
+ if ((isr_reg & OTFDEC_ISR_KEIF) == OTFDEC_ISR_KEIF)
+ {
+ SET_BIT(hotfdec->Instance->ICR, OTFDEC_ICR_KEIF);
+ hotfdec->ErrorCode |= HAL_OTFDEC_KEY_ERROR;
+ }
+
+#if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)
+ hotfdec->ErrorCallback(hotfdec);
+#else
+ HAL_OTFDEC_ErrorCallback(hotfdec);
+#endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief OTFDEC error callback.
+ * @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
+ * the configuration information for OTFDEC module
+ * @retval None
+ */
+__weak void HAL_OTFDEC_ErrorCallback(OTFDEC_HandleTypeDef *hotfdec)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hotfdec);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_OTFDEC_ErrorCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+
+
+
+/** @defgroup OTFDEC_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Peripheral control functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to configure the OTFDEC peripheral
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Lock region keys.
+ * @note Writes to this region KEYRx registers are ignored until next OTFDEC reset.
+ * @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
+ * the configuration information for OTFDEC module
+ * @param RegionIndex index of region the keys of which are locked
+ * @retval HAL state
+ */
+HAL_StatusTypeDef HAL_OTFDEC_RegionKeyLock(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex)
+{
+ OTFDEC_Region_TypeDef *region;
+ uint32_t address;
+
+ /* Check the parameters */
+ assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
+ assert_param(IS_OTFDEC_REGIONINDEX(RegionIndex));
+
+ /* Take Lock */
+ __HAL_LOCK(hotfdec);
+
+ address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
+ region = (OTFDEC_Region_TypeDef *)address;
+
+ SET_BIT(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_KEYLOCK);
+
+ /* Release Lock */
+ __HAL_UNLOCK(hotfdec);
+
+ /* Status is okay */
+ return HAL_OK;
+}
+
+/**
+ * @brief Set region keys.
+ * @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
+ * the configuration information for OTFDEC module
+ * @param RegionIndex index of region the keys of which are set
+ * @param pKey pointer at set of keys
+ * @note The API reads the key CRC computed by the peripheral and compares it with that
+ * theoretically expected. An error is reported if they are different.
+ * @retval HAL state
+ */
+HAL_StatusTypeDef HAL_OTFDEC_RegionSetKey(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t *pKey)
+{
+ OTFDEC_Region_TypeDef *region;
+ uint32_t address;
+
+ /* Check the parameters */
+ assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
+ assert_param(IS_OTFDEC_REGIONINDEX(RegionIndex));
+
+ if (pKey == NULL)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Take Lock */
+ __HAL_LOCK(hotfdec);
+
+ address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
+ region = (OTFDEC_Region_TypeDef *)address;
+
+ /* Set Key */
+ WRITE_REG(region->REG_KEYR0, pKey[0]);
+
+ __DSB();
+ __ISB();
+
+ WRITE_REG(region->REG_KEYR1, pKey[1]);
+
+ __DSB();
+ __ISB();
+
+ WRITE_REG(region->REG_KEYR2, pKey[2]);
+
+ __DSB();
+ __ISB();
+
+ WRITE_REG(region->REG_KEYR3, pKey[3]);
+
+ /* Compute theoretically expected CRC and compare it with that reported by the peripheral */
+ if (HAL_OTFDEC_KeyCRCComputation(pKey) != HAL_OTFDEC_RegionGetKeyCRC(hotfdec, RegionIndex))
+ {
+ /* Release Lock */
+ __HAL_UNLOCK(hotfdec);
+
+ /* Status is okay */
+ return HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hotfdec);
+
+ /* Status is okay */
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief Set region mode.
+ * @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
+ * the configuration information for OTFDEC module
+ * @param RegionIndex index of region the mode of which is set
+ * @param mode This parameter can be only:
+ * @arg @ref OTFDEC_REG_MODE_INSTRUCTION_OR_DATA_ACCESSES
+ All read accesses are decrypted (instruction or data)
+ * @arg @ref OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY_WITH_CIPHER
+ Only instruction accesses are decrypted with proprietary cipher activated
+ * @retval HAL state
+ */
+HAL_StatusTypeDef HAL_OTFDEC_RegionSetMode(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t mode)
+{
+ OTFDEC_Region_TypeDef *region;
+ uint32_t address;
+
+ /* Check the parameters */
+ assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
+ assert_param(IS_OTFDEC_REGIONINDEX(RegionIndex));
+ assert_param(IS_OTFDEC_REGION_OPERATING_MODE(mode));
+
+ /* Take Lock */
+ __HAL_LOCK(hotfdec);
+
+ address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
+ region = (OTFDEC_Region_TypeDef *)address;
+
+ /* Set mode */
+ MODIFY_REG(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_MODE, mode);
+
+ /* Release Lock */
+ __HAL_UNLOCK(hotfdec);
+
+ /* Status is okay */
+ return HAL_OK;
+}
+
+/**
+ * @brief Set region configuration.
+ * @note Region enciphering/deciphering is enabled at the end of this function
+ * @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
+ * the configuration information for OTFDEC module
+ * @param RegionIndex index of region that is configured
+ * @param Config pointer on structure containing the region configuration parameters
+ * @param lock configuration lock enable or disable parameter
+ * This parameter can be one of the following values:
+ * @arg @ref OTFDEC_REG_CONFIGR_LOCK_DISABLE OTFDEC region configuration is not locked
+ * @arg @ref OTFDEC_REG_CONFIGR_LOCK_ENABLE OTFDEC region configuration is locked
+ * @retval HAL state
+ */
+HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex,
+ OTFDEC_RegionConfigTypeDef *Config, uint32_t lock)
+{
+ OTFDEC_Region_TypeDef *region;
+ uint32_t address;
+
+ /* Check the parameters */
+ assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
+ assert_param(IS_OTFDEC_REGIONINDEX(RegionIndex));
+ assert_param(IS_OTFDEC_REGION_CONFIG_LOCK(lock));
+
+ if (Config == NULL)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+
+ /* Take Lock */
+ __HAL_LOCK(hotfdec);
+
+ address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
+ region = (OTFDEC_Region_TypeDef *)address;
+
+ /* Set Nonce */
+ WRITE_REG(region->REG_NONCER0, Config->Nonce[0]);
+
+ WRITE_REG(region->REG_NONCER1, Config->Nonce[1]);
+
+ /* Write region protected area start and end addresses */
+ WRITE_REG(region->REG_START_ADDR, Config->StartAddress);
+
+ WRITE_REG(region->REG_END_ADDR, Config->EndAddress);
+
+ /* Write Version */
+ MODIFY_REG(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_VERSION,
+ (uint32_t)(Config->Version) << OTFDEC_REG_CONFIGR_VERSION_Pos);
+
+ /* Enable region deciphering or enciphering (depending of OTFDEC_CR ENC bit setting) */
+ SET_BIT(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_REG_ENABLE);
+
+ /* Lock the region configuration according to lock parameter value */
+ if (lock == OTFDEC_REG_CONFIGR_LOCK_ENABLE)
+ {
+ SET_BIT(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_LOCK_ENABLE);
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hotfdec);
+
+ /* Status is okay */
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief Configure OTFDEC attributes.
+ * @note This function sets or resets regions privileged access protection.
+ * @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
+ * the configuration information for OTFDEC module
+ * @param Attributes This parameter can be only:
+ * @arg @ref OTFDEC_ATTRIBUTE_PRIV Set privileged access protection
+ * @arg @ref OTFDEC_ATTRIBUTE_NPRIV Reset privileged access protection
+ * @retval HAL state
+ */
+HAL_StatusTypeDef HAL_OTFDEC_ConfigAttributes(OTFDEC_HandleTypeDef *hotfdec, uint32_t Attributes)
+{
+ /* Check the parameters */
+ assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
+ assert_param(IS_OTFDEC_ATTRIBUTE(Attributes));
+
+ /* Take Lock */
+ __HAL_LOCK(hotfdec);
+
+ MODIFY_REG(hotfdec->Instance->PRIVCFGR, OTFDEC_PRIVCFGR_PRIV, Attributes);
+
+ /* Release Lock */
+ __HAL_UNLOCK(hotfdec);
+
+ /* Status is okay */
+ return HAL_OK;
+}
+
+/**
+ * @brief Compute Key CRC
+ * @param pKey pointer at set of keys
+ * @retval CRC value
+ */
+uint32_t HAL_OTFDEC_KeyCRCComputation(uint32_t *pKey)
+{
+ uint8_t crc7_poly = 0x7;
+ uint32_t key_strobe[4] = {0xAA55AA55U, 0x3U, 0x18U, 0xC0U};
+ uint8_t i;
+ uint8_t crc = 0;
+ uint32_t j;
+ uint32_t keyval;
+ uint32_t k;
+ uint32_t *temp = pKey;
+
+ for (j = 0U; j < 4U; j++)
+ {
+ keyval = *temp;
+ temp++;
+ if (j == 0U)
+ {
+ keyval ^= key_strobe[0];
+ }
+ else
+ {
+ keyval ^= (key_strobe[j] << 24) | ((uint32_t)crc << 16) | (key_strobe[j] << 8) | crc;
+ }
+
+ crc = 0;
+ for (i = 0; i < (uint8_t)32; i++)
+ {
+ k = ((((uint32_t)crc >> 7) ^ ((keyval >> ((uint8_t)31 - i)) & ((uint8_t)0xF)))) & 1U;
+ crc <<= 1;
+ if (k != 0U)
+ {
+ crc ^= crc7_poly;
+ }
+ }
+
+ crc ^= (uint8_t)0x55;
+ }
+
+ return (uint32_t) crc;
+}
+
+/**
+ * @brief Enable peripheral enciphering.
+ * @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
+ * the configuration information for OTFDEC module
+ * @note By default, deciphering mode is enabled at reset
+ * @retval HAL state
+ */
+HAL_StatusTypeDef HAL_OTFDEC_EnableEnciphering(OTFDEC_HandleTypeDef *hotfdec)
+{
+ /* Take Lock */
+ __HAL_LOCK(hotfdec);
+
+ SET_BIT(hotfdec->Instance->CR, OTFDEC_CR_ENC);
+
+ /* Release Lock */
+ __HAL_UNLOCK(hotfdec);
+
+ /* Status is okay */
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable peripheral enciphering.
+ * @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
+ * the configuration information for OTFDEC module
+ * @retval HAL state
+ */
+HAL_StatusTypeDef HAL_OTFDEC_DisableEnciphering(OTFDEC_HandleTypeDef *hotfdec)
+{
+ /* Take Lock */
+ __HAL_LOCK(hotfdec);
+
+ CLEAR_BIT(hotfdec->Instance->CR, OTFDEC_CR_ENC);
+
+ /* Release Lock */
+ __HAL_UNLOCK(hotfdec);
+
+ /* Status is okay */
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Cipher data.
+ * @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
+ * the configuration information for OTFDEC module
+ * @param RegionIndex index of region the configuration of which is used to encipher
+ * @param input plain data
+ * @param output ciphered data
+ * @param size plain data size in words
+ * @param start_address starting address in the external memory area
+ where the enciphered data will be eventually stored
+ * @note Region configuration parameters and OTFDEC_CR ENC bit must be set.
+ * @note output pointer points at a temporary area in RAM to store the ciphered data. It is up to the user code
+ * to copy the ciphered data in external RAM once the enciphering process is over.
+ * @retval HAL state
+ */
+HAL_StatusTypeDef HAL_OTFDEC_Cipher(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex,
+ uint32_t *input, uint32_t *output, uint32_t size, uint32_t start_address)
+{
+ uint32_t j;
+ __IO uint32_t *extMem_ptr = (uint32_t *)start_address;
+ uint32_t *in_ptr = input;
+ uint32_t *out_ptr = output;
+
+ /* Check the parameters */
+ assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
+ assert_param(IS_OTFDEC_REGIONINDEX(RegionIndex));
+
+ if ((input == NULL) || (output == NULL) || (size == 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Take Lock */
+ __HAL_LOCK(hotfdec);
+
+ for (j = 0; j < size; j++)
+ {
+ *extMem_ptr = *in_ptr;
+ in_ptr++;
+ *out_ptr = *extMem_ptr;
+ out_ptr++;
+ extMem_ptr++;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hotfdec);
+
+ /* Status is okay */
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief Enable region processing (enciphering or deciphering).
+ * @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
+ * the configuration information for OTFDEC module
+ * @param RegionIndex index of region the enciphering or deciphering is enabled
+ * @note An error is reported when the configuration is locked.
+ * @retval HAL state
+ */
+HAL_StatusTypeDef HAL_OTFDEC_RegionEnable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex)
+{
+ OTFDEC_Region_TypeDef *region;
+ uint32_t address;
+
+ /* Check the parameters */
+ assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
+ assert_param(IS_OTFDEC_REGIONINDEX(RegionIndex));
+
+ /* Take Lock */
+ __HAL_LOCK(hotfdec);
+
+ address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
+ region = (OTFDEC_Region_TypeDef *)address;
+
+ if (READ_BIT(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_LOCK_ENABLE) == OTFDEC_REG_CONFIGR_LOCK_ENABLE)
+ {
+ /* Configuration is locked, REG_EN bit can't be modified */
+ __HAL_UNLOCK(hotfdec);
+
+ return HAL_ERROR;
+ }
+
+ /* Enable region processing */
+ SET_BIT(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_REG_ENABLE);
+
+ /* Release Lock */
+ __HAL_UNLOCK(hotfdec);
+
+ /* Status is okay */
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable region processing (enciphering or deciphering).
+ * @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
+ * the configuration information for OTFDEC module
+ * @param RegionIndex index of region the enciphering or deciphering is disabled
+ * @note An error is reported when the configuration is locked.
+ * @retval HAL state
+ */
+HAL_StatusTypeDef HAL_OTFDEC_RegionDisable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex)
+{
+ OTFDEC_Region_TypeDef *region;
+ uint32_t address;
+
+ /* Check the parameters */
+ assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
+ assert_param(IS_OTFDEC_REGIONINDEX(RegionIndex));
+
+ /* Take Lock */
+ __HAL_LOCK(hotfdec);
+
+ address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
+ region = (OTFDEC_Region_TypeDef *)address;
+
+ if (READ_BIT(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_LOCK_ENABLE) == OTFDEC_REG_CONFIGR_LOCK_ENABLE)
+ {
+ /* Configuration is locked, REG_EN bit can't be modified */
+ __HAL_UNLOCK(hotfdec);
+
+ return HAL_ERROR;
+ }
+
+ /* Disable region processing */
+ CLEAR_BIT(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_REG_ENABLE);
+
+ /* Release Lock */
+ __HAL_UNLOCK(hotfdec);
+
+ /* Status is okay */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup OTFDEC_Exported_Functions_Group4 Peripheral State and Status functions
+ * @brief Peripheral State functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the OTFDEC state.
+ * @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
+ * the configuration information for OTFDEC module
+ * @retval HAL state
+ */
+HAL_OTFDEC_StateTypeDef HAL_OTFDEC_GetState(OTFDEC_HandleTypeDef *hotfdec)
+{
+ return hotfdec->State;
+}
+
+/**
+ * @brief Get OTFDEC configuration attributes.
+ * @note This function returns whether or not the regions access protection is in privileged mode.
+ * @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
+ * the configuration information for OTFDEC module
+ * @param Attributes pointer to attributes variable. This parameter can be only:
+ * @arg @ref OTFDEC_ATTRIBUTE_PRIV Set privileged access protection
+ * @arg @ref OTFDEC_ATTRIBUTE_NPRIV Reset privileged access protection
+ * @retval HAL state
+ */
+HAL_StatusTypeDef HAL_OTFDEC_GetConfigAttributes(OTFDEC_HandleTypeDef *hotfdec, uint32_t *Attributes)
+{
+ /* Check the parameters */
+ assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
+
+ /* Take Lock */
+ __HAL_LOCK(hotfdec);
+
+ *Attributes = READ_BIT(hotfdec->Instance->PRIVCFGR, OTFDEC_PRIVCFGR_PRIV);
+
+ /* Release Lock */
+ __HAL_UNLOCK(hotfdec);
+
+ /* Status is okay */
+ return HAL_OK;
+}
+
+/**
+ * @brief Return region keys CRC.
+ * @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
+ * the configuration information for OTFDEC module
+ * @param RegionIndex index of region the keys CRC of which is read
+ * @retval Key CRC
+ */
+uint32_t HAL_OTFDEC_RegionGetKeyCRC(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex)
+{
+ OTFDEC_Region_TypeDef *region;
+ uint32_t address;
+ uint32_t keycrc;
+
+ /* Check the parameters */
+ assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
+ assert_param(IS_OTFDEC_REGIONINDEX(RegionIndex));
+
+ address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
+ region = (OTFDEC_Region_TypeDef *)address;
+
+ keycrc = (READ_REG(region->REG_CONFIGR)) & OTFDEC_REG_CONFIGR_KEYCRC;
+
+ keycrc >>= OTFDEC_REG_CONFIGR_KEYCRC_Pos;
+
+ return keycrc;
+}
+
+/**
+ * @brief Return region configuration parameters.
+ * @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
+ * the configuration information for OTFDEC module
+ * @param RegionIndex index of region the configuration of which is read
+ * @param Config pointer on structure that will be filled up with the region configuration parameters
+ * @retval HAL state
+ */
+HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex,
+ OTFDEC_RegionConfigTypeDef *Config)
+{
+ OTFDEC_Region_TypeDef *region;
+ uint32_t address;
+
+ /* Check the parameters */
+ assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
+ assert_param(IS_OTFDEC_REGIONINDEX(RegionIndex));
+
+ if (Config == NULL)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Take Lock */
+ __HAL_LOCK(hotfdec);
+
+ address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
+ region = (OTFDEC_Region_TypeDef *)address;
+
+ /* Read Nonce */
+ Config->Nonce[0] = READ_REG(region->REG_NONCER0);
+ Config->Nonce[1] = READ_REG(region->REG_NONCER1);
+
+ /* Read Addresses */
+ Config->StartAddress = READ_REG(region->REG_START_ADDR);
+ Config->EndAddress = READ_REG(region->REG_END_ADDR);
+
+ /* Read Version */
+ Config->Version = (uint16_t)(READ_REG(region->REG_CONFIGR) &
+ OTFDEC_REG_CONFIGR_VERSION) >> OTFDEC_REG_CONFIGR_VERSION_Pos;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hotfdec);
+
+ /* Status is okay */
+ return HAL_OK;
+ }
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* OTFDEC1 */
+
+#endif /* HAL_OTFDEC_MODULE_ENABLED */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd.c
new file mode 100644
index 00000000..0c24acce
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd.c
@@ -0,0 +1,2247 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_pcd.c
+ * @author MCD Application Team
+ * @brief PCD HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the USB Peripheral Controller:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The PCD HAL driver can be used as follows:
+
+ (#) Declare a PCD_HandleTypeDef handle structure, for example:
+ PCD_HandleTypeDef hpcd;
+
+ (#) Fill parameters of Init structure in HCD handle
+
+ (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...)
+
+ (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
+ (##) Enable the PCD/USB Low Level interface clock using
+ (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
+ (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)
+
+ (##) Initialize the related GPIO clocks
+ (##) Configure PCD pin-out
+ (##) Configure PCD NVIC interrupt
+
+ (#)Associate the Upper USB device stack to the HAL PCD Driver:
+ (##) hpcd.pData = pdev;
+
+ (#)Enable PCD transmission and reception:
+ (##) HAL_PCD_Start();
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup PCD PCD
+ * @brief PCD HAL module driver
+ * @{
+ */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PCD_Private_Macros PCD Private Macros
+ * @{
+ */
+#define PCD_MIN(a, b) (((a) < (b)) ? (a) : (b))
+#define PCD_MAX(a, b) (((a) > (b)) ? (a) : (b))
+/**
+ * @}
+ */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup PCD_Private_Functions PCD Private Functions
+ * @{
+ */
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum);
+static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum);
+static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum);
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup PCD_Exported_Functions PCD Exported Functions
+ * @{
+ */
+
+/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the PCD according to the specified
+ * parameters in the PCD_InitTypeDef and initialize the associated handle.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
+{
+#if defined (STM32U575xx) || defined (STM32U585xx)
+ USB_OTG_GlobalTypeDef *USBx;
+#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
+ uint8_t i;
+
+ /* Check the PCD handle allocation */
+ if (hpcd == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
+
+#if defined (STM32U575xx) || defined (STM32U585xx)
+ USBx = hpcd->Instance;
+#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
+
+ if (hpcd->State == HAL_PCD_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hpcd->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->SOFCallback = HAL_PCD_SOFCallback;
+ hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;
+ hpcd->ResetCallback = HAL_PCD_ResetCallback;
+ hpcd->SuspendCallback = HAL_PCD_SuspendCallback;
+ hpcd->ResumeCallback = HAL_PCD_ResumeCallback;
+ hpcd->ConnectCallback = HAL_PCD_ConnectCallback;
+ hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;
+ hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback;
+ hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback;
+ hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback;
+ hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback;
+ hpcd->LPMCallback = HAL_PCDEx_LPM_Callback;
+ hpcd->BCDCallback = HAL_PCDEx_BCD_Callback;
+
+ if (hpcd->MspInitCallback == NULL)
+ {
+ hpcd->MspInitCallback = HAL_PCD_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hpcd->MspInitCallback(hpcd);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+ HAL_PCD_MspInit(hpcd);
+#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
+ }
+
+ hpcd->State = HAL_PCD_STATE_BUSY;
+#if defined (STM32U575xx) || defined (STM32U585xx)
+ /* Disable DMA mode for FS instance */
+ if ((USBx->CID & (0x1U << 8)) == 0U)
+ {
+ hpcd->Init.dma_enable = 0U;
+ }
+#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
+ /* Disable the Interrupts */
+ __HAL_PCD_DISABLE(hpcd);
+
+ /*Init the Core (common init.) */
+ if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK)
+ {
+ hpcd->State = HAL_PCD_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ /* Force Device Mode*/
+ (void)USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE);
+
+ /* Init endpoints structures */
+ for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
+ {
+ /* Init ep structure */
+ hpcd->IN_ep[i].is_in = 1U;
+ hpcd->IN_ep[i].num = i;
+ hpcd->IN_ep[i].tx_fifo_num = i;
+ /* Control until ep is activated */
+ hpcd->IN_ep[i].type = EP_TYPE_CTRL;
+ hpcd->IN_ep[i].maxpacket = 0U;
+ hpcd->IN_ep[i].xfer_buff = 0U;
+ hpcd->IN_ep[i].xfer_len = 0U;
+ }
+
+ for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
+ {
+ hpcd->OUT_ep[i].is_in = 0U;
+ hpcd->OUT_ep[i].num = i;
+ /* Control until ep is activated */
+ hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
+ hpcd->OUT_ep[i].maxpacket = 0U;
+ hpcd->OUT_ep[i].xfer_buff = 0U;
+ hpcd->OUT_ep[i].xfer_len = 0U;
+ }
+
+ /* Init Device */
+ if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK)
+ {
+ hpcd->State = HAL_PCD_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ hpcd->USB_Address = 0U;
+ hpcd->State = HAL_PCD_STATE_READY;
+
+ /* Activate LPM */
+ if (hpcd->Init.lpm_enable == 1U)
+ {
+ (void)HAL_PCDEx_ActivateLPM(hpcd);
+ }
+
+ (void)USB_DevDisconnect(hpcd->Instance);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the PCD peripheral.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
+{
+ /* Check the PCD handle allocation */
+ if (hpcd == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ hpcd->State = HAL_PCD_STATE_BUSY;
+
+ /* Stop Device */
+ if (USB_StopDevice(hpcd->Instance) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ if (hpcd->MspDeInitCallback == NULL)
+ {
+ hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware */
+ hpcd->MspDeInitCallback(hpcd);
+#else
+ /* DeInit the low level hardware: CLOCK, NVIC.*/
+ HAL_PCD_MspDeInit(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+ hpcd->State = HAL_PCD_STATE_RESET;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the PCD MSP.
+ * @param hpcd PCD handle
+ * @retval None
+ */
+__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes PCD MSP.
+ * @param hpcd PCD handle
+ * @retval None
+ */
+__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_MspDeInit could be implemented in the user file
+ */
+}
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+/**
+ * @brief Register a User USB PCD Callback
+ * To be used instead of the weak predefined callback
+ * @param hpcd USB PCD handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
+ * @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
+ * @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
+ * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
+ * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
+ * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
+ * @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
+ * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
+ * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
+ HAL_PCD_CallbackIDTypeDef CallbackID,
+ pPCD_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_PCD_SOF_CB_ID :
+ hpcd->SOFCallback = pCallback;
+ break;
+
+ case HAL_PCD_SETUPSTAGE_CB_ID :
+ hpcd->SetupStageCallback = pCallback;
+ break;
+
+ case HAL_PCD_RESET_CB_ID :
+ hpcd->ResetCallback = pCallback;
+ break;
+
+ case HAL_PCD_SUSPEND_CB_ID :
+ hpcd->SuspendCallback = pCallback;
+ break;
+
+ case HAL_PCD_RESUME_CB_ID :
+ hpcd->ResumeCallback = pCallback;
+ break;
+
+ case HAL_PCD_CONNECT_CB_ID :
+ hpcd->ConnectCallback = pCallback;
+ break;
+
+ case HAL_PCD_DISCONNECT_CB_ID :
+ hpcd->DisconnectCallback = pCallback;
+ break;
+
+ case HAL_PCD_MSPINIT_CB_ID :
+ hpcd->MspInitCallback = pCallback;
+ break;
+
+ case HAL_PCD_MSPDEINIT_CB_ID :
+ hpcd->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hpcd->State == HAL_PCD_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_PCD_MSPINIT_CB_ID :
+ hpcd->MspInitCallback = pCallback;
+ break;
+
+ case HAL_PCD_MSPDEINIT_CB_ID :
+ hpcd->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+ return status;
+}
+
+/**
+ * @brief Unregister an USB PCD Callback
+ * USB PCD callabck is redirected to the weak predefined callback
+ * @param hpcd USB PCD handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
+ * @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
+ * @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
+ * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
+ * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
+ * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
+ * @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
+ * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
+ * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ /* Setup Legacy weak Callbacks */
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_PCD_SOF_CB_ID :
+ hpcd->SOFCallback = HAL_PCD_SOFCallback;
+ break;
+
+ case HAL_PCD_SETUPSTAGE_CB_ID :
+ hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;
+ break;
+
+ case HAL_PCD_RESET_CB_ID :
+ hpcd->ResetCallback = HAL_PCD_ResetCallback;
+ break;
+
+ case HAL_PCD_SUSPEND_CB_ID :
+ hpcd->SuspendCallback = HAL_PCD_SuspendCallback;
+ break;
+
+ case HAL_PCD_RESUME_CB_ID :
+ hpcd->ResumeCallback = HAL_PCD_ResumeCallback;
+ break;
+
+ case HAL_PCD_CONNECT_CB_ID :
+ hpcd->ConnectCallback = HAL_PCD_ConnectCallback;
+ break;
+
+ case HAL_PCD_DISCONNECT_CB_ID :
+ hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;
+ break;
+
+ case HAL_PCD_MSPINIT_CB_ID :
+ hpcd->MspInitCallback = HAL_PCD_MspInit;
+ break;
+
+ case HAL_PCD_MSPDEINIT_CB_ID :
+ hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hpcd->State == HAL_PCD_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_PCD_MSPINIT_CB_ID :
+ hpcd->MspInitCallback = HAL_PCD_MspInit;
+ break;
+
+ case HAL_PCD_MSPDEINIT_CB_ID :
+ hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+ return status;
+}
+
+/**
+ * @brief Register USB PCD Data OUT Stage Callback
+ * To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback
+ * @param hpcd PCD handle
+ * @param pCallback pointer to the USB PCD Data OUT Stage Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_DataOutStageCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->DataOutStageCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief Unregister the USB PCD Data OUT Stage Callback
+ * USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; /* Legacy weak DataOutStageCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief Register USB PCD Data IN Stage Callback
+ * To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback
+ * @param hpcd PCD handle
+ * @param pCallback pointer to the USB PCD Data IN Stage Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_DataInStageCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->DataInStageCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief Unregister the USB PCD Data IN Stage Callback
+ * USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; /* Legacy weak DataInStageCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief Register USB PCD Iso OUT incomplete Callback
+ * To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
+ * @param hpcd PCD handle
+ * @param pCallback pointer to the USB PCD Iso OUT incomplete Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_IsoOutIncpltCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->ISOOUTIncompleteCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief Unregister the USB PCD Iso OUT incomplete Callback
+ * USB PCD Iso OUT incomplete Callback is redirected
+ * to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; /* Legacy weak ISOOUTIncompleteCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief Register USB PCD Iso IN incomplete Callback
+ * To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
+ * @param hpcd PCD handle
+ * @param pCallback pointer to the USB PCD Iso IN incomplete Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_IsoInIncpltCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->ISOINIncompleteCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief Unregister the USB PCD Iso IN incomplete Callback
+ * USB PCD Iso IN incomplete Callback is redirected
+ * to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; /* Legacy weak ISOINIncompleteCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief Register USB PCD BCD Callback
+ * To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined callback
+ * @param hpcd PCD handle
+ * @param pCallback pointer to the USB PCD BCD Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->BCDCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief Unregister the USB PCD BCD Callback
+ * USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->BCDCallback = HAL_PCDEx_BCD_Callback; /* Legacy weak HAL_PCDEx_BCD_Callback */
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief Register USB PCD LPM Callback
+ * To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback
+ * @param hpcd PCD handle
+ * @param pCallback pointer to the USB PCD LPM Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->LPMCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief Unregister the USB PCD LPM Callback
+ * USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->LPMCallback = HAL_PCDEx_LPM_Callback; /* Legacy weak HAL_PCDEx_LPM_Callback */
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the PCD data
+ transfers.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start the USB device
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
+{
+#if defined (STM32U575xx) || defined (STM32U585xx)
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
+
+ __HAL_LOCK(hpcd);
+#if defined (STM32U575xx) || defined (STM32U585xx)
+ if (hpcd->Init.battery_charging_enable == 1U)
+ {
+ /* Enable USB Transceiver */
+ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
+ }
+#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
+ __HAL_PCD_ENABLE(hpcd);
+ (void)USB_DevConnect(hpcd->Instance);
+ __HAL_UNLOCK(hpcd);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the USB device.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
+{
+#if defined (STM32U575xx) || defined (STM32U585xx)
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
+
+ __HAL_LOCK(hpcd);
+ __HAL_PCD_DISABLE(hpcd);
+ (void)USB_DevDisconnect(hpcd->Instance);
+
+ (void)USB_FlushTxFifo(hpcd->Instance, 0x10U);
+
+#if defined (STM32U575xx) || defined (STM32U585xx)
+ if (hpcd->Init.battery_charging_enable == 1U)
+ {
+ /* Disable USB Transceiver */
+ USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
+ }
+#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
+
+ __HAL_UNLOCK(hpcd);
+
+ return HAL_OK;
+}
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+/**
+ * @brief Handles PCD interrupt request.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
+{
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ USB_OTG_EPTypeDef *ep;
+ uint32_t i;
+ uint32_t ep_intr;
+ uint32_t epint;
+ uint32_t epnum;
+ uint32_t fifoemptymsk;
+ uint32_t temp;
+
+ /* ensure that we are in device mode */
+ if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
+ {
+ /* avoid spurious interrupt */
+ if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd))
+ {
+ return;
+ }
+
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))
+ {
+ /* incorrect mode, acknowledge the interrupt */
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
+ }
+
+ /* Handle RxQLevel Interrupt */
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
+ {
+ USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+
+ temp = USBx->GRXSTSP;
+
+ ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];
+
+ if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT)
+ {
+ if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U)
+ {
+ (void)USB_ReadPacket(USBx, ep->xfer_buff,
+ (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4));
+
+ ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
+ ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
+ }
+ }
+ else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT)
+ {
+ (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);
+ ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
+ }
+ else
+ {
+ /* ... */
+ }
+ USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+ }
+
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
+ {
+ epnum = 0U;
+
+ /* Read in the device interrupt bits */
+ ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);
+
+ while (ep_intr != 0U)
+ {
+ if ((ep_intr & 0x1U) != 0U)
+ {
+ epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum);
+
+ if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)
+ {
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);
+ (void)PCD_EP_OutXfrComplete_int(hpcd, epnum);
+ }
+
+ if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
+ {
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
+ /* Class B setup phase done for previous decoded setup */
+ (void)PCD_EP_OutSetupPacket_int(hpcd, epnum);
+ }
+
+ if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
+ {
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);
+ }
+
+ /* Clear Status Phase Received interrupt */
+ if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
+ {
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
+ }
+
+ /* Clear OUT NAK interrupt */
+ if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK)
+ {
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK);
+ }
+ }
+ epnum++;
+ ep_intr >>= 1U;
+ }
+ }
+
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))
+ {
+ /* Read in the device interrupt bits */
+ ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);
+
+ epnum = 0U;
+
+ while (ep_intr != 0U)
+ {
+ if ((ep_intr & 0x1U) != 0U) /* In ITR */
+ {
+ epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum);
+
+ if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
+ {
+ fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));
+ USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
+
+ CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);
+
+ if (hpcd->Init.dma_enable == 1U)
+ {
+ hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket;
+
+ /* this is ZLP, so prepare EP0 for next setup */
+ if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U))
+ {
+ /* prepare to rx more setup packets */
+ (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
+ }
+ }
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->DataInStageCallback(hpcd, (uint8_t)epnum);
+#else
+ HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
+ if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)
+ {
+ CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC);
+ }
+ if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE)
+ {
+ CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE);
+ }
+ if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE)
+ {
+ CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE);
+ }
+ if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)
+ {
+ CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);
+ }
+ if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)
+ {
+ (void)PCD_WriteEmptyTxFifo(hpcd, epnum);
+ }
+ }
+ epnum++;
+ ep_intr >>= 1U;
+ }
+ }
+
+ /* Handle Resume Interrupt */
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
+ {
+ /* Clear the Remote Wake-up Signaling */
+ USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
+
+ if (hpcd->LPM_State == LPM_L1)
+ {
+ hpcd->LPM_State = LPM_L0;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE);
+#else
+ HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
+ else
+ {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->ResumeCallback(hpcd);
+#else
+ HAL_PCD_ResumeCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
+
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
+ }
+
+ /* Handle Suspend Interrupt */
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
+ {
+ if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
+ {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->SuspendCallback(hpcd);
+#else
+ HAL_PCD_SuspendCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
+ }
+
+ /* Handle LPM Interrupt */
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))
+ {
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT);
+
+ if (hpcd->LPM_State == LPM_L0)
+ {
+ hpcd->LPM_State = LPM_L1;
+ hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE);
+#else
+ HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
+ else
+ {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->SuspendCallback(hpcd);
+#else
+ HAL_PCD_SuspendCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* Handle Reset Interrupt */
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
+ {
+ USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
+ (void)USB_FlushTxFifo(hpcd->Instance, 0x10U);
+
+ for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
+ {
+ USBx_INEP(i)->DIEPINT = 0xFB7FU;
+ USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
+ USBx_INEP(i)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
+ USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
+ USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
+ USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
+ }
+ USBx_DEVICE->DAINTMSK |= 0x10001U;
+
+ if (hpcd->Init.use_dedicated_ep1 != 0U)
+ {
+ USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM |
+ USB_OTG_DOEPMSK_XFRCM |
+ USB_OTG_DOEPMSK_EPDM;
+
+ USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM |
+ USB_OTG_DIEPMSK_XFRCM |
+ USB_OTG_DIEPMSK_EPDM;
+ }
+ else
+ {
+ USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM |
+ USB_OTG_DOEPMSK_XFRCM |
+ USB_OTG_DOEPMSK_EPDM |
+ USB_OTG_DOEPMSK_OTEPSPRM |
+ USB_OTG_DOEPMSK_NAKM;
+
+ USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM |
+ USB_OTG_DIEPMSK_XFRCM |
+ USB_OTG_DIEPMSK_EPDM;
+ }
+
+ /* Set Default Address to 0 */
+ USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;
+
+ /* setup EP0 to receive SETUP packets */
+ (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable,
+ (uint8_t *)hpcd->Setup);
+
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);
+ }
+
+ /* Handle Enumeration done Interrupt */
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
+ {
+ (void)USB_ActivateSetup(hpcd->Instance);
+ hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance);
+
+ /* Set USB Turnaround time */
+ (void)USB_SetTurnaroundTime(hpcd->Instance,
+ HAL_RCC_GetHCLKFreq(),
+ (uint8_t)hpcd->Init.speed);
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->ResetCallback(hpcd);
+#else
+ HAL_PCD_ResetCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
+ }
+
+ /* Handle SOF Interrupt */
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
+ {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->SOFCallback(hpcd);
+#else
+ HAL_PCD_SOFCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);
+ }
+
+ /* Handle Incomplete ISO IN Interrupt */
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
+ {
+ /* Keep application checking the corresponding Iso IN endpoint
+ causing the incomplete Interrupt */
+ epnum = 0U;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
+#else
+ HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);
+ }
+
+ /* Handle Incomplete ISO OUT Interrupt */
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
+ {
+ /* Keep application checking the corresponding Iso OUT endpoint
+ causing the incomplete Interrupt */
+ epnum = 0U;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
+#else
+ HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
+ }
+
+ /* Handle Connection event Interrupt */
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))
+ {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->ConnectCallback(hpcd);
+#else
+ HAL_PCD_ConnectCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);
+ }
+
+ /* Handle Disconnection event Interrupt */
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))
+ {
+ temp = hpcd->Instance->GOTGINT;
+
+ if ((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)
+ {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->DisconnectCallback(hpcd);
+#else
+ HAL_PCD_DisconnectCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
+ hpcd->Instance->GOTGINT |= temp;
+ }
+ }
+}
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+
+/**
+ * @brief Data OUT stage callback.
+ * @param hpcd PCD handle
+ * @param epnum endpoint number
+ * @retval None
+ */
+__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ UNUSED(epnum);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_DataOutStageCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Data IN stage callback
+ * @param hpcd PCD handle
+ * @param epnum endpoint number
+ * @retval None
+ */
+__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ UNUSED(epnum);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_DataInStageCallback could be implemented in the user file
+ */
+}
+/**
+ * @brief Setup stage callback
+ * @param hpcd PCD handle
+ * @retval None
+ */
+__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_SetupStageCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief USB Start Of Frame callback.
+ * @param hpcd PCD handle
+ * @retval None
+ */
+__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_SOFCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief USB Reset callback.
+ * @param hpcd PCD handle
+ * @retval None
+ */
+__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_ResetCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Suspend event callback.
+ * @param hpcd PCD handle
+ * @retval None
+ */
+__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_SuspendCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Resume event callback.
+ * @param hpcd PCD handle
+ * @retval None
+ */
+__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_ResumeCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Incomplete ISO OUT callback.
+ * @param hpcd PCD handle
+ * @param epnum endpoint number
+ * @retval None
+ */
+__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ UNUSED(epnum);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Incomplete ISO IN callback.
+ * @param hpcd PCD handle
+ * @param epnum endpoint number
+ * @retval None
+ */
+__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ UNUSED(epnum);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Connection event callback.
+ * @param hpcd PCD handle
+ * @retval None
+ */
+__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_ConnectCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Disconnection event callback.
+ * @param hpcd PCD handle
+ * @retval None
+ */
+__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_DisconnectCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
+ * @brief management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the PCD data
+ transfers.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Connect the USB device
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
+{
+#if defined (STM32U575xx) || defined (STM32U585xx)
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
+
+ __HAL_LOCK(hpcd);
+
+#if defined (STM32U575xx) || defined (STM32U585xx)
+ if (hpcd->Init.battery_charging_enable == 1U)
+ {
+ /* Enable USB Transceiver */
+ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
+ }
+#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
+
+ (void)USB_DevConnect(hpcd->Instance);
+ __HAL_UNLOCK(hpcd);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disconnect the USB device.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
+{
+#if defined (STM32U575xx) || defined (STM32U585xx)
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
+
+ __HAL_LOCK(hpcd);
+ (void)USB_DevDisconnect(hpcd->Instance);
+
+#if defined (STM32U575xx) || defined (STM32U585xx)
+ if (hpcd->Init.battery_charging_enable == 1U)
+ {
+ /* Disable USB Transceiver */
+ USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
+ }
+#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
+
+ __HAL_UNLOCK(hpcd);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the USB Device address.
+ * @param hpcd PCD handle
+ * @param address new device address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
+{
+ __HAL_LOCK(hpcd);
+ hpcd->USB_Address = address;
+ (void)USB_SetDevAddress(hpcd->Instance, address);
+ __HAL_UNLOCK(hpcd);
+
+ return HAL_OK;
+}
+/**
+ * @brief Open and configure an endpoint.
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @param ep_mps endpoint max packet size
+ * @param ep_type endpoint type
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
+ uint16_t ep_mps, uint8_t ep_type)
+{
+ HAL_StatusTypeDef ret = HAL_OK;
+ PCD_EPTypeDef *ep;
+
+ if ((ep_addr & 0x80U) == 0x80U)
+ {
+ ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+ ep->is_in = 1U;
+ }
+ else
+ {
+ ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+ ep->is_in = 0U;
+ }
+
+ ep->num = ep_addr & EP_ADDR_MSK;
+ ep->maxpacket = ep_mps;
+ ep->type = ep_type;
+
+ if (ep->is_in != 0U)
+ {
+ /* Assign a Tx FIFO */
+ ep->tx_fifo_num = ep->num;
+ }
+ /* Set initial data PID. */
+ if (ep_type == EP_TYPE_BULK)
+ {
+ ep->data_pid_start = 0U;
+ }
+
+ __HAL_LOCK(hpcd);
+ (void)USB_ActivateEndpoint(hpcd->Instance, ep);
+ __HAL_UNLOCK(hpcd);
+
+ return ret;
+}
+
+/**
+ * @brief Deactivate an endpoint.
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+ PCD_EPTypeDef *ep;
+
+ if ((ep_addr & 0x80U) == 0x80U)
+ {
+ ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+ ep->is_in = 1U;
+ }
+ else
+ {
+ ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+ ep->is_in = 0U;
+ }
+ ep->num = ep_addr & EP_ADDR_MSK;
+
+ __HAL_LOCK(hpcd);
+ (void)USB_DeactivateEndpoint(hpcd->Instance, ep);
+ __HAL_UNLOCK(hpcd);
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Receive an amount of data.
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @param pBuf pointer to the reception buffer
+ * @param len amount of data to be received
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
+{
+ PCD_EPTypeDef *ep;
+
+ ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+
+ /*setup and start the Xfer */
+ ep->xfer_buff = pBuf;
+ ep->xfer_len = len;
+ ep->xfer_count = 0U;
+ ep->is_in = 0U;
+ ep->num = ep_addr & EP_ADDR_MSK;
+
+ if (hpcd->Init.dma_enable == 1U)
+ {
+ ep->dma_addr = (uint32_t)pBuf;
+ }
+
+ if ((ep_addr & EP_ADDR_MSK) == 0U)
+ {
+ (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
+ }
+ else
+ {
+ (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get Received Data Size
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @retval Data Size
+ */
+uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+ return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count;
+}
+/**
+ * @brief Send an amount of data
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @param pBuf pointer to the transmission buffer
+ * @param len amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
+{
+ PCD_EPTypeDef *ep;
+
+ ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+
+ /*setup and start the Xfer */
+ ep->xfer_buff = pBuf;
+ ep->xfer_len = len;
+ ep->xfer_count = 0U;
+ ep->is_in = 1U;
+ ep->num = ep_addr & EP_ADDR_MSK;
+
+ if (hpcd->Init.dma_enable == 1U)
+ {
+ ep->dma_addr = (uint32_t)pBuf;
+ }
+
+ if ((ep_addr & EP_ADDR_MSK) == 0U)
+ {
+ (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
+ }
+ else
+ {
+ (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set a STALL condition over an endpoint
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+ PCD_EPTypeDef *ep;
+
+ if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints)
+ {
+ return HAL_ERROR;
+ }
+
+ if ((0x80U & ep_addr) == 0x80U)
+ {
+ ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+ ep->is_in = 1U;
+ }
+ else
+ {
+ ep = &hpcd->OUT_ep[ep_addr];
+ ep->is_in = 0U;
+ }
+
+ ep->is_stall = 1U;
+ ep->num = ep_addr & EP_ADDR_MSK;
+
+ __HAL_LOCK(hpcd);
+
+ (void)USB_EPSetStall(hpcd->Instance, ep);
+
+ if ((ep_addr & EP_ADDR_MSK) == 0U)
+ {
+ (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
+ }
+
+ __HAL_UNLOCK(hpcd);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Clear a STALL condition over in an endpoint
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+ PCD_EPTypeDef *ep;
+
+ if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints)
+ {
+ return HAL_ERROR;
+ }
+
+ if ((0x80U & ep_addr) == 0x80U)
+ {
+ ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+ ep->is_in = 1U;
+ }
+ else
+ {
+ ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+ ep->is_in = 0U;
+ }
+
+ ep->is_stall = 0U;
+ ep->num = ep_addr & EP_ADDR_MSK;
+
+ __HAL_LOCK(hpcd);
+ (void)USB_EPClearStall(hpcd->Instance, ep);
+ __HAL_UNLOCK(hpcd);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Flush an endpoint
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+ __HAL_LOCK(hpcd);
+
+ if ((ep_addr & 0x80U) == 0x80U)
+ {
+ (void)USB_FlushTxFifo(hpcd->Instance, (uint32_t)ep_addr & EP_ADDR_MSK);
+ }
+ else
+ {
+ (void)USB_FlushRxFifo(hpcd->Instance);
+ }
+
+ __HAL_UNLOCK(hpcd);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Activate remote wakeup signalling
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
+{
+ return (USB_ActivateRemoteWakeup(hpcd->Instance));
+}
+
+/**
+ * @brief De-activate remote wakeup signalling.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
+{
+ return (USB_DeActivateRemoteWakeup(hpcd->Instance));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the PCD handle state.
+ * @param hpcd PCD handle
+ * @retval HAL state
+ */
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
+{
+ return hpcd->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup PCD_Private_Functions
+ * @{
+ */
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+/**
+ * @brief Check FIFO for the next packet to be loaded.
+ * @param hpcd PCD handle
+ * @param epnum endpoint number
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)
+{
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ USB_OTG_EPTypeDef *ep;
+ uint32_t len;
+ uint32_t len32b;
+ uint32_t fifoemptymsk;
+
+ ep = &hpcd->IN_ep[epnum];
+
+ if (ep->xfer_count > ep->xfer_len)
+ {
+ return HAL_ERROR;
+ }
+
+ len = ep->xfer_len - ep->xfer_count;
+
+ if (len > ep->maxpacket)
+ {
+ len = ep->maxpacket;
+ }
+
+ len32b = (len + 3U) / 4U;
+
+ while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) &&
+ (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U))
+ {
+ /* Write the FIFO */
+ len = ep->xfer_len - ep->xfer_count;
+
+ if (len > ep->maxpacket)
+ {
+ len = ep->maxpacket;
+ }
+ len32b = (len + 3U) / 4U;
+
+ (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len,
+ (uint8_t)hpcd->Init.dma_enable);
+
+ ep->xfer_buff += len;
+ ep->xfer_count += len;
+ }
+
+ if (ep->xfer_len <= ep->xfer_count)
+ {
+ fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));
+ USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
+ }
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief process EP OUT transfer complete interrupt.
+ * @param hpcd PCD handle
+ * @param epnum endpoint number
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
+{
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
+ uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
+
+ if (hpcd->Init.dma_enable == 1U)
+ {
+ if ((DoepintReg & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) /* Class C */
+ {
+ /* StupPktRcvd = 1 this is a setup packet */
+ if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
+ ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
+ {
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
+ }
+ }
+ else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */
+ {
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
+ }
+ else if ((DoepintReg & (USB_OTG_DOEPINT_STUP | USB_OTG_DOEPINT_OTEPSPR)) == 0U)
+ {
+ /* StupPktRcvd = 1 this is a setup packet */
+ if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
+ ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
+ {
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
+ }
+ else
+ {
+ /* out data packet received over EP0 */
+ hpcd->OUT_ep[epnum].xfer_count =
+ hpcd->OUT_ep[epnum].maxpacket -
+ (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ);
+
+ hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket;
+
+ if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U))
+ {
+ /* this is ZLP, so prepare EP0 for next setup */
+ (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
+ }
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
+#else
+ HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
+ }
+ else
+ {
+ /* ... */
+ }
+ }
+ else
+ {
+ if (gSNPSiD == USB_OTG_CORE_ID_310A)
+ {
+ /* StupPktRcvd = 1 this is a setup packet */
+ if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)
+ {
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
+ }
+ else
+ {
+ if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
+ {
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
+ }
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
+#else
+ HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
+ }
+ else
+ {
+ if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U))
+ {
+ /* this is ZLP, so prepare EP0 for next setup */
+ (void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup);
+ }
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
+#else
+ HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
+ }
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief process EP OUT setup packet received interrupt.
+ * @param hpcd PCD handle
+ * @param epnum endpoint number
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
+{
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
+ uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
+
+ if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
+ ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
+ {
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
+ }
+
+ /* Inform the upper layer that a setup packet is available */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->SetupStageCallback(hpcd);
+#else
+ HAL_PCD_SetupStageCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+ if ((gSNPSiD > USB_OTG_CORE_ID_300A) && (hpcd->Init.dma_enable == 1U))
+ {
+ (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
+ }
+
+ return HAL_OK;
+}
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+
+/**
+ * @}
+ */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd_ex.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd_ex.c
new file mode 100644
index 00000000..445074d2
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd_ex.c
@@ -0,0 +1,363 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_pcd_ex.c
+ * @author MCD Application Team
+ * @brief PCD Extended HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the USB Peripheral Controller:
+ * + Extended features functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup PCDEx PCDEx
+ * @brief PCD Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
+ * @{
+ */
+
+/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
+ * @brief PCDEx control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended features functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Update FIFO configuration
+
+@endverbatim
+ * @{
+ */
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+/**
+ * @brief Set Tx FIFO
+ * @param hpcd PCD handle
+ * @param fifo The number of Tx fifo
+ * @param size Fifo size
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
+{
+ uint8_t i;
+ uint32_t Tx_Offset;
+
+ /* TXn min size = 16 words. (n : Transmit FIFO index)
+ When a TxFIFO is not used, the Configuration should be as follows:
+ case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes)
+ --> Txm can use the space allocated for Txn.
+ case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes)
+ --> Txn should be configured with the minimum space of 16 words
+ The FIFO is used optimally when used TxFIFOs are allocated in the top
+ of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
+ When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
+
+ Tx_Offset = hpcd->Instance->GRXFSIZ;
+
+ if (fifo == 0U)
+ {
+ hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset;
+ }
+ else
+ {
+ Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;
+ for (i = 0U; i < (fifo - 1U); i++)
+ {
+ Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);
+ }
+
+ /* Multiply Tx_Size by 2 to get higher performance */
+ hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set Rx FIFO
+ * @param hpcd PCD handle
+ * @param size Size of Rx fifo
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
+{
+ hpcd->Instance->GRXFSIZ = size;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Activate LPM feature.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
+{
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+
+ hpcd->lpm_active = 1U;
+ hpcd->LPM_State = LPM_L0;
+ USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
+ USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivate LPM feature.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
+{
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+
+ hpcd->lpm_active = 0U;
+ USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM;
+ USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
+
+ return HAL_OK;
+}
+
+#if defined (STM32U575xx) || defined (STM32U585xx) || defined (STM32U595xx) || defined (STM32U5A5xx) || defined (STM32U599xx) || defined (STM32U5A9xx)
+/**
+ * @brief Handle BatteryCharging Process.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
+{
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+#if defined (STM32U575xx) || defined (STM32U585xx)
+ uint32_t tickstart = HAL_GetTick();
+#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
+
+ /* Enable DCD : Data Contact Detect */
+ USBx->GCCFG |= USB_OTG_GCCFG_DCDEN;
+
+#if defined (STM32U575xx) || defined (STM32U585xx)
+ /* Wait Detect flag or a timeout is happen*/
+ while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0U)
+ {
+ /* Check for the Timeout */
+ if ((HAL_GetTick() - tickstart) > 1000U)
+ {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->BCDCallback(hpcd, PCD_BCD_ERROR);
+#else
+ HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+ return;
+ }
+ }
+#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
+
+ /* Right response got */
+ HAL_Delay(200U);
+
+#if defined (STM32U575xx) || defined (STM32U585xx)
+ /* Check Detect flag*/
+ if ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == USB_OTG_GCCFG_DCDET)
+ {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION);
+#else
+ HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
+#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
+
+ /*Primary detection: checks if connected to Standard Downstream Port
+ (without charging capability) */
+ USBx->GCCFG &= ~ USB_OTG_GCCFG_DCDEN;
+ HAL_Delay(50U);
+ USBx->GCCFG |= USB_OTG_GCCFG_PDEN;
+ HAL_Delay(50U);
+
+#if defined (STM32U575xx) || defined (STM32U585xx)
+ if ((USBx->GCCFG & USB_OTG_GCCFG_PDET) == 0U)
+#else
+ if ((USBx->GCCFG & USB_OTG_GCCFG_CHGDET) == 0U)
+#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
+ {
+ /* Case of Standard Downstream Port */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
+#else
+ HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* start secondary detection to check connection to Charging Downstream
+ Port or Dedicated Charging Port */
+ USBx->GCCFG &= ~ USB_OTG_GCCFG_PDEN;
+ HAL_Delay(50U);
+ USBx->GCCFG |= USB_OTG_GCCFG_SDEN;
+ HAL_Delay(50U);
+
+#if defined (STM32U575xx) || defined (STM32U585xx)
+ if ((USBx->GCCFG & USB_OTG_GCCFG_SDET) == USB_OTG_GCCFG_SDET)
+#else
+ if ((USBx->GCCFG & USB_OTG_GCCFG_FSVPLUS) == USB_OTG_GCCFG_FSVPLUS)
+#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
+ {
+ /* case Dedicated Charging Port */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
+#else
+ HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* case Charging Downstream Port */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
+#else
+ HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* Battery Charging capability discovery finished */
+ (void)HAL_PCDEx_DeActivateBCD(hpcd);
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
+#else
+ HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief Activate BatteryCharging feature.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
+{
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+
+ USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN);
+ USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN);
+
+#if defined (STM32U575xx) || defined (STM32U585xx)
+ /* Power Down USB transceiver */
+ USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
+
+ /* Enable Battery charging */
+ USBx->GCCFG |= USB_OTG_GCCFG_BCDEN;
+#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
+
+ hpcd->battery_charging_active = 1U;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivate BatteryCharging feature.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
+{
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+
+ USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN);
+ USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN);
+
+#if defined (STM32U575xx) || defined (STM32U585xx)
+ /* Disable Battery charging */
+ USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);
+#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
+
+ hpcd->battery_charging_active = 0U;
+
+ return HAL_OK;
+}
+#endif /* defined (STM32U575xx) || defined (STM32U585xx) || defined (STM32U595xx) || defined (STM32U5A5xx) || defined (STM32U599xx) || defined (STM32U5A9xx) */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+/**
+ * @brief Send LPM message to user layer callback.
+ * @param hpcd PCD handle
+ * @param msg LPM message
+ * @retval HAL status
+ */
+__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ UNUSED(msg);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCDEx_LPM_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Send BatteryCharging message to user layer callback.
+ * @param hpcd PCD handle
+ * @param msg LPM message
+ * @retval HAL status
+ */
+__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ UNUSED(msg);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCDEx_BCD_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pka.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pka.c
new file mode 100644
index 00000000..48bdaf6a
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pka.c
@@ -0,0 +1,2938 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_pka.c
+ * @author MCD Application Team
+ * @brief PKA HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of public key accelerator(PKA):
+ * + Initialization and de-initialization functions
+ * + Start an operation
+ * + Retrieve the operation result
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The PKA HAL driver can be used as follows:
+
+ (#) Declare a PKA_HandleTypeDef handle structure, for example: PKA_HandleTypeDef hpka;
+
+ (#) Initialize the PKA low level resources by implementing the HAL_PKA_MspInit() API:
+ (##) Enable the PKA interface clock
+ (##) NVIC configuration if you need to use interrupt process
+ (+++) Configure the PKA interrupt priority
+ (+++) Enable the NVIC PKA IRQ Channel
+
+ (#) Initialize the PKA registers by calling the HAL_PKA_Init() API which trig
+ HAL_PKA_MspInit().
+
+ (#) Fill entirely the input structure corresponding to your operation:
+ For instance: PKA_ModExpInTypeDef for HAL_PKA_ModExp().
+
+ (#) Execute the operation (in polling or interrupt) and check the returned value.
+
+ (#) Retrieve the result of the operation (For instance, HAL_PKA_ModExp_GetResult for
+ HAL_PKA_ModExp operation). The function to gather the result is different for each
+ kind of operation. The correspondence can be found in the following section.
+
+ (#) Call the function HAL_PKA_DeInit() to restore the default configuration which trig
+ HAL_PKA_MspDeInit().
+
+ *** High level operation ***
+ =================================
+ [..]
+ (+) Input structure requires buffers as uint8_t array.
+
+ (+) Output structure requires buffers as uint8_t array.
+
+ (+) Modular exponentiation using:
+ (++) HAL_PKA_ModExp().
+ (++) HAL_PKA_ModExp_IT().
+ (++) HAL_PKA_ModExpFastMode().
+ (++) HAL_PKA_ModExpFastMode_IT().
+ (++) HAL_PKA_ModExpProtectMode().
+ (++) HAL_PKA_ModExpProtectMode_IT().
+ (++) HAL_PKA_ModExp_GetResult() to retrieve the result of the operation.
+
+ (+) RSA Chinese Remainder Theorem (CRT) using:
+ (++) HAL_PKA_RSACRTExp().
+ (++) HAL_PKA_RSACRTExp_IT().
+ (++) HAL_PKA_RSACRTExp_GetResult() to retrieve the result of the operation.
+
+ (+) ECC Point Check using:
+ (++) HAL_PKA_PointCheck().
+ (++) HAL_PKA_PointCheck_IT().
+ (++) HAL_PKA_PointCheck_IsOnCurve() to retrieve the result of the operation.
+
+ (+) ECDSA Sign
+ (++) HAL_PKA_ECDSASign().
+ (++) HAL_PKA_ECDSASign_IT().
+ (++) HAL_PKA_ECDSASign_GetResult() to retrieve the result of the operation.
+
+ (+) ECDSA Verify
+ (++) HAL_PKA_ECDSAVerif().
+ (++) HAL_PKA_ECDSAVerif_IT().
+ (++) HAL_PKA_ECDSAVerif_IsValidSignature() to retrieve the result of the operation.
+
+ (+) ECC Scalar Multiplication using:
+ (++) HAL_PKA_ECCMul().
+ (++) HAL_PKA_ECCMul_IT().
+ (++) HAL_PKA_ECCMul_GetResult() to retrieve the result of the operation.
+
+ (+) ECC double base ladder using:
+ (++) HAL_PKA_ECCDoubleBaseLadder().
+ (++) HAL_PKA_ECCDoubleBaseLadder_IT().
+ (++) HAL_PKA_ECCDoubleBaseLadder_GetResult() to retrieve the result of the operation.
+
+ (+) ECC projective to affine using:
+ (++) HAL_PKA_ECCProjective2Affine().
+ (++) HAL_PKA_ECCProjective2Affine_IT().
+ (++) HAL_PKA_ECCProjective2Affine_GetResult() to retrieve the result of the operation.
+
+ (+) ECC complete addition using:
+ (++) HAL_PKA_ECCCompleteAddition().
+ (++) HAL_PKA_ECCCompleteAddition_IT().
+ (++) HAL_PKA_ECCCompleteAddition_GetResult() to retrieve the result of the operation.
+
+ *** Low level operation ***
+ =================================
+ [..]
+ (+) Input structure requires buffers as uint32_t array.
+
+ (+) Output structure requires buffers as uint32_t array.
+
+ (+) Arithmetic addition using:
+ (++) HAL_PKA_Add().
+ (++) HAL_PKA_Add_IT().
+ (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
+ The resulting size can be the input parameter or the input parameter size + 1 (overflow).
+
+ (+) Arithmetic subtraction using:
+ (++) HAL_PKA_Sub().
+ (++) HAL_PKA_Sub_IT().
+ (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
+
+ (+) Arithmetic multiplication using:
+ (++) HAL_PKA_Mul().
+ (++) HAL_PKA_Mul_IT().
+ (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
+
+ (+) Comparison using:
+ (++) HAL_PKA_Cmp().
+ (++) HAL_PKA_Cmp_IT().
+ (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
+
+ (+) Modular addition using:
+ (++) HAL_PKA_ModAdd().
+ (++) HAL_PKA_ModAdd_IT().
+ (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
+
+ (+) Modular subtraction using:
+ (++) HAL_PKA_ModSub().
+ (++) HAL_PKA_ModSub_IT().
+ (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
+
+ (+) Modular inversion using:
+ (++) HAL_PKA_ModInv().
+ (++) HAL_PKA_ModInv_IT().
+ (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
+
+ (+) Modular reduction using:
+ (++) HAL_PKA_ModRed().
+ (++) HAL_PKA_ModRed_IT().
+ (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
+
+ (+) Montgomery multiplication using:
+ (++) HAL_PKA_MontgomeryMul().
+ (++) HAL_PKA_MontgomeryMul_IT().
+ (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
+
+ *** Montgomery parameter ***
+ =================================
+ (+) For some operation, the computation of the Montgomery parameter is a prerequisite.
+ (+) Input structure requires buffers as uint8_t array.
+ (+) Output structure requires buffers as uint32_t array.(Only used inside PKA).
+ (+) You can compute the Montgomery parameter using:
+ (++) HAL_PKA_MontgomeryParam().
+ (++) HAL_PKA_MontgomeryParam_IT().
+ (++) HAL_PKA_MontgomeryParam_GetResult() to retrieve the result of the operation.
+
+ *** Polling mode operation ***
+ ===================================
+ [..]
+ (+) When an operation is started in polling mode, the function returns when:
+ (++) A timeout is encounter.
+ (++) The operation is completed.
+
+ *** Interrupt mode operation ***
+ ===================================
+ [..]
+ (+) Add HAL_PKA_IRQHandler to the IRQHandler of PKA.
+ (+) Enable the IRQ using HAL_NVIC_EnableIRQ().
+ (+) When an operation is started in interrupt mode, the function returns immediately.
+ (+) When the operation is completed, the callback HAL_PKA_OperationCpltCallback is called.
+ (+) When an error is encountered, the callback HAL_PKA_ErrorCallback is called.
+ (+) To stop any operation in interrupt mode, use HAL_PKA_Abort().
+
+ *** Utilities ***
+ ===================================
+ [..]
+ (+) To clear the PKA RAM, use HAL_PKA_RAMReset().
+ (+) To get current state, use HAL_PKA_GetState().
+ (+) To get current error, use HAL_PKA_GetError().
+
+ *** Callback registration ***
+ =============================================
+ [..]
+
+ The compilation flag USE_HAL_PKA_REGISTER_CALLBACKS, when set to 1,
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions @ref HAL_PKA_RegisterCallback()
+ to register an interrupt callback.
+ [..]
+
+ Function @ref HAL_PKA_RegisterCallback() allows to register following callbacks:
+ (+) OperationCpltCallback : callback for End of operation.
+ (+) ErrorCallback : callback for error detection.
+ (+) MspInitCallback : callback for Msp Init.
+ (+) MspDeInitCallback : callback for Msp DeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+ [..]
+
+ Use function @ref HAL_PKA_UnRegisterCallback to reset a callback to the default
+ weak function.
+ [..]
+
+ @ref HAL_PKA_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) OperationCpltCallback : callback for End of operation.
+ (+) ErrorCallback : callback for error detection.
+ (+) MspInitCallback : callback for Msp Init.
+ (+) MspDeInitCallback : callback for Msp DeInit.
+ [..]
+
+ By default, after the @ref HAL_PKA_Init() and when the state is @ref HAL_PKA_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples @ref HAL_PKA_OperationCpltCallback(), @ref HAL_PKA_ErrorCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak functions in the @ref HAL_PKA_Init()/ @ref HAL_PKA_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ [..]
+
+ If MspInit or MspDeInit are not null, the @ref HAL_PKA_Init()/ @ref HAL_PKA_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+ [..]
+
+ Callbacks can be registered/unregistered in @ref HAL_PKA_STATE_READY state only.
+ Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ in @ref HAL_PKA_STATE_READY or @ref HAL_PKA_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ [..]
+
+ Then, the user first registers the MspInit/MspDeInit user callbacks
+ using @ref HAL_PKA_RegisterCallback() before calling @ref HAL_PKA_DeInit()
+ or @ref HAL_PKA_Init() function.
+ [..]
+
+ When the compilation flag USE_HAL_PKA_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+#if defined(PKA) && defined(HAL_PKA_MODULE_ENABLED)
+
+/** @defgroup PKA PKA
+ * @brief PKA HAL module driver.
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup PKA_Private_Define PKA Private Define
+ * @{
+ */
+#define PKA_RAM_SIZE 1334U
+
+/* Private macro -------------------------------------------------------------*/
+#define __PKA_RAM_PARAM_END(TAB,INDEX) do{ \
+ TAB[INDEX] = 0UL; \
+ TAB[INDEX + 1U] = 0UL; \
+ } while(0)
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup PKA_Private_Functions PKA Private Functions
+ * @{
+ */
+uint32_t PKA_GetMode(PKA_HandleTypeDef *hpka);
+HAL_StatusTypeDef PKA_PollEndOfOperation(PKA_HandleTypeDef *hpka, uint32_t Timeout, uint32_t Tickstart);
+uint32_t PKA_CheckError(PKA_HandleTypeDef *hpka, uint32_t mode);
+uint32_t PKA_GetBitSize_u8(uint32_t byteNumber);
+uint32_t PKA_GetOptBitSize_u8(uint32_t byteNumber, uint8_t msb);
+uint32_t PKA_GetBitSize_u32(uint32_t wordNumber);
+uint32_t PKA_GetArraySize_u8(uint32_t bitSize);
+void PKA_Memcpy_u32_to_u8(uint8_t dst[], __IO const uint32_t src[], size_t n);
+void PKA_Memcpy_u8_to_u32(__IO uint32_t dst[], const uint8_t src[], size_t n);
+void PKA_Memcpy_u32_to_u32(__IO uint32_t dst[], __IO const uint32_t src[], size_t n);
+HAL_StatusTypeDef PKA_Process(PKA_HandleTypeDef *hpka, uint32_t mode, uint32_t Timeout);
+HAL_StatusTypeDef PKA_Process_IT(PKA_HandleTypeDef *hpka, uint32_t mode);
+void PKA_ModExp_Set(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in);
+void PKA_ModExpFastMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in);
+void PKA_ModExpProtectMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpProtectModeInTypeDef *in);
+void PKA_ECDSASign_Set(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in);
+void PKA_ECDSAVerif_Set(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in);
+void PKA_RSACRTExp_Set(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in);
+void PKA_PointCheck_Set(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in);
+void PKA_ECCMul_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in);
+void PKA_ModRed_Set(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in);
+void PKA_ModInv_Set(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in);
+void PKA_MontgomeryParam_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint8_t *pOp1);
+void PKA_ARI_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint32_t *pOp1, const uint32_t *pOp2,
+ const uint8_t *pOp3);
+void PKA_ECCDoubleBaseLadder_Set(PKA_HandleTypeDef *hpka, PKA_ECCDoubleBaseLadderInTypeDef *in);
+void PKA_ECCProjective2Affine_Set(PKA_HandleTypeDef *hpka, PKA_ECCProjective2AffineInTypeDef *in);
+void PKA_ECCCompleteAddition_Set(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditionInTypeDef *in);
+HAL_StatusTypeDef PKA_WaitOnFlagUntilTimeout(PKA_HandleTypeDef *hpka, uint32_t Flag, FlagStatus Status,
+ uint32_t Tickstart, uint32_t Timeout);
+uint32_t PKA_Result_GetSize(PKA_HandleTypeDef *hpka, uint32_t Startindex, uint32_t Maxsize);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup PKA_Exported_Functions PKA Exported Functions
+ * @{
+ */
+
+/** @defgroup PKA_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ deinitialize the PKAx peripheral:
+
+ (+) User must implement HAL_PKA_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, IT and NVIC ).
+
+ (+) Call the function HAL_PKA_Init() to configure the device.
+
+ (+) Call the function HAL_PKA_DeInit() to restore the default configuration
+ of the selected PKAx peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the PKA according to the specified
+ * parameters in the PKA_InitTypeDef and initialize the associated handle.
+ * @param hpka PKA handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_Init(PKA_HandleTypeDef *hpka)
+{
+ HAL_StatusTypeDef err = HAL_OK;
+ uint32_t tickstart;
+
+ /* Check the PKA handle allocation */
+ if (hpka != NULL)
+ {
+ /* Check the parameters */
+ assert_param(IS_PKA_ALL_INSTANCE(hpka->Instance));
+
+ if (hpka->State == HAL_PKA_STATE_RESET)
+ {
+
+#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
+ /* Init the PKA Callback settings */
+ hpka->OperationCpltCallback = HAL_PKA_OperationCpltCallback; /* Legacy weak OperationCpltCallback */
+ hpka->ErrorCallback = HAL_PKA_ErrorCallback; /* Legacy weak ErrorCallback */
+
+ if (hpka->MspInitCallback == NULL)
+ {
+ hpka->MspInitCallback = HAL_PKA_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware */
+ hpka->MspInitCallback(hpka);
+#else
+ /* Init the low level hardware */
+ HAL_PKA_MspInit(hpka);
+#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
+ }
+
+ /* Set the state to busy */
+ hpka->State = HAL_PKA_STATE_BUSY;
+
+ /* Reset the control register and enable the PKA */
+ hpka->Instance->CR = PKA_CR_EN;
+
+ /* Get current tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait the INITOK flag Setting */
+ if (PKA_WaitOnFlagUntilTimeout(hpka, PKA_SR_INITOK, RESET, tickstart, 5000) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Reset any pending flag */
+ SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC);
+
+ /* Initialize the error code */
+ hpka->ErrorCode = HAL_PKA_ERROR_NONE;
+
+ /* Set the state to ready */
+ hpka->State = HAL_PKA_STATE_READY;
+ }
+ else
+ {
+ err = HAL_ERROR;
+ }
+
+ return err;
+}
+
+/**
+ * @brief DeInitialize the PKA peripheral.
+ * @param hpka PKA handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_DeInit(PKA_HandleTypeDef *hpka)
+{
+ HAL_StatusTypeDef err = HAL_OK;
+
+ /* Check the PKA handle allocation */
+ if (hpka != NULL)
+ {
+ /* Check the parameters */
+ assert_param(IS_PKA_ALL_INSTANCE(hpka->Instance));
+
+ /* Set the state to busy */
+ hpka->State = HAL_PKA_STATE_BUSY;
+
+ /* Reset the control register */
+ /* This abort any operation in progress (PKA RAM content is not guaranteed in this case) */
+ hpka->Instance->CR = 0;
+
+ /* Reset any pending flag */
+ SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC);
+
+#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
+ if (hpka->MspDeInitCallback == NULL)
+ {
+ hpka->MspDeInitCallback = HAL_PKA_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ hpka->MspDeInitCallback(hpka);
+#else
+ /* DeInit the low level hardware: CLOCK, NVIC */
+ HAL_PKA_MspDeInit(hpka);
+#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
+
+ /* Reset the error code */
+ hpka->ErrorCode = HAL_PKA_ERROR_NONE;
+
+ /* Reset the state */
+ hpka->State = HAL_PKA_STATE_RESET;
+ }
+ else
+ {
+ err = HAL_ERROR;
+ }
+
+ return err;
+}
+
+/**
+ * @brief Initialize the PKA MSP.
+ * @param hpka PKA handle
+ * @retval None
+ */
+__weak void HAL_PKA_MspInit(PKA_HandleTypeDef *hpka)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpka);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PKA_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the PKA MSP.
+ * @param hpka PKA handle
+ * @retval None
+ */
+__weak void HAL_PKA_MspDeInit(PKA_HandleTypeDef *hpka)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpka);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PKA_MspDeInit can be implemented in the user file
+ */
+}
+
+#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User PKA Callback
+ * To be used instead of the weak predefined callback
+ * @param hpka Pointer to a PKA_HandleTypeDef structure that contains
+ * the configuration information for the specified PKA.
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_PKA_OPERATION_COMPLETE_CB_ID End of operation callback ID
+ * @arg @ref HAL_PKA_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_PKA_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_PKA_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_RegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID,
+ pPKA_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ if (HAL_PKA_STATE_READY == hpka->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_PKA_OPERATION_COMPLETE_CB_ID :
+ hpka->OperationCpltCallback = pCallback;
+ break;
+
+ case HAL_PKA_ERROR_CB_ID :
+ hpka->ErrorCallback = pCallback;
+ break;
+
+ case HAL_PKA_MSPINIT_CB_ID :
+ hpka->MspInitCallback = pCallback;
+ break;
+
+ case HAL_PKA_MSPDEINIT_CB_ID :
+ hpka->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_PKA_STATE_RESET == hpka->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_PKA_MSPINIT_CB_ID :
+ hpka->MspInitCallback = pCallback;
+ break;
+
+ case HAL_PKA_MSPDEINIT_CB_ID :
+ hpka->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Unregister a PKA Callback
+ * PKA callback is redirected to the weak predefined callback
+ * @param hpka Pointer to a PKA_HandleTypeDef structure that contains
+ * the configuration information for the specified PKA.
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_PKA_OPERATION_COMPLETE_CB_ID End of operation callback ID
+ * @arg @ref HAL_PKA_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_PKA_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_PKA_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_UnRegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (HAL_PKA_STATE_READY == hpka->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_PKA_OPERATION_COMPLETE_CB_ID :
+ hpka->OperationCpltCallback = HAL_PKA_OperationCpltCallback; /* Legacy weak OperationCpltCallback */
+ break;
+
+ case HAL_PKA_ERROR_CB_ID :
+ hpka->ErrorCallback = HAL_PKA_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_PKA_MSPINIT_CB_ID :
+ hpka->MspInitCallback = HAL_PKA_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_PKA_MSPDEINIT_CB_ID :
+ hpka->MspDeInitCallback = HAL_PKA_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_PKA_STATE_RESET == hpka->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_PKA_MSPINIT_CB_ID :
+ hpka->MspInitCallback = HAL_PKA_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_PKA_MSPDEINIT_CB_ID :
+ hpka->MspDeInitCallback = HAL_PKA_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup PKA_Exported_Functions_Group2 IO operation functions
+ * @brief IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the PKA operations.
+
+ (#) There are two modes of operation:
+
+ (++) Blocking mode : The operation is performed in the polling mode.
+ These functions return when data operation is completed.
+ (++) No-Blocking mode : The operation is performed using Interrupts.
+ These functions return immediately.
+ The end of the operation is indicated by HAL_PKA_ErrorCallback in case of error.
+ The end of the operation is indicated by HAL_PKA_OperationCpltCallback in case of success.
+ To stop any operation in interrupt mode, use HAL_PKA_Abort().
+
+ (#) Blocking mode functions are :
+
+ (++) HAL_PKA_ModExp()
+ (++) HAL_PKA_ModExpFastMode()
+ (++) HAL_PKA_ModExpProtectMode()
+ (++) HAL_PKA_ModExp_GetResult();
+
+ (++) HAL_PKA_ECDSASign()
+ (++) HAL_PKA_ECDSASign_GetResult();
+
+ (++) HAL_PKA_ECDSAVerif()
+ (++) HAL_PKA_ECDSAVerif_IsValidSignature();
+
+ (++) HAL_PKA_RSACRTExp()
+ (++) HAL_PKA_RSACRTExp_GetResult();
+
+ (++) HAL_PKA_PointCheck()
+ (++) HAL_PKA_PointCheck_IsOnCurve();
+
+ (++) HAL_PKA_ECCMul()
+ (++) HAL_PKA_ECCMulFastMode()
+ (++) HAL_PKA_ECCMul_GetResult();
+
+ (++) HAL_PKA_ECCDoubleBaseLadder()
+ (++) HAL_PKA_ECCDoubleBaseLadder_GetResult();
+ (++) HAL_PKA_ECCProjective2Affine()
+ (++) HAL_PKA_ECCProjective2Affine_GetResult();
+ (++) HAL_PKA_ECCCompleteAddition()
+ (++) HAL_PKA_ECCCompleteAddition_GetResult();
+
+ (++) HAL_PKA_Add()
+ (++) HAL_PKA_Sub()
+ (++) HAL_PKA_Cmp()
+ (++) HAL_PKA_Mul()
+ (++) HAL_PKA_ModAdd()
+ (++) HAL_PKA_ModSub()
+ (++) HAL_PKA_ModInv()
+ (++) HAL_PKA_ModRed()
+ (++) HAL_PKA_MontgomeryMul()
+ (++) HAL_PKA_Arithmetic_GetResult(P);
+
+ (++) HAL_PKA_MontgomeryParam()
+ (++) HAL_PKA_MontgomeryParam_GetResult();
+
+ (#) No-Blocking mode functions with Interrupt are :
+
+ (++) HAL_PKA_ModExp_IT();
+ (++) HAL_PKA_ModExpFastMode_IT();
+ (++) HAL_PKA_ModExpProtectMode_IT()
+ (++) HAL_PKA_ModExp_GetResult();
+
+ (++) HAL_PKA_ECDSASign_IT();
+ (++) HAL_PKA_ECDSASign_GetResult();
+
+ (++) HAL_PKA_ECDSAVerif_IT();
+ (++) HAL_PKA_ECDSAVerif_IsValidSignature();
+
+ (++) HAL_PKA_RSACRTExp_IT();
+ (++) HAL_PKA_RSACRTExp_GetResult();
+
+ (++) HAL_PKA_PointCheck_IT();
+ (++) HAL_PKA_PointCheck_IsOnCurve();
+
+ (++) HAL_PKA_ECCMul_IT();
+ (++) HAL_PKA_ECCMulFastMode_IT();
+ (++) HAL_PKA_ECCMul_GetResult();
+
+ (++) HAL_PKA_ECCDoubleBaseLadder_IT()
+ (++) HAL_PKA_ECCDoubleBaseLadder_GetResult();
+ (++) HAL_PKA_ECCProjective2Affine_IT()
+ (++) HAL_PKA_ECCProjective2Affine_GetResult();
+ (++) HAL_PKA_ECCCompleteAddition_IT()
+ (++) HAL_PKA_ECCCompleteAddition_GetResult();
+ (++) HAL_PKA_Add_IT();
+ (++) HAL_PKA_Sub_IT();
+ (++) HAL_PKA_Cmp_IT();
+ (++) HAL_PKA_Mul_IT();
+ (++) HAL_PKA_ModAdd_IT();
+ (++) HAL_PKA_ModSub_IT();
+ (++) HAL_PKA_ModInv_IT();
+ (++) HAL_PKA_ModRed_IT();
+ (++) HAL_PKA_MontgomeryMul_IT();
+ (++) HAL_PKA_Arithmetic_GetResult();
+
+ (++) HAL_PKA_MontgomeryParam_IT();
+ (++) HAL_PKA_MontgomeryParam_GetResult();
+
+ (++) HAL_PKA_Abort();
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Modular exponentiation in blocking mode.
+ * @param hpka PKA handle
+ * @param in Input information
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_ModExp(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in, uint32_t Timeout)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_ModExp_Set(hpka, in);
+
+ /* Start the operation */
+ return PKA_Process(hpka, PKA_MODE_MODULAR_EXP, Timeout);
+}
+
+/**
+ * @brief Modular exponentiation in non-blocking mode with Interrupt.
+ * @param hpka PKA handle
+ * @param in Input information
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_ModExp_IT(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_ModExp_Set(hpka, in);
+
+ /* Start the operation */
+ return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP);
+}
+
+/**
+ * @brief Modular exponentiation in blocking mode.
+ * @param hpka PKA handle
+ * @param in Input information
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_ModExpFastMode(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in, uint32_t Timeout)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_ModExpFastMode_Set(hpka, in);
+
+ /* Start the operation */
+ return PKA_Process(hpka, PKA_MODE_MODULAR_EXP_FAST_MODE, Timeout);
+}
+
+/**
+ * @brief Modular exponentiation in non-blocking mode with Interrupt.
+ * @param hpka PKA handle
+ * @param in Input information
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_ModExpFastMode_IT(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_ModExpFastMode_Set(hpka, in);
+
+ /* Start the operation */
+ return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP_FAST_MODE);
+}
+
+/**
+ * @brief Modular exponentiation (protected) in blocking mode.
+ * Useful when a secret information is involved (RSA decryption)
+ * @param hpka PKA handle
+ * @param in Input information
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_ModExpProtectMode(PKA_HandleTypeDef *hpka, PKA_ModExpProtectModeInTypeDef *in,
+ uint32_t Timeout)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_ModExpProtectMode_Set(hpka, in);
+
+ return PKA_Process(hpka, PKA_MODE_MODULAR_EXP_PROTECT, Timeout);
+}
+
+/**
+ * @brief Modular exponentiation (protected) in non-blocking mode with Interrupt.
+ * Useful when a secret information is involved (RSA decryption)
+ * @param hpka PKA handle
+ * @param in Input information
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_ModExpProtectMode_IT(PKA_HandleTypeDef *hpka, PKA_ModExpProtectModeInTypeDef *in)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_ModExpProtectMode_Set(hpka, in);
+
+ return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP_PROTECT);
+}
+
+/**
+ * @brief Retrieve operation result.
+ * @param hpka PKA handle
+ * @param pRes Output buffer
+ * @retval HAL status
+ */
+void HAL_PKA_ModExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes)
+{
+ uint32_t size;
+
+ /* Get output result size */
+ size = PKA_Result_GetSize(hpka, PKA_MODULAR_EXP_OUT_RESULT, 130UL);
+
+ /* Move the result to appropriate location (indicated in out parameter) */
+ PKA_Memcpy_u32_to_u8(pRes, &hpka->Instance->RAM[PKA_MODULAR_EXP_OUT_RESULT], size);
+}
+
+/**
+ * @brief Sign a message using elliptic curves over prime fields in blocking mode.
+ * @param hpka PKA handle
+ * @param in Input information
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_ECDSASign(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in, uint32_t Timeout)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_ECDSASign_Set(hpka, in);
+
+ /* Start the operation */
+ return PKA_Process(hpka, PKA_MODE_ECDSA_SIGNATURE, Timeout);
+}
+
+/**
+ * @brief Sign a message using elliptic curves over prime fields in non-blocking mode with Interrupt.
+ * @param hpka PKA handle
+ * @param in Input information
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_ECDSASign_IT(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_ECDSASign_Set(hpka, in);
+
+ /* Start the operation */
+ return PKA_Process_IT(hpka, PKA_MODE_ECDSA_SIGNATURE);
+}
+
+/**
+ * @brief Retrieve operation result.
+ * @param hpka PKA handle
+ * @param out Output information
+ * @param outExt Additional Output information (facultative)
+ */
+void HAL_PKA_ECDSASign_GetResult(PKA_HandleTypeDef *hpka, PKA_ECDSASignOutTypeDef *out,
+ PKA_ECDSASignOutExtParamTypeDef *outExt)
+{
+ uint32_t size;
+
+ /* Get output result size */
+ size = PKA_Result_GetSize(hpka, PKA_ECDSA_SIGN_OUT_SIGNATURE_R, 20UL);
+
+ if (out != NULL)
+ {
+ PKA_Memcpy_u32_to_u8(out->RSign, &hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_R], size);
+ PKA_Memcpy_u32_to_u8(out->SSign, &hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_S], size);
+ }
+
+ /* If user requires the additional information */
+ if (outExt != NULL)
+ {
+ /* Move the result to appropriate location (indicated in outExt parameter) */
+ PKA_Memcpy_u32_to_u8(outExt->ptX, &hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_FINAL_POINT_X], size);
+ PKA_Memcpy_u32_to_u8(outExt->ptY, &hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y], size);
+ }
+}
+
+/**
+ * @brief Verify the validity of a signature using elliptic curves over prime fields in blocking mode.
+ * @param hpka PKA handle
+ * @param in Input information
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_ECDSAVerif(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in, uint32_t Timeout)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_ECDSAVerif_Set(hpka, in);
+
+ /* Start the operation */
+ return PKA_Process(hpka, PKA_MODE_ECDSA_VERIFICATION, Timeout);
+}
+
+/**
+ * @brief Verify the validity of a signature using elliptic curves
+ * over prime fields in non-blocking mode with Interrupt.
+ * @param hpka PKA handle
+ * @param in Input information
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_ECDSAVerif_IT(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_ECDSAVerif_Set(hpka, in);
+
+ /* Start the operation */
+ return PKA_Process_IT(hpka, PKA_MODE_ECDSA_VERIFICATION);
+}
+
+/**
+ * @brief Return the result of the ECDSA verification operation.
+ * @param hpka PKA handle
+ * @retval 1 if signature is verified, 0 in other case
+ */
+uint32_t HAL_PKA_ECDSAVerif_IsValidSignature(PKA_HandleTypeDef const *const hpka)
+{
+ return (hpka->Instance->RAM[PKA_ECDSA_VERIF_OUT_RESULT] == 0xD60DU) ? 1UL : 0UL;
+}
+
+/**
+ * @brief RSA CRT exponentiation in blocking mode.
+ * @param hpka PKA handle
+ * @param in Input information
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_RSACRTExp(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in, uint32_t Timeout)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_RSACRTExp_Set(hpka, in);
+
+ /* Start the operation */
+ return PKA_Process(hpka, PKA_MODE_RSA_CRT_EXP, Timeout);
+}
+
+/**
+ * @brief RSA CRT exponentiation in non-blocking mode with Interrupt.
+ * @param hpka PKA handle
+ * @param in Input information
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_RSACRTExp_IT(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_RSACRTExp_Set(hpka, in);
+
+ /* Start the operation */
+ return PKA_Process_IT(hpka, PKA_MODE_RSA_CRT_EXP);
+}
+
+/**
+ * @brief Retrieve operation result.
+ * @param hpka PKA handle
+ * @param pRes Pointer to memory location to receive the result of the operation
+ * @retval HAL status
+ */
+void HAL_PKA_RSACRTExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes)
+{
+ uint32_t size;
+
+ /* Move the result to appropriate location (indicated in out parameter) */
+ size = (hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_MOD_NB_BITS] + 7UL) / 8UL;
+
+ PKA_Memcpy_u32_to_u8(pRes, &hpka->Instance->RAM[PKA_RSA_CRT_EXP_OUT_RESULT], size);
+}
+
+/**
+ * @brief Point on elliptic curve check in blocking mode.
+ * @param hpka PKA handle
+ * @param in Input information
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_PointCheck(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in, uint32_t Timeout)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_PointCheck_Set(hpka, in);
+
+ /* Start the operation */
+ return PKA_Process(hpka, PKA_MODE_POINT_CHECK, Timeout);
+}
+
+/**
+ * @brief Point on elliptic curve check in non-blocking mode with Interrupt.
+ * @param hpka PKA handle
+ * @param in Input information
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_PointCheck_IT(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_PointCheck_Set(hpka, in);
+
+ /* Start the operation */
+ return PKA_Process_IT(hpka, PKA_MODE_POINT_CHECK);
+}
+
+/**
+ * @brief Return the result of the point check operation.
+ * @param hpka PKA handle
+ * @retval 1 if point is on curve, 0 in other case
+ */
+uint32_t HAL_PKA_PointCheck_IsOnCurve(PKA_HandleTypeDef const *const hpka)
+{
+#define PKA_POINT_IS_ON_CURVE 0xD60DUL
+ /* Invert the value of the PKA RAM containing the result of the operation */
+ return (hpka->Instance->RAM[PKA_POINT_CHECK_OUT_ERROR] == PKA_POINT_IS_ON_CURVE) ? 1UL : 0UL;
+}
+
+/**
+ * @brief ECC scalar multiplication in blocking mode.
+ * @param hpka PKA handle
+ * @param in Input information
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_ECCMul(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in, uint32_t Timeout)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_ECCMul_Set(hpka, in);
+
+ /* Start the operation */
+ return PKA_Process(hpka, PKA_MODE_ECC_MUL, Timeout);
+}
+
+/**
+ * @brief ECC scalar multiplication in non-blocking mode with Interrupt.
+ * @param hpka PKA handle
+ * @param in Input information
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_ECCMul_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_ECCMul_Set(hpka, in);
+
+ /* Start the operation */
+ return PKA_Process_IT(hpka, PKA_MODE_ECC_MUL);
+}
+/**
+ * @brief Retrieve operation result.
+ * @param hpka PKA handle
+ * @param out Output information
+ * @retval HAL status
+ */
+void HAL_PKA_ECCMul_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCMulOutTypeDef *out)
+{
+ uint32_t size;
+
+ /* Get output result size */
+ size = PKA_Result_GetSize(hpka, PKA_ECC_SCALAR_MUL_OUT_RESULT_X, 20UL);
+
+ /* If a destination buffer is provided */
+ if (out != NULL)
+ {
+ /* Move the result to appropriate location (indicated in out parameter) */
+ PKA_Memcpy_u32_to_u8(out->ptX, &hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_X], size);
+ PKA_Memcpy_u32_to_u8(out->ptY, &hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_Y], size);
+ }
+}
+
+/**
+ * @brief Arithmetic addition in blocking mode.
+ * @param hpka PKA handle
+ * @param in Input information
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_Add(PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in, uint32_t Timeout)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL);
+
+ /* Start the operation */
+ return PKA_Process(hpka, PKA_MODE_ARITHMETIC_ADD, Timeout);
+}
+
+/**
+ * @brief Arithmetic addition in non-blocking mode with Interrupt.
+ * @param hpka PKA handle
+ * @param in Input information
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_Add_IT(PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL);
+
+ /* Start the operation */
+ return PKA_Process_IT(hpka, PKA_MODE_ARITHMETIC_ADD);
+}
+
+/**
+ * @brief Arithmetic subtraction in blocking mode.
+ * @param hpka PKA handle
+ * @param in Input information
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_Sub(PKA_HandleTypeDef *hpka, PKA_SubInTypeDef *in, uint32_t Timeout)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL);
+
+ /* Start the operation */
+ return PKA_Process(hpka, PKA_MODE_ARITHMETIC_SUB, Timeout);
+}
+
+/**
+ * @brief Arithmetic subtraction in non-blocking mode with Interrupt.
+ * @param hpka PKA handle
+ * @param in Input information
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_Sub_IT(PKA_HandleTypeDef *hpka, PKA_SubInTypeDef *in)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL);
+
+ /* Start the operation */
+ return PKA_Process_IT(hpka, PKA_MODE_ARITHMETIC_SUB);
+}
+
+/**
+ * @brief Arithmetic multiplication in blocking mode.
+ * @param hpka PKA handle
+ * @param in Input information
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_Mul(PKA_HandleTypeDef *hpka, PKA_MulInTypeDef *in, uint32_t Timeout)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL);
+
+ /* Start the operation */
+ return PKA_Process(hpka, PKA_MODE_ARITHMETIC_MUL, Timeout);
+}
+
+/**
+ * @brief Arithmetic multiplication in non-blocking mode with Interrupt.
+ * @param hpka PKA handle
+ * @param in Input information
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_Mul_IT(PKA_HandleTypeDef *hpka, PKA_MulInTypeDef *in)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL);
+
+ /* Start the operation */
+ return PKA_Process_IT(hpka, PKA_MODE_ARITHMETIC_MUL);
+}
+
+/**
+ * @brief Comparison in blocking mode.
+ * @param hpka PKA handle
+ * @param in Input information
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_Cmp(PKA_HandleTypeDef *hpka, PKA_CmpInTypeDef *in, uint32_t Timeout)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL);
+
+ /* Start the operation */
+ return PKA_Process(hpka, PKA_MODE_COMPARISON, Timeout);
+}
+
+/**
+ * @brief Comparison in non-blocking mode with Interrupt.
+ * @param hpka PKA handle
+ * @param in Input information
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_Cmp_IT(PKA_HandleTypeDef *hpka, PKA_CmpInTypeDef *in)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL);
+
+ /* Start the operation */
+ return PKA_Process_IT(hpka, PKA_MODE_COMPARISON);
+}
+
+/**
+ * @brief Modular addition in blocking mode.
+ * @param hpka PKA handle
+ * @param in Input information
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_ModAdd(PKA_HandleTypeDef *hpka, PKA_ModAddInTypeDef *in, uint32_t Timeout)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, in->pOp3);
+
+ /* Start the operation */
+ return PKA_Process(hpka, PKA_MODE_MODULAR_ADD, Timeout);
+}
+
+/**
+ * @brief Modular addition in non-blocking mode with Interrupt.
+ * @param hpka PKA handle
+ * @param in Input information
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_ModAdd_IT(PKA_HandleTypeDef *hpka, PKA_ModAddInTypeDef *in)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, in->pOp3);
+
+ /* Start the operation */
+ return PKA_Process_IT(hpka, PKA_MODE_MODULAR_ADD);
+}
+
+/**
+ * @brief Modular inversion in blocking mode.
+ * @param hpka PKA handle
+ * @param in Input information
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_ModInv(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in, uint32_t Timeout)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_ModInv_Set(hpka, in);
+
+ /* Start the operation */
+ return PKA_Process(hpka, PKA_MODE_MODULAR_INV, Timeout);
+}
+
+/**
+ * @brief Modular inversion in non-blocking mode with Interrupt.
+ * @param hpka PKA handle
+ * @param in Input information
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_ModInv_IT(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_ModInv_Set(hpka, in);
+
+ /* Start the operation */
+ return PKA_Process_IT(hpka, PKA_MODE_MODULAR_INV);
+}
+
+/**
+ * @brief Modular subtraction in blocking mode.
+ * @param hpka PKA handle
+ * @param in Input information
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_ModSub(PKA_HandleTypeDef *hpka, PKA_ModSubInTypeDef *in, uint32_t Timeout)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, in->pOp3);
+
+ /* Start the operation */
+ return PKA_Process(hpka, PKA_MODE_MODULAR_SUB, Timeout);
+}
+
+/**
+ * @brief Modular subtraction in non-blocking mode with Interrupt.
+ * @param hpka PKA handle
+ * @param in Input information
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_ModSub_IT(PKA_HandleTypeDef *hpka, PKA_ModSubInTypeDef *in)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, in->pOp3);
+
+ /* Start the operation */
+ return PKA_Process_IT(hpka, PKA_MODE_MODULAR_SUB);
+}
+
+/**
+ * @brief Modular reduction in blocking mode.
+ * @param hpka PKA handle
+ * @param in Input information
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_ModRed(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in, uint32_t Timeout)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_ModRed_Set(hpka, in);
+
+ /* Start the operation */
+ return PKA_Process(hpka, PKA_MODE_MODULAR_RED, Timeout);
+}
+
+/**
+ * @brief Modular reduction in non-blocking mode with Interrupt.
+ * @param hpka PKA handle
+ * @param in Input information
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_ModRed_IT(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_ModRed_Set(hpka, in);
+
+ /* Start the operation */
+ return PKA_Process_IT(hpka, PKA_MODE_MODULAR_RED);
+}
+
+/**
+ * @brief Montgomery multiplication in blocking mode.
+ * @param hpka PKA handle
+ * @param in Input information
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_MontgomeryMul(PKA_HandleTypeDef *hpka, PKA_MontgomeryMulInTypeDef *in, uint32_t Timeout)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, in->pOp3);
+
+ /* Start the operation */
+ return PKA_Process(hpka, PKA_MODE_MONTGOMERY_MUL, Timeout);
+}
+
+/**
+ * @brief Montgomery multiplication in non-blocking mode with Interrupt.
+ * @param hpka PKA handle
+ * @param in Input information
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_MontgomeryMul_IT(PKA_HandleTypeDef *hpka, PKA_MontgomeryMulInTypeDef *in)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, in->pOp3);
+
+ /* Start the operation */
+ return PKA_Process_IT(hpka, PKA_MODE_MONTGOMERY_MUL);
+}
+
+/**
+ * @brief Retrieve operation result.
+ * @param hpka PKA handle
+ * @param pRes Pointer to memory location to receive the result of the operation
+ */
+void HAL_PKA_Arithmetic_GetResult(PKA_HandleTypeDef *hpka, uint32_t *pRes)
+{
+ uint32_t mode = (hpka->Instance->CR & PKA_CR_MODE_Msk) >> PKA_CR_MODE_Pos;
+ uint32_t size = 0;
+
+ /* Move the result to appropriate location (indicated in pRes parameter) */
+ switch (mode)
+ {
+ case PKA_MODE_MONTGOMERY_PARAM:
+ case PKA_MODE_ARITHMETIC_SUB:
+ case PKA_MODE_MODULAR_ADD:
+ case PKA_MODE_MODULAR_RED:
+ case PKA_MODE_MODULAR_INV:
+ case PKA_MODE_MONTGOMERY_MUL:
+ size = hpka->Instance->RAM[2] / 32UL;
+ break;
+ case PKA_MODE_ARITHMETIC_ADD:
+ case PKA_MODE_MODULAR_SUB:
+ size = hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_NB_BITS] / 32UL;
+
+ /* Manage the overflow of the addition */
+ if (hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_OUT_RESULT + size] != 0UL)
+ {
+ size += 1UL;
+ }
+
+ break;
+ case PKA_MODE_COMPARISON:
+ size = 1;
+ break;
+ case PKA_MODE_ARITHMETIC_MUL:
+ size = hpka->Instance->RAM[PKA_ARITHMETIC_MUL_NB_BITS] / 32UL * 2UL;
+ break;
+ default:
+ break;
+ }
+
+ if (pRes != NULL)
+ {
+ switch (mode)
+ {
+ case PKA_MODE_ARITHMETIC_SUB:
+ case PKA_MODE_MODULAR_ADD:
+ case PKA_MODE_MODULAR_RED:
+ case PKA_MODE_MODULAR_INV:
+ case PKA_MODE_MODULAR_SUB:
+ case PKA_MODE_MONTGOMERY_MUL:
+ case PKA_MODE_ARITHMETIC_ADD:
+ case PKA_MODE_COMPARISON:
+ case PKA_MODE_ARITHMETIC_MUL:
+ PKA_Memcpy_u32_to_u32(pRes, &hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_OUT_RESULT], size);
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+/**
+ * @brief Montgomery parameter computation in blocking mode.
+ * @param hpka PKA handle
+ * @param in Input information
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_MontgomeryParam(PKA_HandleTypeDef *hpka, PKA_MontgomeryParamInTypeDef *in, uint32_t Timeout)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_MontgomeryParam_Set(hpka, in->size, in->pOp1);
+
+ /* Start the operation */
+ return PKA_Process(hpka, PKA_MODE_MONTGOMERY_PARAM, Timeout);
+}
+
+/**
+ * @brief Montgomery parameter computation in non-blocking mode with Interrupt.
+ * @param hpka PKA handle
+ * @param in Input information
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_MontgomeryParam_IT(PKA_HandleTypeDef *hpka, PKA_MontgomeryParamInTypeDef *in)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_MontgomeryParam_Set(hpka, in->size, in->pOp1);
+
+ /* Start the operation */
+ return PKA_Process_IT(hpka, PKA_MODE_MONTGOMERY_PARAM);
+}
+
+/**
+ * @brief ECC double base ladder in blocking mode.
+ * @param hpka PKA handle
+ * @param in Input information
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_ECCDoubleBaseLadder(PKA_HandleTypeDef *hpka, PKA_ECCDoubleBaseLadderInTypeDef *in,
+ uint32_t Timeout)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_ECCDoubleBaseLadder_Set(hpka, in);
+
+ return PKA_Process(hpka, PKA_MODE_DOUBLE_BASE_LADDER, Timeout);
+}
+
+/**
+ * @brief ECC double base ladder in non-blocking mode with Interrupt.
+ * @param hpka PKA handle
+ * @param in Input information
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_ECCDoubleBaseLadder_IT(PKA_HandleTypeDef *hpka, PKA_ECCDoubleBaseLadderInTypeDef *in)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_ECCDoubleBaseLadder_Set(hpka, in);
+
+ return PKA_Process_IT(hpka, PKA_MODE_DOUBLE_BASE_LADDER);
+}
+
+/**
+ * @brief ECC projective to affine in blocking mode.
+ * @param hpka PKA handle
+ * @param in Input information
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_ECCProjective2Affine(PKA_HandleTypeDef *hpka, PKA_ECCProjective2AffineInTypeDef *in,
+ uint32_t Timeout)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_ECCProjective2Affine_Set(hpka, in);
+
+ return PKA_Process(hpka, PKA_MODE_ECC_PROJECTIVE_AFF, Timeout);
+}
+
+/**
+ * @brief ECC projective to affine in non-blocking mode with Interrupt.
+ * @param hpka PKA handle
+ * @param in Input information
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_ECCProjective2Affine_IT(PKA_HandleTypeDef *hpka, PKA_ECCProjective2AffineInTypeDef *in)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_ECCProjective2Affine_Set(hpka, in);
+
+ return PKA_Process_IT(hpka, PKA_MODE_ECC_PROJECTIVE_AFF);
+}
+
+/**
+ * @brief ECC complete addition in blocking mode.
+ * @param hpka PKA handle
+ * @param in Input information
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_ECCCompleteAddition(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditionInTypeDef *in,
+ uint32_t Timeout)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_ECCCompleteAddition_Set(hpka, in);
+
+ return PKA_Process(hpka, PKA_MODE_ECC_COMPLETE_ADD, Timeout);
+}
+
+/**
+ * @brief ECC complete addition in non-blocking mode with Interrupt.
+ * @param hpka PKA handle
+ * @param in Input information
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_ECCCompleteAddition_IT(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditionInTypeDef *in)
+{
+ /* Set input parameter in PKA RAM */
+ PKA_ECCCompleteAddition_Set(hpka, in);
+
+ return PKA_Process_IT(hpka, PKA_MODE_ECC_COMPLETE_ADD);
+}
+
+/**
+ * @brief Retrieve operation result.
+ * @param hpka PKA handle
+ * @param pRes pointer to buffer where the result will be copied
+ * @retval HAL status
+ */
+void HAL_PKA_MontgomeryParam_GetResult(PKA_HandleTypeDef *hpka, uint32_t *pRes)
+{
+ uint32_t size;
+
+ /* Retrieve the size of the buffer from the PKA RAM */
+ size = (hpka->Instance->RAM[PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS] + 31UL) / 32UL;
+
+ /* Move the result to appropriate location (indicated in out parameter) */
+ PKA_Memcpy_u32_to_u32(pRes, &hpka->Instance->RAM[PKA_MONTGOMERY_PARAM_OUT_PARAMETER], size);
+}
+
+/**
+ * @brief Abort any ongoing operation.
+ * @param hpka PKA handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PKA_Abort(PKA_HandleTypeDef *hpka)
+{
+ HAL_StatusTypeDef err = HAL_OK;
+
+ /* Clear EN bit */
+ /* This abort any operation in progress (PKA RAM content is not guaranteed in this case) */
+ CLEAR_BIT(hpka->Instance->CR, PKA_CR_EN);
+ SET_BIT(hpka->Instance->CR, PKA_CR_EN);
+
+ /* Reset any pending flag */
+ SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC);
+
+ /* Reset the error code */
+ hpka->ErrorCode = HAL_PKA_ERROR_NONE;
+
+ /* Reset the state */
+ hpka->State = HAL_PKA_STATE_READY;
+
+ return err;
+}
+
+/**
+ * @brief Reset the PKA RAM.
+ * @param hpka PKA handle
+ * @retval None
+ */
+void HAL_PKA_RAMReset(PKA_HandleTypeDef *hpka)
+{
+ uint32_t index;
+
+ /* For each element in the PKA RAM */
+ for (index = 0; index < PKA_RAM_SIZE; index++)
+ {
+ /* Clear the content */
+ hpka->Instance->RAM[index] = 0UL;
+ }
+}
+
+/**
+ * @brief This function handles PKA event interrupt request.
+ * @param hpka PKA handle
+ * @retval None
+ */
+void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka)
+{
+ uint32_t mode = PKA_GetMode(hpka);
+ FlagStatus addErrFlag = __HAL_PKA_GET_FLAG(hpka, PKA_FLAG_ADDRERR);
+ FlagStatus ramErrFlag = __HAL_PKA_GET_FLAG(hpka, PKA_FLAG_RAMERR);
+ FlagStatus procEndFlag = __HAL_PKA_GET_FLAG(hpka, PKA_FLAG_PROCEND);
+ FlagStatus operErrFlag = __HAL_PKA_GET_FLAG(hpka, PKA_FLAG_OPERR);
+
+ /* Address error interrupt occurred */
+ if ((__HAL_PKA_GET_IT_SOURCE(hpka, PKA_IT_ADDRERR) == SET) && (addErrFlag == SET))
+ {
+ hpka->ErrorCode |= HAL_PKA_ERROR_ADDRERR;
+
+ /* Clear ADDRERR flag */
+ __HAL_PKA_CLEAR_FLAG(hpka, PKA_FLAG_ADDRERR);
+ }
+
+ /* RAM access error interrupt occurred */
+ if ((__HAL_PKA_GET_IT_SOURCE(hpka, PKA_IT_RAMERR) == SET) && (ramErrFlag == SET))
+ {
+ hpka->ErrorCode |= HAL_PKA_ERROR_RAMERR;
+
+ /* Clear RAMERR flag */
+ __HAL_PKA_CLEAR_FLAG(hpka, PKA_FLAG_RAMERR);
+ }
+
+ /* OPERATION access error interrupt occurred */
+ if ((__HAL_PKA_GET_IT_SOURCE(hpka, PKA_FLAG_OPERR) == SET) && (operErrFlag == SET))
+ {
+ hpka->ErrorCode |= HAL_PKA_ERROR_OPERATION;
+
+ /* Clear OPERR flag */
+ __HAL_PKA_CLEAR_FLAG(hpka, PKA_FLAG_OPERR);
+ }
+
+ /* Check the operation success in case of ECDSA signature */
+ switch (mode)
+ {
+ case PKA_MODE_ECDSA_SIGNATURE :
+ /* If error output result is different from no error, operation need to be repeated */
+ if (hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_ERROR] != PKA_NO_ERROR)
+ {
+ hpka->ErrorCode |= HAL_PKA_ERROR_OPERATION;
+ }
+ break;
+
+ case PKA_MODE_DOUBLE_BASE_LADDER :
+ /* If error output result is different from no error, operation need to be repeated */
+ if (hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_OUT_ERROR] != PKA_NO_ERROR)
+ {
+ hpka->ErrorCode |= HAL_PKA_ERROR_OPERATION;
+ }
+ break;
+
+ case PKA_MODE_ECC_PROJECTIVE_AFF :
+ /* If error output result is different from no error, operation need to be repeated */
+ if (hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_OUT_ERROR] != PKA_NO_ERROR)
+ {
+ hpka->ErrorCode |= HAL_PKA_ERROR_OPERATION;
+ }
+ break;
+
+ case PKA_MODE_ECC_MUL :
+ /* If error output result is different from no error, operation need to be repeated */
+ if (hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_OUT_ERROR] != PKA_NO_ERROR)
+ {
+ hpka->ErrorCode |= HAL_PKA_ERROR_OPERATION;
+ }
+ break;
+
+ case PKA_MODE_MODULAR_EXP_PROTECT :
+ /* If error output result is different from no error, operation need to be repeated */
+ if (hpka->Instance->RAM[PKA_MODULAR_EXP_OUT_ERROR] != PKA_NO_ERROR)
+ {
+ hpka->ErrorCode |= HAL_PKA_ERROR_OPERATION;
+ }
+ break;
+ default :
+ break;
+ }
+ /* Trigger the error callback if an error is present */
+ if (hpka->ErrorCode != HAL_PKA_ERROR_NONE)
+ {
+#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
+ hpka->ErrorCallback(hpka);
+#else
+ HAL_PKA_ErrorCallback(hpka);
+#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
+ }
+
+ /* End Of Operation interrupt occurred */
+ if ((__HAL_PKA_GET_IT_SOURCE(hpka, PKA_IT_PROCEND) == SET) && (procEndFlag == SET))
+ {
+ /* Clear PROCEND flag */
+ __HAL_PKA_CLEAR_FLAG(hpka, PKA_FLAG_PROCEND);
+
+ /* Set the state to ready */
+ hpka->State = HAL_PKA_STATE_READY;
+
+#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
+ hpka->OperationCpltCallback(hpka);
+#else
+ HAL_PKA_OperationCpltCallback(hpka);
+#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief Process completed callback.
+ * @param hpka PKA handle
+ * @retval None
+ */
+__weak void HAL_PKA_OperationCpltCallback(PKA_HandleTypeDef *hpka)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpka);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PKA_OperationCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Error callback.
+ * @param hpka PKA handle
+ * @retval None
+ */
+__weak void HAL_PKA_ErrorCallback(PKA_HandleTypeDef *hpka)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpka);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PKA_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup PKA_Exported_Functions_Group3 Peripheral State and Error functions
+ * @brief Peripheral State and Error functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### Peripheral State and Error functions #####
+ ===============================================================================
+ [..]
+ This subsection permit to get in run-time the status of the peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the PKA handle state.
+ * @param hpka PKA handle
+ * @retval HAL status
+ */
+HAL_PKA_StateTypeDef HAL_PKA_GetState(PKA_HandleTypeDef *hpka)
+{
+ /* Return PKA handle state */
+ return hpka->State;
+}
+
+/**
+ * @brief Return the PKA error code.
+ * @param hpka PKA handle
+ * @retval PKA error code
+ */
+uint32_t HAL_PKA_GetError(PKA_HandleTypeDef *hpka)
+{
+ /* Return PKA handle error code */
+ return hpka->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup PKA_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Get PKA operating mode.
+ * @param hpka PKA handle
+ * @retval Return the current mode
+ */
+uint32_t PKA_GetMode(PKA_HandleTypeDef *hpka)
+{
+ /* return the shifted PKA_CR_MODE value */
+ return (uint32_t)(READ_BIT(hpka->Instance->CR, PKA_CR_MODE) >> PKA_CR_MODE_Pos);
+}
+
+/**
+ * @brief Wait for operation completion or timeout.
+ * @param hpka PKA handle
+ * @param Timeout Timeout duration in millisecond.
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef PKA_PollEndOfOperation(PKA_HandleTypeDef *hpka, uint32_t Timeout, uint32_t Tickstart)
+{
+ /* Wait for the end of operation or timeout */
+ while ((hpka->Instance->SR & PKA_SR_PROCENDF) == 0UL)
+ {
+ /* Check if timeout is disabled (set to infinite wait) */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0UL))
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Return a hal error code based on PKA error flags.
+ * @param hpka PKA handle
+ * @param mode PKA operating mode
+ * @retval error code
+ */
+uint32_t PKA_CheckError(PKA_HandleTypeDef *hpka, uint32_t mode)
+{
+ uint32_t err = HAL_PKA_ERROR_NONE;
+
+ /* Check RAMERR error */
+ if (__HAL_PKA_GET_FLAG(hpka, PKA_FLAG_RAMERR) == SET)
+ {
+ err |= HAL_PKA_ERROR_RAMERR;
+ }
+
+ /* Check ADDRERR error */
+ if (__HAL_PKA_GET_FLAG(hpka, PKA_FLAG_ADDRERR) == SET)
+ {
+ err |= HAL_PKA_ERROR_ADDRERR;
+ }
+
+ /* Check OPEERR error */
+ if (__HAL_PKA_GET_FLAG(hpka, PKA_FLAG_OPERR) == SET)
+ {
+ err |= HAL_PKA_ERROR_OPERATION;
+ }
+
+ /* Check the operation success in case of ECDSA signature */
+ if (mode == PKA_MODE_ECDSA_SIGNATURE)
+ {
+#define EDCSA_SIGN_NOERROR PKA_NO_ERROR
+ /* If error output result is different from no error, ecsa sign operation need to be repeated */
+ if (hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_ERROR] != EDCSA_SIGN_NOERROR)
+ {
+ err |= HAL_PKA_ERROR_OPERATION;
+ }
+ }
+
+ /* Check the operation success in case of ECC double base ladder*/
+ if (mode == PKA_MODE_DOUBLE_BASE_LADDER)
+ {
+ /* If error output result is different from no error, PKA operation need to be repeated */
+ if (hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_OUT_ERROR] != PKA_NO_ERROR)
+ {
+ err |= HAL_PKA_ERROR_OPERATION;
+ }
+ }
+
+ /* Check the operation success in case of ECC projective to affine*/
+ if (mode == PKA_MODE_ECC_PROJECTIVE_AFF)
+ {
+ /* If error output result is different from no error, PKA operation need to be repeated */
+ if (hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_OUT_ERROR] != PKA_NO_ERROR)
+ {
+ err |= HAL_PKA_ERROR_OPERATION;
+ }
+ }
+
+ /* Check the operation success in case of ECC Fp scalar multiplication*/
+ if (mode == PKA_MODE_ECC_MUL)
+ {
+ /* If error output result is different from no error, PKA operation need to be repeated */
+ if (hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_OUT_ERROR] != PKA_NO_ERROR)
+ {
+ err |= HAL_PKA_ERROR_OPERATION;
+ }
+ }
+
+ /* Check the operation success in case of protected modular exponentiation*/
+ if (mode == PKA_MODE_MODULAR_EXP_PROTECT)
+ {
+ /* If error output result is different from no error, PKA operation need to be repeated */
+ if (hpka->Instance->RAM[PKA_MODULAR_EXP_OUT_ERROR] != PKA_NO_ERROR)
+ {
+ err |= HAL_PKA_ERROR_OPERATION;
+ }
+ }
+
+ return err;
+}
+
+/**
+ * @brief Get number of bits inside an array of u8.
+ * @param byteNumber Number of u8 inside the array
+ */
+uint32_t PKA_GetBitSize_u8(uint32_t byteNumber)
+{
+ /* Convert from number of uint8_t in an array to the associated number of bits in this array */
+ return byteNumber * 8UL;
+}
+
+/**
+ * @brief Get optimal number of bits inside an array of u8.
+ * @param byteNumber Number of u8 inside the array
+ * @param msb Most significant uint8_t of the array
+ */
+uint32_t PKA_GetOptBitSize_u8(uint32_t byteNumber, uint8_t msb)
+{
+ uint32_t position;
+
+ position = 32UL - __CLZ(msb);
+
+ return (((byteNumber - 1UL) * 8UL) + position);
+}
+
+/**
+ * @brief Get number of bits inside an array of u32.
+ * @param wordNumber Number of u32 inside the array
+ */
+uint32_t PKA_GetBitSize_u32(uint32_t wordNumber)
+{
+ /* Convert from number of uint32_t in an array to the associated number of bits in this array */
+ return wordNumber * 32UL;
+}
+
+/**
+ * @brief Get number of uint8_t element in an array of bitSize bits.
+ * @param bitSize Number of bits in an array
+ */
+uint32_t PKA_GetArraySize_u8(uint32_t bitSize)
+{
+ /* Manage the non aligned on uint8_t bitsize: */
+ /* 512 bits requires 64 uint8_t */
+ /* 521 bits requires 66 uint8_t */
+ return ((bitSize + 7UL) / 8UL);
+}
+
+/**
+ * @brief Copy uint32_t array to uint8_t array to fit PKA number representation.
+ * @param dst Pointer to destination
+ * @param src Pointer to source
+ * @param n Number of uint8_t to copy
+ * @retval dst
+ */
+void PKA_Memcpy_u32_to_u8(uint8_t dst[], __IO const uint32_t src[], size_t n)
+{
+ if (dst != NULL)
+ {
+ if (src != NULL)
+ {
+ uint32_t index_uint32_t = 0UL; /* This index is used outside of the loop */
+
+ for (; index_uint32_t < (n / 4UL); index_uint32_t++)
+ {
+ /* Avoid casting from uint8_t* to uint32_t* by copying 4 uint8_t in a row */
+ /* Apply __REV equivalent */
+ uint32_t index_uint8_t = n - 4UL - (index_uint32_t * 4UL);
+ dst[index_uint8_t + 3UL] = (uint8_t)((src[index_uint32_t] & 0x000000FFU));
+ dst[index_uint8_t + 2UL] = (uint8_t)((src[index_uint32_t] & 0x0000FF00U) >> 8UL);
+ dst[index_uint8_t + 1UL] = (uint8_t)((src[index_uint32_t] & 0x00FF0000U) >> 16UL);
+ dst[index_uint8_t + 0UL] = (uint8_t)((src[index_uint32_t] & 0xFF000000U) >> 24UL);
+ }
+
+ /* Manage the buffers not aligned on uint32_t */
+ if ((n % 4UL) == 1UL)
+ {
+ dst[0UL] = (uint8_t)((src[index_uint32_t] & 0x000000FFU));
+ }
+ else if ((n % 4UL) == 2UL)
+ {
+ dst[1UL] = (uint8_t)((src[index_uint32_t] & 0x000000FFU));
+ dst[0UL] = (uint8_t)((src[index_uint32_t] & 0x0000FF00U) >> 8UL);
+ }
+ else if ((n % 4UL) == 3UL)
+ {
+ dst[2UL] = (uint8_t)((src[index_uint32_t] & 0x000000FFU));
+ dst[1UL] = (uint8_t)((src[index_uint32_t] & 0x0000FF00U) >> 8UL);
+ dst[0UL] = (uint8_t)((src[index_uint32_t] & 0x00FF0000U) >> 16UL);
+ }
+ else
+ {
+ /* The last element is already handle in the loop */
+ }
+ }
+ }
+}
+
+/**
+ * @brief Copy uint8_t array to uint32_t array to fit PKA number representation.
+ * @param dst Pointer to destination
+ * @param src Pointer to source
+ * @param n Number of uint8_t to copy (must be multiple of 4)
+ * @retval dst
+ */
+void PKA_Memcpy_u8_to_u32(__IO uint32_t dst[], const uint8_t src[], size_t n)
+{
+ if (dst != NULL)
+ {
+ if (src != NULL)
+ {
+ uint32_t index = 0UL; /* This index is used outside of the loop */
+
+ for (; index < (n / 4UL); index++)
+ {
+ /* Apply the equivalent of __REV from uint8_t to uint32_t */
+ dst[index] = ((uint32_t)src[(n - (index * 4UL) - 1UL)]) \
+ | ((uint32_t)src[(n - (index * 4UL) - 2UL)] << 8UL) \
+ | ((uint32_t)src[(n - (index * 4UL) - 3UL)] << 16UL) \
+ | ((uint32_t)src[(n - (index * 4UL) - 4UL)] << 24UL);
+ }
+
+ /* Manage the buffers not aligned on uint32_t */
+ if ((n % 4UL) == 1UL)
+ {
+ dst[index] = (uint32_t)src[(n - (index * 4UL) - 1UL)];
+ }
+ else if ((n % 4UL) == 2UL)
+ {
+ dst[index] = ((uint32_t)src[(n - (index * 4UL) - 1UL)]) \
+ | ((uint32_t)src[(n - (index * 4UL) - 2UL)] << 8UL);
+ }
+ else if ((n % 4UL) == 3UL)
+ {
+ dst[index] = ((uint32_t)src[(n - (index * 4UL) - 1UL)]) \
+ | ((uint32_t)src[(n - (index * 4UL) - 2UL)] << 8UL) \
+ | ((uint32_t)src[(n - (index * 4UL) - 3UL)] << 16UL);
+ }
+ else
+ {
+ /* The last element is already handle in the loop */
+ }
+ }
+ }
+}
+
+/**
+ * @brief Copy uint32_t array to uint32_t array.
+ * @param dst Pointer to destination
+ * @param src Pointer to source
+ * @param n Number of u32 to be handled
+ * @retval dst
+ */
+void PKA_Memcpy_u32_to_u32(__IO uint32_t dst[], __IO const uint32_t src[], size_t n)
+{
+ /* If a destination buffer is provided */
+ if (dst != NULL)
+ {
+ /* If a source buffer is provided */
+ if (src != NULL)
+ {
+ /* For each element in the array */
+ for (uint32_t index = 0UL; index < n; index++)
+ {
+ /* Copy the content */
+ dst[index] = src[index];
+ }
+ }
+ }
+}
+
+/**
+ * @brief Generic function to start a PKA operation in blocking mode.
+ * @param hpka PKA handle
+ * @param mode PKA operation
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef PKA_Process(PKA_HandleTypeDef *hpka, uint32_t mode, uint32_t Timeout)
+{
+ HAL_StatusTypeDef err = HAL_OK;
+ uint32_t tickstart;
+
+ if (hpka->State == HAL_PKA_STATE_READY)
+ {
+ /* Set the state to busy */
+ hpka->State = HAL_PKA_STATE_BUSY;
+
+ /* Clear any pending error */
+ hpka->ErrorCode = HAL_PKA_ERROR_NONE;
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ /* Set the mode and deactivate the interrupts */
+ MODIFY_REG(hpka->Instance->CR, PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE | PKA_CR_OPERRIE,
+ mode << PKA_CR_MODE_Pos);
+
+ /* Start the computation */
+ hpka->Instance->CR |= PKA_CR_START;
+
+ /* Wait for the end of operation or timeout */
+ if (PKA_PollEndOfOperation(hpka, Timeout, tickstart) != HAL_OK)
+ {
+ /* Abort any ongoing operation */
+ CLEAR_BIT(hpka->Instance->CR, PKA_CR_EN);
+
+ hpka->ErrorCode |= HAL_PKA_ERROR_TIMEOUT;
+
+ /* Make ready for the next operation */
+ SET_BIT(hpka->Instance->CR, PKA_CR_EN);
+ }
+
+ /* Check error */
+ hpka->ErrorCode |= PKA_CheckError(hpka, mode);
+
+ /* Clear all flags */
+ hpka->Instance->CLRFR |= (PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC);
+
+ /* Set the state to ready */
+ hpka->State = HAL_PKA_STATE_READY;
+
+ /* Manage the result based on encountered errors */
+ if (hpka->ErrorCode != HAL_PKA_ERROR_NONE)
+ {
+ err = HAL_ERROR;
+ }
+ }
+ else
+ {
+ err = HAL_ERROR;
+ }
+ return err;
+}
+
+/**
+ * @brief Generic function to start a PKA operation in non-blocking mode with Interrupt.
+ * @param hpka PKA handle
+ * @param mode PKA operation
+ * @retval HAL status
+ */
+HAL_StatusTypeDef PKA_Process_IT(PKA_HandleTypeDef *hpka, uint32_t mode)
+{
+ HAL_StatusTypeDef err = HAL_OK;
+
+ if (hpka->State == HAL_PKA_STATE_READY)
+ {
+ /* Set the state to busy */
+ hpka->State = HAL_PKA_STATE_BUSY;
+
+ /* Clear any pending error */
+ hpka->ErrorCode = HAL_PKA_ERROR_NONE;
+
+ /* Set the mode and activate interrupts */
+ MODIFY_REG(hpka->Instance->CR, PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE | PKA_CR_OPERRIE,
+ (mode << PKA_CR_MODE_Pos) | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE | PKA_CR_OPERRIE);
+
+ /* Start the computation */
+ hpka->Instance->CR |= PKA_CR_START;
+ }
+ else
+ {
+ err = HAL_ERROR;
+ }
+ return err;
+}
+
+/**
+ * @brief Set input parameters.
+ * @param hpka PKA handle
+ * @param in Input information
+ */
+void PKA_ModExp_Set(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in)
+{
+ /* Get the number of bit per operand */
+ hpka->Instance->RAM[PKA_MODULAR_EXP_IN_OP_NB_BITS] = PKA_GetBitSize_u8(in->OpSize);
+
+ /* Get the number of bit of the exponent */
+ hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXP_NB_BITS] = PKA_GetBitSize_u8(in->expSize);
+
+ /* Move the input parameters pOp1 to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT_BASE], in->pOp1, in->OpSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT_BASE + (in->OpSize / 4UL));
+
+ /* Move the exponent to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT], in->pExp, in->expSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT + (in->expSize / 4UL));
+
+ /* Move the modulus to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MODULUS], in->pMod, in->OpSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MODULUS + (in->OpSize / 4UL));
+}
+
+/**
+ * @brief Set input parameters.
+ * @param hpka PKA handle
+ * @param in Input information
+ */
+void PKA_ModExpFastMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in)
+{
+ /* Get the number of bit per operand */
+ hpka->Instance->RAM[PKA_MODULAR_EXP_IN_OP_NB_BITS] = PKA_GetBitSize_u8(in->OpSize);
+
+ /* Get the number of bit of the exponent */
+ hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXP_NB_BITS] = PKA_GetBitSize_u8(in->expSize);
+
+ /* Move the input parameters pOp1 to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT_BASE], in->pOp1, in->OpSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT_BASE + (in->OpSize / 4UL));
+
+ /* Move the exponent to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT], in->pExp, in->expSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT + (in->expSize / 4UL));
+
+ /* Move the modulus to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MODULUS], in->pMod, in->OpSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MODULUS + (in->OpSize / 4UL));
+
+ /* Move the Montgomery parameter to PKA RAM */
+ PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM], in->pMontgomeryParam,
+ in->OpSize / 4UL);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM + (in->OpSize / 4UL));
+}
+
+/**
+ * @brief Set input parameters.
+ * @param hpka PKA handle
+ * @param in Input information
+ */
+void PKA_ModExpProtectMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpProtectModeInTypeDef *in)
+{
+ /* Get the number of bit per operand */
+ hpka->Instance->RAM[PKA_MODULAR_EXP_IN_OP_NB_BITS] = PKA_GetBitSize_u8(in->OpSize);
+
+ /* Get the number of bit of the exponent */
+ hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXP_NB_BITS] = PKA_GetBitSize_u8(in->expSize);
+
+ /* Move the input parameters pOp1 to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE], in->pOp1, in->OpSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE + (in->OpSize / 4UL));
+
+ /* Move the exponent to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT], in->pExp, in->expSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT + (in->expSize / 4UL));
+
+ /* Move the modulus to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_PROTECT_IN_MODULUS], in->pMod, in->OpSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_PROTECT_IN_MODULUS + (in->OpSize / 4UL));
+
+ /* Move Phi value to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_PROTECT_IN_PHI], in->pPhi, in->OpSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_PROTECT_IN_PHI + (in->OpSize / 4UL));
+}
+
+/**
+ * @brief Set input parameters.
+ * @param hpka PKA handle
+ * @param in Input information
+ */
+void PKA_ECDSASign_Set(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in)
+{
+ /* Get the prime order n length */
+ hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_ORDER_NB_BITS] = PKA_GetOptBitSize_u8(in->primeOrderSize, *(in->primeOrder));
+
+ /* Get the modulus p length */
+ hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_MOD_NB_BITS] = PKA_GetOptBitSize_u8(in->modulusSize, *(in->modulus));
+
+ /* Get the coefficient a sign */
+ hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_A_COEFF_SIGN] = in->coefSign;
+
+ /* Move the input parameters coefficient |a| to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_A_COEFF], in->coef, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL));
+
+ /* Move the input parameters coefficient B to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_B_COEFF], in->coefB, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_B_COEFF + ((in->modulusSize + 3UL) / 4UL));
+
+ /* Move the input parameters modulus value p to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_MOD_GF], in->modulus, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL));
+
+ /* Move the input parameters integer k to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_K], in->integer, in->primeOrderSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_K + ((in->primeOrderSize + 3UL) / 4UL));
+
+ /* Move the input parameters base point G coordinate x to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_INITIAL_POINT_X], in->basePointX, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL));
+
+ /* Move the input parameters base point G coordinate y to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y], in->basePointY, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL));
+
+ /* Move the input parameters hash of message z to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_HASH_E], in->hash, in->primeOrderSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_HASH_E + ((in->primeOrderSize + 3UL) / 4UL));
+
+ /* Move the input parameters private key d to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D], in->privateKey, in->primeOrderSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + ((in->primeOrderSize + 3UL) / 4UL));
+
+ /* Move the input parameters prime order n to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_ORDER_N], in->primeOrder, in->primeOrderSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_ORDER_N + ((in->primeOrderSize + 3UL) / 4UL));
+}
+
+/**
+ * @brief Set input parameters.
+ * @param hpka PKA handle
+ * @param in Input information
+ */
+void PKA_ECDSAVerif_Set(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in)
+{
+ /* Get the prime order n length */
+ hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_ORDER_NB_BITS] = PKA_GetOptBitSize_u8(in->primeOrderSize, *(in->primeOrder));
+
+ /* Get the modulus p length */
+ hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_MOD_NB_BITS] = PKA_GetOptBitSize_u8(in->modulusSize, *(in->modulus));
+
+ /* Get the coefficient a sign */
+ hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_A_COEFF_SIGN] = in->coefSign;
+
+ /* Move the input parameters coefficient |a| to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_A_COEFF], in->coef, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL));
+
+ /* Move the input parameters modulus value p to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_MOD_GF], in->modulus, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL));
+
+ /* Move the input parameters base point G coordinate x to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_INITIAL_POINT_X], in->basePointX, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL));
+
+ /* Move the input parameters base point G coordinate y to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y], in->basePointY, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL));
+
+ /* Move the input parameters public-key curve point Q coordinate xQ to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X], in->pPubKeyCurvePtX,
+ in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X + ((in->modulusSize + 3UL) / 4UL));
+
+ /* Move the input parameters public-key curve point Q coordinate xQ to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y], in->pPubKeyCurvePtY,
+ in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y + ((in->modulusSize + 3UL) / 4UL));
+
+ /* Move the input parameters signature part r to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_SIGNATURE_R], in->RSign, in->primeOrderSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_SIGNATURE_R + ((in->primeOrderSize + 3UL) / 4UL));
+
+ /* Move the input parameters signature part s to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_SIGNATURE_S], in->SSign, in->primeOrderSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_SIGNATURE_S + ((in->primeOrderSize + 3UL) / 4UL));
+
+ /* Move the input parameters hash of message z to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_HASH_E], in->hash, in->primeOrderSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_HASH_E + ((in->primeOrderSize + 3UL) / 4UL));
+
+ /* Move the input parameters curve prime order n to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_ORDER_N], in->primeOrder, in->primeOrderSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_ORDER_N + ((in->primeOrderSize + 3UL) / 4UL));
+}
+
+/**
+ * @brief Set input parameters.
+ * @param hpka PKA handle
+ * @param in Input information
+ */
+void PKA_RSACRTExp_Set(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in)
+{
+ /* Get the operand length M */
+ hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_MOD_NB_BITS] = PKA_GetBitSize_u8(in->size);
+
+ /* Move the input parameters operand dP to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_DP_CRT], in->pOpDp, in->size / 2UL);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_RSA_CRT_EXP_IN_DP_CRT + (in->size / 8UL));
+
+ /* Move the input parameters operand dQ to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_DQ_CRT], in->pOpDq, in->size / 2UL);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_RSA_CRT_EXP_IN_DQ_CRT + (in->size / 8UL));
+
+ /* Move the input parameters operand qinv to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_QINV_CRT], in->pOpQinv, in->size / 2UL);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_RSA_CRT_EXP_IN_QINV_CRT + (in->size / 8UL));
+
+ /* Move the input parameters prime p to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_PRIME_P], in->pPrimeP, in->size / 2UL);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_RSA_CRT_EXP_IN_PRIME_P + (in->size / 8UL));
+
+ /* Move the input parameters prime q to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_PRIME_Q], in->pPrimeQ, in->size / 2UL);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_RSA_CRT_EXP_IN_PRIME_Q + (in->size / 8UL));
+
+ /* Move the input parameters operand A to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_EXPONENT_BASE], in->popA, in->size);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_RSA_CRT_EXP_IN_EXPONENT_BASE + (in->size / 4UL));
+}
+
+/**
+ * @brief Set input parameters.
+ * @param hpka PKA handle
+ * @param in Input information
+ */
+void PKA_PointCheck_Set(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in)
+{
+ /* Get the modulus length */
+ hpka->Instance->RAM[PKA_POINT_CHECK_IN_MOD_NB_BITS] = PKA_GetOptBitSize_u8(in->modulusSize, *(in->modulus));
+
+ /* Get the coefficient a sign */
+ hpka->Instance->RAM[PKA_POINT_CHECK_IN_A_COEFF_SIGN] = in->coefSign;
+
+ /* Move the input parameters coefficient |a| to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_A_COEFF], in->coefA, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL));
+
+ /* Move the input parameters coefficient b to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_B_COEFF], in->coefB, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_B_COEFF + ((in->modulusSize + 3UL) / 4UL));
+
+ /* Move the input parameters modulus value p to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_MOD_GF], in->modulus, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL));
+
+ /* Move the input parameters Point P coordinate x to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_X], in->pointX, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL));
+
+ /* Move the input parameters Point P coordinate y to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_Y], in->pointY, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL));
+
+ /* Move the input parameters montgomery param R2 modulus N to PKA RAM */
+ PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_MONTGOMERY_PARAM], in->pMontgomeryParam,
+ (in->modulusSize / 4UL));
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_MONTGOMERY_PARAM + ((in->modulusSize + 3UL) / 4UL));
+}
+
+/**
+ * @brief Set input parameters.
+ * @param hpka PKA handle
+ * @param in Input information
+ */
+void PKA_ECCMul_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in)
+{
+ /* Get the prime order n length */
+ hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS] = PKA_GetOptBitSize_u8(in->scalarMulSize, *(in->primeOrder));
+
+ /* Get the modulus length */
+ hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS] = PKA_GetOptBitSize_u8(in->modulusSize, *(in->modulus));
+
+ /* Get the coefficient a sign */
+ hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN] = in->coefSign;
+
+ /* Move the input parameters coefficient |a| to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF], in->coefA, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL));
+
+ /* Move the input parameters coefficient b to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_B_COEFF], in->coefB, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_B_COEFF + (in->modulusSize / 4UL));
+
+ /* Move the input parameters modulus value p to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_MOD_GF], in->modulus, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL));
+
+ /* Move the input parameters scalar multiplier k to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_K], in->scalarMul, in->scalarMulSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_K + ((in->scalarMulSize + 3UL) / 4UL));
+
+ /* Move the input parameters Point P coordinate x to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X], in->pointX, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL));
+
+ /* Move the input parameters Point P coordinate y to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y], in->pointY, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL));
+
+ /* Move the input parameters curve prime order N to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER], in->primeOrder, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER + (in->modulusSize / 4UL));
+}
+
+
+/**
+ * @brief Set input parameters.
+ * @param hpka PKA handle
+ * @param in Input information
+ */
+void PKA_ModInv_Set(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in)
+{
+ /* Get the number of bit per operand */
+ hpka->Instance->RAM[PKA_MODULAR_INV_NB_BITS] = PKA_GetBitSize_u32(in->size);
+
+ /* Move the input parameters operand A to PKA RAM */
+ PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_MODULAR_INV_IN_OP1], in->pOp1, in->size);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_INV_IN_OP1 + in->size);
+
+ /* Move the input parameters modulus value n to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_INV_IN_OP2_MOD], in->pMod, in->size * 4UL);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_INV_IN_OP2_MOD + in->size);
+}
+
+/**
+ * @brief Set input parameters.
+ * @param hpka PKA handle
+ * @param in Input information
+ */
+void PKA_ModRed_Set(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in)
+{
+ /* Get the number of bit per operand */
+ hpka->Instance->RAM[PKA_MODULAR_REDUC_IN_OP_LENGTH] = PKA_GetBitSize_u32(in->OpSize);
+
+ /* Get the number of bit per modulus */
+ hpka->Instance->RAM[PKA_MODULAR_REDUC_IN_MOD_LENGTH] = PKA_GetBitSize_u8(in->modSize);
+
+ /* Move the input parameters operand A to PKA RAM */
+ PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_MODULAR_REDUC_IN_OPERAND], in->pOp1, in->OpSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_REDUC_IN_OPERAND + in->OpSize);
+
+ /* Move the input parameters modulus value n to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_REDUC_IN_MODULUS], in->pMod, in->modSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_REDUC_IN_MODULUS + (in->modSize / 4UL));
+}
+
+/**
+ * @brief Set input parameters.
+ * @param hpka PKA handle
+ * @param size Size of the operand
+ * @param pOp1 Generic pointer to input data
+ */
+void PKA_MontgomeryParam_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint8_t *pOp1)
+{
+ uint32_t bytetoskip = 0UL;
+ uint32_t newSize;
+
+ if (pOp1 != NULL)
+ {
+ /* Count the number of zero bytes */
+ while ((bytetoskip < size) && (pOp1[bytetoskip] == 0UL))
+ {
+ bytetoskip++;
+ }
+
+ /* Get new size after skipping zero bytes */
+ newSize = size - bytetoskip;
+
+ /* Get the number of bit per operand */
+ hpka->Instance->RAM[PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS] = PKA_GetOptBitSize_u8(newSize, pOp1[bytetoskip]);
+
+ /* Move the input parameters pOp1 to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MONTGOMERY_PARAM_IN_MODULUS], pOp1, size);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MONTGOMERY_PARAM_IN_MODULUS + ((size + 3UL) / 4UL));
+ }
+}
+
+/**
+ * @brief Set input parameters.
+ * @param hpka PKA handle
+ * @param in Input information
+ */
+void PKA_ECCDoubleBaseLadder_Set(PKA_HandleTypeDef *hpka, PKA_ECCDoubleBaseLadderInTypeDef *in)
+{
+ /* Get the prime order n length */
+ hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS] = PKA_GetBitSize_u8(in->primeOrderSize);
+
+ /* Get the modulus p length */
+ hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS] = PKA_GetBitSize_u8(in->modulusSize);
+
+ /* Get the coefficient a sign */
+ hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN] = in->coefSign;
+
+ /* Move the input parameters coefficient |a| to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_A_COEFF], in->coefA, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_A_COEFF + (in->modulusSize / 4UL));
+
+ /* Move the input parameters modulus value p to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_MOD_P], in->modulus, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_MOD_P + (in->modulusSize / 4UL));
+
+ /* Move the input parameters integer k to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER], in->integerK, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER + (in->modulusSize / 4UL));
+
+ /* Move the input parameters integer m to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER], in->integerM, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER + (in->modulusSize / 4UL));
+
+ /* Move the input parameters first point coordinate x to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_POINT1_X], in->basePointX1, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_POINT1_X + (in->modulusSize / 4UL));
+
+ /* Move the input parameters first point coordinate y to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y], in->basePointY1, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y + (in->modulusSize / 4UL));
+
+ /* Move the input parameters first point coordinate z to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z], in->basePointZ1, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z + (in->modulusSize / 4UL));
+
+ /* Move the input parameters second point coordinate x to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_POINT2_X], in->basePointX2, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_POINT2_X + (in->modulusSize / 4UL));
+
+ /* Move the input parameters second point coordinate y to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y], in->basePointY2, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y + (in->modulusSize / 4UL));
+
+ /* Move the input parameters second point coordinate z to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z], in->basePointZ2, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z + (in->modulusSize / 4UL));
+}
+
+/**
+ * @brief Retrieve operation result.
+ * @param hpka PKA handle
+ * @param out Output information
+ * @retval HAL status
+ */
+void HAL_PKA_ECCDoubleBaseLadder_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCDoubleBaseLadderOutTypeDef *out)
+{
+ uint32_t size;
+
+ /* Move the result to appropriate location (indicated in out parameter) */
+ size = hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS] / 8UL;
+ if (out != NULL)
+ {
+ PKA_Memcpy_u32_to_u8(out->ptX, &hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X], size);
+ PKA_Memcpy_u32_to_u8(out->ptY, &hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y], size);
+ }
+}
+
+/**
+ * @brief Set input parameters.
+ * @param hpka PKA handle
+ * @param in Input information
+ */
+void PKA_ECCProjective2Affine_Set(PKA_HandleTypeDef *hpka, PKA_ECCProjective2AffineInTypeDef *in)
+{
+ /* Get the modulus p length */
+ hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS] = PKA_GetBitSize_u8(in->modulusSize);
+
+ /* Move the input parameters modulus value p to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_IN_MOD_P], in->modulus, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_PROJECTIVE_AFF_IN_MOD_P + (in->modulusSize / 4UL));
+
+ /* Move the input parameters point coordinate x to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_IN_POINT_X], in->basePointX, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_PROJECTIVE_AFF_IN_POINT_X + (in->modulusSize / 4UL));
+
+ /* Move the input parameters point coordinate y to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y], in->basePointY, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y + (in->modulusSize / 4UL));
+
+ /* Move the input parameters point coordinate z to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z], in->basePointZ, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z + (in->modulusSize / 4UL));
+
+ /* Move the input parameters montgomery parameter R2 modulus n to PKA RAM */
+ PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2], in->pMontgomeryParam,
+ (in->modulusSize / 4UL));
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 + (in->modulusSize / 4UL));
+}
+
+/**
+ * @brief Retrieve operation result.
+ * @param hpka PKA handle
+ * @param out Output information
+ * @retval HAL status
+ */
+void HAL_PKA_ECCProjective2Affine_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCProjective2AffineOutTypeDef *out)
+{
+ uint32_t size;
+
+ /* Move the result to appropriate location (indicated in out parameter) */
+ size = hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS] / 8UL;
+ if (out != NULL)
+ {
+ PKA_Memcpy_u32_to_u8(out->ptX, &hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X], size);
+ PKA_Memcpy_u32_to_u8(out->ptY, &hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y], size);
+ }
+}
+
+/**
+ * @brief Set input parameters.
+ * @param hpka PKA handle
+ * @param in Input information
+ */
+void PKA_ECCCompleteAddition_Set(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditionInTypeDef *in)
+{
+ /* Get the modulus p length */
+ hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS] = PKA_GetBitSize_u8(in->modulusSize);
+
+ /* Get the coefficient a sign */
+ hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN] = in->coefSign;
+
+ /* Move the input parameters modulus value p to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_MOD_P], in->modulus, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_COMPLETE_ADD_IN_MOD_P + (in->modulusSize / 4UL));
+
+ /* Move the input parameters coefA value to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_A_COEFF], in->coefA, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_COMPLETE_ADD_IN_A_COEFF + (in->modulusSize / 4UL));
+
+ /* Move the input parameters first point x value to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_POINT1_X], in->basePointX1, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_COMPLETE_ADD_IN_POINT1_X + (in->modulusSize / 4UL));
+
+ /* Move the input parameters first point y value to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_POINT1_Y], in->basePointY1, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_COMPLETE_ADD_IN_POINT1_Y + (in->modulusSize / 4UL));
+
+ /* Move the input parameters first point z value to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_POINT1_Z], in->basePointZ1, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_COMPLETE_ADD_IN_POINT1_Z + (in->modulusSize / 4UL));
+
+ /* Move the input parameters second point x value to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_POINT2_X], in->basePointX2, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_COMPLETE_ADD_IN_POINT2_X + (in->modulusSize / 4UL));
+
+ /* Move the input parameters second point y value to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_POINT2_Y], in->basePointY2, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_COMPLETE_ADD_IN_POINT2_Y + (in->modulusSize / 4UL));
+
+ /* Move the input parameters second point z value to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_POINT2_Z], in->basePointZ2, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_COMPLETE_ADD_IN_POINT2_Z + (in->modulusSize / 4UL));
+}
+
+/**
+ * @brief Retrieve operation result.
+ * @param hpka PKA handle
+ * @param out Output information
+ * @retval HAL status
+ */
+void HAL_PKA_ECCCompleteAddition_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditionOutTypeDef *out)
+{
+ uint32_t size;
+
+ /* Move the result to appropriate location (indicated in out parameter) */
+ size = (hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS] + 7UL) / 8UL;
+ if (out != NULL)
+ {
+ PKA_Memcpy_u32_to_u8(out->ptX, &hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_OUT_RESULT_X], size);
+ PKA_Memcpy_u32_to_u8(out->ptY, &hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y], size);
+ PKA_Memcpy_u32_to_u8(out->ptZ, &hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z], size);
+ }
+}
+/**
+ * @brief Generic function to set input parameters.
+ * @param hpka PKA handle
+ * @param size Size of the operand
+ * @param pOp1 Generic pointer to input data
+ * @param pOp2 Generic pointer to input data
+ * @param pOp3 Generic pointer to input data
+ */
+void PKA_ARI_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint32_t *pOp1, const uint32_t *pOp2,
+ const uint8_t *pOp3)
+{
+ /* Get the number of bit per operand */
+ hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_NB_BITS] = PKA_GetBitSize_u32(size);
+
+ if (pOp1 != NULL)
+ {
+ /* Move the input parameters pOp1 to PKA RAM */
+ PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_IN_OP1], pOp1, size);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ARITHMETIC_ALL_OPS_IN_OP1 + size);
+ }
+
+ if (pOp2 != NULL)
+ {
+ /* Move the input parameters pOp2 to PKA RAM */
+ PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_IN_OP2], pOp2, size);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ARITHMETIC_ALL_OPS_IN_OP2 + size);
+ }
+
+ if (pOp3 != NULL)
+ {
+ /* Move the input parameters pOp3 to PKA RAM */
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_IN_OP3], pOp3, size * 4UL);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ARITHMETIC_ALL_OPS_IN_OP3 + size);
+ }
+}
+/**
+ * @brief Handle PKA init Timeout.
+ * @param hpka PKA handle.
+ * @param Flag Specifies the PKA flag to check
+ * @param Status Flag status (SET or RESET)
+ * @param Tickstart Tick start value
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef PKA_WaitOnFlagUntilTimeout(PKA_HandleTypeDef *hpka, uint32_t Flag, FlagStatus Status,
+ uint32_t Tickstart, uint32_t Timeout)
+{
+ /* Wait until flag is set */
+ while (__HAL_PKA_GET_FLAG(hpka, Flag) == Status)
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+ {
+ /* Set the state to ready */
+ hpka->State = HAL_PKA_STATE_READY;
+
+ /* Set the error code to timeout error */
+ hpka->ErrorCode = HAL_PKA_ERROR_TIMEOUT;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Get the size of output result.
+ * @param hpka PKA handle
+ * @param Startindex Specifies the start index of the result in the PKA RAM
+ * @param Maxsize Specifies the possible max size of the result in words
+ * @retval size
+ */
+uint32_t PKA_Result_GetSize(PKA_HandleTypeDef *hpka, uint32_t Startindex, uint32_t Maxsize)
+{
+ uint32_t size;
+ uint32_t current_index = Maxsize - 1UL;
+
+ /* Determinate the last index of the result in the PKA RAM */
+ while ((hpka->Instance->RAM[Startindex + current_index] == 0UL) && (current_index != 0UL))
+ {
+ current_index--;
+ }
+ /* Get the size in bytes */
+ size = (current_index + 1UL) * 4UL;
+
+ return size;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(PKA) && defined(HAL_PKA_MODULE_ENABLED) */
+
+/**
+ * @}
+ */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pssi.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pssi.c
new file mode 100644
index 00000000..45282b8d
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pssi.c
@@ -0,0 +1,1850 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_pssi.c
+ * @author MCD Application Team
+ * @brief PSSI HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Parallel Synchronous Slave Interface (PSSI) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State and Errors functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The PSSI HAL driver can be used as follows:
+
+ (#) Declare a PSSI_HandleTypeDef handle structure, for example:
+ PSSI_HandleTypeDef hpssi;
+
+ (#) Initialize the PSSI low level resources by implementing the @ref HAL_PSSI_MspInit() API:
+ (##) Enable the PSSIx interface clock
+ (##) PSSI pins configuration
+ (+++) Enable the clock for the PSSI GPIOs
+ (+++) Configure PSSI pins as alternate function open-drain
+ (##) NVIC configuration if you need to use interrupt process
+ (+++) Configure the PSSIx interrupt priority
+ (+++) Enable the NVIC PSSI IRQ Channel
+ (##) DMA Configuration if you need to use DMA process
+ (+++) Declare DMA_HandleTypeDef handles structure for the transmit and receive
+ (+++) Enable the DMAx interface clock
+ (+++) Configure the DMA handle parameters
+ (+++) Configure the DMA Tx and Rx
+ (+++) Associate the initialized DMA handle to the hpssi DMA Tx and Rx handle
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
+ the DMA Tx and Rx
+
+ (#) Configure the Communication Bus Width, Control Signals, Input Polarity and Output Polarity
+ in the hpssi Init structure.
+
+ (#) Initialize the PSSI registers by calling the @ref HAL_PSSI_Init(), configure also the low level Hardware
+ (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_PSSI_MspInit(&hpssi) API.
+
+
+ (#) For PSSI IO operations, two operation modes are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Transmit an amount of data by byte in blocking mode using @ref HAL_PSSI_Transmit()
+ (+) Receive an amount of data by byte in blocking mode using @ref HAL_PSSI_Receive()
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Transmit an amount of data in non-blocking mode (DMA) using
+ @ref HAL_PSSI_Transmit_DMA()
+ (+) At transmission end of transfer, @ref HAL_PSSI_TxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_PSSI_TxCpltCallback()
+ (+) Receive an amount of data in non-blocking mode (DMA) using
+ @ref HAL_PSSI_Receive_DMA()
+ (+) At reception end of transfer, @ref HAL_PSSI_RxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_PSSI_RxCpltCallback()
+ (+) In case of transfer Error, @ref HAL_PSSI_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer @ref HAL_PSSI_ErrorCallback()
+ (+) Abort a PSSI process communication with Interrupt using @ref HAL_PSSI_Abort_IT()
+ (+) End of abort process, @ref HAL_PSSI_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_PSSI_AbortCpltCallback()
+
+ *** PSSI HAL driver macros list ***
+ ==================================
+ [..]
+ Below the list of most used macros in PSSI HAL driver.
+
+ (+) @ref HAL_PSSI_ENABLE : Enable the PSSI peripheral
+ (+) @ref HAL_PSSI_DISABLE : Disable the PSSI peripheral
+ (+) @ref HAL_PSSI_GET_FLAG : Check whether the specified PSSI flag is set or not
+ (+) @ref HAL_PSSI_CLEAR_FLAG : Clear the specified PSSI pending flag
+ (+) @ref HAL_PSSI_ENABLE_IT : Enable the specified PSSI interrupt
+ (+) @ref HAL_PSSI_DISABLE_IT : Disable the specified PSSI interrupt
+
+ *** Callback registration ***
+ =============================================
+ Use Functions @ref HAL_PSSI_RegisterCallback() or @ref HAL_PSSI_RegisterAddrCallback()
+ to register an interrupt callback.
+
+ Function @ref HAL_PSSI_RegisterCallback() allows to register following callbacks:
+ (+) TxCpltCallback : callback for transmission end of transfer.
+ (+) RxCpltCallback : callback for reception end of transfer.
+ (+) ErrorCallback : callback for error detection.
+ (+) AbortCpltCallback : callback for abort completion process.
+ (+) MspInitCallback : callback for Msp Init.
+ (+) MspDeInitCallback : callback for Msp DeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+
+ Use function @ref HAL_PSSI_UnRegisterCallback to reset a callback to the default
+ weak function.
+ @ref HAL_PSSI_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TxCpltCallback : callback for transmission end of transfer.
+ (+) RxCpltCallback : callback for reception end of transfer.
+ (+) ErrorCallback : callback for error detection.
+ (+) AbortCpltCallback : callback for abort completion process.
+ (+) MspInitCallback : callback for Msp Init.
+ (+) MspDeInitCallback : callback for Msp DeInit.
+
+
+ By default, after the @ref HAL_PSSI_Init() and when the state is @ref HAL_PSSI_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples @ref HAL_PSSI_TxCpltCallback(), @ref HAL_PSSI_RxCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak functions in the @ref HAL_PSSI_Init()/ @ref HAL_PSSI_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ If MspInit or MspDeInit are not null, the @ref HAL_PSSI_Init()/ @ref HAL_PSSI_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+
+ Callbacks can be registered/unregistered in @ref HAL_PSSI_STATE_READY state only.
+ Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ in @ref HAL_PSSI_STATE_READY or @ref HAL_PSSI_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ Then, the user first registers the MspInit/MspDeInit user callbacks
+ using @ref HAL_PSSI_RegisterCallback() before calling @ref HAL_PSSI_DeInit()
+ or @ref HAL_PSSI_Init() function.
+
+
+ [..]
+ (@) You can refer to the PSSI HAL driver header file for more useful macros
+
+ @endverbatim
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup PSSI PSSI
+ * @brief PSSI HAL module driver
+ * @{
+ */
+
+#ifdef HAL_PSSI_MODULE_ENABLED
+#if defined(PSSI)
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup PSSI_Private_Define PSSI Private Define
+ * @{
+ */
+
+
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/** @defgroup PSSI_Private_Functions PSSI Private Functions
+ * @{
+ */
+/* Private functions to handle DMA transfer */
+void PSSI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+void PSSI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+void PSSI_DMAError(DMA_HandleTypeDef *hdma);
+void PSSI_DMAAbort(DMA_HandleTypeDef *hdma);
+
+
+/* Private functions to handle IT transfer */
+static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode);
+
+
+/* Private functions for PSSI transfer IRQ handler */
+
+
+/* Private functions to handle flags during polling transfer */
+static HAL_StatusTypeDef PSSI_WaitOnStatusUntilTimeout(PSSI_HandleTypeDef *hpssi, uint32_t Flag, FlagStatus Status,
+ uint32_t Timeout, uint32_t Tickstart);
+
+/* Private functions to centralize the enable/disable of Interrupts */
+
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup PSSI_Exported_Functions PSSI Exported Functions
+ * @{
+ */
+
+/** @defgroup PSSI_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ deinitialize the PSSIx peripheral:
+
+ (+) User must implement HAL_PSSI_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+ (+) Call the function HAL_PSSI_Init() to configure the selected device with
+ the selected configuration:
+ (++) Data Width
+ (++) Control Signals
+ (++) Input Clock polarity
+ (++) Output Clock polarity
+
+ (+) Call the function HAL_PSSI_DeInit() to restore the default configuration
+ of the selected PSSIx peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the PSSI according to the specified parameters
+ * in the PSSI_InitTypeDef and initialize the associated handle.
+ * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
+ * the configuration information for the specified PSSI.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PSSI_Init(PSSI_HandleTypeDef *hpssi)
+{
+ /* Check the PSSI handle allocation */
+ if (hpssi == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_PSSI_ALL_INSTANCE(hpssi->Instance));
+ assert_param(IS_PSSI_CONTROL_SIGNAL(hpssi->Init.ControlSignal));
+ assert_param(IS_PSSI_BUSWIDTH(hpssi->Init.BusWidth));
+ assert_param(IS_PSSI_CLOCK_POLARITY(hpssi->Init.ClockPolarity));
+ assert_param(IS_PSSI_DE_POLARITY(hpssi->Init.DataEnablePolarity));
+ assert_param(IS_PSSI_RDY_POLARITY(hpssi->Init.ReadyPolarity));
+
+ if (hpssi->State == HAL_PSSI_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hpssi->Lock = HAL_UNLOCKED;
+
+ /* Init the PSSI Callback settings */
+ hpssi->TxCpltCallback = HAL_PSSI_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ hpssi->RxCpltCallback = HAL_PSSI_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hpssi->ErrorCallback = HAL_PSSI_ErrorCallback; /* Legacy weak ErrorCallback */
+ hpssi->AbortCpltCallback = HAL_PSSI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+
+ if (hpssi->MspInitCallback == NULL)
+ {
+ hpssi->MspInitCallback = HAL_PSSI_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ hpssi->MspInitCallback(hpssi);
+
+ }
+
+ hpssi->State = HAL_PSSI_STATE_BUSY;
+
+ /* Disable the selected PSSI peripheral */
+ HAL_PSSI_DISABLE(hpssi);
+
+ /*---------------------------- PSSIx CR Configuration ----------------------*/
+ /* Configure PSSIx: Control Signal and Bus Width*/
+
+ MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DERDYCFG | PSSI_CR_EDM | PSSI_CR_DEPOL | PSSI_CR_RDYPOL,
+ hpssi->Init.ControlSignal | hpssi->Init.DataEnablePolarity |
+ hpssi->Init.ReadyPolarity | hpssi->Init.BusWidth);
+
+ hpssi->ErrorCode = HAL_PSSI_ERROR_NONE;
+ hpssi->State = HAL_PSSI_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitialize the PSSI peripheral.
+ * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
+ * the configuration information for the specified PSSI.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PSSI_DeInit(PSSI_HandleTypeDef *hpssi)
+{
+ /* Check the PSSI handle allocation */
+ if (hpssi == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_PSSI_ALL_INSTANCE(hpssi->Instance));
+
+ hpssi->State = HAL_PSSI_STATE_BUSY;
+
+ /* Disable the PSSI Peripheral Clock */
+ HAL_PSSI_DISABLE(hpssi);
+
+ if (hpssi->MspDeInitCallback == NULL)
+ {
+ hpssi->MspDeInitCallback = HAL_PSSI_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ hpssi->MspDeInitCallback(hpssi);
+
+ hpssi->ErrorCode = HAL_PSSI_ERROR_NONE;
+ hpssi->State = HAL_PSSI_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpssi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the PSSI MSP.
+ * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
+ * the configuration information for the specified PSSI.
+ * @retval None
+ */
+__weak void HAL_PSSI_MspInit(PSSI_HandleTypeDef *hpssi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpssi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PSSI_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the PSSI MSP.
+ * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
+ * the configuration information for the specified PSSI.
+ * @retval None
+ */
+__weak void HAL_PSSI_MspDeInit(PSSI_HandleTypeDef *hpssi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpssi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PSSI_MspDeInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Register a User PSSI Callback
+ * To be used instead of the weak predefined callback
+ * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
+ * the configuration information for the specified PSSI.
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_PSSI_TX_COMPLETE_CB_ID Tx Transfer completed callback ID
+ * @arg @ref HAL_PSSI_RX_COMPLETE_CB_ID Rx Transfer completed callback ID
+ * @arg @ref HAL_PSSI_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_PSSI_ABORT_CB_ID Abort callback ID
+ * @arg @ref HAL_PSSI_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_PSSI_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PSSI_RegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID,
+ pPSSI_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hpssi);
+
+ if (HAL_PSSI_STATE_READY == hpssi->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_PSSI_TX_COMPLETE_CB_ID :
+ hpssi->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_PSSI_RX_COMPLETE_CB_ID :
+ hpssi->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_PSSI_ERROR_CB_ID :
+ hpssi->ErrorCallback = pCallback;
+ break;
+
+ case HAL_PSSI_ABORT_CB_ID :
+ hpssi->AbortCpltCallback = pCallback;
+ break;
+
+ case HAL_PSSI_MSPINIT_CB_ID :
+ hpssi->MspInitCallback = pCallback;
+ break;
+
+ case HAL_PSSI_MSPDEINIT_CB_ID :
+ hpssi->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_PSSI_STATE_RESET == hpssi->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_PSSI_MSPINIT_CB_ID :
+ hpssi->MspInitCallback = pCallback;
+ break;
+
+ case HAL_PSSI_MSPDEINIT_CB_ID :
+ hpssi->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpssi);
+ return status;
+}
+
+/**
+ * @brief Unregister an PSSI Callback
+ * PSSI callback is redirected to the weak predefined callback
+ * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
+ * the configuration information for the specified PSSI.
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_PSSI_TX_COMPLETE_CB_ID Tx Transfer completed callback ID
+ * @arg @ref HAL_PSSI_RX_COMPLETE_CB_ID Rx Transfer completed callback ID
+ * @arg @ref HAL_PSSI_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_PSSI_ABORT_CB_ID Abort callback ID
+ * @arg @ref HAL_PSSI_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_PSSI_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hpssi);
+
+ if (HAL_PSSI_STATE_READY == hpssi->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_PSSI_TX_COMPLETE_CB_ID :
+ hpssi->TxCpltCallback = HAL_PSSI_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ break;
+
+ case HAL_PSSI_RX_COMPLETE_CB_ID :
+ hpssi->RxCpltCallback = HAL_PSSI_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ break;
+
+ case HAL_PSSI_ERROR_CB_ID :
+ hpssi->ErrorCallback = HAL_PSSI_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_PSSI_ABORT_CB_ID :
+ hpssi->AbortCpltCallback = HAL_PSSI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ break;
+
+ case HAL_PSSI_MSPINIT_CB_ID :
+ hpssi->MspInitCallback = HAL_PSSI_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_PSSI_MSPDEINIT_CB_ID :
+ hpssi->MspDeInitCallback = HAL_PSSI_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_PSSI_STATE_RESET == hpssi->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_PSSI_MSPINIT_CB_ID :
+ hpssi->MspInitCallback = HAL_PSSI_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_PSSI_MSPDEINIT_CB_ID :
+ hpssi->MspDeInitCallback = HAL_PSSI_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpssi);
+ return status;
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup PSSI_Exported_Functions_Group2 Input and Output operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the PSSI data
+ transfers.
+
+ (#) There are two modes of transfer:
+ (++) Blocking mode : The communication is performed in the polling mode.
+ The status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode : The communication is performed using DMA.
+ These functions return the status of the transfer startup.
+ The end of the data processing will be indicated through the
+ dedicated the DMA IRQ .
+
+ (#) Blocking mode functions are :
+ (++) HAL_PSSI_Transmit()
+ (++) HAL_PSSI_Receive()
+
+ (#) No-Blocking mode functions with DMA are :
+ (++) HAL_PSSI_Transmit_DMA()
+ (++) HAL_PSSI_Receive_DMA()
+
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (++) HAL_PSSI_TxCpltCallback()
+ (++) HAL_PSSI_RxCpltCallback()
+ (++) HAL_PSSI_ErrorCallback()
+ (++) HAL_PSSI_AbortCpltCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmits in master mode an amount of data in blocking mode.
+ * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
+ * the configuration information for the specified PSSI.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent (in bytes)
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart;
+ uint32_t transfer_size = Size;
+
+ if (((hpssi->Init.DataWidth == HAL_PSSI_8BITS) && (hpssi->Init.BusWidth != HAL_PSSI_8LINES)) ||
+ ((hpssi->Init.DataWidth == HAL_PSSI_16BITS) && ((Size % 2U) != 0U)) ||
+ ((hpssi->Init.DataWidth == HAL_PSSI_32BITS) && ((Size % 4U) != 0U)))
+ {
+ hpssi->ErrorCode = HAL_PSSI_ERROR_NOT_SUPPORTED;
+ return HAL_ERROR;
+ }
+ if (hpssi->State == HAL_PSSI_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hpssi);
+
+ hpssi->State = HAL_PSSI_STATE_BUSY;
+ hpssi->ErrorCode = HAL_PSSI_ERROR_NONE;
+
+ /* Disable the selected PSSI peripheral */
+ HAL_PSSI_DISABLE(hpssi);
+
+ /* Configure transfer parameters */
+ hpssi->Instance->CR |= PSSI_CR_OUTEN_OUTPUT |
+ ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL);
+ /* DMA Disable */
+ hpssi->Instance->CR &= PSSI_CR_DMA_DISABLE;
+
+ /* Enable the selected PSSI peripheral */
+ HAL_PSSI_ENABLE(hpssi);
+
+ if (hpssi->Init.DataWidth == HAL_PSSI_8BITS)
+ {
+ uint8_t *pbuffer = pData;
+ while (transfer_size > 0U)
+ {
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+ /* Wait until Fifo is ready to transfer one byte flag is set */
+ if (PSSI_WaitOnStatusUntilTimeout(hpssi, PSSI_FLAG_RTT1B, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ hpssi->ErrorCode = HAL_PSSI_ERROR_TIMEOUT;
+ hpssi->State = HAL_PSSI_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hpssi);
+ return HAL_ERROR;
+ }
+ /* Write data to DR */
+ *(__IO uint8_t *)(&hpssi->Instance->DR) = *(uint8_t *)pbuffer;
+
+ /* Increment Buffer pointer */
+ pbuffer++;
+
+ transfer_size--;
+ }
+ }
+ else if (hpssi->Init.DataWidth == HAL_PSSI_16BITS)
+ {
+ uint16_t *pbuffer = (uint16_t *)pData;
+ __IO uint16_t *dr = (__IO uint16_t *)(&hpssi->Instance->DR);
+
+ while (transfer_size > 0U)
+ {
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+ /* Wait until Fifo is ready to transfer four bytes flag is set */
+ if (PSSI_WaitOnStatusUntilTimeout(hpssi, PSSI_FLAG_RTT4B, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ hpssi->ErrorCode = HAL_PSSI_ERROR_TIMEOUT;
+ hpssi->State = HAL_PSSI_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hpssi);
+ return HAL_ERROR;
+ }
+ /* Write data to DR */
+ *dr = *pbuffer;
+
+ /* Increment Buffer pointer */
+ pbuffer++;
+ transfer_size -= 2U;
+
+ }
+ }
+ else if (hpssi->Init.DataWidth == HAL_PSSI_32BITS)
+ {
+ uint32_t *pbuffer = (uint32_t *)pData;
+ while (transfer_size > 0U)
+ {
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+ /* Wait until Fifo is ready to transfer four bytes flag is set */
+ if (PSSI_WaitOnStatusUntilTimeout(hpssi, PSSI_FLAG_RTT4B, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ hpssi->ErrorCode = HAL_PSSI_ERROR_TIMEOUT;
+ hpssi->State = HAL_PSSI_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hpssi);
+ return HAL_ERROR;
+ }
+ /* Write data to DR */
+ *(__IO uint32_t *)(&hpssi->Instance->DR) = *pbuffer;
+
+ /* Increment Buffer pointer */
+ pbuffer++;
+ transfer_size -= 4U;
+ }
+
+ }
+ else
+ {
+ hpssi->ErrorCode = HAL_PSSI_ERROR_NOT_SUPPORTED;
+ hpssi->State = HAL_PSSI_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hpssi);
+ return HAL_ERROR;
+ }
+
+ /* Check Errors Flags */
+ if (HAL_PSSI_GET_FLAG(hpssi, PSSI_FLAG_OVR_RIS) != 0U)
+ {
+ HAL_PSSI_CLEAR_FLAG(hpssi, PSSI_FLAG_OVR_RIS);
+ HAL_PSSI_DISABLE(hpssi);
+ hpssi->ErrorCode = HAL_PSSI_ERROR_UNDER_RUN;
+ hpssi->State = HAL_PSSI_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hpssi);
+ return HAL_ERROR;
+ }
+
+ hpssi->State = HAL_PSSI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hpssi);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+/**
+ * @brief Receives an amount of data in blocking mode.
+ * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
+ * the configuration information for the specified PSSI.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be received (in bytes)
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart;
+ uint32_t transfer_size = Size;
+
+ if (((hpssi->Init.DataWidth == HAL_PSSI_8BITS) && (hpssi->Init.BusWidth != HAL_PSSI_8LINES)) ||
+ ((hpssi->Init.DataWidth == HAL_PSSI_16BITS) && ((Size % 2U) != 0U)) ||
+ ((hpssi->Init.DataWidth == HAL_PSSI_32BITS) && ((Size % 4U) != 0U)))
+ {
+ hpssi->ErrorCode = HAL_PSSI_ERROR_NOT_SUPPORTED;
+ return HAL_ERROR;
+ }
+
+ if (hpssi->State == HAL_PSSI_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hpssi);
+
+ hpssi->State = HAL_PSSI_STATE_BUSY;
+ hpssi->ErrorCode = HAL_PSSI_ERROR_NONE;
+
+ /* Disable the selected PSSI peripheral */
+ HAL_PSSI_DISABLE(hpssi);
+ /* Configure transfer parameters */
+ hpssi->Instance->CR |= PSSI_CR_OUTEN_INPUT |
+ ((hpssi->Init.ClockPolarity == HAL_PSSI_FALLING_EDGE) ? 0U : PSSI_CR_CKPOL);
+
+ /* DMA Disable */
+ hpssi->Instance->CR &= PSSI_CR_DMA_DISABLE;
+
+ /* Enable the selected PSSI peripheral */
+ HAL_PSSI_ENABLE(hpssi);
+ if (hpssi->Init.DataWidth == HAL_PSSI_8BITS)
+ {
+ uint8_t *pbuffer = pData;
+
+ while (transfer_size > 0U)
+ {
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+ /* Wait until Fifo is ready to receive one byte flag is set */
+ if (PSSI_WaitOnStatusUntilTimeout(hpssi, PSSI_FLAG_RTT1B, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ hpssi->ErrorCode = HAL_PSSI_ERROR_TIMEOUT;
+ hpssi->State = HAL_PSSI_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hpssi);
+ return HAL_ERROR;
+ }
+ /* Read data from DR */
+ *pbuffer = *(__IO uint8_t *)(&hpssi->Instance->DR);
+ pbuffer++;
+ transfer_size--;
+ }
+ }
+ else if (hpssi->Init.DataWidth == HAL_PSSI_16BITS)
+ {
+ uint16_t *pbuffer = (uint16_t *)pData;
+ __IO uint16_t *dr = (__IO uint16_t *)(&hpssi->Instance->DR);
+
+ while (transfer_size > 0U)
+ {
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+ /* Wait until Fifo is ready to receive four bytes flag is set */
+ if (PSSI_WaitOnStatusUntilTimeout(hpssi, PSSI_FLAG_RTT4B, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ hpssi->ErrorCode = HAL_PSSI_ERROR_TIMEOUT;
+ hpssi->State = HAL_PSSI_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hpssi);
+ return HAL_ERROR;
+ }
+
+ /* Read data from DR */
+ *pbuffer = *dr;
+ pbuffer++;
+ transfer_size -= 2U;
+
+ }
+ }
+ else if (hpssi->Init.DataWidth == HAL_PSSI_32BITS)
+ {
+ uint32_t *pbuffer = (uint32_t *)pData;
+
+ while (transfer_size > 0U)
+ {
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+ /* Wait until Fifo is ready to receive four bytes flag is set */
+ if (PSSI_WaitOnStatusUntilTimeout(hpssi, PSSI_FLAG_RTT4B, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ hpssi->ErrorCode = HAL_PSSI_ERROR_TIMEOUT;
+ hpssi->State = HAL_PSSI_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hpssi);
+ return HAL_ERROR;
+ }
+
+ /* Read data from DR */
+ *pbuffer = *(__IO uint32_t *)(&hpssi->Instance->DR);
+ pbuffer++;
+ transfer_size -= 4U;
+
+ }
+ }
+ else
+ {
+ hpssi->ErrorCode = HAL_PSSI_ERROR_NOT_SUPPORTED;
+ hpssi->State = HAL_PSSI_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hpssi);
+ return HAL_ERROR;
+ }
+ /* Check Errors Flags */
+
+ if (HAL_PSSI_GET_FLAG(hpssi, PSSI_FLAG_OVR_RIS) != 0U)
+ {
+ HAL_PSSI_CLEAR_FLAG(hpssi, PSSI_FLAG_OVR_RIS);
+ hpssi->ErrorCode = HAL_PSSI_ERROR_OVER_RUN;
+ __HAL_UNLOCK(hpssi);
+ return HAL_ERROR;
+ }
+
+
+ hpssi->State = HAL_PSSI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hpssi);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with DMA
+ * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
+ * the configuration information for the specified PSSI.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent (in bytes)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PSSI_Transmit_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size)
+{
+ HAL_StatusTypeDef dmaxferstatus;
+
+ if (hpssi->State == HAL_PSSI_STATE_READY)
+ {
+
+ /* Process Locked */
+ __HAL_LOCK(hpssi);
+
+ hpssi->State = HAL_PSSI_STATE_BUSY_TX;
+ hpssi->ErrorCode = HAL_PSSI_ERROR_NONE;
+
+ /* Disable the selected PSSI peripheral */
+ HAL_PSSI_DISABLE(hpssi);
+
+ /* Prepare transfer parameters */
+ hpssi->pBuffPtr = pData;
+ hpssi->XferCount = Size;
+
+ if (hpssi->XferCount > PSSI_MAX_NBYTE_SIZE)
+ {
+ hpssi->XferSize = PSSI_MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hpssi->XferSize = hpssi->XferCount;
+ }
+
+ if (hpssi->XferSize > 0U)
+ {
+ if (hpssi->hdmatx != NULL)
+ {
+
+ /* Configure BusWidth */
+ if (hpssi->hdmatx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_BYTE)
+ {
+ MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL,
+ PSSI_CR_DMA_ENABLE | PSSI_CR_OUTEN_OUTPUT |
+ ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL));
+ }
+ else
+ {
+ MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL,
+ PSSI_CR_DMA_ENABLE | hpssi->Init.BusWidth | PSSI_CR_OUTEN_OUTPUT |
+ ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL));
+ }
+
+ /* Set the PSSI DMA transfer complete callback */
+ hpssi->hdmatx->XferCpltCallback = PSSI_DMATransmitCplt;
+
+ /* Set the DMA error callback */
+ hpssi->hdmatx->XferErrorCallback = PSSI_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hpssi->hdmatx->XferHalfCpltCallback = NULL;
+ hpssi->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the DMA */
+ if ((hpssi->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if (hpssi->hdmatx->LinkedListQueue != NULL)
+ {
+ /* Enable the DMA channel */
+ /* Set DMA data size */
+ hpssi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hpssi->XferSize;
+ /* Set DMA source address */
+ hpssi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
+ /* Set DMA destination address */
+ hpssi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
+ (uint32_t)&hpssi->Instance->DR;
+
+ dmaxferstatus = HAL_DMAEx_List_Start_IT(hpssi->hdmatx);
+ }
+ else
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ dmaxferstatus = HAL_DMA_Start_IT(hpssi->hdmatx, (uint32_t)pData, (uint32_t)&hpssi->Instance->DR,
+ hpssi->XferSize);
+ }
+ }
+ else
+ {
+ /* Update PSSI state */
+ hpssi->State = HAL_PSSI_STATE_READY;
+
+ /* Update PSSI error code */
+ hpssi->ErrorCode |= HAL_PSSI_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hpssi);
+
+ return HAL_ERROR;
+ }
+
+ if (dmaxferstatus == HAL_OK)
+ {
+
+
+ /* Update XferCount value */
+ hpssi->XferCount -= hpssi->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hpssi);
+
+ /* Note : The PSSI interrupts must be enabled after unlocking current process
+ to avoid the risk of PSSI interrupt handle execution before current
+ process unlock */
+ /* Enable ERR interrupt */
+ HAL_PSSI_ENABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
+
+ /* Enable DMA Request */
+ hpssi->Instance->CR |= PSSI_CR_DMA_ENABLE;
+ /* Enable the selected PSSI peripheral */
+ HAL_PSSI_ENABLE(hpssi);
+ }
+ else
+ {
+ /* Update PSSI state */
+ hpssi->State = HAL_PSSI_STATE_READY;
+
+ /* Update PSSI error code */
+ hpssi->ErrorCode |= HAL_PSSI_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hpssi);
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hpssi);
+
+ /* Note : The PSSI interrupts must be enabled after unlocking current process
+ to avoid the risk of PSSI interrupt handle execution before current
+ process unlock */
+ /* Enable ERRinterrupt */
+ /* possible to enable all of these */
+
+ HAL_PSSI_ENABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with DMA
+ * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
+ * the configuration information for the specified PSSI.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be received (in bytes)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size)
+{
+
+ HAL_StatusTypeDef dmaxferstatus;
+
+ if (hpssi->State == HAL_PSSI_STATE_READY)
+ {
+
+ /* Disable the selected PSSI peripheral */
+ HAL_PSSI_DISABLE(hpssi);
+ /* Process Locked */
+ __HAL_LOCK(hpssi);
+
+ hpssi->State = HAL_PSSI_STATE_BUSY_RX;
+ hpssi->ErrorCode = HAL_PSSI_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hpssi->pBuffPtr = pData;
+ hpssi->XferCount = Size;
+
+ if (hpssi->XferCount > PSSI_MAX_NBYTE_SIZE)
+ {
+ hpssi->XferSize = PSSI_MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hpssi->XferSize = hpssi->XferCount;
+ }
+
+ if (hpssi->XferSize > 0U)
+ {
+ if (hpssi->hdmarx != NULL)
+ {
+
+ /* Configure BusWidth */
+ if (hpssi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_BYTE)
+ {
+ MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL, PSSI_CR_DMA_ENABLE |
+ ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? PSSI_CR_CKPOL : 0U));
+ }
+ else
+ {
+ MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL,
+ PSSI_CR_DMA_ENABLE | hpssi->Init.BusWidth |
+ ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? PSSI_CR_CKPOL : 0U));
+ }
+
+ /* Set the PSSI DMA transfer complete callback */
+ hpssi->hdmarx->XferCpltCallback = PSSI_DMAReceiveCplt;
+
+ /* Set the DMA error callback */
+ hpssi->hdmarx->XferErrorCallback = PSSI_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hpssi->hdmarx->XferHalfCpltCallback = NULL;
+ hpssi->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA */
+ if ((hpssi->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if (hpssi->hdmarx->LinkedListQueue != NULL)
+ {
+ /* Enable the DMA channel */
+ /* Set DMA data size */
+ hpssi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hpssi->XferSize;
+ /* Set DMA source address */
+ hpssi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
+ (uint32_t)&hpssi->Instance->DR;
+ /* Set DMA destination address */
+ hpssi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
+
+ dmaxferstatus = HAL_DMAEx_List_Start_IT(hpssi->hdmarx);
+ }
+ else
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ dmaxferstatus = HAL_DMA_Start_IT(hpssi->hdmarx, (uint32_t)&hpssi->Instance->DR, (uint32_t)pData,
+ hpssi->XferSize);
+ }
+ }
+ else
+ {
+ /* Update PSSI state */
+ hpssi->State = HAL_PSSI_STATE_READY;
+
+ /* Update PSSI error code */
+ hpssi->ErrorCode |= HAL_PSSI_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hpssi);
+
+ return HAL_ERROR;
+ }
+
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Update XferCount value */
+ hpssi->XferCount -= hpssi->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hpssi);
+
+ /* Note : The PSSI interrupts must be enabled after unlocking current process
+ to avoid the risk of PSSI interrupt handle execution before current
+ process unlock */
+ /* Enable ERR interrupt */
+ HAL_PSSI_ENABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
+
+ /* Enable DMA Request */
+ hpssi->Instance->CR |= PSSI_CR_DMA_ENABLE;
+ /* Enable the selected PSSI peripheral */
+ HAL_PSSI_ENABLE(hpssi);
+ }
+ else
+ {
+ /* Update PSSI state */
+ hpssi->State = HAL_PSSI_STATE_READY;
+
+ /* Update PSSI error code */
+ hpssi->ErrorCode |= HAL_PSSI_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hpssi);
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hpssi);
+
+ /* Enable ERR,interrupt */
+ HAL_PSSI_ENABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+
+/**
+ * @brief Abort a DMA process communication with Interrupt.
+ * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
+ * the configuration information for the specified PSSI.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi)
+{
+
+ /* Process Locked */
+ __HAL_LOCK(hpssi);
+
+ /* Disable Interrupts */
+ HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
+
+ /* Set State at HAL_PSSI_STATE_ABORT */
+ hpssi->State = HAL_PSSI_STATE_ABORT;
+
+ /* Abort DMA TX transfer if any */
+ if ((hpssi->Instance->CR & PSSI_CR_DMAEN) == PSSI_CR_DMAEN)
+ {
+ if (hpssi->State == HAL_PSSI_STATE_BUSY_TX)
+ {
+
+ hpssi->Instance->CR &= ~PSSI_CR_DMAEN;
+
+ if (hpssi->hdmatx != NULL)
+ {
+ /* Set the PSSI DMA Abort callback :
+ will lead to call HAL_PSSI_ErrorCallback() at end of DMA abort procedure */
+ hpssi->hdmatx->XferAbortCallback = PSSI_DMAAbort;
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hpssi->hdmatx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hpssi->hdmatx->XferAbortCallback(hpssi->hdmatx);
+ }
+ }
+
+ }
+ /* Abort DMA RX transfer if any */
+ else if (hpssi->State == HAL_PSSI_STATE_BUSY_RX)
+ {
+
+ hpssi->Instance->CR &= ~PSSI_CR_DMAEN;
+
+ if (hpssi->hdmarx != NULL)
+ {
+ /* Set the PSSI DMA Abort callback :
+ will lead to call HAL_PSSI_ErrorCallback() at end of DMA abort procedure */
+ hpssi->hdmarx->XferAbortCallback = PSSI_DMAAbort;
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hpssi->hdmarx) != HAL_OK)
+ {
+ /* Call Directly hpssi->hdma->XferAbortCallback function in case of error */
+ hpssi->hdmarx->XferAbortCallback(hpssi->hdmarx);
+ }
+ }
+ }
+ else
+ {
+ /* Call the error callback */
+ hpssi->ErrorCallback(hpssi);
+ }
+ }
+
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hpssi);
+
+ /* Note : The PSSI interrupts must be enabled after unlocking current process
+ to avoid the risk of PSSI interrupt handle execution before current
+ process unlock */
+ HAL_PSSI_ENABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
+
+ return HAL_OK;
+
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup PSSI_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+
+/**
+ * @brief This function handles PSSI event interrupt request.
+ * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
+ * the configuration information for the specified PSSI.
+ * @retval None
+ */
+void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi)
+{
+ /* Overrun/ Underrun Errors */
+ if (HAL_PSSI_GET_FLAG(hpssi, PSSI_FLAG_OVR_MIS) != 0U)
+ {
+ /* Reset handle parameters */
+
+ hpssi->XferCount = 0U;
+
+ /* Disable all interrupts */
+ HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
+
+
+ /* Abort DMA TX transfer if any */
+ if ((hpssi->Instance->CR & PSSI_CR_DMAEN) == PSSI_CR_DMAEN)
+ {
+ if (hpssi->State == HAL_PSSI_STATE_BUSY_TX)
+ {
+ /* Set new error code */
+ hpssi->ErrorCode |= HAL_PSSI_ERROR_UNDER_RUN;
+
+ hpssi->Instance->CR &= ~PSSI_CR_DMAEN;
+
+ if (hpssi->hdmatx != NULL)
+ {
+ /* Set the PSSI DMA Abort callback :
+ will lead to call HAL_PSSI_ErrorCallback() at end of DMA abort procedure */
+ hpssi->hdmatx->XferAbortCallback = PSSI_DMAAbort;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hpssi);
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hpssi->hdmatx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hpssi->hdmatx->XferAbortCallback(hpssi->hdmatx);
+ }
+ }
+
+ }
+ /* Abort DMA RX transfer if any */
+ else if (hpssi->State == HAL_PSSI_STATE_BUSY_RX)
+ {
+ /* Set new error code */
+ hpssi->ErrorCode |= HAL_PSSI_ERROR_OVER_RUN;
+
+ hpssi->Instance->CR &= ~PSSI_CR_DMAEN;
+
+ if (hpssi->hdmarx != NULL)
+ {
+ /* Set the PSSI DMA Abort callback :
+ will lead to call HAL_PSSI_ErrorCallback() at end of DMA abort procedure */
+ hpssi->hdmarx->XferAbortCallback = PSSI_DMAAbort;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hpssi);
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hpssi->hdmarx) != HAL_OK)
+ {
+ /* Call Directly hpssi->hdma->XferAbortCallback function in case of error */
+ hpssi->hdmarx->XferAbortCallback(hpssi->hdmarx);
+ }
+ }
+ }
+ else
+ {
+ /* Call the corresponding callback to inform upper layer of the error */
+ hpssi->ErrorCallback(hpssi);
+ }
+ }
+
+ /* If state is an abort treatment on going, don't change state */
+ if (hpssi->State == HAL_PSSI_STATE_ABORT)
+ {
+ hpssi->State = HAL_PSSI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hpssi);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ hpssi->AbortCpltCallback(hpssi);
+
+ }
+ else
+ {
+ /* Set HAL_PSSI_STATE_READY */
+ hpssi->State = HAL_PSSI_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hpssi);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ hpssi->ErrorCallback(hpssi);
+
+ }
+
+ }
+}
+
+
+/**
+ * @brief Tx Transfer complete callback.
+ * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
+ * the configuration information for the specified PSSI.
+ * @retval None
+ */
+__weak void HAL_PSSI_TxCpltCallback(PSSI_HandleTypeDef *hpssi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpssi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PSSI_TxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer complete callback.
+ * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
+ * the configuration information for the specified PSSI.
+ * @retval None
+ */
+__weak void HAL_PSSI_RxCpltCallback(PSSI_HandleTypeDef *hpssi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpssi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PSSI_RxCpltCallback can be implemented in the user file
+ */
+}
+
+
+/**
+ * @brief PSSI error callback.
+ * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
+ * the configuration information for the specified PSSI.
+ * @retval None
+ */
+__weak void HAL_PSSI_ErrorCallback(PSSI_HandleTypeDef *hpssi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpssi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PSSI_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief PSSI abort callback.
+ * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
+ * the configuration information for the specified PSSI.
+ * @retval None
+ */
+__weak void HAL_PSSI_AbortCpltCallback(PSSI_HandleTypeDef *hpssi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpssi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PSSI_AbortCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup PSSI_Exported_Functions_Group3 Peripheral State and Error functions
+ * @brief Peripheral State, Mode and Error functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State, Mode and Error functions #####
+ ===============================================================================
+ [..]
+ This subsection permit to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the PSSI handle state.
+ * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
+ * the configuration information for the specified PSSI.
+ * @retval HAL state
+ */
+HAL_PSSI_StateTypeDef HAL_PSSI_GetState(PSSI_HandleTypeDef *hpssi)
+{
+ /* Return PSSI handle state */
+ return hpssi->State;
+}
+
+
+/**
+ * @brief Return the PSSI error code.
+ * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
+ * the configuration information for the specified PSSI.
+ * @retval PSSI Error Code
+ */
+uint32_t HAL_PSSI_GetError(PSSI_HandleTypeDef *hpssi)
+{
+ return hpssi->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup PSSI_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief PSSI Errors process.
+ * @param hpssi PSSI handle.
+ * @param ErrorCode Error code to handle.
+ * @retval None
+ */
+static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode)
+{
+
+ /* Reset handle parameters */
+
+ hpssi->XferCount = 0U;
+
+ /* Set new error code */
+ hpssi->ErrorCode |= ErrorCode;
+
+ /* Disable all interrupts */
+ HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
+
+
+ /* Abort DMA TX transfer if any */
+ if ((hpssi->Instance->CR & PSSI_CR_DMAEN) == PSSI_CR_DMAEN)
+ {
+ if (hpssi->State == HAL_PSSI_STATE_BUSY_TX)
+ {
+ hpssi->Instance->CR &= ~PSSI_CR_DMAEN;
+
+ if (hpssi->hdmatx != NULL)
+ {
+ /* Set the PSSI DMA Abort callback :
+ will lead to call HAL_PSSI_ErrorCallback() at end of DMA abort procedure */
+ hpssi->hdmatx->XferAbortCallback = PSSI_DMAAbort;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hpssi);
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hpssi->hdmatx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hpssi->hdmatx->XferAbortCallback(hpssi->hdmatx);
+ }
+ }
+
+ }
+ /* Abort DMA RX transfer if any */
+ else if (hpssi->State == HAL_PSSI_STATE_BUSY_RX)
+ {
+ hpssi->Instance->CR &= ~PSSI_CR_DMAEN;
+
+ if (hpssi->hdmarx != NULL)
+ {
+ /* Set the PSSI DMA Abort callback :
+ will lead to call HAL_PSSI_ErrorCallback() at end of DMA abort procedure */
+ hpssi->hdmarx->XferAbortCallback = PSSI_DMAAbort;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hpssi);
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hpssi->hdmarx) != HAL_OK)
+ {
+ /* Call Directly hpssi->hdma->XferAbortCallback function in case of error */
+ hpssi->hdmarx->XferAbortCallback(hpssi->hdmarx);
+ }
+ }
+ }
+ else
+ {
+ /*Nothing to do*/
+ }
+ }
+
+ /* If state is an abort treatment on going, don't change state */
+ if (hpssi->State == HAL_PSSI_STATE_ABORT)
+ {
+ hpssi->State = HAL_PSSI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hpssi);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+
+ hpssi->AbortCpltCallback(hpssi);
+
+ }
+ else
+ {
+ /* Set HAL_PSSI_STATE_READY */
+ hpssi->State = HAL_PSSI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hpssi);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ hpssi->ErrorCallback(hpssi);
+
+ }
+}
+
+/**
+ * @brief DMA PSSI slave transmit process complete callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+void PSSI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Derogation MISRAC2012-Rule-11.5 */
+ PSSI_HandleTypeDef *hpssi = (PSSI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+
+ uint32_t tmperror;
+
+
+ /* Disable Interrupts */
+ HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
+
+ /* Store current volatile hpssi->ErrorCode, misra rule */
+ tmperror = hpssi->ErrorCode;
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ if ((hpssi->State == HAL_PSSI_STATE_ABORT) || (tmperror != HAL_PSSI_ERROR_NONE))
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ PSSI_Error(hpssi, hpssi->ErrorCode);
+ }
+ /* hpssi->State == HAL_PSSI_STATE_BUSY_TX */
+ else
+ {
+ hpssi->State = HAL_PSSI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hpssi);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+
+ hpssi->TxCpltCallback(hpssi);
+
+ }
+
+
+}
+
+/**
+ * @brief DMA PSSI master receive process complete callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+void PSSI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Derogation MISRAC2012-Rule-11.5 */
+ PSSI_HandleTypeDef *hpssi = (PSSI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+
+ uint32_t tmperror;
+
+
+ /* Disable Interrupts */
+ HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
+
+ /* Store current volatile hpssi->ErrorCode, misra rule */
+ tmperror = hpssi->ErrorCode;
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ if ((hpssi->State == HAL_PSSI_STATE_ABORT) || (tmperror != HAL_PSSI_ERROR_NONE))
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ PSSI_Error(hpssi, hpssi->ErrorCode);
+ }
+ /* hpssi->State == HAL_PSSI_STATE_BUSY_RX */
+ else
+ {
+ hpssi->State = HAL_PSSI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hpssi);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ hpssi->RxCpltCallback(hpssi);
+
+ }
+
+
+}
+
+/**
+ * @brief DMA PSSI communication abort callback
+ * (To be called at end of DMA Abort procedure).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+void PSSI_DMAAbort(DMA_HandleTypeDef *hdma)
+{
+ /* Derogation MISRAC2012-Rule-11.5 */
+ PSSI_HandleTypeDef *hpssi = (PSSI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+
+ /* Reset AbortCpltCallback */
+ hpssi->hdmatx->XferAbortCallback = NULL;
+ hpssi->hdmarx->XferAbortCallback = NULL;
+
+ /* Check if come from abort from user */
+ if (hpssi->State == HAL_PSSI_STATE_ABORT)
+ {
+ hpssi->State = HAL_PSSI_STATE_READY;
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+
+ hpssi->AbortCpltCallback(hpssi);
+
+ }
+ else
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ hpssi->ErrorCallback(hpssi);
+ }
+}
+
+/**
+ * @brief This function handles PSSI Communication Timeout.
+ * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
+ * the configuration information for the specified PSSI.
+ * @param Flag Specifies the PSSI flag to check.
+ * @param Status The new Flag status (SET or RESET).
+ * @param Timeout Timeout duration
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef PSSI_WaitOnStatusUntilTimeout(PSSI_HandleTypeDef *hpssi, uint32_t Flag, FlagStatus Status,
+ uint32_t Timeout, uint32_t Tickstart)
+{
+ while ((HAL_PSSI_GET_STATUS(hpssi, Flag) & Flag) == (uint32_t)Status)
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+ {
+ hpssi->ErrorCode |= HAL_PSSI_ERROR_TIMEOUT;
+ hpssi->State = HAL_PSSI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hpssi);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+ return HAL_OK;
+}
+void PSSI_DMAError(DMA_HandleTypeDef *hdma)
+{
+ /* Derogation MISRAC2012-Rule-11.5 */
+ PSSI_HandleTypeDef *hpssi = (PSSI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+
+ uint32_t tmperror;
+
+
+ /* Disable the selected PSSI peripheral */
+ HAL_PSSI_DISABLE(hpssi);
+
+ /* Disable Interrupts */
+ HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
+
+ /* Store current volatile hpssi->ErrorCode, misra rule */
+ tmperror = hpssi->ErrorCode;
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ if ((hpssi->State == HAL_PSSI_STATE_ABORT) || (tmperror != HAL_PSSI_ERROR_NONE))
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ PSSI_Error(hpssi, hpssi->ErrorCode);
+ }
+ else
+ {
+ hpssi->State = HAL_PSSI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hpssi);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ hpssi->ErrorCallback(hpssi);
+
+ }
+
+}
+
+
+
+/**
+ * @}
+ */
+#endif /* PSSI */
+#endif /* HAL_PSSI_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr.c
new file mode 100644
index 00000000..86129f2e
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr.c
@@ -0,0 +1,946 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_pwr.c
+ * @author MCD Application Team
+ * @brief PWR HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Power Controller (PWR) peripheral:
+ * + Initialization/De-Initialization Functions.
+ * + Peripheral Control Functions.
+ * + PWR Attributes Functions.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### PWR peripheral overview #####
+ ==============================================================================
+ [..]
+ (#) The Power control (PWR) provides an overview of the supply architecture
+ for the different power domains and of the supply configuration
+ controller.
+
+ (#) Domain architecture overview for the U5 devices:
+ (+) U5 devices have 2 power domains (CD and SRD).
+ The core domain (CD) contains a CPU (Cortex-M33), a Flash memory and
+ some peripherals dedicated for general purpose. The SRD domain
+ contains the system control and low-power peripherals.
+
+ (#) Every entity has low power mode as described below :
+ (#) The CPU low power modes are :
+ (+) CPU CRun.
+ (+) CPU CSleep.
+ (+) CPU CStop.
+ (#) The system low power modes are :
+ (+) Run.
+ (+) Stop 0.
+ (+) Stop 1.
+ (+) Stop 2.
+ (+) Stop 3.
+ (+) Standby.
+ (+) Shutdown.
+
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) After startup, power management peripheral is not active by default. Use
+ __HAL_RCC_PWR_CLK_ENABLE() macro to enable power interface.
+
+ (#) Call HAL_PWR_EnableBkUpAccess() and HAL_PWR_DisableBkUpAccess() functions
+ to enable/disable access to the backup domain (RCC Backup domain control
+ register RCC_BDCR, RTC registers, TAMP registers, backup registers and
+ backup SRAM).
+
+ (#) Call HAL_PWR_ConfigPVD() after setting parameters to be configured (event
+ mode and voltage threshold) in order to set up the Programmed Voltage
+ Detector, then use HAL_PWR_EnablePVD() and HAL_PWR_DisablePVD()
+ functions to start and stop the PVD detection.
+ (+) PVD level can be one of the following values :
+ (++) 2V0
+ (++) 2V2
+ (++) 2V4
+ (++) 2V5
+ (++) 2V6
+ (++) 2V8
+ (++) 2V9
+ (++) External input analog voltage PVD_IN (compared internally to
+ VREFINT)
+
+ (#) Call HAL_PWR_EnableWakeUpPin() and HAL_PWR_DisableWakeUpPin() functions
+ with the right parameter to configure the wake up pin polarity (Low or
+ High), the wake up pin selection and to enable and disable it.
+
+ (#) Call HAL_PWR_EnterSLEEPMode() function to enter the CPU in Sleep mode.
+ Wake-up from Sleep mode could be following to an event or an
+ interrupt according to low power mode intrinsic request called (__WFI()
+ or __WFE()).
+
+ (#) Call HAL_PWR_EnterSTOPMode() function to enter the whole system to Stop 0
+ mode. Wake-up from Stop 0 mode could be following to an event or an
+ interrupt according to low power mode intrinsic request called (__WFI()
+ or __WFE()). (Regulator state on U5 devices is managed internally but
+ regulator parameter is kept for product compatibility).
+
+ (#) Call HAL_PWR_EnterSTANDBYMode() function to enter the whole system in
+ Standby mode. Wake-up from Standby mode can be following only by an
+ interrupt.
+
+ (#) Call HAL_PWR_EnableSleepOnExit() and HAL_PWR_DisableSleepOnExit() APIs to
+ enable and disable the Cortex-M33 re-entry in Sleep mode after an
+ interruption handling is over.
+
+ (#) Call HAL_PWR_EnableSEVOnPend() and HAL_PWR_DisableSEVOnPend() functions
+ to configure the Cortex-M33 to wake-up after any pending event / interrupt
+ even if it's disabled or has insufficient priority to cause exception
+ entry.
+
+ (#) Call HAL_PWR_PVD_IRQHandler() under PVD_AVD_IRQHandler() function to
+ handle the PWR PVD interrupt request.
+
+ (#) Call HAL_PWR_ConfigAttributes() function to configure PWR item secure and
+ privilege attributes and call HAL_PWR_GetConfigAttributes() function to
+ get the attribute configuration for the selected item.
+
+ *** PWR HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in PWR HAL driver.
+
+ (+) __HAL_PWR_GET_FLAG() : Get the PWR pending flags.
+ (+) __HAL_PWR_CLEAR_FLAG() : Clear the PWR pending flags.
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup PWR PWR
+ * @brief PWR HAL module driver
+ * @{
+ */
+
+#if defined (HAL_PWR_MODULE_ENABLED)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup PWR_Private_Defines PWR Private Defines
+ * @{
+ */
+
+/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
+ * @{
+ */
+#define PVD_RISING_EDGE (0x01U) /*!< Mask for rising edge set as PVD trigger */
+#define PVD_FALLING_EDGE (0x02U) /*!< Mask for falling edge set as PVD trigger */
+#define PVD_MODE_IT (0x04U) /*!< Mask for interruption yielded by PVD threshold crossing */
+#define PVD_MODE_EVT (0x08U) /*!< Mask for event yielded by PVD threshold crossing */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Functions PWR Exported Functions
+ * @{
+ */
+
+/** @defgroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions
+ * @brief Initialization and de-Initialization functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and De-Initialization Functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to deinitialize power peripheral
+ and to manage backup domain access.
+
+ [..]
+ After system reset, the backup domain (RCC Backup domain control register
+ RCC_BDCR, RTC registers, TAMP registers, backup registers and backup SRAM)
+ is protected against possible unwanted write accesses.
+ The HAL_PWR_EnableBkUpAccess() function enables the access to the backup
+ domain.
+ The HAL_PWR_DisableBkUpAccess() function disables the access to the backup
+ domain.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Deinitialize the HAL PWR peripheral registers to their default reset
+ * values.
+ * @note This functionality is not available in this product.
+ * The prototype is kept just to maintain compatibility with other
+ * products.
+ * @retval None.
+ */
+void HAL_PWR_DeInit(void)
+{
+}
+
+/**
+ * @brief Enable access to the backup domain (RCC Backup domain control
+ * register RCC_BDCR, RTC registers, TAMP registers, backup registers
+ * and backup SRAM).
+ * @note After a system reset, the backup domain is protected against
+ * possible unwanted write accesses.
+ * @retval None.
+ */
+void HAL_PWR_EnableBkUpAccess(void)
+{
+ SET_BIT(PWR->DBPR, PWR_DBPR_DBP);
+}
+
+/**
+ * @brief Disable access to the backup domain (RCC Backup domain control
+ * register RCC_BDCR, RTC registers, TAMP registers, backup registers
+ * and backup SRAM).
+ * @retval None.
+ */
+void HAL_PWR_DisableBkUpAccess(void)
+{
+ CLEAR_BIT(PWR->DBPR, PWR_DBPR_DBP);
+}
+/**
+ * @}
+ */
+
+
+/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control Functions
+ * @brief Low power modes configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to control power peripheral.
+
+ *** PVD configuration ***
+ =========================
+ [..]
+ (+) The PVD can be used to monitor the VDD power supply by comparing it
+ to a threshold selected by the PVDLS[2:0] bits in the PWR supply
+ voltage monitoring control register (PWR_SVMCR) and can be enabled by
+ setting the PVDE bit.
+
+ (+) A PVDO flag is available in the PWR supply voltage monitoring control
+ register (PWR_SVMCR) to indicate if VDD is higher or lower than the
+ PVD threshold. This event is internally connected to the EXTI line 16
+ and can generate an interrupt if enabled through the EXTI registers.
+ It is configurable through __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
+
+ (+) The PVD can remain active in Stop 0, Stop 1, Stop 2 modes, and the PVM
+ interrupt can wake up from the Stop mode. The PVD is not functional in
+ Stop 3 mode.
+
+ (+) During Stop 1, Stop 2 and Stop 3 modes, it is possible to set the PVD
+ in ultra-low-power mode to further reduce the current consumption by
+ setting the ULPMEN bit in PWR_CR1 register.
+
+ *** Wake-up pin configuration ***
+ =================================
+ [..]
+ (+) Wake-up pin is used to wake up the system from Stop 3, Standby and
+ Shutdown mode.
+ The pin selection is configurable through the WUCR3 register to map
+ internal signal to wake up pin line.
+ The pin polarity is configurable through the WUCR2 register to be
+ active on rising or falling edges.
+
+ (+) There are up to 24 wake-up signals that can be mapped to up to 8
+ wake-up lines in the STM32U5 family.
+
+ *** Low Power modes configuration ***
+ =====================================
+ [..]
+ This section presents 3 principles low-power modes :
+ (+) Sleep mode : Cortex-M33 is stopped and all PWR domains are remaining
+ active (powered and clocked).
+
+ (+) Stop 0 mode : Cortex-M33 is stopped, clocks are stopped and the
+ regulator is running.
+
+ (+) Standby mode : All PWR domains enter DSTANDBY mode and the VCORE
+ supply regulator is powered off.
+
+ *** Sleep mode ***
+ ==================
+ [..]
+ (+) Entry :
+ The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode()
+ function.
+
+ (++) PWR_SLEEPENTRY_WFI: enter Sleep mode with WFI instruction.
+ (++) PWR_SLEEPENTRY_WFE: enter Sleep mode with WFE instruction.
+
+ -@@- The Regulator parameter is not used for the STM32U5 family and is
+ kept as parameter just to maintain compatibility with other families.
+
+ (+) Exit :
+ According to Sleep entry, any event when entry is __WFE() intrinsic
+ and any interrupt when entry is __WFI() intrinsic can wake up the
+ device from Sleep mode.
+
+ *** Stop 0 mode ***
+ ===================
+ [..]
+ The Stop 0 mode is based on the Cortex-M33 Deepsleep mode combined with
+ the peripheral clock gating. The voltage regulator is configured in main
+ regulator mode. In Stop 0 mode, all clocks in the VCORE domain are stopped.
+ The PLL, MSIS, MSIK, HSI16 and HSE oscillators are disabled.
+ Some peripherals with the LPBAM capability can switch on HSI16 or MSIS or
+ MSIK for transferring data. All SRAMs and register contents are preserved,
+ but the SRAMs can be totally or partially switched off to further reduced
+ consumption.
+ The BOR is always available in Stop 0 mode.
+
+ (+) Entry:
+ The Stop mode is entered using the HAL_PWR_EnterSTOPMode() function
+ with :
+
+ (++) StopEntry:
+ (+++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction.
+ (+++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction.
+
+ -@@- The Regulator parameter is not used for the STM32U5 family and is
+ kept as parameter just to maintain compatibility with other families.
+
+ (+) Exit:
+ Any EXTI line configured in interrupt mode (the corresponding EXTI
+ interrupt vector must be enabled in the NVIC). The interrupt source
+ can be external interrupts or peripherals with wakeup capability.
+ Any peripheral interrupt occurring when the AHB/APB clocks are present
+ due to an autonomous peripheral clock request (the peripheral vector
+ must be enabled in the NVIC).
+
+ *** Standby mode ***
+ ====================
+ [..]
+ The Standby mode is used to achieve the lowest power consumption with BOR.
+ The internal regulator is switched off so that the VCORE domain is powered
+ off.
+ The PLL, the MSI (MSIS and MSIK) RC, the HSI16 RC and the HSE crystal
+ oscillators are also switched off.
+ The RTC can remain active (Standby mode with RTC, Standby mode without
+ RTC).
+ The Brownout reset (BOR) always remains active in Standby mode.
+ The state of each I/O during Standby mode can be selected by software:
+ I/O with internal pull-up, internal pull-down or floating.
+ After entering Standby mode, SRAMs and register contents are lost except
+ for registers and backup SRAM in the Backup domain and Standby circuitry.
+ Optionally, the full SRAM2 or 8 Kbytes or 56 Kbytes can be retained in
+ Standby mode, supplied by the low-power regulator (Standby with RAM2
+ retention mode).
+ The BORL (Brownout reset detector low) can be configured in ultra low
+ power mode to further reduce power consumption during Standby mode.
+ The device exits Standby mode upon an external reset (NRST pin), an IWDG
+ reset, WKUP pin event (configurable rising or falling edge), an RTC event
+ occurs (alarm, periodic wakeup, timestamp), or a tamper detection.
+ The system clock after wakeup is MSIS up to 4 MHz.
+
+ (++) Entry:
+ The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode()
+ function.
+
+ (++) Exit:
+ WKUPx pin edge, RTC event, external Reset in NRST pin, IWDG Reset,
+ BOR reset.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the voltage threshold detected by the Programmed Voltage
+ * Detector (PVD).
+ * @param pConfigPVD : Pointer to a PWR_PVDTypeDef structure that contains the
+ * PVD configuration information (PVDLevel and EventMode).
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *pConfigPVD)
+{
+ /* Check the PVD parameter */
+ if (pConfigPVD == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_PWR_PVD_LEVEL(pConfigPVD->PVDLevel));
+ assert_param(IS_PWR_PVD_MODE(pConfigPVD->Mode));
+
+ /* Set PVDLS[2:0] bits according to PVDLevel value */
+ MODIFY_REG(PWR->SVMCR, PWR_SVMCR_PVDLS, pConfigPVD->PVDLevel);
+
+ /* Disable PVD Event/Interrupt */
+ __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
+ __HAL_PWR_PVD_EXTI_DISABLE_IT();
+ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
+ __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
+
+ /* Configure the PVD in interrupt mode */
+ if ((pConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
+ {
+ __HAL_PWR_PVD_EXTI_ENABLE_IT();
+ }
+
+ /* Configure the PVD in event mode */
+ if ((pConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
+ {
+ __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
+ }
+
+ /* Configure the PVD in rising edge */
+ if ((pConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
+ {
+ __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
+ }
+
+ /* Configure the PVD in falling edge */
+ if ((pConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
+ {
+ __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable the programmable voltage detector (PVD).
+ * @retval None.
+ */
+void HAL_PWR_EnablePVD(void)
+{
+ SET_BIT(PWR->SVMCR, PWR_SVMCR_PVDE);
+}
+
+/**
+ * @brief Disable the programmable voltage detector (PVD).
+ * @retval None.
+ */
+void HAL_PWR_DisablePVD(void)
+{
+ CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_PVDE);
+}
+
+/**
+ * @brief Enable the wake up line functionality.
+ * @note Wake up lines are used to wake up the system from Stop 3, Standby and
+ * Shutdown modes.
+ * @param WakeUpPin : Specifies which wake up line to enable. This parameter
+ * can be one of PWR_WakeUp_Pins_High_Polarity define
+ * group where every param select the wake up line, the
+ * wake up source with high polarity detection and the wake
+ * up selected I/O or can be one of
+ * PWR_WakeUp_Pins_Low_Polarity define group where every
+ * param select the wake up line, the wake up source with
+ * low polarity and the wake up selected I/O or can be one
+ * of PWR_WakeUp_Pins define group where every param select
+ * the wake up line, the wake up source with
+ * high polarity and the first wake up I/O.
+ * @retval None.
+ */
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
+{
+ /* Check the parameter */
+ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPin));
+
+ /* Specifies the wake up line polarity for the event detection (rising or falling edge) */
+ MODIFY_REG(PWR->WUCR2, (PWR_EWUP_MASK & WakeUpPin), (WakeUpPin >> PWR_WUP_POLARITY_SHIFT));
+
+ /* Specifies the wake up line I/O selection */
+ MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(PWR_EWUP_MASK & WakeUpPin) * 2U)),
+ (WakeUpPin >> PWR_WUP_SELECT_SIGNAL_SHIFT));
+
+ /* Enable wake-up line */
+ SET_BIT(PWR->WUCR1, (PWR_EWUP_MASK & WakeUpPin));
+}
+
+/**
+ * @brief Disable the wake up line functionality.
+ * @param WakeUpPin : Specifies the wake up line to disable.
+ * This parameter can be a combination of all the following
+ * values :
+ * @arg @ref PWR_WAKEUP_PIN1
+ * @arg @ref PWR_WAKEUP_PIN2
+ * @arg @ref PWR_WAKEUP_PIN3
+ * @arg @ref PWR_WAKEUP_PIN4
+ * @arg @ref PWR_WAKEUP_PIN6
+ * @arg @ref PWR_WAKEUP_PIN5
+ * @arg @ref PWR_WAKEUP_PIN7
+ * @arg @ref PWR_WAKEUP_PIN8
+ * @retval None
+ */
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPin));
+
+ /* Disable wake-up pin */
+ CLEAR_BIT(PWR->WUCR1, (PWR_EWUP_MASK & WakeUpPin));
+}
+
+/**
+ * @brief Enter the CPU in Sleep mode.
+ * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
+ * @note CPU clock is off and all peripherals including Cortex-M33 core such
+ * as NVIC and SysTick can run and wake up the CPU when an interrupt
+ * or an event occurs.
+ * @param Regulator : Specifies the regulator state in Sleep mode.
+ * This parameter can be one of the following values :
+ * @arg @ref PWR_MAINREGULATOR_ON
+ * @arg @ref PWR_LOWPOWERREGULATOR_ON
+ * @note This parameter is not available in this product.
+ * The parameter is kept just to maintain compatibility with other
+ * products.
+ * @param SleepEntry : Specifies if Sleep mode is entered with WFI or WFE
+ * instruction.
+ * This parameter can be one of the following values :
+ * @arg @ref PWR_SLEEPENTRY_WFI enter Sleep mode with Wait
+ * For Interrupt request.
+ * @arg @ref PWR_SLEEPENTRY_WFE enter Sleep mode with Wait
+ * For Event request.
+ * @note When WFI entry is used, ticks interrupt must be disabled to avoid
+ * unexpected CPU wake up.
+ * @retval None.
+ */
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SleepEntry)
+{
+ UNUSED(Regulator);
+
+ /* Check the parameter */
+ assert_param(IS_PWR_SLEEP_ENTRY(SleepEntry));
+
+ /* Clear SLEEPDEEP bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+ /* Select Sleep mode entry */
+ if (SleepEntry == PWR_SLEEPENTRY_WFI)
+ {
+ /* Wait For Interrupt Request */
+ __WFI();
+ }
+ else
+ {
+ /* Wait For Event Request */
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+}
+
+/**
+ * @brief Enter the whole system to Stop 0 mode.
+ * @note In Stop 0 mode, the regulator remains in main regulator mode,
+ * allowing a very fast wakeup time but with much higher consumption
+ * comparing to other Stop modes.
+ * @note Stop 0 offers the largest number of active peripherals and wakeup
+ * sources, a smaller wakeup time but a higher consumption.
+ * Stop mode achieves the lowest power consumption while retaining
+ * the content of SRAM and registers. All clocks in the VCORE domain
+ * are stopped. The PLL, the MSI (MSIS and MSIK) RC, the HSI16 RC and
+ * the HSE crystal oscillators are disabled. The LSE or LSI is still
+ * running.
+ * @note The system clock when exiting from Stop mode can be either MSIS up
+ * to 24 MHz or HSI16, depending on software configuration.
+ * @param Regulator : Specifies the regulator state in Stop mode.
+ * This parameter can be one of the following values :
+ * @arg @ref PWR_MAINREGULATOR_ON
+ * @arg @ref PWR_LOWPOWERREGULATOR_ON
+ * @note This parameter is not available in this product.
+ * The parameter is kept just to maintain compatibility with other
+ * products.
+ * @param StopEntry : Specifies if Stop mode is entered with WFI or WFE
+ * instruction.
+ * This parameter can be one of the following values :
+ * @arg @ref PWR_STOPENTRY_WFI enter Stop mode with Wait
+ * For Interrupt request.
+ * @arg @ref PWR_STOPENTRY_WFE enter Stop mode with Wait
+ * For Event request.
+ * @retval None.
+ */
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t StopEntry)
+{
+ UNUSED(Regulator);
+
+ /* Check the parameter */
+ assert_param(IS_PWR_STOP_ENTRY(StopEntry));
+
+ /* Select Stop 0 mode */
+ MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, 0U);
+
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+ /* Select Stop mode entry */
+ if (StopEntry == PWR_STOPENTRY_WFI)
+ {
+ /* Wait For Interrupt Request */
+ __WFI();
+ }
+ else
+ {
+ /* Wait For Event Request */
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+/**
+ * @brief Enter the whole system to Standby mode.
+ * @note The Standby mode is used to achieve the lowest power consumption
+ * with BOR. The internal regulator is switched off so that the VCORE
+ * domain is powered off. The PLL, the MSI (MSIS and MSIK) RC, the
+ * HSI16 RC and the HSE crystal oscillators are also switched off.
+ * @note After entering Standby mode, SRAMs and register contents are lost
+ * except for registers and backup SRAM in the Backup domain and
+ * Standby circuitry. Optionally, the full SRAM2 or 8 Kbytes or 56
+ * Kbytes can be retained in Standby mode, supplied by the low-power
+ * regulator (Standby with RAM2 retention mode) through
+ * HAL_PWREx_EnableSRAM2ContentStandbyRetention().
+ * @note The state of each I/O during Standby mode can be selected by
+ * software : I/O with internal pull-up through
+ * HAL_PWREx_EnableGPIOPullUp() and internal pull-down through
+ * HAL_PWREx_EnableGPIOPullDown().
+ * @retval None.
+ */
+void HAL_PWR_EnterSTANDBYMode(void)
+{
+ /* Select Standby mode */
+ MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_2);
+
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+ /* This option is used to ensure that store operations are completed */
+#if defined ( __CC_ARM)
+ __force_stores();
+#endif /*( __CC_ARM)*/
+
+ /* Wait For Interrupt Request */
+ __WFI();
+}
+
+/**
+ * @brief Indicate SLEEP-ON-EXIT feature when returning from handler mode to
+ * thread mode.
+ * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the
+ * processor re-enters Sleep mode when an interruption handling is over.
+ * Setting this bit is useful when the processor is expected to run
+ * only on interruptions handling.
+ * @retval None.
+ */
+void HAL_PWR_EnableSleepOnExit(void)
+{
+ /* Set SLEEPONEXIT bit of Cortex-M33 System Control Register */
+ SET_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
+}
+
+/**
+ * @brief Disable SLEEP-ON-EXIT feature when returning from handler mode to
+ * thread mode.
+ * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the
+ * processor re-enters Sleep mode when an interruption handling is over.
+ * @retval None.
+ */
+void HAL_PWR_DisableSleepOnExit(void)
+{
+ /* Clear SLEEPONEXIT bit of Cortex-M33 System Control Register */
+ CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
+}
+
+/**
+ * @brief Enable CORTEX SEV-ON-PEND feature.
+ * @note Sets SEVONPEND bit of SCR register. When this bit is set, any
+ * pending event / interrupt even if it's disabled or has insufficient
+ * priority to cause exception entry wakes up the Cortex-M33.
+ * @retval None.
+ */
+void HAL_PWR_EnableSEVOnPend(void)
+{
+ /* Set SEVONPEND bit of Cortex-M33 System Control Register */
+ SET_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);
+}
+
+/**
+ * @brief Disable CORTEX SEVONPEND feature.
+ * @note Resets SEVONPEND bit of SCR register. When this bit is reset, only enabled
+ * pending event / interrupt to cause exception entry wakes up the Cortex-M33.
+ * @retval None.
+ */
+void HAL_PWR_DisableSEVOnPend(void)
+{
+ /* Clear SEVONPEND bit of Cortex-M33 System Control Register */
+ CLEAR_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);
+}
+
+/**
+ * @brief This function handles the PWR PVD interrupt request.
+ * @note This API should be called under the PVD_AVD_IRQHandler().
+ * @retval None.
+ */
+void HAL_PWR_PVD_IRQHandler(void)
+{
+ uint32_t rising_flag;
+ uint32_t falling_flag;
+
+ /* Get pending flags */
+ rising_flag = READ_REG(EXTI->RPR1);
+ falling_flag = READ_REG(EXTI->FPR1);
+
+ /* Check PWR EXTI flags for PVD */
+ if (((rising_flag | falling_flag) & PWR_EXTI_LINE_PVD) != 0U)
+ {
+ /* PWR PVD interrupt user callback */
+ HAL_PWR_PVDCallback();
+
+ /* Clear PVD EXTI pending bit */
+ WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_PVD);
+ WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_PVD);
+ }
+}
+
+/**
+ * @brief PWR PVD interrupt callback.
+ * @retval None.
+ */
+__weak void HAL_PWR_PVDCallback(void)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PWR_PVDCallback can be implemented in the user file
+ */
+}
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Exported_Functions_Group3 Attributes Management Functions
+ * @brief Attributes management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### PWR Attributes Functions #####
+ ===============================================================================
+ [..]
+ When the TrustZone security is activated by the TZEN option bit in the
+ FLASH_OPTR register, some PWR register fields can be secured against
+ non-secure access.
+ The PWR TrustZone security allows the following features to be secured
+ through the PWR_SECCFGR register :
+
+ (++) Low-power mode.
+ (++) Wake-up (WKUP) pins.
+ (++) Voltage detection and monitoring.
+ (++) VBAT mode.
+ (++) I/Os pull-up/pull-down configuration.
+
+ Other PWR configuration bits are secure when :
+ (++) The system clock selection is secure in RCC: the voltage scaling
+ (VOS) configuration and the regulator booster (BOOSTEN) are secure.
+ (++) A GPIO is configured as secure: its corresponding bit for pull-up /
+ pull-down configuration in Standby mode is secure.
+ (++) The UCPD1 is secure in the GTZC: the PWR_UCPDR register is secure.
+
+ A non-secure access to a secure-protected register bit is denied :
+ (++) The secured bits are not written (WI) with a non-secure write access.
+ (++) The secured bits are read as 0 (RAZ) with a non-secure read access.
+
+ [..]
+ When the TrustZone security is disabled (TZEN = 0), PWR_SECCFGR is RAZ/WI
+ and all other registers are non-secure.
+
+ [..]
+ By default, after a reset, all PWR registers can be read or written with
+ both privileged and unprivileged accesses, except PWR_PRIVCFGR that can be
+ written with privileged access only. PWR_PRIVCFGR can be read by secure
+ and non secure, privileged and unprivileged accesses.
+ The SPRIV bit in PWR_PRIVCFGR can be written with secure privileged access
+ only. This bit configures the privileged access of all PWR secure
+ functions (defined by PWR_SECCFGR, GTZC, RCC or GPIO).
+ When the SPRIV bit is set in PWR_PRIVCFGR:
+ (++) The PWR secure bits can be written only with privileged access,
+ including PWR_SECCFGR.
+ (++) The PWR secure bits can be read only with privileged access except
+ PWR_SECCFGR and PWR_PRIVCFGR that can be read by privileged or
+ unprivileged access.
+ (++) An unprivileged access to a privileged PWR bit or register is
+ discarded : the bits are read as zero and the write to these bits is
+ ignored (RAZ/WI).
+ The NSPRIV bit of PWR_PRIVCFGR can be written with privileged access only,
+ secure or non-secure. This bit configures the privileged access of all PWR
+ securable functions that are configured as non-secure (defined by
+ PWR_SECCFGR, GTZC, RCC or GPIO).
+ When the NSPRIV bit is set in PWR_PRIVCFGR :
+ (++) The PWR securable bits that are configured as non-secure, can be
+ written only with privileged access.
+ (++) The PWR securable bits that are configured as non-secure, can be read
+ only with privileged access except PWR_PRIVCFGR that can be read by
+ privileged or unprivileged accesses.
+ (++) The VOSRDY and BOOSTRDY bits in PWR_VOSR, PWR_SR, PWR_SVMSR, PWR_BDSR
+ and PWR_WUSR, can be read with privileged or unprivileged accesses.
+ (++) An unprivileged access to a privileged PWR bit or register is
+ discarded : the bits are read as zero and the write to these bits is
+ ignored (RAZ/WI).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the PWR item attributes.
+ * @note Available attributes are security and privilege protection.
+ * @note Security attribute can only be set only by secure access.
+ * @note Privilege attribute for secure items can be managed only by a secure
+ * privileged access.
+ * @note Privilege attribute for nsecure items can be managed by a secure
+ * privileged access or by a nsecure privileged access.
+ * @param Item : Specifies the item(s) to set attributes on.
+ * This parameter can be a combination of @ref PWR_Items.
+ * @param Attributes : Specifies the available attribute(s).
+ * This parameter can be one of @ref PWR_Attributes.
+ * @retval None.
+ */
+void HAL_PWR_ConfigAttributes(uint32_t Item, uint32_t Attributes)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_ITEMS_ATTRIBUTES(Item));
+ assert_param(IS_PWR_ATTRIBUTES(Attributes));
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ /* Secure item management (TZEN = 1) */
+ if ((Attributes & PWR_ITEM_ATTR_SEC_PRIV_MASK) == PWR_ITEM_ATTR_SEC_PRIV_MASK)
+ {
+ /* Privilege item management */
+ if ((Attributes & PWR_SEC_PRIV) == PWR_SEC_PRIV)
+ {
+ SET_BIT(PWR->SECCFGR, Item);
+ SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV);
+ }
+ else
+ {
+ SET_BIT(PWR->SECCFGR, Item);
+ CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV);
+ }
+ }
+ /* NSecure item management */
+ else
+ {
+ /* Privilege item management */
+ if ((Attributes & PWR_NSEC_PRIV) == PWR_NSEC_PRIV)
+ {
+ CLEAR_BIT(PWR->SECCFGR, Item);
+ SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV);
+ }
+ else
+ {
+ CLEAR_BIT(PWR->SECCFGR, Item);
+ CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV);
+ }
+ }
+#else
+ /* NSecure item management (TZEN = 0) */
+ if ((Attributes & PWR_ITEM_ATTR_NSEC_PRIV_MASK) == PWR_ITEM_ATTR_NSEC_PRIV_MASK)
+ {
+ /* Privilege item management */
+ if ((Attributes & PWR_NSEC_PRIV) == PWR_NSEC_PRIV)
+ {
+ SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV);
+ }
+ else
+ {
+ CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV);
+ }
+ }
+#endif /* __ARM_FEATURE_CMSE */
+}
+
+/**
+ * @brief Get attribute(s) of a PWR item.
+ * @param Item : Specifies the item(s) to get attributes of.
+ * This parameter can be one of @ref PWR_Items.
+ * @param pAttributes : Pointer to return attribute(s).
+ * Returned value could be one of @ref PWR_Attributes.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_PWR_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes)
+{
+ uint32_t attributes;
+
+ /* Check attribute pointer */
+ if (pAttributes == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameter */
+ assert_param(IS_PWR_ITEMS_ATTRIBUTES(Item));
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ /* Check item security */
+ if ((PWR->SECCFGR & Item) == Item)
+ {
+ /* Get Secure privileges attribute */
+ attributes = ((PWR->PRIVCFGR & PWR_PRIVCFGR_SPRIV) == 0U) ? PWR_SEC_NPRIV : PWR_SEC_PRIV;
+ }
+ else
+ {
+ /* Get Non-Secure privileges attribute */
+ attributes = ((PWR->PRIVCFGR & PWR_PRIVCFGR_NSPRIV) == 0U) ? PWR_NSEC_NPRIV : PWR_NSEC_PRIV;
+ }
+#else
+ /* Get Non-Secure privileges attribute */
+ attributes = ((PWR->PRIVCFGR & PWR_PRIVCFGR_NSPRIV) == 0U) ? PWR_NSEC_NPRIV : PWR_NSEC_PRIV;
+#endif /* __ARM_FEATURE_CMSE */
+
+ /* return value */
+ *pAttributes = attributes;
+
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (HAL_PWR_MODULE_ENABLED) */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr_ex.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr_ex.c
new file mode 100644
index 00000000..cc4c4b47
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr_ex.c
@@ -0,0 +1,2402 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_pwr_ex.c
+ * @author MCD Application Team
+ * @brief Extended PWR HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Power Controller extension peripheral :
+ * + Power Supply Control Functions
+ * + Low Power Control Functions
+ * + Voltage Monitoring Functions
+ * + Memories Retention Functions
+ * + I/O Pull-Up Pull-Down Configuration Functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Call HAL_PWREx_ControlVoltageScaling() and HAL_PWREx_GetVoltageRange() to
+ set / get the voltage scaling range.
+ (+) Voltage scaling can be one of the following values :
+ (++) voltage output scale 1 : 1V2
+ => Used when system clock frequency is up to 160 MHz
+ (++) voltage output scale 2 : 1V1
+ => Used when system clock frequency is up to 100 MHz
+ (++) voltage output scale 3 : 1V0
+ => Used when system clock frequency is up to 50 MHz
+ (++) voltage output scale 4 : 0V9
+ => Used when system clock frequency is up to 24 MHz
+
+ (#) Call HAL_PWREx_EnableFastSoftStart() and HAL_PWREx_DisableFastSoftStart()
+ to enable / disable the fast software startup for the current regulator.
+
+ (#) Call HAL_PWREx_EnterSTOP1Mode() function to enter the whole system to
+ Stop 1 mode. Wake-up from Stop 1 mode could be following to an event or
+ an interrupt according to low power mode intrinsic request called
+ (__WFI() or __WFE()). (Regulator state on U5 devices is managed
+ internally but regulator parameter is kept for product compatibility).
+
+ (#) Call HAL_PWREx_EnterSTOP2Mode() function to enter the whole system to
+ Stop 2 mode. Wake-up from Stop 2 mode could be following to an event or
+ an interrupt according to low power mode intrinsic request called
+ (__WFI() or __WFE()). (Regulator state on U5 devices is managed
+ internally but regulator parameter is kept for product compatibility).
+
+ (#) Call HAL_PWREx_EnterSTOP3Mode() function to enter the whole system to
+ Stop 3 mode. Wake-up from Stop 3 mode could be following to an event or
+ an interrupt according to low power mode intrinsic request called
+ (__WFI() or __WFE()). (Regulator state on U5 devices is managed
+ internally but regulator parameter is kept for product compatibility).
+
+ (#) Call HAL_PWREx_EnterSHUTDOWNMode() function to enter the whole system in
+ Shutdown mode. Wake-up from Shutdown mode can be following to an external
+ reset (NRST pin), a WKUP pin event (configurable rising or falling edge),
+ or an RTC event occurs (alarm, periodic wakeup, timestamp), or a tamper
+ detection.
+
+ (#) Call HAL_PWREx_ConfigSRDDomain() to force in Run mode or to enter in Stop
+ mode Smart Run Domain when the system enters Stop mode (Stop 0/1/2).
+
+ (#) Call HAL_PWREx_EnableUltraLowPowerMode() and
+ HAL_PWREx_DisableUltraLowPowerMode() to enable / disable the BOR ultra
+ low power mode.
+
+ (#) Call HAL_PWREx_S3WU_IRQHandler() function to handle the PWR Stop 3 wake
+ up interrupt request.
+
+ (#) Call HAL_PWREx_EnableBatteryCharging() and
+ HAL_PWREx_DisableBatteryCharging() to enable / disable the battery
+ charging capability when VDD alimentation is available.
+
+ (#) Call HAL_PWREx_EnableVddUSB(), HAL_PWREx_EnableVddIO2() and
+ HAL_PWREx_EnableVddA() to enable respectively VDDUSB, VDDIO2 and VDDA
+ electrical and logical isolation.
+ It is recommanded to disable VDDUSB, VDDIO2 and VDDA electrical and
+ logical isolation through HAL_PWREx_DisableVddUSB(),
+ HAL_PWREx_DisableVddIO2() and HAL_PWREx_DisableVddA().
+
+ (#) Call HAL_PWREx_ConfigPVM() after setting parameters to be configured
+ (event mode and PVD type) in order to set up the Peripheral Voltage
+ Monitor, then use HAL_PWREx_EnableUVM(), HAL_PWREx_EnableIO2VM(),
+ HAL_PWREx_EnableAVM1() and HAL_PWREx_EnableAVM2() functions to start the
+ PVM VDDx monitoring and use HAL_PWREx_DisableUVM(),
+ HAL_PWREx_DisableIO2VM(), HAL_PWREx_DisableAVM1() and
+ HAL_PWREx_DisableAVM2() to stop the PVM VDDx monitoring.
+ (+) PVM monitored voltages are :
+ (++) VDDUSB versus 1V2
+ (++) VDDIO2 versus 0V9
+ (++) VDDA versus 1V6
+ (++) VDDA versus 1V8
+
+ (#) Call HAL_PWREx_EnableMonitoring() and HAL_PWREx_DisableMonitoring() to
+ enable / disable the VBAT and temperature monitoring.
+
+ (#) Call HAL_PWREx_EnableUCPDStandbyMode() and
+ HAL_PWREx_DisableUCPDStandbyMode() to enable / disable the UCPD
+ configuration memorization in Standby mode.
+
+ (#) Call HAL_PWREx_EnableUCPDDeadBattery() and
+ HAL_PWREx_DisableUCPDDeadBattery() to enable / disable the dead battery
+ behavior.
+
+ (#) Call HAL_PWREx_PVD_PVM_IRQHandler() function to handle the PWR PVD and
+ PVM interrupt request.
+
+ (#) Call HAL_PWREx_EnableSRAM2ContentStandbyRetention() and
+ HAL_PWREx_DisableSRAM2ContentStandbyRetention() to
+ enable / disable the SRAM2 content retention in Stop 3 and Standby low
+ power modes.
+
+ (#) Call HAL_PWREx_EnableRAMsContentStopRetention() and
+ HAL_PWREx_DisableRAMsContentStopRetention() to
+ enable / disable the RAMs content retention in Stop mode (Stop 0/1/2/3).
+ (+) Retained RAM can be one of the following RAMs :
+ (++) SRAM1
+ (++) SRAM2
+ (++) SRAM3
+ (++) SRAM4
+ (++) ICACHE
+ (++) DMA2DRAM
+ (++) PKA32RAM
+ (++) DCACHE1
+ (++) FMAC
+ (++) FDCAN
+ (++) USB
+
+ (#) Call HAL_PWREx_EnableRAMsContentRunRetention() and
+ HAL_PWREx_DisableRAMsContentRunRetention() to
+ enable / disable the RAMs content retention in Run mode.
+ (+) Retained RAM can be one of the following RAMs :
+ (++) SRAM1
+ (++) SRAM2
+ (++) SRAM3
+ (++) SRAM4
+
+ (#) Call HAL_PWREx_EnableFlashFastWakeUp() and
+ HAL_PWREx_DisableFlashFastWakeUp() to enable / disable the flash memory
+ fast wakeup from Stop mode (Stop 0/1).
+
+ (#) Call HAL_PWREx_EnableSRAM4FastWakeUp() and
+ HAL_PWREx_DisableSRAM4FastWakeUp() to enable / disable the SRAM4 memory
+ fast wakeup from Stop mode (Stop 0/1/2).
+
+ (#) Call HAL_PWREx_EnableBkupRAMRetention() and
+ HAL_PWREx_DisableBkupRAMRetention() to enable / disable the Backup RAM
+ content retention in Standby, Shutdown and VBAT modes.
+
+ (#) Call HAL_PWREx_EnablePullUpPullDownConfig() and
+ HAL_PWREx_DisablePullUpPullDownConfig() to I/O enable / disable pull-up
+ and pull-down configuration.
+
+ (#) Call HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() to
+ apply repectively pull-up and pull-down to selected I/O.
+ Call HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() to
+ disable applied repectively pull-up and pull-down to selected I/O.
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup PWREx PWREx
+ * @brief PWR Extended HAL module driver
+ * @{
+ */
+
+#if defined (HAL_PWR_MODULE_ENABLED)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines
+ * @{
+ */
+/*!< PORTI pins mask */
+#define PWR_PORTI_AVAILABLE_PINS (0xFFU)
+/*!< Time out value of flags setting */
+#define PWR_FLAG_SETTING_DELAY (0x32U)
+
+/** @defgroup PWR_PVM_Mode_Mask PWR PVM Mode Mask
+ * @{
+ */
+#define PVM_RISING_EDGE (0x01U) /*!< Mask for rising edge set as PVM trigger */
+#define PVM_FALLING_EDGE (0x02U) /*!< Mask for falling edge set as PVM trigger */
+#define PVM_MODE_IT (0x04U) /*!< Mask for interruption yielded by PVM threshold crossing */
+#define PVM_MODE_EVT (0x08U) /*!< Mask for event yielded by PVM threshold crossing */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup PWREx_Exported_Functions_Group1 Power Supply Control Functions
+ * @brief Power supply control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Power supply control functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to control power supply.
+
+ [..]
+ (+) The STM32U5 Series devices embed two regulators : one LDO (linear
+ voltage regulator) and one SMPS (step down converter) in parallel to
+ provide the VCORE supply for digital peripherals, SRAM1, SRAM2, SRAM3
+ and SRAM4 and embedded Flash memory.
+
+ (+) The SMPS allows the power consumption to be reduced but some
+ peripherals can be perturbed by the noise generated by the SMPS,
+ requiring the application to switch to LDO when running this
+ peripheral in order to reach the best performances.
+
+ (+) The LDO and the SMPS regulators have two modes: Main regulator mode
+ (used when performance is needed), and Low-power regulator mode. LDO
+ or SMPS can be used in all voltage scaling ranges, and in all Stop
+ modes.
+
+ (+) After reset, the regulator is the LDO, in Range 4. Switching to SMPS
+ provides lower consumption in particular at high VDD voltage. It is
+ possible to switch from LDO to SMPS, or from SMPS to LDO on the fly in
+ any range, by configuring the REGSEL bit. It is recommended to switch
+ first to SMPS before changing the voltage range.
+
+ (+) When exiting the Stop or Standby modes, the regulator is the same than
+ when entering low power modes. The voltage range is the Range 4.
+
+ (+) Both regulators can provide four different voltages (voltage scaling)
+ and can operate in Stop modes.
+ Voltage scaling ranges can be one of the following values :
+ (++) voltage output scale 1 : 1V2
+ => Used when system clock frequency is up to 160 MHz
+ (++) voltage output scale 2 : 1V1
+ => Used when system clock frequency is up to 100 MHz
+ (++) voltage output scale 3 : 1V0
+ => Used when system clock frequency is up to 50 MHz
+ (++) voltage output scale 4 : 0V9
+ => Used when system clock frequency is up to 24 MHz
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the main internal regulator output voltage to achieve
+ * a tradeoff between performance and power consumption.
+ * @param VoltageScaling : Specifies the regulator output voltage scale.
+ * This parameter can be one of the following values :
+ * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output scale 1.
+ * Provides a typical output voltage at 1.2 V.
+ * Used when system clock frequency is up to 160 MHz.
+ * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output scale 2.
+ * Provides a typical output voltage at 1.1 V.
+ * Used when system clock frequency is up to 100 MHz.
+ * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output scale 3.
+ * Provides a typical output voltage at 1.0 V.
+ * Used when system clock frequency is up to 50 MHz.
+ * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE4 : Regulator voltage output scale 4.
+ * Provides a typical output voltage at 0.9 V.
+ * Used when system clock frequency is up to 24 MHz.
+ * @note Before moving to voltage scaling 2, it is mandatory to ensure that
+ * the system frequency is between 50 MHz and 100 MHz.
+ * @note Before moving to voltage scaling 3, it is mandatory to ensure that
+ * the system frequency is between 24 MHz and 50 MHz.
+ * @note Before moving to voltage scaling 4, it is mandatory to ensure that
+ * the system frequency is below 24 MHz.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
+{
+ uint32_t timeout;
+ uint32_t vos_old;
+
+ /* Check the parameter */
+ assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
+
+ /* Get the current voltage scale applied */
+ vos_old = READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOS);
+
+ /* No change, nothing to do */
+ if (vos_old == VoltageScaling)
+ {
+ return HAL_OK;
+ }
+
+ /* Check voltage scaling level */
+ /*
+ * The Embedded power distribution (EPOD) must be enabled before switching to
+ * voltage scale 1 / 2 from voltage scale lower.
+ */
+ if (VoltageScaling > PWR_REGULATOR_VOLTAGE_SCALE3)
+ {
+ MODIFY_REG(PWR->VOSR, (PWR_VOSR_VOS | PWR_VOSR_BOOSTEN), (VoltageScaling | PWR_VOSR_BOOSTEN));
+ }
+ else
+ {
+ MODIFY_REG(PWR->VOSR, (PWR_VOSR_VOS | PWR_VOSR_BOOSTEN), VoltageScaling);
+ }
+
+ /* Wait until VOSRDY is rised */
+ timeout = ((PWR_FLAG_SETTING_DELAY * (SystemCoreClock / 1000U)) / 1000U) + 1U;
+ while (HAL_IS_BIT_CLR(PWR->VOSR, PWR_VOSR_VOSRDY) && (timeout != 0U))
+ {
+ timeout--;
+ }
+
+ /* Check time out */
+ if (timeout != 0U)
+ {
+ /* Wait until ACTVOSRDY is rised */
+ timeout = ((PWR_FLAG_SETTING_DELAY * (SystemCoreClock / 1000U)) / 1000U) + 1U;
+ while ((HAL_IS_BIT_CLR(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY)) && (timeout != 0U))
+ {
+ timeout--;
+ }
+ }
+
+ /* Check time out */
+ if (timeout == 0U)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Return Voltage Scaling Range.
+ * @retval Applied voltage scaling value.
+ */
+uint32_t HAL_PWREx_GetVoltageRange(void)
+{
+ return (PWR->SVMSR & PWR_SVMSR_ACTVOS);
+}
+
+/**
+ * @brief Configure the system Power Supply.
+ * @param SupplySource : Specifies the Power Supply source to set after a
+ * system startup.
+ * This parameter can be one of the following values :
+ * @arg PWR_LDO_SUPPLY : The LDO regulator supplies the Vcore Power Domains.
+ * @arg PWR_SMPS_SUPPLY : The SMPS regulator supplies the Vcore Power Domains.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource)
+{
+ uint32_t timeout;
+
+ /* Check the parameter */
+ assert_param(IS_PWR_SUPPLY(SupplySource));
+
+ /* Set maximum time out */
+ timeout = ((PWR_FLAG_SETTING_DELAY * (SystemCoreClock / 1000U)) / 1000U) + 1U;
+
+ /* Configure the LDO as system regulator supply */
+ if (SupplySource == PWR_LDO_SUPPLY)
+ {
+ /* Set the power supply configuration */
+ CLEAR_BIT(PWR->CR3, PWR_CR3_REGSEL);
+
+ /* Wait until system switch on new regulator */
+ while (HAL_IS_BIT_SET(PWR->SVMSR, PWR_SVMSR_REGS) && (timeout != 0U))
+ {
+ timeout--;
+ }
+ }
+ /* Configure the SMPS as system regulator supply */
+ else
+ {
+ /* Set the power supply configuration */
+ SET_BIT(PWR->CR3, PWR_CR3_REGSEL);
+
+ /* Wait until system switch on new regulator */
+ while (HAL_IS_BIT_CLR(PWR->SVMSR, PWR_SVMSR_REGS) && (timeout != 0U))
+ {
+ timeout--;
+ }
+ }
+
+ /* Check time out */
+ if (timeout == 0U)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get the power supply configuration.
+ * @retval The supply configured.
+ */
+uint32_t HAL_PWREx_GetSupplyConfig(void)
+{
+ return (PWR->SVMSR & PWR_SVMSR_REGS);
+}
+
+/**
+ * @brief Enable fast soft start for the current regulator.
+ * @retval None.
+ */
+void HAL_PWREx_EnableFastSoftStart(void)
+{
+ SET_BIT(PWR->CR3, PWR_CR3_FSTEN);
+}
+
+/**
+ * @brief Disable fast soft start for the current regulator.
+ * @retval None.
+ */
+void HAL_PWREx_DisableFastSoftStart(void)
+{
+ CLEAR_BIT(PWR->CR3, PWR_CR3_FSTEN);
+}
+/**
+ * @}
+ */
+
+
+/** @defgroup PWREx_Exported_Functions_Group2 Low Power Control Functions
+ * @brief Low power control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Low power control functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to control low power modes.
+
+ *** Low Power modes configuration ***
+ =====================================
+ [..]
+ This section presents 4 principles low power modes :
+ (+) Stop 1 mode : Cortex-M33 is stopped, clocks are stopped and the
+ regulator is in low power mode. Several peripheral can
+ operate in this mode.
+
+ (+) Stop 2 mode : Cortex-M33 is stopped, clocks are stopped and the
+ regulator is in low power mode. Only autonomous
+ peripherals can operate in this mode.
+
+ (+) Stop 3 mode : Cortex-M33 is stopped, clocks are stopped and the
+ regulator is in low power mode. No peripheral can
+ operate in this mode. Only RAMs content is preserved.
+
+ (+) Shutdown mode : All PWR domains enter Shutdown mode and the VCORE
+ supply regulator is powered off. The SRAMs and
+ register contents are lost except for registers in the
+ Backup domain.
+
+ *** Stop 1 mode ***
+ ===================
+ [..]
+ The Stop 1 mode is based on the Cortex-M33 Deepsleep mode combined with
+ the peripheral clock gating. The voltage regulator is configured in low
+ power mode. In Stop 1 mode, all clocks in the VCORE domain are stopped.
+ The PLL, MSIS, MSIK, HSI16 and HSE oscillators are disabled.
+ Some peripherals with the LPBAM capability can switch on HSI16 or MSIS or
+ MSIK for transferring data. All SRAMs and register contents are preserved,
+ but the SRAMs can be totally or partially switched off to further reduced
+ consumption.
+ The BOR is always available in Stop 1 mode.
+
+ (+) Entry:
+ The Stop 1 mode is entered by using the HAL_PWREx_EnterSTOP1Mode()
+ function.
+
+ (++) PWR_STOPENTRY_WFI: enter Stop 1 mode with WFI instruction.
+ (++) PWR_STOPENTRY_WFE: enter Stop 1 mode with WFE instruction.
+
+ (+) Exit:
+ Any EXTI line configured in interrupt mode (the corresponding EXTI
+ interrupt vector must be enabled in the NVIC). The interrupt source
+ can be external interrupts or peripherals with wakeup capability.
+ Any peripheral interrupt occurring when the AHB/APB clocks are present
+ due to an autonomous peripheral clock request (the peripheral vector
+ must be enabled in the NVIC)
+ Any EXTI line configured in event mode.
+
+ *** Stop 2 mode ***
+ ===================
+ [..]
+ The Stop 2 mode is based on the Cortex-M33 Deepsleep mode combined with
+ peripheral clock gating. In Stop 2 mode, all clocks in the VCORE domain
+ are stopped.
+ The PLL, MSIS, MSIK, HSI16 and HSE oscillators are disabled.
+ Some peripherals with the LPBAM capability can switch on HSI16 or MSIS or
+ MSIK for transferring data. All SRAMs and register contents are preserved,
+ but the SRAMs can be totally or partially switched off to further reduce
+ consumption.
+ The BOR is always available in Stop 2 mode.
+
+ (+) Entry:
+ The Stop 2 mode is entered by using the HAL_PWREx_EnterSTOP2Mode()
+ function.
+
+ (++) PWR_STOPENTRY_WFI: enter Stop 2 mode with WFI instruction.
+ (++) PWR_STOPENTRY_WFE: enter Stop 2 mode with WFE instruction.
+
+ (+) Exit:
+ Any EXTI line configured in interrupt mode (the corresponding EXTI
+ interrupt vector must be enabled in the NVIC). The interrupt source
+ can be external interrupts or peripherals with wakeup capability.
+ Any peripheral interrupt occurring when the AHB/APB clocks are present
+ due to an autonomous peripheral clock request (the peripheral vector
+ must be enabled in the NVIC)
+ Any EXTI line configured in event mode.
+
+ *** Stop 3 mode ***
+ ===================
+ [..]
+ The Stop 3 mode is based on the Cortex�-M33 Deepsleep mode combined with
+ peripheral clock gating. In Stop 3 mode, all clocks in the VCORE domain
+ are stopped.
+ The PLL, MSIS, MSIK, HSI16 and HSE oscillators are disabled.
+ All SRAMs and register contents are preserved, but the SRAMs can be
+ totally or partially switched off to further reduce consumption.
+ The BOR is always available in Stop 3 mode.
+
+ (+) Entry:
+ The Stop 3 mode is entered by using the HAL_PWREx_EnterSTOP3Mode()
+ function.
+
+ (++) PWR_STOPENTRY_WFI: enter Stop 3 mode with WFI instruction.
+ (++) PWR_STOPENTRY_WFE: enter Stop 3 mode with WFE instruction.
+
+ (+) Exit:
+ WKUPx pin edge, RTC or TAMP event, external Reset in NRST pin, IWDG
+ Reset, BOR reset.
+
+ *** Shutdown mode ***
+ ====================
+ [..]
+ The lowest power consumption is reached in Shutdown mode. It is based on
+ the Deepsleep mode with the voltage regulator disabled. The VCORE domain
+ is consequently powered off.
+ The PLL, HSI16, MSIS, MSIK and HSE oscillators are also switched off.
+ The SRAMs and register contents are lost except for registers in the
+ Backup domain.
+ The BOR is not available in Shutdown mode.
+ No power voltage monitoring is possible in this mode, therefore the switch
+ to Backup domain is not supported.
+
+ (+) Entry:
+ The Shutdown mode is entered by using the HAL_PWREx_EnterSHUTDOWNMode()
+ function.
+
+ (+) Exit:
+ WKUPx pin edge, RTC/TAMP event, external Reset in NRST pin.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enter the whole system to Stop 1 mode.
+ * @note Stop 1 offers the largest number of active peripherals and wakeup
+ * sources, a smaller wakeup time but a higher consumption.
+ * @note Stop mode achieves the lowest power consumption while retaining
+ * the content of SRAM and registers. All clocks in the VCORE domain
+ * are stopped. The PLL, the MSI (MSIS and MSIK) RC, the HSI16 RC and
+ * the HSE crystal oscillators are disabled. The LSE or LSI is still
+ * running.
+ * @note The system clock when exiting from Stop mode can be either MSIS up
+ * to 24 MHz or HSI16, depending on software configuration.
+ * @param STOPEntry : Specifies if Stop mode is entered with WFI or WFE
+ * instruction.
+ * This parameter can be one of the following values :
+ * @arg @ref PWR_STOPENTRY_WFI enter Stop mode with Wait
+ * For Interrupt request.
+ * @arg @ref PWR_STOPENTRY_WFE enter Stop mode with Wait
+ * For Event request.
+ * @retval None.
+ */
+void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
+
+ /* Stop 1 mode */
+ MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_0);
+
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+ /* Select Stop mode entry */
+ if (STOPEntry == PWR_STOPENTRY_WFI)
+ {
+ /* Request Wait For Interrupt */
+ __WFI();
+ }
+ else
+ {
+ /* Request Wait For Event */
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+/**
+ * @brief Enter the whole system to Stop 2 mode.
+ * @note In Stop 2 mode, all clocks in the VCORE domain are stopped. The PLL,
+ * MSIS, MSIK, HSI16 and HSE oscillators are disabled.
+ * @note Stop mode achieves the lowest power consumption while retaining
+ * the content of SRAM and registers. All clocks in the VCORE domain
+ * are stopped. The PLL, the MSI (MSIS and MSIK) RC, the HSI16 RC and
+ * the HSE crystal oscillators are disabled. The LSE or LSI is still
+ * running.
+ * @note The system clock when exiting from Stop mode can be either MSIS up
+ * to 24 MHz or HSI16, depending on software configuration.
+ * @param STOPEntry : Specifies if Stop mode is entered with WFI or WFE
+ * instruction.
+ * This parameter can be one of the following values :
+ * @arg @ref PWR_STOPENTRY_WFI enter Stop mode with Wait
+ * For Interrupt request.
+ * @arg @ref PWR_STOPENTRY_WFE enter Stop mode with Wait
+ * For Event request.
+ * @retval None.
+ */
+void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
+
+ /* Stop 2 mode */
+ MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_1);
+
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+ /* Select Stop mode entry */
+ if (STOPEntry == PWR_STOPENTRY_WFI)
+ {
+ /* Request Wait For Interrupt */
+ __WFI();
+ }
+ else
+ {
+ /* Request Wait For Event */
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+/**
+ * @brief Enter the whole system to Stop 3 mode.
+ * @note Stop 3 is the lowest power mode with full retention, but the
+ * functional peripherals and sources of wakeup are reduced to the same
+ * ones than in Standby mode.
+ * @note Stop mode achieves the lowest power consumption while retaining
+ * the content of SRAM and registers. All clocks in the VCORE domain
+ * are stopped. The PLL, the MSI (MSIS and MSIK) RC, the HSI16 RC and
+ * the HSE crystal oscillators are disabled. The LSE or LSI is still
+ * running.
+ * @note The system clock when exiting from Stop mode can be either MSIS up
+ * to 24 MHz or HSI16, depending on software configuration.
+ * @param STOPEntry : Specifies if Stop mode is entered with WFI or WFE
+ * instruction.
+ * This parameter can be one of the following values :
+ * @arg @ref PWR_STOPENTRY_WFI enter Stop mode with Wait
+ * For Interrupt request.
+ * @arg @ref PWR_STOPENTRY_WFE enter Stop mode with Wait
+ * For Event request.
+ * @retval None.
+ */
+void HAL_PWREx_EnterSTOP3Mode(uint8_t STOPEntry)
+{
+ /* Check the parameter */
+ assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
+
+ /* Set Stop mode 3 */
+ MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1));
+
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+ /* Select Stop mode entry */
+ if (STOPEntry == PWR_STOPENTRY_WFI)
+ {
+ /* Request Wait For Interrupt */
+ __WFI();
+ }
+ else
+ {
+ /* Request Wait For Event */
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+/**
+ * @brief Enter the whole system to Shutdown mode.
+ * @note Shutdown mode allows the lowest power consumption. The internal
+ * regulator is switched off so that the VCORE domain is powered off.
+ * The PLL, the HSI16, the MSI (MSIS and MSIK), the LSI and the HSE
+ * oscillators are also switched off.
+ * @note The SRAMs and register contents are lost except for registers in the
+ * Backup domain. The BOR is not available in Shutdown mode. No power
+ * voltage monitoring is possible in this mode, therefore the switch to
+ * Backup domain is not supported.
+ * @retval None.
+ */
+void HAL_PWREx_EnterSHUTDOWNMode(void)
+{
+ /* Set Shutdown mode */
+ MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, (PWR_CR1_LPMS_1 | PWR_CR1_LPMS_2));
+
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+ /* This option is used to ensure that store operations are completed */
+#if defined (__CC_ARM)
+ __force_stores();
+#endif /* (__CC_ARM)*/
+ /* Request Wait For Interrupt */
+ __WFI();
+}
+
+/**
+ * @brief Configure the SRD domain when the System in Stop 0/1/2 mode.
+ * @param SRDState : Specifies the SRD state.
+ * This parameter can be one of the following values :
+ * @arg PWR_SRD_DOMAIN_STOP : SRD in Stop mode when system
+ * goes to Stop 0/1/2 mode
+ * @arg PWR_SRD_DOMAIN_RUN : SRD in Run mode when system
+ * goes to Stop 0/1/2 mode
+ * @retval None.
+ */
+void HAL_PWREx_ConfigSRDDomain(uint32_t SRDState)
+{
+ /* Check the parameter */
+ assert_param(IS_PWR_SRD_STATE(SRDState));
+
+ /* Config the SRD domain */
+ MODIFY_REG(PWR->CR2, PWR_CR2_SRDRUN, SRDState);
+}
+
+/**
+ * @brief Enable BOR ultra-low power mode.
+ * @note BOR operating can be in discontinuous (ultra-low power) mode in
+ * Stop 1, Stop 2, Stop 3 and Standby modes and when the regulator is
+ * in Range 4 (Run, Sleep or Stop 0 mode).
+ * @retval None.
+ */
+void HAL_PWREx_EnableUltraLowPowerMode(void)
+{
+ SET_BIT(PWR->CR1, PWR_CR1_ULPMEN);
+}
+
+/**
+ * @brief Disable BOR ultra-low power mode.
+ * @retval None.
+ */
+void HAL_PWREx_DisableUltraLowPowerMode(void)
+{
+ CLEAR_BIT(PWR->CR1, PWR_CR1_ULPMEN);
+}
+
+/**
+ * @brief This function handles the PWR Wake up from Stop 3 interrupt request.
+ * @note This API should be called under the PWR_S3WU_IRQHandler().
+ * @param WakeUpPin : Specifies the wakeup pin interrupt to be handled.
+ * This parameter can be a combination of @ref PWR_WakeUp_Pins.
+ * @retval None.
+ */
+void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin)
+{
+ /* Check PWR wake up line 1 */
+ if ((WakeUpPin & PWR_WAKEUP_PIN1) != 0U)
+ {
+ if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) != 0U)
+ {
+ /* Clear PWR wake up flag line 1 */
+ SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF1);
+
+ /* PWR S3WU interrupt user callback */
+ HAL_PWREx_S3WUCallback(WakeUpPin);
+ }
+ }
+
+ /* Check PWR wake up line 2 */
+ if ((WakeUpPin & PWR_WAKEUP_PIN2) != 0U)
+ {
+ if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) != 0U)
+ {
+ /* Clear PWR wake up flag line 2 */
+ SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF2);
+
+ /* PWR S3WU interrupt user callback */
+ HAL_PWREx_S3WUCallback(WakeUpPin);
+ }
+ }
+
+ /* Check PWR wake up line 3 */
+ if ((WakeUpPin & PWR_WAKEUP_PIN3) != 0U)
+ {
+ if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) != 0U)
+ {
+ /* Clear PWR wake up flag line 3 */
+ SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF3);
+
+ /* PWR S3WU interrupt user callback */
+ HAL_PWREx_S3WUCallback(WakeUpPin);
+ }
+ }
+
+ /* Check PWR wake up line 4 */
+ if ((WakeUpPin & PWR_WAKEUP_PIN4) != 0U)
+ {
+ if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) != 0U)
+ {
+ /* Clear PWR wake up flag line 4 */
+ SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF4);
+
+ /* PWR S3WU interrupt user callback */
+ HAL_PWREx_S3WUCallback(WakeUpPin);
+ }
+ }
+
+ /* Check PWR wake up line 5 */
+ if ((WakeUpPin & PWR_WAKEUP_PIN5) != 0U)
+ {
+ if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) != 0U)
+ {
+ /* Clear PWR wake up flag line 5 */
+ SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF5);
+
+ /* PWR S3WU interrupt user callback */
+ HAL_PWREx_S3WUCallback(WakeUpPin);
+ }
+ }
+
+ /* Check PWR wake up line 6 */
+ if ((WakeUpPin & PWR_WAKEUP_PIN6) != 0U)
+ {
+ if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) != 0U)
+ {
+ /* Clear PWR wake up flag line 6 */
+ SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF6);
+
+ /* PWR S3WU interrupt user callback */
+ HAL_PWREx_S3WUCallback(WakeUpPin);
+ }
+ }
+
+ /* Check PWR wake up line 7 */
+ if ((WakeUpPin & PWR_WAKEUP_PIN7) != 0U)
+ {
+ if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) != 0U)
+ {
+ /* Clear PWR wake up flag line 7 */
+ SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF7);
+
+ /* PWR S3WU interrupt user callback */
+ HAL_PWREx_S3WUCallback(WakeUpPin);
+ }
+ }
+
+ /* Check PWR wake up line 8 */
+ if ((WakeUpPin & PWR_WAKEUP_PIN8) != 0U)
+ {
+ if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) != 0U)
+ {
+ /* Clear PWR wake up flag line 8 */
+ SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF8);
+
+ /* PWR S3WU interrupt user callback */
+ HAL_PWREx_S3WUCallback(WakeUpPin);
+ }
+ }
+}
+
+/**
+ * @brief PWR S3WU interrupt callback.
+ * @param WakeUpPin : Specifies the wakeup pin interrupt to be handled.
+ * This parameter can be a combination of @ref PWR_WakeUp_Pins.
+ * @retval None.
+ */
+__weak void HAL_PWREx_S3WUCallback(uint32_t WakeUpPin)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(WakeUpPin);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ HAL_PWREx_S3WU_IRQHandler() API can be implemented in the user file
+ */
+}
+/**
+ * @}
+ */
+
+/** @defgroup PWREx_Exported_Functions_Group3 Voltage Monitoring Functions
+ * @brief Voltage monitoring functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Voltage Monitoring Functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing voltage monitoring.
+
+ *** PVM configuration ***
+ =========================
+ [..]
+ (+) The supplies (VDDA, VDDIO2 and VDDUSB) can be independent from VDD and
+ can be monitored with four peripheral voltage monitoring (PVM):
+
+ (++) The UVM monitors the USB supply VDDUSB. VDDUSBRDY indicates if
+ the VDDUSB independent power supply is higher or lower than the
+ VUVM threshold.
+ (++) The IO2VM monitors the PG[15:2] supply VDDIO2. VDDIO2RDY
+ indicates if the VDDIO2 independent power supply is higher or
+ lower than the VIO2VM threshold.
+ (++) The AVM1 monitors the analog supply VDDA. VDDA1RDY indicates if
+ the VDDA independent power supply is higher or lower than the
+ VAVM1 threshold.
+ (++) The AVM2 monitors the analog supply VDDA. VDDA2RDY indicates if
+ the VDDA independent power supply is higher or lower than the
+ VAVM2 threshold.
+
+ (+) Each PVM output is connected to an EXTI line and can generate an
+ interrupt if enabled through the EXTI registers. The PVMx output
+ interrupt is generated when the independent power supply drops below
+ the PVM threshold and/or when it rises above the PVM threshold,
+ depending on EXTI line rising/falling edge configuration.
+
+ (+) Each PVM can remain active in Stop 0, Stop 1, Stop 2 modes, and the
+ PVM interrupt can wake up from the Stop mode. The PVM is not
+ functional in Stop 3 mode.
+
+ *** VBAT charging ***
+ =====================
+ [..]
+ When VDD is present, it is possible to charge the external battery on VBAT
+ through an internal resistance.
+ The VBAT charging is done either through a 5 kOhm resistor or through a 1.5
+ kOhm resistor depending on the VBRS bit value in the PWR_BDCR2 register.
+ The battery charging is enabled by setting VBE bit in the PWR_BDCR2
+ register. It is automatically disabled in VBAT mode.
+
+ *** Backup domain monitoring ***
+ ================================
+ [..]
+ When the Backup domain voltage and temperature monitoring is enabled
+ (MONEN = 1 in the PWR_BDCR1 register), the Backup domain voltage and the
+ temperature are monitored.
+ If the Backup domain voltage monitoring internal tamper is enabled in the
+ TAMP peripheral (ITAMP1E = 1 in the TAMP_CR1 register), a tamper event is
+ generated when the Backup domain voltage is above the functional range.
+ In case the Backup domain voltage is below the functional range,
+ a Brownout reset is generated, erasing all device including Backup domain.
+
+ *** Backup domain battery ***
+ =============================
+ [..]
+ (+) To retain the content of the backup registers and supply the RTC
+ function when VDD is turned off, the VBAT pin can be connected to an
+ optional backup voltage supplied by a battery or by another source.
+ The VBAT pin powers the RTC unit, the LSE oscillator and the PC13 to
+ PC15 I/Os, allowing the RTC to operate even when the main power supply
+ is turned off. The backup SRAM is optionally powered by VBAT pin when
+ the BREN bit is set in the PWR Backup domain control register 1
+ (PWR_BDCR1).
+ The switch to the VBAT supply is controlled by the power down reset
+ embedded in the Reset block.
+
+ (+) After exiting reset, the USB Type-C �dead battery� behavior is enabled,
+ which may have a pull-down effect on CC1 and CC2 pins. It is
+ recommended to disable it in all cases, either to stop this pull-down
+ or to handover control to the UCPD (the UCPD must be initialized
+ before doing the disable).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the voltage monitor threshold detected by the Peripheral
+ * voltage monitoring (PVM).
+ * @param pConfigPVM : Pointer to a PWR_PVMTypeDef structure that contains the
+ * PVM configuration information (PVMType and EventMode).
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *pConfigPVM)
+{
+ /* Check the PVM parameter */
+ if (pConfigPVM == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_PWR_PVM_TYPE(pConfigPVM->PVMType));
+ assert_param(IS_PWR_PVM_MODE(pConfigPVM->Mode));
+
+ /* Check the peripheral voltage monitor type */
+ switch (pConfigPVM->PVMType)
+ {
+ case PWR_UVM: /* Independent USB voltage monitor */
+
+ /* Disable EXTI UVM event and interrupt */
+ __HAL_PWR_UVM_EXTI_DISABLE_EVENT();
+ __HAL_PWR_UVM_EXTI_DISABLE_IT();
+ __HAL_PWR_UVM_EXTI_DISABLE_RISING_EDGE();
+ __HAL_PWR_UVM_EXTI_DISABLE_FALLING_EDGE();
+
+ /* Configure the UVM in interrupt mode */
+ if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
+ {
+ __HAL_PWR_UVM_EXTI_ENABLE_IT();
+ }
+
+ /* Configure the UVM in event mode */
+ if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
+ {
+ __HAL_PWR_UVM_EXTI_ENABLE_EVENT();
+ }
+
+ /* Configure the UVM in rising edge */
+ if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
+ {
+ __HAL_PWR_UVM_EXTI_ENABLE_RISING_EDGE();
+ }
+
+ /* Configure the UVM in falling edge */
+ if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
+ {
+ __HAL_PWR_UVM_EXTI_ENABLE_FALLING_EDGE();
+ }
+
+ break;
+
+ case PWR_IO2VM: /* Independent I/Os voltage monitor */
+
+ /* Disable EXTI IO2VM event and interrupt */
+ __HAL_PWR_IO2VM_EXTI_DISABLE_EVENT();
+ __HAL_PWR_IO2VM_EXTI_DISABLE_IT();
+ __HAL_PWR_IO2VM_EXTI_DISABLE_RISING_EDGE();
+ __HAL_PWR_IO2VM_EXTI_DISABLE_FALLING_EDGE();
+
+ /* Configure the IO2VM in interrupt mode */
+ if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
+ {
+ __HAL_PWR_IO2VM_EXTI_ENABLE_IT();
+ }
+
+ /* Configure the IO2VM in event mode */
+ if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
+ {
+ __HAL_PWR_IO2VM_EXTI_ENABLE_EVENT();
+ }
+
+ /* Configure the IO2VM in rising edge */
+ if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
+ {
+ __HAL_PWR_IO2VM_EXTI_ENABLE_RISING_EDGE();
+ }
+
+ /* Configure the IO2VM in falling edge */
+ if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
+ {
+ __HAL_PWR_IO2VM_EXTI_ENABLE_FALLING_EDGE();
+ }
+
+ break;
+
+ case PWR_AVM1: /* VDDA Independent analog supply voltage monitor 1 (1.6V threshold) */
+
+ /* Disable EXTI AVM1 event and interrupt */
+ __HAL_PWR_AVM1_EXTI_DISABLE_EVENT();
+ __HAL_PWR_AVM1_EXTI_DISABLE_IT();
+ __HAL_PWR_AVM1_EXTI_DISABLE_RISING_EDGE();
+ __HAL_PWR_AVM1_EXTI_DISABLE_FALLING_EDGE();
+
+ /* Configure the AVM1 in interrupt mode */
+ if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
+ {
+ __HAL_PWR_AVM1_EXTI_ENABLE_IT();
+ }
+
+ /* Configure the AVM1 in event mode */
+ if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
+ {
+ __HAL_PWR_AVM1_EXTI_ENABLE_EVENT();
+ }
+
+ /* Configure the AVM1 in rising edge */
+ if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
+ {
+ __HAL_PWR_AVM1_EXTI_ENABLE_RISING_EDGE();
+ }
+
+ /* Configure the AVM1 in falling edge */
+ if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
+ {
+ __HAL_PWR_AVM1_EXTI_ENABLE_FALLING_EDGE();
+ }
+
+ break;
+
+ case PWR_AVM2: /* VDDA Independent analog supply voltage monitor 2 (1.8V threshold) */
+
+ /* Disable EXTI AVM2 event and interrupt */
+ __HAL_PWR_AVM2_EXTI_DISABLE_EVENT();
+ __HAL_PWR_AVM2_EXTI_DISABLE_IT();
+ __HAL_PWR_AVM2_EXTI_DISABLE_RISING_EDGE();
+ __HAL_PWR_AVM2_EXTI_DISABLE_FALLING_EDGE();
+
+ /* Configure the AVM2 in interrupt mode */
+ if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
+ {
+ __HAL_PWR_AVM2_EXTI_ENABLE_IT();
+ }
+
+ /* Configure the AVM2 in event mode */
+ if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
+ {
+ __HAL_PWR_AVM2_EXTI_ENABLE_EVENT();
+ }
+
+ /* Configure the AVM2 in rising edge */
+ if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
+ {
+ __HAL_PWR_AVM2_EXTI_ENABLE_RISING_EDGE();
+ }
+
+ /* Configure the AVM2 in falling edge */
+ if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
+ {
+ __HAL_PWR_AVM2_EXTI_ENABLE_FALLING_EDGE();
+ }
+
+ break;
+
+ default: /* No valid voltage monitor selected */
+ return HAL_ERROR;
+ break;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable VDDUSB supply.
+ * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply
+ * is present for consumption saving.
+ * @retval None.
+ */
+void HAL_PWREx_EnableVddUSB(void)
+{
+ SET_BIT(PWR->SVMCR, PWR_SVMCR_USV);
+}
+
+/**
+ * @brief Disable VDDUSB supply.
+ * @retval None.
+ */
+void HAL_PWREx_DisableVddUSB(void)
+{
+ CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_USV);
+}
+
+/**
+ * @brief Enable VDDIO2 supply.
+ * @note Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply
+ * is present for consumption saving.
+ * @retval None.
+ */
+void HAL_PWREx_EnableVddIO2(void)
+{
+ SET_BIT(PWR->SVMCR, PWR_SVMCR_IO2SV);
+}
+
+/**
+ * @brief Disable VDDIO2 supply.
+ * @retval None.
+ */
+void HAL_PWREx_DisableVddIO2(void)
+{
+ CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_IO2SV);
+}
+
+/**
+ * @brief Enable VDDA supply.
+ * @note Remove VDDA electrical and logical isolation, once VDDA supply is
+ * present for consumption saving.
+ * @retval None.
+ */
+void HAL_PWREx_EnableVddA(void)
+{
+ SET_BIT(PWR->SVMCR, PWR_SVMCR_ASV);
+}
+
+/**
+ * @brief Disable VDDA supply.
+ * @retval None.
+ */
+void HAL_PWREx_DisableVddA(void)
+{
+ CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_ASV);
+}
+
+/**
+ * @brief Enable the UVM Voltage Monitoring : VDDUSB versus 1.2 V.
+ * @retval None.
+ */
+void HAL_PWREx_EnableUVM(void)
+{
+ SET_BIT(PWR->SVMCR, PWR_SVMCR_UVMEN);
+}
+
+/**
+ * @brief Disable the UVM Voltage Monitoring : VDDUSB versus 1.2 V.
+ * @retval None.
+ */
+void HAL_PWREx_DisableUVM(void)
+{
+ CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_UVMEN);
+}
+
+/**
+ * @brief Enable the IO2VM Voltage Monitoring : VDDIO2 versus 0.9 V.
+ * @retval None.
+ */
+void HAL_PWREx_EnableIO2VM(void)
+{
+ SET_BIT(PWR->SVMCR, PWR_SVMCR_IO2VMEN);
+}
+
+/**
+ * @brief Disable the IO2VM Voltage Monitoring : VDDIO2 versus 0.9 V.
+ * @retval None.
+ */
+void HAL_PWREx_DisableIO2VM(void)
+{
+ CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_IO2VMEN);
+}
+
+/**
+ * @brief Enable the AVM1 Voltage Monitoring : VDDA versus 1.6 V.
+ * @retval None.
+ */
+void HAL_PWREx_EnableAVM1(void)
+{
+ SET_BIT(PWR->SVMCR, PWR_SVMCR_AVM1EN);
+}
+
+/**
+ * @brief Disable the AVM1 Voltage Monitoring : VDDA versus 1.6 V.
+ * @retval None.
+ */
+void HAL_PWREx_DisableAVM1(void)
+{
+ CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_AVM1EN);
+}
+
+/**
+ * @brief Enable the AVM2 Voltage Monitoring : VDDA versus 1.8 V.
+ * @retval None.
+ */
+void HAL_PWREx_EnableAVM2(void)
+{
+ SET_BIT(PWR->SVMCR, PWR_SVMCR_AVM2EN);
+}
+
+/**
+ * @brief Disable the AVM2 Voltage Monitoring : VDDA versus 1.8 V.
+ * @retval None.
+ */
+void HAL_PWREx_DisableAVM2(void)
+{
+ CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_AVM2EN);
+}
+
+/**
+ * @brief Enable the VBAT and temperature monitoring.
+ * @retval None.
+ */
+void HAL_PWREx_EnableMonitoring(void)
+{
+ SET_BIT(PWR->BDCR1, PWR_BDCR1_MONEN);
+}
+
+/**
+ * @brief Disable the VBAT and temperature monitoring.
+ * @retval None.
+ */
+void HAL_PWREx_DisableMonitoring(void)
+{
+ CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_MONEN);
+}
+
+/**
+ * @brief Enable UCPD configuration memorization in Standby mode.
+ * @retval None.
+ */
+void HAL_PWREx_EnableUCPDStandbyMode(void)
+{
+ SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STDBY);
+}
+
+/**
+ * @brief Disable UCPD configuration memorization in Standby mode.
+ * @note This function must be called on exiting the Standby mode and before
+ * any UCPD configuration update.
+ * @retval None.
+ */
+void HAL_PWREx_DisableUCPDStandbyMode(void)
+{
+ CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STDBY);
+}
+
+/**
+ * @brief Enable dead battery behavior.
+ * @note After exiting reset, the USB Type-C �dead battery� behavior is
+ * enabled, which may have a pull-down effect on CC1 and CC2 pins.
+ * It is recommended to disable it in all cases, either to stop this
+ * pull-down or to handover control to the UCPD (the UCPD must be
+ * initialized before doing the disable).
+ * @retval None.
+ */
+void HAL_PWREx_EnableUCPDDeadBattery(void)
+{
+ CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS);
+}
+
+/**
+ * @brief Disable dead battery behavior.
+ * @note After exiting reset, the USB Type-C �dead battery� behavior is
+ * enabled, which may have a pull-down effect on CC1 and CC2 pins.
+ * It is recommended to disable it in all cases, either to stop this
+ * pull-down or to handover control to the UCPD (the UCPD must be
+ * initialized before doing the disable).
+ * @retval None.
+ */
+void HAL_PWREx_DisableUCPDDeadBattery(void)
+{
+ SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS);
+}
+
+/**
+ * @brief Enable the Battery charging.
+ * @note When VDD is present, charge the external battery through an internal
+ * resistor.
+ * @param ResistorValue : Specifies the charging resistor.
+ * This parameter can be one of the following values :
+ * @arg PWR_BATTERY_CHARGING_RESISTOR_5 : 5 KOhm resistor.
+ * @arg PWR_BATTERY_CHARGING_RESISTOR_1_5 : 1.5 KOhm resistor.
+ * @retval None.
+ */
+void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue)
+{
+ /* Check the parameter */
+ assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorValue));
+
+ /* Specify the charging resistor */
+ MODIFY_REG(PWR->BDCR2, PWR_BDCR2_VBRS, ResistorValue);
+
+ /* Enable the Battery charging */
+ SET_BIT(PWR->BDCR2, PWR_BDCR2_VBE);
+}
+
+/**
+ * @brief Disable the Battery charging.
+ * @retval None.
+ */
+void HAL_PWREx_DisableBatteryCharging(void)
+{
+ CLEAR_BIT(PWR->BDCR2, PWR_BDCR2_VBE);
+}
+
+/**
+ * @brief This function handles the PWR PVD/PVM interrupt request.
+ * @note This API should be called under the PVD_PVM_IRQHandler().
+ * @retval None.
+ */
+void HAL_PWREx_PVD_PVM_IRQHandler(void)
+{
+ uint32_t rising_flag;
+ uint32_t falling_flag;
+
+ /* Get pending flags */
+ rising_flag = READ_REG(EXTI->RPR1);
+ falling_flag = READ_REG(EXTI->FPR1);
+
+ /* Check PWR exti flags for PVD */
+ if (((rising_flag | falling_flag) & PWR_EXTI_LINE_PVD) != 0U)
+ {
+ /* PWR PVD interrupt user callback */
+ HAL_PWR_PVDCallback();
+
+ /* Clear PVD exti pending bit */
+ WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_PVD);
+ WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_PVD);
+ }
+
+ /* Check PWR exti flags for UVM */
+ if (((rising_flag | falling_flag) & PWR_EXTI_LINE_UVM) != 0U)
+ {
+ /* PWR UVM interrupt user callback */
+ HAL_PWREx_UVMCallback();
+
+ /* Clear UVM exti pending bit */
+ WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_UVM);
+ WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_UVM);
+ }
+
+ /* Check PWR exti flags for IO2VM */
+ if (((rising_flag | falling_flag) & PWR_EXTI_LINE_IO2VM) != 0U)
+ {
+ /* PWR IO2VM interrupt user callback */
+ HAL_PWREx_IO2VMCallback();
+
+ /* Clear IO2VM exti pending bit */
+ WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_IO2VM);
+ WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_IO2VM);
+ }
+
+ /* Check PWR exti flags for AVM1 */
+ if (((rising_flag | falling_flag) & PWR_EXTI_LINE_AVM1) != 0U)
+ {
+ /* PWR AVM1 interrupt user callback */
+ HAL_PWREx_AVM1Callback();
+
+ /* Clear AVM1 exti pending bit */
+ WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_AVM1);
+ WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_AVM1);
+ }
+
+ /* Check PWR exti flags for AVM2 */
+ if (((rising_flag | falling_flag) & PWR_EXTI_LINE_AVM2) != 0U)
+ {
+ /* PWR AVM2 interrupt user callback */
+ HAL_PWREx_AVM2Callback();
+
+ /* Clear AVM2 exti pending bit */
+ WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_AVM2);
+ WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_AVM2);
+ }
+}
+
+/**
+ * @brief PWR UVM interrupt callback.
+ * @retval None.
+ */
+__weak void HAL_PWREx_UVMCallback(void)
+{
+ /* NOTE : This function should not be modified; when the callback is needed,
+ HAL_PWREx_UVMCallback() API can be implemented in the user file
+ */
+}
+
+/**
+ * @brief PWR IO2VM interrupt callback.
+ * @retval None.
+ */
+__weak void HAL_PWREx_IO2VMCallback(void)
+{
+ /* NOTE : This function should not be modified; when the callback is needed,
+ HAL_PWREx_IO2VMCallback() API can be implemented in the user file
+ */
+}
+
+/**
+ * @brief PWR AVM1 interrupt callback.
+ * @retval None.
+ */
+__weak void HAL_PWREx_AVM1Callback(void)
+{
+ /* NOTE : This function should not be modified; when the callback is needed,
+ HAL_PWREx_AVM1Callback() API can be implemented in the user file
+ */
+}
+
+/**
+ * @brief PWR AVM2 interrupt callback.
+ * @retval None.
+ */
+__weak void HAL_PWREx_AVM2Callback(void)
+{
+ /* NOTE : This function should not be modified; when the callback is needed,
+ HAL_PWREx_AVM2Callback() API can be implemented in the user file
+ */
+}
+/**
+ * @}
+ */
+
+/** @defgroup PWREx_Exported_Functions_Group4 Memories Retention Functions
+ * @brief Memories retention functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Memories Retention Functions #####
+ ===============================================================================
+ [..]
+ Several STM32U5 devices RAMs are configurable to keep / lose RAMs content
+ during Stop mode (Stop 0/1/2/3).
+ (+) Retained content RAMs in Stop modes are :
+ (++) SRAM1
+ (++) SRAM2
+ (++) SRAM3
+ (++) SRAM4
+ (++) ICACHE
+ (++) DMA2DRAM
+ (++) PKA32RAM
+ (++) DCACHE
+ (++) FMAC
+ (++) FDCAN
+ (++) USB
+
+ [..]
+ Several STM32U5 devices RAMs are configurable to keep / lose RAMs content
+ during Run mode.
+ (+) Retained content RAMs in Run modes are :
+ (++) SRAM1
+ (++) SRAM2
+ (++) SRAM3
+ (++) SRAM4
+
+ [..]
+ SRAM2 is configurable to keep / lose its content in Stop 3 and Standby
+ modes. The SRAM2 retention feature granularity is at pages level.
+
+ [..]
+ BKPRAM is configurable to keep / lose its content in Standby, Shutdown and
+ VBAT modes.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable SRAM2 page(s) content retention in Stop 3 and Standby mode.
+ * @note When RRSx bit is set, SRAM2 is powered by the low-power regulator in
+ * Stop 3 and Standby mode and its content is kept.
+ * @param SRAM2Pages : Specifies the SRAM2 pages.
+ * This parameter can be one of the following values :
+ * @arg PWR_SRAM2_PAGE1_STANDBY_RETENTION : SRAM2 page 1 retention.
+ * @arg PWR_SRAM2_PAGE2_STANDBY_RETENTION : SRAM2 page 2 retention.
+ * @arg PWR_SRAM2_FULL_STANDBY_RETENTION : SRAM2 page 1 and page 2 retention.
+ * @retval None.
+ */
+void HAL_PWREx_EnableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_SRAM2_STANDBY_RETENTION(SRAM2Pages));
+
+ /* Set RRSx bit(s) */
+ SET_BIT(PWR->CR1, SRAM2Pages);
+}
+
+/**
+ * @brief Disable SRAM2 page(s) content retention in Stop 3 and Standby mode.
+ * @note When RRSx bit is reset, SRAM2 is powered off in Stop 3 and Standby
+ * mode and its content is lost.
+ * @param SRAM2Pages : Specifies the SRAM2 pages.
+ * This parameter can be one of the following values :
+ * @arg PWR_SRAM2_PAGE1_STANDBY_RETENTION : SRAM2 page 1 retention.
+ * @arg PWR_SRAM2_PAGE2_STANDBY_RETENTION : SRAM2 page 2 retention.
+ * @arg PWR_SRAM2_FULL_STANDBY_RETENTION : SRAM2 page 1 and page 2 retention.
+ * @retval None.
+ */
+void HAL_PWREx_DisableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_SRAM2_STANDBY_RETENTION(SRAM2Pages));
+
+ /* Clear RRSx bit(s) */
+ CLEAR_BIT(PWR->CR1, SRAM2Pages);
+}
+
+/**
+ * @brief Enable RAM page(s) content retention in Stop mode (Stop 0, 1, 2, 3).
+ * @note When enabling content retention for a given RAM, memory kept powered
+ * in Stop mode. (Not optimized power consumption)
+ * @param RAMSelection: Specifies RAM page(s) to be retained in Stop mode.
+ * This parameter can be one or a combination of the same
+ * memory @ref PWREx_RAM_Contents_Stop_Retention.
+ * @retval None.
+ */
+void HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection)
+{
+ uint32_t dummy;
+
+ /* Check RAM ID */
+ switch (RAMSelection & SRAM_ID_MASK)
+ {
+ /* SRAM 1 Stop retention */
+ case SRAM1_ID:
+ {
+ /* Check the parameters */
+ assert_param(IS_PWR_SRAM1_STOP_RETENTION(RAMSelection));
+
+ /* Calculate pages mask */
+ dummy = (RAMSelection & ~SRAM_ID_MASK) & (PAGE01_ID | PAGE02_ID | PAGE03_ID);
+ CLEAR_BIT(PWR->CR2, dummy);
+
+ break;
+ }
+
+ /* SRAM 2 Stop retention */
+ case SRAM2_ID:
+ {
+ /* Check the parameters */
+ assert_param(IS_PWR_SRAM2_STOP_RETENTION(RAMSelection));
+
+ /* Calculate pages mask */
+ dummy = (RAMSelection & PWR_SRAM2_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
+ CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM2PDS1_Pos));
+
+ break;
+ }
+
+ /* SRAM 3 Stop retention */
+ case SRAM3_ID:
+ {
+ /* Check the parameters */
+ assert_param(IS_PWR_SRAM3_STOP_RETENTION(RAMSelection));
+
+ /* Calculate pages mask */
+ dummy = (RAMSelection & ~SRAM_ID_MASK) & (PAGE01_ID | PAGE02_ID | PAGE03_ID | PAGE04_ID |
+ PAGE05_ID | PAGE06_ID | PAGE07_ID | PAGE08_ID);
+ CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM3PDS1_Pos));
+
+ break;
+ }
+
+ /* SRAM 4 Stop retention */
+ case SRAM4_ID:
+ {
+ /* Check the parameters */
+ assert_param(IS_PWR_SRAM4_STOP_RETENTION(RAMSelection));
+
+ /* Calculate pages mask */
+ dummy = (RAMSelection & PWR_SRAM4_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
+ CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM4PDS_Pos));
+
+ break;
+ }
+
+ /* ICACHE RAM Stop retention */
+ case ICACHERAM_ID:
+ {
+ /* Check the parameters */
+ assert_param(IS_PWR_ICACHE_STOP_RETENTION(RAMSelection));
+
+ /* Calculate pages mask */
+ dummy = (RAMSelection & PWR_ICACHE_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
+ CLEAR_BIT(PWR->CR2, dummy << PWR_CR2_ICRAMPDS_Pos);
+
+ break;
+ }
+
+ /* DCACHE1 RAM Stop retention */
+ case DCACHE1RAM_ID:
+ {
+ /* Check the parameters */
+ assert_param(IS_PWR_DCACHE1_STOP_RETENTION(RAMSelection));
+
+ /* Calculate pages mask */
+ dummy = (RAMSelection & PWR_DCACHE1_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
+ CLEAR_BIT(PWR->CR2, dummy << PWR_CR2_DC1RAMPDS_Pos);
+
+ break;
+ }
+
+ /* DMA2D RAM Stop retention */
+ case DMA2DRAM_ID:
+ {
+ /* Check the parameters */
+ assert_param(IS_PWR_DMA2DRAM_STOP_RETENTION(RAMSelection));
+
+ /* Calculate pages mask */
+ dummy = (RAMSelection & PWR_DMA2DRAM_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
+ CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_DMA2DRAMPDS_Pos));
+
+ break;
+ }
+
+ /* FMAC, FDCAN and USB RAM Stop retention */
+ case PERIPHRAM_ID:
+ {
+ /* Check the parameters */
+ assert_param(IS_PWR_PERIPHRAM_STOP_RETENTION(RAMSelection));
+
+ /* Calculate pages mask */
+ dummy = (RAMSelection & PWR_PERIPHRAM_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
+ CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_PRAMPDS_Pos));
+
+ break;
+ }
+
+ /* PKA32 RAM Stop retention */
+ case PKARAM_ID:
+ {
+ /* Check the parameters */
+ assert_param(IS_PWR_PKA32RAM_STOP_RETENTION(RAMSelection));
+
+ /* Calculate pages mask */
+ dummy = (RAMSelection & PWR_PKA32RAM_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
+ CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_PKARAMPDS_Pos));
+
+ break;
+ }
+
+ default:
+ {
+ return;
+ break;
+ }
+ }
+}
+
+/**
+ * @brief Disable RAM page(s) content lost in Stop mode (Stop 0, 1, 2, 3).
+ * @note When disabling content lost for a given RAM, memory powered down
+ * in Stop mode. (Optimized power consumption)
+ * @param RAMSelection: Specifies RAM page(s) to be lost in Stop mode.
+ * This parameter can be one or a combination of the same
+ * memory @ref PWREx_RAM_Contents_Stop_Retention.
+ * @retval None.
+ */
+void HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection)
+{
+ uint32_t dummy;
+
+ /* Check RAM ID */
+ switch (RAMSelection & SRAM_ID_MASK)
+ {
+ /* SRAM 1 Stop retention */
+ case SRAM1_ID:
+ {
+ /* Check the parameters */
+ assert_param(IS_PWR_SRAM1_STOP_RETENTION(RAMSelection));
+
+ /* Calculate pages mask */
+ dummy = (RAMSelection & ~SRAM_ID_MASK) & (PAGE01_ID | PAGE02_ID | PAGE03_ID);
+ SET_BIT(PWR->CR2, dummy);
+
+ break;
+ }
+
+ /* SRAM 2 Stop retention */
+ case SRAM2_ID:
+ {
+ /* Check the parameters */
+ assert_param(IS_PWR_SRAM2_STOP_RETENTION(RAMSelection));
+
+ /* Calculate pages mask */
+ dummy = (RAMSelection & PWR_SRAM2_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
+ SET_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM2PDS1_Pos));
+
+ break;
+ }
+
+ /* SRAM 3 Stop retention */
+ case SRAM3_ID:
+ {
+ /* Check the parameters */
+ assert_param(IS_PWR_SRAM3_STOP_RETENTION(RAMSelection));
+
+ /* Calculate pages mask */
+ dummy = (RAMSelection & ~SRAM_ID_MASK) & (PAGE01_ID | PAGE02_ID | PAGE03_ID | PAGE04_ID |
+ PAGE05_ID | PAGE06_ID | PAGE07_ID | PAGE08_ID);
+ SET_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM3PDS1_Pos));
+
+ break;
+ }
+
+ /* SRAM 4 Stop retention */
+ case SRAM4_ID:
+ {
+ /* Check the parameters */
+ assert_param(IS_PWR_SRAM4_STOP_RETENTION(RAMSelection));
+
+ /* Calculate pages mask */
+ dummy = (RAMSelection & PWR_SRAM4_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
+ SET_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM4PDS_Pos));
+
+ break;
+ }
+
+ /* ICACHE RAM Stop retention */
+ case ICACHERAM_ID:
+ {
+ /* Check the parameters */
+ assert_param(IS_PWR_ICACHE_STOP_RETENTION(RAMSelection));
+
+ /* Calculate pages mask */
+ dummy = (RAMSelection & PWR_ICACHE_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
+ SET_BIT(PWR->CR2, (dummy << PWR_CR2_ICRAMPDS_Pos));
+
+ break;
+ }
+
+ /* DCACHE1 RAM Stop retention */
+ case DCACHE1RAM_ID:
+ {
+ /* Check the parameters */
+ assert_param(IS_PWR_DCACHE1_STOP_RETENTION(RAMSelection));
+
+ /* Calculate pages mask */
+ dummy = (RAMSelection & PWR_DCACHE1_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
+ SET_BIT(PWR->CR2, (dummy << PWR_CR2_DC1RAMPDS_Pos));
+
+ break;
+ }
+
+ /* DMA2D RAM Stop retention */
+ case DMA2DRAM_ID:
+ {
+ /* Check the parameters */
+ assert_param(IS_PWR_DMA2DRAM_STOP_RETENTION(RAMSelection));
+
+ /* Calculate pages mask */
+ dummy = (RAMSelection & PWR_DMA2DRAM_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
+ SET_BIT(PWR->CR2, (dummy << PWR_CR2_DMA2DRAMPDS_Pos));
+
+ break;
+ }
+
+ /* FMAC, FDCAN and USB RAM Stop retention */
+ case PERIPHRAM_ID:
+ {
+ /* Check the parameters */
+ assert_param(IS_PWR_PERIPHRAM_STOP_RETENTION(RAMSelection));
+
+ /* Calculate pages mask */
+ dummy = (RAMSelection & PWR_PERIPHRAM_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
+ SET_BIT(PWR->CR2, (dummy << PWR_CR2_PRAMPDS_Pos));
+
+ break;
+ }
+
+ /* PKA32 RAM Stop retention */
+ case PKARAM_ID:
+ {
+ /* Check the parameters */
+ assert_param(IS_PWR_PKA32RAM_STOP_RETENTION(RAMSelection));
+
+ /* Calculate pages mask */
+ dummy = (RAMSelection & PWR_PKA32RAM_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
+ SET_BIT(PWR->CR2, (dummy << PWR_CR2_PKARAMPDS_Pos));
+
+ break;
+ }
+
+ default:
+ {
+ return;
+ break;
+ }
+ }
+}
+
+/**
+ * @brief Enable RAMs full content retention in Run mode.
+ * @param RAMSelection : Specifies the SRAM content to be retained in Run mode.
+ * This parameter can be one or a combination of the following values :
+ * @arg PWR_SRAM1_FULL_RUN_RETENTION : SRAM1 full content retention.
+ * @arg PWR_SRAM2_FULL_RUN_RETENTION : SRAM2 full content retention.
+ * @arg PWR_SRAM3_FULL_RUN_RETENTION : SRAM3 full content retention.
+ * @arg PWR_SRAM4_FULL_RUN_RETENTION : SRAM4 full content retention.
+ * @retval None.
+ */
+void HAL_PWREx_EnableRAMsContentRunRetention(uint32_t RAMSelection)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_RAM_RUN_RETENTION(RAMSelection));
+
+ /* Enable RAM retention in Run mode */
+ CLEAR_BIT(PWR->CR1, RAMSelection);
+}
+
+/**
+ * @brief Disable RAMs full content retention in Run mode.
+ * @param RAMSelection : Specifies the SRAM content to be lost in Run mode.
+ * This parameter can be one or a combination of the following values :
+ * @arg PWR_SRAM1_FULL_RUN_RETENTION : SRAM1 full content lost.
+ * @arg PWR_SRAM2_FULL_RUN_RETENTION : SRAM2 full content lost.
+ * @arg PWR_SRAM3_FULL_RUN_RETENTION : SRAM3 full content lost.
+ * @arg PWR_SRAM4_FULL_RUN_RETENTION : SRAM4 full content lost.
+ * @retval None.
+ */
+void HAL_PWREx_DisableRAMsContentRunRetention(uint32_t RAMSelection)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_RAM_RUN_RETENTION(RAMSelection));
+
+ /* Disable RAM retention in Run mode */
+ SET_BIT(PWR->CR1, RAMSelection);
+}
+
+/**
+ * @brief Enable the Backup RAM retention in Standby, Shutdown and VBAT modes.
+ * @note If BREN is reset, the backup RAM can still be used in Run, Sleep and
+ * Stop modes. However, its content is lost in Standby, Shutdown and
+ * VBAT modes.
+ * @note This bit can be enabled only when LDO regulator is selected as
+ * source supply.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_PWREx_EnableBkupRAMRetention(void)
+{
+ /*
+ Backup RAM retention in Standby, Shutdown and VBAT should be enabled
+ when the Vcore is alimented by the LDO regulator
+ */
+ if (HAL_PWREx_GetSupplyConfig() == PWR_LDO_SUPPLY)
+ {
+ SET_BIT(PWR->BDCR1, PWR_BDCR1_BREN);
+ }
+ /* SMPS regulator selected */
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the Backup RAM retention in Standby, Shutdown and VBAT modes.
+ * @note If BREN is reset, the backup RAM can still be used in Run, Sleep and
+ * Stop modes. However, its content is lost in Standby, Shutdown and
+ * VBAT modes. This bit can be writte
+ * @retval None.
+ */
+void HAL_PWREx_DisableBkupRAMRetention(void)
+{
+ CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_BREN);
+}
+
+/**
+ * @brief Enable the flash memory fast wakeup from Stop 0 and Stop 1 modes.
+ * @note This feature is used to obtain the best trade-off between low-power
+ * consumption and wakeup time when exiting the Stop 0 or Stop 1 modes.
+ * When this feature is enabled, the Flash memory remains in normal
+ * mode in Stop 0 and Stop 1 modes, which offers a faster startup time
+ * with higher consumption.
+ * @retval None.
+ */
+void HAL_PWREx_EnableFlashFastWakeUp(void)
+{
+ SET_BIT(PWR->CR2, PWR_CR2_FLASHFWU);
+}
+
+/**
+ * @brief Disable the Flash Power Down in Stop mode.
+ * @note This feature is used to obtain the best trade-off between low-power
+ * consumption and wakeup time when exiting the Stop 0 or Stop 1 modes.
+ * When this feature is disabled, the Flash memory enters low-power
+ * mode in Stop 0 and Stop 1 modes, which causes a slower startup time
+ * with lower consumption.
+ * @retval None.
+ */
+void HAL_PWREx_DisableFlashFastWakeUp(void)
+{
+ CLEAR_BIT(PWR->CR2, PWR_CR2_FLASHFWU);
+}
+
+/**
+ * @brief Enable the SRAM4 memory fast wakeup from Stop 0, Stop 1 and Stop 2 modes.
+ * @note This bit is used to obtain the best trade-off between low-power consumption
+ * and wakeup time. SRAM4 wakeup time increases the wakeup time when exiting
+ * Stop 0, Stop 1 and Stop 2 modes, and also increases the LPDMA access time
+ * to SRAM4 during Stop modes.
+ * @retval None.
+ */
+void HAL_PWREx_EnableSRAM4FastWakeUp(void)
+{
+ SET_BIT(PWR->CR2, PWR_CR2_SRAM4FWU);
+}
+
+/**
+ * @brief Disable the SRAM4 memory fast wakeup from Stop 0, Stop 1 and Stop 2 modes.
+ * @note This bit is used to obtain the best trade-off between low-power consumption
+ * and wakeup time. SRAM4 wakeup time increases the wakeup time when exiting
+ * Stop 0, Stop 1 and Stop 2 modes, and also increases the LPDMA access time
+ * to SRAM4 during Stop modes.
+ * @retval None.
+ */
+void HAL_PWREx_DisableSRAM4FastWakeUp(void)
+{
+ CLEAR_BIT(PWR->CR2, PWR_CR2_SRAM4FWU);
+}
+/**
+ * @}
+ */
+
+/** @defgroup PWREx_Exported_Functions_Group5 I/O Pull-Up Pull-Down Configuration Functions
+ * @brief I/O pull-up / pull-down configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Voltage monitoring Functions #####
+ ===============================================================================
+ [..]
+ In Standby and Shutdown mode, pull up and pull down can be configured to
+ maintain an I/O in the selected state. If the APC bit in the PWR_APCR
+ register is set, the I/Os can be configured either with a pull-up through
+ PWR_PUCRx registers (x=A,B,C,D,E,F,G,H,I), or with a pull-down through
+ PWR_PDCRx registers (x=A,B,C,D,E,F,G,H,I)), or can be kept in analog state
+ if none of the PWR_PUCRx or PWR_PDCRx register is set.
+
+ [..]
+ The pull-down configuration has highest priority over pull-up
+ configuration in case both PWR_PUCRx and PWR_PDCRx are set for the same
+ I/O.
+ This configuration is lost when exiting the Shutdown but not from Standby
+ mode.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable pull-up and pull-down configuration.
+ * @note When APC bit is set, the I/O pull-up and pull-down configurations
+ * defined in PWR_PUCRx and PWR_PDCRx registers are applied in Standby
+ * and Shutdown modes.
+ * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the
+ * corresponding PDy bit of PWR_PDCRx register is also set (pull-down
+ * configuration priority is higher). HAL_PWREx_EnableGPIOPullUp() and
+ * HAL_PWREx_EnableGPIOPullDown() API's ensure there is no conflict
+ * when setting PUy or PDy bit.
+ * @retval None.
+ */
+void HAL_PWREx_EnablePullUpPullDownConfig(void)
+{
+ SET_BIT(PWR->APCR, PWR_APCR_APC);
+}
+
+/**
+ * @brief Disable pull-up and pull-down configuration.
+ * @note When APC bit is cleared, the I/O pull-up and pull-down configurations
+ * defined in PWR_PUCRx and PWR_PDCRx registers are not applied in
+ * Standby and Shutdown modes.
+ * @retval None.
+ */
+void HAL_PWREx_DisablePullUpPullDownConfig(void)
+{
+ CLEAR_BIT(PWR->APCR, PWR_APCR_APC);
+}
+
+/**
+ * @brief Enable GPIO pull-up state in Standby and Shutdown modes.
+ * @note Set the relevant PUy bits of PWR_PUCRx register to configure the I/O
+ * in pull-up state in Standby and Shutdown modes.
+ * @note This state is effective in Standby and Shutdown modes only if APC
+ * bit is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
+ * @note The configuration is lost when exiting the Shutdown mode due to the
+ * power-on reset, maintained when exiting the Standby mode.
+ * @note To avoid any conflict at Standby and Shutdown modes exits, the
+ * corresponding PDy bit of PWR_PDCRx register is cleared unless it is
+ * reserved.
+ * @note Even if a PUy bit to set is reserved, the other PUy bits entered as
+ * input parameter at the same time are set.
+ * @param GPIO_Port : Specify the IO port.
+ * This parameter can be a value of
+ * @ref PWREx_GPIO_Port.
+ * @param GPIO_Pin : Specify the I/O pins numbers.
+ * This parameter can be a value of
+ * @ref PWREx_GPIO_Pin_Mask.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_GPIO_PORT(GPIO_Port));
+ assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin));
+
+ /* Check GPIO port */
+ switch (GPIO_Port)
+ {
+ case PWR_GPIO_A: /* Apply Pull Up to GPIO port A */
+ SET_BIT(PWR->PUCRA, (GPIO_Pin & (~(PWR_GPIO_BIT_14))));
+ CLEAR_BIT(PWR->PDCRA, (GPIO_Pin & (~(PWR_GPIO_BIT_13 | PWR_GPIO_BIT_15))));
+ break;
+
+ case PWR_GPIO_B: /* Apply Pull Up to GPIO port B */
+ SET_BIT(PWR->PUCRB, GPIO_Pin);
+ CLEAR_BIT(PWR->PDCRB, (GPIO_Pin & (~(PWR_GPIO_BIT_4))));
+ break;
+
+ case PWR_GPIO_C: /* Apply Pull Up to GPIO port C */
+ SET_BIT(PWR->PUCRC, GPIO_Pin);
+ CLEAR_BIT(PWR->PDCRC, GPIO_Pin);
+ break;
+
+ case PWR_GPIO_D: /* Apply Pull Up to GPIO port D */
+ SET_BIT(PWR->PUCRD, GPIO_Pin);
+ CLEAR_BIT(PWR->PDCRD, GPIO_Pin);
+ break;
+
+ case PWR_GPIO_E: /* Apply Pull Up to GPIO port E */
+ SET_BIT(PWR->PUCRE, GPIO_Pin);
+ CLEAR_BIT(PWR->PDCRE, GPIO_Pin);
+ break;
+
+ case PWR_GPIO_F: /* Apply Pull Up to GPIO port F */
+ SET_BIT(PWR->PUCRF, GPIO_Pin);
+ CLEAR_BIT(PWR->PDCRF, GPIO_Pin);
+ break;
+
+ case PWR_GPIO_G: /* Apply Pull Up to GPIO port G */
+ SET_BIT(PWR->PUCRG, GPIO_Pin);
+ CLEAR_BIT(PWR->PDCRG, GPIO_Pin);
+ break;
+
+ case PWR_GPIO_H: /* Apply Pull Up to GPIO port H */
+ SET_BIT(PWR->PUCRH, GPIO_Pin);
+ CLEAR_BIT(PWR->PDCRH, GPIO_Pin);
+ break;
+
+ case PWR_GPIO_I: /* Apply Pull Up to GPIO port I */
+ SET_BIT(PWR->PUCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS));
+ CLEAR_BIT(PWR->PDCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS));
+ break;
+
+ default:
+ return HAL_ERROR;
+ break;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes.
+ * @note Reset the relevant PUy bits of PWR_PUCRx register used to configure
+ * the I/O in pull-up state in Standby and Shutdown modes.
+ * @note Even if a PUy bit to reset is reserved, the other PUy bits entered as
+ * input parameter at the same time are reset.
+ * @param GPIO_Port : Specify the IO port.
+ * This parameter can be a value of
+ * @ref PWREx_GPIO_Port.
+ * @param GPIO_Pin : Specify the I/O pins numbers.
+ * This parameter can be a value of
+ * @ref PWREx_GPIO_Pin_Mask.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_GPIO_PORT(GPIO_Port));
+ assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin));
+
+ /* Check GPIO port */
+ switch (GPIO_Port)
+ {
+ case PWR_GPIO_A: /* Disable Pull Up for GPIO port A */
+ CLEAR_BIT(PWR->PUCRA, (GPIO_Pin & (~(PWR_GPIO_BIT_14))));
+ break;
+
+ case PWR_GPIO_B: /* Disable Pull Up for GPIO port B */
+ CLEAR_BIT(PWR->PUCRB, GPIO_Pin);
+ break;
+
+ case PWR_GPIO_C: /* Disable Pull Up for GPIO port C */
+ CLEAR_BIT(PWR->PUCRC, GPIO_Pin);
+ break;
+
+ case PWR_GPIO_D: /* Disable Pull Up for GPIO port D */
+ CLEAR_BIT(PWR->PUCRD, GPIO_Pin);
+ break;
+
+ case PWR_GPIO_E: /* Disable Pull Up for GPIO port E */
+ CLEAR_BIT(PWR->PUCRE, GPIO_Pin);
+ break;
+
+ case PWR_GPIO_F: /* Disable Pull Up for GPIO port F */
+ CLEAR_BIT(PWR->PUCRF, GPIO_Pin);
+ break;
+
+ case PWR_GPIO_G: /* Disable Pull Up for GPIO port G */
+ CLEAR_BIT(PWR->PUCRG, GPIO_Pin);
+ break;
+
+ case PWR_GPIO_H: /* Disable Pull Up for GPIO port H */
+ CLEAR_BIT(PWR->PUCRH, GPIO_Pin);
+ break;
+
+ case PWR_GPIO_I: /* Disable Pull Up for GPIO port I */
+ CLEAR_BIT(PWR->PUCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS));
+ break;
+
+ default:
+ return HAL_ERROR;
+ break;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable GPIO pull-down state in Standby and Shutdown modes.
+ * @note Set the relevant PDy bits of PWR_PDCRx register to configure the I/O
+ * in pull-down state in Standby and Shutdown modes.
+ * @note This state is effective in Standby and Shutdown modes only if APC bit
+ * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
+ * @note The configuration is lost when exiting the Shutdown mode due to the
+ * power-on reset, maintained when exiting the Standby mode.
+ * @note To avoid any conflict at Standby and Shutdown modes exits, the
+ * corresponding PUy bit of PWR_PUCRx register is cleared unless it is
+ * reserved.
+ * @note Even if a PDy bit to set is reserved, the other PDy bits entered as
+ * input parameter at the same time are set.
+ * @param GPIO_Port : Specify the IO port.
+ * This parameter can be a value of
+ * @ref PWREx_GPIO_Port.
+ * @param GPIO_Pin : Specify the I/O pins numbers.
+ * This parameter can be a value of
+ * @ref PWREx_GPIO_Pin_Mask.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPIO_Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_GPIO_PORT(GPIO_Port));
+ assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin));
+
+ /* Check GPIO port */
+ switch (GPIO_Port)
+ {
+ case PWR_GPIO_A: /* Apply Pull Down to GPIO port A */
+ SET_BIT(PWR->PDCRA, (GPIO_Pin & (~(PWR_GPIO_BIT_13 | PWR_GPIO_BIT_15))));
+ CLEAR_BIT(PWR->PUCRA, (GPIO_Pin & (~(PWR_GPIO_BIT_14))));
+ break;
+
+ case PWR_GPIO_B: /* Apply Pull Down to GPIO port B */
+ SET_BIT(PWR->PDCRB, (GPIO_Pin & (~(PWR_GPIO_BIT_4))));
+ CLEAR_BIT(PWR->PUCRB, GPIO_Pin);
+ break;
+
+ case PWR_GPIO_C: /* Apply Pull Down to GPIO port C */
+ SET_BIT(PWR->PDCRC, GPIO_Pin);
+ CLEAR_BIT(PWR->PUCRC, GPIO_Pin);
+ break;
+
+ case PWR_GPIO_D: /* Apply Pull Down to GPIO port D */
+ SET_BIT(PWR->PDCRD, GPIO_Pin);
+ CLEAR_BIT(PWR->PUCRD, GPIO_Pin);
+ break;
+
+ case PWR_GPIO_E: /* Apply Pull Down to GPIO port E */
+ SET_BIT(PWR->PDCRE, GPIO_Pin);
+ CLEAR_BIT(PWR->PUCRE, GPIO_Pin);
+ break;
+
+ case PWR_GPIO_F: /* Apply Pull Down to GPIO port F */
+ SET_BIT(PWR->PDCRF, GPIO_Pin);
+ CLEAR_BIT(PWR->PUCRF, GPIO_Pin);
+ break;
+
+ case PWR_GPIO_G: /* Apply Pull Down to GPIO port G */
+ SET_BIT(PWR->PDCRG, GPIO_Pin);
+ CLEAR_BIT(PWR->PUCRG, GPIO_Pin);
+ break;
+
+ case PWR_GPIO_H: /* Apply Pull Down to GPIO port H */
+ SET_BIT(PWR->PDCRH, GPIO_Pin);
+ CLEAR_BIT(PWR->PUCRH, GPIO_Pin);
+ break;
+
+ case PWR_GPIO_I: /* Apply Pull Down to GPIO port I */
+ SET_BIT(PWR->PDCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS));
+ CLEAR_BIT(PWR->PUCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS));
+ break;
+
+ default:
+ return HAL_ERROR;
+ break;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable GPIO pull-down state in Standby and Shutdown modes.
+ * @note Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O
+ * in pull-down state in Standby and Shutdown modes.
+ * @note Even if a PDy bit to reset is reserved, the other PDy bits entered as input
+ * parameter at the same time are reset.
+ * @param GPIO_Port : Specify the IO port.
+ * This parameter can be a value of
+ * @ref PWREx_GPIO_Port.
+ * @param GPIO_Pin : Specify the I/O pins numbers.
+ * This parameter can be a value of
+ * @ref PWREx_GPIO_Pin_Mask.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPIO_Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_GPIO_PORT(GPIO_Port));
+ assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin));
+
+ /* Check GPIO port */
+ switch (GPIO_Port)
+ {
+ case PWR_GPIO_A: /* Disable Pull Down for GPIO port A */
+ CLEAR_BIT(PWR->PDCRA, (GPIO_Pin & (~(PWR_GPIO_BIT_13 | PWR_GPIO_BIT_15))));
+ break;
+
+ case PWR_GPIO_B: /* Disable Pull Down for GPIO port B */
+ CLEAR_BIT(PWR->PDCRB, (GPIO_Pin & (~(PWR_GPIO_BIT_4))));
+ break;
+
+ case PWR_GPIO_C: /* Disable Pull Down for GPIO port C */
+ CLEAR_BIT(PWR->PDCRC, GPIO_Pin);
+ break;
+
+ case PWR_GPIO_D: /* Disable Pull Down for GPIO port D */
+ CLEAR_BIT(PWR->PDCRD, GPIO_Pin);
+ break;
+
+ case PWR_GPIO_E: /* Disable Pull Down for GPIO port E */
+ CLEAR_BIT(PWR->PDCRE, GPIO_Pin);
+ break;
+
+ case PWR_GPIO_F: /* Disable Pull Down for GPIO port F */
+ CLEAR_BIT(PWR->PDCRF, GPIO_Pin);
+ break;
+
+ case PWR_GPIO_G: /* Disable Pull Down for GPIO port G */
+ CLEAR_BIT(PWR->PDCRG, GPIO_Pin);
+ break;
+
+ case PWR_GPIO_H: /* Disable Pull Down for GPIO port H */
+ CLEAR_BIT(PWR->PDCRH, GPIO_Pin);
+ break;
+
+ case PWR_GPIO_I: /* Disable Pull Down for GPIO port I */
+ CLEAR_BIT(PWR->PDCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS));
+ break;
+
+ default:
+ return HAL_ERROR;
+ break;
+ }
+
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+#endif /* defined (HAL_PWR_MODULE_ENABLED) */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_ramcfg.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_ramcfg.c
new file mode 100644
index 00000000..fdd5f547
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_ramcfg.c
@@ -0,0 +1,1170 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_ramcfg.c
+ * @author MCD Application Team
+ * @brief RAMCFG HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the RAMs configuration controller peripheral:
+ * + RAMCFG Initialization and De-initialization Functions.
+ * + RAMCFG ECC Operation Functions.
+ * + RAMCFG Configure Wait State Functions.
+ * + RAMCFG Write Protection Functions.
+ * + RAMCFG Erase Operation Functions.
+ * + RAMCFG Handle Interrupt and Callbacks Functions.
+ * + RAMCFG State and Error Functions.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### RAMCFG Peripheral features #####
+ ==============================================================================
+ [..]
+ (+) Each SRAM is managed by a RAMCFG instance.
+
+ (+) Each SRAM can be erased independently through its RAMCFG instance.
+
+ (+) The wait state value for each SRAM can be configured independently
+ through its RAMCFG instance.
+
+ (+) SRAM2 is divided to 64 pages with 1 kB granularity. Each page can be
+ write protected independently through its RAMCFG instance.
+
+ (+) SRAM2, SRAM3 and BKPRAM support ECC correction feature. This mechanism
+ adopts the Single Error Correction Double Error Detection (SECDED)
+ algorithm. This feature provides the following information:
+ (++) Single error address.
+ (++) Double error address.
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Call HAL_RAMCFG_Init() to initialize the RAMCFG peripheral before using
+ any feature. Call HAL_RAMCFG_DeInit() to de-initialize the RAMCFG when
+ using this peripheral is no more needed or a hardware issue has occurred.
+
+ *** ECC feature ***
+ ===================
+ [..]
+ (+) Call HAL_RAMCFG_StartECC() and HAL_RAMCFG_StopECC() to enable and
+ disable ECC hardware process.
+
+ (+) Call HAL_RAMCFG_EnableNotification() and HAL_RAMCFG_DisableNotification()
+ to enable and disable ECC interrupts. Interrupts can be :
+ (++) Single error interrupt.
+ (++) Double error interrupt.
+ (++) Double error interrupt redirected to Non masKable
+ interrupt (NMI).
+
+ (+) Call HAL_RAMCFG_GetSingleErrorAddress() to get the address of the
+ last fail RAM word detected (only for single error) and
+ call HAL_RAMCFG_GetDoubleErrorAddress() to get the address of the
+ last fail RAM word detected (only for double error).
+
+ (+) Call HAL_RAMCFG_IsECCErrorDetected() to check if an ECC single/double
+ error was detected. This API is used in silent mode (No ECC interrupt
+ is enabled).
+
+ *** Wait State feature ***
+ ==========================
+ [..]
+ (+) Call HAL_RAMCFG_ConfigWaitState() to configure the wait state value
+ for a given SRAM according to the HCLK frequency and voltage range
+ scaling.
+
+ (+) Call HAL_RAMCFG_GetWaitState() to get the current configured wait
+ state value.
+
+ *** Write protection feature ***
+ ================================
+ [..]
+ (+) Call HAL_RAMCFG_EnableWriteProtection() to enable the write
+ protection for the given SRAM2 page(s).
+
+ (+) There is no API to disable write protection as this feature can
+ be disabled only by a global peripheral reset or system reset.
+
+ (+) Any write access to a write protected area of SRAM2 causes a
+ HardFault interrupt.
+
+ *** Erase feature ***
+ =====================
+ [..]
+ (+) Call HAL_RAMCFG_Erase() to launch a hardware erase for the given
+ SRAM.
+
+ (+) The erase value is equal to 0 when launching erase hardware through
+ RAMCFG.
+
+ (+) SRAM2 write protected pages are erased when performing an erase
+ through RAMCFG.
+
+ *** RAMCFG HAL driver macros list ***
+ =====================================
+ [..]
+ Below the list of used macros in RAMCFG HAL driver.
+
+ (+) __HAL_RAMCFG_ENABLE_IT : Enable the specified RAMCFG interrupts.
+ (+) __HAL_RAMCFG_DISABLE_IT : Disable the specified RAMCFG interrupts.
+ (+) __HAL_RAMCFG_GET_FLAG : Get the RAMCFG pending flags.
+ (+) __HAL_RAMCFG_CLEAR_FLAG : Clear the RAMCFG pending flags.
+ (+) __HAL_RAMCFG_GET_IT_SOURCE : Check whether the specified RAMCFG
+ interrupt source is enabled or not.
+ @endverbatim
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup RAMCFG RAMCFG
+ * @brief RAMCFG HAL module driver
+ * @{
+ */
+
+#ifdef HAL_RAMCFG_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+
+/** @addtogroup RAMCFG_Private_Constants
+ * @{
+ */
+#define RAMCFG_TIMEOUT_VALUE 50000U
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup RAMCFG_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RAMCFG_Exported_Functions_Group1
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization Functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to initialize and de-initialize the
+ RAMCFG instance.
+ [..]
+ The HAL_RAMCFG_Init() function follows the RAMCFG instance configuration
+ procedures as described in the reference manual.
+ The HAL_RAMCFG_DeInit() function allows to deinitialize the RAMCFG instance.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the RAMCFG by clearing flags and disabling interrupts.
+ * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that contains
+ * the configuration information for the specified RAMCFG
+ * instance.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_RAMCFG_Init(RAMCFG_HandleTypeDef *hramcfg)
+{
+ /* Check the RAMCFG peripheral handle */
+ if (hramcfg == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_RAMCFG_ALL_INSTANCE(hramcfg->Instance));
+
+ /* Update RAMCFG peripheral state */
+ hramcfg->State = HAL_RAMCFG_STATE_BUSY;
+
+#if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1)
+ /* Check if a valid MSP API was registered */
+ if (hramcfg->MspInitCallback == NULL)
+ {
+ /* Init the low level hardware */
+ hramcfg->MspInitCallback = HAL_RAMCFG_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hramcfg->MspInitCallback(hramcfg);
+#else
+ HAL_RAMCFG_MspInit(hramcfg);
+#endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */
+
+ /* Unlock the SRAM ECC enable bit and disable the ECC feature */
+ WRITE_REG(hramcfg->Instance->ECCKEY, RAMCFG_ECC_KEY1);
+ WRITE_REG(hramcfg->Instance->ECCKEY, RAMCFG_ECC_KEY2);
+ hramcfg->Instance->CR &= ~(RAMCFG_CR_ECCE | RAMCFG_CR_ALE);
+
+ /* Disable all RAMCFG interrupts */
+ __HAL_RAMCFG_DISABLE_IT(hramcfg, RAMCFG_IT_ALL);
+
+ /* Clear RAMCFG monitor flags */
+ __HAL_RAMCFG_CLEAR_FLAG(hramcfg, RAMCFG_FLAGS_ALL);
+
+ /* Initialise the RAMCFG error code */
+ hramcfg->ErrorCode = HAL_RAMCFG_ERROR_NONE;
+
+ /* Initialize the RAMCFG state */
+ hramcfg->State = HAL_RAMCFG_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitialize the RAMCFG peripheral.
+ * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that contains
+ * the configuration information for the specified RAMCFG
+ * instance.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_RAMCFG_DeInit(RAMCFG_HandleTypeDef *hramcfg)
+{
+ /* Check the RAMCFG peripheral handle */
+ if (hramcfg == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_RAMCFG_ALL_INSTANCE(hramcfg->Instance));
+
+ /* Unlock the SRAM ECC enable bit and disable the ECC feature */
+ WRITE_REG(hramcfg->Instance->ECCKEY, RAMCFG_ECC_KEY1);
+ WRITE_REG(hramcfg->Instance->ECCKEY, RAMCFG_ECC_KEY2);
+ hramcfg->Instance->CR &= ~(RAMCFG_CR_ECCE | RAMCFG_CR_ALE);
+
+ /* Disable all RAMCFG interrupts */
+ __HAL_RAMCFG_DISABLE_IT(hramcfg, RAMCFG_IT_ALL);
+
+ /* Clear RAMCFG monitor flags */
+ __HAL_RAMCFG_CLEAR_FLAG(hramcfg, RAMCFG_FLAGS_ALL);
+
+#if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1)
+ /* Check if a valid MSP API was registered */
+ if (hramcfg->MspDeInitCallback != NULL)
+ {
+ /* Init the low level hardware */
+ hramcfg->MspDeInitCallback(hramcfg);
+ }
+
+ /* Clean callbacks */
+ hramcfg->DetectSingleErrorCallback = NULL;
+ hramcfg->DetectDoubleErrorCallback = NULL;
+#else
+ HAL_RAMCFG_MspDeInit(hramcfg);
+#endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */
+
+ /* Reset the RAMCFG error code */
+ hramcfg->ErrorCode = HAL_RAMCFG_ERROR_NONE;
+
+ /* Reset the RAMCFG state */
+ hramcfg->State = HAL_RAMCFG_STATE_RESET;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the RAMCFG MSP.
+ * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that contains
+ * the configuration information for the specified RAMCFG.
+ * @retval None.
+ */
+__weak void HAL_RAMCFG_MspInit(RAMCFG_HandleTypeDef *hramcfg)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hramcfg);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RAMCFG_MspInit can be implemented in the user file */
+}
+
+/**
+ * @brief DeInitialize the RAMCFG MSP.
+ * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that contains
+ * the configuration information for the specified RAMCFG.
+ * @retval None.
+ */
+__weak void HAL_RAMCFG_MspDeInit(RAMCFG_HandleTypeDef *hramcfg)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hramcfg);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RAMCFG_MspDeInit can be implemented in the user file */
+}
+/**
+ * @}
+ */
+
+/** @addtogroup RAMCFG_Exported_Functions_Group2
+ *
+@verbatim
+ ===============================================================================
+ ##### ECC Operations Functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to manage ECC feature provided by
+ the RAMCFG peripheral.
+ [..]
+ The HAL_RAMCFG_StartECC() function allows enabling and starting the ECC
+ mechanism for the selected RAMCFG instance.
+ The HAL_RAMCFG_StopECC() function allows disabling and stopping the ECC
+ mechanism for the selected RAMCFG instance.
+ The HAL_RAMCFG_EnableNotification() function allows enabling interrupts
+ for single ECC error, double ECC error and NMI error.
+ The HAL_RAMCFG_DisableNotification() function allows disabling interrupts
+ for single ECC error, double ECC error. When NMI interrupt is enabled it
+ can only be disabled by a global peripheral reset or by a system reset.
+ The HAL_RAMCFG_IsECCErrorDetected() function allows to check if an ECC error
+ has occurred.
+ The HAL_RAMCFG_GetSingleErrorAddress() function allows to get the address of
+ the last single ECC error detected.
+ The HAL_RAMCFG_GetDoubleErrorAddress() function allows to get the address of
+ the last double ECC error detected.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start ECC mechanism for the given SRAM.
+ * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that contains
+ * the configuration information for the specified RAMCFG
+ * instance.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_RAMCFG_StartECC(RAMCFG_HandleTypeDef *hramcfg)
+{
+
+ HAL_StatusTypeDef status = HAL_OK;
+ /* Check the parameters */
+ assert_param(IS_RAMCFG_ECC_INSTANCE(hramcfg->Instance));
+
+ /* Check RAMCFG state */
+ if (hramcfg->State == HAL_RAMCFG_STATE_READY)
+ {
+ /* Update RAMCFG peripheral state */
+ hramcfg->State = HAL_RAMCFG_STATE_BUSY;
+
+ /* Check if ECC mechanism is active */
+ if ((hramcfg->Instance->CR & RAMCFG_CR_ECCE) != RAMCFG_CR_ECCE)
+ {
+ /* Start the SRAM ECC mechanism and latching the error address */
+ hramcfg->Instance->CR |= (RAMCFG_CR_ECCE | RAMCFG_CR_ALE);
+
+ /* Update the RAMCFG state */
+ hramcfg->State = HAL_RAMCFG_STATE_READY;
+ }
+ }
+ else
+ {
+ /* Update the RAMCFG error code and return error */
+ hramcfg->ErrorCode = HAL_RAMCFG_ERROR_BUSY;
+ status = HAL_ERROR;
+
+ }
+
+ return status;
+}
+
+/**
+ * @brief Stop ECC mechanism for the given SRAM.
+ * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that contains
+ * the configuration information for the specified RAMCFG
+ * instance.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_RAMCFG_StopECC(RAMCFG_HandleTypeDef *hramcfg)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ /* Check the parameters */
+ assert_param(IS_RAMCFG_ECC_INSTANCE(hramcfg->Instance));
+
+ /* Check RAMCFG state */
+ if (hramcfg->State == HAL_RAMCFG_STATE_READY)
+ {
+ /* Update RAMCFG peripheral state */
+ hramcfg->State = HAL_RAMCFG_STATE_BUSY;
+
+ /* Check if ECC mechanism is active */
+ if ((hramcfg->Instance->CR & RAMCFG_CR_ECCE) == RAMCFG_CR_ECCE)
+ {
+ /* Unlock the SRAM ECC bit */
+ WRITE_REG(hramcfg->Instance->ECCKEY, RAMCFG_ECC_KEY1);
+ WRITE_REG(hramcfg->Instance->ECCKEY, RAMCFG_ECC_KEY2);
+
+ /* Start the SRAM ECC mechanism and latching the error address */
+ hramcfg->Instance->CR &= ~(RAMCFG_CR_ECCE | RAMCFG_CR_ALE);
+
+ /* Update the RAMCFG state */
+ hramcfg->State = HAL_RAMCFG_STATE_READY;
+ }
+ }
+ else
+ {
+ /* Update the RAMCFG error code and return error */
+ hramcfg->ErrorCode = HAL_RAMCFG_ERROR_BUSY;
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Enable the RAMCFG error interrupts.
+ * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that
+ * contains the configuration information for the
+ * specified RAMCFG instance.
+ * @param Notifications : Select the notification to be enabled.
+ * This parameter can be any value of @ref
+ * RAMCFG_Interrupt group.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_RAMCFG_EnableNotification(RAMCFG_HandleTypeDef *hramcfg, uint32_t Notifications)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ /* Check the parameters */
+ assert_param(IS_RAMCFG_ECC_INSTANCE(hramcfg->Instance));
+ assert_param(IS_RAMCFG_INTERRUPT(Notifications));
+
+ /* Check RAMCFG state */
+ if (hramcfg->State == HAL_RAMCFG_STATE_READY)
+ {
+ /* Update RAMCFG peripheral state */
+ hramcfg->State = HAL_RAMCFG_STATE_BUSY;
+
+ /* Enable RAMCFG interrupts */
+ __HAL_RAMCFG_ENABLE_IT(hramcfg, Notifications);
+
+ /* Update the RAMCFG state */
+ hramcfg->State = HAL_RAMCFG_STATE_READY;
+
+ }
+ else
+ {
+ /* Update the RAMCFG error code and return error */
+ hramcfg->ErrorCode = HAL_RAMCFG_ERROR_BUSY;
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Disable the RAMCFG error interrupts.
+ * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that
+ * contains the configuration information for the
+ * specified RAMCFG instance.
+ * @param Notifications : Select the notification to be disabled.
+ * This parameter can be :
+ * RAMCFG_IT_SINGLEERR : Single Error Interrupt.
+ * RAMCFG_IT_DOUBLEERR : Double Error Interrupt.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_RAMCFG_DisableNotification(RAMCFG_HandleTypeDef *hramcfg, uint32_t Notifications)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ /* Check the parameters */
+ assert_param(IS_RAMCFG_ECC_INSTANCE(hramcfg->Instance));
+ assert_param(IS_RAMCFG_INTERRUPT(Notifications));
+
+ /* Check RAMCFG state */
+ if (hramcfg->State == HAL_RAMCFG_STATE_READY)
+ {
+ /* Update RAMCFG peripheral state */
+ hramcfg->State = HAL_RAMCFG_STATE_BUSY;
+
+ /* Disable RAMCFG interrupts */
+ __HAL_RAMCFG_DISABLE_IT(hramcfg, Notifications);
+
+ /* Update the RAMCFG state */
+ hramcfg->State = HAL_RAMCFG_STATE_READY;
+ }
+ else
+ {
+ /* Update the RAMCFG error code and return error */
+ hramcfg->ErrorCode = HAL_RAMCFG_ERROR_BUSY;
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Check if an ECC single error has occurred.
+ * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that
+ * contains the configuration information for the
+ * specified RAMCFG instance.
+ * @retval State of bit (1 or 0).
+ */
+uint32_t HAL_RAMCFG_IsECCSingleErrorDetected(RAMCFG_HandleTypeDef *hramcfg)
+{
+ /* Check the parameters */
+ assert_param(IS_RAMCFG_ECC_INSTANCE(hramcfg->Instance));
+
+ /* Return the state of SEDC flag */
+ return ((READ_BIT(hramcfg->Instance->ISR, RAMCFG_FLAG_SINGLEERR) == (RAMCFG_FLAG_SINGLEERR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if an ECC double error was occurred.
+ * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that
+ * contains the configuration information for the
+ * specified RAMCFG instance.
+ * @retval State of bit (1 or 0).
+ */
+uint32_t HAL_RAMCFG_IsECCDoubleErrorDetected(RAMCFG_HandleTypeDef *hramcfg)
+{
+ /* Check the parameters */
+ assert_param(IS_RAMCFG_ECC_INSTANCE(hramcfg->Instance));
+
+ /* Return the state of SEDC flag */
+ return ((READ_BIT(hramcfg->Instance->ISR, RAMCFG_FLAG_DOUBLEERR) == (RAMCFG_FLAG_DOUBLEERR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get the RAMCFG single error address.
+ * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that
+ * contains the configuration information for the
+ * specified RAMCFG instance.
+ * @retval Single error address offset.
+ */
+uint32_t HAL_RAMCFG_GetSingleErrorAddress(RAMCFG_HandleTypeDef *hramcfg)
+{
+ /* Check the parameters */
+ assert_param(IS_RAMCFG_ECC_INSTANCE(hramcfg->Instance));
+
+ return hramcfg->Instance->SEAR;
+}
+
+/**
+ * @brief Get the RAMCFG double error address.
+ * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that
+ * contains the configuration information for the
+ * specified RAMCFG instance.
+ * @retval Double error address offset.
+ */
+uint32_t HAL_RAMCFG_GetDoubleErrorAddress(RAMCFG_HandleTypeDef *hramcfg)
+{
+ /* Check the parameters */
+ assert_param(IS_RAMCFG_ECC_INSTANCE(hramcfg->Instance));
+
+ return hramcfg->Instance->DEAR;
+}
+/**
+ * @}
+ */
+
+/** @addtogroup RAMCFG_Exported_Functions_Group3
+ *
+@verbatim
+ ===============================================================================
+ ##### Wait State Functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to get and configure the wait state
+ value .
+ [..]
+ The HAL_RAMCFG_ConfigWaitState() function allows configuring the wait state
+ value.
+ The HAL_RAMCFG_GetWaitState() function allows getting the current wait state
+ value.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the wait state value for the given SRAM.
+ * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that
+ * contains the configuration information for the
+ * specified RAMCFG instance.
+ * @param WaitState : Select the value of wait state to be configured.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_RAMCFG_ConfigWaitState(RAMCFG_HandleTypeDef *hramcfg, uint32_t WaitState)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ /* Check the parameters */
+ assert_param(IS_RAMCFG_ALL_INSTANCE(hramcfg->Instance));
+ assert_param(IS_RAMCFG_WAITSTATE(WaitState));
+
+ /* Check RAMCFG state */
+ if (hramcfg->State == HAL_RAMCFG_STATE_READY)
+ {
+ /* Update RAMCFG peripheral state */
+ hramcfg->State = HAL_RAMCFG_STATE_BUSY;
+
+ /* Set the SRAM wait state */
+ hramcfg->Instance->CR = WaitState;
+
+ /* Update RAMCFG peripheral state */
+ hramcfg->State = HAL_RAMCFG_STATE_READY;
+ }
+ else
+ {
+ /* Update the RAMCFG error code and return error */
+ hramcfg->ErrorCode = HAL_RAMCFG_ERROR_BUSY;
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Get the current wait state value for the given SRAM.
+ * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that
+ * contains the configuration information for the
+ * specified RAMCFG instance.
+ * @retval Wait state value.
+ */
+uint32_t HAL_RAMCFG_GetWaitState(RAMCFG_HandleTypeDef *hramcfg)
+{
+ /* Check the parameters */
+ assert_param(IS_RAMCFG_ALL_INSTANCE(hramcfg->Instance));
+
+ /* Return the configured wait state number */
+ return (hramcfg->Instance->CR & RAMCFG_CR_WSC);
+}
+/**
+ * @}
+ */
+
+/** @addtogroup RAMCFG_Exported_Functions_Group4
+ *
+@verbatim
+ ===============================================================================
+ ##### Write Protection Functions #####
+ ===============================================================================
+ [..]
+ This section provides functions to enable write protection feature for
+ the page(s) of SRAM2.
+ [..]
+ The HAL_RAMCFG_EnableWriteProtection() function allows the user to enable the write
+ protection for the page(s) of SRAM2.
+ The HAL_RAMCFG_GetWaitState() function allows get the current wait state
+ value. Disabling SRAM2 page(s) protection is performed only by a glabal
+ peripheral reset or a by a system reset.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable write protection for the given page(s).
+ * Write protection feature can be disabled only by system reset.
+ * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that
+ * contains the configuration information for the
+ * specified RAMCFG instance.
+ * @param StartPage : Select the start page number.
+ * @param NbPage : Number of page to be protected.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_RAMCFG_EnableWriteProtection(RAMCFG_HandleTypeDef *hramcfg, uint32_t StartPage, uint32_t NbPage)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t page_mask_0 = 0U;
+ uint32_t page_mask_1 = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RAMCFG_WP_INSTANCE(hramcfg->Instance));
+ assert_param(IS_RAMCFG_WRITEPROTECTION_PAGE(StartPage + NbPage));
+
+ /* Check RAMCFG state */
+ if (hramcfg->State == HAL_RAMCFG_STATE_READY)
+ {
+ /* Update RAMCFG peripheral state */
+ hramcfg->State = HAL_RAMCFG_STATE_BUSY;
+
+ /* Repeat for page number to be protected */
+ for (uint32_t count = 0U; count < NbPage; count++)
+ {
+ if ((StartPage + count) < 32U)
+ {
+ page_mask_0 |= (1UL << (StartPage + count));
+ }
+ else
+ {
+ page_mask_1 |= (1UL << ((StartPage + count) - 32U));
+ }
+ }
+
+ /* Apply mask to protect pages */
+ SET_BIT(hramcfg->Instance->WPR1, page_mask_0);
+ SET_BIT(hramcfg->Instance->WPR2, page_mask_1);
+
+ /* Update the RAMCFG state */
+ hramcfg->State = HAL_RAMCFG_STATE_READY;
+ }
+ else
+ {
+ /* Update the RAMCFG error code and return error */
+ hramcfg->ErrorCode = HAL_RAMCFG_ERROR_BUSY;
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+/**
+ * @}
+ */
+
+/** @addtogroup RAMCFG_Exported_Functions_Group5
+ *
+@verbatim
+ ===============================================================================
+ ##### Erase Operation Functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing a hardware erase for the given SRAM.
+ [..]
+ The HAL_RAMCFG_Erase() function allows a hardware mass erase for the given
+ SRAM. The erase value for all SRAMs is 0.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Launch a Mass Erase for the given SRAM.
+ * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that
+ * contains the configuration information for the
+ * specified RAMCFG instance.
+
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_RAMCFG_Erase(RAMCFG_HandleTypeDef *hramcfg)
+{
+ uint32_t timeout = RAMCFG_TIMEOUT_VALUE;
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Check the parameters */
+ assert_param(IS_RAMCFG_ALL_INSTANCE(hramcfg->Instance));
+
+ /* Check RAMCFG state */
+ if (hramcfg->State == HAL_RAMCFG_STATE_READY)
+ {
+ /* Update RAMCFG peripheral state */
+ hramcfg->State = HAL_RAMCFG_STATE_BUSY;
+
+ /* Unlock the RAMCFG erase bit */
+ WRITE_REG(hramcfg->Instance->ERKEYR, RAMCFG_ERASE_KEY1);
+ WRITE_REG(hramcfg->Instance->ERKEYR, RAMCFG_ERASE_KEY2);
+
+ /* Start the SRAM erase operation */
+ hramcfg->Instance->CR |= RAMCFG_CR_SRAMER;
+
+ /*
+ Wait for the SRAM hardware erase operation to complete by polling on
+ SRAMBUSY flag to be reset.
+ */
+ while (__HAL_RAMCFG_GET_FLAG(hramcfg, RAMCFG_FLAG_SRAMBUSY) != 0U)
+ {
+ if (timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > timeout) || (timeout == 0U))
+ {
+ /* Update the RAMCFG error code */
+ hramcfg->ErrorCode = HAL_RAMCFG_ERROR_TIMEOUT;
+
+ /* Update the RAMCFG state and return error status */
+ hramcfg->State = HAL_RAMCFG_STATE_ERROR;
+ return HAL_ERROR;
+ }
+ }
+ }
+ }
+ else
+ {
+ /* Update the error code and return error status */
+ hramcfg->ErrorCode = HAL_RAMCFG_ERROR_BUSY;
+ return HAL_ERROR;
+ }
+
+ /* Update the RAMCFG state */
+ hramcfg->State = HAL_RAMCFG_STATE_READY;
+
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/** @addtogroup RAMCFG_Exported_Functions_Group6
+ *
+@verbatim
+ ===============================================================================
+ ##### Handle Interrupt and Callbacks Functions #####
+ ===============================================================================
+ [..]
+ This section provides functions to handle RAMCFG interrupts and
+ Register / UnRegister the different callbacks.
+ [..]
+ The HAL_RAMCFG_IRQHandler() function allows the user to handle the active RAMCFG
+ interrupt request.
+ The HAL_RAMCFG_RegisterCallback() function allows the user to register the selected
+ RAMCFG callbacks.
+ The HAL_RAMCFG_UnRegisterCallback() function allows the user to unregister the
+ selected RAMCFG callbacks.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Handles RAMCFG interrupt request.
+ * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that
+ * contains the configuration information for the
+ * specified RAMCFG instance.
+ * @retval None.
+ */
+void HAL_RAMCFG_IRQHandler(RAMCFG_HandleTypeDef *hramcfg)
+{
+ /* Single Error Interrupt Management ****************************************/
+ if (__HAL_RAMCFG_GET_IT_SOURCE(hramcfg, RAMCFG_IT_SINGLEERR) != 0U)
+ {
+ if (__HAL_RAMCFG_GET_FLAG(hramcfg, RAMCFG_FLAG_SINGLEERR) != 0U)
+ {
+ /* Clear active flags */
+ __HAL_RAMCFG_CLEAR_FLAG(hramcfg, RAMCFG_FLAG_SINGLEERR);
+
+#if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1)
+ /* Check if a valid single error callback is registered */
+ if (hramcfg->DetectSingleErrorCallback != NULL)
+ {
+ /* Single error detection callback */
+ hramcfg->DetectSingleErrorCallback(hramcfg);
+ }
+#else
+ HAL_RAMCFG_DetectSingleErrorCallback(hramcfg);
+#endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* Double Error Interrupt Management ****************************************/
+ if (__HAL_RAMCFG_GET_IT_SOURCE(hramcfg, RAMCFG_IT_DOUBLEERR) != 0U)
+ {
+ if (__HAL_RAMCFG_GET_FLAG(hramcfg, RAMCFG_FLAG_DOUBLEERR) != 0U)
+ {
+ /* Clear active flags */
+ __HAL_RAMCFG_CLEAR_FLAG(hramcfg, RAMCFG_FLAG_DOUBLEERR);
+
+#if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1)
+ /* Check if a valid double error callback is registered */
+ if (hramcfg->DetectDoubleErrorCallback != NULL)
+ {
+ /* Double error detection callback */
+ hramcfg->DetectDoubleErrorCallback(hramcfg);
+ }
+#else
+ HAL_RAMCFG_DetectDoubleErrorCallback(hramcfg);
+#endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */
+ }
+ }
+}
+
+/**
+ * @brief RAMCFG single error detection callback.
+ * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that contains
+ * the configuration information for the specified RAMCFG.
+ * @retval None.
+ */
+__weak void HAL_RAMCFG_DetectSingleErrorCallback(RAMCFG_HandleTypeDef *hramcfg)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hramcfg);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RAMCFG_DetectSingleErrorCallback can be implemented in
+ the user file. */
+}
+
+/**
+ * @brief RAMCFG double error detection callback.
+ * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that contains
+ * the configuration information for the specified RAMCFG.
+ * @retval None.
+ */
+__weak void HAL_RAMCFG_DetectDoubleErrorCallback(RAMCFG_HandleTypeDef *hramcfg)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hramcfg);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RAMCFG_DetectDoubleErrorCallback can be implemented in
+ the user file. */
+}
+
+#if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register RAMCFG callbacks.
+ * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that
+ * contains the configuration information for the
+ * specified RAMCFG instance.
+ * @param CallbackID : User Callback identifier a HAL_MDMA_CallbackIDTypeDef
+ * ENUM as parameter.
+ * @param pCallback : Pointer to private callback function.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_RAMCFG_RegisterCallback(RAMCFG_HandleTypeDef *hramcfg,
+ HAL_RAMCFG_CallbackIDTypeDef CallbackID,
+ void (* pCallback)(RAMCFG_HandleTypeDef *_hramcfg))
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code and return error */
+ hramcfg->ErrorCode |= HAL_RAMCFG_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_RAMCFG_ALL_INSTANCE(hramcfg->Instance));
+
+ /* Check RAMCFG state */
+ if (hramcfg->State == HAL_RAMCFG_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_RAMCFG_SE_DETECT_CB_ID:
+ /* Register single error callback */
+ hramcfg->DetectSingleErrorCallback = pCallback;
+ break;
+
+ case HAL_RAMCFG_DE_DETECT_CB_ID:
+ /* Register single error callback */
+ hramcfg->DetectDoubleErrorCallback = pCallback;
+ break;
+
+ case HAL_RAMCFG_MSPINIT_CB_ID :
+ /* Register msp init callback */
+ hramcfg->MspInitCallback = pCallback;
+ break;
+
+ case HAL_RAMCFG_MSPDEINIT_CB_ID :
+ /* Register msp de-init callback */
+ hramcfg->MspDeInitCallback = pCallback;
+ break;
+
+ default:
+ /* Update the error code and return error */
+ hramcfg->ErrorCode |= HAL_RAMCFG_ERROR_INVALID_CALLBACK;
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hramcfg->State == HAL_RAMCFG_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_RAMCFG_MSPINIT_CB_ID :
+ /* Register msp init callback */
+ hramcfg->MspInitCallback = pCallback;
+ break;
+
+ case HAL_RAMCFG_MSPDEINIT_CB_ID :
+ /* Register msp de-init callback */
+ hramcfg->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code and return error */
+ hramcfg->ErrorCode |= HAL_RAMCFG_ERROR_INVALID_CALLBACK;
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code and return error */
+ hramcfg->ErrorCode = HAL_RAMCFG_ERROR_INVALID_CALLBACK;
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief UnRegister RAMCFG callbacks.
+ * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that
+ * contains the configuration information for the
+ * specified RAMCFG instance.
+ * @param CallbackID : User Callback identifier a HAL_MDMA_CallbackIDTypeDef
+ * ENUM as parameter.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_RAMCFG_UnRegisterCallback(RAMCFG_HandleTypeDef *hramcfg, HAL_RAMCFG_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_RAMCFG_ALL_INSTANCE(hramcfg->Instance));
+
+ /* Check RAMCFG state */
+ if (hramcfg->State == HAL_RAMCFG_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_RAMCFG_SE_DETECT_CB_ID:
+ /* UnRegister single error callback */
+ hramcfg->DetectSingleErrorCallback = NULL;
+ break;
+
+ case HAL_RAMCFG_DE_DETECT_CB_ID:
+ /* UnRegister double error callback */
+ hramcfg->DetectDoubleErrorCallback = NULL;
+ break;
+
+ case HAL_RAMCFG_MSPINIT_CB_ID :
+ /* UnRegister msp init callback */
+ hramcfg->MspInitCallback = NULL;
+ break;
+
+ case HAL_RAMCFG_MSPDEINIT_CB_ID :
+ /* UnRegister msp de-init callback */
+ hramcfg->MspDeInitCallback = NULL;
+ break;
+
+ case HAL_RAMCFG_ALL_CB_ID:
+ /* UnRegister all available callbacks */
+ hramcfg->DetectSingleErrorCallback = NULL;
+ hramcfg->DetectDoubleErrorCallback = NULL;
+ hramcfg->MspDeInitCallback = NULL;
+ hramcfg->MspInitCallback = NULL;
+ break;
+
+ default:
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hramcfg->State == HAL_RAMCFG_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_RAMCFG_MSPINIT_CB_ID :
+ /* UnRegister msp init callback */
+ hramcfg->MspInitCallback = NULL;
+ break;
+
+ case HAL_RAMCFG_MSPDEINIT_CB_ID :
+ /* UnRegister msp de-init callback */
+ hramcfg->MspDeInitCallback = NULL;
+ break;
+
+ case HAL_RAMCFG_ALL_CB_ID:
+ /* UnRegister all available callbacks */
+ hramcfg->MspDeInitCallback = NULL;
+ hramcfg->MspInitCallback = NULL;
+ break;
+
+ default :
+ /* Update the error code */
+ hramcfg->ErrorCode |= HAL_RAMCFG_ERROR_INVALID_CALLBACK;
+
+ /* Update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code and return error */
+ hramcfg->ErrorCode = HAL_RAMCFG_ERROR_INVALID_CALLBACK;
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+/**
+ * @}
+ */
+#endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */
+
+/** @addtogroup RAMCFG_Exported_Functions_Group7
+ *
+@verbatim
+ ===============================================================================
+ ##### State and Error Functions #####
+ ===============================================================================
+ [..]
+ This section provides functions to check and get the RAMCFG state
+ and the error code .
+ [..]
+ The HAL_RAMCFG_GetState() function allows the user to get the RAMCFG peripheral
+ state.
+ The HAL_RAMCFG_GetError() function allows the user to get the RAMCFG peripheral error
+ code.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Get the RAMCFG peripheral state.
+ * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that
+ * contains the configuration information for the
+ * specified RAMCFG instance.
+ * @retval RAMCFG state.
+ */
+HAL_RAMCFG_StateTypeDef HAL_RAMCFG_GetState(RAMCFG_HandleTypeDef *hramcfg)
+{
+ /* Check the parameters */
+ assert_param(IS_RAMCFG_ALL_INSTANCE(hramcfg->Instance));
+
+ /* Return the RAMCFG state */
+ return hramcfg->State;
+}
+
+/**
+ * @brief Get the RAMCFG peripheral error code.
+ * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that
+ * contains the configuration information for the
+ * specified RAMCFG instance.
+ * @retval RAMCFG error code.
+ */
+uint32_t HAL_RAMCFG_GetError(RAMCFG_HandleTypeDef *hramcfg)
+{
+ /* Check the parameters */
+ assert_param(IS_RAMCFG_ALL_INSTANCE(hramcfg->Instance));
+
+ /* Return the RAMCFG error code */
+ return hramcfg->ErrorCode;
+}
+/**
+ * @}
+ */
+
+
+#endif /* HAL_RAMCFG_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc.c
new file mode 100644
index 00000000..60c1e06e
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc.c
@@ -0,0 +1,2223 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_rcc.c
+ * @author MCD Application Team
+ * @brief RCC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Reset and Clock Control (RCC) peripheral:
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### RCC specific features #####
+ ==============================================================================
+ [..]
+ After reset the device is running from Multiple Speed Internal oscillator
+ (4 MHz) with Flash 0 wait state. Flash prefetch buffer, D-Cache
+ and I-Cache are disabled, and all peripherals are off except internal
+ SRAM, Flash and JTAG.
+
+ (+) There is no prescaler on High speed (AHBs) and Low speed (APBs) busses:
+ all peripherals mapped on these busses are running at MSI speed.
+ (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
+ (+) All GPIOs are in analog mode, except the JTAG pins which
+ are assigned to be used for debug purpose.
+
+ [..]
+ Once the device started from reset, the user application has to:
+ (+) Configure the clock source to be used to drive the System clock
+ (if the application needs higher frequency/performance)
+ (+) Configure the System clock frequency and Flash settings
+ (+) Configure the AHB and APB busses prescalers
+ (+) Enable the clock for the peripheral(s) to be used
+ (+) Configure the clock source(s) for peripherals which clocks are not
+ derived from the System clock (SAIx, SYSTICK, RTC, ADC, USB OTG FS/SDMMC1/RNG)
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup RCC RCC
+ * @brief RCC HAL module driver
+ * @{
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RCC_Private_Constants RCC Private Constants
+ * @{
+ */
+#define PLLDIVR_RESET_VALUE (0x01010280U)
+/**
+ * @}
+ */
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCC_Private_Macros
+ * @{
+ */
+#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
+ (((__OSCILLATOR__) & ~RCC_OSCILLATORTYPE_ALL) == 0x00U))
+
+#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
+ ((__HSE__) == RCC_HSE_BYPASS) || ((__HSE__) == RCC_HSE_BYPASS_DIGITAL))
+
+#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
+ ((__LSE__) == RCC_LSE_BYPASS))
+
+#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
+
+#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)( RCC_ICSCR3_HSITRIM >>\
+ RCC_ICSCR3_HSITRIM_Pos))
+
+#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
+
+#define IS_RCC_LSIDIV(__LSIDIV__) (((__LSIDIV__) == RCC_LSI_DIV1) || ((__LSIDIV__) == RCC_LSI_DIV128))
+
+#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))
+
+#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 255U)
+
+#define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))
+
+#define IS_RCC_SHSI(__SHSI__) (((__SHSI__) == RCC_SHSI_OFF) || ((__SHSI__) == RCC_SHSI_ON))
+
+#define IS_RCC_MSIK(__MSIK__) (((__MSIK__) == RCC_MSIK_OFF) || ((__MSIK__) == RCC_MSIK_ON))
+
+#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || \
+ ((PLL) == RCC_PLL_ON))
+
+#define IS_RCC_PLLMBOOST_VALUE(VALUE) (((VALUE) == RCC_PLLMBOOST_DIV1) || \
+ ((VALUE) == RCC_PLLMBOOST_DIV2) || \
+ ((VALUE) == RCC_PLLMBOOST_DIV4) || \
+ ((VALUE) == RCC_PLLMBOOST_DIV6) || \
+ ((VALUE) == RCC_PLLMBOOST_DIV8) || \
+ ((VALUE) == RCC_PLLMBOOST_DIV10) || \
+ ((VALUE) == RCC_PLLMBOOST_DIV12) || \
+ ((VALUE) == RCC_PLLMBOOST_DIV14) || \
+ ((VALUE) == RCC_PLLMBOOST_DIV16))
+
+#define IS_RCC_PLLCLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL1_DIVP) || \
+ ((VALUE) == RCC_PLL1_DIVQ) || \
+ ((VALUE) == RCC_PLL1_DIVR))
+
+#define IS_RCC_PLLRGE_VALUE(VALUE) (((VALUE) == RCC_PLLVCIRANGE_0) || \
+ ((VALUE) == RCC_PLLVCIRANGE_1))
+
+#define IS_RCC_PLLFRACN_VALUE(VALUE) ((VALUE) <= 8191U)
+
+#define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 0x1FU))
+
+#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \
+ ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
+ ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
+ ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
+
+#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV512))
+
+#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
+ ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
+ ((__PCLK__) == RCC_HCLK_DIV16))
+
+#define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1)
+
+#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
+ ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
+ ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
+ ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
+ ((__SOURCE__) == RCC_MCO1SOURCE_PLL1CLK) || \
+ ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \
+ ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \
+ ((__SOURCE__) == RCC_MCO1SOURCE_HSI48)|| \
+ ((__SOURCE__) == RCC_MCO1SOURCE_MSIK))
+
+#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \
+ ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \
+ ((__DIV__) == RCC_MCODIV_16))
+
+#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \
+ ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \
+ ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \
+ ((__DRIVE__) == RCC_LSEDRIVE_HIGH))
+
+#define IS_RCC_ITEM_ATTRIBUTES(ITEM) ((0U < (ITEM)) && ((ITEM) <= 0x1FFFU))
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define IS_RCC_ATTRIBUTES(ATTRIBUTES) (((ATTRIBUTES) == RCC_SEC_PRIV) || \
+ ((ATTRIBUTES) == RCC_SEC_NPRIV) || \
+ ((ATTRIBUTES) == RCC_NSEC_PRIV) || \
+ ((ATTRIBUTES) == RCC_NSEC_NPRIV))
+#else
+#define IS_RCC_ATTRIBUTES(ATTRIBUTES) (((ATTRIBUTES) == RCC_NSEC_NPRIV) || ((ATTRIBUTES) == RCC_NSEC_PRIV))
+#endif /* __ARM_FEATURE_CMSE */
+/**
+ * @}
+ */
+
+/* Private define ------------------------------------------------------------*/
+/** @defgroup RCC_Private_Constants RCC Private Constants
+ * @{
+ */
+#define LSI_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */
+#define HSI48_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */
+#define SHSI_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */
+#define MSIK_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */
+#define PLL_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */
+#define CLOCKSWITCH_TIMEOUT_VALUE 5000UL /* 5 s */
+#define EPOD_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup RCC_Private_Macros RCC Private Macros
+ * @{
+ */
+
+#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
+
+#define MCO1_GPIO_PORT GPIOA
+
+#define MCO1_PIN GPIO_PIN_8
+
+#define RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) \
+ (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (uint32_t)(__HAL_RCC_PLLSOURCE__)))
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup RCC_Private_Functions RCC Private Functions
+ * @{
+ */
+static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Functions RCC Exported Functions
+ * @{
+ */
+
+/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to configure the internal and external oscillators
+ (HSE, HSI, LSE, MSI, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
+ and APB2).
+
+ [..] Internal/external clock and PLL configuration
+ (+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through
+ the PLL as System clock source.
+
+ (+) MSI (Multiple Speed Internal): Its frequency is software trimmable from 100KHZ to 48MHZ.
+ It can be used to generate the clock for the USB OTG FS (48 MHz).
+ The number of flash wait states is automatically adjusted when MSI range is updated with
+ HAL_RCC_OscConfig() and the MSI is used as System clock source.
+
+ (+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC
+ clock source.
+
+ (+) HSE (high-speed external): 4 to 48 MHz crystal oscillator used directly or
+ through the PLL as System clock source. Can be used also optionally as RTC clock source.
+
+ (+) LSE (low-speed external): 32.768 KHz oscillator used optionally as RTC clock source.
+
+ (+) PLL (clocked by HSI, HSE or MSI) providing up to three independent output clocks:
+ (++) The first output is used to generate the high speed system clock (up to 80MHz).
+ (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
+ the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
+ (++) The third output is used to generate an accurate clock to achieve
+ high-quality audio performance on SAI interface.
+
+ (+) PLL2 (clocked by HSI, HSE or MSI) providing up to three independent output clocks:
+ (++) The first output is used to generate SAR ADC1 clock.
+ (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
+ the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
+ (++) The Third output is used to generate an accurate clock to achieve
+ high-quality audio performance on SAI interface.
+
+ (+) PLL3 (clocked by HSI , HSE or MSI) providing up to two independent output clocks:
+ (++) The first output is used to generate SAR ADC4 clock.
+ (++) The second output is used to generate an accurate clock to achieve
+ high-quality audio performance on SAI interface.
+
+ (+) CSS (Clock security system): once enabled, if a HSE clock failure occurs
+ (HSE used directly or through PLL as System clock source), the System clock
+ is automatically switched to HSI and an interrupt is generated if enabled.
+ The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt)
+ exception vector.
+
+ (+) MCO (microcontroller clock output): used to output MSI, LSI, HSI, LSE, HSE or
+ main PLL clock (through a configurable prescaler) on PA8 pin.
+
+ [..] System, AHB and APB busses clocks configuration
+ (+) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI,
+ HSE and main PLL.
+ The AHB clock (HCLK) is derived from System clock through configurable
+ prescaler and used to clock the CPU, memory and peripherals mapped
+ on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
+ from AHB clock through configurable prescalers and used to clock
+ the peripherals mapped on these busses. You can use
+ "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
+
+ -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
+
+ (+@) SAI: the SAI clock can be derived either from a specific PLL (PLL2) or (PLL3) or
+ from an external clock mapped on the SAI_CKIN pin.
+ You have to use HAL_RCCEx_PeriphCLKConfig() function to configure this clock.
+ (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
+ divided by 2 to 31.
+ You have to use __HAL_RCC_RTC_ENABLE() and HAL_RCCEx_PeriphCLKConfig() function
+ to configure this clock.
+ (+@) USB OTG FS, SDMMC1 and RNG: USB OTG FS requires a frequency equal to 48 MHz
+ to work correctly, while the SDMMC1 and RNG peripherals require a frequency
+ equal or lower than to 48 MHz. This clock is derived of the main PLL or PLL2
+ through PLLQ divider. You have to enable the peripheral clock and use
+ HAL_RCCEx_PeriphCLKConfig() function to configure this clock.
+ (+@) IWDG clock which is always the LSI clock.
+
+
+ (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 80 MHz.
+ The clock source frequency should be adapted depending on the device voltage range
+ as listed in the Reference Manual "Clock source frequency versus voltage scaling" chapter.
+
+ @endverbatim
+
+
+ Table 1. HCLK clock frequency for STM32U5xx devices
+ +-------------------------------------------------------+----------------------------------------+
+ | Latency | HCLK clock frequency (MHz) 0.9V-1.2V |
+ | |-------------------------------------|---------------------+------------------|
+ | | voltage range 1 | voltage range 2 | voltage range 3 | voltage range 4 |
+ | | 1.1 V - 1.2V | 1.0 V - 1.1V | 0.9 V - 1.0V | 0.9V |
+ |-----------------|------------------|------------------|---------------------|------------------|
+ |0WS(1 CPU cycles)| 0 < HCLK <= 32 | 0 < HCLK <= 25 | 0 < HCLK <= 12.5 | 0 < HCLK <= 8 |
+ |-----------------|------------------|------------------|---------------------|------------------|
+ |1WS(2 CPU cycles)| 32 < HCLK <= 64 | 25 < HCLK <= 50 | 12.5 < HCLK <= 25 | 8 < HCLK <= 16 |
+ |-----------------|------------------|------------------|---------------------|------------------|
+ |2WS(3 CPU cycles)| 64 < HCLK <= 96 | 50 < HCLK <= 75 | 25 < HCLK <= 37.5 | 16 < HCLK <= 24 |
+ |-----------------|------------------|------------------|---------------------|------------------|
+ |3WS(4 CPU cycles)| 96 < HCLK <= 128 | 75 < HCLK <= 100 | 37.5 < HCLK <= 50 | - |
+ |-----------------|------------------|------------------|---------------------|------------------|
+ |4WS(5 CPU cycles)|128 < HCLK <= 160 | - | - | - |
+ +-----------------+------------------+------------------+---------------------+------------------+
+ * @{
+ */
+
+/**
+ * @brief Reset the RCC clock configuration to the default reset state.
+ * @note The default reset state of the clock configuration is given below:
+ * - MSI ON and used as system clock source
+ * - HSE, HSI, PLL, PLL2 and PLLISAI2 OFF
+ * - AHB, APB1 and APB2 prescaler set to 1
+ * - CSS, MCO1 OFF
+ * - All interrupts disabled
+ * - All interrupt and reset flags cleared
+ * @note This function doesn't modify the configuration of the
+ * - Peripheral clocks
+ * - LSI, LSE and RTC clocks
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCC_DeInit(void)
+{
+ uint32_t tickstart;
+
+ /* Increasing the CPU frequency */
+ if (FLASH_LATENCY_DEFAULT > __HAL_FLASH_GET_LATENCY())
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT);
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ if (__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ tickstart = HAL_GetTick();
+
+ /* Set MSION bit */
+ SET_BIT(RCC->CR, RCC_CR_MSISON);
+
+ /* Insure MSIRDY bit is set before writing default MSIRANGE value */
+ while (READ_BIT(RCC->CR, RCC_CR_MSISRDY) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set MSIRANGE default value */
+ MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSISRANGE, RCC_MSIRANGE_4);
+
+ /* Set MSITRIM default value */
+ WRITE_REG(RCC->ICSCR2, 0x00084210U);
+
+ /* Set MSIKRANGE default value */
+ MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSIKRANGE, RCC_MSIKRANGE_4);
+
+ /* Set MSIRGSEL default value */
+ MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL, 0x0U);
+
+ tickstart = HAL_GetTick();
+
+ /* Reset CFGR register (MSI is selected as system clock source) */
+ CLEAR_REG(RCC->CFGR1);
+ CLEAR_REG(RCC->CFGR2);
+
+ /* Wait till clock switch is ready */
+ while (READ_BIT(RCC->CFGR1, RCC_CFGR1_SWS) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Reset MSIKON, HSECSSON , HSEON, HSEBYP, HSION, HSIKERON, PLL1ON, PLL2ON, PLL3ON bits */
+ CLEAR_BIT(RCC->CR, RCC_CR_MSIKON | RCC_CR_MSIPLLSEL | RCC_CR_MSIPLLFAST | RCC_CR_MSIKERON | RCC_CR_CSSON | \
+ RCC_CR_HSION | RCC_CR_HSIKERON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON | RCC_CR_HSI48ON | \
+ RCC_CR_HSEON | RCC_CR_SHSION);
+
+ /* Reset HSEBYP & HSEEXT bits */
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP | RCC_CR_HSEEXT);
+
+ tickstart = HAL_GetTick();
+
+ /* Clear PLL1ON bit */
+ CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON);
+
+ /* Wait till PLL1 is disabled */
+ while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ tickstart = HAL_GetTick();
+
+ /* Reset PLL2N bit */
+ CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
+
+ /* Wait till PLL2 is disabled */
+ while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ tickstart = HAL_GetTick();
+
+ /* Reset PLL3 bit */
+ CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
+
+ /* Wait till PLL3 is disabled */
+ while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Reset PLL1CFGR register */
+ CLEAR_REG(RCC->PLL1CFGR);
+
+ /* Reset PLL1DIVR register */
+ WRITE_REG(RCC->PLL1DIVR, PLLDIVR_RESET_VALUE);
+
+ /* Reset PLL1FRACR register */
+ CLEAR_REG(RCC->PLL1FRACR);
+
+ /* Reset PLL2CFGR register */
+ CLEAR_REG(RCC->PLL2CFGR);
+
+ /* Reset PLL2DIVR register */
+ WRITE_REG(RCC->PLL2DIVR, PLLDIVR_RESET_VALUE);
+
+ /* Reset PLL2FRACR register */
+ CLEAR_REG(RCC->PLL2FRACR);
+
+ /* Reset PLL3CFGR register */
+ CLEAR_REG(RCC->PLL3CFGR);
+
+ /* Reset PLL3DIVR register */
+ WRITE_REG(RCC->PLL3DIVR, PLLDIVR_RESET_VALUE);
+
+ /* Reset PLL3FRACR register */
+ CLEAR_REG(RCC->PLL3FRACR);
+
+ /* Disable all interrupts */
+ CLEAR_REG(RCC->CIER);
+
+ /* Clear all interrupts flags */
+ WRITE_REG(RCC->CICR, 0xFFFFFFFFU);
+
+ /* Reset all CSR flags */
+ SET_BIT(RCC->CSR, RCC_CSR_RMVF);
+
+ /* Update the SystemCoreClock global variable */
+ SystemCoreClock = MSI_VALUE;
+
+ /* Decreasing the number of wait states because of lower CPU frequency */
+ if (FLASH_LATENCY_DEFAULT < __HAL_FLASH_GET_LATENCY())
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT);
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ if (__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Adapt Systick interrupt period */
+ return (HAL_InitTick(TICK_INT_PRIORITY));
+
+}
+
+/**
+ * @brief Initialize the RCC Oscillators according to the specified parameters in the
+ * RCC_OscInitTypeDef.
+ * @param pRCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
+ * contains the configuration information for the RCC Oscillators.
+ * @note The PLL is not disabled when used as system clock.
+ * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
+ * supported by this function. User should request a transition to LSE Off
+ * first and then LSE On or LSE Bypass.
+ * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
+ * supported by this function. User should request a transition to HSE Off
+ * first and then HSE On or HSE Bypass.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct)
+{
+ uint32_t tickstart;
+ HAL_StatusTypeDef status;
+ uint32_t sysclk_source;
+ uint32_t pll_config;
+ FlagStatus pwrboosten = RESET;
+
+ /* Check Null pointer */
+ if (pRCC_OscInitStruct == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_RCC_OSCILLATORTYPE(pRCC_OscInitStruct->OscillatorType));
+
+ sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
+ pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
+
+ /*----------------------------- MSI Configuration --------------------------*/
+ if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_MSI(pRCC_OscInitStruct->MSIState));
+ assert_param(IS_RCC_MSICALIBRATION_VALUE(pRCC_OscInitStruct->MSICalibrationValue));
+ assert_param(IS_RCC_MSI_CLOCK_RANGE(pRCC_OscInitStruct->MSIClockRange));
+
+ /*Check if MSI is used as system clock or as PLL source when PLL is selected as system clock*/
+
+ if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) ||
+ ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_MSI)))
+ {
+ if ((READ_BIT(RCC->CR, RCC_CR_MSISRDY) != 0U) && (pRCC_OscInitStruct->MSIState == RCC_MSI_OFF))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Otherwise, just the calibration and MSI range change are allowed */
+ else
+ {
+ /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
+ must be correctly programmed according to the frequency of the CPU clock
+ (HCLK) and the supply voltage of the device */
+ if (pRCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
+ {
+ /* Decrease number of wait states update if necessary */
+ /* Only possible when MSI is the System clock source */
+ if(sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI)
+ {
+ if (RCC_SetFlashLatencyFromMSIRange(pRCC_OscInitStruct->MSIClockRange) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Selects the Multiple Speed oscillator (MSI) clock range */
+ __HAL_RCC_MSI_RANGE_CONFIG(pRCC_OscInitStruct->MSIClockRange);
+ /* Adjusts the Multiple Speed oscillator (MSI) calibration value */
+ __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST((pRCC_OscInitStruct->MSICalibrationValue), \
+ (pRCC_OscInitStruct->MSIClockRange));
+ }
+ else
+ {
+ /* Else, keep current flash latency while decreasing applies */
+ /* Selects the Multiple Speed oscillator (MSI) clock range */
+ __HAL_RCC_MSI_RANGE_CONFIG(pRCC_OscInitStruct->MSIClockRange);
+ /* Adjusts the Multiple Speed oscillator (MSI) calibration value */
+ __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST((pRCC_OscInitStruct->MSICalibrationValue), \
+ (pRCC_OscInitStruct->MSIClockRange));
+
+ if(sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI)
+ {
+ if (RCC_SetFlashLatencyFromMSIRange(pRCC_OscInitStruct->MSIClockRange) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Update the SystemCoreClock global variable */
+ (void) HAL_RCC_GetHCLKFreq();
+ /* Configure the source of time base considering new system clocks settings*/
+ status = HAL_InitTick(uwTickPrio);
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ }
+ }
+ else
+ {
+ /* Check the MSI State */
+ if (pRCC_OscInitStruct->MSIState != RCC_MSI_OFF)
+ {
+ /* Enable the Internal High Speed oscillator (MSI) */
+ __HAL_RCC_MSI_ENABLE();
+
+ tickstart = HAL_GetTick();
+
+ /* Wait till MSI is ready */
+ while (READ_BIT(RCC->CR, RCC_CR_MSISRDY) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Selects the Multiple Speed oscillator (MSI) clock range */
+ __HAL_RCC_MSI_RANGE_CONFIG(pRCC_OscInitStruct->MSIClockRange);
+ /* Adjusts the Multiple Speed oscillator (MSI) calibration value */
+ __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST((pRCC_OscInitStruct->MSICalibrationValue), \
+ (pRCC_OscInitStruct->MSIClockRange));
+
+ }
+ else
+ {
+ /* Disable the Internal High Speed oscillator (MSI) */
+ __HAL_RCC_MSI_DISABLE();
+
+ tickstart = HAL_GetTick();
+
+ /* Wait till MSI is ready */
+ while (READ_BIT(RCC->CR, RCC_CR_MSISRDY) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+ /*------------------------------- HSE Configuration ------------------------*/
+ if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSE(pRCC_OscInitStruct->HSEState));
+
+ /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
+ if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) ||
+ ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE)))
+ {
+ if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (pRCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+ {
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Set the new HSE configuration ---------------------------------------*/
+ __HAL_RCC_HSE_CONFIG(pRCC_OscInitStruct->HSEState);
+
+ /* Check the HSE State */
+ if (pRCC_OscInitStruct->HSEState != RCC_HSE_OFF)
+ {
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSE is ready */
+ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSE is disabled */
+ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+ /*----------------------------- HSI Configuration --------------------------*/
+ if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSI(pRCC_OscInitStruct->HSIState));
+ assert_param(IS_RCC_HSI_CALIBRATION_VALUE(pRCC_OscInitStruct->HSICalibrationValue));
+
+ /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
+ if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI) ||
+ ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI)))
+ {
+ /* When HSI is used as system clock it will not be disabled */
+ if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (pRCC_OscInitStruct->HSIState == RCC_HSI_OFF))
+ {
+ return HAL_ERROR;
+ }
+ /* Otherwise, just the calibration is allowed */
+ else
+ {
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value */
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(pRCC_OscInitStruct->HSICalibrationValue);
+ }
+ }
+ else
+ {
+ /* Check the HSI State */
+ if (pRCC_OscInitStruct->HSIState != RCC_HSI_OFF)
+ {
+ /* Enable the Internal High Speed oscillator (HSI) */
+ __HAL_RCC_HSI_ENABLE();
+
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is ready */
+ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value */
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(pRCC_OscInitStruct->HSICalibrationValue);
+ }
+ else
+ {
+ /* Disable the Internal High Speed oscillator (HSI) */
+ __HAL_RCC_HSI_DISABLE();
+
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is disabled */
+ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+ /*------------------------------ LSI Configuration -------------------------*/
+ if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_LSI(pRCC_OscInitStruct->LSIState));
+
+ FlagStatus pwrclkchanged = RESET;
+
+ /* Update LSI configuration in Backup Domain control register */
+ /* Requires to enable write access to Backup Domain of necessary */
+ if (__HAL_RCC_PWR_IS_CLK_DISABLED())
+ {
+ __HAL_RCC_PWR_CLK_ENABLE();
+ pwrclkchanged = SET;
+ }
+
+ if (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP))
+ {
+ /* Enable write access to Backup domain */
+ SET_BIT(PWR->DBPR, PWR_DBPR_DBP);
+
+ /* Wait for Backup domain Write protection disable */
+ tickstart = HAL_GetTick();
+
+ while (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP))
+ {
+ if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Check the LSI State */
+ if (pRCC_OscInitStruct->LSIState != RCC_LSI_OFF)
+ {
+ uint32_t bdcr_temp = RCC->BDCR;
+
+ /* Check LSI division factor */
+ assert_param(IS_RCC_LSIDIV(pRCC_OscInitStruct->LSIDiv));
+
+ if (pRCC_OscInitStruct->LSIDiv != (bdcr_temp & RCC_BDCR_LSIPREDIV))
+ {
+ if (((bdcr_temp & RCC_BDCR_LSIRDY) == RCC_BDCR_LSIRDY) && \
+ ((bdcr_temp & RCC_BDCR_LSION) != RCC_BDCR_LSION))
+ {
+ /* If LSIRDY is set while LSION is not enabled, LSIPREDIV can't be updated */
+ /* The LSIPREDIV cannot be changed if the LSI is used by the IWDG or by the RTC */
+ return HAL_ERROR;
+ }
+
+ /* Turn off LSI before changing RCC_BDCR_LSIPREDIV */
+ if ((bdcr_temp & RCC_BDCR_LSION) == RCC_BDCR_LSION)
+ {
+ __HAL_RCC_LSI_DISABLE();
+
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSI is disabled */
+ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSIRDY) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Set LSI division factor */
+ MODIFY_REG(RCC->BDCR, RCC_BDCR_LSIPREDIV, pRCC_OscInitStruct->LSIDiv);
+ }
+
+ /* Enable the Internal Low Speed oscillator (LSI) */
+ __HAL_RCC_LSI_ENABLE();
+
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSI is ready */
+ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSIRDY) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Disable the Internal Low Speed oscillator (LSI) */
+ __HAL_RCC_LSI_DISABLE();
+
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSI is disabled */
+ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSIRDY) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Restore clock configuration if changed */
+ if (pwrclkchanged == SET)
+ {
+ __HAL_RCC_PWR_CLK_DISABLE();
+ }
+ }
+ /*------------------------------ LSE Configuration -------------------------*/
+ if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+ {
+ FlagStatus pwrclkchanged = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_LSE(pRCC_OscInitStruct->LSEState));
+
+ /* Update LSE configuration in Backup Domain control register */
+ /* Requires to enable write access to Backup Domain of necessary */
+ if (__HAL_RCC_PWR_IS_CLK_DISABLED())
+ {
+ __HAL_RCC_PWR_CLK_ENABLE();
+ pwrclkchanged = SET;
+ }
+
+ if (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP))
+ {
+ /* Enable write access to Backup domain */
+ SET_BIT(PWR->DBPR, PWR_DBPR_DBP);
+
+ /* Wait for Backup domain Write protection disable */
+ tickstart = HAL_GetTick();
+
+ while (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP))
+ {
+ if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Set the new LSE configuration -----------------------------------------*/
+ if ((pRCC_OscInitStruct->LSEState & RCC_BDCR_LSEON) != 0U)
+ {
+ if ((pRCC_OscInitStruct->LSEState & RCC_BDCR_LSEBYP) != 0U)
+ {
+ /* LSE oscillator bypass enable */
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+ }
+ else
+ {
+ /* LSE oscillator enable */
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+ }
+ }
+ else
+ {
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
+ }
+
+ /* Check the LSE State */
+ if (pRCC_OscInitStruct->LSEState != RCC_LSE_OFF)
+ {
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Enable LSESYS additionally if requested */
+ if ((pRCC_OscInitStruct->LSEState & RCC_BDCR_LSESYSEN) != 0U)
+ {
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN);
+
+ /* Wait till LSESYS is ready */
+ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Make sure LSESYSEN/LSESYSRDY are reset */
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN);
+
+ /* Wait till LSESYSRDY is cleared */
+ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is disabled */
+ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ if (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN) != 0U)
+ {
+ /* Reset LSESYSEN once LSE is disabled */
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN);
+
+ /* Wait till LSESYSRDY is cleared */
+ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Restore clock configuration if changed */
+ if (pwrclkchanged == SET)
+ {
+ __HAL_RCC_PWR_CLK_DISABLE();
+ }
+ }
+ /*------------------------------ HSI48 Configuration -----------------------*/
+ if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSI48(pRCC_OscInitStruct->HSI48State));
+
+ /* Check the HSI48 State */
+ if (pRCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
+ {
+ /* Enable the Internal High Speed oscillator (HSI48) */
+ __HAL_RCC_HSI48_ENABLE();
+
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI48 is ready */
+ while (READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Disable the Internal High Speed oscillator (HSI48) */
+ __HAL_RCC_HSI48_DISABLE();
+
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI48 is disabled */
+ while (READ_BIT(RCC->CR, RCC_CR_HSI48RDY) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /*------------------------------ SHSI Configuration -----------------------*/
+ if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_SHSI) == RCC_OSCILLATORTYPE_SHSI)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SHSI(pRCC_OscInitStruct->SHSIState));
+
+ /* Check the SHSI State */
+ if (pRCC_OscInitStruct->SHSIState != RCC_SHSI_OFF)
+ {
+ /* Enable the Secure Internal High Speed oscillator (SHSI) */
+ __HAL_RCC_SHSI_ENABLE();
+
+ tickstart = HAL_GetTick();
+
+ /* Wait till SHSI is ready */
+ while (READ_BIT(RCC->CR, RCC_CR_SHSIRDY) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > SHSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Disable the Secure Internal High Speed oscillator (SHSI) */
+ __HAL_RCC_SHSI_DISABLE();
+
+ tickstart = HAL_GetTick();
+
+ /* Wait till SHSI is disabled */
+ while (READ_BIT(RCC->CR, RCC_CR_SHSIRDY) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > SHSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ /*------------------------------ MSIK Configuration -----------------------*/
+ if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSIK) == RCC_OSCILLATORTYPE_MSIK)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_MSIK(pRCC_OscInitStruct->MSIKState));
+ assert_param(IS_RCC_MSIK_CLOCK_RANGE(pRCC_OscInitStruct->MSIKClockRange));
+ assert_param(IS_RCC_MSICALIBRATION_VALUE(pRCC_OscInitStruct->MSICalibrationValue));
+
+ /* Check the MSIK State */
+ if (pRCC_OscInitStruct->MSIKState != RCC_MSIK_OFF)
+ {
+
+ /* Selects the Multiple Speed of kernel high speed oscillator (MSIK) clock range .*/
+ __HAL_RCC_MSIK_RANGE_CONFIG(pRCC_OscInitStruct->MSIKClockRange);
+ /* Adjusts the Multiple Speed of kernel high speed oscillator (MSIK) calibration value.*/
+ __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST((pRCC_OscInitStruct->MSICalibrationValue), \
+ (pRCC_OscInitStruct->MSIClockRange));
+
+ /* Enable the Internal kernel High Speed oscillator (MSIK) */
+ __HAL_RCC_MSIK_ENABLE();
+
+ tickstart = HAL_GetTick();
+
+ /* Wait till MSIK is ready */
+ while (READ_BIT(RCC->CR, RCC_CR_MSIKRDY) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > MSIK_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Disable the Internal High Speed Kernel oscillator (MSIK) */
+ __HAL_RCC_MSIK_DISABLE();
+
+ tickstart = HAL_GetTick();
+
+ /* Wait till MSIK is disabled */
+ while (READ_BIT(RCC->CR, RCC_CR_MSIKRDY) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > MSIK_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ /*-------------------------------- PLL Configuration -----------------------*/
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL(pRCC_OscInitStruct->PLL.PLLState));
+
+ if ((pRCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
+ {
+ /* Check if the PLL is used as system clock or not */
+ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+ {
+ if ((pRCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_PLLMBOOST_VALUE(pRCC_OscInitStruct->PLL.PLLMBOOST));
+ assert_param(IS_RCC_PLLSOURCE(pRCC_OscInitStruct->PLL.PLLSource));
+ assert_param(IS_RCC_PLLM_VALUE(pRCC_OscInitStruct->PLL.PLLM));
+ assert_param(IS_RCC_PLLN_VALUE(pRCC_OscInitStruct->PLL.PLLN));
+ assert_param(IS_RCC_PLLP_VALUE(pRCC_OscInitStruct->PLL.PLLP));
+ assert_param(IS_RCC_PLLQ_VALUE(pRCC_OscInitStruct->PLL.PLLQ));
+ assert_param(IS_RCC_PLLR_VALUE(pRCC_OscInitStruct->PLL.PLLR));
+
+ /* Disable the main PLL */
+ __HAL_RCC_PLL_DISABLE();
+
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Enable PWR CLK */
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /*Disable EPOD to configure PLL1MBOOST*/
+ if (READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN) == PWR_VOSR_BOOSTEN)
+ {
+ pwrboosten = SET;
+ }
+ CLEAR_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN);
+
+ /* Configure the main PLL clock source, multiplication and division factors */
+ __HAL_RCC_PLL_CONFIG(pRCC_OscInitStruct->PLL.PLLSource,
+ pRCC_OscInitStruct->PLL.PLLMBOOST,
+ pRCC_OscInitStruct->PLL.PLLM,
+ pRCC_OscInitStruct->PLL.PLLN,
+ pRCC_OscInitStruct->PLL.PLLP,
+ pRCC_OscInitStruct->PLL.PLLQ,
+ pRCC_OscInitStruct->PLL.PLLR);
+
+ assert_param(IS_RCC_PLLFRACN_VALUE(pRCC_OscInitStruct->PLL.PLLFRACN));
+
+ /* Disable PLL1FRACN */
+ __HAL_RCC_PLLFRACN_DISABLE();
+
+ /* Configure PLL PLL1FRACN */
+ __HAL_RCC_PLLFRACN_CONFIG(pRCC_OscInitStruct->PLL.PLLFRACN);
+
+ /* Enable PLL1FRACN */
+ __HAL_RCC_PLLFRACN_ENABLE();
+
+ assert_param(IS_RCC_PLLRGE_VALUE(pRCC_OscInitStruct->PLL.PLLRGE));
+
+ /* Select PLL1 input reference frequency range: VCI */
+ __HAL_RCC_PLL_VCIRANGE(pRCC_OscInitStruct->PLL.PLLRGE);
+
+ if (pwrboosten == SET)
+ {
+ /* Enable the EPOD to reach max frequency */
+ SET_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN);
+ }
+
+ /*Disable PWR clk */
+ __HAL_RCC_PWR_CLK_DISABLE();
+
+ /* Enable PLL System Clock output */
+ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR);
+
+ /* Enable the main PLL */
+ __HAL_RCC_PLL_ENABLE();
+
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Disable the main PLL */
+ __HAL_RCC_PLL_DISABLE();
+
+ /* Disable main PLL outputs to save power if no PLLs on */
+ __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL1_DIVP | RCC_PLL1_DIVQ | RCC_PLL1_DIVR);
+
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is disabled */
+ while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the CPU, AHB and APB busses clocks according to the specified
+ * parameters in the pRCC_ClkInitStruct.
+ * @param pRCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
+ * contains the configuration information for the RCC peripheral.
+ * @param FLatency FLASH Latency
+ * This parameter can be one of the following values:
+ * @arg FLASH_LATENCY_0 FLASH 0 Latency cycle
+ * @arg FLASH_LATENCY_1 FLASH 1 Latency cycle
+ * @arg FLASH_LATENCY_2 FLASH 2 Latency cycles
+ * @arg FLASH_LATENCY_3 FLASH 3 Latency cycles
+ * @arg FLASH_LATENCY_4 FLASH 4 Latency cycles
+ * @arg FLASH_LATENCY_5 FLASH 5 Latency cycles
+ *
+ * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
+ * and updated by HAL_RCC_GetHCLKFreq() function called within this function
+ *
+ * @note The MSI is used by default as system clock source after
+ * startup from Reset, wake-up from STANDBY mode. After restart from Reset,
+ * the MSI frequency is set to its default value 4 MHz.
+ * @note The HSI can be selected as system clock source after wakeup
+ * from STOP modes or in case of failure of the HSE used directly or indirectly
+ * as system clock (if the Clock Security System CSS is enabled).
+ * @note A switch from one clock source to another occurs only if the target
+ * clock source is ready (clock stable after startup delay or PLL locked).
+ * If a clock source which is not yet ready is selected, the switch will
+ * occur when the clock source is ready.
+ * @note You can use HAL_RCC_GetClockConfig() function to know which clock is
+ * currently used as system clock source.
+ *
+ * @note Depending on the device voltage range, the software has to set correctly
+ * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
+ * (for more details refer to section above "Initialization/de-initialization functions")
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *const pRCC_ClkInitStruct, uint32_t FLatency)
+{
+ HAL_StatusTypeDef status;
+ uint32_t tickstart;
+
+ /* Check Null pointer */
+ if (pRCC_ClkInitStruct == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_RCC_CLOCKTYPE(pRCC_ClkInitStruct->ClockType));
+ assert_param(IS_FLASH_LATENCY(FLatency));
+
+ /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
+ must be correctly programmed according to the frequency of the CPU clock
+ (HCLK) and the supply voltage of the device */
+
+ /* Increasing the number of wait states because of higher CPU frequency */
+ if (FLatency > __HAL_FLASH_GET_LATENCY())
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ __HAL_FLASH_SET_LATENCY(FLatency);
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ if (__HAL_FLASH_GET_LATENCY() != FLatency)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /*------------------------- SYSCLK Configuration ---------------------------*/
+ if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+ {
+ assert_param(IS_RCC_SYSCLKSOURCE(pRCC_ClkInitStruct->SYSCLKSource));
+
+ /* PLL is selected as System Clock Source */
+ if (pRCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ {
+ __HAL_RCC_PWR_CLK_ENABLE();
+ tickstart = HAL_GetTick();
+ /* Check if EPOD is enabled */
+ if (READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN) != 0U)
+ {
+ /* Wait till BOOST is ready */
+ while (READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTRDY) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > EPOD_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ __HAL_RCC_PWR_CLK_DISABLE();
+
+ /* Check the PLL ready flag */
+ if (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == 0U)
+ {
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* HSE is selected as System Clock Source */
+ if (pRCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ {
+ /* Check the HSE ready flag */
+ if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
+ {
+ return HAL_ERROR;
+ }
+ }
+ /* MSI is selected as System Clock Source */
+ else if (pRCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
+ {
+ /* Check the MSI ready flag */
+ if (READ_BIT(RCC->CR, RCC_CR_MSISRDY) == 0U)
+ {
+ return HAL_ERROR;
+ }
+ }
+ /* HSI is selected as System Clock Source */
+ else
+ {
+ /* Check the HSI ready flag */
+ if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
+ {
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SW, pRCC_ClkInitStruct->SYSCLKSource);
+
+ tickstart = HAL_GetTick();
+
+ if (pRCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+ {
+ if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ if (pRCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
+ {
+ if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else if (pRCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI)
+ {
+ if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
+ {
+ if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+
+ /*-------------------------- HCLK Configuration --------------------------*/
+ if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+ {
+ assert_param(IS_RCC_HCLK(pRCC_ClkInitStruct->AHBCLKDivider));
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, pRCC_ClkInitStruct->AHBCLKDivider);
+ }
+
+ /*-------------------------- PCLK1 Configuration ---------------------------*/
+ if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ {
+ assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB1CLKDivider));
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, pRCC_ClkInitStruct->APB1CLKDivider);
+ }
+
+ /*-------------------------- PCLK2 Configuration ---------------------------*/
+ if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+ {
+ assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB2CLKDivider));
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, ((pRCC_ClkInitStruct->APB2CLKDivider) << 4));
+ }
+
+ /*-------------------------- PCLK3 Configuration ---------------------------*/
+ if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK3) == RCC_CLOCKTYPE_PCLK3)
+ {
+ assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB3CLKDivider));
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_PPRE3, pRCC_ClkInitStruct->APB3CLKDivider);
+ }
+
+ /* Decreasing the number of wait states because of lower CPU frequency */
+ if (FLatency < __HAL_FLASH_GET_LATENCY())
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ __HAL_FLASH_SET_LATENCY(FLatency);
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ if (__HAL_FLASH_GET_LATENCY() != FLatency)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Update the SystemCoreClock global variable */
+ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos];
+
+ /* Configure the source of time base considering new system clocks settings*/
+ status = HAL_InitTick(uwTickPrio);
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
+ * @brief RCC clocks control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to:
+
+ (+) Output clock to MCO pin.
+ (+) Retrieve current clock frequencies.
+ (+) Enable the Clock Security System.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Select the clock source to output on MCO pin(PA8).
+ * @note PA8 should be configured in alternate function mode.
+ * @param RCC_MCOx specifies the output direction for the clock source.
+ * For STM32U5xx family this parameter can have only one value:
+ * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
+ * @param RCC_MCOSource specifies the clock source to output.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled, no clock on MCO
+ * @arg @ref RCC_MCO1SOURCE_SYSCLK system clock selected as MCO source
+ * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source
+ * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
+ * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee
+ * @arg @ref RCC_MCO1SOURCE_PLL1CLK main PLL clock selected as MCO source
+ * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
+ * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
+ * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48
+ * @param RCC_MCODiv specifies the MCO prescaler.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MCODIV_1 no division applied to MCO clock
+ * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock
+ * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock
+ * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock
+ * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock
+ * @retval None
+ */
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
+{
+ GPIO_InitTypeDef gpio_initstruct;
+ /* Check the parameters */
+ assert_param(IS_RCC_MCO(RCC_MCOx));
+ assert_param(IS_RCC_MCODIV(RCC_MCODiv));
+ assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
+
+ /* MCO Clock Enable */
+ MCO1_CLK_ENABLE();
+
+ /* Configure the MCO1 pin in alternate function mode */
+ gpio_initstruct.Pin = MCO1_PIN;
+ gpio_initstruct.Mode = GPIO_MODE_AF_PP;
+ gpio_initstruct.Speed = GPIO_SPEED_FREQ_HIGH;
+ gpio_initstruct.Pull = GPIO_NOPULL;
+ gpio_initstruct.Alternate = GPIO_AF0_MCO;
+ HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio_initstruct);
+
+ /* Mask MCOSEL[] and MCOPRE[] bits then set MCO1 clock source and prescaler */
+ MODIFY_REG(RCC->CFGR1, (RCC_CFGR1_MCOSEL | RCC_CFGR1_MCOPRE), (RCC_MCOSource | RCC_MCODiv));
+}
+
+/**
+ * @brief Return the SYSCLK frequency.
+ * @note The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ * @note If SYSCLK source is MSI, function returns values based on MSI
+ * Value as defined by the MSI range.
+ * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
+ * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
+ * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**),
+ * HSI_VALUE(*) or MSI Value multiplied/divided by the PLL factors.
+ * @note (*) HSI_VALUE is a constant defined in stm32u5xx_hal_conf.h file (default value
+ * 16 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ * @note (**) HSE_VALUE is a constant defined in stm32u5xx_hal_conf.h file (default value
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ * @note The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ * @note This function can be used by the user application to compute the
+ * baudrate for the communication peripherals or configure other parameters.
+ * @note Each time SYSCLK changes, this function must be called to update the
+ * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
+ * @retval SYSCLK frequency
+ */
+uint32_t HAL_RCC_GetSysClockFreq(void)
+{
+ uint32_t msirange = 0U;
+ uint32_t pllsource;
+ uint32_t pllr;
+ uint32_t pllm;
+ uint32_t pllfracen;
+ uint32_t sysclockfreq = 0U;
+ uint32_t sysclk_source;
+ uint32_t pll_oscsource;
+ float_t fracn1;
+ float_t pllvco;
+
+ sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
+ pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE();
+
+ if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) ||
+ ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_oscsource == RCC_PLLSOURCE_MSI)))
+ {
+ /* MSI or PLL with MSI source used as system clock source */
+
+ /* Get SYSCLK source */
+ if (READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL) == 0U)
+ {
+ /* MSISRANGE from RCC_CSR applies */
+ msirange = (RCC->CSR & RCC_CSR_MSISSRANGE) >> RCC_CSR_MSISSRANGE_Pos;
+ }
+ else
+ {
+ /* MSIRANGE from RCC_CR applies */
+ msirange = (RCC->ICSCR1 & RCC_ICSCR1_MSISRANGE) >> RCC_ICSCR1_MSISRANGE_Pos;
+ }
+ /*MSI frequency range in HZ*/
+ msirange = MSIRangeTable[msirange];
+
+ if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI)
+ {
+ /* MSI used as system clock source */
+ sysclockfreq = msirange;
+ }
+ }
+ else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
+ {
+ /* HSI used as system clock source */
+ sysclockfreq = HSI_VALUE;
+ }
+ else if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE)
+ {
+ /* HSE used as system clock source */
+ sysclockfreq = HSE_VALUE;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+ {
+ /* PLL used as system clock source
+ PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+ SYSCLK = PLL_VCO / PLLR
+ */
+ pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC);
+ pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U;
+ pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN) >> RCC_PLL1CFGR_PLL1FRACEN_Pos);
+ fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN) >> \
+ RCC_PLL1FRACR_PLL1FRACN_Pos));
+
+ if (pllm != 0U)
+ {
+ switch (pllsource)
+ {
+ case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
+ pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
+ (fracn1 / (float_t)0x2000) + (float_t)1U);
+ break;
+
+ case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
+ pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
+ (fracn1 / (float_t)0x2000) + (float_t)1U);
+ break;
+
+ case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
+ default:
+ pllvco = ((float_t) msirange / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
+ (fracn1 / (float_t)0x2000) + (float_t)1U);
+ break;
+ }
+
+ pllr = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U);
+ sysclockfreq = (uint32_t)(float_t)((float_t)pllvco / (float_t)pllr);
+ }
+ else
+ {
+ sysclockfreq = 0;
+ }
+ }
+
+ return sysclockfreq;
+}
+
+/**
+ * @brief Return the HCLK frequency.
+ * @note Each time HCLK changes, this function must be called to update the
+ * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
+ *
+ * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
+ * @retval HCLK frequency in Hz
+ */
+uint32_t HAL_RCC_GetHCLKFreq(void)
+{
+ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos];
+ return SystemCoreClock;
+}
+
+/**
+ * @brief Return the PCLK1 frequency.
+ * @note Each time PCLK1 changes, this function must be called to update the
+ * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
+ * @retval PCLK1 frequency in Hz
+ */
+uint32_t HAL_RCC_GetPCLK1Freq(void)
+{
+ /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
+ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR2 & RCC_CFGR2_PPRE1) >> RCC_CFGR2_PPRE1_Pos]);
+}
+
+/**
+ * @brief Return the PCLK2 frequency.
+ * @note Each time PCLK2 changes, this function must be called to update the
+ * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
+ * @retval PCLK2 frequency in Hz
+ */
+uint32_t HAL_RCC_GetPCLK2Freq(void)
+{
+ /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
+ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR2 & RCC_CFGR2_PPRE2) >> RCC_CFGR2_PPRE2_Pos]);
+}
+
+/**
+ * @brief Return the PCLK3 frequency.
+ * @note Each time PCLK3 changes, this function must be called to update the
+ * right PCLK3 value. Otherwise, any configuration based on this function will be incorrect.
+ * @retval PCLK3 frequency in Hz
+ */
+uint32_t HAL_RCC_GetPCLK3Freq(void)
+{
+ /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
+ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR3 & RCC_CFGR3_PPRE3) >> RCC_CFGR3_PPRE3_Pos]);
+}
+/**
+ * @brief Get the pRCC_OscInitStruct according to the internal
+ * RCC configuration registers.
+ * @param pRCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
+ * will be configured.
+ * @retval None
+ */
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct)
+{
+ /* Check the parameters */
+ assert_param(pRCC_OscInitStruct != (void *)NULL);
+
+ /* Set all possible values for the Oscillator type parameter ---------------*/
+ pRCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \
+ RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI48;
+
+ /* Get the HSE configuration -----------------------------------------------*/
+ if ((RCC->CR & (RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == RCC_CR_HSEBYP)
+ {
+ pRCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
+ }
+ else if ((RCC->CR & (RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == (RCC_CR_HSEBYP | RCC_CR_HSEEXT))
+ {
+ pRCC_OscInitStruct->HSEState = RCC_HSE_BYPASS_DIGITAL;
+ }
+ else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
+ {
+ pRCC_OscInitStruct->HSEState = RCC_HSE_ON;
+ }
+ else
+ {
+ pRCC_OscInitStruct->HSEState = RCC_HSE_OFF;
+ }
+
+ /* Get the MSI configuration -----------------------------------------------*/
+ if ((RCC->CR & RCC_CR_MSISON) == RCC_CR_MSISON)
+ {
+ pRCC_OscInitStruct->MSIState = RCC_MSI_ON;
+ }
+ else
+ {
+ pRCC_OscInitStruct->MSIState = RCC_MSI_OFF;
+ }
+
+ pRCC_OscInitStruct->MSIClockRange = (uint32_t)((RCC->CR & RCC_ICSCR1_MSISRANGE));
+ if (pRCC_OscInitStruct->MSIClockRange >= RCC_MSIRANGE_12)
+ {
+ pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->ICSCR2 & RCC_ICSCR2_MSITRIM3) >> \
+ RCC_ICSCR2_MSITRIM3_Pos);
+ }
+ else if (pRCC_OscInitStruct->MSIClockRange >= RCC_MSIRANGE_8)
+ {
+ pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->ICSCR2 & RCC_ICSCR2_MSITRIM2) >> \
+ RCC_ICSCR2_MSITRIM2_Pos);
+ }
+ else if (pRCC_OscInitStruct->MSIClockRange >= RCC_MSIRANGE_4)
+ {
+ pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->ICSCR2 & RCC_ICSCR2_MSITRIM1) >> \
+ RCC_ICSCR2_MSITRIM1_Pos);
+ }
+ else /*if (pRCC_OscInitStruct->MSIClockRange >= RCC_MSIRANGE_0)*/
+ {
+ pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->ICSCR2 & RCC_ICSCR2_MSITRIM0) >> \
+ RCC_ICSCR2_MSITRIM0_Pos);
+ }
+
+ /* Get the HSI configuration -----------------------------------------------*/
+ if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION)
+ {
+ pRCC_OscInitStruct->HSIState = RCC_HSI_ON;
+ }
+ else
+ {
+ pRCC_OscInitStruct->HSIState = RCC_HSI_OFF;
+ }
+
+ pRCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->ICSCR3 & RCC_ICSCR3_HSITRIM) >> RCC_ICSCR3_HSITRIM_Pos);
+
+ /* Get the LSE configuration -----------------------------------------------*/
+ if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
+ {
+ pRCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
+ }
+ else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
+ {
+ pRCC_OscInitStruct->LSEState = RCC_LSE_ON;
+ }
+ else
+ {
+ pRCC_OscInitStruct->LSEState = RCC_LSE_OFF;
+ }
+
+ /* Get the LSI configuration -----------------------------------------------*/
+ if ((RCC->BDCR & RCC_BDCR_LSION) == RCC_BDCR_LSION)
+ {
+ pRCC_OscInitStruct->LSIState = RCC_LSI_ON;
+ }
+ else
+ {
+ pRCC_OscInitStruct->LSIState = RCC_LSI_OFF;
+ }
+
+ /* Get the HSI48 configuration ---------------------------------------------*/
+ if ((RCC->CR & RCC_CR_HSI48ON) == RCC_CR_HSI48ON)
+ {
+ pRCC_OscInitStruct->HSI48State = RCC_HSI48_ON;
+ }
+ else
+ {
+ pRCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;
+ }
+
+ /* Get the PLL configuration -----------------------------------------------*/
+ if ((RCC->CR & RCC_CR_PLL1ON) == RCC_CR_PLL1ON)
+ {
+ pRCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
+ }
+ else
+ {
+ pRCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
+ }
+ pRCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC);
+ pRCC_OscInitStruct->PLL.PLLM = (uint32_t)(((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U);
+ pRCC_OscInitStruct->PLL.PLLN = (uint32_t)(((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) >> RCC_PLL1DIVR_PLL1N_Pos) + 1U);
+ pRCC_OscInitStruct->PLL.PLLQ = (uint32_t)(((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1Q) >> RCC_PLL1DIVR_PLL1Q_Pos) + 1U);
+ pRCC_OscInitStruct->PLL.PLLR = (uint32_t)(((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U);
+ pRCC_OscInitStruct->PLL.PLLP = (uint32_t)(((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + 1U);
+ pRCC_OscInitStruct->PLL.PLLRGE = (uint32_t)((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1RGE));
+ pRCC_OscInitStruct->PLL.PLLFRACN = (uint32_t)(((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN) >> \
+ RCC_PLL1FRACR_PLL1FRACN_Pos));
+ pRCC_OscInitStruct->PLL.PLLMBOOST = (uint32_t)(((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1MBOOST) >> \
+ RCC_PLL1CFGR_PLL1MBOOST_Pos) + 1U);
+}
+
+/**
+ * @brief Configure the pRCC_ClkInitStruct according to the internal
+ * RCC configuration registers.
+ * @param pRCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
+ * will be configured.
+ * @param pFLatency Pointer on the Flash Latency.
+ * @retval None
+ */
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *pRCC_ClkInitStruct, uint32_t *pFLatency)
+{
+ /* Check the parameters */
+ assert_param(pRCC_ClkInitStruct != (void *)NULL);
+ assert_param(pFLatency != (void *)NULL);
+
+ /* Set all possible values for the Clock type parameter --------------------*/
+ pRCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | \
+ RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3;
+
+ /* Get the SYSCLK configuration --------------------------------------------*/
+ pRCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR1 & RCC_CFGR1_SW);
+
+ /* Get the HCLK configuration ----------------------------------------------*/
+ pRCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_HPRE);
+
+ /* Get the APB1 configuration ----------------------------------------------*/
+ pRCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PPRE1);
+
+ /* Get the APB2 configuration ----------------------------------------------*/
+ pRCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR2 & RCC_CFGR2_PPRE2) >> 4);
+
+ /* Get the APB3 configuration ----------------------------------------------*/
+ pRCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->CFGR3 & RCC_CFGR3_PPRE3);
+
+ /* Get the Flash Wait State (Latency) configuration ------------------------*/
+ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
+}
+
+/**
+ * @brief Get and clear reset flags
+ * @note Once reset flags are retrieved, this API is clearing them in order
+ * to isolate next reset reason.
+ * @retval can be a combination of @ref RCC_Reset_Flag
+ */
+uint32_t HAL_RCC_GetResetSource(void)
+{
+ uint32_t reset;
+
+ /* Get all reset flags */
+ reset = RCC->CSR & RCC_RESET_FLAG_ALL;
+
+ /* Clear Reset flags */
+ RCC->CSR |= RCC_CSR_RMVF;
+
+ return reset;
+}
+
+/**
+ * @brief Enable the Clock Security System.
+ * @note If a failure is detected on the HSE oscillator clock, this oscillator
+ * is automatically disabled and an interrupt is generated to inform the
+ * software about the failure (Clock Security System Interrupt, CSSI),
+ * allowing the MCU to perform rescue operations. The CSSI is linked to
+ * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
+ * @note The Clock Security System can only be cleared by reset.
+ * @retval None
+ */
+void HAL_RCC_EnableCSS(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_CSSON);
+}
+
+/**
+ * @brief Handle the RCC Clock Security System interrupt request.
+ * @note This API should be called under the NMI_Handler().
+ * @retval None
+ */
+void HAL_RCC_NMI_IRQHandler(void)
+{
+ /* Check RCC CSSF interrupt flag */
+ if (__HAL_RCC_GET_IT(RCC_IT_CSS))
+ {
+ /* RCC Clock Security System interrupt user callback */
+ HAL_RCC_CSSCallback();
+
+ /* Clear RCC CSS pending bit */
+ __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
+ }
+}
+
+/**
+ * @brief RCC Clock Security System interrupt callback.
+ * @retval none
+ */
+__weak void HAL_RCC_CSSCallback(void)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RCC_CSSCallback should be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+/** @defgroup RCC_Exported_Functions_Group3 Attributes management functions
+ * @brief Attributes management functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### RCC attributes functions #####
+ ===============================================================================
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Configure the RCC item attribute(s).
+ * @note Available attributes are to secure items and set RCC as privileged.
+ * @param Item Item(s) to set attributes on.
+ * This parameter can be a one or a combination of @ref RCC_items
+ * @param Attributes specifies the RCC secure/privilege attributes.
+ * This parameter can be a value of @ref RCC_attributes
+ * @retval None
+ */
+void HAL_RCC_ConfigAttributes(uint32_t Item, uint32_t Attributes)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_ITEM_ATTRIBUTES(Item));
+ assert_param(IS_RCC_ATTRIBUTES(Attributes));
+
+ switch (Attributes)
+ {
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ /* Secure Privilege attribute */
+ case RCC_SEC_PRIV:
+ SET_BIT(RCC->SECCFGR, Item);
+ SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV);
+ break;
+ /* Secure Non-Privilege attribute */
+ case RCC_SEC_NPRIV:
+ SET_BIT(RCC->SECCFGR, Item);
+ CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV);
+ break;
+ /* Non-secure Privilege attribute */
+ case RCC_NSEC_PRIV:
+ CLEAR_BIT(RCC->SECCFGR, Item);
+ SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV);
+ break;
+ /* Non-secure Non-Privilege attribute */
+ case RCC_NSEC_NPRIV:
+ CLEAR_BIT(RCC->SECCFGR, Item);
+ CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV);
+ break;
+#else
+ /* Non-secure Privilege attribute */
+ case RCC_NSEC_PRIV:
+ SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV);
+ break;
+ /* Non-secure Non-Privilege attribute */
+ case RCC_NSEC_NPRIV:
+ CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV);
+ break;
+#endif /* __ARM_FEATURE_CMSE */
+ default:
+ /* Nothing to do */
+ break;
+ }
+}
+/**
+ * @}
+ */
+
+/**
+ * @brief Get the attribute of a RCC item.
+ * @note Secure and non-secure attributes are only available from secure state
+ * when the system implements the security (TZEN=1)
+ * @param Item Single item to get secure/non-secure and privilege/non-privilege attribute from.
+ * This parameter can be a one value of @ref RCC_items except RCC_ALL.
+ * @param pAttributes pointer to return the attributes.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_RCC_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes)
+{
+ uint32_t attributes;
+
+ /* Check null pointer */
+ if (pAttributes == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_RCC_ITEM_ATTRIBUTES(Item));
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+ /* Check item security */
+ if ((RCC->SECCFGR & Item) == Item)
+ {
+ /* Get Secure privileges attribute */
+ attributes = ((RCC->PRIVCFGR & RCC_PRIVCFGR_SPRIV) == 0U) ? RCC_SEC_NPRIV : RCC_SEC_PRIV;
+ }
+ else
+ {
+ /* Get Non-Secure privileges attribute */
+ attributes = ((RCC->PRIVCFGR & RCC_PRIVCFGR_NSPRIV) == 0U) ? RCC_NSEC_NPRIV : RCC_NSEC_PRIV;
+ }
+#else
+ /* Get Non-Secure privileges attribute */
+ attributes = ((RCC->PRIVCFGR & RCC_PRIVCFGR_NSPRIV) == 0U) ? RCC_NSEC_NPRIV : RCC_NSEC_PRIV;
+#endif /* __ARM_FEATURE_CMSE */
+
+ /* return value */
+ *pAttributes = attributes;
+
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup RCC_Private_Functions
+ * @{
+ */
+/**
+ * @brief Update number of Flash wait states in line with MSI range and current
+ voltage range.
+ * @param msirange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_15
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange)
+{
+ uint32_t vos;
+ uint32_t latency; /* default value 0WS */
+
+ if (__HAL_RCC_PWR_IS_CLK_ENABLED())
+ {
+ vos = HAL_PWREx_GetVoltageRange();
+ }
+ else
+ {
+ __HAL_RCC_PWR_CLK_ENABLE();
+ vos = HAL_PWREx_GetVoltageRange();
+ __HAL_RCC_PWR_CLK_DISABLE();
+ }
+
+ if ((vos == PWR_REGULATOR_VOLTAGE_SCALE1) || (vos == PWR_REGULATOR_VOLTAGE_SCALE2))
+ {
+
+ if (msirange < RCC_MSIRANGE_1)
+ {
+ /* MSI = 48Mhz */
+ latency = FLASH_LATENCY_1; /* 1WS */
+ }
+ else
+ {
+ /* MSI < 48Mhz */
+ latency = FLASH_LATENCY_0; /* 0WS */
+ }
+ }
+ else
+ {
+ if (msirange < RCC_MSIRANGE_1)
+ {
+ /* MSI = 48Mhz */
+ if (vos == PWR_REGULATOR_VOLTAGE_SCALE3)
+ {
+ latency = FLASH_LATENCY_3; /* 3WS */
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ if (msirange > RCC_MSIRANGE_2)
+
+ {
+ if (vos == PWR_REGULATOR_VOLTAGE_SCALE4)
+ {
+ if (msirange > RCC_MSIRANGE_3)
+ {
+ latency = FLASH_LATENCY_0; /* 1WS */
+ }
+ else
+ {
+ latency = FLASH_LATENCY_1; /* 0WS */
+ }
+ }
+ else
+ {
+ latency = FLASH_LATENCY_0; /* 0WS */
+ }
+ }
+ else
+ {
+ if (msirange == RCC_MSIRANGE_1)
+
+ {
+ if (vos == PWR_REGULATOR_VOLTAGE_SCALE3)
+ {
+ latency = FLASH_LATENCY_1; /* 1WS */
+ }
+ else
+ {
+ latency = FLASH_LATENCY_2; /* 2WS */
+ }
+ }
+ else
+ {
+ latency = FLASH_LATENCY_1; /* 1WS */
+ }
+ }
+ }
+ }
+
+ __HAL_FLASH_SET_LATENCY(latency);
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ if ((FLASH->ACR & FLASH_ACR_LATENCY) != latency)
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+#endif /* HAL_RCC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc_ex.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc_ex.c
new file mode 100644
index 00000000..2b9be9d9
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc_ex.c
@@ -0,0 +1,3531 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_rcc_ex.c
+ * @author MCD Application Team
+ * @brief Extended RCC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities RCC extended peripheral:
+ * + Extended Peripheral Control functions
+ * + Extended Clock management functions
+ * + Extended Clock Recovery System Control functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup RCCEx RCCEx
+ * @brief RCC Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
+ * @{
+ */
+#define PLL1_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */
+#define PLL2_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */
+#define PLL3_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */
+
+#define LSCO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
+
+#define LSCO_GPIO_PORT GPIOA
+
+#define LSCO_PIN GPIO_PIN_2
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCCEx_Private_Macros
+ * @{
+ */
+
+#define IS_RCC_PLL2CLOCKOUT_VALUE(VALUE) ((0x00010000U <= (VALUE)) && ((VALUE) <= 0x00070000U))
+
+#define IS_RCC_PLL3CLOCKOUT_VALUE(VALUE) ((0x00010000U <= (VALUE)) && ((VALUE) <= 0x00070000U))
+
+#define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \
+ ((__SOURCE__) == RCC_LSCOSOURCE_LSE))
+
+#define IS_RCC_MSIPLLMODE_SELECT(__SOURCE__) (((__SOURCE__) == RCC_MSISPLL_MODE_SEL) || \
+ ((__SOURCE__) == RCC_MSIKPLL_MODE_SEL))
+
+#define IS_RCC_PERIPHCLOCK(__SELECTION__) ((((__SELECTION__) & RCC_PERIPHCLOCK_ALL) != 0x00u) && \
+ (((__SELECTION__) & ~RCC_PERIPHCLOCK_ALL) == 0x00u))
+
+#define IS_RCC_USART1CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \
+ ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI) || \
+ ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE))
+
+#define IS_RCC_USART2CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI) || \
+ ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE))
+
+#define IS_RCC_USART3CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI) || \
+ ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE))
+
+#define IS_RCC_UART4CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI) || \
+ ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE))
+
+#define IS_RCC_UART5CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI) || \
+ ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE))
+
+#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK3) || \
+ ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI) || \
+ ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \
+ ((__SOURCE__) == RCC_LPUART1CLKSOURCE_MSIK))
+
+#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
+ ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)|| \
+ ((__SOURCE__) == RCC_I2C1CLKSOURCE_MSIK))
+
+#define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \
+ ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI)|| \
+ ((__SOURCE__) == RCC_I2C2CLKSOURCE_MSIK))
+
+#define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK3) || \
+ ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK ) || \
+ ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI ) || \
+ ((__SOURCE__) == RCC_I2C3CLKSOURCE_MSIK))
+
+#define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK)|| \
+ ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI)|| \
+ ((__SOURCE__) == RCC_I2C4CLKSOURCE_MSIK))
+
+#define IS_RCC_SAI1CLK(__SOURCE__) \
+ (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2) || \
+ ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3) || \
+ ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL1) || \
+ ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN) || \
+ ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI))
+
+#define IS_RCC_SAI2CLK(__SOURCE__) \
+ (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL2) || \
+ ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3) || \
+ ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL1) || \
+ ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN) || \
+ ((__SOURCE__) == RCC_SAI2CLKSOURCE_HSI))
+
+#define IS_RCC_LPTIM1CLK(__SOURCE__) \
+ (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_MSIK) || \
+ ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \
+ ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \
+ ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE))
+
+#define IS_RCC_LPTIM2CLK(__SOURCE__) \
+ (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \
+ ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \
+ ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE))
+
+#define IS_RCC_LPTIM34CLK(__SOURCE__) \
+ (((__SOURCE__) == RCC_LPTIM34CLKSOURCE_MSIK) || \
+ ((__SOURCE__) == RCC_LPTIM34CLKSOURCE_LSI) || \
+ ((__SOURCE__) == RCC_LPTIM34CLKSOURCE_HSI) || \
+ ((__SOURCE__) == RCC_LPTIM34CLKSOURCE_LSE))
+
+#define IS_RCC_FDCAN1CLK(__SOURCE__) \
+ (((__SOURCE__) == RCC_FDCAN1CLKSOURCE_HSE) || \
+ ((__SOURCE__) == RCC_FDCAN1CLKSOURCE_PLL1) || \
+ ((__SOURCE__) == RCC_FDCAN1CLKSOURCE_PLL2))
+
+#define IS_RCC_SDMMCCLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_SDMMCCLKSOURCE_CLK48) || \
+ ((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL1))
+
+#define IS_RCC_RNGCLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \
+ ((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48_DIV2) || \
+ ((__SOURCE__) == RCC_RNGCLKSOURCE_HSI))
+
+#define IS_RCC_SAESCLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_SAESCLKSOURCE_SHSI) || \
+ ((__SOURCE__) == RCC_SAESCLKSOURCE_SHSI_DIV2))
+
+#define IS_RCC_ADCDACCLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_ADCDACCLKSOURCE_HCLK) || \
+ ((__SOURCE__) == RCC_ADCDACCLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_ADCDACCLKSOURCE_PLL2) || \
+ ((__SOURCE__) == RCC_ADCDACCLKSOURCE_HSE) || \
+ ((__SOURCE__) == RCC_ADCDACCLKSOURCE_HSI) || \
+ ((__SOURCE__) == RCC_ADCDACCLKSOURCE_MSIK))
+
+#define IS_RCC_MDF1CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_MDF1CLKSOURCE_HCLK) || \
+ ((__SOURCE__) == RCC_MDF1CLKSOURCE_PLL1) || \
+ ((__SOURCE__) == RCC_MDF1CLKSOURCE_PLL3) || \
+ ((__SOURCE__) == RCC_MDF1CLKSOURCE_PIN) || \
+ ((__SOURCE__) == RCC_MDF1CLKSOURCE_MSIK))
+
+#define IS_RCC_ADF1CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_ADF1CLKSOURCE_HCLK) || \
+ ((__SOURCE__) == RCC_ADF1CLKSOURCE_PLL1) || \
+ ((__SOURCE__) == RCC_ADF1CLKSOURCE_PLL3) || \
+ ((__SOURCE__) == RCC_ADF1CLKSOURCE_PIN) || \
+ ((__SOURCE__) == RCC_ADF1CLKSOURCE_MSIK))
+
+#define IS_RCC_OSPICLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_OSPICLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_OSPICLKSOURCE_MSIK) || \
+ ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL1) ||\
+ ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL2))
+
+#define IS_RCC_CLK48CLKSOURCE(__SOURCE__)\
+ (((__SOURCE__) == RCC_CLK48CLKSOURCE_HSI48)|| \
+ ((__SOURCE__) == RCC_CLK48CLKSOURCE_PLL2) || \
+ ((__SOURCE__) == RCC_CLK48CLKSOURCE_PLL1) || \
+ ((__SOURCE__) == RCC_CLK48CLKSOURCE_MSIK))
+
+#define IS_RCC_SPI1CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_SPI1CLKSOURCE_PCLK2) || \
+ ((__SOURCE__) == RCC_SPI1CLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_SPI1CLKSOURCE_HSI)|| \
+ ((__SOURCE__) == RCC_SPI1CLKSOURCE_MSIK))
+
+#define IS_RCC_SPI2CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_SPI2CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_SPI2CLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_SPI2CLKSOURCE_HSI)|| \
+ ((__SOURCE__) == RCC_SPI2CLKSOURCE_MSIK))
+
+#define IS_RCC_SPI3CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_SPI3CLKSOURCE_PCLK3) || \
+ ((__SOURCE__) == RCC_SPI3CLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_SPI3CLKSOURCE_HSI)|| \
+ ((__SOURCE__) == RCC_SPI3CLKSOURCE_MSIK))
+
+#define IS_RCC_DAC1CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_DAC1CLKSOURCE_LSE) || \
+ ((__SOURCE__) == RCC_DAC1CLKSOURCE_LSI))
+
+#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
+#if defined(CRS)
+
+#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \
+ ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \
+ ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))
+
+#define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \
+ ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \
+ ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
+ ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
+
+#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
+ ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
+
+#define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU))
+
+#define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU))
+
+#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
+
+#define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
+ ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
+
+#endif /* CRS */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup RCCEx_Private_Functions RCCEx Private Functions
+ * @{
+ */
+static HAL_StatusTypeDef RCCEx_PLLSource_Enable(uint32_t PllSource);
+static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *Pll2);
+static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *Pll3);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
+ * @{
+ */
+
+/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
+ * @brief Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the RCC Clocks
+ frequencies.
+ [..]
+ (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
+ select the RTC clock source; in this case the Backup domain will be reset in
+ order to modify the RTC Clock source, as consequence RTC registers (including
+ the backup registers) are set to their reset values.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initialize the RCC extended peripherals clocks according to the specified
+ * parameters in the RCC_PeriphCLKInitTypeDef.
+ * @param pPeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * contains a field PeriphClockSelection which can be a combination of the following values:
+ * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_LPTIM34 LPTIM34 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_SAES SAES peripheral clock
+ * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADCDAC ADC1,ADC4,DAC peripheral clock
+ * @arg @ref RCC_PERIPHCLK_MDF1 MDF1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADF1 ADF1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
+ * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock
+ * @arg @ref RCC_PERIPHCLK_CLK48 CLK48 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_SDMMC SDMMC peripheral clock
+ * @arg @ref RCC_PERIPHCLK_SPI1 SPI1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_SPI2 SPI2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_SPI3 SPI3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_OSPI OSPI peripheral clock
+ * @arg @ref RCC_PERIPHCLK_FDCAN1 FDCAN1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_DAC1 DAC1 peripheral clock
+ *
+ * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+ * the RTC clock source: in this case the access to Backup domain is enabled.
+ *
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit)
+{
+ uint32_t tmpregister;
+ uint32_t tickstart;
+ HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
+ HAL_StatusTypeDef status = HAL_OK; /* Final status */
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PERIPHCLOCK(pPeriphClkInit->PeriphClockSelection));
+
+ /*-------------------------- USART1 clock source configuration -------------------*/
+ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_USART1CLKSOURCE(pPeriphClkInit->Usart1ClockSelection));
+
+ /* Configure the USART1 clock source */
+ __HAL_RCC_USART1_CONFIG(pPeriphClkInit->Usart1ClockSelection);
+ }
+
+ /*-------------------------- USART2 clock source configuration -------------------*/
+ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_USART2CLKSOURCE(pPeriphClkInit->Usart2ClockSelection));
+
+ /* Configure the USART2 clock source */
+ __HAL_RCC_USART2_CONFIG(pPeriphClkInit->Usart2ClockSelection);
+ }
+
+ /*-------------------------- USART3 clock source configuration -------------------*/
+ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_USART3CLKSOURCE(pPeriphClkInit->Usart3ClockSelection));
+
+ /* Configure the USART3 clock source */
+ __HAL_RCC_USART3_CONFIG(pPeriphClkInit->Usart3ClockSelection);
+ }
+
+ /*-------------------------- UART4 clock source configuration --------------------*/
+ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_UART4CLKSOURCE(pPeriphClkInit->Uart4ClockSelection));
+
+ /* Configure the UART4 clock source */
+ __HAL_RCC_UART4_CONFIG(pPeriphClkInit->Uart4ClockSelection);
+ }
+
+ /*-------------------------- UART5 clock source configuration --------------------*/
+ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_UART5CLKSOURCE(pPeriphClkInit->Uart5ClockSelection));
+
+ /* Configure the UART5 clock source */
+ __HAL_RCC_UART5_CONFIG(pPeriphClkInit->Uart5ClockSelection);
+ }
+
+ /*-------------------------- LPUART1 clock source configuration ------------------*/
+ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_LPUART1CLKSOURCE(pPeriphClkInit->Lpuart1ClockSelection));
+
+ /* Configure the LPUART1 clock source */
+ __HAL_RCC_LPUART1_CONFIG(pPeriphClkInit->Lpuart1ClockSelection);
+ }
+
+ /*-------------------------- I2C1 clock source configuration ---------------------*/
+ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2C1CLKSOURCE(pPeriphClkInit->I2c1ClockSelection));
+
+ /* Configure the I2C1 clock source */
+ __HAL_RCC_I2C1_CONFIG(pPeriphClkInit->I2c1ClockSelection);
+ }
+
+ /*-------------------------- I2C2 clock source configuration ---------------------*/
+ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2C2CLKSOURCE(pPeriphClkInit->I2c2ClockSelection));
+
+ /* Configure the I2C2 clock source */
+ __HAL_RCC_I2C2_CONFIG(pPeriphClkInit->I2c2ClockSelection);
+ }
+
+ /*-------------------------- I2C3 clock source configuration ---------------------*/
+ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2C3CLKSOURCE(pPeriphClkInit->I2c3ClockSelection));
+
+ /* Configure the I2C3 clock source */
+ __HAL_RCC_I2C3_CONFIG(pPeriphClkInit->I2c3ClockSelection);
+ }
+
+ /*-------------------------- I2C4 clock source configuration ---------------------*/
+ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2C4CLKSOURCE(pPeriphClkInit->I2c4ClockSelection));
+
+ /* Configure the I2C4 clock source */
+ __HAL_RCC_I2C4_CONFIG(pPeriphClkInit->I2c4ClockSelection);
+ }
+
+ /*-------------------------- LPTIM1 clock source configuration -------------------*/
+ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
+ {
+ assert_param(IS_RCC_LPTIM1CLK(pPeriphClkInit->Lptim1ClockSelection));
+ __HAL_RCC_LPTIM1_CONFIG(pPeriphClkInit->Lptim1ClockSelection);
+ }
+
+ /*-------------------------- LPTIM2 clock source configuration -------------------*/
+ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
+ {
+ assert_param(IS_RCC_LPTIM2CLK(pPeriphClkInit->Lptim2ClockSelection));
+ __HAL_RCC_LPTIM2_CONFIG(pPeriphClkInit->Lptim2ClockSelection);
+ }
+
+ /*-------------------------- LPTIM34 clock source configuration -------------------*/
+ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM34) == (RCC_PERIPHCLK_LPTIM34))
+ {
+ assert_param(IS_RCC_LPTIM34CLK(pPeriphClkInit->Lptim34ClockSelection));
+ __HAL_RCC_LPTIM34_CONFIG(pPeriphClkInit->Lptim34ClockSelection);
+ }
+
+ /*-------------------------- SAI1 clock source configuration ---------------------*/
+ if ((((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1))
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SAI1CLK(pPeriphClkInit->Sai1ClockSelection));
+
+ switch (pPeriphClkInit->Sai1ClockSelection)
+ {
+ case RCC_SAI1CLKSOURCE_PLL1: /* PLL is used as clock source for SAI1*/
+ /* Enable SAI Clock output generated from System PLL */
+ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
+ /* SAI1 clock source config set later after clock selection check */
+ break;
+
+ case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/
+ /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
+ ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
+ /* SAI1 clock source config set later after clock selection check */
+ break;
+
+ case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI1*/
+ /* PLL3 P input clock, parameters M, N & P configuration clock output (PLL3ClockOut) */
+ ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
+ /* SAI1 clock source config set later after clock selection check */
+ break;
+
+ case RCC_SAI1CLKSOURCE_PIN: /* External clock is used as source of SAI1 clock*/
+ /* SAI1 clock source configuration done later after clock selection check */
+ break;
+
+ case RCC_SAI1CLKSOURCE_HSI: /* HSI is used as source of SAI1 clock*/
+ /* SAI1 clock source config set later after clock selection check */
+ break;
+
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+
+ if (ret == HAL_OK)
+ {
+ /* Set the source of SAI1 clock*/
+ __HAL_RCC_SAI1_CONFIG(pPeriphClkInit->Sai1ClockSelection);
+ }
+ else
+ {
+ /* set overall return value */
+ status = ret;
+ }
+ }
+
+ /*-------------------------- SAI2 clock source configuration ---------------------*/
+ if ((((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2))
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SAI2CLK(pPeriphClkInit->Sai2ClockSelection));
+
+ switch (pPeriphClkInit->Sai2ClockSelection)
+ {
+ case RCC_SAI2CLKSOURCE_PLL1: /* PLL is used as clock source for SAI2*/
+ /* Enable SAI Clock output generated from System PLL */
+ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
+ /* SAI2 clock source config set later after clock selection check */
+ break;
+
+ case RCC_SAI2CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
+ /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
+ ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
+ /* SAI2 clock source config set later after clock selection check */
+ break;
+
+ case RCC_SAI2CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/
+ /* PLL3 P input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */
+ ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
+ /* SAI2 clock source config set later after clock selection check */
+ break;
+
+ case RCC_SAI2CLKSOURCE_PIN: /* External clock is used as source of SAI2 clock*/
+ /* SAI2 clock source configuration done later after clock selection check */
+ break;
+ case RCC_SAI2CLKSOURCE_HSI: /* HSI is used as source of SAI2 clock*/
+ /* SAI2 clock source config set later after clock selection check */
+ break;
+
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+
+ if (ret == HAL_OK)
+ {
+ /* Set the source of SAI2 clock*/
+ __HAL_RCC_SAI2_CONFIG(pPeriphClkInit->Sai2ClockSelection);
+ }
+ else
+ {
+ /* set overall return value */
+ status = ret;
+ }
+ }
+
+ /*-------------------------- ADCDAC clock source configuration ----------------------*/
+ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADCDAC) == RCC_PERIPHCLK_ADCDAC)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_ADCDACCLKSOURCE(pPeriphClkInit->AdcDacClockSelection));
+
+ switch (pPeriphClkInit->AdcDacClockSelection)
+ {
+ case RCC_ADCDACCLKSOURCE_PLL2:
+ /* PLL2 input clock, parameters M, N,P, & R configuration and clock output (PLL2ClockOut) */
+ ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
+ break;
+
+ case RCC_ADCDACCLKSOURCE_SYSCLK:
+ case RCC_ADCDACCLKSOURCE_HCLK:
+ case RCC_ADCDACCLKSOURCE_HSE:
+ case RCC_ADCDACCLKSOURCE_HSI:
+ case RCC_ADCDACCLKSOURCE_MSIK:
+ break;
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+
+ if (ret == HAL_OK)
+ {
+ /* Configure the ADC1 interface clock source */
+ __HAL_RCC_ADCDAC_CONFIG(pPeriphClkInit->AdcDacClockSelection);
+ }
+ else
+ {
+ /* set overall return value */
+ status = ret;
+ }
+ }
+
+ /*-------------------------- MDF1 clock source configuration -------------------*/
+ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_MDF1) == RCC_PERIPHCLK_MDF1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_MDF1CLKSOURCE(pPeriphClkInit->Mdf1ClockSelection));
+
+ switch (pPeriphClkInit->Mdf1ClockSelection)
+ {
+ case RCC_MDF1CLKSOURCE_PLL1:
+ /* Enable PLL1 Clock output generated from System PLL */
+ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
+ break;
+ case RCC_MDF1CLKSOURCE_PLL3:
+ /* PLL3 Q input clock, parameters M, N & Q configuration and clock output (PLL3ClockOut) */
+ ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
+ break;
+ case RCC_MDF1CLKSOURCE_HCLK:
+ break;
+ case RCC_MDF1CLKSOURCE_PIN:
+ break;
+ case RCC_MDF1CLKSOURCE_MSIK:
+ break;
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+
+ if (ret == HAL_OK)
+ {
+ /* Configure the MDF1 interface clock source */
+ __HAL_RCC_MDF1_CONFIG(pPeriphClkInit->Mdf1ClockSelection);
+ }
+ else
+ {
+ /* set overall return value */
+ status = ret;
+ }
+ }
+
+ /*-------------------------- ADF1 clock source configuration -------------------*/
+ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADF1) == RCC_PERIPHCLK_ADF1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_ADF1CLKSOURCE(pPeriphClkInit->Adf1ClockSelection));
+
+ switch (pPeriphClkInit->Adf1ClockSelection)
+ {
+ case RCC_ADF1CLKSOURCE_PLL1:
+ /* Enable PLL1 Clock output generated from System PLL */
+ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
+ break;
+ case RCC_ADF1CLKSOURCE_PLL3:
+ /* PLL3 Q input clock, parameters M, N & Q configuration and clock output (PLL3ClockOut) */
+ ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
+ break;
+ case RCC_ADF1CLKSOURCE_HCLK:
+ break;
+ case RCC_ADF1CLKSOURCE_PIN:
+ break;
+ case RCC_ADF1CLKSOURCE_MSIK:
+ break;
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+
+ if (ret == HAL_OK)
+ {
+ /* Configure the ADF1 interface clock source */
+ __HAL_RCC_ADF1_CONFIG(pPeriphClkInit->Adf1ClockSelection);
+ }
+ else
+ {
+ /* set overall return value */
+ status = ret;
+ }
+ }
+
+ /*-------------------------- RTC clock source configuration ----------------------*/
+ if ((pPeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
+ {
+ FlagStatus pwrclkchanged = RESET;
+ /* Check for RTC Parameters used to output RTCCLK */
+ assert_param(IS_RCC_RTCCLKSOURCE(pPeriphClkInit->RTCClockSelection));
+
+ /* Enable Power Clock */
+ if (__HAL_RCC_PWR_IS_CLK_DISABLED())
+ {
+ __HAL_RCC_PWR_CLK_ENABLE();
+ pwrclkchanged = SET;
+ }
+ /* Enable write access to Backup domain */
+ SET_BIT(PWR->DBPR, PWR_DBPR_DBP);
+
+ /* Wait for Backup domain Write protection disable */
+ tickstart = HAL_GetTick();
+
+ while (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP))
+ {
+ if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+ {
+ ret = HAL_TIMEOUT;
+ break;
+ }
+ }
+
+ if (ret == HAL_OK)
+ {
+ /* Reset the Backup domain only if the RTC Clock source selection is modified from default */
+ tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
+
+ if ((tmpregister != RCC_RTCCLKSOURCE_NO_CLK) && (tmpregister != pPeriphClkInit->RTCClockSelection))
+ {
+ /* Store the content of BDCR register before the reset of Backup Domain */
+ tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
+ /* RTC Clock selection can be changed only if the Backup Domain is reset */
+ __HAL_RCC_BACKUPRESET_FORCE();
+ __HAL_RCC_BACKUPRESET_RELEASE();
+ /* Restore the Content of BDCR register */
+ RCC->BDCR = tmpregister;
+ }
+
+ /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
+ if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ ret = HAL_TIMEOUT;
+ break;
+ }
+ }
+ }
+
+ if (ret == HAL_OK)
+ {
+ /* Apply new RTC clock source selection */
+ __HAL_RCC_RTC_CONFIG(pPeriphClkInit->RTCClockSelection);
+ }
+ else
+ {
+ /* set overall return value */
+ status = ret;
+ }
+ }
+ else
+ {
+ /* set overall return value */
+ status = ret;
+ }
+
+ /* Restore clock configuration if changed */
+ if (pwrclkchanged == SET)
+ {
+ __HAL_RCC_PWR_CLK_DISABLE();
+ }
+ }
+
+ /*-------------------------------------- CK48 Configuration -----------------------------------*/
+ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_CLK48CLKSOURCE(pPeriphClkInit->Clk48ClockSelection));
+
+ switch (pPeriphClkInit->Clk48ClockSelection)
+ {
+ case RCC_CLK48CLKSOURCE_PLL2:
+ /* PLL2 input clock, parameters M, N,P,Q & R configuration and clock output (PLL2ClockOut) */
+ ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
+ break;
+ case RCC_CLK48CLKSOURCE_PLL1:
+ /* Enable CLK48 Clock output generated from System PLL */
+ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+ break;
+ case RCC_CLK48CLKSOURCE_HSI48:
+ break;
+ case RCC_CLK48CLKSOURCE_MSIK:
+ break;
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+ if (ret == HAL_OK)
+ {
+ /* Configure the CLK48 source */
+ __HAL_RCC_CLK48_CONFIG(pPeriphClkInit->Clk48ClockSelection);
+ }
+ else
+ {
+ /* set overall return value */
+ status = ret;
+ }
+ }
+
+ /*------------------------------ RNG Configuration -------------------------*/
+ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)
+ {
+
+ /* Check the parameters */
+ assert_param(IS_RCC_RNGCLKSOURCE(pPeriphClkInit->RngClockSelection));
+
+ switch (pPeriphClkInit->RngClockSelection)
+ {
+ case RCC_RNGCLKSOURCE_HSI48_DIV2: /* HSI48/2 is used as clock source for RNG*/
+ /* RNG clock source configuration done later after clock selection check */
+ break;
+ case RCC_RNGCLKSOURCE_HSI: /* HSI is used as clock source for RNG*/
+ /* RNG clock source configuration done later after clock selection check */
+ break;
+ case RCC_RNGCLKSOURCE_HSI48:
+ /* HSI48 oscillator is used as source of RNG clock */
+ /* RNG clock source configuration done later after clock selection check */
+ break;
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+
+ if (ret == HAL_OK)
+ {
+ /* Set the source of RNG clock*/
+ __HAL_RCC_RNG_CONFIG(pPeriphClkInit->RngClockSelection);
+ }
+ else
+ {
+ /* set overall return value */
+ status = ret;
+ }
+ }
+
+ /*-------------------------- SAES clock source configuration ----------------*/
+ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAES) == RCC_PERIPHCLK_SAES)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SAESCLKSOURCE(pPeriphClkInit->SaesClockSelection));
+
+ /* Configure the SAES clock source */
+ __HAL_RCC_SAES_CONFIG(pPeriphClkInit->SaesClockSelection);
+ }
+
+ /*-------------------------- SDMMC1/2 clock source configuration -------------------*/
+ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == (RCC_PERIPHCLK_SDMMC))
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SDMMCCLKSOURCE(pPeriphClkInit->SdmmcClockSelection));
+
+ if (pPeriphClkInit->SdmmcClockSelection == RCC_SDMMCCLKSOURCE_PLL1)
+ {
+ /* Enable PLL1 P CLK output */
+ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
+ }
+
+ /* Configure the SDMMC1/2 clock source */
+ __HAL_RCC_SDMMC_CONFIG(pPeriphClkInit->SdmmcClockSelection);
+ }
+
+ /*-------------------------- SPI1 clock source configuration ----------------*/
+ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI1) == RCC_PERIPHCLK_SPI1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SPI1CLKSOURCE(pPeriphClkInit->Spi1ClockSelection));
+
+ /* Configure the SPI1 clock source */
+ __HAL_RCC_SPI1_CONFIG(pPeriphClkInit->Spi1ClockSelection);
+ }
+
+ /*-------------------------- SPI2 clock source configuration ----------------*/
+ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI2) == RCC_PERIPHCLK_SPI2)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SPI2CLKSOURCE(pPeriphClkInit->Spi2ClockSelection));
+
+ /* Configure the SPI2 clock source */
+ __HAL_RCC_SPI2_CONFIG(pPeriphClkInit->Spi2ClockSelection);
+ }
+
+ /*-------------------------- SPI3 clock source configuration ----------------*/
+ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI3) == RCC_PERIPHCLK_SPI3)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SPI3CLKSOURCE(pPeriphClkInit->Spi3ClockSelection));
+
+ /* Configure the SPI3 clock source */
+ __HAL_RCC_SPI3_CONFIG(pPeriphClkInit->Spi3ClockSelection);
+ }
+
+ /*-------------------------- OctoSPIx clock source configuration ----------------*/
+ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_OSPICLKSOURCE(pPeriphClkInit->OspiClockSelection));
+
+ if (pPeriphClkInit->OspiClockSelection == RCC_OSPICLKSOURCE_PLL1)
+ {
+ /* Enable PLL1 Q CLK output */
+ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+ }
+ if (pPeriphClkInit->OspiClockSelection == RCC_OSPICLKSOURCE_PLL2)
+ {
+ /* Enable PLL2 Q CLK output */
+ __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ);
+ }
+ /* Configure the OctoSPI clock source */
+ __HAL_RCC_OSPI_CONFIG(pPeriphClkInit->OspiClockSelection);
+ }
+
+ /*-------------------------- FDCAN1 kernel clock source configuration -------------*/
+ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN1) == (RCC_PERIPHCLK_FDCAN1))
+ {
+ assert_param(IS_RCC_FDCAN1CLK(pPeriphClkInit->Fdcan1ClockSelection));
+
+ switch (pPeriphClkInit->Fdcan1ClockSelection)
+ {
+ case RCC_FDCAN1CLKSOURCE_HSE: /* HSE is used as source of FDCAN1 kernel clock*/
+ /* FDCAN1 kernel clock source config set later after clock selection check */
+ break;
+ case RCC_FDCAN1CLKSOURCE_PLL1: /* PLL1 is used as clock source for FDCAN1 kernel clock*/
+ /* Enable 48M2 Clock output generated from System PLL */
+ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+ /* FDCAN1 kernel clock source config set later after clock selection check */
+ break;
+ case RCC_FDCAN1CLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN1 kernel clock*/
+ /* PLL2 input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
+ ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
+ /* FDCAN1 kernel clock source config set later after clock selection check */
+ break;
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+ if (ret == HAL_OK)
+ {
+ /* Set the source of FDCAN1 kernel clock*/
+ __HAL_RCC_FDCAN1_CONFIG(pPeriphClkInit->Fdcan1ClockSelection);
+ }
+ else
+ {
+ /* set overall return value */
+ status = ret;
+ }
+ }
+
+ /*-------------------------- DAC1 clock source configuration ----------------*/
+ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DAC1) == RCC_PERIPHCLK_DAC1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_DAC1CLKSOURCE(pPeriphClkInit->Dac1ClockSelection));
+
+ /* Configure the DAC1 clock source */
+ __HAL_RCC_DAC1_CONFIG(pPeriphClkInit->Dac1ClockSelection);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
+ * @param pPeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * returns the configuration information for the Extended Peripherals
+ * clocks(USART1, USART2, USART3, UART4, UART5, LPUART, I2C1, I2C2, I2C3, LPTIM1, LPTIM2, SAI1, SAI2,
+ * SAES, ADC1, ADC4, MDF1, MDF2, RTC, CLK48, SDMMC1, I2C4, SPI12, SPI3, OSPI, FDCAN1, DAC1).
+ * @retval None
+ */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit)
+{
+ /* Set all possible values for the extended clock type parameter------------*/
+ pPeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
+ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \
+ RCC_PERIPHCLK_SAES | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \
+ RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | \
+ RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDMMC | \
+ RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | \
+ RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_OSPI | \
+ RCC_PERIPHCLK_FDCAN1 | RCC_PERIPHCLK_DAC1;
+
+ /* Get the PLL2 Clock configuration -----------------------------------------------*/
+ pPeriphClkInit->PLL2.PLL2Source = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC) >> RCC_PLL2CFGR_PLL2SRC_Pos);
+ pPeriphClkInit->PLL2.PLL2M = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M_Pos) + 1U;
+ pPeriphClkInit->PLL2.PLL2N = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N) >> RCC_PLL2DIVR_PLL2N_Pos) + 1U;
+ pPeriphClkInit->PLL2.PLL2P = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2P) >> RCC_PLL2DIVR_PLL2P_Pos) + 1U;
+ pPeriphClkInit->PLL2.PLL2Q = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2Q) >> RCC_PLL2DIVR_PLL2Q_Pos) + 1U;
+ pPeriphClkInit->PLL2.PLL2R = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2R) >> RCC_PLL2DIVR_PLL2R_Pos) + 1U;
+ pPeriphClkInit->PLL2.PLL2RGE = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2RGE) >> RCC_PLL2CFGR_PLL2RGE_Pos);
+ pPeriphClkInit->PLL2.PLL2FRACN = (uint32_t)((RCC->PLL2FRACR & RCC_PLL2FRACR_PLL2FRACN) >> \
+ RCC_PLL2FRACR_PLL2FRACN_Pos);
+
+ /* Get the PLL3 Clock configuration -----------------------------------------------*/
+ pPeriphClkInit->PLL3.PLL3Source = (uint32_t)((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3SRC) >> RCC_PLL3CFGR_PLL3SRC_Pos);
+ pPeriphClkInit->PLL3.PLL3M = (uint32_t)((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3M) >> RCC_PLL3CFGR_PLL3M_Pos) + 1U;
+ pPeriphClkInit->PLL3.PLL3N = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N) >> RCC_PLL3DIVR_PLL3N_Pos) + 1U;
+ pPeriphClkInit->PLL3.PLL3P = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3P) >> RCC_PLL3DIVR_PLL3P_Pos) + 1U;
+ pPeriphClkInit->PLL3.PLL3Q = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3Q) >> RCC_PLL3DIVR_PLL3Q_Pos) + 1U;
+ pPeriphClkInit->PLL3.PLL3R = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3R) >> RCC_PLL3DIVR_PLL3R_Pos) + 1U;
+ pPeriphClkInit->PLL3.PLL3RGE = (uint32_t)((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3RGE) >> RCC_PLL3CFGR_PLL3RGE_Pos);
+ pPeriphClkInit->PLL3.PLL3FRACN = (uint32_t)((RCC->PLL3FRACR & RCC_PLL3FRACR_PLL3FRACN) >> \
+ RCC_PLL3FRACR_PLL3FRACN_Pos);
+
+ /* Get the USART1 clock source ---------------------------------------------*/
+ pPeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
+
+ /* Get the USART2 clock source ---------------------------------------------*/
+ pPeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
+
+ /* Get the USART3 clock source ---------------------------------------------*/
+ pPeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
+
+ /* Get the UART4 clock source ----------------------------------------------*/
+ pPeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();
+
+ /* Get the UART5 clock source ----------------------------------------------*/
+ pPeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();
+
+ /* Get the LPUART1 clock source --------------------------------------------*/
+ pPeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();
+
+ /* Get the I2C1 clock source -----------------------------------------------*/
+ pPeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
+
+ /* Get the I2C2 clock source -----------------------------------------------*/
+ pPeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
+
+ /* Get the I2C3 clock source -----------------------------------------------*/
+ pPeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
+
+ /* Get the I2C4 clock source -----------------------------------------------*/
+ pPeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE();
+
+ /* Get the LPTIM1 clock source ---------------------------------------------*/
+ pPeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
+
+ /* Get the LPTIM2 clock source ---------------------------------------------*/
+ pPeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE();
+
+ /* Get the LPTIM34 clock source --------------------------------------------*/
+ pPeriphClkInit->Lptim34ClockSelection = __HAL_RCC_GET_LPTIM34_SOURCE();
+
+ /* Get the FDCAN1 clock source ---------------------------------------------*/
+ pPeriphClkInit->Fdcan1ClockSelection = __HAL_RCC_GET_FDCAN1_SOURCE();
+
+ /* Get the MDF1 clock source -----------------------------------------------*/
+ pPeriphClkInit->Mdf1ClockSelection = __HAL_RCC_GET_MDF1_SOURCE();
+
+ /* Get the ADF1 clock source -----------------------------------------------*/
+ pPeriphClkInit->Adf1ClockSelection = __HAL_RCC_GET_ADF1_SOURCE();
+
+ /* Get the SAES clock source -----------------------------------------------*/
+ pPeriphClkInit->SaesClockSelection = __HAL_RCC_GET_SAES_SOURCE();
+
+ /* Get the SAI1 clock source -----------------------------------------------*/
+ pPeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
+
+ /* Get the SAI2 clock source -----------------------------------------------*/
+ pPeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
+
+ /* Get the CLK48 clock source ----------------------------------------------*/
+ pPeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
+
+ /* Get the SDMMC clock source ----------------------------------------------*/
+ pPeriphClkInit->SdmmcClockSelection = __HAL_RCC_GET_SDMMC_SOURCE();
+
+ /* Get the ADCDAC clock source ---------------------------------------------*/
+ pPeriphClkInit->AdcDacClockSelection = __HAL_RCC_GET_ADCDAC_SOURCE();
+
+ /* Get the DAC1 clock source -----------------------------------------------*/
+ pPeriphClkInit->Dac1ClockSelection = __HAL_RCC_GET_DAC1_SOURCE();
+
+ /* Get the OSPI clock source -----------------------------------------------*/
+ pPeriphClkInit->OspiClockSelection = __HAL_RCC_GET_OSPI_SOURCE();
+
+ /* Get the SPI1 clock source -----------------------------------------------*/
+ pPeriphClkInit->Spi1ClockSelection = __HAL_RCC_GET_SPI1_SOURCE();
+
+ /* Get the SPI2 clock source -----------------------------------------------*/
+ pPeriphClkInit->Spi2ClockSelection = __HAL_RCC_GET_SPI2_SOURCE();
+
+ /* Get the SPI3 clock source -----------------------------------------------*/
+ pPeriphClkInit->Spi3ClockSelection = __HAL_RCC_GET_SPI3_SOURCE();
+
+ /* Get the RTC clock source ------------------------------------------------*/
+ pPeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
+
+ /* Get the RNG clock source ------------------------------------------------*/
+ pPeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE();
+}
+
+/**
+ * @brief Returns the PLL1 clock frequencies :PLL1_P_Frequency,PLL1_R_Frequency and PLL1_Q_Frequency
+ * @note The PLL1 clock frequencies computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ * @note The function returns values based on HSE_VALUE, HSI_VALUE or MSI Value multiplied/divided by the PLL
+ * factors.
+ * @note This function can be used by the user application to compute the
+ * baud-rate for the communication peripherals or configure other parameters.
+ *
+ * @note Each time PLL1CLK changes, this function must be called to update the
+ * right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect.
+ * @param PLL1_Clocks structure.
+ * @retval None
+ */
+void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks)
+{
+ uint32_t pll1source;
+ uint32_t pll1m;
+ uint32_t pll1n;
+ uint32_t pll1fracen;
+ float_t fracn1;
+ float_t pll1vco;
+
+ pll1n = (RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N);
+ pll1source = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC);
+ pll1m = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U;
+ pll1fracen = RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN;
+ fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN) >> \
+ RCC_PLL1FRACR_PLL1FRACN_Pos));
+
+ if (pll1m != 0U)
+ {
+ switch (pll1source)
+ {
+
+ case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
+ pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
+ (fracn1 / (float_t)0x2000) + (float_t)1);
+ break;
+ case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
+ pll1vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll1m) * \
+ ((float_t)pll1n + (fracn1 / (float_t)0x2000) + (float_t)1);
+ break;
+ case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
+ pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
+ (fracn1 / (float_t)0x2000) + (float_t)1);
+ break;
+ default:
+ pll1vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll1m) * \
+ ((float_t)pll1n + (fracn1 / (float_t)0x2000) + (float_t)1);
+ break;
+ }
+
+ if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL1_DIVP) != 0U)
+ {
+ PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & \
+ RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + \
+ (float_t)1));
+ }
+ else
+ {
+ PLL1_Clocks->PLL1_P_Frequency = 0U;
+ }
+
+ if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL1_DIVQ) != 0U)
+ {
+ PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & \
+ RCC_PLL1DIVR_PLL1Q) >> RCC_PLL1DIVR_PLL1Q_Pos) + \
+ (float_t)1));
+ }
+ else
+ {
+ PLL1_Clocks->PLL1_Q_Frequency = 0U;
+ }
+
+ if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL1_DIVR) != 0U)
+ {
+ PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & \
+ RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + \
+ (float_t)1));
+ }
+ else
+ {
+ PLL1_Clocks->PLL1_R_Frequency = 0U;
+ }
+
+ }
+ else
+ {
+ PLL1_Clocks->PLL1_P_Frequency = 0U;
+ PLL1_Clocks->PLL1_Q_Frequency = 0U;
+ PLL1_Clocks->PLL1_R_Frequency = 0U;
+ }
+}
+
+/**
+ * @brief Returns the PLL2 clock frequencies :PLL2_P_Frequency,PLL2_R_Frequency and PLL2_Q_Frequency
+ * @note The PLL2 clock frequencies computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL
+ * factors.
+ * @note This function can be used by the user application to compute the
+ * baud-rate for the communication peripherals or configure other parameters.
+ *
+ * @note Each time PLL2CLK changes, this function must be called to update the
+ * right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect.
+ * @param PLL2_Clocks structure.
+ * @retval None
+ */
+void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks)
+{
+ uint32_t pll2source;
+ uint32_t pll2m;
+ uint32_t pll2n;
+ uint32_t pll2fracen;
+ float_t fracn2;
+ float_t pll2vco;
+
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N
+ PLL2xCLK = PLL2_VCO / PLL2x */
+ pll2n = (RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N);
+ pll2source = (RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC);
+ pll2m = ((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M_Pos) + 1U;
+ pll2fracen = RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2FRACEN;
+ fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_PLL2FRACN) >> \
+ RCC_PLL2FRACR_PLL2FRACN_Pos));
+
+ if (pll2m != 0U)
+ {
+ switch (pll2source)
+ {
+ case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
+ pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N) + \
+ (fracn2 / (float_t)0x2000) + (float_t)1);
+ break;
+
+ case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
+ pll2vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll2m) * \
+ ((float_t)pll2n + (fracn2 / (float_t)0x2000) + (float_t)1);
+ break;
+
+ case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
+ pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N) + \
+ (fracn2 / (float_t)0x2000) + (float_t)1);
+ break;
+
+ default:
+ pll2vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t) pll2m) \
+ * ((float_t)pll2n + (fracn2 / (float_t)0x2000) + (float_t)1);
+ break;
+ }
+ if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL2_DIVP) != 0U)
+ {
+ PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & \
+ RCC_PLL2DIVR_PLL2P) >> RCC_PLL2DIVR_PLL2P_Pos) + \
+ (float_t)1));
+ }
+ else
+ {
+ PLL2_Clocks->PLL2_P_Frequency = 0U;
+ }
+ if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL2_DIVQ) != 0U)
+ {
+ PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & \
+ RCC_PLL2DIVR_PLL2Q) >> RCC_PLL2DIVR_PLL2Q_Pos) + \
+ (float_t)1));
+ }
+ else
+ {
+ PLL2_Clocks->PLL2_Q_Frequency = 0U;
+ }
+ if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL2_DIVR) != 0U)
+ {
+ PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & \
+ RCC_PLL2DIVR_PLL2R) >> RCC_PLL2DIVR_PLL2R_Pos) + \
+ (float_t)1));
+ }
+ else
+ {
+ PLL2_Clocks->PLL2_R_Frequency = 0U;
+ }
+ }
+ else
+ {
+ PLL2_Clocks->PLL2_P_Frequency = 0U;
+ PLL2_Clocks->PLL2_Q_Frequency = 0U;
+ PLL2_Clocks->PLL2_R_Frequency = 0U;
+ }
+}
+
+/**
+ * @brief Returns the PLL3 clock frequencies :PLL3_P_Frequency,PLL3_R_Frequency and PLL3_Q_Frequency
+ * @note The PLL3 clock frequencies computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL
+ * factors.
+ * @note This function can be used by the user application to compute the
+ * baud-rate for the communication peripherals or configure other parameters.
+ *
+ * @note Each time PLL3CLK changes, this function must be called to update the
+ * right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect.
+ * @param PLL3_Clocks structure.
+ * @retval None
+ */
+void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks)
+{
+ uint32_t pll3source;
+ uint32_t pll3m;
+ uint32_t pll3n;
+ uint32_t pll3fracen;
+ float_t fracn3;
+ float_t pll3vco;
+
+ /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N
+ PLL3xCLK = PLL3_VCO / PLLxR
+ */
+
+ pll3n = (RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N);
+ pll3source = (RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3SRC);
+ pll3m = ((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3M) >> RCC_PLL3CFGR_PLL3M_Pos) + 1U;
+ pll3fracen = RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3FRACEN;
+ fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_PLL3FRACN) >> \
+ RCC_PLL3FRACR_PLL3FRACN_Pos));
+
+ if (pll3m != 0U)
+ {
+ switch (pll3source)
+ {
+ case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
+ pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N) + \
+ (fracn3 / (float_t)0x2000) + (float_t)1);
+
+ break;
+ case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
+ pll3vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll3m) * \
+ ((float_t)pll3n + (fracn3 / (float_t)0x2000) + (float_t)1);
+ break;
+
+ case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
+ pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N) + \
+ (fracn3 / (float_t)0x2000) + (float_t)1);
+ break;
+
+ default:
+ pll3vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll3m) * \
+ ((float_t)pll3n + (fracn3 / (float_t)0x2000) + (float_t)1);
+ break;
+ }
+
+ if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL3_DIVP) != 0U)
+ {
+ PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & \
+ RCC_PLL3DIVR_PLL3P) >> RCC_PLL3DIVR_PLL3P_Pos) + \
+ (float_t)1));
+ }
+ else
+ {
+ PLL3_Clocks->PLL3_P_Frequency = 0U;
+ }
+
+ if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL3_DIVQ) != 0U)
+ {
+ PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & \
+ RCC_PLL3DIVR_PLL3Q) >> RCC_PLL3DIVR_PLL3Q_Pos) + \
+ (float_t)1));
+ }
+ else
+ {
+ PLL3_Clocks->PLL3_Q_Frequency = 0U;
+ }
+
+ if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL3_DIVR) != 0U)
+ {
+ PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & \
+ RCC_PLL3DIVR_PLL3R) >> RCC_PLL3DIVR_PLL3R_Pos) + \
+ (float_t)1));
+ }
+ else
+ {
+ PLL3_Clocks->PLL3_R_Frequency = 0U;
+ }
+
+ }
+ else
+ {
+ PLL3_Clocks->PLL3_P_Frequency = 0U;
+ PLL3_Clocks->PLL3_Q_Frequency = 0U;
+ PLL3_Clocks->PLL3_R_Frequency = 0U;
+ }
+}
+
+/**
+ * @brief Return the peripheral clock frequency for peripherals
+ * @note Return 0 if peripheral clock identifier not managed by this API
+ * @param PeriphClk Peripheral clock identifier
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_LPTIM34 LPTIM34 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_SAES SAES peripheral clock
+ * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADCDAC ADC1,ADC4, DAC1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_MDF1 MDF1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_MDF1 MDF1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
+ * @arg @ref RCC_PERIPHCLK_CLK48 CLK48 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_SDMMC SDMMC peripheral clock
+ * @arg @ref RCC_PERIPHCLK_SPI1 SPI1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_SPI2 SPI2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_SPI3 SPI3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_OSPI OSPI peripheral clock
+ * @arg @ref RCC_PERIPHCLK_FDCAN1 FDCAN1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_DAC1 DAC1 peripheral clock
+ * @retval Frequency in Hz
+ */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+{
+ PLL1_ClocksTypeDef pll1_clocks;
+ PLL2_ClocksTypeDef pll2_clocks;
+ PLL3_ClocksTypeDef pll3_clocks;
+
+ uint32_t frequency;
+ uint32_t srcclk;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
+
+ if (PeriphClk == RCC_PERIPHCLK_RTC)
+ {
+ /* Get the current RTC source */
+ srcclk = __HAL_RCC_GET_RTC_SOURCE();
+
+ /* Check if LSE is ready and if RTC clock selection is LSE */
+ if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_RTCCLKSOURCE_LSE))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Check if LSI is ready and if RTC clock selection is LSI */
+ else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_RTCCLKSOURCE_LSI))
+ {
+ if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIPREDIV))
+ {
+ frequency = LSI_VALUE / 128U;
+ }
+ else
+ {
+ frequency = LSI_VALUE;
+ }
+ }
+ /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_RTCCLKSOURCE_HSE_DIV32))
+ {
+ frequency = HSE_VALUE / 32U;
+ }
+ /* Clock not enabled for RTC*/
+ else
+ {
+ frequency = 0U;
+ }
+ }
+ else
+ {
+ /* Other external peripheral clock source than RTC */
+ switch (PeriphClk)
+ {
+ case RCC_PERIPHCLK_SAI1:
+
+ srcclk = __HAL_RCC_GET_SAI1_SOURCE();
+
+ switch (srcclk)
+ {
+ case RCC_SAI1CLKSOURCE_PLL1: /* PLL1P is the clock source for SAI1 */
+
+ HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+ frequency = pll1_clocks.PLL1_P_Frequency;
+ break;
+
+ case RCC_SAI1CLKSOURCE_PLL2: /* PLL2P is the clock source for SAI1 */
+
+ HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ frequency = pll2_clocks.PLL2_P_Frequency;
+ break;
+
+ case RCC_SAI1CLKSOURCE_PLL3: /* PLLI3P is the clock source for SAI1 */
+
+ HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+ frequency = pll3_clocks.PLL3_P_Frequency;
+ break;
+
+ case RCC_SAI1CLKSOURCE_PIN:
+
+ frequency = EXTERNAL_SAI1_CLOCK_VALUE;
+ break;
+
+ case RCC_SAI1CLKSOURCE_HSI: /* HSI is the clock source for SAI1 */
+
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
+ {
+ frequency = HSI_VALUE;
+ }
+ else
+ {
+ frequency = 0U;
+ }
+ break;
+
+ default :
+ {
+ frequency = 0U;
+ break;
+ }
+ }
+ break;
+
+ case RCC_PERIPHCLK_SAI2:
+
+ srcclk = __HAL_RCC_GET_SAI2_SOURCE();
+
+ switch (srcclk)
+ {
+ case RCC_SAI2CLKSOURCE_PLL1: /* PLL1P is the clock source for SAI1 */
+
+ HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+ frequency = pll1_clocks.PLL1_P_Frequency;
+ break;
+
+ case RCC_SAI2CLKSOURCE_PLL2: /* PLL2P is the clock source for SAI1 */
+
+ HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ frequency = pll2_clocks.PLL2_P_Frequency;
+ break;
+
+ case RCC_SAI2CLKSOURCE_PLL3: /* PLLI3P is the clock source for SAI1 */
+
+ HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+ frequency = pll3_clocks.PLL3_P_Frequency;
+ break;
+
+ case RCC_SAI2CLKSOURCE_PIN:
+
+ frequency = EXTERNAL_SAI1_CLOCK_VALUE;
+ break;
+
+ case RCC_SAI2CLKSOURCE_HSI: /* HSI is the clock source for SAI1 */
+
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
+ {
+ frequency = HSI_VALUE;
+ }
+ else
+ {
+ frequency = 0U;
+ }
+ break;
+
+ default :
+
+ frequency = 0U;
+ break;
+
+ }
+ break;
+ case RCC_PERIPHCLK_SAES:
+ /* Get the current SAES source */
+ srcclk = __HAL_RCC_GET_SAES_SOURCE();
+
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (srcclk == RCC_SAESCLKSOURCE_SHSI))
+ {
+ frequency = HSI_VALUE;
+ }
+ else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (srcclk == RCC_SAESCLKSOURCE_SHSI_DIV2))
+ {
+ frequency = HSI_VALUE >> 1U;
+ }
+ /* Clock not enabled for SAES */
+ else
+ {
+ frequency = 0U;
+ }
+ break;
+
+ case RCC_PERIPHCLK_CLK48:
+
+ srcclk = __HAL_RCC_GET_CLK48_SOURCE();
+
+ switch (srcclk)
+ {
+ case RCC_CLK48CLKSOURCE_PLL1: /* PLL1Q */
+
+ HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+ frequency = pll1_clocks.PLL1_Q_Frequency;
+ break;
+
+ case RCC_CLK48CLKSOURCE_PLL2: /* PLL2Q */
+
+ HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ frequency = pll2_clocks.PLL2_Q_Frequency;
+ break;
+
+ case RCC_CLK48CLKSOURCE_HSI48: /* HSI48 */
+
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY))
+ {
+ frequency = HSI48_VALUE;
+ }
+ else
+ {
+ frequency = 0U;
+ }
+ break;
+
+ case RCC_CLK48CLKSOURCE_MSIK: /* MSIK frequency range in HZ */
+
+ frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
+ break;
+
+ default :
+
+ frequency = 0U;
+ break;
+
+ }
+ break;
+
+ case RCC_PERIPHCLK_SDMMC:
+ srcclk = __HAL_RCC_GET_SDMMC_SOURCE();
+ if (srcclk == RCC_SDMMCCLKSOURCE_CLK48)
+ {
+ srcclk = __HAL_RCC_GET_CLK48_SOURCE();
+
+ switch (srcclk)
+ {
+ case RCC_CLK48CLKSOURCE_PLL1: /* PLL1Q */
+ {
+ HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+ frequency = pll1_clocks.PLL1_Q_Frequency;
+ break;
+ }
+ case RCC_CLK48CLKSOURCE_PLL2: /* PLL2Q */
+ {
+ HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ frequency = pll2_clocks.PLL2_Q_Frequency;
+ break;
+ }
+ case RCC_CLK48CLKSOURCE_HSI48: /* HSI48 */
+ {
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY))
+ {
+ frequency = HSI48_VALUE;
+ }
+ else
+ {
+ frequency = 0U;
+ }
+ break;
+ }
+ case RCC_CLK48CLKSOURCE_MSIK: /* MSIK frequency range in HZ */
+ {
+ frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
+ break;
+ }
+ default :
+ {
+ frequency = 0U;
+ break;
+ }
+ }
+ break;
+ }
+ else if (srcclk == RCC_SDMMCCLKSOURCE_PLL1)
+ {
+ HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+ frequency = pll1_clocks.PLL1_P_Frequency;
+ }
+ else
+ {
+ frequency = 0U;
+ }
+ break;
+
+ case RCC_PERIPHCLK_USART1:
+ /* Get the current USART1 source */
+ srcclk = __HAL_RCC_GET_USART1_SOURCE();
+
+ if (srcclk == RCC_USART1CLKSOURCE_PCLK2)
+ {
+ frequency = HAL_RCC_GetPCLK2Freq();
+ }
+ else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART1CLKSOURCE_HSI))
+ {
+ frequency = HSI_VALUE;
+ }
+ else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART1CLKSOURCE_LSE))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for USART1 */
+ else
+ {
+ frequency = 0U;
+ }
+ break;
+
+ case RCC_PERIPHCLK_USART2:
+ /* Get the current USART2 source */
+ srcclk = __HAL_RCC_GET_USART2_SOURCE();
+
+ if (srcclk == RCC_USART2CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART2CLKSOURCE_HSI))
+ {
+ frequency = HSI_VALUE;
+ }
+ else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART2CLKSOURCE_LSE))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for USART2 */
+ else
+ {
+ frequency = 0U;
+ }
+ break;
+
+ case RCC_PERIPHCLK_USART3:
+ /* Get the current USART3 source */
+ srcclk = __HAL_RCC_GET_USART3_SOURCE();
+
+ if (srcclk == RCC_USART3CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART3CLKSOURCE_HSI))
+ {
+ frequency = HSI_VALUE;
+ }
+ else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART3CLKSOURCE_LSE))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for USART3 */
+ else
+ {
+ frequency = 0U;
+ }
+ break;
+
+ case RCC_PERIPHCLK_UART4:
+ /* Get the current UART4 source */
+ srcclk = __HAL_RCC_GET_UART4_SOURCE();
+
+ if (srcclk == RCC_UART4CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ else if (srcclk == RCC_UART4CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART4CLKSOURCE_HSI))
+ {
+ frequency = HSI_VALUE;
+ }
+ else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART4CLKSOURCE_LSE))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for UART4 */
+ else
+ {
+ frequency = 0U;
+ }
+ break;
+
+ case RCC_PERIPHCLK_UART5:
+ /* Get the current UART5 source */
+ srcclk = __HAL_RCC_GET_UART5_SOURCE();
+
+ if (srcclk == RCC_UART5CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ else if (srcclk == RCC_UART5CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART5CLKSOURCE_HSI))
+ {
+ frequency = HSI_VALUE;
+ }
+ else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART5CLKSOURCE_LSE))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for UART5 */
+ else
+ {
+ frequency = 0U;
+ }
+ break;
+
+ case RCC_PERIPHCLK_LPUART1:
+ /* Get the current LPUART1 source */
+ srcclk = __HAL_RCC_GET_LPUART1_SOURCE();
+
+ if (srcclk == RCC_LPUART1CLKSOURCE_PCLK3)
+ {
+ frequency = HAL_RCC_GetPCLK3Freq();
+ }
+ else if (srcclk == RCC_LPUART1CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_HSI))
+ {
+ frequency = HSI_VALUE;
+ }
+ else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPUART1CLKSOURCE_LSE))
+ {
+ frequency = LSE_VALUE;
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_MSIK))
+ {
+ frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
+ }
+ /* Clock not enabled for LPUART1 */
+ else
+ {
+ frequency = 0U;
+ }
+ break;
+
+ case RCC_PERIPHCLK_ADCDAC:
+
+ srcclk = __HAL_RCC_GET_ADCDAC_SOURCE();
+
+ if (srcclk == RCC_ADCDACCLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ else if (srcclk == RCC_ADCDACCLKSOURCE_PLL2)
+ {
+ HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ frequency = pll2_clocks.PLL2_R_Frequency;
+ }
+ else if (srcclk == RCC_ADCDACCLKSOURCE_HCLK)
+ {
+ frequency = HAL_RCC_GetHCLKFreq();
+ break;
+ }
+ else if (srcclk == RCC_ADCDACCLKSOURCE_MSIK)
+ {
+ frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)];
+ break;
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_ADCDACCLKSOURCE_HSE))
+ {
+ frequency = HSE_VALUE;
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_ADCDACCLKSOURCE_HSI))
+ {
+ frequency = HSI_VALUE;
+ }
+ /* Clock not enabled for ADC */
+ else
+ {
+ frequency = 0U;
+ }
+ break;
+
+ case RCC_PERIPHCLK_MDF1:
+ /* Get the current MDF1 source */
+ srcclk = __HAL_RCC_GET_MDF1_SOURCE();
+
+ switch (srcclk)
+ {
+ case RCC_MDF1CLKSOURCE_PLL1:
+
+ HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+ frequency = pll1_clocks.PLL1_P_Frequency;
+ break;
+
+ case RCC_MDF1CLKSOURCE_PLL3:
+
+ HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+ frequency = pll3_clocks.PLL3_Q_Frequency;
+ break;
+
+ case RCC_MDF1CLKSOURCE_HCLK:
+
+ frequency = HAL_RCC_GetHCLKFreq();
+ break;
+
+ case RCC_MDF1CLKSOURCE_PIN:
+
+ frequency = EXTERNAL_SAI1_CLOCK_VALUE;
+ break;
+
+ case RCC_MDF1CLKSOURCE_MSIK:
+
+ frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
+ break;
+
+ default:
+
+ frequency = 0U;
+ break;
+
+ }
+ break;
+
+ case RCC_PERIPHCLK_ADF1:
+ /* Get the current ADF1 source */
+ srcclk = __HAL_RCC_GET_ADF1_SOURCE();
+
+ switch (srcclk)
+ {
+ case RCC_ADF1CLKSOURCE_PLL1:
+
+ HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+ frequency = pll1_clocks.PLL1_P_Frequency;
+ break;
+
+ case RCC_ADF1CLKSOURCE_PLL3:
+
+ HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+ frequency = pll3_clocks.PLL3_Q_Frequency;
+ break;
+
+ case RCC_ADF1CLKSOURCE_HCLK:
+
+ frequency = HAL_RCC_GetHCLKFreq();
+ break;
+
+ case RCC_ADF1CLKSOURCE_PIN:
+
+ frequency = EXTERNAL_SAI1_CLOCK_VALUE;
+ break;
+
+ case RCC_ADF1CLKSOURCE_MSIK:
+
+ frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
+ break;
+
+ default:
+
+ frequency = 0U;
+ break;
+ }
+ break;
+
+ case RCC_PERIPHCLK_I2C1:
+ /* Get the current I2C1 source */
+ srcclk = __HAL_RCC_GET_I2C1_SOURCE();
+
+ if (srcclk == RCC_I2C1CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C1CLKSOURCE_HSI))
+ {
+ frequency = HSI_VALUE;
+ }
+ /* Clock not enabled for I2C1 */
+ else
+ {
+ frequency = 0U;
+ }
+ break;
+
+ case RCC_PERIPHCLK_I2C2:
+ /* Get the current I2C2 source */
+ srcclk = __HAL_RCC_GET_I2C2_SOURCE();
+
+ if (srcclk == RCC_I2C2CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ else if (srcclk == RCC_I2C2CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C2CLKSOURCE_HSI))
+ {
+ frequency = HSI_VALUE;
+ }
+ /* Clock not enabled for I2C2 */
+ else
+ {
+ frequency = 0U;
+ }
+ break;
+
+ case RCC_PERIPHCLK_I2C3:
+ /* Get the current I2C3 source */
+ srcclk = __HAL_RCC_GET_I2C3_SOURCE();
+
+ switch (srcclk)
+ {
+ case RCC_I2C3CLKSOURCE_PCLK3:
+ {
+ frequency = HAL_RCC_GetPCLK3Freq();
+ break;
+ }
+ case RCC_I2C3CLKSOURCE_HSI:
+ {
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
+ {
+ frequency = HSI_VALUE;
+ }
+ else
+ {
+ frequency = 0U;
+ }
+ break;
+ }
+ case RCC_I2C3CLKSOURCE_SYSCLK:
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ break;
+ }
+ case RCC_I2C3CLKSOURCE_MSIK:
+ {
+ frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)];
+ break;
+ }
+ default:
+ {
+ frequency = 0U;
+ break;
+ }
+ }
+ break;
+
+ case RCC_PERIPHCLK_I2C4:
+ /* Get the current I2C4 source */
+ srcclk = __HAL_RCC_GET_I2C4_SOURCE();
+
+ if (srcclk == RCC_I2C4CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ else if (srcclk == RCC_I2C4CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C4CLKSOURCE_HSI))
+ {
+ frequency = HSI_VALUE;
+ }
+ /* Clock not enabled for I2C4 */
+ else
+ {
+ frequency = 0U;
+ }
+ break;
+
+ case RCC_PERIPHCLK_LPTIM34:
+ /* Get the current LPTIM34 source */
+ srcclk = __HAL_RCC_GET_LPTIM34_SOURCE();
+
+ if (srcclk == RCC_LPTIM34CLKSOURCE_MSIK)
+ {
+ frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
+ }
+ else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_LPTIM34CLKSOURCE_LSI))
+ {
+ frequency = LSI_VALUE;
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM34CLKSOURCE_HSI))
+ {
+ frequency = HSI_VALUE;
+ }
+ else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM34CLKSOURCE_LSE))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for LPTIM34 */
+ else
+ {
+ frequency = 0U;
+ }
+ break;
+
+ case RCC_PERIPHCLK_LPTIM1:
+ /* Get the current LPTIM1 source */
+ srcclk = __HAL_RCC_GET_LPTIM1_SOURCE();
+
+ if (srcclk == RCC_LPTIM1CLKSOURCE_MSIK)
+ {
+ frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
+ }
+ else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSI))
+ {
+ frequency = LSI_VALUE;
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_HSI))
+ {
+ frequency = HSI_VALUE;
+ }
+ else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSE))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for LPTIM1 */
+ else
+ {
+ frequency = 0U;
+ }
+ break;
+
+ case RCC_PERIPHCLK_LPTIM2:
+ /* Get the current LPTIM2 source */
+ srcclk = __HAL_RCC_GET_LPTIM2_SOURCE();
+
+ if (srcclk == RCC_LPTIM2CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_LSI))
+ {
+ frequency = LSI_VALUE;
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_HSI))
+ {
+ frequency = HSI_VALUE;
+ }
+ else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_LSE))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for LPTIM2 */
+ else
+ {
+ frequency = 0U;
+ }
+ break;
+
+ case RCC_PERIPHCLK_FDCAN1:
+ /* Get the current FDCAN1 kernel source */
+ srcclk = __HAL_RCC_GET_FDCAN1_SOURCE();
+
+ if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_FDCAN1CLKSOURCE_HSE))
+ {
+ frequency = HSE_VALUE;
+ }
+ else if (srcclk == RCC_FDCAN1CLKSOURCE_PLL1) /* PLL1 ? */
+ {
+ HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+ frequency = pll1_clocks.PLL1_Q_Frequency;
+ }
+ else if (srcclk == RCC_FDCAN1CLKSOURCE_PLL2) /* PLL2 ? */
+ {
+ HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ frequency = pll2_clocks.PLL2_P_Frequency;
+ }
+ /* Clock not enabled for FDCAN1 */
+ else
+ {
+ frequency = 0U;
+ }
+ break;
+
+ case RCC_PERIPHCLK_SPI1:
+ /* Get the current SPI1 kernel source */
+ srcclk = __HAL_RCC_GET_SPI1_SOURCE();
+ switch (srcclk)
+ {
+ case RCC_SPI1CLKSOURCE_PCLK2:
+
+ frequency = HAL_RCC_GetPCLK2Freq();
+ break;
+
+ case RCC_SPI1CLKSOURCE_SYSCLK:
+
+ frequency = HAL_RCC_GetSysClockFreq();
+ break;
+
+ case RCC_SPI1CLKSOURCE_HSI:
+
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
+ {
+ frequency = HSI_VALUE;
+ }
+ else
+ {
+ frequency = 0U;
+ }
+ break;
+
+ case RCC_SPI1CLKSOURCE_MSIK:
+
+ frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
+ break;
+
+ default:
+
+ frequency = 0U;
+ break;
+
+ }
+ break;
+
+ case RCC_PERIPHCLK_SPI2:
+ /* Get the current SPI2 kernel source */
+ srcclk = __HAL_RCC_GET_SPI2_SOURCE();
+ switch (srcclk)
+ {
+ case RCC_SPI2CLKSOURCE_PCLK1:
+
+ frequency = HAL_RCC_GetPCLK1Freq();
+ break;
+
+ case RCC_SPI2CLKSOURCE_SYSCLK:
+
+ frequency = HAL_RCC_GetSysClockFreq();
+ break;
+
+ case RCC_SPI2CLKSOURCE_HSI:
+
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
+ {
+ frequency = HSI_VALUE;
+ }
+ else
+ {
+ frequency = 0U;
+ }
+ break;
+
+ case RCC_SPI2CLKSOURCE_MSIK:
+
+ frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
+ break;
+
+ default:
+
+ frequency = 0U;
+ break;
+
+ }
+ break;
+
+ case RCC_PERIPHCLK_SPI3:
+ /* Get the current SPI3 kernel source */
+ srcclk = __HAL_RCC_GET_SPI3_SOURCE();
+ switch (srcclk)
+ {
+ case RCC_SPI3CLKSOURCE_PCLK3:
+
+ frequency = HAL_RCC_GetPCLK3Freq();
+ break;
+
+ case RCC_SPI3CLKSOURCE_SYSCLK:
+
+ frequency = HAL_RCC_GetSysClockFreq();
+ break;
+
+ case RCC_SPI3CLKSOURCE_HSI:
+
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
+ {
+ frequency = HSI_VALUE;
+ }
+ else
+ {
+ frequency = 0U;
+ }
+ break;
+
+ case RCC_SPI3CLKSOURCE_MSIK:
+
+ frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
+ break;
+
+ default:
+
+ frequency = 0U;
+ break;
+ }
+ break;
+
+ case RCC_PERIPHCLK_OSPI:
+ /* Get the current OSPI kernel source */
+ srcclk = __HAL_RCC_GET_OSPI_SOURCE();
+
+ switch (srcclk)
+ {
+ case RCC_OSPICLKSOURCE_PLL2:
+
+ HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ frequency = pll2_clocks.PLL2_Q_Frequency;
+ break;
+
+ case RCC_OSPICLKSOURCE_PLL1:
+
+ HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+ frequency = pll1_clocks.PLL1_Q_Frequency;
+ break;
+
+ case RCC_OSPICLKSOURCE_SYSCLK:
+
+ frequency = HAL_RCC_GetSysClockFreq();
+ break;
+
+ case RCC_OSPICLKSOURCE_MSIK:
+
+ frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
+ break;
+
+ default:
+
+ frequency = 0U;
+ break;
+ }
+ break;
+
+ case RCC_PERIPHCLK_DAC1:
+ /* Get the current DAC1 kernel source */
+ srcclk = __HAL_RCC_GET_DAC1_SOURCE();
+ /* Check if LSE is ready and if DAC1 clock selection is LSE */
+ if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_DAC1CLKSOURCE_LSE))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Check if LSI is ready and if DAC1 clock selection is LSI */
+ else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_DAC1CLKSOURCE_LSI))
+ {
+ frequency = LSI_VALUE;
+ }
+ /* Clock not enabled for DAC1*/
+ else
+ {
+ frequency = 0U;
+ }
+ break;
+
+ default:
+ frequency = 0U;
+ break;
+ }
+ }
+ return (frequency);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions
+ * @brief Extended Clock management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended clock management functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the
+ activation or deactivation of MSI PLL-mode, PLL2, PLL3, LSE CSS,
+ Low speed clock output and clock after wake-up from STOP mode.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable PLL2.
+ * @param PLL2Init pointer to an RCC_PLL2InitTypeDef structure that
+ * contains the configuration information for the PLL2
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init)
+{
+ uint32_t tickstart;
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* check for PLL2 Parameters used to output PLL2CLK */
+ assert_param(IS_RCC_PLLSOURCE(PLL2Init->PLL2Source));
+ assert_param(IS_RCC_PLLM_VALUE(PLL2Init->PLL2M));
+ assert_param(IS_RCC_PLLN_VALUE(PLL2Init->PLL2N));
+ assert_param(IS_RCC_PLLP_VALUE(PLL2Init->PLL2P));
+ assert_param(IS_RCC_PLLQ_VALUE(PLL2Init->PLL2Q));
+ assert_param(IS_RCC_PLLR_VALUE(PLL2Init->PLL2R));
+ assert_param(IS_RCC_PLL2CLOCKOUT_VALUE(PLL2Init->PLL2ClockOut));
+
+ /* Disable the PLL2 */
+ __HAL_RCC_PLL2_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL2 is ready to be updated */
+ while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
+ {
+ status = HAL_TIMEOUT;
+ break;
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Make sure PLL2Source is ready */
+ status = RCCEx_PLLSource_Enable(PLL2Init->PLL2Source);
+
+ if (status == HAL_OK)
+ {
+ /* Configure the PLL2 clock source, multiplication factor N, */
+ /* and division factors M, P, Q and R */
+ __HAL_RCC_PLL2_CONFIG(PLL2Init->PLL2Source, PLL2Init->PLL2M, PLL2Init->PLL2N,
+ PLL2Init->PLL2P, PLL2Init->PLL2Q, PLL2Init->PLL2R);
+
+ /* Disable PLL2FRACN */
+ __HAL_RCC_PLL2FRACN_DISABLE();
+
+ /* Configure PLL PLL2FRACN */
+ __HAL_RCC_PLL2FRACN_CONFIG(PLL2Init->PLL2FRACN);
+
+ /* Enable PLL2FRACN */
+ __HAL_RCC_PLL2FRACN_ENABLE();
+
+ /* Select PLL2 input reference frequency range: VCI */
+ __HAL_RCC_PLL2_VCIRANGE(PLL2Init->PLL2RGE);
+
+ /* Configure the PLL2 Clock output(s) */
+ __HAL_RCC_PLL2CLKOUT_ENABLE(PLL2Init->PLL2ClockOut);
+
+ /* Enable the PLL2 again by setting PLL2ON to 1*/
+ __HAL_RCC_PLL2_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL2 is ready */
+ while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
+ {
+ status = HAL_TIMEOUT;
+ break;
+ }
+ }
+ }
+ }
+ return status;
+}
+
+/**
+ * @brief Disable PLL2.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void)
+{
+ uint32_t tickstart;
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Disable the PLL2 */
+ __HAL_RCC_PLL2_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL2 is ready */
+ while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
+ {
+ status = HAL_TIMEOUT;
+ break;
+ }
+ }
+
+ /* To save power disable the PLL2 Source, FRACN and Clock outputs */
+ CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN | RCC_PLL2CFGR_PLL2QEN | RCC_PLL2CFGR_PLL2REN | RCC_PLL2CFGR_PLL2SRC | \
+ RCC_PLL2CFGR_PLL2FRACEN);
+
+ return status;
+}
+
+/**
+ * @brief Enable PLL3.
+ * @param PLL3Init pointer to an RCC_PLL3InitTypeDef structure that
+ * contains the configuration information for the PLL3
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_EnablePLL3(RCC_PLL3InitTypeDef *PLL3Init)
+{
+ uint32_t tickstart;
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* check for PLL3 Parameters used to output PLL3CLK */
+ assert_param(IS_RCC_PLLSOURCE(PLL3Init->PLL3Source));
+ assert_param(IS_RCC_PLLM_VALUE(PLL3Init->PLL3M));
+ assert_param(IS_RCC_PLLN_VALUE(PLL3Init->PLL3N));
+ assert_param(IS_RCC_PLLP_VALUE(PLL3Init->PLL3P));
+ assert_param(IS_RCC_PLL3CLOCKOUT_VALUE(PLL3Init->PLL3ClockOut));
+
+ /* Disable the PLL3 */
+ __HAL_RCC_PLL3_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL3 is ready to be updated */
+ while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
+ {
+ status = HAL_TIMEOUT;
+ break;
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Make sure PLL3Source is ready */
+ status = RCCEx_PLLSource_Enable(PLL3Init->PLL3Source);
+
+ if (status == HAL_OK)
+ {
+ /* Configure the PLL3 clock source, multiplication factor N, */
+ /* and division factors M and P */
+ __HAL_RCC_PLL3_CONFIG(PLL3Init->PLL3Source, PLL3Init->PLL3M, PLL3Init->PLL3N, PLL3Init->PLL3P, PLL3Init->PLL3Q, \
+ PLL3Init->PLL3R);
+
+ /* Disable PLL3FRACN . */
+ __HAL_RCC_PLL3FRACN_DISABLE();
+
+ /* Configure PLL PLL3FRACN */
+ __HAL_RCC_PLL3FRACN_CONFIG(PLL3Init->PLL3FRACN);
+
+ /* Enable PLL3FRACN . */
+ __HAL_RCC_PLL3FRACN_ENABLE();
+
+ /* Select PLL3 input reference frequency range: VCI */
+ __HAL_RCC_PLL3_VCIRANGE(PLL3Init->PLL3RGE);
+
+ /* Configure the PLL3 Clock output(s) */
+ __HAL_RCC_PLL3CLKOUT_ENABLE(PLL3Init->PLL3ClockOut);
+
+ /* Enable the PLL3 again by setting PLL3ON to 1*/
+ __HAL_RCC_PLL3_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL3 is ready */
+ while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
+ {
+ status = HAL_TIMEOUT;
+ break;
+ }
+ }
+ }
+ }
+ return status;
+}
+
+/**
+ * @brief Disable PLL3.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_DisablePLL3(void)
+{
+ uint32_t tickstart;
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Disable the PLL3 */
+ __HAL_RCC_PLL3_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL3 is ready */
+ while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
+ {
+ status = HAL_TIMEOUT;
+ break;
+ }
+ }
+
+ /* To save power disable the PLL3 Source and Clock outputs */
+ CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN | RCC_PLL3CFGR_PLL3QEN | RCC_PLL3CFGR_PLL3REN | RCC_PLL3CFGR_PLL3SRC | \
+ RCC_PLL3CFGR_PLL3FRACEN);
+
+ return status;
+}
+
+/**
+ * @brief Select which MSI output clock uses the PLL mode.
+ * @note Prior to disable PLL-mode (MSIPLLEN = 0) before call HAL_RCCEx_EnableMSIPLLModeSelection.
+ * @note The MSI kernel clock output uses the same oscillator source than the MSI system
+ * clock output, then the PLL mode is applied to the both clocks outputs.
+ * @param MSIPLLModeSelection specifies which MSI output clock uses the PLL mode.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MSISPLL_MODE_SEL PLL mode applied to MSIS (MSI system) clock output
+ * @arg @ref RCC_MSIKPLL_MODE_SEL PLL mode applied to MSIK (MSI kernel) clock output
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_EnableMSIPLLModeSelection(uint32_t MSIPLLModeSelection)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ assert_param(IS_RCC_MSIPLLMODE_SELECT(MSIPLLModeSelection));
+ if (READ_BIT(RCC->CR, RCC_CR_MSIPLLEN) == 0U)
+ {
+ /* This bit is used only if PLL mode is disabled (MSIPLLEN = 0) */
+ if (MSIPLLModeSelection == RCC_MSISPLL_MODE_SEL)
+ {
+ SET_BIT(RCC->CR, RCC_CR_MSIPLLSEL);
+ }
+ else
+ {
+ CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLSEL);
+ }
+ status = HAL_OK;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Enable the fast PLL mode start-up of the MSI clock
+ * @note Prior to enable PLL-mode (MSIPLLEN = 1) before call HAL_RCCEx_EnableMSIPLLFastStartup.
+ * @note The fast start-up feature is not active the first time the PLL mode is selected. The
+ * fast start-up is active when the MSI in PLL mode returns from switch off.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_EnableMSIPLLFastStartup(void)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ if (READ_BIT(RCC->CR, RCC_CR_MSIPLLEN) == RCC_CR_MSIPLLEN)
+ {
+ /* This bit is used only if PLL mode is selected (MSIPLLEN = 1) */
+ SET_BIT(RCC->CR, RCC_CR_MSIPLLFAST);
+ status = HAL_OK;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Disable the fast PLL mode start-up of the MSI clock
+ * @note the MSI fast startup mode disabled only when PLL-mode is enabled
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_DisableMSIPLLFastStartup(void)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ if (READ_BIT(RCC->CR, RCC_CR_MSIPLLEN) == RCC_CR_MSIPLLEN)
+ {
+ /* This bit is used only if PLL mode is selected (MSIPLLEN = 1) */
+ CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLFAST);
+ status = HAL_OK;
+ }
+ return status;
+}
+
+/**
+ * @brief Configure the oscillator clock source for wakeup from Stop and CSS backup clock.
+ * @param WakeUpClk Wakeup clock
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI oscillator selection
+ * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI oscillator selection
+ * @note This function shall not be called after the Clock Security System on HSE has been
+ * enabled.
+ * @retval None
+ */
+void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)
+{
+ assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk));
+
+ __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk);
+}
+
+/**
+ * @brief Configure the oscillator Kernel clock source for wakeup from Stop
+ * @param WakeUpClk: Kernel Wakeup clock
+ * This parameter can be one of the following values:
+ * @arg RCC_STOP_KERWAKEUPCLOCK_MSI: MSI oscillator selection
+ * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI oscillator selection
+ * @retval None
+ */
+void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk)
+{
+ assert_param(IS_RCC_STOP_KERWAKEUPCLOCK(WakeUpClk));
+
+ __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(WakeUpClk);
+}
+
+/**
+ * @brief Configure the MSI range after standby mode.
+ * @note After Standby its frequency can be selected between 3 possible values (1, 3.072 or 4 MHz).
+ * @param MSIRange MSI range
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MSIRANGE_4 Range 4 around 4 MHz (reset value)
+ * @arg @ref RCC_MSIRANGE_5 Range 5 around 2 MHz
+ * @arg @ref RCC_MSIRANGE_6 Range 6 around 1.5 MHz
+ * @arg @ref RCC_MSIRANGE_7 Range 7 around 1 MHz
+ * @arg @ref RCC_MSIRANGE_8 Range 8 around 3.072 MHz
+ * @retval None
+ */
+void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange)
+{
+ assert_param(IS_RCC_MSI_STANDBY_CLOCK_RANGE(MSIRange));
+
+ __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(MSIRange);
+}
+
+/**
+ * @brief Enable the LSE Clock Security System.
+ * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled
+ * with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC
+ * clock with HAL_RCCEx_PeriphCLKConfig().
+ * @retval None
+ */
+void HAL_RCCEx_EnableLSECSS(void)
+{
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
+}
+
+/**
+ * @brief Disable the LSE Clock Security System.
+ * @note LSE Clock Security System can only be disabled after a LSE failure detection.
+ * @retval None
+ */
+void HAL_RCCEx_DisableLSECSS(void)
+{
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
+}
+
+/**
+ * @brief Handle the RCC LSE Clock Security System interrupt request.
+ * @retval None
+ */
+void HAL_RCCEx_LSECSS_IRQHandler(void)
+{
+ if (READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) != 0U)
+ {
+ /* RCC LSE Clock Security System interrupt user callback */
+ HAL_RCCEx_LSECSS_Callback();
+ }
+}
+
+/**
+ * @brief RCCEx LSE Clock Security System interrupt callback.
+ * @retval none
+ */
+__weak void HAL_RCCEx_LSECSS_Callback(void)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
+ */
+}
+
+/**
+ * @brief Select the Low Speed clock source to output on LSCO pin (PA2).
+ * @param LSCOSource specifies the Low Speed clock source to output.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_LSCOSOURCE_LSI LSI clock selected as LSCO source
+ * @arg @ref RCC_LSCOSOURCE_LSE LSE clock selected as LSCO source
+ * @retval None
+ */
+void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)
+{
+ GPIO_InitTypeDef gpio_initstruct;
+ FlagStatus pwrclkchanged = RESET;
+ FlagStatus backupchanged = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_LSCOSOURCE(LSCOSource));
+
+ /* LSCO Pin Clock Enable */
+ LSCO_CLK_ENABLE();
+
+ /* Configure the LSCO pin in analog mode */
+ gpio_initstruct.Pin = LSCO_PIN;
+ gpio_initstruct.Mode = GPIO_MODE_ANALOG;
+ gpio_initstruct.Speed = GPIO_SPEED_FREQ_HIGH;
+ gpio_initstruct.Pull = GPIO_NOPULL;
+ HAL_GPIO_Init(LSCO_GPIO_PORT, &gpio_initstruct);
+
+ /* Update LSCOSEL clock source in Backup Domain control register */
+ if (__HAL_RCC_PWR_IS_CLK_DISABLED())
+ {
+ __HAL_RCC_PWR_CLK_ENABLE();
+ pwrclkchanged = SET;
+ }
+ if (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP))
+ {
+ HAL_PWR_EnableBkUpAccess();
+ backupchanged = SET;
+ }
+
+ MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN);
+
+ if (backupchanged == SET)
+ {
+ HAL_PWR_DisableBkUpAccess();
+ }
+ if (pwrclkchanged == SET)
+ {
+ __HAL_RCC_PWR_CLK_DISABLE();
+ }
+}
+
+/**
+ * @brief Disable the Low Speed clock output.
+ * @retval None
+ */
+void HAL_RCCEx_DisableLSCO(void)
+{
+ FlagStatus pwrclkchanged = RESET;
+ FlagStatus backupchanged = RESET;
+
+ /* Update LSCOEN bit in Backup Domain control register */
+ if (__HAL_RCC_PWR_IS_CLK_DISABLED())
+ {
+ __HAL_RCC_PWR_CLK_ENABLE();
+ pwrclkchanged = SET;
+ }
+ if (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP))
+ {
+ /* Enable access to the backup domain */
+ HAL_PWR_EnableBkUpAccess();
+ backupchanged = SET;
+ }
+
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
+
+ /* Restore previous configuration */
+ if (backupchanged == SET)
+ {
+ /* Disable access to the backup domain */
+ HAL_PWR_DisableBkUpAccess();
+ }
+ if (pwrclkchanged == SET)
+ {
+ __HAL_RCC_PWR_CLK_DISABLE();
+ }
+}
+
+/**
+ * @brief Enable the PLL-mode of the MSI.
+ * @note Prior to enable the PLL-mode of the MSI for automatic hardware
+ * calibration LSE oscillator is to be enabled with HAL_RCC_OscConfig().
+ * @retval None
+ */
+void HAL_RCCEx_EnableMSIPLLMode(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_MSIPLLEN);
+}
+
+/**
+ * @brief Disable the PLL-mode of the MSI.
+ * @note PLL-mode of the MSI is automatically reset when LSE oscillator is disabled.
+ * @retval None
+ */
+void HAL_RCCEx_DisableMSIPLLMode(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN);
+}
+
+/**
+ * @}
+ */
+
+#if defined(CRS)
+
+/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions
+ * @brief Extended Clock Recovery System Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended Clock Recovery System Control functions #####
+ ===============================================================================
+ [..]
+ For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows:
+
+ (#) In System clock config, HSI48 needs to be enabled
+
+ (#) Enable CRS clock in IP MSP init which will use CRS functions
+
+ (#) Call CRS functions as follows:
+ (##) Prepare synchronization configuration necessary for HSI48 calibration
+ (+++) Default values can be set for frequency Error Measurement (reload and error limit)
+ and also HSI48 oscillator smooth trimming.
+ (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
+ directly reload value with target and sychronization frequencies values
+ (##) Call function HAL_RCCEx_CRSConfig which
+ (+++) Resets CRS registers to their default values.
+ (+++) Configures CRS registers with synchronization configuration
+ (+++) Enables automatic calibration and frequency error counter feature
+ Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
+ periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
+ provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock
+ precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
+ should be used as SYNC signal.
+
+ (##) A polling function is provided to wait for complete synchronization
+ (+++) Call function HAL_RCCEx_CRSWaitSynchronization()
+ (+++) According to CRS status, user can decide to adjust again the calibration or continue
+ application if synchronization is OK
+
+ (#) User can retrieve information related to synchronization in calling function
+ HAL_RCCEx_CRSGetSynchronizationInfo()
+
+ (#) Regarding synchronization status and synchronization information, user can try a new calibration
+ in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
+ Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value),
+ it means that the actual frequency is lower than the target (and so, that the TRIM value should be
+ incremented), while when it is detected during the upcounting phase it means that the actual frequency
+ is higher (and that the TRIM value should be decremented).
+
+ (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go
+ through CRS Handler (CRS_IRQn/CRS_IRQHandler)
+ (++) Call function HAL_RCCEx_CRSConfig()
+ (++) Enable CRS_IRQn (thanks to NVIC functions)
+ (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT)
+ (++) Implement CRS status management in the following user callbacks called from
+ HAL_RCCEx_CRS_IRQHandler():
+ (+++) HAL_RCCEx_CRS_SyncOkCallback()
+ (+++) HAL_RCCEx_CRS_SyncWarnCallback()
+ (+++) HAL_RCCEx_CRS_ExpectedSyncCallback()
+ (+++) HAL_RCCEx_CRS_ErrorCallback()
+
+ (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate().
+ This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start automatic synchronization for polling mode
+ * @param pInit Pointer on RCC_CRSInitTypeDef structure
+ * @retval None
+ */
+void HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef *const pInit)
+{
+ uint32_t value;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
+ assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
+ assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
+ assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
+ assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
+ assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
+
+ /* CONFIGURATION */
+
+ /* Before configuration, reset CRS registers to their default values*/
+ __HAL_RCC_CRS_FORCE_RESET();
+ __HAL_RCC_CRS_RELEASE_RESET();
+
+ /* Set the SYNCDIV[2:0] bits according to Prescaler value */
+ /* Set the SYNCSRC[1:0] bits according to Source value */
+ /* Set the SYNCSPOL bit according to Polarity value */
+ value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
+ /* Set the RELOAD[15:0] bits according to ReloadValue value */
+ value |= pInit->ReloadValue;
+ /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
+ value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos);
+ WRITE_REG(CRS->CFGR, value);
+
+ /* Adjust HSI48 oscillator smooth trimming */
+ /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */
+ MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos));
+
+ /* START AUTOMATIC SYNCHRONIZATION*/
+
+ /* Enable Automatic trimming & Frequency error counter */
+ SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);
+}
+
+/**
+ * @brief Generate the software synchronization event
+ * @retval None
+ */
+void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
+{
+ SET_BIT(CRS->CR, CRS_CR_SWSYNC);
+}
+
+/**
+ * @brief Return synchronization info
+ * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
+ * @retval None
+ */
+void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
+{
+ /* Check the parameter */
+ assert_param(pSynchroInfo != (void *) NULL);
+
+ /* Get the reload value */
+ pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
+
+ /* Get HSI48 oscillator smooth trimming */
+ pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
+
+ /* Get Frequency error capture */
+ pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
+
+ /* Get Frequency error direction */
+ pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
+}
+
+/**
+ * @brief Wait for CRS Synchronization status.
+ * @param Timeout Duration of the timeout
+ * @note Timeout is based on the maximum time to receive a SYNC event based on synchronization
+ * frequency.
+ * @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
+ * @retval Combination of Synchronization status
+ * This parameter can be a combination of the following values:
+ * @arg @ref RCC_CRS_TIMEOUT
+ * @arg @ref RCC_CRS_SYNCOK
+ * @arg @ref RCC_CRS_SYNCWARN
+ * @arg @ref RCC_CRS_SYNCERR
+ * @arg @ref RCC_CRS_SYNCMISS
+ * @arg @ref RCC_CRS_TRIMOVF
+ */
+uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
+{
+ uint32_t crsstatus = RCC_CRS_NONE;
+ uint32_t tickstart;
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait for CRS flag or timeout detection */
+ do
+ {
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ crsstatus = RCC_CRS_TIMEOUT;
+ }
+ }
+ /* Check CRS SYNCOK flag */
+ if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
+ {
+ /* CRS SYNC event OK */
+ crsstatus |= RCC_CRS_SYNCOK;
+
+ /* Clear CRS SYNC event OK bit */
+ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
+ }
+
+ /* Check CRS SYNCWARN flag */
+ if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
+ {
+ /* CRS SYNC warning */
+ crsstatus |= RCC_CRS_SYNCWARN;
+
+ /* Clear CRS SYNCWARN bit */
+ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
+ }
+
+ /* Check CRS TRIM overflow flag */
+ if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
+ {
+ /* CRS SYNC Error */
+ crsstatus |= RCC_CRS_TRIMOVF;
+
+ /* Clear CRS Error bit */
+ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
+ }
+
+ /* Check CRS Error flag */
+ if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
+ {
+ /* CRS SYNC Error */
+ crsstatus |= RCC_CRS_SYNCERR;
+
+ /* Clear CRS Error bit */
+ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
+ }
+
+ /* Check CRS SYNC Missed flag */
+ if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
+ {
+ /* CRS SYNC Missed */
+ crsstatus |= RCC_CRS_SYNCMISS;
+
+ /* Clear CRS SYNC Missed bit */
+ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
+ }
+
+ /* Check CRS Expected SYNC flag */
+ if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
+ {
+ /* frequency error counter reached a zero value */
+ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
+ }
+ } while (RCC_CRS_NONE == crsstatus);
+
+ return crsstatus;
+}
+
+/**
+ * @brief Handle the Clock Recovery System interrupt request.
+ * @retval None
+ */
+void HAL_RCCEx_CRS_IRQHandler(void)
+{
+ uint32_t crserror = RCC_CRS_NONE;
+ /* Get current IT flags and IT sources values */
+ uint32_t itflags = READ_REG(CRS->ISR);
+ uint32_t itsources = READ_REG(CRS->CR);
+
+ /* Check CRS SYNCOK flag */
+ if (((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U))
+ {
+ /* Clear CRS SYNC event OK flag */
+ WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
+
+ /* user callback */
+ HAL_RCCEx_CRS_SyncOkCallback();
+ }
+ /* Check CRS SYNCWARN flag */
+ else if (((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U))
+ {
+ /* Clear CRS SYNCWARN flag */
+ WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
+
+ /* user callback */
+ HAL_RCCEx_CRS_SyncWarnCallback();
+ }
+ /* Check CRS Expected SYNC flag */
+ else if (((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U))
+ {
+ /* frequency error counter reached a zero value */
+ WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
+
+ /* user callback */
+ HAL_RCCEx_CRS_ExpectedSyncCallback();
+ }
+ /* Check CRS Error flags */
+ else
+ {
+ if (((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U))
+ {
+ if ((itflags & RCC_CRS_FLAG_SYNCERR) != 0U)
+ {
+ crserror |= RCC_CRS_SYNCERR;
+ }
+ if ((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U)
+ {
+ crserror |= RCC_CRS_SYNCMISS;
+ }
+ if ((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U)
+ {
+ crserror |= RCC_CRS_TRIMOVF;
+ }
+
+ /* Clear CRS Error flags */
+ WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
+
+ /* user error callback */
+ HAL_RCCEx_CRS_ErrorCallback(crserror);
+ }
+ }
+}
+
+/**
+ * @brief RCCEx Clock Recovery System SYNCOK interrupt callback.
+ * @retval none
+ */
+__weak void HAL_RCCEx_CRS_SyncOkCallback(void)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file
+ */
+}
+
+/**
+ * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback.
+ * @retval none
+ */
+__weak void HAL_RCCEx_CRS_SyncWarnCallback(void)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file
+ */
+}
+
+/**
+ * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback.
+ * @retval none
+ */
+__weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file
+ */
+}
+
+/**
+ * @brief RCCEx Clock Recovery System Error interrupt callback.
+ * @param Error Combination of Error status.
+ * This parameter can be a combination of the following values:
+ * @arg @ref RCC_CRS_SYNCERR
+ * @arg @ref RCC_CRS_SYNCMISS
+ * @arg @ref RCC_CRS_TRIMOVF
+ * @retval none
+ */
+__weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(Error);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+#endif /* CRS */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCCEx_Private_Functions
+ * @{
+ */
+/**
+ * @brief Configure the PLL 1 source clock.
+ * @param PllSource PLL1 source clock it can be :
+ * RCC_PLLSOURCE_NONE
+ * RCC_PLLSOURCE_MSI
+ * RCC_PLLSOURCE_HSI
+ * RCC_PLLSOURCE_HSE
+ *
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef RCCEx_PLLSource_Enable(uint32_t PllSource)
+{
+ uint32_t tickstart;
+ HAL_StatusTypeDef status = HAL_OK;
+
+ switch (PllSource)
+ {
+ case RCC_PLLSOURCE_MSI:
+ /* Check whether MSI in not ready and enable it */
+ if (READ_BIT(RCC->CR, RCC_CR_MSISRDY) == 0U)
+ {
+ /* Enable the Internal Multi Speed oscillator (MSI). */
+ __HAL_RCC_MSI_ENABLE();
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait till MSI is ready */
+ while (READ_BIT(RCC->CR, RCC_CR_MSISRDY) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
+ {
+ status = HAL_TIMEOUT;
+ break;
+ }
+ }
+ }
+ break;
+
+ case RCC_PLLSOURCE_HSI:
+ /* Check whether HSI in not ready and enable it */
+ if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
+ {
+ /* Enable the Internal High Speed oscillator (HSI) */
+ __HAL_RCC_HSI_ENABLE();
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait till MSI is ready */
+ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+ {
+ status = HAL_TIMEOUT;
+ break;
+ }
+ }
+ }
+ break;
+
+ case RCC_PLLSOURCE_HSE:
+ /* Check whether HSE in not ready and enable it */
+ if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
+ {
+ /* Enable the External High Speed oscillator (HSE) */
+ SET_BIT(RCC->CR, RCC_CR_HSEON);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSE is ready */
+ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
+ {
+ status = HAL_TIMEOUT;
+ break;
+ }
+ }
+ }
+ break;
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Configure the PLL2 VCI ranges, multiplication and division factors and enable it
+ * @param pll2: Pointer to an RCC_PLL2InitTypeDef structure that
+ * contains the configuration parameters as well as VCI clock ranges.
+ * @note PLL2 is temporary disable to apply new parameters
+ *
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2)
+{
+
+ uint32_t tickstart;
+ assert_param(IS_RCC_PLLSOURCE(pll2->PLL2Source));
+ assert_param(IS_RCC_PLLM_VALUE(pll2->PLL2M));
+ assert_param(IS_RCC_PLLN_VALUE(pll2->PLL2N));
+ assert_param(IS_RCC_PLLP_VALUE(pll2->PLL2P));
+ assert_param(IS_RCC_PLLQ_VALUE(pll2->PLL2Q));
+ assert_param(IS_RCC_PLLR_VALUE(pll2->PLL2R));
+
+ /* Disable PLL2 */
+ __HAL_RCC_PLL2_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Configure PLL2 multiplication and division factors */
+ __HAL_RCC_PLL2_CONFIG(pll2->PLL2Source,
+ pll2->PLL2M,
+ pll2->PLL2N,
+ pll2->PLL2P,
+ pll2->PLL2Q,
+ pll2->PLL2R);
+
+ /* Select PLL2 input reference frequency range: VCI */
+ __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE);
+
+ /* Configure the PLL2 Clock output(s) */
+ __HAL_RCC_PLL2CLKOUT_ENABLE(pll2->PLL2ClockOut);
+
+ /* Disable PLL2FRACN */
+ __HAL_RCC_PLL2FRACN_DISABLE();
+
+ /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */
+ __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN);
+
+ /* Enable PLL2FRACN */
+ __HAL_RCC_PLL2FRACN_ENABLE();
+
+ /* Enable PLL2 */
+ __HAL_RCC_PLL2_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL2 is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ return HAL_OK;
+
+}
+
+/**
+ * @brief Configure the parameters N & P & optionally M of PLL3 and enable PLL3 output clock(s).
+ * @param pll3 pointer to an RCC_PLL3InitTypeDef structure that
+ * contains the configuration parameters N & P & optionally M as well as PLL3 output clock(s)
+ * @note PLL3 is temporary disable to apply new parameters
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3)
+{
+ uint32_t tickstart;
+ assert_param(IS_RCC_PLLSOURCE(pll3->PLL3Source));
+ assert_param(IS_RCC_PLLM_VALUE(pll3->PLL3M));
+ assert_param(IS_RCC_PLLN_VALUE(pll3->PLL3N));
+ assert_param(IS_RCC_PLLP_VALUE(pll3->PLL3P));
+ assert_param(IS_RCC_PLLQ_VALUE(pll3->PLL3Q));
+ assert_param(IS_RCC_PLLR_VALUE(pll3->PLL3R));
+
+ /* Disable PLL3 */
+ __HAL_RCC_PLL3_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Configure PLL3 multiplication and division factors */
+ __HAL_RCC_PLL3_CONFIG(pll3->PLL3Source,
+ pll3->PLL3M,
+ pll3->PLL3N,
+ pll3->PLL3P,
+ pll3->PLL3Q,
+ pll3->PLL3R);
+
+ /* Select PLL3 input reference frequency range: VCI */
+ __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE);
+
+ /* Configure the PLL3 Clock output(s) */
+ __HAL_RCC_PLL3CLKOUT_ENABLE(pll3->PLL3ClockOut);
+
+ /* Disable PLL3FRACN */
+ __HAL_RCC_PLL3FRACN_DISABLE();
+
+ /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */
+ __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN);
+
+ /* Enable PLL3FRACN */
+ __HAL_RCC_PLL3FRACN_ENABLE();
+
+ /* Enable PLL3 */
+ __HAL_RCC_PLL3_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL3 is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng.c
new file mode 100644
index 00000000..fb402fdb
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng.c
@@ -0,0 +1,1033 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_rng.c
+ * @author MCD Application Team
+ * @brief RNG HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Random Number Generator (RNG) peripheral:
+ * + Initialization and configuration functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The RNG HAL driver can be used as follows:
+
+ (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro
+ in HAL_RNG_MspInit().
+ (#) Activate the RNG peripheral using HAL_RNG_Init() function.
+ (#) Wait until the 32 bit Random Number Generator contains a valid
+ random data using (polling/interrupt) mode.
+ (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.
+
+ ##### Callback registration #####
+ ==================================
+
+ [..]
+ The compilation define USE_HAL_RNG_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ [..]
+ Use Function @ref HAL_RNG_RegisterCallback() to register a user callback.
+ Function @ref HAL_RNG_RegisterCallback() allows to register following callbacks:
+ (+) ErrorCallback : RNG Error Callback.
+ (+) MspInitCallback : RNG MspInit.
+ (+) MspDeInitCallback : RNG MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ [..]
+ Use function @ref HAL_RNG_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function.
+ @ref HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) ErrorCallback : RNG Error Callback.
+ (+) MspInitCallback : RNG MspInit.
+ (+) MspDeInitCallback : RNG MspDeInit.
+
+ [..]
+ For specific callback ReadyDataCallback, use dedicated register callbacks:
+ respectively @ref HAL_RNG_RegisterReadyDataCallback() , @ref HAL_RNG_UnRegisterReadyDataCallback().
+
+ [..]
+ By default, after the @ref HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET
+ all callbacks are set to the corresponding weak (surcharged) functions:
+ example @ref HAL_RNG_ErrorCallback().
+ Exception done for MspInit and MspDeInit functions that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_RNG_Init()
+ and @ref HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_RNG_Init() and @ref HAL_RNG_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+ [..]
+ Callbacks can be registered/unregistered in HAL_RNG_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_RNG_STATE_READY or HAL_RNG_STATE_RESET state, thus registered (user)
+ MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_RNG_RegisterCallback() before calling @ref HAL_RNG_DeInit()
+ or @ref HAL_RNG_Init() function.
+
+ [..]
+ When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available
+ and weak (surcharged) callbacks are used.
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+#if defined (RNG)
+
+/** @addtogroup RNG
+ * @brief RNG HAL module driver.
+ * @{
+ */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RNG_Private_Constants RNG Private Constants
+ * @{
+ */
+#define RNG_TIMEOUT_VALUE 4U
+/**
+ * @}
+ */
+/* Private macros ------------------------------------------------------------*/
+/* Private functions prototypes ----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup RNG_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RNG_Exported_Functions_Group1
+ * @brief Initialization and configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and configuration functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the RNG according to the specified parameters
+ in the RNG_InitTypeDef and create the associated handle
+ (+) DeInitialize the RNG peripheral
+ (+) Initialize the RNG MSP
+ (+) DeInitialize RNG MSP
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the RNG peripheral and creates the associated handle.
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
+{
+ uint32_t tickstart;
+ /* Check the RNG handle allocation */
+ if (hrng == NULL)
+ {
+ return HAL_ERROR;
+ }
+ /* Check the parameters */
+ assert_param(IS_RNG_ALL_INSTANCE(hrng->Instance));
+ assert_param(IS_RNG_CED(hrng->Init.ClockErrorDetection));
+
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+ if (hrng->State == HAL_RNG_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hrng->Lock = HAL_UNLOCKED;
+
+ hrng->ReadyDataCallback = HAL_RNG_ReadyDataCallback; /* Legacy weak ReadyDataCallback */
+ hrng->ErrorCallback = HAL_RNG_ErrorCallback; /* Legacy weak ErrorCallback */
+
+ if (hrng->MspInitCallback == NULL)
+ {
+ hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware */
+ hrng->MspInitCallback(hrng);
+ }
+#else
+ if (hrng->State == HAL_RNG_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hrng->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware */
+ HAL_RNG_MspInit(hrng);
+ }
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+
+ /* Change RNG peripheral state */
+ hrng->State = HAL_RNG_STATE_BUSY;
+
+ /* Disable RNG */
+ __HAL_RNG_DISABLE(hrng);
+
+ /* Clock Error Detection Configuration when CONDRT bit is set to 1 */
+ MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST, hrng->Init.ClockErrorDetection | RNG_CR_CONDRST);
+
+
+ /* Writing bit CONDRST=0 */
+ CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait for conditioning reset process to be completed */
+ while (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST))
+ {
+ if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
+ {
+ /* New check to avoid false timeout detection in case of preemption */
+ if (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST))
+ {
+ hrng->State = HAL_RNG_STATE_READY;
+ hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Enable the RNG Peripheral */
+ __HAL_RNG_ENABLE(hrng);
+
+ /* verify that no seed error */
+ if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
+ {
+ hrng->State = HAL_RNG_STATE_ERROR;
+ return HAL_ERROR;
+ }
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ /* Check if data register contains valid random data */
+ while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
+ {
+ /* New check to avoid false timeout detection in case of preemption */
+ if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET)
+ {
+ hrng->State = HAL_RNG_STATE_ERROR;
+ hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Initialize the RNG state */
+ hrng->State = HAL_RNG_STATE_READY;
+
+ /* Initialise the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_NONE;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the RNG peripheral.
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
+{
+ uint32_t tickstart;
+
+ /* Check the RNG handle allocation */
+ if (hrng == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Clear Clock Error Detection bit when CONDRT bit is set to 1 */
+ MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST, RNG_CED_ENABLE | RNG_CR_CONDRST);
+
+ /* Writing bit CONDRST=0 */
+ CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait for conditioning reset process to be completed */
+ while (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST))
+ {
+ if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
+ {
+ /* New check to avoid false timeout detection in case of preemption */
+ if (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST))
+ {
+ hrng->State = HAL_RNG_STATE_READY;
+ hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrng);
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Disable the RNG Peripheral */
+ CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN);
+
+ /* Clear RNG interrupt status flags */
+ CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS);
+
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+ if (hrng->MspDeInitCallback == NULL)
+ {
+ hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware */
+ hrng->MspDeInitCallback(hrng);
+#else
+ /* DeInit the low level hardware */
+ HAL_RNG_MspDeInit(hrng);
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+
+ /* Update the RNG state */
+ hrng->State = HAL_RNG_STATE_RESET;
+
+ /* Initialise the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_NONE;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hrng);
+
+ /* Return the function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the RNG MSP.
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
+ * @retval None
+ */
+__weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrng);
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_RNG_MspInit must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief DeInitializes the RNG MSP.
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
+ * @retval None
+ */
+__weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrng);
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_RNG_MspDeInit must be implemented in the user file.
+ */
+}
+
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User RNG Callback
+ * To be used instead of the weak predefined callback
+ * @param hrng RNG handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_RNG_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_RNG_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID,
+ pRNG_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hrng);
+
+ if (HAL_RNG_STATE_READY == hrng->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_RNG_ERROR_CB_ID :
+ hrng->ErrorCallback = pCallback;
+ break;
+
+ case HAL_RNG_MSPINIT_CB_ID :
+ hrng->MspInitCallback = pCallback;
+ break;
+
+ case HAL_RNG_MSPDEINIT_CB_ID :
+ hrng->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_RNG_STATE_RESET == hrng->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_RNG_MSPINIT_CB_ID :
+ hrng->MspInitCallback = pCallback;
+ break;
+
+ case HAL_RNG_MSPDEINIT_CB_ID :
+ hrng->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hrng);
+ return status;
+}
+
+/**
+ * @brief Unregister an RNG Callback
+ * RNG callabck is redirected to the weak predefined callback
+ * @param hrng RNG handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_RNG_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_RNG_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hrng);
+
+ if (HAL_RNG_STATE_READY == hrng->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_RNG_ERROR_CB_ID :
+ hrng->ErrorCallback = HAL_RNG_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_RNG_MSPINIT_CB_ID :
+ hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_RNG_MSPDEINIT_CB_ID :
+ hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_RNG_STATE_RESET == hrng->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_RNG_MSPINIT_CB_ID :
+ hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_RNG_MSPDEINIT_CB_ID :
+ hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hrng);
+ return status;
+}
+
+/**
+ * @brief Register Data Ready RNG Callback
+ * To be used instead of the weak HAL_RNG_ReadyDataCallback() predefined callback
+ * @param hrng RNG handle
+ * @param pCallback pointer to the Data Ready Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hrng);
+
+ if (HAL_RNG_STATE_READY == hrng->State)
+ {
+ hrng->ReadyDataCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hrng);
+ return status;
+}
+
+/**
+ * @brief UnRegister the Data Ready RNG Callback
+ * Data Ready RNG Callback is redirected to the weak HAL_RNG_ReadyDataCallback() predefined callback
+ * @param hrng RNG handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hrng);
+
+ if (HAL_RNG_STATE_READY == hrng->State)
+ {
+ hrng->ReadyDataCallback = HAL_RNG_ReadyDataCallback; /* Legacy weak ReadyDataCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hrng);
+ return status;
+}
+
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RNG_Exported_Functions_Group2
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Get the 32 bit Random number
+ (+) Get the 32 bit Random number with interrupt enabled
+ (+) Handle RNG interrupt request
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Generates a 32-bit random number.
+ * @note This function checks value of RNG_FLAG_DRDY flag to know if valid
+ * random number is available in the DR register (RNG_FLAG_DRDY flag set
+ * whenever a random number is available through the RNG_DR register).
+ * After transitioning from 0 to 1 (random number available),
+ * RNG_FLAG_DRDY flag remains high until output buffer becomes empty after reading
+ * four words from the RNG_DR register, i.e. further function calls
+ * will immediately return a new u32 random number (additional words are
+ * available and can be read by the application, till RNG_FLAG_DRDY flag remains high).
+ * @note When no more random number data is available in DR register, RNG_FLAG_DRDY
+ * flag is automatically cleared.
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
+ * @param random32bit pointer to generated random number variable if successful.
+ * @retval HAL status
+ */
+
+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit)
+{
+ uint32_t tickstart;
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process Locked */
+ __HAL_LOCK(hrng);
+
+ /* Check RNG peripheral state */
+ if (hrng->State == HAL_RNG_STATE_READY)
+ {
+ /* Change RNG peripheral state */
+ hrng->State = HAL_RNG_STATE_BUSY;
+ /* Check if there is a seed error */
+ if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
+ {
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_SEED;
+ /* Reset from seed error */
+ status = RNG_RecoverSeedError(hrng);
+ if (status == HAL_ERROR)
+ {
+ return status;
+ }
+ }
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check if data register contains valid random data */
+ while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
+ {
+ /* New check to avoid false timeout detection in case of preemption */
+ if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
+ {
+ hrng->State = HAL_RNG_STATE_READY;
+ hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrng);
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Get a 32bit Random number */
+ hrng->RandomNumber = hrng->Instance->DR;
+ /* In case of seed error, the value available in the RNG_DR register must not
+ be used as it may not have enough entropy */
+ if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
+ {
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_SEED;
+ /* Clear bit DRDY */
+ CLEAR_BIT(hrng->Instance->SR, RNG_FLAG_DRDY);
+ }
+ else /* No seed error */
+ {
+ *random32bit = hrng->RandomNumber;
+ }
+ hrng->State = HAL_RNG_STATE_READY;
+ }
+ else
+ {
+ hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
+ status = HAL_ERROR;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrng);
+
+ return status;
+}
+
+/**
+ * @brief Generates a 32-bit random number in interrupt mode.
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process Locked */
+ __HAL_LOCK(hrng);
+
+ /* Check RNG peripheral state */
+ if (hrng->State == HAL_RNG_STATE_READY)
+ {
+ /* Change RNG peripheral state */
+ hrng->State = HAL_RNG_STATE_BUSY;
+
+ /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
+ __HAL_RNG_ENABLE_IT(hrng);
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrng);
+
+ hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Handles RNG interrupt request.
+ * @note In the case of a clock error, the RNG is no more able to generate
+ * random numbers because the PLL48CLK clock is not correct. User has
+ * to check that the clock controller is correctly configured to provide
+ * the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT().
+ * The clock error has no impact on the previously generated
+ * random numbers, and the RNG_DR register contents can be used.
+ * @note In the case of a seed error, the generation of random numbers is
+ * interrupted as long as the SECS bit is '1'. If a number is
+ * available in the RNG_DR register, it must not be used because it may
+ * not have enough entropy. In this case, it is recommended to clear the
+ * SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable
+ * the RNG peripheral to reinitialize and restart the RNG.
+ * @note User-written HAL_RNG_ErrorCallback() API is called once whether SEIS
+ * or CEIS are set.
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
+ * @retval None
+
+ */
+void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
+{
+ uint32_t rngclockerror = 0U;
+
+ /* RNG clock error interrupt occurred */
+ if (__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET)
+ {
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_CLOCK;
+ rngclockerror = 1U;
+ }
+ else if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
+ {
+ /* Check if Seed Error Current Status (SECS) is set */
+ if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) == RESET)
+ {
+ /* RNG IP performed the reset automatically (auto-reset) */
+ /* Clear bit SEIS */
+ CLEAR_BIT(hrng->Instance->SR, RNG_IT_SEI);
+ }
+ else
+ {
+ /* Seed Error has not been recovered : Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_SEED;
+ rngclockerror = 1U;
+ /* Disable the IT */
+ __HAL_RNG_DISABLE_IT(hrng);
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ if (rngclockerror == 1U)
+ {
+ /* Change RNG peripheral state */
+ hrng->State = HAL_RNG_STATE_ERROR;
+
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+ /* Call registered Error callback */
+ hrng->ErrorCallback(hrng);
+#else
+ /* Call legacy weak Error callback */
+ HAL_RNG_ErrorCallback(hrng);
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+
+ /* Clear the clock error flag */
+ __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI | RNG_IT_SEI);
+
+ return;
+ }
+
+ /* Check RNG data ready interrupt occurred */
+ if (__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)
+ {
+ /* Generate random number once, so disable the IT */
+ __HAL_RNG_DISABLE_IT(hrng);
+
+ /* Get the 32bit Random number (DRDY flag automatically cleared) */
+ hrng->RandomNumber = hrng->Instance->DR;
+
+ if (hrng->State != HAL_RNG_STATE_ERROR)
+ {
+ /* Change RNG peripheral state */
+ hrng->State = HAL_RNG_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrng);
+
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+ /* Call registered Data Ready callback */
+ hrng->ReadyDataCallback(hrng, hrng->RandomNumber);
+#else
+ /* Call legacy weak Data Ready callback */
+ HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber);
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+ }
+ }
+}
+
+/**
+ * @brief Read latest generated random number.
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
+ * @retval random value
+ */
+uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)
+{
+ return (hrng->RandomNumber);
+}
+
+/**
+ * @brief Data Ready callback in non-blocking mode.
+ * @note When RNG_FLAG_DRDY flag value is set, first random number has been read
+ * from DR register in IRQ Handler and is provided as callback parameter.
+ * Depending on valid data available in the conditioning output buffer,
+ * additional words can be read by the application from DR register till
+ * DRDY bit remains high.
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
+ * @param random32bit generated random number.
+ * @retval None
+ */
+__weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrng);
+ UNUSED(random32bit);
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_RNG_ReadyDataCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief RNG error callbacks.
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
+ * @retval None
+ */
+__weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrng);
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_RNG_ErrorCallback must be implemented in the user file.
+ */
+}
+/**
+ * @}
+ */
+
+
+/** @addtogroup RNG_Exported_Functions_Group3
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the RNG state.
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
+ * @retval HAL state
+ */
+HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
+{
+ return hrng->State;
+}
+
+/**
+ * @brief Return the RNG handle error code.
+ * @param hrng: pointer to a RNG_HandleTypeDef structure.
+ * @retval RNG Error Code
+ */
+uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng)
+{
+ /* Return RNG Error Code */
+ return hrng->ErrorCode;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup RNG_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief RNG sequence to recover from a seed error
+ * @param hrng pointer to a RNG_HandleTypeDef structure.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng)
+{
+ __IO uint32_t count = 0U;
+
+ /*Check if seed error current status (SECS)is set */
+ if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) == RESET)
+ {
+ /* RNG performed the reset automatically (auto-reset) */
+ /* Clear bit SEIS */
+ CLEAR_BIT(hrng->Instance->SR, RNG_IT_SEI);
+ }
+ else /* Sequence to fully recover from a seed error*/
+ {
+ /* Writing bit CONDRST=1*/
+ SET_BIT(hrng->Instance->CR, RNG_CR_CONDRST);
+ /* Writing bit CONDRST=0*/
+ CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST);
+
+ /* Wait for conditioning reset process to be completed */
+ count = RNG_TIMEOUT_VALUE;
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ hrng->State = HAL_RNG_STATE_READY;
+ hrng->ErrorCode |= HAL_RNG_ERROR_TIMEOUT;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrng);
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+ /* Call registered Error callback */
+ hrng->ErrorCallback(hrng);
+#else
+ /* Call legacy weak Error callback */
+ HAL_RNG_ErrorCallback(hrng);
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+ return HAL_ERROR;
+ }
+ } while (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST));
+
+ if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
+ {
+ /* Clear bit SEIS */
+ CLEAR_BIT(hrng->Instance->SR, RNG_IT_SEI);
+ }
+
+ /* Wait for SECS to be cleared */
+ count = RNG_TIMEOUT_VALUE;
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ hrng->State = HAL_RNG_STATE_READY;
+ hrng->ErrorCode |= HAL_RNG_ERROR_TIMEOUT;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrng);
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+ /* Call registered Error callback */
+ hrng->ErrorCallback(hrng);
+#else
+ /* Call legacy weak Error callback */
+ HAL_RNG_ErrorCallback(hrng);
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+ return HAL_ERROR;
+ }
+ } while (HAL_IS_BIT_SET(hrng->Instance->SR, RNG_FLAG_SECS));
+ }
+ /* Update the error code */
+ hrng->ErrorCode &= ~ HAL_RNG_ERROR_SEED;
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+#endif /* HAL_RNG_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+#endif /* RNG */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng_ex.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng_ex.c
new file mode 100644
index 00000000..c2f225b7
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng_ex.c
@@ -0,0 +1,338 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_rng_ex.c
+ * @author MCD Application Team
+ * @brief Extended RNG HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Random Number Generator (RNG) peripheral:
+ * + Lock configuration functions
+ * + Reset the RNG
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+#if defined(RNG)
+
+/** @addtogroup RNGEx
+ * @brief RNG Extended HAL module driver.
+ * @{
+ */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+#if defined(RNG_CR_CONDRST)
+/* Private types -------------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RNGEx_Private_Constants RNGEx Private Constants
+ * @{
+ */
+#define RNG_TIMEOUT_VALUE 2U
+/**
+ * @}
+ */
+/* Private macros ------------------------------------------------------------*/
+/* Private functions prototypes ----------------------------------------------*/
+/* Private functions --------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup RNGEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RNGEx_Exported_Functions_Group1
+ * @brief Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Configuration and lock functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure the RNG with the specified parameters in the RNG_ConfigTypeDef
+ (+) Lock RNG configuration Allows user to lock a configuration until next reset.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the RNG with the specified parameters in the
+ * RNG_ConfigTypeDef.
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
+ * @param pConf: pointer to a RNG_ConfigTypeDef structure that contains
+ * the configuration information for RNG module
+
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf)
+{
+ uint32_t tickstart;
+ uint32_t cr_value;
+ HAL_StatusTypeDef status ;
+
+ /* Check the RNG handle allocation */
+ if ((hrng == NULL) || (pConf == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_RNG_ALL_INSTANCE(hrng->Instance));
+ assert_param(IS_RNG_CLOCK_DIVIDER(pConf->ClockDivider));
+ assert_param(IS_RNG_NIST_COMPLIANCE(pConf->NistCompliance));
+ assert_param(IS_RNG_CONFIG1(pConf->Config1));
+ assert_param(IS_RNG_CONFIG2(pConf->Config2));
+ assert_param(IS_RNG_CONFIG3(pConf->Config3));
+ assert_param(IS_RNG_ARDIS(pConf->AutoReset));
+
+ /* Check RNG peripheral state */
+ if (hrng->State == HAL_RNG_STATE_READY)
+ {
+ /* Change RNG peripheral state */
+ hrng->State = HAL_RNG_STATE_BUSY;
+
+ /* Disable RNG */
+ __HAL_RNG_DISABLE(hrng);
+
+ /* RNG CR register configuration. Set value in CR register for :
+ - NIST Compliance setting
+ - Clock divider value
+ - Automatic reset to clear SECS bit
+ - CONFIG 1, CONFIG 2 and CONFIG 3 values */
+ cr_value = (uint32_t)(pConf->ClockDivider | pConf->NistCompliance | pConf->AutoReset
+ | (pConf->Config1 << RNG_CR_RNG_CONFIG1_Pos)
+ | (pConf->Config2 << RNG_CR_RNG_CONFIG2_Pos)
+ | (pConf->Config3 << RNG_CR_RNG_CONFIG3_Pos));
+
+ MODIFY_REG(hrng->Instance->CR, RNG_CR_NISTC | RNG_CR_CLKDIV | RNG_CR_RNG_CONFIG1
+ | RNG_CR_RNG_CONFIG2 | RNG_CR_RNG_CONFIG3,
+ (uint32_t)(RNG_CR_CONDRST | cr_value));
+
+ /* RNG health test control in accordance with NIST */
+ WRITE_REG(hrng->Instance->HTCR, pConf->HealthTest);
+
+ /* Writing bit CONDRST=0*/
+ CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST);
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait for conditioning reset process to be completed */
+ while (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST))
+ {
+ if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
+ {
+ /* New check to avoid false timeout detection in case of prememption */
+ if (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST))
+ {
+ hrng->State = HAL_RNG_STATE_READY;
+ hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Enable RNG */
+ __HAL_RNG_ENABLE(hrng);
+
+ /* Initialize the RNG state */
+ hrng->State = HAL_RNG_STATE_READY;
+
+ /* function status */
+ status = HAL_OK;
+ }
+ else
+ {
+ hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
+ status = HAL_ERROR;
+ }
+
+ /* Return the function status */
+ return status;
+}
+
+/**
+ * @brief Get the RNG Configuration and fill parameters in the
+ * RNG_ConfigTypeDef.
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
+ * @param pConf: pointer to a RNG_ConfigTypeDef structure that contains
+ * the configuration information for RNG module
+
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RNGEx_GetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf)
+{
+
+ HAL_StatusTypeDef status ;
+
+ /* Check the RNG handle allocation */
+ if ((hrng == NULL) || (pConf == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check RNG peripheral state */
+ if (hrng->State == HAL_RNG_STATE_READY)
+ {
+ /* Change RNG peripheral state */
+ hrng->State = HAL_RNG_STATE_BUSY;
+
+ /* Get RNG parameters */
+ pConf->Config1 = (uint32_t)((hrng->Instance->CR & RNG_CR_RNG_CONFIG1) >> RNG_CR_RNG_CONFIG1_Pos) ;
+ pConf->Config2 = (uint32_t)((hrng->Instance->CR & RNG_CR_RNG_CONFIG2) >> RNG_CR_RNG_CONFIG2_Pos);
+ pConf->Config3 = (uint32_t)((hrng->Instance->CR & RNG_CR_RNG_CONFIG3) >> RNG_CR_RNG_CONFIG3_Pos);
+ pConf->ClockDivider = (hrng->Instance->CR & RNG_CR_CLKDIV);
+ pConf->NistCompliance = (hrng->Instance->CR & RNG_CR_NISTC);
+ pConf->AutoReset = (hrng->Instance->CR & RNG_CR_ARDIS);
+ pConf->HealthTest = (hrng->Instance->HTCR);
+
+ /* Initialize the RNG state */
+ hrng->State = HAL_RNG_STATE_READY;
+
+ /* function status */
+ status = HAL_OK;
+ }
+ else
+ {
+ hrng->ErrorCode |= HAL_RNG_ERROR_BUSY;
+ status = HAL_ERROR;
+ }
+
+ /* Return the function status */
+ return status;
+}
+
+/**
+ * @brief RNG current configuration lock.
+ * @note This function allows to lock RNG peripheral configuration.
+ * Once locked, HW RNG reset has to be performed prior any further
+ * configuration update.
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check the RNG handle allocation */
+ if (hrng == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check RNG peripheral state */
+ if (hrng->State == HAL_RNG_STATE_READY)
+ {
+ /* Change RNG peripheral state */
+ hrng->State = HAL_RNG_STATE_BUSY;
+
+ /* Perform RNG configuration Lock */
+ MODIFY_REG(hrng->Instance->CR, RNG_CR_CONFIGLOCK, RNG_CR_CONFIGLOCK);
+
+ /* Change RNG peripheral state */
+ hrng->State = HAL_RNG_STATE_READY;
+
+ /* function status */
+ status = HAL_OK;
+ }
+ else
+ {
+ hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
+ status = HAL_ERROR;
+ }
+
+ /* Return the function status */
+ return status;
+}
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup RNGEx_Exported_Functions_Group2
+ * @brief Recover from seed error function
+ *
+@verbatim
+ ===============================================================================
+ ##### Configuration and lock functions #####
+ ===============================================================================
+ [..] This section provide function allowing to:
+ (+) Recover from a seed error
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief RNG sequence to recover from a seed error
+ * @param hrng: pointer to a RNG_HandleTypeDef structure.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check the RNG handle allocation */
+ if (hrng == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check RNG peripheral state */
+ if (hrng->State == HAL_RNG_STATE_READY)
+ {
+ /* Change RNG peripheral state */
+ hrng->State = HAL_RNG_STATE_BUSY;
+
+ /* sequence to fully recover from a seed error */
+ status = RNG_RecoverSeedError(hrng);
+ }
+ else
+ {
+ hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
+ status = HAL_ERROR;
+ }
+
+ /* Return the function status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* RNG_CR_CONDRST */
+#endif /* HAL_RNG_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+#endif /* RNG */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rtc.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rtc.c
new file mode 100644
index 00000000..208ee460
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rtc.c
@@ -0,0 +1,2194 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_rtc.c
+ * @author MCD Application Team
+ * @brief RTC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Real-Time Clock (RTC) peripheral:
+ * + Initialization/de-initialization functions
+ * + Calendar (Time and Date) configuration
+ * + Alarms (Alarm A and Alarm B) configuration
+ * + WakeUp Timer configuration
+ * + TimeStamp configuration
+ * + Tampers configuration
+ * + Backup Data Registers configuration
+ * + RTC Tamper and TimeStamp Pins Selection
+ * + Interrupts and flags management
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ===============================================================================
+ ##### RTC Operating Condition #####
+ ===============================================================================
+ [..] The real-time clock (RTC) and the RTC backup registers can be powered
+ from the VBAT voltage when the main VDD supply is powered off.
+ To retain the content of the RTC backup registers and supply the RTC
+ when VDD is turned off, VBAT pin can be connected to an optional
+ standby voltage supplied by a battery or by another source.
+
+ ##### Backup Domain Reset #####
+ ===============================================================================
+ [..] The backup domain reset sets all RTC registers and the RCC_BDCR register
+ to their reset values.
+ A backup domain reset is generated when one of the following events occurs:
+ (#) Software reset, triggered by setting the BDRST bit in the
+ RCC Backup domain control register (RCC_BDCR).
+ (#) VDD or VBAT power on, if both supplies have previously been powered off.
+ (#) Tamper detection event resets all data backup registers.
+
+ ##### Backup Domain Access #####
+ ==================================================================
+ [..] After reset, the backup domain (RTC registers and RTC backup data registers)
+ is protected against possible unwanted write accesses.
+ [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
+ (+) Enable the Power Controller (PWR) APB1 interface clock using the
+ __HAL_RCC_PWR_CLK_ENABLE() function.
+ (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
+ (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function.
+ (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function.
+
+ [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
+ (#) Call the function HAL_RCCEx_PeriphCLKConfig with RCC_PERIPHCLK_RTC for
+ PeriphClockSelection and select RTCClockSelection (LSE, LSI or HSEdiv32)
+ (#) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() macro.
+
+ ##### How to use RTC Driver #####
+ ===================================================================
+ [..]
+ (+) Enable the RTC domain access (see description in the section above).
+ (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
+ format using the HAL_RTC_Init() function.
+
+ *** Time and Date configuration ***
+ ===================================
+ [..]
+ (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
+ and HAL_RTC_SetDate() functions.
+ (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.
+
+ *** Alarm configuration ***
+ ===========================
+ [..]
+ (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
+ You can also configure the RTC Alarm with interrupt mode using the
+ HAL_RTC_SetAlarm_IT() function.
+ (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
+
+ ##### RTC and low power modes #####
+ ==================================================================
+ [..] The MCU can be woken up from a low power mode by an RTC alternate
+ function.
+ [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
+ RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
+ These RTC alternate functions can wake up the system from the Stop and
+ Standby low power modes.
+ [..] The system can also wake up from low power modes without depending
+ on an external interrupt (Auto-wakeup mode), by using the RTC alarm
+ or the RTC wakeup events.
+ [..] The RTC provides a programmable time base for waking up from the
+ Stop or Standby mode at regular intervals.
+ Wakeup from STOP and STANDBY modes is possible only when the RTC clock source
+ is LSE or LSI.
+
+ *** Callback registration ***
+ =============================================
+ When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions. This is the recommended configuration
+ in order to optimize memory/code consumption footprint/performances.
+
+ The compilation define USE_RTC_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Function @ref HAL_RTC_RegisterCallback() to register an interrupt callback.
+
+ Function @ref HAL_RTC_RegisterCallback() allows to register following callbacks:
+ (+) AlarmAEventCallback : RTC Alarm A Event callback.
+ (+) AlarmBEventCallback : RTC Alarm B Event callback.
+ (+) TimeStampEventCallback : RTC TimeStamp Event callback.
+ (+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback.
+ (+) SSRUEventCallback : RTC SSRU Event callback.
+ (+) Tamper1EventCallback : RTC Tamper 1 Event callback.
+ (+) Tamper2EventCallback : RTC Tamper 2 Event callback.
+ (+) Tamper3EventCallback : RTC Tamper 3 Event callback.
+ (+) Tamper4EventCallback : RTC Tamper 4 Event callback.
+ (+) Tamper5EventCallback : RTC Tamper 5 Event callback.
+ (+) Tamper6EventCallback : RTC Tamper 6 Event callback.
+ (+) Tamper7EventCallback : RTC Tamper 7 Event callback.
+ (+) Tamper8EventCallback : RTC Tamper 8 Event callback.
+ (+) InternalTamper1EventCallback : RTC InternalTamper 1 Event callback.
+ (+) InternalTamper2EventCallback : RTC InternalTamper 2 Event callback.
+ (+) InternalTamper3EventCallback : RTC InternalTamper 3 Event callback.
+ (+) InternalTamper5EventCallback : RTC InternalTamper 5 Event callback.
+ (+) InternalTamper6EventCallback : RTC InternalTamper 6 Event callback.
+ (+) InternalTamper7EventCallback : RTC InternalTamper 7 Event callback.
+ (+) InternalTamper8EventCallback : RTC InternalTamper 8 Event callback.
+ (+) InternalTamper9EventCallback : RTC InternalTamper 9 Event callback.
+ (+) InternalTamper11EventCallback : RTC InternalTamper 11 Event callback.
+ (+) InternalTamper12EventCallback : RTC InternalTamper 12 Event callback.
+ (+) InternalTamper13EventCallback : RTC InternalTamper 13 Event callback.
+ (+) MspInitCallback : RTC MspInit callback.
+ (+) MspDeInitCallback : RTC MspDeInit callback.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_RTC_UnRegisterCallback() to reset a callback to the default
+ weak function.
+ @ref HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) AlarmAEventCallback : RTC Alarm A Event callback.
+ (+) AlarmBEventCallback : RTC Alarm B Event callback.
+ (+) TimeStampEventCallback : RTC TimeStamp Event callback.
+ (+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback.
+ (+) SSRUEventCallback : RTC SSRU Event callback.
+ (+) Tamper1EventCallback : RTC Tamper 1 Event callback.
+ (+) Tamper2EventCallback : RTC Tamper 2 Event callback.
+ (+) Tamper3EventCallback : RTC Tamper 3 Event callback.
+ (+) Tamper4EventCallback : RTC Tamper 4 Event callback.
+ (+) Tamper5EventCallback : RTC Tamper 5 Event callback.
+ (+) Tamper6EventCallback : RTC Tamper 6 Event callback.
+ (+) Tamper7EventCallback : RTC Tamper 7 Event callback.
+ (+) Tamper8EventCallback : RTC Tamper 8 Event callback.
+ (+) InternalTamper1EventCallback : RTC InternalTamper 1 Event callback.
+ (+) InternalTamper2EventCallback : RTC InternalTamper 2 Event callback.
+ (+) InternalTamper3EventCallback : RTC InternalTamper 3 Event callback.
+ (+) InternalTamper5EventCallback : RTC InternalTamper 5 Event callback.
+ (+) InternalTamper6EventCallback : RTC InternalTamper 6 Event callback.
+ (+) InternalTamper7EventCallback : RTC InternalTamper 7 Event callback.
+ (+) InternalTamper8EventCallback : RTC InternalTamper 8 Event callback.
+ (+) InternalTamper9EventCallback : RTC InternalTamper 9 Event callback.
+ (+) InternalTamper11EventCallback : RTC InternalTamper 11 Event callback.
+ (+) InternalTamper12EventCallback : RTC InternalTamper 12 Event callback.
+ (+) InternalTamper13EventCallback : RTC InternalTamper 13 Event callback.
+ (+) MspInitCallback : RTC MspInit callback.
+ (+) MspDeInitCallback : RTC MspDeInit callback.
+
+ By default, after the @ref HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET,
+ all callbacks are set to the corresponding weak functions :
+ examples @ref AlarmAEventCallback(), @ref TimeStampEventCallback().
+ Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function
+ in the @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit() only when these callbacks are null
+ (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_RTC_RegisterCallback() before calling @ref HAL_RTC_DeInit()
+ or @ref HAL_RTC_Init() function.
+
+ When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+
+/** @addtogroup RTC
+ * @brief RTC HAL module driver
+ * @{
+ */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup RTC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RTC_Exported_Functions_Group1
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to initialize and configure the
+ RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
+ RTC registers Write protection, enter and exit the RTC initialization mode,
+ RTC registers synchronization check and reference clock detection enable.
+ (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
+ It is split into 2 programmable prescalers to minimize power consumption.
+ (++) A 7-bit asynchronous prescaler and a 15-bit synchronous prescaler.
+ (++) When both prescalers are used, it is recommended to configure the
+ asynchronous prescaler to a high value to minimize power consumption.
+ (#) All RTC registers are Write protected. Writing to the RTC registers
+ is enabled by writing a key into the Write Protection register, RTC_WPR.
+ (#) To configure the RTC Calendar, user application should enter
+ initialization mode. In this mode, the calendar counter is stopped
+ and its value can be updated. When the initialization sequence is
+ complete, the calendar restarts counting after 4 RTCCLK cycles.
+ (#) To read the calendar through the shadow registers after Calendar
+ initialization, calendar update or after wakeup from low power modes
+ the software must first clear the RSF flag. The software must then
+ wait until it is set again before reading the calendar, which means
+ that the calendar registers have been correctly copied into the
+ RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function
+ implements the above software sequence (RSF clear and RSF check).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the RTC peripheral
+ * @param hrtc RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Check the RTC peripheral state */
+ if (hrtc != NULL)
+ {
+ /* Check the parameters */
+ assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
+ assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat));
+ assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv));
+ assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv));
+ assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut));
+ assert_param(IS_RTC_OUTPUT_REMAP(hrtc->Init.OutPutRemap));
+ assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity));
+ assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType));
+ assert_param(IS_RTC_OUTPUT_PULLUP(hrtc->Init.OutPutPullUp));
+ assert_param(IS_RTC_BINARY_MODE(hrtc->Init.BinMode));
+ assert_param(IS_RTC_BINARY_MIX_BCDU(hrtc->Init.BinMixBcdU));
+
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ if (hrtc->State == HAL_RTC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hrtc->Lock = HAL_UNLOCKED;
+ /* Legacy weak AlarmAEventCallback */
+ hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback;
+ /* Legacy weak AlarmBEventCallback */
+ hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback;
+ /* Legacy weak TimeStampEventCallback */
+ hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback;
+ /* Legacy weak WakeUpTimerEventCallback */
+ hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback;
+ /* Legacy weak SSRUEventCallback */
+ hrtc->SSRUEventCallback = HAL_RTCEx_SSRUEventCallback;
+ /* Legacy weak Tamper1EventCallback */
+ hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback;
+ /* Legacy weak Tamper2EventCallback */
+ hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback;
+ /* Legacy weak Tamper3EventCallback */
+ hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback;
+ /* Legacy weak Tamper4EventCallback */
+ hrtc->Tamper4EventCallback = HAL_RTCEx_Tamper4EventCallback;
+ /* Legacy weak Tamper5EventCallback */
+ hrtc->Tamper5EventCallback = HAL_RTCEx_Tamper5EventCallback;
+ /* Legacy weak Tamper6EventCallback */
+ hrtc->Tamper6EventCallback = HAL_RTCEx_Tamper6EventCallback;
+ /* Legacy weak Tamper7EventCallback */
+ hrtc->Tamper7EventCallback = HAL_RTCEx_Tamper7EventCallback;
+ /* Legacy weak Tamper8EventCallback */
+ hrtc->Tamper8EventCallback = HAL_RTCEx_Tamper8EventCallback;
+ /* Legacy weak InternalTamper1EventCallback */
+ hrtc->InternalTamper1EventCallback = HAL_RTCEx_InternalTamper1EventCallback;
+ /* Legacy weak InternalTamper2EventCallback */
+ hrtc->InternalTamper2EventCallback = HAL_RTCEx_InternalTamper2EventCallback;
+ /* Legacy weak InternalTamper3EventCallback */
+ hrtc->InternalTamper3EventCallback = HAL_RTCEx_InternalTamper3EventCallback;
+ /* Legacy weak InternalTamper5EventCallback */
+ hrtc->InternalTamper5EventCallback = HAL_RTCEx_InternalTamper5EventCallback;
+ /* Legacy weak InternalTamper6EventCallback */
+ hrtc->InternalTamper6EventCallback = HAL_RTCEx_InternalTamper6EventCallback;
+ /* Legacy weak InternalTamper7EventCallback */
+ hrtc->InternalTamper7EventCallback = HAL_RTCEx_InternalTamper7EventCallback;
+ /* Legacy weak InternalTamper8EventCallback */
+ hrtc->InternalTamper8EventCallback = HAL_RTCEx_InternalTamper8EventCallback;
+ /* Legacy weak InternalTamper9EventCallback */
+ hrtc->InternalTamper9EventCallback = HAL_RTCEx_InternalTamper9EventCallback;
+ /* Legacy weak InternalTamper11EventCallback */
+ hrtc->InternalTamper11EventCallback = HAL_RTCEx_InternalTamper11EventCallback;
+ /* Legacy weak InternalTamper12EventCallback */
+ hrtc->InternalTamper12EventCallback = HAL_RTCEx_InternalTamper12EventCallback;
+ /* Legacy weak InternalTamper13EventCallback */
+ hrtc->InternalTamper13EventCallback = HAL_RTCEx_InternalTamper13EventCallback;
+ if (hrtc->MspInitCallback == NULL)
+ {
+ hrtc->MspInitCallback = HAL_RTC_MspInit;
+ }
+ /* Init the low level hardware */
+ hrtc->MspInitCallback(hrtc);
+
+ if (hrtc->MspDeInitCallback == NULL)
+ {
+ hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
+ }
+ }
+#else
+ if (hrtc->State == HAL_RTC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hrtc->Lock = HAL_UNLOCKED;
+
+ /* Initialize RTC MSP */
+ HAL_RTC_MspInit(hrtc);
+ }
+#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
+
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Enter Initialization mode */
+ status = RTC_EnterInitMode(hrtc);
+ if (status == HAL_OK)
+ {
+ /* Clear RTC_CR FMT, OSEL and POL Bits */
+ CLEAR_BIT(RTC->CR, (RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE));
+ /* Set RTC_CR register */
+ SET_BIT(RTC->CR, (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity));
+
+ /* Configure the RTC PRER */
+ WRITE_REG(RTC->PRER, ((hrtc->Init.SynchPrediv) | (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos)));
+
+ /* Configure the Binary mode */
+ MODIFY_REG(RTC->ICSR, RTC_ICSR_BIN | RTC_ICSR_BCDU, hrtc->Init.BinMode | hrtc->Init.BinMixBcdU);
+
+ /* Exit Initialization mode */
+ status = RTC_ExitInitMode(hrtc);
+ if (status == HAL_OK)
+ {
+ MODIFY_REG(RTC->CR, \
+ RTC_CR_TAMPALRM_PU | RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN, \
+ hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap);
+ }
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ if (status == HAL_OK)
+ {
+ hrtc->State = HAL_RTC_STATE_READY;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief DeInitialize the RTC peripheral.
+ * @note This function does not reset the RTC Backup Data registers.
+ * @param hrtc RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
+{
+ HAL_StatusTypeDef status;
+
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Enter Initialization mode */
+ status = RTC_EnterInitMode(hrtc);
+ if (status == HAL_OK)
+ {
+ /* Reset all RTC CR register bits */
+ CLEAR_REG(RTC->CR);
+ WRITE_REG(RTC->DR, (uint32_t)(RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
+ CLEAR_REG(RTC->TR);
+ WRITE_REG(RTC->WUTR, RTC_WUTR_WUT);
+ WRITE_REG(RTC->PRER, ((uint32_t)(RTC_PRER_PREDIV_A | 0xFFU)));
+ CLEAR_REG(RTC->ALRMAR);
+ CLEAR_REG(RTC->ALRMBR);
+ CLEAR_REG(RTC->SHIFTR);
+ CLEAR_REG(RTC->CALR);
+ CLEAR_REG(RTC->ALRMASSR);
+ CLEAR_REG(RTC->ALRMBSSR);
+ WRITE_REG(RTC->SCR, RTC_SCR_CITSF | RTC_SCR_CTSOVF | RTC_SCR_CTSF | RTC_SCR_CWUTF | RTC_SCR_CALRBF | \
+ RTC_SCR_CALRAF);
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ WRITE_REG(RTC->SECCFGR, (RTC_SECCFGR_SEC | RTC_SECCFGR_INITSEC | RTC_SECCFGR_CALSEC | RTC_SECCFGR_TSSEC \
+ | RTC_SECCFGR_WUTSEC | RTC_SECCFGR_ALRBSEC | RTC_SECCFGR_ALRASEC));
+#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+ CLEAR_REG(RTC->PRIVCFGR);
+
+ /* Exit initialization mode */
+ status = RTC_ExitInitMode(hrtc);
+ if (status == HAL_OK)
+ {
+ /* Reset TAMP registers */
+ WRITE_REG(TAMP->CR1, RTC_INT_TAMPER_ALL);
+ CLEAR_REG(TAMP->CR2);
+ CLEAR_REG(TAMP->CR3);
+ CLEAR_REG(TAMP->FLTCR);
+ WRITE_REG(TAMP->ATCR1, TAMP_ATCR1_ATCKSEL);
+ CLEAR_REG(TAMP->ATOR);
+ CLEAR_REG(TAMP->ATCR2);
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ WRITE_REG(TAMP->SECCFGR, TAMP_SECCFGR_TAMPSEC);
+#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+ CLEAR_REG(TAMP->PRIVCFGR);
+ }
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ if (status == HAL_OK)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ if (hrtc->MspDeInitCallback == NULL)
+ {
+ hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
+ }
+
+ /* DeInit the low level hardware: CLOCK, NVIC.*/
+ hrtc->MspDeInitCallback(hrtc);
+
+#else
+ /* De-Initialize RTC MSP */
+ HAL_RTC_MspDeInit(hrtc);
+#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
+
+ hrtc->State = HAL_RTC_STATE_RESET;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hrtc);
+
+ return status;
+}
+
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User RTC Callback
+ * To be used instead of the weak predefined callback
+ * @param hrtc RTC handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID
+ * @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID
+ * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID
+ * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID WakeUp Timer Event Callback ID
+ * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID
+ * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID
+ * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID
+ * @arg @ref HAL_RTC_TAMPER4_EVENT_CB_ID Tamper 4 Callback ID
+ * @arg @ref HAL_RTC_TAMPER5_EVENT_CB_ID Tamper 5 Callback ID
+ * @arg @ref HAL_RTC_TAMPER6_EVENT_CB_ID Tamper 6 Callback ID
+ * @arg @ref HAL_RTC_TAMPER7_EVENT_CB_ID Tamper 7 Callback ID
+ * @arg @ref HAL_RTC_TAMPER8_EVENT_CB_ID Tamper 8 Callback ID
+ * @arg @ref HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID Internal Tamper 1 Callback ID
+ * @arg @ref HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID Internal Tamper 2 Callback ID
+ * @arg @ref HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID Internal Tamper 3 Callback ID
+ * @arg @ref HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID Internal Tamper 5 Callback ID
+ * @arg @ref HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID Internal Tamper 6 Callback ID
+ * @arg @ref HAL_RTC_INTERNAL_TAMPER7_EVENT_CB_ID Internal Tamper 7 Callback ID
+ * @arg @ref HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID Internal Tamper 8 Callback ID
+ * @arg @ref HAL_RTC_INTERNAL_TAMPER9_EVENT_CB_ID Internal Tamper 9 Callback ID
+ * @arg @ref HAL_RTC_INTERNAL_TAMPER11_EVENT_CB_ID Internal Tamper 11 Callback ID
+ * @arg @ref HAL_RTC_INTERNAL_TAMPER12_EVENT_CB_ID Internal Tamper 12 Callback ID
+ * @arg @ref HAL_RTC_INTERNAL_TAMPER13_EVENT_CB_ID Internal Tamper 13 Callback ID
+ * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID
+ * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID,
+ pRTC_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hrtc);
+
+ if (HAL_RTC_STATE_READY == hrtc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_RTC_ALARM_A_EVENT_CB_ID :
+ hrtc->AlarmAEventCallback = pCallback;
+ break;
+
+ case HAL_RTC_ALARM_B_EVENT_CB_ID :
+ hrtc->AlarmBEventCallback = pCallback;
+ break;
+
+ case HAL_RTC_TIMESTAMP_EVENT_CB_ID :
+ hrtc->TimeStampEventCallback = pCallback;
+ break;
+
+ case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID :
+ hrtc->WakeUpTimerEventCallback = pCallback;
+ break;
+
+ case HAL_RTC_SSRU_EVENT_CB_ID :
+ hrtc->SSRUEventCallback = pCallback;
+ break;
+
+ case HAL_RTC_TAMPER1_EVENT_CB_ID :
+ hrtc->Tamper1EventCallback = pCallback;
+ break;
+
+ case HAL_RTC_TAMPER2_EVENT_CB_ID :
+ hrtc->Tamper2EventCallback = pCallback;
+ break;
+
+ case HAL_RTC_TAMPER3_EVENT_CB_ID :
+ hrtc->Tamper3EventCallback = pCallback;
+ break;
+
+ case HAL_RTC_TAMPER4_EVENT_CB_ID :
+ hrtc->Tamper4EventCallback = pCallback;
+ break;
+
+ case HAL_RTC_TAMPER5_EVENT_CB_ID :
+ hrtc->Tamper5EventCallback = pCallback;
+ break;
+
+ case HAL_RTC_TAMPER6_EVENT_CB_ID :
+ hrtc->Tamper6EventCallback = pCallback;
+ break;
+
+ case HAL_RTC_TAMPER7_EVENT_CB_ID :
+ hrtc->Tamper7EventCallback = pCallback;
+ break;
+
+ case HAL_RTC_TAMPER8_EVENT_CB_ID :
+ hrtc->Tamper8EventCallback = pCallback;
+ break;
+
+ case HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID :
+ hrtc->InternalTamper1EventCallback = pCallback;
+ break;
+
+ case HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID :
+ hrtc->InternalTamper2EventCallback = pCallback;
+ break;
+
+ case HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID :
+ hrtc->InternalTamper3EventCallback = pCallback;
+ break;
+
+ case HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID :
+ hrtc->InternalTamper5EventCallback = pCallback;
+ break;
+
+ case HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID :
+ hrtc->InternalTamper6EventCallback = pCallback;
+ break;
+
+ case HAL_RTC_INTERNAL_TAMPER7_EVENT_CB_ID :
+ hrtc->InternalTamper7EventCallback = pCallback;
+ break;
+
+ case HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID :
+ hrtc->InternalTamper8EventCallback = pCallback;
+ break;
+
+ case HAL_RTC_INTERNAL_TAMPER9_EVENT_CB_ID :
+ hrtc->InternalTamper9EventCallback = pCallback;
+ break;
+
+ case HAL_RTC_INTERNAL_TAMPER11_EVENT_CB_ID :
+ hrtc->InternalTamper11EventCallback = pCallback;
+ break;
+
+ case HAL_RTC_INTERNAL_TAMPER12_EVENT_CB_ID :
+ hrtc->InternalTamper12EventCallback = pCallback;
+ break;
+
+ case HAL_RTC_INTERNAL_TAMPER13_EVENT_CB_ID :
+ hrtc->InternalTamper13EventCallback = pCallback;
+ break;
+ case HAL_RTC_MSPINIT_CB_ID :
+ hrtc->MspInitCallback = pCallback;
+ break;
+
+ case HAL_RTC_MSPDEINIT_CB_ID :
+ hrtc->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_RTC_STATE_RESET == hrtc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_RTC_MSPINIT_CB_ID :
+ hrtc->MspInitCallback = pCallback;
+ break;
+
+ case HAL_RTC_MSPDEINIT_CB_ID :
+ hrtc->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hrtc);
+
+ return status;
+}
+
+/**
+ * @brief Unregister an RTC Callback
+ * RTC callback is redirected to the weak predefined callback
+ * @param hrtc RTC handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID
+ * @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID
+ * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID
+ * @arg @ref HAL_RTC_SSRU_EVENT_CB_ID SSRU Callback ID
+ * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID WakeUp Timer Event Callback ID
+ * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID
+ * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID
+ * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID
+ * @arg @ref HAL_RTC_TAMPER4_EVENT_CB_ID Tamper 4 Callback ID
+ * @arg @ref HAL_RTC_TAMPER5_EVENT_CB_ID Tamper 5 Callback ID
+ * @arg @ref HAL_RTC_TAMPER6_EVENT_CB_ID Tamper 6 Callback ID
+ * @arg @ref HAL_RTC_TAMPER7_EVENT_CB_ID Tamper 7 Callback ID
+ * @arg @ref HAL_RTC_TAMPER8_EVENT_CB_ID Tamper 8 Callback ID
+ * @arg @ref HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID Internal Tamper 1 Callback ID
+ * @arg @ref HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID Internal Tamper 2 Callback ID
+ * @arg @ref HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID Internal Tamper 3 Callback ID
+ * @arg @ref HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID Internal Tamper 5 Callback ID
+ * @arg @ref HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID Internal Tamper 6 Callback ID
+ * @arg @ref HAL_RTC_INTERNAL_TAMPER7_EVENT_CB_ID Internal Tamper 7 Callback ID
+ * @arg @ref HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID Internal Tamper 8 Callback ID
+ * @arg @ref HAL_RTC_INTERNAL_TAMPER9_EVENT_CB_ID Internal Tamper 9 Callback ID
+ * @arg @ref HAL_RTC_INTERNAL_TAMPER11_EVENT_CB_ID Internal Tamper 11 Callback ID
+ * @arg @ref HAL_RTC_INTERNAL_TAMPER12_EVENT_CB_ID Internal Tamper 12 Callback ID
+ * @arg @ref HAL_RTC_INTERNAL_TAMPER13_EVENT_CB_ID Internal Tamper 13 Callback ID
+ * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID
+ * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hrtc);
+
+ if (HAL_RTC_STATE_READY == hrtc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_RTC_ALARM_A_EVENT_CB_ID :
+ /* Legacy weak AlarmAEventCallback */
+ hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback;
+ break;
+
+ case HAL_RTC_ALARM_B_EVENT_CB_ID :
+ /* Legacy weak AlarmBEventCallback */
+ hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback;
+ break;
+
+ case HAL_RTC_TIMESTAMP_EVENT_CB_ID :
+ /* Legacy weak TimeStampEventCallback */
+ hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback;
+ break;
+
+ case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID :
+ /* Legacy weak WakeUpTimerEventCallback */
+ hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback;
+ break;
+
+ case HAL_RTC_SSRU_EVENT_CB_ID :
+ /* Legacy weak SSRUEventCallback */
+ hrtc->SSRUEventCallback = HAL_RTCEx_SSRUEventCallback;
+ break;
+
+ case HAL_RTC_TAMPER1_EVENT_CB_ID :
+ /* Legacy weak Tamper1EventCallback */
+ hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback;
+ break;
+
+ case HAL_RTC_TAMPER2_EVENT_CB_ID :
+ /* Legacy weak Tamper2EventCallback */
+ hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback;
+ break;
+
+ case HAL_RTC_TAMPER3_EVENT_CB_ID :
+ /* Legacy weak Tamper3EventCallback */
+ hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback;
+ break;
+
+ case HAL_RTC_TAMPER4_EVENT_CB_ID :
+ /* Legacy weak Tamper4EventCallback */
+ hrtc->Tamper4EventCallback = HAL_RTCEx_Tamper4EventCallback;
+ break;
+
+ case HAL_RTC_TAMPER5_EVENT_CB_ID :
+ /* Legacy weak Tamper5EventCallback */
+ hrtc->Tamper5EventCallback = HAL_RTCEx_Tamper5EventCallback;
+ break;
+
+ case HAL_RTC_TAMPER6_EVENT_CB_ID :
+ /* Legacy weak Tamper6EventCallback */
+ hrtc->Tamper6EventCallback = HAL_RTCEx_Tamper6EventCallback;
+ break;
+
+ case HAL_RTC_TAMPER7_EVENT_CB_ID :
+ /* Legacy weak Tamper7EventCallback */
+ hrtc->Tamper7EventCallback = HAL_RTCEx_Tamper7EventCallback;
+ break;
+
+ case HAL_RTC_TAMPER8_EVENT_CB_ID :
+ /* Legacy weak Tamper8EventCallback */
+ hrtc->Tamper8EventCallback = HAL_RTCEx_Tamper8EventCallback;
+ break;
+
+ case HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID :
+ /* Legacy weak InternalTamper1EventCallback */
+ hrtc->InternalTamper1EventCallback = HAL_RTCEx_InternalTamper1EventCallback;
+ break;
+
+ case HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID :
+ /* Legacy weak InternalTamper2EventCallback */
+ hrtc->InternalTamper2EventCallback = HAL_RTCEx_InternalTamper2EventCallback;
+ break;
+
+ case HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID :
+ /* Legacy weak InternalTamper3EventCallback */
+ hrtc->InternalTamper3EventCallback = HAL_RTCEx_InternalTamper3EventCallback;
+ break;
+
+ case HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID :
+ /* Legacy weak InternalTamper5EventCallback */
+ hrtc->InternalTamper5EventCallback = HAL_RTCEx_InternalTamper5EventCallback;
+ break;
+
+ case HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID :
+ /* Legacy weak InternalTamper6EventCallback */
+ hrtc->InternalTamper6EventCallback = HAL_RTCEx_InternalTamper6EventCallback;
+ break;
+
+ case HAL_RTC_INTERNAL_TAMPER7_EVENT_CB_ID :
+ /* Legacy weak InternalTamper7EventCallback */
+ hrtc->InternalTamper7EventCallback = HAL_RTCEx_InternalTamper7EventCallback;
+ break;
+
+ case HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID :
+ /* Legacy weak InternalTamper8EventCallback */
+ hrtc->InternalTamper8EventCallback = HAL_RTCEx_InternalTamper8EventCallback;
+ break;
+
+ case HAL_RTC_INTERNAL_TAMPER9_EVENT_CB_ID :
+ /* Legacy weak InternalTamper9EventCallback */
+ hrtc->InternalTamper9EventCallback = HAL_RTCEx_InternalTamper9EventCallback;
+ break;
+
+ case HAL_RTC_INTERNAL_TAMPER11_EVENT_CB_ID :
+ /* Legacy weak InternalTamper11EventCallback */
+ hrtc->InternalTamper11EventCallback = HAL_RTCEx_InternalTamper11EventCallback;
+ break;
+
+ case HAL_RTC_INTERNAL_TAMPER12_EVENT_CB_ID :
+ /* Legacy weak InternalTamper12EventCallback */
+ hrtc->InternalTamper12EventCallback = HAL_RTCEx_InternalTamper12EventCallback;
+ break;
+
+ case HAL_RTC_INTERNAL_TAMPER13_EVENT_CB_ID :
+ /* Legacy weak InternalTamper13EventCallback */
+ hrtc->InternalTamper13EventCallback = HAL_RTCEx_InternalTamper13EventCallback;
+ break;
+ case HAL_RTC_MSPINIT_CB_ID :
+ hrtc->MspInitCallback = HAL_RTC_MspInit;
+ break;
+
+ case HAL_RTC_MSPDEINIT_CB_ID :
+ hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_RTC_STATE_RESET == hrtc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_RTC_MSPINIT_CB_ID :
+ hrtc->MspInitCallback = HAL_RTC_MspInit;
+ break;
+
+ case HAL_RTC_MSPDEINIT_CB_ID :
+ hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hrtc);
+
+ return status;
+}
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+
+/**
+ * @brief Initialize the RTC MSP.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+__weak void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the RTC MSP.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Exported_Functions_Group2
+ * @brief RTC Time and Date functions
+ *
+@verbatim
+ ===============================================================================
+ ##### RTC Time and Date functions #####
+ ===============================================================================
+
+ [..] This section provides functions allowing to configure Time and Date features
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set RTC current time.
+ * @param hrtc RTC handle
+ * @param sTime Pointer to Time structure
+ * if Binary mode is RTC_BINARY_ONLY, this parameter is not used and RTC_SSR will be automatically
+ * reset to 0xFFFFFFFF
+ * else sTime->SubSeconds is not used and RTC_SSR will be automatically reset to the
+ * A 7-bit async prescaler (RTC_PRER_PREDIV_A)
+ * @param Format Format of sTime->Hours, sTime->Minutes and sTime->Seconds.
+ * if Binary mode is RTC_BINARY_ONLY, this parameter is not used
+ * else this parameter can be one of the following values
+ * @arg RTC_FORMAT_BIN: Binary format
+ * @arg RTC_FORMAT_BCD: BCD format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
+{
+ uint32_t tmpreg;
+ HAL_StatusTypeDef status;
+
+#ifdef USE_FULL_ASSERT
+ /* Check the parameters depending of the Binary mode with 32-bit free-running counter configuration. */
+ if (READ_BIT(RTC->ICSR, RTC_ICSR_BIN) == RTC_BINARY_NONE)
+ {
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+ }
+#endif /* USE_FULL_ASSERT */
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Enter Initialization mode */
+ status = RTC_EnterInitMode(hrtc);
+ if (status == HAL_OK)
+ {
+ /* Check Binary mode ((32-bit free-running counter) */
+ if (READ_BIT(RTC->ICSR, RTC_ICSR_BIN) != RTC_BINARY_ONLY)
+ {
+ if (Format == RTC_FORMAT_BIN)
+ {
+ if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U)
+ {
+ assert_param(IS_RTC_HOUR12(sTime->Hours));
+ assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
+ }
+ else
+ {
+ sTime->TimeFormat = 0x00U;
+ assert_param(IS_RTC_HOUR24(sTime->Hours));
+ }
+ assert_param(IS_RTC_MINUTES(sTime->Minutes));
+ assert_param(IS_RTC_SECONDS(sTime->Seconds));
+
+ tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << RTC_TR_HU_Pos) | \
+ ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << RTC_TR_MNU_Pos) | \
+ ((uint32_t)RTC_ByteToBcd2(sTime->Seconds) << RTC_TR_SU_Pos) | \
+ (((uint32_t)sTime->TimeFormat) << RTC_TR_PM_Pos));
+ }
+ else
+ {
+ if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U)
+ {
+ assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sTime->Hours)));
+ assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
+ }
+ else
+ {
+ sTime->TimeFormat = 0x00U;
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));
+ }
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
+ tmpreg = (((uint32_t)(sTime->Hours) << RTC_TR_HU_Pos) | \
+ ((uint32_t)(sTime->Minutes) << RTC_TR_MNU_Pos) | \
+ ((uint32_t)(sTime->Seconds) << RTC_TR_SU_Pos) | \
+ ((uint32_t)(sTime->TimeFormat) << RTC_TR_PM_Pos));
+ }
+
+ /* Set the RTC_TR register */
+ WRITE_REG(RTC->TR, (tmpreg & RTC_TR_RESERVED_MASK));
+
+ /* This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */
+ CLEAR_BIT(RTC->CR, RTC_CR_BKP);
+
+ /* This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */
+ SET_BIT(RTC->CR, (sTime->DayLightSaving | sTime->StoreOperation));
+ }
+
+ /* Exit Initialization mode */
+ status = RTC_ExitInitMode(hrtc);
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ if (status == HAL_OK)
+ {
+ hrtc->State = HAL_RTC_STATE_READY;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return status;
+}
+
+/**
+ * @brief Daylight Saving Time, Add one hour to the calendar in one single operation
+ * without going through the initialization procedure.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc)
+{
+ UNUSED(hrtc);
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+ SET_BIT(RTC->CR, RTC_CR_ADD1H);
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+}
+
+/**
+ * @brief Daylight Saving Time, Subtract one hour from the calendar in one
+ * single operation without going through the initialization procedure.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc)
+{
+ UNUSED(hrtc);
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+ SET_BIT(RTC->CR, RTC_CR_SUB1H);
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+}
+
+/**
+ * @brief Daylight Saving Time, Set the store operation bit.
+ * @note It can be used by the software in order to memorize the DST status.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc)
+{
+ UNUSED(hrtc);
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+ SET_BIT(RTC->CR, RTC_CR_BKP);
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+}
+
+/**
+ * @brief Daylight Saving Time, Clear the store operation bit.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc)
+{
+ UNUSED(hrtc);
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+ CLEAR_BIT(RTC->CR, RTC_CR_BKP);
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+}
+
+/**
+ * @brief Daylight Saving Time, Read the store operation bit.
+ * @param hrtc RTC handle
+ * @retval operation see RTC_StoreOperation_Definitions
+ */
+uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc)
+{
+ UNUSED(hrtc);
+ return READ_BIT(RTC->CR, RTC_CR_BKP);
+}
+
+/**
+ * @brief Get RTC current time.
+ * @note You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds
+ * value in second fraction ratio with time unit following generic formula:
+ * Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
+ * This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
+ * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
+ * in the higher-order calendar shadow registers to ensure consistency between the time and date values.
+ * Reading RTC current time locks the values in calendar shadow registers until Current date is read
+ * to ensure consistency between the time and date values.
+ * @param hrtc RTC handle
+ * @param sTime
+ * if Binary mode is RTC_BINARY_ONLY, sTime->SubSeconds only is updated
+ * else
+ * Pointer to Time structure with Hours, Minutes and Seconds fields returned
+ * with input format (BIN or BCD), also SubSeconds field returning the
+ * RTC_SSR register content and SecondFraction field the Synchronous pre-scaler
+ * factor to be used for second fraction ratio computation.
+ * @param Format Format of sTime->Hours, sTime->Minutes and sTime->Seconds.
+ * if Binary mode is RTC_BINARY_ONLY, this parameter is not used
+ * else this parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary format
+ * @arg RTC_FORMAT_BCD: BCD format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
+{
+ uint32_t tmpreg;
+
+ UNUSED(hrtc);
+ /* Get subseconds structure field from the corresponding register*/
+ sTime->SubSeconds = READ_REG(RTC->SSR);
+
+ if (READ_BIT(RTC->ICSR, RTC_ICSR_BIN) != RTC_BINARY_ONLY)
+ {
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+
+ /* Get SecondFraction structure field from the corresponding register field*/
+ sTime->SecondFraction = (uint32_t)(READ_REG(RTC->PRER) & RTC_PRER_PREDIV_S);
+
+ /* Get the TR register */
+ tmpreg = (uint32_t)(READ_REG(RTC->TR) & RTC_TR_RESERVED_MASK);
+
+ /* Fill the structure fields with the read parameters */
+ sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> RTC_TR_HU_Pos);
+ sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos);
+ sTime->Seconds = (uint8_t)((tmpreg & (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos);
+ sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> RTC_TR_PM_Pos);
+
+ /* Check the input parameters format */
+ if (Format == RTC_FORMAT_BIN)
+ {
+ /* Convert the time structure parameters to Binary format */
+ sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours);
+ sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes);
+ sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds);
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set RTC current date.
+ * @param hrtc RTC handle
+ * @param sDate Pointer to date structure
+ * @param Format Format of sDate->Year, sDate->Month and sDate->Weekday.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary format
+ * @arg RTC_FORMAT_BCD: BCD format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
+{
+ uint32_t datetmpreg;
+ HAL_StatusTypeDef status;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ if ((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U))
+ {
+ sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU);
+ }
+
+ assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));
+
+ if (Format == RTC_FORMAT_BIN)
+ {
+ assert_param(IS_RTC_YEAR(sDate->Year));
+ assert_param(IS_RTC_MONTH(sDate->Month));
+ assert_param(IS_RTC_DATE(sDate->Date));
+
+ datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << RTC_DR_YU_Pos) | \
+ ((uint32_t)RTC_ByteToBcd2(sDate->Month) << RTC_DR_MU_Pos) | \
+ ((uint32_t)RTC_ByteToBcd2(sDate->Date) << RTC_DR_DU_Pos) | \
+ ((uint32_t)sDate->WeekDay << RTC_DR_WDU_Pos));
+ }
+ else
+ {
+ assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
+ assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month)));
+ assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date)));
+
+ datetmpreg = ((((uint32_t)sDate->Year) << RTC_DR_YU_Pos) | \
+ (((uint32_t)sDate->Month) << RTC_DR_MU_Pos) | \
+ (((uint32_t)sDate->Date) << RTC_DR_DU_Pos) | \
+ (((uint32_t)sDate->WeekDay) << RTC_DR_WDU_Pos));
+ }
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Enter Initialization mode */
+ status = RTC_EnterInitMode(hrtc);
+ if (status == HAL_OK)
+ {
+ /* Set the RTC_DR register */
+ WRITE_REG(RTC->DR, (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK));
+
+ /* Exit Initialization mode */
+ status = RTC_ExitInitMode(hrtc);
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ if (status == HAL_OK)
+ {
+ hrtc->State = HAL_RTC_STATE_READY ;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return status;
+}
+
+/**
+ * @brief Get RTC current date.
+ * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
+ * in the higher-order calendar shadow registers to ensure consistency between the time and date values.
+ * Reading RTC current time locks the values in calendar shadow registers until Current date is read.
+ * @param hrtc RTC handle
+ * @param sDate Pointer to Date structure
+ * @param Format Format of sDate->Year, sDate->Month and sDate->Weekday.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary format
+ * @arg RTC_FORMAT_BCD: BCD format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
+{
+ uint32_t datetmpreg;
+
+ UNUSED(hrtc);
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+
+ /* Get the DR register */
+ datetmpreg = (uint32_t)(READ_REG(RTC->DR) & RTC_DR_RESERVED_MASK);
+
+ /* Fill the structure fields with the read parameters */
+ sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> RTC_DR_YU_Pos);
+ sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> RTC_DR_MU_Pos);
+ sDate->Date = (uint8_t)((datetmpreg & (RTC_DR_DT | RTC_DR_DU)) >> RTC_DR_DU_Pos);
+ sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> RTC_DR_WDU_Pos);
+
+ /* Check the input parameters format */
+ if (Format == RTC_FORMAT_BIN)
+ {
+ /* Convert the date structure parameters to Binary format */
+ sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);
+ sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month);
+ sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date);
+ }
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Exported_Functions_Group3
+ * @brief RTC Alarm functions
+ *
+@verbatim
+ ===============================================================================
+ ##### RTC Alarm functions #####
+ ===============================================================================
+
+ [..] This section provides functions allowing to configure Alarm feature
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Set the specified RTC Alarm.
+ * @param hrtc RTC handle
+ * @param sAlarm Pointer to Alarm structure
+ * if Binary mode is RTC_BINARY_ONLY, 3 fields only are used
+ * sAlarm->AlarmTime.SubSeconds
+ * sAlarm->AlarmSubSecondMask
+ * sAlarm->BinaryAutoClr
+ * @param Format of the entered parameters.
+ * if Binary mode is RTC_BINARY_ONLY, this parameter is not used
+ * else this parameter can be one of the following values
+ * @arg RTC_FORMAT_BIN: Binary format
+ * @arg RTC_FORMAT_BCD: BCD format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
+{
+ uint32_t tmpreg = 0;
+ uint32_t binaryMode;
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+#ifdef USE_FULL_ASSERT
+ /* Check the parameters depending of the Binary mode (32-bit free-running counter configuration). */
+ if (READ_BIT(RTC->ICSR, RTC_ICSR_BIN) == RTC_BINARY_NONE)
+ {
+ assert_param(IS_RTC_FORMAT(Format));
+ assert_param(IS_RTC_ALARM(sAlarm->Alarm));
+ assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
+ }
+ else if (READ_BIT(RTC->ICSR, RTC_ICSR_BIN) == RTC_BINARY_ONLY)
+ {
+ assert_param(IS_RTC_ALARM_SUB_SECOND_BINARY_MASK(sAlarm->AlarmSubSecondMask));
+ assert_param(IS_RTC_ALARMSUBSECONDBIN_AUTOCLR(sAlarm->BinaryAutoClr));
+ }
+ else /* RTC_BINARY_MIX */
+ {
+ assert_param(IS_RTC_FORMAT(Format));
+ assert_param(IS_RTC_ALARM(sAlarm->Alarm));
+ assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
+ /* In Binary Mix Mode, the RTC can not generate an alarm on a match involving all calendar items
+ + the upper SSR bits */
+ assert_param((sAlarm->AlarmSubSecondMask >> RTC_ALRMASSR_MASKSS_Pos) <=
+ (8U + (READ_BIT(RTC->ICSR, RTC_ICSR_BCDU) >> RTC_ICSR_BCDU_Pos)));
+ }
+#endif /* USE_FULL_ASSERT */
+
+ /* Get Binary mode (32-bit free-running counter configuration) */
+ binaryMode = READ_BIT(RTC->ICSR, RTC_ICSR_BIN);
+
+ if (binaryMode != RTC_BINARY_ONLY)
+ {
+ if (Format == RTC_FORMAT_BIN)
+ {
+ if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U)
+ {
+ assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
+ assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ sAlarm->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
+ }
+ assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
+ assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
+
+ if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
+ }
+ else
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
+ }
+ tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
+ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
+ ((uint32_t)sAlarm->AlarmMask));
+ }
+ else /* format BCD */
+ {
+ if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U)
+ {
+ assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
+ assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ sAlarm->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
+ }
+
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
+
+#ifdef USE_FULL_ASSERT
+ if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
+ }
+ else
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
+ }
+
+#endif /* USE_FULL_ASSERT */
+ tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
+ ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
+ ((uint32_t)(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \
+ ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
+ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
+ ((uint32_t)sAlarm->AlarmMask));
+ }
+ }
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Configure the Alarm register */
+ if (sAlarm->Alarm == RTC_ALARM_A)
+ {
+ /* Disable the Alarm A interrupt */
+ /* In case of interrupt mode is used, the interrupt source must disabled */
+ CLEAR_BIT(RTC->CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE));
+ /* Clear flag alarm A */
+ WRITE_REG(RTC->SCR, RTC_SCR_CALRAF);
+
+ if (binaryMode == RTC_BINARY_ONLY)
+ {
+ WRITE_REG(RTC->ALRMASSR, sAlarm->AlarmSubSecondMask | sAlarm->BinaryAutoClr);
+ }
+ else
+ {
+ WRITE_REG(RTC->ALRMAR, tmpreg);
+ WRITE_REG(RTC->ALRMASSR, sAlarm->AlarmSubSecondMask);
+ }
+
+ WRITE_REG(RTC->ALRABINR, sAlarm->AlarmTime.SubSeconds);
+
+ if (sAlarm->FlagAutoClr == ALARM_FLAG_AUTOCLR_ENABLE)
+ {
+ /* Configure the Alarm A output clear */
+ SET_BIT(RTC->CR, RTC_CR_ALRAOCLR);
+ }
+ else
+ {
+ /* Disable the Alarm A output clear */
+ CLEAR_BIT(RTC->CR, RTC_CR_ALRAOCLR);
+ }
+ /* Configure the Alarm state: Enable Alarm */
+ SET_BIT(RTC->CR, RTC_CR_ALRAE);
+ }
+ else
+ {
+ /* Disable the Alarm B interrupt */
+ /* In case of interrupt mode is used, the interrupt source must disabled */
+ CLEAR_BIT(RTC->CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE));
+ /* Clear flag alarm B */
+ WRITE_REG(RTC->SCR, RTC_SCR_CALRBF);
+
+ if (binaryMode == RTC_BINARY_ONLY)
+ {
+ WRITE_REG(RTC->ALRMBSSR, sAlarm->AlarmSubSecondMask | sAlarm->BinaryAutoClr);
+ }
+ else
+ {
+ WRITE_REG(RTC->ALRMBR, tmpreg);
+ WRITE_REG(RTC->ALRMBSSR, sAlarm->AlarmSubSecondMask);
+ }
+
+ WRITE_REG(RTC->ALRBBINR, sAlarm->AlarmTime.SubSeconds);
+ if (sAlarm->FlagAutoClr == ALARM_FLAG_AUTOCLR_ENABLE)
+ {
+ /* Configure the Alarm B output clear */
+ SET_BIT(RTC->CR, RTC_CR_ALRBOCLR);
+ }
+ else
+ {
+ /* Disable the Alarm B output clear */
+ CLEAR_BIT(RTC->CR, RTC_CR_ALRBOCLR);
+ }
+ /* Configure the Alarm state: Enable Alarm */
+ SET_BIT(RTC->CR, RTC_CR_ALRBE);
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the specified RTC Alarm with Interrupt.
+ * @param hrtc RTC handle
+ * @param sAlarm Pointer to Alarm structure
+ * if Binary mode is RTC_BINARY_ONLY, 3 fields only are used
+ * sAlarm->AlarmTime.SubSeconds
+ * sAlarm->AlarmSubSecondMask
+ * sAlarm->BinaryAutoClr
+ * @param Format Specifies the format of the entered parameters.
+ * if Binary mode is RTC_BINARY_ONLY, this parameter is not used
+ * else this parameter can be one of the following values
+ * @arg RTC_FORMAT_BIN: Binary format
+ * @arg RTC_FORMAT_BCD: BCD format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
+{
+ uint32_t tmpreg = 0;
+ uint32_t binaryMode;
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+#ifdef USE_FULL_ASSERT
+ /* Check the parameters depending of the Binary mode (32-bit free-running counter configuration). */
+ if (READ_BIT(RTC->ICSR, RTC_ICSR_BIN) == RTC_BINARY_NONE)
+ {
+ assert_param(IS_RTC_FORMAT(Format));
+ assert_param(IS_RTC_ALARM(sAlarm->Alarm));
+ assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
+ }
+ else if (READ_BIT(RTC->ICSR, RTC_ICSR_BIN) == RTC_BINARY_ONLY)
+ {
+ assert_param(IS_RTC_ALARM_SUB_SECOND_BINARY_MASK(sAlarm->AlarmSubSecondMask));
+ assert_param(IS_RTC_ALARMSUBSECONDBIN_AUTOCLR(sAlarm->BinaryAutoClr));
+ }
+ else /* RTC_BINARY_MIX */
+ {
+ assert_param(IS_RTC_FORMAT(Format));
+ assert_param(IS_RTC_ALARM(sAlarm->Alarm));
+ assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
+ /* In Binary Mix Mode, the RTC can not generate an alarm on a match
+ involving all calendar items + the upper SSR bits */
+ assert_param((sAlarm->AlarmSubSecondMask >> RTC_ALRMASSR_MASKSS_Pos) <=
+ (8U + (READ_BIT(RTC->ICSR, RTC_ICSR_BCDU) >> RTC_ICSR_BCDU_Pos)));
+ }
+#endif /* USE_FULL_ASSERT */
+
+ /* Get Binary mode (32-bit free-running counter configuration) */
+ binaryMode = READ_BIT(RTC->ICSR, RTC_ICSR_BIN);
+
+ if (binaryMode != RTC_BINARY_ONLY)
+ {
+ if (Format == RTC_FORMAT_BIN)
+ {
+ if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U)
+ {
+ assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
+ assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ sAlarm->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
+ }
+ assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
+ assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
+
+ if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
+ }
+ else
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
+ }
+ tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
+ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
+ ((uint32_t)sAlarm->AlarmMask));
+ }
+ else /* Format BCD */
+ {
+ if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U)
+ {
+ assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
+ assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ sAlarm->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
+ }
+
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
+
+#ifdef USE_FULL_ASSERT
+ if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
+ }
+ else
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
+ }
+
+#endif /* USE_FULL_ASSERT */
+ tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
+ ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
+ ((uint32_t)(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \
+ ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
+ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
+ ((uint32_t)sAlarm->AlarmMask));
+
+ }
+ }
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Configure the Alarm registers */
+ if (sAlarm->Alarm == RTC_ALARM_A)
+ {
+ /* Disable the Alarm A interrupt */
+ CLEAR_BIT(RTC->CR, RTC_CR_ALRAE | RTC_CR_ALRAIE);
+ /* Clear flag alarm A */
+ WRITE_REG(RTC->SCR, RTC_SCR_CALRAF);
+
+ if (binaryMode == RTC_BINARY_ONLY)
+ {
+ RTC->ALRMASSR = sAlarm->AlarmSubSecondMask | sAlarm->BinaryAutoClr;
+ }
+ else
+ {
+ WRITE_REG(RTC->ALRMAR, tmpreg);
+ WRITE_REG(RTC->ALRMASSR, sAlarm->AlarmSubSecondMask);
+ }
+
+ WRITE_REG(RTC->ALRABINR, sAlarm->AlarmTime.SubSeconds);
+
+ if (sAlarm->FlagAutoClr == ALARM_FLAG_AUTOCLR_ENABLE)
+ {
+ /* Configure the Alarm A output clear */
+ SET_BIT(RTC->CR, RTC_CR_ALRAOCLR);
+ }
+ else
+ {
+ /* Disable the Alarm A output clear*/
+ CLEAR_BIT(RTC->CR, RTC_CR_ALRAOCLR);
+ }
+
+ /* Configure the Alarm interrupt */
+ SET_BIT(RTC->CR, RTC_CR_ALRAE | RTC_CR_ALRAIE);
+ }
+ else
+ {
+ /* Disable the Alarm B interrupt */
+ CLEAR_BIT(RTC->CR, RTC_CR_ALRBE | RTC_CR_ALRBIE);
+ /* Clear flag alarm B */
+ WRITE_REG(RTC->SCR, RTC_SCR_CALRBF);
+
+ if (binaryMode == RTC_BINARY_ONLY)
+ {
+ WRITE_REG(RTC->ALRMBSSR, sAlarm->AlarmSubSecondMask | sAlarm->BinaryAutoClr);
+ }
+ else
+ {
+ WRITE_REG(RTC->ALRMBR, tmpreg);
+ WRITE_REG(RTC->ALRMBSSR, sAlarm->AlarmSubSecondMask);
+ }
+
+ WRITE_REG(RTC->ALRBBINR, sAlarm->AlarmTime.SubSeconds);
+
+ if (sAlarm->FlagAutoClr == ALARM_FLAG_AUTOCLR_ENABLE)
+ {
+ /* Configure the Alarm B Output clear */
+ SET_BIT(RTC->CR, RTC_CR_ALRBOCLR);
+ }
+ else
+ {
+ /* Disable the Alarm B Output clear */
+ CLEAR_BIT(RTC->CR, RTC_CR_ALRBOCLR);
+ }
+
+ /* Configure the Alarm interrupt */
+ SET_BIT(RTC->CR, RTC_CR_ALRBE | RTC_CR_ALRBIE);
+ }
+
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivate the specified RTC Alarm.
+ * @param hrtc RTC handle
+ * @param Alarm Specifies the Alarm.
+ * This parameter can be one of the following values:
+ * @arg RTC_ALARM_A: AlarmA
+ * @arg RTC_ALARM_B: AlarmB
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_ALARM(Alarm));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* In case of interrupt mode is used, the interrupt source must disabled */
+ if (Alarm == RTC_ALARM_A)
+ {
+ CLEAR_BIT(RTC->CR, RTC_CR_ALRAE | RTC_CR_ALRAIE);
+ /* AlarmA, Clear SSCLR */
+ CLEAR_BIT(RTC->ALRMASSR, RTC_ALRMASSR_SSCLR);
+ }
+ else
+ {
+ CLEAR_BIT(RTC->CR, RTC_CR_ALRBE | RTC_CR_ALRBIE);
+ /* AlarmB, Clear SSCLR */
+ CLEAR_BIT(RTC->ALRMBSSR, RTC_ALRMBSSR_SSCLR);
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get the RTC Alarm value and masks.
+ * @param hrtc RTC handle
+ * @param sAlarm Pointer to Date structure
+ * @param Alarm Specifies the Alarm.
+ * This parameter can be one of the following values:
+ * @arg RTC_ALARM_A: AlarmA
+ * @arg RTC_ALARM_B: AlarmB
+ * @param Format Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary format
+ * @arg RTC_FORMAT_BCD: BCD format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
+{
+ uint32_t tmpreg;
+ uint32_t subsecondtmpreg;
+
+ UNUSED(hrtc);
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+ assert_param(IS_RTC_ALARM(Alarm));
+
+ if (Alarm == RTC_ALARM_A)
+ {
+ /* AlarmA */
+ sAlarm->Alarm = RTC_ALARM_A;
+
+ tmpreg = READ_REG(RTC->ALRMAR);
+ subsecondtmpreg = (uint32_t)(READ_REG(RTC->ALRMASSR) & RTC_ALRMASSR_SS);
+
+ /* Fill the structure with the read parameters */
+ sAlarm->AlarmTime.Hours = (uint8_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> RTC_ALRMAR_HU_Pos);
+ sAlarm->AlarmTime.Minutes = (uint8_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> RTC_ALRMAR_MNU_Pos);
+ sAlarm->AlarmTime.Seconds = (uint8_t)((tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU)) >> RTC_ALRMAR_SU_Pos);
+ sAlarm->AlarmTime.TimeFormat = (uint8_t)((tmpreg & RTC_ALRMAR_PM) >> RTC_ALRMAR_PM_Pos);
+ sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
+ sAlarm->AlarmDateWeekDay = (uint8_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> RTC_ALRMAR_DU_Pos);
+ sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
+ sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
+ }
+ else
+ {
+ sAlarm->Alarm = RTC_ALARM_B;
+
+ tmpreg = READ_REG(RTC->ALRMBR);
+ subsecondtmpreg = (uint32_t)(READ_REG(RTC->ALRMBSSR) & RTC_ALRMBSSR_SS);
+
+ /* Fill the structure with the read parameters */
+ sAlarm->AlarmTime.Hours = (uint8_t)((tmpreg & (RTC_ALRMBR_HT | RTC_ALRMBR_HU)) >> RTC_ALRMBR_HU_Pos);
+ sAlarm->AlarmTime.Minutes = (uint8_t)((tmpreg & (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU)) >> RTC_ALRMBR_MNU_Pos);
+ sAlarm->AlarmTime.Seconds = (uint8_t)((tmpreg & (RTC_ALRMBR_ST | RTC_ALRMBR_SU)) >> RTC_ALRMBR_SU_Pos);
+ sAlarm->AlarmTime.TimeFormat = (uint8_t)((tmpreg & RTC_ALRMBR_PM) >> RTC_ALRMBR_PM_Pos);
+ sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
+ sAlarm->AlarmDateWeekDay = (uint8_t)((tmpreg & (RTC_ALRMBR_DT | RTC_ALRMBR_DU)) >> RTC_ALRMBR_DU_Pos);
+ sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMBR_WDSEL);
+ sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
+ }
+
+ if (Format == RTC_FORMAT_BIN)
+ {
+ sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
+ sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);
+ sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds);
+ sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
+ }
+
+ return HAL_OK;
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ * @brief Handle Alarm secure interrupt request.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc)
+{
+ /* Get interrupt status */
+ uint32_t tmp = READ_REG(RTC->SMISR);
+
+ if ((tmp & RTC_SMISR_ALRAMF) != 0u)
+ {
+ /* Clear the AlarmA interrupt pending bit */
+ WRITE_REG(RTC->SCR, RTC_SCR_CALRAF);
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Compare Match registered Callback */
+ hrtc->AlarmAEventCallback(hrtc);
+#else
+ HAL_RTC_AlarmAEventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+ }
+
+ if ((tmp & RTC_SMISR_ALRBMF) != 0u)
+ {
+ /* Clear the AlarmB interrupt pending bit */
+ WRITE_REG(RTC->SCR, RTC_SCR_CALRBF);
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Compare Match registered Callback */
+ hrtc->AlarmBEventCallback(hrtc);
+#else
+ HAL_RTCEx_AlarmBEventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+
+ }
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+}
+
+#else /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/**
+ * @brief Handle Alarm non-secure interrupt request.
+ * @note Alarm non-secure is available in non-secure driver.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc)
+{
+ /* Get interrupt status */
+ uint32_t tmp = READ_REG(RTC->MISR);
+
+ if ((tmp & RTC_MISR_ALRAMF) != 0U)
+ {
+ /* Clear the AlarmA interrupt pending bit */
+ WRITE_REG(RTC->SCR, RTC_SCR_CALRAF);
+
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Compare Match registered Callback */
+ hrtc->AlarmAEventCallback(hrtc);
+#else
+ HAL_RTC_AlarmAEventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+ }
+
+ if ((tmp & RTC_MISR_ALRBMF) != 0U)
+ {
+ /* Clear the AlarmB interrupt pending bit */
+ WRITE_REG(RTC->SCR, RTC_SCR_CALRBF);
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Compare Match registered Callback */
+ hrtc->AlarmBEventCallback(hrtc);
+#else
+ HAL_RTCEx_AlarmBEventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+ }
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+}
+#endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/**
+ * @brief Alarm A secure secure callback.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the secure secure callback is needed,
+ the HAL_RTC_AlarmAEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Handle AlarmA Polling request.
+ * @param hrtc RTC handle
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ while (READ_BIT(RTC->SR, RTC_SR_ALRAF) == 0U)
+ {
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear the Alarm interrupt pending bit */
+ WRITE_REG(RTC->SCR, RTC_SCR_CALRAF);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Exported_Functions_Group4
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Wait for RTC Time and Date Synchronization
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are
+ * synchronized with RTC APB clock.
+ * @note The RTC Resynchronization mode is write protected, use the
+ * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
+ * @note To read the calendar through the shadow registers after Calendar
+ * initialization, calendar update or after wakeup from low power modes
+ * the software must first clear the RSF flag.
+ * The software must then wait until it is set again before reading
+ * the calendar, which means that the calendar registers have been
+ * correctly copied into the RTC_TR and RTC_DR shadow registers.
+ * @param hrtc RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc)
+{
+ uint32_t tickstart;
+
+ UNUSED(hrtc);
+ /* Clear RSF flag */
+ CLEAR_BIT(RTC->ICSR, RTC_ICSR_RSF);
+
+ tickstart = HAL_GetTick();
+
+ /* Wait the registers to be synchronised */
+ while (READ_BIT(RTC->ICSR, RTC_ICSR_RSF) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Exported_Functions_Group5
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Get RTC state
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Return the RTC handle state.
+ * @param hrtc RTC handle
+ * @retval HAL state
+ */
+HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc)
+{
+ /* Return RTC handle state */
+ return hrtc->State;
+}
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Private_Functions
+ * @{
+ */
+/**
+ * @brief Enter the RTC Initialization mode.
+ * @note The RTC Initialization mode is write protected, use the
+ * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
+ * @param hrtc RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc)
+{
+ uint32_t tickstart;
+ HAL_StatusTypeDef status = HAL_OK;
+
+ UNUSED(hrtc);
+ /* Check if the Initialization mode is set */
+ if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U)
+ {
+ /* Set the Initialization mode */
+ SET_BIT(RTC->ICSR, RTC_ICSR_INIT);
+
+ tickstart = HAL_GetTick();
+ /* Wait till RTC is in INIT state and if Time out is reached exit */
+ while ((READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) && (status != HAL_TIMEOUT))
+ {
+ if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ status = HAL_TIMEOUT;
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ }
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Exit the RTC Initialization mode.
+ * @param hrtc RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Exit Initialization mode */
+ CLEAR_BIT(RTC->ICSR, RTC_ICSR_INIT);
+
+ /* If CR_BYPSHAD bit = 0, wait for synchro */
+ if (READ_BIT(RTC->CR, RTC_CR_BYPSHAD) == 0U)
+ {
+ if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ status = HAL_TIMEOUT;
+ }
+ }
+ else /* WA 2.9.6 Calendar initialization may fail in case of consecutive INIT mode entry. */
+ {
+ /* Clear BYPSHAD bit */
+ CLEAR_BIT(RTC->CR, RTC_CR_BYPSHAD);
+ if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ status = HAL_TIMEOUT;
+ }
+ /* Restore BYPSHAD bit */
+ SET_BIT(RTC->CR, RTC_CR_BYPSHAD);
+ }
+ return status;
+}
+
+/**
+ * @brief Convert a 2 digit decimal to BCD format.
+ * @param Value Byte to be converted
+ * @retval Converted byte
+ */
+uint8_t RTC_ByteToBcd2(uint8_t Value)
+{
+ uint32_t bcdhigh = 0U;
+ uint8_t tmp_Value = Value;
+
+ while (tmp_Value >= 10U)
+ {
+ bcdhigh++;
+ tmp_Value -= 10U;
+ }
+
+ return ((uint8_t)(bcdhigh << 4U) | tmp_Value);
+}
+
+/**
+ * @brief Convert from 2 digit BCD to Binary.
+ * @param Value BCD value to be converted
+ * @retval Converted word
+ */
+uint8_t RTC_Bcd2ToByte(uint8_t Value)
+{
+ uint32_t tmp;
+ tmp = (((uint32_t)Value & 0xF0U) >> 4) * 10U;
+ return (uint8_t)(tmp + ((uint32_t)Value & 0x0FU));
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_RTC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rtc_ex.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rtc_ex.c
new file mode 100644
index 00000000..fbaa5281
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rtc_ex.c
@@ -0,0 +1,3291 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_rtc_ex.c
+ * @author MCD Application Team
+ * @brief Extended RTC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Real Time Clock (RTC) Extended peripheral:
+ * + RTC Time Stamp functions
+ * + RTC Tamper functions
+ * + RTC Wake-up functions
+ * + Extended Control functions
+ * + Extended RTC features functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (+) Enable the RTC domain access.
+ (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
+ format using the HAL_RTC_Init() function.
+
+ *** RTC Wakeup configuration ***
+ ================================
+ [..]
+ (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer()
+ function. You can also configure the RTC Wakeup timer with interrupt mode
+ using the HAL_RTCEx_SetWakeUpTimer_IT() function.
+ (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer()
+ function.
+
+ *** Outputs configuration ***
+ =============================
+ [..] The RTC has 2 different outputs:
+ (+) RTC_ALARM: this output is used to manage the RTC Alarm A, Alarm B
+ and WaKeUp signals.
+ To output the selected RTC signal, use the HAL_RTC_Init() function.
+ (+) RTC_CALIB: this output is 512Hz signal or 1Hz.
+ To enable the RTC_CALIB, use the HAL_RTCEx_SetCalibrationOutPut() function.
+ (+) Two pins can be used as RTC_ALARM or RTC_CALIB (PC13, PB2) managed on
+ the RTC_OR register.
+ (+) When the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin is
+ automatically configured in output alternate function.
+
+ *** Smooth digital Calibration configuration ***
+ ================================================
+ [..]
+ (+) Configure the RTC Original Digital Calibration Value and the corresponding
+ calibration cycle period (32s,16s and 8s) using the HAL_RTCEx_SetSmoothCalib()
+ function.
+
+ *** TimeStamp configuration ***
+ ===============================
+ [..]
+ (+) Enable the RTC TimeStamp using the HAL_RTCEx_SetTimeStamp() function.
+ You can also configure the RTC TimeStamp with interrupt mode using the
+ HAL_RTCEx_SetTimeStamp_IT() function.
+ (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
+ function.
+
+ *** Internal TimeStamp configuration ***
+ ===============================
+ [..]
+ (+) Enable the RTC internal TimeStamp using the HAL_RTCEx_SetInternalTimeStamp() function.
+ User has to check internal timestamp occurrence using __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG.
+ (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
+ function.
+
+ *** Tamper configuration ***
+ ============================
+ [..]
+ (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge
+ or Level according to the Tamper filter (if equal to 0 Edge else Level)
+ value, sampling frequency, NoErase, MaskFlag, precharge or discharge and
+ Pull-UP using the HAL_RTCEx_SetTamper() function. You can configure RTC Tamper
+ with interrupt mode using HAL_RTCEx_SetTamper_IT() function.
+ (+) The default configuration of the Tamper erases the backup registers. To avoid
+ erase, enable the NoErase field on the RTC_TAMPCR register.
+ (+) With new RTC tamper configuration, you have to call HAL_RTC_Init() in order to
+ perform TAMP base address offset calculation.
+ (+) If you do not intend to have tamper using RTC clock, you can bypass its initialization
+ by setting ClockEnable inti field to RTC_CLOCK_DISABLE.
+ (+) Enable Internal tamper using HAL_RTCEx_SetInternalTamper. IT mode can be chosen using
+ setting Interrupt field.
+
+ *** Backup Data Registers configuration ***
+ ===========================================
+ [..]
+ (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite()
+ function.
+ (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead()
+ function.
+ (+) Before calling these functions you have to call HAL_RTC_Init() in order to
+ perform TAMP base address offset calculation.
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup RTCEx
+ * @brief RTC Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define TAMP_ALL (TAMP_CR1_TAMP1E | TAMP_CR1_TAMP2E | TAMP_CR1_TAMP3E | TAMP_CR1_TAMP4E | \
+ TAMP_CR1_TAMP5E | TAMP_CR1_TAMP6E | TAMP_CR1_TAMP7E | TAMP_CR1_TAMP8E)
+
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup RTCEx_Exported_Functions
+ * @{
+ */
+
+
+/** @addtogroup RTCEx_Exported_Functions_Group1
+ * @brief RTC TimeStamp and Tamper functions
+ *
+@verbatim
+ ===============================================================================
+ ##### RTC TimeStamp and Tamper functions #####
+ ===============================================================================
+
+ [..] This section provides functions allowing to configure TimeStamp feature
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set TimeStamp.
+ * @note This API must be called before enabling the TimeStamp feature.
+ * @param hrtc RTC handle
+ * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is
+ * activated.
+ * This parameter can be one of the following values:
+ * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
+ * rising edge of the related pin.
+ * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
+ * falling edge of the related pin.
+ * @param RTC_TimeStampPin specifies the RTC TimeStamp Pin.
+ * This parameter can be one of the following values:
+ * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
+ * The RTC TimeStamp Pin is per default PC13, but for reasons of
+ * compatibility, this parameter is required.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
+{
+ /* Check the parameters */
+ assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
+ assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
+ UNUSED(RTC_TimeStampPin);
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Get the RTC_CR register and clear the bits to be configured */
+ CLEAR_BIT(RTC->CR, (RTC_CR_TSEDGE | RTC_CR_TSE));
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Configure the Time Stamp TSEDGE and Enable bits */
+ SET_BIT(RTC->CR, (uint32_t)TimeStampEdge | RTC_CR_TSE);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set TimeStamp with Interrupt.
+ * @note This API must be called before enabling the TimeStamp feature.
+ * @param hrtc RTC handle
+ * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is
+ * activated.
+ * This parameter can be one of the following values:
+ * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
+ * rising edge of the related pin.
+ * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
+ * falling edge of the related pin.
+ * @param RTC_TimeStampPin Specifies the RTC TimeStamp Pin.
+ * This parameter can be one of the following values:
+ * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
+ * The RTC TimeStamp Pin is per default PC13, but for reasons of
+ * compatibility, this parameter is required.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
+{
+ /* Check the parameters */
+ assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
+ assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
+ UNUSED(RTC_TimeStampPin);
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Get the RTC_CR register and clear the bits to be configured */
+ CLEAR_BIT(RTC->CR, (RTC_CR_TSEDGE | RTC_CR_TSE));
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Configure the Time Stamp TSEDGE before Enable bit to avoid unwanted TSF setting. */
+ SET_BIT(RTC->CR, (uint32_t)TimeStampEdge);
+
+ /* Enable timestamp and IT */
+ SET_BIT(RTC->CR, RTC_CR_TSE | RTC_CR_TSIE);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivate TimeStamp.
+ * @param hrtc RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
+{
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* In case of interrupt mode is used, the interrupt source must disabled */
+ CLEAR_BIT(RTC->CR, (RTC_CR_TSEDGE | RTC_CR_TSE | RTC_CR_TSIE));
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set Internal TimeStamp.
+ * @note This API must be called before enabling the internal TimeStamp feature.
+ * @param hrtc RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc)
+{
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Configure the internal Time Stamp Enable bits */
+ SET_BIT(RTC->CR, RTC_CR_ITSE);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivate Internal TimeStamp.
+ * @param hrtc RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc)
+{
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Configure the internal Time Stamp Enable bits */
+ CLEAR_BIT(RTC->CR, RTC_CR_ITSE);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get the RTC TimeStamp value.
+ * @param hrtc RTC handle
+ * @param sTimeStamp Pointer to Time structure
+ * @param sTimeStampDate Pointer to Date structure
+ * @param Format specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp,
+ RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
+{
+ uint32_t tmptime;
+ uint32_t tmpdate;
+
+ UNUSED(hrtc);
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+
+ /* Get the TimeStamp time and date registers values */
+ tmptime = READ_BIT(RTC->TSTR, RTC_TR_RESERVED_MASK);
+ tmpdate = READ_BIT(RTC->TSDR, RTC_DR_RESERVED_MASK);
+
+ /* Fill the Time structure fields with the read parameters */
+ sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TSTR_HT | RTC_TSTR_HU)) >> RTC_TSTR_HU_Pos);
+ sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TSTR_MNT | RTC_TSTR_MNU)) >> RTC_TSTR_MNU_Pos);
+ sTimeStamp->Seconds = (uint8_t)((tmptime & (RTC_TSTR_ST | RTC_TSTR_SU)) >> RTC_TSTR_SU_Pos);
+ sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TSTR_PM)) >> RTC_TSTR_PM_Pos);
+ sTimeStamp->SubSeconds = READ_BIT(RTC->TSSSR, RTC_TSSSR_SS);
+
+ /* Fill the Date structure fields with the read parameters */
+ sTimeStampDate->Year = 0U;
+ sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_TSDR_MT | RTC_TSDR_MU)) >> RTC_TSDR_MU_Pos);
+ sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_TSDR_DT | RTC_TSDR_DU));
+ sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_TSDR_WDU)) >> RTC_TSDR_WDU_Pos);
+
+ /* Check the input parameters format */
+ if (Format == RTC_FORMAT_BIN)
+ {
+ /* Convert the TimeStamp structure parameters to Binary format */
+ sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);
+ sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes);
+ sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds);
+
+ /* Convert the DateTimeStamp structure parameters to Binary format */
+ sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month);
+ sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date);
+ sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay);
+ }
+
+ /* Clear the TIMESTAMP Flags */
+ WRITE_REG(RTC->SCR, (RTC_SCR_CITSF | RTC_SCR_CTSF));
+
+ return HAL_OK;
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ * @brief Handle TimeStamp secure interrupt request.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+void HAL_RTCEx_TimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
+{
+ if (READ_BIT(RTC->SMISR, RTC_SMISR_TSMF) != 0U)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call TimeStampEvent registered Callback */
+ hrtc->TimeStampEventCallback(hrtc);
+#else
+ HAL_RTCEx_TimeStampEventCallback(hrtc);
+#endif /*(USE_HAL_RTC_REGISTER_CALLBACKS == 1)*/
+ /* Clearing flags after the Callback because the content of RTC_TSTR and RTC_TSDR are cleared when
+ TSF bit is reset.*/
+ WRITE_REG(RTC->SCR, RTC_SCR_CITSF | RTC_SCR_CTSF);
+ }
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+}
+
+#else /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/**
+ * @brief Handle TimeStamp non-secure interrupt request.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+void HAL_RTCEx_TimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
+{
+ if (READ_BIT(RTC->MISR, RTC_MISR_TSMF) != 0U)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call TimeStampEvent registered Callback */
+ hrtc->TimeStampEventCallback(hrtc);
+#else
+ HAL_RTCEx_TimeStampEventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
+ /* Clearing flags after the Callback because the content of RTC_TSTR and RTC_TSDR are cleared when
+ TSF bit is reset.*/
+ WRITE_REG(RTC->SCR, RTC_SCR_CITSF | RTC_SCR_CTSF);
+ }
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+}
+#endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/**
+ * @brief TimeStamp callback.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Handle TimeStamp polling request.
+ * @param hrtc RTC handle
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ while (READ_BIT(RTC->SR, RTC_SR_TSF) == 0U)
+ {
+ if (READ_BIT(RTC->SR, RTC_SR_TSOVF) != 0U)
+ {
+ /* Clear the TIMESTAMP OverRun Flag */
+ WRITE_REG(RTC->SCR, RTC_SCR_CTSOVF);
+
+ /* Change TIMESTAMP state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTCEx_Exported_Functions_Group2
+ * @brief RTC Wake-up functions
+ *
+@verbatim
+ ===============================================================================
+ ##### RTC Wake-up functions #####
+ ===============================================================================
+
+ [..] This section provides functions allowing to configure Wake-up feature
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set wake up timer.
+ * @param hrtc RTC handle
+ * @param WakeUpCounter Wake up counter
+ * @param WakeUpClock Wake up clock
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
+{
+ uint32_t tickstart;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
+ assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Clear WUTE in RTC_CR to disable the wakeup timer */
+ CLEAR_BIT(RTC->CR, RTC_CR_WUTE);
+
+ /* Poll WUTWF until it is set in RTC_ICSR to make sure the access to wakeup autoreload
+ counter and to WUCKSEL[2:0] bits is allowed. This step must be skipped in
+ calendar initialization mode. */
+ if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U)
+ {
+ tickstart = HAL_GetTick();
+ while (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Configure the clock source */
+ MODIFY_REG(RTC->CR, RTC_CR_WUCKSEL, (uint32_t)WakeUpClock);
+
+ /* Configure the Wakeup Timer counter */
+ WRITE_REG(RTC->WUTR, (uint32_t)WakeUpCounter);
+
+ /* Enable the Wakeup Timer */
+ SET_BIT(RTC->CR, RTC_CR_WUTE);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set wake up timer with interrupt.
+ * @param hrtc RTC handle
+ * @param WakeUpCounter Wake up counter
+ * @param WakeUpClock Wake up clock
+ * @param WakeUpAutoClr Wake up auto clear value (look at WUTOCLR in reference manual)
+ * - No effect if WakeUpAutoClr is set to zero
+ * - This feature is meaningful in case of Low power mode to avoid any RTC software execution
+ * after Wake Up.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock,
+ uint32_t WakeUpAutoClr)
+{
+ uint32_t tickstart;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
+ assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
+ /* (0x0000<=WUTOCLR<=WUT) */
+ assert_param(WakeUpAutoClr <= WakeUpCounter);
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Clear WUTE in RTC_CR to disable the wakeup timer */
+ CLEAR_BIT(RTC->CR, RTC_CR_WUTE);
+
+ /* Clear flag Wake-Up */
+ WRITE_REG(RTC->SCR, RTC_SCR_CWUTF);
+
+ /* Poll WUTWF until it is set in RTC_ICSR to make sure the access to wakeup autoreload
+ counter and to WUCKSEL[2:0] bits is allowed. This step must be skipped in
+ calendar initialization mode. */
+ if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U)
+ {
+ tickstart = HAL_GetTick();
+ while (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Configure the Wakeup Timer counter and auto clear value */
+ WRITE_REG(RTC->WUTR, (uint32_t)(WakeUpCounter | (WakeUpAutoClr << RTC_WUTR_WUTOCLR_Pos)));
+
+ /* Configure the clock source */
+ MODIFY_REG(RTC->CR, RTC_CR_WUCKSEL, (uint32_t)WakeUpClock);
+
+ /* Configure the Interrupt in the RTC_CR register and Enable the Wakeup Timer*/
+ SET_BIT(RTC->CR, (RTC_CR_WUTIE | RTC_CR_WUTE));
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivate wake up timer counter.
+ * @param hrtc RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
+{
+ uint32_t tickstart;
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Disable the Wakeup Timer */
+ /* In case of interrupt mode is used, the interrupt source must disabled */
+ CLEAR_BIT(RTC->CR, (RTC_CR_WUTE | RTC_CR_WUTIE));
+
+ tickstart = HAL_GetTick();
+ /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
+ while (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get wake up timer counter.
+ * @param hrtc RTC handle
+ * @retval Counter value
+ */
+uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
+{
+ UNUSED(hrtc);
+ /* Get the counter value */
+ return (uint32_t)(READ_BIT(RTC->WUTR, RTC_WUTR_WUT));
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ * @brief Handle Wake Up Timer secure interrupt request.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
+{
+ if ((RTC->SMISR & RTC_SMISR_WUTMF) != 0u)
+ {
+ /* Immediately clear flags */
+ WRITE_REG(RTC->SCR, RTC_SCR_CWUTF);
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call wake up timer registered Callback */
+ hrtc->WakeUpTimerEventCallback(hrtc);
+#else
+ HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
+ }
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+}
+
+#else /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/**
+ * @brief Handle Wake Up Timer non-secure interrupt request.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
+{
+ /* Get the pending status of the WAKEUPTIMER Interrupt */
+ if (READ_BIT(RTC->MISR, RTC_MISR_WUTMF) != 0U)
+ {
+ /* Clear the WAKEUPTIMER interrupt pending bit */
+ WRITE_REG(RTC->SCR, RTC_SCR_CWUTF);
+
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call WakeUpTimerEvent registered Callback */
+ hrtc->WakeUpTimerEventCallback(hrtc);
+#else
+ /* WAKEUPTIMER callback */
+ HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+ }
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+}
+#endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/**
+ * @brief Wake Up Timer callback.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file
+ */
+}
+
+
+/**
+ * @brief Handle Wake Up Timer Polling.
+ * @param hrtc RTC handle
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ while (READ_BIT(RTC->SR, RTC_SR_WUTF) == 0U)
+ {
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear the WAKEUPTIMER Flag */
+ WRITE_REG(RTC->SCR, RTC_SCR_CWUTF);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup RTCEx_Exported_Functions_Group3
+ * @brief Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Write a data in a specified RTC Backup data register
+ (+) Read a data in a specified RTC Backup data register
+ (+) Set the Coarse calibration parameters.
+ (+) Deactivate the Coarse calibration parameters
+ (+) Set the Smooth calibration parameters.
+ (+) Set Low Power calibration parameter.
+ (+) Configure the Synchronization Shift Control Settings.
+ (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ (+) Enable the RTC reference clock detection.
+ (+) Disable the RTC reference clock detection.
+ (+) Enable the Bypass Shadow feature.
+ (+) Disable the Bypass Shadow feature.
+
+@endverbatim
+ * @{
+ */
+
+
+
+/**
+ * @brief Set the Smooth calibration parameters.
+ * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses
+ * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field
+ * SmoothCalibMinusPulsesValue must be equal to 0.
+ * @param hrtc RTC handle
+ * @param SmoothCalibPeriod Select the Smooth Calibration Period.
+ * This parameter can be can be one of the following values :
+ * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
+ * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
+ * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
+ * @param SmoothCalibPlusPulses Select to Set or reset the CALP bit.
+ * This parameter can be one of the following values:
+ * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses.
+ * @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
+ * @param SmoothCalibMinusPulsesValue Select the value of CALM[8:0] bits.
+ * This parameter can be one any value from 0 to 0x000001FF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod,
+ uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
+{
+ uint32_t tickstart;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod));
+ assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses));
+ assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmoothCalibMinusPulsesValue));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* check if a calibration is pending*/
+ if (READ_BIT(RTC->ICSR, RTC_ICSR_RECALPF) != 0U)
+ {
+ tickstart = HAL_GetTick();
+
+ /* check if a calibration is pending*/
+ while (READ_BIT(RTC->ICSR, RTC_ICSR_RECALPF) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Configure the Smooth calibration settings */
+ MODIFY_REG(RTC->CALR, (RTC_CALR_CALP | RTC_CALR_CALW8 | RTC_CALR_CALW16 | RTC_CALR_CALM),
+ (uint32_t)(SmoothCalibPeriod | SmoothCalibPlusPulses | SmoothCalibMinusPulsesValue));
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Select the low power Calibration mode.
+ * @param hrtc: RTC handle
+ * @param LowPowerCalib: Low power Calibration mode.
+ * This parameter can be can be one of the following values :
+ * @arg RTC_LPCAL_SET: Low power mode.
+ * @arg RTC_LPCAL_RESET: High consumption mode.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetLowPowerCalib(RTC_HandleTypeDef *hrtc, uint32_t LowPowerCalib)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_LOW_POWER_CALIB(LowPowerCalib));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Configure the Smooth calibration settings */
+ MODIFY_REG(RTC->CALR, RTC_CALR_LPCAL, LowPowerCalib);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the Synchronization Shift Control Settings.
+ * @note When REFCKON is set, firmware must not write to Shift control register.
+ * @param hrtc RTC handle
+ * @param ShiftAdd1S Select to add or not 1 second to the time calendar.
+ * This parameter can be one of the following values:
+ * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
+ * @arg RTC_SHIFTADD1S_RESET: No effect.
+ * @param ShiftSubFS Select the number of Second Fractions to substitute.
+ * This parameter can be one any value from 0 to 0x7FFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
+{
+ uint32_t tickstart;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S));
+ assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ tickstart = HAL_GetTick();
+
+ /* Wait until the shift is completed*/
+ while (READ_BIT(RTC->ICSR, RTC_ICSR_SHPF) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check if the reference clock detection is disabled */
+ if (READ_BIT(RTC->CR, RTC_CR_REFCKON) == 0U)
+ {
+ /* Configure the Shift settings */
+ MODIFY_REG(RTC->SHIFTR, RTC_SHIFTR_SUBFS, (uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S));
+
+ /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+ if (READ_BIT(RTC->CR, RTC_CR_BYPSHAD) == 0U)
+ {
+ if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+ else
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ * @param hrtc RTC handle
+ * @param CalibOutput Select the Calibration output Selection .
+ * This parameter can be one of the following values:
+ * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
+ * @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Configure the RTC_CR register */
+ MODIFY_REG(RTC->CR, RTC_CR_COSEL, CalibOutput);
+
+ /* Enable calibration output */
+ SET_BIT(RTC->CR, RTC_CR_COE);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ * @param hrtc RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc)
+{
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Disable calibration output */
+ CLEAR_BIT(RTC->CR, RTC_CR_COE);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable the RTC reference clock detection.
+ * @param hrtc RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc)
+{
+ HAL_StatusTypeDef status;
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Enter Initialization mode */
+ status = RTC_EnterInitMode(hrtc);
+ if (status == HAL_OK)
+ {
+ /* Enable clockref detection */
+ SET_BIT(RTC->CR, RTC_CR_REFCKON);
+
+ /* Exit Initialization mode */
+ status = RTC_ExitInitMode(hrtc);
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ if (status == HAL_OK)
+ {
+ hrtc->State = HAL_RTC_STATE_READY;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return status;
+}
+
+/**
+ * @brief Disable the RTC reference clock detection.
+ * @param hrtc RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc)
+{
+ HAL_StatusTypeDef status;
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Enter Initialization mode */
+ status = RTC_EnterInitMode(hrtc);
+ if (status == HAL_OK)
+ {
+ /* Disable clockref detection */
+ CLEAR_BIT(RTC->CR, RTC_CR_REFCKON);
+
+ /* Exit Initialization mode */
+ status = RTC_ExitInitMode(hrtc);
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ if (status == HAL_OK)
+ {
+ hrtc->State = HAL_RTC_STATE_READY;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return status;
+}
+
+/**
+ * @brief Enable the Bypass Shadow feature.
+ * @note When the Bypass Shadow is enabled the calendar value are taken
+ * directly from the Calendar counter.
+ * @param hrtc RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc)
+{
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Set the BYPSHAD bit */
+ SET_BIT(RTC->CR, RTC_CR_BYPSHAD);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the Bypass Shadow feature.
+ * @note When the Bypass Shadow is enabled the calendar value are taken
+ * directly from the Calendar counter.
+ * @param hrtc RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc)
+{
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Reset the BYPSHAD bit */
+ CLEAR_BIT(RTC->CR, RTC_CR_BYPSHAD);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Increment Monotonic counter.
+ * @param hrtc RTC handle
+ * @param Instance Monotonic counter Instance
+ * This parameter can be can be one of the following values :
+ * @arg RTC_MONOTONIC_COUNTER_1
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterIncrement(RTC_HandleTypeDef *hrtc, uint32_t Instance)
+{
+ UNUSED(hrtc);
+ UNUSED(Instance);
+ /* This register is read-only only and is incremented by one when a write access is done to this
+ register. This register cannot roll-over and is frozen when reaching the maximum value. */
+ CLEAR_REG(TAMP->COUNTR);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Monotonic counter incrementation.
+ * @param hrtc RTC handle
+ * @param Instance Monotonic counter Instance
+ * This parameter can be can be one of the following values :
+ * @arg RTC_MONOTONIC_COUNTER_1
+ * @param Value Pointer to the counter monotonic counter value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(RTC_HandleTypeDef *hrtc, uint32_t Instance, uint32_t *Value)
+{
+ UNUSED(hrtc);
+ UNUSED(Instance);
+
+ /* This register is read-only only and is incremented by one when a write access is done to this
+ register. This register cannot roll-over and is frozen when reaching the maximum value. */
+ *Value = READ_REG(TAMP->COUNTR);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set SSR Underflow detection with Interrupt.
+ * @param hrtc RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetSSRU_IT(RTC_HandleTypeDef *hrtc)
+{
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Enable IT SSRU */
+ __HAL_RTC_SSRU_ENABLE_IT(hrtc, RTC_IT_SSRU);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivate SSR Underflow.
+ * @param hrtc RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateSSRU(RTC_HandleTypeDef *hrtc)
+{
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* In case of interrupt mode is used, the interrupt source must disabled */
+ __HAL_RTC_SSRU_DISABLE_IT(hrtc, RTC_IT_TS);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ * @brief Handle SSR underflow interrupt request.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+void HAL_RTCEx_SSRUIRQHandler(RTC_HandleTypeDef *hrtc)
+{
+ if ((RTC->SMISR & RTC_SMISR_SSRUMF) != 0u)
+ {
+ /* Immediately clear flags */
+ RTC->SCR = RTC_SCR_CSSRUF;
+
+ /* SSRU callback */
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call SSRUEvent registered Callback */
+ hrtc->SSRUEventCallback(hrtc);
+#else
+ HAL_RTCEx_SSRUEventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+
+ }
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+}
+#else
+/**
+ * @brief Handle SSR underflow interrupt request.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+void HAL_RTCEx_SSRUIRQHandler(RTC_HandleTypeDef *hrtc)
+{
+ if ((RTC->MISR & RTC_MISR_SSRUMF) != 0u)
+ {
+ /* Immediately clear flags */
+ RTC->SCR = RTC_SCR_CSSRUF;
+
+ /* SSRU callback */
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call SSRUEvent registered Callback */
+ hrtc->SSRUEventCallback(hrtc);
+#else
+ HAL_RTCEx_SSRUEventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
+ }
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/**
+ * @brief SSR underflow callback.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+__weak void HAL_RTCEx_SSRUEventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_SSRUEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTCEx_Exported_Functions_Group4
+ * @brief Extended features functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended features functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) RTC Alarm B callback
+ (+) RTC Poll for Alarm B request
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Alarm B callback.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Handle Alarm B Polling request.
+ * @param hrtc RTC handle
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ while (READ_BIT(RTC->SR, RTC_SR_ALRBF) == 0U)
+ {
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear the Alarm Flag */
+ WRITE_REG(RTC->SCR, RTC_SCR_CALRBF);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTCEx_Exported_Functions_Group5
+ * @brief Extended RTC Tamper functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Tamper functions #####
+ ==============================================================================
+ [..]
+ (+) Before calling any tamper or internal tamper function, you have to call first
+ HAL_RTC_Init() function.
+ (+) In that ine you can select to output tamper event on RTC pin.
+ [..]
+ (+) Enable the Tamper and configure the Tamper filter count, trigger Edge
+ or Level according to the Tamper filter (if equal to 0 Edge else Level)
+ value, sampling frequency, NoErase, MaskFlag, precharge or discharge and
+ Pull-UP, timestamp using the HAL_RTCEx_SetTamper() function.
+ You can configure Tamper with interrupt mode using HAL_RTCEx_SetTamper_IT() function.
+ (+) The default configuration of the Tamper erases the backup registers. To avoid
+ erase, enable the NoErase field on the TAMP_TAMPCR register.
+ [..]
+ (+) Enable Internal Tamper and configure it with interrupt, timestamp using
+ the HAL_RTCEx_SetInternalTamper() function.
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Set Tamper
+ * @param hrtc RTC handle
+ * @param sTamper Pointer to Tamper Structure.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
+{
+ uint32_t tmpreg;
+
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* Check the parameters */
+ assert_param(IS_RTC_TAMPER(sTamper->Tamper));
+ assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
+ assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase));
+ assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));
+ assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
+ /* Mask flag only supported by TAMPER 1, 2 and 3 */
+ assert_param(!((sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) && (sTamper->Tamper > RTC_TAMPER_3)));
+ assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
+ assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
+ assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
+ assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
+ /* Trigger and Filter have exclusive configurations */
+ assert_param(((sTamper->Filter != RTC_TAMPERFILTER_DISABLE) && \
+ ((sTamper->Trigger == RTC_TAMPERTRIGGER_LOWLEVEL) || \
+ (sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL))) \
+ || ((sTamper->Filter == RTC_TAMPERFILTER_DISABLE) && \
+ ((sTamper->Trigger == RTC_TAMPERTRIGGER_RISINGEDGE) || \
+ (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE))));
+
+ /* Configuration register 2 */
+ tmpreg = READ_REG(TAMP->CR2);
+ tmpreg &= ~((sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos) | \
+ (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos));
+
+ if ((sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL) || (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE))
+ {
+ tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos);
+ }
+
+ if (sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)
+ {
+ tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos);
+ }
+
+ if (sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
+ {
+ tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos);
+ }
+ WRITE_REG(TAMP->CR2, tmpreg);
+
+ /* Filter control register */
+ WRITE_REG(TAMP->FLTCR, sTamper->Filter | sTamper->SamplingFrequency | sTamper->PrechargeDuration | \
+ sTamper->TamperPullUp);
+
+ /* Timestamp on tamper */
+ if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sTamper->TimeStampOnTamperDetection)
+ {
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+ MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sTamper->TimeStampOnTamperDetection);
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ }
+
+ /* Control register 1 */
+ SET_BIT(TAMP->CR1, sTamper->Tamper);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Set Tamper in IT mode
+ * @param hrtc RTC handle
+ * @param sTamper Pointer to Tamper Structure.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
+{
+ uint32_t tmpreg;
+
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* Check the parameters */
+ assert_param(IS_RTC_TAMPER(sTamper->Tamper));
+ assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
+ assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase));
+ assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));
+ assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
+ assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
+ assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
+ assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
+ assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
+
+ /* Configuration register 2 */
+ tmpreg = READ_REG(TAMP->CR2);
+ tmpreg &= ~((sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos) | \
+ (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos));
+
+ if (sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
+ {
+ tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos);
+ }
+
+ if (sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)
+ {
+ /* Feature only supported by TAMPER 1, 2 and 3 */
+ if (sTamper->Tamper < RTC_TAMPER_4)
+ {
+ tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ if (sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
+ {
+ tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos);
+ }
+ WRITE_REG(TAMP->CR2, tmpreg);
+
+ /* Filter control register */
+ WRITE_REG(TAMP->FLTCR, sTamper->Filter | sTamper->SamplingFrequency | sTamper->PrechargeDuration | \
+ sTamper->TamperPullUp);
+
+ /* Timestamp on tamper */
+ if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sTamper->TimeStampOnTamperDetection)
+ {
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+ MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sTamper->TimeStampOnTamperDetection);
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ }
+
+ /* Interrupt enable register */
+ SET_BIT(TAMP->IER, sTamper->Tamper);
+
+ /* Control register 1 */
+ SET_BIT(TAMP->CR1, sTamper->Tamper);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivate Tamper.
+ * @param hrtc RTC handle
+ * @param Tamper Selected tamper pin.
+ * This parameter can be a combination of the following values:
+ * @arg RTC_TAMPER_1
+ * @arg RTC_TAMPER_2
+ * @arg RTC_TAMPER_3
+ * @arg RTC_TAMPER_4
+ * @arg RTC_TAMPER_5
+ * @arg RTC_TAMPER_6
+ * @arg RTC_TAMPER_7
+ * @arg RTC_TAMPER_8
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)
+{
+ UNUSED(hrtc);
+ assert_param(IS_RTC_TAMPER(Tamper));
+
+ /* Disable the selected Tamper pin */
+ CLEAR_BIT(TAMP->CR1, Tamper);
+
+ /* Clear tamper mask/noerase/trigger configuration */
+ CLEAR_BIT(TAMP->CR2, (Tamper << TAMP_CR2_TAMP1TRG_Pos) | (Tamper << TAMP_CR2_TAMP1MSK_Pos) | \
+ (Tamper << TAMP_CR2_TAMP1NOERASE_Pos));
+
+ /* Clear tamper interrupt mode configuration */
+ CLEAR_BIT(TAMP->IER, Tamper);
+
+ /* Clear tamper interrupt and event flags (WO register) */
+ WRITE_REG(TAMP->SCR, Tamper);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set all active Tampers at the same time.
+ * @param hrtc RTC handle
+ * @param sAllTamper Pointer to active Tamper Structure.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, RTC_ActiveTampersTypeDef *sAllTamper)
+{
+ uint32_t IER;
+ uint32_t CR1;
+ uint32_t CR2;
+ uint32_t ATCR1;
+ uint32_t ATCR2;
+ uint32_t CR;
+ uint32_t i;
+ uint32_t tickstart;
+
+#ifdef USE_FULL_ASSERT
+ for (i = 0; i < RTC_TAMP_NB; i++)
+ {
+ assert_param(IS_RTC_TAMPER_ERASE_MODE(sAllTamper->TampInput[i].NoErase));
+ assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sAllTamper->TampInput[i].MaskFlag));
+ /* Mask flag only supported by TAMPER 1, 2 and 3 */
+ assert_param(!((sAllTamper->TampInput[i].MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) && (i > RTC_TAMPER_3)));
+ }
+ assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sAllTamper->TimeStampOnTamperDetection));
+#endif /* USE_FULL_ASSERT */
+
+ /* Active Tampers must not be already enabled */
+ if (READ_BIT(TAMP->ATOR, TAMP_ATOR_INITS) != 0U)
+ {
+ /* Disable all actives tampers with HAL_RTCEx_DeactivateActiveTampers.
+ No need to check return value because it returns always HAL_OK */
+ (void) HAL_RTCEx_DeactivateActiveTampers(hrtc);
+ }
+
+ /* Set TimeStamp on tamper detection */
+ CR = READ_REG(RTC->CR);
+ if ((CR & RTC_CR_TAMPTS) != (sAllTamper->TimeStampOnTamperDetection))
+ {
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+ MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sAllTamper->TimeStampOnTamperDetection);
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ }
+
+ CR1 = READ_REG(TAMP->CR1);
+ CR2 = READ_REG(TAMP->CR2);
+ ATCR2 = 0U;
+ IER = READ_REG(TAMP->IER);
+
+ /* Set common parameters */
+ ATCR1 = (sAllTamper->ActiveFilter | (sAllTamper->ActiveOutputChangePeriod << TAMP_ATCR1_ATPER_Pos) | \
+ sAllTamper->ActiveAsyncPrescaler);
+
+ /* Set specific parameters for each active tamper inputs if enable */
+ for (i = 0; i < RTC_TAMP_NB; i++)
+ {
+ if (sAllTamper->TampInput[i].Enable != RTC_ATAMP_DISABLE)
+ {
+ CR1 |= (TAMP_CR1_TAMP1E << i);
+ ATCR1 |= (TAMP_ATCR1_TAMP1AM << i);
+
+ if (sAllTamper->TampInput[i].Interrupt != RTC_ATAMP_INTERRUPT_DISABLE)
+ {
+ /* Interrupt enable register */
+ IER |= (TAMP_IER_TAMP1IE << i);
+ }
+
+ if (sAllTamper->TampInput[i].MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)
+ {
+ CR2 |= (TAMP_CR2_TAMP1MSK << i);
+ }
+
+ if (sAllTamper->TampInput[i].NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
+ {
+ CR2 |= (TAMP_CR2_TAMP1NOERASE << i);
+ }
+
+ /* Configure ATOSELx[] in case of output sharing */
+ ATCR2 |= sAllTamper->TampInput[i].Output << ((3u * i) + TAMP_ATCR2_ATOSEL1_Pos);
+
+ if (i != sAllTamper->TampInput[i].Output)
+ {
+ ATCR1 |= TAMP_ATCR1_ATOSHARE;
+ }
+ }
+ }
+
+ WRITE_REG(TAMP->IER, IER);
+ WRITE_REG(TAMP->IER, IER);
+ WRITE_REG(TAMP->ATCR1, ATCR1);
+ WRITE_REG(TAMP->ATCR2, ATCR2);
+ WRITE_REG(TAMP->CR2, CR2);
+ WRITE_REG(TAMP->CR1, CR1);
+
+ /* Write seed */
+ for (i = 0; i < RTC_ATAMP_SEED_NB_UINT32; i++)
+ {
+ WRITE_REG(TAMP->ATSEEDR, sAllTamper->Seed[i]);
+ }
+
+ /* Wait till RTC SEEDF flag is set and if Time out is reached exit */
+ tickstart = HAL_GetTick();
+ while (READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) != 0u)
+ {
+ if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get active Tampers configuration.
+ * @param sAllTamper Pointer to active Tamper Structure.
+ * @retval none
+ */
+void HAL_RTCEx_GetActiveTampers(RTC_ActiveTampersTypeDef *sAllTamper)
+{
+ uint32_t i ;
+
+ sAllTamper->ActiveFilter = (uint32_t)(TAMP->ATCR1 & TAMP_ATCR1_FLTEN);
+ sAllTamper->ActiveOutputChangePeriod = (uint32_t)((TAMP->ATCR1 & TAMP_ATCR1_ATPER) >> TAMP_ATCR1_ATPER_Pos);
+ sAllTamper->ActiveAsyncPrescaler = (uint32_t)(TAMP->ATCR1 & TAMP_ATCR1_ATCKSEL);
+ sAllTamper->TimeStampOnTamperDetection = (uint32_t)(RTC->CR & RTC_CR_TAMPTS);
+ /* Set specific parameters for each active tamper inputs if enable */
+ for (i = 0; i < RTC_TAMP_NB; i++)
+ {
+ sAllTamper->TampInput[i].Enable = (uint32_t)(((TAMP->CR1 & (TAMP_CR1_TAMP1E << i))) >> i);
+ sAllTamper->TampInput[i].Interrupt = (uint32_t)(((TAMP->IER & (TAMP_IER_TAMP1IE << i))) >> i);
+ sAllTamper->TampInput[i].MaskFlag = (uint32_t)(((TAMP->CR2 & (TAMP_CR2_TAMP1MSK << i))) >> i);
+ sAllTamper->TampInput[i].NoErase = (uint32_t)(((TAMP->CR2 & (TAMP_CR2_TAMP1NOERASE << i))) >> i);
+ sAllTamper->TampInput[i].Output = (uint32_t)(((TAMP->ATCR2 & (TAMP_ATCR2_ATOSEL1 << ((3u * i)))) \
+ >> ((3u * i) + TAMP_ATCR2_ATOSEL1_Pos)));
+ }
+}
+
+/**
+ * @brief Write a new seed. Active tamper must be enabled.
+ * @param hrtc RTC handle
+ * @param pSeed Pointer to active tamper seed values.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, uint32_t *pSeed)
+{
+ uint32_t i;
+ uint32_t tickstart;
+
+ /* Active Tampers must be enabled */
+ if (READ_BIT(TAMP->ATOR, TAMP_ATOR_INITS) == 0U)
+ {
+ return HAL_ERROR;
+ }
+
+ for (i = 0; i < RTC_ATAMP_SEED_NB_UINT32; i++)
+ {
+ WRITE_REG(TAMP->ATSEEDR, pSeed[i]);
+ }
+
+ /* Wait till RTC SEEDF flag is set and if Time out is reached exit */
+ tickstart = HAL_GetTick();
+ while (READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Lock the Boot hardware Key
+ * @param hrtc RTC handle
+ * @note The backup registers from TAMP_BKP0R to TAMP_BKP7R cannot be accessed neither in
+ * read nor in write (they are read as 0 and write ignore).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetBoothardwareKey(RTC_HandleTypeDef *hrtc)
+{
+ UNUSED(hrtc);
+ WRITE_REG(TAMP->SECCFGR, TAMP_SECCFGR_BHKLOCK);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivate all Active Tampers at the same time.
+ * @param hrtc RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateActiveTampers(RTC_HandleTypeDef *hrtc)
+{
+ /* Get Active tampers */
+ uint32_t ATamp_mask = READ_BIT(TAMP->ATCR1, TAMP_ALL);
+
+ UNUSED(hrtc);
+ /* Disable all actives tampers but not passives tampers */
+ CLEAR_BIT(TAMP->CR1, ATamp_mask);
+ /* Disable no erase and mask */
+ CLEAR_BIT(TAMP->CR2, (ATamp_mask | ((ATamp_mask & (TAMP_ATCR1_TAMP1AM | TAMP_ATCR1_TAMP2AM | TAMP_ATCR1_TAMP3AM))\
+ << TAMP_CR2_TAMP1MSK_Pos)));
+
+ /* Clear tamper interrupt and event flags (WO register) of all actives tampers but not passives tampers */
+ WRITE_REG(TAMP->SCR, ATamp_mask);
+
+ /* Clear all active tampers interrupt mode configuration but not passives tampers */
+ CLEAR_BIT(TAMP->IER, ATamp_mask);
+
+ CLEAR_BIT(TAMP->ATCR1, TAMP_ALL | TAMP_ATCR1_ATCKSEL | TAMP_ATCR1_ATPER | \
+ TAMP_ATCR1_ATOSHARE | TAMP_ATCR1_FLTEN);
+
+ CLEAR_BIT(TAMP->ATCR2, TAMP_ATCR2_ATOSEL1 | TAMP_ATCR2_ATOSEL2 | TAMP_ATCR2_ATOSEL3 | TAMP_ATCR2_ATOSEL4 |
+ TAMP_ATCR2_ATOSEL5 | TAMP_ATCR2_ATOSEL6 | TAMP_ATCR2_ATOSEL7 | TAMP_ATCR2_ATOSEL8);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Tamper event polling.
+ * @param hrtc RTC handle
+ * @param Tamper Selected tamper pin.
+ * This parameter can be a combination of the following values:
+ * @arg RTC_TAMPER_1
+ * @arg RTC_TAMPER_2
+ * @arg RTC_TAMPER_3
+ * @arg RTC_TAMPER_4
+ * @arg RTC_TAMPER_5
+ * @arg RTC_TAMPER_6
+ * @arg RTC_TAMPER_7
+ * @arg RTC_TAMPER_8
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_PollForTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t Tamper, uint32_t Timeout)
+{
+ UNUSED(hrtc);
+ assert_param(IS_RTC_TAMPER(Tamper));
+
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Get the status of the Interrupt */
+ while (READ_BIT(TAMP->SR, Tamper) != Tamper)
+ {
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear the Tamper Flag */
+ WRITE_REG(TAMP->SCR, Tamper);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Set Internal Tamper
+ * @param hrtc RTC handle
+ * @param sIntTamper Pointer to Internal Tamper Structure.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* Check the parameters */
+ assert_param(IS_RTC_INTERNAL_TAMPER(sIntTamper->IntTamper));
+ assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sIntTamper->TimeStampOnTamperDetection));
+ assert_param(IS_RTC_TAMPER_ERASE_MODE(sIntTamper->NoErase));
+
+ /* timestamp on internal tamper */
+ if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sIntTamper->TimeStampOnTamperDetection)
+ {
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+ MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sIntTamper->TimeStampOnTamperDetection);
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ }
+
+ if (sIntTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
+ {
+ /* Control register 3 */
+ SET_BIT(TAMP->CR3, (sIntTamper->IntTamper >> (TAMP_CR1_ITAMP1E_Pos - TAMP_CR3_ITAMP1NOER_Pos)));
+ }
+ else
+ {
+ CLEAR_BIT(TAMP->CR3, (sIntTamper->IntTamper >> (TAMP_CR1_ITAMP1E_Pos - TAMP_CR3_ITAMP1NOER_Pos)));
+ }
+
+ /* Control register 1 */
+ SET_BIT(TAMP->CR1, sIntTamper->IntTamper);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get Internal Tamper Configuration
+ * @param sIntTamper Pointer to Internal Tamper Structure.
+ * @retval HAL status
+ */
+void HAL_RTCEx_GetInternalTampers(RTC_InternalTamperTypeDef *sIntTamper)
+{
+ sIntTamper->IntTamper = (uint32_t)(TAMP->CR1 & (RTC_INT_TAMPER_ALL));
+ sIntTamper->TimeStampOnTamperDetection = (uint32_t)(RTC->CR & RTC_CR_TAMPTS);
+ if ((uint32_t)(TAMP->CR3 & (sIntTamper->IntTamper >> (TAMP_CR1_ITAMP1E_Pos - TAMP_CR3_ITAMP1NOER_Pos))) != 0U)
+ {
+ sIntTamper->NoErase = RTC_TAMPER_ERASE_BACKUP_DISABLE;
+ }
+ else
+ {
+ sIntTamper->NoErase = RTC_TAMPER_ERASE_BACKUP_ENABLE;
+ }
+}
+
+/**
+ * @brief Set Internal Tamper in interrupt mode
+ * @param hrtc RTC handle
+ * @param sIntTamper Pointer to Internal Tamper Structure.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* Check the parameters */
+ assert_param(IS_RTC_INTERNAL_TAMPER(sIntTamper->IntTamper));
+ assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sIntTamper->TimeStampOnTamperDetection));
+ assert_param(IS_RTC_TAMPER_ERASE_MODE(sIntTamper->NoErase));
+
+ /* timestamp on internal tamper */
+ if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sIntTamper->TimeStampOnTamperDetection)
+ {
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+ MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sIntTamper->TimeStampOnTamperDetection);
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ }
+
+ /* Interrupt enable register */
+ SET_BIT(TAMP->IER, sIntTamper->IntTamper);
+
+ if (sIntTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
+ {
+ /* Control register 3 */
+ SET_BIT(TAMP->CR3, (sIntTamper->IntTamper >> (TAMP_CR1_ITAMP1E_Pos - TAMP_CR3_ITAMP1NOER_Pos)));
+ }
+ else
+ {
+ CLEAR_BIT(TAMP->CR3, (sIntTamper->IntTamper >> (TAMP_CR1_ITAMP1E_Pos - TAMP_CR3_ITAMP1NOER_Pos)));
+ }
+
+ /* Control register 1 */
+ SET_BIT(TAMP->CR1, sIntTamper->IntTamper);
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivate Internal Tamper.
+ * @param hrtc RTC handle
+ * @param IntTamper Selected internal tamper event.
+ * This parameter can be any combination of existing internal tampers.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(RTC_HandleTypeDef *hrtc, uint32_t IntTamper)
+{
+ UNUSED(hrtc);
+ assert_param(IS_RTC_INTERNAL_TAMPER(IntTamper));
+
+ /* Disable the selected Tamper pin */
+ CLEAR_BIT(TAMP->CR1, IntTamper);
+
+ /* Clear internal tamper interrupt mode configuration */
+ CLEAR_BIT(TAMP->IER, IntTamper);
+
+ /* Clear internal tamper interrupt */
+ WRITE_REG(TAMP->SCR, IntTamper);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Internal Tamper event polling.
+ * @param hrtc RTC handle
+ * @param IntTamper selected tamper.
+ * This parameter can be any combination of existing internal tampers.
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t IntTamper, uint32_t Timeout)
+{
+ UNUSED(hrtc);
+ assert_param(IS_RTC_INTERNAL_TAMPER(IntTamper));
+
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Get the status of the Interrupt */
+ while (READ_BIT(TAMP->SR, IntTamper) != IntTamper)
+ {
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear the Tamper Flag */
+ WRITE_REG(TAMP->SCR, IntTamper);
+
+ return HAL_OK;
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/** @brief Handle Tamper secure interrupt request.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc)
+{
+ uint32_t tmp;
+
+ /* Get secure interrupt status */
+ tmp = READ_REG(TAMP->SMISR);
+
+ /* Immediately clear flags */
+ WRITE_REG(TAMP->SCR, tmp);
+
+ /* Check Tamper1 status */
+ if ((tmp & RTC_TAMPER_1) == RTC_TAMPER_1)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Tamper 1 Event registered secure Callback */
+ hrtc->Tamper1EventCallback(hrtc);
+#else
+ /* Tamper1 secure callback */
+ HAL_RTCEx_Tamper1EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
+ }
+
+ /* Check Tamper2 status */
+ if ((tmp & RTC_TAMPER_2) == RTC_TAMPER_2)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Tamper 2 Event registered secure Callback */
+ hrtc->Tamper2EventCallback(hrtc);
+#else
+ /* Tamper2 secure callback */
+ HAL_RTCEx_Tamper2EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
+ }
+
+ /* Check Tamper3 status */
+ if ((tmp & RTC_TAMPER_3) == RTC_TAMPER_3)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Tamper 3 Event registered secure Callback */
+ hrtc->Tamper3EventCallback(hrtc);
+#else
+ /* Tamper3 secure callback */
+ HAL_RTCEx_Tamper3EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
+ }
+
+ /* Check Tamper4 status */
+ if ((tmp & RTC_TAMPER_4) == RTC_TAMPER_4)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Tamper 4 Event registered secure Callback */
+ hrtc->Tamper4EventCallback(hrtc);
+#else
+ /* Tamper4 secure callback */
+ HAL_RTCEx_Tamper4EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
+ }
+
+ /* Check Tamper5 status */
+ if ((tmp & RTC_TAMPER_5) == RTC_TAMPER_5)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Tamper 5 Event registered secure Callback */
+ hrtc->Tamper5EventCallback(hrtc);
+#else
+ /* Tamper5 secure callback */
+ HAL_RTCEx_Tamper5EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
+ }
+
+ /* Check Tamper6 status */
+ if ((tmp & RTC_TAMPER_6) == RTC_TAMPER_6)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Tamper 6 Event registered secure Callback */
+ hrtc->Tamper6EventCallback(hrtc);
+#else
+ /* Tamper6 secure callback */
+ HAL_RTCEx_Tamper6EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
+ }
+
+ /* Check Tamper7 status */
+ if ((tmp & RTC_TAMPER_7) == RTC_TAMPER_7)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Tamper 7 Event registered secure Callback */
+ hrtc->Tamper7EventCallback(hrtc);
+#else
+ /* Tamper7 secure callback */
+ HAL_RTCEx_Tamper7EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
+ }
+
+ /* Check Tamper8 status */
+ if ((tmp & RTC_TAMPER_8) == RTC_TAMPER_8)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Tamper 8 Event registered secure Callback */
+ hrtc->Tamper8EventCallback(hrtc);
+#else
+ /* Tamper8 secure callback */
+ HAL_RTCEx_Tamper8EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
+ }
+
+ /* Check Internal Tamper1 status */
+ if ((tmp & RTC_INT_TAMPER_1) == RTC_INT_TAMPER_1)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Internal Tamper 1 Event registered secure Callback */
+ hrtc->InternalTamper1EventCallback(hrtc);
+#else
+ /* Internal Tamper1 secure callback */
+ HAL_RTCEx_InternalTamper1EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
+ }
+
+ /* Check Internal Tamper2 status */
+ if ((tmp & RTC_INT_TAMPER_2) == RTC_INT_TAMPER_2)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Internal Tamper 2 Event registered secure Callback */
+ hrtc->InternalTamper2EventCallback(hrtc);
+#else
+ /* Internal Tamper2 secure callback */
+ HAL_RTCEx_InternalTamper2EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
+ }
+
+ /* Check Internal Tamper3 status */
+ if ((tmp & RTC_INT_TAMPER_3) == RTC_INT_TAMPER_3)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Internal Tamper 3 Event registered secure Callback */
+ hrtc->InternalTamper3EventCallback(hrtc);
+#else
+ /* Internal Tamper3 secure callback */
+ HAL_RTCEx_InternalTamper3EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
+ }
+
+ /* Check Internal Tamper5 status */
+ if ((tmp & RTC_INT_TAMPER_5) == RTC_INT_TAMPER_5)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Internal Tamper 5 Event registered secure Callback */
+ hrtc->InternalTamper5EventCallback(hrtc);
+#else
+ /* Internal Tamper5 secure callback */
+ HAL_RTCEx_InternalTamper5EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
+ }
+ /* Check Internal Tamper6 status */
+ if ((tmp & RTC_INT_TAMPER_6) == RTC_INT_TAMPER_6)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Internal Tamper 6 Event registered secure Callback */
+ hrtc->InternalTamper6EventCallback(hrtc);
+#else
+ /* Internal Tamper6 secure callback */
+ HAL_RTCEx_InternalTamper6EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
+ }
+
+ /* Check Internal Tamper7 status */
+ if ((tmp & RTC_INT_TAMPER_7) == RTC_INT_TAMPER_7)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Internal Tamper 7 Event registered secure Callback */
+ hrtc->InternalTamper7EventCallback(hrtc);
+#else
+ /* Internal Tamper7 secure callback */
+ HAL_RTCEx_InternalTamper7EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
+ }
+
+ /* Check Internal Tamper8 status */
+ if ((tmp & RTC_INT_TAMPER_8) == RTC_INT_TAMPER_8)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Internal Tamper 8 Event registered secure Callback */
+ hrtc->InternalTamper8EventCallback(hrtc);
+#else
+ /* Internal Tamper8 secure callback */
+ HAL_RTCEx_InternalTamper8EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
+ }
+
+ /* Check Internal Tamper9 status */
+ if ((tmp & RTC_INT_TAMPER_9) == RTC_INT_TAMPER_9)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Internal Tamper 9 Event registered secure Callback */
+ hrtc->InternalTamper9EventCallback(hrtc);
+#else
+ /* Internal Tamper9 secure callback */
+ HAL_RTCEx_InternalTamper9EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
+ }
+
+ /* Check Internal Tamper11 status */
+ if ((tmp & RTC_INT_TAMPER_11) == RTC_INT_TAMPER_11)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Internal Tamper 11 Event registered secure Callback */
+ hrtc->InternalTamper11EventCallback(hrtc);
+#else
+ /* Internal Tamper11 secure callback */
+ HAL_RTCEx_InternalTamper11EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+ }
+
+ /* Check Internal Tamper12 status */
+ if ((tmp & RTC_INT_TAMPER_12) == RTC_INT_TAMPER_12)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Internal Tamper 12 Event registered secure Callback */
+ hrtc->InternalTamper12EventCallback(hrtc);
+#else
+ /* Internal Tamper 12 secure callback */
+ HAL_RTCEx_InternalTamper12EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+ }
+
+ /* Check Internal Tamper13 status */
+ if ((tmp & RTC_INT_TAMPER_13) == RTC_INT_TAMPER_13)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Internal Tamper 13 Event registered secure Callback */
+ hrtc->InternalTamper13EventCallback(hrtc);
+#else
+ /* Internal Tamper 13 secure callback */
+ HAL_RTCEx_InternalTamper13EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+ }
+}
+
+
+#else
+/**
+ * @brief Handle Tamper non-secure interrupt request.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc)
+{
+ /* Get interrupt status */
+ uint32_t tmp = READ_REG(TAMP->MISR);
+
+ /* Immediately clear flags */
+ WRITE_REG(TAMP->SCR, tmp);
+
+ /* Check Tamper1 status */
+ if ((tmp & RTC_TAMPER_1) == RTC_TAMPER_1)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Tamper 1 Event registered Callback */
+ hrtc->Tamper1EventCallback(hrtc);
+#else
+ /* Tamper1 callback */
+ HAL_RTCEx_Tamper1EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
+ }
+
+ /* Check Tamper2 status */
+ if ((tmp & RTC_TAMPER_2) == RTC_TAMPER_2)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Tamper 2 Event registered Callback */
+ hrtc->Tamper2EventCallback(hrtc);
+#else
+ /* Tamper2 callback */
+ HAL_RTCEx_Tamper2EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
+ }
+
+ /* Check Tamper3 status */
+ if ((tmp & RTC_TAMPER_3) == RTC_TAMPER_3)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Tamper 3 Event registered Callback */
+ hrtc->Tamper3EventCallback(hrtc);
+#else
+ /* Tamper3 callback */
+ HAL_RTCEx_Tamper3EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
+ }
+
+ /* Check Tamper4 status */
+ if ((tmp & RTC_TAMPER_4) == RTC_TAMPER_4)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Tamper 4 Event registered Callback */
+ hrtc->Tamper4EventCallback(hrtc);
+#else
+ /* Tamper4 callback */
+ HAL_RTCEx_Tamper4EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
+ }
+
+ /* Check Tamper5 status */
+ if ((tmp & RTC_TAMPER_5) == RTC_TAMPER_5)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Tamper 5 Event registered Callback */
+ hrtc->Tamper5EventCallback(hrtc);
+#else
+ /* Tamper5 callback */
+ HAL_RTCEx_Tamper5EventCallback(hrtc);
+#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
+ }
+
+ /* Check Tamper6 status */
+ if ((tmp & RTC_TAMPER_6) == RTC_TAMPER_6)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Tamper 6 Event registered Callback */
+ hrtc->Tamper6EventCallback(hrtc);
+#else
+ /* Tamper6 callback */
+ HAL_RTCEx_Tamper6EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
+ }
+
+ /* Check Tamper7 status */
+ if ((tmp & RTC_TAMPER_7) == RTC_TAMPER_7)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Tamper 7 Event registered Callback */
+ hrtc->Tamper7EventCallback(hrtc);
+#else
+ /* Tamper7 callback */
+ HAL_RTCEx_Tamper7EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
+ }
+
+ /* Check Tamper8 status */
+ if ((tmp & RTC_TAMPER_8) == RTC_TAMPER_8)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Tamper 8 Event registered Callback */
+ hrtc->Tamper8EventCallback(hrtc);
+#else
+ /* Tamper8 callback */
+ HAL_RTCEx_Tamper8EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
+ }
+
+ /* Check Internal Tamper1 status */
+ if ((tmp & RTC_INT_TAMPER_1) == RTC_INT_TAMPER_1)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Internal Tamper 1 Event registered Callback */
+ hrtc->InternalTamper1EventCallback(hrtc);
+#else
+ /* Internal Tamper1 callback */
+ HAL_RTCEx_InternalTamper1EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
+ }
+
+ /* Check Internal Tamper2 status */
+ if ((tmp & RTC_INT_TAMPER_2) == RTC_INT_TAMPER_2)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Internal Tamper 2 Event registered Callback */
+ hrtc->InternalTamper2EventCallback(hrtc);
+#else
+ /* Internal Tamper2 callback */
+ HAL_RTCEx_InternalTamper2EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
+ }
+
+ /* Check Internal Tamper3 status */
+ if ((tmp & RTC_INT_TAMPER_3) == RTC_INT_TAMPER_3)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Internal Tamper 3 Event registered Callback */
+ hrtc->InternalTamper3EventCallback(hrtc);
+#else
+ /* Internal Tamper3 callback */
+ HAL_RTCEx_InternalTamper3EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
+ }
+
+ /* Check Internal Tamper5 status */
+ if ((tmp & RTC_INT_TAMPER_5) == RTC_INT_TAMPER_5)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Internal Tamper 5 Event registered Callback */
+ hrtc->InternalTamper5EventCallback(hrtc);
+#else
+ /* Internal Tamper5 callback */
+ HAL_RTCEx_InternalTamper5EventCallback(hrtc);
+#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
+ }
+ /* Check Internal Tamper6 status */
+ if ((tmp & RTC_INT_TAMPER_6) == RTC_INT_TAMPER_6)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Internal Tamper 6 Event registered Callback */
+ hrtc->InternalTamper6EventCallback(hrtc);
+#else
+ /* Internal Tamper6 callback */
+ HAL_RTCEx_InternalTamper6EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
+ }
+ /* Check Internal Tamper7 status */
+ if ((tmp & RTC_INT_TAMPER_7) == RTC_INT_TAMPER_7)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Internal Tamper 7 Event registered Callback */
+ hrtc->InternalTamper7EventCallback(hrtc);
+#else
+ /* Internal Tamper7 callback */
+ HAL_RTCEx_InternalTamper7EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
+ }
+ /* Check Internal Tamper8 status */
+ if ((tmp & RTC_INT_TAMPER_8) == RTC_INT_TAMPER_8)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Internal Tamper 8 Event registered Callback */
+ hrtc->InternalTamper8EventCallback(hrtc);
+#else
+ /* Internal Tamper8 callback */
+ HAL_RTCEx_InternalTamper8EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
+ }
+ /* Check Internal Tamper9 status */
+ if ((tmp & RTC_INT_TAMPER_9) == RTC_INT_TAMPER_9)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Internal Tamper 9 Event registered Callback */
+ hrtc->InternalTamper9EventCallback(hrtc);
+#else
+ /* Internal Tamper9 callback */
+ HAL_RTCEx_InternalTamper9EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
+ }
+ /* Check Internal Tamper11 status */
+ if ((tmp & RTC_INT_TAMPER_11) == RTC_INT_TAMPER_11)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Internal Tamper 11 Event registered Callback */
+ hrtc->InternalTamper11EventCallback(hrtc);
+#else
+ /* Internal Tamper11 callback */
+ HAL_RTCEx_InternalTamper11EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
+ }
+
+ /* Check Internal Tamper12 status */
+ if ((tmp & RTC_INT_TAMPER_12) == RTC_INT_TAMPER_12)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Internal Tamper 12 Event registered Callback */
+ hrtc->InternalTamper12EventCallback(hrtc);
+#else
+ /* Internal Tamper12 callback */
+ HAL_RTCEx_InternalTamper12EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
+ }
+
+ /* Check Internal Tamper13 status */
+ if ((tmp & RTC_INT_TAMPER_13) == RTC_INT_TAMPER_13)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Internal Tamper 13 Event registered Callback */
+ hrtc->InternalTamper13EventCallback(hrtc);
+#else
+ /* Internal Tamper13 callback */
+ HAL_RTCEx_InternalTamper13EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/**
+ * @brief Tamper 1 callback.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file
+ */
+}
+
+
+/**
+ * @brief Tamper 2 callback.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tamper 3 callback.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tamper 4 callback.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+__weak void HAL_RTCEx_Tamper4EventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_Tamper4EventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tamper 5 callback.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+__weak void HAL_RTCEx_Tamper5EventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_Tamper5EventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tamper 6 callback.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+__weak void HAL_RTCEx_Tamper6EventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_Tamper6EventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tamper 7 callback.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+__weak void HAL_RTCEx_Tamper7EventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_Tamper7EventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tamper 8 callback.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+__weak void HAL_RTCEx_Tamper8EventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_Tamper8EventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Internal Tamper 1 callback.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+__weak void HAL_RTCEx_InternalTamper1EventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_InternalTamper1EventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Internal Tamper 2 callback.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+__weak void HAL_RTCEx_InternalTamper2EventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_InternalTamper2EventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Internal Tamper 3 callback.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+__weak void HAL_RTCEx_InternalTamper3EventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_InternalTamper3EventCallback could be implemented in the user file
+ */
+}
+
+
+/**
+ * @brief Internal Tamper 5 callback.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+__weak void HAL_RTCEx_InternalTamper5EventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_InternalTamper5EventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Internal Tamper 6 callback.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+__weak void HAL_RTCEx_InternalTamper6EventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_InternalTamper6EventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Internal Tamper 7 callback.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+__weak void HAL_RTCEx_InternalTamper7EventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_InternalTamper7EventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Internal Tamper 8 callback.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+__weak void HAL_RTCEx_InternalTamper8EventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_InternalTamper8EventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Internal Tamper 9 callback.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+__weak void HAL_RTCEx_InternalTamper9EventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_InternalTamper9EventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Internal Tamper 11 callback.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+__weak void HAL_RTCEx_InternalTamper11EventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_InternalTamper11EventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Internal Tamper 12 callback.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+__weak void HAL_RTCEx_InternalTamper12EventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_InternalTamper12EventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Internal Tamper 13 callback.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+__weak void HAL_RTCEx_InternalTamper13EventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_InternalTamper13EventCallback could be implemented in the user file
+ */
+}
+/**
+ * @}
+ */
+
+
+/** @addtogroup RTCEx_Exported_Functions_Group6
+ * @brief Extended RTC Backup register functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended RTC Backup register functions #####
+ ===============================================================================
+ [..]
+ (+) Before calling any tamper or internal tamper function, you have to call first
+ HAL_RTC_Init() function.
+ (+) In that ine you can select to output tamper event on RTC pin.
+ [..]
+ This subsection provides functions allowing to
+ (+) Write a data in a specified RTC Backup data register
+ (+) Read a data in a specified RTC Backup data register
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Write a data in a specified RTC Backup data register.
+ * @param hrtc RTC handle
+ * @param BackupRegister RTC Backup data Register number.
+ * This parameter can be RTC_BKP_DRx where x can be from 0 to RTC_BACKUP_NB
+ * @param Data Data to be written in the specified Backup data register.
+ * @retval None
+ */
+void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
+{
+ uint32_t tmp;
+
+ UNUSED(hrtc);
+ /* Check the parameters */
+ assert_param(IS_RTC_BKP(BackupRegister));
+
+ tmp = (uint32_t) &(TAMP->BKP0R);
+ tmp += (BackupRegister * 4U);
+
+ /* Write the specified register */
+ *(__IO uint32_t *)tmp = (uint32_t)Data;
+}
+
+
+/**
+ * @brief Reads data from the specified RTC Backup data Register.
+ * @param hrtc RTC handle
+ * @param BackupRegister RTC Backup data Register number.
+ * This parameter can be RTC_BKP_DRx where x can be from 0 to RTC_BACKUP_NB
+ * @retval Read value
+ */
+uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
+{
+ uint32_t tmp;
+
+ UNUSED(hrtc);
+ /* Check the parameters */
+ assert_param(IS_RTC_BKP(BackupRegister));
+
+ tmp = (uint32_t) &(TAMP->BKP0R);
+ tmp += (BackupRegister * 4U);
+
+ /* Read the specified register */
+ return (*(__IO uint32_t *)tmp);
+}
+
+/**
+ * @brief Reset the RTC Backup data Register and the device secrets.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+void HAL_RTCEx_BKUPErase(RTC_HandleTypeDef *hrtc)
+{
+ UNUSED(hrtc);
+ WRITE_REG(TAMP->CR2, TAMP_CR2_BKERASE);
+}
+
+/**
+ * @brief Block the access to the RTC Backup data Register and the device secrets.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+void HAL_RTCEx_BKUPBlock_Enable(RTC_HandleTypeDef *hrtc)
+{
+ UNUSED(hrtc);
+ WRITE_REG(TAMP->CR2, TAMP_CR2_BKBLOCK);
+}
+
+/**
+ * @brief Disable the Block to the access to the RTC Backup data Register and the device secrets.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+void HAL_RTCEx_BKUPBlock_Disable(RTC_HandleTypeDef *hrtc)
+{
+ UNUSED(hrtc);
+ CLEAR_BIT(TAMP->CR2, TAMP_CR2_BKBLOCK);
+}
+
+/**
+ * @brief Enable and Disable the erase of the configurable Device Secerts
+ * @note This API must be called before enabling the Tamper.
+ * @param hrtc RTC handle
+ * @param SecretDeviceConf Specifies the configuration of the Secrets Devices
+ * This parameter can be one of the following values:
+ * @arg TAMP_SECRETDEVICE_ERASE_ENABLE: Configurable device secrets are is included in the device secrets
+ * protected by TAMP peripheral.
+ * @arg TAMP_SECRETDEVICE_ERASE_DISABLE: Configurable device secrets are not included in the device
+ * secrets protected by TAMP peripheral.
+ * @retval None
+ */
+void HAL_RTCEx_Erase_SecretDev_Conf(RTC_HandleTypeDef *hrtc, uint32_t SecretDeviceConf)
+{
+ UNUSED(hrtc);
+
+ if (SecretDeviceConf != TAMP_SECRETDEVICE_ERASE_ENABLE)
+ {
+ CLEAR_BIT(TAMP->ERCFGR, TAMP_ERCFGR0);
+ }
+ else
+ {
+ SET_BIT(TAMP->ERCFGR, TAMP_ERCFGR0);
+ }
+}
+
+/**
+ * @brief Get the erase configuration of the Device Secerts
+ * @retval RTCEx_TAMP_Secret_Device_Conf_Erase
+ */
+uint32_t HAL_RTCEx_Get_Erase_SecretDev_Conf(void)
+{
+ if (READ_BIT(TAMP->ERCFGR, TAMP_ERCFGR0) == TAMP_ERCFGR0)
+ {
+ return TAMP_SECRETDEVICE_ERASE_ENABLE;
+ }
+ else
+ {
+ return TAMP_SECRETDEVICE_ERASE_DISABLE;
+ }
+}
+/**
+ * @}
+ */
+
+
+/** @addtogroup RTCEx_Exported_Functions_Group7
+ * @brief Extended RTC security functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended RTC security functions #####
+ ===============================================================================
+ [..]
+ (+) Before calling security function, you have to call first
+ HAL_RTC_Init() function.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Get the security level of the RTC.
+ * To set the secure level please call HAL_RTCEx_SecureModeSet.
+ * @param hrtc RTC handle
+ * @param secureState Secure state
+ * @retval HAL_StatusTypeDef
+ */
+HAL_StatusTypeDef HAL_RTCEx_SecureModeGet(RTC_HandleTypeDef *hrtc, RTC_SecureStateTypeDef *secureState)
+{
+ UNUSED(hrtc);
+ /* Read registers */
+ uint32_t rtc_seccfgr = READ_REG(RTC->SECCFGR);
+ uint32_t tamp_seccfgr = READ_REG(TAMP->SECCFGR);
+
+ /* RTC */
+ secureState->rtcSecureFull = READ_BIT(rtc_seccfgr, RTC_SECCFGR_SEC);
+
+ /* Warning, rtcNonSecureFeatures is only relevant if secureState->rtcSecureFull == RTC_SECURE_FULL_NO */
+ secureState->rtcNonSecureFeatures = READ_BIT(rtc_seccfgr, RTC_NONSECURE_FEATURE_ALL);
+
+ /* TAMP */
+ secureState->tampSecureFull = READ_BIT(tamp_seccfgr, TAMP_SECCFGR_TAMPSEC);
+
+ /* Monotonic Counter */
+ secureState->MonotonicCounterSecure = READ_BIT(tamp_seccfgr, TAMP_SECCFGR_CNT1SEC);
+
+ /* Backup register start zones
+ Warning : Backup register start zones are shared with privilege configuration */
+ secureState->backupRegisterStartZone2 = READ_BIT(tamp_seccfgr, TAMP_SECCFGR_BKPRWSEC) >> TAMP_SECCFGR_BKPRWSEC_Pos;
+ secureState->backupRegisterStartZone3 = READ_BIT(tamp_seccfgr, TAMP_SECCFGR_BKPWSEC) >> TAMP_SECCFGR_BKPWSEC_Pos;
+
+ return HAL_OK;
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ * @brief Set the security level of the RTC/TAMP/Backup registers.
+ * To get the current security level call HAL_RTCEx_SecureModeGet.
+ * @param hrtc RTC handle
+ * @param secureState Secure state
+ * @retval HAL_StatusTypeDef
+ */
+HAL_StatusTypeDef HAL_RTCEx_SecureModeSet(RTC_HandleTypeDef *hrtc, RTC_SecureStateTypeDef *secureState)
+{
+ UNUSED(hrtc);
+ assert_param(IS_RTC_SECURE_FULL(secureState->rtcSecureFull));
+ assert_param(IS_RTC_NONSECURE_FEATURES(secureState->rtcNonSecureFeatures));
+ assert_param(IS_TAMP_SECURE_FULL(secureState->tampSecureFull));
+ assert_param(IS_RTC_BKP(secureState->backupRegisterStartZone2));
+ assert_param(IS_RTC_BKP(secureState->backupRegisterStartZone3));
+ assert_param(IS_TAMP_MONOTONIC_CNT_SECURE(secureState->MonotonicCounterSecure));
+
+ /* RTC, rtcNonSecureFeatures is only relevant if secureState->rtcSecureFull == RTC_SECURE_FULL_NO */
+ WRITE_REG(RTC->SECCFGR, secureState->rtcSecureFull | secureState->rtcNonSecureFeatures);
+
+ /* Tamper + Backup register + Monotonic counter
+ Warning : Backup register start zone are Shared with privilege configuration */
+ WRITE_REG(TAMP->SECCFGR,
+ secureState->tampSecureFull | secureState->MonotonicCounterSecure |
+ (TAMP_SECCFGR_BKPRWSEC & (secureState->backupRegisterStartZone2 << TAMP_SECCFGR_BKPRWSEC_Pos)) |
+ (TAMP_SECCFGR_BKPWSEC & (secureState->backupRegisterStartZone3 << TAMP_SECCFGR_BKPWSEC_Pos)));
+
+ return HAL_OK;
+}
+
+
+#endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTCEx_Exported_Functions_Group8
+ * @brief Extended RTC privilege functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended RTC privilege functions #####
+ ===============================================================================
+ [..]
+ (+) Before calling privilege function, you have to call first
+ HAL_RTC_Init() function.
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Set the privilege level of the RTC/TAMP registers.
+ * To get the current privilege level call HAL_RTCEx_PrivilegeModeGet.
+ * @param hrtc RTC handle
+ * @param privilegeState Privilege state
+ * @retval HAL_StatusTypeDef
+ */
+HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeSet(RTC_HandleTypeDef *hrtc, RTC_PrivilegeStateTypeDef *privilegeState)
+{
+ UNUSED(hrtc);
+ assert_param(IS_RTC_PRIVILEGE_FULL(privilegeState->rtcPrivilegeFull));
+ assert_param(IS_RTC_PRIVILEGE_FEATURES(privilegeState->rtcPrivilegeFeatures));
+ assert_param(IS_TAMP_PRIVILEGE_FULL(privilegeState->tampPrivilegeFull));
+ assert_param(IS_TAMP_MONOTONIC_CNT_PRIVILEGE(privilegeState->MonotonicCounterPrivilege));
+ assert_param(IS_RTC_PRIVILEGE_BKUP_ZONE(privilegeState->backupRegisterPrivZone));
+ assert_param(IS_RTC_BKP(privilegeState->backupRegisterStartZone2));
+ assert_param(IS_RTC_BKP(privilegeState->backupRegisterStartZone3));
+
+ /* RTC privilege configuration */
+ WRITE_REG(RTC->PRIVCFGR, privilegeState->rtcPrivilegeFull | privilegeState->rtcPrivilegeFeatures);
+
+ /* TAMP, Monotonic counter and Backup registers privilege configuration
+ Warning : privilegeState->backupRegisterPrivZone is only writable in secure mode or if trustzone is disabled.
+ In non secure mode, a notification is generated through a flag/interrupt in the TZIC
+ (TrustZone interrupt controller). The bits are not written. */
+ WRITE_REG(TAMP->PRIVCFGR, privilegeState->tampPrivilegeFull | privilegeState->backupRegisterPrivZone | \
+ privilegeState->MonotonicCounterPrivilege);
+
+ /* Backup register start zone
+ Warning : This parameter is only writable in secure mode or if trustzone is disabled.
+ In non secure mode, a notification is generated through a flag/interrupt in the TZIC
+ (TrustZone interrupt controller). The bits are not written.
+ Warning : Backup register start zones are shared with secure configuration */
+ MODIFY_REG(TAMP->SECCFGR,
+ (TAMP_SECCFGR_BKPRWSEC | TAMP_SECCFGR_BKPWSEC),
+ ((privilegeState->backupRegisterStartZone2 << TAMP_SECCFGR_BKPRWSEC_Pos) | \
+ (privilegeState->backupRegisterStartZone3 << TAMP_SECCFGR_BKPWSEC_Pos)));
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get the privilege level of the RTC.
+ * To set the privilege level please call HAL_RTCEx_PrivilegeModeSet.
+ * @param hrtc RTC handle
+ * @param privilegeState Privilege state
+ * @retval HAL_StatusTypeDef
+ */
+HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeGet(RTC_HandleTypeDef *hrtc, RTC_PrivilegeStateTypeDef *privilegeState)
+{
+ /* Read registers */
+ uint32_t rtc_privcfgr = READ_REG(RTC->PRIVCFGR);
+ uint32_t tamp_privcfgr = READ_REG(TAMP->PRIVCFGR);
+ uint32_t tamp_seccfgr = READ_REG(TAMP->SECCFGR);
+
+ UNUSED(hrtc);
+ /* RTC privilege configuration */
+ privilegeState->rtcPrivilegeFull = READ_BIT(rtc_privcfgr, RTC_PRIVCFGR_PRIV);
+
+ /* Warning, rtcPrivilegeFeatures is only relevant if privilegeState->rtcPrivilegeFull == RTC_PRIVILEGE_FULL_NO */
+ privilegeState->rtcPrivilegeFeatures = READ_BIT(rtc_privcfgr, RTC_PRIVILEGE_FEATURE_ALL);
+
+ /* TAMP and Backup registers privilege configuration */
+ privilegeState->tampPrivilegeFull = READ_BIT(tamp_privcfgr, TAMP_PRIVCFGR_TAMPPRIV);
+
+ /* Monotonic registers privilege configuration */
+ privilegeState->MonotonicCounterPrivilege = READ_BIT(tamp_privcfgr, TAMP_PRIVCFGR_CNT1PRIV);
+
+ /* Backup registers Zones */
+ privilegeState->backupRegisterPrivZone = READ_BIT(tamp_privcfgr, (TAMP_PRIVCFGR_BKPWPRIV | TAMP_PRIVCFGR_BKPRWPRIV));
+
+ /* Backup register start zones
+ Warning : Shared with secure configuration */
+ privilegeState->backupRegisterStartZone2 = READ_BIT(tamp_seccfgr, TAMP_SECCFGR_BKPRWSEC) >> TAMP_SECCFGR_BKPRWSEC_Pos;
+ privilegeState->backupRegisterStartZone3 = READ_BIT(tamp_seccfgr, TAMP_SECCFGR_BKPWSEC) >> TAMP_SECCFGR_BKPWSEC_Pos;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sai.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sai.c
new file mode 100644
index 00000000..a3bff261
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sai.c
@@ -0,0 +1,2896 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_sai.c
+ * @author MCD Application Team
+ * @brief SAI HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Serial Audio Interface (SAI) peripheral:
+ * + Initialization/de-initialization functions
+ * + I/O operation functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+
+ [..]
+ The SAI HAL driver can be used as follows:
+
+ (#) Declare a SAI_HandleTypeDef handle structure (eg. SAI_HandleTypeDef hsai).
+ (#) Initialize the SAI low level resources by implementing the HAL_SAI_MspInit() API:
+ (##) Enable the SAI interface clock.
+ (##) SAI pins configuration:
+ (+++) Enable the clock for the SAI GPIOs.
+ (+++) Configure these SAI pins as alternate function pull-up.
+ (##) NVIC configuration if you need to use interrupt process (HAL_SAI_Transmit_IT()
+ and HAL_SAI_Receive_IT() APIs):
+ (+++) Configure the SAI interrupt priority.
+ (+++) Enable the NVIC SAI IRQ handle.
+
+ (##) DMA Configuration if you need to use DMA process (HAL_SAI_Transmit_DMA()
+ and HAL_SAI_Receive_DMA() APIs):
+ (+++) Declare a DMA handle structure for the Tx/Rx stream.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx Stream.
+ (+++) Associate the initialized DMA handle to the SAI DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
+ DMA Tx/Rx Stream.
+
+ (#) The initialization can be done by two ways
+ (##) Expert mode : Initialize the structures Init, FrameInit and SlotInit and call HAL_SAI_Init().
+ (##) Simplified mode : Initialize the high part of Init Structure and call HAL_SAI_InitProtocol().
+
+ [..]
+ (@) The specific SAI interrupts (FIFO request and Overrun underrun interrupt)
+ will be managed using the macros __HAL_SAI_ENABLE_IT() and __HAL_SAI_DISABLE_IT()
+ inside the transmit and receive process.
+ [..]
+ (@) Make sure that either:
+ (+@) PLLSAI1CLK output is configured or
+ (+@) PLLSAI2CLK output is configured or
+ (+@) PLLSAI3CLK output is configured or
+ (+@) External clock source is configured after setting correctly
+ the define constant EXTERNAL_SAI1_CLOCK_VALUE or EXTERNAL_SAI2_CLOCK_VALUE
+ in the stm32u5xx_hal_conf.h file.
+
+ [..]
+ (@) In master Tx mode: enabling the audio block immediately generates the bit clock
+ for the external slaves even if there is no data in the FIFO, However FS signal
+ generation is conditioned by the presence of data in the FIFO.
+
+ [..]
+ (@) In master Rx mode: enabling the audio block immediately generates the bit clock
+ and FS signal for the external slaves.
+
+ [..]
+ (@) It is mandatory to respect the following conditions in order to avoid bad SAI behavior:
+ (+@) First bit Offset <= (SLOT size - Data size)
+ (+@) Data size <= SLOT size
+ (+@) Number of SLOT x SLOT size = Frame length
+ (+@) The number of slots should be even when SAI_FS_CHANNEL_IDENTIFICATION is selected.
+
+ [..]
+ (@) PDM interface can be activated through HAL_SAI_Init function.
+ Please note that PDM interface is only available for SAI1 sub-block A.
+ PDM microphone delays can be tuned with HAL_SAIEx_ConfigPdmMicDelay function.
+
+ [..]
+ Three operation modes are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_SAI_Transmit()
+ (+) Receive an amount of data in blocking mode using HAL_SAI_Receive()
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Send an amount of data in non-blocking mode using HAL_SAI_Transmit_IT()
+ (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SAI_TxCpltCallback()
+ (+) Receive an amount of data in non-blocking mode using HAL_SAI_Receive_IT()
+ (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SAI_RxCpltCallback()
+ (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_SAI_ErrorCallback()
+
+ *** DMA mode IO operation ***
+ =============================
+ [..]
+ (+) Send an amount of data in non-blocking mode (DMA) using HAL_SAI_Transmit_DMA()
+ (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SAI_TxCpltCallback()
+ (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SAI_Receive_DMA()
+ (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SAI_RxCpltCallback()
+ (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_SAI_ErrorCallback()
+ (+) Pause the DMA Transfer using HAL_SAI_DMAPause()
+ (+) Resume the DMA Transfer using HAL_SAI_DMAResume()
+ (+) Stop the DMA Transfer using HAL_SAI_DMAStop()
+
+ *** SAI HAL driver additional function list ***
+ ===============================================
+ [..]
+ Below the list the others API available SAI HAL driver :
+
+ (+) HAL_SAI_EnableTxMuteMode(): Enable the mute in tx mode
+ (+) HAL_SAI_DisableTxMuteMode(): Disable the mute in tx mode
+ (+) HAL_SAI_EnableRxMuteMode(): Enable the mute in Rx mode
+ (+) HAL_SAI_DisableRxMuteMode(): Disable the mute in Rx mode
+ (+) HAL_SAI_FlushRxFifo(): Flush the rx fifo.
+ (+) HAL_SAI_Abort(): Abort the current transfer
+
+ *** SAI HAL driver macros list ***
+ ==================================
+ [..]
+ Below the list of most used macros in SAI HAL driver :
+
+ (+) __HAL_SAI_ENABLE(): Enable the SAI peripheral
+ (+) __HAL_SAI_DISABLE(): Disable the SAI peripheral
+ (+) __HAL_SAI_ENABLE_IT(): Enable the specified SAI interrupts
+ (+) __HAL_SAI_DISABLE_IT(): Disable the specified SAI interrupts
+ (+) __HAL_SAI_GET_IT_SOURCE(): Check if the specified SAI interrupt source is
+ enabled or disabled
+ (+) __HAL_SAI_GET_FLAG(): Check whether the specified SAI flag is set or not
+
+ *** Callback registration ***
+ =============================
+ [..]
+ The compilation define USE_HAL_SAI_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use functions HAL_SAI_RegisterCallback() to register a user callback.
+
+ [..]
+ Function HAL_SAI_RegisterCallback() allows to register following callbacks:
+ (+) RxCpltCallback : SAI receive complete.
+ (+) RxHalfCpltCallback : SAI receive half complete.
+ (+) TxCpltCallback : SAI transmit complete.
+ (+) TxHalfCpltCallback : SAI transmit half complete.
+ (+) ErrorCallback : SAI error.
+ (+) MspInitCallback : SAI MspInit.
+ (+) MspDeInitCallback : SAI MspDeInit.
+ [..]
+ This function takes as parameters the HAL peripheral handle, the callback ID
+ and a pointer to the user callback function.
+
+ [..]
+ Use function HAL_SAI_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function.
+ HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the callback ID.
+ [..]
+ This function allows to reset following callbacks:
+ (+) RxCpltCallback : SAI receive complete.
+ (+) RxHalfCpltCallback : SAI receive half complete.
+ (+) TxCpltCallback : SAI transmit complete.
+ (+) TxHalfCpltCallback : SAI transmit half complete.
+ (+) ErrorCallback : SAI error.
+ (+) MspInitCallback : SAI MspInit.
+ (+) MspDeInitCallback : SAI MspDeInit.
+
+ [..]
+ By default, after the HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET
+ all callbacks are reset to the corresponding legacy weak (surcharged) functions:
+ examples HAL_SAI_RxCpltCallback(), HAL_SAI_ErrorCallback().
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak (surcharged) functions in the HAL_SAI_Init
+ and HAL_SAI_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_SAI_Init and HAL_SAI_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+ [..]
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using HAL_SAI_RegisterCallback before calling HAL_SAI_DeInit
+ or HAL_SAI_Init function.
+
+ [..]
+ When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
+ @endverbatim
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SAI SAI
+ * @brief SAI HAL module driver
+ * @{
+ */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/** @defgroup SAI_Private_Typedefs SAI Private Typedefs
+ * @{
+ */
+typedef enum
+{
+ SAI_MODE_DMA,
+ SAI_MODE_IT
+} SAI_ModeTypedef;
+/**
+ * @}
+ */
+
+/* Private define ------------------------------------------------------------*/
+/** @defgroup SAI_Private_Constants SAI Private Constants
+ * @{
+ */
+#define SAI_DEFAULT_TIMEOUT 4U
+#define SAI_LONG_TIMEOUT 1000U
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup SAI_Private_Functions SAI Private Functions
+ * @{
+ */
+static void SAI_FillFifo(SAI_HandleTypeDef *hsai);
+static uint32_t SAI_InterruptFlag(const SAI_HandleTypeDef *hsai, SAI_ModeTypedef mode);
+static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
+static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
+
+static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai);
+static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai);
+static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai);
+static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai);
+static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai);
+static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai);
+static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai);
+
+static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma);
+static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma);
+static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void SAI_DMAError(DMA_HandleTypeDef *hdma);
+static void SAI_DMAAbort(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup SAI_Exported_Functions SAI Exported Functions
+ * @{
+ */
+
+/** @defgroup SAI_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ de-initialize the SAIx peripheral:
+
+ (+) User must implement HAL_SAI_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+ (+) Call the function HAL_SAI_Init() to configure the selected device with
+ the selected configuration:
+ (++) Mode (Master/slave TX/RX)
+ (++) Protocol
+ (++) Data Size
+ (++) MCLK Output
+ (++) Audio frequency
+ (++) FIFO Threshold
+ (++) Frame Config
+ (++) Slot Config
+ (++) PDM Config
+
+ (+) Call the function HAL_SAI_DeInit() to restore the default configuration
+ of the selected SAI peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the structure FrameInit, SlotInit and the low part of
+ * Init according to the specified parameters and call the function
+ * HAL_SAI_Init to initialize the SAI block.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @param protocol one of the supported protocol @ref SAI_Protocol
+ * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize
+ * the configuration information for SAI module.
+ * @param nbslot Number of slot.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check the parameters */
+ assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol));
+ assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize));
+
+ switch (protocol)
+ {
+ case SAI_I2S_STANDARD :
+ case SAI_I2S_MSBJUSTIFIED :
+ case SAI_I2S_LSBJUSTIFIED :
+ status = SAI_InitI2S(hsai, protocol, datasize, nbslot);
+ break;
+ case SAI_PCM_LONG :
+ case SAI_PCM_SHORT :
+ status = SAI_InitPCM(hsai, protocol, datasize, nbslot);
+ break;
+ default :
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ status = HAL_SAI_Init(hsai);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initialize the SAI according to the specified parameters.
+ * in the SAI_InitTypeDef structure and initialize the associated handle.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
+{
+ uint32_t tmpregisterGCR;
+ uint32_t ckstr_bits;
+ uint32_t syncen_bits;
+
+ /* Check the SAI handle allocation */
+ if (hsai == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* check the instance */
+ assert_param(IS_SAI_ALL_INSTANCE(hsai->Instance));
+
+ /* Check the SAI Block parameters */
+ assert_param(IS_SAI_AUDIO_FREQUENCY(hsai->Init.AudioFrequency));
+ assert_param(IS_SAI_BLOCK_PROTOCOL(hsai->Init.Protocol));
+ assert_param(IS_SAI_BLOCK_MODE(hsai->Init.AudioMode));
+ assert_param(IS_SAI_BLOCK_DATASIZE(hsai->Init.DataSize));
+ assert_param(IS_SAI_BLOCK_FIRST_BIT(hsai->Init.FirstBit));
+ assert_param(IS_SAI_BLOCK_CLOCK_STROBING(hsai->Init.ClockStrobing));
+ assert_param(IS_SAI_BLOCK_SYNCHRO(hsai->Init.Synchro));
+ assert_param(IS_SAI_BLOCK_MCK_OUTPUT(hsai->Init.MckOutput));
+ assert_param(IS_SAI_BLOCK_OUTPUT_DRIVE(hsai->Init.OutputDrive));
+ assert_param(IS_SAI_BLOCK_NODIVIDER(hsai->Init.NoDivider));
+ assert_param(IS_SAI_BLOCK_FIFO_THRESHOLD(hsai->Init.FIFOThreshold));
+ assert_param(IS_SAI_MONO_STEREO_MODE(hsai->Init.MonoStereoMode));
+ assert_param(IS_SAI_BLOCK_COMPANDING_MODE(hsai->Init.CompandingMode));
+ assert_param(IS_SAI_BLOCK_TRISTATE_MANAGEMENT(hsai->Init.TriState));
+ assert_param(IS_SAI_BLOCK_SYNCEXT(hsai->Init.SynchroExt));
+ assert_param(IS_SAI_BLOCK_MCK_OVERSAMPLING(hsai->Init.MckOverSampling));
+
+ /* Check the SAI Block Frame parameters */
+ assert_param(IS_SAI_BLOCK_FRAME_LENGTH(hsai->FrameInit.FrameLength));
+ assert_param(IS_SAI_BLOCK_ACTIVE_FRAME(hsai->FrameInit.ActiveFrameLength));
+ assert_param(IS_SAI_BLOCK_FS_DEFINITION(hsai->FrameInit.FSDefinition));
+ assert_param(IS_SAI_BLOCK_FS_POLARITY(hsai->FrameInit.FSPolarity));
+ assert_param(IS_SAI_BLOCK_FS_OFFSET(hsai->FrameInit.FSOffset));
+
+ /* Check the SAI Block Slot parameters */
+ assert_param(IS_SAI_BLOCK_FIRSTBIT_OFFSET(hsai->SlotInit.FirstBitOffset));
+ assert_param(IS_SAI_BLOCK_SLOT_SIZE(hsai->SlotInit.SlotSize));
+ assert_param(IS_SAI_BLOCK_SLOT_NUMBER(hsai->SlotInit.SlotNumber));
+ assert_param(IS_SAI_SLOT_ACTIVE(hsai->SlotInit.SlotActive));
+
+ /* Check the SAI PDM parameters */
+ assert_param(IS_FUNCTIONAL_STATE(hsai->Init.PdmInit.Activation));
+ if (hsai->Init.PdmInit.Activation == ENABLE)
+ {
+ assert_param(IS_SAI_PDM_MIC_PAIRS_NUMBER(hsai->Init.PdmInit.MicPairsNbr));
+ assert_param(IS_SAI_PDM_CLOCK_ENABLE(hsai->Init.PdmInit.ClockEnable));
+ /* Check that SAI sub-block is SAI1 sub-block A, in master RX mode with free protocol */
+ if ((hsai->Instance != SAI1_Block_A) ||
+ (hsai->Init.AudioMode != SAI_MODEMASTER_RX) ||
+ (hsai->Init.Protocol != SAI_FREE_PROTOCOL))
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ if (hsai->State == HAL_SAI_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hsai->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ /* Reset callback pointers to the weak predefined callbacks */
+ hsai->RxCpltCallback = HAL_SAI_RxCpltCallback;
+ hsai->RxHalfCpltCallback = HAL_SAI_RxHalfCpltCallback;
+ hsai->TxCpltCallback = HAL_SAI_TxCpltCallback;
+ hsai->TxHalfCpltCallback = HAL_SAI_TxHalfCpltCallback;
+ hsai->ErrorCallback = HAL_SAI_ErrorCallback;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ if (hsai->MspInitCallback == NULL)
+ {
+ hsai->MspInitCallback = HAL_SAI_MspInit;
+ }
+ hsai->MspInitCallback(hsai);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_SAI_MspInit(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+ }
+
+ /* Disable the selected SAI peripheral */
+ if (SAI_Disable(hsai) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ hsai->State = HAL_SAI_STATE_BUSY;
+
+ /* SAI Block Synchro Configuration -----------------------------------------*/
+ /* This setting must be done with both audio block (A & B) disabled */
+ switch (hsai->Init.SynchroExt)
+ {
+ case SAI_SYNCEXT_DISABLE :
+ tmpregisterGCR = 0;
+ break;
+ case SAI_SYNCEXT_OUTBLOCKA_ENABLE :
+ tmpregisterGCR = SAI_GCR_SYNCOUT_0;
+ break;
+ case SAI_SYNCEXT_OUTBLOCKB_ENABLE :
+ tmpregisterGCR = SAI_GCR_SYNCOUT_1;
+ break;
+ default :
+ tmpregisterGCR = 0;
+ break;
+ }
+
+ switch (hsai->Init.Synchro)
+ {
+ case SAI_ASYNCHRONOUS :
+ syncen_bits = 0;
+ break;
+ case SAI_SYNCHRONOUS :
+ syncen_bits = SAI_xCR1_SYNCEN_0;
+ break;
+ case SAI_SYNCHRONOUS_EXT_SAI1 :
+ syncen_bits = SAI_xCR1_SYNCEN_1;
+ break;
+ case SAI_SYNCHRONOUS_EXT_SAI2 :
+ syncen_bits = SAI_xCR1_SYNCEN_1;
+ tmpregisterGCR |= SAI_GCR_SYNCIN_0;
+ break;
+ default :
+ syncen_bits = 0;
+ break;
+ }
+
+ if ((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B))
+ {
+ SAI1->GCR = tmpregisterGCR;
+ }
+ else
+ {
+ SAI2->GCR = tmpregisterGCR;
+ }
+
+ if (hsai->Init.AudioFrequency != SAI_AUDIO_FREQUENCY_MCKDIV)
+ {
+ uint32_t freq = 0;
+ uint32_t tmpval;
+
+ /* In this case, the MCKDIV value is calculated to get AudioFrequency */
+ if ((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B))
+ {
+ freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1);
+ }
+ if ((hsai->Instance == SAI2_Block_A) || (hsai->Instance == SAI2_Block_B))
+ {
+ freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI2);
+ }
+
+ /* Configure Master Clock Divider using the following formula :
+ - If NODIV = 1 :
+ MCKDIV[5:0] = SAI_CK_x / (FS * (FRL + 1))
+ - If NODIV = 0 :
+ MCKDIV[5:0] = SAI_CK_x / (FS * (OSR + 1) * 256) */
+ if (hsai->Init.NoDivider == SAI_MASTERDIVIDER_DISABLE)
+ {
+ /* NODIV = 1 */
+ uint32_t tmpframelength;
+
+ if (hsai->Init.Protocol == SAI_SPDIF_PROTOCOL)
+ {
+ /* For SPDIF protocol, frame length is set by hardware to 64 */
+ tmpframelength = 64U;
+ }
+ else if (hsai->Init.Protocol == SAI_AC97_PROTOCOL)
+ {
+ /* For AC97 protocol, frame length is set by hardware to 256 */
+ tmpframelength = 256U;
+ }
+ else
+ {
+ /* For free protocol, frame length is set by user */
+ tmpframelength = hsai->FrameInit.FrameLength;
+ }
+
+ /* (freq x 10) to keep Significant digits */
+ tmpval = (freq * 10U) / (hsai->Init.AudioFrequency * tmpframelength);
+ }
+ else
+ {
+ /* NODIV = 0 */
+ uint32_t tmposr;
+ tmposr = (hsai->Init.MckOverSampling == SAI_MCK_OVERSAMPLING_ENABLE) ? 2U : 1U;
+ /* (freq x 10) to keep Significant digits */
+ tmpval = (freq * 10U) / (hsai->Init.AudioFrequency * tmposr * 256U);
+ }
+ hsai->Init.Mckdiv = tmpval / 10U;
+
+ /* Round result to the nearest integer */
+ if ((tmpval % 10U) > 8U)
+ {
+ hsai->Init.Mckdiv += 1U;
+ }
+
+ /* For SPDIF protocol, SAI shall provide a bit clock twice faster the symbol-rate */
+ if (hsai->Init.Protocol == SAI_SPDIF_PROTOCOL)
+ {
+ hsai->Init.Mckdiv = hsai->Init.Mckdiv >> 1;
+ }
+ }
+
+ /* Check the SAI Block master clock divider parameter */
+ assert_param(IS_SAI_BLOCK_MASTER_DIVIDER(hsai->Init.Mckdiv));
+
+ /* Compute CKSTR bits of SAI CR1 according ClockStrobing and AudioMode */
+ if ((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
+ {
+ /* Transmit */
+ ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? 0U : SAI_xCR1_CKSTR;
+ }
+ else
+ {
+ /* Receive */
+ ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? SAI_xCR1_CKSTR : 0U;
+ }
+
+ /* SAI Block Configuration -------------------------------------------------*/
+ /* SAI CR1 Configuration */
+ hsai->Instance->CR1 &= ~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG | SAI_xCR1_DS | \
+ SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN | \
+ SAI_xCR1_MONO | SAI_xCR1_OUTDRIV | SAI_xCR1_DMAEN | \
+ SAI_xCR1_NODIV | SAI_xCR1_MCKDIV | SAI_xCR1_OSR | \
+ SAI_xCR1_MCKEN);
+
+ hsai->Instance->CR1 |= (hsai->Init.AudioMode | hsai->Init.Protocol | \
+ hsai->Init.DataSize | hsai->Init.FirstBit | \
+ ckstr_bits | syncen_bits | \
+ hsai->Init.MonoStereoMode | hsai->Init.OutputDrive | \
+ hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20) | \
+ hsai->Init.MckOverSampling | hsai->Init.MckOutput);
+
+ /* SAI CR2 Configuration */
+ hsai->Instance->CR2 &= ~(SAI_xCR2_FTH | SAI_xCR2_FFLUSH | SAI_xCR2_COMP | SAI_xCR2_CPL);
+ hsai->Instance->CR2 |= (hsai->Init.FIFOThreshold | hsai->Init.CompandingMode | hsai->Init.TriState);
+
+ /* SAI Frame Configuration -----------------------------------------*/
+ hsai->Instance->FRCR &= (~(SAI_xFRCR_FRL | SAI_xFRCR_FSALL | SAI_xFRCR_FSDEF | \
+ SAI_xFRCR_FSPOL | SAI_xFRCR_FSOFF));
+ hsai->Instance->FRCR |= ((hsai->FrameInit.FrameLength - 1U) |
+ hsai->FrameInit.FSOffset |
+ hsai->FrameInit.FSDefinition |
+ hsai->FrameInit.FSPolarity |
+ ((hsai->FrameInit.ActiveFrameLength - 1U) << 8));
+
+ /* SAI Block_x SLOT Configuration ------------------------------------------*/
+ /* This register has no meaning in AC 97 and SPDIF audio protocol */
+ hsai->Instance->SLOTR &= (~(SAI_xSLOTR_FBOFF | SAI_xSLOTR_SLOTSZ | \
+ SAI_xSLOTR_NBSLOT | SAI_xSLOTR_SLOTEN));
+
+ hsai->Instance->SLOTR |= hsai->SlotInit.FirstBitOffset | hsai->SlotInit.SlotSize | \
+ (hsai->SlotInit.SlotActive << 16) | ((hsai->SlotInit.SlotNumber - 1U) << 8);
+
+ /* SAI PDM Configuration ---------------------------------------------------*/
+ if (hsai->Instance == SAI1_Block_A)
+ {
+ /* Disable PDM interface */
+ SAI1->PDMCR &= ~(SAI_PDMCR_PDMEN);
+ if (hsai->Init.PdmInit.Activation == ENABLE)
+ {
+ /* Configure and enable PDM interface */
+ SAI1->PDMCR = (hsai->Init.PdmInit.ClockEnable |
+ ((hsai->Init.PdmInit.MicPairsNbr - 1U) << SAI_PDMCR_MICNBR_Pos));
+ SAI1->PDMCR |= SAI_PDMCR_PDMEN;
+ }
+ }
+
+ /* Initialize the error code */
+ hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+
+ /* Initialize the SAI state */
+ hsai->State = HAL_SAI_STATE_READY;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsai);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitialize the SAI peripheral.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai)
+{
+ /* Check the SAI handle allocation */
+ if (hsai == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ hsai->State = HAL_SAI_STATE_BUSY;
+
+ /* Disabled All interrupt and clear all the flag */
+ hsai->Instance->IMR = 0;
+ hsai->Instance->CLRFR = 0xFFFFFFFFU;
+
+ /* Disable the SAI */
+ if (SAI_Disable(hsai) != HAL_OK)
+ {
+ /* Reset SAI state to ready */
+ hsai->State = HAL_SAI_STATE_READY;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsai);
+
+ return HAL_ERROR;
+ }
+
+ /* Flush the fifo */
+ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
+
+ /* Disable SAI PDM interface */
+ if (hsai->Instance == SAI1_Block_A)
+ {
+ /* Reset PDM delays */
+ SAI1->PDMDLY = 0U;
+
+ /* Disable PDM interface */
+ SAI1->PDMCR &= ~(SAI_PDMCR_PDMEN);
+ }
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ if (hsai->MspDeInitCallback == NULL)
+ {
+ hsai->MspDeInitCallback = HAL_SAI_MspDeInit;
+ }
+ hsai->MspDeInitCallback(hsai);
+#else
+ HAL_SAI_MspDeInit(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+
+ /* Initialize the error code */
+ hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+
+ /* Initialize the SAI state */
+ hsai->State = HAL_SAI_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsai);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the SAI MSP.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None
+ */
+__weak void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsai);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SAI_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the SAI MSP.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None
+ */
+__weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsai);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SAI_MspDeInit could be implemented in the user file
+ */
+}
+
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a user SAI callback
+ * to be used instead of the weak predefined callback.
+ * @param hsai SAI handle.
+ * @param CallbackID ID of the callback to be registered.
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SAI_RX_COMPLETE_CB_ID receive complete callback ID.
+ * @arg @ref HAL_SAI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID.
+ * @arg @ref HAL_SAI_TX_COMPLETE_CB_ID transmit complete callback ID.
+ * @arg @ref HAL_SAI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID.
+ * @arg @ref HAL_SAI_ERROR_CB_ID error callback ID.
+ * @arg @ref HAL_SAI_MSPINIT_CB_ID MSP init callback ID.
+ * @arg @ref HAL_SAI_MSPDEINIT_CB_ID MSP de-init callback ID.
+ * @param pCallback pointer to the callback function.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_SAI_RegisterCallback(SAI_HandleTypeDef *hsai,
+ HAL_SAI_CallbackIDTypeDef CallbackID,
+ pSAI_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* update the error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ if (HAL_SAI_STATE_READY == hsai->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SAI_RX_COMPLETE_CB_ID :
+ hsai->RxCpltCallback = pCallback;
+ break;
+ case HAL_SAI_RX_HALFCOMPLETE_CB_ID :
+ hsai->RxHalfCpltCallback = pCallback;
+ break;
+ case HAL_SAI_TX_COMPLETE_CB_ID :
+ hsai->TxCpltCallback = pCallback;
+ break;
+ case HAL_SAI_TX_HALFCOMPLETE_CB_ID :
+ hsai->TxHalfCpltCallback = pCallback;
+ break;
+ case HAL_SAI_ERROR_CB_ID :
+ hsai->ErrorCallback = pCallback;
+ break;
+ case HAL_SAI_MSPINIT_CB_ID :
+ hsai->MspInitCallback = pCallback;
+ break;
+ case HAL_SAI_MSPDEINIT_CB_ID :
+ hsai->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update the error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_SAI_STATE_RESET == hsai->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SAI_MSPINIT_CB_ID :
+ hsai->MspInitCallback = pCallback;
+ break;
+ case HAL_SAI_MSPDEINIT_CB_ID :
+ hsai->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update the error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update the error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+ }
+ return status;
+}
+
+/**
+ * @brief Unregister a user SAI callback.
+ * SAI callback is redirected to the weak predefined callback.
+ * @param hsai SAI handle.
+ * @param CallbackID ID of the callback to be unregistered.
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SAI_RX_COMPLETE_CB_ID receive complete callback ID.
+ * @arg @ref HAL_SAI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID.
+ * @arg @ref HAL_SAI_TX_COMPLETE_CB_ID transmit complete callback ID.
+ * @arg @ref HAL_SAI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID.
+ * @arg @ref HAL_SAI_ERROR_CB_ID error callback ID.
+ * @arg @ref HAL_SAI_MSPINIT_CB_ID MSP init callback ID.
+ * @arg @ref HAL_SAI_MSPDEINIT_CB_ID MSP de-init callback ID.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_SAI_UnRegisterCallback(SAI_HandleTypeDef *hsai,
+ HAL_SAI_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (HAL_SAI_STATE_READY == hsai->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SAI_RX_COMPLETE_CB_ID :
+ hsai->RxCpltCallback = HAL_SAI_RxCpltCallback;
+ break;
+ case HAL_SAI_RX_HALFCOMPLETE_CB_ID :
+ hsai->RxHalfCpltCallback = HAL_SAI_RxHalfCpltCallback;
+ break;
+ case HAL_SAI_TX_COMPLETE_CB_ID :
+ hsai->TxCpltCallback = HAL_SAI_TxCpltCallback;
+ break;
+ case HAL_SAI_TX_HALFCOMPLETE_CB_ID :
+ hsai->TxHalfCpltCallback = HAL_SAI_TxHalfCpltCallback;
+ break;
+ case HAL_SAI_ERROR_CB_ID :
+ hsai->ErrorCallback = HAL_SAI_ErrorCallback;
+ break;
+ case HAL_SAI_MSPINIT_CB_ID :
+ hsai->MspInitCallback = HAL_SAI_MspInit;
+ break;
+ case HAL_SAI_MSPDEINIT_CB_ID :
+ hsai->MspDeInitCallback = HAL_SAI_MspDeInit;
+ break;
+ default :
+ /* update the error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_SAI_STATE_RESET == hsai->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SAI_MSPINIT_CB_ID :
+ hsai->MspInitCallback = HAL_SAI_MspInit;
+ break;
+ case HAL_SAI_MSPDEINIT_CB_ID :
+ hsai->MspDeInitCallback = HAL_SAI_MspDeInit;
+ break;
+ default :
+ /* update the error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update the error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+ return status;
+}
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Exported_Functions_Group2 IO operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the SAI data
+ transfers.
+
+ (+) There are two modes of transfer:
+ (++) Blocking mode : The communication is performed in the polling mode.
+ The status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode : The communication is performed using Interrupts
+ or DMA. These functions return the status of the transfer startup.
+ The end of the data processing will be indicated through the
+ dedicated SAI IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+
+ (+) Blocking mode functions are :
+ (++) HAL_SAI_Transmit()
+ (++) HAL_SAI_Receive()
+
+ (+) Non Blocking mode functions with Interrupt are :
+ (++) HAL_SAI_Transmit_IT()
+ (++) HAL_SAI_Receive_IT()
+
+ (+) Non Blocking mode functions with DMA are :
+ (++) HAL_SAI_Transmit_DMA()
+ (++) HAL_SAI_Receive_DMA()
+
+ (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (++) HAL_SAI_TxCpltCallback()
+ (++) HAL_SAI_RxCpltCallback()
+ (++) HAL_SAI_ErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmit an amount of data in blocking mode.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t temp;
+
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ if (hsai->State == HAL_SAI_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsai);
+
+ hsai->XferSize = Size;
+ hsai->XferCount = Size;
+ hsai->pBuffPtr = pData;
+ hsai->State = HAL_SAI_STATE_BUSY_TX;
+ hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+
+ /* Check if the SAI is already enabled */
+ if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
+ {
+ /* fill the fifo with data before to enabled the SAI */
+ SAI_FillFifo(hsai);
+ /* Enable SAI peripheral */
+ __HAL_SAI_ENABLE(hsai);
+ }
+
+ while (hsai->XferCount > 0U)
+ {
+ /* Write data if the FIFO is not full */
+ if ((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL)
+ {
+ if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
+ {
+ hsai->Instance->DR = *hsai->pBuffPtr;
+ hsai->pBuffPtr++;
+ }
+ else if (hsai->Init.DataSize <= SAI_DATASIZE_16)
+ {
+ temp = (uint32_t)(*hsai->pBuffPtr);
+ hsai->pBuffPtr++;
+ temp |= ((uint32_t)(*hsai->pBuffPtr) << 8);
+ hsai->pBuffPtr++;
+ hsai->Instance->DR = temp;
+ }
+ else
+ {
+ temp = (uint32_t)(*hsai->pBuffPtr);
+ hsai->pBuffPtr++;
+ temp |= ((uint32_t)(*hsai->pBuffPtr) << 8);
+ hsai->pBuffPtr++;
+ temp |= ((uint32_t)(*hsai->pBuffPtr) << 16);
+ hsai->pBuffPtr++;
+ temp |= ((uint32_t)(*hsai->pBuffPtr) << 24);
+ hsai->pBuffPtr++;
+ hsai->Instance->DR = temp;
+ }
+ hsai->XferCount--;
+ }
+ else
+ {
+ /* Check for the Timeout */
+ if ((((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) && (Timeout != HAL_MAX_DELAY))
+ {
+ /* Update error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
+
+ /* Clear all the flags */
+ hsai->Instance->CLRFR = 0xFFFFFFFFU;
+
+ /* Disable SAI peripheral */
+ /* No need to check return value because state update, unlock and error return will be performed later */
+ (void) SAI_Disable(hsai);
+
+ /* Flush the fifo */
+ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
+
+ /* Change the SAI state */
+ hsai->State = HAL_SAI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsai);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ hsai->State = HAL_SAI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsai);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be received
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t temp;
+
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ if (hsai->State == HAL_SAI_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsai);
+
+ hsai->pBuffPtr = pData;
+ hsai->XferSize = Size;
+ hsai->XferCount = Size;
+ hsai->State = HAL_SAI_STATE_BUSY_RX;
+ hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+
+ /* Check if the SAI is already enabled */
+ if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
+ {
+ /* Enable SAI peripheral */
+ __HAL_SAI_ENABLE(hsai);
+ }
+
+ /* Receive data */
+ while (hsai->XferCount > 0U)
+ {
+ if ((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_EMPTY)
+ {
+ if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
+ {
+ *hsai->pBuffPtr = (uint8_t)hsai->Instance->DR;
+ hsai->pBuffPtr++;
+ }
+ else if (hsai->Init.DataSize <= SAI_DATASIZE_16)
+ {
+ temp = hsai->Instance->DR;
+ *hsai->pBuffPtr = (uint8_t)temp;
+ hsai->pBuffPtr++;
+ *hsai->pBuffPtr = (uint8_t)(temp >> 8);
+ hsai->pBuffPtr++;
+ }
+ else
+ {
+ temp = hsai->Instance->DR;
+ *hsai->pBuffPtr = (uint8_t)temp;
+ hsai->pBuffPtr++;
+ *hsai->pBuffPtr = (uint8_t)(temp >> 8);
+ hsai->pBuffPtr++;
+ *hsai->pBuffPtr = (uint8_t)(temp >> 16);
+ hsai->pBuffPtr++;
+ *hsai->pBuffPtr = (uint8_t)(temp >> 24);
+ hsai->pBuffPtr++;
+ }
+ hsai->XferCount--;
+ }
+ else
+ {
+ /* Check for the Timeout */
+ if ((((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) && (Timeout != HAL_MAX_DELAY))
+ {
+ /* Update error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
+
+ /* Clear all the flags */
+ hsai->Instance->CLRFR = 0xFFFFFFFFU;
+
+ /* Disable SAI peripheral */
+ /* No need to check return value because state update, unlock and error return will be performed later */
+ (void) SAI_Disable(hsai);
+
+ /* Flush the fifo */
+ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
+
+ /* Change the SAI state */
+ hsai->State = HAL_SAI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsai);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ hsai->State = HAL_SAI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsai);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with Interrupt.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
+{
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ if (hsai->State == HAL_SAI_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsai);
+
+ hsai->pBuffPtr = pData;
+ hsai->XferSize = Size;
+ hsai->XferCount = Size;
+ hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+ hsai->State = HAL_SAI_STATE_BUSY_TX;
+
+ if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
+ {
+ hsai->InterruptServiceRoutine = SAI_Transmit_IT8Bit;
+ }
+ else if (hsai->Init.DataSize <= SAI_DATASIZE_16)
+ {
+ hsai->InterruptServiceRoutine = SAI_Transmit_IT16Bit;
+ }
+ else
+ {
+ hsai->InterruptServiceRoutine = SAI_Transmit_IT32Bit;
+ }
+
+ /* Fill the fifo before starting the communication */
+ SAI_FillFifo(hsai);
+
+ /* Enable FRQ and OVRUDR interrupts */
+ __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+
+ /* Check if the SAI is already enabled */
+ if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
+ {
+ /* Enable SAI peripheral */
+ __HAL_SAI_ENABLE(hsai);
+ }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsai);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with Interrupt.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be received
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
+{
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ if (hsai->State == HAL_SAI_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsai);
+
+ hsai->pBuffPtr = pData;
+ hsai->XferSize = Size;
+ hsai->XferCount = Size;
+ hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+ hsai->State = HAL_SAI_STATE_BUSY_RX;
+
+ if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
+ {
+ hsai->InterruptServiceRoutine = SAI_Receive_IT8Bit;
+ }
+ else if (hsai->Init.DataSize <= SAI_DATASIZE_16)
+ {
+ hsai->InterruptServiceRoutine = SAI_Receive_IT16Bit;
+ }
+ else
+ {
+ hsai->InterruptServiceRoutine = SAI_Receive_IT32Bit;
+ }
+
+ /* Enable TXE and OVRUDR interrupts */
+ __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+
+ /* Check if the SAI is already enabled */
+ if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
+ {
+ /* Enable SAI peripheral */
+ __HAL_SAI_ENABLE(hsai);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsai);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Pause the audio stream playing from the Media.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai)
+{
+ /* Process Locked */
+ __HAL_LOCK(hsai);
+
+ /* Pause the audio file playing by disabling the SAI DMA requests */
+ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsai);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resume the audio stream playing from the Media.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai)
+{
+ /* Process Locked */
+ __HAL_LOCK(hsai);
+
+ /* Enable the SAI DMA requests */
+ hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
+
+ /* If the SAI peripheral is still not enabled, enable it */
+ if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
+ {
+ /* Enable SAI peripheral */
+ __HAL_SAI_ENABLE(hsai);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsai);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the audio stream playing from the Media.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process Locked */
+ __HAL_LOCK(hsai);
+
+ /* Disable the SAI DMA request */
+ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
+
+ /* Abort the SAI Tx DMA Stream */
+ if ((hsai->State == HAL_SAI_STATE_BUSY_TX) && (hsai->hdmatx != NULL))
+ {
+ if (HAL_DMA_Abort(hsai->hdmatx) != HAL_OK)
+ {
+ /* If the DMA Tx errorCode is different from DMA No Transfer then return Error */
+ if (hsai->hdmatx->ErrorCode != HAL_DMA_ERROR_NO_XFER)
+ {
+ status = HAL_ERROR;
+ hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
+ }
+ }
+ }
+
+ /* Abort the SAI Rx DMA Stream */
+ if ((hsai->State == HAL_SAI_STATE_BUSY_RX) && (hsai->hdmarx != NULL))
+ {
+ if (HAL_DMA_Abort(hsai->hdmarx) != HAL_OK)
+ {
+ /* If the DMA Rx errorCode is different from DMA No Transfer then return Error */
+ if (hsai->hdmarx->ErrorCode != HAL_DMA_ERROR_NO_XFER)
+ {
+ status = HAL_ERROR;
+ hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
+ }
+ }
+ }
+
+ /* Disable SAI peripheral */
+ if (SAI_Disable(hsai) != HAL_OK)
+ {
+ status = HAL_ERROR;
+ }
+
+ /* Flush the fifo */
+ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
+
+ /* Set hsai state to ready */
+ hsai->State = HAL_SAI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsai);
+
+ return status;
+}
+
+/**
+ * @brief Abort the current transfer and disable the SAI.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process Locked */
+ __HAL_LOCK(hsai);
+
+ /* Check SAI DMA is enabled or not */
+ if ((hsai->Instance->CR1 & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
+ {
+ /* Disable the SAI DMA request */
+ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
+
+ /* Abort the SAI Tx DMA Stream */
+ if ((hsai->State == HAL_SAI_STATE_BUSY_TX) && (hsai->hdmatx != NULL))
+ {
+ if (HAL_DMA_Abort(hsai->hdmatx) != HAL_OK)
+ {
+ /* If the DMA Tx errorCode is different from DMA No Transfer then return Error */
+ if (hsai->hdmatx->ErrorCode != HAL_DMA_ERROR_NO_XFER)
+ {
+ status = HAL_ERROR;
+ hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
+ }
+ }
+ }
+
+ /* Abort the SAI Rx DMA Stream */
+ if ((hsai->State == HAL_SAI_STATE_BUSY_RX) && (hsai->hdmarx != NULL))
+ {
+ if (HAL_DMA_Abort(hsai->hdmarx) != HAL_OK)
+ {
+ /* If the DMA Rx errorCode is different from DMA No Transfer then return Error */
+ if (hsai->hdmarx->ErrorCode != HAL_DMA_ERROR_NO_XFER)
+ {
+ status = HAL_ERROR;
+ hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
+ }
+ }
+ }
+ }
+
+ /* Disabled All interrupt and clear all the flag */
+ hsai->Instance->IMR = 0;
+ hsai->Instance->CLRFR = 0xFFFFFFFFU;
+
+ /* Disable SAI peripheral */
+ if (SAI_Disable(hsai) != HAL_OK)
+ {
+ status = HAL_ERROR;
+ }
+
+ /* Flush the fifo */
+ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
+
+ /* Set hsai state to ready */
+ hsai->State = HAL_SAI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsai);
+
+ return status;
+}
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with DMA.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef status;
+ uint32_t tickstart = HAL_GetTick();
+
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ if (hsai->State == HAL_SAI_STATE_READY)
+ {
+ uint32_t dmaSrcSize;
+
+ /* Process Locked */
+ __HAL_LOCK(hsai);
+
+ hsai->pBuffPtr = pData;
+ hsai->XferSize = Size;
+ hsai->XferCount = Size;
+ hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+ hsai->State = HAL_SAI_STATE_BUSY_TX;
+
+ /* Set the SAI Tx DMA Half transfer complete callback */
+ hsai->hdmatx->XferHalfCpltCallback = SAI_DMATxHalfCplt;
+
+ /* Set the SAI TxDMA transfer complete callback */
+ hsai->hdmatx->XferCpltCallback = SAI_DMATxCplt;
+
+ /* Set the DMA error callback */
+ hsai->hdmatx->XferErrorCallback = SAI_DMAError;
+
+ /* Set the DMA Tx abort callback */
+ hsai->hdmatx->XferAbortCallback = NULL;
+
+ /* For transmission, the DMA source is data buffer.
+ We have to compute DMA size of a source block transfer in bytes according SAI data size. */
+ if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
+ {
+ dmaSrcSize = (uint32_t) Size;
+ }
+ else if (hsai->Init.DataSize <= SAI_DATASIZE_16)
+ {
+ dmaSrcSize = 2U * (uint32_t) Size;
+ }
+ else
+ {
+ dmaSrcSize = 4U * (uint32_t) Size;
+ }
+
+ /* Enable the Tx DMA Stream */
+ if ((hsai->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if (hsai->hdmatx->LinkedListQueue != NULL)
+ {
+ /* Set DMA data size */
+ hsai->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = dmaSrcSize;
+
+ /* Set DMA source address */
+ hsai->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hsai->pBuffPtr;
+
+ /* Set DMA destination address */
+ hsai->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hsai->Instance->DR;
+
+ status = HAL_DMAEx_List_Start_IT(hsai->hdmatx);
+ }
+ else
+ {
+ __HAL_UNLOCK(hsai);
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_DMA_Start_IT(hsai->hdmatx, (uint32_t)hsai->pBuffPtr, (uint32_t)&hsai->Instance->DR, dmaSrcSize);
+ }
+
+ if (status != HAL_OK)
+ {
+ __HAL_UNLOCK(hsai);
+ return HAL_ERROR;
+ }
+
+ /* Enable the interrupts for error handling */
+ __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
+
+ /* Enable SAI Tx DMA Request */
+ hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
+
+ /* Wait until FIFO is not empty */
+ while ((hsai->Instance->SR & SAI_xSR_FLVL) == SAI_FIFOSTATUS_EMPTY)
+ {
+ /* Check for the Timeout */
+ if ((HAL_GetTick() - tickstart) > SAI_LONG_TIMEOUT)
+ {
+ /* Update error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsai);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check if the SAI is already enabled */
+ if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
+ {
+ /* Enable SAI peripheral */
+ __HAL_SAI_ENABLE(hsai);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsai);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with DMA.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be received
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef status;
+
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ if (hsai->State == HAL_SAI_STATE_READY)
+ {
+ uint32_t dmaSrcSize;
+
+ /* Process Locked */
+ __HAL_LOCK(hsai);
+
+ hsai->pBuffPtr = pData;
+ hsai->XferSize = Size;
+ hsai->XferCount = Size;
+ hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+ hsai->State = HAL_SAI_STATE_BUSY_RX;
+
+ /* Set the SAI Rx DMA Half transfer complete callback */
+ hsai->hdmarx->XferHalfCpltCallback = SAI_DMARxHalfCplt;
+
+ /* Set the SAI Rx DMA transfer complete callback */
+ hsai->hdmarx->XferCpltCallback = SAI_DMARxCplt;
+
+ /* Set the DMA error callback */
+ hsai->hdmarx->XferErrorCallback = SAI_DMAError;
+
+ /* Set the DMA Rx abort callback */
+ hsai->hdmarx->XferAbortCallback = NULL;
+
+ /* For reception, the DMA source is SAI DR register.
+ We have to compute DMA size of a source block transfer in bytes according SAI data size. */
+ if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
+ {
+ dmaSrcSize = (uint32_t) Size;
+ }
+ else if (hsai->Init.DataSize <= SAI_DATASIZE_16)
+ {
+ dmaSrcSize = 2U * (uint32_t) Size;
+ }
+ else
+ {
+ dmaSrcSize = 4U * (uint32_t) Size;
+ }
+
+ /* Enable the Rx DMA Stream */
+ if ((hsai->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if (hsai->hdmarx->LinkedListQueue != NULL)
+ {
+ /* Set DMA data size */
+ hsai->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = dmaSrcSize;
+
+ /* Set DMA source address */
+ hsai->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hsai->Instance->DR;
+
+ /* Set DMA destination address */
+ hsai->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hsai->pBuffPtr;
+
+ status = HAL_DMAEx_List_Start_IT(hsai->hdmarx);
+ }
+ else
+ {
+ __HAL_UNLOCK(hsai);
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_DMA_Start_IT(hsai->hdmarx, (uint32_t)&hsai->Instance->DR, (uint32_t)hsai->pBuffPtr, dmaSrcSize);
+ }
+
+ if (status != HAL_OK)
+ {
+ __HAL_UNLOCK(hsai);
+ return HAL_ERROR;
+ }
+
+ /* Enable the interrupts for error handling */
+ __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
+
+ /* Enable SAI Rx DMA Request */
+ hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
+
+ /* Check if the SAI is already enabled */
+ if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
+ {
+ /* Enable SAI peripheral */
+ __HAL_SAI_ENABLE(hsai);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsai);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Enable the Tx mute mode.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @param val value sent during the mute @ref SAI_Block_Mute_Value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val)
+{
+ assert_param(IS_SAI_BLOCK_MUTE_VALUE(val));
+
+ if (hsai->State != HAL_SAI_STATE_RESET)
+ {
+ CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE);
+ SET_BIT(hsai->Instance->CR2, SAI_xCR2_MUTE | (uint32_t)val);
+ return HAL_OK;
+ }
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Disable the Tx mute mode.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai)
+{
+ if (hsai->State != HAL_SAI_STATE_RESET)
+ {
+ CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE);
+ return HAL_OK;
+ }
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Enable the Rx mute detection.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @param callback function called when the mute is detected.
+ * @param counter number a data before mute detection max 63.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter)
+{
+ assert_param(IS_SAI_BLOCK_MUTE_COUNTER(counter));
+
+ if (hsai->State != HAL_SAI_STATE_RESET)
+ {
+ /* set the mute counter */
+ CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTECNT);
+ SET_BIT(hsai->Instance->CR2, (uint32_t)((uint32_t)counter << SAI_xCR2_MUTECNT_Pos));
+ hsai->mutecallback = callback;
+ /* enable the IT interrupt */
+ __HAL_SAI_ENABLE_IT(hsai, SAI_IT_MUTEDET);
+ return HAL_OK;
+ }
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Disable the Rx mute detection.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai)
+{
+ if (hsai->State != HAL_SAI_STATE_RESET)
+ {
+ /* set the mutecallback to NULL */
+ hsai->mutecallback = NULL;
+ /* enable the IT interrupt */
+ __HAL_SAI_DISABLE_IT(hsai, SAI_IT_MUTEDET);
+ return HAL_OK;
+ }
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Handle SAI interrupt request.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None
+ */
+void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
+{
+ if (hsai->State != HAL_SAI_STATE_RESET)
+ {
+ uint32_t itflags = hsai->Instance->SR;
+ uint32_t itsources = hsai->Instance->IMR;
+ uint32_t cr1config = hsai->Instance->CR1;
+ uint32_t tmperror;
+
+ /* SAI Fifo request interrupt occurred -----------------------------------*/
+ if (((itflags & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((itsources & SAI_IT_FREQ) == SAI_IT_FREQ))
+ {
+ hsai->InterruptServiceRoutine(hsai);
+ }
+ /* SAI Overrun error interrupt occurred ----------------------------------*/
+ else if (((itflags & SAI_FLAG_OVRUDR) == SAI_FLAG_OVRUDR) && ((itsources & SAI_IT_OVRUDR) == SAI_IT_OVRUDR))
+ {
+ /* Clear the SAI Overrun flag */
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
+ /* Get the SAI error code */
+ tmperror = ((hsai->State == HAL_SAI_STATE_BUSY_RX) ? HAL_SAI_ERROR_OVR : HAL_SAI_ERROR_UDR);
+ /* Change the SAI error code */
+ hsai->ErrorCode |= tmperror;
+ /* the transfer is not stopped, we will forward the information to the user and we let
+ the user decide what needs to be done */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->ErrorCallback(hsai);
+#else
+ HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+ }
+ /* SAI mutedet interrupt occurred ----------------------------------*/
+ else if (((itflags & SAI_FLAG_MUTEDET) == SAI_FLAG_MUTEDET) && ((itsources & SAI_IT_MUTEDET) == SAI_IT_MUTEDET))
+ {
+ /* Clear the SAI mutedet flag */
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_MUTEDET);
+ /* call the call back function */
+ if (hsai->mutecallback != NULL)
+ {
+ /* inform the user that an RX mute event has been detected */
+ hsai->mutecallback();
+ }
+ }
+ /* SAI AFSDET interrupt occurred ----------------------------------*/
+ else if (((itflags & SAI_FLAG_AFSDET) == SAI_FLAG_AFSDET) && ((itsources & SAI_IT_AFSDET) == SAI_IT_AFSDET))
+ {
+ /* Clear the SAI AFSDET flag */
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_AFSDET);
+
+ /* Change the SAI error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_AFSDET;
+
+ /* Check SAI DMA is enabled or not */
+ if ((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
+ {
+ /* Abort the SAI DMA Streams */
+ if (hsai->hdmatx != NULL)
+ {
+ /* Set the DMA Tx abort callback */
+ hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
+
+ /* Abort DMA in IT mode */
+ if (HAL_DMA_Abort_IT(hsai->hdmatx) != HAL_OK)
+ {
+ /* Update SAI error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
+
+ /* Call SAI error callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->ErrorCallback(hsai);
+#else
+ HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+ }
+ }
+ if (hsai->hdmarx != NULL)
+ {
+ /* Set the DMA Rx abort callback */
+ hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
+
+ /* Abort DMA in IT mode */
+ if (HAL_DMA_Abort_IT(hsai->hdmarx) != HAL_OK)
+ {
+ /* Update SAI error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
+
+ /* Call SAI error callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->ErrorCallback(hsai);
+#else
+ HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+ }
+ }
+ }
+ else
+ {
+ /* Abort SAI */
+ /* No need to check return value because HAL_SAI_ErrorCallback will be called later */
+ (void) HAL_SAI_Abort(hsai);
+
+ /* Set error callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->ErrorCallback(hsai);
+#else
+ HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+ }
+ }
+ /* SAI LFSDET interrupt occurred ----------------------------------*/
+ else if (((itflags & SAI_FLAG_LFSDET) == SAI_FLAG_LFSDET) && ((itsources & SAI_IT_LFSDET) == SAI_IT_LFSDET))
+ {
+ /* Clear the SAI LFSDET flag */
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_LFSDET);
+
+ /* Change the SAI error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_LFSDET;
+
+ /* Check SAI DMA is enabled or not */
+ if ((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
+ {
+ /* Abort the SAI DMA Streams */
+ if (hsai->hdmatx != NULL)
+ {
+ /* Set the DMA Tx abort callback */
+ hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
+
+ /* Abort DMA in IT mode */
+ if (HAL_DMA_Abort_IT(hsai->hdmatx) != HAL_OK)
+ {
+ /* Update SAI error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
+
+ /* Call SAI error callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->ErrorCallback(hsai);
+#else
+ HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+ }
+ }
+ if (hsai->hdmarx != NULL)
+ {
+ /* Set the DMA Rx abort callback */
+ hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
+
+ /* Abort DMA in IT mode */
+ if (HAL_DMA_Abort_IT(hsai->hdmarx) != HAL_OK)
+ {
+ /* Update SAI error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
+
+ /* Call SAI error callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->ErrorCallback(hsai);
+#else
+ HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+ }
+ }
+ }
+ else
+ {
+ /* Abort SAI */
+ /* No need to check return value because HAL_SAI_ErrorCallback will be called later */
+ (void) HAL_SAI_Abort(hsai);
+
+ /* Set error callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->ErrorCallback(hsai);
+#else
+ HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+ }
+ }
+ /* SAI WCKCFG interrupt occurred ----------------------------------*/
+ else if (((itflags & SAI_FLAG_WCKCFG) == SAI_FLAG_WCKCFG) && ((itsources & SAI_IT_WCKCFG) == SAI_IT_WCKCFG))
+ {
+ /* Clear the SAI WCKCFG flag */
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_WCKCFG);
+
+ /* Change the SAI error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_WCKCFG;
+
+ /* Check SAI DMA is enabled or not */
+ if ((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
+ {
+ /* Abort the SAI DMA Streams */
+ if (hsai->hdmatx != NULL)
+ {
+ /* Set the DMA Tx abort callback */
+ hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
+
+ /* Abort DMA in IT mode */
+ if (HAL_DMA_Abort_IT(hsai->hdmatx) != HAL_OK)
+ {
+ /* Update SAI error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
+
+ /* Call SAI error callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->ErrorCallback(hsai);
+#else
+ HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+ }
+ }
+ if (hsai->hdmarx != NULL)
+ {
+ /* Set the DMA Rx abort callback */
+ hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
+
+ /* Abort DMA in IT mode */
+ if (HAL_DMA_Abort_IT(hsai->hdmarx) != HAL_OK)
+ {
+ /* Update SAI error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
+
+ /* Call SAI error callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->ErrorCallback(hsai);
+#else
+ HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+ }
+ }
+ }
+ else
+ {
+ /* If WCKCFG occurs, SAI audio block is automatically disabled */
+ /* Disable all interrupts and clear all flags */
+ hsai->Instance->IMR = 0U;
+ hsai->Instance->CLRFR = 0xFFFFFFFFU;
+ /* Set the SAI state to ready to be able to start again the process */
+ hsai->State = HAL_SAI_STATE_READY;
+
+ /* Initialize XferCount */
+ hsai->XferCount = 0U;
+
+ /* SAI error callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->ErrorCallback(hsai);
+#else
+ HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+ }
+ }
+ /* SAI CNRDY interrupt occurred ----------------------------------*/
+ else if (((itflags & SAI_FLAG_CNRDY) == SAI_FLAG_CNRDY) && ((itsources & SAI_IT_CNRDY) == SAI_IT_CNRDY))
+ {
+ /* Clear the SAI CNRDY flag */
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_CNRDY);
+ /* Change the SAI error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_CNREADY;
+ /* the transfer is not stopped, we will forward the information to the user and we let
+ the user decide what needs to be done */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->ErrorCallback(hsai);
+#else
+ HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+}
+
+/**
+ * @brief Tx Transfer completed callback.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None
+ */
+__weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsai);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SAI_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx Transfer Half completed callback.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None
+ */
+__weak void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsai);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SAI_TxHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callback.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None
+ */
+__weak void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsai);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SAI_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer half completed callback.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None
+ */
+__weak void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsai);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SAI_RxHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SAI error callback.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None
+ */
+__weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsai);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SAI_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Exported_Functions_Group3 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the SAI handle state.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval HAL state
+ */
+HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai)
+{
+ return hsai->State;
+}
+
+/**
+ * @brief Return the SAI error code.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for the specified SAI Block.
+ * @retval SAI Error Code
+ */
+uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai)
+{
+ return hsai->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SAI_Private_Functions
+ * @brief Private functions
+ * @{
+ */
+
+/**
+ * @brief Initialize the SAI I2S protocol according to the specified parameters
+ * in the SAI_InitTypeDef and create the associated handle.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @param protocol one of the supported protocol.
+ * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize.
+ * @param nbslot number of slot minimum value is 2 and max is 16.
+ * the value must be a multiple of 2.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ hsai->Init.Protocol = SAI_FREE_PROTOCOL;
+ hsai->Init.FirstBit = SAI_FIRSTBIT_MSB;
+ /* Compute ClockStrobing according AudioMode */
+ if ((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
+ {
+ /* Transmit */
+ hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE;
+ }
+ else
+ {
+ /* Receive */
+ hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_RISINGEDGE;
+ }
+ hsai->FrameInit.FSDefinition = SAI_FS_CHANNEL_IDENTIFICATION;
+ hsai->SlotInit.SlotActive = SAI_SLOTACTIVE_ALL;
+ hsai->SlotInit.FirstBitOffset = 0;
+ hsai->SlotInit.SlotNumber = nbslot;
+
+ /* in IS2 the number of slot must be even */
+ if ((nbslot & 0x1U) != 0U)
+ {
+ return HAL_ERROR;
+ }
+
+ if (protocol == SAI_I2S_STANDARD)
+ {
+ hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW;
+ hsai->FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT;
+ }
+ else
+ {
+ /* SAI_I2S_MSBJUSTIFIED or SAI_I2S_LSBJUSTIFIED */
+ hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH;
+ hsai->FrameInit.FSOffset = SAI_FS_FIRSTBIT;
+ }
+
+ /* Frame definition */
+ switch (datasize)
+ {
+ case SAI_PROTOCOL_DATASIZE_16BIT:
+ hsai->Init.DataSize = SAI_DATASIZE_16;
+ hsai->FrameInit.FrameLength = 32U * (nbslot / 2U);
+ hsai->FrameInit.ActiveFrameLength = 16U * (nbslot / 2U);
+ hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B;
+ break;
+ case SAI_PROTOCOL_DATASIZE_16BITEXTENDED :
+ hsai->Init.DataSize = SAI_DATASIZE_16;
+ hsai->FrameInit.FrameLength = 64U * (nbslot / 2U);
+ hsai->FrameInit.ActiveFrameLength = 32U * (nbslot / 2U);
+ hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
+ break;
+ case SAI_PROTOCOL_DATASIZE_24BIT:
+ hsai->Init.DataSize = SAI_DATASIZE_24;
+ hsai->FrameInit.FrameLength = 64U * (nbslot / 2U);
+ hsai->FrameInit.ActiveFrameLength = 32U * (nbslot / 2U);
+ hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
+ break;
+ case SAI_PROTOCOL_DATASIZE_32BIT:
+ hsai->Init.DataSize = SAI_DATASIZE_32;
+ hsai->FrameInit.FrameLength = 64U * (nbslot / 2U);
+ hsai->FrameInit.ActiveFrameLength = 32U * (nbslot / 2U);
+ hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
+ break;
+ default :
+ status = HAL_ERROR;
+ break;
+ }
+ if (protocol == SAI_I2S_LSBJUSTIFIED)
+ {
+ if (datasize == SAI_PROTOCOL_DATASIZE_16BITEXTENDED)
+ {
+ hsai->SlotInit.FirstBitOffset = 16;
+ }
+ if (datasize == SAI_PROTOCOL_DATASIZE_24BIT)
+ {
+ hsai->SlotInit.FirstBitOffset = 8;
+ }
+ }
+ return status;
+}
+
+/**
+ * @brief Initialize the SAI PCM protocol according to the specified parameters
+ * in the SAI_InitTypeDef and create the associated handle.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @param protocol one of the supported protocol
+ * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize
+ * @param nbslot number of slot minimum value is 1 and the max is 16.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ hsai->Init.Protocol = SAI_FREE_PROTOCOL;
+ hsai->Init.FirstBit = SAI_FIRSTBIT_MSB;
+ /* Compute ClockStrobing according AudioMode */
+ if ((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
+ {
+ /* Transmit */
+ hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_RISINGEDGE;
+ }
+ else
+ {
+ /* Receive */
+ hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE;
+ }
+ hsai->FrameInit.FSDefinition = SAI_FS_STARTFRAME;
+ hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH;
+ hsai->FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT;
+ hsai->SlotInit.FirstBitOffset = 0;
+ hsai->SlotInit.SlotNumber = nbslot;
+ hsai->SlotInit.SlotActive = SAI_SLOTACTIVE_ALL;
+
+ if (protocol == SAI_PCM_SHORT)
+ {
+ hsai->FrameInit.ActiveFrameLength = 1;
+ }
+ else
+ {
+ /* SAI_PCM_LONG */
+ hsai->FrameInit.ActiveFrameLength = 13;
+ }
+
+ switch (datasize)
+ {
+ case SAI_PROTOCOL_DATASIZE_16BIT:
+ hsai->Init.DataSize = SAI_DATASIZE_16;
+ hsai->FrameInit.FrameLength = 16U * nbslot;
+ hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B;
+ break;
+ case SAI_PROTOCOL_DATASIZE_16BITEXTENDED :
+ hsai->Init.DataSize = SAI_DATASIZE_16;
+ hsai->FrameInit.FrameLength = 32U * nbslot;
+ hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
+ break;
+ case SAI_PROTOCOL_DATASIZE_24BIT :
+ hsai->Init.DataSize = SAI_DATASIZE_24;
+ hsai->FrameInit.FrameLength = 32U * nbslot;
+ hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
+ break;
+ case SAI_PROTOCOL_DATASIZE_32BIT:
+ hsai->Init.DataSize = SAI_DATASIZE_32;
+ hsai->FrameInit.FrameLength = 32U * nbslot;
+ hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
+ break;
+ default :
+ status = HAL_ERROR;
+ break;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Fill the fifo.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None
+ */
+static void SAI_FillFifo(SAI_HandleTypeDef *hsai)
+{
+ uint32_t temp;
+
+ /* fill the fifo with data before to enabled the SAI */
+ while (((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) && (hsai->XferCount > 0U))
+ {
+ if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
+ {
+ hsai->Instance->DR = *hsai->pBuffPtr;
+ hsai->pBuffPtr++;
+ }
+ else if (hsai->Init.DataSize <= SAI_DATASIZE_16)
+ {
+ temp = (uint32_t)(*hsai->pBuffPtr);
+ hsai->pBuffPtr++;
+ temp |= ((uint32_t)(*hsai->pBuffPtr) << 8);
+ hsai->pBuffPtr++;
+ hsai->Instance->DR = temp;
+ }
+ else
+ {
+ temp = (uint32_t)(*hsai->pBuffPtr);
+ hsai->pBuffPtr++;
+ temp |= ((uint32_t)(*hsai->pBuffPtr) << 8);
+ hsai->pBuffPtr++;
+ temp |= ((uint32_t)(*hsai->pBuffPtr) << 16);
+ hsai->pBuffPtr++;
+ temp |= ((uint32_t)(*hsai->pBuffPtr) << 24);
+ hsai->pBuffPtr++;
+ hsai->Instance->DR = temp;
+ }
+ hsai->XferCount--;
+ }
+}
+
+/**
+ * @brief Return the interrupt flag to set according the SAI setup.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @param mode SAI_MODE_DMA or SAI_MODE_IT
+ * @retval the list of the IT flag to enable
+ */
+static uint32_t SAI_InterruptFlag(const SAI_HandleTypeDef *hsai, SAI_ModeTypedef mode)
+{
+ uint32_t tmpIT = SAI_IT_OVRUDR;
+
+ if (mode == SAI_MODE_IT)
+ {
+ tmpIT |= SAI_IT_FREQ;
+ }
+
+ if ((hsai->Init.Protocol == SAI_AC97_PROTOCOL) &&
+ ((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODEMASTER_RX)))
+ {
+ tmpIT |= SAI_IT_CNRDY;
+ }
+
+ if ((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
+ {
+ tmpIT |= SAI_IT_AFSDET | SAI_IT_LFSDET;
+ }
+ else
+ {
+ /* hsai has been configured in master mode */
+ tmpIT |= SAI_IT_WCKCFG;
+ }
+ return tmpIT;
+}
+
+/**
+ * @brief Disable the SAI and wait for the disabling.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None
+ */
+static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai)
+{
+ uint32_t count = SAI_DEFAULT_TIMEOUT * (SystemCoreClock / 7U / 1000U);
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Disable the SAI instance */
+ __HAL_SAI_DISABLE(hsai);
+
+ do
+ {
+ /* Check for the Timeout */
+ if (count == 0U)
+ {
+ /* Update error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
+ status = HAL_TIMEOUT;
+ break;
+ }
+ count--;
+ } while ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != 0U);
+
+ return status;
+}
+
+/**
+ * @brief Tx Handler for Transmit in Interrupt mode 8-Bit transfer.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None
+ */
+static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai)
+{
+ if (hsai->XferCount == 0U)
+ {
+ /* Handle the end of the transmission */
+ /* Disable FREQ and OVRUDR interrupts */
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+ hsai->State = HAL_SAI_STATE_READY;
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->TxCpltCallback(hsai);
+#else
+ HAL_SAI_TxCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Write data on DR register */
+ hsai->Instance->DR = *hsai->pBuffPtr;
+ hsai->pBuffPtr++;
+ hsai->XferCount--;
+ }
+}
+
+/**
+ * @brief Tx Handler for Transmit in Interrupt mode for 16-Bit transfer.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None
+ */
+static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai)
+{
+ if (hsai->XferCount == 0U)
+ {
+ /* Handle the end of the transmission */
+ /* Disable FREQ and OVRUDR interrupts */
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+ hsai->State = HAL_SAI_STATE_READY;
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->TxCpltCallback(hsai);
+#else
+ HAL_SAI_TxCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Write data on DR register */
+ uint32_t temp;
+ temp = (uint32_t)(*hsai->pBuffPtr);
+ hsai->pBuffPtr++;
+ temp |= ((uint32_t)(*hsai->pBuffPtr) << 8);
+ hsai->pBuffPtr++;
+ hsai->Instance->DR = temp;
+ hsai->XferCount--;
+ }
+}
+
+/**
+ * @brief Tx Handler for Transmit in Interrupt mode for 32-Bit transfer.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None
+ */
+static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai)
+{
+ if (hsai->XferCount == 0U)
+ {
+ /* Handle the end of the transmission */
+ /* Disable FREQ and OVRUDR interrupts */
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+ hsai->State = HAL_SAI_STATE_READY;
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->TxCpltCallback(hsai);
+#else
+ HAL_SAI_TxCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Write data on DR register */
+ uint32_t temp;
+ temp = (uint32_t)(*hsai->pBuffPtr);
+ hsai->pBuffPtr++;
+ temp |= ((uint32_t)(*hsai->pBuffPtr) << 8);
+ hsai->pBuffPtr++;
+ temp |= ((uint32_t)(*hsai->pBuffPtr) << 16);
+ hsai->pBuffPtr++;
+ temp |= ((uint32_t)(*hsai->pBuffPtr) << 24);
+ hsai->pBuffPtr++;
+ hsai->Instance->DR = temp;
+ hsai->XferCount--;
+ }
+}
+
+/**
+ * @brief Rx Handler for Receive in Interrupt mode 8-Bit transfer.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None
+ */
+static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai)
+{
+ /* Receive data */
+ *hsai->pBuffPtr = (uint8_t)hsai->Instance->DR;
+ hsai->pBuffPtr++;
+ hsai->XferCount--;
+
+ /* Check end of the transfer */
+ if (hsai->XferCount == 0U)
+ {
+ /* Disable TXE and OVRUDR interrupts */
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+
+ /* Clear the SAI Overrun flag */
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
+
+ hsai->State = HAL_SAI_STATE_READY;
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->RxCpltCallback(hsai);
+#else
+ HAL_SAI_RxCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief Rx Handler for Receive in Interrupt mode for 16-Bit transfer.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None
+ */
+static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai)
+{
+ uint32_t temp;
+
+ /* Receive data */
+ temp = hsai->Instance->DR;
+ *hsai->pBuffPtr = (uint8_t)temp;
+ hsai->pBuffPtr++;
+ *hsai->pBuffPtr = (uint8_t)(temp >> 8);
+ hsai->pBuffPtr++;
+ hsai->XferCount--;
+
+ /* Check end of the transfer */
+ if (hsai->XferCount == 0U)
+ {
+ /* Disable TXE and OVRUDR interrupts */
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+
+ /* Clear the SAI Overrun flag */
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
+
+ hsai->State = HAL_SAI_STATE_READY;
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->RxCpltCallback(hsai);
+#else
+ HAL_SAI_RxCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief Rx Handler for Receive in Interrupt mode for 32-Bit transfer.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None
+ */
+static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai)
+{
+ uint32_t temp;
+
+ /* Receive data */
+ temp = hsai->Instance->DR;
+ *hsai->pBuffPtr = (uint8_t)temp;
+ hsai->pBuffPtr++;
+ *hsai->pBuffPtr = (uint8_t)(temp >> 8);
+ hsai->pBuffPtr++;
+ *hsai->pBuffPtr = (uint8_t)(temp >> 16);
+ hsai->pBuffPtr++;
+ *hsai->pBuffPtr = (uint8_t)(temp >> 24);
+ hsai->pBuffPtr++;
+ hsai->XferCount--;
+
+ /* Check end of the transfer */
+ if (hsai->XferCount == 0U)
+ {
+ /* Disable TXE and OVRUDR interrupts */
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+
+ /* Clear the SAI Overrun flag */
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
+
+ hsai->State = HAL_SAI_STATE_READY;
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->RxCpltCallback(hsai);
+#else
+ HAL_SAI_RxCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief DMA SAI transmit process complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma)
+{
+ SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Check if DMA in circular mode */
+ if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR)
+ {
+ hsai->XferCount = 0;
+
+ /* Disable SAI Tx DMA Request */
+ hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
+
+ /* Stop the interrupts error handling */
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
+
+ hsai->State = HAL_SAI_STATE_READY;
+ }
+
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->TxCpltCallback(hsai);
+#else
+ HAL_SAI_TxCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA SAI transmit process half complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->TxHalfCpltCallback(hsai);
+#else
+ HAL_SAI_TxHalfCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA SAI receive process complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma)
+{
+ SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Check if DMA in circular mode*/
+ if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR)
+ {
+ /* Disable Rx DMA Request */
+ hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
+ hsai->XferCount = 0;
+
+ /* Stop the interrupts error handling */
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
+
+ hsai->State = HAL_SAI_STATE_READY;
+ }
+
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->RxCpltCallback(hsai);
+#else
+ HAL_SAI_RxCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA SAI receive process half complete callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->RxHalfCpltCallback(hsai);
+#else
+ HAL_SAI_RxHalfCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA SAI communication error callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SAI_DMAError(DMA_HandleTypeDef *hdma)
+{
+ SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Set SAI error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
+
+ /* Disable the SAI DMA request */
+ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
+
+ /* Disable SAI peripheral */
+ /* No need to check return value because state will be updated and HAL_SAI_ErrorCallback will be called later */
+ (void) SAI_Disable(hsai);
+
+ /* Set the SAI state ready to be able to start again the process */
+ hsai->State = HAL_SAI_STATE_READY;
+
+ /* Initialize XferCount */
+ hsai->XferCount = 0U;
+
+ /* SAI error Callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->ErrorCallback(hsai);
+#else
+ HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA SAI Abort callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SAI_DMAAbort(DMA_HandleTypeDef *hdma)
+{
+ SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Disable DMA request */
+ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
+
+ /* Disable all interrupts and clear all flags */
+ hsai->Instance->IMR = 0U;
+ hsai->Instance->CLRFR = 0xFFFFFFFFU;
+
+ if (hsai->ErrorCode != HAL_SAI_ERROR_WCKCFG)
+ {
+ /* Disable SAI peripheral */
+ /* No need to check return value because state will be updated and HAL_SAI_ErrorCallback will be called later */
+ (void) SAI_Disable(hsai);
+
+ /* Flush the fifo */
+ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
+ }
+ /* Set the SAI state to ready to be able to start again the process */
+ hsai->State = HAL_SAI_STATE_READY;
+
+ /* Initialize XferCount */
+ hsai->XferCount = 0U;
+
+ /* SAI error Callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->ErrorCallback(hsai);
+#else
+ HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_SAI_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sai_ex.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sai_ex.c
new file mode 100644
index 00000000..6104e09e
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sai_ex.c
@@ -0,0 +1,128 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_sai_ex.c
+ * @author MCD Application Team
+ * @brief SAI Extended HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionality of the SAI Peripheral Controller:
+ * + Modify PDM microphone delays.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+#ifdef HAL_SAI_MODULE_ENABLED
+
+/** @defgroup SAIEx SAIEx
+ * @brief SAI Extended HAL module driver
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SAIEx_Private_Defines SAIEx Extended Private Defines
+ * @{
+ */
+#define SAI_PDM_DELAY_MASK 0x77U
+#define SAI_PDM_DELAY_OFFSET 8U
+#define SAI_PDM_RIGHT_DELAY_OFFSET 4U
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SAIEx_Exported_Functions SAIEx Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup SAIEx_Exported_Functions_Group1 Peripheral Control functions
+ * @brief SAIEx control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended features functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Modify PDM microphone delays
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure PDM microphone delays.
+ * @param hsai SAI handle.
+ * @param pdmMicDelay Microphone delays configuration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t offset;
+
+ /* Check that SAI sub-block is SAI1 sub-block A */
+ if (hsai->Instance != SAI1_Block_A)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check microphone delay parameters */
+ assert_param(IS_SAI_PDM_MIC_PAIRS_NUMBER(pdmMicDelay->MicPair));
+ assert_param(IS_SAI_PDM_MIC_DELAY(pdmMicDelay->LeftDelay));
+ assert_param(IS_SAI_PDM_MIC_DELAY(pdmMicDelay->RightDelay));
+
+ /* Compute offset on PDMDLY register according mic pair number */
+ offset = SAI_PDM_DELAY_OFFSET * (pdmMicDelay->MicPair - 1U);
+
+ /* Check SAI state and offset */
+ if ((hsai->State != HAL_SAI_STATE_RESET) && (offset <= 24U))
+ {
+ /* Reset current delays for specified microphone */
+ SAI1->PDMDLY &= ~(SAI_PDM_DELAY_MASK << offset);
+
+ /* Apply new microphone delays */
+ SAI1->PDMDLY |= (((pdmMicDelay->RightDelay << SAI_PDM_RIGHT_DELAY_OFFSET) | pdmMicDelay->LeftDelay) << offset);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ }
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_SAI_MODULE_ENABLED */
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sd.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sd.c
new file mode 100644
index 00000000..9602c554
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sd.c
@@ -0,0 +1,3948 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_sd.c
+ * @author MCD Application Team
+ * @brief SD card HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Secure Digital (SD) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This driver implements a high level communication layer for read and write from/to
+ this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by
+ the user in HAL_SD_MspInit() function (MSP layer).
+ Basically, the MSP layer configuration should be the same as we provide in the
+ examples.
+ You can easily tailor this configuration according to hardware resources.
+
+ [..]
+ This driver is a generic layered driver for SDMMC memories which uses the HAL
+ SDMMC driver functions to interface with SD and uSD cards devices.
+ It is used as follows:
+
+ (#)Initialize the SDMMC low level resources by implementing the HAL_SD_MspInit() API:
+ (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE();
+ (##) SDMMC pins configuration for SD card
+ (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
+ (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()
+ and according to your pin assignment;
+ (##) NVIC configuration if you need to use interrupt process (HAL_SD_ReadBlocks_IT()
+ and HAL_SD_WriteBlocks_IT() APIs).
+ (+++) Configure the SDMMC interrupt priorities using function HAL_NVIC_SetPriority();
+ (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ()
+ (+++) SDMMC interrupts are managed using the macros __HAL_SD_ENABLE_IT()
+ and __HAL_SD_DISABLE_IT() inside the communication process.
+ (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_GET_IT()
+ and __HAL_SD_CLEAR_IT()
+ (##) No general propose DMA Configuration is needed, an Internal DMA for SDMMC Peripheral are used.
+
+ (#) At this stage, you can perform SD read/write/erase operations after SD card initialization
+
+
+ *** SD Card Initialization and configuration ***
+ ================================================
+ [..]
+ To initialize the SD Card, use the HAL_SD_Init() function. It Initializes
+ SDMMC Peripheral(STM32 side) and the SD Card, and put it into StandBy State (Ready for data transfer).
+ This function provide the following operations:
+
+ (#) Apply the SD Card initialization process at 400KHz and check the SD Card
+ type (Standard Capacity or High Capacity). You can change or adapt this
+ frequency by adjusting the "ClockDiv" field.
+ The SD Card frequency (SDMMC_CK) is computed as follows:
+
+ SDMMC_CK = SDMMCCLK / (2 * ClockDiv)
+
+ In initialization mode and according to the SD Card standard,
+ make sure that the SDMMC_CK frequency doesn't exceed 400KHz.
+
+ This phase of initialization is done through SDMMC_Init() and
+ SDMMC_PowerState_ON() SDMMC low level APIs.
+
+ (#) Initialize the SD card. The API used is HAL_SD_InitCard().
+ This phase allows the card initialization and identification
+ and check the SD Card type (Standard Capacity or High Capacity)
+ The initialization flow is compatible with SD standard.
+
+ This API (HAL_SD_InitCard()) could be used also to reinitialize the card in case
+ of plug-off plug-in.
+
+ (#) Configure the SD Card Data transfer frequency. You can change or adapt this
+ frequency by adjusting the "ClockDiv" field.
+ In transfer mode and according to the SD Card standard, make sure that the
+ SDMMC_CK frequency doesn't exceed 25MHz and 100MHz in High-speed mode switch.
+
+ (#) Select the corresponding SD Card according to the address read with the step 2.
+
+ (#) Configure the SD Card in wide bus mode: 4-bits data.
+
+ *** SD Card Read operation ***
+ ==============================
+ [..]
+ (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks().
+ This function support only 512-bytes block length (the block size should be
+ chosen as 512 bytes).
+ You can choose either one block read operation or multiple block read operation
+ by adjusting the "NumberOfBlocks" parameter.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_SD_GetCardState() function for SD card state.
+
+ (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().
+ This function support only 512-bytes block length (the block size should be
+ chosen as 512 bytes).
+ You can choose either one block read operation or multiple block read operation
+ by adjusting the "NumberOfBlocks" parameter.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_SD_GetCardState() function for SD card state.
+ You could also check the DMA transfer process through the SD Rx interrupt event.
+
+ (+) You can read from SD card in Interrupt mode by using function HAL_SD_ReadBlocks_IT().
+ This function support only 512-bytes block length (the block size should be
+ chosen as 512 bytes).
+ You can choose either one block read operation or multiple block read operation
+ by adjusting the "NumberOfBlocks" parameter.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_SD_GetCardState() function for SD card state.
+ You could also check the IT transfer process through the SD Rx interrupt event.
+
+ *** SD Card Write operation ***
+ ===============================
+ [..]
+ (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks().
+ This function support only 512-bytes block length (the block size should be
+ chosen as 512 bytes).
+ You can choose either one block read operation or multiple block read operation
+ by adjusting the "NumberOfBlocks" parameter.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_SD_GetCardState() function for SD card state.
+
+ (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().
+ This function support only 512-bytes block length (the block size should be
+ chosen as 512 bytes).
+ You can choose either one block read operation or multiple block read operation
+ by adjusting the "NumberOfBlocks" parameter.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_SD_GetCardState() function for SD card state.
+ You could also check the DMA transfer process through the SD Tx interrupt event.
+
+ (+) You can write to SD card in Interrupt mode by using function HAL_SD_WriteBlocks_IT().
+ This function support only 512-bytes block length (the block size should be
+ chosen as 512 bytes).
+ You can choose either one block read operation or multiple block read operation
+ by adjusting the "NumberOfBlocks" parameter.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_SD_GetCardState() function for SD card state.
+ You could also check the IT transfer process through the SD Tx interrupt event.
+
+ *** SD card status ***
+ ======================
+ [..]
+ (+) The SD Status contains status bits that are related to the SD Memory
+ Card proprietary features. To get SD card status use the HAL_SD_GetCardStatus().
+
+ *** SD card information ***
+ ===========================
+ [..]
+ (+) To get SD card information, you can use the function HAL_SD_GetCardInfo().
+ It returns useful information about the SD card such as block size, card type,
+ block number ...
+
+ *** SD card CSD register ***
+ ============================
+ (+) The HAL_SD_GetCardCSD() API allows to get the parameters of the CSD register.
+ Some of the CSD parameters are useful for card initialization and identification.
+
+ *** SD card CID register ***
+ ============================
+ (+) The HAL_SD_GetCardCID() API allows to get the parameters of the CID register.
+ Some of the CSD parameters are useful for card initialization and identification.
+
+ *** SD HAL driver macros list ***
+ ==================================
+ [..]
+ Below the list of most used macros in SD HAL driver.
+
+ (+) __HAL_SD_ENABLE_IT: Enable the SD device interrupt
+ (+) __HAL_SD_DISABLE_IT: Disable the SD device interrupt
+ (+) __HAL_SD_GET_FLAG:Check whether the specified SD flag is set or not
+ (+) __HAL_SD_CLEAR_FLAG: Clear the SD's pending flags
+
+ (@) You can refer to the SD HAL driver header file for more useful macros
+
+ *** Callback registration ***
+ =============================================
+ [..]
+ The compilation define USE_HAL_SD_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ Use Functions @ref HAL_SD_RegisterCallback() to register a user callback,
+ it allows to register following callbacks:
+ (+) TxCpltCallback : callback when a transmission transfer is completed.
+ (+) RxCpltCallback : callback when a reception transfer is completed.
+ (+) ErrorCallback : callback when error occurs.
+ (+) AbortCpltCallback : callback when abort is completed.
+ (+) Read_DMADblBuf0CpltCallback : callback when the DMA reception of first buffer is completed.
+ (+) Read_DMADblBuf1CpltCallback : callback when the DMA reception of second buffer is completed.
+ (+) Write_DMADblBuf0CpltCallback : callback when the DMA transmission of first buffer is completed.
+ (+) Write_DMADblBuf1CpltCallback : callback when the DMA transmission of second buffer is completed.
+ (+) MspInitCallback : SD MspInit.
+ (+) MspDeInitCallback : SD MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+ For specific callbacks TransceiverCallback use dedicated register callbacks:
+ respectively @ref HAL_SD_RegisterTransceiverCallback().
+
+ Use function @ref HAL_SD_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function. It allows to reset following callbacks:
+ (+) TxCpltCallback : callback when a transmission transfer is completed.
+ (+) RxCpltCallback : callback when a reception transfer is completed.
+ (+) ErrorCallback : callback when error occurs.
+ (+) AbortCpltCallback : callback when abort is completed.
+ (+) Read_DMALnkLstBufCpltCallback : callback when the DMA reception of linked list node buffer is completed.
+ (+) Write_DMALnkLstBufCpltCallback : callback when the DMA transmission of linked list node buffer is completed.
+ (+) MspInitCallback : SD MspInit.
+ (+) MspDeInitCallback : SD MspDeInit.
+ This function) takes as parameters the HAL peripheral handle and the Callback ID.
+ For specific callbacks TransceiverCallback use dedicated unregister callbacks:
+ respectively @ref HAL_SD_UnRegisterTransceiverCallback().
+
+ By default, after the @ref HAL_SD_Init and if the state is HAL_SD_STATE_RESET
+ all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_SD_Init
+ and @ref HAL_SD_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_SD_Init and @ref HAL_SD_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_SD_RegisterCallback before calling @ref HAL_SD_DeInit
+ or @ref HAL_SD_Init function.
+
+ When The compilation define USE_HAL_SD_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
+ @endverbatim
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SD
+ * @{
+ */
+
+#ifdef HAL_SD_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup SD_Private_Defines
+ * @{
+ */
+/* Frequencies used in the driver for clock divider calculation */
+#define SD_INIT_FREQ 400000U /* Initialization phase : 400 kHz max */
+#define SD_NORMAL_SPEED_FREQ 25000000U /* Normal speed phase : 25 MHz max */
+#define SD_HIGH_SPEED_FREQ 50000000U /* High speed phase : 50 MHz max */
+/* Private macro -------------------------------------------------------------*/
+#if defined (DLYB_SDMMC1) && defined (DLYB_SDMMC2)
+#define SD_GET_DLYB_INSTANCE(SDMMC_INSTANCE) (((SDMMC_INSTANCE) == SDMMC1)? \
+ DLYB_SDMMC1 : DLYB_SDMMC2 )
+#elif defined (DLYB_SDMMC1)
+#define SD_GET_DLYB_INSTANCE(SDMMC_INSTANCE) ( DLYB_SDMMC1 )
+#endif /* (DLYB_SDMMC1) && defined (DLYB_SDMMC2) */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup SD_Private_Functions SD Private Functions
+ * @{
+ */
+static uint32_t SD_InitCard(SD_HandleTypeDef *hsd);
+static uint32_t SD_PowerON(SD_HandleTypeDef *hsd);
+static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
+static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus);
+static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd);
+static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd);
+static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR);
+static void SD_PowerOFF(SD_HandleTypeDef *hsd);
+static void SD_Write_IT(SD_HandleTypeDef *hsd);
+static void SD_Read_IT(SD_HandleTypeDef *hsd);
+static uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd);
+#if (USE_SD_TRANSCEIVER != 0U)
+static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd);
+static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd);
+#endif /* USE_SD_TRANSCEIVER */
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SD_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup SD_Exported_Functions_Group1
+ * @brief Initialization and de-initialization functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to initialize/de-initialize the SD
+ card device to be ready for use.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the SD according to the specified parameters in the
+ SD_HandleTypeDef and create the associated handle.
+ * @param hsd: Pointer to the SD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)
+{
+ HAL_SD_CardStatusTypeDef CardStatus;
+ uint32_t speedgrade;
+ uint32_t unitsize;
+ uint32_t tickstart;
+
+ /* Check the SD handle allocation */
+ if (hsd == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SDMMC_ALL_INSTANCE(hsd->Instance));
+ assert_param(IS_SDMMC_CLOCK_EDGE(hsd->Init.ClockEdge));
+ assert_param(IS_SDMMC_CLOCK_POWER_SAVE(hsd->Init.ClockPowerSave));
+ assert_param(IS_SDMMC_BUS_WIDE(hsd->Init.BusWide));
+ assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hsd->Init.HardwareFlowControl));
+ assert_param(IS_SDMMC_CLKDIV(hsd->Init.ClockDiv));
+
+ if (hsd->State == HAL_SD_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hsd->Lock = HAL_UNLOCKED;
+
+#if (USE_SD_TRANSCEIVER != 0U)
+ /* Force SDMMC_TRANSCEIVER_PRESENT for Legacy usage */
+ if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_UNKNOWN)
+ {
+ hsd->Init.TranceiverPresent = SDMMC_TRANSCEIVER_PRESENT;
+ }
+#endif /*USE_SD_TRANSCEIVER */
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+ /* Reset Callback pointers in HAL_SD_STATE_RESET only */
+ hsd->TxCpltCallback = HAL_SD_TxCpltCallback;
+ hsd->RxCpltCallback = HAL_SD_RxCpltCallback;
+ hsd->ErrorCallback = HAL_SD_ErrorCallback;
+ hsd->AbortCpltCallback = HAL_SD_AbortCallback;
+ hsd->Read_DMALnkLstBufCpltCallback = HAL_SDEx_Read_DMALnkLstBufCpltCallback;
+ hsd->Write_DMALnkLstBufCpltCallback = HAL_SDEx_Write_DMALnkLstBufCpltCallback;
+#if (USE_SD_TRANSCEIVER != 0U)
+ if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT)
+ {
+ hsd->DriveTransceiver_1_8V_Callback = HAL_SD_DriveTransceiver_1_8V_Callback;
+ }
+#endif /* USE_SD_TRANSCEIVER */
+
+ if (hsd->MspInitCallback == NULL)
+ {
+ hsd->MspInitCallback = HAL_SD_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hsd->MspInitCallback(hsd);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ HAL_SD_MspInit(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+ }
+
+ hsd->State = HAL_SD_STATE_BUSY;
+
+ /* Initialize the Card parameters */
+ if (HAL_SD_InitCard(hsd) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ if (HAL_SD_GetCardStatus(hsd, &CardStatus) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ /* Get Initial Card Speed from Card Status*/
+ speedgrade = CardStatus.UhsSpeedGrade;
+ unitsize = CardStatus.UhsAllocationUnitSize;
+ if ((hsd->SdCard.CardType == CARD_SDHC_SDXC) && ((speedgrade != 0U) || (unitsize != 0U)))
+ {
+ hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED;
+ }
+ else
+ {
+ if (hsd->SdCard.CardType == CARD_SDHC_SDXC)
+ {
+ hsd->SdCard.CardSpeed = CARD_HIGH_SPEED;
+ }
+ else
+ {
+ hsd->SdCard.CardSpeed = CARD_NORMAL_SPEED;
+ }
+
+ }
+ /* Configure the bus wide */
+ if (HAL_SD_ConfigWideBusOperation(hsd, hsd->Init.BusWide) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Verify that SD card is ready to use after Initialization */
+ tickstart = HAL_GetTick();
+ while ((HAL_SD_GetCardState(hsd) != HAL_SD_CARD_TRANSFER))
+ {
+ if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+ {
+ hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Initialize the error code */
+ hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+ /* Initialize the SD operation */
+ hsd->Context = SD_CONTEXT_NONE;
+
+ /* Initialize the SD state */
+ hsd->State = HAL_SD_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the SD Card.
+ * @param hsd: Pointer to SD handle
+ * @note This function initializes the SD card. It could be used when a card
+ re-initialization is needed.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
+{
+ uint32_t errorstate;
+ SD_InitTypeDef Init;
+ uint32_t sdmmc_clk;
+
+ /* Default SDMMC peripheral configuration for SD card initialization */
+ Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING;
+ Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE;
+ Init.BusWide = SDMMC_BUS_WIDE_1B;
+ Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
+
+ /* Init Clock should be less or equal to 400Khz*/
+ sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC);
+ if (sdmmc_clk == 0U)
+ {
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->ErrorCode = SDMMC_ERROR_INVALID_PARAMETER;
+ return HAL_ERROR;
+ }
+ Init.ClockDiv = sdmmc_clk / (2U * SD_INIT_FREQ);
+
+#if (USE_SD_TRANSCEIVER != 0U)
+ Init.TranceiverPresent = hsd->Init.TranceiverPresent;
+
+ if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT)
+ {
+ /* Set Transceiver polarity */
+ hsd->Instance->POWER |= SDMMC_POWER_DIRPOL;
+ }
+#elif defined (USE_SD_DIRPOL)
+ /* Set Transceiver polarity */
+ hsd->Instance->POWER |= SDMMC_POWER_DIRPOL;
+#endif /* USE_SD_TRANSCEIVER */
+
+ /* Initialize SDMMC peripheral interface with default configuration */
+ (void)SDMMC_Init(hsd->Instance, Init);
+
+ /* Set Power State to ON */
+ (void)SDMMC_PowerState_ON(hsd->Instance);
+
+ /* wait 74 Cycles: required power up waiting time before starting
+ the SD initialization sequence */
+ sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv);
+ HAL_Delay(1U + (74U * 1000U / (sdmmc_clk)));
+
+ /* Identify card operating voltage */
+ errorstate = SD_PowerON(hsd);
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->ErrorCode |= errorstate;
+ return HAL_ERROR;
+ }
+
+ /* Card initialization */
+ errorstate = SD_InitCard(hsd);
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->ErrorCode |= errorstate;
+ return HAL_ERROR;
+ }
+
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief De-Initializes the SD card.
+ * @param hsd: Pointer to SD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)
+{
+ /* Check the SD handle allocation */
+ if (hsd == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SDMMC_ALL_INSTANCE(hsd->Instance));
+
+ hsd->State = HAL_SD_STATE_BUSY;
+
+#if (USE_SD_TRANSCEIVER != 0U)
+ /* Deactivate the 1.8V Mode */
+ if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT)
+ {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+ if (hsd->DriveTransceiver_1_8V_Callback == NULL)
+ {
+ hsd->DriveTransceiver_1_8V_Callback = HAL_SD_DriveTransceiver_1_8V_Callback;
+ }
+ hsd->DriveTransceiver_1_8V_Callback(RESET);
+#else
+ HAL_SD_DriveTransceiver_1_8V_Callback(RESET);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+ }
+#endif /* USE_SD_TRANSCEIVER */
+
+ /* Set SD power state to off */
+ SD_PowerOFF(hsd);
+
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+ if (hsd->MspDeInitCallback == NULL)
+ {
+ hsd->MspDeInitCallback = HAL_SD_MspDeInit;
+ }
+
+ /* DeInit the low level hardware */
+ hsd->MspDeInitCallback(hsd);
+#else
+ /* De-Initialize the MSP layer */
+ HAL_SD_MspDeInit(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+
+ hsd->ErrorCode = HAL_SD_ERROR_NONE;
+ hsd->State = HAL_SD_STATE_RESET;
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Initializes the SD MSP.
+ * @param hsd: Pointer to SD handle
+ * @retval None
+ */
+__weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SD_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief De-Initialize SD MSP.
+ * @param hsd: Pointer to SD handle
+ * @retval None
+ */
+__weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SD_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup SD_Exported_Functions_Group2
+ * @brief Data transfer functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the data
+ transfer from/to SD card.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Reads block(s) from a specified address in a card. The Data transfer
+ * is managed by polling mode.
+ * @note This API should be followed by a check on the card state through
+ * HAL_SD_GetCardState().
+ * @param hsd: Pointer to SD handle
+ * @param pData: pointer to the buffer that will contain the received data
+ * @param BlockAdd: Block Address from where data is to be read
+ * @param NumberOfBlocks: Number of SD blocks to read
+ * @param Timeout: Specify timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks,
+ uint32_t Timeout)
+{
+ SDMMC_DataInitTypeDef config;
+ uint32_t errorstate;
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t count;
+ uint32_t data;
+ uint32_t dataremaining;
+ uint32_t add = BlockAdd;
+ uint8_t *tempbuff = pData;
+
+ if (NULL == pData)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if (hsd->State == HAL_SD_STATE_READY)
+ {
+ hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+ if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ hsd->State = HAL_SD_STATE_BUSY;
+
+ /* Initialize data control register */
+ hsd->Instance->DCTRL = 0U;
+
+ if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ {
+ add *= 512U;
+ }
+
+ /* Configure the SD DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = NumberOfBlocks * BLOCKSIZE;
+ config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
+ config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDMMC_DPSM_DISABLE;
+ (void)SDMMC_ConfigData(hsd->Instance, &config);
+ __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
+
+ /* Read block(s) in polling mode */
+ if (NumberOfBlocks > 1U)
+ {
+ hsd->Context = SD_CONTEXT_READ_MULTIPLE_BLOCK;
+
+ /* Read Multi Block command */
+ errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
+ }
+ else
+ {
+ hsd->Context = SD_CONTEXT_READ_SINGLE_BLOCK;
+
+ /* Read Single Block command */
+ errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
+ }
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
+ return HAL_ERROR;
+ }
+
+ /* Poll on SDMMC flags */
+ dataremaining = config.DataLength;
+ while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+ {
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U))
+ {
+ /* Read data from SDMMC Rx FIFO */
+ for (count = 0U; count < 8U; count++)
+ {
+ data = SDMMC_ReadFIFO(hsd->Instance);
+ *tempbuff = (uint8_t)(data & 0xFFU);
+ tempbuff++;
+ *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
+ tempbuff++;
+ *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
+ tempbuff++;
+ *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
+ tempbuff++;
+ }
+ dataremaining -= 32U;
+ }
+
+ if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
+ return HAL_TIMEOUT;
+ }
+ }
+ __SDMMC_CMDTRANS_DISABLE(hsd->Instance);
+
+ /* Send stop transmission command in case of multiblock read */
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
+ {
+ if (hsd->SdCard.CardType != CARD_SECURED)
+ {
+ /* Send stop transmission command */
+ errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Get error state */
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
+ return HAL_ERROR;
+ }
+ else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
+ return HAL_ERROR;
+ }
+ else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+ hsd->State = HAL_SD_STATE_READY;
+
+ return HAL_OK;
+ }
+ else
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_BUSY;
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Allows to write block(s) to a specified address in a card. The Data
+ * transfer is managed by polling mode.
+ * @note This API should be followed by a check on the card state through
+ * HAL_SD_GetCardState().
+ * @param hsd: Pointer to SD handle
+ * @param pData: pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd: Block Address where data will be written
+ * @param NumberOfBlocks: Number of SD blocks to write
+ * @param Timeout: Specify timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks,
+ uint32_t Timeout)
+{
+ SDMMC_DataInitTypeDef config;
+ uint32_t errorstate;
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t count;
+ uint32_t data;
+ uint32_t dataremaining;
+ uint32_t add = BlockAdd;
+ uint8_t *tempbuff = pData;
+
+ if (NULL == pData)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if (hsd->State == HAL_SD_STATE_READY)
+ {
+ hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+ if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ hsd->State = HAL_SD_STATE_BUSY;
+
+ /* Initialize data control register */
+ hsd->Instance->DCTRL = 0U;
+
+ if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ {
+ add *= 512U;
+ }
+
+ /* Configure the SD DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = NumberOfBlocks * BLOCKSIZE;
+ config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;
+ config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDMMC_DPSM_DISABLE;
+ (void)SDMMC_ConfigData(hsd->Instance, &config);
+ __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
+
+ /* Write Blocks in Polling mode */
+ if (NumberOfBlocks > 1U)
+ {
+ hsd->Context = SD_CONTEXT_WRITE_MULTIPLE_BLOCK;
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
+ }
+ else
+ {
+ hsd->Context = SD_CONTEXT_WRITE_SINGLE_BLOCK;
+
+ /* Write Single Block command */
+ errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
+ }
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
+ return HAL_ERROR;
+ }
+
+ /* Write block(s) in polling mode */
+ dataremaining = config.DataLength;
+ while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT |
+ SDMMC_FLAG_DATAEND))
+ {
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U))
+ {
+ /* Write data to SDMMC Tx FIFO */
+ for (count = 0U; count < 8U; count++)
+ {
+ data = (uint32_t)(*tempbuff);
+ tempbuff++;
+ data |= ((uint32_t)(*tempbuff) << 8U);
+ tempbuff++;
+ data |= ((uint32_t)(*tempbuff) << 16U);
+ tempbuff++;
+ data |= ((uint32_t)(*tempbuff) << 24U);
+ tempbuff++;
+ (void)SDMMC_WriteFIFO(hsd->Instance, &data);
+ }
+ dataremaining -= 32U;
+ }
+
+ if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
+ return HAL_TIMEOUT;
+ }
+ }
+ __SDMMC_CMDTRANS_DISABLE(hsd->Instance);
+
+ /* Send stop transmission command in case of multiblock write */
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
+ {
+ if (hsd->SdCard.CardType != CARD_SECURED)
+ {
+ /* Send stop transmission command */
+ errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Get error state */
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
+ return HAL_ERROR;
+ }
+ else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
+ return HAL_ERROR;
+ }
+ else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR))
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+ hsd->State = HAL_SD_STATE_READY;
+
+ return HAL_OK;
+ }
+ else
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_BUSY;
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Reads block(s) from a specified address in a card. The Data transfer
+ * is managed in interrupt mode.
+ * @note This API should be followed by a check on the card state through
+ * HAL_SD_GetCardState().
+ * @note You could also check the IT transfer process through the SD Rx
+ * interrupt event.
+ * @param hsd: Pointer to SD handle
+ * @param pData: Pointer to the buffer that will contain the received data
+ * @param BlockAdd: Block Address from where data is to be read
+ * @param NumberOfBlocks: Number of blocks to read.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks)
+{
+ SDMMC_DataInitTypeDef config;
+ uint32_t errorstate;
+ uint32_t add = BlockAdd;
+
+ if (NULL == pData)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if (hsd->State == HAL_SD_STATE_READY)
+ {
+ hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+ if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ hsd->State = HAL_SD_STATE_BUSY;
+
+ /* Initialize data control register */
+ hsd->Instance->DCTRL = 0U;
+
+ hsd->pRxBuffPtr = pData;
+ hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks;
+
+ if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ {
+ add *= 512U;
+ }
+
+ /* Configure the SD DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = BLOCKSIZE * NumberOfBlocks;
+ config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
+ config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDMMC_DPSM_DISABLE;
+ (void)SDMMC_ConfigData(hsd->Instance, &config);
+ __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
+
+ /* Read Blocks in IT mode */
+ if (NumberOfBlocks > 1U)
+ {
+ hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_IT);
+
+ /* Read Multi Block command */
+ errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
+ }
+ else
+ {
+ hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_IT);
+
+ /* Read Single Block command */
+ errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
+ }
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
+ return HAL_ERROR;
+ }
+
+ __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND |
+ SDMMC_FLAG_RXFIFOHF));
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Writes block(s) to a specified address in a card. The Data transfer
+ * is managed in interrupt mode.
+ * @note This API should be followed by a check on the card state through
+ * HAL_SD_GetCardState().
+ * @note You could also check the IT transfer process through the SD Tx
+ * interrupt event.
+ * @param hsd: Pointer to SD handle
+ * @param pData: Pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd: Block Address where data will be written
+ * @param NumberOfBlocks: Number of blocks to write
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks)
+{
+ SDMMC_DataInitTypeDef config;
+ uint32_t errorstate;
+ uint32_t add = BlockAdd;
+
+ if (NULL == pData)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if (hsd->State == HAL_SD_STATE_READY)
+ {
+ hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+ if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ hsd->State = HAL_SD_STATE_BUSY;
+
+ /* Initialize data control register */
+ hsd->Instance->DCTRL = 0U;
+
+ hsd->pTxBuffPtr = pData;
+ hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks;
+
+ if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ {
+ add *= 512U;
+ }
+
+ /* Configure the SD DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = BLOCKSIZE * NumberOfBlocks;
+ config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;
+ config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDMMC_DPSM_DISABLE;
+ (void)SDMMC_ConfigData(hsd->Instance, &config);
+
+ __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
+
+ /* Write Blocks in Polling mode */
+ if (NumberOfBlocks > 1U)
+ {
+ hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_IT);
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
+ }
+ else
+ {
+ hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_IT);
+
+ /* Write Single Block command */
+ errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
+ }
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
+ return HAL_ERROR;
+ }
+
+ /* Enable transfer interrupts */
+ __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND |
+ SDMMC_FLAG_TXFIFOHE));
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Reads block(s) from a specified address in a card. The Data transfer
+ * is managed by DMA mode.
+ * @note This API should be followed by a check on the card state through
+ * HAL_SD_GetCardState().
+ * @note You could also check the DMA transfer process through the SD Rx
+ * interrupt event.
+ * @param hsd: Pointer SD handle
+ * @param pData: Pointer to the buffer that will contain the received data
+ * @param BlockAdd: Block Address from where data is to be read
+ * @param NumberOfBlocks: Number of blocks to read.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks)
+{
+ SDMMC_DataInitTypeDef config;
+ uint32_t errorstate;
+ uint32_t add = BlockAdd;
+
+ if (NULL == pData)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if (hsd->State == HAL_SD_STATE_READY)
+ {
+ hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+ if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ hsd->State = HAL_SD_STATE_BUSY;
+
+ /* Initialize data control register */
+ hsd->Instance->DCTRL = 0U;
+
+ hsd->pRxBuffPtr = pData;
+ hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks;
+
+ if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ {
+ add *= 512U;
+ }
+
+ /* Configure the SD DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = BLOCKSIZE * NumberOfBlocks;
+ config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
+ config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDMMC_DPSM_DISABLE;
+ (void)SDMMC_ConfigData(hsd->Instance, &config);
+
+ __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
+ hsd->Instance->IDMABASER = (uint32_t) pData ;
+ hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
+
+ /* Read Blocks in DMA mode */
+ if (NumberOfBlocks > 1U)
+ {
+ hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
+
+ /* Read Multi Block command */
+ errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
+ }
+ else
+ {
+ hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_DMA);
+
+ /* Read Single Block command */
+ errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
+ }
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
+ return HAL_ERROR;
+ }
+
+ /* Enable transfer interrupts */
+ __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND));
+
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Writes block(s) to a specified address in a card. The Data transfer
+ * is managed by DMA mode.
+ * @note This API should be followed by a check on the card state through
+ * HAL_SD_GetCardState().
+ * @note You could also check the DMA transfer process through the SD Tx
+ * interrupt event.
+ * @param hsd: Pointer to SD handle
+ * @param pData: Pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd: Block Address where data will be written
+ * @param NumberOfBlocks: Number of blocks to write
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks)
+{
+ SDMMC_DataInitTypeDef config;
+ uint32_t errorstate;
+ uint32_t add = BlockAdd;
+
+ if (NULL == pData)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if (hsd->State == HAL_SD_STATE_READY)
+ {
+ hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+ if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ hsd->State = HAL_SD_STATE_BUSY;
+
+ /* Initialize data control register */
+ hsd->Instance->DCTRL = 0U;
+
+ hsd->pTxBuffPtr = pData;
+ hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks;
+
+ if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ {
+ add *= 512U;
+ }
+
+ /* Configure the SD DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = BLOCKSIZE * NumberOfBlocks;
+ config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;
+ config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDMMC_DPSM_DISABLE;
+ (void)SDMMC_ConfigData(hsd->Instance, &config);
+
+
+ __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
+
+ hsd->Instance->IDMABASER = (uint32_t) pData ;
+ hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
+
+ /* Write Blocks in Polling mode */
+ if (NumberOfBlocks > 1U)
+ {
+ hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
+ }
+ else
+ {
+ hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_DMA);
+
+ /* Write Single Block command */
+ errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
+ }
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
+ return HAL_ERROR;
+ }
+
+ /* Enable transfer interrupts */
+ __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND));
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Erases the specified memory area of the given SD card.
+ * @note This API should be followed by a check on the card state through
+ * HAL_SD_GetCardState().
+ * @param hsd: Pointer to SD handle
+ * @param BlockStartAdd: Start Block address
+ * @param BlockEndAdd: End Block address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
+{
+ uint32_t errorstate;
+ uint32_t start_add = BlockStartAdd;
+ uint32_t end_add = BlockEndAdd;
+
+ if (hsd->State == HAL_SD_STATE_READY)
+ {
+ hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+ if (end_add < start_add)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if (end_add > (hsd->SdCard.LogBlockNbr))
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ hsd->State = HAL_SD_STATE_BUSY;
+
+ /* Check if the card command class supports erase command */
+ if (((hsd->SdCard.Class) & SDMMC_CCCC_ERASE) == 0U)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode |= HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode |= HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Get start and end block for high capacity cards */
+ if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ {
+ start_add *= 512U;
+ end_add *= 512U;
+ }
+
+ /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */
+ if (hsd->SdCard.CardType != CARD_SECURED)
+ {
+ /* Send CMD32 SD_ERASE_GRP_START with argument as addr */
+ errorstate = SDMMC_CmdSDEraseStartAdd(hsd->Instance, start_add);
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Send CMD33 SD_ERASE_GRP_END with argument as addr */
+ errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, end_add);
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+ }
+
+ /* Send CMD38 ERASE */
+ errorstate = SDMMC_CmdErase(hsd->Instance, 0UL);
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ hsd->State = HAL_SD_STATE_READY;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief This function handles SD card interrupt request.
+ * @param hsd: Pointer to SD handle
+ * @retval None
+ */
+void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
+{
+ uint32_t errorstate;
+ uint32_t context = hsd->Context;
+
+ /* Check for SDMMC interrupt flags */
+ if ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & SD_CONTEXT_IT) != 0U))
+ {
+ SD_Read_IT(hsd);
+ }
+
+ else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) != RESET)
+ {
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DATAEND);
+
+ __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+ SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE | \
+ SDMMC_IT_RXFIFOHF);
+
+ __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_IDMABTC);
+ __SDMMC_CMDTRANS_DISABLE(hsd->Instance);
+
+ if ((context & SD_CONTEXT_IT) != 0U)
+ {
+ if (((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+ {
+ errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ hsd->ErrorCode |= errorstate;
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+ hsd->ErrorCallback(hsd);
+#else
+ HAL_SD_ErrorCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
+ if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
+ {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+ hsd->RxCpltCallback(hsd);
+#else
+ HAL_SD_RxCpltCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+ }
+ else
+ {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+ hsd->TxCpltCallback(hsd);
+#else
+ HAL_SD_TxCpltCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+ }
+ }
+ else if ((context & SD_CONTEXT_DMA) != 0U)
+ {
+ hsd->Instance->DLEN = 0;
+ hsd->Instance->DCTRL = 0;
+ hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
+
+ /* Stop Transfer for Write Multi blocks or Read Multi blocks */
+ if (((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+ {
+ errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ hsd->ErrorCode |= errorstate;
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+ hsd->ErrorCallback(hsd);
+#else
+ HAL_SD_ErrorCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+ }
+ }
+
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
+ if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+ {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+ hsd->TxCpltCallback(hsd);
+#else
+ HAL_SD_TxCpltCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+ }
+ if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
+ {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+ hsd->RxCpltCallback(hsd);
+#else
+ HAL_SD_RxCpltCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+
+ else if ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & SD_CONTEXT_IT) != 0U))
+ {
+ SD_Write_IT(hsd);
+ }
+
+ else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR |
+ SDMMC_FLAG_TXUNDERR) != RESET)
+ {
+ /* Set Error code */
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL) != RESET)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
+ }
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DTIMEOUT) != RESET)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
+ }
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_RXOVERR) != RESET)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
+ }
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_TXUNDERR) != RESET)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
+ }
+
+ /* Clear All flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+ /* Disable all interrupts */
+ __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+ SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR);
+
+ __SDMMC_CMDTRANS_DISABLE(hsd->Instance);
+ hsd->Instance->DCTRL |= SDMMC_DCTRL_FIFORST;
+ hsd->Instance->CMD |= SDMMC_CMD_CMDSTOP;
+ hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
+ hsd->Instance->CMD &= ~(SDMMC_CMD_CMDSTOP);
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DABORT);
+
+ if ((context & SD_CONTEXT_IT) != 0U)
+ {
+ /* Set the SD state to ready to be able to start again the process */
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+ hsd->ErrorCallback(hsd);
+#else
+ HAL_SD_ErrorCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+ }
+ else if ((context & SD_CONTEXT_DMA) != 0U)
+ {
+ if (hsd->ErrorCode != HAL_SD_ERROR_NONE)
+ {
+ /* Disable Internal DMA */
+ __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_IDMABTC);
+ hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
+
+ /* Set the SD state to ready to be able to start again the process */
+ hsd->State = HAL_SD_STATE_READY;
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+ hsd->ErrorCallback(hsd);
+#else
+ HAL_SD_ErrorCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+
+ else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_IDMABTC) != RESET)
+ {
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_IDMABTC);
+
+ if ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
+ {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+ hsd->Write_DMALnkLstBufCpltCallback(hsd);
+#else
+ HAL_SDEx_Write_DMALnkLstBufCpltCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+ }
+ else /* SD_CONTEXT_READ_MULTIPLE_BLOCK */
+ {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+ hsd->Read_DMALnkLstBufCpltCallback(hsd);
+#else
+ HAL_SDEx_Read_DMALnkLstBufCpltCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+}
+
+/**
+ * @brief return the SD state
+ * @param hsd: Pointer to sd handle
+ * @retval HAL state
+ */
+HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd)
+{
+ return hsd->State;
+}
+
+/**
+ * @brief Return the SD error code
+ * @param hsd : Pointer to a SD_HandleTypeDef structure that contains
+ * the configuration information.
+ * @retval SD Error Code
+ */
+uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd)
+{
+ return hsd->ErrorCode;
+}
+
+/**
+ * @brief Tx Transfer completed callbacks
+ * @param hsd: Pointer to SD handle
+ * @retval None
+ */
+__weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SD_TxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callbacks
+ * @param hsd: Pointer SD handle
+ * @retval None
+ */
+__weak void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SD_RxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief SD error callbacks
+ * @param hsd: Pointer SD handle
+ * @retval None
+ */
+__weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SD_ErrorCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief SD Abort callbacks
+ * @param hsd: Pointer SD handle
+ * @retval None
+ */
+__weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SD_AbortCallback can be implemented in the user file
+ */
+}
+
+#if (USE_SD_TRANSCEIVER != 0U)
+/**
+ * @brief Enable/Disable the SD Transceiver 1.8V Mode Callback.
+ * @param status: Voltage Switch State
+ * @retval None
+ */
+__weak void HAL_SD_DriveTransceiver_1_8V_Callback(FlagStatus status)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(status);
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SD_EnableTransceiver could be implemented in the user file
+ */
+}
+#endif /* USE_SD_TRANSCEIVER */
+
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+/**
+ * @brief Register a User SD Callback
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hsd : SD handle
+ * @param CallbackID : ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SD_TX_CPLT_CB_ID SD Tx Complete Callback ID
+ * @arg @ref HAL_SD_RX_CPLT_CB_ID SD Rx Complete Callback ID
+ * @arg @ref HAL_SD_ERROR_CB_ID SD Error Callback ID
+ * @arg @ref HAL_SD_ABORT_CB_ID SD Abort Callback ID
+ * @arg @ref HAL_SD_READ_DMA_LNKLST_BUF_CPLT_CB_ID SD DMA Rx Linked List Node buffer Callback ID
+ * @arg @ref HAL_SD_WRITE_DMA_LNKLST_BUF_CPLT_CB_ID SD DMA Tx Linked List Node buffer Callback ID
+ * @arg @ref HAL_SD_MSP_INIT_CB_ID SD MspInit Callback ID
+ * @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID
+ * @param pCallback : pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID,
+ pSD_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hsd);
+
+ if (hsd->State == HAL_SD_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SD_TX_CPLT_CB_ID :
+ hsd->TxCpltCallback = pCallback;
+ break;
+ case HAL_SD_RX_CPLT_CB_ID :
+ hsd->RxCpltCallback = pCallback;
+ break;
+ case HAL_SD_ERROR_CB_ID :
+ hsd->ErrorCallback = pCallback;
+ break;
+ case HAL_SD_ABORT_CB_ID :
+ hsd->AbortCpltCallback = pCallback;
+ break;
+ case HAL_SD_READ_DMA_LNKLST_BUF_CPLT_CB_ID :
+ hsd->Read_DMALnkLstBufCpltCallback = pCallback;
+ break;
+ case HAL_SD_WRITE_DMA_LNKLST_BUF_CPLT_CB_ID :
+ hsd->Write_DMALnkLstBufCpltCallback = pCallback;
+ break;
+ case HAL_SD_MSP_INIT_CB_ID :
+ hsd->MspInitCallback = pCallback;
+ break;
+ case HAL_SD_MSP_DEINIT_CB_ID :
+ hsd->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* Update the error code */
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hsd->State == HAL_SD_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SD_MSP_INIT_CB_ID :
+ hsd->MspInitCallback = pCallback;
+ break;
+ case HAL_SD_MSP_DEINIT_CB_ID :
+ hsd->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* Update the error code */
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsd);
+ return status;
+}
+
+/**
+ * @brief Unregister a User SD Callback
+ * SD Callback is redirected to the weak (surcharged) predefined callback
+ * @param hsd : SD handle
+ * @param CallbackID : ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SD_TX_CPLT_CB_ID SD Tx Complete Callback ID
+ * @arg @ref HAL_SD_RX_CPLT_CB_ID SD Rx Complete Callback ID
+ * @arg @ref HAL_SD_ERROR_CB_ID SD Error Callback ID
+ * @arg @ref HAL_SD_ABORT_CB_ID SD Abort Callback ID
+ * @arg @ref HAL_SD_READ_DMA_LNKLST_BUF_CPLT_CB_ID SD DMA Rx Linked List Node buffer Callback ID
+ * @arg @ref HAL_SD_WRITE_DMA_LNKLST_BUF_CPLT_CB_ID SD DMA Tx Linked List Node buffer Callback ID
+ * @arg @ref HAL_SD_MSP_INIT_CB_ID SD MspInit Callback ID
+ * @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hsd);
+
+ if (hsd->State == HAL_SD_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SD_TX_CPLT_CB_ID :
+ hsd->TxCpltCallback = HAL_SD_TxCpltCallback;
+ break;
+ case HAL_SD_RX_CPLT_CB_ID :
+ hsd->RxCpltCallback = HAL_SD_RxCpltCallback;
+ break;
+ case HAL_SD_ERROR_CB_ID :
+ hsd->ErrorCallback = HAL_SD_ErrorCallback;
+ break;
+ case HAL_SD_ABORT_CB_ID :
+ hsd->AbortCpltCallback = HAL_SD_AbortCallback;
+ break;
+ case HAL_SD_READ_DMA_LNKLST_BUF_CPLT_CB_ID :
+ hsd->Read_DMALnkLstBufCpltCallback = HAL_SDEx_Read_DMALnkLstBufCpltCallback;
+ break;
+ case HAL_SD_WRITE_DMA_LNKLST_BUF_CPLT_CB_ID :
+ hsd->Write_DMALnkLstBufCpltCallback = HAL_SDEx_Write_DMALnkLstBufCpltCallback;
+ break;
+ case HAL_SD_MSP_INIT_CB_ID :
+ hsd->MspInitCallback = HAL_SD_MspInit;
+ break;
+ case HAL_SD_MSP_DEINIT_CB_ID :
+ hsd->MspDeInitCallback = HAL_SD_MspDeInit;
+ break;
+ default :
+ /* Update the error code */
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hsd->State == HAL_SD_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SD_MSP_INIT_CB_ID :
+ hsd->MspInitCallback = HAL_SD_MspInit;
+ break;
+ case HAL_SD_MSP_DEINIT_CB_ID :
+ hsd->MspDeInitCallback = HAL_SD_MspDeInit;
+ break;
+ default :
+ /* Update the error code */
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsd);
+ return status;
+}
+
+#if (USE_SD_TRANSCEIVER != 0U)
+/**
+ * @brief Register a User SD Transceiver Callback
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hsd : SD handle
+ * @param pCallback : pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_SD_RegisterTransceiverCallback(SD_HandleTypeDef *hsd, pSD_TransceiverCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hsd);
+
+ if (hsd->State == HAL_SD_STATE_READY)
+ {
+ hsd->DriveTransceiver_1_8V_Callback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsd);
+ return status;
+}
+
+/**
+ * @brief Unregister a User SD Transceiver Callback
+ * SD Callback is redirected to the weak (surcharged) predefined callback
+ * @param hsd : SD handle
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_SD_UnRegisterTransceiverCallback(SD_HandleTypeDef *hsd)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hsd);
+
+ if (hsd->State == HAL_SD_STATE_READY)
+ {
+ hsd->DriveTransceiver_1_8V_Callback = HAL_SD_DriveTransceiver_1_8V_Callback;
+ }
+ else
+ {
+ /* Update the error code */
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsd);
+ return status;
+}
+#endif /* USE_SD_TRANSCEIVER */
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SD_Exported_Functions_Group3
+ * @brief management functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the SD card
+ operations and get the related information
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns information the information of the card which are stored on
+ * the CID register.
+ * @param hsd: Pointer to SD handle
+ * @param pCID: Pointer to a HAL_SD_CardCIDTypeDef structure that
+ * contains all CID register parameters
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID)
+{
+ pCID->ManufacturerID = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24U);
+
+ pCID->OEM_AppliID = (uint16_t)((hsd->CID[0] & 0x00FFFF00U) >> 8U);
+
+ pCID->ProdName1 = (((hsd->CID[0] & 0x000000FFU) << 24U) | ((hsd->CID[1] & 0xFFFFFF00U) >> 8U));
+
+ pCID->ProdName2 = (uint8_t)(hsd->CID[1] & 0x000000FFU);
+
+ pCID->ProdRev = (uint8_t)((hsd->CID[2] & 0xFF000000U) >> 24U);
+
+ pCID->ProdSN = (((hsd->CID[2] & 0x00FFFFFFU) << 8U) | ((hsd->CID[3] & 0xFF000000U) >> 24U));
+
+ pCID->Reserved1 = (uint8_t)((hsd->CID[3] & 0x00F00000U) >> 20U);
+
+ pCID->ManufactDate = (uint16_t)((hsd->CID[3] & 0x000FFF00U) >> 8U);
+
+ pCID->CID_CRC = (uint8_t)((hsd->CID[3] & 0x000000FEU) >> 1U);
+
+ pCID->Reserved2 = 1U;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Returns information the information of the card which are stored on
+ * the CSD register.
+ * @param hsd: Pointer to SD handle
+ * @param pCSD: Pointer to a HAL_SD_CardCSDTypeDef structure that
+ * contains all CSD register parameters
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD)
+{
+ pCSD->CSDStruct = (uint8_t)((hsd->CSD[0] & 0xC0000000U) >> 30U);
+
+ pCSD->SysSpecVersion = (uint8_t)((hsd->CSD[0] & 0x3C000000U) >> 26U);
+
+ pCSD->Reserved1 = (uint8_t)((hsd->CSD[0] & 0x03000000U) >> 24U);
+
+ pCSD->TAAC = (uint8_t)((hsd->CSD[0] & 0x00FF0000U) >> 16U);
+
+ pCSD->NSAC = (uint8_t)((hsd->CSD[0] & 0x0000FF00U) >> 8U);
+
+ pCSD->MaxBusClkFrec = (uint8_t)(hsd->CSD[0] & 0x000000FFU);
+
+ pCSD->CardComdClasses = (uint16_t)((hsd->CSD[1] & 0xFFF00000U) >> 20U);
+
+ pCSD->RdBlockLen = (uint8_t)((hsd->CSD[1] & 0x000F0000U) >> 16U);
+
+ pCSD->PartBlockRead = (uint8_t)((hsd->CSD[1] & 0x00008000U) >> 15U);
+
+ pCSD->WrBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00004000U) >> 14U);
+
+ pCSD->RdBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00002000U) >> 13U);
+
+ pCSD->DSRImpl = (uint8_t)((hsd->CSD[1] & 0x00001000U) >> 12U);
+
+ pCSD->Reserved2 = 0U; /*!< Reserved */
+
+ if (hsd->SdCard.CardType == CARD_SDSC)
+ {
+ pCSD->DeviceSize = (((hsd->CSD[1] & 0x000003FFU) << 2U) | ((hsd->CSD[2] & 0xC0000000U) >> 30U));
+
+ pCSD->MaxRdCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x38000000U) >> 27U);
+
+ pCSD->MaxRdCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x07000000U) >> 24U);
+
+ pCSD->MaxWrCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x00E00000U) >> 21U);
+
+ pCSD->MaxWrCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x001C0000U) >> 18U);
+
+ pCSD->DeviceSizeMul = (uint8_t)((hsd->CSD[2] & 0x00038000U) >> 15U);
+
+ hsd->SdCard.BlockNbr = (pCSD->DeviceSize + 1U) ;
+ hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U));
+ hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU));
+
+ hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U);
+ hsd->SdCard.LogBlockSize = 512U;
+ }
+ else if (hsd->SdCard.CardType == CARD_SDHC_SDXC)
+ {
+ /* Byte 7 */
+ pCSD->DeviceSize = (((hsd->CSD[1] & 0x0000003FU) << 16U) | ((hsd->CSD[2] & 0xFFFF0000U) >> 16U));
+
+ hsd->SdCard.BlockNbr = ((pCSD->DeviceSize + 1U) * 1024U);
+ hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr;
+ hsd->SdCard.BlockSize = 512U;
+ hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize;
+ }
+ else
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ pCSD->EraseGrSize = (uint8_t)((hsd->CSD[2] & 0x00004000U) >> 14U);
+
+ pCSD->EraseGrMul = (uint8_t)((hsd->CSD[2] & 0x00003F80U) >> 7U);
+
+ pCSD->WrProtectGrSize = (uint8_t)(hsd->CSD[2] & 0x0000007FU);
+
+ pCSD->WrProtectGrEnable = (uint8_t)((hsd->CSD[3] & 0x80000000U) >> 31U);
+
+ pCSD->ManDeflECC = (uint8_t)((hsd->CSD[3] & 0x60000000U) >> 29U);
+
+ pCSD->WrSpeedFact = (uint8_t)((hsd->CSD[3] & 0x1C000000U) >> 26U);
+
+ pCSD->MaxWrBlockLen = (uint8_t)((hsd->CSD[3] & 0x03C00000U) >> 22U);
+
+ pCSD->WriteBlockPaPartial = (uint8_t)((hsd->CSD[3] & 0x00200000U) >> 21U);
+
+ pCSD->Reserved3 = 0;
+
+ pCSD->ContentProtectAppli = (uint8_t)((hsd->CSD[3] & 0x00010000U) >> 16U);
+
+ pCSD->FileFormatGroup = (uint8_t)((hsd->CSD[3] & 0x00008000U) >> 15U);
+
+ pCSD->CopyFlag = (uint8_t)((hsd->CSD[3] & 0x00004000U) >> 14U);
+
+ pCSD->PermWrProtect = (uint8_t)((hsd->CSD[3] & 0x00002000U) >> 13U);
+
+ pCSD->TempWrProtect = (uint8_t)((hsd->CSD[3] & 0x00001000U) >> 12U);
+
+ pCSD->FileFormat = (uint8_t)((hsd->CSD[3] & 0x00000C00U) >> 10U);
+
+ pCSD->ECC = (uint8_t)((hsd->CSD[3] & 0x00000300U) >> 8U);
+
+ pCSD->CSD_CRC = (uint8_t)((hsd->CSD[3] & 0x000000FEU) >> 1U);
+
+ pCSD->Reserved4 = 1;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Gets the SD status info.
+ * @param hsd: Pointer to SD handle
+ * @param pStatus: Pointer to the HAL_SD_CardStatusTypeDef structure that
+ * will contain the SD card status information
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus)
+{
+ uint32_t sd_status[16];
+ uint32_t errorstate;
+ HAL_StatusTypeDef status = HAL_OK;
+
+ errorstate = SD_SendSDStatus(hsd, sd_status);
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ status = HAL_ERROR;
+ }
+ else
+ {
+ pStatus->DataBusWidth = (uint8_t)((sd_status[0] & 0xC0U) >> 6U);
+
+ pStatus->SecuredMode = (uint8_t)((sd_status[0] & 0x20U) >> 5U);
+
+ pStatus->CardType = (uint16_t)(((sd_status[0] & 0x00FF0000U) >> 8U) | ((sd_status[0] & 0xFF000000U) >> 24U));
+
+ pStatus->ProtectedAreaSize = (((sd_status[1] & 0xFFU) << 24U) | ((sd_status[1] & 0xFF00U) << 8U) |
+ ((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U) >> 24U));
+
+ pStatus->SpeedClass = (uint8_t)(sd_status[2] & 0xFFU);
+
+ pStatus->PerformanceMove = (uint8_t)((sd_status[2] & 0xFF00U) >> 8U);
+
+ pStatus->AllocationUnitSize = (uint8_t)((sd_status[2] & 0xF00000U) >> 20U);
+
+ pStatus->EraseSize = (uint16_t)(((sd_status[2] & 0xFF000000U) >> 16U) | (sd_status[3] & 0xFFU));
+
+ pStatus->EraseTimeout = (uint8_t)((sd_status[3] & 0xFC00U) >> 10U);
+
+ pStatus->EraseOffset = (uint8_t)((sd_status[3] & 0x0300U) >> 8U);
+
+ pStatus->UhsSpeedGrade = (uint8_t)((sd_status[3] & 0x00F0U) >> 4U);
+ pStatus->UhsAllocationUnitSize = (uint8_t)(sd_status[3] & 0x000FU) ;
+ pStatus->VideoSpeedClass = (uint8_t)((sd_status[4] & 0xFF000000U) >> 24U);
+ }
+
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode = errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Gets the SD card info.
+ * @param hsd: Pointer to SD handle
+ * @param pCardInfo: Pointer to the HAL_SD_CardInfoTypeDef structure that
+ * will contain the SD card status information
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo)
+{
+ pCardInfo->CardType = (uint32_t)(hsd->SdCard.CardType);
+ pCardInfo->CardVersion = (uint32_t)(hsd->SdCard.CardVersion);
+ pCardInfo->Class = (uint32_t)(hsd->SdCard.Class);
+ pCardInfo->RelCardAdd = (uint32_t)(hsd->SdCard.RelCardAdd);
+ pCardInfo->BlockNbr = (uint32_t)(hsd->SdCard.BlockNbr);
+ pCardInfo->BlockSize = (uint32_t)(hsd->SdCard.BlockSize);
+ pCardInfo->LogBlockNbr = (uint32_t)(hsd->SdCard.LogBlockNbr);
+ pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables wide bus operation for the requested card if supported by
+ * card.
+ * @param hsd: Pointer to SD handle
+ * @param WideMode: Specifies the SD card wide bus mode
+ * This parameter can be one of the following values:
+ * @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer
+ * @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer
+ * @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode)
+{
+ SDMMC_InitTypeDef Init;
+ uint32_t errorstate;
+ uint32_t sdmmc_clk;
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_SDMMC_BUS_WIDE(WideMode));
+
+ /* Change State */
+ hsd->State = HAL_SD_STATE_BUSY;
+
+ if (hsd->SdCard.CardType != CARD_SECURED)
+ {
+ if (WideMode == SDMMC_BUS_WIDE_8B)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ }
+ else if (WideMode == SDMMC_BUS_WIDE_4B)
+ {
+ errorstate = SD_WideBus_Enable(hsd);
+
+ hsd->ErrorCode |= errorstate;
+ }
+ else if (WideMode == SDMMC_BUS_WIDE_1B)
+ {
+ errorstate = SD_WideBus_Disable(hsd);
+
+ hsd->ErrorCode |= errorstate;
+ }
+ else
+ {
+ /* WideMode is not a valid argument*/
+ hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+ }
+ }
+ else
+ {
+ /* MMC Card does not support this feature */
+ hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ }
+
+ if (hsd->ErrorCode != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ status = HAL_ERROR;
+ }
+ else
+ {
+ sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC);
+ if (sdmmc_clk != 0U)
+ {
+ /* Configure the SDMMC peripheral */
+ Init.ClockEdge = hsd->Init.ClockEdge;
+ Init.ClockPowerSave = hsd->Init.ClockPowerSave;
+ Init.BusWide = WideMode;
+ Init.HardwareFlowControl = hsd->Init.HardwareFlowControl;
+
+ /* Check if user Clock div < Normal speed 25Mhz, no change in Clockdiv */
+ if (hsd->Init.ClockDiv >= (sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ)))
+ {
+ Init.ClockDiv = hsd->Init.ClockDiv;
+ }
+ else if (hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED)
+ {
+ /* UltraHigh speed SD card,user Clock div */
+ Init.ClockDiv = hsd->Init.ClockDiv;
+ }
+ else if (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED)
+ {
+ /* High speed SD card, Max Frequency = 50Mhz */
+ if (hsd->Init.ClockDiv == 0U)
+ {
+ if (sdmmc_clk > SD_HIGH_SPEED_FREQ)
+ {
+ Init.ClockDiv = sdmmc_clk / (2U * SD_HIGH_SPEED_FREQ);
+ }
+ else
+ {
+ Init.ClockDiv = hsd->Init.ClockDiv;
+ }
+ }
+ else
+ {
+ if ((sdmmc_clk / (2U * hsd->Init.ClockDiv)) > SD_HIGH_SPEED_FREQ)
+ {
+ Init.ClockDiv = sdmmc_clk / (2U * SD_HIGH_SPEED_FREQ);
+ }
+ else
+ {
+ Init.ClockDiv = hsd->Init.ClockDiv;
+ }
+ }
+ }
+ else
+ {
+ /* No High speed SD card, Max Frequency = 25Mhz */
+ if (hsd->Init.ClockDiv == 0U)
+ {
+ if (sdmmc_clk > SD_NORMAL_SPEED_FREQ)
+ {
+ Init.ClockDiv = sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ);
+ }
+ else
+ {
+ Init.ClockDiv = hsd->Init.ClockDiv;
+ }
+ }
+ else
+ {
+ if ((sdmmc_clk / (2U * hsd->Init.ClockDiv)) > SD_NORMAL_SPEED_FREQ)
+ {
+ Init.ClockDiv = sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ);
+ }
+ else
+ {
+ Init.ClockDiv = hsd->Init.ClockDiv;
+ }
+ }
+ }
+
+#if (USE_SD_TRANSCEIVER != 0U)
+ Init.TranceiverPresent = hsd->Init.TranceiverPresent;
+#endif /* USE_SD_TRANSCEIVER */
+
+ (void)SDMMC_Init(hsd->Instance, Init);
+ }
+ else
+ {
+ hsd->ErrorCode |= SDMMC_ERROR_INVALID_PARAMETER;
+ status = HAL_ERROR;
+ }
+ }
+
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ status = HAL_ERROR;
+ }
+
+ /* Change State */
+ hsd->State = HAL_SD_STATE_READY;
+
+ return status;
+}
+
+/**
+ * @brief Configure the speed bus mode
+ * @param hsd: Pointer to the SD handle
+ * @param SpeedMode: Specifies the SD card speed bus mode
+ * This parameter can be one of the following values:
+ * @arg SDMMC_SPEED_MODE_AUTO: Max speed mode supported by the card
+ * @arg SDMMC_SPEED_MODE_DEFAULT: Default Speed/SDR12 mode
+ * @arg SDMMC_SPEED_MODE_HIGH: High Speed/SDR25 mode
+ * @arg SDMMC_SPEED_MODE_ULTRA: Ultra high speed mode
+ * @retval HAL status
+ */
+
+HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t SpeedMode)
+{
+ uint32_t tickstart;
+ uint32_t errorstate;
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_SDMMC_SPEED_MODE(SpeedMode));
+ /* Change State */
+ hsd->State = HAL_SD_STATE_BUSY;
+
+#if (USE_SD_TRANSCEIVER != 0U)
+ if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT)
+ {
+ switch (SpeedMode)
+ {
+ case SDMMC_SPEED_MODE_AUTO:
+ {
+ if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) ||
+ (hsd->SdCard.CardType == CARD_SDHC_SDXC))
+ {
+ hsd->Instance->CLKCR |= SDMMC_CLKCR_BUSSPEED;
+ /* Enable Ultra High Speed */
+ if (SD_UltraHighSpeed(hsd) != HAL_SD_ERROR_NONE)
+ {
+ if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ status = HAL_ERROR;
+ }
+ }
+ }
+ else if (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED)
+ {
+ /* Enable High Speed */
+ if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ /*Nothing to do, Use defaultSpeed */
+ }
+ break;
+ }
+ case SDMMC_SPEED_MODE_ULTRA:
+ {
+ if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) ||
+ (hsd->SdCard.CardType == CARD_SDHC_SDXC))
+ {
+ /* Enable UltraHigh Speed */
+ if (SD_UltraHighSpeed(hsd) != HAL_SD_ERROR_NONE)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ status = HAL_ERROR;
+ }
+ hsd->Instance->CLKCR |= SDMMC_CLKCR_BUSSPEED;
+ }
+ else
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ status = HAL_ERROR;
+ }
+ break;
+ }
+ case SDMMC_SPEED_MODE_DDR:
+ {
+ if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) ||
+ (hsd->SdCard.CardType == CARD_SDHC_SDXC))
+ {
+ /* Enable DDR Mode*/
+ if (SD_DDR_Mode(hsd) != HAL_SD_ERROR_NONE)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ status = HAL_ERROR;
+ }
+ hsd->Instance->CLKCR |= SDMMC_CLKCR_BUSSPEED | SDMMC_CLKCR_DDR;
+ }
+ else
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ status = HAL_ERROR;
+ }
+ break;
+ }
+ case SDMMC_SPEED_MODE_HIGH:
+ {
+ if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) ||
+ (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) ||
+ (hsd->SdCard.CardType == CARD_SDHC_SDXC))
+ {
+ /* Enable High Speed */
+ if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ status = HAL_ERROR;
+ }
+ break;
+ }
+ case SDMMC_SPEED_MODE_DEFAULT:
+ break;
+ default:
+ hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ switch (SpeedMode)
+ {
+ case SDMMC_SPEED_MODE_AUTO:
+ {
+ if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) ||
+ (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) ||
+ (hsd->SdCard.CardType == CARD_SDHC_SDXC))
+ {
+ /* Enable High Speed */
+ if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ /*Nothing to do, Use defaultSpeed */
+ }
+ break;
+ }
+ case SDMMC_SPEED_MODE_HIGH:
+ {
+ if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) ||
+ (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) ||
+ (hsd->SdCard.CardType == CARD_SDHC_SDXC))
+ {
+ /* Enable High Speed */
+ if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ status = HAL_ERROR;
+ }
+ break;
+ }
+ case SDMMC_SPEED_MODE_DEFAULT:
+ break;
+ case SDMMC_SPEED_MODE_ULTRA: /*not valid without transceiver*/
+ default:
+ hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+ status = HAL_ERROR;
+ break;
+ }
+ }
+#else
+ switch (SpeedMode)
+ {
+ case SDMMC_SPEED_MODE_AUTO:
+ {
+ if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) ||
+ (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) ||
+ (hsd->SdCard.CardType == CARD_SDHC_SDXC))
+ {
+ /* Enable High Speed */
+ if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ /*Nothing to do, Use defaultSpeed */
+ }
+ break;
+ }
+ case SDMMC_SPEED_MODE_HIGH:
+ {
+ if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) ||
+ (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) ||
+ (hsd->SdCard.CardType == CARD_SDHC_SDXC))
+ {
+ /* Enable High Speed */
+ if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ status = HAL_ERROR;
+ }
+ break;
+ }
+ case SDMMC_SPEED_MODE_DEFAULT:
+ break;
+ case SDMMC_SPEED_MODE_ULTRA: /*not valid without transceiver*/
+ default:
+ hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+ status = HAL_ERROR;
+ break;
+ }
+#endif /* USE_SD_TRANSCEIVER */
+
+ /* Verify that SD card is ready to use after Speed mode switch*/
+ tickstart = HAL_GetTick();
+ while ((HAL_SD_GetCardState(hsd) != HAL_SD_CARD_TRANSFER))
+ {
+ if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+ {
+ hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ status = HAL_ERROR;
+ }
+
+ /* Change State */
+ hsd->State = HAL_SD_STATE_READY;
+ return status;
+}
+
+/**
+ * @brief Gets the current sd card data state.
+ * @param hsd: pointer to SD handle
+ * @retval Card state
+ */
+HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd)
+{
+ uint32_t cardstate;
+ uint32_t errorstate;
+ uint32_t resp1 = 0;
+
+ errorstate = SD_SendStatus(hsd, &resp1);
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ hsd->ErrorCode |= errorstate;
+ }
+
+ cardstate = ((resp1 >> 9U) & 0x0FU);
+
+ return (HAL_SD_CardStateTypeDef)cardstate;
+}
+
+/**
+ * @brief Abort the current transfer and disable the SD.
+ * @param hsd: pointer to a SD_HandleTypeDef structure that contains
+ * the configuration information for SD module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd)
+{
+ HAL_SD_CardStateTypeDef CardState;
+
+ /* DIsable All interrupts */
+ __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+ SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR);
+
+ /* Clear All flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+ /* If IDMA Context, disable Internal DMA */
+ hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
+
+ hsd->State = HAL_SD_STATE_READY;
+
+ /* Initialize the SD operation */
+ hsd->Context = SD_CONTEXT_NONE;
+
+ CardState = HAL_SD_GetCardState(hsd);
+ if ((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+ {
+ hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
+ }
+ if (hsd->ErrorCode != HAL_SD_ERROR_NONE)
+ {
+ return HAL_ERROR;
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort the current transfer and disable the SD (IT mode).
+ * @param hsd: pointer to a SD_HandleTypeDef structure that contains
+ * the configuration information for SD module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd)
+{
+ HAL_SD_CardStateTypeDef CardState;
+
+ /* Disable All interrupts */
+ __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+ SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR);
+
+ /* If IDMA Context, disable Internal DMA */
+ hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
+
+ /* Clear All flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+ CardState = HAL_SD_GetCardState(hsd);
+ hsd->State = HAL_SD_STATE_READY;
+
+ if ((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+ {
+ hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
+ }
+
+ if (hsd->ErrorCode != HAL_SD_ERROR_NONE)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+ hsd->AbortCpltCallback(hsd);
+#else
+ HAL_SD_AbortCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private function ----------------------------------------------------------*/
+/** @addtogroup SD_Private_Functions
+ * @{
+ */
+
+
+/**
+ * @brief Initializes the sd card.
+ * @param hsd: Pointer to SD handle
+ * @retval SD Card error state
+ */
+static uint32_t SD_InitCard(SD_HandleTypeDef *hsd)
+{
+ HAL_SD_CardCSDTypeDef CSD;
+ uint32_t errorstate;
+ uint16_t sd_rca = 1U;
+
+ /* Check the power State */
+ if (SDMMC_GetPowerState(hsd->Instance) == 0U)
+ {
+ /* Power off */
+ return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+ }
+
+ if (hsd->SdCard.CardType != CARD_SECURED)
+ {
+ /* Send CMD2 ALL_SEND_CID */
+ errorstate = SDMMC_CmdSendCID(hsd->Instance);
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ return errorstate;
+ }
+ else
+ {
+ /* Get Card identification number data */
+ hsd->CID[0U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
+ hsd->CID[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
+ hsd->CID[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);
+ hsd->CID[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
+ }
+ }
+
+ if (hsd->SdCard.CardType != CARD_SECURED)
+ {
+ /* Send CMD3 SET_REL_ADDR with argument 0 */
+ /* SD Card publishes its RCA. */
+ errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca);
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ return errorstate;
+ }
+ }
+ if (hsd->SdCard.CardType != CARD_SECURED)
+ {
+ /* Get the SD card RCA */
+ hsd->SdCard.RelCardAdd = sd_rca;
+
+ /* Send CMD9 SEND_CSD with argument as card's RCA */
+ errorstate = SDMMC_CmdSendCSD(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ return errorstate;
+ }
+ else
+ {
+ /* Get Card Specific Data */
+ hsd->CSD[0U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
+ hsd->CSD[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
+ hsd->CSD[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);
+ hsd->CSD[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
+ }
+ }
+
+ /* Get the Card Class */
+ hsd->SdCard.Class = (SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2) >> 20U);
+
+ /* Get CSD parameters */
+ if (HAL_SD_GetCardCSD(hsd, &CSD) != HAL_OK)
+ {
+ return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ }
+
+ /* Select the Card */
+ errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16U));
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ return errorstate;
+ }
+
+ /* All cards are initialized */
+ return HAL_SD_ERROR_NONE;
+}
+
+/**
+ * @brief Enquires cards about their operating voltage and configures clock
+ * controls and stores SD information that will be needed in future
+ * in the SD handle.
+ * @param hsd: Pointer to SD handle
+ * @retval error state
+ */
+static uint32_t SD_PowerON(SD_HandleTypeDef *hsd)
+{
+ __IO uint32_t count = 0U;
+ uint32_t response = 0U;
+ uint32_t validvoltage = 0U;
+ uint32_t errorstate;
+#if (USE_SD_TRANSCEIVER != 0U)
+ uint32_t tickstart = HAL_GetTick();
+#endif /* USE_SD_TRANSCEIVER */
+
+ /* CMD0: GO_IDLE_STATE */
+ errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ return errorstate;
+ }
+
+ /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */
+ errorstate = SDMMC_CmdOperCond(hsd->Instance);
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ hsd->SdCard.CardVersion = CARD_V1_X;
+ /* CMD0: GO_IDLE_STATE */
+ errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ return errorstate;
+ }
+
+ }
+ else
+ {
+ hsd->SdCard.CardVersion = CARD_V2_X;
+ }
+
+ if (hsd->SdCard.CardVersion == CARD_V2_X)
+ {
+ /* SEND CMD55 APP_CMD with RCA as 0 */
+ errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ }
+ }
+ /* SD CARD */
+ /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
+ while ((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U))
+ {
+ /* SEND CMD55 APP_CMD with RCA as 0 */
+ errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ return errorstate;
+ }
+
+ /* Send CMD41 */
+ errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACITY |
+ SD_SWITCH_1_8V_CAPACITY);
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ }
+
+ /* Get command response */
+ response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
+
+ /* Get operating voltage*/
+ validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);
+
+ count++;
+ }
+
+ if (count >= SDMMC_MAX_VOLT_TRIAL)
+ {
+ return HAL_SD_ERROR_INVALID_VOLTRANGE;
+ }
+
+ if ((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
+ {
+ hsd->SdCard.CardType = CARD_SDHC_SDXC;
+#if (USE_SD_TRANSCEIVER != 0U)
+ if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT)
+ {
+ if ((response & SD_SWITCH_1_8V_CAPACITY) == SD_SWITCH_1_8V_CAPACITY)
+ {
+ hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED;
+
+ /* Start switching procedue */
+ hsd->Instance->POWER |= SDMMC_POWER_VSWITCHEN;
+
+ /* Send CMD11 to switch 1.8V mode */
+ errorstate = SDMMC_CmdVoltageSwitch(hsd->Instance);
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ return errorstate;
+ }
+
+ /* Check to CKSTOP */
+ while ((hsd->Instance->STA & SDMMC_FLAG_CKSTOP) != SDMMC_FLAG_CKSTOP)
+ {
+ if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+ {
+ return HAL_SD_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear CKSTOP Flag */
+ hsd->Instance->ICR = SDMMC_FLAG_CKSTOP;
+
+ /* Check to BusyD0 */
+ if ((hsd->Instance->STA & SDMMC_FLAG_BUSYD0) != SDMMC_FLAG_BUSYD0)
+ {
+ /* Error when activate Voltage Switch in SDMMC Peripheral */
+ return SDMMC_ERROR_UNSUPPORTED_FEATURE;
+ }
+ else
+ {
+ /* Enable Transceiver Switch PIN */
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+ hsd->DriveTransceiver_1_8V_Callback(SET);
+#else
+ HAL_SD_DriveTransceiver_1_8V_Callback(SET);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+
+ /* Switch ready */
+ hsd->Instance->POWER |= SDMMC_POWER_VSWITCH;
+
+ /* Check VSWEND Flag */
+ while ((hsd->Instance->STA & SDMMC_FLAG_VSWEND) != SDMMC_FLAG_VSWEND)
+ {
+ if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+ {
+ return HAL_SD_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear VSWEND Flag */
+ hsd->Instance->ICR = SDMMC_FLAG_VSWEND;
+
+ /* Check BusyD0 status */
+ if ((hsd->Instance->STA & SDMMC_FLAG_BUSYD0) == SDMMC_FLAG_BUSYD0)
+ {
+ /* Error when enabling 1.8V mode */
+ return HAL_SD_ERROR_INVALID_VOLTRANGE;
+ }
+ /* Switch to 1.8V OK */
+
+ /* Disable VSWITCH FLAG from SDMMC Peripheral */
+ hsd->Instance->POWER = 0x13U;
+
+ /* Clean Status flags */
+ hsd->Instance->ICR = 0xFFFFFFFFU;
+ }
+ }
+ }
+#endif /* USE_SD_TRANSCEIVER */
+ }
+
+ return HAL_SD_ERROR_NONE;
+}
+
+/**
+ * @brief Turns the SDMMC output signals off.
+ * @param hsd: Pointer to SD handle
+ * @retval None
+ */
+static void SD_PowerOFF(SD_HandleTypeDef *hsd)
+{
+ /* Set Power State to OFF */
+ (void)SDMMC_PowerState_OFF(hsd->Instance);
+}
+
+/**
+ * @brief Send Status info command.
+ * @param hsd: pointer to SD handle
+ * @param pSDstatus: Pointer to the buffer that will contain the SD card status
+ * SD Status register)
+ * @retval error state
+ */
+static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
+{
+ SDMMC_DataInitTypeDef config;
+ uint32_t errorstate;
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t count;
+ uint32_t *pData = pSDstatus;
+
+ /* Check SD response */
+ if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+ {
+ return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
+ }
+
+ /* Set block size for card if it is not equal to current block size for card */
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U);
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_NONE;
+ return errorstate;
+ }
+
+ /* Send CMD55 */
+ errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_NONE;
+ return errorstate;
+ }
+
+ /* Configure the SD DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = 64U;
+ config.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B;
+ config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
+ config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDMMC_DPSM_ENABLE;
+ (void)SDMMC_ConfigData(hsd->Instance, &config);
+
+ /* Send ACMD13 (SD_APP_STAUS) with argument as card's RCA */
+ errorstate = SDMMC_CmdStatusRegister(hsd->Instance);
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_NONE;
+ return errorstate;
+ }
+
+ /* Get status data */
+ while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+ {
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
+ {
+ for (count = 0U; count < 8U; count++)
+ {
+ *pData = SDMMC_ReadFIFO(hsd->Instance);
+ pData++;
+ }
+ }
+
+ if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+ {
+ return HAL_SD_ERROR_TIMEOUT;
+ }
+ }
+
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+ {
+ return HAL_SD_ERROR_DATA_TIMEOUT;
+ }
+ else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+ {
+ return HAL_SD_ERROR_DATA_CRC_FAIL;
+ }
+ else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
+ {
+ return HAL_SD_ERROR_RX_OVERRUN;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DPSMACT)))
+ {
+ *pData = SDMMC_ReadFIFO(hsd->Instance);
+ pData++;
+
+ if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+ {
+ return HAL_SD_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear all the static status flags*/
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+ return HAL_SD_ERROR_NONE;
+}
+
+/**
+ * @brief Returns the current card's status.
+ * @param hsd: Pointer to SD handle
+ * @param pCardStatus: pointer to the buffer that will contain the SD card
+ * status (Card Status register)
+ * @retval error state
+ */
+static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
+{
+ uint32_t errorstate;
+
+ if (pCardStatus == NULL)
+ {
+ return HAL_SD_ERROR_PARAM;
+ }
+
+ /* Send Status command */
+ errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ return errorstate;
+ }
+
+ /* Get SD card status */
+ *pCardStatus = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
+
+ return HAL_SD_ERROR_NONE;
+}
+
+/**
+ * @brief Enables the SDMMC wide bus mode.
+ * @param hsd: pointer to SD handle
+ * @retval error state
+ */
+static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd)
+{
+ uint32_t scr[2U] = {0UL, 0UL};
+ uint32_t errorstate;
+
+ if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+ {
+ return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
+ }
+
+ /* Get SCR Register */
+ errorstate = SD_FindSCR(hsd, scr);
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ return errorstate;
+ }
+
+ /* If requested card supports wide bus operation */
+ if ((scr[1U] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO)
+ {
+ /* Send CMD55 APP_CMD with argument as card's RCA.*/
+ errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ return errorstate;
+ }
+
+ /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
+ errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2U);
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ return errorstate;
+ }
+
+ return HAL_SD_ERROR_NONE;
+ }
+ else
+ {
+ return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+ }
+}
+
+/**
+ * @brief Disables the SDMMC wide bus mode.
+ * @param hsd: Pointer to SD handle
+ * @retval error state
+ */
+static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd)
+{
+ uint32_t scr[2U] = {0UL, 0UL};
+ uint32_t errorstate;
+
+ if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+ {
+ return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
+ }
+
+ /* Get SCR Register */
+ errorstate = SD_FindSCR(hsd, scr);
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ return errorstate;
+ }
+
+ /* If requested card supports 1 bit mode operation */
+ if ((scr[1U] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO)
+ {
+ /* Send CMD55 APP_CMD with argument as card's RCA */
+ errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ return errorstate;
+ }
+
+ /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */
+ errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0U);
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ return errorstate;
+ }
+
+ return HAL_SD_ERROR_NONE;
+ }
+ else
+ {
+ return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+ }
+}
+
+
+/**
+ * @brief Finds the SD card SCR register value.
+ * @param hsd: Pointer to SD handle
+ * @param pSCR: pointer to the buffer that will contain the SCR value
+ * @retval error state
+ */
+static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
+{
+ SDMMC_DataInitTypeDef config;
+ uint32_t errorstate;
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t index = 0U;
+ uint32_t tempscr[2U] = {0UL, 0UL};
+ uint32_t *scr = pSCR;
+
+ /* Set Block Size To 8 Bytes */
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8U);
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ return errorstate;
+ }
+
+ /* Send CMD55 APP_CMD with argument as card's RCA */
+ errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16U));
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ return errorstate;
+ }
+
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = 8U;
+ config.DataBlockSize = SDMMC_DATABLOCK_SIZE_8B;
+ config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
+ config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDMMC_DPSM_ENABLE;
+ (void)SDMMC_ConfigData(hsd->Instance, &config);
+
+ /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */
+ errorstate = SDMMC_CmdSendSCR(hsd->Instance);
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ return errorstate;
+ }
+
+ while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND |
+ SDMMC_FLAG_DATAEND))
+ {
+ if ((!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOE)) && (index == 0U))
+ {
+ tempscr[0] = SDMMC_ReadFIFO(hsd->Instance);
+ tempscr[1] = SDMMC_ReadFIFO(hsd->Instance);
+ index++;
+ }
+
+
+ if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+ {
+ return HAL_SD_ERROR_TIMEOUT;
+ }
+ }
+
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+ {
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
+
+ return HAL_SD_ERROR_DATA_TIMEOUT;
+ }
+ else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+ {
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
+
+ return HAL_SD_ERROR_DATA_CRC_FAIL;
+ }
+ else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
+ {
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
+
+ return HAL_SD_ERROR_RX_OVERRUN;
+ }
+ else
+ {
+ /* No error flag set */
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+ *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) | \
+ ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24));
+ scr++;
+ *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) | \
+ ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24));
+
+ }
+
+ return HAL_SD_ERROR_NONE;
+}
+
+/**
+ * @brief Wrap up reading in non-blocking mode.
+ * @param hsd: pointer to a SD_HandleTypeDef structure that contains
+ * the configuration information.
+ * @retval None
+ */
+static void SD_Read_IT(SD_HandleTypeDef *hsd)
+{
+ uint32_t count;
+ uint32_t data;
+ uint8_t *tmp;
+
+ tmp = hsd->pRxBuffPtr;
+
+ if (hsd->RxXferSize >= 32U)
+ {
+ /* Read data from SDMMC Rx FIFO */
+ for (count = 0U; count < 8U; count++)
+ {
+ data = SDMMC_ReadFIFO(hsd->Instance);
+ *tmp = (uint8_t)(data & 0xFFU);
+ tmp++;
+ *tmp = (uint8_t)((data >> 8U) & 0xFFU);
+ tmp++;
+ *tmp = (uint8_t)((data >> 16U) & 0xFFU);
+ tmp++;
+ *tmp = (uint8_t)((data >> 24U) & 0xFFU);
+ tmp++;
+ }
+
+ hsd->pRxBuffPtr = tmp;
+ hsd->RxXferSize -= 32U;
+ }
+}
+
+/**
+ * @brief Wrap up writing in non-blocking mode.
+ * @param hsd: pointer to a SD_HandleTypeDef structure that contains
+ * the configuration information.
+ * @retval None
+ */
+static void SD_Write_IT(SD_HandleTypeDef *hsd)
+{
+ uint32_t count;
+ uint32_t data;
+ uint8_t *tmp;
+
+ tmp = hsd->pTxBuffPtr;
+
+ if (hsd->TxXferSize >= 32U)
+ {
+ /* Write data to SDMMC Tx FIFO */
+ for (count = 0U; count < 8U; count++)
+ {
+ data = (uint32_t)(*tmp);
+ tmp++;
+ data |= ((uint32_t)(*tmp) << 8U);
+ tmp++;
+ data |= ((uint32_t)(*tmp) << 16U);
+ tmp++;
+ data |= ((uint32_t)(*tmp) << 24U);
+ tmp++;
+ (void)SDMMC_WriteFIFO(hsd->Instance, &data);
+ }
+
+ hsd->pTxBuffPtr = tmp;
+ hsd->TxXferSize -= 32U;
+ }
+}
+
+/**
+ * @brief Switches the SD card to High Speed mode.
+ * This API must be used after "Transfer State"
+ * @note This operation should be followed by the configuration
+ * of PLL to have SDMMCCK clock between 50 and 120 MHz
+ * @param hsd: SD handle
+ * @retval SD Card error state
+ */
+uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd)
+{
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
+ SDMMC_DataInitTypeDef sdmmc_datainitstructure;
+ uint32_t SD_hs[16] = {0};
+ uint32_t count;
+ uint32_t loop = 0 ;
+ uint32_t Timeout = HAL_GetTick();
+
+ if (hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED)
+ {
+ /* Standard Speed Card <= 12.5Mhz */
+ return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+ }
+
+ if (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED)
+ {
+ /* Initialize the Data control register */
+ hsd->Instance->DCTRL = 0;
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U);
+
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ return errorstate;
+ }
+
+ /* Configure the SD DPSM (Data Path State Machine) */
+ sdmmc_datainitstructure.DataTimeOut = SDMMC_DATATIMEOUT;
+ sdmmc_datainitstructure.DataLength = 64U;
+ sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ;
+ sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
+ sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE;
+
+ (void)SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure);
+
+
+ errorstate = SDMMC_CmdSwitch(hsd->Instance, SDMMC_SDR25_SWITCH_PATTERN);
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ return errorstate;
+ }
+
+ while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND |
+ SDMMC_FLAG_DATAEND))
+ {
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
+ {
+ for (count = 0U; count < 8U; count++)
+ {
+ SD_hs[(8U * loop) + count] = SDMMC_ReadFIFO(hsd->Instance);
+ }
+ loop ++;
+ }
+
+ if ((HAL_GetTick() - Timeout) >= SDMMC_DATATIMEOUT)
+ {
+ hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_SD_ERROR_TIMEOUT;
+ }
+ }
+
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+ {
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
+
+ return errorstate;
+ }
+ else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+ {
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
+
+ errorstate = SDMMC_ERROR_DATA_CRC_FAIL;
+
+ return errorstate;
+ }
+ else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
+ {
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
+
+ errorstate = SDMMC_ERROR_RX_OVERRUN;
+
+ return errorstate;
+ }
+ else
+ {
+ /* No error flag set */
+ }
+
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+ /* Test if the switch mode HS is ok */
+ if ((((uint8_t *)SD_hs)[13] & 2U) != 2U)
+ {
+ errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
+ }
+
+ }
+
+ return errorstate;
+}
+
+#if (USE_SD_TRANSCEIVER != 0U)
+/**
+ * @brief Switches the SD card to Ultra High Speed mode.
+ * This API must be used after "Transfer State"
+ * @note This operation should be followed by the configuration
+ * of PLL to have SDMMCCK clock between 50 and 120 MHz
+ * @param hsd: SD handle
+ * @retval SD Card error state
+ */
+static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd)
+{
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
+ SDMMC_DataInitTypeDef sdmmc_datainitstructure;
+ uint32_t SD_hs[16] = {0};
+ uint32_t count;
+ uint32_t loop = 0 ;
+ uint32_t Timeout = HAL_GetTick();
+
+ if (hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED)
+ {
+ /* Standard Speed Card <= 12.5Mhz */
+ return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+ }
+
+ if (hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED)
+ {
+ /* Initialize the Data control register */
+ hsd->Instance->DCTRL = 0;
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U);
+
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ return errorstate;
+ }
+
+ /* Configure the SD DPSM (Data Path State Machine) */
+ sdmmc_datainitstructure.DataTimeOut = SDMMC_DATATIMEOUT;
+ sdmmc_datainitstructure.DataLength = 64U;
+ sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ;
+ sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
+ sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE;
+
+ if (SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure) != HAL_OK)
+ {
+ return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR);
+ }
+
+ errorstate = SDMMC_CmdSwitch(hsd->Instance, SDMMC_SDR104_SWITCH_PATTERN);
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ return errorstate;
+ }
+
+ while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND |
+ SDMMC_FLAG_DATAEND))
+ {
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
+ {
+ for (count = 0U; count < 8U; count++)
+ {
+ SD_hs[(8U * loop) + count] = SDMMC_ReadFIFO(hsd->Instance);
+ }
+ loop ++;
+ }
+
+ if ((HAL_GetTick() - Timeout) >= SDMMC_DATATIMEOUT)
+ {
+ hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_SD_ERROR_TIMEOUT;
+ }
+ }
+
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+ {
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
+
+ return errorstate;
+ }
+ else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+ {
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
+
+ errorstate = SDMMC_ERROR_DATA_CRC_FAIL;
+
+ return errorstate;
+ }
+ else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
+ {
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
+
+ errorstate = SDMMC_ERROR_RX_OVERRUN;
+
+ return errorstate;
+ }
+ else
+ {
+ /* No error flag set */
+ }
+
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+ /* Test if the switch mode HS is ok */
+ if ((((uint8_t *)SD_hs)[13] & 2U) != 2U)
+ {
+ errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
+ }
+ else
+ {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+ hsd->DriveTransceiver_1_8V_Callback(SET);
+#else
+ HAL_SD_DriveTransceiver_1_8V_Callback(SET);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2)
+ /* Enable DelayBlock Peripheral */
+ /* SDMMC_FB_CLK tuned feedback clock selected as receive clock, for SDR104 */
+ MODIFY_REG(hsd->Instance->CLKCR, SDMMC_CLKCR_SELCLKRX, SDMMC_CLKCR_SELCLKRX_1);
+ LL_DLYB_Enable(SD_GET_DLYB_INSTANCE(hsd->Instance));
+#endif /* (DLYB_SDMMC1) || (DLYB_SDMMC2) */
+ }
+ }
+
+ return errorstate;
+}
+
+/**
+ * @brief Switches the SD card to Double Data Rate (DDR) mode.
+ * This API must be used after "Transfer State"
+ * @note This operation should be followed by the configuration
+ * of PLL to have SDMMCCK clock less than 50MHz
+ * @param hsd: SD handle
+ * @retval SD Card error state
+ */
+static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd)
+{
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
+ SDMMC_DataInitTypeDef sdmmc_datainitstructure;
+ uint32_t SD_hs[16] = {0};
+ uint32_t count;
+ uint32_t loop = 0 ;
+ uint32_t Timeout = HAL_GetTick();
+
+ if (hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED)
+ {
+ /* Standard Speed Card <= 12.5Mhz */
+ return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+ }
+
+ if (hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED)
+ {
+ /* Initialize the Data control register */
+ hsd->Instance->DCTRL = 0;
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U);
+
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ return errorstate;
+ }
+
+ /* Configure the SD DPSM (Data Path State Machine) */
+ sdmmc_datainitstructure.DataTimeOut = SDMMC_DATATIMEOUT;
+ sdmmc_datainitstructure.DataLength = 64U;
+ sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ;
+ sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
+ sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE;
+
+ if (SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure) != HAL_OK)
+ {
+ return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR);
+ }
+
+ errorstate = SDMMC_CmdSwitch(hsd->Instance, SDMMC_DDR50_SWITCH_PATTERN);
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ return errorstate;
+ }
+
+ while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND |
+ SDMMC_FLAG_DATAEND))
+ {
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
+ {
+ for (count = 0U; count < 8U; count++)
+ {
+ SD_hs[(8U * loop) + count] = SDMMC_ReadFIFO(hsd->Instance);
+ }
+ loop ++;
+ }
+
+ if ((HAL_GetTick() - Timeout) >= SDMMC_DATATIMEOUT)
+ {
+ hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_SD_ERROR_TIMEOUT;
+ }
+ }
+
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+ {
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
+
+ return errorstate;
+ }
+ else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+ {
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
+
+ errorstate = SDMMC_ERROR_DATA_CRC_FAIL;
+
+ return errorstate;
+ }
+ else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
+ {
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
+
+ errorstate = SDMMC_ERROR_RX_OVERRUN;
+
+ return errorstate;
+ }
+ else
+ {
+ /* No error flag set */
+ }
+
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+ /* Test if the switch mode is ok */
+ if ((((uint8_t *)SD_hs)[13] & 2U) != 2U)
+ {
+ errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
+ }
+ else
+ {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+ hsd->DriveTransceiver_1_8V_Callback(SET);
+#else
+ HAL_SD_DriveTransceiver_1_8V_Callback(SET);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2)
+ /* Enable DelayBlock Peripheral */
+ /* SDMMC_CKin feedback clock selected as receive clock, for DDR50 */
+ MODIFY_REG(hsd->Instance->CLKCR, SDMMC_CLKCR_SELCLKRX, SDMMC_CLKCR_SELCLKRX_0);
+ LL_DLYB_Enable(SD_GET_DLYB_INSTANCE(hsd->Instance));
+#endif /* (DLYB_SDMMC1) || (DLYB_SDMMC2) */
+ }
+ }
+
+ return errorstate;
+}
+
+#endif /* USE_SD_TRANSCEIVER */
+
+/**
+ * @brief Read DMA Linked list node Transfer completed callbacks
+ * @param hsd: SD handle
+ * @retval None
+ */
+__weak void HAL_SDEx_Read_DMALnkLstBufCpltCallback(SD_HandleTypeDef *hsd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SDEx_Read_DMALnkLstBufCpltCallback can be implemented in the user file
+ */
+}
+/**
+ * @brief Read DMA Linked list node Transfer completed callbacks
+ * @param hsd: SD handle
+ * @retval None
+ */
+__weak void HAL_SDEx_Write_DMALnkLstBufCpltCallback(SD_HandleTypeDef *hsd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SDEx_Write_DMALnkLstBufCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_SD_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sd_ex.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sd_ex.c
new file mode 100644
index 00000000..d017a799
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sd_ex.c
@@ -0,0 +1,394 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_sd_ex.c
+ * @author MCD Application Team
+ * @brief SD card Extended HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Secure Digital (SD) peripheral:
+ * + Extended features functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The SD Extension HAL driver can be used as follows:
+ (+) Configure Buffer0 and Buffer1 start address and Buffer size using HAL_SDEx_ConfigDMAMultiBuffer() function.
+ (+) Start Read and Write for multibuffer mode using HAL_SDEx_ReadBlocksDMAMultiBuffer()
+ and HAL_SDEx_WriteBlocksDMAMultiBuffer() functions.
+
+ @endverbatim
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SDEx SDEx
+ * @brief SD Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_SD_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SDEx_Exported_Functions
+ * @{
+ */
+
+
+/** @addtogroup SDEx_Exported_Functions_Group1
+ * @brief Linked List management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Linked List management functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the needed functions.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Build Linked List node.
+ * @param pNode: Pointer to new node to add.
+ * @param pNodeConf: Pointer to configuration parameters for new node to add.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDEx_DMALinkedList_BuildNode(SD_DMALinkNodeTypeDef *pNode, SD_DMALinkNodeConfTypeDef *pNodeConf)
+{
+
+ (void)SDMMC_DMALinkedList_BuildNode(pNode, pNodeConf);
+
+ return (HAL_OK);
+
+}
+
+/**
+ * @brief Insert new Linked List node.
+ * @param pLinkedList: Pointer to the linkedlist that contains transfer nodes
+ * @param pPrevNode: Pointer to previous node.
+ * @param pNewNode: Pointer to new node to insert.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDEx_DMALinkedList_InsertNode(SD_DMALinkedListTypeDef *pLinkedList,
+ SD_DMALinkNodeTypeDef *pPrevNode, SD_DMALinkNodeTypeDef *pNewNode)
+{
+
+ (void)SDMMC_DMALinkedList_InsertNode(pLinkedList, pPrevNode, pNewNode);
+
+ return (HAL_OK);
+
+}
+/**
+ * @brief Remove Linked List node.
+ * @param pLinkedList: Pointer to the linkedlist that contains transfer nodes
+ * @param pNode: Pointer to node to remove.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDEx_DMALinkedList_RemoveNode(SD_DMALinkedListTypeDef *pLinkedList, SD_DMALinkNodeTypeDef *pNode)
+{
+
+ if (SDMMC_DMALinkedList_RemoveNode(pLinkedList, pNode) != SDMMC_ERROR_NONE)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief Lock Linked List node.
+ * @param pNode: Pointer to node to remove.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDEx_DMALinkedList_LockNode(SD_DMALinkNodeTypeDef *pNode)
+{
+
+ if (SDMMC_DMALinkedList_LockNode(pNode) != SDMMC_ERROR_NONE)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief Unlock Linked List node.
+ * @param pNode: Pointer to node to remove.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDEx_DMALinkedList_UnlockNode(SD_DMALinkNodeTypeDef *pNode)
+{
+
+ if (SDMMC_DMALinkedList_UnlockNode(pNode) != SDMMC_ERROR_NONE)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief Enable Circular mode for DMA Linked List.
+ * @param pLinkedList: Pointer to the linkedlist that contains transfer nodes
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDEx_DMALinkedList_EnableCircularMode(SD_DMALinkedListTypeDef *pLinkedList)
+{
+
+ (void)SDMMC_DMALinkedList_EnableCircularMode(pLinkedList);
+
+ return HAL_OK;
+
+}
+/**
+ * @brief Disable Circular mode for DMA Linked List.
+ * @param pLinkedList: Pointer to the linkedlist that contains transfer nodes
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDEx_DMALinkedList_DisableCircularMode(SD_DMALinkedListTypeDef *pLinkedList)
+{
+
+ (void)SDMMC_DMALinkedList_DisableCircularMode(pLinkedList);
+
+ return HAL_OK;
+
+}
+
+
+/**
+ * @brief Reads block(s) from a specified address in a card. The received Data will be stored in linked list buffers.
+ * linked list should be prepared before call this function .
+ * @param hsd: SD handle
+ * @param pLinkedList: pointer to first linked list node
+ * @param BlockAdd: Block Address from where data is to be read
+ * @param NumberOfBlocks: Total number of blocks to read
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDEx_DMALinkedList_ReadBlocks(SD_HandleTypeDef *hsd, SDMMC_DMALinkedListTypeDef *pLinkedList,
+ uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+ SDMMC_DataInitTypeDef config;
+ uint32_t errorstate;
+ uint32_t DmaBase0_reg;
+ uint32_t DmaBase1_reg;
+ uint32_t add = BlockAdd;
+
+ if (hsd->State == HAL_SD_STATE_READY)
+ {
+ if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ hsd->Instance->IDMABASER = (uint32_t) pLinkedList->pHeadNode->IDMABASER;
+ hsd->Instance->IDMABSIZE = (uint32_t) pLinkedList->pHeadNode->IDMABSIZE;
+
+ hsd->Instance->IDMABAR = (uint32_t) pLinkedList->pHeadNode;
+ hsd->Instance->IDMALAR = (uint32_t) SDMMC_IDMALAR_ABR | SDMMC_IDMALAR_ULS | SDMMC_IDMALAR_ULA |
+ sizeof(SDMMC_DMALinkNodeTypeDef) ; /* Initial configuration */
+
+ DmaBase0_reg = hsd->Instance->IDMABASER;
+ DmaBase1_reg = hsd->Instance->IDMABAR;
+
+ if ((hsd->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U))
+ {
+ hsd->ErrorCode = HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ /* Initialize data control register */
+ hsd->Instance->DCTRL = 0;
+ /* Clear old Flags*/
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+ hsd->ErrorCode = HAL_SD_ERROR_NONE;
+ hsd->State = HAL_SD_STATE_BUSY;
+
+ if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ {
+ add *= 512U;
+ }
+
+ /* Configure the SD DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = BLOCKSIZE * NumberOfBlocks;
+ config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
+ config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDMMC_DPSM_DISABLE;
+ (void)SDMMC_ConfigData(hsd->Instance, &config);
+
+ hsd->Instance->DCTRL |= SDMMC_DCTRL_FIFORST;
+
+ __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
+
+ hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
+
+ /* Read Blocks in DMA mode */
+ hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
+
+ /* Read Multi Block command */
+ errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->ErrorCode |= errorstate;
+ return HAL_ERROR;
+ }
+
+ __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND |
+ SDMMC_IT_IDMABTC));
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+
+}
+
+/**
+ * @brief Write block(s) to a specified address in a card. The transferred Data are stored linked list nodes buffers .
+ * linked list should be prepared before call this function .
+ * @param hsd: SD handle
+ * @param pLinkedList: pointer to first linked list node
+ * @param BlockAdd: Block Address from where data is to be read
+ * @param NumberOfBlocks: Total number of blocks to read
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDEx_DMALinkedList_WriteBlocks(SD_HandleTypeDef *hsd, SDMMC_DMALinkedListTypeDef *pLinkedList,
+ uint32_t BlockAdd, uint32_t NumberOfBlocks)
+
+{
+ SDMMC_DataInitTypeDef config;
+ uint32_t errorstate;
+ uint32_t DmaBase0_reg;
+ uint32_t DmaBase1_reg;
+ uint32_t add = BlockAdd;
+
+ if (hsd->State == HAL_SD_STATE_READY)
+ {
+ if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ hsd->Instance->IDMABASER = (uint32_t) pLinkedList->pHeadNode->IDMABASER;
+ hsd->Instance->IDMABSIZE = (uint32_t) pLinkedList->pHeadNode->IDMABSIZE;
+
+ hsd->Instance->IDMABAR = (uint32_t) pLinkedList->pHeadNode;
+ hsd->Instance->IDMALAR = (uint32_t) SDMMC_IDMALAR_ABR | SDMMC_IDMALAR_ULS | SDMMC_IDMALAR_ULA |
+ sizeof(SDMMC_DMALinkNodeTypeDef) ; /* Initial configuration */
+
+ DmaBase0_reg = hsd->Instance->IDMABASER;
+ DmaBase1_reg = hsd->Instance->IDMABAR;
+
+ if ((hsd->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U))
+ {
+ hsd->ErrorCode = HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ /* Initialize data control register */
+ hsd->Instance->DCTRL = 0;
+
+ hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+ hsd->State = HAL_SD_STATE_BUSY;
+
+ if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ {
+ add *= 512U;
+ }
+
+ /* Configure the SD DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = BLOCKSIZE * NumberOfBlocks;
+ config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;
+ config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDMMC_DPSM_DISABLE;
+ (void)SDMMC_ConfigData(hsd->Instance, &config);
+
+ __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
+
+ hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
+
+ /* Write Blocks in DMA mode */
+ hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->ErrorCode |= errorstate;
+ return HAL_ERROR;
+ }
+
+ __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND |
+ SDMMC_IT_IDMABTC));
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_SD_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smartcard.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smartcard.c
new file mode 100644
index 00000000..e4f04575
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smartcard.c
@@ -0,0 +1,3249 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_smartcard.c
+ * @author MCD Application Team
+ * @brief SMARTCARD HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the SMARTCARD peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State and Error functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The SMARTCARD HAL driver can be used as follows:
+
+ (#) Declare a SMARTCARD_HandleTypeDef handle structure (eg. SMARTCARD_HandleTypeDef hsmartcard).
+ (#) Associate a USART to the SMARTCARD handle hsmartcard.
+ (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
+ (++) Enable the USARTx interface clock.
+ (++) USART pins configuration:
+ (+++) Enable the clock for the USART GPIOs.
+ (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
+ (++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
+ and HAL_SMARTCARD_Receive_IT() APIs):
+ (+++) Configure the USARTx interrupt priority.
+ (+++) Enable the NVIC USART IRQ handle.
+ (++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
+ and HAL_SMARTCARD_Receive_DMA() APIs):
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx channel.
+ (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete
+ interrupt on the DMA Tx/Rx channel.
+
+ (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
+ the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
+ error enabling or disabling in the hsmartcard handle Init structure.
+
+ (#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...)
+ in the hsmartcard handle AdvancedInit structure.
+
+ (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
+ (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customized HAL_SMARTCARD_MspInit() API.
+ [..]
+ (@) The specific SMARTCARD interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
+
+ [..]
+ [..] Three operation modes are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
+ (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Send an amount of data in non-blocking mode using HAL_SMARTCARD_Transmit_IT()
+ (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
+ (+) Receive an amount of data in non-blocking mode using HAL_SMARTCARD_Receive_IT()
+ (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
+ (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Send an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
+ (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
+ (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
+ (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
+ (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
+
+ *** SMARTCARD HAL driver macros list ***
+ ========================================
+ [..]
+ Below the list of most used macros in SMARTCARD HAL driver.
+
+ (+) __HAL_SMARTCARD_GET_FLAG : Check whether or not the specified SMARTCARD flag is set
+ (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
+ (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
+ (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
+ (+) __HAL_SMARTCARD_GET_IT_SOURCE: Check whether or not the specified SMARTCARD interrupt is enabled
+
+ [..]
+ (@) You can refer to the SMARTCARD HAL driver header file for more useful macros
+
+ ##### Callback registration #####
+ ==================================
+
+ [..]
+ The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ [..]
+ Use Function HAL_SMARTCARD_RegisterCallback() to register a user callback.
+ Function HAL_SMARTCARD_RegisterCallback() allows to register following callbacks:
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+ (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
+ (+) RxFifoFullCallback : Rx Fifo Full Callback.
+ (+) TxFifoEmptyCallback : Tx Fifo Empty Callback.
+ (+) MspInitCallback : SMARTCARD MspInit.
+ (+) MspDeInitCallback : SMARTCARD MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ [..]
+ Use function HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function.
+ HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+ (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
+ (+) RxFifoFullCallback : Rx Fifo Full Callback.
+ (+) TxFifoEmptyCallback : Tx Fifo Empty Callback.
+ (+) MspInitCallback : SMARTCARD MspInit.
+ (+) MspDeInitCallback : SMARTCARD MspDeInit.
+
+ [..]
+ By default, after the HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET
+ all callbacks are set to the corresponding weak (surcharged) functions:
+ examples HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are respectively
+ reset to the legacy weak (surcharged) functions in the HAL_SMARTCARD_Init()
+ and HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+ [..]
+ Callbacks can be registered/unregistered in HAL_SMARTCARD_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_SMARTCARD_STATE_READY or HAL_SMARTCARD_STATE_RESET state, thus registered (user)
+ MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using HAL_SMARTCARD_RegisterCallback() before calling HAL_SMARTCARD_DeInit()
+ or HAL_SMARTCARD_Init() function.
+
+ [..]
+ When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available
+ and weak (surcharged) callbacks are used.
+
+
+ @endverbatim
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SMARTCARD SMARTCARD
+ * @brief HAL SMARTCARD module driver
+ * @{
+ */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
+ * @{
+ */
+#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U /*!< SMARTCARD TX or RX enable acknowledge time-out value */
+
+#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
+ USART_CR1_RE | USART_CR1_OVER8| \
+ USART_CR1_FIFOEN)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
+
+#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \
+ USART_CR2_CPHA | USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */
+
+#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | \
+ USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */
+
+#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT | \
+ USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */
+
+#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */
+
+#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup SMARTCARD_Private_Functions
+ * @{
+ */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag,
+ FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
+static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_TxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_RxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
+ * @{
+ */
+
+/** @defgroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and Configuration functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USARTx
+ associated to the SmartCard.
+ (+) These parameters can be configured:
+ (++) Baud Rate
+ (++) Parity: parity should be enabled, frame Length is fixed to 8 bits plus parity
+ (++) Receiver/transmitter modes
+ (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)
+ (++) Prescaler value
+ (++) Guard bit time
+ (++) NACK enabling or disabling on transmission error
+
+ (+) The following advanced features can be configured as well:
+ (++) TX and/or RX pin level inversion
+ (++) data logical level inversion
+ (++) RX and TX pins swap
+ (++) RX overrun detection disabling
+ (++) DMA disabling on RX error
+ (++) MSB first on communication line
+ (++) Time out enabling (and if activated, timeout value)
+ (++) Block length
+ (++) Auto-retry counter
+ [..]
+ The HAL_SMARTCARD_Init() API follows the USART synchronous configuration procedures
+ (details for the procedures are available in reference manual).
+
+@endverbatim
+
+ The USART frame format is given in the following table:
+
+ Table 1. USART frame format.
+ +---------------------------------------------------------------+
+ | M1M0 bits | PCE bit | USART frame |
+ |-----------------------|---------------------------------------|
+ | 01 | 1 | | SB | 8 bit data | PB | STB | |
+ +---------------------------------------------------------------+
+
+
+ * @{
+ */
+
+/**
+ * @brief Initialize the SMARTCARD mode according to the specified
+ * parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Check the SMARTCARD handle allocation */
+ if (hsmartcard == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the USART associated to the SMARTCARD handle */
+ assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
+
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hsmartcard->Lock = HAL_UNLOCKED;
+
+#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
+ SMARTCARD_InitCallbacksToDefault(hsmartcard);
+
+ if (hsmartcard->MspInitCallback == NULL)
+ {
+ hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hsmartcard->MspInitCallback(hsmartcard);
+#else
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_SMARTCARD_MspInit(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+ }
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Disable the Peripheral to set smartcard mode */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* In SmartCard mode, the following bits must be kept cleared:
+ - LINEN in the USART_CR2 register,
+ - HDSEL and IREN bits in the USART_CR3 register.*/
+ CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_LINEN);
+ CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN));
+
+ /* set the USART in SMARTCARD mode */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_SCEN);
+
+ /* Set the SMARTCARD Communication parameters */
+ if (SMARTCARD_SetConfig(hsmartcard) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the SMARTCARD transmission completion indication */
+ SMARTCARD_TRANSMISSION_COMPLETION_SETTING(hsmartcard);
+
+ if (hsmartcard->AdvancedInit.AdvFeatureInit != SMARTCARD_ADVFEATURE_NO_INIT)
+ {
+ SMARTCARD_AdvFeatureConfig(hsmartcard);
+ }
+
+ /* Enable the Peripheral */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* TEACK and/or REACK to check before moving hsmartcard->gState and hsmartcard->RxState to Ready */
+ return (SMARTCARD_CheckIdleState(hsmartcard));
+}
+
+/**
+ * @brief DeInitialize the SMARTCARD peripheral.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Check the SMARTCARD handle allocation */
+ if (hsmartcard == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the USART/UART associated to the SMARTCARD handle */
+ assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ WRITE_REG(hsmartcard->Instance->CR1, 0x0U);
+ WRITE_REG(hsmartcard->Instance->CR2, 0x0U);
+ WRITE_REG(hsmartcard->Instance->CR3, 0x0U);
+ WRITE_REG(hsmartcard->Instance->RTOR, 0x0U);
+ WRITE_REG(hsmartcard->Instance->GTPR, 0x0U);
+
+ /* DeInit the low level hardware */
+#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
+ if (hsmartcard->MspDeInitCallback == NULL)
+ {
+ hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ hsmartcard->MspDeInitCallback(hsmartcard);
+#else
+ HAL_SMARTCARD_MspDeInit(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->gState = HAL_SMARTCARD_STATE_RESET;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_RESET;
+
+ /* Process Unlock */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the SMARTCARD MSP.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the SMARTCARD MSP.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_MspDeInit can be implemented in the user file
+ */
+}
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User SMARTCARD Callback
+ * To be used instead of the weak predefined callback
+ * @param hsmartcard smartcard handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
+ * @arg @ref HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
+ * @arg @ref HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
+ HAL_SMARTCARD_CallbackIDTypeDef CallbackID,
+ pSMARTCARD_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hsmartcard);
+
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+
+ case HAL_SMARTCARD_TX_COMPLETE_CB_ID :
+ hsmartcard->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_RX_COMPLETE_CB_ID :
+ hsmartcard->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_ERROR_CB_ID :
+ hsmartcard->ErrorCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID :
+ hsmartcard->AbortCpltCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID :
+ hsmartcard->AbortTransmitCpltCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID :
+ hsmartcard->AbortReceiveCpltCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_RX_FIFO_FULL_CB_ID :
+ hsmartcard->RxFifoFullCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID :
+ hsmartcard->TxFifoEmptyCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_MSPINIT_CB_ID :
+ hsmartcard->MspInitCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_MSPDEINIT_CB_ID :
+ hsmartcard->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hsmartcard->gState == HAL_SMARTCARD_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SMARTCARD_MSPINIT_CB_ID :
+ hsmartcard->MspInitCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_MSPDEINIT_CB_ID :
+ hsmartcard->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsmartcard);
+
+ return status;
+}
+
+/**
+ * @brief Unregister an SMARTCARD callback
+ * SMARTCARD callback is redirected to the weak predefined callback
+ * @param hsmartcard smartcard handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
+ * @arg @ref HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
+ * @arg @ref HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
+ HAL_SMARTCARD_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hsmartcard);
+
+ if (HAL_SMARTCARD_STATE_READY == hsmartcard->gState)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SMARTCARD_TX_COMPLETE_CB_ID :
+ hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ break;
+
+ case HAL_SMARTCARD_RX_COMPLETE_CB_ID :
+ hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ break;
+
+ case HAL_SMARTCARD_ERROR_CB_ID :
+ hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID :
+ hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ break;
+
+ case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID :
+ hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak
+ AbortTransmitCpltCallback*/
+ break;
+
+ case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID :
+ hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak
+ AbortReceiveCpltCallback */
+ break;
+
+ case HAL_SMARTCARD_RX_FIFO_FULL_CB_ID :
+ hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
+ break;
+
+ case HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID :
+ hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
+ break;
+
+ case HAL_SMARTCARD_MSPINIT_CB_ID :
+ hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; /* Legacy weak MspInitCallback */
+ break;
+
+ case HAL_SMARTCARD_MSPDEINIT_CB_ID :
+ hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; /* Legacy weak MspDeInitCallback */
+ break;
+
+ default :
+ /* Update the error code */
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_SMARTCARD_STATE_RESET == hsmartcard->gState)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SMARTCARD_MSPINIT_CB_ID :
+ hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit;
+ break;
+
+ case HAL_SMARTCARD_MSPDEINIT_CB_ID :
+ hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsmartcard);
+
+ return status;
+}
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions
+ * @brief SMARTCARD Transmit and Receive functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
+
+ [..]
+ Smartcard is a single wire half duplex communication protocol.
+ The Smartcard interface is designed to support asynchronous protocol Smartcards as
+ defined in the ISO 7816-3 standard. The USART should be configured as:
+ (+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
+ (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
+
+ [..]
+ (#) There are two modes of transfer:
+ (##) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (##) Non-Blocking mode: The communication is performed using Interrupts
+ or DMA, the relevant API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ (##) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
+ will be executed respectively at the end of the Transmit or Receive process
+ The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication
+ error is detected.
+
+ (#) Blocking mode APIs are :
+ (##) HAL_SMARTCARD_Transmit()
+ (##) HAL_SMARTCARD_Receive()
+
+ (#) Non Blocking mode APIs with Interrupt are :
+ (##) HAL_SMARTCARD_Transmit_IT()
+ (##) HAL_SMARTCARD_Receive_IT()
+ (##) HAL_SMARTCARD_IRQHandler()
+
+ (#) Non Blocking mode functions with DMA are :
+ (##) HAL_SMARTCARD_Transmit_DMA()
+ (##) HAL_SMARTCARD_Receive_DMA()
+
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (##) HAL_SMARTCARD_TxCpltCallback()
+ (##) HAL_SMARTCARD_RxCpltCallback()
+ (##) HAL_SMARTCARD_ErrorCallback()
+
+ [..]
+ (#) Non-Blocking mode transfers could be aborted using Abort API's :
+ (##) HAL_SMARTCARD_Abort()
+ (##) HAL_SMARTCARD_AbortTransmit()
+ (##) HAL_SMARTCARD_AbortReceive()
+ (##) HAL_SMARTCARD_Abort_IT()
+ (##) HAL_SMARTCARD_AbortTransmit_IT()
+ (##) HAL_SMARTCARD_AbortReceive_IT()
+
+ (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT),
+ a set of Abort Complete Callbacks are provided:
+ (##) HAL_SMARTCARD_AbortCpltCallback()
+ (##) HAL_SMARTCARD_AbortTransmitCpltCallback()
+ (##) HAL_SMARTCARD_AbortReceiveCpltCallback()
+
+ (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+ Errors are handled as follows :
+ (##) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ to be evaluated by user : this concerns Frame Error,
+ Parity Error or Noise Error in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer,
+ Error code is set to allow user to identify error type,
+ and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
+ If user wants to abort it, Abort services should be called by user.
+ (##) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ This concerns Frame Error in Interrupt mode transmission, Overrun Error in Interrupt
+ mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type,
+ and HAL_SMARTCARD_ErrorCallback() user callback is executed.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Send an amount of data in blocking mode.
+ * @note When FIFO mode is enabled, writing a data in the TDR register adds one
+ * data to the TXFIFO. Write operations to the TDR register are performed
+ * when TXFNF flag is set. From hardware perspective, TXFNF flag and
+ * TXE are mapped on the same bit-field.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be sent.
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout)
+{
+ uint32_t tickstart;
+ uint8_t *ptmpdata = pData;
+
+ /* Check that a Tx process is not already ongoing */
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ if ((ptmpdata == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ /* Disable the Peripheral first to update mode for TX master */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor
+ the bidirectional line to detect a NACK signal in case of parity error.
+ Therefore, the receiver block must be enabled as well (RE bit must be set). */
+ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ {
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+ }
+ /* Enable Tx */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
+
+ /* Enable the Peripheral */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* Perform a TX/RX FIFO Flush */
+ __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->TxXferSize = Size;
+ hsmartcard->TxXferCount = Size;
+
+ while (hsmartcard->TxXferCount > 0U)
+ {
+ hsmartcard->TxXferCount--;
+ if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ hsmartcard->Instance->TDR = (uint8_t)(*ptmpdata & 0xFFU);
+ ptmpdata++;
+ }
+ if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET,
+ tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable the Peripheral first to update mode */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ {
+ /* In case of TX only mode, if NACK is enabled, receiver block has been enabled
+ for Transmit phase. Disable this receiver block. */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+ }
+ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
+ || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ {
+ /* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */
+ __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
+ }
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* At end of Tx process, restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode.
+ * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
+ * is not empty. Read operations from the RDR register are performed when
+ * RXFNE flag is set. From hardware perspective, RXFNE flag and
+ * RXNE are mapped on the same bit-field.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be received.
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout)
+{
+ uint32_t tickstart;
+ uint8_t *ptmpdata = pData;
+
+ /* Check that a Rx process is not already ongoing */
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ {
+ if ((ptmpdata == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ hsmartcard->RxXferSize = Size;
+ hsmartcard->RxXferCount = Size;
+
+ /* Check the remain data to be received */
+ while (hsmartcard->RxXferCount > 0U)
+ {
+ hsmartcard->RxXferCount--;
+
+ if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ *ptmpdata = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FF);
+ ptmpdata++;
+ }
+
+ /* At end of Rx process, restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in interrupt mode.
+ * @note When FIFO mode is disabled, USART interrupt is generated whenever
+ * USART_TDR register is empty, i.e one interrupt per data to transmit.
+ * @note When FIFO mode is enabled, USART interrupt is generated whenever
+ * TXFIFO threshold reached. In that case the interrupt rate depends on
+ * TXFIFO threshold configuration.
+ * @note This function sets the hsmartcard->TxIsr function pointer according to
+ * the FIFO mode (data transmission processing depends on FIFO mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be sent.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Tx process is not already ongoing */
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
+
+ hsmartcard->pTxBuffPtr = pData;
+ hsmartcard->TxXferSize = Size;
+ hsmartcard->TxXferCount = Size;
+ hsmartcard->TxISR = NULL;
+
+ /* Disable the Peripheral first to update mode for TX master */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor
+ the bidirectional line to detect a NACK signal in case of parity error.
+ Therefore, the receiver block must be enabled as well (RE bit must be set). */
+ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ {
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+ }
+ /* Enable Tx */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
+
+ /* Enable the Peripheral */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* Perform a TX/RX FIFO Flush */
+ __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
+
+ /* Configure Tx interrupt processing */
+ if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_ENABLE)
+ {
+ /* Set the Tx ISR function pointer */
+ hsmartcard->TxISR = SMARTCARD_TxISR_FIFOEN;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Enable the SMARTCARD Error Interrupt: (Frame error) */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the TX FIFO threshold interrupt */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE);
+ }
+ else
+ {
+ /* Set the Tx ISR function pointer */
+ hsmartcard->TxISR = SMARTCARD_TxISR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Enable the SMARTCARD Error Interrupt: (Frame error) */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the SMARTCARD Transmit Data Register Empty Interrupt */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in interrupt mode.
+ * @note When FIFO mode is disabled, USART interrupt is generated whenever
+ * USART_RDR register can be read, i.e one interrupt per data to receive.
+ * @note When FIFO mode is enabled, USART interrupt is generated whenever
+ * RXFIFO threshold reached. In that case the interrupt rate depends on
+ * RXFIFO threshold configuration.
+ * @note This function sets the hsmartcard->RxIsr function pointer according to
+ * the FIFO mode (data reception processing depends on FIFO mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Rx process is not already ongoing */
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
+
+ hsmartcard->pRxBuffPtr = pData;
+ hsmartcard->RxXferSize = Size;
+ hsmartcard->RxXferCount = Size;
+
+ /* Configure Rx interrupt processing */
+ if ((hsmartcard->FifoMode == SMARTCARD_FIFOMODE_ENABLE) && (Size >= hsmartcard->NbRxDataToProcess))
+ {
+ /* Set the Rx ISR function pointer */
+ hsmartcard->RxISR = SMARTCARD_RxISR_FIFOEN;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Enable the SMARTCART Parity Error interrupt and RX FIFO Threshold interrupt */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTIE);
+ }
+ else
+ {
+ /* Set the Rx ISR function pointer */
+ hsmartcard->RxISR = SMARTCARD_RxISR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Enable the SMARTCARD Parity Error and Data Register not empty Interrupts */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+ }
+
+ /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in DMA mode.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be sent.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check that a Tx process is not already ongoing */
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->pTxBuffPtr = pData;
+ hsmartcard->TxXferSize = Size;
+ hsmartcard->TxXferCount = Size;
+
+ /* Disable the Peripheral first to update mode for TX master */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor
+ the bidirectional line to detect a NACK signal in case of parity error.
+ Therefore, the receiver block must be enabled as well (RE bit must be set). */
+ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ {
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+ }
+ /* Enable Tx */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
+
+ /* Enable the Peripheral */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* Perform a TX/RX FIFO Flush */
+ __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
+
+ /* Set the SMARTCARD DMA transfer complete callback */
+ hsmartcard->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
+
+ /* Set the SMARTCARD error callback */
+ hsmartcard->hdmatx->XferErrorCallback = SMARTCARD_DMAError;
+
+ /* Set the DMA abort callback */
+ hsmartcard->hdmatx->XferAbortCallback = NULL;
+
+ /* Check linked list mode */
+ if ((hsmartcard->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if ((hsmartcard->hdmatx->LinkedListQueue != NULL) && (hsmartcard->hdmatx->LinkedListQueue->Head != NULL))
+ {
+ /* Set DMA data size */
+ hsmartcard->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = Size;
+
+ /* Set DMA source address */
+ hsmartcard->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
+ (uint32_t)hsmartcard->pTxBuffPtr;
+
+ /* Set DMA destination address */
+ hsmartcard->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
+ (uint32_t)&hsmartcard->Instance->TDR;
+
+ /* Enable the SMARTCARD transmit DMA channel */
+ status = HAL_DMAEx_List_Start_IT(hsmartcard->hdmatx);
+ }
+ else
+ {
+ /* Update status */
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Enable the SMARTCARD transmit DMA channel */
+ status = HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr,
+ (uint32_t)&hsmartcard->Instance->TDR, Size);
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Clear the TC flag in the ICR register */
+ CLEAR_BIT(hsmartcard->Instance->ICR, USART_ICR_TCCF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Enable the UART Error Interrupt: (Frame error) */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the SMARTCARD associated USART CR3 register */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Set error code to DMA */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Restore hsmartcard->State to ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in DMA mode.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be received.
+ * @note The SMARTCARD-associated USART parity is enabled (PCE = 1),
+ * the received data contain the parity bit (MSB position).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check that a Rx process is not already ongoing */
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
+
+ hsmartcard->pRxBuffPtr = pData;
+ hsmartcard->RxXferSize = Size;
+
+ /* Set the SMARTCARD DMA transfer complete callback */
+ hsmartcard->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
+
+ /* Set the SMARTCARD DMA error callback */
+ hsmartcard->hdmarx->XferErrorCallback = SMARTCARD_DMAError;
+
+ /* Set the DMA abort callback */
+ hsmartcard->hdmarx->XferAbortCallback = NULL;
+
+ /* Check linked list mode */
+ if ((hsmartcard->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if ((hsmartcard->hdmarx->LinkedListQueue != NULL) && (hsmartcard->hdmarx->LinkedListQueue->Head != NULL))
+ {
+ /* Set DMA data size */
+ hsmartcard->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = Size;
+
+ /* Set DMA source address */
+ hsmartcard->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
+ (uint32_t)&hsmartcard->Instance->RDR;
+
+ /* Set DMA destination address */
+ hsmartcard->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
+ (uint32_t)hsmartcard->pRxBuffPtr;
+
+ /* Enable the SMARTCARD receive DMA channel */
+ status = HAL_DMAEx_List_Start_IT(hsmartcard->hdmarx);
+ }
+ else
+ {
+ /* Update status */
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Enable the DMA channel */
+ status = HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR,
+ (uint32_t)hsmartcard->pRxBuffPtr, Size);
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Enable the SMARTCARD Parity Error Interrupt */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
+
+ /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the SMARTCARD associated USART CR3 register */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Set error code to DMA */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Restore hsmartcard->State to ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Abort ongoing transfers (blocking mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SMARTCARD Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and
+ ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1,
+ (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE |
+ USART_CR1_EOBIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
+
+ /* Disable the SMARTCARD DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if (hsmartcard->hdmatx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hsmartcard->hdmatx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(hsmartcard->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hsmartcard->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Disable the SMARTCARD DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if (hsmartcard->hdmarx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hsmartcard->hdmarx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(hsmartcard->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hsmartcard->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Reset Tx and Rx transfer counters */
+ hsmartcard->TxXferCount = 0U;
+ hsmartcard->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
+ SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Reset Handle ErrorCode to No Error */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (blocking mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SMARTCARD Interrupts (Tx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable TCIE, TXEIE and TXFTIE interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE);
+
+ /* Check if a receive process is ongoing or not. If not disable ERR IT */
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ }
+
+ /* Disable the SMARTCARD DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if (hsmartcard->hdmatx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hsmartcard->hdmatx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(hsmartcard->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hsmartcard->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Reset Tx transfer counter */
+ hsmartcard->TxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
+
+ /* Restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (blocking mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SMARTCARD Interrupts (Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable RTOIE, EOBIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE |
+ USART_CR1_EOBIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+ /* Check if a Transmit process is ongoing or not. If not disable ERR IT */
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ }
+
+ /* Disable the SMARTCARD DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if (hsmartcard->hdmarx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hsmartcard->hdmarx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(hsmartcard->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hsmartcard->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Reset Rx transfer counter */
+ hsmartcard->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
+ SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (Interrupt mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SMARTCARD Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ uint32_t abortcplt = 1U;
+
+ /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and
+ ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1,
+ (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE |
+ USART_CR1_EOBIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
+
+ /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle,
+ DMA Abort complete callbacks should be initialised before any call
+ to DMA Abort functions */
+ /* DMA Tx Handle is valid */
+ if (hsmartcard->hdmatx != NULL)
+ {
+ /* Set DMA Abort Complete callback if SMARTCARD DMA Tx request if enabled.
+ Otherwise, set it to NULL */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxAbortCallback;
+ }
+ else
+ {
+ hsmartcard->hdmatx->XferAbortCallback = NULL;
+ }
+ }
+ /* DMA Rx Handle is valid */
+ if (hsmartcard->hdmarx != NULL)
+ {
+ /* Set DMA Abort Complete callback if SMARTCARD DMA Rx request if enabled.
+ Otherwise, set it to NULL */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ {
+ hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxAbortCallback;
+ }
+ else
+ {
+ hsmartcard->hdmarx->XferAbortCallback = NULL;
+ }
+ }
+
+ /* Disable the SMARTCARD DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable DMA Tx at UART level */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if (hsmartcard->hdmatx != NULL)
+ {
+ /* SMARTCARD Tx DMA Abort callback has already been initialised :
+ will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
+ {
+ hsmartcard->hdmatx->XferAbortCallback = NULL;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* Disable the SMARTCARD DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if (hsmartcard->hdmarx != NULL)
+ {
+ /* SMARTCARD Rx DMA Abort callback has already been initialised :
+ will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
+ {
+ hsmartcard->hdmarx->XferAbortCallback = NULL;
+ abortcplt = 1U;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+ if (abortcplt == 1U)
+ {
+ /* Reset Tx and Rx transfer counters */
+ hsmartcard->TxXferCount = 0U;
+ hsmartcard->RxXferCount = 0U;
+
+ /* Clear ISR function pointers */
+ hsmartcard->RxISR = NULL;
+ hsmartcard->TxISR = NULL;
+
+ /* Reset errorCode */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
+ SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ hsmartcard->AbortCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort complete callback */
+ HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (Interrupt mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SMARTCARD Interrupts (Tx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable TCIE, TXEIE and TXFTIE interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE);
+
+ /* Check if a receive process is ongoing or not. If not disable ERR IT */
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ }
+
+ /* Disable the SMARTCARD DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if (hsmartcard->hdmatx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback :
+ will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+ hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxOnlyAbortCallback;
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
+ {
+ /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
+ hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ hsmartcard->TxXferCount = 0U;
+
+ /* Clear TxISR function pointers */
+ hsmartcard->TxISR = NULL;
+
+ /* Restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ hsmartcard->AbortTransmitCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
+ HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ hsmartcard->TxXferCount = 0U;
+
+ /* Clear TxISR function pointers */
+ hsmartcard->TxISR = NULL;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
+
+ /* Restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ hsmartcard->AbortTransmitCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
+ HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (Interrupt mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SMARTCARD Interrupts (Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable RTOIE, EOBIE, RXNE, PE, RXFT and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE |
+ USART_CR1_EOBIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+ /* Check if a Transmit process is ongoing or not. If not disable ERR IT */
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ }
+
+ /* Disable the SMARTCARD DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if (hsmartcard->hdmarx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback :
+ will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+ hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxOnlyAbortCallback;
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
+ {
+ /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
+ hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ hsmartcard->RxXferCount = 0U;
+
+ /* Clear RxISR function pointer */
+ hsmartcard->RxISR = NULL;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
+ SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ hsmartcard->AbortReceiveCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
+ HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ hsmartcard->RxXferCount = 0U;
+
+ /* Clear RxISR function pointer */
+ hsmartcard->RxISR = NULL;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
+ SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ hsmartcard->AbortReceiveCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
+ HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle SMARTCARD interrupt requests.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ uint32_t isrflags = READ_REG(hsmartcard->Instance->ISR);
+ uint32_t cr1its = READ_REG(hsmartcard->Instance->CR1);
+ uint32_t cr3its = READ_REG(hsmartcard->Instance->CR3);
+ uint32_t errorflags;
+ uint32_t errorcode;
+
+ /* If no error occurs */
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
+ if (errorflags == 0U)
+ {
+ /* SMARTCARD in mode Receiver ---------------------------------------------------*/
+ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
+ && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+ || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+ {
+ if (hsmartcard->RxISR != NULL)
+ {
+ hsmartcard->RxISR(hsmartcard);
+ }
+ return;
+ }
+ }
+
+ /* If some errors occur */
+ if ((errorflags != 0U)
+ && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
+ || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U))))
+ {
+ /* SMARTCARD parity error interrupt occurred -------------------------------------*/
+ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+ {
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_PEF);
+
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
+ }
+
+ /* SMARTCARD frame error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_FEF);
+
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
+ }
+
+ /* SMARTCARD noise error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_NEF);
+
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
+ }
+
+ /* SMARTCARD Over-Run interrupt occurred -----------------------------------------*/
+ if (((isrflags & USART_ISR_ORE) != 0U)
+ && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+ || ((cr3its & USART_CR3_RXFTIE) != 0U)
+ || ((cr3its & USART_CR3_EIE) != 0U)))
+ {
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_OREF);
+
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
+ }
+
+ /* SMARTCARD receiver timeout interrupt occurred -----------------------------------------*/
+ if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
+ {
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_RTOF);
+
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_RTO;
+ }
+
+ /* Call SMARTCARD Error Call back function if need be --------------------------*/
+ if (hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
+ {
+ /* SMARTCARD in mode Receiver ---------------------------------------------------*/
+ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
+ && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+ || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+ {
+ if (hsmartcard->RxISR != NULL)
+ {
+ hsmartcard->RxISR(hsmartcard);
+ }
+ }
+
+ /* If Error is to be considered as blocking :
+ - Receiver Timeout error in Reception
+ - Overrun error in Reception
+ - any error occurs in DMA mode reception
+ */
+ errorcode = hsmartcard->ErrorCode;
+ if ((HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ || ((errorcode & (HAL_SMARTCARD_ERROR_RTO | HAL_SMARTCARD_ERROR_ORE)) != 0U))
+ {
+ /* Blocking error : transfer is aborted
+ Set the SMARTCARD state ready to be able to start again the process,
+ Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+ SMARTCARD_EndRxTransfer(hsmartcard);
+
+ /* Disable the SMARTCARD DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the SMARTCARD DMA Rx channel */
+ if (hsmartcard->hdmarx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback :
+ will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
+ hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
+ {
+ /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
+ hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
+ }
+ }
+ else
+ {
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hsmartcard->ErrorCallback(hsmartcard);
+#else
+ /* Call legacy weak user error callback */
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ }
+ }
+ else
+ {
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hsmartcard->ErrorCallback(hsmartcard);
+#else
+ /* Call legacy weak user error callback */
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ }
+ }
+ /* other error type to be considered as blocking :
+ - Frame error in Transmission
+ */
+ else if ((hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
+ && ((errorcode & HAL_SMARTCARD_ERROR_FE) != 0U))
+ {
+ /* Blocking error : transfer is aborted
+ Set the SMARTCARD state ready to be able to start again the process,
+ Disable Tx Interrupts, and disable Tx DMA request, if ongoing */
+ SMARTCARD_EndTxTransfer(hsmartcard);
+
+ /* Disable the SMARTCARD DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the SMARTCARD DMA Tx channel */
+ if (hsmartcard->hdmatx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback :
+ will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
+ hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
+ {
+ /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
+ hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
+ }
+ }
+ else
+ {
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hsmartcard->ErrorCallback(hsmartcard);
+#else
+ /* Call legacy weak user error callback */
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ }
+ }
+ else
+ {
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hsmartcard->ErrorCallback(hsmartcard);
+#else
+ /* Call legacy weak user error callback */
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ }
+ }
+ else
+ {
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hsmartcard->ErrorCallback(hsmartcard);
+#else
+ /* Call legacy weak user error callback */
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ }
+ }
+ return;
+
+ } /* End if some error occurs */
+
+ /* SMARTCARD in mode Receiver, end of block interruption ------------------------*/
+ if (((isrflags & USART_ISR_EOBF) != 0U) && ((cr1its & USART_CR1_EOBIE) != 0U))
+ {
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+ __HAL_UNLOCK(hsmartcard);
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx complete callback */
+ hsmartcard->RxCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Rx complete callback */
+ HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ /* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information
+ to be available during HAL_SMARTCARD_RxCpltCallback() processing */
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_EOBF);
+ return;
+ }
+
+ /* SMARTCARD in mode Transmitter ------------------------------------------------*/
+ if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
+ && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
+ || ((cr3its & USART_CR3_TXFTIE) != 0U)))
+ {
+ if (hsmartcard->TxISR != NULL)
+ {
+ hsmartcard->TxISR(hsmartcard);
+ }
+ return;
+ }
+
+ /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
+ if (__HAL_SMARTCARD_GET_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET)
+ {
+ if (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET)
+ {
+ SMARTCARD_EndTransmit_IT(hsmartcard);
+ return;
+ }
+ }
+
+ /* SMARTCARD TX Fifo Empty occurred ----------------------------------------------*/
+ if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
+ {
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Fifo Empty Callback */
+ hsmartcard->TxFifoEmptyCallback(hsmartcard);
+#else
+ /* Call legacy weak Tx Fifo Empty Callback */
+ HAL_SMARTCARDEx_TxFifoEmptyCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ return;
+ }
+
+ /* SMARTCARD RX Fifo Full occurred ----------------------------------------------*/
+ if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
+ {
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx Fifo Full Callback */
+ hsmartcard->RxFifoFullCallback(hsmartcard);
+#else
+ /* Call legacy weak Rx Fifo Full Callback */
+ HAL_SMARTCARDEx_RxFifoFullCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ return;
+ }
+}
+
+/**
+ * @brief Tx Transfer completed callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief SMARTCARD error callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_ErrorCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief SMARTCARD Abort Complete callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_AbortCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief SMARTCARD Abort Complete callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_AbortTransmitCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief SMARTCARD Abort Receive Complete callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_AbortReceiveCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Exported_Functions_Group4 Peripheral State and Errors functions
+ * @brief SMARTCARD State and Errors functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Errors functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to return the State of SmartCard
+ handle and also return Peripheral Errors occurred during communication process
+ (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state
+ of the SMARTCARD peripheral.
+ (+) HAL_SMARTCARD_GetError() checks in run-time errors that could occur during
+ communication.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the SMARTCARD handle state.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval SMARTCARD handle state
+ */
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Return SMARTCARD handle state */
+ uint32_t temp1;
+ uint32_t temp2;
+ temp1 = (uint32_t)hsmartcard->gState;
+ temp2 = (uint32_t)hsmartcard->RxState;
+
+ return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2);
+}
+
+/**
+ * @brief Return the SMARTCARD handle error code.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval SMARTCARD handle Error Code
+ */
+uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ return hsmartcard->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
+ * @{
+ */
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Initialize the callbacks to their default values.
+ * @param hsmartcard SMARTCARD handle.
+ * @retval none
+ */
+void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Init the SMARTCARD Callback settings */
+ hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
+ hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak
+ AbortTransmitCpltCallback */
+ hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak
+ AbortReceiveCpltCallback */
+ hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak
+ RxFifoFullCallback */
+ hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak
+ TxFifoEmptyCallback */
+
+}
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+
+/**
+ * @brief Configure the SMARTCARD associated USART peripheral.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ uint32_t tmpreg;
+ SMARTCARD_ClockSourceTypeDef clocksource;
+ HAL_StatusTypeDef ret = HAL_OK;
+ static const uint16_t SMARTCARDPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
+ uint32_t pclk;
+
+ /* Check the parameters */
+ assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
+ assert_param(IS_SMARTCARD_BAUDRATE(hsmartcard->Init.BaudRate));
+ assert_param(IS_SMARTCARD_WORD_LENGTH(hsmartcard->Init.WordLength));
+ assert_param(IS_SMARTCARD_STOPBITS(hsmartcard->Init.StopBits));
+ assert_param(IS_SMARTCARD_PARITY(hsmartcard->Init.Parity));
+ assert_param(IS_SMARTCARD_MODE(hsmartcard->Init.Mode));
+ assert_param(IS_SMARTCARD_POLARITY(hsmartcard->Init.CLKPolarity));
+ assert_param(IS_SMARTCARD_PHASE(hsmartcard->Init.CLKPhase));
+ assert_param(IS_SMARTCARD_LASTBIT(hsmartcard->Init.CLKLastBit));
+ assert_param(IS_SMARTCARD_ONE_BIT_SAMPLE(hsmartcard->Init.OneBitSampling));
+ assert_param(IS_SMARTCARD_NACK(hsmartcard->Init.NACKEnable));
+ assert_param(IS_SMARTCARD_TIMEOUT(hsmartcard->Init.TimeOutEnable));
+ assert_param(IS_SMARTCARD_AUTORETRY_COUNT(hsmartcard->Init.AutoRetryCount));
+ assert_param(IS_SMARTCARD_CLOCKPRESCALER(hsmartcard->Init.ClockPrescaler));
+
+ /*-------------------------- USART CR1 Configuration -----------------------*/
+ /* In SmartCard mode, M and PCE are forced to 1 (8 bits + parity).
+ * Oversampling is forced to 16 (OVER8 = 0).
+ * Configure the Parity and Mode:
+ * set PS bit according to hsmartcard->Init.Parity value
+ * set TE and RE bits according to hsmartcard->Init.Mode value */
+ tmpreg = (((uint32_t)hsmartcard->Init.Parity) | ((uint32_t)hsmartcard->Init.Mode) |
+ ((uint32_t)hsmartcard->Init.WordLength));
+ MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+
+ /*-------------------------- USART CR2 Configuration -----------------------*/
+ tmpreg = hsmartcard->Init.StopBits;
+ /* Synchronous mode is activated by default */
+ tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity;
+ tmpreg |= (uint32_t) hsmartcard->Init.CLKPhase | hsmartcard->Init.CLKLastBit;
+ tmpreg |= (uint32_t) hsmartcard->Init.TimeOutEnable;
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg);
+
+ /*-------------------------- USART CR3 Configuration -----------------------*/
+ /* Configure
+ * - one-bit sampling method versus three samples' majority rule
+ * according to hsmartcard->Init.OneBitSampling
+ * - NACK transmission in case of parity error according
+ * to hsmartcard->Init.NACKEnable
+ * - autoretry counter according to hsmartcard->Init.AutoRetryCount */
+
+ tmpreg = (uint32_t) hsmartcard->Init.OneBitSampling | hsmartcard->Init.NACKEnable;
+ tmpreg |= ((uint32_t)hsmartcard->Init.AutoRetryCount << USART_CR3_SCARCNT_Pos);
+ MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_FIELDS, tmpreg);
+
+ /*--------------------- SMARTCARD clock PRESC Configuration ----------------*/
+ /* Configure
+ * - SMARTCARD Clock Prescaler: set PRESCALER according to hsmartcard->Init.ClockPrescaler value */
+ MODIFY_REG(hsmartcard->Instance->PRESC, USART_PRESC_PRESCALER, hsmartcard->Init.ClockPrescaler);
+
+ /*-------------------------- USART GTPR Configuration ----------------------*/
+ tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << USART_GTPR_GT_Pos));
+ MODIFY_REG(hsmartcard->Instance->GTPR, (uint16_t)(USART_GTPR_GT | USART_GTPR_PSC), (uint16_t)tmpreg);
+
+ /*-------------------------- USART RTOR Configuration ----------------------*/
+ tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << USART_RTOR_BLEN_Pos);
+ if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE)
+ {
+ assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
+ tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue;
+ }
+ MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO | USART_RTOR_BLEN), tmpreg);
+
+ /*-------------------------- USART BRR Configuration -----------------------*/
+ SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource);
+ tmpreg = 0U;
+ switch (clocksource)
+ {
+ case SMARTCARD_CLOCKSOURCE_PCLK1:
+ pclk = HAL_RCC_GetPCLK1Freq();
+ tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ break;
+ case SMARTCARD_CLOCKSOURCE_PCLK2:
+ pclk = HAL_RCC_GetPCLK2Freq();
+ tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ break;
+ case SMARTCARD_CLOCKSOURCE_HSI:
+ tmpreg = (uint16_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ break;
+ case SMARTCARD_CLOCKSOURCE_SYSCLK:
+ pclk = HAL_RCC_GetSysClockFreq();
+ tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ break;
+ case SMARTCARD_CLOCKSOURCE_LSE:
+ tmpreg = (uint16_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ break;
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+
+ /* USARTDIV must be greater than or equal to 0d16 */
+ if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX))
+ {
+ hsmartcard->Instance->BRR = tmpreg;
+ }
+ else
+ {
+ ret = HAL_ERROR;
+ }
+
+ /* Initialize the number of data to process during RX/TX ISR execution */
+ hsmartcard->NbTxDataToProcess = 1U;
+ hsmartcard->NbRxDataToProcess = 1U;
+
+ /* Clear ISR function pointers */
+ hsmartcard->RxISR = NULL;
+ hsmartcard->TxISR = NULL;
+
+ return ret;
+}
+
+
+/**
+ * @brief Configure the SMARTCARD associated USART peripheral advanced features.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Check whether the set of advanced features to configure is properly set */
+ assert_param(IS_SMARTCARD_ADVFEATURE_INIT(hsmartcard->AdvancedInit.AdvFeatureInit));
+
+ /* if required, configure TX pin active level inversion */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXINVERT_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_TXINV(hsmartcard->AdvancedInit.TxPinLevelInvert));
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_TXINV, hsmartcard->AdvancedInit.TxPinLevelInvert);
+ }
+
+ /* if required, configure RX pin active level inversion */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXINVERT_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_RXINV(hsmartcard->AdvancedInit.RxPinLevelInvert));
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_RXINV, hsmartcard->AdvancedInit.RxPinLevelInvert);
+ }
+
+ /* if required, configure data inversion */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DATAINVERT_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_DATAINV(hsmartcard->AdvancedInit.DataInvert));
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_DATAINV, hsmartcard->AdvancedInit.DataInvert);
+ }
+
+ /* if required, configure RX/TX pins swap */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_SWAP_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_SWAP(hsmartcard->AdvancedInit.Swap));
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_SWAP, hsmartcard->AdvancedInit.Swap);
+ }
+
+ /* if required, configure RX overrun detection disabling */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT))
+ {
+ assert_param(IS_SMARTCARD_OVERRUN(hsmartcard->AdvancedInit.OverrunDisable));
+ MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_OVRDIS, hsmartcard->AdvancedInit.OverrunDisable);
+ }
+
+ /* if required, configure DMA disabling on reception error */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(hsmartcard->AdvancedInit.DMADisableonRxError));
+ MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_DDRE, hsmartcard->AdvancedInit.DMADisableonRxError);
+ }
+
+ /* if required, configure MSB first on communication line */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_MSBFIRST(hsmartcard->AdvancedInit.MSBFirst));
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_MSBFIRST, hsmartcard->AdvancedInit.MSBFirst);
+ }
+
+}
+
+/**
+ * @brief Check the SMARTCARD Idle State.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ uint32_t tickstart;
+
+ /* Initialize the SMARTCARD ErrorCode */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ /* Check if the Transmitter is enabled */
+ if ((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ {
+ /* Wait until TEACK flag is set */
+ if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart,
+ SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Check if the Receiver is enabled */
+ if ((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+ {
+ /* Wait until REACK flag is set */
+ if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, tickstart,
+ SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Initialize the SMARTCARD states */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle SMARTCARD Communication Timeout.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param Flag Specifies the SMARTCARD flag to check.
+ * @param Status The new Flag status (SET or RESET).
+ * @param Tickstart Tick start value
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag,
+ FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
+{
+ /* Wait until flag is set */
+ while ((__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) ? SET : RESET) == Status)
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
+ interrupts for the interrupt process */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+
+/**
+ * @brief End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable TXEIE, TCIE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* At end of Tx process, restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+}
+
+
+/**
+ * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* At end of Rx process, restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+}
+
+
+/**
+ * @brief DMA SMARTCARD transmit process complete callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
+ hsmartcard->TxXferCount = 0U;
+
+ /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+ in the SMARTCARD associated USART CR3 register */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ /* Enable the SMARTCARD Transmit Complete Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
+}
+
+/**
+ * @brief DMA SMARTCARD receive process complete callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
+ hsmartcard->RxXferCount = 0U;
+
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+ in the SMARTCARD associated USART CR3 register */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ /* At end of Rx process, restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx complete callback */
+ hsmartcard->RxCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Rx complete callback */
+ HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+}
+
+/**
+ * @brief DMA SMARTCARD communication error callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
+
+ /* Stop SMARTCARD DMA Tx request if ongoing */
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
+ {
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ hsmartcard->TxXferCount = 0U;
+ SMARTCARD_EndTxTransfer(hsmartcard);
+ }
+ }
+
+ /* Stop SMARTCARD DMA Rx request if ongoing */
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
+ {
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ {
+ hsmartcard->RxXferCount = 0U;
+ SMARTCARD_EndRxTransfer(hsmartcard);
+ }
+ }
+
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_DMA;
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hsmartcard->ErrorCallback(hsmartcard);
+#else
+ /* Call legacy weak user error callback */
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+}
+
+/**
+ * @brief DMA SMARTCARD communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
+ hsmartcard->RxXferCount = 0U;
+ hsmartcard->TxXferCount = 0U;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hsmartcard->ErrorCallback(hsmartcard);
+#else
+ /* Call legacy weak user error callback */
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+}
+
+/**
+ * @brief DMA SMARTCARD Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
+
+ hsmartcard->hdmatx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if (hsmartcard->hdmarx != NULL)
+ {
+ if (hsmartcard->hdmarx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ hsmartcard->TxXferCount = 0U;
+ hsmartcard->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
+ SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ hsmartcard->AbortCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort complete callback */
+ HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+}
+
+
+/**
+ * @brief DMA SMARTCARD Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
+
+ hsmartcard->hdmarx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if (hsmartcard->hdmatx != NULL)
+ {
+ if (hsmartcard->hdmatx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ hsmartcard->TxXferCount = 0U;
+ hsmartcard->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
+ SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ hsmartcard->AbortCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort complete callback */
+ HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+}
+
+
+/**
+ * @brief DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to
+ * HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer)
+ * (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+ * and leads to user Tx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
+
+ hsmartcard->TxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
+
+ /* Restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ hsmartcard->AbortTransmitCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
+ HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+}
+
+/**
+ * @brief DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to
+ * HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer)
+ * (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+ * and leads to user Rx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
+
+ hsmartcard->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
+ SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ hsmartcard->AbortReceiveCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
+ HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+}
+
+/**
+ * @brief Send an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
+ * and when the FIFO mode is disabled.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Check that a Tx process is ongoing */
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
+ {
+ if (hsmartcard->TxXferCount == 0U)
+ {
+ /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+
+ /* Enable the SMARTCARD Transmit Complete Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
+ }
+ else
+ {
+ hsmartcard->Instance->TDR = (uint8_t)(*hsmartcard->pTxBuffPtr & 0xFFU);
+ hsmartcard->pTxBuffPtr++;
+ hsmartcard->TxXferCount--;
+ }
+ }
+}
+
+/**
+ * @brief Send an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
+ * and when the FIFO mode is enabled.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+static void SMARTCARD_TxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ uint16_t nb_tx_data;
+
+ /* Check that a Tx process is ongoing */
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
+ {
+ for (nb_tx_data = hsmartcard->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
+ {
+ if (hsmartcard->TxXferCount == 0U)
+ {
+ /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+
+ /* Enable the SMARTCARD Transmit Complete Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
+ }
+ else if (READ_BIT(hsmartcard->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
+ {
+ hsmartcard->Instance->TDR = (uint8_t)(*hsmartcard->pTxBuffPtr & 0xFFU);
+ hsmartcard->pTxBuffPtr++;
+ hsmartcard->TxXferCount--;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ }
+}
+
+/**
+ * @brief Wrap up transmission in non-blocking mode.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable the SMARTCARD Transmit Complete Interrupt */
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
+
+ /* Check if a receive process is ongoing or not. If not disable ERR IT */
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ }
+
+ /* Disable the Peripheral first to update mode */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ {
+ /* In case of TX only mode, if NACK is enabled, receiver block has been enabled
+ for Transmit phase. Disable this receiver block. */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+ }
+ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
+ || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ {
+ /* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */
+ __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
+ }
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* Tx process is ended, restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* Clear TxISR function pointer */
+ hsmartcard->TxISR = NULL;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx complete callback */
+ hsmartcard->TxCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Tx complete callback */
+ HAL_SMARTCARD_TxCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_SMARTCARD_Receive_IT()
+ * and when the FIFO mode is disabled.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Check that a Rx process is ongoing */
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
+ {
+ *hsmartcard->pRxBuffPtr = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF);
+ hsmartcard->pRxBuffPtr++;
+
+ hsmartcard->RxXferCount--;
+ if (hsmartcard->RxXferCount == 0U)
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+
+ /* Check if a transmit process is ongoing or not. If not disable ERR IT */
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ }
+
+ /* Disable the SMARTCARD Parity Error Interrupt */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
+
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Clear RxISR function pointer */
+ hsmartcard->RxISR = NULL;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx complete callback */
+ hsmartcard->RxCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Rx complete callback */
+ HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ }
+ }
+ else
+ {
+ /* Clear RXNE interrupt flag */
+ __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST);
+ }
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_SMARTCARD_Receive_IT()
+ * and when the FIFO mode is enabled.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+static void SMARTCARD_RxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ uint16_t nb_rx_data;
+ uint16_t rxdatacount;
+
+ /* Check that a Rx process is ongoing */
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
+ {
+ for (nb_rx_data = hsmartcard->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)
+ {
+ *hsmartcard->pRxBuffPtr = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF);
+ hsmartcard->pRxBuffPtr++;
+
+ hsmartcard->RxXferCount--;
+ if (hsmartcard->RxXferCount == 0U)
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+
+ /* Check if a transmit process is ongoing or not. If not disable ERR IT */
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ }
+
+ /* Disable the SMARTCARD Parity Error Interrupt */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
+
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Clear RxISR function pointer */
+ hsmartcard->RxISR = NULL;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx complete callback */
+ hsmartcard->RxCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Rx complete callback */
+ HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ }
+ }
+
+ /* When remaining number of bytes to receive is less than the RX FIFO
+ threshold, next incoming frames are processed as if FIFO mode was
+ disabled (i.e. one interrupt per received frame).
+ */
+ rxdatacount = hsmartcard->RxXferCount;
+ if (((rxdatacount != 0U)) && (rxdatacount < hsmartcard->NbRxDataToProcess))
+ {
+ /* Disable the UART RXFT interrupt*/
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTIE);
+
+ /* Update the RxISR function pointer */
+ hsmartcard->RxISR = SMARTCARD_RxISR;
+
+ /* Enable the UART Data Register Not Empty interrupt */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+ }
+ }
+ else
+ {
+ /* Clear RXNE interrupt flag */
+ __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST);
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smartcard_ex.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smartcard_ex.c
new file mode 100644
index 00000000..a9ad00d4
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smartcard_ex.c
@@ -0,0 +1,494 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_smartcard_ex.c
+ * @author MCD Application Team
+ * @brief SMARTCARD HAL module driver.
+ * This file provides extended firmware functions to manage the following
+ * functionalities of the SmartCard.
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ =============================================================================
+ ##### SMARTCARD peripheral extended features #####
+ =============================================================================
+ [..]
+ The Extended SMARTCARD HAL driver can be used as follows:
+
+ (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(),
+ then program SMARTCARD advanced features if required (TX/RX pins swap, TimeOut,
+ auto-retry counter,...) in the hsmartcard AdvancedInit structure.
+
+ (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
+
+ -@- When SMARTCARD operates in FIFO mode, FIFO mode must be enabled prior
+ starting RX/TX transfers. Also RX/TX FIFO thresholds must be
+ configured prior starting RX/TX transfers.
+
+ @endverbatim
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SMARTCARDEx SMARTCARDEx
+ * @brief SMARTCARD Extended HAL module driver
+ * @{
+ */
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup SMARTCARDEx_Private_Constants SMARTCARD Extended Private Constants
+ * @{
+ */
+/* UART RX FIFO depth */
+#define RX_FIFO_DEPTH 8U
+
+/* UART TX FIFO depth */
+#define TX_FIFO_DEPTH 8U
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard);
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SMARTCARDEx_Exported_Functions SMARTCARD Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup SMARTCARDEx_Exported_Functions_Group1 Extended Peripheral Control functions
+ * @brief Extended control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the SMARTCARD.
+ (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly
+ (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly
+ (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature
+ (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature
+
+@endverbatim
+ * @{
+ */
+
+/** @brief Update on the fly the SMARTCARD block length in RTOR register.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param BlockLength SMARTCARD block length (8-bit long at most)
+ * @retval None
+ */
+void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
+{
+ MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << USART_RTOR_BLEN_Pos));
+}
+
+/** @brief Update on the fly the receiver timeout value in RTOR register.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param TimeOutValue receiver timeout value in number of baud blocks. The timeout
+ * value must be less or equal to 0x0FFFFFFFF.
+ * @retval None
+ */
+void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
+{
+ assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
+ MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_RTO, TimeOutValue);
+}
+
+/** @brief Enable the SMARTCARD receiver timeout feature.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Set the USART RTOEN bit */
+ SET_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/** @brief Disable the SMARTCARD receiver timeout feature.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Clear the USART RTOEN bit */
+ CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARDEx_Exported_Functions_Group2 Extended Peripheral IO operation functions
+ * @brief SMARTCARD Transmit and Receive functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of FIFO mode related callback functions.
+
+ (#) TX/RX Fifos Callbacks:
+ (++) HAL_SMARTCARDEx_RxFifoFullCallback()
+ (++) HAL_SMARTCARDEx_TxFifoEmptyCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief SMARTCARD RX Fifo full callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARDEx_RxFifoFullCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARDEx_RxFifoFullCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief SMARTCARD TX Fifo empty callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARDEx_TxFifoEmptyCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARDEx_TxFifoEmptyCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARDEx_Exported_Functions_Group3 Extended Peripheral FIFO Control functions
+ * @brief SMARTCARD control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral FIFO Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the SMARTCARD
+ FIFO feature.
+ (+) HAL_SMARTCARDEx_EnableFifoMode() API enables the FIFO mode
+ (+) HAL_SMARTCARDEx_DisableFifoMode() API disables the FIFO mode
+ (+) HAL_SMARTCARDEx_SetTxFifoThreshold() API sets the TX FIFO threshold
+ (+) HAL_SMARTCARDEx_SetRxFifoThreshold() API sets the RX FIFO threshold
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable the FIFO mode.
+ * @param hsmartcard SMARTCARD handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ uint32_t tmpcr1;
+
+ /* Check parameters */
+ assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance));
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Save actual SMARTCARD configuration */
+ tmpcr1 = READ_REG(hsmartcard->Instance->CR1);
+
+ /* Disable SMARTCARD */
+ __HAL_SMARTCARD_DISABLE(hsmartcard);
+
+ /* Enable FIFO mode */
+ SET_BIT(tmpcr1, USART_CR1_FIFOEN);
+ hsmartcard->FifoMode = SMARTCARD_FIFOMODE_ENABLE;
+
+ /* Restore SMARTCARD configuration */
+ WRITE_REG(hsmartcard->Instance->CR1, tmpcr1);
+
+ /* Determine the number of data to process during RX/TX ISR execution */
+ SMARTCARDEx_SetNbDataToProcess(hsmartcard);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the FIFO mode.
+ * @param hsmartcard SMARTCARD handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ uint32_t tmpcr1;
+
+ /* Check parameters */
+ assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance));
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Save actual SMARTCARD configuration */
+ tmpcr1 = READ_REG(hsmartcard->Instance->CR1);
+
+ /* Disable SMARTCARD */
+ __HAL_SMARTCARD_DISABLE(hsmartcard);
+
+ /* Enable FIFO mode */
+ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
+ hsmartcard->FifoMode = SMARTCARD_FIFOMODE_DISABLE;
+
+ /* Restore SMARTCARD configuration */
+ WRITE_REG(hsmartcard->Instance->CR1, tmpcr1);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the TXFIFO threshold.
+ * @param hsmartcard SMARTCARD handle.
+ * @param Threshold TX FIFO threshold value
+ * This parameter can be one of the following values:
+ * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_8
+ * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_4
+ * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_2
+ * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_3_4
+ * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_7_8
+ * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_8_8
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
+{
+ uint32_t tmpcr1;
+
+ /* Check parameters */
+ assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance));
+ assert_param(IS_SMARTCARD_TXFIFO_THRESHOLD(Threshold));
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Save actual SMARTCARD configuration */
+ tmpcr1 = READ_REG(hsmartcard->Instance->CR1);
+
+ /* Disable SMARTCARD */
+ __HAL_SMARTCARD_DISABLE(hsmartcard);
+
+ /* Update TX threshold configuration */
+ MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
+
+ /* Determine the number of data to process during RX/TX ISR execution */
+ SMARTCARDEx_SetNbDataToProcess(hsmartcard);
+
+ /* Restore SMARTCARD configuration */
+ MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_UE, tmpcr1);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the RXFIFO threshold.
+ * @param hsmartcard SMARTCARD handle.
+ * @param Threshold RX FIFO threshold value
+ * This parameter can be one of the following values:
+ * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_8
+ * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_4
+ * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_2
+ * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_3_4
+ * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_7_8
+ * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_8_8
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
+{
+ uint32_t tmpcr1;
+
+ /* Check parameters */
+ assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance));
+ assert_param(IS_SMARTCARD_RXFIFO_THRESHOLD(Threshold));
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Save actual SMARTCARD configuration */
+ tmpcr1 = READ_REG(hsmartcard->Instance->CR1);
+
+ /* Disable SMARTCARD */
+ __HAL_SMARTCARD_DISABLE(hsmartcard);
+
+ /* Update RX threshold configuration */
+ MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
+
+ /* Determine the number of data to process during RX/TX ISR execution */
+ SMARTCARDEx_SetNbDataToProcess(hsmartcard);
+
+ /* Restore SMARTCARD configuration */
+ MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_UE, tmpcr1);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARDEx_Private_Functions SMARTCARD Extended Private Functions
+ * @{
+ */
+
+/**
+ * @brief Calculate the number of data to process in RX/TX ISR.
+ * @note The RX FIFO depth and the TX FIFO depth is extracted from
+ * the USART configuration registers.
+ * @param hsmartcard SMARTCARD handle.
+ * @retval None
+ */
+static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ uint8_t rx_fifo_depth;
+ uint8_t tx_fifo_depth;
+ uint8_t rx_fifo_threshold;
+ uint8_t tx_fifo_threshold;
+ /* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */
+ static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
+ static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
+
+ if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_DISABLE)
+ {
+ hsmartcard->NbTxDataToProcess = 1U;
+ hsmartcard->NbRxDataToProcess = 1U;
+ }
+ else
+ {
+ rx_fifo_depth = RX_FIFO_DEPTH;
+ tx_fifo_depth = TX_FIFO_DEPTH;
+ rx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
+ tx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
+ hsmartcard->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / \
+ (uint16_t)denominator[tx_fifo_threshold];
+ hsmartcard->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / \
+ (uint16_t)denominator[rx_fifo_threshold];
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smbus.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smbus.c
new file mode 100644
index 00000000..5f334d8f
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smbus.c
@@ -0,0 +1,2744 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_smbus.c
+ * @author MCD Application Team
+ * @brief SMBUS HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the System Management Bus (SMBus) peripheral,
+ * based on I2C principles of operation :
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State and Errors functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The SMBUS HAL driver can be used as follows:
+
+ (#) Declare a SMBUS_HandleTypeDef handle structure, for example:
+ SMBUS_HandleTypeDef hsmbus;
+
+ (#)Initialize the SMBUS low level resources by implementing the @ref HAL_SMBUS_MspInit() API:
+ (##) Enable the SMBUSx interface clock
+ (##) SMBUS pins configuration
+ (+++) Enable the clock for the SMBUS GPIOs
+ (+++) Configure SMBUS pins as alternate function open-drain
+ (##) NVIC configuration if you need to use interrupt process
+ (+++) Configure the SMBUSx interrupt priority
+ (+++) Enable the NVIC SMBUS IRQ Channel
+
+ (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing mode,
+ Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode,
+ Peripheral mode and Packet Error Check mode in the hsmbus Init structure.
+
+ (#) Initialize the SMBUS registers by calling the @ref HAL_SMBUS_Init() API:
+ (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customized @ref HAL_SMBUS_MspInit(&hsmbus) API.
+
+ (#) To check if target device is ready for communication, use the function @ref HAL_SMBUS_IsDeviceReady()
+
+ (#) For SMBUS IO operations, only one mode of operations is available within this driver
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode
+ using @ref HAL_SMBUS_Master_Transmit_IT()
+ (++) At transmission end of transfer @ref HAL_SMBUS_MasterTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_SMBUS_MasterTxCpltCallback()
+ (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode
+ using @ref HAL_SMBUS_Master_Receive_IT()
+ (++) At reception end of transfer @ref HAL_SMBUS_MasterRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_SMBUS_MasterRxCpltCallback()
+ (+) Abort a master/host SMBUS process communication with Interrupt using @ref HAL_SMBUS_Master_Abort_IT()
+ (++) The associated previous transfer callback is called at the end of abort process
+ (++) mean @ref HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit
+ (++) mean @ref HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive
+ (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode
+ using @ref HAL_SMBUS_EnableListen_IT() @ref HAL_SMBUS_DisableListen_IT()
+ (++) When address slave/device SMBUS match, @ref HAL_SMBUS_AddrCallback() is executed and user can
+ add his own code to check the Address Match Code and the transmission direction
+ request by master/host (Write/Read).
+ (++) At Listen mode end @ref HAL_SMBUS_ListenCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_SMBUS_ListenCpltCallback()
+ (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode
+ using @ref HAL_SMBUS_Slave_Transmit_IT()
+ (++) At transmission end of transfer @ref HAL_SMBUS_SlaveTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_SMBUS_SlaveTxCpltCallback()
+ (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode
+ using @ref HAL_SMBUS_Slave_Receive_IT()
+ (++) At reception end of transfer @ref HAL_SMBUS_SlaveRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_SMBUS_SlaveRxCpltCallback()
+ (+) Enable/Disable the SMBUS alert mode using @ref HAL_SMBUS_EnableAlert_IT() @ref HAL_SMBUS_DisableAlert_IT()
+ (++) When SMBUS Alert is generated @ref HAL_SMBUS_ErrorCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback()
+ to check the Alert Error Code using function @ref HAL_SMBUS_GetError()
+ (+) Get HAL state machine or error values using @ref HAL_SMBUS_GetState() or @ref HAL_SMBUS_GetError()
+ (+) In case of transfer Error, @ref HAL_SMBUS_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback()
+ to check the Error Code using function @ref HAL_SMBUS_GetError()
+
+ *** SMBUS HAL driver macros list ***
+ ==================================
+ [..]
+ Below the list of most used macros in SMBUS HAL driver.
+
+ (+) @ref __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral
+ (+) @ref __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral
+ (+) @ref __HAL_SMBUS_GET_FLAG: Check whether the specified SMBUS flag is set or not
+ (+) @ref __HAL_SMBUS_CLEAR_FLAG: Clear the specified SMBUS pending flag
+ (+) @ref __HAL_SMBUS_ENABLE_IT: Enable the specified SMBUS interrupt
+ (+) @ref __HAL_SMBUS_DISABLE_IT: Disable the specified SMBUS interrupt
+
+ *** Callback registration ***
+ =============================================
+ [..]
+ The compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions @ref HAL_SMBUS_RegisterCallback() or @ref HAL_SMBUS_RegisterAddrCallback()
+ to register an interrupt callback.
+ [..]
+ Function @ref HAL_SMBUS_RegisterCallback() allows to register following callbacks:
+ (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+ (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+ (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
+ (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
+ (+) ListenCpltCallback : callback for end of listen mode.
+ (+) ErrorCallback : callback for error detection.
+ (+) MspInitCallback : callback for Msp Init.
+ (+) MspDeInitCallback : callback for Msp DeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+ [..]
+ For specific callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_RegisterAddrCallback.
+ [..]
+ Use function @ref HAL_SMBUS_UnRegisterCallback to reset a callback to the default
+ weak function.
+ @ref HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+ (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+ (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
+ (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
+ (+) ListenCpltCallback : callback for end of listen mode.
+ (+) ErrorCallback : callback for error detection.
+ (+) MspInitCallback : callback for Msp Init.
+ (+) MspDeInitCallback : callback for Msp DeInit.
+ [..]
+ For callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_UnRegisterAddrCallback.
+ [..]
+ By default, after the @ref HAL_SMBUS_Init() and when the state is @ref HAL_I2C_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples @ref HAL_SMBUS_MasterTxCpltCallback(), @ref HAL_SMBUS_MasterRxCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak functions in the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ If MspInit or MspDeInit are not null, the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+ [..]
+ Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
+ Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ Then, the user first registers the MspInit/MspDeInit user callbacks
+ using @ref HAL_SMBUS_RegisterCallback() before calling @ref HAL_SMBUS_DeInit()
+ or @ref HAL_SMBUS_Init() function.
+ [..]
+ When the compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
+ [..]
+ (@) You can refer to the SMBUS HAL driver header file for more useful macros
+
+ @endverbatim
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SMBUS SMBUS
+ * @brief SMBUS HAL module driver
+ * @{
+ */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SMBUS_Private_Define SMBUS Private Constants
+ * @{
+ */
+#define TIMING_CLEAR_MASK (0xF0FFFFFFUL) /*!< SMBUS TIMING clear register Mask */
+#define HAL_TIMEOUT_ADDR (10000U) /*!< 10 s */
+#define HAL_TIMEOUT_BUSY (25U) /*!< 25 ms */
+#define HAL_TIMEOUT_DIR (25U) /*!< 25 ms */
+#define HAL_TIMEOUT_RXNE (25U) /*!< 25 ms */
+#define HAL_TIMEOUT_STOPF (25U) /*!< 25 ms */
+#define HAL_TIMEOUT_TC (25U) /*!< 25 ms */
+#define HAL_TIMEOUT_TCR (25U) /*!< 25 ms */
+#define HAL_TIMEOUT_TXIS (25U) /*!< 25 ms */
+#define MAX_NBYTE_SIZE 255U
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
+ * @{
+ */
+static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status,
+ uint32_t Timeout);
+
+static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
+static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
+static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags);
+static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags);
+
+static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus);
+
+static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus);
+
+static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
+ uint32_t Request);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SMBUS_Exported_Functions SMBUS Exported Functions
+ * @{
+ */
+
+/** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ deinitialize the SMBUSx peripheral:
+
+ (+) User must Implement HAL_SMBUS_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, IT and NVIC ).
+
+ (+) Call the function HAL_SMBUS_Init() to configure the selected device with
+ the selected configuration:
+ (++) Clock Timing
+ (++) Bus Timeout
+ (++) Analog Filer mode
+ (++) Own Address 1
+ (++) Addressing mode (Master, Slave)
+ (++) Dual Addressing mode
+ (++) Own Address 2
+ (++) Own Address 2 Mask
+ (++) General call mode
+ (++) Nostretch mode
+ (++) Packet Error Check mode
+ (++) Peripheral mode
+
+
+ (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration
+ of the selected SMBUSx peripheral.
+
+ (+) Enable/Disable Analog/Digital filters with HAL_SMBUS_ConfigAnalogFilter() and
+ HAL_SMBUS_ConfigDigitalFilter().
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the SMBUS according to the specified parameters
+ * in the SMBUS_InitTypeDef and initialize the associated handle.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Check the SMBUS handle allocation */
+ if (hsmbus == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+ assert_param(IS_SMBUS_ANALOG_FILTER(hsmbus->Init.AnalogFilter));
+ assert_param(IS_SMBUS_OWN_ADDRESS1(hsmbus->Init.OwnAddress1));
+ assert_param(IS_SMBUS_ADDRESSING_MODE(hsmbus->Init.AddressingMode));
+ assert_param(IS_SMBUS_DUAL_ADDRESS(hsmbus->Init.DualAddressMode));
+ assert_param(IS_SMBUS_OWN_ADDRESS2(hsmbus->Init.OwnAddress2));
+ assert_param(IS_SMBUS_OWN_ADDRESS2_MASK(hsmbus->Init.OwnAddress2Masks));
+ assert_param(IS_SMBUS_GENERAL_CALL(hsmbus->Init.GeneralCallMode));
+ assert_param(IS_SMBUS_NO_STRETCH(hsmbus->Init.NoStretchMode));
+ assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode));
+ assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode));
+
+ if (hsmbus->State == HAL_SMBUS_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hsmbus->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->MasterTxCpltCallback = HAL_SMBUS_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+ hsmbus->MasterRxCpltCallback = HAL_SMBUS_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+ hsmbus->SlaveTxCpltCallback = HAL_SMBUS_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
+ hsmbus->SlaveRxCpltCallback = HAL_SMBUS_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
+ hsmbus->ListenCpltCallback = HAL_SMBUS_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
+ hsmbus->ErrorCallback = HAL_SMBUS_ErrorCallback; /* Legacy weak ErrorCallback */
+ hsmbus->AddrCallback = HAL_SMBUS_AddrCallback; /* Legacy weak AddrCallback */
+
+ if (hsmbus->MspInitCallback == NULL)
+ {
+ hsmbus->MspInitCallback = HAL_SMBUS_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ hsmbus->MspInitCallback(hsmbus);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ HAL_SMBUS_MspInit(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+ /* Disable the selected SMBUS peripheral */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+ /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/
+ /* Configure SMBUSx: Frequency range */
+ hsmbus->Instance->TIMINGR = hsmbus->Init.Timing & TIMING_CLEAR_MASK;
+
+ /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/
+ /* Configure SMBUSx: Bus Timeout */
+ hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TIMOUTEN;
+ hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TEXTEN;
+ hsmbus->Instance->TIMEOUTR = hsmbus->Init.SMBusTimeout;
+
+ /*---------------------------- SMBUSx OAR1 Configuration -----------------------*/
+ /* Configure SMBUSx: Own Address1 and ack own address1 mode */
+ hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
+
+ if (hsmbus->Init.OwnAddress1 != 0UL)
+ {
+ if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT)
+ {
+ hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1);
+ }
+ }
+
+ /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */
+ /* AUTOEND and NACK bit will be manage during Transfer process */
+ hsmbus->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
+
+ /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/
+ /* Configure SMBUSx: Dual mode and Own Address2 */
+ hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | \
+ (hsmbus->Init.OwnAddress2Masks << 8U));
+
+ /*---------------------------- SMBUSx CR1 Configuration ------------------------*/
+ /* Configure SMBUSx: Generalcall and NoStretch mode */
+ hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | \
+ hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter);
+
+ /* Enable Slave Byte Control only in case of Packet Error Check is enabled
+ and SMBUS Peripheral is set in Slave mode */
+ if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE) && \
+ ((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
+ (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)))
+ {
+ hsmbus->Instance->CR1 |= I2C_CR1_SBC;
+ }
+
+ /* Enable the selected SMBUS peripheral */
+ __HAL_SMBUS_ENABLE(hsmbus);
+
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+ hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitialize the SMBUS peripheral.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Check the SMBUS handle allocation */
+ if (hsmbus == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+ /* Disable the SMBUS Peripheral Clock */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ if (hsmbus->MspDeInitCallback == NULL)
+ {
+ hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ hsmbus->MspDeInitCallback(hsmbus);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_SMBUS_MspDeInit(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+ hsmbus->PreviousState = HAL_SMBUS_STATE_RESET;
+ hsmbus->State = HAL_SMBUS_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the SMBUS MSP.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+__weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the SMBUS MSP.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+__weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Configure Analog noise filter.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param AnalogFilter This parameter can be one of the following values:
+ * @arg @ref SMBUS_ANALOGFILTER_ENABLE
+ * @arg @ref SMBUS_ANALOGFILTER_DISABLE
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter)
+{
+ /* Check the parameters */
+ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+ assert_param(IS_SMBUS_ANALOG_FILTER(AnalogFilter));
+
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+ /* Disable the selected SMBUS peripheral */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+ /* Reset ANOFF bit */
+ hsmbus->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
+
+ /* Set analog filter bit*/
+ hsmbus->Instance->CR1 |= AnalogFilter;
+
+ __HAL_SMBUS_ENABLE(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Configure Digital noise filter.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter)
+{
+ uint32_t tmpreg;
+
+ /* Check the parameters */
+ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+ assert_param(IS_SMBUS_DIGITAL_FILTER(DigitalFilter));
+
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+ /* Disable the selected SMBUS peripheral */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+ /* Get the old register value */
+ tmpreg = hsmbus->Instance->CR1;
+
+ /* Reset I2C DNF bits [11:8] */
+ tmpreg &= ~(I2C_CR1_DNF);
+
+ /* Set I2Cx DNF coefficient */
+ tmpreg |= DigitalFilter << I2C_CR1_DNF_Pos;
+
+ /* Store the new register value */
+ hsmbus->Instance->CR1 = tmpreg;
+
+ __HAL_SMBUS_ENABLE(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User SMBUS Callback
+ * To be used instead of the weak predefined callback
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+ * @arg @ref HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+ * @arg @ref HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+ * @arg @ref HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+ * @arg @ref HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+ * @arg @ref HAL_SMBUS_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID,
+ pSMBUS_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hsmbus);
+
+ if (HAL_SMBUS_STATE_READY == hsmbus->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID :
+ hsmbus->MasterTxCpltCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID :
+ hsmbus->MasterRxCpltCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID :
+ hsmbus->SlaveTxCpltCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID :
+ hsmbus->SlaveRxCpltCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_LISTEN_COMPLETE_CB_ID :
+ hsmbus->ListenCpltCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_ERROR_CB_ID :
+ hsmbus->ErrorCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_MSPINIT_CB_ID :
+ hsmbus->MspInitCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_MSPDEINIT_CB_ID :
+ hsmbus->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_SMBUS_STATE_RESET == hsmbus->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SMBUS_MSPINIT_CB_ID :
+ hsmbus->MspInitCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_MSPDEINIT_CB_ID :
+ hsmbus->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsmbus);
+ return status;
+}
+
+/**
+ * @brief Unregister an SMBUS Callback
+ * SMBUS callback is redirected to the weak predefined callback
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+ * @arg @ref HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+ * @arg @ref HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+ * @arg @ref HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+ * @arg @ref HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+ * @arg @ref HAL_SMBUS_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hsmbus);
+
+ if (HAL_SMBUS_STATE_READY == hsmbus->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID :
+ hsmbus->MasterTxCpltCallback = HAL_SMBUS_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+ break;
+
+ case HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID :
+ hsmbus->MasterRxCpltCallback = HAL_SMBUS_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+ break;
+
+ case HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID :
+ hsmbus->SlaveTxCpltCallback = HAL_SMBUS_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
+ break;
+
+ case HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID :
+ hsmbus->SlaveRxCpltCallback = HAL_SMBUS_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
+ break;
+
+ case HAL_SMBUS_LISTEN_COMPLETE_CB_ID :
+ hsmbus->ListenCpltCallback = HAL_SMBUS_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
+ break;
+
+ case HAL_SMBUS_ERROR_CB_ID :
+ hsmbus->ErrorCallback = HAL_SMBUS_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_SMBUS_MSPINIT_CB_ID :
+ hsmbus->MspInitCallback = HAL_SMBUS_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_SMBUS_MSPDEINIT_CB_ID :
+ hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_SMBUS_STATE_RESET == hsmbus->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SMBUS_MSPINIT_CB_ID :
+ hsmbus->MspInitCallback = HAL_SMBUS_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_SMBUS_MSPDEINIT_CB_ID :
+ hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsmbus);
+ return status;
+}
+
+/**
+ * @brief Register the Slave Address Match SMBUS Callback
+ * To be used instead of the weak HAL_SMBUS_AddrCallback() predefined callback
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param pCallback pointer to the Address Match Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hsmbus);
+
+ if (HAL_SMBUS_STATE_READY == hsmbus->State)
+ {
+ hsmbus->AddrCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsmbus);
+ return status;
+}
+
+/**
+ * @brief UnRegister the Slave Address Match SMBUS Callback
+ * Info Ready SMBUS Callback is redirected to the weak HAL_SMBUS_AddrCallback() predefined callback
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hsmbus);
+
+ if (HAL_SMBUS_STATE_READY == hsmbus->State)
+ {
+ hsmbus->AddrCallback = HAL_SMBUS_AddrCallback; /* Legacy weak AddrCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsmbus);
+ return status;
+}
+
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the SMBUS data
+ transfers.
+
+ (#) Blocking mode function to check if device is ready for usage is :
+ (++) HAL_SMBUS_IsDeviceReady()
+
+ (#) There is only one mode of transfer:
+ (++) Non-Blocking mode : The communication is performed using Interrupts.
+ These functions return the status of the transfer startup.
+ The end of the data processing will be indicated through the
+ dedicated SMBUS IRQ when using Interrupt mode.
+
+ (#) Non-Blocking mode functions with Interrupt are :
+ (++) HAL_SMBUS_Master_Transmit_IT()
+ (++) HAL_SMBUS_Master_Receive_IT()
+ (++) HAL_SMBUS_Slave_Transmit_IT()
+ (++) HAL_SMBUS_Slave_Receive_IT()
+ (++) HAL_SMBUS_EnableListen_IT() or alias HAL_SMBUS_EnableListen_IT()
+ (++) HAL_SMBUS_DisableListen_IT()
+ (++) HAL_SMBUS_EnableAlert_IT()
+ (++) HAL_SMBUS_DisableAlert_IT()
+
+ (#) A set of Transfer Complete Callbacks are provided in non-Blocking mode:
+ (++) HAL_SMBUS_MasterTxCpltCallback()
+ (++) HAL_SMBUS_MasterRxCpltCallback()
+ (++) HAL_SMBUS_SlaveTxCpltCallback()
+ (++) HAL_SMBUS_SlaveRxCpltCallback()
+ (++) HAL_SMBUS_AddrCallback()
+ (++) HAL_SMBUS_ListenCpltCallback()
+ (++) HAL_SMBUS_ErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions)
+{
+ uint32_t tmp;
+
+ /* Check the parameters */
+ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+ /* Prepare transfer parameters */
+ hsmbus->pBuffPtr = pData;
+ hsmbus->XferCount = Size;
+ hsmbus->XferOptions = XferOptions;
+
+ /* In case of Quick command, remove autoend mode */
+ /* Manage the stop generation by software */
+ if (hsmbus->pBuffPtr == NULL)
+ {
+ hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
+ }
+
+ if (Size > MAX_NBYTE_SIZE)
+ {
+ hsmbus->XferSize = MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hsmbus->XferSize = Size;
+ }
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
+ if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
+ {
+ /* Check if the Autonomous mode is enabled */
+ if ((hsmbus->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN)
+ {
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | \
+ (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_NO_START_WRITE);
+ }
+ else
+ {
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | \
+ (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE);
+ }
+ }
+ else
+ {
+ /* If transfer direction not change, do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+
+ /* Store current volatile XferOptions, misra rule */
+ tmp = hsmbus->XferOptions;
+
+ if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && \
+ (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
+ {
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ }
+ /* Else transfer direction change, so generate Restart with new transfer direction */
+ else
+ {
+ /* Convert OTHER_xxx XferOptions if any */
+ SMBUS_ConvertOtherXferOptions(hsmbus);
+
+ /* Handle Transfer */
+ /* Check if the Autonomous mode is enabled */
+ if ((hsmbus->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN)
+ {
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
+ SMBUS_GENERATE_NO_START_WRITE);
+ }
+ else
+ {
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
+ SMBUS_GENERATE_START_WRITE);
+ }
+ }
+
+ /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */
+ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
+ if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
+ {
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Note : The SMBUS interrupts must be enabled after unlocking current process
+ to avoid the risk of SMBUS interrupt handle execution before current
+ process unlock */
+ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions)
+{
+ uint32_t tmp;
+
+ /* Check the parameters */
+ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hsmbus->pBuffPtr = pData;
+ hsmbus->XferCount = Size;
+ hsmbus->XferOptions = XferOptions;
+
+ /* In case of Quick command, remove autoend mode */
+ /* Manage the stop generation by software */
+ if (hsmbus->pBuffPtr == NULL)
+ {
+ hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
+ }
+
+ if (Size > MAX_NBYTE_SIZE)
+ {
+ hsmbus->XferSize = MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hsmbus->XferSize = Size;
+ }
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
+ if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
+ {
+ /* Check if the Autonomous mode is enabled */
+ if ((hsmbus->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN)
+ {
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | \
+ (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_NO_START_READ);
+ }
+ else
+ {
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | \
+ (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ);
+ }
+ }
+ else
+ {
+ /* If transfer direction not change, do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+
+ /* Store current volatile XferOptions, Misra rule */
+ tmp = hsmbus->XferOptions;
+
+ if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && \
+ (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
+ {
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ }
+ /* Else transfer direction change, so generate Restart with new transfer direction */
+ else
+ {
+ /* Convert OTHER_xxx XferOptions if any */
+ SMBUS_ConvertOtherXferOptions(hsmbus);
+
+ /* Handle Transfer */
+ /* Check if the Autonomous mode is enabled */
+ if ((hsmbus->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN)
+ {
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
+ SMBUS_GENERATE_NO_START_READ);
+ }
+ else
+ {
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
+ SMBUS_GENERATE_START_READ);
+ }
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Note : The SMBUS interrupts must be enabled after unlocking current process
+ to avoid the risk of SMBUS interrupt handle execution before current
+ process unlock */
+ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Abort a master/host SMBUS process communication with Interrupt.
+ * @note This abort can be called only if state is ready
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
+{
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ /* Keep the same state as previous */
+ /* to perform as well the call of the corresponding end of transfer callback */
+ if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ {
+ hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
+ }
+ else if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ {
+ hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
+ }
+ else
+ {
+ /* Wrong usage of abort function */
+ /* This function should be used only in case of abort monitored by master device */
+ return HAL_ERROR;
+ }
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+
+ /* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */
+ /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
+ SMBUS_TransferConfig(hsmbus, DevAddress, 1, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Note : The SMBUS interrupts must be enabled after unlocking current process
+ to avoid the risk of SMBUS interrupt handle execution before current
+ process unlock */
+ if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ {
+ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
+ }
+ else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ {
+ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions)
+{
+ /* Check the parameters */
+ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
+ {
+ if ((pData == NULL) || (Size == 0UL))
+ {
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_TX);
+
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = (HAL_SMBUS_STATE_SLAVE_BUSY_TX | HAL_SMBUS_STATE_LISTEN);
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+
+ /* Set SBC bit to manage Acknowledge at each bit */
+ hsmbus->Instance->CR1 |= I2C_CR1_SBC;
+
+ /* Enable Address Acknowledge */
+ hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Prepare transfer parameters */
+ hsmbus->pBuffPtr = pData;
+ hsmbus->XferCount = Size;
+ hsmbus->XferOptions = XferOptions;
+
+ /* Convert OTHER_xxx XferOptions if any */
+ SMBUS_ConvertOtherXferOptions(hsmbus);
+
+ if (Size > MAX_NBYTE_SIZE)
+ {
+ hsmbus->XferSize = MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hsmbus->XferSize = Size;
+ }
+
+ /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
+ if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
+ {
+ SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize,
+ SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
+ }
+ else
+ {
+ /* Set NBYTE to transmit */
+ SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+
+ /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
+ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
+ if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
+ {
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ }
+
+ /* Clear ADDR flag after prepare the transfer parameters */
+ /* This action will generate an acknowledge to the HOST */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Note : The SMBUS interrupts must be enabled after unlocking current process
+ to avoid the risk of SMBUS interrupt handle execution before current
+ process unlock */
+ /* REnable ADDR interrupt */
+ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX | SMBUS_IT_ADDR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions)
+{
+ /* Check the parameters */
+ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
+ {
+ if ((pData == NULL) || (Size == 0UL))
+ {
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_RX);
+
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = (HAL_SMBUS_STATE_SLAVE_BUSY_RX | HAL_SMBUS_STATE_LISTEN);
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+
+ /* Set SBC bit to manage Acknowledge at each bit */
+ hsmbus->Instance->CR1 |= I2C_CR1_SBC;
+
+ /* Enable Address Acknowledge */
+ hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Prepare transfer parameters */
+ hsmbus->pBuffPtr = pData;
+ hsmbus->XferSize = Size;
+ hsmbus->XferCount = Size;
+ hsmbus->XferOptions = XferOptions;
+
+ /* Convert OTHER_xxx XferOptions if any */
+ SMBUS_ConvertOtherXferOptions(hsmbus);
+
+ /* Set NBYTE to receive */
+ /* If XferSize equal "1", or XferSize equal "2" with PEC requested (mean 1 data byte + 1 PEC byte */
+ /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */
+ /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */
+ /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */
+ if (((SMBUS_GET_PEC_MODE(hsmbus) != 0UL) && (hsmbus->XferSize == 2U)) || (hsmbus->XferSize == 1U))
+ {
+ SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ }
+ else
+ {
+ SMBUS_TransferConfig(hsmbus, 0, 1, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP);
+ }
+
+ /* Clear ADDR flag after prepare the transfer parameters */
+ /* This action will generate an acknowledge to the HOST */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Note : The SMBUS interrupts must be enabled after unlocking current process
+ to avoid the risk of SMBUS interrupt handle execution before current
+ process unlock */
+ /* REnable ADDR interrupt */
+ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_ADDR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Enable the Address listen mode with Interrupt.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus)
+{
+ hsmbus->State = HAL_SMBUS_STATE_LISTEN;
+
+ /* Enable the Address Match interrupt */
+ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ADDR);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the Address listen mode with Interrupt.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Disable Address listen mode only if a transfer is not ongoing */
+ if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
+ {
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Disable the Address Match interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Enable the SMBUS alert mode with Interrupt.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUSx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Enable SMBus alert */
+ hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN;
+
+ /* Clear ALERT flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
+
+ /* Enable Alert Interrupt */
+ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ALERT);
+
+ return HAL_OK;
+}
+/**
+ * @brief Disable the SMBUS alert mode with Interrupt.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUSx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Enable SMBus alert */
+ hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN;
+
+ /* Disable Alert Interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ALERT);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Check if target device is ready for communication.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param Trials Number of trials
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials,
+ uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ __IO uint32_t SMBUS_Trials = 0UL;
+
+ FlagStatus tmp1;
+ FlagStatus tmp2;
+
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+
+ do
+ {
+ /* Generate Start */
+ hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode, DevAddress);
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is set or a NACK flag is set*/
+ tickstart = HAL_GetTick();
+
+ tmp1 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+ tmp2 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF);
+
+ while ((tmp1 == RESET) && (tmp2 == RESET))
+ {
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
+ {
+ /* Device is ready */
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Update SMBUS error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+ return HAL_ERROR;
+ }
+ }
+
+ tmp1 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+ tmp2 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF);
+ }
+
+ /* Check if the NACKF flag has not been set */
+ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET)
+ {
+ /* Wait until STOPF flag is reset */
+ if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Clear STOP Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+
+ /* Device is ready */
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Wait until STOPF flag is reset */
+ if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Clear NACK Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
+
+ /* Clear STOP Flag, auto generated with autoend*/
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+ }
+
+ /* Check if the maximum allowed number of trials has been reached */
+ if (SMBUS_Trials == Trials)
+ {
+ /* Generate Stop */
+ hsmbus->Instance->CR2 |= I2C_CR2_STOP;
+
+ /* Wait until STOPF flag is reset */
+ if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Clear STOP Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+ }
+
+ /* Increment Trials */
+ SMBUS_Trials++;
+ } while (SMBUS_Trials < Trials);
+
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Update SMBUS error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+
+/**
+ * @brief Handle SMBUS event interrupt request.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Use a local variable to store the current ISR flags */
+ /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */
+ uint32_t tmpisrvalue = READ_REG(hsmbus->Instance->ISR);
+ uint32_t tmpcr1value = READ_REG(hsmbus->Instance->CR1);
+
+ /* SMBUS in mode Transmitter ---------------------------------------------------*/
+ if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) \
+ && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || \
+ (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || \
+ (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || \
+ (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || \
+ (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
+ {
+ /* Slave mode selected */
+ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
+ {
+ (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue);
+ }
+ /* Master mode selected */
+ else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ {
+ (void)SMBUS_Master_ISR(hsmbus, tmpisrvalue);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+
+ /* SMBUS in mode Receiver ----------------------------------------------------*/
+ if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) \
+ && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || \
+ (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || \
+ (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || \
+ (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || \
+ (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
+ {
+ /* Slave mode selected */
+ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
+ {
+ (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue);
+ }
+ /* Master mode selected */
+ else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ {
+ (void)SMBUS_Master_ISR(hsmbus, tmpisrvalue);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+
+ /* SMBUS in mode Listener Only --------------------------------------------------*/
+ if (((SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_ADDRI) != RESET) || \
+ (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_STOPI) != RESET) || \
+ (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_NACKI) != RESET)) && \
+ ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || \
+ (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || \
+ (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
+ {
+ if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
+ {
+ (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue);
+ }
+ }
+}
+
+/**
+ * @brief Handle SMBUS error interrupt request.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
+{
+ SMBUS_ITErrorHandler(hsmbus);
+}
+
+/**
+ * @brief Master Tx Transfer completed callback.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+__weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_MasterTxCpltCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Master Rx Transfer completed callback.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+__weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_MasterRxCpltCallback() could be implemented in the user file
+ */
+}
+
+/** @brief Slave Tx Transfer completed callback.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+__weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_SlaveTxCpltCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Slave Rx Transfer completed callback.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+__weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_SlaveRxCpltCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Slave Address Match callback.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param TransferDirection Master request Transfer Direction (Write/Read)
+ * @param AddrMatchCode Address Match Code
+ * @retval None
+ */
+__weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+ UNUSED(TransferDirection);
+ UNUSED(AddrMatchCode);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_AddrCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Listen Complete callback.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+__weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_ListenCpltCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SMBUS error callback.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+__weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_ErrorCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief Peripheral State and Errors functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the SMBUS handle state.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval HAL state
+ */
+uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Return SMBUS handle state */
+ return hsmbus->State;
+}
+
+/**
+ * @brief Return the SMBUS error code.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval SMBUS Error Code
+ */
+uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus)
+{
+ return hsmbus->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
+ * @brief Data transfers Private functions
+ * @{
+ */
+
+/**
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param StatusFlags Value of Interrupt Flags.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
+{
+ uint16_t DevAddress;
+
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_AF) != RESET)
+ {
+ /* Clear NACK Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
+
+ /* Set corresponding Error Code */
+ /* No need to generate STOP, it is automatically done */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call the Error callback to inform upper layer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->ErrorCallback(hsmbus);
+#else
+ HAL_SMBUS_ErrorCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_STOPF) != RESET)
+ {
+ /* Check and treat errors if errors occurs during STOP process */
+ SMBUS_ITErrorHandler(hsmbus);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ {
+ /* Disable Interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
+
+ /* Clear STOP Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ SMBUS_RESET_CR2(hsmbus);
+
+ /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */
+ /* Disable the selected SMBUS peripheral */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+ hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Re-enable the selected SMBUS peripheral */
+ __HAL_SMBUS_ENABLE(hsmbus);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->MasterTxCpltCallback(hsmbus);
+#else
+ HAL_SMBUS_MasterTxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ {
+ /* Store Last receive data if any */
+ if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET)
+ {
+ /* Read data from RXDR */
+ *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
+
+ /* Increment Buffer pointer */
+ hsmbus->pBuffPtr++;
+
+ if ((hsmbus->XferSize > 0U))
+ {
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ }
+
+ /* Disable Interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
+
+ /* Clear STOP Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ SMBUS_RESET_CR2(hsmbus);
+
+ hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->MasterRxCpltCallback(hsmbus);
+#else
+ HAL_SMBUS_MasterRxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET)
+ {
+ /* Read data from RXDR */
+ *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
+
+ /* Increment Buffer pointer */
+ hsmbus->pBuffPtr++;
+
+ /* Increment Size counter */
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TXIS) != RESET)
+ {
+ /* Write data to TXDR */
+ hsmbus->Instance->TXDR = *hsmbus->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hsmbus->pBuffPtr++;
+
+ /* Increment Size counter */
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET)
+ {
+ if ((hsmbus->XferCount != 0U) && (hsmbus->XferSize == 0U))
+ {
+ DevAddress = (uint16_t)(hsmbus->Instance->CR2 & I2C_CR2_SADD);
+
+ if (hsmbus->XferCount > MAX_NBYTE_SIZE)
+ {
+ SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE,
+ (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
+ hsmbus->XferSize = MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hsmbus->XferSize = hsmbus->XferCount;
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
+ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
+ if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
+ {
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ }
+ }
+ else if ((hsmbus->XferCount == 0U) && (hsmbus->XferSize == 0U))
+ {
+ /* Call TxCpltCallback() if no stop mode is set */
+ if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ {
+ /* Disable Interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->MasterTxCpltCallback(hsmbus);
+#else
+ HAL_SMBUS_MasterTxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ {
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->MasterRxCpltCallback(hsmbus);
+#else
+ HAL_SMBUS_MasterRxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TC) != RESET)
+ {
+ if (hsmbus->XferCount == 0U)
+ {
+ /* Specific use case for Quick command */
+ if (hsmbus->pBuffPtr == NULL)
+ {
+ /* Generate a Stop command */
+ hsmbus->Instance->CR2 |= I2C_CR2_STOP;
+ }
+ /* Call TxCpltCallback() if no stop mode is set */
+ else if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
+ {
+ /* No Generate Stop, to permit restart mode */
+ /* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ {
+ /* Disable Interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->MasterTxCpltCallback(hsmbus);
+#else
+ HAL_SMBUS_MasterTxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ {
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->MasterRxCpltCallback(hsmbus);
+#else
+ HAL_SMBUS_MasterRxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+}
+/**
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param StatusFlags Value of Interrupt Flags.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
+{
+ uint8_t TransferDirection;
+ uint16_t SlaveAddrCode;
+
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_AF) != RESET)
+ {
+ /* Check that SMBUS transfer finished */
+ /* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */
+ /* Mean XferCount == 0*/
+ /* So clear Flag NACKF only */
+ if (hsmbus->XferCount == 0U)
+ {
+ /* Clear NACK Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+ }
+ else
+ {
+ /* if no, error usecase, a Non-Acknowledge of last Data is generated by the HOST*/
+ /* Clear NACK Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
+
+ /* Set HAL State to "Idle" State, mean to LISTEN state */
+ /* So reset Slave Busy state */
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
+ hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
+
+ /* Disable RX/TX Interrupts, keep only ADDR Interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
+
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call the Error callback to inform upper layer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->ErrorCallback(hsmbus);
+#else
+ HAL_SMBUS_ErrorCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ }
+ else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_ADDR) != RESET)
+ {
+ TransferDirection = (uint8_t)(SMBUS_GET_DIR(hsmbus));
+ SlaveAddrCode = (uint16_t)(SMBUS_GET_ADDR_MATCH(hsmbus));
+
+ /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/
+ /* Other ADDRInterrupt will be treat in next Listen usecase */
+ __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_ADDRI);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call Slave Addr callback */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
+#else
+ HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ else if ((SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) || \
+ (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET))
+ {
+ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
+ {
+ /* Read data from RXDR */
+ *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
+
+ /* Increment Buffer pointer */
+ hsmbus->pBuffPtr++;
+
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+
+ if (hsmbus->XferCount == 1U)
+ {
+ /* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */
+ /* or only the last Byte of Transfer */
+ /* So reset the RELOAD bit mode */
+ hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE;
+ SMBUS_TransferConfig(hsmbus, 0, 1, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ }
+ else if (hsmbus->XferCount == 0U)
+ {
+ /* Last Byte is received, disable Interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
+
+ /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_LISTEN */
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->SlaveRxCpltCallback(hsmbus);
+#else
+ HAL_SMBUS_SlaveRxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Set Reload for next Bytes */
+ SMBUS_TransferConfig(hsmbus, 0, 1, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE),
+ SMBUS_NO_STARTSTOP);
+
+ /* Ack last Byte Read */
+ hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
+ }
+ }
+ else if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
+ {
+ if ((hsmbus->XferCount != 0U) && (hsmbus->XferSize == 0U))
+ {
+ if (hsmbus->XferCount > MAX_NBYTE_SIZE)
+ {
+ SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE,
+ (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
+ hsmbus->XferSize = MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hsmbus->XferSize = hsmbus->XferCount;
+ SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
+ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
+ if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
+ {
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ }
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TXIS) != RESET)
+ {
+ /* Write data to TXDR only if XferCount not reach "0" */
+ /* A TXIS flag can be set, during STOP treatment */
+ /* Check if all Data have already been sent */
+ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
+ if (hsmbus->XferCount > 0U)
+ {
+ /* Write data to TXDR */
+ hsmbus->Instance->TXDR = *hsmbus->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hsmbus->pBuffPtr++;
+
+ hsmbus->XferCount--;
+ hsmbus->XferSize--;
+ }
+
+ if (hsmbus->XferCount == 0U)
+ {
+ /* Last Byte is Transmitted */
+ /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->SlaveTxCpltCallback(hsmbus);
+#else
+ HAL_SMBUS_SlaveTxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Check if STOPF is set */
+ if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_STOPF) != RESET)
+ {
+ if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
+ {
+ /* Store Last receive data if any */
+ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
+ {
+ /* Read data from RXDR */
+ *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
+
+ /* Increment Buffer pointer */
+ hsmbus->pBuffPtr++;
+
+ if ((hsmbus->XferSize > 0U))
+ {
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ }
+
+ /* Disable RX and TX Interrupts */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
+
+ /* Disable ADDR Interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
+
+ /* Disable Address Acknowledge */
+ hsmbus->Instance->CR2 |= I2C_CR2_NACK;
+
+ /* Clear Configuration Register 2 */
+ SMBUS_RESET_CR2(hsmbus);
+
+ /* Clear STOP Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+
+ /* Clear ADDR flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
+
+ hsmbus->XferOptions = 0;
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->ListenCpltCallback(hsmbus);
+#else
+ HAL_SMBUS_ListenCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+}
+/**
+ * @brief Manage the enabling of Interrupts.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
+ * @retval HAL status
+ */
+static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
+{
+ uint32_t tmpisr = 0UL;
+
+ if ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)
+ {
+ /* Enable ERR interrupt */
+ tmpisr |= SMBUS_IT_ERRI;
+ }
+
+ if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
+ {
+ /* Enable ADDR, STOP interrupt */
+ tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_ERRI;
+ }
+
+ if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
+ {
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+ tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI;
+ }
+
+ if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
+ {
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI;
+ }
+
+ /* Enable interrupts only at the end */
+ /* to avoid the risk of SMBUS interrupt handle execution before */
+ /* all interrupts requested done */
+ __HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr);
+}
+/**
+ * @brief Manage the disabling of Interrupts.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
+ * @retval HAL status
+ */
+static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
+{
+ uint32_t tmpisr = 0UL;
+ uint32_t tmpstate = hsmbus->State;
+
+ if ((tmpstate == HAL_SMBUS_STATE_READY) && ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT))
+ {
+ /* Disable ERR interrupt */
+ tmpisr |= SMBUS_IT_ERRI;
+ }
+
+ if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
+ {
+ /* Disable TC, STOP, NACK and TXI interrupt */
+ tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI;
+
+ if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL)
+ && ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
+ {
+ /* Disable ERR interrupt */
+ tmpisr |= SMBUS_IT_ERRI;
+ }
+
+ if ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
+ {
+ /* Disable STOP and NACK interrupt */
+ tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
+ }
+ }
+
+ if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
+ {
+ /* Disable TC, STOP, NACK and RXI interrupt */
+ tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI;
+
+ if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL)
+ && ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
+ {
+ /* Disable ERR interrupt */
+ tmpisr |= SMBUS_IT_ERRI;
+ }
+
+ if ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
+ {
+ /* Disable STOP and NACK interrupt */
+ tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
+ }
+ }
+
+ if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
+ {
+ /* Disable ADDR, STOP and NACK interrupt */
+ tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI;
+
+ if (SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL)
+ {
+ /* Disable ERR interrupt */
+ tmpisr |= SMBUS_IT_ERRI;
+ }
+ }
+
+ /* Disable interrupts only at the end */
+ /* to avoid a breaking situation like at "t" time */
+ /* all disable interrupts request are not done */
+ __HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr);
+}
+
+/**
+ * @brief SMBUS interrupts error handler.
+ * @param hsmbus SMBUS handle.
+ * @retval None
+ */
+static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
+{
+ uint32_t itflags = READ_REG(hsmbus->Instance->ISR);
+ uint32_t itsources = READ_REG(hsmbus->Instance->CR1);
+ uint32_t tmpstate;
+ uint32_t tmperror;
+
+ /* SMBUS Bus error interrupt occurred ------------------------------------*/
+ if (((itflags & SMBUS_FLAG_BERR) == SMBUS_FLAG_BERR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR;
+
+ /* Clear BERR flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR);
+ }
+
+ /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/
+ if (((itflags & SMBUS_FLAG_OVR) == SMBUS_FLAG_OVR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR;
+
+ /* Clear OVR flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR);
+ }
+
+ /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/
+ if (((itflags & SMBUS_FLAG_ARLO) == SMBUS_FLAG_ARLO) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO;
+
+ /* Clear ARLO flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO);
+ }
+
+ /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/
+ if (((itflags & SMBUS_FLAG_TIMEOUT) == SMBUS_FLAG_TIMEOUT) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT;
+
+ /* Clear TIMEOUT flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT);
+ }
+
+ /* SMBUS Alert error interrupt occurred -----------------------------------------------*/
+ if (((itflags & SMBUS_FLAG_ALERT) == SMBUS_FLAG_ALERT) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT;
+
+ /* Clear ALERT flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
+ }
+
+ /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/
+ if (((itflags & SMBUS_FLAG_PECERR) == SMBUS_FLAG_PECERR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR;
+
+ /* Clear PEC error flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
+ }
+
+ /* Store current volatile hsmbus->State, misra rule */
+ tmperror = hsmbus->ErrorCode;
+
+ /* Call the Error Callback in case of Error detected */
+ if ((tmperror != HAL_SMBUS_ERROR_NONE) && (tmperror != HAL_SMBUS_ERROR_ACKF))
+ {
+ /* Do not Reset the HAL state in case of ALERT error */
+ if ((tmperror & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT)
+ {
+ /* Store current volatile hsmbus->State, misra rule */
+ tmpstate = hsmbus->State;
+
+ if (((tmpstate & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
+ || ((tmpstate & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX))
+ {
+ /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */
+ /* keep HAL_SMBUS_STATE_LISTEN if set */
+ hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
+ hsmbus->State = HAL_SMBUS_STATE_LISTEN;
+ }
+ }
+
+ /* Call the Error callback to inform upper layer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->ErrorCallback(hsmbus);
+#else
+ HAL_SMBUS_ErrorCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief Handle SMBUS Communication Timeout.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param Flag Specifies the SMBUS flag to check.
+ * @param Status The new Flag status (SET or RESET).
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status,
+ uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Wait until flag is set */
+ while ((FlagStatus)(__HAL_SMBUS_GET_FLAG(hsmbus, Flag)) == Status)
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
+ {
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Update SMBUS error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
+ * @param hsmbus SMBUS handle.
+ * @param DevAddress specifies the slave address to be programmed.
+ * @param Size specifies the number of bytes to be programmed.
+ * This parameter must be a value between 0 and 255.
+ * @param Mode New state of the SMBUS START condition generation.
+ * This parameter can be one or a combination of the following values:
+ * @arg @ref SMBUS_RELOAD_MODE Enable Reload mode.
+ * @arg @ref SMBUS_AUTOEND_MODE Enable Automatic end mode.
+ * @arg @ref SMBUS_SOFTEND_MODE Enable Software end mode and Reload mode.
+ * @arg @ref SMBUS_SENDPEC_MODE Enable Packet Error Calculation mode.
+ * @param Request New state of the SMBUS START condition generation.
+ * This parameter can be one of the following values:
+ * @arg @ref SMBUS_NO_STARTSTOP Don't Generate stop and start condition.
+ * @arg @ref SMBUS_GENERATE_STOP Generate stop condition (Size should be set to 0).
+ * @arg @ref SMBUS_GENERATE_START_READ Generate Restart for read request.
+ * @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request.
+ * @retval None
+ */
+static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
+ uint32_t Request)
+{
+ /* Check the parameters */
+ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+ assert_param(IS_SMBUS_TRANSFER_MODE(Mode));
+ assert_param(IS_SMBUS_TRANSFER_REQUEST(Request));
+
+ /* update CR2 register */
+ MODIFY_REG(hsmbus->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
+ (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - I2C_CR2_RD_WRN_Pos))) | \
+ I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \
+ (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
+ (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
+ (uint32_t)Mode | (uint32_t)Request));
+}
+
+/**
+ * @brief Convert SMBUSx OTHER_xxx XferOptions to functional XferOptions.
+ * @param hsmbus SMBUS handle.
+ * @retval None
+ */
+static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC */
+ /* it request implicitly to generate a restart condition */
+ /* set XferOptions to SMBUS_FIRST_FRAME */
+ if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_NO_PEC)
+ {
+ hsmbus->XferOptions = SMBUS_FIRST_FRAME;
+ }
+ /* else if user set XferOptions to SMBUS_OTHER_FRAME_WITH_PEC */
+ /* it request implicitly to generate a restart condition */
+ /* set XferOptions to SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE */
+ else if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_WITH_PEC)
+ {
+ hsmbus->XferOptions = SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE;
+ }
+ /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_NO_PEC */
+ /* it request implicitly to generate a restart condition */
+ /* then generate a stop condition at the end of transfer */
+ /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_NO_PEC */
+ else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)
+ {
+ hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_NO_PEC;
+ }
+ /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC */
+ /* it request implicitly to generate a restart condition */
+ /* then generate a stop condition at the end of transfer */
+ /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC */
+ else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)
+ {
+ hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+}
+/**
+ * @}
+ */
+
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smbus_ex.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smbus_ex.c
new file mode 100644
index 00000000..e651a0bd
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smbus_ex.c
@@ -0,0 +1,374 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_smbus_ex.c
+ * @author MCD Application Team
+ * @brief SMBUS Extended HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of SMBUS Extended peripheral:
+ * + Extended features functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### SMBUS peripheral Extended features #####
+ ==============================================================================
+
+ [..] Comparing to other previous devices, the SMBUS interface for STM32U5xx
+ devices contains the following additional features
+
+ (+) Disable or enable wakeup from Stop mode(s)
+ (+) Disable or enable Fast Mode Plus
+
+ ##### How to use this driver #####
+ ==============================================================================
+ (#) Configure the enable or disable of SMBUS Wake Up Mode using the functions :
+ (++) HAL_SMBUSEx_EnableWakeUp()
+ (++) HAL_SMBUSEx_DisableWakeUp()
+ (#) Configure the enable or disable of fast mode plus driving capability using the functions :
+ (++) HAL_SMBUSEx_ConfigFastModePlus()
+ (#) Set or get or clear the autonomous mode configuration using these functions :
+ (++) HAL_SMBUSEx_SetConfigAutonomousMode()
+ (++) HAL_SMBUSEx_GetConfigAutonomousMode()
+ (++) HAL_SMBUSEx_ClearConfigAutonomousMode()
+ @endverbatim
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SMBUSEx SMBUSEx
+ * @brief SMBUS Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup SMBUSEx_Exported_Functions_Group2 SMBUS Extended WakeUp Mode Functions
+ * @brief WakeUp configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended WakeUp Mode Functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to enable and
+ disable WakeUp from Stop mode(s).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable SMBUS wakeup from Stop mode(s).
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUSx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUSEx_EnableWakeUp(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hsmbus->Instance));
+
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+ /* Disable the selected SMBUS peripheral */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+ /* Enable wakeup from stop mode */
+ hsmbus->Instance->CR1 |= I2C_CR1_WUPEN;
+
+ __HAL_SMBUS_ENABLE(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Disable SMBUS wakeup from Stop mode(s).
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUSx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUSEx_DisableWakeUp(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hsmbus->Instance));
+
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+ /* Disable the selected SMBUS peripheral */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+ /* Disable wakeup from stop mode */
+ hsmbus->Instance->CR1 &= ~(I2C_CR1_WUPEN);
+
+ __HAL_SMBUS_ENABLE(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SMBUSEx_Exported_Functions_Group3 SMBUS Extended FastModePlus Functions
+ * @brief FastModePlus Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended FastModePlus Function #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to configure
+ Fast Mode Plus.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure SMBUS Fast Mode Plus.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUSx peripheral.
+ * @param FastModePlus New state of the Fast Mode Plus.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUSEx_ConfigFastModePlus(SMBUS_HandleTypeDef *hsmbus, uint32_t FastModePlus)
+{
+ /* Check the parameters */
+ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+ assert_param(IS_SMBUS_FASTMODEPLUS(FastModePlus));
+
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+ /* Disable the selected SMBUS peripheral */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+ if (FastModePlus == SMBUS_FASTMODEPLUS_ENABLE)
+ {
+ /* Set SMBUSx FMP bit */
+ hsmbus->Instance->CR1 |= (I2C_CR1_FMP);
+ }
+ else
+ {
+ /* Reset SMBUSx FMP bit */
+ hsmbus->Instance->CR1 &= ~(I2C_CR1_FMP);
+ }
+
+ __HAL_SMBUS_ENABLE(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup SMBUSEx_Exported_Functions_Group4 SMBUS Extended Autonomous Mode Functions
+ * @brief SMBUS Extended Autonomous Mode Functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended Autonomous Mode functions #####
+ ===============================================================================
+ [..] This section provides functions allowing Set,Get and clear
+ Autonomous Mode configuration.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set Autonomous Mode configuration
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUSx peripheral.
+ * @param sConfig Pointer to a SMBUS_AutonomousModeConfTypeDef structure that contains
+ * the configuration information of the autonomous mode for the specified SMBUSx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUSEx_SetConfigAutonomousMode(SMBUS_HandleTypeDef *hsmbus,
+ SMBUS_AutonomousModeConfTypeDef *sConfig)
+{
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+ /* Check the parameters */
+ assert_param(IS_SMBUS_TRIG_SOURCE(hsmbus->Instance, sConfig->TriggerSelection));
+
+ assert_param(IS_SMBUS_AUTO_MODE_TRG_POL(sConfig->TriggerPolarity));
+
+ /* Disable the selected SMBUS peripheral to be able to configure AUTOCR */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+ /* SMBUSx AUTOCR Configuration */
+ WRITE_REG(hsmbus->Instance->AUTOCR, (sConfig->TriggerState | ((sConfig->TriggerSelection) & \
+ I2C_AUTOCR_TRIGSEL_Msk) | sConfig->TriggerPolarity));
+
+ /* Enable the selected SMBUS peripheral */
+ __HAL_SMBUS_ENABLE(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Get Autonomous Mode configuration
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUSx peripheral.
+ * @param sConfig Pointer to a SMBUS_AutonomousModeConfTypeDef structure that contains
+ * the configuration information of the autonomous mode for the specified SMBUSx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUSEx_GetConfigAutonomousMode(SMBUS_HandleTypeDef *hsmbus, \
+ SMBUS_AutonomousModeConfTypeDef *sConfig)
+{
+ uint32_t autocr_tmp;
+
+ autocr_tmp = hsmbus->Instance->AUTOCR;
+
+ sConfig->TriggerState = (autocr_tmp & I2C_AUTOCR_TRIGEN);
+ if (IS_SMBUS_GRP2_INSTANCE(hsmbus->Instance))
+ {
+ sConfig->TriggerSelection = ((autocr_tmp & I2C_AUTOCR_TRIGSEL) | SMBUS_TRIG_GRP2);
+ }
+ else
+ {
+ sConfig->TriggerSelection = ((autocr_tmp & I2C_AUTOCR_TRIGSEL) | SMBUS_TRIG_GRP1);
+ }
+ sConfig->TriggerPolarity = (autocr_tmp & I2C_AUTOCR_TRIGPOL);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Clear Autonomous Mode configuration
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUSEx_ClearConfigAutonomousMode(SMBUS_HandleTypeDef *hsmbus)
+{
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+ /* Disable the selected SMBUS peripheral to be able to clear AUTOCR */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+ CLEAR_REG(hsmbus->Instance->AUTOCR);
+
+ /* Enable the selected SMBUS peripheral */
+ __HAL_SMBUS_ENABLE(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi.c
new file mode 100644
index 00000000..03101c21
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi.c
@@ -0,0 +1,3864 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_spi.c
+ * @author MCD Application Team
+ * @brief SPI HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Serial Peripheral Interface (SPI) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The SPI HAL driver can be used as follows:
+
+ (#) Declare a SPI_HandleTypeDef handle structure, for example:
+ SPI_HandleTypeDef hspi;
+
+ (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
+ (##) Enable the SPIx interface clock
+ (##) SPI pins configuration
+ (+++) Enable the clock for the SPI GPIOs
+ (+++) Configure these SPI pins as alternate function push-pull
+ (##) NVIC configuration if you need to use interrupt process or DMA process
+ (+++) Configure the SPIx interrupt priority
+ (+++) Enable the NVIC SPI IRQ handle
+ (##) DMA Configuration if you need to use DMA process
+ (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
+ (+++) Enable the DMAx clock
+ (+++) Configure the DMA handle parameters
+ (+++) Configure the DMA Tx or Rx Stream/Channel
+ (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx
+ or Rx Stream/Channel
+
+ (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
+ management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
+
+ (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
+ (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customized HAL_SPI_MspInit() API.
+ [..]
+ Callback registration:
+
+ (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1UL
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
+
+ Function HAL_SPI_RegisterCallback() allows to register following callbacks:
+ (+) TxCpltCallback : SPI Tx Completed callback
+ (+) RxCpltCallback : SPI Rx Completed callback
+ (+) TxRxCpltCallback : SPI TxRx Completed callback
+ (+) TxHalfCpltCallback : SPI Tx Half Completed callback
+ (+) RxHalfCpltCallback : SPI Rx Half Completed callback
+ (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
+ (+) ErrorCallback : SPI Error callback
+ (+) AbortCpltCallback : SPI Abort callback
+ (+) MspInitCallback : SPI Msp Init callback
+ (+) MspDeInitCallback : SPI Msp DeInit callback
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+
+ (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
+ weak function.
+ HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TxCpltCallback : SPI Tx Completed callback
+ (+) RxCpltCallback : SPI Rx Completed callback
+ (+) TxRxCpltCallback : SPI TxRx Completed callback
+ (+) TxHalfCpltCallback : SPI Tx Half Completed callback
+ (+) RxHalfCpltCallback : SPI Rx Half Completed callback
+ (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
+ (+) ErrorCallback : SPI Error callback
+ (+) AbortCpltCallback : SPI Abort callback
+ (+) MspInitCallback : SPI Msp Init callback
+ (+) MspDeInitCallback : SPI Msp DeInit callback
+
+ By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+
+ Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
+ Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ Then, the user first registers the MspInit/MspDeInit user callbacks
+ using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
+ or HAL_SPI_Init() function.
+
+ When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
+
+ [..]
+ Circular mode restriction:
+ (+) The DMA circular mode cannot be used when the SPI is configured in these modes:
+ (++) Master 2Lines RxOnly
+ (++) Master 1Line Rx
+ (+) The CRC feature is not managed when the DMA circular mode is enabled
+ (+) The functions HAL_SPI_DMAPause()/ HAL_SPI_DMAResume() are not supported. Return always
+ HAL_ERROR with ErrorCode set to HAL_SPI_ERROR_NOT_SUPPORTED.
+ Those functions are maintained for backward compatibility reasons.
+
+ @endverbatim
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SPI SPI
+ * @brief SPI HAL module driver
+ * @{
+ */
+#ifdef HAL_SPI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup SPI_Private_Constants SPI Private Constants
+ * @{
+ */
+#define SPI_DEFAULT_TIMEOUT 100UL
+#define MAX_FIFO_LENGTH 16UL
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup SPI_Private_Functions SPI Private Functions
+ * @{
+ */
+static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAError(DMA_HandleTypeDef *hdma);
+static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus FlagStatus,
+ uint32_t Timeout, uint32_t Tickstart);
+static void SPI_TxISR_8BIT(SPI_HandleTypeDef *hspi);
+static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi);
+static void SPI_TxISR_32BIT(SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_8BIT(SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_16BIT(SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_32BIT(SPI_HandleTypeDef *hspi);
+static void SPI_AbortTransfer(SPI_HandleTypeDef *hspi);
+static void SPI_CloseTransfer(SPI_HandleTypeDef *hspi);
+static uint32_t SPI_GetPacketSize(SPI_HandleTypeDef *hspi);
+
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SPI_Exported_Functions SPI Exported Functions
+ * @{
+ */
+
+/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ de-initialize the SPIx peripheral:
+
+ (+) User must implement HAL_SPI_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+ (+) Call the function HAL_SPI_Init() to configure the selected device with
+ the selected configuration:
+ (++) Mode
+ (++) Direction
+ (++) Data Size
+ (++) Clock Polarity and Phase
+ (++) NSS Management
+ (++) BaudRate Prescaler
+ (++) FirstBit
+ (++) TIMode
+ (++) CRC Calculation
+ (++) CRC Polynomial if CRC enabled
+ (++) CRC Length, used only with Data8 and Data16
+ (++) FIFO reception threshold
+ (++) FIFO transmission threshold
+
+ (+) Call the function HAL_SPI_DeInit() to restore the default configuration
+ of the selected SPIx peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the SPI according to the specified parameters
+ * in the SPI_InitTypeDef and initialize the associated handle.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
+{
+ uint32_t crc_length;
+ uint32_t packet_length;
+
+ /* Check the SPI handle allocation */
+ if (hspi == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
+ assert_param(IS_SPI_MODE(hspi->Init.Mode));
+ assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
+ if (IS_SPI_LIMITED_INSTANCE(hspi->Instance))
+ {
+ assert_param(IS_SPI_LIMITED_DATASIZE(hspi->Init.DataSize));
+ assert_param(IS_SPI_LIMITED_FIFOTHRESHOLD(hspi->Init.FifoThreshold));
+ }
+ else
+ {
+ assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
+ assert_param(IS_SPI_FIFOTHRESHOLD(hspi->Init.FifoThreshold));
+ }
+ assert_param(IS_SPI_NSS(hspi->Init.NSS));
+ assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
+ assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
+ assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
+ assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
+ if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
+ {
+ assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
+ assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
+ }
+#if (USE_SPI_CRC != 0UL)
+ assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ if (IS_SPI_LIMITED_INSTANCE(hspi->Instance))
+ {
+ assert_param(IS_SPI_LIMITED_CRC_LENGTH(hspi->Init.CRCLength));
+ }
+ else
+ {
+ assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
+ }
+ assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
+ assert_param(IS_SPI_CRC_INITIALIZATION_PATTERN(hspi->Init.TxCRCInitializationPattern));
+ assert_param(IS_SPI_CRC_INITIALIZATION_PATTERN(hspi->Init.RxCRCInitializationPattern));
+ }
+#else
+ hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+#endif /* USE_SPI_CRC */
+
+ assert_param(IS_SPI_RDY_MASTER_MANAGEMENT(hspi->Init.ReadyMasterManagement));
+ assert_param(IS_SPI_RDY_POLARITY(hspi->Init.ReadyPolarity));
+
+ /* Verify that the SPI instance supports Data Size higher than 16bits */
+ if ((IS_SPI_LIMITED_INSTANCE(hspi->Instance)) && (hspi->Init.DataSize > SPI_DATASIZE_16BIT))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Verify that the SPI instance supports requested data packing */
+ packet_length = SPI_GetPacketSize(hspi);
+ if (((IS_SPI_LIMITED_INSTANCE(hspi->Instance)) && (packet_length > SPI_LOWEND_FIFO_SIZE)) ||
+ ((IS_SPI_FULL_INSTANCE(hspi->Instance)) && (packet_length > SPI_HIGHEND_FIFO_SIZE)))
+ {
+ return HAL_ERROR;
+ }
+#if (USE_SPI_CRC != 0UL)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* Verify that the SPI instance supports CRC Length higher than 16bits */
+ if ((IS_SPI_LIMITED_INSTANCE(hspi->Instance)) && (hspi->Init.CRCLength > SPI_CRC_LENGTH_16BIT))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Align the CRC Length on the data size */
+ if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
+ {
+ crc_length = (hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) << SPI_CFG1_CRCSIZE_Pos;
+ }
+ else
+ {
+ crc_length = hspi->Init.CRCLength;
+ }
+
+ /* Verify that the CRC Length is higher than DataSize */
+ if ((hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) > (crc_length >> SPI_CFG1_CRCSIZE_Pos))
+ {
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ crc_length = hspi->Init.DataSize << SPI_CFG1_CRCSIZE_Pos;
+ }
+#endif /* USE_SPI_CRC */
+
+ if (hspi->State == HAL_SPI_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hspi->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+ /* Init the SPI Callback settings */
+ hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
+ hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
+ hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
+ hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+
+ if (hspi->MspInitCallback == NULL)
+ {
+ hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+ hspi->MspInitCallback(hspi);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+ HAL_SPI_MspInit(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ }
+
+ hspi->State = HAL_SPI_STATE_BUSY;
+
+ /* Disable the selected SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+#if (USE_SPI_CRC == 0)
+ /* Keep the default value of CRCSIZE in case of CRC is not used */
+ crc_length = hspi->Instance->CFG1 & SPI_CFG1_CRCSIZE;
+#endif /* USE_SPI_CRC */
+
+ /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
+ /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
+ Communication speed, First bit, CRC calculation state, CRC Length */
+
+ /* SPIx NSS Software Management Configuration */
+ if ((hspi->Init.NSS == SPI_NSS_SOFT) && (((hspi->Init.Mode == SPI_MODE_MASTER) && \
+ (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_LOW)) || \
+ ((hspi->Init.Mode == SPI_MODE_SLAVE) && \
+ (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_HIGH))))
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_SSI);
+ }
+
+ /* SPIx CFG1 Configuration */
+ WRITE_REG(hspi->Instance->CFG1, (hspi->Init.BaudRatePrescaler | hspi->Init.CRCCalculation | crc_length |
+ hspi->Init.FifoThreshold | hspi->Init.DataSize));
+
+ /* SPIx CFG2 Configuration */
+ WRITE_REG(hspi->Instance->CFG2, (hspi->Init.NSSPMode | hspi->Init.TIMode |
+ hspi->Init.NSSPolarity | hspi->Init.NSS |
+ hspi->Init.CLKPolarity | hspi->Init.CLKPhase |
+ hspi->Init.FirstBit | hspi->Init.Mode |
+ hspi->Init.MasterInterDataIdleness | hspi->Init.Direction |
+ hspi->Init.MasterSSIdleness | hspi->Init.IOSwap |
+ hspi->Init.ReadyMasterManagement | hspi->Init.ReadyPolarity));
+
+#if (USE_SPI_CRC != 0UL)
+ /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
+ /* Configure : CRC Polynomial */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* Initialize TXCRC Pattern Initial Value */
+ if (hspi->Init.TxCRCInitializationPattern == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN)
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_TCRCINI);
+ }
+ else
+ {
+ CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_TCRCINI);
+ }
+
+ /* Initialize RXCRC Pattern Initial Value */
+ if (hspi->Init.RxCRCInitializationPattern == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN)
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_RCRCINI);
+ }
+ else
+ {
+ CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_RCRCINI);
+ }
+
+ /* Enable 33/17 bits CRC computation */
+ if (((IS_SPI_LIMITED_INSTANCE(hspi->Instance)) && (crc_length == SPI_CRC_LENGTH_16BIT)) ||
+ ((IS_SPI_FULL_INSTANCE(hspi->Instance)) && (crc_length == SPI_CRC_LENGTH_32BIT)))
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRC33_17);
+ }
+ else
+ {
+ CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_CRC33_17);
+ }
+
+ /* Write CRC polynomial in SPI Register */
+ WRITE_REG(hspi->Instance->CRCPOLY, hspi->Init.CRCPolynomial);
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Insure that Underrun configuration is managed only by Salve */
+ if (hspi->Init.Mode == SPI_MODE_SLAVE)
+ {
+#if (USE_SPI_CRC != 0UL)
+ MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, SPI_CFG1_UDRCFG);
+#endif /* USE_SPI_CRC */
+ }
+
+#if defined(SPI_I2SCFGR_I2SMOD)
+ /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
+ CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
+#endif /* SPI_I2SCFGR_I2SMOD */
+
+ /* Insure that AFCNTR is managed only by Master */
+ if ((hspi->Init.Mode & SPI_MODE_MASTER) == SPI_MODE_MASTER)
+ {
+ /* Alternate function GPIOs control */
+ MODIFY_REG(hspi->Instance->CFG2, SPI_CFG2_AFCNTR, (hspi->Init.MasterKeepIOState));
+ }
+
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->State = HAL_SPI_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief De-Initialize the SPI peripheral.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
+{
+ /* Check the SPI handle allocation */
+ if (hspi == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check SPI Instance parameter */
+ assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
+
+ hspi->State = HAL_SPI_STATE_BUSY;
+
+ /* Disable the SPI Peripheral Clock */
+ __HAL_SPI_DISABLE(hspi);
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+ if (hspi->MspDeInitCallback == NULL)
+ {
+ hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+ hspi->MspDeInitCallback(hspi);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+ HAL_SPI_MspDeInit(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->State = HAL_SPI_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the SPI MSP.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_MspInit should be implemented in the user file
+ */
+}
+
+/**
+ * @brief De-Initialize the SPI MSP.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_MspDeInit should be implemented in the user file
+ */
+}
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+/**
+ * @brief Register a User SPI Callback
+ * To be used instead of the weak predefined callback
+ * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI.
+ * @param CallbackID ID of the callback to be registered
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
+ pSPI_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Lock the process */
+ __HAL_LOCK(hspi);
+
+ if (HAL_SPI_STATE_READY == hspi->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SPI_TX_COMPLETE_CB_ID :
+ hspi->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_RX_COMPLETE_CB_ID :
+ hspi->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_TX_RX_COMPLETE_CB_ID :
+ hspi->TxRxCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
+ hspi->TxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
+ hspi->RxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
+ hspi->TxRxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_ERROR_CB_ID :
+ hspi->ErrorCallback = pCallback;
+ break;
+
+ case HAL_SPI_ABORT_CB_ID :
+ hspi->AbortCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_MSPINIT_CB_ID :
+ hspi->MspInitCallback = pCallback;
+ break;
+
+ case HAL_SPI_MSPDEINIT_CB_ID :
+ hspi->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_SPI_STATE_RESET == hspi->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SPI_MSPINIT_CB_ID :
+ hspi->MspInitCallback = pCallback;
+ break;
+
+ case HAL_SPI_MSPDEINIT_CB_ID :
+ hspi->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hspi);
+ return status;
+}
+
+/**
+ * @brief Unregister an SPI Callback
+ * SPI callback is redirected to the weak predefined callback
+ * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI.
+ * @param CallbackID ID of the callback to be unregistered
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Lock the process */
+ __HAL_LOCK(hspi);
+
+ if (HAL_SPI_STATE_READY == hspi->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SPI_TX_COMPLETE_CB_ID :
+ hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ break;
+
+ case HAL_SPI_RX_COMPLETE_CB_ID :
+ hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ break;
+
+ case HAL_SPI_TX_RX_COMPLETE_CB_ID :
+ hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
+ break;
+
+ case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
+ hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ break;
+
+ case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
+ hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ break;
+
+ case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
+ hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
+ break;
+
+ case HAL_SPI_ERROR_CB_ID :
+ hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_SPI_ABORT_CB_ID :
+ hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ break;
+
+ case HAL_SPI_MSPINIT_CB_ID :
+ hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_SPI_MSPDEINIT_CB_ID :
+ hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_SPI_STATE_RESET == hspi->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SPI_MSPINIT_CB_ID :
+ hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_SPI_MSPDEINIT_CB_ID :
+ hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hspi);
+ return status;
+}
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the SPI
+ data transfers.
+
+ [..] The SPI supports master and slave mode :
+
+ (#) There are two modes of transfer:
+ (##) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (##) No-Blocking mode: The communication is performed using Interrupts
+ or DMA, These APIs return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
+ will be executed respectively at the end of the transmit or Receive process
+ The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
+
+ (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
+ exist for 1Line (simplex) and 2Lines (full duplex) modes.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmit an amount of data in blocking mode.
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData : pointer to data buffer
+ * @param Size : amount of data to be sent
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+#if defined (__GNUC__)
+ __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR));
+#endif /* __GNUC__ */
+
+ uint32_t tickstart;
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction));
+
+ /* Lock the process */
+ __HAL_LOCK(hspi);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if (hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ if ((pData == NULL) || (Size == 0UL))
+ {
+ errorcode = HAL_ERROR;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_TX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (uint8_t *)pData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+
+ /*Init field not used in handle to zero */
+ hspi->pRxBuffPtr = NULL;
+ hspi->RxXferSize = (uint16_t) 0UL;
+ hspi->RxXferCount = (uint16_t) 0UL;
+ hspi->TxISR = NULL;
+ hspi->RxISR = NULL;
+
+ /* Configure communication direction : 1Line */
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_TX(hspi);
+ }
+
+ /* Set the number of data at current transfer */
+ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
+
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+
+ if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER))
+ {
+ /* Master transfer start */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
+ }
+
+ /* Transmit data in 32 Bit mode */
+ if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance)))
+ {
+ /* Transmit data in 32 Bit mode */
+ while (hspi->TxXferCount > 0UL)
+ {
+ /* Wait until TXP flag is set to send data */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP))
+ {
+ *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint32_t);
+ hspi->TxXferCount--;
+ }
+ else
+ {
+ /* Timeout management */
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+ {
+ /* Call standard close procedure with error check */
+ SPI_CloseTransfer(hspi);
+
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
+ hspi->State = HAL_SPI_STATE_READY;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ /* Transmit data in 16 Bit mode */
+ else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ /* Transmit data in 16 Bit mode */
+ while (hspi->TxXferCount > 0UL)
+ {
+ /* Wait until TXP flag is set to send data */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP))
+ {
+ if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
+ {
+ *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint32_t);
+ hspi->TxXferCount -= (uint16_t)2UL;
+ }
+ else
+ {
+#if defined (__GNUC__)
+ *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr);
+#else
+ *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
+#endif /* __GNUC__ */
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount--;
+ }
+ }
+ else
+ {
+ /* Timeout management */
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+ {
+ /* Call standard close procedure with error check */
+ SPI_CloseTransfer(hspi);
+
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
+ hspi->State = HAL_SPI_STATE_READY;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ /* Transmit data in 8 Bit mode */
+ else
+ {
+ while (hspi->TxXferCount > 0UL)
+ {
+ /* Wait until TXP flag is set to send data */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP))
+ {
+ if ((hspi->TxXferCount > 3UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA))
+ {
+ *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint32_t);
+ hspi->TxXferCount -= (uint16_t)4UL;
+ }
+ else if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
+ {
+#if defined (__GNUC__)
+ *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr);
+#else
+ *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
+#endif /* __GNUC__ */
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount -= (uint16_t)2UL;
+ }
+ else
+ {
+ *((__IO uint8_t *)&hspi->Instance->TXDR) = *((uint8_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint8_t);
+ hspi->TxXferCount--;
+ }
+ }
+ else
+ {
+ /* Timeout management */
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+ {
+ /* Call standard close procedure with error check */
+ SPI_CloseTransfer(hspi);
+
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
+ hspi->State = HAL_SPI_STATE_READY;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Wait for Tx (and CRC) data to be sent */
+ if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+
+ /* Call standard close procedure with error check */
+ SPI_CloseTransfer(hspi);
+
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+
+ hspi->State = HAL_SPI_STATE_READY;
+
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ return HAL_ERROR;
+ }
+ return errorcode;
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode.
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData : pointer to data buffer
+ * @param Size : amount of data to be received
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart;
+ HAL_StatusTypeDef errorcode = HAL_OK;
+#if defined (__GNUC__)
+ __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR));
+#endif /* __GNUC__ */
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction));
+
+ if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+ return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
+ }
+
+ /* Lock the process */
+ __HAL_LOCK(hspi);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if (hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ if ((pData == NULL) || (Size == 0UL))
+ {
+ errorcode = HAL_ERROR;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pRxBuffPtr = (uint8_t *)pData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /*Init field not used in handle to zero */
+ hspi->pTxBuffPtr = NULL;
+ hspi->TxXferSize = (uint16_t) 0UL;
+ hspi->TxXferCount = (uint16_t) 0UL;
+ hspi->RxISR = NULL;
+ hspi->TxISR = NULL;
+
+ /* Configure communication direction: 1Line */
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_RX(hspi);
+ }
+
+ /* Set the number of data at current transfer */
+ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
+
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+
+ if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER))
+ {
+ /* Master transfer start */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
+ }
+
+ /* Receive data in 32 Bit mode */
+ if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance)))
+ {
+ /* Transfer loop */
+ while (hspi->RxXferCount > 0UL)
+ {
+ /* Check the RXWNE/EOT flag */
+ if ((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_EOT)) != 0UL)
+ {
+ *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint32_t);
+ hspi->RxXferCount--;
+ }
+ else
+ {
+ /* Timeout management */
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+ {
+ /* Call standard close procedure with error check */
+ SPI_CloseTransfer(hspi);
+
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
+ hspi->State = HAL_SPI_STATE_READY;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ /* Receive data in 16 Bit mode */
+ else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ /* Transfer loop */
+ while (hspi->RxXferCount > 0UL)
+ {
+ /* Check the RXWNE/FRLVL flag */
+ if ((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_FRLVL)) != 0UL)
+ {
+ if ((hspi->Instance->SR & SPI_FLAG_RXWNE) != 0UL)
+ {
+ *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint32_t);
+ hspi->RxXferCount -= (uint16_t)2UL;
+ }
+ else
+ {
+#if defined (__GNUC__)
+ *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
+#else
+ *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
+#endif /* __GNUC__ */
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount--;
+ }
+ }
+ else
+ {
+ /* Timeout management */
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+ {
+ /* Call standard close procedure with error check */
+ SPI_CloseTransfer(hspi);
+
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
+ hspi->State = HAL_SPI_STATE_READY;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ /* Receive data in 8 Bit mode */
+ else
+ {
+ /* Transfer loop */
+ while (hspi->RxXferCount > 0UL)
+ {
+ /* Check the RXWNE/FRLVL flag */
+ if ((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_FRLVL)) != 0UL)
+ {
+ if ((hspi->Instance->SR & SPI_FLAG_RXWNE) != 0UL)
+ {
+ *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint32_t);
+ hspi->RxXferCount -= (uint16_t)4UL;
+ }
+ else if ((hspi->Instance->SR & SPI_FLAG_FRLVL) > SPI_RX_FIFO_1PACKET)
+ {
+#if defined (__GNUC__)
+ *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
+#else
+ *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
+#endif /* __GNUC__ */
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount -= (uint16_t)2UL;
+ }
+ else
+ {
+ *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint8_t);
+ hspi->RxXferCount--;
+ }
+ }
+ else
+ {
+ /* Timeout management */
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+ {
+ /* Call standard close procedure with error check */
+ SPI_CloseTransfer(hspi);
+
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
+ hspi->State = HAL_SPI_STATE_READY;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Wait for Rx (and CRC) data to be received */
+ if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+
+ /* Call standard close procedure with error check */
+ SPI_CloseTransfer(hspi);
+
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+
+ hspi->State = HAL_SPI_STATE_READY;
+
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ return HAL_ERROR;
+ }
+ return errorcode;
+}
+
+/**
+ * @brief Transmit and Receive an amount of data in blocking mode.
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pTxData: pointer to transmission data buffer
+ * @param pRxData: pointer to reception data buffer
+ * @param Size : amount of data to be sent and received
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
+ uint32_t Timeout)
+{
+ HAL_SPI_StateTypeDef tmp_state;
+ HAL_StatusTypeDef errorcode = HAL_OK;
+#if defined (__GNUC__)
+ __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR));
+ __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR));
+#endif /* __GNUC__ */
+
+ uint32_t tickstart;
+ uint32_t tmp_mode;
+ uint16_t initial_TxXferCount;
+ uint16_t initial_RxXferCount;
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+ /* Lock the process */
+ __HAL_LOCK(hspi);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ initial_TxXferCount = Size;
+ initial_RxXferCount = Size;
+ tmp_state = hspi->State;
+ tmp_mode = hspi->Init.Mode;
+
+ if (!((tmp_state == HAL_SPI_STATE_READY) || \
+ ((tmp_mode == SPI_MODE_MASTER) && \
+ (hspi->Init.Direction == SPI_DIRECTION_2LINES) && \
+ (tmp_state == HAL_SPI_STATE_BUSY_RX))))
+ {
+ errorcode = HAL_BUSY;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL))
+ {
+ errorcode = HAL_ERROR;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+ if (hspi->State != HAL_SPI_STATE_BUSY_RX)
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+ }
+
+ /* Set the transaction information */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pRxBuffPtr = (uint8_t *)pRxData;
+ hspi->RxXferCount = Size;
+ hspi->RxXferSize = Size;
+ hspi->pTxBuffPtr = (uint8_t *)pTxData;
+ hspi->TxXferCount = Size;
+ hspi->TxXferSize = Size;
+
+ /*Init field not used in handle to zero */
+ hspi->RxISR = NULL;
+ hspi->TxISR = NULL;
+
+ /* Set the number of data at current transfer */
+ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
+
+ __HAL_SPI_ENABLE(hspi);
+
+ if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER))
+ {
+ /* Master transfer start */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
+ }
+
+ /* Transmit and Receive data in 32 Bit mode */
+ if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance)))
+ {
+ while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL))
+ {
+ /* Check TXP flag */
+ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL))
+ {
+ *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint32_t);
+ hspi->TxXferCount --;
+ initial_TxXferCount = hspi->TxXferCount;
+ }
+
+ /* Check RXWNE/EOT flag */
+ if (((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_EOT)) != 0UL) && (initial_RxXferCount > 0UL))
+ {
+ *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint32_t);
+ hspi->RxXferCount --;
+ initial_RxXferCount = hspi->RxXferCount;
+ }
+
+ /* Timeout management */
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+ {
+ /* Call standard close procedure with error check */
+ SPI_CloseTransfer(hspi);
+
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
+ hspi->State = HAL_SPI_STATE_READY;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Transmit and Receive data in 16 Bit mode */
+ else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL))
+ {
+ /* Check TXP flag */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP) && (initial_TxXferCount > 0UL))
+ {
+ if ((initial_TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
+ {
+ *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint32_t);
+ hspi->TxXferCount -= (uint16_t)2UL;
+ initial_TxXferCount = hspi->TxXferCount;
+ }
+ else
+ {
+#if defined (__GNUC__)
+ *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr);
+#else
+ *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
+#endif /* __GNUC__ */
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount--;
+ initial_TxXferCount = hspi->TxXferCount;
+ }
+ }
+
+ /* Check RXWNE/FRLVL flag */
+ if (((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_FRLVL)) != 0UL) && (initial_RxXferCount > 0UL))
+ {
+ if ((hspi->Instance->SR & SPI_FLAG_RXWNE) != 0UL)
+ {
+ *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint32_t);
+ hspi->RxXferCount -= (uint16_t)2UL;
+ initial_RxXferCount = hspi->RxXferCount;
+ }
+ else
+ {
+#if defined (__GNUC__)
+ *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
+#else
+ *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
+#endif /* __GNUC__ */
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount--;
+ initial_RxXferCount = hspi->RxXferCount;
+ }
+ }
+
+ /* Timeout management */
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+ {
+ /* Call standard close procedure with error check */
+ SPI_CloseTransfer(hspi);
+
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
+ hspi->State = HAL_SPI_STATE_READY;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Transmit and Receive data in 8 Bit mode */
+ else
+ {
+ while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL))
+ {
+ /* check TXP flag */
+ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL))
+ {
+ if ((initial_TxXferCount > 3UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA))
+ {
+ *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint32_t);
+ hspi->TxXferCount -= (uint16_t)4UL;
+ initial_TxXferCount = hspi->TxXferCount;
+ }
+ else if ((initial_TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
+ {
+#if defined (__GNUC__)
+ *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr);
+#else
+ *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
+#endif /* __GNUC__ */
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount -= (uint16_t)2UL;
+ initial_TxXferCount = hspi->TxXferCount;
+ }
+ else
+ {
+ *((__IO uint8_t *)&hspi->Instance->TXDR) = *((uint8_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint8_t);
+ hspi->TxXferCount--;
+ initial_TxXferCount = hspi->TxXferCount;
+ }
+ }
+
+ /* Wait until RXWNE/FRLVL flag is reset */
+ if (((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_FRLVL)) != 0UL) && (initial_RxXferCount > 0UL))
+ {
+ if ((hspi->Instance->SR & SPI_FLAG_RXWNE) != 0UL)
+ {
+ *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint32_t);
+ hspi->RxXferCount -= (uint16_t)4UL;
+ initial_RxXferCount = hspi->RxXferCount;
+ }
+ else if ((hspi->Instance->SR & SPI_FLAG_FRLVL) > SPI_RX_FIFO_1PACKET)
+ {
+#if defined (__GNUC__)
+ *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
+#else
+ *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
+#endif /* __GNUC__ */
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount -= (uint16_t)2UL;
+ initial_RxXferCount = hspi->RxXferCount;
+ }
+ else
+ {
+ *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint8_t);
+ hspi->RxXferCount--;
+ initial_RxXferCount = hspi->RxXferCount;
+ }
+ }
+
+ /* Timeout management */
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+ {
+ /* Call standard close procedure with error check */
+ SPI_CloseTransfer(hspi);
+
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
+ hspi->State = HAL_SPI_STATE_READY;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Wait for Tx/Rx (and CRC) data to be sent/received */
+ if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+
+ /* Call standard close procedure with error check */
+ SPI_CloseTransfer(hspi);
+
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+
+ hspi->State = HAL_SPI_STATE_READY;
+
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ return HAL_ERROR;
+ }
+ return errorcode;
+}
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with Interrupt.
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData: pointer to data buffer
+ * @param Size : amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction));
+
+ /* Lock the process */
+ __HAL_LOCK(hspi);
+
+ if ((pData == NULL) || (Size == 0UL))
+ {
+ errorcode = HAL_ERROR;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ if (hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_TX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (uint8_t *)pData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+
+ /* Init field not used in handle to zero */
+ hspi->pRxBuffPtr = NULL;
+ hspi->RxXferSize = (uint16_t) 0UL;
+ hspi->RxXferCount = (uint16_t) 0UL;
+ hspi->RxISR = NULL;
+
+ /* Set the function for IT treatment */
+ if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance)))
+ {
+ hspi->TxISR = SPI_TxISR_32BIT;
+ }
+ else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ hspi->TxISR = SPI_TxISR_16BIT;
+ }
+ else
+ {
+ hspi->TxISR = SPI_TxISR_8BIT;
+ }
+
+ /* Configure communication direction : 1Line */
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_TX(hspi);
+ }
+
+ /* Set the number of data at current transfer */
+ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
+
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+
+ /* Enable EOT, TXP, FRE, MODF and UDR interrupts */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF));
+
+ if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER))
+ {
+ /* Master transfer start */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
+ }
+
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with Interrupt.
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData: pointer to data buffer
+ * @param Size : amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction));
+
+ if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+ return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
+ }
+
+ /* Lock the process */
+ __HAL_LOCK(hspi);
+
+ if (hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ if ((pData == NULL) || (Size == 0UL))
+ {
+ errorcode = HAL_ERROR;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pRxBuffPtr = (uint8_t *)pData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /* Init field not used in handle to zero */
+ hspi->pTxBuffPtr = NULL;
+ hspi->TxXferSize = (uint16_t) 0UL;
+ hspi->TxXferCount = (uint16_t) 0UL;
+ hspi->TxISR = NULL;
+
+ /* Set the function for IT treatment */
+ if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance)))
+ {
+ hspi->RxISR = SPI_RxISR_32BIT;
+ }
+ else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ hspi->RxISR = SPI_RxISR_16BIT;
+ }
+ else
+ {
+ hspi->RxISR = SPI_RxISR_8BIT;
+ }
+
+ /* Configure communication direction : 1Line */
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_RX(hspi);
+ }
+
+ /* Note : The SPI must be enabled after unlocking current process
+ to avoid the risk of SPI interrupt handle execution before current
+ process unlock */
+
+ /* Set the number of data at current transfer */
+ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
+
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+
+ /* Enable EOT, RXP, OVR, FRE and MODF interrupts */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_RXP | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF));
+
+ if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER))
+ {
+ /* Master transfer start */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
+ }
+
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pTxData: pointer to transmission data buffer
+ * @param pRxData: pointer to reception data buffer
+ * @param Size : amount of data to be sent and received
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+{
+ HAL_SPI_StateTypeDef tmp_state;
+ HAL_StatusTypeDef errorcode = HAL_OK;
+ uint32_t max_fifo_length = 0UL;
+ uint32_t tmp_TxXferCount;
+
+#if defined (__GNUC__)
+ __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR));
+#endif /* __GNUC__ */
+
+ uint32_t tmp_mode;
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+ /* Lock the process */
+ __HAL_LOCK(hspi);
+
+ /* Init temporary variables */
+ tmp_state = hspi->State;
+ tmp_mode = hspi->Init.Mode;
+
+ if (!((tmp_state == HAL_SPI_STATE_READY) || \
+ ((tmp_mode == SPI_MODE_MASTER) && \
+ (hspi->Init.Direction == SPI_DIRECTION_2LINES) && \
+ (tmp_state == HAL_SPI_STATE_BUSY_RX))))
+ {
+ errorcode = HAL_BUSY;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL))
+ {
+ errorcode = HAL_ERROR;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+ if (hspi->State != HAL_SPI_STATE_BUSY_RX)
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+ }
+
+ /* Set the transaction information */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (uint8_t *)pTxData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+ hspi->pRxBuffPtr = (uint8_t *)pRxData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+ tmp_TxXferCount = hspi->TxXferCount;
+
+ /* Set the function for IT treatment */
+ if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance)))
+ {
+ hspi->TxISR = SPI_TxISR_32BIT;
+ hspi->RxISR = SPI_RxISR_32BIT;
+ }
+ else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ hspi->RxISR = SPI_RxISR_16BIT;
+ hspi->TxISR = SPI_TxISR_16BIT;
+ }
+ else
+ {
+ hspi->RxISR = SPI_RxISR_8BIT;
+ hspi->TxISR = SPI_TxISR_8BIT;
+ }
+
+ /* Set the number of data at current transfer */
+ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
+
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+
+ /* Fill in the TxFIFO */
+ while ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (tmp_TxXferCount != 0UL))
+ {
+ if (max_fifo_length < MAX_FIFO_LENGTH)
+ {
+ /* Transmit data in 32 Bit mode */
+ if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
+ {
+ *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint32_t);
+ hspi->TxXferCount--;
+ tmp_TxXferCount = hspi->TxXferCount;
+ }
+ /* Transmit data in 16 Bit mode */
+ else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
+ {
+ *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint32_t);
+ hspi->TxXferCount -= (uint16_t)2UL;
+ tmp_TxXferCount = hspi->TxXferCount;
+ }
+ else
+ {
+#if defined (__GNUC__)
+ *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr);
+#else
+ *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
+#endif /* __GNUC__ */
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount--;
+ tmp_TxXferCount = hspi->TxXferCount;
+ }
+ }
+ /* Transmit data in 8 Bit mode */
+ else
+ {
+ if ((hspi->TxXferCount > 3UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA))
+ {
+ *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint32_t);
+ hspi->TxXferCount -= (uint16_t)4UL;
+ tmp_TxXferCount = hspi->TxXferCount;
+ }
+ else if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
+ {
+#if defined (__GNUC__)
+ *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr);
+#else
+ *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
+#endif /* __GNUC__ */
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount -= (uint16_t)2UL;
+ tmp_TxXferCount = hspi->TxXferCount;
+ }
+ else
+ {
+ *((__IO uint8_t *)&hspi->Instance->TXDR) = *((uint8_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint8_t);
+ hspi->TxXferCount--;
+ tmp_TxXferCount = hspi->TxXferCount;
+ }
+ }
+
+ max_fifo_length++;
+ }
+ else
+ {
+ errorcode = HAL_BUSY;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+ }
+
+ /* Enable EOT, DXP, UDR, OVR, FRE and MODF interrupts */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF));
+
+ if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER))
+ {
+ /* Start Master transfer */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
+ }
+
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+
+
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with DMA.
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData: pointer to data buffer
+ * @param Size : amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef errorcode;
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction));
+
+ /* Lock the process */
+ __HAL_LOCK(hspi);
+
+ if (hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ if ((pData == NULL) || (Size == 0UL))
+ {
+ errorcode = HAL_ERROR;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_TX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (uint8_t *)pData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+
+ /* Init field not used in handle to zero */
+ hspi->pRxBuffPtr = NULL;
+ hspi->TxISR = NULL;
+ hspi->RxISR = NULL;
+ hspi->RxXferSize = (uint16_t)0UL;
+ hspi->RxXferCount = (uint16_t)0UL;
+
+ /* Configure communication direction : 1Line */
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_TX(hspi);
+ }
+
+ /* Packing mode management is enabled by the DMA settings */
+ if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmatx->Init.SrcDataWidth != DMA_SRC_DATAWIDTH_WORD) && \
+ (IS_SPI_FULL_INSTANCE(hspi->Instance))) || \
+ ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_BYTE)))
+ {
+ /* Restriction the DMA data received is not allowed in this mode */
+ errorcode = HAL_ERROR;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ /* Adjust XferCount according to DMA alignment / Data size */
+ if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
+ {
+ if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
+ {
+ hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL;
+ }
+ if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
+ {
+ hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 3UL) >> 2UL;
+ }
+ }
+ else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT)
+ {
+ if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
+ {
+ hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL;
+ }
+ }
+ else
+ {
+ /* Adjustment done */
+ }
+
+ /* Set the SPI TxDMA Half transfer complete callback */
+ hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
+
+ /* Set the SPI TxDMA transfer complete callback */
+ hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
+
+ /* Set the DMA error callback */
+ hspi->hdmatx->XferErrorCallback = SPI_DMAError;
+
+ /* Set the DMA AbortCpltCallback */
+ hspi->hdmatx->XferAbortCallback = NULL;
+
+ /* Clear TXDMAEN bit*/
+ CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN);
+
+ if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
+ {
+ hspi->TxXferCount = Size;
+ }
+ else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT)
+ {
+ hspi->TxXferCount = Size * 2U;
+ }
+ else
+ {
+ hspi->TxXferCount = Size * 4U;
+ }
+
+ /* Enable the Tx DMA Stream/Channel */
+ if ((hspi->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if (hspi->hdmatx->LinkedListQueue != NULL)
+ {
+ /* Set DMA data size */
+ hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hspi->TxXferCount;
+
+ /* Set DMA source address */
+ hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hspi->pTxBuffPtr;
+
+ /* Set DMA destination address */
+ hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hspi->Instance->TXDR;
+
+ errorcode = HAL_DMAEx_List_Start_IT(hspi->hdmatx);
+ }
+ else
+ {
+ /* Update SPI error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+
+ hspi->State = HAL_SPI_STATE_READY;
+ errorcode = HAL_ERROR;
+ return errorcode;
+ }
+ }
+ else
+ {
+ errorcode = HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR,
+ hspi->TxXferCount);
+ }
+
+ /* Check status */
+ if (errorcode != HAL_OK)
+ {
+ /* Update SPI error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+
+ hspi->State = HAL_SPI_STATE_READY;
+ errorcode = HAL_ERROR;
+ return errorcode;
+ }
+
+ /* Set the number of data at current transfer */
+ if (hspi->hdmatx->Mode == DMA_LINKEDLIST_CIRCULAR)
+ {
+ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, 0UL);
+ }
+ else
+ {
+ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
+ }
+
+ /* Enable Tx DMA Request */
+ SET_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN);
+
+ /* Enable the SPI Error Interrupt Bit */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF));
+
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+
+ if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER))
+ {
+ /* Master transfer start */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
+ }
+
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with DMA.
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData: pointer to data buffer
+ * @param Size : amount of data to be sent
+ * @note When the CRC feature is enabled the pData Length must be Size + 1.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef errorcode;
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction));
+
+ if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+ return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
+ }
+
+ /* Lock the process */
+ __HAL_LOCK(hspi);
+
+ if (hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ if ((pData == NULL) || (Size == 0UL))
+ {
+ errorcode = HAL_ERROR;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pRxBuffPtr = (uint8_t *)pData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /*Init field not used in handle to zero */
+ hspi->RxISR = NULL;
+ hspi->TxISR = NULL;
+ hspi->TxXferSize = (uint16_t) 0UL;
+ hspi->TxXferCount = (uint16_t) 0UL;
+
+ /* Configure communication direction : 1Line */
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_RX(hspi);
+ }
+
+ /* Packing mode management is enabled by the DMA settings */
+ if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmarx->Init.DestDataWidth != DMA_DEST_DATAWIDTH_WORD) && \
+ (IS_SPI_FULL_INSTANCE(hspi->Instance))) || \
+ ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_BYTE)))
+ {
+ /* Restriction the DMA data received is not allowed in this mode */
+ errorcode = HAL_ERROR;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ /* Clear RXDMAEN bit */
+ CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN);
+
+ /* Adjust XferCount according to DMA alignment / Data size */
+ if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
+ {
+ if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_HALFWORD)
+ {
+ hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL;
+ }
+ if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_WORD)
+ {
+ hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 3UL) >> 2UL;
+ }
+ }
+ else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT)
+ {
+ if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_WORD)
+ {
+ hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL;
+ }
+ }
+ else
+ {
+ /* Adjustment done */
+ }
+
+ /* Set the SPI RxDMA Half transfer complete callback */
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
+
+ /* Set the SPI Rx DMA transfer complete callback */
+ hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
+
+ /* Set the DMA error callback */
+ hspi->hdmarx->XferErrorCallback = SPI_DMAError;
+
+ /* Set the DMA AbortCpltCallback */
+ hspi->hdmarx->XferAbortCallback = NULL;
+
+ if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
+ {
+ hspi->RxXferCount = Size;
+ }
+ else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT)
+ {
+ hspi->RxXferCount = Size * 2U;
+ }
+ else
+ {
+ hspi->RxXferCount = Size * 4U;
+ }
+
+ /* Enable the Rx DMA Stream/Channel */
+ if ((hspi->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if (hspi->hdmarx->LinkedListQueue != NULL)
+ {
+ /* Set DMA data size */
+ hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hspi->RxXferCount;
+
+ /* Set DMA source address */
+ hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hspi->Instance->RXDR;
+
+ /* Set DMA destination address */
+ hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hspi->pRxBuffPtr;
+
+ errorcode = HAL_DMAEx_List_Start_IT(hspi->hdmarx);
+ }
+ else
+ {
+ /* Update SPI error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+
+ hspi->State = HAL_SPI_STATE_READY;
+ errorcode = HAL_ERROR;
+ return errorcode;
+ }
+ }
+ else
+ {
+ errorcode = HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr,
+ hspi->RxXferCount);
+ }
+
+ /* Check status */
+ if (errorcode != HAL_OK)
+ {
+ /* Update SPI error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+
+ hspi->State = HAL_SPI_STATE_READY;
+ errorcode = HAL_ERROR;
+ return errorcode;
+ }
+
+ /* Set the number of data at current transfer */
+ if (hspi->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR)
+ {
+ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, 0UL);
+ }
+ else
+ {
+ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
+ }
+
+ /* Enable Rx DMA Request */
+ SET_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN);
+
+ /* Enable the SPI Error Interrupt Bit */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF));
+
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+
+ if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER))
+ {
+ /* Master transfer start */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
+ }
+
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pTxData: pointer to transmission data buffer
+ * @param pRxData: pointer to reception data buffer
+ * @param Size : amount of data to be sent
+ * @note When the CRC feature is enabled the pRxData Length must be Size + 1
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size)
+{
+ HAL_SPI_StateTypeDef tmp_state;
+ HAL_StatusTypeDef errorcode;
+
+ uint32_t tmp_mode;
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+ /* Lock the process */
+ __HAL_LOCK(hspi);
+
+ /* Init temporary variables */
+ tmp_state = hspi->State;
+ tmp_mode = hspi->Init.Mode;
+
+ if (!((tmp_state == HAL_SPI_STATE_READY) || \
+ ((tmp_mode == SPI_MODE_MASTER) && \
+ (hspi->Init.Direction == SPI_DIRECTION_2LINES) && \
+ (tmp_state == HAL_SPI_STATE_BUSY_RX))))
+ {
+ errorcode = HAL_BUSY;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL))
+ {
+ errorcode = HAL_ERROR;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+ if (hspi->State != HAL_SPI_STATE_BUSY_RX)
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+ }
+
+ /* Set the transaction information */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (uint8_t *)pTxData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+ hspi->pRxBuffPtr = (uint8_t *)pRxData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /* Init field not used in handle to zero */
+ hspi->RxISR = NULL;
+ hspi->TxISR = NULL;
+
+ /* Reset the Tx/Rx DMA bits */
+ CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
+
+ /* Packing mode management is enabled by the DMA settings */
+ if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmarx->Init.DestDataWidth != DMA_DEST_DATAWIDTH_WORD) && \
+ (IS_SPI_FULL_INSTANCE(hspi->Instance))) || \
+ ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_BYTE)))
+ {
+ /* Restriction the DMA data received is not allowed in this mode */
+ errorcode = HAL_ERROR;
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ /* Adjust XferCount according to DMA alignment / Data size */
+ if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
+ {
+ if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
+ {
+ hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL;
+ }
+ if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
+ {
+ hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 3UL) >> 2UL;
+ }
+ if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_HALFWORD)
+ {
+ hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL;
+ }
+ if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_WORD)
+ {
+ hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 3UL) >> 2UL;
+ }
+ }
+ else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT)
+ {
+ if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
+ {
+ hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL;
+ }
+ if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_WORD)
+ {
+ hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL;
+ }
+ }
+ else
+ {
+ /* Adjustment done */
+ }
+
+ /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
+ if (hspi->State == HAL_SPI_STATE_BUSY_RX)
+ {
+ /* Set the SPI Rx DMA Half transfer complete callback */
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
+ hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
+ }
+ else
+ {
+ /* Set the SPI Tx/Rx DMA Half transfer complete callback */
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
+ hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
+ }
+
+ /* Set the DMA error callback */
+ hspi->hdmarx->XferErrorCallback = SPI_DMAError;
+
+ /* Set the DMA AbortCallback */
+ hspi->hdmarx->XferAbortCallback = NULL;
+
+ if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
+ {
+ hspi->RxXferCount = Size;
+ }
+ else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT)
+ {
+ hspi->RxXferCount = Size * 2U;
+ }
+ else
+ {
+ hspi->RxXferCount = Size * 4U;
+ }
+ /* Enable the Rx DMA Stream/Channel */
+ if ((hspi->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if (hspi->hdmarx->LinkedListQueue != NULL)
+ {
+ /* Set DMA data size */
+ hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hspi->RxXferCount;
+
+ /* Set DMA source address */
+ hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hspi->Instance->RXDR;
+
+ /* Set DMA destination address */
+ hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hspi->pRxBuffPtr;
+
+ errorcode = HAL_DMAEx_List_Start_IT(hspi->hdmarx);
+ }
+ else
+ {
+ /* Update SPI error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+
+ hspi->State = HAL_SPI_STATE_READY;
+ errorcode = HAL_ERROR;
+ return errorcode;
+ }
+ }
+ else
+ {
+ errorcode = HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr,
+ hspi->RxXferCount);
+ }
+
+ /* Check status */
+ if (errorcode != HAL_OK)
+ {
+ /* Update SPI error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+
+ hspi->State = HAL_SPI_STATE_READY;
+ errorcode = HAL_ERROR;
+ return errorcode;
+ }
+
+ /* Enable Rx DMA Request */
+ SET_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN);
+
+ /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
+ is performed in DMA reception complete callback */
+ hspi->hdmatx->XferHalfCpltCallback = NULL;
+ hspi->hdmatx->XferCpltCallback = NULL;
+ hspi->hdmatx->XferErrorCallback = NULL;
+ hspi->hdmatx->XferAbortCallback = NULL;
+
+ if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
+ {
+ hspi->TxXferCount = Size;
+ }
+ else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT)
+ {
+ hspi->TxXferCount = Size * 2U;
+ }
+ else
+ {
+ hspi->TxXferCount = Size * 4U;
+ }
+
+ /* Enable the Tx DMA Stream/Channel */
+ if ((hspi->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if (hspi->hdmatx->LinkedListQueue != NULL)
+ {
+ /* Set DMA data size */
+ hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hspi->TxXferCount;
+
+ /* Set DMA source address */
+ hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hspi->pTxBuffPtr;
+
+ /* Set DMA destination address */
+ hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hspi->Instance->TXDR;
+
+ errorcode = HAL_DMAEx_List_Start_IT(hspi->hdmatx);
+ }
+ else
+ {
+ /* Update SPI error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+
+ hspi->State = HAL_SPI_STATE_READY;
+ errorcode = HAL_ERROR;
+ return errorcode;
+ }
+ }
+ else
+ {
+ errorcode = HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR,
+ hspi->TxXferCount);
+ }
+
+ /* Check status */
+ if (errorcode != HAL_OK)
+ {
+ /* Update SPI error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+
+ hspi->State = HAL_SPI_STATE_READY;
+ errorcode = HAL_ERROR;
+ return errorcode;
+ }
+
+ if ((hspi->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR) && (hspi->hdmatx->Mode == DMA_LINKEDLIST_CIRCULAR))
+ {
+ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, 0UL);
+ }
+ else
+ {
+ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
+ }
+
+ /* Enable Tx DMA Request */
+ SET_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN);
+
+ /* Enable the SPI Error Interrupt Bit */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_OVR | SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF));
+
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+
+ if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER))
+ {
+ /* Master transfer start */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
+ }
+
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Abort ongoing transfer (blocking mode).
+ * @param hspi SPI handle.
+ * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
+ * started in Interrupt or DMA mode.
+ * @note This procedure performs following operations :
+ * + Disable SPI Interrupts (depending of transfer direction)
+ * + Disable the DMA transfer in the peripheral register (if enabled)
+ * + Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * + Set handle State to READY.
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
+{
+ HAL_StatusTypeDef errorcode;
+
+ __IO uint32_t count;
+
+ /* Lock the process */
+ __HAL_LOCK(hspi);
+
+ /* Set hspi->state to aborting to avoid any interaction */
+ hspi->State = HAL_SPI_STATE_ABORT;
+
+ /* Initialized local variable */
+ errorcode = HAL_OK;
+ count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24UL / 1000UL);
+
+ /* If master communication on going, make sure current frame is done before closing the connection */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART))
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CSUSP);
+ do
+ {
+ count--;
+ if (count == 0UL)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
+ }
+ } while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART));
+ }
+
+ /* Disable the SPI DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN))
+ {
+ if (hspi->hdmatx != NULL)
+ {
+ /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
+ hspi->hdmatx->XferAbortCallback = NULL;
+
+ /* Abort DMA Tx Handle linked to SPI Peripheral */
+ if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hspi->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+ }
+ }
+ }
+
+ /* Disable the SPI DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN))
+ {
+ if (hspi->hdmarx != NULL)
+ {
+ /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
+ hspi->hdmarx->XferAbortCallback = NULL;
+
+ /* Abort DMA Rx Handle linked to SPI Peripheral */
+ if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hspi->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+ }
+ }
+ }
+
+ /* Proceed with abort procedure */
+ SPI_AbortTransfer(hspi);
+
+ /* Check error during Abort procedure */
+ if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
+ {
+ /* return HAL_Error in case of error during Abort procedure */
+ errorcode = HAL_ERROR;
+ }
+ else
+ {
+ /* Reset errorCode */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ }
+
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+
+ /* Restore hspi->state to ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ return errorcode;
+}
+
+/**
+ * @brief Abort ongoing transfer (Interrupt mode).
+ * @param hspi SPI handle.
+ * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
+ * started in Interrupt or DMA mode.
+ * @note This procedure performs following operations :
+ * + Disable SPI Interrupts (depending of transfer direction)
+ * + Disable the DMA transfer in the peripheral register (if enabled)
+ * + Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * + Set handle State to READY
+ * + At abort completion, call user abort complete callback.
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
+{
+ HAL_StatusTypeDef errorcode;
+ __IO uint32_t count;
+ uint32_t dma_tx_abort_done = 1UL;
+ uint32_t dma_rx_abort_done = 1UL;
+
+ /* Set hspi->state to aborting to avoid any interaction */
+ hspi->State = HAL_SPI_STATE_ABORT;
+
+ /* Initialized local variable */
+ errorcode = HAL_OK;
+ count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24UL / 1000UL);
+
+ /* If master communication on going, make sure current frame is done before closing the connection */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART))
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CSUSP);
+ do
+ {
+ count--;
+ if (count == 0UL)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
+ }
+ } while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART));
+ }
+
+ /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialized
+ before any call to DMA Abort functions */
+
+ if (hspi->hdmatx != NULL)
+ {
+ if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN))
+ {
+ /* Set DMA Abort Complete callback if SPI DMA Tx request if enabled */
+ hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
+
+ dma_tx_abort_done = 0UL;
+
+ /* Abort DMA Tx Handle linked to SPI Peripheral */
+ if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hspi->hdmatx) == HAL_DMA_ERROR_NO_XFER)
+ {
+ dma_tx_abort_done = 1UL;
+ hspi->hdmatx->XferAbortCallback = NULL;
+ }
+ }
+ }
+ else
+ {
+ hspi->hdmatx->XferAbortCallback = NULL;
+ }
+ }
+
+ if (hspi->hdmarx != NULL)
+ {
+ if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN))
+ {
+ /* Set DMA Abort Complete callback if SPI DMA Rx request if enabled */
+ hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
+
+ dma_rx_abort_done = 0UL;
+
+ /* Abort DMA Rx Handle linked to SPI Peripheral */
+ if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hspi->hdmarx) == HAL_DMA_ERROR_NO_XFER)
+ {
+ dma_rx_abort_done = 1UL;
+ hspi->hdmarx->XferAbortCallback = NULL;
+ }
+ }
+ }
+ else
+ {
+ hspi->hdmarx->XferAbortCallback = NULL;
+ }
+ }
+
+ /* If no running DMA transfer, finish cleanup and call callbacks */
+ if ((dma_tx_abort_done == 1UL) && (dma_rx_abort_done == 1UL))
+ {
+ /* Proceed with abort procedure */
+ SPI_AbortTransfer(hspi);
+
+ /* Check error during Abort procedure */
+ if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
+ {
+ /* return HAL_Error in case of error during Abort procedure */
+ errorcode = HAL_ERROR;
+ }
+ else
+ {
+ /* Reset errorCode */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ }
+
+ /* Restore hspi->state to ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+ hspi->AbortCpltCallback(hspi);
+#else
+ HAL_SPI_AbortCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ }
+
+ return errorcode;
+}
+
+/**
+ * @brief Pause the DMA Transfer.
+ * This API is not supported, it is maintained for backward compatibility.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL_ERROR
+ */
+HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
+{
+ /* Set error code to not supported */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_NOT_SUPPORTED);
+
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Resume the DMA Transfer.
+ * This API is not supported, it is maintained for backward compatibility.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL_ERROR
+ */
+HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
+{
+ /* Set error code to not supported */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_NOT_SUPPORTED);
+
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Stop the DMA Transfer.
+ * This API is not supported, it is maintained for backward compatibility.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL_ERROR
+ */
+HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
+{
+ /* Set error code to not supported */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_NOT_SUPPORTED);
+
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Handle SPI interrupt request.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval None
+ */
+void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
+{
+ uint32_t itsource = hspi->Instance->IER;
+ uint32_t itflag = hspi->Instance->SR;
+ uint32_t trigger = itsource & itflag;
+ uint32_t cfg1 = hspi->Instance->CFG1;
+ uint32_t handled = 0UL;
+
+ HAL_SPI_StateTypeDef State = hspi->State;
+#if defined (__GNUC__)
+ __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR));
+#endif /* __GNUC__ */
+
+
+ /* SPI in mode Transmitter and Receiver ------------------------------------*/
+ if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && \
+ HAL_IS_BIT_SET(trigger, SPI_FLAG_DXP))
+ {
+ hspi->TxISR(hspi);
+ hspi->RxISR(hspi);
+ handled = 1UL;
+ }
+
+ /* SPI in mode Receiver ----------------------------------------------------*/
+ if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_RXP) && \
+ HAL_IS_BIT_CLR(trigger, SPI_FLAG_DXP))
+ {
+ hspi->RxISR(hspi);
+ handled = 1UL;
+ }
+
+ /* SPI in mode Transmitter -------------------------------------------------*/
+ if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_TXP) && \
+ HAL_IS_BIT_CLR(trigger, SPI_FLAG_DXP))
+ {
+ hspi->TxISR(hspi);
+ handled = 1UL;
+ }
+
+
+ if (handled != 0UL)
+ {
+ return;
+ }
+
+ /* SPI End Of Transfer: DMA or IT based transfer */
+ if (HAL_IS_BIT_SET(trigger, SPI_FLAG_EOT))
+ {
+ /* Clear EOT/TXTF/SUSP flag */
+ __HAL_SPI_CLEAR_EOTFLAG(hspi);
+ __HAL_SPI_CLEAR_TXTFFLAG(hspi);
+ __HAL_SPI_CLEAR_SUSPFLAG(hspi);
+
+ /* Disable EOT interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT);
+
+ /* DMA Normal Mode */
+ if (HAL_IS_BIT_CLR(cfg1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN) ||
+ ((State != HAL_SPI_STATE_BUSY_RX) && (hspi->hdmarx->Mode != DMA_LINKEDLIST_CIRCULAR)) ||
+ ((State != HAL_SPI_STATE_BUSY_TX) && (hspi->hdmatx->Mode != DMA_LINKEDLIST_CIRCULAR)))
+ {
+ /* For the IT based receive extra polling maybe required for last packet */
+ if (HAL_IS_BIT_CLR(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN))
+ {
+ /* Pooling remaining data */
+ while (hspi->RxXferCount != 0UL)
+ {
+ /* Receive data in 32 Bit mode */
+ if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
+ {
+ *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint32_t);
+ }
+ /* Receive data in 16 Bit mode */
+ else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+#if defined (__GNUC__)
+ *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
+#else
+ *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
+#endif /* __GNUC__ */
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ }
+ /* Receive data in 8 Bit mode */
+ else
+ {
+ *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint8_t);
+ }
+
+ hspi->RxXferCount--;
+ }
+ }
+
+ /* Call SPI Standard close procedure */
+ SPI_CloseTransfer(hspi);
+
+ hspi->State = HAL_SPI_STATE_READY;
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+ hspi->ErrorCallback(hspi);
+#else
+ HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ return;
+ }
+ }
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+ /* Call appropriate user callback */
+ if (State == HAL_SPI_STATE_BUSY_TX_RX)
+ {
+ hspi->TxRxCpltCallback(hspi);
+ }
+ else if (State == HAL_SPI_STATE_BUSY_RX)
+ {
+ hspi->RxCpltCallback(hspi);
+ }
+ else if (State == HAL_SPI_STATE_BUSY_TX)
+ {
+ hspi->TxCpltCallback(hspi);
+ }
+#else
+ /* Call appropriate user callback */
+ if (State == HAL_SPI_STATE_BUSY_TX_RX)
+ {
+ HAL_SPI_TxRxCpltCallback(hspi);
+ }
+ else if (State == HAL_SPI_STATE_BUSY_RX)
+ {
+ HAL_SPI_RxCpltCallback(hspi);
+ }
+ else if (State == HAL_SPI_STATE_BUSY_TX)
+ {
+ HAL_SPI_TxCpltCallback(hspi);
+ }
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ else
+ {
+ /* End of the appropriate call */
+ }
+
+ return;
+ }
+
+ if (HAL_IS_BIT_SET(itflag, SPI_FLAG_SUSP) && HAL_IS_BIT_SET(itsource, SPI_FLAG_EOT))
+ {
+ /* Abort on going, clear SUSP flag to avoid infinite looping */
+ __HAL_SPI_CLEAR_SUSPFLAG(hspi);
+
+ return;
+ }
+
+ /* SPI in Error Treatment --------------------------------------------------*/
+ if ((trigger & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE | SPI_FLAG_UDR)) != 0UL)
+ {
+ /* SPI Overrun error interrupt occurred ----------------------------------*/
+ if ((trigger & SPI_FLAG_OVR) != 0UL)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+
+ /* SPI Mode Fault error interrupt occurred -------------------------------*/
+ if ((trigger & SPI_FLAG_MODF) != 0UL)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
+ __HAL_SPI_CLEAR_MODFFLAG(hspi);
+ }
+
+ /* SPI Frame error interrupt occurred ------------------------------------*/
+ if ((trigger & SPI_FLAG_FRE) != 0UL)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
+ __HAL_SPI_CLEAR_FREFLAG(hspi);
+ }
+
+ /* SPI Underrun error interrupt occurred ------------------------------------*/
+ if ((trigger & SPI_FLAG_UDR) != 0UL)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_UDR);
+ __HAL_SPI_CLEAR_UDRFLAG(hspi);
+ }
+
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Disable all interrupts */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_RXP | SPI_IT_TXP | SPI_IT_MODF |
+ SPI_IT_OVR | SPI_IT_FRE | SPI_IT_UDR));
+
+ /* Disable the SPI DMA requests if enabled */
+ if (HAL_IS_BIT_SET(cfg1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN))
+ {
+ /* Disable the SPI DMA requests */
+ CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
+
+ /* Abort the SPI DMA Rx channel */
+ if (hspi->hdmarx != NULL)
+ {
+ /* Set the SPI DMA Abort callback :
+ will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
+ hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
+ if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ }
+ }
+ /* Abort the SPI DMA Tx channel */
+ if (hspi->hdmatx != NULL)
+ {
+ /* Set the SPI DMA Abort callback :
+ will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
+ hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
+ if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ }
+ }
+ }
+ else
+ {
+ /* Restore hspi->State to Ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+ hspi->ErrorCallback(hspi);
+#else
+ HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ }
+ }
+ return;
+ }
+}
+
+/**
+ * @brief Tx Transfer completed callback.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_TxCpltCallback should be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callback.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_RxCpltCallback should be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx and Rx Transfer completed callback.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_TxRxCpltCallback should be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx Half Transfer completed callback.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Half Transfer completed callback.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx and Rx Half Transfer callback.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
+ */
+}
+
+/**
+ * @brief SPI error callback.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_ErrorCallback should be implemented in the user file
+ */
+ /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
+ and user can use HAL_SPI_GetError() API to check the latest error occurred
+ */
+}
+
+/**
+ * @brief SPI Abort Complete callback.
+ * @param hspi SPI handle.
+ * @retval None
+ */
+__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_AbortCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief SPI control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the SPI.
+ (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
+ (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the SPI handle state.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval SPI state
+ */
+HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
+{
+ /* Return SPI handle state */
+ return hspi->State;
+}
+
+/**
+ * @brief Return the SPI error code.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval SPI error code in bitmap format
+ */
+uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
+{
+ /* Return SPI ErrorCode */
+ return hspi->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Private_Functions
+ * @brief Private functions
+ * @{
+ */
+
+/**
+ * @brief DMA SPI transmit process complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ if (hspi->State != HAL_SPI_STATE_ABORT)
+ {
+ if (hspi->hdmatx->Mode == DMA_LINKEDLIST_CIRCULAR)
+ {
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+ hspi->TxCpltCallback(hspi);
+#else
+ HAL_SPI_TxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Enable EOT interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT);
+ }
+ }
+}
+
+/**
+ * @brief DMA SPI receive process complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ if (hspi->State != HAL_SPI_STATE_ABORT)
+ {
+ if (hspi->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR)
+ {
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+ hspi->RxCpltCallback(hspi);
+#else
+ HAL_SPI_RxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Enable EOT interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT);
+ }
+ }
+}
+
+/**
+ * @brief DMA SPI transmit receive process complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ if (hspi->State != HAL_SPI_STATE_ABORT)
+ {
+ if ((hspi->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR) &&
+ (hspi->hdmatx->Mode == DMA_LINKEDLIST_CIRCULAR))
+ {
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+ hspi->TxRxCpltCallback(hspi);
+#else
+ HAL_SPI_TxRxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Enable EOT interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT);
+ }
+ }
+}
+
+/**
+ * @brief DMA SPI half transmit process complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+ hspi->TxHalfCpltCallback(hspi);
+#else
+ HAL_SPI_TxHalfCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA SPI half receive process complete callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+ hspi->RxHalfCpltCallback(hspi);
+#else
+ HAL_SPI_RxHalfCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA SPI half transmit receive process complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+ hspi->TxRxHalfCpltCallback(hspi);
+#else
+ HAL_SPI_TxRxHalfCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA SPI communication error callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAError(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* if DMA error is FIFO error ignore it */
+ if (HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_NONE)
+ {
+ /* Call SPI standard close procedure */
+ SPI_CloseTransfer(hspi);
+
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ hspi->State = HAL_SPI_STATE_READY;
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+ hspi->ErrorCallback(hspi);
+#else
+ HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief DMA SPI communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ hspi->RxXferCount = (uint16_t) 0UL;
+ hspi->TxXferCount = (uint16_t) 0UL;
+
+ /* Restore hspi->State to Ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+ hspi->ErrorCallback(hspi);
+#else
+ HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA SPI Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ hspi->hdmatx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if (hspi->hdmarx != NULL)
+ {
+ if (hspi->hdmarx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* Call the Abort procedure */
+ SPI_AbortTransfer(hspi);
+
+ /* Restore hspi->State to Ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+ hspi->AbortCpltCallback(hspi);
+#else
+ HAL_SPI_AbortCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA SPI Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ hspi->hdmarx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if (hspi->hdmatx != NULL)
+ {
+ if (hspi->hdmatx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* Call the Abort procedure */
+ SPI_AbortTransfer(hspi);
+
+ /* Restore hspi->State to Ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+ hspi->AbortCpltCallback(hspi);
+#else
+ HAL_SPI_AbortCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief Manage the receive 8-bit in Interrupt context.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_RxISR_8BIT(SPI_HandleTypeDef *hspi)
+{
+ /* Receive data in 8 Bit mode */
+ *((uint8_t *)hspi->pRxBuffPtr) = (*(__IO uint8_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint8_t);
+ hspi->RxXferCount--;
+
+ /* Disable IT if no more data excepted */
+ if (hspi->RxXferCount == 0UL)
+ {
+ /* Disable RXP interrupts */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP);
+ }
+}
+
+
+/**
+ * @brief Manage the 16-bit receive in Interrupt context.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_RxISR_16BIT(SPI_HandleTypeDef *hspi)
+{
+ /* Receive data in 16 Bit mode */
+#if defined (__GNUC__)
+ __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR));
+
+ *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
+#else
+ *((uint16_t *)hspi->pRxBuffPtr) = (*(__IO uint16_t *)&hspi->Instance->RXDR);
+#endif /* __GNUC__ */
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount--;
+
+ /* Disable IT if no more data excepted */
+ if (hspi->RxXferCount == 0UL)
+ {
+ /* Disable RXP interrupts */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP);
+ }
+}
+
+
+/**
+ * @brief Manage the 32-bit receive in Interrupt context.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_RxISR_32BIT(SPI_HandleTypeDef *hspi)
+{
+ /* Receive data in 32 Bit mode */
+ *((uint32_t *)hspi->pRxBuffPtr) = (*(__IO uint32_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint32_t);
+ hspi->RxXferCount--;
+
+ /* Disable IT if no more data excepted */
+ if (hspi->RxXferCount == 0UL)
+ {
+ /* Disable RXP interrupts */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP);
+ }
+}
+
+
+/**
+ * @brief Handle the data 8-bit transmit in Interrupt mode.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_TxISR_8BIT(SPI_HandleTypeDef *hspi)
+{
+ /* Transmit data in 8 Bit mode */
+ *(__IO uint8_t *)&hspi->Instance->TXDR = *((uint8_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint8_t);
+ hspi->TxXferCount--;
+
+ /* Disable IT if no more data excepted */
+ if (hspi->TxXferCount == 0UL)
+ {
+ /* Disable TXP interrupts */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP);
+ }
+}
+
+/**
+ * @brief Handle the data 16-bit transmit in Interrupt mode.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi)
+{
+ /* Transmit data in 16 Bit mode */
+#if defined (__GNUC__)
+ __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR));
+
+ *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr);
+#else
+ *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
+#endif /* __GNUC__ */
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount--;
+
+ /* Disable IT if no more data excepted */
+ if (hspi->TxXferCount == 0UL)
+ {
+ /* Disable TXP interrupts */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP);
+ }
+}
+
+/**
+ * @brief Handle the data 32-bit transmit in Interrupt mode.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_TxISR_32BIT(SPI_HandleTypeDef *hspi)
+{
+ /* Transmit data in 32 Bit mode */
+ *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint32_t);
+ hspi->TxXferCount--;
+
+ /* Disable IT if no more data excepted */
+ if (hspi->TxXferCount == 0UL)
+ {
+ /* Disable TXP interrupts */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP);
+ }
+}
+
+/**
+ * @brief Abort Transfer and clear flags.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_AbortTransfer(SPI_HandleTypeDef *hspi)
+{
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Disable ITs */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_RXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | \
+ SPI_IT_FRE | SPI_IT_MODF));
+
+ /* Clear the Status flags in the SR register */
+ __HAL_SPI_CLEAR_EOTFLAG(hspi);
+ __HAL_SPI_CLEAR_TXTFFLAG(hspi);
+
+ /* Disable Tx DMA Request */
+ CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
+
+ /* Clear the Error flags in the SR register */
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ __HAL_SPI_CLEAR_UDRFLAG(hspi);
+ __HAL_SPI_CLEAR_FREFLAG(hspi);
+ __HAL_SPI_CLEAR_MODFFLAG(hspi);
+ __HAL_SPI_CLEAR_SUSPFLAG(hspi);
+
+#if (USE_SPI_CRC != 0U)
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+#endif /* USE_SPI_CRC */
+
+ hspi->TxXferCount = (uint16_t)0UL;
+ hspi->RxXferCount = (uint16_t)0UL;
+}
+
+
+/**
+ * @brief Close Transfer and clear flags.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval HAL_ERROR: if any error detected
+ * HAL_OK: if nothing detected
+ */
+static void SPI_CloseTransfer(SPI_HandleTypeDef *hspi)
+{
+ uint32_t itflag = hspi->Instance->SR;
+
+ __HAL_SPI_CLEAR_EOTFLAG(hspi);
+ __HAL_SPI_CLEAR_TXTFFLAG(hspi);
+
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Disable ITs */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_RXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | \
+ SPI_IT_FRE | SPI_IT_MODF));
+
+ /* Disable Tx DMA Request */
+ CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
+
+ /* Report UnderRun error for non RX Only communication */
+ if (hspi->State != HAL_SPI_STATE_BUSY_RX)
+ {
+ if ((itflag & SPI_FLAG_UDR) != 0UL)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_UDR);
+ __HAL_SPI_CLEAR_UDRFLAG(hspi);
+ }
+ }
+
+ /* Report OverRun error for non TX Only communication */
+ if (hspi->State != HAL_SPI_STATE_BUSY_TX)
+ {
+ if ((itflag & SPI_FLAG_OVR) != 0UL)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+
+#if (USE_SPI_CRC != 0UL)
+ /* Check if CRC error occurred */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ if ((itflag & SPI_FLAG_CRCERR) != 0UL)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ }
+ }
+#endif /* USE_SPI_CRC */
+ }
+
+ /* SPI Mode Fault error interrupt occurred -------------------------------*/
+ if ((itflag & SPI_FLAG_MODF) != 0UL)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
+ __HAL_SPI_CLEAR_MODFFLAG(hspi);
+ }
+
+ /* SPI Frame error interrupt occurred ------------------------------------*/
+ if ((itflag & SPI_FLAG_FRE) != 0UL)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
+ __HAL_SPI_CLEAR_FREFLAG(hspi);
+ }
+
+ hspi->TxXferCount = (uint16_t)0UL;
+ hspi->RxXferCount = (uint16_t)0UL;
+}
+
+/**
+ * @brief Handle SPI Communication Timeout.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param Flag: SPI flag to check
+ * @param Status: flag state to check
+ * @param Timeout: Timeout duration
+ * @param Tickstart: Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status,
+ uint32_t Tickstart, uint32_t Timeout)
+{
+ /* Wait until flag is set */
+ while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) == Status)
+ {
+ /* Check for the Timeout */
+ if ((((HAL_GetTick() - Tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Compute configured packet size from fifo perspective.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval Packet size occupied in the fifo
+ */
+static uint32_t SPI_GetPacketSize(SPI_HandleTypeDef *hspi)
+{
+ uint32_t fifo_threashold = (hspi->Init.FifoThreshold >> SPI_CFG1_FTHLV_Pos) + 1UL;
+ uint32_t data_size = (hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) + 1UL;
+
+ /* Convert data size to Byte */
+ data_size = (data_size + 7UL) / 8UL;
+
+ return data_size * fifo_threashold;
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi_ex.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi_ex.c
new file mode 100644
index 00000000..0c1ab238
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi_ex.c
@@ -0,0 +1,334 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_spi_ex.c
+ * @author MCD Application Team
+ * @brief Extended SPI HAL module driver.
+ * This file provides firmware functions to manage the following
+ * SPI peripheral extended functionalities :
+ * + IO operation functions
+ * + Peripheral Control functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SPIEx SPIEx
+ * @brief SPI Extended HAL module driver
+ * @{
+ */
+#ifdef HAL_SPI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions
+ * @{
+ */
+
+/** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of extended functions to manage the SPI
+ data transfers.
+
+ (#) SPIEx function:
+ (++) HAL_SPIEx_FlushRxFifo()
+ (++) HAL_SPIEx_FlushRxFifo()
+ (++) HAL_SPIEx_EnableLockConfiguration()
+ (++) HAL_SPIEx_ConfigureUnderrun()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Flush the RX fifo.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi)
+{
+ uint8_t count = 0;
+ uint32_t itflag = hspi->Instance->SR;
+ __IO uint32_t tmpreg;
+
+ while (((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_RX_FIFO_0PACKET) || ((itflag & SPI_FLAG_RXWNE) != 0UL))
+ {
+ count += (uint8_t)4UL;
+ tmpreg = hspi->Instance->RXDR;
+ UNUSED(tmpreg); /* To avoid GCC warning */
+
+ if (IS_SPI_FULL_INSTANCE(hspi->Instance))
+ {
+ if (count > SPI_HIGHEND_FIFO_SIZE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ else
+ {
+ if (count > SPI_LOWEND_FIFO_SIZE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Enable the Lock for the AF configuration of associated IOs
+ * and write protect the Content of Configuration register 2
+ * when SPI is enabled
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_SPIEx_EnableLockConfiguration(SPI_HandleTypeDef *hspi)
+{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ if (hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ /* Check if the SPI is disabled to edit IOLOCK bit */
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_IOLOCK);
+ }
+ else
+ {
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_IOLOCK);
+
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Configure the UNDERRUN condition and behavior of slave transmitter.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param UnderrunDetection : Detection of underrun condition at slave transmitter
+ * This parameter is not supported in this SPI version.
+ * It is kept in order to not break the compatibility.
+ * @param UnderrunBehaviour : Behavior of slave transmitter at underrun condition
+ * This parameter can be a value of @ref SPI_Underrun_Behaviour.
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection,
+ uint32_t UnderrunBehaviour)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(UnderrunDetection);
+
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Check State and Insure that Underrun configuration is managed only by Salve */
+ if ((hspi->State != HAL_SPI_STATE_READY) || (hspi->Init.Mode != SPI_MODE_SLAVE))
+ {
+ errorcode = HAL_BUSY;
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SPI_UNDERRUN_BEHAVIOUR(UnderrunBehaviour));
+
+ /* Check if the SPI is disabled to edit CFG1 register */
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Configure Underrun fields */
+ MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, UnderrunBehaviour);
+ }
+ else
+ {
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Configure Underrun fields */
+ MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, UnderrunBehaviour);
+
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Set Autonomous Mode configuration
+ * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPIx peripheral.
+ * @param sConfig Pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information of the autonomous mode for the specified SPIx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPIEx_SetConfigAutonomousMode(SPI_HandleTypeDef *hspi, SPI_AutonomousModeConfTypeDef *sConfig)
+{
+ if (hspi->State == HAL_SPI_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ hspi->State = HAL_SPI_STATE_BUSY;
+
+ /* Check the parameters */
+ assert_param(IS_SPI_TRIG_SOURCE(hspi->Instance, sConfig->TriggerSelection));
+
+ assert_param(IS_SPI_AUTO_MODE_TRG_POL(sConfig->TriggerPolarity));
+
+ /* Disable the selected SPI peripheral to be able to configure AUTOCR */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* SPIx AUTOCR Configuration */
+ WRITE_REG(hspi->Instance->AUTOCR, (sConfig->TriggerState | ((sConfig->TriggerSelection) & SPI_AUTOCR_TRIGSEL_Msk) |
+ sConfig->TriggerPolarity));
+
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Get Autonomous Mode configuration
+ * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPIx peripheral.
+ * @param sConfig Pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information of the autonomous mode for the specified SPIx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPIEx_GetConfigAutonomousMode(SPI_HandleTypeDef *hspi, SPI_AutonomousModeConfTypeDef *sConfig)
+{
+ uint32_t autocr_tmp;
+
+ autocr_tmp = hspi->Instance->AUTOCR;
+
+ sConfig->TriggerState = (autocr_tmp & SPI_AUTOCR_TRIGEN);
+ if (IS_SPI_GRP2_INSTANCE(hspi->Instance))
+ {
+ sConfig->TriggerSelection = ((autocr_tmp & SPI_AUTOCR_TRIGSEL) | SPI_TRIG_GRP2);
+ }
+ else
+ {
+ sConfig->TriggerSelection = ((autocr_tmp & SPI_AUTOCR_TRIGSEL) | SPI_TRIG_GRP1);
+ }
+ sConfig->TriggerPolarity = (autocr_tmp & SPI_AUTOCR_TRIGPOL);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Clear Autonomous Mode configuration
+ * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPIx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPIEx_ClearConfigAutonomousMode(SPI_HandleTypeDef *hspi)
+{
+ if (hspi->State == HAL_SPI_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ hspi->State = HAL_SPI_STATE_BUSY;
+
+ /* Disable the selected SPI peripheral to be able to clear AUTOCR */
+ __HAL_SPI_DISABLE(hspi);
+
+ CLEAR_REG(hspi->Instance->AUTOCR);
+
+ /* Enable the selected SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sram.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sram.c
new file mode 100644
index 00000000..1d340c94
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sram.c
@@ -0,0 +1,1233 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_sram.c
+ * @author MCD Application Team
+ * @brief SRAM HAL module driver.
+ * This file provides a generic firmware to drive SRAM memories
+ * mounted as external device.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This driver is a generic layered driver which contains a set of APIs used to
+ control SRAM memories. It uses the FMC layer functions to interface
+ with SRAM devices.
+ The following sequence should be followed to configure the FMC to interface
+ with SRAM/PSRAM memories:
+
+ (#) Declare a SRAM_HandleTypeDef handle structure, for example:
+ SRAM_HandleTypeDef hsram; and:
+
+ (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
+ values of the structure member.
+
+ (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
+ base register instance for NOR or SRAM device
+
+ (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
+ base register instance for NOR or SRAM extended mode
+
+ (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
+ mode timings; for example:
+ FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming;
+ and fill its fields with the allowed values of the structure member.
+
+ (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
+ performs the following sequence:
+
+ (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
+ (##) Control register configuration using the FMC NORSRAM interface function
+ FMC_NORSRAM_Init()
+ (##) Timing register configuration using the FMC NORSRAM interface function
+ FMC_NORSRAM_Timing_Init()
+ (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
+ FMC_NORSRAM_Extended_Timing_Init()
+ (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
+
+ (#) At this stage you can perform read/write accesses from/to the memory connected
+ to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
+ following APIs:
+ (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
+ (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
+
+ (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
+ HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
+
+ (#) You can continuously monitor the SRAM device HAL state by calling the function
+ HAL_SRAM_GetState()
+
+ *** Callback registration ***
+ =============================================
+ [..]
+ The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ Use Functions @ref HAL_SRAM_RegisterCallback() to register a user callback,
+ it allows to register following callbacks:
+ (+) MspInitCallback : SRAM MspInit.
+ (+) MspDeInitCallback : SRAM MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_SRAM_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function. It allows to reset following callbacks:
+ (+) MspInitCallback : SRAM MspInit.
+ (+) MspDeInitCallback : SRAM MspDeInit.
+ This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+ By default, after the @ref HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET
+ all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_SRAM_Init
+ and @ref HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_SRAM_Init and @ref HAL_SRAM_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_SRAM_RegisterCallback before calling @ref HAL_SRAM_DeInit
+ or @ref HAL_SRAM_Init function.
+
+ When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+
+/** @defgroup SRAM SRAM
+ * @brief SRAM driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void SRAM_DMACplt(DMA_HandleTypeDef *hdma);
+static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma);
+static void SRAM_DMAError(DMA_HandleTypeDef *hdma);
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SRAM_Exported_Functions SRAM Exported Functions
+ * @{
+ */
+
+/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions.
+ *
+ @verbatim
+ ==============================================================================
+ ##### SRAM Initialization and de_initialization functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to initialize/de-initialize
+ the SRAM memory
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Performs the SRAM device initialization sequence
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param Timing Pointer to SRAM control timing structure
+ * @param ExtTiming Pointer to SRAM extended mode timing structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing,
+ FMC_NORSRAM_TimingTypeDef *ExtTiming)
+{
+ /* Check the SRAM handle parameter */
+ if (hsram == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ if (hsram->State == HAL_SRAM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hsram->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+ if (hsram->MspInitCallback == NULL)
+ {
+ hsram->MspInitCallback = HAL_SRAM_MspInit;
+ }
+ hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
+ hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
+
+ /* Init the low level hardware */
+ hsram->MspInitCallback(hsram);
+#else
+ /* Initialize the low level hardware (MSP) */
+ HAL_SRAM_MspInit(hsram);
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
+ }
+
+ /* Initialize SRAM control Interface */
+ (void)FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
+
+ /* Initialize SRAM timing Interface */
+ (void)FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
+
+ /* Initialize SRAM extended mode timing Interface */
+ (void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,
+ hsram->Init.ExtendedMode);
+
+ /* Enable the NORSRAM device */
+ __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
+
+ /* Enable FMC Peripheral */
+ __FMC_ENABLE();
+
+ /* Initialize the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Performs the SRAM device De-initialization sequence.
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
+{
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+ if (hsram->MspDeInitCallback == NULL)
+ {
+ hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
+ }
+
+ /* DeInit the low level hardware */
+ hsram->MspDeInitCallback(hsram);
+#else
+ /* De-Initialize the low level hardware (MSP) */
+ HAL_SRAM_MspDeInit(hsram);
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
+
+ /* Configure the SRAM registers with their reset values */
+ (void)FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
+
+ /* Reset the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief SRAM MSP Init.
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval None
+ */
+__weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsram);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SRAM_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SRAM MSP DeInit.
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval None
+ */
+__weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsram);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SRAM_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DMA transfer complete callback.
+ * @param hdma pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval None
+ */
+__weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdma);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DMA transfer complete error callback.
+ * @param hdma pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval None
+ */
+__weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdma);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
+ * @brief Input Output and memory control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### SRAM Input and Output functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to use and control the SRAM memory
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Reads 8-bit buffer from SRAM memory.
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param pAddress Pointer to read start address
+ * @param pDstBuffer Pointer to destination buffer
+ * @param BufferSize Size of the buffer to read from memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
+ uint32_t BufferSize)
+{
+ uint32_t size;
+ __IO uint8_t *psramaddress = (uint8_t *)pAddress;
+ uint8_t *pdestbuff = pDstBuffer;
+ HAL_SRAM_StateTypeDef state = hsram->State;
+
+ /* Check the SRAM controller state */
+ if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Read data from memory */
+ for (size = BufferSize; size != 0U; size--)
+ {
+ *pdestbuff = *psramaddress;
+ pdestbuff++;
+ psramaddress++;
+ }
+
+ /* Update the SRAM controller state */
+ hsram->State = state;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Writes 8-bit buffer to SRAM memory.
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param pAddress Pointer to write start address
+ * @param pSrcBuffer Pointer to source buffer to write
+ * @param BufferSize Size of the buffer to write to memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
+ uint32_t BufferSize)
+{
+ uint32_t size;
+ __IO uint8_t *psramaddress = (uint8_t *)pAddress;
+ uint8_t *psrcbuff = pSrcBuffer;
+
+ /* Check the SRAM controller state */
+ if (hsram->State == HAL_SRAM_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Write data to memory */
+ for (size = BufferSize; size != 0U; size--)
+ {
+ *psramaddress = *psrcbuff;
+ psrcbuff++;
+ psramaddress++;
+ }
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Reads 16-bit buffer from SRAM memory.
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param pAddress Pointer to read start address
+ * @param pDstBuffer Pointer to destination buffer
+ * @param BufferSize Size of the buffer to read from memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
+ uint32_t BufferSize)
+{
+ uint32_t size;
+ __IO uint32_t *psramaddress = pAddress;
+ uint16_t *pdestbuff = pDstBuffer;
+ uint8_t limit;
+ HAL_SRAM_StateTypeDef state = hsram->State;
+
+ /* Check the SRAM controller state */
+ if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Check if the size is a 32-bits multiple */
+ limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
+
+ /* Read data from memory */
+ for (size = BufferSize; size != limit; size -= 2U)
+ {
+ *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
+ pdestbuff++;
+ *pdestbuff = (uint16_t)(((*psramaddress) & 0xFFFF0000U) >> 16U);
+ pdestbuff++;
+ psramaddress++;
+ }
+
+ /* Read last 16-bits if size is not 32-bits multiple */
+ if (limit != 0U)
+ {
+ *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
+ }
+
+ /* Update the SRAM controller state */
+ hsram->State = state;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Writes 16-bit buffer to SRAM memory.
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param pAddress Pointer to write start address
+ * @param pSrcBuffer Pointer to source buffer to write
+ * @param BufferSize Size of the buffer to write to memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
+ uint32_t BufferSize)
+{
+ uint32_t size;
+ __IO uint32_t *psramaddress = pAddress;
+ uint16_t *psrcbuff = pSrcBuffer;
+ uint8_t limit;
+
+ /* Check the SRAM controller state */
+ if (hsram->State == HAL_SRAM_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Check if the size is a 32-bits multiple */
+ limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
+
+ /* Write data to memory */
+ for (size = BufferSize; size != limit; size -= 2U)
+ {
+ *psramaddress = (uint32_t)(*psrcbuff);
+ psrcbuff++;
+ *psramaddress |= ((uint32_t)(*psrcbuff) << 16U);
+ psrcbuff++;
+ psramaddress++;
+ }
+
+ /* Write last 16-bits if size is not 32-bits multiple */
+ if (limit != 0U)
+ {
+ *psramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psramaddress) & 0xFFFF0000U);
+ }
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Reads 32-bit buffer from SRAM memory.
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param pAddress Pointer to read start address
+ * @param pDstBuffer Pointer to destination buffer
+ * @param BufferSize Size of the buffer to read from memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
+ uint32_t BufferSize)
+{
+ uint32_t size;
+ __IO uint32_t *psramaddress = pAddress;
+ uint32_t *pdestbuff = pDstBuffer;
+ HAL_SRAM_StateTypeDef state = hsram->State;
+
+ /* Check the SRAM controller state */
+ if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Read data from memory */
+ for (size = BufferSize; size != 0U; size--)
+ {
+ *pdestbuff = *psramaddress;
+ pdestbuff++;
+ psramaddress++;
+ }
+
+ /* Update the SRAM controller state */
+ hsram->State = state;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Writes 32-bit buffer to SRAM memory.
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param pAddress Pointer to write start address
+ * @param pSrcBuffer Pointer to source buffer to write
+ * @param BufferSize Size of the buffer to write to memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
+ uint32_t BufferSize)
+{
+ uint32_t size;
+ __IO uint32_t *psramaddress = pAddress;
+ uint32_t *psrcbuff = pSrcBuffer;
+
+ /* Check the SRAM controller state */
+ if (hsram->State == HAL_SRAM_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Write data to memory */
+ for (size = BufferSize; size != 0U; size--)
+ {
+ *psramaddress = *psrcbuff;
+ psrcbuff++;
+ psramaddress++;
+ }
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Reads a Words data from the SRAM memory using DMA transfer.
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param pAddress Pointer to read start address
+ * @param pDstBuffer Pointer to destination buffer
+ * @param BufferSize Size of the buffer to read from memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
+ uint32_t BufferSize)
+{
+ HAL_StatusTypeDef status;
+ HAL_SRAM_StateTypeDef state = hsram->State;
+ uint32_t size;
+ uint32_t data_width;
+
+ /* Check the SRAM controller state */
+ if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Configure DMA user callbacks */
+ if (state == HAL_SRAM_STATE_READY)
+ {
+ hsram->hdma->XferCpltCallback = SRAM_DMACplt;
+ }
+ else
+ {
+ hsram->hdma->XferCpltCallback = SRAM_DMACpltProt;
+ }
+ hsram->hdma->XferErrorCallback = SRAM_DMAError;
+
+ if ((hsram->hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if ((hsram->hdma->LinkedListQueue != 0U) && (hsram->hdma->LinkedListQueue->Head != 0U))
+ {
+ /* Check destination data width and set the size to be transferred */
+ data_width = hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2;
+
+ if (data_width == DMA_DEST_DATAWIDTH_WORD)
+ {
+ size = (BufferSize * 4U);
+ }
+ else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD)
+ {
+ size = (BufferSize * 2U);
+ }
+ else
+ {
+ size = (BufferSize);
+ }
+ /* Set Source , destination , buffer size */
+ /* Set DMA data size */
+ hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = size;
+ /* Set DMA source address */
+ hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pAddress;
+ /* Set DMA destination address */
+ hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pDstBuffer;
+
+ /* Enable the DMA Stream */
+ status = HAL_DMAEx_List_Start_IT(hsram->hdma);
+ }
+ else
+ {
+ /* Change SRAM state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ __HAL_UNLOCK(hsram);
+
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Check destination data width and set the size to be transferred */
+ data_width = hsram->hdma->Init.DestDataWidth;
+
+ if (data_width == DMA_DEST_DATAWIDTH_WORD)
+ {
+ size = (BufferSize * 4U);
+ }
+ else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD)
+ {
+ size = (BufferSize * 2U);
+ }
+ else
+ {
+ size = (BufferSize);
+ }
+
+ /* Enable the DMA Stream */
+ status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, size);
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Writes a Words data buffer to SRAM memory using DMA transfer.
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param pAddress Pointer to write start address
+ * @param pSrcBuffer Pointer to source buffer to write
+ * @param BufferSize Size of the buffer to write to memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
+ uint32_t BufferSize)
+{
+ HAL_StatusTypeDef status;
+ uint32_t size;
+ uint32_t data_width;
+
+ /* Check the SRAM controller state */
+ if (hsram->State == HAL_SRAM_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Configure DMA user callbacks */
+ hsram->hdma->XferCpltCallback = SRAM_DMACplt;
+ hsram->hdma->XferErrorCallback = SRAM_DMAError;
+
+ if ((hsram->hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if ((hsram->hdma->LinkedListQueue != 0U) && (hsram->hdma->LinkedListQueue->Head != 0U))
+ {
+ /* Check destination data width and set the size to be transferred */
+ data_width = hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2;
+
+ if (data_width == DMA_DEST_DATAWIDTH_WORD)
+ {
+ size = (BufferSize * 4U);
+ }
+ else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD)
+ {
+ size = (BufferSize * 2U);
+ }
+ else
+ {
+ size = (BufferSize);
+ }
+ /* Set Source , destination , buffer size */
+ /* Set DMA data size */
+ hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = size;
+ /* Set DMA source address */
+ hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pSrcBuffer;
+ /* Set DMA destination address */
+ hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pAddress;
+ /* Enable the DMA Stream */
+ status = HAL_DMAEx_List_Start_IT(hsram->hdma);
+ }
+ else
+ {
+ /* Change SRAM state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ __HAL_UNLOCK(hsram);
+
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Check destination data width and set the size to be transferred */
+ data_width = hsram->hdma->Init.DestDataWidth;
+
+ if (data_width == DMA_DEST_DATAWIDTH_WORD)
+ {
+ size = (BufferSize * 4U);
+ }
+ else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD)
+ {
+ size = (BufferSize * 2U);
+ }
+ else
+ {
+ size = (BufferSize);
+ }
+
+ /* Enable the DMA Stream */
+ status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, size);
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User SRAM Callback
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hsram : SRAM handle
+ * @param CallbackId : ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID
+ * @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID
+ * @param pCallback : pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
+ pSRAM_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ HAL_SRAM_StateTypeDef state;
+
+ if (pCallback == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hsram);
+
+ state = hsram->State;
+ if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED))
+ {
+ switch (CallbackId)
+ {
+ case HAL_SRAM_MSP_INIT_CB_ID :
+ hsram->MspInitCallback = pCallback;
+ break;
+ case HAL_SRAM_MSP_DEINIT_CB_ID :
+ hsram->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsram);
+ return status;
+}
+
+/**
+ * @brief Unregister a User SRAM Callback
+ * SRAM Callback is redirected to the weak (surcharged) predefined callback
+ * @param hsram : SRAM handle
+ * @param CallbackId : ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID
+ * @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID
+ * @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID
+ * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ HAL_SRAM_StateTypeDef state;
+
+ /* Process locked */
+ __HAL_LOCK(hsram);
+
+ state = hsram->State;
+ if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
+ {
+ switch (CallbackId)
+ {
+ case HAL_SRAM_MSP_INIT_CB_ID :
+ hsram->MspInitCallback = HAL_SRAM_MspInit;
+ break;
+ case HAL_SRAM_MSP_DEINIT_CB_ID :
+ hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
+ break;
+ case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
+ hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
+ break;
+ case HAL_SRAM_DMA_XFER_ERR_CB_ID :
+ hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (state == HAL_SRAM_STATE_RESET)
+ {
+ switch (CallbackId)
+ {
+ case HAL_SRAM_MSP_INIT_CB_ID :
+ hsram->MspInitCallback = HAL_SRAM_MspInit;
+ break;
+ case HAL_SRAM_MSP_DEINIT_CB_ID :
+ hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsram);
+ return status;
+}
+
+/**
+ * @brief Register a User SRAM Callback for DMA transfers
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hsram : SRAM handle
+ * @param CallbackId : ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID
+ * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
+ * @param pCallback : pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
+ pSRAM_DmaCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ HAL_SRAM_StateTypeDef state;
+
+ if (pCallback == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hsram);
+
+ state = hsram->State;
+ if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
+ {
+ switch (CallbackId)
+ {
+ case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
+ hsram->DmaXferCpltCallback = pCallback;
+ break;
+ case HAL_SRAM_DMA_XFER_ERR_CB_ID :
+ hsram->DmaXferErrorCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsram);
+ return status;
+}
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup SRAM_Exported_Functions_Group3 Control functions
+ * @brief Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### SRAM Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control dynamically
+ the SRAM interface.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables dynamically SRAM write operation.
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
+{
+ /* Check the SRAM controller state */
+ if (hsram->State == HAL_SRAM_STATE_PROTECTED)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Enable write operation */
+ (void)FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables dynamically SRAM write operation.
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
+{
+ /* Check the SRAM controller state */
+ if (hsram->State == HAL_SRAM_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Disable write operation */
+ (void)FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_PROTECTED;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### SRAM State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the SRAM controller
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the SRAM controller state
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval HAL state
+ */
+HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
+{
+ return hsram->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @brief DMA SRAM process complete callback.
+ * @param hdma : DMA handle
+ * @retval None
+ */
+static void SRAM_DMACplt(DMA_HandleTypeDef *hdma)
+{
+ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
+
+ /* Disable the DMA channel */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+ hsram->DmaXferCpltCallback(hdma);
+#else
+ HAL_SRAM_DMA_XferCpltCallback(hdma);
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA SRAM process complete callback.
+ * @param hdma : DMA handle
+ * @retval None
+ */
+static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
+{
+ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
+
+ /* Disable the DMA channel */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_PROTECTED;
+
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+ hsram->DmaXferCpltCallback(hdma);
+#else
+ HAL_SRAM_DMA_XferCpltCallback(hdma);
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA SRAM error callback.
+ * @param hdma : DMA handle
+ * @retval None
+ */
+static void SRAM_DMAError(DMA_HandleTypeDef *hdma)
+{
+ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
+
+ /* Disable the DMA channel */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_ERROR;
+
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+ hsram->DmaXferErrorCallback(hdma);
+#else
+ HAL_SRAM_DMA_XferErrorCallback(hdma);
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim.c
new file mode 100644
index 00000000..d2b540a8
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim.c
@@ -0,0 +1,8241 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_tim.c
+ * @author MCD Application Team
+ * @brief TIM HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Timer (TIM) peripheral:
+ * + TIM Time Base Initialization
+ * + TIM Time Base Start
+ * + TIM Time Base Start Interruption
+ * + TIM Time Base Start DMA
+ * + TIM Output Compare/PWM Initialization
+ * + TIM Output Compare/PWM Channel Configuration
+ * + TIM Output Compare/PWM Start
+ * + TIM Output Compare/PWM Start Interruption
+ * + TIM Output Compare/PWM Start DMA
+ * + TIM Input Capture Initialization
+ * + TIM Input Capture Channel Configuration
+ * + TIM Input Capture Start
+ * + TIM Input Capture Start Interruption
+ * + TIM Input Capture Start DMA
+ * + TIM One Pulse Initialization
+ * + TIM One Pulse Channel Configuration
+ * + TIM One Pulse Start
+ * + TIM Encoder Interface Initialization
+ * + TIM Encoder Interface Start
+ * + TIM Encoder Interface Start Interruption
+ * + TIM Encoder Interface Start DMA
+ * + Commutation Event configuration with Interruption and DMA
+ * + TIM OCRef clear configuration
+ * + TIM External Clock configuration
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### TIMER Generic features #####
+ ==============================================================================
+ [..] The Timer features include:
+ (#) 16-bit up, down, up/down auto-reload counter.
+ (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
+ counter clock frequency either by any factor between 1 and 65536.
+ (#) Up to 4 independent channels for:
+ (++) Input Capture
+ (++) Output Compare
+ (++) PWM generation (Edge and Center-aligned Mode)
+ (++) One-pulse mode output
+ (#) Synchronization circuit to control the timer with external signals and to interconnect
+ several timers together.
+ (#) Supports incremental encoder for positioning purposes
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Initialize the TIM low level resources by implementing the following functions
+ depending on the selected feature:
+ (++) Time Base : HAL_TIM_Base_MspInit()
+ (++) Input Capture : HAL_TIM_IC_MspInit()
+ (++) Output Compare : HAL_TIM_OC_MspInit()
+ (++) PWM generation : HAL_TIM_PWM_MspInit()
+ (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
+ (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
+
+ (#) Initialize the TIM low level resources :
+ (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
+ (##) TIM pins configuration
+ (+++) Enable the clock for the TIM GPIOs using the following function:
+ __HAL_RCC_GPIOx_CLK_ENABLE();
+ (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+
+ (#) The external Clock can be configured, if needed (the default clock is the
+ internal clock from the APBx), using the following function:
+ HAL_TIM_ConfigClockSource, the clock configuration should be done before
+ any start function.
+
+ (#) Configure the TIM in the desired functioning mode using one of the
+ Initialization function of this driver:
+ (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
+ (++) HAL_TIM_OC_Init, HAL_TIM_OC_ConfigChannel and optionally HAL_TIMEx_OC_ConfigPulseOnCompare:
+ to use the Timer to generate an Output Compare signal.
+ (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
+ PWM signal.
+ (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
+ external signal.
+ (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
+ in One Pulse Mode.
+ (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
+
+ (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
+ (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
+ (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
+ (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
+ (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
+ (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
+ (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
+
+ (#) The DMA Burst is managed with the two following functions:
+ HAL_TIM_DMABurst_WriteStart()
+ HAL_TIM_DMABurst_ReadStart()
+
+ *** Callback registration ***
+ =============================================
+
+ [..]
+ The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ [..]
+ Use Function HAL_TIM_RegisterCallback() to register a callback.
+ HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
+ the Callback ID and a pointer to the user callback function.
+
+ [..]
+ Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default
+ weak function.
+ HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+
+ [..]
+ These functions allow to register/unregister following callbacks:
+ (+) Base_MspInitCallback : TIM Base Msp Init Callback.
+ (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
+ (+) IC_MspInitCallback : TIM IC Msp Init Callback.
+ (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback.
+ (+) OC_MspInitCallback : TIM OC Msp Init Callback.
+ (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback.
+ (+) PWM_MspInitCallback : TIM PWM Msp Init Callback.
+ (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback.
+ (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback.
+ (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.
+ (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback.
+ (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback.
+ (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback.
+ (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback.
+ (+) PeriodElapsedCallback : TIM Period Elapsed Callback.
+ (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback.
+ (+) TriggerCallback : TIM Trigger Callback.
+ (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback.
+ (+) IC_CaptureCallback : TIM Input Capture Callback.
+ (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback.
+ (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback.
+ (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback.
+ (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
+ (+) ErrorCallback : TIM Error Callback.
+ (+) CommutationCallback : TIM Commutation Callback.
+ (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback.
+ (+) BreakCallback : TIM Break Callback.
+ (+) Break2Callback : TIM Break2 Callback.
+ (+) EncoderIndexCallback : TIM Encoder Index Callback.
+ (+) DirectionChangeCallback : TIM Direction Change Callback
+ (+) IndexErrorCallback : TIM Index Error Callback.
+ (+) TransitionErrorCallback : TIM Transition Error Callback
+
+ [..]
+By default, after the Init and when the state is HAL_TIM_STATE_RESET
+all interrupt callbacks are set to the corresponding weak functions:
+ examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback().
+
+ [..]
+ Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
+ functionalities in the Init / DeInit only when these callbacks are null
+ (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
+ keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
+
+ [..]
+ Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
+ Exception done MspInit / MspDeInit that can be registered / unregistered
+ in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
+ thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using HAL_TIM_RegisterCallback() before calling DeInit or Init function.
+
+ [..]
+ When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup TIM TIM
+ * @brief TIM HAL module driver
+ * @{
+ */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup TIM_Private_Constants
+ * @{
+ */
+#define TIMx_AF2_OCRSEL TIM1_AF2_OCRSEL
+
+/**
+ * @}
+ */
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup TIM_Private_Functions
+ * @{
+ */
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter);
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter);
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter);
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+ TIM_SlaveConfigTypeDef *sSlaveConfig);
+/**
+ * @}
+ */
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup TIM_Exported_Functions TIM Exported Functions
+ * @{
+ */
+
+/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
+ * @brief Time Base functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Time Base functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM base.
+ (+) De-initialize the TIM base.
+ (+) Start the Time Base.
+ (+) Stop the Time Base.
+ (+) Start the Time Base and enable interrupt.
+ (+) Stop the Time Base and disable interrupt.
+ (+) Start the Time Base and enable DMA transfer.
+ (+) Stop the Time Base and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Time base Unit according to the specified
+ * parameters in the TIM_HandleTypeDef and initialize the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
+ * @param htim TIM Base handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
+{
+ /* Check the TIM handle allocation */
+ if (htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+ if (htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy weak callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->Base_MspInitCallback == NULL)
+ {
+ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->Base_MspInitCallback(htim);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ HAL_TIM_Base_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Set the Time Base configuration */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Initialize the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Initialize the TIM state*/
+ htim->State = HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM Base peripheral
+ * @param htim TIM Base handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->Base_MspDeInitCallback == NULL)
+ {
+ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->Base_MspDeInitCallback(htim);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_TIM_Base_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Change the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Base MSP.
+ * @param htim TIM Base handle
+ * @retval None
+ */
+__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_Base_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Base MSP.
+ * @param htim TIM Base handle
+ * @retval None
+ */
+__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_Base_MspDeInit could be implemented in the user file
+ */
+}
+
+
+/**
+ * @brief Starts the TIM Base generation.
+ * @param htim TIM Base handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
+{
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ /* Check the TIM state */
+ if (htim->State != HAL_TIM_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Base generation.
+ * @param htim TIM Base handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Base generation in interrupt mode.
+ * @param htim TIM Base handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
+{
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ /* Check the TIM state */
+ if (htim->State != HAL_TIM_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Enable the TIM Update interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Base generation in interrupt mode.
+ * @param htim TIM Base handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ /* Disable the TIM Update interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Base generation in DMA mode.
+ * @param htim TIM Base handle
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
+{
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+ /* Set the TIM state */
+ if (htim->State == HAL_TIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (htim->State == HAL_TIM_STATE_READY)
+ {
+ if ((pData == NULL) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the DMA Period elapsed callbacks */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+
+ /* Enable the TIM Update DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Base generation in DMA mode.
+ * @param htim TIM Base handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
+
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
+ * @brief TIM Output Compare functions
+ *
+@verbatim
+ ==============================================================================
+ ##### TIM Output Compare functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM Output Compare.
+ (+) De-initialize the TIM Output Compare.
+ (+) Start the TIM Output Compare.
+ (+) Stop the TIM Output Compare.
+ (+) Start the TIM Output Compare and enable interrupt.
+ (+) Stop the TIM Output Compare and disable interrupt.
+ (+) Start the TIM Output Compare and enable DMA transfer.
+ (+) Stop the TIM Output Compare and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Output Compare according to the specified
+ * parameters in the TIM_HandleTypeDef and initializes the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
+ * @param htim TIM Output Compare handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
+{
+ /* Check the TIM handle allocation */
+ if (htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+ if (htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy weak callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->OC_MspInitCallback == NULL)
+ {
+ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->OC_MspInitCallback(htim);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_OC_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Init the base time for the Output Compare */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Initialize the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Initialize the TIM state*/
+ htim->State = HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM peripheral
+ * @param htim TIM Output Compare handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->OC_MspDeInitCallback == NULL)
+ {
+ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->OC_MspDeInitCallback(htim);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_OC_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Change the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Output Compare MSP.
+ * @param htim TIM Output Compare handle
+ * @retval None
+ */
+__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_OC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Output Compare MSP.
+ * @param htim TIM Output Compare handle
+ * @retval None
+ */
+__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_OC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Check the TIM channel state */
+ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ /* Enable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation in interrupt mode.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Check the TIM channel state */
+ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Enable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Enable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation in interrupt mode.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Disable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation in DMA mode.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to TIM peripheral
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Set the TIM channel state */
+ if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
+ {
+ if ((pData == NULL) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+
+ /* Enable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+
+ /* Enable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Enable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation in DMA mode.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Disable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
+ * @brief TIM PWM functions
+ *
+@verbatim
+ ==============================================================================
+ ##### TIM PWM functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM PWM.
+ (+) De-initialize the TIM PWM.
+ (+) Start the TIM PWM.
+ (+) Stop the TIM PWM.
+ (+) Start the TIM PWM and enable interrupt.
+ (+) Stop the TIM PWM and disable interrupt.
+ (+) Start the TIM PWM and enable DMA transfer.
+ (+) Stop the TIM PWM and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM PWM Time Base according to the specified
+ * parameters in the TIM_HandleTypeDef and initializes the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
+ * @param htim TIM PWM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
+{
+ /* Check the TIM handle allocation */
+ if (htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+ if (htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy weak callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->PWM_MspInitCallback == NULL)
+ {
+ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->PWM_MspInitCallback(htim);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_PWM_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Init the base time for the PWM */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Initialize the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Initialize the TIM state*/
+ htim->State = HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM peripheral
+ * @param htim TIM PWM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->PWM_MspDeInitCallback == NULL)
+ {
+ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->PWM_MspDeInitCallback(htim);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_PWM_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Change the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM PWM MSP.
+ * @param htim TIM PWM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_PWM_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM PWM MSP.
+ * @param htim TIM PWM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_PWM_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the PWM signal generation.
+ * @param htim TIM handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Check the TIM channel state */
+ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the PWM signal generation.
+ * @param htim TIM PWM handle
+ * @param Channel TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the PWM signal generation in interrupt mode.
+ * @param htim TIM PWM handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Check the TIM channel state */
+ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Enable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Stops the PWM signal generation in interrupt mode.
+ * @param htim TIM PWM handle
+ * @param Channel TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Disable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Starts the TIM PWM signal generation in DMA mode.
+ * @param htim TIM PWM handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to TIM peripheral
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Set the TIM channel state */
+ if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
+ {
+ if ((pData == NULL) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+
+ /* Enable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Output Capture/Compare 3 request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Stops the TIM PWM signal generation in DMA mode.
+ * @param htim TIM PWM handle
+ * @param Channel TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Disable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
+ * @brief TIM Input Capture functions
+ *
+@verbatim
+ ==============================================================================
+ ##### TIM Input Capture functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM Input Capture.
+ (+) De-initialize the TIM Input Capture.
+ (+) Start the TIM Input Capture.
+ (+) Stop the TIM Input Capture.
+ (+) Start the TIM Input Capture and enable interrupt.
+ (+) Stop the TIM Input Capture and disable interrupt.
+ (+) Start the TIM Input Capture and enable DMA transfer.
+ (+) Stop the TIM Input Capture and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Input Capture Time base according to the specified
+ * parameters in the TIM_HandleTypeDef and initializes the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
+ * @param htim TIM Input Capture handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
+{
+ /* Check the TIM handle allocation */
+ if (htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+ if (htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy weak callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->IC_MspInitCallback == NULL)
+ {
+ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->IC_MspInitCallback(htim);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_IC_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Init the base time for the input capture */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Initialize the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Initialize the TIM state*/
+ htim->State = HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM peripheral
+ * @param htim TIM Input Capture handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->IC_MspDeInitCallback == NULL)
+ {
+ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->IC_MspDeInitCallback(htim);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_IC_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Change the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Input Capture MSP.
+ * @param htim TIM Input Capture handle
+ * @retval None
+ */
+__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_IC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Input Capture MSP.
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_IC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM Input Capture measurement.
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ uint32_t tmpsmcr;
+ HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Check the TIM channel state */
+ if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ /* Enable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Input Capture measurement.
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Input Capture measurement in interrupt mode.
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpsmcr;
+
+ HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Check the TIM channel state */
+ if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Enable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Enable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Stops the TIM Input Capture measurement in interrupt mode.
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Disable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Starts the TIM Input Capture measurement in DMA mode.
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param pData The destination Buffer address.
+ * @param Length The length of data to be transferred from TIM peripheral to memory.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpsmcr;
+
+ HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+ /* Set the TIM channel state */
+ if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
+ {
+ if ((pData == NULL) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ /* Enable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Stops the TIM Input Capture measurement in DMA mode.
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
+ /* Return function status */
+ return status;
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
+ * @brief TIM One Pulse functions
+ *
+@verbatim
+ ==============================================================================
+ ##### TIM One Pulse functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM One Pulse.
+ (+) De-initialize the TIM One Pulse.
+ (+) Start the TIM One Pulse.
+ (+) Stop the TIM One Pulse.
+ (+) Start the TIM One Pulse and enable interrupt.
+ (+) Stop the TIM One Pulse and disable interrupt.
+ (+) Start the TIM One Pulse and enable DMA transfer.
+ (+) Stop the TIM One Pulse and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM One Pulse Time Base according to the specified
+ * parameters in the TIM_HandleTypeDef and initializes the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
+ * @note When the timer instance is initialized in One Pulse mode, timer
+ * channels 1 and channel 2 are reserved and cannot be used for other
+ * purpose.
+ * @param htim TIM One Pulse handle
+ * @param OnePulseMode Select the One pulse mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
+ * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
+{
+ /* Check the TIM handle allocation */
+ if (htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_OPM_MODE(OnePulseMode));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+ if (htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy weak callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->OnePulse_MspInitCallback == NULL)
+ {
+ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->OnePulse_MspInitCallback(htim);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_OnePulse_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Configure the Time base in the One Pulse Mode */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Reset the OPM Bit */
+ htim->Instance->CR1 &= ~TIM_CR1_OPM;
+
+ /* Configure the OPM Mode */
+ htim->Instance->CR1 |= OnePulseMode;
+
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Initialize the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Initialize the TIM state*/
+ htim->State = HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM One Pulse
+ * @param htim TIM One Pulse handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->OnePulse_MspDeInitCallback == NULL)
+ {
+ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->OnePulse_MspDeInitCallback(htim);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_TIM_OnePulse_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM One Pulse MSP.
+ * @param htim TIM One Pulse handle
+ * @retval None
+ */
+__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_OnePulse_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM One Pulse MSP.
+ * @param htim TIM One Pulse handle
+ * @retval None
+ */
+__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM One Pulse signal generation.
+ * @note Though OutputChannel parameter is deprecated and ignored by the function
+ * it has been kept to avoid HAL_TIM API compatibility break.
+ * @note The pulse output channel is determined when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel See note above
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(OutputChannel);
+
+ /* Check the TIM channels state */
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ /* Enable the Capture compare and the Input Capture channels
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+ whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+ No need to enable the counter, it's enabled automatically by hardware
+ (the counter starts in response to a stimulus and generate a pulse */
+
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM One Pulse signal generation.
+ * @note Though OutputChannel parameter is deprecated and ignored by the function
+ * it has been kept to avoid HAL_TIM API compatibility break.
+ * @note The pulse output channel is determined when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel See note above
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(OutputChannel);
+
+ /* Disable the Capture compare and the Input Capture channels
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+ whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM One Pulse signal generation in interrupt mode.
+ * @note Though OutputChannel parameter is deprecated and ignored by the function
+ * it has been kept to avoid HAL_TIM API compatibility break.
+ * @note The pulse output channel is determined when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel See note above
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(OutputChannel);
+
+ /* Check the TIM channels state */
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ /* Enable the Capture compare and the Input Capture channels
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+ whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+ No need to enable the counter, it's enabled automatically by hardware
+ (the counter starts in response to a stimulus and generate a pulse */
+
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM One Pulse signal generation in interrupt mode.
+ * @note Though OutputChannel parameter is deprecated and ignored by the function
+ * it has been kept to avoid HAL_TIM API compatibility break.
+ * @note The pulse output channel is determined when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel See note above
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(OutputChannel);
+
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+
+ /* Disable the Capture compare and the Input Capture channels
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+ whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
+ * @brief TIM Encoder functions
+ *
+@verbatim
+ ==============================================================================
+ ##### TIM Encoder functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM Encoder.
+ (+) De-initialize the TIM Encoder.
+ (+) Start the TIM Encoder.
+ (+) Stop the TIM Encoder.
+ (+) Start the TIM Encoder and enable interrupt.
+ (+) Stop the TIM Encoder and disable interrupt.
+ (+) Start the TIM Encoder and enable DMA transfer.
+ (+) Stop the TIM Encoder and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Encoder Interface and initialize the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
+ * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together
+ * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
+ * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
+ * @note When the timer instance is initialized in Encoder mode, timer
+ * channels 1 and channel 2 are reserved and cannot be used for other
+ * purpose.
+ * @param htim TIM Encoder Interface handle
+ * @param sConfig TIM Encoder Interface configuration structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
+{
+ uint32_t tmpsmcr;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+
+ /* Check the TIM handle allocation */
+ if (htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+ assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
+ assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
+ assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
+ assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
+ assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
+
+ if (htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy weak callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->Encoder_MspInitCallback == NULL)
+ {
+ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->Encoder_MspInitCallback(htim);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_Encoder_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Reset the SMS and ECE bits */
+ htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
+
+ /* Configure the Time base in the Encoder Mode */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = htim->Instance->SMCR;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = htim->Instance->CCMR1;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = htim->Instance->CCER;
+
+ /* Set the encoder Mode */
+ tmpsmcr |= sConfig->EncoderMode;
+
+ /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+ tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
+ tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
+
+ /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
+ tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
+ tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
+ tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
+ tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
+
+ /* Set the TI1 and the TI2 Polarities */
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
+ tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
+ tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
+
+ /* Write to TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+
+ /* Write to TIMx CCMR1 */
+ htim->Instance->CCMR1 = tmpccmr1;
+
+ /* Write to TIMx CCER */
+ htim->Instance->CCER = tmpccer;
+
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Initialize the TIM state*/
+ htim->State = HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief DeInitializes the TIM Encoder interface
+ * @param htim TIM Encoder Interface handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->Encoder_MspDeInitCallback == NULL)
+ {
+ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->Encoder_MspDeInitCallback(htim);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_TIM_Encoder_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Encoder Interface MSP.
+ * @param htim TIM Encoder Interface handle
+ * @retval None
+ */
+__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_Encoder_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Encoder Interface MSP.
+ * @param htim TIM Encoder Interface handle
+ * @retval None
+ */
+__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM Encoder Interface.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+ /* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Set the TIM channel(s) state */
+ if (Channel == TIM_CHANNEL_1)
+ {
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else if (Channel == TIM_CHANNEL_2)
+ {
+ if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else
+ {
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+
+ /* Enable the encoder interface channels */
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ break;
+ }
+
+ default :
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ break;
+ }
+ }
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Encoder Interface.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1 and 2
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ break;
+ }
+
+ default :
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ break;
+ }
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel(s) state */
+ if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
+ {
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Encoder Interface in interrupt mode.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+ /* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Set the TIM channel(s) state */
+ if (Channel == TIM_CHANNEL_1)
+ {
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else if (Channel == TIM_CHANNEL_2)
+ {
+ if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else
+ {
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+
+ /* Enable the encoder interface channels */
+ /* Enable the capture compare Interrupts 1 and/or 2 */
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ default :
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Encoder Interface in interrupt mode.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1 and 2
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+ if (Channel == TIM_CHANNEL_1)
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare Interrupts 1 */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ }
+ else if (Channel == TIM_CHANNEL_2)
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare Interrupts 2 */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+ else
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare Interrupts 1 and 2 */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel(s) state */
+ if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
+ {
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Encoder Interface in DMA mode.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @param pData1 The destination Buffer address for IC1.
+ * @param pData2 The destination Buffer address for IC2.
+ * @param Length The length of data to be transferred from TIM peripheral to memory.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
+ uint32_t *pData2, uint16_t Length)
+{
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+ /* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Set the TIM channel(s) state */
+ if (Channel == TIM_CHANNEL_1)
+ {
+ if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
+ {
+ if ((pData1 == NULL) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ }
+ else if (Channel == TIM_CHANNEL_2)
+ {
+ if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
+ {
+ if ((pData2 == NULL) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
+ {
+ if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Input Capture DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
+ /* Enable the DMA channel */
+ if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Input Capture DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ break;
+ }
+
+ default:
+ {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+ /* Enable the TIM Input Capture DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ /* Enable the TIM Input Capture DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ break;
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Encoder Interface in DMA mode.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1 and 2
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+ if (Channel == TIM_CHANNEL_1)
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare DMA Request 1 */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ }
+ else if (Channel == TIM_CHANNEL_2)
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare DMA Request 2 */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ }
+ else
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare DMA Request 1 and 2 */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel(s) state */
+ if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
+ {
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+ * @brief TIM IRQ handler management
+ *
+@verbatim
+ ==============================================================================
+ ##### IRQ handler management #####
+ ==============================================================================
+ [..]
+ This section provides Timer IRQ handler function.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief This function handles TIM interrupts requests.
+ * @param htim TIM handle
+ * @retval None
+ */
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
+{
+ /* Capture compare 1 event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
+ {
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
+ {
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+ /* Input capture event */
+ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
+ {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureCallback(htim);
+#else
+ HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ /* Output compare event */
+ else
+ {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->OC_DelayElapsedCallback(htim);
+ htim->PWM_PulseFinishedCallback(htim);
+#else
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ }
+ /* Capture compare 2 event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
+ {
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ /* Input capture event */
+ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
+ {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureCallback(htim);
+#else
+ HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ /* Output compare event */
+ else
+ {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->OC_DelayElapsedCallback(htim);
+ htim->PWM_PulseFinishedCallback(htim);
+#else
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ /* Capture compare 3 event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
+ {
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ /* Input capture event */
+ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
+ {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureCallback(htim);
+#else
+ HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ /* Output compare event */
+ else
+ {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->OC_DelayElapsedCallback(htim);
+ htim->PWM_PulseFinishedCallback(htim);
+#else
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ /* Capture compare 4 event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
+ {
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ /* Input capture event */
+ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
+ {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureCallback(htim);
+#else
+ HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ /* Output compare event */
+ else
+ {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->OC_DelayElapsedCallback(htim);
+ htim->PWM_PulseFinishedCallback(htim);
+#else
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ /* TIM Update event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
+ {
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PeriodElapsedCallback(htim);
+#else
+ HAL_TIM_PeriodElapsedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ }
+ /* TIM Break input event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
+ {
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->BreakCallback(htim);
+#else
+ HAL_TIMEx_BreakCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ }
+ /* TIM Break2 input event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
+ {
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
+ {
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->Break2Callback(htim);
+#else
+ HAL_TIMEx_Break2Callback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ }
+ /* TIM Trigger detection event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
+ {
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->TriggerCallback(htim);
+#else
+ HAL_TIM_TriggerCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ }
+ /* TIM commutation event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
+ {
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->CommutationCallback(htim);
+#else
+ HAL_TIMEx_CommutCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ }
+ /* TIM Encoder index event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_IDX) != RESET)
+ {
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_IDX) != RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_IDX);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->EncoderIndexCallback(htim);
+#else
+ HAL_TIMEx_EncoderIndexCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ }
+ /* TIM Direction change event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_DIR) != RESET)
+ {
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_DIR) != RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_DIR);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->DirectionChangeCallback(htim);
+#else
+ HAL_TIMEx_DirectionChangeCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ }
+ /* TIM Index error event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_IERR) != RESET)
+ {
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_IERR) != RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_IERR);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IndexErrorCallback(htim);
+#else
+ HAL_TIMEx_IndexErrorCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ }
+ /* TIM Transition error event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TERR) != RESET)
+ {
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TERR) != RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_TERR);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->TransitionErrorCallback(htim);
+#else
+ HAL_TIMEx_TransitionErrorCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
+ * @brief TIM Peripheral Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
+ (+) Configure External Clock source.
+ (+) Configure Complementary channels, break features and dead time.
+ (+) Configure Master and the Slave synchronization.
+ (+) Configure the DMA Burst Mode.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the TIM Output Compare Channels according to the specified
+ * parameters in the TIM_OC_InitTypeDef.
+ * @param htim TIM Output Compare handle
+ * @param sConfig TIM Output Compare configuration structure
+ * @param Channel TIM Channels to configure
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
+ TIM_OC_InitTypeDef *sConfig,
+ uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CHANNELS(Channel));
+ assert_param(IS_TIM_OC_CHANNEL_MODE(sConfig->OCMode, Channel));
+ assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ /* Configure the TIM Channel 1 in Output Compare */
+ TIM_OC1_SetConfig(htim->Instance, sConfig);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Configure the TIM Channel 2 in Output Compare */
+ TIM_OC2_SetConfig(htim->Instance, sConfig);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+ /* Configure the TIM Channel 3 in Output Compare */
+ TIM_OC3_SetConfig(htim->Instance, sConfig);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+ /* Configure the TIM Channel 4 in Output Compare */
+ TIM_OC4_SetConfig(htim->Instance, sConfig);
+ break;
+ }
+
+ case TIM_CHANNEL_5:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
+
+ /* Configure the TIM Channel 5 in Output Compare */
+ TIM_OC5_SetConfig(htim->Instance, sConfig);
+ break;
+ }
+
+ case TIM_CHANNEL_6:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
+
+ /* Configure the TIM Channel 6 in Output Compare */
+ TIM_OC6_SetConfig(htim->Instance, sConfig);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ __HAL_UNLOCK(htim);
+
+ return status;
+}
+
+/**
+ * @brief Initializes the TIM Input Capture Channels according to the specified
+ * parameters in the TIM_IC_InitTypeDef.
+ * @param htim TIM IC handle
+ * @param sConfig TIM Input Capture configuration structure
+ * @param Channel TIM Channel to configure
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
+ assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
+ assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ if (Channel == TIM_CHANNEL_1)
+ {
+ /* TI1 Configuration */
+ TIM_TI1_SetConfig(htim->Instance,
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
+
+ /* Reset the IC1PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+ /* Set the IC1PSC value */
+ htim->Instance->CCMR1 |= sConfig->ICPrescaler;
+ }
+ else if (Channel == TIM_CHANNEL_2)
+ {
+ /* TI2 Configuration */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ TIM_TI2_SetConfig(htim->Instance,
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
+
+ /* Reset the IC2PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+ /* Set the IC2PSC value */
+ htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
+ }
+ else if (Channel == TIM_CHANNEL_3)
+ {
+ /* TI3 Configuration */
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+ TIM_TI3_SetConfig(htim->Instance,
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
+
+ /* Reset the IC3PSC Bits */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
+
+ /* Set the IC3PSC value */
+ htim->Instance->CCMR2 |= sConfig->ICPrescaler;
+ }
+ else if (Channel == TIM_CHANNEL_4)
+ {
+ /* TI4 Configuration */
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+ TIM_TI4_SetConfig(htim->Instance,
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
+
+ /* Reset the IC4PSC Bits */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
+
+ /* Set the IC4PSC value */
+ htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+
+ __HAL_UNLOCK(htim);
+
+ return status;
+}
+
+/**
+ * @brief Initializes the TIM PWM channels according to the specified
+ * parameters in the TIM_OC_InitTypeDef.
+ * @param htim TIM PWM handle
+ * @param sConfig TIM PWM configuration structure
+ * @param Channel TIM Channels to be configured
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
+ TIM_OC_InitTypeDef *sConfig,
+ uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CHANNELS(Channel));
+ assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
+ assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+ assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ /* Configure the Channel 1 in PWM mode */
+ TIM_OC1_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel1 */
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
+ htim->Instance->CCMR1 |= sConfig->OCFastMode;
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Configure the Channel 2 in PWM mode */
+ TIM_OC2_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel2 */
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
+ htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+ /* Configure the Channel 3 in PWM mode */
+ TIM_OC3_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel3 */
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
+ htim->Instance->CCMR2 |= sConfig->OCFastMode;
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+ /* Configure the Channel 4 in PWM mode */
+ TIM_OC4_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel4 */
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
+ htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
+ break;
+ }
+
+ case TIM_CHANNEL_5:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
+
+ /* Configure the Channel 5 in PWM mode */
+ TIM_OC5_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel5*/
+ htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
+ htim->Instance->CCMR3 |= sConfig->OCFastMode;
+ break;
+ }
+
+ case TIM_CHANNEL_6:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
+
+ /* Configure the Channel 6 in PWM mode */
+ TIM_OC6_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel6 */
+ htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
+ htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ __HAL_UNLOCK(htim);
+
+ return status;
+}
+
+/**
+ * @brief Initializes the TIM One Pulse Channels according to the specified
+ * parameters in the TIM_OnePulse_InitTypeDef.
+ * @param htim TIM One Pulse handle
+ * @param sConfig TIM One Pulse configuration structure
+ * @param OutputChannel TIM output channel to configure
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @param InputChannel TIM input Channel to configure
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @note To output a waveform with a minimum delay user can enable the fast
+ * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
+ * output is forced in response to the edge detection on TIx input,
+ * without taking in account the comparison.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
+ uint32_t OutputChannel, uint32_t InputChannel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ TIM_OC_InitTypeDef temp1;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
+ assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
+
+ if (OutputChannel != InputChannel)
+ {
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Extract the Output compare configuration from sConfig structure */
+ temp1.OCMode = sConfig->OCMode;
+ temp1.Pulse = sConfig->Pulse;
+ temp1.OCPolarity = sConfig->OCPolarity;
+ temp1.OCNPolarity = sConfig->OCNPolarity;
+ temp1.OCIdleState = sConfig->OCIdleState;
+ temp1.OCNIdleState = sConfig->OCNIdleState;
+
+ switch (OutputChannel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ TIM_OC1_SetConfig(htim->Instance, &temp1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ TIM_OC2_SetConfig(htim->Instance, &temp1);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ switch (InputChannel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
+ sConfig->ICSelection, sConfig->ICFilter);
+
+ /* Reset the IC1PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+ /* Select the Trigger source */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= TIM_TS_TI1FP1;
+
+ /* Select the Slave Mode */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
+ sConfig->ICSelection, sConfig->ICFilter);
+
+ /* Reset the IC2PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+ /* Select the Trigger source */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= TIM_TS_TI2FP2;
+
+ /* Select the Slave Mode */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+ }
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return status;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
+ * @param htim TIM handle
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @arg TIM_DMABASE_CCMR3
+ * @arg TIM_DMABASE_CCR5
+ * @arg TIM_DMABASE_CCR6
+ * @arg TIM_DMABASE_DTR2
+ * @arg TIM_DMABASE_ECR
+ * @arg TIM_DMABASE_TISEL
+ * @arg TIM_DMABASE_AF1
+ * @arg TIM_DMABASE_AF2
+ * @arg TIM_DMABASE_OR1
+ * @param BurstRequestSrc TIM DMA Request sources
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+ * @param BurstBuffer The Buffer address.
+ * @param BurstLength DMA Burst length. This parameter can be one value
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
+ * @note This function should be used only when BurstLength is equal to DMA data transfer length.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t BlockDataLength = 0;
+ uint32_t data_width;
+ DMA_HandleTypeDef *hdma = NULL;
+
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+ switch (BurstRequestSrc)
+ {
+ case TIM_DMA_UPDATE:
+ {
+ hdma = htim->hdma[TIM_DMA_ID_UPDATE];
+ break;
+ }
+ case TIM_DMA_CC1:
+ {
+ hdma = htim->hdma[TIM_DMA_ID_CC1];
+ break;
+ }
+ case TIM_DMA_CC2:
+ {
+ hdma = htim->hdma[TIM_DMA_ID_CC2];
+ break;
+ }
+ case TIM_DMA_CC3:
+ {
+ hdma = htim->hdma[TIM_DMA_ID_CC3];
+ break;
+ }
+ case TIM_DMA_CC4:
+ {
+ hdma = htim->hdma[TIM_DMA_ID_CC4];
+ break;
+ }
+ case TIM_DMA_COM:
+ {
+ hdma = htim->hdma[TIM_DMA_ID_COMMUTATION];
+ break;
+ }
+ case TIM_DMA_TRIGGER:
+ {
+ hdma = htim->hdma[TIM_DMA_ID_TRIGGER];
+ break;
+ }
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (hdma != NULL)
+ {
+
+ if (((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) && (hdma->LinkedListQueue != 0U)
+ && (hdma->LinkedListQueue->Head != 0U))
+ {
+ data_width = hdma->LinkedListQueue->Head->LinkRegisters[0] & DMA_CTR1_SDW_LOG2;
+ }
+ else
+ {
+ data_width = hdma->Init.SrcDataWidth;
+ }
+
+ switch (data_width)
+ {
+ case DMA_SRC_DATAWIDTH_BYTE:
+ {
+ BlockDataLength = (BurstLength >> TIM_DCR_DBL_Pos) + 1UL;
+ break;
+ }
+ case DMA_SRC_DATAWIDTH_HALFWORD:
+ {
+ BlockDataLength = ((BurstLength >> TIM_DCR_DBL_Pos) + 1UL) * 2UL;
+ break;
+ }
+ case DMA_SRC_DATAWIDTH_WORD:
+ {
+ BlockDataLength = ((BurstLength >> TIM_DCR_DBL_Pos) + 1UL) * 4UL;
+ break;
+ }
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+ BlockDataLength);
+ }
+
+
+ return status;
+}
+
+/**
+ * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
+ * @param htim TIM handle
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @arg TIM_DMABASE_CCMR3
+ * @arg TIM_DMABASE_CCR5
+ * @arg TIM_DMABASE_CCR6
+ * @arg TIM_DMABASE_DTR2
+ * @arg TIM_DMABASE_ECR
+ * @arg TIM_DMABASE_TISEL
+ * @arg TIM_DMABASE_AF1
+ * @arg TIM_DMABASE_AF2
+ * @arg TIM_DMABASE_OR1
+ * @param BurstRequestSrc TIM DMA Request sources
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+ * @param BurstBuffer The Buffer address.
+ * @param BurstLength DMA Burst length. This parameter can be one value
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
+ * @param DataLength Data length. This parameter can be one value
+ * between 1 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
+ uint32_t BurstLength, uint32_t DataLength)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpDBSS = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+ assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+ assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
+
+ if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
+ {
+ if ((BurstBuffer == NULL) && (BurstLength > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
+ }
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+ switch (BurstRequestSrc)
+ {
+ case TIM_DMA_UPDATE:
+ {
+ /* Set the DMA Period elapsed callbacks */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Configure the DMA Burst Source Selection */
+ tmpDBSS = TIM_DCR_DBSS_0;
+ break;
+ }
+ case TIM_DMA_CC1:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Configure the DMA Burst Source Selection */
+ tmpDBSS = TIM_DCR_DBSS_1;
+ break;
+ }
+ case TIM_DMA_CC2:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Configure the DMA Burst Source Selection */
+ tmpDBSS = (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0);
+ break;
+ }
+ case TIM_DMA_CC3:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Configure the DMA Burst Source Selection */
+ tmpDBSS = TIM_DCR_DBSS_2;
+ break;
+ }
+ case TIM_DMA_CC4:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Configure the DMA Burst Source Selection */
+ tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0);
+ break;
+ }
+ case TIM_DMA_COM:
+ {
+ /* Set the DMA commutation callbacks */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Configure the DMA Burst Source Selection */
+ tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1);
+ break;
+ }
+ case TIM_DMA_TRIGGER:
+ {
+ /* Set the DMA trigger callbacks */
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Configure the DMA Burst Source Selection */
+ tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0);
+ break;
+ }
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Configure the DMA Burst Mode */
+ htim->Instance->DCR = (BurstBaseAddress | BurstLength | tmpDBSS);
+ /* Enable the TIM DMA Request */
+ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Stops the TIM DMA Burst mode
+ * @param htim TIM handle
+ * @param BurstRequestSrc TIM DMA Request sources to disable
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+ /* Abort the DMA transfer (at least disable the DMA channel) */
+ switch (BurstRequestSrc)
+ {
+ case TIM_DMA_UPDATE:
+ {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+ break;
+ }
+ case TIM_DMA_CC1:
+ {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
+ }
+ case TIM_DMA_CC2:
+ {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
+ }
+ case TIM_DMA_CC3:
+ {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
+ }
+ case TIM_DMA_CC4:
+ {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ break;
+ }
+ case TIM_DMA_COM:
+ {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ break;
+ }
+ case TIM_DMA_TRIGGER:
+ {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ break;
+ }
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+ * @param htim TIM handle
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @arg TIM_DMABASE_CCMR3
+ * @arg TIM_DMABASE_CCR5
+ * @arg TIM_DMABASE_CCR6
+ * @arg TIM_DMABASE_DTR2
+ * @arg TIM_DMABASE_ECR
+ * @arg TIM_DMABASE_TISEL
+ * @arg TIM_DMABASE_AF1
+ * @arg TIM_DMABASE_AF2
+ * @arg TIM_DMABASE_OR1
+ * @param BurstRequestSrc TIM DMA Request sources
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+ * @param BurstBuffer The Buffer address.
+ * @param BurstLength DMA Burst length. This parameter can be one value
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
+ * @note This function should be used only when BurstLength is equal to DMA data transfer length.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t BlockDataLength = 0;
+ uint32_t data_width;
+ DMA_HandleTypeDef *hdma = NULL;
+
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+ switch (BurstRequestSrc)
+ {
+ case TIM_DMA_UPDATE:
+ {
+ hdma = htim->hdma[TIM_DMA_ID_UPDATE];
+ break;
+ }
+ case TIM_DMA_CC1:
+ {
+ hdma = htim->hdma[TIM_DMA_ID_CC1];
+ break;
+ }
+ case TIM_DMA_CC2:
+ {
+ hdma = htim->hdma[TIM_DMA_ID_CC2];
+ break;
+ }
+ case TIM_DMA_CC3:
+ {
+ hdma = htim->hdma[TIM_DMA_ID_CC3];
+ break;
+ }
+ case TIM_DMA_CC4:
+ {
+ hdma = htim->hdma[TIM_DMA_ID_CC4];
+ break;
+ }
+ case TIM_DMA_COM:
+ {
+ hdma = htim->hdma[TIM_DMA_ID_COMMUTATION];
+ break;
+ }
+ case TIM_DMA_TRIGGER:
+ {
+ hdma = htim->hdma[TIM_DMA_ID_TRIGGER];
+ break;
+ }
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (hdma != NULL)
+ {
+
+ if (((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) && (hdma->LinkedListQueue != 0U)
+ && (hdma->LinkedListQueue->Head != 0U))
+ {
+ data_width = hdma->LinkedListQueue->Head->LinkRegisters[0] & DMA_CTR1_SDW_LOG2;
+ }
+ else
+ {
+ data_width = hdma->Init.SrcDataWidth;
+ }
+
+ switch (data_width)
+
+ {
+ case DMA_SRC_DATAWIDTH_BYTE:
+ {
+ BlockDataLength = ((BurstLength) >> TIM_DCR_DBL_Pos) + 1UL;
+ break;
+ }
+ case DMA_SRC_DATAWIDTH_HALFWORD:
+ {
+ BlockDataLength = ((BurstLength >> TIM_DCR_DBL_Pos) + 1UL) * 2UL;
+ break;
+ }
+ case DMA_SRC_DATAWIDTH_WORD:
+ {
+ BlockDataLength = ((BurstLength >> TIM_DCR_DBL_Pos) + 1UL) * 4UL;
+ break;
+ }
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+ BlockDataLength);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+ * @param htim TIM handle
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @arg TIM_DMABASE_CCMR3
+ * @arg TIM_DMABASE_CCR5
+ * @arg TIM_DMABASE_CCR6
+ * @arg TIM_DMABASE_DTR2
+ * @arg TIM_DMABASE_ECR
+ * @arg TIM_DMABASE_TISEL
+ * @arg TIM_DMABASE_AF1
+ * @arg TIM_DMABASE_AF2
+ * @arg TIM_DMABASE_OR1
+ * @param BurstRequestSrc TIM DMA Request sources
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+ * @param BurstBuffer The Buffer address.
+ * @param BurstLength DMA Burst length. This parameter can be one value
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
+ * @param DataLength Data length. This parameter can be one value
+ * between 1 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
+ uint32_t BurstLength, uint32_t DataLength)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpDBSS = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+ assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+ assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
+
+ if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
+ {
+ if ((BurstBuffer == NULL) && (BurstLength > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
+ }
+ }
+ else
+ {
+ /* nothing to do */
+ }
+ switch (BurstRequestSrc)
+ {
+ case TIM_DMA_UPDATE:
+ {
+ /* Set the DMA Period elapsed callbacks */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Configure the DMA Burst Source Selection */
+ tmpDBSS = TIM_DCR_DBSS_0;
+ break;
+ }
+ case TIM_DMA_CC1:
+ {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Configure the DMA Burst Source Selection */
+ tmpDBSS = TIM_DCR_DBSS_1;
+ break;
+ }
+ case TIM_DMA_CC2:
+ {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Configure the DMA Burst Source Selection */
+ tmpDBSS = (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0);
+ break;
+ }
+ case TIM_DMA_CC3:
+ {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Configure the DMA Burst Source Selection */
+ tmpDBSS = TIM_DCR_DBSS_2;
+ break;
+ }
+ case TIM_DMA_CC4:
+ {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Configure the DMA Burst Source Selection */
+ tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0);
+ break;
+ }
+ case TIM_DMA_COM:
+ {
+ /* Set the DMA commutation callbacks */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Configure the DMA Burst Source Selection */
+ tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1);
+ break;
+ }
+ case TIM_DMA_TRIGGER:
+ {
+ /* Set the DMA trigger callbacks */
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Configure the DMA Burst Source Selection */
+ tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0);
+ break;
+ }
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Configure the DMA Burst Mode */
+ htim->Instance->DCR = (BurstBaseAddress | BurstLength | tmpDBSS);
+
+ /* Enable the TIM DMA Request */
+ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Stop the DMA burst reading
+ * @param htim TIM handle
+ * @param BurstRequestSrc TIM DMA Request sources to disable.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+ /* Abort the DMA transfer (at least disable the DMA channel) */
+ switch (BurstRequestSrc)
+ {
+ case TIM_DMA_UPDATE:
+ {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+ break;
+ }
+ case TIM_DMA_CC1:
+ {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
+ }
+ case TIM_DMA_CC2:
+ {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
+ }
+ case TIM_DMA_CC3:
+ {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
+ }
+ case TIM_DMA_CC4:
+ {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ break;
+ }
+ case TIM_DMA_COM:
+ {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ break;
+ }
+ case TIM_DMA_TRIGGER:
+ {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ break;
+ }
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Generate a software event
+ * @param htim TIM handle
+ * @param EventSource specifies the event source.
+ * This parameter can be one of the following values:
+ * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
+ * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
+ * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
+ * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
+ * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
+ * @arg TIM_EVENTSOURCE_COM: Timer COM event source
+ * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
+ * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
+ * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
+ * @note Basic timers can only generate an update event.
+ * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
+ * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant
+ * only for timer instances supporting break input(s).
+ * @retval HAL status
+ */
+
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_EVENT_SOURCE(EventSource));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ /* Change the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Set the event sources */
+ htim->Instance->EGR = EventSource;
+
+ /* Change the TIM state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the OCRef clear feature
+ * @param htim TIM handle
+ * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
+ * contains the OCREF clear feature and parameters for the TIM peripheral.
+ * @param Channel specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @arg TIM_CHANNEL_4: TIM Channel 4
+ * @arg TIM_CHANNEL_5: TIM Channel 5
+ * @arg TIM_CHANNEL_6: TIM Channel 6
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
+ TIM_ClearInputConfigTypeDef *sClearInputConfig,
+ uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ switch (sClearInputConfig->ClearInputSource)
+ {
+ case TIM_CLEARINPUTSOURCE_NONE:
+ {
+ /* Clear the OCREF clear selection bit and the the ETR Bits */
+ CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
+ break;
+ }
+
+ case TIM_CLEARINPUTSOURCE_COMP1:
+ case TIM_CLEARINPUTSOURCE_COMP2:
+ {
+ /* Clear the OCREF clear selection bit */
+ CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
+
+ /* Clear TIM1_AF2_OCRSEL (reset value) */
+ MODIFY_REG(htim->Instance->AF2, TIMx_AF2_OCRSEL, sClearInputConfig->ClearInputSource);
+ break;
+ }
+
+ case TIM_CLEARINPUTSOURCE_ETR:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
+ assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
+ assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
+
+ /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
+ if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
+ {
+ htim->State = HAL_TIM_STATE_READY;
+ __HAL_UNLOCK(htim);
+ return HAL_ERROR;
+ }
+
+ TIM_ETR_SetConfig(htim->Instance,
+ sClearInputConfig->ClearInputPrescaler,
+ sClearInputConfig->ClearInputPolarity,
+ sClearInputConfig->ClearInputFilter);
+
+ /* Set the OCREF clear selection bit */
+ SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
+
+ /* Clear TIMx_AF2_OCRSEL (reset value) */
+ CLEAR_BIT(htim->Instance->AF2, TIMx_AF2_OCRSEL);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+ {
+ /* Enable the OCREF clear feature for Channel 1 */
+ SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+ }
+ else
+ {
+ /* Disable the OCREF clear feature for Channel 1 */
+ CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+ }
+ break;
+ }
+ case TIM_CHANNEL_2:
+ {
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+ {
+ /* Enable the OCREF clear feature for Channel 2 */
+ SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
+ }
+ else
+ {
+ /* Disable the OCREF clear feature for Channel 2 */
+ CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
+ }
+ break;
+ }
+ case TIM_CHANNEL_3:
+ {
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+ {
+ /* Enable the OCREF clear feature for Channel 3 */
+ SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
+ }
+ else
+ {
+ /* Disable the OCREF clear feature for Channel 3 */
+ CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
+ }
+ break;
+ }
+ case TIM_CHANNEL_4:
+ {
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+ {
+ /* Enable the OCREF clear feature for Channel 4 */
+ SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+ }
+ else
+ {
+ /* Disable the OCREF clear feature for Channel 4 */
+ CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+ }
+ break;
+ }
+ case TIM_CHANNEL_5:
+ {
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+ {
+ /* Enable the OCREF clear feature for Channel 5 */
+ SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
+ }
+ else
+ {
+ /* Disable the OCREF clear feature for Channel 5 */
+ CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
+ }
+ break;
+ }
+ case TIM_CHANNEL_6:
+ {
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+ {
+ /* Enable the OCREF clear feature for Channel 6 */
+ SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
+ }
+ else
+ {
+ /* Disable the OCREF clear feature for Channel 6 */
+ CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
+ }
+ break;
+ }
+ default:
+ break;
+ }
+ }
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return status;
+}
+
+/**
+ * @brief Configures the clock source to be used
+ * @param htim TIM handle
+ * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
+ * contains the clock source information for the TIM peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpsmcr;
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
+
+ /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
+ tmpsmcr = htim->Instance->SMCR;
+ tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+ htim->Instance->SMCR = tmpsmcr;
+
+ switch (sClockSourceConfig->ClockSource)
+ {
+ case TIM_CLOCKSOURCE_INTERNAL:
+ {
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ break;
+ }
+
+ case TIM_CLOCKSOURCE_ETRMODE1:
+ {
+ /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
+ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+
+ /* Check ETR input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ /* Configure the ETR Clock source */
+ TIM_ETR_SetConfig(htim->Instance,
+ sClockSourceConfig->ClockPrescaler,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+
+ /* Select the External clock mode1 and the ETRF trigger */
+ tmpsmcr = htim->Instance->SMCR;
+ tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
+ /* Write to TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+ break;
+ }
+
+ case TIM_CLOCKSOURCE_ETRMODE2:
+ {
+ /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
+ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
+
+ /* Check ETR input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ /* Configure the ETR Clock source */
+ TIM_ETR_SetConfig(htim->Instance,
+ sClockSourceConfig->ClockPrescaler,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ /* Enable the External clock mode2 */
+ htim->Instance->SMCR |= TIM_SMCR_ECE;
+ break;
+ }
+
+ case TIM_CLOCKSOURCE_TI1:
+ {
+ /* Check whether or not the timer instance supports external clock mode 1 */
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+ /* Check TI1 input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ TIM_TI1_ConfigInputStage(htim->Instance,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
+ break;
+ }
+
+ case TIM_CLOCKSOURCE_TI2:
+ {
+ /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+ /* Check TI2 input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ TIM_TI2_ConfigInputStage(htim->Instance,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
+ break;
+ }
+
+ case TIM_CLOCKSOURCE_TI1ED:
+ {
+ /* Check whether or not the timer instance supports external clock mode 1 */
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+ /* Check TI1 input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ TIM_TI1_ConfigInputStage(htim->Instance,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
+ break;
+ }
+
+ case TIM_CLOCKSOURCE_ITR0:
+ case TIM_CLOCKSOURCE_ITR1:
+ case TIM_CLOCKSOURCE_ITR2:
+ case TIM_CLOCKSOURCE_ITR3:
+ case TIM_CLOCKSOURCE_ITR4:
+ case TIM_CLOCKSOURCE_ITR5:
+ case TIM_CLOCKSOURCE_ITR6:
+ case TIM_CLOCKSOURCE_ITR7:
+ case TIM_CLOCKSOURCE_ITR8:
+ case TIM_CLOCKSOURCE_ITR11:
+ {
+ /* Check whether or not the timer instance supports internal trigger input */
+ assert_param(IS_TIM_CLOCKSOURCE_INSTANCE((htim->Instance), sClockSourceConfig->ClockSource));
+
+ TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return status;
+}
+
+/**
+ * @brief Selects the signal connected to the TI1 input: direct from CH1_input
+ * or a XOR combination between CH1_input, CH2_input & CH3_input
+ * @param htim TIM handle.
+ * @param TI1_Selection Indicate whether or not channel 1 is connected to the
+ * output of a XOR gate.
+ * This parameter can be one of the following values:
+ * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
+ * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
+ * pins are connected to the TI1 input (XOR combination)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
+{
+ uint32_t tmpcr2;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = htim->Instance->CR2;
+
+ /* Reset the TI1 selection */
+ tmpcr2 &= ~TIM_CR2_TI1S;
+
+ /* Set the TI1 selection */
+ tmpcr2 |= TI1_Selection;
+
+ /* Write to TIMxCR2 */
+ htim->Instance->CR2 = tmpcr2;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the TIM in Slave mode
+ * @param htim TIM handle.
+ * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
+ * contains the selected trigger (internal trigger input, filtered
+ * timer input or external trigger input) and the Slave mode
+ * (Disable, Reset, Gated, Trigger, External clock mode 1, Reset + Trigger, Gated + Reset).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+ assert_param(IS_TIM_TRIGGER_INSTANCE(htim->Instance, sSlaveConfig->InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+ {
+ htim->State = HAL_TIM_STATE_READY;
+ __HAL_UNLOCK(htim);
+ return HAL_ERROR;
+ }
+
+ /* Disable Trigger Interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
+
+ /* Disable Trigger DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the TIM in Slave mode in interrupt mode
+ * @param htim TIM handle.
+ * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
+ * contains the selected trigger (internal trigger input, filtered
+ * timer input or external trigger input) and the Slave mode
+ * (Disable, Reset, Gated, Trigger, External clock mode 1, Reset + Trigger, Gated + Reset).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
+ TIM_SlaveConfigTypeDef *sSlaveConfig)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+ assert_param(IS_TIM_TRIGGER_INSTANCE(htim->Instance, sSlaveConfig->InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+ {
+ htim->State = HAL_TIM_STATE_READY;
+ __HAL_UNLOCK(htim);
+ return HAL_ERROR;
+ }
+
+ /* Enable Trigger Interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
+
+ /* Disable Trigger DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read the captured value from Capture Compare unit
+ * @param htim TIM handle.
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval Captured value
+ */
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ uint32_t tmpreg = 0U;
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ /* Return the capture 1 value */
+ tmpreg = htim->Instance->CCR1;
+
+ break;
+ }
+ case TIM_CHANNEL_2:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Return the capture 2 value */
+ tmpreg = htim->Instance->CCR2;
+
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+ /* Return the capture 3 value */
+ tmpreg = htim->Instance->CCR3;
+
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+ /* Return the capture 4 value */
+ tmpreg = htim->Instance->CCR4;
+
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ return tmpreg;
+}
+
+/**
+ * @brief Start the DMA data transfer.
+ * @param hdma DMA handle
+ * @param src : The source memory Buffer address.
+ * @param dst : The destination memory Buffer address.
+ * @param length : The size of a source block transfer in byte.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef TIM_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t src, uint32_t dst,
+ uint32_t length)
+{
+ HAL_StatusTypeDef status ;
+
+ /* Enable the DMA channel */
+ if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if ((hdma->LinkedListQueue != 0U) && (hdma->LinkedListQueue->Head != 0U))
+ {
+ /* Enable the DMA channel */
+ hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = length;
+ hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = src;
+ hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = dst;
+
+ status = HAL_DMAEx_List_Start_IT(hdma);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_DMA_Start_IT(hdma, src, dst, length);
+ }
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+ * @brief TIM Callbacks functions
+ *
+@verbatim
+ ==============================================================================
+ ##### TIM Callbacks functions #####
+ ==============================================================================
+ [..]
+ This section provides TIM callback functions:
+ (+) TIM Period elapsed callback
+ (+) TIM Output Compare callback
+ (+) TIM Input capture callback
+ (+) TIM Trigger callback
+ (+) TIM Error callback
+ (+) TIM Index callback
+ (+) TIM Direction change callback
+ (+) TIM Index error callback
+ (+) TIM Transition error callback
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Period elapsed callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Period elapsed half complete callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Output Compare callback in non-blocking mode
+ * @param htim TIM OC handle
+ * @retval None
+ */
+__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Input Capture callback in non-blocking mode
+ * @param htim TIM IC handle
+ * @retval None
+ */
+__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_IC_CaptureCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Input Capture half complete callback in non-blocking mode
+ * @param htim TIM IC handle
+ * @retval None
+ */
+__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief PWM Pulse finished callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief PWM Pulse finished half complete callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Hall Trigger detection callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_TriggerCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Hall Trigger detection half complete callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Timer error callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_ErrorCallback could be implemented in the user file
+ */
+}
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User TIM callback to be used instead of the weak predefined callback
+ * @param htim tim handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
+ * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
+ * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
+ * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
+ * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
+ * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
+ * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
+ * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
+ * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
+ * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
+ * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
+ * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
+ * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
+ * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
+ * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+ * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
+ * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+ * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
+ * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+ * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
+ * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
+ * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
+ * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
+ * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
+ * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
+ * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
+ * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
+ * @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID
+ * @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback ID
+ * @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID
+ * @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transition Error Callback ID
+ * @param pCallback pointer to the callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
+ pTIM_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(htim);
+
+ if (htim->State == HAL_TIM_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_TIM_BASE_MSPINIT_CB_ID :
+ htim->Base_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+ htim->Base_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_IC_MSPINIT_CB_ID :
+ htim->IC_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_IC_MSPDEINIT_CB_ID :
+ htim->IC_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_OC_MSPINIT_CB_ID :
+ htim->OC_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_OC_MSPDEINIT_CB_ID :
+ htim->OC_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_MSPINIT_CB_ID :
+ htim->PWM_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+ htim->PWM_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+ htim->OnePulse_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+ htim->OnePulse_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+ htim->Encoder_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+ htim->Encoder_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+ htim->HallSensor_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+ htim->HallSensor_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_PERIOD_ELAPSED_CB_ID :
+ htim->PeriodElapsedCallback = pCallback;
+ break;
+
+ case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
+ htim->PeriodElapsedHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_TIM_TRIGGER_CB_ID :
+ htim->TriggerCallback = pCallback;
+ break;
+
+ case HAL_TIM_TRIGGER_HALF_CB_ID :
+ htim->TriggerHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_TIM_IC_CAPTURE_CB_ID :
+ htim->IC_CaptureCallback = pCallback;
+ break;
+
+ case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
+ htim->IC_CaptureHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
+ htim->OC_DelayElapsedCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
+ htim->PWM_PulseFinishedCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
+ htim->PWM_PulseFinishedHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_TIM_ERROR_CB_ID :
+ htim->ErrorCallback = pCallback;
+ break;
+
+ case HAL_TIM_COMMUTATION_CB_ID :
+ htim->CommutationCallback = pCallback;
+ break;
+
+ case HAL_TIM_COMMUTATION_HALF_CB_ID :
+ htim->CommutationHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_TIM_BREAK_CB_ID :
+ htim->BreakCallback = pCallback;
+ break;
+
+ case HAL_TIM_BREAK2_CB_ID :
+ htim->Break2Callback = pCallback;
+ break;
+
+ case HAL_TIM_ENCODER_INDEX_CB_ID :
+ htim->EncoderIndexCallback = pCallback;
+ break;
+
+ case HAL_TIM_DIRECTION_CHANGE_CB_ID :
+ htim->DirectionChangeCallback = pCallback;
+ break;
+
+ case HAL_TIM_INDEX_ERROR_CB_ID :
+ htim->IndexErrorCallback = pCallback;
+ break;
+
+ case HAL_TIM_TRANSITION_ERROR_CB_ID :
+ htim->TransitionErrorCallback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (htim->State == HAL_TIM_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_TIM_BASE_MSPINIT_CB_ID :
+ htim->Base_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+ htim->Base_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_IC_MSPINIT_CB_ID :
+ htim->IC_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_IC_MSPDEINIT_CB_ID :
+ htim->IC_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_OC_MSPINIT_CB_ID :
+ htim->OC_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_OC_MSPDEINIT_CB_ID :
+ htim->OC_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_MSPINIT_CB_ID :
+ htim->PWM_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+ htim->PWM_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+ htim->OnePulse_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+ htim->OnePulse_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+ htim->Encoder_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+ htim->Encoder_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+ htim->HallSensor_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+ htim->HallSensor_MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return status;
+}
+
+/**
+ * @brief Unregister a TIM callback
+ * TIM callback is redirected to the weak predefined callback
+ * @param htim tim handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
+ * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
+ * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
+ * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
+ * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
+ * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
+ * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
+ * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
+ * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
+ * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
+ * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
+ * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
+ * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
+ * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
+ * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+ * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
+ * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+ * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
+ * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+ * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
+ * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
+ * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
+ * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
+ * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
+ * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
+ * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
+ * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
+ * @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID
+ * @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback ID
+ * @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID
+ * @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transition Error Callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(htim);
+
+ if (htim->State == HAL_TIM_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_TIM_BASE_MSPINIT_CB_ID :
+ /* Legacy weak Base MspInit Callback */
+ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
+ break;
+
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+ /* Legacy weak Base Msp DeInit Callback */
+ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
+ break;
+
+ case HAL_TIM_IC_MSPINIT_CB_ID :
+ /* Legacy weak IC Msp Init Callback */
+ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
+ break;
+
+ case HAL_TIM_IC_MSPDEINIT_CB_ID :
+ /* Legacy weak IC Msp DeInit Callback */
+ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
+ break;
+
+ case HAL_TIM_OC_MSPINIT_CB_ID :
+ /* Legacy weak OC Msp Init Callback */
+ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
+ break;
+
+ case HAL_TIM_OC_MSPDEINIT_CB_ID :
+ /* Legacy weak OC Msp DeInit Callback */
+ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
+ break;
+
+ case HAL_TIM_PWM_MSPINIT_CB_ID :
+ /* Legacy weak PWM Msp Init Callback */
+ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
+ break;
+
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+ /* Legacy weak PWM Msp DeInit Callback */
+ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+ /* Legacy weak One Pulse Msp Init Callback */
+ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+ /* Legacy weak One Pulse Msp DeInit Callback */
+ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
+ break;
+
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+ /* Legacy weak Encoder Msp Init Callback */
+ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
+ break;
+
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+ /* Legacy weak Encoder Msp DeInit Callback */
+ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+ /* Legacy weak Hall Sensor Msp Init Callback */
+ htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+ /* Legacy weak Hall Sensor Msp DeInit Callback */
+ htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
+ break;
+
+ case HAL_TIM_PERIOD_ELAPSED_CB_ID :
+ /* Legacy weak Period Elapsed Callback */
+ htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
+ break;
+
+ case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
+ /* Legacy weak Period Elapsed half complete Callback */
+ htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
+ break;
+
+ case HAL_TIM_TRIGGER_CB_ID :
+ /* Legacy weak Trigger Callback */
+ htim->TriggerCallback = HAL_TIM_TriggerCallback;
+ break;
+
+ case HAL_TIM_TRIGGER_HALF_CB_ID :
+ /* Legacy weak Trigger half complete Callback */
+ htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
+ break;
+
+ case HAL_TIM_IC_CAPTURE_CB_ID :
+ /* Legacy weak IC Capture Callback */
+ htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
+ break;
+
+ case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
+ /* Legacy weak IC Capture half complete Callback */
+ htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
+ break;
+
+ case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
+ /* Legacy weak OC Delay Elapsed Callback */
+ htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
+ break;
+
+ case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
+ /* Legacy weak PWM Pulse Finished Callback */
+ htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
+ break;
+
+ case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
+ /* Legacy weak PWM Pulse Finished half complete Callback */
+ htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
+ break;
+
+ case HAL_TIM_ERROR_CB_ID :
+ /* Legacy weak Error Callback */
+ htim->ErrorCallback = HAL_TIM_ErrorCallback;
+ break;
+
+ case HAL_TIM_COMMUTATION_CB_ID :
+ /* Legacy weak Commutation Callback */
+ htim->CommutationCallback = HAL_TIMEx_CommutCallback;
+ break;
+
+ case HAL_TIM_COMMUTATION_HALF_CB_ID :
+ /* Legacy weak Commutation half complete Callback */
+ htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
+ break;
+
+ case HAL_TIM_BREAK_CB_ID :
+ /* Legacy weak Break Callback */
+ htim->BreakCallback = HAL_TIMEx_BreakCallback;
+ break;
+
+ case HAL_TIM_BREAK2_CB_ID :
+ /* Legacy weak Break2 Callback */
+ htim->Break2Callback = HAL_TIMEx_Break2Callback;
+ break;
+
+ case HAL_TIM_ENCODER_INDEX_CB_ID :
+ /* Legacy weak Encoder Index Callback */
+ htim->EncoderIndexCallback = HAL_TIMEx_EncoderIndexCallback;
+ break;
+
+ case HAL_TIM_DIRECTION_CHANGE_CB_ID :
+ /* Legacy weak Direction Change Callback */
+ htim->DirectionChangeCallback = HAL_TIMEx_DirectionChangeCallback;
+ break;
+
+ case HAL_TIM_INDEX_ERROR_CB_ID :
+ /* Legacy weak Index Error Callback */
+ htim->IndexErrorCallback = HAL_TIMEx_IndexErrorCallback;
+ break;
+
+ case HAL_TIM_TRANSITION_ERROR_CB_ID :
+ /* Legacy weak Transition Error Callback */
+ htim->TransitionErrorCallback = HAL_TIMEx_TransitionErrorCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (htim->State == HAL_TIM_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_TIM_BASE_MSPINIT_CB_ID :
+ /* Legacy weak Base MspInit Callback */
+ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
+ break;
+
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+ /* Legacy weak Base Msp DeInit Callback */
+ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
+ break;
+
+ case HAL_TIM_IC_MSPINIT_CB_ID :
+ /* Legacy weak IC Msp Init Callback */
+ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
+ break;
+
+ case HAL_TIM_IC_MSPDEINIT_CB_ID :
+ /* Legacy weak IC Msp DeInit Callback */
+ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
+ break;
+
+ case HAL_TIM_OC_MSPINIT_CB_ID :
+ /* Legacy weak OC Msp Init Callback */
+ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
+ break;
+
+ case HAL_TIM_OC_MSPDEINIT_CB_ID :
+ /* Legacy weak OC Msp DeInit Callback */
+ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
+ break;
+
+ case HAL_TIM_PWM_MSPINIT_CB_ID :
+ /* Legacy weak PWM Msp Init Callback */
+ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
+ break;
+
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+ /* Legacy weak PWM Msp DeInit Callback */
+ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+ /* Legacy weak One Pulse Msp Init Callback */
+ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+ /* Legacy weak One Pulse Msp DeInit Callback */
+ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
+ break;
+
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+ /* Legacy weak Encoder Msp Init Callback */
+ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
+ break;
+
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+ /* Legacy weak Encoder Msp DeInit Callback */
+ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+ /* Legacy weak Hall Sensor Msp Init Callback */
+ htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+ /* Legacy weak Hall Sensor Msp DeInit Callback */
+ htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return status;
+}
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
+ * @brief TIM Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the TIM Base handle state.
+ * @param htim TIM Base handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM OC handle state.
+ * @param htim TIM Output Compare handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM PWM handle state.
+ * @param htim TIM handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM Input Capture handle state.
+ * @param htim TIM IC handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM One Pulse Mode handle state.
+ * @param htim TIM OPM handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM Encoder Mode handle state.
+ * @param htim TIM Encoder Interface handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM Encoder Mode handle state.
+ * @param htim TIM handle
+ * @retval Active channel
+ */
+HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim)
+{
+ return htim->Channel;
+}
+
+/**
+ * @brief Return actual state of the TIM channel.
+ * @param htim TIM handle
+ * @param Channel TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @arg TIM_CHANNEL_4: TIM Channel 4
+ * @arg TIM_CHANNEL_5: TIM Channel 5
+ * @arg TIM_CHANNEL_6: TIM Channel 6
+ * @retval TIM Channel state
+ */
+HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ HAL_TIM_ChannelStateTypeDef channel_state;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+
+ return channel_state;
+}
+
+/**
+ * @brief Return actual state of a DMA burst operation.
+ * @param htim TIM handle
+ * @retval DMA burst state
+ */
+HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+
+ return htim->DMABurstState;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Private_Functions TIM Private Functions
+ * @{
+ */
+
+/**
+ * @brief TIM DMA error callback
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void TIM_DMAError(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_READY;
+ }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->ErrorCallback(htim);
+#else
+ HAL_TIM_ErrorCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief TIM DMA Delay Pulse complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PWM_PulseFinishedCallback(htim);
+#else
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief TIM DMA Delay Pulse half complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PWM_PulseFinishedHalfCpltCallback(htim);
+#else
+ HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief TIM DMA Capture complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureCallback(htim);
+#else
+ HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief TIM DMA Capture half complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureHalfCpltCallback(htim);
+#else
+ HAL_TIM_IC_CaptureHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief TIM DMA Period Elapse complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PeriodElapsedCallback(htim);
+#else
+ HAL_TIM_PeriodElapsedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief TIM DMA Period Elapse half complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PeriodElapsedHalfCpltCallback(htim);
+#else
+ HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief TIM DMA Trigger callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->TriggerCallback(htim);
+#else
+ HAL_TIM_TriggerCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief TIM DMA Trigger half complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->TriggerHalfCpltCallback(htim);
+#else
+ HAL_TIM_TriggerHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief Time Base configuration
+ * @param TIMx TIM peripheral
+ * @param Structure TIM Base configuration structure
+ * @retval None
+ */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
+{
+ uint32_t tmpcr1;
+ tmpcr1 = TIMx->CR1;
+
+ /* Set TIM Time Base Unit parameters ---------------------------------------*/
+ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+ {
+ /* Select the Counter Mode */
+ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
+ tmpcr1 |= Structure->CounterMode;
+ }
+
+ if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+ {
+ /* Set the clock division */
+ tmpcr1 &= ~TIM_CR1_CKD;
+ tmpcr1 |= (uint32_t)Structure->ClockDivision;
+ }
+
+ /* Set the auto-reload preload */
+ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
+
+ TIMx->CR1 = tmpcr1;
+
+ /* Set the Autoreload value */
+ TIMx->ARR = (uint32_t)Structure->Period ;
+
+ /* Set the Prescaler value */
+ TIMx->PSC = Structure->Prescaler;
+
+ if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
+ {
+ /* Set the Repetition Counter value */
+ TIMx->RCR = Structure->RepetitionCounter;
+ }
+
+ /* Generate an update event to reload the Prescaler
+ and the repetition counter (only for advanced timer) value immediately */
+ TIMx->EGR = TIM_EGR_UG;
+}
+
+/**
+ * @brief Timer Output Compare 1 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config The output configuration structure
+ * @retval None
+ */
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC1E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR1;
+
+ /* Reset the Output Compare Mode Bits */
+ tmpccmrx &= ~TIM_CCMR1_OC1M;
+ tmpccmrx &= ~TIM_CCMR1_CC1S;
+ /* Select the Output Compare Mode */
+ tmpccmrx |= OC_Config->OCMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC1P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= OC_Config->OCPolarity;
+
+ if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
+ {
+ /* Check parameters */
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= ~TIM_CCER_CC1NP;
+ /* Set the Output N Polarity */
+ tmpccer |= OC_Config->OCNPolarity;
+ /* Reset the Output N State */
+ tmpccer &= ~TIM_CCER_CC1NE;
+ }
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Check parameters */
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS1;
+ tmpcr2 &= ~TIM_CR2_OIS1N;
+ /* Set the Output Idle state */
+ tmpcr2 |= OC_Config->OCIdleState;
+ /* Set the Output N Idle state */
+ tmpcr2 |= OC_Config->OCNIdleState;
+ }
+
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR1 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Timer Output Compare 2 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config The output configuration structure
+ * @retval None
+ */
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC2E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR1;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= ~TIM_CCMR1_OC2M;
+ tmpccmrx &= ~TIM_CCMR1_CC2S;
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (OC_Config->OCMode << 8U);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC2P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 4U);
+
+ if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
+ {
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= ~TIM_CCER_CC2NP;
+ /* Set the Output N Polarity */
+ tmpccer |= (OC_Config->OCNPolarity << 4U);
+ /* Reset the Output N State */
+ tmpccer &= ~TIM_CCER_CC2NE;
+
+ }
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Check parameters */
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS2;
+ tmpcr2 &= ~TIM_CR2_OIS2N;
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 2U);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (OC_Config->OCNIdleState << 2U);
+ }
+
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR2 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Timer Output Compare 3 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config The output configuration structure
+ * @retval None
+ */
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
+
+ /* Disable the Channel 3: Reset the CC2E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC3E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmrx = TIMx->CCMR2;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= ~TIM_CCMR2_OC3M;
+ tmpccmrx &= ~TIM_CCMR2_CC3S;
+ /* Select the Output Compare Mode */
+ tmpccmrx |= OC_Config->OCMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC3P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 8U);
+
+ if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
+ {
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= ~TIM_CCER_CC3NP;
+ /* Set the Output N Polarity */
+ tmpccer |= (OC_Config->OCNPolarity << 8U);
+ /* Reset the Output N State */
+ tmpccer &= ~TIM_CCER_CC3NE;
+ }
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Check parameters */
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS3;
+ tmpcr2 &= ~TIM_CR2_OIS3N;
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 4U);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (OC_Config->OCNIdleState << 4U);
+ }
+
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR3 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Timer Output Compare 4 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config The output configuration structure
+ * @retval None
+ */
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC4E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmrx = TIMx->CCMR2;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= ~TIM_CCMR2_OC4M;
+ tmpccmrx &= ~TIM_CCMR2_CC4S;
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (OC_Config->OCMode << 8U);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC4P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 12U);
+
+ if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_4))
+ {
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= ~TIM_CCER_CC4NP;
+ /* Set the Output N Polarity */
+ tmpccer |= (OC_Config->OCNPolarity << 12U);
+ /* Reset the Output N State */
+ tmpccer &= ~TIM_CCER_CC4NE;
+ }
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Check parameters */
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS4;
+ /* Reset the Output Compare N IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS4N;
+
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 6U);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (OC_Config->OCNIdleState << 6U);
+ }
+
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR4 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Timer Output Compare 5 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config The output configuration structure
+ * @retval None
+ */
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
+ TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
+
+ /* Disable the output: Reset the CCxE Bit */
+ TIMx->CCER &= ~TIM_CCER_CC5E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR3;
+
+ /* Reset the Output Compare Mode Bits */
+ tmpccmrx &= ~(TIM_CCMR3_OC5M);
+ /* Select the Output Compare Mode */
+ tmpccmrx |= OC_Config->OCMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC5P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 16U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS5;
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 8U);
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR3 */
+ TIMx->CCMR3 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR5 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Timer Output Compare 6 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config The output configuration structure
+ * @retval None
+ */
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
+ TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
+
+ /* Disable the output: Reset the CCxE Bit */
+ TIMx->CCER &= ~TIM_CCER_CC6E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR3;
+
+ /* Reset the Output Compare Mode Bits */
+ tmpccmrx &= ~(TIM_CCMR3_OC6M);
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (OC_Config->OCMode << 8U);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint32_t)~TIM_CCER_CC6P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 20U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS6;
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 10U);
+ }
+
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR3 */
+ TIMx->CCMR3 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR6 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Slave Timer configuration function
+ * @param htim TIM handle
+ * @param sSlaveConfig Slave timer configuration
+ * @retval None
+ */
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+ TIM_SlaveConfigTypeDef *sSlaveConfig)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpsmcr;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = htim->Instance->SMCR;
+
+ /* Reset the Trigger Selection Bits */
+ tmpsmcr &= ~TIM_SMCR_TS;
+ /* Set the Input Trigger source */
+ tmpsmcr |= sSlaveConfig->InputTrigger;
+
+ /* Reset the slave mode Bits */
+ tmpsmcr &= ~TIM_SMCR_SMS;
+ /* Set the slave mode */
+ tmpsmcr |= sSlaveConfig->SlaveMode;
+
+ /* Write to TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+
+ /* Configure the trigger prescaler, filter, and polarity */
+ switch (sSlaveConfig->InputTrigger)
+ {
+ case TIM_TS_ETRF:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+ /* Configure the ETR Trigger source */
+ TIM_ETR_SetConfig(htim->Instance,
+ sSlaveConfig->TriggerPrescaler,
+ sSlaveConfig->TriggerPolarity,
+ sSlaveConfig->TriggerFilter);
+ break;
+ }
+
+ case TIM_TS_TI1F_ED:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+ if ((sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) || \
+ (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_COMBINED_GATEDRESET))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ tmpccer = htim->Instance->CCER;
+ htim->Instance->CCER &= ~TIM_CCER_CC1E;
+ tmpccmr1 = htim->Instance->CCMR1;
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ htim->Instance->CCMR1 = tmpccmr1;
+ htim->Instance->CCER = tmpccer;
+ break;
+ }
+
+ case TIM_TS_TI1FP1:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+ /* Configure TI1 Filter and Polarity */
+ TIM_TI1_ConfigInputStage(htim->Instance,
+ sSlaveConfig->TriggerPolarity,
+ sSlaveConfig->TriggerFilter);
+ break;
+ }
+
+ case TIM_TS_TI2FP2:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+ /* Configure TI2 Filter and Polarity */
+ TIM_TI2_ConfigInputStage(htim->Instance,
+ sSlaveConfig->TriggerPolarity,
+ sSlaveConfig->TriggerFilter);
+ break;
+ }
+
+ case TIM_TS_ITR0:
+ case TIM_TS_ITR1:
+ case TIM_TS_ITR2:
+ case TIM_TS_ITR3:
+ case TIM_TS_ITR4:
+ case TIM_TS_ITR5:
+ case TIM_TS_ITR6:
+ case TIM_TS_ITR7:
+ case TIM_TS_ITR8:
+ case TIM_TS_ITR11:
+ {
+ /* Check the parameter */
+ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE((htim->Instance), sSlaveConfig->InputTrigger));
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Configure the TI1 as Input.
+ * @param TIMx to select the TIM peripheral.
+ * @param TIM_ICPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
+ * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
+ * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
+ * protected against un-initialized filter and polarity values.
+ */
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC1E;
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+
+ /* Select the Input */
+ if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
+ {
+ tmpccmr1 &= ~TIM_CCMR1_CC1S;
+ tmpccmr1 |= TIM_ICSelection;
+ }
+ else
+ {
+ tmpccmr1 |= TIM_CCMR1_CC1S_0;
+ }
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
+
+ /* Select the Polarity and set the CC1E Bit */
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+ tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the Polarity and Filter for TI1.
+ * @param TIMx to select the TIM peripheral.
+ * @param TIM_ICPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ tmpccer = TIMx->CCER;
+ TIMx->CCER &= ~TIM_CCER_CC1E;
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ tmpccmr1 |= (TIM_ICFilter << 4U);
+
+ /* Select the Polarity and set the CC1E Bit */
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+ tmpccer |= TIM_ICPolarity;
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI2 as Input.
+ * @param TIMx to select the TIM peripheral
+ * @param TIM_ICPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
+ * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
+ * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
+ * protected against un-initialized filter and polarity values.
+ */
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC2E;
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+
+ /* Select the Input */
+ tmpccmr1 &= ~TIM_CCMR1_CC2S;
+ tmpccmr1 |= (TIM_ICSelection << 8U);
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC2F;
+ tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
+
+ /* Select the Polarity and set the CC2E Bit */
+ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1 ;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the Polarity and Filter for TI2.
+ * @param TIMx to select the TIM peripheral.
+ * @param TIM_ICPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC2E;
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC2F;
+ tmpccmr1 |= (TIM_ICFilter << 12U);
+
+ /* Select the Polarity and set the CC2E Bit */
+ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ tmpccer |= (TIM_ICPolarity << 4U);
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1 ;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI3 as Input.
+ * @param TIMx to select the TIM peripheral
+ * @param TIM_ICPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
+ * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
+ * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+ * protected against un-initialized filter and polarity values.
+ */
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr2;
+ uint32_t tmpccer;
+
+ /* Disable the Channel 3: Reset the CC3E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC3E;
+ tmpccmr2 = TIMx->CCMR2;
+ tmpccer = TIMx->CCER;
+
+ /* Select the Input */
+ tmpccmr2 &= ~TIM_CCMR2_CC3S;
+ tmpccmr2 |= TIM_ICSelection;
+
+ /* Set the filter */
+ tmpccmr2 &= ~TIM_CCMR2_IC3F;
+ tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
+
+ /* Select the Polarity and set the CC3E Bit */
+ tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
+ tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
+
+ /* Write to TIMx CCMR2 and CCER registers */
+ TIMx->CCMR2 = tmpccmr2;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI4 as Input.
+ * @param TIMx to select the TIM peripheral
+ * @param TIM_ICPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
+ * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
+ * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+ * protected against un-initialized filter and polarity values.
+ * @retval None
+ */
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr2;
+ uint32_t tmpccer;
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC4E;
+ tmpccmr2 = TIMx->CCMR2;
+ tmpccer = TIMx->CCER;
+
+ /* Select the Input */
+ tmpccmr2 &= ~TIM_CCMR2_CC4S;
+ tmpccmr2 |= (TIM_ICSelection << 8U);
+
+ /* Set the filter */
+ tmpccmr2 &= ~TIM_CCMR2_IC4F;
+ tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
+
+ /* Select the Polarity and set the CC4E Bit */
+ tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
+ tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
+
+ /* Write to TIMx CCMR2 and CCER registers */
+ TIMx->CCMR2 = tmpccmr2;
+ TIMx->CCER = tmpccer ;
+}
+
+/**
+ * @brief Selects the Input Trigger source
+ * @param TIMx to select the TIM peripheral
+ * @param InputTriggerSource The Input Trigger source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0: Internal Trigger 0
+ * @arg TIM_TS_ITR1: Internal Trigger 1
+ * @arg TIM_TS_ITR2: Internal Trigger 2
+ * @arg TIM_TS_ITR3: Internal Trigger 3
+ * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
+ * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
+ * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
+ * @arg TIM_TS_ETRF: External Trigger input
+ * @arg TIM_TS_ITR4: Internal Trigger 4
+ * @arg TIM_TS_ITR5: Internal Trigger 5
+ * @arg TIM_TS_ITR6: Internal Trigger 6
+ * @arg TIM_TS_ITR7: Internal Trigger 7
+ * @arg TIM_TS_ITR8: Internal Trigger 8
+ * @arg TIM_TS_ITR11: Internal Trigger 11
+ * @retval None
+ */
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
+{
+ uint32_t tmpsmcr;
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = TIMx->SMCR;
+ /* Reset the TS Bits */
+ tmpsmcr &= ~TIM_SMCR_TS;
+ /* Set the Input Trigger source and the slave mode*/
+ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+}
+/**
+ * @brief Configures the TIMx External Trigger (ETR).
+ * @param TIMx to select the TIM peripheral
+ * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
+ * This parameter can be one of the following values:
+ * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
+ * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
+ * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
+ * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity The external Trigger Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
+ * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
+ * @param ExtTRGFilter External Trigger Filter.
+ * This parameter must be a value between 0x00 and 0x0F
+ * @retval None
+ */
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
+ uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
+{
+ uint32_t tmpsmcr;
+
+ tmpsmcr = TIMx->SMCR;
+
+ /* Reset the ETR Bits */
+ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+
+ /* Set the Prescaler, the Filter value and the Polarity */
+ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
+
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+}
+
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel x.
+ * @param TIMx to select the TIM peripheral
+ * @param Channel specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @arg TIM_CHANNEL_4: TIM Channel 4
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @param ChannelState specifies the TIM Channel CCxE bit new state.
+ * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
+ * @retval None
+ */
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
+{
+ uint32_t tmp;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+ assert_param(IS_TIM_CHANNELS(Channel));
+
+ tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
+
+ /* Reset the CCxE Bit */
+ TIMx->CCER &= ~tmp;
+
+ /* Set or reset the CCxE Bit */
+ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
+}
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Reset interrupt callbacks to the legacy weak callbacks.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval None
+ */
+void TIM_ResetCallback(TIM_HandleTypeDef *htim)
+{
+ /* Reset the TIM callback to the legacy weak callbacks */
+ htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
+ htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
+ htim->TriggerCallback = HAL_TIM_TriggerCallback;
+ htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
+ htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
+ htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
+ htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
+ htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
+ htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
+ htim->ErrorCallback = HAL_TIM_ErrorCallback;
+ htim->CommutationCallback = HAL_TIMEx_CommutCallback;
+ htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
+ htim->BreakCallback = HAL_TIMEx_BreakCallback;
+ htim->Break2Callback = HAL_TIMEx_Break2Callback;
+ htim->EncoderIndexCallback = HAL_TIMEx_EncoderIndexCallback;
+ htim->DirectionChangeCallback = HAL_TIMEx_DirectionChangeCallback;
+ htim->IndexErrorCallback = HAL_TIMEx_IndexErrorCallback;
+ htim->TransitionErrorCallback = HAL_TIMEx_TransitionErrorCallback;
+}
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim_ex.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim_ex.c
new file mode 100644
index 00000000..1ae8e14f
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim_ex.c
@@ -0,0 +1,3518 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_tim_ex.c
+ * @author MCD Application Team
+ * @brief TIM HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Timer Extended peripheral:
+ * + Time Hall Sensor Interface Initialization
+ * + Time Hall Sensor Interface Start
+ * + Time Complementary signal break and dead time configuration
+ * + Time Master and Slave synchronization configuration
+ * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
+ * + Time OCRef clear configuration
+ * + Timer remapping capabilities configuration
+ * + Timer encoder index configuration
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### TIMER Extended features #####
+ ==============================================================================
+ [..]
+ The Timer Extended features include:
+ (#) Complementary outputs with programmable dead-time for :
+ (++) Output Compare
+ (++) PWM generation (Edge and Center-aligned Mode)
+ (++) One-pulse mode output
+ (#) Synchronization circuit to control the timer with external signals and to
+ interconnect several timers together.
+ (#) Break input to put the timer output signals in reset state or in a known state.
+ (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
+ positioning purposes
+ (#) In case of Pulse on compare, configure pulse length and delay
+ (#) Encoder index configuration
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Initialize the TIM low level resources by implementing the following functions
+ depending on the selected feature:
+ (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
+
+ (#) Initialize the TIM low level resources :
+ (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
+ (##) TIM pins configuration
+ (+++) Enable the clock for the TIM GPIOs using the following function:
+ __HAL_RCC_GPIOx_CLK_ENABLE();
+ (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+
+ (#) The external Clock can be configured, if needed (the default clock is the
+ internal clock from the APBx), using the following function:
+ HAL_TIM_ConfigClockSource, the clock configuration should be done before
+ any start function.
+
+ (#) Configure the TIM in the desired functioning mode using one of the
+ initialization function of this driver:
+ (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the
+ Timer Hall Sensor Interface and the commutation event with the corresponding
+ Interrupt and DMA request if needed (Note that One Timer is used to interface
+ with the Hall sensor Interface and another Timer should be used to use
+ the commutation event).
+ (#) In case of Pulse On Compare:
+ (++) HAL_TIMEx_OC_ConfigPulseOnCompare(): to configure pulse width and prescaler
+
+
+ (#) Activate the TIM peripheral using one of the start functions:
+ (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(),
+ HAL_TIMEx_OCN_Start_IT()
+ (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(),
+ HAL_TIMEx_PWMN_Start_IT()
+ (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
+ (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(),
+ HAL_TIMEx_HallSensor_Start_IT().
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup TIMEx TIMEx
+ * @brief TIM Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Constants TIM Extended Private Constants
+ * @{
+ */
+/* Timeout for break input rearm */
+#define TIM_BREAKINPUT_REARM_TIMEOUT 5UL /* 5 milliseconds */
+/**
+ * @}
+ */
+/* End of private constants --------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma);
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
+ * @brief Timer Hall Sensor functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Timer Hall Sensor functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure TIM HAL Sensor.
+ (+) De-initialize TIM HAL Sensor.
+ (+) Start the Hall Sensor Interface.
+ (+) Stop the Hall Sensor Interface.
+ (+) Start the Hall Sensor Interface and enable interrupts.
+ (+) Stop the Hall Sensor Interface and disable interrupts.
+ (+) Start the Hall Sensor Interface and enable DMA transfers.
+ (+) Stop the Hall Sensor Interface and disable DMA transfers.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle.
+ * @note When the timer instance is initialized in Hall Sensor Interface mode,
+ * timer channels 1 and channel 2 are reserved and cannot be used for
+ * other purpose.
+ * @param htim TIM Hall Sensor Interface handle
+ * @param sConfig TIM Hall Sensor configuration structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
+{
+ TIM_OC_InitTypeDef OC_Config;
+
+ /* Check the TIM handle allocation */
+ if (htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+ assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+
+ if (htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy week callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->HallSensor_MspInitCallback == NULL)
+ {
+ htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->HallSensor_MspInitCallback(htim);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIMEx_HallSensor_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Configure the Time base in the Encoder Mode */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
+ TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
+
+ /* Reset the IC1PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+ /* Set the IC1PSC value */
+ htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
+
+ /* Enable the Hall sensor interface (XOR function of the three inputs) */
+ htim->Instance->CR2 |= TIM_CR2_TI1S;
+
+ /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= TIM_TS_TI1F_ED;
+
+ /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
+
+ /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
+ OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
+ OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
+ OC_Config.OCMode = TIM_OCMODE_PWM2;
+ OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
+ OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
+ OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
+ OC_Config.Pulse = sConfig->Commutation_Delay;
+
+ TIM_OC2_SetConfig(htim->Instance, &OC_Config);
+
+ /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
+ register to 101 */
+ htim->Instance->CR2 &= ~TIM_CR2_MMS;
+ htim->Instance->CR2 |= TIM_TRGO_OC2REF;
+
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Initialize the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Initialize the TIM state*/
+ htim->State = HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM Hall Sensor interface
+ * @param htim TIM Hall Sensor Interface handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->HallSensor_MspDeInitCallback == NULL)
+ {
+ htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->HallSensor_MspDeInitCallback(htim);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_TIMEx_HallSensor_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Change the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Hall Sensor MSP.
+ * @param htim TIM Hall Sensor Interface handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Hall Sensor MSP.
+ * @param htim TIM Hall Sensor Interface handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM Hall Sensor Interface.
+ * @param htim TIM Hall Sensor Interface handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
+{
+ uint32_t tmpsmcr;
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Check the TIM channels state */
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ /* Enable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Hall sensor Interface.
+ * @param htim TIM Hall Sensor Interface handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1, 2 and 3
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
+ * @param htim TIM Hall Sensor Interface handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
+{
+ uint32_t tmpsmcr;
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Check the TIM channels state */
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ /* Enable the capture compare Interrupts 1 event */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+ /* Enable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
+ * @param htim TIM Hall Sensor Interface handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare Interrupts event */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Hall Sensor Interface in DMA mode.
+ * @param htim TIM Hall Sensor Interface handle
+ * @param pData The destination Buffer address.
+ * @param Length The length of data to be transferred from TIM peripheral to memory.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
+{
+ uint32_t tmpsmcr;
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Set the TIM channel state */
+ if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
+ {
+ if ((pData == NULL) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ /* Enable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+ /* Set the DMA Input Capture 1 Callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel for Capture 1*/
+ if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the capture compare 1 Interrupt */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Hall Sensor Interface in DMA mode.
+ * @param htim TIM Hall Sensor Interface handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+
+ /* Disable the capture compare Interrupts 1 event */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
+ * @brief Timer Complementary Output Compare functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Timer Complementary Output Compare functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Start the Complementary Output Compare/PWM.
+ (+) Stop the Complementary Output Compare/PWM.
+ (+) Start the Complementary Output Compare/PWM and enable interrupts.
+ (+) Stop the Complementary Output Compare/PWM and disable interrupts.
+ (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
+ (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the TIM Output Compare signal generation on the complementary
+ * output.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Check the TIM complementary channel state */
+ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ /* Enable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation on the complementary
+ * output.
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation in interrupt mode
+ * on the complementary output.
+ * @param htim TIM OC handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Check the TIM complementary channel state */
+ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Output Compare interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Output Compare interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Output Compare interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ break;
+ }
+
+
+ case TIM_CHANNEL_4:
+ {
+ /* Enable the TIM Output Compare interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Enable the TIM Break interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+ /* Enable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation in interrupt mode
+ * on the complementary output.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpccer;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Output Compare interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Output Compare interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Output Compare interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Output Compare interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Disable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the TIM Break interrupt (only if no more channel is active) */
+ tmpccer = htim->Instance->CCER;
+ if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE)) == (uint32_t)RESET)
+ {
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+ }
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation in DMA mode
+ * on the complementary output.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to TIM peripheral
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Set the TIM complementary channel state */
+ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
+ {
+ if ((pData == NULL) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+ /* Enable the DMA channel */
+ if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Output Compare DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+ /* Enable the DMA channel */
+ if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Output Compare DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+ /* Enable the DMA channel */
+ if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Output Compare DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+ /* Enable the DMA channel */
+ if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Output Compare DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Enable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation in DMA mode
+ * on the complementary output.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Output Compare DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Output Compare DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Output Compare DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Output Compare interrupt */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Disable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
+ * @brief Timer Complementary PWM functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Timer Complementary PWM functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Start the Complementary PWM.
+ (+) Stop the Complementary PWM.
+ (+) Start the Complementary PWM and enable interrupts.
+ (+) Stop the Complementary PWM and disable interrupts.
+ (+) Start the Complementary PWM and enable DMA transfers.
+ (+) Stop the Complementary PWM and disable DMA transfers.
+ (+) Start the Complementary Input Capture measurement.
+ (+) Stop the Complementary Input Capture.
+ (+) Start the Complementary Input Capture and enable interrupts.
+ (+) Stop the Complementary Input Capture and disable interrupts.
+ (+) Start the Complementary Input Capture and enable DMA transfers.
+ (+) Stop the Complementary Input Capture and disable DMA transfers.
+ (+) Start the Complementary One Pulse generation.
+ (+) Stop the Complementary One Pulse.
+ (+) Start the Complementary One Pulse and enable interrupts.
+ (+) Stop the Complementary One Pulse and disable interrupts.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the PWM signal generation on the complementary output.
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Check the TIM complementary channel state */
+ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ /* Enable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the PWM signal generation on the complementary output.
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the PWM signal generation in interrupt mode on the
+ * complementary output.
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Check the TIM complementary channel state */
+ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Enable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Enable the TIM Break interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+ /* Enable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Stops the PWM signal generation in interrupt mode on the
+ * complementary output.
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpccer;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Disable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the TIM Break interrupt (only if no more channel is active) */
+ tmpccer = htim->Instance->CCER;
+ if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE)) == (uint32_t)RESET)
+ {
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+ }
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Starts the TIM PWM signal generation in DMA mode on the
+ * complementary output
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to TIM peripheral
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Set the TIM complementary channel state */
+ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
+ {
+ if ((pData == NULL) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+ /* Enable the DMA channel */
+ if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+ /* Enable the DMA channel */
+ if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+ /* Enable the DMA channel */
+ if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+ /* Enable the DMA channel */
+ if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Enable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
+ * output
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Disable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
+ * @brief Timer Complementary One Pulse functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Timer Complementary One Pulse functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Start the Complementary One Pulse generation.
+ (+) Stop the Complementary One Pulse.
+ (+) Start the Complementary One Pulse and enable interrupts.
+ (+) Stop the Complementary One Pulse and disable interrupts.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the TIM One Pulse signal generation on the complementary
+ * output.
+ * @note OutputChannel must match the pulse output channel chosen when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel pulse output channel to enable
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+ /* Check the TIM channels state */
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ /* Enable the complementary One Pulse output channel and the Input Capture channel */
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM One Pulse signal generation on the complementary
+ * output.
+ * @note OutputChannel must match the pulse output channel chosen when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel pulse output channel to disable
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+ /* Disable the complementary One Pulse output channel and the Input Capture channel */
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
+ * complementary channel.
+ * @note OutputChannel must match the pulse output channel chosen when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel pulse output channel to enable
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+ /* Check the TIM channels state */
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+
+ /* Enable the complementary One Pulse output channel and the Input Capture channel */
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
+ * complementary channel.
+ * @note OutputChannel must match the pulse output channel chosen when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel pulse output channel to disable
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+
+ /* Disable the complementary One Pulse output channel and the Input Capture channel */
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Configure the commutation event in case of use of the Hall sensor interface.
+ (+) Configure Output channels for OC and PWM mode.
+
+ (+) Configure Complementary channels, break features and dead time.
+ (+) Configure Master synchronization.
+ (+) Configure timer remapping capabilities.
+ (+) Select timer input source.
+ (+) Enable or disable channel grouping.
+ (+) Configure Pulse on compare.
+ (+) Configure Encoder index.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the TIM commutation event sequence.
+ * @note This function is mandatory to use the commutation event in order to
+ * update the configuration at each commutation detection on the TRGI input of the Timer,
+ * the typical use of this feature is with the use of another Timer(interface Timer)
+ * configured in Hall sensor interface, this interface Timer will generate the
+ * commutation at its TRGO output (connected to Timer used in this function) each time
+ * the TI1 of the Interface Timer detect a commutation at its input TI1.
+ * @param htim TIM handle
+ * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected
+ * @arg TIM_TS_ITR4: Internal trigger 4 selected
+ * @arg TIM_TS_ITR5: Internal trigger 5 selected
+ * @arg TIM_TS_ITR6: Internal trigger 6 selected
+ * @arg TIM_TS_ITR7: Internal trigger 7 selected
+ * @arg TIM_TS_ITR8: Internal trigger 8 selected
+ * @arg TIM_TS_ITR11: Internal trigger 11 selected
+ * @arg TIM_TS_NONE: No trigger is needed
+ * @param CommutationSource the Commutation Event source
+ * This parameter can be one of the following values:
+ * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+ * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
+ uint32_t CommutationSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
+ (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) ||
+ (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) ||
+ (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11))
+ {
+ /* Select the Input trigger */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= InputTrigger;
+ }
+
+ /* Select the Capture Compare preload feature */
+ htim->Instance->CR2 |= TIM_CR2_CCPC;
+ /* Select the Commutation event source */
+ htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+ htim->Instance->CR2 |= CommutationSource;
+
+ /* Disable Commutation Interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
+
+ /* Disable Commutation DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the TIM commutation event sequence with interrupt.
+ * @note This function is mandatory to use the commutation event in order to
+ * update the configuration at each commutation detection on the TRGI input of the Timer,
+ * the typical use of this feature is with the use of another Timer(interface Timer)
+ * configured in Hall sensor interface, this interface Timer will generate the
+ * commutation at its TRGO output (connected to Timer used in this function) each time
+ * the TI1 of the Interface Timer detect a commutation at its input TI1.
+ * @param htim TIM handle
+ * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected
+ * @arg TIM_TS_ITR4: Internal trigger 4 selected
+ * @arg TIM_TS_ITR5: Internal trigger 5 selected
+ * @arg TIM_TS_ITR6: Internal trigger 6 selected
+ * @arg TIM_TS_ITR7: Internal trigger 7 selected
+ * @arg TIM_TS_ITR8: Internal trigger 8 selected
+ * @arg TIM_TS_ITR11: Internal trigger 11 selected
+ * @arg TIM_TS_NONE: No trigger is needed
+ * @param CommutationSource the Commutation Event source
+ * This parameter can be one of the following values:
+ * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+ * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
+ uint32_t CommutationSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
+ (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) ||
+ (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) ||
+ (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11))
+ {
+ /* Select the Input trigger */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= InputTrigger;
+ }
+
+ /* Select the Capture Compare preload feature */
+ htim->Instance->CR2 |= TIM_CR2_CCPC;
+ /* Select the Commutation event source */
+ htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+ htim->Instance->CR2 |= CommutationSource;
+
+ /* Disable Commutation DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
+
+ /* Enable the Commutation Interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the TIM commutation event sequence with DMA.
+ * @note This function is mandatory to use the commutation event in order to
+ * update the configuration at each commutation detection on the TRGI input of the Timer,
+ * the typical use of this feature is with the use of another Timer(interface Timer)
+ * configured in Hall sensor interface, this interface Timer will generate the
+ * commutation at its TRGO output (connected to Timer used in this function) each time
+ * the TI1 of the Interface Timer detect a commutation at its input TI1.
+ * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set
+ * @param htim TIM handle
+ * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected
+ * @arg TIM_TS_ITR4: Internal trigger 4 selected
+ * @arg TIM_TS_ITR5: Internal trigger 5 selected
+ * @arg TIM_TS_ITR6: Internal trigger 6 selected
+ * @arg TIM_TS_ITR7: Internal trigger 7 selected
+ * @arg TIM_TS_ITR8: Internal trigger 8 selected
+ * @arg TIM_TS_ITR11: Internal trigger 11 selected
+ * @arg TIM_TS_NONE: No trigger is needed
+ * @param CommutationSource the Commutation Event source
+ * This parameter can be one of the following values:
+ * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+ * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
+ uint32_t CommutationSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
+ (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) ||
+ (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) ||
+ (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11))
+ {
+ /* Select the Input trigger */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= InputTrigger;
+ }
+
+ /* Select the Capture Compare preload feature */
+ htim->Instance->CR2 |= TIM_CR2_CCPC;
+ /* Select the Commutation event source */
+ htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+ htim->Instance->CR2 |= CommutationSource;
+
+ /* Enable the Commutation DMA Request */
+ /* Set the DMA Commutation Callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
+
+ /* Disable Commutation Interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
+
+ /* Enable the Commutation DMA Request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the TIM in master mode.
+ * @param htim TIM handle.
+ * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
+ * contains the selected trigger output (TRGO) and the Master/Slave
+ * mode.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+ TIM_MasterConfigTypeDef *sMasterConfig)
+{
+ uint32_t tmpcr2;
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
+ assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
+
+ /* Check input state */
+ __HAL_LOCK(htim);
+
+ /* Change the handler state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = htim->Instance->CR2;
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = htim->Instance->SMCR;
+
+ /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
+ if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
+
+ /* Clear the MMS2 bits */
+ tmpcr2 &= ~TIM_CR2_MMS2;
+ /* Select the TRGO2 source*/
+ tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
+ }
+
+ /* Reset the MMS Bits */
+ tmpcr2 &= ~TIM_CR2_MMS;
+ /* Select the TRGO source */
+ tmpcr2 |= sMasterConfig->MasterOutputTrigger;
+
+ /* Update TIMx CR2 */
+ htim->Instance->CR2 = tmpcr2;
+
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ /* Reset the MSM Bit */
+ tmpsmcr &= ~TIM_SMCR_MSM;
+ /* Set master mode */
+ tmpsmcr |= sMasterConfig->MasterSlaveMode;
+
+ /* Update TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+ }
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
+ * and the AOE(automatic output enable).
+ * @param htim TIM handle
+ * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
+ * contains the BDTR Register configuration information for the TIM peripheral.
+ * @note Interrupts can be generated when an active level is detected on the
+ * break input, the break 2 input or the system break input. Break
+ * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+ TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
+{
+ /* Keep this variable initialized to 0 as it is used to configure BDTR register */
+ uint32_t tmpbdtr = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
+ assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
+ assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
+ assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
+ assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
+ assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
+ assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
+ assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
+
+ /* Check input state */
+ __HAL_LOCK(htim);
+
+ /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
+ the OSSI State, the dead time value and the Automatic Output Enable Bit */
+
+ /* Set the BDTR bits */
+ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
+
+ if (IS_TIM_ADVANCED_INSTANCE(htim->Instance))
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
+
+ /* Set BREAK AF mode */
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
+ }
+
+ if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
+ assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
+ assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
+
+ /* Set the BREAK2 input related BDTR bits */
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
+
+ if (IS_TIM_ADVANCED_INSTANCE(htim->Instance))
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode));
+
+ /* Set BREAK2 AF mode */
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode);
+ }
+ }
+
+ /* Set TIMx_BDTR */
+ htim->Instance->BDTR = tmpbdtr;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the break input source.
+ * @param htim TIM handle.
+ * @param BreakInput Break input to configure
+ * This parameter can be one of the following values:
+ * @arg TIM_BREAKINPUT_BRK: Timer break input
+ * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
+ * @param sBreakInputConfig Break input source configuration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
+ uint32_t BreakInput,
+ TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
+
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmporx;
+ uint32_t bkin_enable_mask;
+ uint32_t bkin_polarity_mask;
+ uint32_t bkin_enable_bitpos;
+ uint32_t bkin_polarity_bitpos;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_BREAKINPUT(BreakInput));
+ assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
+ assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
+ if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_MDF1)
+ {
+ assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
+ }
+
+ /* Check input state */
+ __HAL_LOCK(htim);
+
+ switch (sBreakInputConfig->Source)
+ {
+ case TIM_BREAKINPUTSOURCE_BKIN:
+ {
+ bkin_enable_mask = TIM1_AF1_BKINE;
+ bkin_enable_bitpos = TIM1_AF1_BKINE_Pos;
+ bkin_polarity_mask = TIM1_AF1_BKINP;
+ bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos;
+ break;
+ }
+ case TIM_BREAKINPUTSOURCE_COMP1:
+ {
+ bkin_enable_mask = TIM1_AF1_BKCMP1E;
+ bkin_enable_bitpos = TIM1_AF1_BKCMP1E_Pos;
+ bkin_polarity_mask = TIM1_AF1_BKCMP1P;
+ bkin_polarity_bitpos = TIM1_AF1_BKCMP1P_Pos;
+ break;
+ }
+ case TIM_BREAKINPUTSOURCE_COMP2:
+ {
+ bkin_enable_mask = TIM1_AF1_BKCMP2E;
+ bkin_enable_bitpos = TIM1_AF1_BKCMP2E_Pos;
+ bkin_polarity_mask = TIM1_AF1_BKCMP2P;
+ bkin_polarity_bitpos = TIM1_AF1_BKCMP2P_Pos;
+ break;
+ }
+ case TIM_BREAKINPUTSOURCE_MDF1:
+ {
+ bkin_enable_mask = TIM1_AF1_BKDF1BK0E;
+ bkin_enable_bitpos = 8U;
+ bkin_polarity_mask = 0U;
+ bkin_polarity_bitpos = 0U;
+ break;
+ }
+
+ default:
+ {
+ bkin_enable_mask = 0U;
+ bkin_polarity_mask = 0U;
+ bkin_enable_bitpos = 0U;
+ bkin_polarity_bitpos = 0U;
+ break;
+ }
+ }
+
+ switch (BreakInput)
+ {
+ case TIM_BREAKINPUT_BRK:
+ {
+ /* Get the TIMx_AF1 register value */
+ tmporx = htim->Instance->AF1;
+
+ /* Enable the break input */
+ tmporx &= ~bkin_enable_mask;
+ tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
+
+ /* Set the break input polarity */
+ tmporx &= ~bkin_polarity_mask;
+ tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+
+ /* Set TIMx_AF1 */
+ htim->Instance->AF1 = tmporx;
+ break;
+ }
+ case TIM_BREAKINPUT_BRK2:
+ {
+ /* Get the TIMx_AF2 register value */
+ tmporx = htim->Instance->AF2;
+
+ /* Enable the break input */
+ tmporx &= ~bkin_enable_mask;
+ tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
+
+ /* Set the break input polarity */
+ tmporx &= ~bkin_polarity_mask;
+ tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+
+ /* Set TIMx_AF2 */
+ htim->Instance->AF2 = tmporx;
+ break;
+ }
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ __HAL_UNLOCK(htim);
+
+ return status;
+}
+
+/**
+ * @brief Configures the TIMx Remapping input capabilities.
+ * @param htim TIM handle.
+ * @param Remap specifies the TIM remapping source.
+ * For TIM1, the parameter can take one of the following values:
+ * @arg TIM_TIM1_ETR_GPIO TIM1 ETR is connected to GPIO
+ * @arg TIM_TIM1_ETR_COMP1 TIM1 ETR is connected to COMP1 output
+ * @arg TIM_TIM1_ETR_COMP2 TIM1 ETR is connected to COMP2 output
+ * @arg TIM_TIM1_ETR_HSI TIM1 ETR is connected to HSI
+ * @arg TIM_TIM1_ETR_MSIS TIM1_ETR is connected to MSIS
+ * @arg TIM_TIM1_ETR_ADC1_AWD1 TIM1 ETR is connected to ADC1 AWD1
+ * @arg TIM_TIM1_ETR_ADC1_AWD2 TIM1 ETR is connected to ADC1 AWD2
+ * @arg TIM_TIM1_ETR_ADC1_AWD3 TIM1 ETR is connected to ADC1 AWD3
+ * @arg TIM_TIM1_ETR_ADC4_AWD1 TIM1 ETR is connected to ADC4 AWD1
+ * @arg TIM_TIM1_ETR_ADC4_AWD2 TIM1 ETR is connected to ADC4 AWD2
+ * @arg TIM_TIM1_ETR_ADC4_AWD3 TIM1 ETR is connected to ADC4 AWD3
+ *
+ * For TIM2, the parameter can take one of the following values:
+ * @arg TIM_TIM2_ETR_GPIO TIM2 ETR is connected to GPIO
+ * @arg TIM_TIM2_ETR_COMP1 TIM2 ETR is connected to COMP1 output
+ * @arg TIM_TIM2_ETR_COMP2 TIM2 ETR is connected to COMP2 output
+ * @arg TIM_TIM2_ETR_MSIK TIM2 ETR is connected to MSIK
+ * @arg TIM_TIM2_ETR_HSI TIM2 ETR is connected to HSI
+ * @arg TIM_TIM2_ETR_MSIS TIM2_ETR is connected to MSIS
+ * @arg TIM_TIM2_ETR_TIM3_ETR TIM2 ETR is connected to TIM3 ETR pin
+ * @arg TIM_TIM2_ETR_TIM4_ETR TIM2 ETR is connected to TIM4 ETR pin
+ * @arg TIM_TIM2_ETR_TIM5_ETR TIM2 ETR is connected to TIM5 ETR pin
+ * @arg TIM_TIM2_ETR_LSE TIM2 ETR is connected to LSE
+ *
+ * For TIM3, the parameter can take one of the following values:
+ * @arg TIM_TIM3_ETR_GPIO TIM3 ETR is connected to GPIO
+ * @arg TIM_TIM3_ETR_COMP1 TIM3 ETR is connected to COMP1 output
+ * @arg TIM_TIM3_ETR_COMP2 TIM3 ETR is connected to COMP2 output
+ * @arg TIM_TIM3_ETR_MSIK TIM3 ETR is connected to MSIK
+ * @arg TIM_TIM3_ETR_HSI TIM3 ETR is connected to HSI
+ * @arg TIM_TIM3_ETR_MSIS TIM3_ETR is connected to MSIS
+ * @arg TIM_TIM3_ETR_TIM2_ETR TIM3 ETR is connected to TIM2 ETR pin
+ * @arg TIM_TIM3_ETR_TIM4_ETR TIM3 ETR is connected to TIM4 ETR pin
+ * @arg TIM_TIM3_ETR_ADC1_AWD1 TIM3 ETR is connected to ADC1 AWD1
+ * @arg TIM_TIM3_ETR_ADC1_AWD2 TIM3 ETR is connected to ADC1 AWD2
+ * @arg TIM_TIM3_ETR_ADC1_AWD3 TIM3 ETR is connected to ADC1 AWD3
+ *
+ * For TIM4, the parameter can take one of the following values:
+ * @arg TIM_TIM4_ETR_GPIO TIM4 ETR is connected to GPIO
+ * @arg TIM_TIM4_ETR_COMP1 TIM4 ETR is connected to COMP1 output
+ * @arg TIM_TIM4_ETR_COMP2 TIM4 ETR is connected to COMP2 output
+ * @arg TIM_TIM4_ETR_MSIK TIM4 ETR is connected to MSIK
+ * @arg TIM_TIM4_ETR_HSI TIM4 ETR is connected to HSI
+ * @arg TIM_TIM4_ETR_MSIS TIM4_ETR is connected to MSIS
+ * @arg TIM_TIM4_ETR_TIM3_ETR TIM4 ETR is connected to TIM3 ETR pin
+ * @arg TIM_TIM4_ETR_TIM5_ETR TIM4 ETR is connected to TIM5 ETR pin
+ *
+ * For TIM5, the parameter can take one of the following values:
+ * @arg TIM_TIM5_ETR_GPIO TIM5 ETR is connected to GPIO
+ * @arg TIM_TIM5_ETR_COMP1 TIM5 ETR is connected to COMP1 output
+ * @arg TIM_TIM5_ETR_COMP2 TIM5 ETR is connected to COMP2 output
+ * @arg TIM_TIM5_ETR_MSIK TIM5 ETR is connected to MSIK
+ * @arg TIM_TIM5_ETR_HSI TIM5 ETR is connected to HSI
+ * @arg TIM_TIM5_ETR_MSIS TIM5_ETR is connected to MSIS
+ * @arg TIM_TIM5_ETR_TIM2_ETR TIM5 ETR is connected to TIM2 ETR pin
+ * @arg TIM_TIM5_ETR_TIM3_ETR TIM5 ETR is connected to TIM3 ETR pin
+ *
+ * For TIM8, the parameter can take one of the following values:
+ * @arg TIM_TIM8_ETR_GPIO TIM8 ETR is connected to GPIO
+ * @arg TIM_TIM8_ETR_COMP1 TIM8 ETR is connected to COMP1 output
+ * @arg TIM_TIM8_ETR_COMP2 TIM8 ETR is connected to COMP2 output
+ * @arg TIM_TIM8_ETR_MSIK TIM8 ETR is connected to MSIK
+ * @arg TIM_TIM8_ETR_HSI TIM8 ETR is connected to HSI
+ * @arg TIM_TIM8_ETR_MSIS TIM8_ETR is connected to MSIS
+ * @arg TIM_TIM8_ETR_ADC1_AWD1 TIM8 ETR is connected to ADC1 AWD1
+ * @arg TIM_TIM8_ETR_ADC1_AWD2 TIM8 ETR is connected to ADC1 AWD2
+ * @arg TIM_TIM8_ETR_ADC1_AWD3 TIM8 ETR is connected to ADC1 AWD3
+ * @arg TIM_TIM8_ETR_ADC4_AWD1 TIM8 ETR is connected to ADC4 AWD1
+ * @arg TIM_TIM8_ETR_ADC4_AWD2 TIM8 ETR is connected to ADC4 AWD2
+ * @arg TIM_TIM8_ETR_ADC4_AWD3 TIM8 ETR is connected to ADC4 AWD3
+ *
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
+{
+ /* Check parameters */
+ assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_REMAP(Remap));
+
+ __HAL_LOCK(htim);
+
+ MODIFY_REG(htim->Instance->AF1, TIM1_AF1_ETRSEL_Msk, Remap);
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Select the timer input source
+ * @param htim TIM handle.
+ * @param Channel specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TI1 input channel
+ * @arg TIM_CHANNEL_2: TI2 input channel
+ * @arg TIM_CHANNEL_4: TIM Channel 4
+ * @param TISelection parameter of the TIM_TISelectionStruct structure is detailed as follows:
+ * For TIM1, the parameter is one of the following values:
+ * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO
+ * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output
+ * @arg TIM_TIM1_TI1_COMP2: TIM1 TI1 is connected to COMP2 output
+ *
+ * For TIM2, the parameter is one of the following values:
+ * @arg TIM_TIM2_TI1_GPIO: TIM2 TI1 is connected to GPIO
+ * @arg TIM_TIM2_TI1_COMP1: TIM2 TI1 is connected to COMP1 output
+ * @arg TIM_TIM2_TI1_COMP2: TIM2 TI1 is connected to COMP1 output
+ * @arg TIM_TIM2_TI2_GPIO: TIM2 TI2 is connected to GPIO
+ * @arg TIM_TIM2_TI2_COMP1: TIM2 TI2 is connected to COMP1 output
+ * @arg TIM_TIM2_TI2_COMP2: TIM2 TI2 is connected to COMP1 output
+ * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO
+ * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output
+ * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output
+ *
+ * For TIM3, the parameter is one of the following values:
+ * @arg TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to GPIO
+ * @arg TIM_TIM3_TI1_COMP1: TIM3 TI1 is connected to COMP1 output
+ * @arg TIM_TIM3_TI1_COMP2: TIM3 TI1 is connected to COMP2 output
+ * @arg TIM_TIM3_TI2_GPIO: TIM3 TI2 is connected to GPIO
+ * @arg TIM_TIM3_TI2_COMP1: TIM3 TI2 is connected to COMP1 output
+ * @arg TIM_TIM3_TI2_COMP2: TIM3 TI2 is connected to COMP1 output
+ *
+ * For TIM4, the parameter is one of the following values:
+ * @arg TIM_TIM4_TI1_GPIO: TIM4 TI1 is connected to GPIO
+ * @arg TIM_TIM4_TI1_COMP1: TIM4 TI1 is connected to COMP1 output
+ * @arg TIM_TIM4_TI1_COMP2: TIM4 TI1 is connected to COMP2 output
+ * @arg TIM_TIM4_TI2_GPIO: TIM4 TI2 is connected to GPIO
+ * @arg TIM_TIM4_TI2_COMP1: TIM4 TI2 is connected to COMP1 output
+ * @arg TIM_TIM4_TI2_COMP2: TIM4 TI2 is connected to COMP2 output
+ *
+ * For TIM5, the parameter is one of the following values:
+ * @arg TIM_TIM5_TI1_GPIO: TIM5 TI1 is connected to GPIO
+ * @arg TIM_TIM5_TI1_LSI: TIM5 TI1 is connected to LSI
+ * @arg TIM_TIM5_TI1_LSE: TIM5 TI1 is connected to LSE
+ * @arg TIM_TIM5_TI1_RTC_WKUP: TIM5 TI1 is connected to RTC wakeup interrupt
+ * @arg TIM_TIM5_TI1_COMP1: TIM5 TI1 is connected to COMP1 output
+ * @arg TIM_TIM5_TI1_COMP2: TIM5 TI1 is connected to COMP2 output
+ * @arg TIM_TIM5_TI2_GPIO: TIM5 TI2 is connected to GPIO
+ * @arg TIM_TIM5_TI2_COMP1: TIM5 TI2 is connected to COMP1 output
+ * @arg TIM_TIM5_TI2_COMP2: TIM5 TI2 is connected to COMP2 output
+ *
+ * For TIM8, the parameter is one of the following values:
+ * @arg TIM_TIM8_TI1_GPIO: TIM8 TI1 is connected to GPIO
+ * @arg TIM_TIM8_TI1_COMP1: TIM8 TI1 is connected to COMP1 output
+ * @arg TIM_TIM8_TI1_COMP2: TIM8 TI1 is connected to COMP2 output
+ *
+ * For TIM15, the parameter is one of the following values:
+ * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO
+ * @arg TIM_TIM15_TI1_LSE: TIM15 TI1 is connected to LSE
+ * @arg TIM_TIM15_TI1_COMP1: TIM8 TI1 is connected to COMP1 output
+ * @arg TIM_TIM15_TI1_COMP2: TIM8 TI1 is connected to COMP2 output
+ * @arg TIM_TIM15_TI2_GPIO: TIM15 TI2 is connected to GPIO
+ * @arg TIM_TIM15_TI2_TIM2: TIM15 TI2 is connected to TIM2 CH2
+ * @arg TIM_TIM15_TI2_TIM3: TIM15 TI2 is connected to TIM3 CH2
+ * @arg TIM_TIM15_TI2_COMP2: TIM8 TI1 is connected to COMP2 output
+ *
+ * For TIM16, the parameter can have the following values:
+ * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO
+ * @arg TIM_TIM16_TI1_MCO: TIM16 TI1 is connected to MCO
+ * @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI
+ * @arg TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE
+ * @arg TIM_TIM16_TI1_RTC_WKUP: TIM16 TI1 is connected to RTC wakeup interrupt
+ * @arg TIM_TIM16_TI1_HSE_DIV32: TIM16 TI1 is connected to HSE/32
+ * @arg TIM_TIM16_TI1_MSIS_1024: TIM16 TI1 is connected to MSIS/1024
+ * @arg TIM_TIM16_TI1_MSIS_4: TIM16 TI1 is connected to MSIS/4
+ * @arg TIM_TIM16_TI1_HSI_256: TIM16 TI1 is connected to HSI/256
+ *
+ * For TIM17, the parameter can have the following values:
+ * @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO
+ * @arg TIM_TIM17_TI1_MCO: TIM17 TI1 is connected to MCO
+ * @arg TIM_TIM17_TI1_LSI: TIM17 TI1 is connected to LSI
+ * @arg TIM_TIM17_TI1_LSE: TIM17 TI1 is connected to LSE
+ * @arg TIM_TIM17_TI1_RTC_WKUP: TIM17 TI1 is connected to RTC wakeup interrupt
+ * @arg TIM_TIM17_TI1_HSE_DIV32: TIM17 TI1 is connected to HSE/32
+ * @arg TIM_TIM17_TI1_MSIS_1024: TIM17 TI1 is connected to MSIS/024
+ * @arg TIM_TIM17_TI1_MSIS_4: TIM17 TI1 is connected to MSIS/4
+ * @arg TIM_TIM17_TI1_HSI_256: TIM17 TI1 is connected to HSI/256
+ *
+ * (*) Value not defined in all devices. \n
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_TIM_TISEL_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TISEL(TISelection));
+
+ __HAL_LOCK(htim);
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI1SEL, TISelection);
+ break;
+ case TIM_CHANNEL_2:
+ MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI2SEL, TISelection);
+ break;
+ case TIM_CHANNEL_4:
+ MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI4SEL, TISelection);
+ break;
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ __HAL_UNLOCK(htim);
+
+ return status;
+}
+
+/**
+ * @brief Group channel 5 and channel 1, 2 or 3
+ * @param htim TIM handle.
+ * @param Channels specifies the reference signal(s) the OC5REF is combined with.
+ * This parameter can be any combination of the following values:
+ * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
+ * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
+ * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
+ * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
+{
+ /* Check parameters */
+ assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_GROUPCH5(Channels));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Clear GC5Cx bit fields */
+ htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1);
+
+ /* Set GC5Cx bit fields */
+ htim->Instance->CCR5 |= Channels;
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disarm the designated break input (when it operates in bidirectional mode).
+ * @param htim TIM handle.
+ * @param BreakInput Break input to disarm
+ * This parameter can be one of the following values:
+ * @arg TIM_BREAKINPUT_BRK: Timer break input
+ * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
+ * @note The break input can be disarmed only when it is configured in
+ * bidirectional mode and when when MOE is reset.
+ * @note Purpose is to be able to have the input voltage back to high-state,
+ * whatever the time constant on the output .
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpbdtr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_BREAKINPUT(BreakInput));
+
+ switch (BreakInput)
+ {
+ case TIM_BREAKINPUT_BRK:
+ {
+ /* Check initial conditions */
+ tmpbdtr = READ_REG(htim->Instance->BDTR);
+ if ((READ_BIT(tmpbdtr, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) &&
+ (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
+ {
+ /* Break input BRK is disarmed */
+ SET_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM);
+ }
+ break;
+ }
+
+ case TIM_BREAKINPUT_BRK2:
+ {
+ /* Check initial conditions */
+ tmpbdtr = READ_REG(htim->Instance->BDTR);
+ if ((READ_BIT(tmpbdtr, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) &&
+ (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
+ {
+ /* Break input BRK is disarmed */
+ SET_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM);
+ }
+ break;
+ }
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Arm the designated break input (when it operates in bidirectional mode).
+ * @param htim TIM handle.
+ * @param BreakInput Break input to arm
+ * This parameter can be one of the following values:
+ * @arg TIM_BREAKINPUT_BRK: Timer break input
+ * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
+ * @note Arming is possible at anytime, even if fault is present.
+ * @note Break input is automatically armed as soon as MOE bit is set.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tickstart;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_BREAKINPUT(BreakInput));
+
+ switch (BreakInput)
+ {
+ case TIM_BREAKINPUT_BRK:
+ {
+ /* Check initial conditions */
+ if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKBID) == TIM_BDTR_BKBID)
+ {
+ /* Break input BRK is re-armed automatically by hardware. Poll to check whether fault condition disappeared */
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+ while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
+ {
+ if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT)
+ {
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ break;
+ }
+
+ case TIM_BREAKINPUT_BRK2:
+ {
+ /* Check initial conditions */
+ if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID)
+ {
+ /* Break input BRK2 is re-armed automatically by hardware. Poll to check whether fault condition disappeared */
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+ while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
+ {
+ if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT)
+ {
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ break;
+ }
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Enable dithering
+ * @param htim TIM handle
+ * @note Main usage is PWM mode
+ * @note This function must be called when timer is stopped or disabled (CEN =0)
+ * @note If dithering is activated, pay attention to ARR, CCRx, CNT interpretation:
+ * - CNT: only CNT[11:0] holds the non-dithered part for 16b timers (or CNT[26:0] for 32b timers)
+ * - ARR: ARR[15:4] holds the non-dithered part, and ARR[3:0] the dither part for 16b timers
+ * - CCRx: CCRx[15:4] holds the non-dithered part, and CCRx[3:0] the dither part for 16b timers
+ * - ARR and CCRx values are limited to 0xFFEF in dithering mode for 16b timers
+ * (corresponds to 4094 for the integer part and 15 for the dithered part).
+ * @note Macros @ref __HAL_TIM_CALC_PERIOD_DITHER() __HAL_TIM_CALC_DELAY_DITHER() __HAL_TIM_CALC_PULSE_DITHER()
+ * can be used to calculate period (ARR) and delay (CCRx) value.
+ * @note Enabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part.
+ * @note Enabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part.
+ * So it may be necessary to read ARR value or CCRx value with macros @ref __HAL_TIM_GET_AUTORELOAD()
+ * __HAL_TIM_GET_COMPARE() and if necessary update Init structure field htim->Init.Period .
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ SET_BIT(htim->Instance->CR1, TIM_CR1_DITHEN);
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable dithering
+ * @param htim TIM handle
+ * @note This function must be called when timer is stopped or disabled (CEN =0)
+ * @note If dithering is activated, pay attention to ARR, CCRx, CNT interpretation:
+ * - CNT: only CNT[11:0] holds the non-dithered part for 16b timers (or CNT[26:0] for 32b timers)
+ * - ARR: ARR[15:4] holds the non-dithered part, and ARR[3:0] the dither part for 16b timers
+ * - CCRx: CCRx[15:4] holds the non-dithered part, and CCRx[3:0] the dither part for 16b timers
+ * - ARR and CCRx values are limited to 0xFFEF in dithering mode
+ * (corresponds to 4094 for the integer part and 15 for the dithered part).
+ * @note Disabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part.
+ * So it may be necessary to read ARR value or CCRx value with macros @ref __HAL_TIM_GET_AUTORELOAD()
+ * __HAL_TIM_GET_COMPARE() and if necessary update Init structure field htim->Init.Period .
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ CLEAR_BIT(htim->Instance->CR1, TIM_CR1_DITHEN);
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the pulse on compare pulse width and pulse prescaler
+ * @param htim TIM Output Compare handle
+ * @param PulseWidthPrescaler Pulse width prescaler
+ * This parameter can be a number between Min_Data = 0x0 and Max_Data = 0x7
+ * @param PulseWidth Pulse width
+ * This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OC_ConfigPulseOnCompare(TIM_HandleTypeDef *htim,
+ uint32_t PulseWidthPrescaler,
+ uint32_t PulseWidth)
+{
+ uint32_t tmpecr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_PULSEONCOMPARE_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_PULSEONCOMPARE_WIDTH(PulseWidth));
+ assert_param(IS_TIM_PULSEONCOMPARE_WIDTHPRESCALER(PulseWidthPrescaler));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Get the TIMx ECR register value */
+ tmpecr = htim->Instance->ECR;
+ /* Reset the Pulse width prescaler and the Pulse width */
+ tmpecr &= ~(TIM_ECR_PWPRSC | TIM_ECR_PW);
+ /* Set the Pulse width prescaler and Pulse width*/
+ tmpecr |= PulseWidthPrescaler << TIM_ECR_PWPRSC_Pos;
+ tmpecr |= PulseWidth << TIM_ECR_PW_Pos;
+ /* Write to TIMx ECR */
+ htim->Instance->ECR = tmpecr;
+
+ /* Change the TIM state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure preload source of Slave Mode Selection bitfield (SMS in SMCR register)
+ * @param htim TIM handle
+ * @param Source Source of slave mode selection preload
+ * This parameter can be one of the following values:
+ * @arg TIM_SMS_PRELOAD_SOURCE_UPDATE: Timer update event is used as source of Slave Mode Selection preload
+ * @arg TIM_SMS_PRELOAD_SOURCE_INDEX: Timer index event is used as source of Slave Mode Selection preload
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigSlaveModePreload(TIM_HandleTypeDef *htim, uint32_t Source)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_SLAVE_PRELOAD_SOURCE(Source));
+
+ MODIFY_REG(htim->Instance->SMCR, TIM_SMCR_SMSPS, Source);
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable preload of Slave Mode Selection bitfield (SMS in SMCR register)
+ * @param htim TIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_EnableSlaveModePreload(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+
+ SET_BIT(htim->Instance->SMCR, TIM_SMCR_SMSPE);
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable preload of Slave Mode Selection bitfield (SMS in SMCR register)
+ * @param htim TIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_DisableSlaveModePreload(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+
+ CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_SMSPE);
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable deadtime preload
+ * @param htim TIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_EnableDeadTimePreload(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+
+ SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE);
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable deadtime preload
+ * @param htim TIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_DisableDeadTimePreload(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+
+ CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE);
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure deadtime
+ * @param htim TIM handle
+ * @param Deadtime Deadtime value
+ * @note This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigDeadTime(TIM_HandleTypeDef *htim, uint32_t Deadtime)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_DEADTIME(Deadtime));
+
+ MODIFY_REG(htim->Instance->BDTR, TIM_BDTR_DTG, Deadtime);
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure asymmetrical deadtime
+ * @param htim TIM handle
+ * @param FallingDeadtime Falling edge deadtime value
+ * @note This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigAsymmetricalDeadTime(TIM_HandleTypeDef *htim, uint32_t FallingDeadtime)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_DEADTIME(FallingDeadtime));
+
+ MODIFY_REG(htim->Instance->DTR2, TIM_DTR2_DTGF, FallingDeadtime);
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable asymmetrical deadtime
+ * @param htim TIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_EnableAsymmetricalDeadTime(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+
+ SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE);
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable asymmetrical deadtime
+ * @param htim TIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_DisableAsymmetricalDeadTime(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+
+ CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE);
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the encoder index.
+ * @note warning in case of encoder mode clock plus direction
+ * @ref TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 or @ref TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2
+ * Direction must be set to @ref TIM_ENCODERINDEX_DIRECTION_UP_DOWN
+ * @param htim TIM handle.
+ * @param sEncoderIndexConfig Encoder index configuration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigEncoderIndex(TIM_HandleTypeDef *htim,
+ TIMEx_EncoderIndexConfigTypeDef *sEncoderIndexConfig)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODERINDEX_POLARITY(sEncoderIndexConfig->Polarity));
+ assert_param(IS_TIM_ENCODERINDEX_PRESCALER(sEncoderIndexConfig->Prescaler));
+ assert_param(IS_TIM_ENCODERINDEX_FILTER(sEncoderIndexConfig->Filter));
+ assert_param(IS_TIM_ENCODERINDEX_BLANKING(sEncoderIndexConfig->Blanking));
+ assert_param(IS_FUNCTIONAL_STATE(sEncoderIndexConfig->FirstIndexEnable));
+ assert_param(IS_TIM_ENCODERINDEX_POSITION(sEncoderIndexConfig->Position));
+ assert_param(IS_TIM_ENCODERINDEX_DIRECTION(sEncoderIndexConfig->Direction));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ /* Configures the TIMx External Trigger (ETR) which is used as Index input */
+ TIM_ETR_SetConfig(htim->Instance,
+ sEncoderIndexConfig->Prescaler,
+ sEncoderIndexConfig->Polarity,
+ sEncoderIndexConfig->Filter);
+
+ /* Configures the encoder index */
+ if (HAL_GetREVID() >= REV_ID_B) /* supported in cut2 */
+ {
+ MODIFY_REG(htim->Instance->ECR,
+ TIM_ECR_IDIR_Msk | TIM_ECR_IBLK_Msk | TIM_ECR_FIDX_Msk | TIM_ECR_IPOS_Msk,
+ (sEncoderIndexConfig->Direction |
+ (sEncoderIndexConfig->Blanking) |
+ ((sEncoderIndexConfig->FirstIndexEnable == ENABLE) ? (0x1U << TIM_ECR_FIDX_Pos) : 0U) |
+ sEncoderIndexConfig->Position |
+ TIM_ECR_IE));
+ }
+ else
+ {
+ MODIFY_REG(htim->Instance->ECR,
+ TIM_ECR_IDIR_Msk | TIM_ECR_FIDX_Msk | TIM_ECR_IPOS_Msk,
+ (sEncoderIndexConfig->Direction |
+ ((sEncoderIndexConfig->FirstIndexEnable == ENABLE) ? (0x1U << TIM_ECR_FIDX_Pos) : 0U) |
+ sEncoderIndexConfig->Position |
+ TIM_ECR_IE));
+ }
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable encoder index
+ * @param htim TIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_EnableEncoderIndex(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+ SET_BIT(htim->Instance->ECR, TIM_ECR_IE);
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable encoder index
+ * @param htim TIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_DisableEncoderIndex(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+ CLEAR_BIT(htim->Instance->ECR, TIM_ECR_IE);
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable encoder first index
+ * @param htim TIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_EnableEncoderFirstIndex(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+ SET_BIT(htim->Instance->ECR, TIM_ECR_FIDX);
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable encoder first index
+ * @param htim TIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+ CLEAR_BIT(htim->Instance->ECR, TIM_ECR_FIDX);
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
+ * @brief Extended Callbacks functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Extended Callbacks functions #####
+ ==============================================================================
+ [..]
+ This section provides Extended TIM callback functions:
+ (+) Timer Commutation callback
+ (+) Timer Break callback
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Hall commutation changed callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIMEx_CommutCallback could be implemented in the user file
+ */
+}
+/**
+ * @brief Hall commutation changed half complete callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Hall Break detection callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIMEx_BreakCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Hall Break2 detection callback in non blocking mode
+ * @param htim: TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIMEx_Break2Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Encoder index callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIMEx_EncoderIndexCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Direction change callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIMEx_DirectionChangeCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Index error callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIMEx_IndexErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Transition error callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIMEx_TransitionErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
+ * @brief Extended Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Extended Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the TIM Hall Sensor interface handle state.
+ * @param htim TIM Hall Sensor handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return actual state of the TIM complementary channel.
+ * @param htim TIM handle
+ * @param ChannelN TIM Complementary channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @arg TIM_CHANNEL_4: TIM Channel 4
+ * @retval TIM Complementary channel state
+ */
+HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN)
+{
+ HAL_TIM_ChannelStateTypeDef channel_state;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));
+
+ channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);
+
+ return channel_state;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
+ * @{
+ */
+
+/**
+ * @brief TIM DMA Commutation callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->CommutationCallback(htim);
+#else
+ HAL_TIMEx_CommutCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief TIM DMA Commutation half complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->CommutationHalfCpltCallback(htim);
+#else
+ HAL_TIMEx_CommutHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+
+/**
+ * @brief TIM DMA Delay Pulse complete callback (complementary channel).
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PWM_PulseFinishedCallback(htim);
+#else
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief TIM DMA error callback (complementary channel)
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->ErrorCallback(htim);
+#else
+ HAL_TIM_ErrorCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel xN.
+ * @param TIMx to select the TIM peripheral
+ * @param Channel specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @arg TIM_CHANNEL_4: TIM Channel 4
+ * @param ChannelNState specifies the TIM Channel CCxNE bit new state.
+ * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
+ * @retval None
+ */
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
+{
+ uint32_t tmp;
+
+ tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
+
+ /* Reset the CCxNE Bit */
+ TIMx->CCER &= ~tmp;
+
+ /* Set or reset the CCxNE Bit */
+ TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
+}
+
+/**
+ * @brief Enable HSE/32 .
+ * @note This function should be called to enable the HSE/32 when it is selected as TIM17_TI1 or TIM16_TI1 input
+ * source.
+ * @param htim TIM handle.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_TIMEx_EnableHSE32(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_HSE32_INSTANCE(htim->Instance));
+
+ /* The Cut1.x contains a limitation when using HSE/32 as input capture for TIM16
+ Bug ID 56: On TIM16, the HSE/32 input capture requires the set of HSE32EN bit of TIM17 Option Register */
+ if (HAL_GetREVID() < REV_ID_B) /* Cut1.x */
+ {
+ __HAL_RCC_TIM17_CLK_ENABLE();
+ SET_BIT(TIM17->OR1, TIM_OR1_HSE32EN);
+ }
+ else
+ {
+ SET_BIT(htim->Instance->OR1, TIM_OR1_HSE32EN);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable HSE/32 .
+ * @note This function should be called to Disable the HSE/32 .
+ * @param htim TIM handle.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_TIMEx_DisableHSE32(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_HSE32_INSTANCE(htim->Instance));
+
+ if (HAL_GetREVID() < REV_ID_B) /* Cut1.x */
+ {
+ __HAL_RCC_TIM17_CLK_ENABLE();
+ CLEAR_BIT(TIM17->OR1, TIM_OR1_HSE32EN);
+ }
+ else
+ {
+ CLEAR_BIT(htim->Instance->OR1, TIM_OR1_HSE32EN);
+ }
+
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_timebase_rtc_alarm_template.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_timebase_rtc_alarm_template.c
new file mode 100644
index 00000000..0eefe30a
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_timebase_rtc_alarm_template.c
@@ -0,0 +1,277 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_timebase_rtc_alarm_template.c
+ * @author MCD Application Team
+ * @brief HAL time base based on the hardware RTC_ALARM Template.
+ *
+ * This file overrides the native HAL time base functions (defined as weak)
+ * to use the RTC ALARM for time base generation:
+ * + Initializes the RTC peripheral to increment the seconds registers each 1ms
+ * + The alarm is configured to assert an interrupt when the RTC reaches 1ms
+ * + HAL_IncTick is called at each Alarm event
+ * + HSE (default), LSE or LSI can be selected as RTC clock source
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This file must be copied to the application folder and modified as follows:
+ (#) Rename it to 'stm32u5xx_hal_timebase_rtc_alarm.c'
+ (#) Add this file and the RTC HAL drivers to your project and uncomment
+ HAL_RTC_MODULE_ENABLED define in stm32u5xx_hal_conf.h
+
+ [..]
+ (@) HAL RTC alarm and HAL RTC wakeup drivers can not be used with low power modes:
+ The wake up capability of the RTC may be intrusive in case of prior low power mode
+ configuration requiring different wake up sources.
+ Application/Example behavior is no more guaranteed
+ (@) The stm32u5xx_hal_timebase_tim use is recommended for the Applications/Examples
+ requiring low power modes
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup HAL_TimeBase_RTC_Alarm_Template HAL TimeBase RTC Alarm Template
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* Uncomment the line below to select the appropriate RTC Clock source for your application:
+ + RTC_CLOCK_SOURCE_HSE: can be selected for applications requiring timing precision.
+ + RTC_CLOCK_SOURCE_LSE: can be selected for applications with low constraint on timing
+ precision.
+ + RTC_CLOCK_SOURCE_LSI: can be selected for applications with low constraint on timing
+ precision.
+ */
+/* #define RTC_CLOCK_SOURCE_HSE */
+/* #define RTC_CLOCK_SOURCE_LSE */
+#define RTC_CLOCK_SOURCE_LSI
+
+/* The time base should be 1ms
+ Time base = ((RTC_ASYNCH_PREDIV + 1) * (RTC_SYNCH_PREDIV + 1)) / RTC_CLOCK
+*/
+#if defined (RTC_CLOCK_SOURCE_HSE)
+#define RTC_ASYNCH_PREDIV 99U
+#define RTC_SYNCH_PREDIV 4U
+#elif defined (RTC_CLOCK_SOURCE_LSE)
+#define RTC_ASYNCH_PREDIV 0U
+#define RTC_SYNCH_PREDIV 32U
+#elif defined (RTC_CLOCK_SOURCE_LSI)
+#define RTC_ASYNCH_PREDIV 0U
+#define RTC_SYNCH_PREDIV 31U
+#else
+#error Please select the RTC Clock source
+#endif /* RTC_CLOCK_SOURCE_LSE */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+static RTC_HandleTypeDef hRTC_Handle;
+
+/* Private function prototypes -----------------------------------------------*/
+void RTC_IRQHandler(void);
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1U)
+void TimeBase_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @brief This function configures the RTC_ALARMA as a time base source.
+ * The time source is configured to have 1ms time base with a dedicated
+ * Tick interrupt priority.
+ * @note This function is called automatically at the beginning of program after
+ * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
+ * @param TickPriority Tick interrupt priority.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+ HAL_StatusTypeDef Status;
+
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+
+ /* Disable bkup domain protection */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ HAL_PWR_EnableBkUpAccess();
+
+ /* Force and Release the Backup domain reset */
+ __HAL_RCC_BACKUPRESET_FORCE();
+ __HAL_RCC_BACKUPRESET_RELEASE();
+
+ /* Enable RTC Clock */
+ __HAL_RCC_RTC_ENABLE();
+ __HAL_RCC_RTCAPB_CLK_ENABLE();
+
+#if defined (RTC_CLOCK_SOURCE_LSE)
+ /* Configure LSE as RTC clock source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+ RCC_OscInitStruct.LSEState = RCC_LSE_ON_RTC_ONLY;
+ PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
+#elif defined (RTC_CLOCK_SOURCE_LSI)
+ /* Configure LSI as RTC clock source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+ RCC_OscInitStruct.LSIDiv = RCC_LSI_DIV1;
+ RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+ PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
+#elif defined (RTC_CLOCK_SOURCE_HSE)
+ /* Configure HSE as RTC clock source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+ PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_HSE_DIV32;
+#else
+#error Please select the RTC Clock source
+#endif /* RTC_CLOCK_SOURCE_LSE */
+
+ Status = HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+ if (Status == HAL_OK)
+ {
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
+ Status = HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+ }
+
+ if (Status == HAL_OK)
+ {
+ hRTC_Handle.Instance = RTC;
+ hRTC_Handle.Init.HourFormat = RTC_HOURFORMAT_24;
+ hRTC_Handle.Init.AsynchPrediv = RTC_ASYNCH_PREDIV;
+ hRTC_Handle.Init.SynchPrediv = RTC_SYNCH_PREDIV;
+ hRTC_Handle.Init.OutPut = RTC_OUTPUT_DISABLE;
+ hRTC_Handle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
+ hRTC_Handle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
+ hRTC_Handle.Init.BinMode = RTC_BINARY_NONE;
+
+ Status = HAL_RTC_Init(&hRTC_Handle);
+
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1U)
+ HAL_RTC_RegisterCallback(&hRTC_Handle, HAL_RTC_ALARM_A_EVENT_CB_ID, TimeBase_RTC_AlarmAEventCallback);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+ }
+
+ if (Status == HAL_OK)
+ {
+ /* RTC variables */
+ RTC_AlarmTypeDef RTC_AlarmStructure;
+
+ /* RTC Alarm Generation */
+ RTC_AlarmStructure.Alarm = RTC_ALARM_A;
+ RTC_AlarmStructure.AlarmDateWeekDay = RTC_WEEKDAY_MONDAY;
+ RTC_AlarmStructure.AlarmDateWeekDaySel = RTC_ALARMDATEWEEKDAYSEL_DATE;
+ /* Mask all and keep only subsecond, to have one match in each time base 1ms(uwTickFreq) */
+ RTC_AlarmStructure.AlarmMask = RTC_ALARMMASK_ALL;
+ RTC_AlarmStructure.AlarmSubSecondMask = RTC_ALARMSUBSECONDMASK_NONE;
+ RTC_AlarmStructure.AlarmTime.TimeFormat = RTC_HOURFORMAT_24;
+ RTC_AlarmStructure.AlarmTime.Hours = 0;
+ RTC_AlarmStructure.AlarmTime.Minutes = 0;
+ RTC_AlarmStructure.AlarmTime.Seconds = 0;
+ RTC_AlarmStructure.AlarmTime.SubSeconds = 0;
+
+ /* Set the specified RTC Alarm with Interrupt */
+ Status = HAL_RTC_SetAlarm_IT(&hRTC_Handle, &RTC_AlarmStructure, RTC_FORMAT_BCD);
+ }
+
+ if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+ {
+ /* Enable the RTC global Interrupt */
+ HAL_NVIC_SetPriority(RTC_IRQn, TickPriority, 0);
+ uwTickPrio = TickPriority;
+ }
+ else
+ {
+ Status = HAL_ERROR;
+ }
+
+ HAL_NVIC_EnableIRQ(RTC_IRQn);
+
+ return Status;
+}
+
+/**
+ * @brief Suspend Tick increment.
+ * @note Disable the tick increment by disabling RTC ALARM interrupt.
+ * @retval None
+ */
+void HAL_SuspendTick(void)
+{
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
+ /* Disable RTC ALARM update Interrupt */
+ __HAL_RTC_ALARM_DISABLE_IT(&hRTC_Handle, RTC_IT_ALRA);
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
+}
+
+/**
+ * @brief Resume Tick increment.
+ * @note Enable the tick increment by Enabling RTC ALARM interrupt.
+ * @retval None
+ */
+void HAL_ResumeTick(void)
+{
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
+ /* Enable RTC ALARM Update interrupt */
+ __HAL_RTC_ALARM_ENABLE_IT(&hRTC_Handle, RTC_IT_ALRA);
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
+}
+
+/**
+ * @brief ALARM A Event Callback in non blocking mode
+ * @note This function is called when RTC_ALARM interrupt took place, inside
+ * RTC_ALARM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
+ * a global variable "uwTick" used as application time base.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1U)
+void TimeBase_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
+#else
+void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ HAL_IncTick();
+}
+
+/**
+ * @brief This function handles RTC ALARM interrupt request.
+ * @retval None
+ */
+void RTC_IRQHandler(void)
+{
+ HAL_RTC_AlarmIRQHandler(&hRTC_Handle);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_timebase_rtc_wakeup_template.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_timebase_rtc_wakeup_template.c
new file mode 100644
index 00000000..f820d252
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_timebase_rtc_wakeup_template.c
@@ -0,0 +1,261 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_timebase_rtc_wakeup_template.c
+ * @author MCD Application Team
+ * @brief HAL time base based on the hardware RTC_WAKEUP Template.
+ *
+ * This file overrides the native HAL time base functions (defined as weak)
+ * to use the RTC WAKEUP for the time base generation:
+ * + Initializes the RTC peripheral and configures the wakeup timer to be
+ * incremented each 1ms
+ * + The wakeup feature is configured to assert an interrupt each 1ms
+ * + HAL_IncTick is called inside the HAL_RTCEx_WakeUpTimerEventCallback
+ * + HSE (default), LSE or LSI can be selected as RTC clock source
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This file must be copied to the application folder and modified as follows:
+ (#) Rename it to 'stm32u5xx_hal_timebase_rtc_wakeup.c'
+ (#) Add this file and the RTC HAL drivers to your project and uncomment
+ HAL_RTC_MODULE_ENABLED define in stm32u5xx_hal_conf.h
+
+ [..]
+ (@) HAL RTC alarm and HAL RTC wakeup drivers can not be used with low power modes:
+ The wake up capability of the RTC may be intrusive in case of prior low power mode
+ configuration requiring different wake up sources.
+ Application/Example behavior is no more guaranteed
+ (@) The stm32u5xx_hal_timebase_tim use is recommended for the Applications/Examples
+ requiring low power modes
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup HAL_TimeBase_RTC_Alarm_Template HAL TimeBase RTC Alarm Template
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* Uncomment the line below to select the appropriate RTC Clock source for your application:
+ + RTC_CLOCK_SOURCE_HSE: can be selected for applications requiring timing precision.
+ + RTC_CLOCK_SOURCE_LSE: can be selected for applications with low constraint on timing
+ precision.
+ + RTC_CLOCK_SOURCE_LSI: can be selected for applications with low constraint on timing
+ precision.
+ */
+/* #define RTC_CLOCK_SOURCE_HSE */
+/* #define RTC_CLOCK_SOURCE_LSE */
+#define RTC_CLOCK_SOURCE_LSI
+
+/* The time base should be 1ms
+ Time base = ((RTC_ASYNCH_PREDIV + 1) * (RTC_SYNCH_PREDIV + 1)) / RTC_CLOCK
+*/
+#if defined (RTC_CLOCK_SOURCE_HSE)
+#define RTC_ASYNCH_PREDIV 99U
+#define RTC_SYNCH_PREDIV 4U
+#elif defined (RTC_CLOCK_SOURCE_LSE)
+#define RTC_ASYNCH_PREDIV 0U
+#define RTC_SYNCH_PREDIV 32U
+#elif defined (RTC_CLOCK_SOURCE_LSI)
+#define RTC_ASYNCH_PREDIV 0U
+#define RTC_SYNCH_PREDIV 31U
+#else
+#error Please select the RTC Clock source
+#endif /* RTC_CLOCK_SOURCE_LSE */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+static RTC_HandleTypeDef hRTC_Handle;
+
+/* Private function prototypes -----------------------------------------------*/
+void RTC_IRQHandler(void);
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1U)
+void TimeBase_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @brief This function configures the RTC_ALARMA as a time base source.
+ * The time source is configured to have 1ms time base with a dedicated
+ * Tick interrupt priority.
+ * @note This function is called automatically at the beginning of program after
+ * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
+ * @param TickPriority Tick interrupt priority.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+ HAL_StatusTypeDef Status;
+
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+
+ /* Disable bkup domain protection */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ HAL_PWR_EnableBkUpAccess();
+
+ /* Force and Release the Backup domain reset */
+ __HAL_RCC_BACKUPRESET_FORCE();
+ __HAL_RCC_BACKUPRESET_RELEASE();
+
+ /* Enable RTC Clock */
+ __HAL_RCC_RTC_ENABLE();
+ __HAL_RCC_RTCAPB_CLK_ENABLE();
+
+#if defined (RTC_CLOCK_SOURCE_LSE)
+ /* Configure LSE as RTC clock source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+ RCC_OscInitStruct.LSEState = RCC_LSE_RTC_ONLY;
+ PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
+#elif defined (RTC_CLOCK_SOURCE_LSI)
+ /* Configure LSI as RTC clock source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+ RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+ RCC_OscInitStruct.LSIDiv = RCC_LSI_DIV1;
+ PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
+#elif defined (RTC_CLOCK_SOURCE_HSE)
+ /* Configure HSE as RTC clock source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+ PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_HSE_DIV32;
+#else
+#error Please select the RTC Clock source
+#endif /* RTC_CLOCK_SOURCE_LSE */
+
+ Status = HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+ if (Status == HAL_OK)
+ {
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
+ Status = HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+ }
+
+ if (Status == HAL_OK)
+ {
+ hRTC_Handle.Instance = RTC;
+ hRTC_Handle.Init.HourFormat = RTC_HOURFORMAT_24;
+ hRTC_Handle.Init.AsynchPrediv = RTC_ASYNCH_PREDIV;
+ hRTC_Handle.Init.SynchPrediv = RTC_SYNCH_PREDIV;
+ hRTC_Handle.Init.OutPut = RTC_OUTPUT_DISABLE;
+ hRTC_Handle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
+ hRTC_Handle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
+ hRTC_Handle.Init.BinMode = RTC_BINARY_NONE;
+
+ Status = HAL_RTC_Init(&hRTC_Handle);
+
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1U)
+ HAL_RTC_RegisterCallback(&hRTC_Handle, HAL_RTC_WAKEUPTIMER_EVENT_CB_ID, TimeBase_RTCEx_WakeUpTimerEventCallback);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+ }
+
+ if (Status == HAL_OK)
+ {
+ Status = HAL_RTCEx_SetWakeUpTimer_IT(&hRTC_Handle, 0, RTC_WAKEUPCLOCK_CK_SPRE_16BITS, 0);
+ }
+
+ if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+ {
+ /* Enable the RTC global Interrupt */
+ HAL_NVIC_SetPriority(RTC_IRQn, TickPriority, 0U);
+ uwTickPrio = TickPriority;
+ }
+ else
+ {
+ Status = HAL_ERROR;
+ }
+
+ HAL_NVIC_EnableIRQ(RTC_IRQn);
+
+ return Status;
+}
+
+/**
+ * @brief Suspend Tick increment.
+ * @note Disable the tick increment by disabling RTC_WKUP interrupt.
+ * @retval None
+ */
+void HAL_SuspendTick(void)
+{
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
+ /* Disable WAKE UP TIMER Interrupt */
+ __HAL_RTC_WAKEUPTIMER_DISABLE_IT(&hRTC_Handle, RTC_IT_WUT);
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
+}
+
+/**
+ * @brief Resume Tick increment.
+ * @note Enable the tick increment by Enabling RTC_WKUP interrupt.
+ * @retval None
+ */
+void HAL_ResumeTick(void)
+{
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
+ /* Enable WAKE UP TIMER interrupt */
+ __HAL_RTC_WAKEUPTIMER_ENABLE_IT(&hRTC_Handle, RTC_IT_WUT);
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
+}
+
+/**
+ * @brief Wake Up Timer Event Callback in non blocking mode
+ * @note This function is called when RTC_WKUP interrupt took place, inside
+ * RTC_WKUP_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
+ * a global variable "uwTick" used as application time base.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1U)
+void TimeBase_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
+#else
+void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ HAL_IncTick();
+}
+
+/**
+ * @brief This function handles WAKE UP TIMER interrupt request.
+ * @retval None
+ */
+void RTC_IRQHandler(void)
+{
+ HAL_RTCEx_WakeUpTimerIRQHandler(&hRTC_Handle);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_timebase_tim_template.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_timebase_tim_template.c
new file mode 100644
index 00000000..9dfa8e77
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_timebase_tim_template.c
@@ -0,0 +1,203 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_timebase_tim_template.c
+ * @author MCD Application Team
+ * @brief HAL time base based on the hardware TIM.
+ *
+ * This file overrides the native HAL time base functions (defined as weak)
+ * the TIM time base:
+ * + Initializes the TIM peripheral to generate a Period elapsed Event each 1ms
+ * + HAL_IncTick is called inside HAL_TIM_PeriodElapsedCallback ie each 1ms
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This file must be copied to the application folder and modified as follows:
+ (#) Rename it to 'stm32u5xx_hal_timebase_tim.c'
+ (#) Add this file and the TIM HAL drivers to your project and uncomment
+ HAL_TIM_MODULE_ENABLED define in stm32u5xx_hal_conf.h
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup HAL_TimeBase
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+static TIM_HandleTypeDef TimHandle;
+
+/* Private function prototypes -----------------------------------------------*/
+void TIM6_IRQHandler(void);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1U)
+void TimeBase_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @brief This function configures the TIM6 as a time base source.
+ * The time source is configured to have 1ms time base with a dedicated
+ * Tick interrupt priority.
+ * @note This function is called automatically at the beginning of program after
+ * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
+ * @param TickPriority Tick interrupt priority.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+ RCC_ClkInitTypeDef clkconfig;
+ uint32_t uwTimclock;
+ uint32_t uwAPB1Prescaler;
+ uint32_t uwPrescalerValue;
+ uint32_t pFLatency;
+ HAL_StatusTypeDef Status;
+
+ /* Enable TIM6 clock */
+ __HAL_RCC_TIM6_CLK_ENABLE();
+
+ /* Get clock configuration */
+ HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
+
+ /* Get APB1 prescaler */
+ uwAPB1Prescaler = clkconfig.APB1CLKDivider;
+
+ /* Compute TIM6 clock */
+ if (uwAPB1Prescaler == RCC_HCLK_DIV1)
+ {
+ uwTimclock = HAL_RCC_GetPCLK1Freq();
+ }
+ else
+ {
+ uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq();
+ }
+
+ /* Compute the prescaler value to have TIM6 counter clock equal to 100KHz */
+ uwPrescalerValue = (uint32_t)((uwTimclock / 100000U) - 1U);
+
+ /* Initialize TIM6 */
+ TimHandle.Instance = TIM6;
+
+ /* Initialize TIMx peripheral as follow:
+ + Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base.
+ + Prescaler = (uwTimclock/100000 - 1) to have a 100KHz counter clock.
+ + ClockDivision = 0
+ + Counter direction = Up
+ */
+ TimHandle.Init.Period = (1000000U / 1000U) - 1U;
+ TimHandle.Init.Prescaler = uwPrescalerValue;
+ TimHandle.Init.ClockDivision = 0;
+ TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
+ Status = HAL_TIM_Base_Init(&TimHandle);
+ if (Status == HAL_OK)
+ {
+ /* Start the TIM time Base generation in interrupt mode */
+ Status = HAL_TIM_Base_Start_IT(&TimHandle);
+ if (Status == HAL_OK)
+ {
+ if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+ {
+ /* Enable the TIM6 global Interrupt */
+ HAL_NVIC_SetPriority(TIM6_IRQn, TickPriority, 0);
+ uwTickPrio = TickPriority;
+ }
+ else
+ {
+ Status = HAL_ERROR;
+ }
+ }
+ }
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1U)
+ HAL_TIM_RegisterCallback(&TimHandle, HAL_TIM_PERIOD_ELAPSED_CB_ID, TimeBase_TIM_PeriodElapsedCallback);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ HAL_NVIC_EnableIRQ(TIM6_IRQn);
+
+ /* Return function Status */
+ return Status;
+}
+
+/**
+ * @brief Suspend Tick increment.
+ * @note Disable the tick increment by disabling TIM6 update interrupt.
+ * @param None
+ * @retval None
+ */
+void HAL_SuspendTick(void)
+{
+ /* Disable TIM6 update Interrupt */
+ __HAL_TIM_DISABLE_IT(&TimHandle, TIM_IT_UPDATE);
+}
+
+/**
+ * @brief Resume Tick increment.
+ * @note Enable the tick increment by Enabling TIM6 update interrupt.
+ * @param None
+ * @retval None
+ */
+void HAL_ResumeTick(void)
+{
+ /* Enable TIM6 Update interrupt */
+ __HAL_TIM_ENABLE_IT(&TimHandle, TIM_IT_UPDATE);
+}
+
+/**
+ * @brief Period elapsed callback in non blocking mode
+ * @note This function is called when TIM6 interrupt took place, inside
+ * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
+ * a global variable "uwTick" used as application time base.
+ * @param htim TIM handle
+ * @retval None
+ */
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1U)
+void TimeBase_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+#else
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ HAL_IncTick();
+}
+
+/**
+ * @brief This function handles TIM interrupt request.
+ * @param None
+ * @retval None
+ */
+void TIM6_IRQHandler(void)
+{
+ HAL_TIM_IRQHandler(&TimHandle);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tsc.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tsc.c
new file mode 100644
index 00000000..5cbb12c8
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tsc.c
@@ -0,0 +1,1125 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_tsc.c
+ * @author MCD Application Team
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Touch Sensing Controller (TSC) peripheral:
+ * + Initialization and De-initialization
+ * + Channel IOs, Shield IOs and Sampling IOs configuration
+ * + Start and Stop an acquisition
+ * + Read acquisition result
+ * + Interrupts and flags management
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+================================================================================
+ ##### TSC specific features #####
+================================================================================
+ [..]
+ (#) Proven and robust surface charge transfer acquisition principle
+
+ (#) Supports up to 3 capacitive sensing channels per group
+
+ (#) Capacitive sensing channels can be acquired in parallel offering a very good
+ response time
+
+ (#) Spread spectrum feature to improve system robustness in noisy environments
+
+ (#) Full hardware management of the charge transfer acquisition sequence
+
+ (#) Programmable charge transfer frequency
+
+ (#) Programmable sampling capacitor I/O pin
+
+ (#) Programmable channel I/O pin
+
+ (#) Programmable max count value to avoid long acquisition when a channel is faulty
+
+ (#) Dedicated end of acquisition and max count error flags with interrupt capability
+
+ (#) One sampling capacitor for up to 3 capacitive sensing channels to reduce the system
+ components
+
+ (#) Compatible with proximity, touchkey, linear and rotary touch sensor implementation
+
+ ##### How to use this driver #####
+================================================================================
+ [..]
+ (#) Enable the TSC interface clock using __HAL_RCC_TSC_CLK_ENABLE() macro.
+
+ (#) GPIO pins configuration
+ (++) Enable the clock for the TSC GPIOs using __HAL_RCC_GPIOx_CLK_ENABLE() macro.
+ (++) Configure the TSC pins used as sampling IOs in alternate function output Open-Drain mode,
+ and TSC pins used as channel/shield IOs in alternate function output Push-Pull mode
+ using HAL_GPIO_Init() function.
+
+ (#) Interrupts configuration
+ (++) Configure the NVIC (if the interrupt model is used) using HAL_NVIC_SetPriority()
+ and HAL_NVIC_EnableIRQ() and function.
+
+ (#) TSC configuration
+ (++) Configure all TSC parameters and used TSC IOs using HAL_TSC_Init() function.
+
+ [..] TSC peripheral alternate functions are mapped on AF9.
+
+ *** Acquisition sequence ***
+ ===================================
+ [..]
+ (+) Discharge all IOs using HAL_TSC_IODischarge() function.
+ (+) Wait a certain time allowing a good discharge of all capacitors. This delay depends
+ of the sampling capacitor and electrodes design.
+ (+) Select the channel IOs to be acquired using HAL_TSC_IOConfig() function.
+ (+) Launch the acquisition using either HAL_TSC_Start() or HAL_TSC_Start_IT() function.
+ If the synchronized mode is selected, the acquisition will start as soon as the signal
+ is received on the synchro pin.
+ (+) Wait the end of acquisition using either HAL_TSC_PollForAcquisition() or
+ HAL_TSC_GetState() function or using WFI instruction for example.
+ (+) Check the group acquisition status using HAL_TSC_GroupGetStatus() function.
+ (+) Read the acquisition value using HAL_TSC_GroupGetValue() function.
+
+ *** Callback registration ***
+ =============================================
+
+ [..]
+ The compilation flag USE_HAL_TSC_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions @ref HAL_TSC_RegisterCallback() to register an interrupt callback.
+
+ [..]
+ Function @ref HAL_TSC_RegisterCallback() allows to register following callbacks:
+ (+) ConvCpltCallback : callback for conversion complete process.
+ (+) ErrorCallback : callback for error detection.
+ (+) MspInitCallback : callback for Msp Init.
+ (+) MspDeInitCallback : callback for Msp DeInit.
+ [..]
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ [..]
+ Use function @ref HAL_TSC_UnRegisterCallback to reset a callback to the default
+ weak function.
+ @ref HAL_TSC_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ [..]
+ This function allows to reset following callbacks:
+ (+) ConvCpltCallback : callback for conversion complete process.
+ (+) ErrorCallback : callback for error detection.
+ (+) MspInitCallback : callback for Msp Init.
+ (+) MspDeInitCallback : callback for Msp DeInit.
+
+ [..]
+ By default, after the @ref HAL_TSC_Init() and when the state is @ref HAL_TSC_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples @ref HAL_TSC_ConvCpltCallback(), @ref HAL_TSC_ErrorCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak functions in the @ref HAL_TSC_Init()/ @ref HAL_TSC_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ If MspInit or MspDeInit are not null, the @ref HAL_TSC_Init()/ @ref HAL_TSC_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+
+ [..]
+ Callbacks can be registered/unregistered in @ref HAL_TSC_STATE_READY state only.
+ Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ in @ref HAL_TSC_STATE_READY or @ref HAL_TSC_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ Then, the user first registers the MspInit/MspDeInit user callbacks
+ using @ref HAL_TSC_RegisterCallback() before calling @ref HAL_TSC_DeInit()
+ or @ref HAL_TSC_Init() function.
+
+ [..]
+ When the compilation flag USE_HAL_TSC_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
+ @endverbatim
+ ******************************************************************************
+
+ Table 1. IOs for the STM32U5xx devices
+ +--------------------------------+
+ | IOs | TSC functions |
+ |--------------|-----------------|
+ | PB12 (AF9) | TSC_G1_IO1 |
+ | PB13 (AF9) | TSC_G1_IO2 |
+ | PB14 (AF9) | TSC_G1_IO3 |
+ | PC3 (AF9) | TSC_G1_IO4 |
+ |--------------|-----------------|
+ | PB4 (AF9) | TSC_G2_IO1 |
+ | PB5 (AF9) | TSC_G2_IO2 |
+ | PB6 (AF9) | TSC_G2_IO3 |
+ | PB7 (AF9) | TSC_G2_IO4 |
+ |--------------|-----------------|
+ | PC2 (AF9) | TSC_G3_IO1 |
+ | PC10 (AF9) | TSC_G3_IO2 |
+ | PC11 (AF9) | TSC_G3_IO3 |
+ | PC12 (AF9) | TSC_G3_IO4 |
+ |--------------|-----------------|
+ | PC6 (AF9) | TSC_G4_IO1 |
+ | PC7 (AF9) | TSC_G4_IO2 |
+ | PC8 (AF9) | TSC_G4_IO3 |
+ | PC9 (AF9) | TSC_G4_IO4 |
+ |--------------|-----------------|
+ | PE10 (AF9) | TSC_G5_IO1 |
+ | PE11 (AF9) | TSC_G5_IO2 |
+ | PE12 (AF9) | TSC_G5_IO3 |
+ | PE13 (AF9) | TSC_G5_IO4 |
+ |--------------|-----------------|
+ | PD10 (AF9) | TSC_G6_IO1 |
+ | PD11 (AF9) | TSC_G6_IO2 |
+ | PD12 (AF9) | TSC_G6_IO3 |
+ | PD13 (AF9) | TSC_G6_IO4 |
+ |--------------|-----------------|
+ | PE2 (AF9) | TSC_G7_IO1 |
+ | PE3 (AF9) | TSC_G7_IO2 |
+ | PE4 (AF9) | TSC_G7_IO3 |
+ | PE5 (AF9) | TSC_G7_IO4 |
+ |--------------|-----------------|
+ | PF14 (AF9) | TSC_G8_IO1 |
+ | PF15 (AF9) | TSC_G8_IO2 |
+ | PG0 (AF9) | TSC_G8_IO3 |
+ | PG1 (AF9) | TSC_G8_IO4 |
+ |--------------|-----------------|
+ | PB10 (AF9) | TSC_SYNC |
+ | PD2 (AF9) | |
+ +--------------------------------+
+
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup TSC TSC
+ * @brief HAL TSC module driver
+ * @{
+ */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static uint32_t TSC_extract_groups(uint32_t iomask);
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup TSC_Exported_Functions TSC Exported Functions
+ * @{
+ */
+
+/** @defgroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the TSC.
+ (+) De-initialize the TSC.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the TSC peripheral according to the specified parameters
+ * in the TSC_InitTypeDef structure and initialize the associated handle.
+ * @param htsc TSC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef *htsc)
+{
+ /* Check TSC handle allocation */
+ if (htsc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+ assert_param(IS_TSC_CTPH(htsc->Init.CTPulseHighLength));
+ assert_param(IS_TSC_CTPL(htsc->Init.CTPulseLowLength));
+ assert_param(IS_TSC_SS(htsc->Init.SpreadSpectrum));
+ assert_param(IS_TSC_SSD(htsc->Init.SpreadSpectrumDeviation));
+ assert_param(IS_TSC_SS_PRESC(htsc->Init.SpreadSpectrumPrescaler));
+ assert_param(IS_TSC_PG_PRESC(htsc->Init.PulseGeneratorPrescaler));
+ assert_param(IS_TSC_PG_PRESC_VS_CTPL(htsc->Init.PulseGeneratorPrescaler, htsc->Init.CTPulseLowLength));
+ assert_param(IS_TSC_MCV(htsc->Init.MaxCountValue));
+ assert_param(IS_TSC_IODEF(htsc->Init.IODefaultMode));
+ assert_param(IS_TSC_SYNC_POL(htsc->Init.SynchroPinPolarity));
+ assert_param(IS_TSC_ACQ_MODE(htsc->Init.AcquisitionMode));
+ assert_param(IS_TSC_MCE_IT(htsc->Init.MaxCountInterrupt));
+ assert_param(IS_TSC_GROUP(htsc->Init.ChannelIOs));
+ assert_param(IS_TSC_GROUP(htsc->Init.ShieldIOs));
+ assert_param(IS_TSC_GROUP(htsc->Init.SamplingIOs));
+
+ if (htsc->State == HAL_TSC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htsc->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
+ /* Init the TSC Callback settings */
+ htsc->ConvCpltCallback = HAL_TSC_ConvCpltCallback; /* Legacy weak ConvCpltCallback */
+ htsc->ErrorCallback = HAL_TSC_ErrorCallback; /* Legacy weak ErrorCallback */
+
+ if (htsc->MspInitCallback == NULL)
+ {
+ htsc->MspInitCallback = HAL_TSC_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ htsc->MspInitCallback(htsc);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX */
+ HAL_TSC_MspInit(htsc);
+#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
+ }
+
+ /* Initialize the TSC state */
+ htsc->State = HAL_TSC_STATE_BUSY;
+
+ /*--------------------------------------------------------------------------*/
+ /* Set TSC parameters */
+
+ /* Enable TSC */
+ htsc->Instance->CR = TSC_CR_TSCE;
+
+ /* Set all functions */
+ htsc->Instance->CR |= (htsc->Init.CTPulseHighLength |
+ htsc->Init.CTPulseLowLength |
+ (htsc->Init.SpreadSpectrumDeviation << TSC_CR_SSD_Pos) |
+ htsc->Init.SpreadSpectrumPrescaler |
+ htsc->Init.PulseGeneratorPrescaler |
+ htsc->Init.MaxCountValue |
+ htsc->Init.SynchroPinPolarity |
+ htsc->Init.AcquisitionMode);
+
+ /* Spread spectrum */
+ if (htsc->Init.SpreadSpectrum == ENABLE)
+ {
+ htsc->Instance->CR |= TSC_CR_SSE;
+ }
+
+ /* Disable Schmitt trigger hysteresis on all used TSC IOs */
+ htsc->Instance->IOHCR = (~(htsc->Init.ChannelIOs | htsc->Init.ShieldIOs | htsc->Init.SamplingIOs));
+
+ /* Set channel and shield IOs */
+ htsc->Instance->IOCCR = (htsc->Init.ChannelIOs | htsc->Init.ShieldIOs);
+
+ /* Set sampling IOs */
+ htsc->Instance->IOSCR = htsc->Init.SamplingIOs;
+
+ /* Set the groups to be acquired */
+ htsc->Instance->IOGCSR = TSC_extract_groups(htsc->Init.ChannelIOs);
+
+ /* Disable interrupts */
+ htsc->Instance->IER &= (~(TSC_IT_EOA | TSC_IT_MCE));
+
+ /* Clear flags */
+ htsc->Instance->ICR = (TSC_FLAG_EOA | TSC_FLAG_MCE);
+
+ /*--------------------------------------------------------------------------*/
+
+ /* Initialize the TSC state */
+ htsc->State = HAL_TSC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Deinitialize the TSC peripheral registers to their default reset values.
+ * @param htsc TSC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc)
+{
+ /* Check TSC handle allocation */
+ if (htsc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_BUSY;
+
+#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
+ if (htsc->MspDeInitCallback == NULL)
+ {
+ htsc->MspDeInitCallback = HAL_TSC_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ htsc->MspDeInitCallback(htsc);
+#else
+ /* DeInit the low level hardware */
+ HAL_TSC_MspDeInit(htsc);
+#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
+
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_RESET;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(htsc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the TSC MSP.
+ * @param htsc Pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval None
+ */
+__weak void HAL_TSC_MspInit(TSC_HandleTypeDef *htsc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htsc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TSC_MspInit could be implemented in the user file.
+ */
+}
+
+/**
+ * @brief DeInitialize the TSC MSP.
+ * @param htsc Pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval None
+ */
+__weak void HAL_TSC_MspDeInit(TSC_HandleTypeDef *htsc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htsc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TSC_MspDeInit could be implemented in the user file.
+ */
+}
+
+#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User TSC Callback
+ * To be used instead of the weak predefined callback
+ * @param htsc Pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_TSC_CONV_COMPLETE_CB_ID Conversion completed callback ID
+ * @arg @ref HAL_TSC_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_TSC_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_TSC_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID,
+ pTSC_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(htsc);
+
+ if (HAL_TSC_STATE_READY == htsc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_TSC_CONV_COMPLETE_CB_ID :
+ htsc->ConvCpltCallback = pCallback;
+ break;
+
+ case HAL_TSC_ERROR_CB_ID :
+ htsc->ErrorCallback = pCallback;
+ break;
+
+ case HAL_TSC_MSPINIT_CB_ID :
+ htsc->MspInitCallback = pCallback;
+ break;
+
+ case HAL_TSC_MSPDEINIT_CB_ID :
+ htsc->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_TSC_STATE_RESET == htsc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_TSC_MSPINIT_CB_ID :
+ htsc->MspInitCallback = pCallback;
+ break;
+
+ case HAL_TSC_MSPDEINIT_CB_ID :
+ htsc->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(htsc);
+ return status;
+}
+
+/**
+ * @brief Unregister an TSC Callback
+ * TSC callback is redirected to the weak predefined callback
+ * @param htsc Pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_TSC_CONV_COMPLETE_CB_ID Conversion completed callback ID
+ * @arg @ref HAL_TSC_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_TSC_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_TSC_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TSC_UnRegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(htsc);
+
+ if (HAL_TSC_STATE_READY == htsc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_TSC_CONV_COMPLETE_CB_ID :
+ htsc->ConvCpltCallback = HAL_TSC_ConvCpltCallback; /* Legacy weak ConvCpltCallback */
+ break;
+
+ case HAL_TSC_ERROR_CB_ID :
+ htsc->ErrorCallback = HAL_TSC_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_TSC_MSPINIT_CB_ID :
+ htsc->MspInitCallback = HAL_TSC_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_TSC_MSPDEINIT_CB_ID :
+ htsc->MspDeInitCallback = HAL_TSC_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_TSC_STATE_RESET == htsc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_TSC_MSPINIT_CB_ID :
+ htsc->MspInitCallback = HAL_TSC_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_TSC_MSPDEINIT_CB_ID :
+ htsc->MspDeInitCallback = HAL_TSC_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(htsc);
+ return status;
+}
+
+#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup TSC_Exported_Functions_Group2 Input and Output operation functions
+ * @brief Input and Output operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO Operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start acquisition in polling mode.
+ (+) Start acquisition in interrupt mode.
+ (+) Stop conversion in polling mode.
+ (+) Stop conversion in interrupt mode.
+ (+) Poll for acquisition completed.
+ (+) Get group acquisition status.
+ (+) Get group acquisition value.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start the acquisition.
+ * @param htsc Pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef *htsc)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(htsc);
+
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_BUSY;
+
+ /* Clear interrupts */
+ __HAL_TSC_DISABLE_IT(htsc, (TSC_IT_EOA | TSC_IT_MCE));
+
+ /* Clear flags */
+ __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
+
+ /* Set touch sensing IOs not acquired to the specified IODefaultMode */
+ if (htsc->Init.IODefaultMode == TSC_IODEF_OUT_PP_LOW)
+ {
+ __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
+ }
+ else
+ {
+ __HAL_TSC_SET_IODEF_INFLOAT(htsc);
+ }
+
+ /* Launch the acquisition */
+ __HAL_TSC_START_ACQ(htsc);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(htsc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Start the acquisition in interrupt mode.
+ * @param htsc Pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef *htsc)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+ assert_param(IS_TSC_MCE_IT(htsc->Init.MaxCountInterrupt));
+
+ /* Process locked */
+ __HAL_LOCK(htsc);
+
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_BUSY;
+
+ /* Enable end of acquisition interrupt */
+ __HAL_TSC_ENABLE_IT(htsc, TSC_IT_EOA);
+
+ /* Enable max count error interrupt (optional) */
+ if (htsc->Init.MaxCountInterrupt == ENABLE)
+ {
+ __HAL_TSC_ENABLE_IT(htsc, TSC_IT_MCE);
+ }
+ else
+ {
+ __HAL_TSC_DISABLE_IT(htsc, TSC_IT_MCE);
+ }
+
+ /* Clear flags */
+ __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
+
+ /* Set touch sensing IOs not acquired to the specified IODefaultMode */
+ if (htsc->Init.IODefaultMode == TSC_IODEF_OUT_PP_LOW)
+ {
+ __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
+ }
+ else
+ {
+ __HAL_TSC_SET_IODEF_INFLOAT(htsc);
+ }
+
+ /* Launch the acquisition */
+ __HAL_TSC_START_ACQ(htsc);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(htsc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the acquisition previously launched in polling mode.
+ * @param htsc Pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef *htsc)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(htsc);
+
+ /* Stop the acquisition */
+ __HAL_TSC_STOP_ACQ(htsc);
+
+ /* Set touch sensing IOs in low power mode (output push-pull) */
+ __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
+
+ /* Clear flags */
+ __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
+
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(htsc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the acquisition previously launched in interrupt mode.
+ * @param htsc Pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef *htsc)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(htsc);
+
+ /* Stop the acquisition */
+ __HAL_TSC_STOP_ACQ(htsc);
+
+ /* Set touch sensing IOs in low power mode (output push-pull) */
+ __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
+
+ /* Disable interrupts */
+ __HAL_TSC_DISABLE_IT(htsc, (TSC_IT_EOA | TSC_IT_MCE));
+
+ /* Clear flags */
+ __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
+
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(htsc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Start acquisition and wait until completion.
+ * @note There is no need of a timeout parameter as the max count error is already
+ * managed by the TSC peripheral.
+ * @param htsc Pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval HAL state
+ */
+HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef *htsc)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(htsc);
+
+ /* Check end of acquisition */
+ while (HAL_TSC_GetState(htsc) == HAL_TSC_STATE_BUSY)
+ {
+ /* The timeout (max count error) is managed by the TSC peripheral itself. */
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(htsc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get the acquisition status for a group.
+ * @param htsc Pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @param gx_index Index of the group
+ * @retval Group status
+ */
+TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef *htsc, uint32_t gx_index)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+ assert_param(IS_TSC_GROUP_INDEX(gx_index));
+
+ /* Return the group status */
+ return (__HAL_TSC_GET_GROUP_STATUS(htsc, gx_index));
+}
+
+/**
+ * @brief Get the acquisition measure for a group.
+ * @param htsc Pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @param gx_index Index of the group
+ * @retval Acquisition measure
+ */
+uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef *htsc, uint32_t gx_index)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+ assert_param(IS_TSC_GROUP_INDEX(gx_index));
+
+ /* Return the group acquisition counter */
+ return htsc->Instance->IOGXCR[gx_index];
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TSC_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure TSC IOs
+ (+) Discharge TSC IOs
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure TSC IOs.
+ * @param htsc Pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @param config Pointer to the configuration structure.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, TSC_IOConfigTypeDef *config)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+ assert_param(IS_TSC_GROUP(config->ChannelIOs));
+ assert_param(IS_TSC_GROUP(config->ShieldIOs));
+ assert_param(IS_TSC_GROUP(config->SamplingIOs));
+
+ /* Process locked */
+ __HAL_LOCK(htsc);
+
+ /* Stop acquisition */
+ __HAL_TSC_STOP_ACQ(htsc);
+
+ /* Disable Schmitt trigger hysteresis on all used TSC IOs */
+ htsc->Instance->IOHCR = (~(config->ChannelIOs | config->ShieldIOs | config->SamplingIOs));
+
+ /* Set channel and shield IOs */
+ htsc->Instance->IOCCR = (config->ChannelIOs | config->ShieldIOs);
+
+ /* Set sampling IOs */
+ htsc->Instance->IOSCR = config->SamplingIOs;
+
+ /* Set groups to be acquired */
+ htsc->Instance->IOGCSR = TSC_extract_groups(config->ChannelIOs);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(htsc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Discharge TSC IOs.
+ * @param htsc Pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @param choice This parameter can be set to ENABLE or DISABLE.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef *htsc, FunctionalState choice)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(htsc);
+
+ if (choice == ENABLE)
+ {
+ __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
+ }
+ else
+ {
+ __HAL_TSC_SET_IODEF_INFLOAT(htsc);
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(htsc);
+
+ /* Return the group acquisition counter */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions
+ * @brief Peripheral State and Errors functions
+ *
+@verbatim
+ ===============================================================================
+ ##### State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Get TSC state.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the TSC handle state.
+ * @param htsc Pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval HAL state
+ */
+HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef *htsc)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+ if (htsc->State == HAL_TSC_STATE_BUSY)
+ {
+ /* Check end of acquisition flag */
+ if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_EOA) != RESET)
+ {
+ /* Check max count error flag */
+ if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_MCE) != RESET)
+ {
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_ERROR;
+ }
+ else
+ {
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_READY;
+ }
+ }
+ }
+
+ /* Return TSC state */
+ return htsc->State;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+
+/**
+ * @brief Handle TSC interrupt request.
+ * @param htsc Pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval None
+ */
+void HAL_TSC_IRQHandler(TSC_HandleTypeDef *htsc)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+ /* Check if the end of acquisition occurred */
+ if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_EOA) != RESET)
+ {
+ /* Clear EOA flag */
+ __HAL_TSC_CLEAR_FLAG(htsc, TSC_FLAG_EOA);
+ }
+
+ /* Check if max count error occurred */
+ if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_MCE) != RESET)
+ {
+ /* Clear MCE flag */
+ __HAL_TSC_CLEAR_FLAG(htsc, TSC_FLAG_MCE);
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_ERROR;
+#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
+ htsc->ErrorCallback(htsc);
+#else
+ /* Conversion completed callback */
+ HAL_TSC_ErrorCallback(htsc);
+#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_READY;
+#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
+ htsc->ConvCpltCallback(htsc);
+#else
+ /* Conversion completed callback */
+ HAL_TSC_ConvCpltCallback(htsc);
+#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief Acquisition completed callback in non-blocking mode.
+ * @param htsc Pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval None
+ */
+__weak void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef *htsc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htsc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TSC_ConvCpltCallback could be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Error callback in non-blocking mode.
+ * @param htsc Pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval None
+ */
+__weak void HAL_TSC_ErrorCallback(TSC_HandleTypeDef *htsc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htsc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TSC_ErrorCallback could be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup TSC_Private_Functions TSC Private Functions
+ * @{
+ */
+
+/**
+ * @brief Utility function used to set the acquired groups mask.
+ * @param iomask Channels IOs mask
+ * @retval Acquired groups mask
+ */
+static uint32_t TSC_extract_groups(uint32_t iomask)
+{
+ uint32_t groups = 0UL;
+ uint32_t idx;
+
+ for (idx = 0UL; idx < (uint32_t)TSC_NB_OF_GROUPS; idx++)
+ {
+ if ((iomask & (0x0FUL << (idx * 4UL))) != 0UL)
+ {
+ groups |= (1UL << idx);
+ }
+ }
+
+ return groups;
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart.c
new file mode 100644
index 00000000..14998aaa
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart.c
@@ -0,0 +1,4577 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_uart.c
+ * @author MCD Application Team
+ * @brief UART HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ *
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ The UART HAL driver can be used as follows:
+
+ (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
+ (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
+ (++) Enable the USARTx interface clock.
+ (++) UART pins configuration:
+ (+++) Enable the clock for the UART GPIOs.
+ (+++) Configure these UART pins as alternate function pull-up.
+ (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
+ and HAL_UART_Receive_IT() APIs):
+ (+++) Configure the USARTx interrupt priority.
+ (+++) Enable the NVIC USART IRQ handle.
+ (++) UART interrupts handling:
+ -@@- The specific UART interrupts (Transmission complete interrupt,
+ RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts)
+ are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT()
+ inside the transmit and receive processes.
+ (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
+ and HAL_UART_Receive_DMA() APIs):
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx channel.
+ (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete
+ interrupt on the DMA Tx/Rx channel.
+
+ (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value , Hardware
+ flow control and Mode (Receiver/Transmitter) in the huart handle Init structure.
+
+ (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...)
+ in the huart handle AdvancedInit structure.
+
+ (#) For the UART asynchronous mode, initialize the UART registers by calling
+ the HAL_UART_Init() API.
+
+ (#) For the UART Half duplex mode, initialize the UART registers by calling
+ the HAL_HalfDuplex_Init() API.
+
+ (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers
+ by calling the HAL_LIN_Init() API.
+
+ (#) For the UART Multiprocessor mode, initialize the UART registers
+ by calling the HAL_MultiProcessor_Init() API.
+
+ (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
+ by calling the HAL_RS485Ex_Init() API.
+
+ [..]
+ (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(),
+ also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by
+ calling the customized HAL_UART_MspInit() API.
+
+ ##### Callback registration #####
+ ==================================
+
+ [..]
+ The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ [..]
+ Use Function @ref HAL_UART_RegisterCallback() to register a user callback.
+ Function @ref HAL_UART_RegisterCallback() allows to register following callbacks:
+ (+) TxHalfCpltCallback : Tx Half Complete Callback.
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxHalfCpltCallback : Rx Half Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+ (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
+ (+) WakeupCallback : Wakeup Callback.
+ (+) RxFifoFullCallback : Rx Fifo Full Callback.
+ (+) TxFifoEmptyCallback : Tx Fifo Empty Callback.
+ (+) MspInitCallback : UART MspInit.
+ (+) MspDeInitCallback : UART MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ [..]
+ Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function.
+ @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TxHalfCpltCallback : Tx Half Complete Callback.
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxHalfCpltCallback : Rx Half Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+ (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
+ (+) WakeupCallback : Wakeup Callback.
+ (+) RxFifoFullCallback : Rx Fifo Full Callback.
+ (+) TxFifoEmptyCallback : Tx Fifo Empty Callback.
+ (+) MspInitCallback : UART MspInit.
+ (+) MspDeInitCallback : UART MspDeInit.
+
+ [..]
+ For specific callback RxEventCallback, use dedicated registration/reset functions:
+ respectively @ref HAL_UART_RegisterRxEventCallback() , @ref HAL_UART_UnRegisterRxEventCallback().
+
+ [..]
+ By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
+ all callbacks are set to the corresponding weak (surcharged) functions:
+ examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init()
+ and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+ [..]
+ Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user)
+ MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit()
+ or @ref HAL_UART_Init() function.
+
+ [..]
+ When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available
+ and weak (surcharged) callbacks are used.
+
+
+ @endverbatim
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup UART UART
+ * @brief HAL UART module driver
+ * @{
+ */
+
+#ifdef HAL_UART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup UART_Private_Constants UART Private Constants
+ * @{
+ */
+#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | \
+ USART_CR1_OVER8 | USART_CR1_FIFOEN)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
+
+#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT | USART_CR3_TXFTCFG | \
+ USART_CR3_RXFTCFG)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */
+
+#define LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */
+#define LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */
+
+#define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */
+#define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup UART_Private_Functions
+ * @{
+ */
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAError(DMA_HandleTypeDef *hdma);
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_TxISR_8BIT(UART_HandleTypeDef *huart);
+static void UART_TxISR_16BIT(UART_HandleTypeDef *huart);
+static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart);
+static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart);
+static void UART_EndTransmit_IT(UART_HandleTypeDef *huart);
+static void UART_RxISR_8BIT(UART_HandleTypeDef *huart);
+static void UART_RxISR_16BIT(UART_HandleTypeDef *huart);
+static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart);
+static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart);
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @addtogroup UART_Private_variables
+ * @{
+ */
+const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
+/**
+ * @}
+ */
+
+/* Exported Constants --------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup UART_Exported_Functions UART Exported Functions
+ * @{
+ */
+
+/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
+ in asynchronous mode.
+ (+) For the asynchronous mode the parameters below can be configured:
+ (++) Baud Rate
+ (++) Word Length
+ (++) Stop Bit
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ (++) Hardware flow control
+ (++) Receiver/transmitter modes
+ (++) Over Sampling Method
+ (++) One-Bit Sampling Method
+ (+) For the asynchronous mode, the following advanced features can be configured as well:
+ (++) TX and/or RX pin level inversion
+ (++) data logical level inversion
+ (++) RX and TX pins swap
+ (++) RX overrun detection disabling
+ (++) DMA disabling on RX error
+ (++) MSB first on communication line
+ (++) auto Baud rate detection
+ [..]
+ The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API
+ follow respectively the UART asynchronous, UART Half duplex, UART LIN mode
+ and UART multiprocessor mode configuration procedures (details for the procedures
+ are available in reference manual).
+
+@endverbatim
+
+ Depending on the frame length defined by the M1 and M0 bits (7-bit,
+ 8-bit or 9-bit), the possible UART formats are listed in the
+ following table.
+
+ Table 1. UART frame format.
+ +-----------------------------------------------------------------------+
+ | M1 bit | M0 bit | PCE bit | UART frame |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 0 | | SB | 8 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 0 | | SB | 9 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 0 | | SB | 7 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
+ +-----------------------------------------------------------------------+
+
+ * @{
+ */
+
+/**
+ * @brief Initialize the UART mode according to the specified
+ * parameters in the UART_InitTypeDef and initialize the associated handle.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
+{
+ /* Check the UART handle allocation */
+ if (huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
+ {
+ /* Check the parameters */
+ assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
+ }
+ else
+ {
+ /* Check the parameters */
+ assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
+ }
+
+ if (huart->gState == HAL_UART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ UART_InitCallbacksToDefault(huart);
+
+ if (huart->MspInitCallback == NULL)
+ {
+ huart->MspInitCallback = HAL_UART_MspInit;
+ }
+
+ /* Init the low level hardware */
+ huart->MspInitCallback(huart);
+#else
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ {
+ UART_AdvFeatureConfig(huart);
+ }
+
+ /* In asynchronous mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
+ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+/**
+ * @brief Initialize the half-duplex mode according to the specified
+ * parameters in the UART_InitTypeDef and creates the associated handle.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
+{
+ /* Check the UART handle allocation */
+ if (huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check UART instance */
+ assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
+
+ if (huart->gState == HAL_UART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ UART_InitCallbacksToDefault(huart);
+
+ if (huart->MspInitCallback == NULL)
+ {
+ huart->MspInitCallback = HAL_UART_MspInit;
+ }
+
+ /* Init the low level hardware */
+ huart->MspInitCallback(huart);
+#else
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ {
+ UART_AdvFeatureConfig(huart);
+ }
+
+ /* In half-duplex mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN and IREN bits in the USART_CR3 register.*/
+ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
+
+ /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
+ SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
+
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+
+/**
+ * @brief Initialize the LIN mode according to the specified
+ * parameters in the UART_InitTypeDef and creates the associated handle.
+ * @param huart UART handle.
+ * @param BreakDetectLength Specifies the LIN break detection length.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection
+ * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
+{
+ /* Check the UART handle allocation */
+ if (huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the LIN UART instance */
+ assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
+ /* Check the Break detection length parameter */
+ assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
+
+ /* LIN mode limited to 16-bit oversampling only */
+ if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
+ {
+ return HAL_ERROR;
+ }
+ /* LIN mode limited to 8-bit data length */
+ if (huart->Init.WordLength != UART_WORDLENGTH_8B)
+ {
+ return HAL_ERROR;
+ }
+
+ if (huart->gState == HAL_UART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ UART_InitCallbacksToDefault(huart);
+
+ if (huart->MspInitCallback == NULL)
+ {
+ huart->MspInitCallback = HAL_UART_MspInit;
+ }
+
+ /* Init the low level hardware */
+ huart->MspInitCallback(huart);
+#else
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ {
+ UART_AdvFeatureConfig(huart);
+ }
+
+ /* In LIN mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN and IREN bits in the USART_CR3 register.*/
+ CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));
+
+ /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
+ SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
+
+ /* Set the USART LIN Break detection length. */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
+
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+
+/**
+ * @brief Initialize the multiprocessor mode according to the specified
+ * parameters in the UART_InitTypeDef and initialize the associated handle.
+ * @param huart UART handle.
+ * @param Address UART node address (4-, 6-, 7- or 8-bit long).
+ * @param WakeUpMethod Specifies the UART wakeup method.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection
+ * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark
+ * @note If the user resorts to idle line detection wake up, the Address parameter
+ * is useless and ignored by the initialization function.
+ * @note If the user resorts to address mark wake up, the address length detection
+ * is configured by default to 4 bits only. For the UART to be able to
+ * manage 6-, 7- or 8-bit long addresses detection, the API
+ * HAL_MultiProcessorEx_AddressLength_Set() must be called after
+ * HAL_MultiProcessor_Init().
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
+{
+ /* Check the UART handle allocation */
+ if (huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the wake up method parameter */
+ assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
+
+ if (huart->gState == HAL_UART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ UART_InitCallbacksToDefault(huart);
+
+ if (huart->MspInitCallback == NULL)
+ {
+ huart->MspInitCallback = HAL_UART_MspInit;
+ }
+
+ /* Init the low level hardware */
+ huart->MspInitCallback(huart);
+#else
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ {
+ UART_AdvFeatureConfig(huart);
+ }
+
+ /* In multiprocessor mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN, HDSEL and IREN bits in the USART_CR3 register. */
+ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+
+ if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)
+ {
+ /* If address mark wake up method is chosen, set the USART address node */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS));
+ }
+
+ /* Set the wake up method by setting the WAKE bit in the CR1 register */
+ MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
+
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+
+/**
+ * @brief DeInitialize the UART peripheral.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
+{
+ /* Check the UART handle allocation */
+ if (huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ __HAL_UART_DISABLE(huart);
+
+ huart->Instance->CR1 = 0x0U;
+ huart->Instance->CR2 = 0x0U;
+ huart->Instance->CR3 = 0x0U;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ if (huart->MspDeInitCallback == NULL)
+ {
+ huart->MspDeInitCallback = HAL_UART_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ huart->MspDeInitCallback(huart);
+#else
+ /* DeInit the low level hardware */
+ HAL_UART_MspDeInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->gState = HAL_UART_STATE_RESET;
+ huart->RxState = HAL_UART_STATE_RESET;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the UART MSP.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the UART MSP.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_MspDeInit can be implemented in the user file
+ */
+}
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User UART Callback
+ * To be used instead of the weak predefined callback
+ * @param huart uart handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+ * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+ * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+ * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+ * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
+ * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
+ * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
+ * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
+ pUART_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ __HAL_LOCK(huart);
+
+ if (huart->gState == HAL_UART_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_UART_TX_HALFCOMPLETE_CB_ID :
+ huart->TxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_TX_COMPLETE_CB_ID :
+ huart->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_RX_HALFCOMPLETE_CB_ID :
+ huart->RxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_RX_COMPLETE_CB_ID :
+ huart->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_ERROR_CB_ID :
+ huart->ErrorCallback = pCallback;
+ break;
+
+ case HAL_UART_ABORT_COMPLETE_CB_ID :
+ huart->AbortCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
+ huart->AbortTransmitCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
+ huart->AbortReceiveCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_RX_FIFO_FULL_CB_ID :
+ huart->RxFifoFullCallback = pCallback;
+ break;
+
+ case HAL_UART_TX_FIFO_EMPTY_CB_ID :
+ huart->TxFifoEmptyCallback = pCallback;
+ break;
+
+ case HAL_UART_MSPINIT_CB_ID :
+ huart->MspInitCallback = pCallback;
+ break;
+
+ case HAL_UART_MSPDEINIT_CB_ID :
+ huart->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (huart->gState == HAL_UART_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_UART_MSPINIT_CB_ID :
+ huart->MspInitCallback = pCallback;
+ break;
+
+ case HAL_UART_MSPDEINIT_CB_ID :
+ huart->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ }
+
+ __HAL_UNLOCK(huart);
+
+ return status;
+}
+
+/**
+ * @brief Unregister an UART Callback
+ * UART callaback is redirected to the weak predefined callback
+ * @param huart uart handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+ * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+ * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+ * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+ * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
+ * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
+ * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
+ * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ __HAL_LOCK(huart);
+
+ if (HAL_UART_STATE_READY == huart->gState)
+ {
+ switch (CallbackID)
+ {
+ case HAL_UART_TX_HALFCOMPLETE_CB_ID :
+ huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ break;
+
+ case HAL_UART_TX_COMPLETE_CB_ID :
+ huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ break;
+
+ case HAL_UART_RX_HALFCOMPLETE_CB_ID :
+ huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ break;
+
+ case HAL_UART_RX_COMPLETE_CB_ID :
+ huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ break;
+
+ case HAL_UART_ERROR_CB_ID :
+ huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_UART_ABORT_COMPLETE_CB_ID :
+ huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ break;
+
+ case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
+ huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak
+ AbortTransmitCpltCallback */
+ break;
+
+ case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
+ huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak
+ AbortReceiveCpltCallback */
+ break;
+
+ case HAL_UART_RX_FIFO_FULL_CB_ID :
+ huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
+ break;
+
+ case HAL_UART_TX_FIFO_EMPTY_CB_ID :
+ huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
+ break;
+
+ case HAL_UART_MSPINIT_CB_ID :
+ huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */
+ break;
+
+ case HAL_UART_MSPDEINIT_CB_ID :
+ huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */
+ break;
+
+ default :
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_UART_STATE_RESET == huart->gState)
+ {
+ switch (CallbackID)
+ {
+ case HAL_UART_MSPINIT_CB_ID :
+ huart->MspInitCallback = HAL_UART_MspInit;
+ break;
+
+ case HAL_UART_MSPDEINIT_CB_ID :
+ huart->MspDeInitCallback = HAL_UART_MspDeInit;
+ break;
+
+ default :
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ }
+
+ __HAL_UNLOCK(huart);
+
+ return status;
+}
+
+/**
+ * @brief Register a User UART Rx Event Callback
+ * To be used instead of the weak predefined callback
+ * @param huart Uart handle
+ * @param pCallback Pointer to the Rx Event Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(huart);
+
+ if (huart->gState == HAL_UART_STATE_READY)
+ {
+ huart->RxEventCallback = pCallback;
+ }
+ else
+ {
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(huart);
+
+ return status;
+}
+
+/**
+ * @brief UnRegister the UART Rx Event Callback
+ * UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback
+ * @param huart Uart handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(huart);
+
+ if (huart->gState == HAL_UART_STATE_READY)
+ {
+ huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */
+ }
+ else
+ {
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(huart);
+ return status;
+}
+
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Exported_Functions_Group2 IO operation functions
+ * @brief UART Transmit/Receive functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ This subsection provides a set of functions allowing to manage the UART asynchronous
+ and Half duplex data transfers.
+
+ (#) There are two mode of transfer:
+ (+) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (+) Non-Blocking mode: The communication is performed using Interrupts
+ or DMA, These API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
+ will be executed respectively at the end of the transmit or Receive process
+ The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected
+
+ (#) Blocking mode API's are :
+ (+) HAL_UART_Transmit()
+ (+) HAL_UART_Receive()
+
+ (#) Non-Blocking mode API's with Interrupt are :
+ (+) HAL_UART_Transmit_IT()
+ (+) HAL_UART_Receive_IT()
+ (+) HAL_UART_IRQHandler()
+
+ (#) Non-Blocking mode API's with DMA are :
+ (+) HAL_UART_Transmit_DMA()
+ (+) HAL_UART_Receive_DMA()
+ (+) HAL_UART_DMAPause()
+ (+) HAL_UART_DMAResume()
+ (+) HAL_UART_DMAStop()
+
+ (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
+ (+) HAL_UART_TxHalfCpltCallback()
+ (+) HAL_UART_TxCpltCallback()
+ (+) HAL_UART_RxHalfCpltCallback()
+ (+) HAL_UART_RxCpltCallback()
+ (+) HAL_UART_ErrorCallback()
+
+ (#) Non-Blocking mode transfers could be aborted using Abort API's :
+ (+) HAL_UART_Abort()
+ (+) HAL_UART_AbortTransmit()
+ (+) HAL_UART_AbortReceive()
+ (+) HAL_UART_Abort_IT()
+ (+) HAL_UART_AbortTransmit_IT()
+ (+) HAL_UART_AbortReceive_IT()
+
+ (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
+ (+) HAL_UART_AbortCpltCallback()
+ (+) HAL_UART_AbortTransmitCpltCallback()
+ (+) HAL_UART_AbortReceiveCpltCallback()
+
+ (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced
+ reception services:
+ (+) HAL_UARTEx_RxEventCallback()
+
+ (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+ Errors are handled as follows :
+ (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error
+ in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user
+ to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
+ Transfer is kept ongoing on UART side.
+ If user wants to abort it, Abort services should be called by user.
+ (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback()
+ user callback is executed.
+
+ -@- In the Half duplex communication, it is forbidden to run the transmit
+ and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Send an amount of data in blocking mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pData.
+ * @note When FIFO mode is enabled, writing a data in the TDR register adds one
+ * data to the TXFIFO. Write operations to the TDR register are performed
+ * when TXFNF flag is set. From hardware perspective, TXFNF flag and
+ * TXE are mapped on the same bit-field.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint8_t *pdata8bits;
+ uint16_t *pdata16bits;
+ uint32_t tickstart;
+
+ /* Check that a Tx process is not already ongoing */
+ if (huart->gState == HAL_UART_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ __HAL_LOCK(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->gState = HAL_UART_STATE_BUSY_TX;
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ huart->TxXferSize = Size;
+ huart->TxXferCount = Size;
+
+ /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ pdata8bits = NULL;
+ pdata16bits = (uint16_t *) pData;
+ }
+ else
+ {
+ pdata8bits = pData;
+ pdata16bits = NULL;
+ }
+
+ __HAL_UNLOCK(huart);
+
+ while (huart->TxXferCount > 0U)
+ {
+ if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if (pdata8bits == NULL)
+ {
+ huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
+ pdata16bits++;
+ }
+ else
+ {
+ huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
+ pdata8bits++;
+ }
+ huart->TxXferCount--;
+ }
+
+ if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* At end of Tx process, restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pData.
+ * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
+ * is not empty. Read operations from the RDR register are performed when
+ * RXFNE flag is set. From hardware perspective, RXFNE flag and
+ * RXNE are mapped on the same bit-field.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint8_t *pdata8bits;
+ uint16_t *pdata16bits;
+ uint16_t uhMask;
+ uint32_t tickstart;
+
+ /* Check that a Rx process is not already ongoing */
+ if (huart->RxState == HAL_UART_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ __HAL_LOCK(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->RxState = HAL_UART_STATE_BUSY_RX;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ huart->RxXferSize = Size;
+ huart->RxXferCount = Size;
+
+ /* Computation of UART mask to apply to RDR register */
+ UART_MASK_COMPUTATION(huart);
+ uhMask = huart->Mask;
+
+ /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ pdata8bits = NULL;
+ pdata16bits = (uint16_t *) pData;
+ }
+ else
+ {
+ pdata8bits = pData;
+ pdata16bits = NULL;
+ }
+
+ __HAL_UNLOCK(huart);
+
+ /* as long as data have to be received */
+ while (huart->RxXferCount > 0U)
+ {
+ if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if (pdata8bits == NULL)
+ {
+ *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
+ pdata16bits++;
+ }
+ else
+ {
+ *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
+ pdata8bits++;
+ }
+ huart->RxXferCount--;
+ }
+
+ /* At end of Rx process, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in interrupt mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pData.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Tx process is not already ongoing */
+ if (huart->gState == HAL_UART_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ __HAL_LOCK(huart);
+
+ huart->pTxBuffPtr = pData;
+ huart->TxXferSize = Size;
+ huart->TxXferCount = Size;
+ huart->TxISR = NULL;
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->gState = HAL_UART_STATE_BUSY_TX;
+
+ /* Configure Tx interrupt processing */
+ if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+ {
+ /* Set the Tx ISR function pointer according to the data word length */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ huart->TxISR = UART_TxISR_16BIT_FIFOEN;
+ }
+ else
+ {
+ huart->TxISR = UART_TxISR_8BIT_FIFOEN;
+ }
+
+ __HAL_UNLOCK(huart);
+
+ /* Enable the TX FIFO threshold interrupt */
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+ }
+ else
+ {
+ /* Set the Tx ISR function pointer according to the data word length */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ huart->TxISR = UART_TxISR_16BIT;
+ }
+ else
+ {
+ huart->TxISR = UART_TxISR_8BIT;
+ }
+
+ __HAL_UNLOCK(huart);
+
+ /* Enable the Transmit Data Register Empty interrupt */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in interrupt mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pData.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Rx process is not already ongoing */
+ if (huart->RxState == HAL_UART_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ __HAL_LOCK(huart);
+
+ /* Set Reception type to Standard reception */
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ if (!(IS_LPUART_INSTANCE(huart->Instance)))
+ {
+ /* Check that USART RTOEN bit is set */
+ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+ {
+ /* Enable the UART Receiver Timeout Interrupt */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+ }
+ }
+
+ return (UART_Start_Receive_IT(huart, pData, Size));
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in DMA mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pData.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef status;
+ uint16_t nbByte = Size;
+
+ /* Check that a Tx process is not already ongoing */
+ if (huart->gState == HAL_UART_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ __HAL_LOCK(huart);
+
+ huart->pTxBuffPtr = pData;
+ huart->TxXferSize = Size;
+ huart->TxXferCount = Size;
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->gState = HAL_UART_STATE_BUSY_TX;
+
+ if (huart->hdmatx != NULL)
+ {
+ /* Set the UART DMA transfer complete callback */
+ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
+
+ /* Set the UART DMA Half transfer complete callback */
+ huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
+
+ /* Set the DMA error callback */
+ huart->hdmatx->XferErrorCallback = UART_DMAError;
+
+ /* Set the DMA abort callback */
+ huart->hdmatx->XferAbortCallback = NULL;
+
+ /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
+ should be aligned on a u16 frontier, so nbByte should be equal to Size * 2 */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ nbByte = Size * 2U;
+ }
+
+ /* Check linked list mode */
+ if ((huart->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if ((huart->hdmatx->LinkedListQueue != NULL) && (huart->hdmatx->LinkedListQueue->Head != NULL))
+ {
+ /* Set DMA data size */
+ huart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte;
+
+ /* Set DMA source address */
+ huart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)huart->pTxBuffPtr;
+
+ /* Set DMA destination address */
+ huart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
+ (uint32_t)&huart->Instance->TDR;
+
+ /* Enable the UART transmit DMA channel */
+ status = HAL_DMAEx_List_Start_IT(huart->hdmatx);
+ }
+ else
+ {
+ /* Update status */
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Enable the UART transmit DMA channel */
+ status = HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, nbByte);
+ }
+
+ if (status != HAL_OK)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ __HAL_UNLOCK(huart);
+
+ /* Restore huart->gState to ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ return HAL_ERROR;
+ }
+ }
+ /* Clear the TC flag in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
+
+ __HAL_UNLOCK(huart);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the UART CR3 register */
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in DMA mode.
+ * @note When the UART parity is enabled (PCE = 1), the received data contain
+ * the parity bit (MSB position).
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pData.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Rx process is not already ongoing */
+ if (huart->RxState == HAL_UART_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ __HAL_LOCK(huart);
+
+ /* Set Reception type to Standard reception */
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ if (!(IS_LPUART_INSTANCE(huart->Instance)))
+ {
+ /* Check that USART RTOEN bit is set */
+ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+ {
+ /* Enable the UART Receiver Timeout Interrupt */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+ }
+ }
+
+ return (UART_Start_Receive_DMA(huart, pData, Size));
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Pause the DMA Transfer.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
+{
+ const HAL_UART_StateTypeDef gstate = huart->gState;
+ const HAL_UART_StateTypeDef rxstate = huart->RxState;
+
+ __HAL_LOCK(huart);
+
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
+ (gstate == HAL_UART_STATE_BUSY_TX))
+ {
+ /* Disable the UART DMA Tx request */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+ }
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
+ (rxstate == HAL_UART_STATE_BUSY_RX))
+ {
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the UART DMA Rx request */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ }
+
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resume the DMA Transfer.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
+{
+ __HAL_LOCK(huart);
+
+ if (huart->gState == HAL_UART_STATE_BUSY_TX)
+ {
+ /* Enable the UART DMA Tx request */
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+ }
+ if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+ {
+ /* Clear the Overrun flag before resuming the Rx transfer */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+
+ /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the UART DMA Rx request */
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ }
+
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the DMA Transfer.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
+{
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() /
+ HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback:
+ indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
+ interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
+ the stream and the corresponding call back is executed. */
+
+ const HAL_UART_StateTypeDef gstate = huart->gState;
+ const HAL_UART_StateTypeDef rxstate = huart->RxState;
+
+ /* Stop UART DMA Tx request if ongoing */
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
+ (gstate == HAL_UART_STATE_BUSY_TX))
+ {
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the UART DMA Tx channel */
+ if (huart->hdmatx != NULL)
+ {
+ if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ UART_EndTxTransfer(huart);
+ }
+
+ /* Stop UART DMA Rx request if ongoing */
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
+ (rxstate == HAL_UART_STATE_BUSY_RX))
+ {
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel */
+ if (huart->hdmarx != NULL)
+ {
+ if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ UART_EndRxTransfer(huart);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (blocking mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable UART Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
+{
+ /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
+ USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);
+
+ /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+ }
+
+ /* Disable the UART DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if (huart->hdmatx != NULL)
+ {
+ /* Set the UART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ huart->hdmatx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Disable the UART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if (huart->hdmarx != NULL)
+ {
+ /* Set the UART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ huart->hdmarx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Reset Tx and Rx transfer counters */
+ huart->TxXferCount = 0U;
+ huart->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Flush the whole TX FIFO (if needed) */
+ if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+ {
+ __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+ }
+
+ /* Discard the received data */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+ /* Restore huart->gState and huart->RxState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (blocking mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable UART Interrupts (Tx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
+{
+ /* Disable TCIE, TXEIE and TXFTIE interrupts */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+
+ /* Disable the UART DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if (huart->hdmatx != NULL)
+ {
+ /* Set the UART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ huart->hdmatx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Reset Tx transfer counter */
+ huart->TxXferCount = 0U;
+
+ /* Flush the whole TX FIFO (if needed) */
+ if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+ {
+ __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+ }
+
+ /* Restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (blocking mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable UART Interrupts (Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
+{
+ /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
+
+ /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+ }
+
+ /* Disable the UART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if (huart->hdmarx != NULL)
+ {
+ /* Set the UART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ huart->hdmarx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Reset Rx transfer counter */
+ huart->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Discard the received data */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+ /* Restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (Interrupt mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable UART Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
+{
+ uint32_t abortcplt = 1U;
+
+ /* Disable interrupts */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE |
+ USART_CR1_TXEIE_TXFNFIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
+
+ /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+ }
+
+ /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
+ before any call to DMA Abort functions */
+ /* DMA Tx Handle is valid */
+ if (huart->hdmatx != NULL)
+ {
+ /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
+ Otherwise, set it to NULL */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;
+ }
+ else
+ {
+ huart->hdmatx->XferAbortCallback = NULL;
+ }
+ }
+ /* DMA Rx Handle is valid */
+ if (huart->hdmarx != NULL)
+ {
+ /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
+ Otherwise, set it to NULL */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;
+ }
+ else
+ {
+ huart->hdmarx->XferAbortCallback = NULL;
+ }
+ }
+
+ /* Disable the UART DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable DMA Tx at UART level */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if (huart->hdmatx != NULL)
+ {
+ /* UART Tx DMA Abort callback has already been initialised :
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+ {
+ huart->hdmatx->XferAbortCallback = NULL;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* Disable the UART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if (huart->hdmarx != NULL)
+ {
+ /* UART Rx DMA Abort callback has already been initialised :
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+ {
+ huart->hdmarx->XferAbortCallback = NULL;
+ abortcplt = 1U;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+ if (abortcplt == 1U)
+ {
+ /* Reset Tx and Rx transfer counters */
+ huart->TxXferCount = 0U;
+ huart->RxXferCount = 0U;
+
+ /* Clear ISR function pointers */
+ huart->RxISR = NULL;
+ huart->TxISR = NULL;
+
+ /* Reset errorCode */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Flush the whole TX FIFO (if needed) */
+ if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+ {
+ __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+ }
+
+ /* Discard the received data */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+ /* Restore huart->gState and huart->RxState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ huart->AbortCpltCallback(huart);
+#else
+ /* Call legacy weak Abort complete callback */
+ HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (Interrupt mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable UART Interrupts (Tx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
+{
+ /* Disable interrupts */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+
+ /* Disable the UART DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if (huart->hdmatx != NULL)
+ {
+ /* Set the UART DMA Abort callback :
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+ huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+ {
+ /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */
+ huart->hdmatx->XferAbortCallback(huart->hdmatx);
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ huart->TxXferCount = 0U;
+
+ /* Clear TxISR function pointers */
+ huart->TxISR = NULL;
+
+ /* Restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ huart->AbortTransmitCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
+ HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ huart->TxXferCount = 0U;
+
+ /* Clear TxISR function pointers */
+ huart->TxISR = NULL;
+
+ /* Flush the whole TX FIFO (if needed) */
+ if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+ {
+ __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+ }
+
+ /* Restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ huart->AbortTransmitCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
+ HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (Interrupt mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable UART Interrupts (Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+ /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+ }
+
+ /* Disable the UART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if (huart->hdmarx != NULL)
+ {
+ /* Set the UART DMA Abort callback :
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+ huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+ {
+ /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
+ huart->hdmarx->XferAbortCallback(huart->hdmarx);
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ huart->RxXferCount = 0U;
+
+ /* Clear RxISR function pointer */
+ huart->pRxBuffPtr = NULL;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Discard the received data */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+ /* Restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ huart->AbortReceiveCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
+ HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ huart->RxXferCount = 0U;
+
+ /* Clear RxISR function pointer */
+ huart->pRxBuffPtr = NULL;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ huart->AbortReceiveCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
+ HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle UART interrupt request.
+ * @param huart UART handle.
+ * @retval None
+ */
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
+{
+ uint32_t isrflags = READ_REG(huart->Instance->ISR);
+ uint32_t cr1its = READ_REG(huart->Instance->CR1);
+ uint32_t cr3its = READ_REG(huart->Instance->CR3);
+
+ uint32_t errorflags;
+ uint32_t errorcode;
+
+ /* If no error occurs */
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
+ if (errorflags == 0U)
+ {
+ /* UART in mode Receiver ---------------------------------------------------*/
+ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
+ && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+ || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+ {
+ if (huart->RxISR != NULL)
+ {
+ huart->RxISR(huart);
+ }
+ return;
+ }
+ }
+
+ /* If some errors occur */
+ if ((errorflags != 0U)
+ && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
+ || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))))
+ {
+ /* UART parity error interrupt occurred -------------------------------------*/
+ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_PE;
+ }
+
+ /* UART frame error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_FE;
+ }
+
+ /* UART noise error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_NE;
+ }
+
+ /* UART Over-Run interrupt occurred -----------------------------------------*/
+ if (((isrflags & USART_ISR_ORE) != 0U)
+ && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
+ ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_ORE;
+ }
+
+ /* UART Receiver Timeout interrupt occurred ---------------------------------*/
+ if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_RTO;
+ }
+
+ /* Call UART Error Call back function if need be ----------------------------*/
+ if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+ {
+ /* UART in mode Receiver --------------------------------------------------*/
+ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
+ && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+ || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+ {
+ if (huart->RxISR != NULL)
+ {
+ huart->RxISR(huart);
+ }
+ }
+
+ /* If Error is to be considered as blocking :
+ - Receiver Timeout error in Reception
+ - Overrun error in Reception
+ - any error occurs in DMA mode reception
+ */
+ errorcode = huart->ErrorCode;
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
+ ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
+ {
+ /* Blocking error : transfer is aborted
+ Set the UART state ready to be able to start again the process,
+ Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+ UART_EndRxTransfer(huart);
+
+ /* Disable the UART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel */
+ if (huart->hdmarx != NULL)
+ {
+ /* Set the UART DMA Abort callback :
+ will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
+ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+ {
+ /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
+ huart->hdmarx->XferAbortCallback(huart->hdmarx);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ }
+ else
+ {
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ }
+ }
+ return;
+
+ } /* End if some error occurs */
+
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : */
+ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ && ((isrflags & USART_ISR_IDLE) != 0U)
+ && ((cr1its & USART_ISR_IDLE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+
+ /* Check if DMA mode is enabled in UART */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ /* DMA mode enabled */
+ /* Check received length : If all expected data are received, do nothing,
+ (DMA cplt callback will be called).
+ Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
+ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
+ if ((nb_remaining_rx_data > 0U)
+ && (nb_remaining_rx_data < huart->RxXferSize))
+ {
+ /* Reception is not complete */
+ huart->RxXferCount = nb_remaining_rx_data;
+
+ /* In Normal mode, end DMA xfer and HAL UART Rx process*/
+ if (huart->hdmarx->Mode != DMA_LINKEDLIST_CIRCULAR)
+ {
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+ in the UART CR3 register */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* At end of Rx process, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+ /* Last bytes received, so no need as the abort is immediate */
+ (void)HAL_DMA_Abort(huart->hdmarx);
+ }
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
+#else
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+ return;
+ }
+ else
+ {
+ /* DMA mode not enabled */
+ /* Check received length : If all expected data are received, do nothing.
+ Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
+ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
+ if ((huart->RxXferCount > 0U)
+ && (nb_rx_data > 0U))
+ {
+ /* Disable the UART Parity Error Interrupt and RXNE interrupts */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+
+ /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+ /* Rx process is completed, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* Clear RxISR function pointer */
+ huart->RxISR = NULL;
+
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxEventCallback(huart, nb_rx_data);
+#else
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+ return;
+ }
+ }
+
+ /* UART in mode Transmitter ------------------------------------------------*/
+ if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
+ && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
+ || ((cr3its & USART_CR3_TXFTIE) != 0U)))
+ {
+ if (huart->TxISR != NULL)
+ {
+ huart->TxISR(huart);
+ }
+ return;
+ }
+
+ /* UART in mode Transmitter (transmission end) -----------------------------*/
+ if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
+ {
+ UART_EndTransmit_IT(huart);
+ return;
+ }
+
+ /* UART TX Fifo Empty occurred ----------------------------------------------*/
+ if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
+ {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Fifo Empty Callback */
+ huart->TxFifoEmptyCallback(huart);
+#else
+ /* Call legacy weak Tx Fifo Empty Callback */
+ HAL_UARTEx_TxFifoEmptyCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ return;
+ }
+
+ /* UART RX Fifo Full occurred ----------------------------------------------*/
+ if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
+ {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx Fifo Full Callback */
+ huart->RxFifoFullCallback(huart);
+#else
+ /* Call legacy weak Rx Fifo Full Callback */
+ HAL_UARTEx_RxFifoFullCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ return;
+ }
+}
+
+/**
+ * @brief Tx Transfer completed callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_TxCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Tx Half Transfer completed callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_UART_TxHalfCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_RxCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Rx Half Transfer completed callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_UART_RxHalfCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief UART error callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_ErrorCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief UART Abort Complete callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_AbortCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief UART Abort Complete callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief UART Abort Receive Complete callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Reception Event Callback (Rx event notification called after use of advanced reception service).
+ * @param huart UART handle
+ * @param Size Number of data available in application reception buffer (indicates a position in
+ * reception buffer until which, data are available)
+ * @retval None
+ */
+__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+ UNUSED(Size);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UARTEx_RxEventCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
+ * @brief UART control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the UART.
+ (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly
+ (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature
+ (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature
+ (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
+ (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
+ (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
+ (+) UART_SetConfig() API configures the UART peripheral
+ (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features
+ (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization
+ (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
+ (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
+ (+) HAL_LIN_SendBreak() API transmits the break characters
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Update on the fly the receiver timeout value in RTOR register.
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @param TimeoutValue receiver timeout value in number of baud blocks. The timeout
+ * value must be less or equal to 0x0FFFFFFFF.
+ * @retval None
+ */
+void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue)
+{
+ if (!(IS_LPUART_INSTANCE(huart->Instance)))
+ {
+ assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue));
+ MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue);
+ }
+}
+
+/**
+ * @brief Enable the UART receiver timeout feature.
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart)
+{
+ if (!(IS_LPUART_INSTANCE(huart->Instance)))
+ {
+ if (huart->gState == HAL_UART_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Set the USART RTOEN bit */
+ SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Disable the UART receiver timeout feature.
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart)
+{
+ if (!(IS_LPUART_INSTANCE(huart->Instance)))
+ {
+ if (huart->gState == HAL_UART_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Clear the USART RTOEN bit */
+ CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Enable UART in mute mode (does not mean UART enters mute mode;
+ * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
+{
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Enable USART mute mode by setting the MME bit in the CR1 register */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_MME);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ return (UART_CheckIdleState(huart));
+}
+
+/**
+ * @brief Disable UART mute mode (does not mean the UART actually exits mute mode
+ * as it may not have been in mute mode at this very moment).
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
+{
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Disable USART mute mode by clearing the MME bit in the CR1 register */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ return (UART_CheckIdleState(huart));
+}
+
+/**
+ * @brief Enter UART mute mode (means UART actually enters mute mode).
+ * @note To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
+ * @param huart UART handle.
+ * @retval None
+ */
+void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
+{
+ __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);
+}
+
+/**
+ * @brief Enable the UART transmitter and disable the UART receiver.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
+{
+ __HAL_LOCK(huart);
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Clear TE and RE bits */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+
+ /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TE);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable the UART receiver and disable the UART transmitter.
+ * @param huart UART handle.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
+{
+ __HAL_LOCK(huart);
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Clear TE and RE bits */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+
+ /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RE);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Transmit break characters.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
+{
+ /* Check the parameters */
+ assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
+
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Send break characters */
+ __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions
+ * @brief UART Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Error functions #####
+ ==============================================================================
+ [..]
+ This subsection provides functions allowing to :
+ (+) Return the UART handle state.
+ (+) Return the UART handle error code
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the UART handle state.
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART.
+ * @retval HAL state
+ */
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
+{
+ uint32_t temp1;
+ uint32_t temp2;
+ temp1 = huart->gState;
+ temp2 = huart->RxState;
+
+ return (HAL_UART_StateTypeDef)(temp1 | temp2);
+}
+
+/**
+ * @brief Return the UART handle error code.
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART.
+ * @retval UART Error Code
+ */
+uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
+{
+ return huart->ErrorCode;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Private_Functions UART Private Functions
+ * @{
+ */
+
+/**
+ * @brief Initialize the callbacks to their default values.
+ * @param huart UART handle.
+ * @retval none
+ */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart)
+{
+ /* Init the UART Callback settings */
+ huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */
+ huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+ huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
+ huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
+ huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
+ huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak RxEventCallback */
+
+}
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+ * @brief Configure the UART peripheral.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
+{
+ uint32_t tmpreg;
+ uint16_t brrtemp;
+ uint32_t clocksource;
+ uint32_t usartdiv;
+ HAL_StatusTypeDef ret = HAL_OK;
+ uint32_t lpuart_ker_ck_pres;
+ uint32_t pclk;
+
+ /* Check the parameters */
+ assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
+ assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+ if (UART_INSTANCE_LOWPOWER(huart))
+ {
+ assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits));
+ }
+ else
+ {
+ assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
+ assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
+ }
+
+ assert_param(IS_UART_PARITY(huart->Init.Parity));
+ assert_param(IS_UART_MODE(huart->Init.Mode));
+ assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
+ assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
+ assert_param(IS_UART_PRESCALER(huart->Init.ClockPrescaler));
+
+ /*-------------------------- USART CR1 Configuration -----------------------*/
+ /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
+ * the UART Word Length, Parity, Mode and oversampling:
+ * set the M bits according to huart->Init.WordLength value
+ * set PCE and PS bits according to huart->Init.Parity value
+ * set TE and RE bits according to huart->Init.Mode value
+ * set OVER8 bit according to huart->Init.OverSampling value */
+ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
+ MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+
+ /*-------------------------- USART CR2 Configuration -----------------------*/
+ /* Configure the UART Stop Bits: Set STOP[13:12] bits according
+ * to huart->Init.StopBits value */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
+
+ /*-------------------------- USART CR3 Configuration -----------------------*/
+ /* Configure
+ * - UART HardWare Flow Control: set CTSE and RTSE bits according
+ * to huart->Init.HwFlowCtl value
+ * - one-bit sampling method versus three samples' majority rule according
+ * to huart->Init.OneBitSampling (not applicable to LPUART) */
+ tmpreg = (uint32_t)huart->Init.HwFlowCtl;
+
+ if (!(UART_INSTANCE_LOWPOWER(huart)))
+ {
+ tmpreg |= huart->Init.OneBitSampling;
+ }
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
+
+ /*-------------------------- USART PRESC Configuration -----------------------*/
+ /* Configure
+ * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
+ MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
+
+ /*-------------------------- USART BRR Configuration -----------------------*/
+ UART_GETCLOCKSOURCE(huart, clocksource);
+
+ /* Check LPUART instance */
+ if (UART_INSTANCE_LOWPOWER(huart))
+ {
+ /* Retrieve frequency clock */
+ pclk = HAL_RCCEx_GetPeriphCLKFreq(clocksource);
+
+ /* If proper clock source reported */
+ if (pclk != 0U)
+ {
+ /* Compute clock after Prescaler */
+ lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]);
+
+ /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
+ if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
+ (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate)))
+ {
+ ret = HAL_ERROR;
+ }
+ else
+ {
+ /* Check computed UsartDiv value is in allocated range
+ (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */
+ usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
+ {
+ huart->Instance->BRR = usartdiv;
+ }
+ else
+ {
+ ret = HAL_ERROR;
+ }
+ } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
+ (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
+ } /* if (pclk != 0) */
+ }
+ /* Check UART Over Sampling to set Baud Rate Register */
+ else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
+ {
+ pclk = HAL_RCCEx_GetPeriphCLKFreq(clocksource);
+
+ /* USARTDIV must be greater than or equal to 0d16 */
+ if (pclk != 0U)
+ {
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+ {
+ brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
+ brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+ huart->Instance->BRR = brrtemp;
+ }
+ else
+ {
+ ret = HAL_ERROR;
+ }
+ }
+ }
+ else
+ {
+ pclk = HAL_RCCEx_GetPeriphCLKFreq(clocksource);
+
+ if (pclk != 0U)
+ {
+ /* USARTDIV must be greater than or equal to 0d16 */
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+ {
+ huart->Instance->BRR = usartdiv;
+ }
+ else
+ {
+ ret = HAL_ERROR;
+ }
+ }
+ }
+
+ /* Initialize the number of data to process during RX/TX ISR execution */
+ huart->NbTxDataToProcess = 1;
+ huart->NbRxDataToProcess = 1;
+
+ /* Clear ISR function pointers */
+ huart->RxISR = NULL;
+ huart->TxISR = NULL;
+
+ return ret;
+}
+
+/**
+ * @brief Configure the UART peripheral advanced features.
+ * @param huart UART handle.
+ * @retval None
+ */
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
+{
+ /* Check whether the set of advanced features to configure is properly set */
+ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
+
+ /* if required, configure TX pin active level inversion */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
+ }
+
+ /* if required, configure RX pin active level inversion */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
+ }
+
+ /* if required, configure data inversion */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
+ }
+
+ /* if required, configure RX/TX pins swap */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
+ }
+
+ /* if required, configure RX overrun detection disabling */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
+ {
+ assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
+ }
+
+ /* if required, configure DMA disabling on reception error */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
+ }
+
+ /* if required, configure auto Baud rate detection scheme */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
+ {
+ assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
+ assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
+ /* set auto Baudrate detection parameters if detection is enabled */
+ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
+ {
+ assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
+ }
+ }
+
+ /* if required, configure MSB first on communication line */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
+ }
+}
+
+/**
+ * @brief Check the UART Idle State.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
+{
+ uint32_t tickstart;
+
+ /* Initialize the UART ErrorCode */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ /* Check if the Transmitter is enabled */
+ if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ {
+ /* Wait until TEACK flag is set */
+ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check if the Receiver is enabled */
+ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+ {
+ /* Wait until REACK flag is set */
+ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Initialize the UART State */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle UART Communication Timeout.
+ * @param huart UART handle.
+ * @param Flag Specifies the UART flag to check
+ * @param Status Flag status (SET or RESET)
+ * @param Tickstart Tick start value
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
+ uint32_t Tickstart, uint32_t Timeout)
+{
+ /* Wait until flag is set */
+ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
+ interrupts for the interrupt process */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
+ USART_CR1_TXEIE_TXFNFIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+
+ __HAL_UNLOCK(huart);
+
+ return HAL_TIMEOUT;
+ }
+
+ if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
+ {
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
+ {
+ /* Clear Receiver Timeout flag*/
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
+
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
+ interrupts for the interrupt process */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
+ USART_CR1_TXEIE_TXFNFIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ErrorCode = HAL_UART_ERROR_RTO;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Start Receive operation in interrupt mode.
+ * @note This function could be called by all HAL UART API providing reception in Interrupt mode.
+ * @note When calling this function, parameters validity is considered as already checked,
+ * i.e. Rx State, buffer address, ...
+ * UART Handle is assumed as Locked.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ huart->pRxBuffPtr = pData;
+ huart->RxXferSize = Size;
+ huart->RxXferCount = Size;
+ huart->RxISR = NULL;
+
+ /* Computation of UART mask to apply to RDR register */
+ UART_MASK_COMPUTATION(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Configure Rx interrupt processing */
+ if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))
+ {
+ /* Set the Rx ISR function pointer according to the data word length */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ huart->RxISR = UART_RxISR_16BIT_FIFOEN;
+ }
+ else
+ {
+ huart->RxISR = UART_RxISR_8BIT_FIFOEN;
+ }
+
+ __HAL_UNLOCK(huart);
+
+ /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+ }
+ else
+ {
+ /* Set the Rx ISR function pointer according to the data word length */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ huart->RxISR = UART_RxISR_16BIT;
+ }
+ else
+ {
+ huart->RxISR = UART_RxISR_8BIT;
+ }
+
+ __HAL_UNLOCK(huart);
+
+ /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Start Receive operation in DMA mode.
+ * @note This function could be called by all HAL UART API providing reception in DMA mode.
+ * @note When calling this function, parameters validity is considered as already checked,
+ * i.e. Rx State, buffer address, ...
+ * UART Handle is assumed as Locked.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef status;
+ uint16_t nbByte = Size;
+
+ huart->pRxBuffPtr = pData;
+ huart->RxXferSize = Size;
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+ if (huart->hdmarx != NULL)
+ {
+ /* Set the UART DMA transfer complete callback */
+ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
+
+ /* Set the UART DMA Half transfer complete callback */
+ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
+
+ /* Set the DMA error callback */
+ huart->hdmarx->XferErrorCallback = UART_DMAError;
+
+ /* Set the DMA abort callback */
+ huart->hdmarx->XferAbortCallback = NULL;
+
+ /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
+ should be aligned on a u16 frontier, so nbByte should be equal to Size * 2 */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ nbByte = Size * 2U;
+ }
+
+ /* Check linked list mode */
+ if ((huart->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if ((huart->hdmarx->LinkedListQueue != NULL) && (huart->hdmarx->LinkedListQueue->Head != NULL))
+ {
+ /* Set DMA data size */
+ huart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte;
+
+ /* Set DMA source address */
+ huart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
+ (uint32_t)&huart->Instance->RDR;
+
+ /* Set DMA destination address */
+ huart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)huart->pRxBuffPtr;
+
+ /* Enable the UART receive DMA channel */
+ status = HAL_DMAEx_List_Start_IT(huart->hdmarx);
+ }
+ else
+ {
+ /* Update status */
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Enable the UART receive DMA channel */
+ status = HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, nbByte);
+ }
+
+ if (status != HAL_OK)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ __HAL_UNLOCK(huart);
+
+ /* Restore huart->RxState to ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ return HAL_ERROR;
+ }
+ }
+ __HAL_UNLOCK(huart);
+
+ /* Enable the UART Parity Error Interrupt */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the UART CR3 register */
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
+{
+ /* Disable TXEIE, TCIE, TXFT interrupts */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE));
+
+ /* At end of Tx process, restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+}
+
+
+/**
+ * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+ /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ }
+
+ /* At end of Rx process, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* Reset RxIsr function pointer */
+ huart->RxISR = NULL;
+}
+
+
+/**
+ * @brief DMA UART transmit process complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+ /* Check if DMA in circular mode */
+ if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR)
+ {
+ huart->TxXferCount = 0U;
+
+ /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+ in the UART CR3 register */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Enable the UART Transmit Complete Interrupt */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ }
+ /* DMA Circular mode */
+ else
+ {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Tx complete callback*/
+ huart->TxCpltCallback(huart);
+#else
+ /*Call legacy weak Tx complete callback*/
+ HAL_UART_TxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief DMA UART transmit process half complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Tx Half complete callback*/
+ huart->TxHalfCpltCallback(huart);
+#else
+ /*Call legacy weak Tx Half complete callback*/
+ HAL_UART_TxHalfCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA UART receive process complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+ /* Check if DMA in circular mode */
+ if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR)
+ {
+ huart->RxXferCount = 0U;
+
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+ in the UART CR3 register */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* At end of Rx process, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ }
+ }
+
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : use Rx Event callback */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* In other cases : use Rx Complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief DMA UART receive process half complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : use Rx Event callback */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, huart->RxXferSize / 2U);
+#else
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* In other cases : use Rx Half Complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Half complete callback*/
+ huart->RxHalfCpltCallback(huart);
+#else
+ /*Call legacy weak Rx Half complete callback*/
+ HAL_UART_RxHalfCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief DMA UART communication error callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMAError(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+ const HAL_UART_StateTypeDef gstate = huart->gState;
+ const HAL_UART_StateTypeDef rxstate = huart->RxState;
+
+ /* Stop UART DMA Tx request if ongoing */
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
+ (gstate == HAL_UART_STATE_BUSY_TX))
+ {
+ huart->TxXferCount = 0U;
+ UART_EndTxTransfer(huart);
+ }
+
+ /* Stop UART DMA Rx request if ongoing */
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
+ (rxstate == HAL_UART_STATE_BUSY_RX))
+ {
+ huart->RxXferCount = 0U;
+ UART_EndRxTransfer(huart);
+ }
+
+ huart->ErrorCode |= HAL_UART_ERROR_DMA;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA UART communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ huart->RxXferCount = 0U;
+ huart->TxXferCount = 0U;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA UART Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+ huart->hdmatx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if (huart->hdmarx != NULL)
+ {
+ if (huart->hdmarx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ huart->TxXferCount = 0U;
+ huart->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Flush the whole TX FIFO (if needed) */
+ if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+ {
+ __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+ }
+
+ /* Restore huart->gState and huart->RxState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ huart->AbortCpltCallback(huart);
+#else
+ /* Call legacy weak Abort complete callback */
+ HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+
+/**
+ * @brief DMA UART Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+ huart->hdmarx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if (huart->hdmatx != NULL)
+ {
+ if (huart->hdmatx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ huart->TxXferCount = 0U;
+ huart->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Discard the received data */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+ /* Restore huart->gState and huart->RxState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ huart->AbortCpltCallback(huart);
+#else
+ /* Call legacy weak Abort complete callback */
+ HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+
+/**
+ * @brief DMA UART Tx communication abort callback, when initiated by user by a call to
+ * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)
+ * (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+ * and leads to user Tx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+ huart->TxXferCount = 0U;
+
+ /* Flush the whole TX FIFO (if needed) */
+ if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+ {
+ __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+ }
+
+ /* Restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ huart->AbortTransmitCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
+ HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA UART Rx communication abort callback, when initiated by user by a call to
+ * HAL_UART_AbortReceive_IT API (Abort only Rx transfer)
+ * (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+ * and leads to user Rx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ huart->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Discard the received data */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+ /* Restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ huart->AbortReceiveCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
+ HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief TX interrupt handler for 7 or 8 bits data word length .
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Transmit_IT().
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_TxISR_8BIT(UART_HandleTypeDef *huart)
+{
+ /* Check that a Tx process is ongoing */
+ if (huart->gState == HAL_UART_STATE_BUSY_TX)
+ {
+ if (huart->TxXferCount == 0U)
+ {
+ /* Disable the UART Transmit Data Register Empty Interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+
+ /* Enable the UART Transmit Complete Interrupt */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ }
+ else
+ {
+ huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
+ huart->pTxBuffPtr++;
+ huart->TxXferCount--;
+ }
+ }
+}
+
+/**
+ * @brief TX interrupt handler for 9 bits data word length.
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Transmit_IT().
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_TxISR_16BIT(UART_HandleTypeDef *huart)
+{
+ uint16_t *tmp;
+
+ /* Check that a Tx process is ongoing */
+ if (huart->gState == HAL_UART_STATE_BUSY_TX)
+ {
+ if (huart->TxXferCount == 0U)
+ {
+ /* Disable the UART Transmit Data Register Empty Interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+
+ /* Enable the UART Transmit Complete Interrupt */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ }
+ else
+ {
+ tmp = (uint16_t *) huart->pTxBuffPtr;
+ huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
+ huart->pTxBuffPtr += 2U;
+ huart->TxXferCount--;
+ }
+ }
+}
+
+/**
+ * @brief TX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Transmit_IT().
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
+{
+ uint16_t nb_tx_data;
+
+ /* Check that a Tx process is ongoing */
+ if (huart->gState == HAL_UART_STATE_BUSY_TX)
+ {
+ for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
+ {
+ if (huart->TxXferCount == 0U)
+ {
+ /* Disable the TX FIFO threshold interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+
+ /* Enable the UART Transmit Complete Interrupt */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
+ break; /* force exit loop */
+ }
+ else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
+ {
+ huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
+ huart->pTxBuffPtr++;
+ huart->TxXferCount--;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ }
+}
+
+/**
+ * @brief TX interrupt handler for 9 bits data word length and FIFO mode is enabled.
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Transmit_IT().
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
+{
+ uint16_t *tmp;
+ uint16_t nb_tx_data;
+
+ /* Check that a Tx process is ongoing */
+ if (huart->gState == HAL_UART_STATE_BUSY_TX)
+ {
+ for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
+ {
+ if (huart->TxXferCount == 0U)
+ {
+ /* Disable the TX FIFO threshold interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+
+ /* Enable the UART Transmit Complete Interrupt */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
+ break; /* force exit loop */
+ }
+ else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
+ {
+ tmp = (uint16_t *) huart->pTxBuffPtr;
+ huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
+ huart->pTxBuffPtr += 2U;
+ huart->TxXferCount--;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ }
+}
+
+/**
+ * @brief Wrap up transmission in non-blocking mode.
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval None
+ */
+static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
+{
+ /* Disable the UART Transmit Complete Interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
+ /* Tx process is ended, restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Cleat TxISR function pointer */
+ huart->TxISR = NULL;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Tx complete callback*/
+ huart->TxCpltCallback(huart);
+#else
+ /*Call legacy weak Tx complete callback*/
+ HAL_UART_TxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief RX interrupt handler for 7 or 8 bits data word length .
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
+{
+ uint16_t uhMask = huart->Mask;
+ uint16_t uhdata;
+
+ /* Check that a Rx process is ongoing */
+ if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+ {
+ uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+ *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
+ huart->pRxBuffPtr++;
+ huart->RxXferCount--;
+
+ if (huart->RxXferCount == 0U)
+ {
+ /* Disable the UART Parity Error Interrupt and RXNE interrupts */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Rx process is completed, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Clear RxISR function pointer */
+ huart->RxISR = NULL;
+
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ /* Set reception type to Standard */
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* Disable IDLE interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+ {
+ /* Clear IDLE Flag */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ }
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+ else
+ {
+ /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ }
+ }
+ else
+ {
+ /* Clear RXNE interrupt flag */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+ }
+}
+
+/**
+ * @brief RX interrupt handler for 9 bits data word length .
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Receive_IT()
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
+{
+ uint16_t *tmp;
+ uint16_t uhMask = huart->Mask;
+ uint16_t uhdata;
+
+ /* Check that a Rx process is ongoing */
+ if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+ {
+ uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+ tmp = (uint16_t *) huart->pRxBuffPtr ;
+ *tmp = (uint16_t)(uhdata & uhMask);
+ huart->pRxBuffPtr += 2U;
+ huart->RxXferCount--;
+
+ if (huart->RxXferCount == 0U)
+ {
+ /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Rx process is completed, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Clear RxISR function pointer */
+ huart->RxISR = NULL;
+
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ /* Set reception type to Standard */
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* Disable IDLE interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+ {
+ /* Clear IDLE Flag */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ }
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+ else
+ {
+ /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ }
+ }
+ else
+ {
+ /* Clear RXNE interrupt flag */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+ }
+}
+
+/**
+ * @brief RX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Receive_IT()
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
+{
+ uint16_t uhMask = huart->Mask;
+ uint16_t uhdata;
+ uint16_t nb_rx_data;
+ uint16_t rxdatacount;
+ uint32_t isrflags = READ_REG(huart->Instance->ISR);
+ uint32_t cr1its = READ_REG(huart->Instance->CR1);
+ uint32_t cr3its = READ_REG(huart->Instance->CR3);
+
+ /* Check that a Rx process is ongoing */
+ if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+ {
+ nb_rx_data = huart->NbRxDataToProcess;
+ while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
+ {
+ uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+ *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
+ huart->pRxBuffPtr++;
+ huart->RxXferCount--;
+ isrflags = READ_REG(huart->Instance->ISR);
+
+ /* If some non blocking errors occurred */
+ if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
+ {
+ /* UART parity error interrupt occurred -------------------------------------*/
+ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_PE;
+ }
+
+ /* UART frame error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_FE;
+ }
+
+ /* UART noise error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_NE;
+ }
+
+ /* Call UART Error Call back function if need be ----------------------------*/
+ if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+ {
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ }
+ }
+
+ if (huart->RxXferCount == 0U)
+ {
+ /* Disable the UART Parity Error Interrupt and RXFT interrupt*/
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
+ and RX FIFO Threshold interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+ /* Rx process is completed, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Clear RxISR function pointer */
+ huart->RxISR = NULL;
+
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ /* Set reception type to Standard */
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* Disable IDLE interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+ {
+ /* Clear IDLE Flag */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ }
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+ else
+ {
+ /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ }
+ }
+
+ /* When remaining number of bytes to receive is less than the RX FIFO
+ threshold, next incoming frames are processed as if FIFO mode was
+ disabled (i.e. one interrupt per received frame).
+ */
+ rxdatacount = huart->RxXferCount;
+ if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
+ {
+ /* Disable the UART RXFT interrupt*/
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+
+ /* Update the RxISR function pointer */
+ huart->RxISR = UART_RxISR_8BIT;
+
+ /* Enable the UART Data Register Not Empty interrupt */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+ }
+ }
+ else
+ {
+ /* Clear RXNE interrupt flag */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+ }
+}
+
+/**
+ * @brief RX interrupt handler for 9 bits data word length and FIFO mode is enabled.
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Receive_IT()
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
+{
+ uint16_t *tmp;
+ uint16_t uhMask = huart->Mask;
+ uint16_t uhdata;
+ uint16_t nb_rx_data;
+ uint16_t rxdatacount;
+ uint32_t isrflags = READ_REG(huart->Instance->ISR);
+ uint32_t cr1its = READ_REG(huart->Instance->CR1);
+ uint32_t cr3its = READ_REG(huart->Instance->CR3);
+
+ /* Check that a Rx process is ongoing */
+ if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+ {
+ nb_rx_data = huart->NbRxDataToProcess;
+ while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
+ {
+ uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+ tmp = (uint16_t *) huart->pRxBuffPtr ;
+ *tmp = (uint16_t)(uhdata & uhMask);
+ huart->pRxBuffPtr += 2U;
+ huart->RxXferCount--;
+ isrflags = READ_REG(huart->Instance->ISR);
+
+ /* If some non blocking errors occurred */
+ if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
+ {
+ /* UART parity error interrupt occurred -------------------------------------*/
+ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_PE;
+ }
+
+ /* UART frame error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_FE;
+ }
+
+ /* UART noise error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_NE;
+ }
+
+ /* Call UART Error Call back function if need be ----------------------------*/
+ if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+ {
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ }
+ }
+
+ if (huart->RxXferCount == 0U)
+ {
+ /* Disable the UART Parity Error Interrupt and RXFT interrupt*/
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
+ and RX FIFO Threshold interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+ /* Rx process is completed, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Clear RxISR function pointer */
+ huart->RxISR = NULL;
+
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ /* Set reception type to Standard */
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* Disable IDLE interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+ {
+ /* Clear IDLE Flag */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ }
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+ else
+ {
+ /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ }
+ }
+
+ /* When remaining number of bytes to receive is less than the RX FIFO
+ threshold, next incoming frames are processed as if FIFO mode was
+ disabled (i.e. one interrupt per received frame).
+ */
+ rxdatacount = huart->RxXferCount;
+ if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
+ {
+ /* Disable the UART RXFT interrupt*/
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+
+ /* Update the RxISR function pointer */
+ huart->RxISR = UART_RxISR_16BIT;
+
+ /* Enable the UART Data Register Not Empty interrupt */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+ }
+ }
+ else
+ {
+ /* Clear RXNE interrupt flag */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_UART_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart_ex.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart_ex.c
new file mode 100644
index 00000000..984b0031
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart_ex.c
@@ -0,0 +1,1115 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_uart_ex.c
+ * @author MCD Application Team
+ * @brief Extended UART HAL module driver.
+ * This file provides firmware functions to manage the following extended
+ * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ *
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### UART peripheral extended features #####
+ ==============================================================================
+
+ (#) Declare a UART_HandleTypeDef handle structure.
+
+ (#) For the UART RS485 Driver Enable mode, initialize the UART registers
+ by calling the HAL_RS485Ex_Init() API.
+
+ (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
+
+ -@- When UART operates in FIFO mode, FIFO mode must be enabled prior
+ starting RX/TX transfers. Also RX/TX FIFO thresholds must be
+ configured prior starting RX/TX transfers.
+
+ @endverbatim
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup UARTEx UARTEx
+ * @brief UART Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_UART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup UARTEX_Private_Constants UARTEx Private Constants
+ * @{
+ */
+/* UART RX FIFO depth */
+#define RX_FIFO_DEPTH 8U
+
+/* UART TX FIFO depth */
+#define TX_FIFO_DEPTH 8U
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup UARTEx_Private_Functions UARTEx Private Functions
+ * @{
+ */
+static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
+static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions
+ * @{
+ */
+
+/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Extended Initialization and Configuration Functions
+ *
+@verbatim
+===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
+ in asynchronous mode.
+ (+) For the asynchronous mode the parameters below can be configured:
+ (++) Baud Rate
+ (++) Word Length
+ (++) Stop Bit
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ (++) Hardware flow control
+ (++) Receiver/transmitter modes
+ (++) Over Sampling Method
+ (++) One-Bit Sampling Method
+ (+) For the asynchronous mode, the following advanced features can be configured as well:
+ (++) TX and/or RX pin level inversion
+ (++) data logical level inversion
+ (++) RX and TX pins swap
+ (++) RX overrun detection disabling
+ (++) DMA disabling on RX error
+ (++) MSB first on communication line
+ (++) auto Baud rate detection
+ [..]
+ The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration
+ procedures (details for the procedures are available in reference manual).
+
+@endverbatim
+
+ Depending on the frame length defined by the M1 and M0 bits (7-bit,
+ 8-bit or 9-bit), the possible UART formats are listed in the
+ following table.
+
+ Table 1. UART frame format.
+ +-----------------------------------------------------------------------+
+ | M1 bit | M0 bit | PCE bit | UART frame |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 0 | | SB | 8 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 0 | | SB | 9 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 0 | | SB | 7 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
+ +-----------------------------------------------------------------------+
+
+ * @{
+ */
+
+/**
+ * @brief Initialize the RS485 Driver enable feature according to the specified
+ * parameters in the UART_InitTypeDef and creates the associated handle.
+ * @param huart UART handle.
+ * @param Polarity Select the driver enable polarity.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high
+ * @arg @ref UART_DE_POLARITY_LOW DE signal is active low
+ * @param AssertionTime Driver Enable assertion time:
+ * 5-bit value defining the time between the activation of the DE (Driver Enable)
+ * signal and the beginning of the start bit. It is expressed in sample time
+ * units (1/8 or 1/16 bit time, depending on the oversampling rate)
+ * @param DeassertionTime Driver Enable deassertion time:
+ * 5-bit value defining the time between the end of the last stop bit, in a
+ * transmitted message, and the de-activation of the DE (Driver Enable) signal.
+ * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
+ * oversampling rate).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
+ uint32_t DeassertionTime)
+{
+ uint32_t temp;
+
+ /* Check the UART handle allocation */
+ if (huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+ /* Check the Driver Enable UART instance */
+ assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
+
+ /* Check the Driver Enable polarity */
+ assert_param(IS_UART_DE_POLARITY(Polarity));
+
+ /* Check the Driver Enable assertion time */
+ assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
+
+ /* Check the Driver Enable deassertion time */
+ assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
+
+ if (huart->gState == HAL_UART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ UART_InitCallbacksToDefault(huart);
+
+ if (huart->MspInitCallback == NULL)
+ {
+ huart->MspInitCallback = HAL_UART_MspInit;
+ }
+
+ /* Init the low level hardware */
+ huart->MspInitCallback(huart);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX */
+ HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ {
+ UART_AdvFeatureConfig(huart);
+ }
+
+ /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
+ SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
+
+ /* Set the Driver Enable polarity */
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
+
+ /* Set the Driver Enable assertion and deassertion times */
+ temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
+ temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
+ MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);
+
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions
+ * @brief Extended functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ This subsection provides a set of Wakeup and FIFO mode related callback functions.
+
+ (#) TX/RX Fifos Callbacks:
+ (+) HAL_UARTEx_RxFifoFullCallback()
+ (+) HAL_UARTEx_TxFifoEmptyCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief UART RX Fifo full callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief UART TX Fifo empty callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides the following functions:
+ (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
+ detection length to more than 4 bits for multiprocessor address mark wake up.
+ (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode
+ trigger: address match, Start Bit detection or RXNE bit status.
+ (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode
+ (+) HAL_UARTEx_DisableStopMode() API disables the above functionality
+ (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode
+ (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode
+ (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
+ (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold
+
+ [..] This subsection also provides a set of additional functions providing enhanced reception
+ services to user. (For example, these functions allow application to handle use cases
+ where number of data to be received is unknown).
+
+ (#) Compared to standard reception services which only consider number of received
+ data elements as reception completion criteria, these functions also consider additional events
+ as triggers for updating reception status to caller :
+ (+) Detection of inactivity period (RX line has not been active for a given period).
+ (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state)
+ for 1 frame time, after last received byte.
+ (++) RX inactivity detected by RTO, i.e. line has been in idle state
+ for a programmable time, after last received byte.
+ (+) Detection that a specific character has been received.
+
+ (#) There are two mode of transfer:
+ (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received,
+ or till IDLE event occurs. Reception is handled only during function execution.
+ When function exits, no data reception could occur. HAL status and number of actually received data elements,
+ are returned by function after finishing transfer.
+ (+) Non-Blocking mode: The reception is performed using Interrupts or DMA.
+ These API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode.
+ The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process
+ The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected.
+
+ (#) Blocking mode API:
+ (+) HAL_UARTEx_ReceiveToIdle()
+
+ (#) Non-Blocking mode API with Interrupt:
+ (+) HAL_UARTEx_ReceiveToIdle_IT()
+
+ (#) Non-Blocking mode API with DMA:
+ (+) HAL_UARTEx_ReceiveToIdle_DMA()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief By default in multiprocessor mode, when the wake up method is set
+ * to address mark, the UART handles only 4-bit long addresses detection;
+ * this API allows to enable longer addresses detection (6-, 7- or 8-bit
+ * long).
+ * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode,
+ * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
+ * @param huart UART handle.
+ * @param AddressLength This parameter can be one of the following values:
+ * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address
+ * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
+{
+ /* Check the UART handle allocation */
+ if (huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the address length parameter */
+ assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the address length */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
+
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->gState to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+/**
+ * @brief Set Wakeup from Stop mode interrupt flag selection.
+ * @note It is the application responsibility to enable the interrupt used as
+ * usart_wkup interrupt source before entering low-power mode.
+ * @param huart UART handle.
+ * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_WAKEUP_ON_ADDRESS
+ * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tickstart;
+
+ /* check the wake-up from stop mode UART instance */
+ assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
+ /* check the wake-up selection parameter */
+ assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+
+ if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS)
+ {
+ UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ /* Wait until REACK flag is set */
+ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+ {
+ status = HAL_TIMEOUT;
+ }
+ else
+ {
+ /* Initialize the UART State */
+ huart->gState = HAL_UART_STATE_READY;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return status;
+}
+
+/**
+ * @brief Enable UART Stop Mode.
+ * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
+{
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ /* Set UESM bit */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable UART Stop Mode.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
+{
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ /* Clear UESM bit */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable the FIFO mode.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart)
+{
+ uint32_t tmpcr1;
+
+ /* Check parameters */
+ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Save actual UART configuration */
+ tmpcr1 = READ_REG(huart->Instance->CR1);
+
+ /* Disable UART */
+ __HAL_UART_DISABLE(huart);
+
+ /* Enable FIFO mode */
+ SET_BIT(tmpcr1, USART_CR1_FIFOEN);
+ huart->FifoMode = UART_FIFOMODE_ENABLE;
+
+ /* Restore UART configuration */
+ WRITE_REG(huart->Instance->CR1, tmpcr1);
+
+ /* Determine the number of data to process during RX/TX ISR execution */
+ UARTEx_SetNbDataToProcess(huart);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the FIFO mode.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart)
+{
+ uint32_t tmpcr1;
+
+ /* Check parameters */
+ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Save actual UART configuration */
+ tmpcr1 = READ_REG(huart->Instance->CR1);
+
+ /* Disable UART */
+ __HAL_UART_DISABLE(huart);
+
+ /* Enable FIFO mode */
+ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
+ huart->FifoMode = UART_FIFOMODE_DISABLE;
+
+ /* Restore UART configuration */
+ WRITE_REG(huart->Instance->CR1, tmpcr1);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the TXFIFO threshold.
+ * @param huart UART handle.
+ * @param Threshold TX FIFO threshold value
+ * This parameter can be one of the following values:
+ * @arg @ref UART_TXFIFO_THRESHOLD_1_8
+ * @arg @ref UART_TXFIFO_THRESHOLD_1_4
+ * @arg @ref UART_TXFIFO_THRESHOLD_1_2
+ * @arg @ref UART_TXFIFO_THRESHOLD_3_4
+ * @arg @ref UART_TXFIFO_THRESHOLD_7_8
+ * @arg @ref UART_TXFIFO_THRESHOLD_8_8
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
+{
+ uint32_t tmpcr1;
+
+ /* Check parameters */
+ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+ assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Save actual UART configuration */
+ tmpcr1 = READ_REG(huart->Instance->CR1);
+
+ /* Disable UART */
+ __HAL_UART_DISABLE(huart);
+
+ /* Update TX threshold configuration */
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
+
+ /* Determine the number of data to process during RX/TX ISR execution */
+ UARTEx_SetNbDataToProcess(huart);
+
+ /* Restore UART configuration */
+ WRITE_REG(huart->Instance->CR1, tmpcr1);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the RXFIFO threshold.
+ * @param huart UART handle.
+ * @param Threshold RX FIFO threshold value
+ * This parameter can be one of the following values:
+ * @arg @ref UART_RXFIFO_THRESHOLD_1_8
+ * @arg @ref UART_RXFIFO_THRESHOLD_1_4
+ * @arg @ref UART_RXFIFO_THRESHOLD_1_2
+ * @arg @ref UART_RXFIFO_THRESHOLD_3_4
+ * @arg @ref UART_RXFIFO_THRESHOLD_7_8
+ * @arg @ref UART_RXFIFO_THRESHOLD_8_8
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
+{
+ uint32_t tmpcr1;
+
+ /* Check the parameters */
+ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+ assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold));
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Save actual UART configuration */
+ tmpcr1 = READ_REG(huart->Instance->CR1);
+
+ /* Disable UART */
+ __HAL_UART_DISABLE(huart);
+
+ /* Update RX threshold configuration */
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
+
+ /* Determine the number of data to process during RX/TX ISR execution */
+ UARTEx_SetNbDataToProcess(huart);
+
+ /* Restore UART configuration */
+ WRITE_REG(huart->Instance->CR1, tmpcr1);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode till either the expected number of data
+ * is received or an IDLE event occurs.
+ * @note HAL_OK is returned if reception is completed (expected number of data has been received)
+ * or if reception is stopped after IDLE event (less than the expected number of data has been received)
+ * In this case, RxLen output parameter indicates number of data available in reception buffer.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of uint16_t. In this case, Size must indicate the number
+ * of uint16_t available through pData.
+ * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
+ * is not empty. Read operations from the RDR register are performed when
+ * RXFNE flag is set. From hardware perspective, RXFNE flag and
+ * RXNE are mapped on the same bit-field.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
+ * @param Size Amount of data elements (uint8_t or uint16_t) to be received.
+ * @param RxLen Number of data elements finally received
+ * (could be lower than Size, in case reception ends on IDLE event)
+ * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
+ uint32_t Timeout)
+{
+ uint8_t *pdata8bits;
+ uint16_t *pdata16bits;
+ uint16_t uhMask;
+ uint32_t tickstart;
+
+ /* Check that a Rx process is not already ongoing */
+ if (huart->RxState == HAL_UART_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ __HAL_LOCK(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->RxState = HAL_UART_STATE_BUSY_RX;
+ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ huart->RxXferSize = Size;
+ huart->RxXferCount = Size;
+
+ /* Computation of UART mask to apply to RDR register */
+ UART_MASK_COMPUTATION(huart);
+ uhMask = huart->Mask;
+
+ /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ pdata8bits = NULL;
+ pdata16bits = (uint16_t *) pData;
+ }
+ else
+ {
+ pdata8bits = pData;
+ pdata16bits = NULL;
+ }
+
+ __HAL_UNLOCK(huart);
+
+ /* Initialize output number of received elements */
+ *RxLen = 0U;
+
+ /* as long as data have to be received */
+ while (huart->RxXferCount > 0U)
+ {
+ /* Check if IDLE flag is set */
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE))
+ {
+ /* Clear IDLE flag in ISR */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+
+ /* If Set, but no data ever received, clear flag without exiting loop */
+ /* If Set, and data has already been received, this means Idle Event is valid : End reception */
+ if (*RxLen > 0U)
+ {
+ huart->RxState = HAL_UART_STATE_READY;
+
+ return HAL_OK;
+ }
+ }
+
+ /* Check if RXNE flag is set */
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE))
+ {
+ if (pdata8bits == NULL)
+ {
+ *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
+ pdata16bits++;
+ }
+ else
+ {
+ *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
+ pdata8bits++;
+ }
+ /* Increment number of received elements */
+ *RxLen += 1U;
+ huart->RxXferCount--;
+ }
+
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ huart->RxState = HAL_UART_STATE_READY;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Set number of received elements in output parameter : RxLen */
+ *RxLen = huart->RxXferSize - huart->RxXferCount;
+ /* At end of Rx process, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in interrupt mode till either the expected number of data
+ * is received or an IDLE event occurs.
+ * @note Reception is initiated by this function call. Further progress of reception is achieved thanks
+ * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating
+ * number of received data elements.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of uint16_t. In this case, Size must indicate the number
+ * of uint16_t available through pData.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
+ * @param Size Amount of data elements (uint8_t or uint16_t) to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check that a Rx process is not already ongoing */
+ if (huart->RxState == HAL_UART_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ __HAL_LOCK(huart);
+
+ /* Set Reception type to reception till IDLE Event*/
+ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+
+ status = UART_Start_Receive_IT(huart, pData, Size);
+
+ /* Check Rx process has been successfully started */
+ if (status == HAL_OK)
+ {
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ }
+ else
+ {
+ /* In case of errors already pending when reception is started,
+ Interrupts may have already been raised and lead to reception abortion.
+ (Overrun error for instance).
+ In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
+ status = HAL_ERROR;
+ }
+ }
+
+ return status;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in DMA mode till either the expected number
+ * of data is received or an IDLE event occurs.
+ * @note Reception is initiated by this function call. Further progress of reception is achieved thanks
+ * to DMA services, transferring automatically received data elements in user reception buffer and
+ * calling registered callbacks at half/end of reception. UART IDLE events are also used to consider
+ * reception phase as ended. In all cases, callback execution will indicate number of received data elements.
+ * @note When the UART parity is enabled (PCE = 1), the received data contain
+ * the parity bit (MSB position).
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of uint16_t. In this case, Size must indicate the number
+ * of uint16_t available through pData.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
+ * @param Size Amount of data elements (uint8_t or uint16_t) to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check that a Rx process is not already ongoing */
+ if (huart->RxState == HAL_UART_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ __HAL_LOCK(huart);
+
+ /* Set Reception type to reception till IDLE Event*/
+ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+
+ status = UART_Start_Receive_DMA(huart, pData, Size);
+
+ /* Check Rx process has been successfully started */
+ if (status == HAL_OK)
+ {
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ }
+ else
+ {
+ /* In case of errors already pending when reception is started,
+ Interrupts may have already been raised and lead to reception abortion.
+ (Overrun error for instance).
+ In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
+ status = HAL_ERROR;
+ }
+ }
+
+ return status;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Set autonomous mode Configuration.
+ * @param huart UART handle.
+ * @param sConfig Autonomous mode structure parameters.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_SetConfigAutonomousMode(UART_HandleTypeDef *huart, UART_AutonomousModeConfTypeDef *sConfig)
+{
+ uint32_t tmpreg;
+
+ if (huart->gState == HAL_UART_STATE_READY)
+ {
+ /* Check the parameters */
+ assert_param(IS_UART_TRIGGER_POLARITY(sConfig->TriggerPolarity));
+ assert_param(IS_UART_IDLE_FRAME_TRANSMIT(sConfig->IdleFrame));
+ assert_param(IS_UART_TX_DATA_SIZE(sConfig->DataSize));
+ if (IS_LPUART_INSTANCE(huart->Instance))
+ {
+ assert_param(IS_LPUART_TRIGGER_SELECTION(sConfig->TriggerSelection));
+ }
+ else
+ {
+ assert_param(IS_UART_TRIGGER_SELECTION(sConfig->TriggerSelection));
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Disable UART */
+ __HAL_UART_DISABLE(huart);
+
+ /* Disable Transmitter */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_TE);
+
+ /* Clear AUTOCR register */
+ CLEAR_REG(huart->Instance->AUTOCR);
+
+ /* UART AUTOCR Configuration */
+ tmpreg = ((sConfig->DataSize << USART_AUTOCR_TDN_Pos) | (sConfig->TriggerPolarity) | \
+ (sConfig->AutonomousModeState) | (sConfig->IdleFrame) | \
+ (sConfig->TriggerSelection << USART_AUTOCR_TRIGSEL_Pos));
+
+ WRITE_REG(huart->Instance->AUTOCR, tmpreg);
+
+ /* Enable UART */
+ __HAL_UART_ENABLE(huart);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Get autonomous mode Configuration.
+ * @param huart UART handle.
+ * @param sConfig Autonomous mode structure parameters.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_GetConfigAutonomousMode(UART_HandleTypeDef *huart, UART_AutonomousModeConfTypeDef *sConfig)
+{
+ uint32_t tmpreg;
+
+ /* Read AUTOCR register */
+ tmpreg = READ_REG(huart->Instance->AUTOCR);
+
+ /* Fill Autonomous structure parameter */
+ sConfig->AutonomousModeState = (tmpreg & USART_AUTOCR_TRIGEN);
+ sConfig->TriggerSelection = ((tmpreg & USART_AUTOCR_TRIGSEL) >> USART_AUTOCR_TRIGSEL_Pos);
+ sConfig->TriggerPolarity = (tmpreg & USART_AUTOCR_TRIGPOL);
+ sConfig->IdleFrame = (tmpreg & USART_AUTOCR_IDLEDIS);
+ sConfig->DataSize = (tmpreg & USART_AUTOCR_TDN);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Clear autonomous mode Configuration.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_ClearConfigAutonomousMode(UART_HandleTypeDef *huart)
+{
+ if (huart->gState == HAL_UART_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Disable UART */
+ __HAL_UART_DISABLE(huart);
+
+ /* Clear AUTOCR register */
+ CLEAR_REG(huart->Instance->AUTOCR);
+
+ /* Enable UART */
+ __HAL_UART_ENABLE(huart);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup UARTEx_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection.
+ * @param huart UART handle.
+ * @param WakeUpSelection UART wake up from stop mode parameters.
+ * @retval None
+ */
+static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
+{
+ assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));
+
+ /* Set the USART address length */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength);
+
+ /* Set the USART address node */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));
+}
+
+/**
+ * @brief Calculate the number of data to process in RX/TX ISR.
+ * @note The RX FIFO depth and the TX FIFO depth is extracted from
+ * the UART configuration registers.
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart)
+{
+ uint8_t rx_fifo_depth;
+ uint8_t tx_fifo_depth;
+ uint8_t rx_fifo_threshold;
+ uint8_t tx_fifo_threshold;
+ static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
+ static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
+
+ if (huart->FifoMode == UART_FIFOMODE_DISABLE)
+ {
+ huart->NbTxDataToProcess = 1U;
+ huart->NbRxDataToProcess = 1U;
+ }
+ else
+ {
+ rx_fifo_depth = RX_FIFO_DEPTH;
+ tx_fifo_depth = TX_FIFO_DEPTH;
+ rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
+ tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
+ huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
+ (uint16_t)denominator[tx_fifo_threshold];
+ huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
+ (uint16_t)denominator[rx_fifo_threshold];
+ }
+}
+/**
+ * @}
+ */
+
+#endif /* HAL_UART_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_usart.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_usart.c
new file mode 100644
index 00000000..fcf2061e
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_usart.c
@@ -0,0 +1,3834 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_usart.c
+ * @author MCD Application Team
+ * @brief USART HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter
+ * Peripheral (USART).
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State and Error functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ The USART HAL driver can be used as follows:
+
+ (#) Declare a USART_HandleTypeDef handle structure (eg. USART_HandleTypeDef husart).
+ (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API:
+ (++) Enable the USARTx interface clock.
+ (++) USART pins configuration:
+ (+++) Enable the clock for the USART GPIOs.
+ (+++) Configure these USART pins as alternate function pull-up.
+ (++) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
+ HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
+ (+++) Configure the USARTx interrupt priority.
+ (+++) Enable the NVIC USART IRQ handle.
+ (++) USART interrupts handling:
+ -@@- The specific USART interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
+ (++) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
+ HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs):
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx channel.
+ (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer
+ complete interrupt on the DMA Tx/Rx channel.
+
+ (#) Program the Baud Rate, Word Length, Stop Bit, Parity, and Mode
+ (Receiver/Transmitter) in the husart handle Init structure.
+
+ (#) Initialize the USART registers by calling the HAL_USART_Init() API:
+ (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customized HAL_USART_MspInit(&husart) API.
+
+ [..]
+ (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's
+ HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and
+ HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef.
+
+ ##### Callback registration #####
+ ==================================
+
+ [..]
+ The compilation define USE_HAL_USART_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ [..]
+ Use Function @ref HAL_USART_RegisterCallback() to register a user callback.
+ Function @ref HAL_USART_RegisterCallback() allows to register following callbacks:
+ (+) TxHalfCpltCallback : Tx Half Complete Callback.
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxHalfCpltCallback : Rx Half Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) TxRxCpltCallback : Tx Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) RxFifoFullCallback : Rx Fifo Full Callback.
+ (+) TxFifoEmptyCallback : Tx Fifo Empty Callback.
+ (+) MspInitCallback : USART MspInit.
+ (+) MspDeInitCallback : USART MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ [..]
+ Use function @ref HAL_USART_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function.
+ @ref HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TxHalfCpltCallback : Tx Half Complete Callback.
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxHalfCpltCallback : Rx Half Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) TxRxCpltCallback : Tx Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) RxFifoFullCallback : Rx Fifo Full Callback.
+ (+) TxFifoEmptyCallback : Tx Fifo Empty Callback.
+ (+) MspInitCallback : USART MspInit.
+ (+) MspDeInitCallback : USART MspDeInit.
+
+ [..]
+ By default, after the @ref HAL_USART_Init() and when the state is HAL_USART_STATE_RESET
+ all callbacks are set to the corresponding weak (surcharged) functions:
+ examples @ref HAL_USART_TxCpltCallback(), @ref HAL_USART_RxHalfCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_USART_Init()
+ and @ref HAL_USART_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_USART_Init() and @ref HAL_USART_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+ [..]
+ Callbacks can be registered/unregistered in HAL_USART_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_USART_STATE_READY or HAL_USART_STATE_RESET state, thus registered (user)
+ MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_USART_RegisterCallback() before calling @ref HAL_USART_DeInit()
+ or @ref HAL_USART_Init() function.
+
+ [..]
+ When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available
+ and weak (surcharged) callbacks are used.
+
+
+ @endverbatim
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup USART USART
+ * @brief HAL USART Synchronous module driver
+ * @{
+ */
+
+#ifdef HAL_USART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup USART_Private_Constants USART Private Constants
+ * @{
+ */
+#define USART_DUMMY_DATA ((uint16_t) 0xFFFF) /*!< USART transmitted dummy data */
+#define USART_TEACK_REACK_TIMEOUT 1000U /*!< USART TX or RX enable acknowledge time-out value */
+#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
+ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8 | \
+ USART_CR1_FIFOEN )) /*!< USART CR1 fields of parameters set by USART_SetConfig API */
+
+#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | \
+ USART_CR2_LBCL | USART_CR2_STOP | USART_CR2_SLVEN | \
+ USART_CR2_DIS_NSS)) /*!< USART CR2 fields of parameters set by USART_SetConfig API */
+
+#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< USART or USART CR3 fields of parameters set by USART_SetConfig API */
+
+#define USART_BRR_MIN 0x10U /* USART BRR minimum authorized value */
+#define USART_BRR_MAX 0xFFFFU /* USART BRR maximum authorized value */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup USART_Private_Functions
+ * @{
+ */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+static void USART_EndTransfer(USART_HandleTypeDef *husart);
+static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMAError(DMA_HandleTypeDef *hdma);
+static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status,
+ uint32_t Tickstart, uint32_t Timeout);
+static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart);
+static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart);
+static void USART_TxISR_8BIT(USART_HandleTypeDef *husart);
+static void USART_TxISR_16BIT(USART_HandleTypeDef *husart);
+static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart);
+static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart);
+static void USART_EndTransmit_IT(USART_HandleTypeDef *husart);
+static void USART_RxISR_8BIT(USART_HandleTypeDef *husart);
+static void USART_RxISR_16BIT(USART_HandleTypeDef *husart);
+static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart);
+static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart);
+
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup USART_Exported_Functions USART Exported Functions
+ * @{
+ */
+
+/** @defgroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USART
+ in asynchronous and in synchronous modes.
+ (+) For the asynchronous mode only these parameters can be configured:
+ (++) Baud Rate
+ (++) Word Length
+ (++) Stop Bit
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ (++) USART polarity
+ (++) USART phase
+ (++) USART LastBit
+ (++) Receiver/transmitter modes
+
+ [..]
+ The HAL_USART_Init() function follows the USART synchronous configuration
+ procedure (details for the procedure are available in reference manual).
+
+@endverbatim
+
+ Depending on the frame length defined by the M1 and M0 bits (7-bit,
+ 8-bit or 9-bit), the possible USART formats are listed in the
+ following table.
+
+ Table 1. USART frame format.
+ +-----------------------------------------------------------------------+
+ | M1 bit | M0 bit | PCE bit | USART frame |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 0 | | SB | 8 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 0 | | SB | 9 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 0 | | SB | 7 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
+ +-----------------------------------------------------------------------+
+
+ * @{
+ */
+
+/**
+ * @brief Initialize the USART mode according to the specified
+ * parameters in the USART_InitTypeDef and initialize the associated handle.
+ * @param husart USART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
+{
+ /* Check the USART handle allocation */
+ if (husart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_USART_INSTANCE(husart->Instance));
+
+ if (husart->State == HAL_USART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ husart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ USART_InitCallbacksToDefault(husart);
+
+ if (husart->MspInitCallback == NULL)
+ {
+ husart->MspInitCallback = HAL_USART_MspInit;
+ }
+
+ /* Init the low level hardware */
+ husart->MspInitCallback(husart);
+#else
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_USART_MspInit(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+
+ husart->State = HAL_USART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_USART_DISABLE(husart);
+
+ /* Set the Usart Communication parameters */
+ if (USART_SetConfig(husart) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ /* In Synchronous mode, the following bits must be kept cleared:
+ - LINEN bit in the USART_CR2 register
+ - HDSEL, SCEN and IREN bits in the USART_CR3 register.
+ */
+ husart->Instance->CR2 &= ~USART_CR2_LINEN;
+ husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
+
+ /* Enable the Peripheral */
+ __HAL_USART_ENABLE(husart);
+
+ /* TEACK and/or REACK to check before moving husart->State to Ready */
+ return (USART_CheckIdleState(husart));
+}
+
+/**
+ * @brief DeInitialize the USART peripheral.
+ * @param husart USART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
+{
+ /* Check the USART handle allocation */
+ if (husart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_USART_INSTANCE(husart->Instance));
+
+ husart->State = HAL_USART_STATE_BUSY;
+
+ husart->Instance->CR1 = 0x0U;
+ husart->Instance->CR2 = 0x0U;
+ husart->Instance->CR3 = 0x0U;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ if (husart->MspDeInitCallback == NULL)
+ {
+ husart->MspDeInitCallback = HAL_USART_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ husart->MspDeInitCallback(husart);
+#else
+ /* DeInit the low level hardware */
+ HAL_USART_MspDeInit(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_RESET;
+
+ /* Process Unlock */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the USART MSP.
+ * @param husart USART handle.
+ * @retval None
+ */
+__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USART_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the USART MSP.
+ * @param husart USART handle.
+ * @retval None
+ */
+__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USART_MspDeInit can be implemented in the user file
+ */
+}
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User USART Callback
+ * To be used instead of the weak predefined callback
+ * @param husart usart handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+ * @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+ * @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_USART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
+ * @arg @ref HAL_USART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
+ * @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
++ */
+HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID,
+ pUSART_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(husart);
+
+ if (husart->State == HAL_USART_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_USART_TX_HALFCOMPLETE_CB_ID :
+ husart->TxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_USART_TX_COMPLETE_CB_ID :
+ husart->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_USART_RX_HALFCOMPLETE_CB_ID :
+ husart->RxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_USART_RX_COMPLETE_CB_ID :
+ husart->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_USART_TX_RX_COMPLETE_CB_ID :
+ husart->TxRxCpltCallback = pCallback;
+ break;
+
+ case HAL_USART_ERROR_CB_ID :
+ husart->ErrorCallback = pCallback;
+ break;
+
+ case HAL_USART_ABORT_COMPLETE_CB_ID :
+ husart->AbortCpltCallback = pCallback;
+ break;
+
+ case HAL_USART_RX_FIFO_FULL_CB_ID :
+ husart->RxFifoFullCallback = pCallback;
+ break;
+
+ case HAL_USART_TX_FIFO_EMPTY_CB_ID :
+ husart->TxFifoEmptyCallback = pCallback;
+ break;
+
+ case HAL_USART_MSPINIT_CB_ID :
+ husart->MspInitCallback = pCallback;
+ break;
+
+ case HAL_USART_MSPDEINIT_CB_ID :
+ husart->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (husart->State == HAL_USART_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_USART_MSPINIT_CB_ID :
+ husart->MspInitCallback = pCallback;
+ break;
+
+ case HAL_USART_MSPDEINIT_CB_ID :
+ husart->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(husart);
+
+ return status;
+}
+
+/**
+ * @brief Unregister an USART Callback
+ * USART callaback is redirected to the weak predefined callback
+ * @param husart usart handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+ * @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+ * @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_USART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
+ * @arg @ref HAL_USART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
+ * @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(husart);
+
+ if (HAL_USART_STATE_READY == husart->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_USART_TX_HALFCOMPLETE_CB_ID :
+ husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ break;
+
+ case HAL_USART_TX_COMPLETE_CB_ID :
+ husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ break;
+
+ case HAL_USART_RX_HALFCOMPLETE_CB_ID :
+ husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ break;
+
+ case HAL_USART_RX_COMPLETE_CB_ID :
+ husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ break;
+
+ case HAL_USART_TX_RX_COMPLETE_CB_ID :
+ husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
+ break;
+
+ case HAL_USART_ERROR_CB_ID :
+ husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_USART_ABORT_COMPLETE_CB_ID :
+ husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ break;
+
+ case HAL_USART_RX_FIFO_FULL_CB_ID :
+ husart->RxFifoFullCallback = HAL_USARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
+ break;
+
+ case HAL_USART_TX_FIFO_EMPTY_CB_ID :
+ husart->TxFifoEmptyCallback = HAL_USARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
+ break;
+
+ case HAL_USART_MSPINIT_CB_ID :
+ husart->MspInitCallback = HAL_USART_MspInit; /* Legacy weak MspInitCallback */
+ break;
+
+ case HAL_USART_MSPDEINIT_CB_ID :
+ husart->MspDeInitCallback = HAL_USART_MspDeInit; /* Legacy weak MspDeInitCallback */
+ break;
+
+ default :
+ /* Update the error code */
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_USART_STATE_RESET == husart->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_USART_MSPINIT_CB_ID :
+ husart->MspInitCallback = HAL_USART_MspInit;
+ break;
+
+ case HAL_USART_MSPDEINIT_CB_ID :
+ husart->MspDeInitCallback = HAL_USART_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(husart);
+
+ return status;
+}
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Exported_Functions_Group2 IO operation functions
+ * @brief USART Transmit and Receive functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to manage the USART synchronous
+ data transfers.
+
+ [..] The USART supports master mode only: it cannot receive or send data related to an input
+ clock (SCLK is always an output).
+
+ [..]
+
+ (#) There are two modes of transfer:
+ (++) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode: The communication is performed using Interrupts
+ or DMA, These API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks
+ will be executed respectively at the end of the transmit or Receive process
+ The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected
+
+ (#) Blocking mode API's are :
+ (++) HAL_USART_Transmit() in simplex mode
+ (++) HAL_USART_Receive() in full duplex receive only
+ (++) HAL_USART_TransmitReceive() in full duplex mode
+
+ (#) Non-Blocking mode API's with Interrupt are :
+ (++) HAL_USART_Transmit_IT() in simplex mode
+ (++) HAL_USART_Receive_IT() in full duplex receive only
+ (++) HAL_USART_TransmitReceive_IT() in full duplex mode
+ (++) HAL_USART_IRQHandler()
+
+ (#) No-Blocking mode API's with DMA are :
+ (++) HAL_USART_Transmit_DMA() in simplex mode
+ (++) HAL_USART_Receive_DMA() in full duplex receive only
+ (++) HAL_USART_TransmitReceive_DMA() in full duplex mode
+ (++) HAL_USART_DMAPause()
+ (++) HAL_USART_DMAResume()
+ (++) HAL_USART_DMAStop()
+
+ (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
+ (++) HAL_USART_TxCpltCallback()
+ (++) HAL_USART_RxCpltCallback()
+ (++) HAL_USART_TxHalfCpltCallback()
+ (++) HAL_USART_RxHalfCpltCallback()
+ (++) HAL_USART_ErrorCallback()
+ (++) HAL_USART_TxRxCpltCallback()
+
+ (#) Non-Blocking mode transfers could be aborted using Abort API's :
+ (++) HAL_USART_Abort()
+ (++) HAL_USART_Abort_IT()
+
+ (#) For Abort services based on interrupts (HAL_USART_Abort_IT), a Abort Complete Callbacks is provided:
+ (++) HAL_USART_AbortCpltCallback()
+
+ (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+ Errors are handled as follows :
+ (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ to be evaluated by user : this concerns Frame Error,
+ Parity Error or Noise Error in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify
+ error type, and HAL_USART_ErrorCallback() user callback is executed.
+ Transfer is kept ongoing on USART side.
+ If user wants to abort it, Abort services should be called by user.
+ (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type,
+ and HAL_USART_ErrorCallback() user callback is executed.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Simplex send an amount of data in blocking mode.
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pTxData.
+ * @param husart USART handle.
+ * @param pTxData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
+{
+ uint8_t *ptxdata8bits;
+ uint16_t *ptxdata16bits;
+ uint32_t tickstart;
+
+ if (husart->State == HAL_USART_STATE_READY)
+ {
+ if ((pTxData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_TX;
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ husart->TxXferSize = Size;
+ husart->TxXferCount = Size;
+
+ /* In case of 9bits/No Parity transfer, pTxData needs to be handled as a uint16_t pointer */
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ ptxdata8bits = NULL;
+ ptxdata16bits = (uint16_t *) pTxData;
+ }
+ else
+ {
+ ptxdata8bits = pTxData;
+ ptxdata16bits = NULL;
+ }
+
+ /* Check the remaining data to be sent */
+ while (husart->TxXferCount > 0U)
+ {
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if (ptxdata8bits == NULL)
+ {
+ husart->Instance->TDR = (uint16_t)(*ptxdata16bits & 0x01FFU);
+ ptxdata16bits++;
+ }
+ else
+ {
+ husart->Instance->TDR = (uint8_t)(*ptxdata8bits & 0xFFU);
+ ptxdata8bits++;
+ }
+
+ husart->TxXferCount--;
+ }
+
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear Transmission Complete Flag */
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
+
+ /* Clear overrun flag and discard the received data */
+ __HAL_USART_CLEAR_OREFLAG(husart);
+ __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
+ __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
+
+ /* At end of Tx process, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode.
+ * @note To receive synchronous data, dummy data are simultaneously transmitted.
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pRxData.
+ * @param husart USART handle.
+ * @param pRxData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
+{
+ uint8_t *prxdata8bits;
+ uint16_t *prxdata16bits;
+ uint16_t uhMask;
+ uint32_t tickstart;
+
+ if (husart->State == HAL_USART_STATE_READY)
+ {
+ if ((pRxData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_RX;
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ husart->RxXferSize = Size;
+ husart->RxXferCount = Size;
+
+ /* Computation of USART mask to apply to RDR register */
+ USART_MASK_COMPUTATION(husart);
+ uhMask = husart->Mask;
+
+ /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ prxdata8bits = NULL;
+ prxdata16bits = (uint16_t *) pRxData;
+ }
+ else
+ {
+ prxdata8bits = pRxData;
+ prxdata16bits = NULL;
+ }
+
+ /* as long as data have to be received */
+ while (husart->RxXferCount > 0U)
+ {
+ if (husart->SlaveMode == USART_SLAVEMODE_DISABLE)
+ {
+ /* Wait until TXE flag is set to send dummy byte in order to generate the
+ * clock for the slave to send data.
+ * Whatever the frame length (7, 8 or 9-bit long), the same dummy value
+ * can be written for all the cases. */
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FF);
+ }
+
+ /* Wait for RXNE Flag */
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if (prxdata8bits == NULL)
+ {
+ *prxdata16bits = (uint16_t)(husart->Instance->RDR & uhMask);
+ prxdata16bits++;
+ }
+ else
+ {
+ *prxdata8bits = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU));
+ prxdata8bits++;
+ }
+
+ husart->RxXferCount--;
+
+ }
+
+ /* Clear SPI slave underrun flag and discard transmit data */
+ if (husart->SlaveMode == USART_SLAVEMODE_ENABLE)
+ {
+ __HAL_USART_CLEAR_UDRFLAG(husart);
+ __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
+ }
+
+ /* At end of Rx process, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Full-Duplex Send and Receive an amount of data in blocking mode.
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
+ * of u16 available through pTxData and through pRxData.
+ * @param husart USART handle.
+ * @param pTxData pointer to TX data buffer (u8 or u16 data elements).
+ * @param pRxData pointer to RX data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be sent (same amount to be received).
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size, uint32_t Timeout)
+{
+ uint8_t *prxdata8bits;
+ uint16_t *prxdata16bits;
+ uint8_t *ptxdata8bits;
+ uint16_t *ptxdata16bits;
+ uint16_t uhMask;
+ uint16_t rxdatacount;
+ uint32_t tickstart;
+
+ if (husart->State == HAL_USART_STATE_READY)
+ {
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_RX;
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ husart->RxXferSize = Size;
+ husart->TxXferSize = Size;
+ husart->TxXferCount = Size;
+ husart->RxXferCount = Size;
+
+ /* Computation of USART mask to apply to RDR register */
+ USART_MASK_COMPUTATION(husart);
+ uhMask = husart->Mask;
+
+ /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ prxdata8bits = NULL;
+ ptxdata8bits = NULL;
+ ptxdata16bits = (uint16_t *) pTxData;
+ prxdata16bits = (uint16_t *) pRxData;
+ }
+ else
+ {
+ prxdata8bits = pRxData;
+ ptxdata8bits = pTxData;
+ ptxdata16bits = NULL;
+ prxdata16bits = NULL;
+ }
+
+ if ((husart->TxXferCount == 0x01U) || (husart->SlaveMode == USART_SLAVEMODE_ENABLE))
+ {
+ /* Wait until TXE flag is set to send data */
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if (ptxdata8bits == NULL)
+ {
+ husart->Instance->TDR = (uint16_t)(*ptxdata16bits & uhMask);
+ ptxdata16bits++;
+ }
+ else
+ {
+ husart->Instance->TDR = (uint8_t)(*ptxdata8bits & (uint8_t)(uhMask & 0xFFU));
+ ptxdata8bits++;
+ }
+
+ husart->TxXferCount--;
+ }
+
+ /* Check the remain data to be sent */
+ /* rxdatacount is a temporary variable for MISRAC2012-Rule-13.5 */
+ rxdatacount = husart->RxXferCount;
+ while ((husart->TxXferCount > 0U) || (rxdatacount > 0U))
+ {
+ if (husart->TxXferCount > 0U)
+ {
+ /* Wait until TXE flag is set to send data */
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if (ptxdata8bits == NULL)
+ {
+ husart->Instance->TDR = (uint16_t)(*ptxdata16bits & uhMask);
+ ptxdata16bits++;
+ }
+ else
+ {
+ husart->Instance->TDR = (uint8_t)(*ptxdata8bits & (uint8_t)(uhMask & 0xFFU));
+ ptxdata8bits++;
+ }
+
+ husart->TxXferCount--;
+ }
+
+ if (husart->RxXferCount > 0U)
+ {
+ /* Wait for RXNE Flag */
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if (prxdata8bits == NULL)
+ {
+ *prxdata16bits = (uint16_t)(husart->Instance->RDR & uhMask);
+ prxdata16bits++;
+ }
+ else
+ {
+ *prxdata8bits = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU));
+ prxdata8bits++;
+ }
+
+ husart->RxXferCount--;
+ }
+ rxdatacount = husart->RxXferCount;
+ }
+
+ /* At end of TxRx process, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in interrupt mode.
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pTxData.
+ * @param husart USART handle.
+ * @param pTxData pointer to data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be sent.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
+{
+ if (husart->State == HAL_USART_STATE_READY)
+ {
+ if ((pTxData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pTxBuffPtr = pTxData;
+ husart->TxXferSize = Size;
+ husart->TxXferCount = Size;
+ husart->TxISR = NULL;
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_TX;
+
+ /* The USART Error Interrupts: (Frame error, noise error, overrun error)
+ are not managed by the USART Transmit Process to avoid the overrun interrupt
+ when the usart mode is configured for transmit and receive "USART_MODE_TX_RX"
+ to benefit for the frame error and noise interrupts the usart mode should be
+ configured only for transmit "USART_MODE_TX" */
+
+ /* Configure Tx interrupt processing */
+ if (husart->FifoMode == USART_FIFOMODE_ENABLE)
+ {
+ /* Set the Tx ISR function pointer according to the data word length */
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ husart->TxISR = USART_TxISR_16BIT_FIFOEN;
+ }
+ else
+ {
+ husart->TxISR = USART_TxISR_8BIT_FIFOEN;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the TX FIFO threshold interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TXFT);
+ }
+ else
+ {
+ /* Set the Tx ISR function pointer according to the data word length */
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ husart->TxISR = USART_TxISR_16BIT;
+ }
+ else
+ {
+ husart->TxISR = USART_TxISR_8BIT;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the USART Transmit Data Register Empty Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in interrupt mode.
+ * @note To receive synchronous data, dummy data are simultaneously transmitted.
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pRxData.
+ * @param husart USART handle.
+ * @param pRxData pointer to data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
+{
+ uint16_t nb_dummy_data;
+
+ if (husart->State == HAL_USART_STATE_READY)
+ {
+ if ((pRxData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pRxBuffPtr = pRxData;
+ husart->RxXferSize = Size;
+ husart->RxXferCount = Size;
+ husart->RxISR = NULL;
+
+ USART_MASK_COMPUTATION(husart);
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_RX;
+
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Configure Rx interrupt processing */
+ if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess))
+ {
+ /* Set the Rx ISR function pointer according to the data word length */
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ husart->RxISR = USART_RxISR_16BIT_FIFOEN;
+ }
+ else
+ {
+ husart->RxISR = USART_RxISR_8BIT_FIFOEN;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the USART Parity Error interrupt and RX FIFO Threshold interrupt */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ SET_BIT(husart->Instance->CR3, USART_CR3_RXFTIE);
+ }
+ else
+ {
+ /* Set the Rx ISR function pointer according to the data word length */
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ husart->RxISR = USART_RxISR_16BIT;
+ }
+ else
+ {
+ husart->RxISR = USART_RxISR_8BIT;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the USART Parity Error and Data Register not empty Interrupts */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+ }
+
+ if (husart->SlaveMode == USART_SLAVEMODE_DISABLE)
+ {
+ /* Send dummy data in order to generate the clock for the Slave to send the next data.
+ When FIFO mode is disabled only one data must be transferred.
+ When FIFO mode is enabled data must be transmitted until the RX FIFO reaches its threshold.
+ */
+ if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess))
+ {
+ for (nb_dummy_data = husart->NbRxDataToProcess ; nb_dummy_data > 0U ; nb_dummy_data--)
+ {
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
+ }
+ }
+ else
+ {
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
+ }
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Full-Duplex Send and Receive an amount of data in interrupt mode.
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
+ * of u16 available through pTxData and through pRxData.
+ * @param husart USART handle.
+ * @param pTxData pointer to TX data buffer (u8 or u16 data elements).
+ * @param pRxData pointer to RX data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be sent (same amount to be received).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size)
+{
+
+ if (husart->State == HAL_USART_STATE_READY)
+ {
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pRxBuffPtr = pRxData;
+ husart->RxXferSize = Size;
+ husart->RxXferCount = Size;
+ husart->pTxBuffPtr = pTxData;
+ husart->TxXferSize = Size;
+ husart->TxXferCount = Size;
+
+ /* Computation of USART mask to apply to RDR register */
+ USART_MASK_COMPUTATION(husart);
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_TX_RX;
+
+ /* Configure TxRx interrupt processing */
+ if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess))
+ {
+ /* Set the Rx ISR function pointer according to the data word length */
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ husart->TxISR = USART_TxISR_16BIT_FIFOEN;
+ husart->RxISR = USART_RxISR_16BIT_FIFOEN;
+ }
+ else
+ {
+ husart->TxISR = USART_TxISR_8BIT_FIFOEN;
+ husart->RxISR = USART_RxISR_8BIT_FIFOEN;
+ }
+
+ /* Process Locked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the USART Parity Error interrupt */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+
+ /* Enable the TX and RX FIFO Threshold interrupts */
+ SET_BIT(husart->Instance->CR3, (USART_CR3_TXFTIE | USART_CR3_RXFTIE));
+ }
+ else
+ {
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ husart->TxISR = USART_TxISR_16BIT;
+ husart->RxISR = USART_RxISR_16BIT;
+ }
+ else
+ {
+ husart->TxISR = USART_TxISR_8BIT;
+ husart->RxISR = USART_RxISR_8BIT;
+ }
+
+ /* Process Locked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the USART Parity Error and USART Data Register not empty Interrupts */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+
+ /* Enable the USART Transmit Data Register Empty Interrupt */
+ SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in DMA mode.
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pTxData.
+ * @param husart USART handle.
+ * @param pTxData pointer to data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be sent.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t *tmp;
+ uint16_t nbByte = Size;
+
+ if (husart->State == HAL_USART_STATE_READY)
+ {
+ if ((pTxData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pTxBuffPtr = pTxData;
+ husart->TxXferSize = Size;
+ husart->TxXferCount = Size;
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_TX;
+
+ if (husart->hdmatx != NULL)
+ {
+ /* Set the USART DMA transfer complete callback */
+ husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
+
+ /* Set the USART DMA Half transfer complete callback */
+ husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
+
+ /* Set the DMA error callback */
+ husart->hdmatx->XferErrorCallback = USART_DMAError;
+
+ /* In case of 9bits/No Parity transfer, pTxData buffer provided as input parameter
+ should be aligned on a u16 frontier, so nbByte should be equal to Size multiplied by 2 */
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ nbByte = Size * 2U;
+ }
+
+ tmp = (uint32_t *)&pTxData;
+
+ /* Check linked list mode */
+ if ((husart->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if ((husart->hdmatx->LinkedListQueue != NULL) && (husart->hdmatx->LinkedListQueue->Head != NULL))
+ {
+ /* Set DMA data size */
+ husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte;
+
+ /* Set DMA source address */
+ husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = *(uint32_t *)tmp;
+
+ /* Set DMA destination address */
+ husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
+ (uint32_t)&husart->Instance->TDR;
+
+ /* Enable the USART transmit DMA channel */
+ status = HAL_DMAEx_List_Start_IT(husart->hdmatx);
+ }
+ else
+ {
+ /* Update status */
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Enable the USART transmit DMA channel */
+ status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, nbByte);
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Clear the TC flag in the ICR register */
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the USART CR3 register */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Set error code to DMA */
+ husart->ErrorCode = HAL_USART_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Restore husart->State to ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in DMA mode.
+ * @note When the USART parity is enabled (PCE = 1), the received data contain
+ * the parity bit (MSB position).
+ * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave.
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pRxData.
+ * @param husart USART handle.
+ * @param pRxData pointer to data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t *tmp = (uint32_t *)&pRxData;
+ uint16_t nbByte = Size;
+
+ /* Check that a Rx process is not already ongoing */
+ if (husart->State == HAL_USART_STATE_READY)
+ {
+ if ((pRxData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pRxBuffPtr = pRxData;
+ husart->RxXferSize = Size;
+ husart->pTxBuffPtr = pRxData;
+ husart->TxXferSize = Size;
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_RX;
+
+ if (husart->hdmarx != NULL)
+ {
+ /* Set the USART DMA Rx transfer complete callback */
+ husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
+
+ /* Set the USART DMA Half transfer complete callback */
+ husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
+
+ /* Set the USART DMA Rx transfer error callback */
+ husart->hdmarx->XferErrorCallback = USART_DMAError;
+
+ /* In case of 9bits/No Parity transfer, pTxData buffer provided as input parameter
+ should be aligned on a u16 frontier, so nbByte should be equal to Size multiplied by 2 */
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ nbByte = Size * 2U;
+ }
+
+ /* Check linked list mode */
+ if ((husart->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if ((husart->hdmarx->LinkedListQueue != NULL) && (husart->hdmarx->LinkedListQueue->Head != NULL))
+ {
+ /* Set DMA data size */
+ husart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte;
+
+ /* Set DMA source address */
+ husart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
+ (uint32_t)&husart->Instance->RDR;
+
+ /* Set DMA destination address */
+ husart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = *(uint32_t *)tmp;
+
+ /* Enable the USART receive DMA channel */
+ status = HAL_DMAEx_List_Start_IT(husart->hdmarx);
+ }
+ else
+ {
+ /* Update status */
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Enable the USART receive DMA channel */
+ status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t *)tmp, nbByte);
+ }
+ }
+
+ if ((status == HAL_OK) &&
+ (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
+ {
+ /* Enable the USART transmit DMA channel: the transmit channel is used in order
+ to generate in the non-blocking mode the clock to the slave device,
+ this mode isn't a simplex receive mode but a full-duplex receive mode */
+
+ /* Set the USART DMA Tx Complete and Error callback to Null */
+ if (husart->hdmatx != NULL)
+ {
+ husart->hdmatx->XferErrorCallback = NULL;
+ husart->hdmatx->XferHalfCpltCallback = NULL;
+ husart->hdmatx->XferCpltCallback = NULL;
+
+ /* Check linked list mode */
+ if ((husart->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if ((husart->hdmatx->LinkedListQueue != NULL) && (husart->hdmatx->LinkedListQueue->Head != NULL))
+ {
+ /* Set DMA data size */
+ husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte;
+
+ /* Set DMA source address */
+ husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = *(uint32_t *)tmp;
+
+ /* Set DMA destination address */
+ husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
+ (uint32_t)&husart->Instance->TDR;
+
+ /* Enable the USART transmit DMA channel */
+ status = HAL_DMAEx_List_Start_IT(husart->hdmatx);
+ }
+ else
+ {
+ /* Update status */
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, nbByte);
+ }
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the USART Parity Error Interrupt */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the USART CR3 register */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the USART CR3 register */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ if ((husart->hdmarx != NULL) && ((husart->hdmarx->Mode & DMA_LINKEDLIST) != DMA_LINKEDLIST))
+ {
+ status = HAL_DMA_Abort(husart->hdmarx);
+ }
+
+ /* No need to check on error code */
+ UNUSED(status);
+
+ /* Set error code to DMA */
+ husart->ErrorCode = HAL_USART_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Restore husart->State to ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
+ * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
+ * of u16 available through pTxData and through pRxData.
+ * @param husart USART handle.
+ * @param pTxData pointer to TX data buffer (u8 or u16 data elements).
+ * @param pRxData pointer to RX data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be received/sent.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size)
+{
+ HAL_StatusTypeDef status;
+ uint32_t *tmp;
+ uint16_t nbByte = Size;
+
+ if (husart->State == HAL_USART_STATE_READY)
+ {
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pRxBuffPtr = pRxData;
+ husart->RxXferSize = Size;
+ husart->pTxBuffPtr = pTxData;
+ husart->TxXferSize = Size;
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_TX_RX;
+
+ if ((husart->hdmarx != NULL) && (husart->hdmatx != NULL))
+ {
+ /* Set the USART DMA Rx transfer complete callback */
+ husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
+
+ /* Set the USART DMA Half transfer complete callback */
+ husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
+
+ /* Set the USART DMA Tx transfer complete callback */
+ husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
+
+ /* Set the USART DMA Half transfer complete callback */
+ husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
+
+ /* Set the USART DMA Tx transfer error callback */
+ husart->hdmatx->XferErrorCallback = USART_DMAError;
+
+ /* Set the USART DMA Rx transfer error callback */
+ husart->hdmarx->XferErrorCallback = USART_DMAError;
+
+ /* In case of 9bits/No Parity transfer, pTxData buffer provided as input parameter
+ should be aligned on a u16 frontier, so nbByte should be equal to Size multiplied by 2 */
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ nbByte = Size * 2U;
+ }
+
+ /* Check linked list mode */
+ tmp = (uint32_t *)&pRxData;
+ if ((husart->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if ((husart->hdmarx->LinkedListQueue != NULL) && (husart->hdmarx->LinkedListQueue->Head != NULL))
+ {
+ /* Set DMA data size */
+ husart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte;
+
+ /* Set DMA source address */
+ husart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
+ (uint32_t)&husart->Instance->RDR;
+
+ /* Set DMA destination address */
+ husart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = *(uint32_t *)tmp;
+
+ /* Enable the USART receive DMA channel */
+ status = HAL_DMAEx_List_Start_IT(husart->hdmarx);
+ }
+ else
+ {
+ /* Update status */
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Enable the USART receive DMA channel */
+ status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t *)tmp, nbByte);
+ }
+
+ /* Enable the USART transmit DMA channel */
+ if (status == HAL_OK)
+ {
+ tmp = (uint32_t *)&pTxData;
+
+ /* Check linked list mode */
+ if ((husart->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if ((husart->hdmatx->LinkedListQueue != NULL) && (husart->hdmatx->LinkedListQueue->Head != NULL))
+ {
+ /* Set DMA data size */
+ husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte;
+
+ /* Set DMA source address */
+ husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = *(uint32_t *)tmp;
+
+ /* Set DMA destination address */
+ husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
+ (uint32_t)&husart->Instance->TDR;
+
+ /* Enable the USART transmit DMA channel */
+ status = HAL_DMAEx_List_Start_IT(husart->hdmatx);
+ }
+ else
+ {
+ /* Update status */
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, nbByte);
+ }
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the USART Parity Error Interrupt */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Clear the TC flag in the ICR register */
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the USART CR3 register */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the USART CR3 register */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ if ((husart->hdmarx != NULL) && ((husart->hdmarx->Mode & DMA_LINKEDLIST) != DMA_LINKEDLIST))
+ {
+ status = HAL_DMA_Abort(husart->hdmarx);
+ }
+
+ /* No need to check on error code */
+ UNUSED(status);
+
+ /* Set error code to DMA */
+ husart->ErrorCode = HAL_USART_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Restore husart->State to ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Pause the DMA Transfer.
+ * @param husart USART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
+{
+ const HAL_USART_StateTypeDef state = husart->State;
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ if ((HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) &&
+ (state == HAL_USART_STATE_BUSY_TX))
+ {
+ /* Disable the USART DMA Tx request */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+ }
+ else if ((state == HAL_USART_STATE_BUSY_RX) ||
+ (state == HAL_USART_STATE_BUSY_TX_RX))
+ {
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable the USART DMA Tx request */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+ }
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+ {
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the USART DMA Rx request */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resume the DMA Transfer.
+ * @param husart USART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
+{
+ const HAL_USART_StateTypeDef state = husart->State;
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ if (state == HAL_USART_STATE_BUSY_TX)
+ {
+ /* Enable the USART DMA Tx request */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+ }
+ else if ((state == HAL_USART_STATE_BUSY_RX) ||
+ (state == HAL_USART_STATE_BUSY_TX_RX))
+ {
+ /* Clear the Overrun flag before resuming the Rx transfer*/
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF);
+
+ /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the USART DMA Rx request before the DMA Tx request */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Enable the USART DMA Tx request */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the DMA Transfer.
+ * @param husart USART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
+{
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() /
+ HAL_USART_TxHalfCpltCallback / HAL_USART_RxHalfCpltCallback:
+ indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
+ interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
+ the stream and the corresponding call back is executed. */
+
+ /* Disable the USART Tx/Rx DMA requests */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the USART DMA tx channel */
+ if (husart->hdmatx != NULL)
+ {
+ if (HAL_DMA_Abort(husart->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ husart->ErrorCode = HAL_USART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Abort the USART DMA rx channel */
+ if (husart->hdmarx != NULL)
+ {
+ if (HAL_DMA_Abort(husart->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ husart->ErrorCode = HAL_USART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ USART_EndTransfer(husart);
+ husart->State = HAL_USART_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (blocking mode).
+ * @param husart USART handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable USART Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart)
+{
+ /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE |
+ USART_CR1_TCIE));
+ CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
+
+ /* Disable the USART DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if (husart->hdmatx != NULL)
+ {
+ /* Set the USART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ husart->hdmatx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(husart->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ husart->ErrorCode = HAL_USART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Disable the USART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if (husart->hdmarx != NULL)
+ {
+ /* Set the USART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ husart->hdmarx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(husart->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ husart->ErrorCode = HAL_USART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Reset Tx and Rx transfer counters */
+ husart->TxXferCount = 0U;
+ husart->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
+
+ /* Flush the whole TX FIFO (if needed) */
+ if (husart->FifoMode == USART_FIFOMODE_ENABLE)
+ {
+ __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
+ }
+
+ /* Discard the received data */
+ __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
+
+ /* Restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Reset Handle ErrorCode to No Error */
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (Interrupt mode).
+ * @param husart USART handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable USART Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
+{
+ uint32_t abortcplt = 1U;
+
+ /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE |
+ USART_CR1_TCIE));
+ CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
+
+ /* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised
+ before any call to DMA Abort functions */
+ /* DMA Tx Handle is valid */
+ if (husart->hdmatx != NULL)
+ {
+ /* Set DMA Abort Complete callback if USART DMA Tx request if enabled.
+ Otherwise, set it to NULL */
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+ {
+ husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback;
+ }
+ else
+ {
+ husart->hdmatx->XferAbortCallback = NULL;
+ }
+ }
+ /* DMA Rx Handle is valid */
+ if (husart->hdmarx != NULL)
+ {
+ /* Set DMA Abort Complete callback if USART DMA Rx request if enabled.
+ Otherwise, set it to NULL */
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+ {
+ husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback;
+ }
+ else
+ {
+ husart->hdmarx->XferAbortCallback = NULL;
+ }
+ }
+
+ /* Disable the USART DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable DMA Tx at USART level */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if (husart->hdmatx != NULL)
+ {
+ /* USART Tx DMA Abort callback has already been initialised :
+ will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK)
+ {
+ husart->hdmatx->XferAbortCallback = NULL;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* Disable the USART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if (husart->hdmarx != NULL)
+ {
+ /* USART Rx DMA Abort callback has already been initialised :
+ will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
+ {
+ husart->hdmarx->XferAbortCallback = NULL;
+ abortcplt = 1U;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+ if (abortcplt == 1U)
+ {
+ /* Reset Tx and Rx transfer counters */
+ husart->TxXferCount = 0U;
+ husart->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
+
+ /* Flush the whole TX FIFO (if needed) */
+ if (husart->FifoMode == USART_FIFOMODE_ENABLE)
+ {
+ __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
+ }
+
+ /* Discard the received data */
+ __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
+
+ /* Restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Complete Callback */
+ husart->AbortCpltCallback(husart);
+#else
+ /* Call legacy weak Abort Complete Callback */
+ HAL_USART_AbortCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle USART interrupt request.
+ * @param husart USART handle.
+ * @retval None
+ */
+void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
+{
+ uint32_t isrflags = READ_REG(husart->Instance->ISR);
+ uint32_t cr1its = READ_REG(husart->Instance->CR1);
+ uint32_t cr3its = READ_REG(husart->Instance->CR3);
+
+ uint32_t errorflags;
+ uint32_t errorcode;
+
+ /* If no error occurs */
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF |
+ USART_ISR_UDR));
+ if (errorflags == 0U)
+ {
+ /* USART in mode Receiver ---------------------------------------------------*/
+ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
+ && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+ || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+ {
+ if (husart->RxISR != NULL)
+ {
+ husart->RxISR(husart);
+ }
+ return;
+ }
+ }
+
+ /* If some errors occur */
+ if ((errorflags != 0U)
+ && (((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
+ || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U)))
+ {
+ /* USART parity error interrupt occurred -------------------------------------*/
+ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+ {
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF);
+
+ husart->ErrorCode |= HAL_USART_ERROR_PE;
+ }
+
+ /* USART frame error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF);
+
+ husart->ErrorCode |= HAL_USART_ERROR_FE;
+ }
+
+ /* USART noise error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF);
+
+ husart->ErrorCode |= HAL_USART_ERROR_NE;
+ }
+
+ /* USART Over-Run interrupt occurred -----------------------------------------*/
+ if (((isrflags & USART_ISR_ORE) != 0U)
+ && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
+ ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))
+ {
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);
+
+ husart->ErrorCode |= HAL_USART_ERROR_ORE;
+ }
+
+ /* USART Receiver Timeout interrupt occurred ---------------------------------*/
+ if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
+ {
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_RTOF);
+
+ husart->ErrorCode |= HAL_USART_ERROR_RTO;
+ }
+
+ /* USART SPI slave underrun error interrupt occurred -------------------------*/
+ if (((isrflags & USART_ISR_UDR) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ /* Ignore SPI slave underrun errors when reception is going on */
+ if (husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+ __HAL_USART_CLEAR_UDRFLAG(husart);
+ return;
+ }
+ else
+ {
+ __HAL_USART_CLEAR_UDRFLAG(husart);
+ husart->ErrorCode |= HAL_USART_ERROR_UDR;
+ }
+ }
+
+ /* Call USART Error Call back function if need be --------------------------*/
+ if (husart->ErrorCode != HAL_USART_ERROR_NONE)
+ {
+ /* USART in mode Receiver ---------------------------------------------------*/
+ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
+ && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+ || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+ {
+ if (husart->RxISR != NULL)
+ {
+ husart->RxISR(husart);
+ }
+ }
+
+ /* If Overrun error occurs, or if any error occurs in DMA mode reception,
+ consider error as blocking */
+ errorcode = husart->ErrorCode & HAL_USART_ERROR_ORE;
+ if ((HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) ||
+ (errorcode != 0U))
+ {
+ /* Blocking error : transfer is aborted
+ Set the USART state ready to be able to start again the process,
+ Disable Interrupts, and disable DMA requests, if ongoing */
+ USART_EndTransfer(husart);
+
+ /* Disable the USART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR);
+
+ /* Abort the USART DMA Tx channel */
+ if (husart->hdmatx != NULL)
+ {
+ /* Set the USART Tx DMA Abort callback to NULL : no callback
+ executed at end of DMA abort procedure */
+ husart->hdmatx->XferAbortCallback = NULL;
+
+ /* Abort DMA TX */
+ (void)HAL_DMA_Abort_IT(husart->hdmatx);
+ }
+
+ /* Abort the USART DMA Rx channel */
+ if (husart->hdmarx != NULL)
+ {
+ /* Set the USART Rx DMA Abort callback :
+ will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */
+ husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError;
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
+ {
+ /* Call Directly husart->hdmarx->XferAbortCallback function in case of error */
+ husart->hdmarx->XferAbortCallback(husart->hdmarx);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Error Callback */
+ husart->ErrorCallback(husart);
+#else
+ /* Call legacy weak Error Callback */
+ HAL_USART_ErrorCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Error Callback */
+ husart->ErrorCallback(husart);
+#else
+ /* Call legacy weak Error Callback */
+ HAL_USART_ErrorCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ }
+ else
+ {
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Error Callback */
+ husart->ErrorCallback(husart);
+#else
+ /* Call legacy weak Error Callback */
+ HAL_USART_ErrorCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ }
+ }
+ return;
+
+ } /* End if some error occurs */
+
+
+ /* USART in mode Transmitter ------------------------------------------------*/
+ if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
+ && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
+ || ((cr3its & USART_CR3_TXFTIE) != 0U)))
+ {
+ if (husart->TxISR != NULL)
+ {
+ husart->TxISR(husart);
+ }
+ return;
+ }
+
+ /* USART in mode Transmitter (transmission end) -----------------------------*/
+ if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
+ {
+ USART_EndTransmit_IT(husart);
+ return;
+ }
+
+ /* USART TX Fifo Empty occurred ----------------------------------------------*/
+ if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
+ {
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Fifo Empty Callback */
+ husart->TxFifoEmptyCallback(husart);
+#else
+ /* Call legacy weak Tx Fifo Empty Callback */
+ HAL_USARTEx_TxFifoEmptyCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ return;
+ }
+
+ /* USART RX Fifo Full occurred ----------------------------------------------*/
+ if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
+ {
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx Fifo Full Callback */
+ husart->RxFifoFullCallback(husart);
+#else
+ /* Call legacy weak Rx Fifo Full Callback */
+ HAL_USARTEx_RxFifoFullCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ return;
+ }
+}
+
+/**
+ * @brief Tx Transfer completed callback.
+ * @param husart USART handle.
+ * @retval None
+ */
+__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USART_TxCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Tx Half Transfer completed callback.
+ * @param husart USART handle.
+ * @retval None
+ */
+__weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_USART_TxHalfCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callback.
+ * @param husart USART handle.
+ * @retval None
+ */
+__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_USART_RxCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Rx Half Transfer completed callback.
+ * @param husart USART handle.
+ * @retval None
+ */
+__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USART_RxHalfCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx/Rx Transfers completed callback for the non-blocking process.
+ * @param husart USART handle.
+ * @retval None
+ */
+__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USART_TxRxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief USART error callback.
+ * @param husart USART handle.
+ * @retval None
+ */
+__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USART_ErrorCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief USART Abort Complete callback.
+ * @param husart USART handle.
+ * @retval None
+ */
+__weak void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USART_AbortCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Exported_Functions_Group4 Peripheral State and Error functions
+ * @brief USART Peripheral State and Error functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Error functions #####
+ ==============================================================================
+ [..]
+ This subsection provides functions allowing to :
+ (+) Return the USART handle state
+ (+) Return the USART handle error code
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Return the USART handle state.
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART.
+ * @retval USART handle state
+ */
+HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
+{
+ return husart->State;
+}
+
+/**
+ * @brief Return the USART error code.
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART.
+ * @retval USART handle Error Code
+ */
+uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
+{
+ return husart->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Private_Functions USART Private Functions
+ * @{
+ */
+
+/**
+ * @brief Initialize the callbacks to their default values.
+ * @param husart USART handle.
+ * @retval none
+ */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart)
+{
+ /* Init the USART Callback settings */
+ husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
+ husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */
+ husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ husart->RxFifoFullCallback = HAL_USARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
+ husart->TxFifoEmptyCallback = HAL_USARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
+}
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+
+/**
+ * @brief End ongoing transfer on USART peripheral (following error detection or Transfer completion).
+ * @param husart USART handle.
+ * @retval None
+ */
+static void USART_EndTransfer(USART_HandleTypeDef *husart)
+{
+ /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE |
+ USART_CR1_TCIE));
+ CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
+
+ /* At end of process, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+}
+
+/**
+ * @brief DMA USART transmit process complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
+
+ /* Check if DMA in circular mode */
+ if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR)
+ {
+ husart->TxXferCount = 0U;
+
+ if (husart->State == HAL_USART_STATE_BUSY_TX)
+ {
+ /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+ in the USART CR3 register */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Enable the USART Transmit Complete Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
+ }
+ }
+ /* DMA Circular mode */
+ else
+ {
+ if (husart->State == HAL_USART_STATE_BUSY_TX)
+ {
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Complete Callback */
+ husart->TxCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Complete Callback */
+ HAL_USART_TxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ }
+}
+
+/**
+ * @brief DMA USART transmit process half complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Half Complete Callback */
+ husart->TxHalfCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Half Complete Callback */
+ HAL_USART_TxHalfCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA USART receive process complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
+
+ /* Check if DMA in circular mode*/
+ if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR)
+ {
+ husart->RxXferCount = 0U;
+
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit
+ in USART CR3 register */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+ /* similarly, disable the DMA TX transfer that was started to provide the
+ clock to the slave device */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ if (husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx Complete Callback */
+ husart->RxCpltCallback(husart);
+#else
+ /* Call legacy weak Rx Complete Callback */
+ HAL_USART_RxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
+ else
+ {
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Rx Complete Callback */
+ husart->TxRxCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Rx Complete Callback */
+ HAL_USART_TxRxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ husart->State = HAL_USART_STATE_READY;
+ }
+ /* DMA circular mode */
+ else
+ {
+ if (husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx Complete Callback */
+ husart->RxCpltCallback(husart);
+#else
+ /* Call legacy weak Rx Complete Callback */
+ HAL_USART_RxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
+ else
+ {
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Rx Complete Callback */
+ husart->TxRxCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Rx Complete Callback */
+ HAL_USART_TxRxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ }
+}
+
+/**
+ * @brief DMA USART receive process half complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx Half Complete Callback */
+ husart->RxHalfCpltCallback(husart);
+#else
+ /* Call legacy weak Rx Half Complete Callback */
+ HAL_USART_RxHalfCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA USART communication error callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void USART_DMAError(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
+
+ husart->RxXferCount = 0U;
+ husart->TxXferCount = 0U;
+ USART_EndTransfer(husart);
+
+ husart->ErrorCode |= HAL_USART_ERROR_DMA;
+ husart->State = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Error Callback */
+ husart->ErrorCallback(husart);
+#else
+ /* Call legacy weak Error Callback */
+ HAL_USART_ErrorCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA USART communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
+ husart->RxXferCount = 0U;
+ husart->TxXferCount = 0U;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Error Callback */
+ husart->ErrorCallback(husart);
+#else
+ /* Call legacy weak Error Callback */
+ HAL_USART_ErrorCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA USART Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
+
+ husart->hdmatx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if (husart->hdmarx != NULL)
+ {
+ if (husart->hdmarx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ husart->TxXferCount = 0U;
+ husart->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
+
+ /* Restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Complete Callback */
+ husart->AbortCpltCallback(husart);
+#else
+ /* Call legacy weak Abort Complete Callback */
+ HAL_USART_AbortCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+
+}
+
+
+/**
+ * @brief DMA USART Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
+
+ husart->hdmarx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if (husart->hdmatx != NULL)
+ {
+ if (husart->hdmatx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ husart->TxXferCount = 0U;
+ husart->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
+
+ /* Restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Complete Callback */
+ husart->AbortCpltCallback(husart);
+#else
+ /* Call legacy weak Abort Complete Callback */
+ HAL_USART_AbortCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+}
+
+
+/**
+ * @brief Handle USART Communication Timeout.
+ * @param husart USART handle.
+ * @param Flag Specifies the USART flag to check.
+ * @param Status the Flag status (SET or RESET).
+ * @param Tickstart Tick start value
+ * @param Timeout timeout duration.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status,
+ uint32_t Tickstart, uint32_t Timeout)
+{
+ /* Wait until flag is set */
+ while ((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+ {
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the USART peripheral.
+ * @param husart USART handle.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
+{
+ uint32_t tmpreg;
+ USART_ClockSourceTypeDef clocksource;
+ HAL_StatusTypeDef ret = HAL_OK;
+ uint16_t brrtemp;
+ uint32_t usartdiv = 0x00000000;
+ uint32_t pclk;
+
+ /* Check the parameters */
+ assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
+ assert_param(IS_USART_PHASE(husart->Init.CLKPhase));
+ assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit));
+ assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));
+ assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength));
+ assert_param(IS_USART_STOPBITS(husart->Init.StopBits));
+ assert_param(IS_USART_PARITY(husart->Init.Parity));
+ assert_param(IS_USART_MODE(husart->Init.Mode));
+ assert_param(IS_USART_PRESCALER(husart->Init.ClockPrescaler));
+
+ /*-------------------------- USART CR1 Configuration -----------------------*/
+ /* Clear M, PCE, PS, TE and RE bits and configure
+ * the USART Word Length, Parity and Mode:
+ * set the M bits according to husart->Init.WordLength value
+ * set PCE and PS bits according to husart->Init.Parity value
+ * set TE and RE bits according to husart->Init.Mode value
+ * force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */
+ tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8;
+ MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+
+ /*---------------------------- USART CR2 Configuration ---------------------*/
+ /* Clear and configure the USART Clock, CPOL, CPHA, LBCL STOP and SLVEN bits:
+ * set CPOL bit according to husart->Init.CLKPolarity value
+ * set CPHA bit according to husart->Init.CLKPhase value
+ * set LBCL bit according to husart->Init.CLKLastBit value (used in SPI master mode only)
+ * set STOP[13:12] bits according to husart->Init.StopBits value */
+ tmpreg = (uint32_t)(USART_CLOCK_ENABLE);
+ tmpreg |= (uint32_t)husart->Init.CLKLastBit;
+ tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase);
+ tmpreg |= (uint32_t)husart->Init.StopBits;
+ MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg);
+
+ /*-------------------------- USART PRESC Configuration -----------------------*/
+ /* Configure
+ * - USART Clock Prescaler : set PRESCALER according to husart->Init.ClockPrescaler value */
+ MODIFY_REG(husart->Instance->PRESC, USART_PRESC_PRESCALER, husart->Init.ClockPrescaler);
+
+ /*-------------------------- USART BRR Configuration -----------------------*/
+ /* BRR is filled-up according to OVER8 bit setting which is forced to 1 */
+ USART_GETCLOCKSOURCE(husart, clocksource);
+
+ switch (clocksource)
+ {
+ case USART_CLOCKSOURCE_PCLK1:
+ pclk = HAL_RCC_GetPCLK1Freq();
+ usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler));
+ break;
+ case USART_CLOCKSOURCE_PCLK2:
+ pclk = HAL_RCC_GetPCLK2Freq();
+ usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler));
+ break;
+ case USART_CLOCKSOURCE_HSI:
+ usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HSI_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler));
+ break;
+ case USART_CLOCKSOURCE_SYSCLK:
+ pclk = HAL_RCC_GetSysClockFreq();
+ usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler));
+ break;
+ case USART_CLOCKSOURCE_LSE:
+ usartdiv = (uint32_t)(USART_DIV_SAMPLING8(LSE_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler));
+ break;
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+
+ /* USARTDIV must be greater than or equal to 0d16 and smaller than or equal to ffff */
+ if ((usartdiv >= USART_BRR_MIN) && (usartdiv <= USART_BRR_MAX))
+ {
+ brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
+ brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+ husart->Instance->BRR = brrtemp;
+ }
+ else
+ {
+ ret = HAL_ERROR;
+ }
+
+ /* Initialize the number of data to process during RX/TX ISR execution */
+ husart->NbTxDataToProcess = 1U;
+ husart->NbRxDataToProcess = 1U;
+
+ /* Clear ISR function pointers */
+ husart->RxISR = NULL;
+ husart->TxISR = NULL;
+
+ return ret;
+}
+
+/**
+ * @brief Check the USART Idle State.
+ * @param husart USART handle.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart)
+{
+ uint32_t tickstart;
+
+ /* Initialize the USART ErrorCode */
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ /* Check if the Transmitter is enabled */
+ if ((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ {
+ /* Wait until TEACK flag is set */
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Check if the Receiver is enabled */
+ if ((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+ {
+ /* Wait until REACK flag is set */
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Initialize the USART state*/
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Simplex send an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_USART_Transmit_IT().
+ * @note The USART errors are not managed to avoid the overrun error.
+ * @note ISR function executed when FIFO mode is disabled and when the
+ * data word length is less than 9 bits long.
+ * @param husart USART handle.
+ * @retval None
+ */
+static void USART_TxISR_8BIT(USART_HandleTypeDef *husart)
+{
+ const HAL_USART_StateTypeDef state = husart->State;
+
+ /* Check that a Tx process is ongoing */
+ if ((state == HAL_USART_STATE_BUSY_TX) ||
+ (state == HAL_USART_STATE_BUSY_TX_RX))
+ {
+ if (husart->TxXferCount == 0U)
+ {
+ /* Disable the USART Transmit data register empty interrupt */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
+
+ /* Enable the USART Transmit Complete Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
+ }
+ else
+ {
+ husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr & (uint8_t)0xFF);
+ husart->pTxBuffPtr++;
+ husart->TxXferCount--;
+ }
+ }
+}
+
+/**
+ * @brief Simplex send an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_USART_Transmit_IT().
+ * @note The USART errors are not managed to avoid the overrun error.
+ * @note ISR function executed when FIFO mode is disabled and when the
+ * data word length is 9 bits long.
+ * @param husart USART handle.
+ * @retval None
+ */
+static void USART_TxISR_16BIT(USART_HandleTypeDef *husart)
+{
+ const HAL_USART_StateTypeDef state = husart->State;
+ uint16_t *tmp;
+
+ if ((state == HAL_USART_STATE_BUSY_TX) ||
+ (state == HAL_USART_STATE_BUSY_TX_RX))
+ {
+ if (husart->TxXferCount == 0U)
+ {
+ /* Disable the USART Transmit data register empty interrupt */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
+
+ /* Enable the USART Transmit Complete Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
+ }
+ else
+ {
+ tmp = (uint16_t *) husart->pTxBuffPtr;
+ husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU);
+ husart->pTxBuffPtr += 2U;
+ husart->TxXferCount--;
+ }
+ }
+}
+
+/**
+ * @brief Simplex send an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_USART_Transmit_IT().
+ * @note The USART errors are not managed to avoid the overrun error.
+ * @note ISR function executed when FIFO mode is enabled and when the
+ * data word length is less than 9 bits long.
+ * @param husart USART handle.
+ * @retval None
+ */
+static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart)
+{
+ const HAL_USART_StateTypeDef state = husart->State;
+ uint16_t nb_tx_data;
+
+ /* Check that a Tx process is ongoing */
+ if ((state == HAL_USART_STATE_BUSY_TX) ||
+ (state == HAL_USART_STATE_BUSY_TX_RX))
+ {
+ for (nb_tx_data = husart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
+ {
+ if (husart->TxXferCount == 0U)
+ {
+ /* Disable the TX FIFO threshold interrupt */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXFT);
+
+ /* Enable the USART Transmit Complete Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
+
+ break; /* force exit loop */
+ }
+ else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET)
+ {
+ husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr & (uint8_t)0xFF);
+ husart->pTxBuffPtr++;
+ husart->TxXferCount--;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ }
+}
+
+/**
+ * @brief Simplex send an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_USART_Transmit_IT().
+ * @note The USART errors are not managed to avoid the overrun error.
+ * @note ISR function executed when FIFO mode is enabled and when the
+ * data word length is 9 bits long.
+ * @param husart USART handle.
+ * @retval None
+ */
+static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart)
+{
+ const HAL_USART_StateTypeDef state = husart->State;
+ uint16_t *tmp;
+ uint16_t nb_tx_data;
+
+ /* Check that a Tx process is ongoing */
+ if ((state == HAL_USART_STATE_BUSY_TX) ||
+ (state == HAL_USART_STATE_BUSY_TX_RX))
+ {
+ for (nb_tx_data = husart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
+ {
+ if (husart->TxXferCount == 0U)
+ {
+ /* Disable the TX FIFO threshold interrupt */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXFT);
+
+ /* Enable the USART Transmit Complete Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
+
+ break; /* force exit loop */
+ }
+ else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET)
+ {
+ tmp = (uint16_t *) husart->pTxBuffPtr;
+ husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU);
+ husart->pTxBuffPtr += 2U;
+ husart->TxXferCount--;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ }
+}
+
+/**
+ * @brief Wraps up transmission in non-blocking mode.
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval None
+ */
+static void USART_EndTransmit_IT(USART_HandleTypeDef *husart)
+{
+ /* Disable the USART Transmit Complete Interrupt */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TC);
+
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
+
+ /* Clear TxISR function pointer */
+ husart->TxISR = NULL;
+
+ if (husart->State == HAL_USART_STATE_BUSY_TX)
+ {
+ /* Clear overrun flag and discard the received data */
+ __HAL_USART_CLEAR_OREFLAG(husart);
+ __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
+
+ /* Tx process is completed, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Complete Callback */
+ husart->TxCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Complete Callback */
+ HAL_USART_TxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ else if (husart->RxXferCount == 0U)
+ {
+ /* TxRx process is completed, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Rx Complete Callback */
+ husart->TxRxCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Rx Complete Callback */
+ HAL_USART_TxRxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+}
+
+
+/**
+ * @brief Simplex receive an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_USART_Receive_IT().
+ * @note ISR function executed when FIFO mode is disabled and when the
+ * data word length is less than 9 bits long.
+ * @param husart USART handle
+ * @retval None
+ */
+static void USART_RxISR_8BIT(USART_HandleTypeDef *husart)
+{
+ const HAL_USART_StateTypeDef state = husart->State;
+ uint16_t txdatacount;
+ uint16_t uhMask = husart->Mask;
+ uint32_t txftie;
+
+ if ((state == HAL_USART_STATE_BUSY_RX) ||
+ (state == HAL_USART_STATE_BUSY_TX_RX))
+ {
+ *husart->pRxBuffPtr = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
+ husart->pRxBuffPtr++;
+ husart->RxXferCount--;
+
+ if (husart->RxXferCount == 0U)
+ {
+ /* Disable the USART Parity Error Interrupt and RXNE interrupt*/
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Clear RxISR function pointer */
+ husart->RxISR = NULL;
+
+ /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */
+ txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE);
+ txdatacount = husart->TxXferCount;
+
+ if (state == HAL_USART_STATE_BUSY_RX)
+ {
+ /* Clear SPI slave underrun flag and discard transmit data */
+ if (husart->SlaveMode == USART_SLAVEMODE_ENABLE)
+ {
+ __HAL_USART_CLEAR_UDRFLAG(husart);
+ __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
+ }
+
+ /* Rx process is completed, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx Complete Callback */
+ husart->RxCpltCallback(husart);
+#else
+ /* Call legacy weak Rx Complete Callback */
+ HAL_USART_RxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) &&
+ (txftie != USART_CR3_TXFTIE) &&
+ (txdatacount == 0U))
+ {
+ /* TxRx process is completed, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Rx Complete Callback */
+ husart->TxRxCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Rx Complete Callback */
+ HAL_USART_TxRxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ else if ((state == HAL_USART_STATE_BUSY_RX) &&
+ (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
+ {
+ /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+}
+
+/**
+ * @brief Simplex receive an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_USART_Receive_IT().
+ * @note ISR function executed when FIFO mode is disabled and when the
+ * data word length is 9 bits long.
+ * @param husart USART handle
+ * @retval None
+ */
+static void USART_RxISR_16BIT(USART_HandleTypeDef *husart)
+{
+ const HAL_USART_StateTypeDef state = husart->State;
+ uint16_t txdatacount;
+ uint16_t *tmp;
+ uint16_t uhMask = husart->Mask;
+ uint32_t txftie;
+
+ if ((state == HAL_USART_STATE_BUSY_RX) ||
+ (state == HAL_USART_STATE_BUSY_TX_RX))
+ {
+ tmp = (uint16_t *) husart->pRxBuffPtr;
+ *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
+ husart->pRxBuffPtr += 2U;
+ husart->RxXferCount--;
+
+ if (husart->RxXferCount == 0U)
+ {
+ /* Disable the USART Parity Error Interrupt and RXNE interrupt*/
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Clear RxISR function pointer */
+ husart->RxISR = NULL;
+
+ /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */
+ txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE);
+ txdatacount = husart->TxXferCount;
+
+ if (state == HAL_USART_STATE_BUSY_RX)
+ {
+ /* Clear SPI slave underrun flag and discard transmit data */
+ if (husart->SlaveMode == USART_SLAVEMODE_ENABLE)
+ {
+ __HAL_USART_CLEAR_UDRFLAG(husart);
+ __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
+ }
+
+ /* Rx process is completed, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx Complete Callback */
+ husart->RxCpltCallback(husart);
+#else
+ /* Call legacy weak Rx Complete Callback */
+ HAL_USART_RxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) &&
+ (txftie != USART_CR3_TXFTIE) &&
+ (txdatacount == 0U))
+ {
+ /* TxRx process is completed, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Rx Complete Callback */
+ husart->TxRxCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Rx Complete Callback */
+ HAL_USART_TxRxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ else if ((state == HAL_USART_STATE_BUSY_RX) &&
+ (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
+ {
+ /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+}
+
+/**
+ * @brief Simplex receive an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_USART_Receive_IT().
+ * @note ISR function executed when FIFO mode is enabled and when the
+ * data word length is less than 9 bits long.
+ * @param husart USART handle
+ * @retval None
+ */
+static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart)
+{
+ HAL_USART_StateTypeDef state = husart->State;
+ uint16_t txdatacount;
+ uint16_t rxdatacount;
+ uint16_t uhMask = husart->Mask;
+ uint16_t nb_rx_data;
+ uint32_t txftie;
+
+ /* Check that a Rx process is ongoing */
+ if ((state == HAL_USART_STATE_BUSY_RX) ||
+ (state == HAL_USART_STATE_BUSY_TX_RX))
+ {
+ for (nb_rx_data = husart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)
+ {
+ if (__HAL_USART_GET_FLAG(husart, USART_FLAG_RXFNE) == SET)
+ {
+ *husart->pRxBuffPtr = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU));
+ husart->pRxBuffPtr++;
+ husart->RxXferCount--;
+
+ if (husart->RxXferCount == 0U)
+ {
+ /* Disable the USART Parity Error Interrupt */
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error)
+ and RX FIFO Threshold interrupt */
+ CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+ /* Clear RxISR function pointer */
+ husart->RxISR = NULL;
+
+ /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */
+ txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE);
+ txdatacount = husart->TxXferCount;
+
+ if (state == HAL_USART_STATE_BUSY_RX)
+ {
+ /* Clear SPI slave underrun flag and discard transmit data */
+ if (husart->SlaveMode == USART_SLAVEMODE_ENABLE)
+ {
+ __HAL_USART_CLEAR_UDRFLAG(husart);
+ __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
+ }
+
+ /* Rx process is completed, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+ state = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx Complete Callback */
+ husart->RxCpltCallback(husart);
+#else
+ /* Call legacy weak Rx Complete Callback */
+ HAL_USART_RxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) &&
+ (txftie != USART_CR3_TXFTIE) &&
+ (txdatacount == 0U))
+ {
+ /* TxRx process is completed, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+ state = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Rx Complete Callback */
+ husart->TxRxCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Rx Complete Callback */
+ HAL_USART_TxRxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ else if ((state == HAL_USART_STATE_BUSY_RX) &&
+ (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
+ {
+ /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ }
+
+ /* When remaining number of bytes to receive is less than the RX FIFO
+ threshold, next incoming frames are processed as if FIFO mode was
+ disabled (i.e. one interrupt per received frame).
+ */
+ rxdatacount = husart->RxXferCount;
+ if (((rxdatacount != 0U)) && (rxdatacount < husart->NbRxDataToProcess))
+ {
+ /* Disable the USART RXFT interrupt*/
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_RXFTIE);
+
+ /* Update the RxISR function pointer */
+ husart->RxISR = USART_RxISR_8BIT;
+
+ /* Enable the USART Data Register Not Empty interrupt */
+ SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+
+ if ((husart->TxXferCount == 0U) &&
+ (state == HAL_USART_STATE_BUSY_TX_RX) &&
+ (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
+ {
+ /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
+ }
+ }
+ }
+ else
+ {
+ /* Clear RXNE interrupt flag */
+ __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
+ }
+}
+
+/**
+ * @brief Simplex receive an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_USART_Receive_IT().
+ * @note ISR function executed when FIFO mode is enabled and when the
+ * data word length is 9 bits long.
+ * @param husart USART handle
+ * @retval None
+ */
+static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart)
+{
+ HAL_USART_StateTypeDef state = husart->State;
+ uint16_t txdatacount;
+ uint16_t rxdatacount;
+ uint16_t *tmp;
+ uint16_t uhMask = husart->Mask;
+ uint16_t nb_rx_data;
+ uint32_t txftie;
+
+ /* Check that a Tx process is ongoing */
+ if ((state == HAL_USART_STATE_BUSY_RX) ||
+ (state == HAL_USART_STATE_BUSY_TX_RX))
+ {
+ for (nb_rx_data = husart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)
+ {
+ if (__HAL_USART_GET_FLAG(husart, USART_FLAG_RXFNE) == SET)
+ {
+ tmp = (uint16_t *) husart->pRxBuffPtr;
+ *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
+ husart->pRxBuffPtr += 2U;
+ husart->RxXferCount--;
+
+ if (husart->RxXferCount == 0U)
+ {
+ /* Disable the USART Parity Error Interrupt */
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error)
+ and RX FIFO Threshold interrupt */
+ CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+ /* Clear RxISR function pointer */
+ husart->RxISR = NULL;
+
+ /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */
+ txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE);
+ txdatacount = husart->TxXferCount;
+
+ if (state == HAL_USART_STATE_BUSY_RX)
+ {
+ /* Clear SPI slave underrun flag and discard transmit data */
+ if (husart->SlaveMode == USART_SLAVEMODE_ENABLE)
+ {
+ __HAL_USART_CLEAR_UDRFLAG(husart);
+ __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
+ }
+
+ /* Rx process is completed, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+ state = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx Complete Callback */
+ husart->RxCpltCallback(husart);
+#else
+ /* Call legacy weak Rx Complete Callback */
+ HAL_USART_RxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) &&
+ (txftie != USART_CR3_TXFTIE) &&
+ (txdatacount == 0U))
+ {
+ /* TxRx process is completed, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+ state = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Rx Complete Callback */
+ husart->TxRxCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Rx Complete Callback */
+ HAL_USART_TxRxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ else if ((state == HAL_USART_STATE_BUSY_RX) &&
+ (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
+ {
+ /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ }
+
+ /* When remaining number of bytes to receive is less than the RX FIFO
+ threshold, next incoming frames are processed as if FIFO mode was
+ disabled (i.e. one interrupt per received frame).
+ */
+ rxdatacount = husart->RxXferCount;
+ if (((rxdatacount != 0U)) && (rxdatacount < husart->NbRxDataToProcess))
+ {
+ /* Disable the USART RXFT interrupt*/
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_RXFTIE);
+
+ /* Update the RxISR function pointer */
+ husart->RxISR = USART_RxISR_16BIT;
+
+ /* Enable the USART Data Register Not Empty interrupt */
+ SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+
+ if ((husart->TxXferCount == 0U) &&
+ (state == HAL_USART_STATE_BUSY_TX_RX) &&
+ (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
+ {
+ /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
+ }
+ }
+ }
+ else
+ {
+ /* Clear RXNE interrupt flag */
+ __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_USART_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_usart_ex.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_usart_ex.c
new file mode 100644
index 00000000..f641ee9a
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_usart_ex.c
@@ -0,0 +1,655 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_usart_ex.c
+ * @author MCD Application Team
+ * @brief Extended USART HAL module driver.
+ * This file provides firmware functions to manage the following extended
+ * functionalities of the Universal Synchronous Receiver Transmitter Peripheral (USART).
+ * + Peripheral Control functions
+ *
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### USART peripheral extended features #####
+ ==============================================================================
+
+ (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
+
+ -@- When USART operates in FIFO mode, FIFO mode must be enabled prior
+ starting RX/TX transfers. Also RX/TX FIFO thresholds must be
+ configured prior starting RX/TX transfers.
+
+ (#) Slave mode enabling/disabling and NSS pin configuration.
+
+ -@- When USART operates in Slave mode, Slave mode must be enabled prior
+ starting RX/TX transfers.
+
+ @endverbatim
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup USARTEx USARTEx
+ * @brief USART Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_USART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/** @defgroup USARTEx_Private_Constants USARTEx Private Constants
+ * @{
+ */
+/* USART RX FIFO depth */
+#define RX_FIFO_DEPTH 8U
+
+/* USART TX FIFO depth */
+#define TX_FIFO_DEPTH 8U
+/**
+ * @}
+ */
+
+/* Private define ------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup USARTEx_Private_Functions USARTEx Private Functions
+ * @{
+ */
+static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup USARTEx_Exported_Functions USARTEx Exported Functions
+ * @{
+ */
+
+/** @defgroup USARTEx_Exported_Functions_Group1 IO operation functions
+ * @brief Extended USART Transmit/Receive functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ This subsection provides a set of FIFO mode related callback functions.
+
+ (#) TX/RX Fifos Callbacks:
+ (+) HAL_USARTEx_RxFifoFullCallback()
+ (+) HAL_USARTEx_TxFifoEmptyCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief USART RX Fifo full callback.
+ * @param husart USART handle.
+ * @retval None
+ */
+__weak void HAL_USARTEx_RxFifoFullCallback(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USARTEx_RxFifoFullCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief USART TX Fifo empty callback.
+ * @param husart USART handle.
+ * @retval None
+ */
+__weak void HAL_USARTEx_TxFifoEmptyCallback(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USARTEx_TxFifoEmptyCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USARTEx_Exported_Functions_Group2 Peripheral Control functions
+ * @brief Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides the following functions:
+ (+) HAL_USARTEx_EnableSPISlaveMode() API enables the SPI slave mode
+ (+) HAL_USARTEx_DisableSPISlaveMode() API disables the SPI slave mode
+ (+) HAL_USARTEx_ConfigNSS API configures the Slave Select input pin (NSS)
+ (+) HAL_USARTEx_EnableFifoMode() API enables the FIFO mode
+ (+) HAL_USARTEx_DisableFifoMode() API disables the FIFO mode
+ (+) HAL_USARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
+ (+) HAL_USARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold
+
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable the SPI slave mode.
+ * @note When the USART operates in SPI slave mode, it handles data flow using
+ * the serial interface clock derived from the external SCLK signal
+ * provided by the external master SPI device.
+ * @note In SPI slave mode, the USART must be enabled before starting the master
+ * communications (or between frames while the clock is stable). Otherwise,
+ * if the USART slave is enabled while the master is in the middle of a
+ * frame, it will become desynchronized with the master.
+ * @note The data register of the slave needs to be ready before the first edge
+ * of the communication clock or before the end of the ongoing communication,
+ * otherwise the SPI slave will transmit zeros.
+ * @param husart USART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart)
+{
+ uint32_t tmpcr1;
+
+ /* Check parameters */
+ assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance));
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->State = HAL_USART_STATE_BUSY;
+
+ /* Save actual USART configuration */
+ tmpcr1 = READ_REG(husart->Instance->CR1);
+
+ /* Disable USART */
+ __HAL_USART_DISABLE(husart);
+
+ /* In SPI slave mode mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bit in the USART_CR2 register
+ - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/
+ CLEAR_BIT(husart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(husart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+
+ /* Enable SPI slave mode */
+ SET_BIT(husart->Instance->CR2, USART_CR2_SLVEN);
+
+ /* Restore USART configuration */
+ WRITE_REG(husart->Instance->CR1, tmpcr1);
+
+ husart->SlaveMode = USART_SLAVEMODE_ENABLE;
+
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Enable USART */
+ __HAL_USART_ENABLE(husart);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the SPI slave mode.
+ * @param husart USART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart)
+{
+ uint32_t tmpcr1;
+
+ /* Check parameters */
+ assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance));
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->State = HAL_USART_STATE_BUSY;
+
+ /* Save actual USART configuration */
+ tmpcr1 = READ_REG(husart->Instance->CR1);
+
+ /* Disable USART */
+ __HAL_USART_DISABLE(husart);
+
+ /* Disable SPI slave mode */
+ CLEAR_BIT(husart->Instance->CR2, USART_CR2_SLVEN);
+
+ /* Restore USART configuration */
+ WRITE_REG(husart->Instance->CR1, tmpcr1);
+
+ husart->SlaveMode = USART_SLAVEMODE_DISABLE;
+
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the Slave Select input pin (NSS).
+ * @note Software NSS management: SPI slave will always be selected and NSS
+ * input pin will be ignored.
+ * @note Hardware NSS management: the SPI slave selection depends on NSS
+ * input pin. The slave is selected when NSS is low and deselected when
+ * NSS is high.
+ * @param husart USART handle.
+ * @param NSSConfig NSS configuration.
+ * This parameter can be one of the following values:
+ * @arg @ref USART_NSS_HARD
+ * @arg @ref USART_NSS_SOFT
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig)
+{
+ uint32_t tmpcr1;
+
+ /* Check parameters */
+ assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance));
+ assert_param(IS_USART_NSS(NSSConfig));
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->State = HAL_USART_STATE_BUSY;
+
+ /* Save actual USART configuration */
+ tmpcr1 = READ_REG(husart->Instance->CR1);
+
+ /* Disable USART */
+ __HAL_USART_DISABLE(husart);
+
+ /* Program DIS_NSS bit in the USART_CR2 register */
+ MODIFY_REG(husart->Instance->CR2, USART_CR2_DIS_NSS, NSSConfig);
+
+ /* Restore USART configuration */
+ WRITE_REG(husart->Instance->CR1, tmpcr1);
+
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable the FIFO mode.
+ * @param husart USART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart)
+{
+ uint32_t tmpcr1;
+
+ /* Check parameters */
+ assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->State = HAL_USART_STATE_BUSY;
+
+ /* Save actual USART configuration */
+ tmpcr1 = READ_REG(husart->Instance->CR1);
+
+ /* Disable USART */
+ __HAL_USART_DISABLE(husart);
+
+ /* Enable FIFO mode */
+ SET_BIT(tmpcr1, USART_CR1_FIFOEN);
+ husart->FifoMode = USART_FIFOMODE_ENABLE;
+
+ /* Restore USART configuration */
+ WRITE_REG(husart->Instance->CR1, tmpcr1);
+
+ /* Determine the number of data to process during RX/TX ISR execution */
+ USARTEx_SetNbDataToProcess(husart);
+
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the FIFO mode.
+ * @param husart USART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart)
+{
+ uint32_t tmpcr1;
+
+ /* Check parameters */
+ assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->State = HAL_USART_STATE_BUSY;
+
+ /* Save actual USART configuration */
+ tmpcr1 = READ_REG(husart->Instance->CR1);
+
+ /* Disable USART */
+ __HAL_USART_DISABLE(husart);
+
+ /* Enable FIFO mode */
+ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
+ husart->FifoMode = USART_FIFOMODE_DISABLE;
+
+ /* Restore USART configuration */
+ WRITE_REG(husart->Instance->CR1, tmpcr1);
+
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the TXFIFO threshold.
+ * @param husart USART handle.
+ * @param Threshold TX FIFO threshold value
+ * This parameter can be one of the following values:
+ * @arg @ref USART_TXFIFO_THRESHOLD_1_8
+ * @arg @ref USART_TXFIFO_THRESHOLD_1_4
+ * @arg @ref USART_TXFIFO_THRESHOLD_1_2
+ * @arg @ref USART_TXFIFO_THRESHOLD_3_4
+ * @arg @ref USART_TXFIFO_THRESHOLD_7_8
+ * @arg @ref USART_TXFIFO_THRESHOLD_8_8
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold)
+{
+ uint32_t tmpcr1;
+
+ /* Check parameters */
+ assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));
+ assert_param(IS_USART_TXFIFO_THRESHOLD(Threshold));
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->State = HAL_USART_STATE_BUSY;
+
+ /* Save actual USART configuration */
+ tmpcr1 = READ_REG(husart->Instance->CR1);
+
+ /* Disable USART */
+ __HAL_USART_DISABLE(husart);
+
+ /* Update TX threshold configuration */
+ MODIFY_REG(husart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
+
+ /* Determine the number of data to process during RX/TX ISR execution */
+ USARTEx_SetNbDataToProcess(husart);
+
+ /* Restore USART configuration */
+ WRITE_REG(husart->Instance->CR1, tmpcr1);
+
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the RXFIFO threshold.
+ * @param husart USART handle.
+ * @param Threshold RX FIFO threshold value
+ * This parameter can be one of the following values:
+ * @arg @ref USART_RXFIFO_THRESHOLD_1_8
+ * @arg @ref USART_RXFIFO_THRESHOLD_1_4
+ * @arg @ref USART_RXFIFO_THRESHOLD_1_2
+ * @arg @ref USART_RXFIFO_THRESHOLD_3_4
+ * @arg @ref USART_RXFIFO_THRESHOLD_7_8
+ * @arg @ref USART_RXFIFO_THRESHOLD_8_8
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold)
+{
+ uint32_t tmpcr1;
+
+ /* Check the parameters */
+ assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));
+ assert_param(IS_USART_RXFIFO_THRESHOLD(Threshold));
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->State = HAL_USART_STATE_BUSY;
+
+ /* Save actual USART configuration */
+ tmpcr1 = READ_REG(husart->Instance->CR1);
+
+ /* Disable USART */
+ __HAL_USART_DISABLE(husart);
+
+ /* Update RX threshold configuration */
+ MODIFY_REG(husart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
+
+ /* Determine the number of data to process during RX/TX ISR execution */
+ USARTEx_SetNbDataToProcess(husart);
+
+ /* Restore USART configuration */
+ WRITE_REG(husart->Instance->CR1, tmpcr1);
+
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set autonomous mode Configuration.
+ * @param husart USART handle.
+ * @param sConfig Autonomous mode structure parameters.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USARTEx_SetConfigAutonomousMode(USART_HandleTypeDef *husart,
+ USART_AutonomousModeConfTypeDef *sConfig)
+{
+ uint32_t tmpreg;
+
+ if (husart->State == HAL_USART_STATE_READY)
+ {
+ /* Check the parameters */
+ assert_param(IS_USART_TRIGGER_POLARITY(sConfig->TriggerPolarity));
+ assert_param(IS_USART_IDLE_FRAME_TRANSMIT(sConfig->IdleFrame));
+ assert_param(IS_USART_TX_DATA_SIZE(sConfig->DataSize));
+ assert_param(IS_USART_TRIGGER_SELECTION(sConfig->TriggerSelection));
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->State = HAL_USART_STATE_BUSY;
+
+ /* Disable USART */
+ __HAL_USART_DISABLE(husart);
+
+ /* Disable Transmitter */
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_TE);
+
+ /* Clear AUTOCR register */
+ CLEAR_REG(husart->Instance->AUTOCR);
+
+ /* USART AUTOCR Configuration */
+ tmpreg = ((sConfig->DataSize << USART_AUTOCR_TDN_Pos) | (sConfig->TriggerPolarity) |
+ (sConfig->AutonomousModeState) | (sConfig->IdleFrame) |
+ (sConfig->TriggerSelection << USART_AUTOCR_TRIGSEL_Pos));
+
+ WRITE_REG(husart->Instance->AUTOCR, tmpreg);
+
+ /* Enable USART */
+ __HAL_USART_ENABLE(husart);
+
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Get autonomous mode Configuration.
+ * @param husart USART handle.
+ * @param sConfig Autonomous mode structure parameters.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USARTEx_GetConfigAutonomousMode(USART_HandleTypeDef *husart,
+ USART_AutonomousModeConfTypeDef *sConfig)
+{
+ uint32_t tmpreg;
+
+ /* Read AUTOCR register */
+ tmpreg = READ_REG(husart->Instance->AUTOCR);
+
+ /* Fill Autonomous structure parameter */
+ sConfig->AutonomousModeState = (tmpreg & USART_AUTOCR_TRIGEN);
+ sConfig->TriggerSelection = ((tmpreg & USART_AUTOCR_TRIGSEL) >> USART_AUTOCR_TRIGSEL_Pos);
+ sConfig->TriggerPolarity = (tmpreg & USART_AUTOCR_TRIGPOL);
+ sConfig->IdleFrame = (tmpreg & USART_AUTOCR_IDLEDIS);
+ sConfig->DataSize = (tmpreg & USART_AUTOCR_TDN);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Clear autonomous mode Configuration.
+ * @param husart USART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USARTEx_ClearConfigAutonomousMode(USART_HandleTypeDef *husart)
+{
+ if (husart->State == HAL_USART_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->State = HAL_USART_STATE_BUSY;
+
+ /* Disable USART */
+ __HAL_USART_DISABLE(husart);
+
+ /* Clear AUTOCR register */
+ CLEAR_REG(husart->Instance->AUTOCR);
+
+ /* Enable USART */
+ __HAL_USART_ENABLE(husart);
+
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup USARTEx_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Calculate the number of data to process in RX/TX ISR.
+ * @note The RX FIFO depth and the TX FIFO depth is extracted from
+ * the USART configuration registers.
+ * @param husart USART handle.
+ * @retval None
+ */
+static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart)
+{
+ uint8_t rx_fifo_depth;
+ uint8_t tx_fifo_depth;
+ uint8_t rx_fifo_threshold;
+ uint8_t tx_fifo_threshold;
+ /* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */
+ static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
+ static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
+
+ if (husart->FifoMode == USART_FIFOMODE_DISABLE)
+ {
+ husart->NbTxDataToProcess = 1U;
+ husart->NbRxDataToProcess = 1U;
+ }
+ else
+ {
+ rx_fifo_depth = RX_FIFO_DEPTH;
+ tx_fifo_depth = TX_FIFO_DEPTH;
+ rx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3,
+ USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos) & 0xFFU);
+ tx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3,
+ USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos) & 0xFFU);
+ husart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
+ (uint16_t)denominator[tx_fifo_threshold];
+ husart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
+ (uint16_t)denominator[rx_fifo_threshold];
+ }
+}
+/**
+ * @}
+ */
+
+#endif /* HAL_USART_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_wwdg.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_wwdg.c
new file mode 100644
index 00000000..1514c152
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_wwdg.c
@@ -0,0 +1,420 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_wwdg.c
+ * @author MCD Application Team
+ * @brief WWDG HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Window Watchdog (WWDG) peripheral:
+ * + Initialization and Configuration functions
+ * + IO operation functions
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### WWDG Specific features #####
+ ==============================================================================
+ [..]
+ Once enabled the WWDG generates a system reset on expiry of a programmed
+ time period, unless the program refreshes the counter (T[6;0] downcounter)
+ before reaching 0x3F value (i.e. a reset is generated when the counter
+ value rolls down from 0x40 to 0x3F).
+
+ (+) An MCU reset is also generated if the counter value is refreshed
+ before the counter has reached the refresh window value. This
+ implies that the counter must be refreshed in a limited window.
+ (+) Once enabled the WWDG cannot be disabled except by a system reset.
+ (+) If required by application, an Early Wakeup Interrupt can be triggered
+ in order to be warned before WWDG expiration. The Early Wakeup Interrupt
+ (EWI) can be used if specific safety operations or data logging must
+ be performed before the actual reset is generated. When the downcounter
+ reaches 0x40, interrupt occurs. This mechanism requires WWDG interrupt
+ line to be enabled in NVIC. Once enabled, EWI interrupt cannot be
+ disabled except by a system reset.
+ (+) WWDGRST flag in RCC CSR register can be used to inform when a WWDG
+ reset occurs.
+ (+) The WWDG counter input clock is derived from the APB clock divided
+ by a programmable prescaler.
+ (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler)
+ (+) WWDG timeout (mS) = 1000 * (T[5;0] + 1) / WWDG clock (Hz)
+ where T[5;0] are the lowest 6 bits of Counter.
+ (+) WWDG Counter refresh is allowed between the following limits :
+ (++) min time (mS) = 1000 * (Counter - Window) / WWDG clock
+ (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
+ (+) Typical values:
+ (++) Counter min (T[5;0] = 0x00) at 56MHz (PCLK1) with zero prescaler:
+ max timeout before reset: approximately 73.14us
+ (++) Counter max (T[5;0] = 0x3F) at 56MHz (PCLK1) with prescaler
+ dividing by 128:
+ max timeout before reset: approximately 599.18ms
+
+ ##### How to use this driver #####
+ ==============================================================================
+
+ *** Common driver usage ***
+ ===========================
+
+ [..]
+ (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
+ (+) Configure the WWDG prescaler, refresh window value, counter value and early
+ interrupt status using HAL_WWDG_Init() function. This will automatically
+ enable WWDG and start its downcounter. Time reference can be taken from
+ function exit. Care must be taken to provide a counter value
+ greater than 0x40 to prevent generation of immediate reset.
+ (+) If the Early Wakeup Interrupt (EWI) feature is enabled, an interrupt is
+ generated when the counter reaches 0x40. When HAL_WWDG_IRQHandler is
+ triggered by the interrupt service routine, flag will be automatically
+ cleared and HAL_WWDG_WakeupCallback user callback will be executed. User
+ can add his own code by customization of callback HAL_WWDG_WakeupCallback.
+ (+) Then the application program must refresh the WWDG counter at regular
+ intervals during normal operation to prevent an MCU reset, using
+ HAL_WWDG_Refresh() function. This operation must occur only when
+ the counter is lower than the refresh window value already programmed.
+
+ *** Callback registration ***
+ =============================
+
+ [..]
+ The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows
+ the user to configure dynamically the driver callbacks. Use Functions
+ HAL_WWDG_RegisterCallback() to register a user callback.
+
+ (+) Function HAL_WWDG_RegisterCallback() allows to register following
+ callbacks:
+ (++) EwiCallback : callback for Early WakeUp Interrupt.
+ (++) MspInitCallback : WWDG MspInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ (+) Use function HAL_WWDG_UnRegisterCallback() to reset a callback to
+ the default weak (surcharged) function. HAL_WWDG_UnRegisterCallback()
+ takes as parameters the HAL peripheral handle and the Callback ID.
+ This function allows to reset following callbacks:
+ (++) EwiCallback : callback for Early WakeUp Interrupt.
+ (++) MspInitCallback : WWDG MspInit.
+
+ [..]
+ When calling HAL_WWDG_Init function, callbacks are reset to the
+ corresponding legacy weak (surcharged) functions:
+ HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have
+ not been registered before.
+
+ [..]
+ When compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
+ *** WWDG HAL driver macros list ***
+ ===================================
+ [..]
+ Below the list of available macros in WWDG HAL driver.
+ (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral
+ (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
+ (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags
+ (+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt
+
+ @endverbatim
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+/** @defgroup WWDG WWDG
+ * @brief WWDG HAL module driver.
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Functions WWDG Exported Functions
+ * @{
+ */
+
+/** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions
+ * @brief Initialization and Configuration functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and Configuration functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and start the WWDG according to the specified parameters
+ in the WWDG_InitTypeDef of associated handle.
+ (+) Initialize the WWDG MSP.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the WWDG according to the specified.
+ * parameters in the WWDG_InitTypeDef of associated handle.
+ * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
+{
+ /* Check the WWDG handle allocation */
+ if (hwwdg == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
+ assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));
+ assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));
+ assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
+ assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode));
+
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+ /* Reset Callback pointers */
+ if (hwwdg->EwiCallback == NULL)
+ {
+ hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
+ }
+
+ if (hwwdg->MspInitCallback == NULL)
+ {
+ hwwdg->MspInitCallback = HAL_WWDG_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hwwdg->MspInitCallback(hwwdg);
+#else
+ /* Init the low level hardware */
+ HAL_WWDG_MspInit(hwwdg);
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
+
+ /* Set WWDG Counter */
+ WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));
+
+ /* Set WWDG Prescaler and Window */
+ WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window));
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Initialize the WWDG MSP.
+ * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @note When rewriting this function in user file, mechanism may be added
+ * to avoid multiple initialize when HAL_WWDG_Init function is called
+ * again to change parameters.
+ * @retval None
+ */
+__weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hwwdg);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_WWDG_MspInit could be implemented in the user file
+ */
+}
+
+
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User WWDG Callback
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hwwdg WWDG handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
+ * @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID,
+ pWWDG_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ switch (CallbackID)
+ {
+ case HAL_WWDG_EWI_CB_ID:
+ hwwdg->EwiCallback = pCallback;
+ break;
+
+ case HAL_WWDG_MSPINIT_CB_ID:
+ hwwdg->MspInitCallback = pCallback;
+ break;
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+ }
+
+ return status;
+}
+
+
+/**
+ * @brief Unregister a WWDG Callback
+ * WWDG Callback is redirected to the weak (surcharged) predefined callback
+ * @param hwwdg WWDG handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
+ * @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ switch (CallbackID)
+ {
+ case HAL_WWDG_EWI_CB_ID:
+ hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
+ break;
+
+ case HAL_WWDG_MSPINIT_CB_ID:
+ hwwdg->MspInitCallback = HAL_WWDG_MspInit;
+ break;
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ return status;
+}
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
+ * @brief IO operation functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Refresh the WWDG.
+ (+) Handle WWDG interrupt request and associated function callback.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Refresh the WWDG.
+ * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg)
+{
+ /* Write to WWDG CR the WWDG Counter value to refresh with */
+ WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter));
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle WWDG interrupt request.
+ * @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations
+ * or data logging must be performed before the actual reset is generated.
+ * The EWI interrupt is enabled by calling HAL_WWDG_Init function with
+ * EWIMode set to WWDG_EWI_ENABLE.
+ * When the downcounter reaches the value 0x40, and EWI interrupt is
+ * generated and the corresponding Interrupt Service Routine (ISR) can
+ * be used to trigger specific actions (such as communications or data
+ * logging), before resetting the device.
+ * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @retval None
+ */
+void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
+{
+ /* Check if Early Wakeup Interrupt is enable */
+ if (__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
+ {
+ /* Check if WWDG Early Wakeup Interrupt occurred */
+ if (__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
+ {
+ /* Clear the WWDG Early Wakeup flag */
+ __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
+
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+ /* Early Wakeup registered callback */
+ hwwdg->EwiCallback(hwwdg);
+#else
+ /* Early Wakeup callback */
+ HAL_WWDG_EarlyWakeupCallback(hwwdg);
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
+ }
+ }
+}
+
+
+/**
+ * @brief WWDG Early Wakeup callback.
+ * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @retval None
+ */
+__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hwwdg);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_WWDG_EarlyWakeupCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_WWDG_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_adc.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_adc.c
new file mode 100644
index 00000000..41dbb303
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_adc.c
@@ -0,0 +1,1162 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_adc.c
+ * @author MCD Application Team
+ * @brief ADC LL module driver
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_ll_adc.h"
+#include "stm32u5xx_ll_bus.h"
+
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined (ADC1) || defined (ADC2) || defined (ADC4)
+
+/** @addtogroup ADC_LL ADC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup ADC_LL_Private_Constants
+ * @{
+ */
+
+/* Definitions of ADC hardware constraints delays */
+/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
+/* not timeout values: */
+/* Timeout values for ADC operations are dependent to device clock */
+/* configuration (system clock versus ADC clock), */
+/* and therefore must be defined in user application. */
+/* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
+/* values definition. */
+/* Note: ADC timeout values are defined here in CPU cycles to be independent */
+/* of device clock setting. */
+/* In user application, ADC timeout values should be defined with */
+/* temporal values, in function of device clock settings. */
+/* Highest ratio CPU clock frequency vs ADC clock frequency: */
+/* - ADC clock from synchronous clock with AHB prescaler 512, */
+/* APB prescaler 16, ADC prescaler 4. */
+/* - ADC clock from asynchronous clock (PLL) with prescaler 1, */
+/* with highest ratio CPU clock frequency vs HSI clock frequency */
+/* Unit: CPU cycles. */
+#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 16UL * 4UL)
+#define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
+#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
+
+/**
+ * @}
+ */
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup ADC_LL_Private_Macros
+ * @{
+ */
+
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* applicable for the twoinstances. */
+#define IS_LL_ADC_CLOCK(__CLOCK__) \
+ ( ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \
+ )
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* ADC instance. */
+#define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
+ ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_14B) \
+ || ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
+ || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
+ || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
+ || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
+ )
+
+#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
+ ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
+ || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
+ )
+
+#define IS_LL_ADC_LEFT_BIT_SHIFT(__LEFT_BIT_SHIFT__) \
+ ( ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_NONE) \
+ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_1) \
+ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_2) \
+ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_3) \
+ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_4) \
+ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_5) \
+ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_6) \
+ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_7) \
+ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_8) \
+ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_9) \
+ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_10) \
+ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_11) \
+ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_12) \
+ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_13) \
+ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_14) \
+ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_15) \
+ )
+
+#define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
+ ( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
+ || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
+ )
+
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* ADC group regular */
+#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
+ ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE15) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM1_CH1) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM2_CH1) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM3_CH1) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM4_OUT) \
+ )
+
+#define IS_LL_ADC4_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
+ ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2_ADC4) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4_ADC4) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO_ADC4) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO_ADC4) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC4) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM1_CH1_ADC4) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM3_CH2_ADC4) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE15_ADC4) \
+ )
+
+#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
+ ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
+ || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
+ )
+
+#define IS_LL_ADC_REG_DATA_TRANSFER_MODE(__REG_DATA_TRANSFER_MODE__) \
+ ( ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DR_TRANSFER) \
+ || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
+ || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
+ || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_MDF_TRANSFER) \
+ )
+#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
+ ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE_ADC4) \
+ || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED_ADC4) \
+ || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED_ADC4) \
+ )
+
+#define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
+ ( ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
+ || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
+ )
+
+#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
+ ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
+ )
+
+#define IS_LL_ADC_REG_SEQ_MODE(__REG_SEQ_MODE__) \
+ ( ((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_FIXED) \
+ || ((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_CONFIGURABLE) \
+ )
+
+#define IS_LL_ADC4_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
+ ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC4_REG_SEQ_SCAN_DISABLE) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC4_REG_SEQ_SCAN_ENABLE_2RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC4_REG_SEQ_SCAN_ENABLE_3RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC4_REG_SEQ_SCAN_ENABLE_4RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC4_REG_SEQ_SCAN_ENABLE_5RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC4_REG_SEQ_SCAN_ENABLE_6RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC4_REG_SEQ_SCAN_ENABLE_7RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC4_REG_SEQ_SCAN_ENABLE_8RANKS) \
+ )
+
+#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
+ ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
+ )
+
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* ADC group injected */
+
+#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
+ ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM3_CH1) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM4_OUT) \
+ )
+
+#define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
+ ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
+ || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
+ || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \
+ )
+
+#define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
+ ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
+ || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
+ )
+
+#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
+ ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
+ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
+ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
+ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
+ )
+
+#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
+ ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
+ || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
+ )
+
+/**
+ * @}
+ */
+
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup ADC_LL_EF_Init
+ * @{
+ */
+/**
+ * @brief De-initialize registers of all ADC instances belonging to
+ * the same ADC common instance to their default reset values.
+ * @note This function is performing a hard reset, using high level
+ * clock source RCC ADC reset.
+ * Caution: On this STM32 series, if several ADC instances are available
+ * on the selected device, RCC ADC reset will reset
+ * all ADC instances belonging to the common ADC instance.
+ * To de-initialize only 1 ADC instance, use
+ * function @ref LL_ADC_DeInit().
+ * @param pADCxyCOMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC common registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *pADCxyCOMMON)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_COMMON_INSTANCE(pADCxyCOMMON));
+
+ if (pADCxyCOMMON == ADC12_COMMON)
+ {
+ /* Force reset of ADC clock (core clock) */
+ LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC1);
+
+ /* Release reset of ADC clock (core clock) */
+ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC1);
+ }
+ else /*if ( pADCxyCOMMON == ADC4_COMMON)*/
+ {
+ /* Force reset of ADC clock (core clock) */
+ LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_ADC4);
+
+ /* Release reset of ADC clock (core clock) */
+ LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_ADC4);
+ }
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Initialize some features of ADC common parameters
+ * (all ADC instances belonging to the same ADC common instance)
+ * and multimode (for devices with several ADC instances available).
+ * @note The setting of ADC common parameters is conditioned to
+ * ADC instances state:
+ * All ADC instances belonging to the same ADC common instance
+ * must be disabled.
+ * @param pADCxyCOMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param pADC_CommonInit Pointer to a @ref LL_ADC_CommonInitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC common registers are initialized
+ * - ERROR: ADC common registers are not initialized
+ */
+ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *pADCxyCOMMON, LL_ADC_CommonInitTypeDef *pADC_CommonInit)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_COMMON_INSTANCE(pADCxyCOMMON));
+ assert_param(IS_LL_ADC_CLOCK(pADC_CommonInit->CommonClock));
+
+ /* Note: Hardware constraint (refer to description of functions */
+ /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
+ /* On this STM32 series, setting of these features is conditioned to */
+ /* ADC state: */
+ /* All ADC instances of the ADC common group must be disabled. */
+ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(pADCxyCOMMON) == 0UL)
+ {
+ /* Configuration of ADC hierarchical scope: */
+ /* - common to several ADC */
+ /* (all ADC instances belonging to the same ADC common instance) */
+ /* - Set ADC clock (conversion clock) */
+ LL_ADC_SetCommonClock(pADCxyCOMMON, pADC_CommonInit->CommonClock);
+ }
+ else
+ {
+ /* Initialization error: One or several ADC instances belonging to */
+ /* the same ADC common instance are not disabled. */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
+ * @param pADC_CommonInit Pointer to a @ref LL_ADC_CommonInitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInit)
+{
+ /* Set pADC_CommonInit fields to default values */
+ /* Set fields of ADC common */
+ /* (all ADC instances belonging to the same ADC common instance) */
+ pADC_CommonInit->CommonClock = LL_ADC_CLOCK_ASYNC_DIV2;
+
+}
+
+/**
+ * @brief De-initialize registers of the selected ADC instance
+ * to their default reset values.
+ * @note To reset all ADC instances quickly (perform a hard reset),
+ * use function @ref LL_ADC_CommonDeInit().
+ * @param pADCx ADC instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC registers are de-initialized
+ * - ERROR: ADC registers are not de-initialized
+ */
+ErrorStatus LL_ADC_DeInit(ADC_TypeDef *pADCx)
+{
+ ErrorStatus status = SUCCESS;
+ __IO uint32_t timeout_cpu_cycles = 0UL;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(pADCx));
+
+ /* Disable ADC instance if not already disabled. */
+ if (LL_ADC_IsEnabled(pADCx) == 1UL)
+ {
+ /* Set ADC group regular trigger source to SW start to ensure to not */
+ /* have an external trigger event occurring during the conversion stop */
+ /* ADC disable process. */
+ LL_ADC_REG_SetTriggerSource(pADCx, LL_ADC_REG_TRIG_SOFTWARE);
+
+ /* Stop potential ADC conversion on going on ADC group regular. */
+ if (LL_ADC_REG_IsConversionOngoing(pADCx) != 0UL)
+ {
+ if (LL_ADC_REG_IsStopConversionOngoing(pADCx) == 0UL)
+ {
+ LL_ADC_REG_StopConversion(pADCx);
+ }
+ }
+
+ /* Wait for ADC conversions are effectively stopped */
+ timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
+ if (pADCx != ADC4) /* ADC1 or ADC2 */
+ {
+ while ((LL_ADC_REG_IsStopConversionOngoing(pADCx)
+ | LL_ADC_INJ_IsStopConversionOngoing(pADCx)) == 1UL)
+ {
+ timeout_cpu_cycles--;
+ if (timeout_cpu_cycles == 0UL)
+ {
+ /* Time-out error */
+ status = ERROR;
+ break;
+ }
+ }
+ }
+ else
+ {
+ while (LL_ADC_REG_IsStopConversionOngoing(pADCx) == 1UL)
+ {
+ timeout_cpu_cycles--;
+ if (timeout_cpu_cycles == 0UL)
+ {
+ /* Time-out error */
+ status = ERROR;
+ }
+ }
+ }
+ /* Disable the ADC instance */
+ LL_ADC_Disable(pADCx);
+
+ /* Wait for ADC instance is effectively disabled */
+ timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
+ while (LL_ADC_IsDisableOngoing(pADCx) == 1UL)
+ {
+ timeout_cpu_cycles--;
+ if (timeout_cpu_cycles == 0UL)
+ {
+ /* Time-out error */
+ status = ERROR;
+ }
+ }
+ }
+
+ if (pADCx != ADC4) /* ADC1 or ADC2 */
+ {
+ CLEAR_BIT(pADCx->IER,
+ (LL_ADC_IT_AWD3
+ | LL_ADC_IT_AWD2
+ | LL_ADC_IT_AWD1
+ | LL_ADC_IT_JQOVF
+ | LL_ADC_IT_OVR
+ | LL_ADC_IT_JEOS
+ | LL_ADC_IT_JEOC
+ | LL_ADC_IT_EOS
+ | LL_ADC_IT_EOC
+ | LL_ADC_IT_EOSMP
+ | LL_ADC_IT_ADRDY
+ )
+ );
+
+ /* Reset register ISR */
+ SET_BIT(pADCx->ISR,
+ (LL_ADC_FLAG_AWD3
+ | LL_ADC_FLAG_AWD2
+ | LL_ADC_FLAG_AWD1
+ | LL_ADC_FLAG_JQOVF
+ | LL_ADC_FLAG_OVR
+ | LL_ADC_FLAG_JEOS
+ | LL_ADC_FLAG_JEOC
+ | LL_ADC_FLAG_EOS
+ | LL_ADC_FLAG_EOC
+ | LL_ADC_FLAG_EOSMP
+ | LL_ADC_FLAG_ADRDY
+ )
+ );
+
+ /* Reset register CR */
+ /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */
+ /* "read-set": no direct reset applicable. */
+ CLEAR_BIT(pADCx->CR, ADC_CR_ADVREGEN);
+ SET_BIT(pADCx->CR, ADC_CR_DEEPPWD);
+
+ /* Reset register CFGR */
+ CLEAR_BIT(pADCx->CFGR1, ADC_CFGR1_AWD1CH | ADC_CFGR1_JAUTO | ADC_CFGR1_JAWD1EN |
+ ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_JDISCEN |
+ ADC_CFGR1_DISCNUM | ADC_CFGR1_DISCEN | ADC_CFGR1_AUTDLY |
+ ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD |
+ ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL |
+ ADC_CFGR1_RES | ADC_CFGR1_DMNGT);
+
+ /* Reset register CFGR2 */
+ CLEAR_BIT(pADCx->CFGR2, ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS |
+ ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE);
+
+ /* Reset register SMPR1 */
+ CLEAR_BIT(pADCx->SMPR1,
+ (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7
+ | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4
+ | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1)
+ );
+
+ /* Reset register SMPR2 */
+ CLEAR_BIT(pADCx->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 |
+ ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 |
+ ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10);
+
+ /* Reset register LTR1 and HTR1 */
+ CLEAR_BIT(pADCx->LTR1, ADC_LTR_LT);
+ SET_BIT(pADCx->HTR1, ADC_HTR_HT);
+
+ /* Reset register LTR2 and HTR2*/
+ CLEAR_BIT(pADCx->LTR2, ADC_LTR_LT);
+ SET_BIT(pADCx->HTR2, ADC_HTR_HT);
+
+ /* Reset register LTR3 and HTR3 */
+ CLEAR_BIT(pADCx->LTR3, ADC_LTR_LT);
+ SET_BIT(pADCx->HTR3, ADC_HTR_HT);
+
+ /* Reset register SQR1 */
+ CLEAR_BIT(pADCx->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 | ADC_SQR1_SQ1 | ADC_SQR1_L);
+
+ /* Reset register SQR2 */
+ CLEAR_BIT(pADCx->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 | ADC_SQR2_SQ6 | ADC_SQR2_SQ5);
+
+ /* Reset register SQR3 */
+ CLEAR_BIT(pADCx->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 | ADC_SQR3_SQ11 | ADC_SQR3_SQ10);
+
+ /* Reset register SQR4 */
+ CLEAR_BIT(pADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
+
+ /* Reset register JSQR */
+ CLEAR_BIT(pADCx->JSQR,
+ (ADC_JSQR_JL
+ | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN
+ | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
+ | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1)
+ );
+ /* Reset register DR */
+ /* bits in access mode read only, no direct reset applicable*/
+
+ /* Reset register OFR1 */
+ CLEAR_BIT(pADCx->OFR1, ADC_OFR1_SSAT | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
+ /* Reset register OFR2 */
+ CLEAR_BIT(pADCx->OFR2, ADC_OFR2_SSAT | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
+ /* Reset register OFR3 */
+ CLEAR_BIT(pADCx->OFR3, ADC_OFR3_SSAT | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
+ /* Reset register OFR4 */
+ CLEAR_BIT(pADCx->OFR4, ADC_OFR4_SSAT | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
+
+ /* Reset register GCOMP */
+ CLEAR_BIT(pADCx->GCOMP, ADC_GCOMP_GCOMP | ADC_GCOMP_GCOMPCOEFF);
+
+ /* Reset registers JDR1, JDR2, JDR3, JDR4 */
+ /* bits in access mode read only, no direct reset applicable*/
+
+ /* Reset register AWD2CR */
+ CLEAR_BIT(pADCx->AWD2CR, ADC_AWD2CR_AWD2CH);
+
+ /* Reset register AWD3CR */
+ CLEAR_BIT(pADCx->AWD3CR, ADC_AWD3CR_AWD3CH);
+
+ /* Reset register DIFSEL */
+ CLEAR_BIT(pADCx->DIFSEL, ADC_DIFSEL_DIFSEL);
+
+ /* Reset register PCSEL */
+ CLEAR_BIT(pADCx->PCSEL, ADC_PCSEL_PCSEL);
+
+ /* Reset register CALFACT */
+ CLEAR_BIT(pADCx->CALFACT, ADC_CALFACT_CAPTURE_COEF | ADC_CALFACT_LATCH_COEF);
+ }
+ else
+ {
+ /* Check whether ADC state is compliant with expected state */
+ if (READ_BIT(pADCx->CR, (ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) == 0UL)
+ {
+ /* ========== Reset ADC registers ========== */
+ /* Reset register IER */
+ CLEAR_BIT(pADCx->IER,
+ (LL_ADC_IT_ADRDY
+ | LL_ADC_IT_EOC
+ | LL_ADC_IT_EOS
+ | LL_ADC_IT_OVR
+ | LL_ADC_IT_EOSMP
+ | LL_ADC_IT_AWD1
+ | LL_ADC_IT_AWD2
+ | LL_ADC_IT_AWD3
+ | LL_ADC_IT_EOCAL
+ | LL_ADC_IT_LDORDY
+ )
+ );
+
+ /* Reset register ISR */
+ SET_BIT(pADCx->ISR,
+ (LL_ADC_FLAG_ADRDY
+ | LL_ADC_FLAG_EOC
+ | LL_ADC_FLAG_EOS
+ | LL_ADC_FLAG_OVR
+ | LL_ADC_FLAG_EOSMP
+ | LL_ADC_FLAG_AWD1
+ | LL_ADC_FLAG_AWD2
+ | LL_ADC_FLAG_AWD3
+ | LL_ADC_FLAG_EOCAL
+ | LL_ADC_FLAG_LDORDY
+ )
+ );
+
+ /* Reset register CR */
+ /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */
+ /* "read-set": no direct reset applicable. */
+ CLEAR_BIT(pADCx->CR, ADC_CR_ADVREGEN);
+
+ /* Reset register CFGR1 */
+ CLEAR_BIT(pADCx->CFGR1,
+ (ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN
+ | ADC4_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD
+ | ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC4_CFGR1_ALIGN | ADC_CFGR1_RES
+ | ADC4_CFGR1_SCANDIR | ADC4_CFGR1_DMACFG | ADC4_CFGR1_DMAEN)
+ );
+
+ /* Reset register CFGR2 */
+ /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */
+ /* already done above. */
+ CLEAR_BIT(pADCx->CFGR2,
+ (ADC_CFGR2_TROVS | ADC_CFGR2_OVSS | ADC4_CFGR2_OVSR
+ | ADC_CFGR2_ROVSE | ADC4_CFGR2_LFTRIG)
+ );
+
+ /* Reset register SMPR */
+ CLEAR_BIT(pADCx->SMPR1, ADC4_SMPR_SMP1 | ADC4_SMPR_SMP2 | ADC4_SMPR_SMPSEL);
+
+ /* Reset register TR1 */
+ MODIFY_REG(pADCx->AWD1TR, ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1, ADC_AWD1TR_HT1);
+
+ /* Reset register TR2 */
+ MODIFY_REG(pADCx->AWD2TR, ADC_AWD2TR_HT2 | ADC_AWD2TR_LT2, ADC_AWD2TR_HT2);
+
+ /* Reset register TR3 */
+ MODIFY_REG(pADCx->AWD3TR, ADC_AWD3TR_HT3 | ADC_AWD3TR_LT3, ADC_AWD3TR_HT3);
+
+ /* Reset register CHSELR */
+ CLEAR_BIT(pADCx->CHSELR,
+ (ADC_CHSELR_CHSEL23 | ADC_CHSELR_CHSEL22 | ADC_CHSELR_CHSEL21 | ADC_CHSELR_CHSEL20
+ | ADC_CHSELR_CHSEL19 | ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16
+ | ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12
+ | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8
+ | ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4
+ | ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0)
+ );
+
+ /* Reset register DR */
+ /* bits in access mode read only, no direct reset applicable */
+
+ /* Reset register CALFACT */
+ CLEAR_BIT(pADCx->CALFACT, ADC4_CALFACT_CALFACT);
+
+ /* Reset register CCR */
+ CLEAR_BIT(ADC4_COMMON->CCR, ADC_CCR_VBATEN | ADC_CCR_VSENSEEN | ADC_CCR_VREFEN | ADC_CCR_PRESC);
+ }
+ else
+ {
+ /* ADC instance is in an unknown state */
+ /* Need to performing a hard reset of ADC instance, using high level */
+ /* clock source RCC ADC reset. */
+ /* Caution: On this STM32 series, if several ADC instances are available */
+ /* on the selected device, RCC ADC reset will reset */
+ /* all ADC instances belonging to the common ADC instance. */
+ status = ERROR;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initialize some features of ADC instance.
+ * @note These parameters have an impact on ADC scope: ADC instance.
+ * Affects both group regular and group injected (availability
+ * of ADC group injected depends on STM32 families).
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Instance .
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ * @note After using this function, some other features must be configured
+ * using LL unitary functions.
+ * The minimum configuration remaining to be done is:
+ * - Set ADC group regular or group injected sequencer:
+ * map channel on the selected sequencer rank.
+ * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
+ * - Set ADC channel sampling time
+ * Refer to function LL_ADC_SetChannelSamplingTime();
+ * @param pADCx ADC instance
+ * @param pADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC registers are initialized
+ * - ERROR: ADC registers are not initialized
+ */
+ErrorStatus LL_ADC_Init(ADC_TypeDef *pADCx, LL_ADC_InitTypeDef *pADC_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(pADCx));
+
+ assert_param(IS_LL_ADC_RESOLUTION(pADC_InitStruct->Resolution));
+ assert_param(IS_LL_ADC_LOW_POWER(pADC_InitStruct->LowPowerMode));
+ if (pADCx != ADC4) /* ADC1 or ADC2 */
+ {
+ assert_param(IS_LL_ADC_LEFT_BIT_SHIFT(pADC_InitStruct->LeftBitShift));
+ }
+ else
+ {
+ assert_param(IS_LL_ADC_DATA_ALIGN(pADC_InitStruct->DataAlignment));
+ }
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* ADC instance must be disabled. */
+ if (LL_ADC_IsEnabled(pADCx) == 0UL)
+ {
+ /* Configuration of ADC hierarchical scope: */
+ /* - ADC instance */
+ /* - Set ADC data resolution */
+ /* - Set ADC conversion data alignment */
+ /* - Set ADC low power mode */
+ if (pADCx != ADC4) /* ADC1 or ADC2 */
+ {
+ MODIFY_REG(pADCx->CFGR1,
+ ADC_CFGR1_RES | ADC4_CFGR1_WAIT, pADC_InitStruct->Resolution | pADC_InitStruct->LowPowerMode);
+ MODIFY_REG(pADCx->CFGR2, ADC_CFGR2_LSHIFT, pADC_InitStruct->LeftBitShift);
+ }
+ else
+ {
+ MODIFY_REG(pADCx->CFGR1,
+ ADC_CFGR1_RES | ADC4_CFGR1_ALIGN | ADC4_CFGR1_WAIT,
+ __LL_ADC_RESOLUTION_ADC1_TO_ADC4(pADC_InitStruct->Resolution)
+ | pADC_InitStruct->DataAlignment
+ | pADC_InitStruct->LowPowerMode
+ );
+ }
+ }
+ else
+ {
+ /* Initialization error: ADC instance is not disabled. */
+ status = ERROR;
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
+ * @param pADCx ADC instance
+ * @param pADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_ADC_StructInit(ADC_TypeDef *pADCx, LL_ADC_InitTypeDef *pADC_InitStruct)
+{
+ /* Set pADC_InitStruct fields to default values */
+ /* Set fields of ADC instance */
+ pADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
+ if (pADCx != ADC4) /* ADC1 or ADC2 */
+ {
+ pADC_InitStruct->Resolution = LL_ADC_RESOLUTION_14B;
+ pADC_InitStruct->LeftBitShift = LL_ADC_LEFT_BIT_SHIFT_NONE;
+ }
+ else
+ {
+ pADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
+ pADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
+ }
+}
+
+/**
+ * @brief Initialize some features of ADC group regular.
+ * @note These parameters have an impact on ADC scope: ADC group regular.
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ * (functions with prefix "REG").
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ * @note After using this function, other features must be configured
+ * using LL unitary functions.
+ * The minimum configuration remaining to be done is:
+ * - Set ADC group regular or group injected sequencer:
+ * map channel on the selected sequencer rank.
+ * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
+ * - Set ADC channel sampling time
+ * Refer to function LL_ADC_SetChannelSamplingTime();
+ * @param pADCx ADC instance
+ * @param pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC registers are initialized
+ * - ERROR: ADC registers are not initialized
+ */
+ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *pADCx, LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(pADCx));
+ if (pADCx == ADC1)
+ {
+ assert_param(IS_LL_ADC_REG_TRIG_SOURCE(pADC_RegInitStruct->TriggerSource));
+ assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(pADC_RegInitStruct->SequencerLength));
+ assert_param(IS_LL_ADC_REG_DATA_TRANSFER_MODE(pADC_RegInitStruct->DataTransferMode));
+ }
+ else
+ {
+ assert_param(IS_LL_ADC4_REG_TRIG_SOURCE(pADC_RegInitStruct->TriggerSource));
+ assert_param(IS_LL_ADC4_REG_SEQ_SCAN_LENGTH(pADC_RegInitStruct->SequencerLength));
+ assert_param(IS_LL_ADC_REG_DMA_TRANSFER(pADC_RegInitStruct->DMATransfer));
+ if ((LL_ADC_REG_GetSequencerConfigurable(pADCx) == LL_ADC_REG_SEQ_FIXED)
+ || (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+ )
+ {
+ assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(pADC_RegInitStruct->SequencerDiscont));
+
+ /* ADC group regular continuous mode and discontinuous mode */
+ /* can not be enabled simultenaeously */
+ assert_param((pADC_RegInitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
+ || (pADC_RegInitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
+ }
+ }
+ if (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+ {
+ assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(pADC_RegInitStruct->SequencerDiscont));
+ }
+ assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(pADC_RegInitStruct->ContinuousMode));
+ assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(pADC_RegInitStruct->Overrun));
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* ADC instance must be disabled. */
+ if (LL_ADC_IsEnabled(pADCx) == 0UL)
+ {
+ /* Configuration of ADC hierarchical scope: */
+ /* - ADC group regular */
+ /* - Set ADC group regular trigger source */
+ /* - Set ADC group regular sequencer length */
+ /* - Set ADC group regular sequencer discontinuous mode */
+ /* - Set ADC group regular continuous mode */
+ /* - Set ADC group regular conversion data transfer: no transfer or */
+ /* transfer by DMA, and DMA requests mode */
+ /* - Set ADC group regular overrun behavior */
+ /* Note: On this STM32 series, ADC trigger edge is set when starting */
+ /* ADC conversion. */
+ /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
+ if (pADCx != ADC4) /* ADC1 or ADC2 */
+ {
+ if (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+ {
+ MODIFY_REG(pADCx->CFGR1,
+ ADC_CFGR1_EXTSEL
+ | ADC_CFGR1_EXTEN
+ | ADC_CFGR1_DISCEN
+ | ADC_CFGR1_DISCNUM
+ | ADC_CFGR1_CONT
+ | ADC_CFGR1_DMNGT
+ | ADC_CFGR1_OVRMOD
+ ,
+ pADC_RegInitStruct->TriggerSource
+ | pADC_RegInitStruct->SequencerDiscont
+ | pADC_RegInitStruct->ContinuousMode
+ | pADC_RegInitStruct->DataTransferMode
+ | pADC_RegInitStruct->Overrun
+ );
+ }
+ else
+ {
+ MODIFY_REG(pADCx->CFGR1,
+ ADC_CFGR1_EXTSEL
+ | ADC_CFGR1_EXTEN
+ | ADC_CFGR1_DISCEN
+ | ADC_CFGR1_DISCNUM
+ | ADC_CFGR1_CONT
+ | ADC_CFGR1_DMNGT
+ | ADC_CFGR1_OVRMOD
+ ,
+ pADC_RegInitStruct->TriggerSource
+ | LL_ADC_REG_SEQ_DISCONT_DISABLE
+ | pADC_RegInitStruct->ContinuousMode
+ | pADC_RegInitStruct->DataTransferMode
+ | pADC_RegInitStruct->Overrun
+ );
+ }
+ }
+ else
+ {
+ if ((LL_ADC_REG_GetSequencerConfigurable(pADCx) == LL_ADC_REG_SEQ_FIXED)
+ || (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+ )
+ {
+ MODIFY_REG(pADCx->CFGR1,
+ ADC_CFGR1_EXTSEL
+ | ADC_CFGR1_EXTEN
+ | ADC_CFGR1_DISCEN
+ | ADC_CFGR1_CONT
+ | ADC4_CFGR1_DMAEN
+ | ADC4_CFGR1_DMACFG
+ | ADC_CFGR1_OVRMOD
+ ,
+ pADC_RegInitStruct->TriggerSource
+ | pADC_RegInitStruct->SequencerDiscont
+ | pADC_RegInitStruct->ContinuousMode
+ | pADC_RegInitStruct->DMATransfer
+ | pADC_RegInitStruct->Overrun
+ );
+ }
+ else
+ {
+ MODIFY_REG(pADCx->CFGR1,
+ ADC_CFGR1_EXTSEL
+ | ADC_CFGR1_EXTEN
+ | ADC_CFGR1_DISCEN
+ | ADC_CFGR1_CONT
+ | ADC4_CFGR1_DMAEN
+ | ADC4_CFGR1_DMACFG
+ | ADC_CFGR1_OVRMOD
+ ,
+ pADC_RegInitStruct->TriggerSource
+ | LL_ADC_REG_SEQ_DISCONT_DISABLE
+ | pADC_RegInitStruct->ContinuousMode
+ | pADC_RegInitStruct->DMATransfer
+ | pADC_RegInitStruct->Overrun
+ );
+ }
+ }
+
+ /* Set ADC group regular sequencer length and scan direction */
+ if (pADCx == ADC4)
+ {
+ if (LL_ADC_REG_GetSequencerConfigurable(pADCx) != LL_ADC_REG_SEQ_FIXED)
+ {
+ LL_ADC_REG_SetSequencerLength(pADCx, pADC_RegInitStruct->SequencerLength);
+ }
+ }
+ else
+ {
+ LL_ADC_REG_SetSequencerLength(pADCx, pADC_RegInitStruct->SequencerLength);
+ }
+ }
+ else
+ {
+ /* Initialization error: ADC instance is not disabled. */
+ status = ERROR;
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
+ * @param pADCx ADC instance
+ * @param pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_ADC_REG_StructInit(ADC_TypeDef *pADCx, LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
+{
+ /* Set pADC_RegInitStruct fields to default values */
+ /* Set fields of ADC group regular */
+ /* Note: On this STM32 series, ADC trigger edge is set when starting */
+ /* ADC conversion. */
+ /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
+ pADC_RegInitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
+ pADC_RegInitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
+ pADC_RegInitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
+ pADC_RegInitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
+ pADC_RegInitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
+ if (pADCx != ADC4) /* ADC1 or ADC2 */
+ {
+ pADC_RegInitStruct->DataTransferMode = LL_ADC_REG_DR_TRANSFER;
+ }
+ else
+ {
+ pADC_RegInitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE_ADC4;
+ }
+}
+
+/**
+ * @brief Initialize some features of ADC group injected.
+ * @note These parameters have an impact on ADC scope: ADC group injected.
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ * (functions with prefix "INJ").
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ * @note After using this function, other features must be configured
+ * using LL unitary functions.
+ * The minimum configuration remaining to be done is:
+ * - Set ADC group injected sequencer:
+ * map channel on the selected sequencer rank.
+ * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
+ * - Set ADC channel sampling time
+ * Refer to function LL_ADC_SetChannelSamplingTime();
+ * @param pADCx ADC instance
+ * @param pADC_InjInitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC registers are initialized
+ * - ERROR: ADC registers are not initialized
+ */
+ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *pADCx, LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(pADCx));
+ assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(pADC_InjInitStruct->TriggerSource));
+ assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(pADC_InjInitStruct->SequencerLength));
+ if (pADC_InjInitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
+ {
+ assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(pADC_InjInitStruct->SequencerDiscont));
+ }
+ assert_param(IS_LL_ADC_INJ_TRIG_AUTO(pADC_InjInitStruct->TrigAuto));
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* ADC instance must be disabled. */
+ if (LL_ADC_IsEnabled(pADCx) == 0UL)
+ {
+ /* Configuration of ADC hierarchical scope: */
+ /* - ADC group injected */
+ /* - Set ADC group injected trigger source */
+ /* - Set ADC group injected sequencer length */
+ /* - Set ADC group injected sequencer discontinuous mode */
+ /* - Set ADC group injected conversion trigger: independent or */
+ /* from ADC group regular */
+ /* Note: On this STM32 series, ADC trigger edge is set when starting */
+ /* ADC conversion. */
+ /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */
+ if (pADC_InjInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+ {
+ MODIFY_REG(pADCx->CFGR1,
+ ADC_CFGR1_JDISCEN | ADC_CFGR1_JAUTO,
+ pADC_InjInitStruct->SequencerDiscont | pADC_InjInitStruct->TrigAuto
+ );
+ }
+ else
+ {
+ MODIFY_REG(pADCx->CFGR1,
+ ADC_CFGR1_JDISCEN | ADC_CFGR1_JAUTO,
+ LL_ADC_REG_SEQ_DISCONT_DISABLE | pADC_InjInitStruct->TrigAuto
+ );
+ }
+
+ MODIFY_REG(pADCx->JSQR,
+ ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN | ADC_JSQR_JL,
+ pADC_InjInitStruct->TriggerSource | pADC_InjInitStruct->SequencerLength
+ );
+ }
+ else
+ {
+ /* Initialization error: ADC instance is not disabled. */
+ status = ERROR;
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
+ * @param pADC_InjInitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct)
+{
+ /* Set pADC_InjInitStruct fields to default values */
+ /* Set fields of ADC group injected */
+ pADC_InjInitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
+ pADC_InjInitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
+ pADC_InjInitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
+ pADC_InjInitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* ADC1 || ADC2 || ADC4 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_comp.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_comp.c
new file mode 100644
index 00000000..8bb9c244
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_comp.c
@@ -0,0 +1,255 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_comp.c
+ * @author MCD Application Team
+ * @brief COMP LL module driver
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_ll_comp.h"
+
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined (COMP1) || defined (COMP2)
+
+/** @addtogroup COMP_LL COMP
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup COMP_LL_Private_Macros
+ * @{
+ */
+
+/* Check of parameters for configuration of COMP hierarchical scope: */
+/* COMP instance. */
+
+#define IS_LL_COMP_POWER_MODE(__POWER_MODE__) \
+ (((__POWER_MODE__) == LL_COMP_POWERMODE_HIGHSPEED) \
+ || ((__POWER_MODE__) == LL_COMP_POWERMODE_MEDIUMSPEED) \
+ || ((__POWER_MODE__) == LL_COMP_POWERMODE_ULTRALOWPOWER) \
+ )
+
+/* Note: On this STM32 series, comparator input plus parameters are */
+/* the same on all COMP instances. */
+/* However, comparator instance kept as macro parameter for */
+/* compatibility with other STM32 families. */
+#define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \
+ (((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \
+ || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2) \
+ || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO3) \
+ )
+
+/* Note: On this STM32 series, comparator input minus parameters are */
+/* the same on all COMP instances. */
+/* However, comparator instance kept as macro parameter for */
+/* compatibility with other STM32 families. */
+#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \
+ (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2) \
+ )
+
+#define IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__) \
+ (((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_NONE) \
+ || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_LOW) \
+ || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_MEDIUM) \
+ || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_HIGH) \
+ )
+
+#define IS_LL_COMP_OUTPUT_POLARITY(__POLARITY__) \
+ (((__POLARITY__) == LL_COMP_OUTPUTPOL_NONINVERTED) \
+ || ((__POLARITY__) == LL_COMP_OUTPUTPOL_INVERTED) \
+ )
+
+#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__OUTPUT_BLANKING_SOURCE__) \
+ (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1) \
+ )
+
+/**
+ * @}
+ */
+
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup COMP_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup COMP_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize registers of the selected COMP instance
+ * to their default reset values.
+ * @note If comparator is locked, de-initialization by software is
+ * not possible.
+ * The only way to unlock the comparator is a device hardware reset.
+ * @param COMPx COMP instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: COMP registers are de-initialized
+ * - ERROR: COMP registers are not de-initialized
+ */
+ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_COMP_ALL_INSTANCE(COMPx));
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* COMP instance must not be locked. */
+ if (LL_COMP_IsLocked(COMPx) == 0UL)
+ {
+ LL_COMP_WriteReg(COMPx, CSR, 0x00000000UL);
+
+ }
+ else
+ {
+ /* Comparator instance is locked: de-initialization by software is */
+ /* not possible. */
+ /* The only way to unlock the comparator is a device hardware reset. */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initialize some features of COMP instance.
+ * @note This function configures features of the selected COMP instance.
+ * Some features are also available at scope COMP common instance
+ * (common to several COMP instances).
+ * Refer to functions having argument "COMPxy_COMMON" as parameter.
+ * @param COMPx COMP instance
+ * @param COMP_InitStruct Pointer to a @ref LL_COMP_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: COMP registers are initialized
+ * - ERROR: COMP registers are not initialized
+ */
+ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_COMP_ALL_INSTANCE(COMPx));
+ assert_param(IS_LL_COMP_POWER_MODE(COMP_InitStruct->PowerMode));
+ assert_param(IS_LL_COMP_INPUT_PLUS(COMPx, COMP_InitStruct->InputPlus));
+ assert_param(IS_LL_COMP_INPUT_MINUS(COMPx, COMP_InitStruct->InputMinus));
+ assert_param(IS_LL_COMP_INPUT_HYSTERESIS(COMP_InitStruct->InputHysteresis));
+ assert_param(IS_LL_COMP_OUTPUT_POLARITY(COMP_InitStruct->OutputPolarity));
+ assert_param(IS_LL_COMP_OUTPUT_BLANKING_SOURCE(COMP_InitStruct->OutputBlankingSource));
+
+ /* Note: Hardware constraint (refer to description of this function) */
+ /* COMP instance must not be locked. */
+ if (LL_COMP_IsLocked(COMPx) == 0UL)
+ {
+ /* Configuration of comparator instance : */
+ /* - PowerMode */
+ /* - InputPlus */
+ /* - InputMinus */
+ /* - InputHysteresis */
+ /* - OutputPolarity */
+ /* - OutputBlankingSource */
+ MODIFY_REG(COMPx->CSR,
+ COMP_CSR_PWRMODE
+ | COMP_CSR_INPSEL
+ | COMP_CSR_INMSEL
+ | COMP_CSR_HYST
+ | COMP_CSR_POLARITY
+ | COMP_CSR_BLANKSEL
+ ,
+ COMP_InitStruct->PowerMode
+ | COMP_InitStruct->InputPlus
+ | COMP_InitStruct->InputMinus
+ | COMP_InitStruct->InputHysteresis
+ | COMP_InitStruct->OutputPolarity
+ | COMP_InitStruct->OutputBlankingSource
+ );
+
+ }
+ else
+ {
+ /* Initialization error: COMP instance is locked. */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_COMP_InitTypeDef field to default value.
+ * @param COMP_InitStruct Pointer to a @ref LL_COMP_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct)
+{
+ /* Set COMP_InitStruct fields to default values */
+ COMP_InitStruct->PowerMode = LL_COMP_POWERMODE_ULTRALOWPOWER;
+ COMP_InitStruct->InputPlus = LL_COMP_INPUT_PLUS_IO1;
+ COMP_InitStruct->InputMinus = LL_COMP_INPUT_MINUS_VREFINT;
+ COMP_InitStruct->InputHysteresis = LL_COMP_HYSTERESIS_NONE;
+ COMP_InitStruct->OutputPolarity = LL_COMP_OUTPUTPOL_NONINVERTED;
+ COMP_InitStruct->OutputBlankingSource = LL_COMP_BLANKINGSRC_NONE;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* COMP1 || COMP2 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_cordic.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_cordic.c
new file mode 100644
index 00000000..2aac578c
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_cordic.c
@@ -0,0 +1,102 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_cordic.c
+ * @author MCD Application Team
+ * @brief CORDIC LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_ll_cordic.h"
+#include "stm32u5xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined(CORDIC)
+
+/** @addtogroup CORDIC_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CORDIC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup CORDIC_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-Initialize CORDIC peripheral registers to their default reset values.
+ * @param CORDICx CORDIC Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: CORDIC registers are de-initialized
+ * - ERROR: CORDIC registers are not de-initialized
+ */
+ErrorStatus LL_CORDIC_DeInit(CORDIC_TypeDef *CORDICx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_CORDIC_ALL_INSTANCE(CORDICx));
+
+ if (CORDICx == CORDIC)
+ {
+ /* Force CORDIC reset */
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CORDIC);
+
+ /* Release CORDIC reset */
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CORDIC);
+ }
+ else
+ {
+ status = ERROR;
+ }
+
+ return (status);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(CORDIC) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_crc.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_crc.c
new file mode 100644
index 00000000..8b5e7fc7
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_crc.c
@@ -0,0 +1,104 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_crc.c
+ * @author MCD Application Team
+ * @brief CRC LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_ll_crc.h"
+#include "stm32u5xx_ll_bus.h"
+
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined (CRC)
+
+/** @addtogroup CRC_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CRC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup CRC_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize CRC registers (Registers restored to their default values).
+ * @param CRCx CRC Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: CRC registers are de-initialized
+ * - ERROR: CRC registers are not de-initialized
+ */
+ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_CRC_ALL_INSTANCE(CRCx));
+
+ if (CRCx == CRC)
+ {
+ /* Force CRC reset */
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CRC);
+
+ /* Release CRC reset */
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CRC);
+ }
+ else
+ {
+ status = ERROR;
+ }
+
+ return (status);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (CRC) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_crs.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_crs.c
new file mode 100644
index 00000000..ed41f2da
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_crs.c
@@ -0,0 +1,83 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_crs.h
+ * @author MCD Application Team
+ * @brief CRS LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_ll_crs.h"
+#include "stm32u5xx_ll_bus.h"
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined(CRS)
+
+/** @defgroup CRS_LL CRS
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CRS_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup CRS_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-Initializes CRS peripheral registers to their default reset values.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: CRS registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_CRS_DeInit(void)
+{
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_CRS);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_CRS);
+
+ return SUCCESS;
+}
+
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(CRS) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dac.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dac.c
new file mode 100644
index 00000000..45737c60
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dac.c
@@ -0,0 +1,296 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_dac.c
+ * @author MCD Application Team
+ * @brief DAC LL module driver
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_ll_dac.h"
+#include "stm32u5xx_ll_bus.h"
+
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined(DAC1)
+
+/** @addtogroup DAC_LL DAC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup DAC_LL_Private_Macros
+ * @{
+ */
+#define IS_LL_DAC_CHANNEL(__DAC_CHANNEL__) \
+ ( ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \
+ || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2) \
+ )
+
+#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \
+ ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM5_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM1_CH1) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM3_CH1) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \
+ )
+
+#define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__) \
+ ( ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \
+ || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \
+ || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
+ )
+
+#define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_MODE__, __WAVE_AUTO_GENERATION_CONFIG__) \
+ ( (((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \
+ && ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0)) \
+ ) \
+ ||(((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
+ && ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095)) \
+ ) \
+ )
+
+#define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__) \
+ ( ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE) \
+ || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \
+ )
+
+#define IS_LL_DAC_OUTPUT_CONNECTION(__OUTPUT_CONNECTION__) \
+ ( ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_GPIO) \
+ || ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_INTERNAL) \
+ )
+
+#define IS_LL_DAC_OUTPUT_MODE(__OUTPUT_MODE__) \
+ ( ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_NORMAL) \
+ || ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD) \
+ )
+
+/**
+ * @}
+ */
+
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DAC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DAC_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize registers of the selected DAC instance
+ * to their default reset values.
+ * @param DACx DAC instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: DAC registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_INSTANCE(DACx));
+
+#ifdef DAC1
+ /* Force reset of DAC clock */
+ LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_DAC1);
+
+ /* Release reset of DAC clock */
+ LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_DAC1);
+#endif /* DAC1 */
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Initialize some features of DAC channel.
+ * @note @ref LL_DAC_Init() aims to ease basic configuration of a DAC channel.
+ * Leaving it ready to be enabled and output:
+ * a level by calling one of
+ * @ref LL_DAC_ConvertData12RightAligned
+ * @ref LL_DAC_ConvertData12LeftAligned
+ * @ref LL_DAC_ConvertData8RightAligned
+ * or one of the supported autogenerated wave.
+ * @note This function allows configuration of:
+ * - Output mode
+ * - Trigger
+ * - Wave generation
+ * @note The setting of these parameters by function @ref LL_DAC_Init()
+ * is conditioned to DAC state:
+ * DAC channel must be disabled.
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @param DAC_InitStruct Pointer to a @ref LL_DAC_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: DAC registers are initialized
+ * - ERROR: DAC registers are not initialized
+ */
+ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_INSTANCE(DACx));
+ assert_param(IS_LL_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_LL_DAC_TRIGGER_SOURCE(DAC_InitStruct->TriggerSource));
+ assert_param(IS_LL_DAC_OUTPUT_BUFFER(DAC_InitStruct->OutputBuffer));
+ assert_param(IS_LL_DAC_OUTPUT_CONNECTION(DAC_InitStruct->OutputConnection));
+ assert_param(IS_LL_DAC_OUTPUT_MODE(DAC_InitStruct->OutputMode));
+ assert_param(IS_LL_DAC_WAVE_AUTO_GENER_MODE(DAC_InitStruct->WaveAutoGeneration));
+ if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
+ {
+ assert_param(IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(DAC_InitStruct->WaveAutoGeneration,
+ DAC_InitStruct->WaveAutoGenerationConfig));
+ }
+
+ /* Note: Hardware constraint (refer to description of this function) */
+ /* DAC instance must be disabled. */
+ if (LL_DAC_IsEnabled(DACx, DAC_Channel) == 0UL)
+ {
+ /* Configuration of DAC channel: */
+ /* - TriggerSource */
+ /* - WaveAutoGeneration */
+ /* - OutputBuffer */
+ /* - OutputConnection */
+ /* - OutputMode */
+ if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
+ {
+ MODIFY_REG(DACx->CR,
+ (DAC_CR_TSEL1
+ | DAC_CR_WAVE1
+ | DAC_CR_MAMP1
+ ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ ,
+ (DAC_InitStruct->TriggerSource
+ | DAC_InitStruct->WaveAutoGeneration
+ | DAC_InitStruct->WaveAutoGenerationConfig
+ ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+ }
+ else
+ {
+ MODIFY_REG(DACx->CR,
+ (DAC_CR_TSEL1
+ | DAC_CR_WAVE1
+ ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ ,
+ (DAC_InitStruct->TriggerSource
+ | LL_DAC_WAVE_AUTO_GENERATION_NONE
+ ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+ }
+ MODIFY_REG(DACx->MCR,
+ (DAC_MCR_MODE1_1
+ | DAC_MCR_MODE1_0
+ | DAC_MCR_MODE1_2
+ ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ ,
+ (DAC_InitStruct->OutputBuffer
+ | DAC_InitStruct->OutputConnection
+ | DAC_InitStruct->OutputMode
+ ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+ }
+ else
+ {
+ /* Initialization error: DAC instance is not disabled. */
+ status = ERROR;
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_DAC_InitTypeDef field to default value.
+ * @param DAC_InitStruct pointer to a @ref LL_DAC_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct)
+{
+ /* Set DAC_InitStruct fields to default values */
+ DAC_InitStruct->TriggerSource = LL_DAC_TRIG_SOFTWARE;
+ DAC_InitStruct->WaveAutoGeneration = LL_DAC_WAVE_AUTO_GENERATION_NONE;
+ /* Note: Parameter discarded if wave auto generation is disabled, */
+ /* set anyway to its default value. */
+ DAC_InitStruct->WaveAutoGenerationConfig = LL_DAC_NOISE_LFSR_UNMASK_BIT0;
+ DAC_InitStruct->OutputBuffer = LL_DAC_OUTPUT_BUFFER_ENABLE;
+ DAC_InitStruct->OutputConnection = LL_DAC_OUTPUT_CONNECT_GPIO;
+ DAC_InitStruct->OutputMode = LL_DAC_OUTPUT_MODE_NORMAL;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* DAC1 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dlyb.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dlyb.c
new file mode 100644
index 00000000..7cec0a73
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dlyb.c
@@ -0,0 +1,241 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_dlyb.c
+ * @author MCD Application Team
+ * @brief DelayBlock Low Layer HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the DelayBlock peripheral:
+ * + input clock frequency
+ * + up to 12 oversampling phases
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### DelayBlock peripheral features #####
+ ==============================================================================
+ [..] The DelayBlock is used to generate an Output clock which is de-phased from the Input
+ clock. The phase of the Output clock is programmed by FW. The Output clock is then used
+ to clock the receive data in i.e. a SDMMC, OSPI or QSPI interface.
+ The delay is Voltage and Temperature dependent, which may require FW to do re-tuning
+ and recenter the Output clock phase to the receive data.
+
+ [..] The DelayBlock features include the following:
+ (+) Input clock frequency.
+ (+) Up to 12 oversampling phases.
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This driver is a considered as a driver of service for external devices drivers
+ that interfaces with the DELAY peripheral.
+ The LL_DLYB_SetDelay() function, configure the Delay value configured on SEL and UNIT.
+ The LL_DLYB_GetDelay() function, return the Delay value configured on SEL and UNIT.
+ The LL_DLYB_GetClockPeriod()function, get the clock period.
+
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup DLYB DLYB
+ * @brief DLYB LL module driver.
+ * @{
+ */
+
+#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_QSPI_MODULE_ENABLED)|| defined(HAL_OSPI_MODULE_ENABLED)
+
+/**
+ @cond 0
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define DLYB_TIMEOUT 0xFFU
+#define DLYB_LNG_10_0_MASK 0x07FF0000U
+#define DLYB_LNG_11_10_MASK 0x0C000000U
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/**
+ @endcond
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup DLYB_LL_Exported_Functions
+ * @brief Configuration and control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to
+ (+) Control the DLYB.
+@endverbatim
+ * @{
+ */
+
+/** @addtogroup DLYB_Control_Functions DLYB Control functions
+ * @{
+ */
+
+/**
+ * @brief Set the Delay value configured on SEL and UNIT.
+ * @param DLYBx: Pointer to DLYB instance.
+ * @param pdlyb_cfg: Pointer to DLYB configuration structure.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: the Delay value is set.
+ * - ERROR: the Delay value is not set.
+ */
+void LL_DLYB_SetDelay(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg)
+{
+ /* Check the DelayBlock instance */
+ assert_param(IS_DLYB_ALL_INSTANCE(DLYBx));
+
+ /* Enable the length sampling */
+ SET_BIT(DLYBx->CR, DLYB_CR_SEN);
+
+ /* Update the UNIT and SEL field */
+ DLYBx->CFGR = (pdlyb_cfg->PhaseSel) | ((pdlyb_cfg->Units) << DLYB_CFGR_UNIT_Pos);
+
+ /* Disable the length sampling */
+ CLEAR_BIT(DLYBx->CR, DLYB_CR_SEN);
+}
+
+/**
+ * @brief Get the Delay value configured on SEL and UNIT.
+ * @param DLYBx: Pointer to DLYB instance.
+ * @param pdlyb_cfg: Pointer to DLYB configuration structure.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: the Delay value is received.
+ * - ERROR: the Delay value is not received.
+ */
+void LL_DLYB_GetDelay(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg)
+{
+ /* Check the DelayBlock instance */
+ assert_param(IS_DLYB_ALL_INSTANCE(DLYBx));
+
+ /* Fill the DelayBlock configuration structure with SEL and UNIT value */
+ pdlyb_cfg->Units = ((DLYBx->CFGR & DLYB_CFGR_UNIT) >> DLYB_CFGR_UNIT_Pos);
+ pdlyb_cfg->PhaseSel = (DLYBx->CFGR & DLYB_CFGR_SEL);
+}
+
+/**
+ * @brief Get the clock period.
+ * @param DLYBx: Pointer to DLYB instance.
+ * @param pdlyb_cfg: Pointer to DLYB configuration structure.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: there is a valid period detected and stored in pdlyb_cfg.
+ * - ERROR: there is no valid period detected.
+ */
+uint32_t LL_DLYB_GetClockPeriod(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg)
+{
+ uint32_t i = 0U;
+ uint32_t nb ;
+ uint32_t lng ;
+ uint32_t tickstart;
+
+ /* Check the DelayBlock instance */
+ assert_param(IS_DLYB_ALL_INSTANCE(DLYBx));
+
+ /* Enable the length sampling */
+ SET_BIT(DLYBx->CR, DLYB_CR_SEN);
+
+ /* Delay line length detection */
+ while (i < DLYB_MAX_UNIT)
+ {
+ /* Set the Delay of the UNIT(s)*/
+ DLYBx->CFGR = DLYB_MAX_SELECT | (i << DLYB_CFGR_UNIT_Pos);
+
+ /* Waiting for a LNG valid value */
+ tickstart = HAL_GetTick();
+ while ((DLYBx->CFGR & DLYB_CFGR_LNGF) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) >= DLYB_TIMEOUT)
+ {
+ /* New check to avoid false timeout detection in case of preemption */
+ if ((DLYBx->CFGR & DLYB_CFGR_LNGF) == 0U)
+ {
+ return (uint32_t) HAL_TIMEOUT;
+ }
+ }
+ }
+
+ if ((DLYBx->CFGR & DLYB_LNG_10_0_MASK) != 0U)
+ {
+ if ((DLYBx->CFGR & (DLYB_CFGR_LNG_11 | DLYB_CFGR_LNG_10)) != DLYB_LNG_11_10_MASK)
+ {
+ /* Delay line length is configured to one input clock period*/
+ break;
+ }
+ }
+ i++;
+ }
+
+ if (DLYB_MAX_UNIT != i)
+ {
+ /* Determine how many unit delays (nb) span one input clock period */
+ lng = (DLYBx->CFGR & DLYB_CFGR_LNG) >> 16U;
+ nb = 10U;
+ while ((nb > 0U) && ((lng >> nb) == 0U))
+ {
+ nb--;
+ }
+ if (nb != 0U)
+ {
+ pdlyb_cfg->PhaseSel = nb ;
+ pdlyb_cfg->Units = i ;
+
+ /* Disable the length sampling */
+ DLYBx->CR = DLYB_CR_SEN;
+
+ return (uint32_t)SUCCESS;
+ }
+ }
+
+ /* Disable the length sampling */
+ DLYBx->CR = DLYB_CR_SEN;
+
+ return (uint32_t)ERROR;
+
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* HAL_SD_MODULE_ENABLED || HAL_QSPI_MODULE_ENABLED || HAL_OSPI_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dma.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dma.c
new file mode 100644
index 00000000..3286a2e0
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dma.c
@@ -0,0 +1,1180 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_dma.c
+ * @author MCD Application Team
+ * @brief DMA LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### LL DMA driver acronyms #####
+ ==============================================================================
+ [..] Acronyms table :
+ =========================================
+ || Acronym || ||
+ =========================================
+ || SRC || Source ||
+ || DEST || Destination ||
+ || ADDR || Address ||
+ || ADDRS || Addresses ||
+ || INC || Increment / Incremented ||
+ || DEC || Decrement / Decremented ||
+ || BLK || Block ||
+ || RPT || Repeat / Repeated ||
+ || TRIG || Trigger ||
+ =========================================
+ @endverbatim
+ ******************************************************************************
+ */
+
+#if defined (USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_ll_dma.h"
+#include "stm32u5xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if (defined (GPDMA1) || defined (LPDMA1))
+
+/** @addtogroup DMA_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup DMA_LL_Private_Macros
+ * @{
+ */
+#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, Channel) ((((INSTANCE) == GPDMA1) && \
+ (((Channel) == LL_DMA_CHANNEL_0) || \
+ ((Channel) == LL_DMA_CHANNEL_1) || \
+ ((Channel) == LL_DMA_CHANNEL_2) || \
+ ((Channel) == LL_DMA_CHANNEL_3) || \
+ ((Channel) == LL_DMA_CHANNEL_4) || \
+ ((Channel) == LL_DMA_CHANNEL_5) || \
+ ((Channel) == LL_DMA_CHANNEL_6) || \
+ ((Channel) == LL_DMA_CHANNEL_7) || \
+ ((Channel) == LL_DMA_CHANNEL_8) || \
+ ((Channel) == LL_DMA_CHANNEL_9) || \
+ ((Channel) == LL_DMA_CHANNEL_10) || \
+ ((Channel) == LL_DMA_CHANNEL_11) || \
+ ((Channel) == LL_DMA_CHANNEL_12) || \
+ ((Channel) == LL_DMA_CHANNEL_13) || \
+ ((Channel) == LL_DMA_CHANNEL_14) || \
+ ((Channel) == LL_DMA_CHANNEL_15) || \
+ ((Channel) == LL_DMA_CHANNEL_ALL))) || \
+ (((INSTANCE) == LPDMA1) && \
+ (((Channel) == LL_DMA_CHANNEL_0) || \
+ ((Channel) == LL_DMA_CHANNEL_1) || \
+ ((Channel) == LL_DMA_CHANNEL_2) || \
+ ((Channel) == LL_DMA_CHANNEL_3) || \
+ ((Channel) == LL_DMA_CHANNEL_ALL))))
+
+
+#define IS_LL_GPDMA_CHANNEL_INSTANCE(INSTANCE, Channel) (((INSTANCE) == GPDMA1) && \
+ (((Channel) == LL_DMA_CHANNEL_0) || \
+ ((Channel) == LL_DMA_CHANNEL_1) || \
+ ((Channel) == LL_DMA_CHANNEL_2) || \
+ ((Channel) == LL_DMA_CHANNEL_3) || \
+ ((Channel) == LL_DMA_CHANNEL_4) || \
+ ((Channel) == LL_DMA_CHANNEL_5) || \
+ ((Channel) == LL_DMA_CHANNEL_6) || \
+ ((Channel) == LL_DMA_CHANNEL_7) || \
+ ((Channel) == LL_DMA_CHANNEL_8) || \
+ ((Channel) == LL_DMA_CHANNEL_9) || \
+ ((Channel) == LL_DMA_CHANNEL_10) || \
+ ((Channel) == LL_DMA_CHANNEL_11) || \
+ ((Channel) == LL_DMA_CHANNEL_12) || \
+ ((Channel) == LL_DMA_CHANNEL_13) || \
+ ((Channel) == LL_DMA_CHANNEL_14) || \
+ ((Channel) == LL_DMA_CHANNEL_15)))
+
+#define IS_LL_DMA_2D_CHANNEL_INSTANCE(INSTANCE, Channel) (((INSTANCE) == GPDMA1) && \
+ (((Channel) == LL_DMA_CHANNEL_12) || \
+ ((Channel) == LL_DMA_CHANNEL_13) || \
+ ((Channel) == LL_DMA_CHANNEL_14) || \
+ ((Channel) == LL_DMA_CHANNEL_15)))
+
+#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY) || \
+ ((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
+ ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH))
+
+#define IS_LL_DMA_DATA_ALIGNMENT(__VALUE__) (((__VALUE__) == LL_DMA_DATA_ALIGN_ZEROPADD) || \
+ ((__VALUE__) == LL_DMA_DATA_ALIGN_SIGNEXTPADD) || \
+ ((__VALUE__) == LL_DMA_DATA_PACK_UNPACK))
+
+#define IS_LL_DMA_BURST_LENGTH(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= 64U))
+
+#define IS_LL_DMA_SRC_DATA_WIDTH(__VALUE__) (((__VALUE__) == LL_DMA_SRC_DATAWIDTH_BYTE) || \
+ ((__VALUE__) == LL_DMA_SRC_DATAWIDTH_HALFWORD) || \
+ ((__VALUE__) == LL_DMA_SRC_DATAWIDTH_WORD))
+
+#define IS_LL_DMA_DEST_DATA_WIDTH(__VALUE__) (((__VALUE__) == LL_DMA_DEST_DATAWIDTH_BYTE) || \
+ ((__VALUE__) == LL_DMA_DEST_DATAWIDTH_HALFWORD) || \
+ ((__VALUE__) == LL_DMA_DEST_DATAWIDTH_WORD))
+
+#define IS_LL_DMA_SRC_INCREMENT_MODE(__VALUE__) (((__VALUE__) == LL_DMA_SRC_FIXED) || \
+ ((__VALUE__) == LL_DMA_SRC_INCREMENT))
+
+#define IS_LL_DMA_DEST_INCREMENT_MODE(__VALUE__) (((__VALUE__) == LL_DMA_DEST_FIXED) || \
+ ((__VALUE__) == LL_DMA_DEST_INCREMENT))
+
+#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_LOW_PRIORITY_LOW_WEIGHT) || \
+ ((__VALUE__) == LL_DMA_LOW_PRIORITY_MID_WEIGHT) || \
+ ((__VALUE__) == LL_DMA_LOW_PRIORITY_HIGH_WEIGHT) || \
+ ((__VALUE__) == LL_DMA_HIGH_PRIORITY))
+
+#define IS_LL_DMA_BLK_DATALENGTH(__VALUE__) ((__VALUE__) <= 0xFFFFU)
+
+#define IS_LL_DMA_BLK_REPEATCOUNT(__VALUE__) ((__VALUE__) <= 0x0EFFU)
+
+#define IS_LL_DMA_TRIGGER_MODE(__VALUE__) (((__VALUE__) == LL_DMA_TRIGM_BLK_TRANSFER) || \
+ ((__VALUE__) == LL_DMA_TRIGM_RPT_BLK_TRANSFER) || \
+ ((__VALUE__) == LL_DMA_TRIGM_LLI_LINK_TRANSFER) || \
+ ((__VALUE__) == LL_DMA_TRIGM_SINGLBURST_TRANSFER ))
+
+#define IS_LL_DMA_TRIGGER_POLARITY(__VALUE__) (((__VALUE__) == LL_DMA_TRIG_POLARITY_MASKED) || \
+ ((__VALUE__) == LL_DMA_TRIG_POLARITY_RISING) || \
+ ((__VALUE__) == LL_DMA_TRIG_POLARITY_FALLING))
+
+#define IS_LL_DMA_BLKHW_REQUEST(__VALUE__) (((__VALUE__) == LL_DMA_HWREQUEST_SINGLEBURST) || \
+ ((__VALUE__) == LL_DMA_HWREQUEST_BLK))
+
+#define IS_LL_DMA_TRIGGER_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_TRIGGER_TIM15_TRGO)
+
+#define IS_LL_DMA_REQUEST_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_REQUEST_LPTIM3_UE)
+
+#define IS_LL_DMA_TRANSFER_EVENT_MODE(__VALUE__) (((__VALUE__) == LL_DMA_TCEM_BLK_TRANSFER) || \
+ ((__VALUE__) == LL_DMA_TCEM_RPT_BLK_TRANSFER) || \
+ ((__VALUE__) == LL_DMA_TCEM_EACH_LLITEM_TRANSFER) || \
+ ((__VALUE__) == LL_DMA_TCEM_LAST_LLITEM_TRANSFER))
+
+#define IS_LL_DMA_DEST_HALFWORD_EXCHANGE(__VALUE__) (((__VALUE__) == LL_DMA_DEST_HALFWORD_PRESERVE) || \
+ ((__VALUE__) == LL_DMA_DEST_HALFWORD_EXCHANGE))
+
+#define IS_LL_DMA_DEST_BYTE_EXCHANGE(__VALUE__) (((__VALUE__) == LL_DMA_DEST_BYTE_PRESERVE) || \
+ ((__VALUE__) == LL_DMA_DEST_BYTE_EXCHANGE))
+
+#define IS_LL_DMA_SRC_BYTE_EXCHANGE(__VALUE__) (((__VALUE__) == LL_DMA_SRC_BYTE_PRESERVE) || \
+ ((__VALUE__) == LL_DMA_SRC_BYTE_EXCHANGE))
+
+#define IS_LL_DMA_LINK_ALLOCATED_PORT(__VALUE__) (((__VALUE__) == LL_DMA_LINK_ALLOCATED_PORT0) || \
+ ((__VALUE__) == LL_DMA_LINK_ALLOCATED_PORT1))
+
+#define IS_LL_DMA_SRC_ALLOCATED_PORT(__VALUE__) (((__VALUE__) == LL_DMA_SRC_ALLOCATED_PORT0) || \
+ ((__VALUE__) == LL_DMA_SRC_ALLOCATED_PORT1))
+
+#define IS_LL_DMA_DEST_ALLOCATED_PORT(__VALUE__) (((__VALUE__) == LL_DMA_DEST_ALLOCATED_PORT0) || \
+ ((__VALUE__) == LL_DMA_DEST_ALLOCATED_PORT1))
+
+#define IS_LL_DMA_LINK_STEP_MODE(__VALUE__) (((__VALUE__) == LL_DMA_LSM_FULL_EXECUTION) || \
+ ((__VALUE__) == LL_DMA_LSM_1LINK_EXECUTION))
+
+#define IS_LL_DMA_BURST_SRC_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BURST_SRC_ADDR_INCREMENT) || \
+ ((__VALUE__) == LL_DMA_BURST_SRC_ADDR_DECREMENT))
+
+#define IS_LL_DMA_BURST_DEST_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BURST_DEST_ADDR_INCREMENT) || \
+ ((__VALUE__) == LL_DMA_BURST_DEST_ADDR_DECREMENT))
+
+#define IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(__VALUE__) ((__VALUE__) <= 0x1FFFU)
+
+#define IS_LL_DMA_BLKRPT_SRC_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BLKRPT_SRC_ADDR_INCREMENT) || \
+ ((__VALUE__) == LL_DMA_BLKRPT_SRC_ADDR_DECREMENT))
+
+#define IS_LL_DMA_BLKRPT_DEST_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BLKRPT_DEST_ADDR_INCREMENT) || \
+ ((__VALUE__) == LL_DMA_BLKRPT_DEST_ADDR_DECREMENT))
+
+#define IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(__VALUE__) ((__VALUE__) <= 0xFFFFU)
+
+#define IS_LL_DMA_LINK_BASEADDR(__VALUE__) (((__VALUE__) & 0xFFFFU) == 0U)
+
+#define IS_LL_DMA_LINK_ADDR_OFFSET(__VALUE__) (((__VALUE__) & 0x03U) == 0U)
+
+#define IS_LL_DMA_LINK_UPDATE_REGISTERS(__VALUE__) ((((__VALUE__) & 0x01FE0000U) == 0U) && ((__VALUE__) != 0U))
+
+#define IS_LL_DMA_LINK_NODETYPE(__VALUE__) (((__VALUE__) == LL_DMA_GPDMA_2D_NODE) || \
+ ((__VALUE__) == LL_DMA_GPDMA_LINEAR_NODE) || \
+ ((__VALUE__) == LL_DMA_LPDMA_LINEAR_NODE))
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define IS_LL_DMA_CHANNEL_SRC_SEC(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_SRC_NSEC) || \
+ ((__VALUE__) == LL_DMA_CHANNEL_SRC_SEC))
+
+#define IS_LL_DMA_CHANNEL_DEST_SEC(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_DEST_NSEC) || \
+ ((__VALUE__) == LL_DMA_CHANNEL_DEST_SEC))
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup DMA_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DMA_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the DMA registers to their default reset values.
+ * @note This API is used for all available DMA channels.
+ * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use
+ * helper macros :
+ * @arg @ref LL_DMA_GET_INSTANCE
+ * @arg @ref LL_DMA_GET_CHANNEL
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS : DMA registers are de-initialized.
+ * - ERROR : DMA registers are not de-initialized.
+ */
+uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ DMA_Channel_TypeDef *tmp;
+ ErrorStatus status = SUCCESS;
+
+ /* Check the DMA Instance DMAx and Channel parameters */
+ assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
+
+ if (Channel == LL_DMA_CHANNEL_ALL)
+ {
+ if (DMAx == GPDMA1)
+ {
+ /* Force reset of DMA clock */
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPDMA1);
+
+ /* Release reset of DMA clock */
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPDMA1);
+ }
+ else
+ {
+ /* Force reset of DMA clock */
+ LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_LPDMA1);
+
+ /* Release reset of DMA clock */
+ LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_LPDMA1);
+ }
+ }
+ else
+ {
+ /* Get the DMA Channel Instance */
+ tmp = (DMA_Channel_TypeDef *)(LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
+
+ /* Suspend DMA channel */
+ LL_DMA_SuspendChannel(DMAx, Channel);
+
+ /* Disable the selected Channel */
+ LL_DMA_ResetChannel(DMAx, Channel);
+
+ /* Reset DMAx_Channely control register */
+ LL_DMA_WriteReg(tmp, CLBAR, 0U);
+
+ /* Reset DMAx_Channely control register */
+ LL_DMA_WriteReg(tmp, CCR, 0U);
+
+ /* Reset DMAx_Channely Configuration register */
+ LL_DMA_WriteReg(tmp, CTR1, 0U);
+
+ /* Reset DMAx_Channely transfer register 2 */
+ LL_DMA_WriteReg(tmp, CTR2, 0U);
+
+ /* Reset DMAx_Channely block number of data register */
+ LL_DMA_WriteReg(tmp, CBR1, 0U);
+
+ /* Reset DMAx_Channely source address register */
+ LL_DMA_WriteReg(tmp, CSAR, 0U);
+
+ /* Reset DMAx_Channely destination address register */
+ LL_DMA_WriteReg(tmp, CDAR, 0U);
+
+ /* Check DMA channel */
+ if (IS_LL_DMA_2D_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
+ {
+ /* Reset DMAx_Channely transfer register 3 */
+ LL_DMA_WriteReg(tmp, CTR3, 0U);
+
+ /* Reset DMAx_Channely Block register 2 */
+ LL_DMA_WriteReg(tmp, CBR2, 0U);
+ }
+
+ /* Reset DMAx_Channely Linked list address register */
+ LL_DMA_WriteReg(tmp, CLLR, 0U);
+
+ /* Reset DMAx_Channely pending flags */
+ LL_DMA_WriteReg(tmp, CFCR, 0x00003F00U);
+
+ /* Reset DMAx_Channely attribute */
+ LL_DMA_DisableChannelPrivilege(DMAx, Channel);
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ LL_DMA_DisableChannelSecure(DMAx, Channel);
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+ }
+
+ return (uint32_t)status;
+}
+
+/**
+ * @brief Initialize the DMA registers according to the specified parameters
+ * in DMA_InitStruct.
+ * @note This API is used for all available DMA channels.
+ * @note A software request transfer can be done once programming the direction
+ * field in memory to memory value.
+ * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use
+ * helper macros :
+ * @arg @ref LL_DMA_GET_INSTANCE
+ * @arg @ref LL_DMA_GET_CHANNEL
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS : DMA registers are initialized.
+ * - ERROR : Not applicable.
+ */
+uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
+{
+ /* Check the DMA Instance DMAx and Channel parameters*/
+ assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
+
+ /* Check the DMA parameters from DMA_InitStruct */
+ assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
+
+ /* Check direction */
+ if (DMA_InitStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY)
+ {
+ assert_param(IS_LL_DMA_REQUEST_SELECTION(DMA_InitStruct->Request));
+ }
+
+ assert_param(IS_LL_DMA_DATA_ALIGNMENT(DMA_InitStruct->DataAlignment));
+ assert_param(IS_LL_DMA_SRC_DATA_WIDTH(DMA_InitStruct->SrcDataWidth));
+ assert_param(IS_LL_DMA_DEST_DATA_WIDTH(DMA_InitStruct->DestDataWidth));
+ assert_param(IS_LL_DMA_SRC_INCREMENT_MODE(DMA_InitStruct->SrcIncMode));
+ assert_param(IS_LL_DMA_DEST_INCREMENT_MODE(DMA_InitStruct->DestIncMode));
+ assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
+ assert_param(IS_LL_DMA_BLK_DATALENGTH(DMA_InitStruct->BlkDataLength));
+ assert_param(IS_LL_DMA_TRIGGER_POLARITY(DMA_InitStruct->TriggerPolarity));
+ assert_param(IS_LL_DMA_BLKHW_REQUEST(DMA_InitStruct->BlkHWRequest));
+ assert_param(IS_LL_DMA_TRANSFER_EVENT_MODE(DMA_InitStruct->TransferEventMode));
+ assert_param(IS_LL_DMA_LINK_STEP_MODE(DMA_InitStruct->LinkStepMode));
+ assert_param(IS_LL_DMA_LINK_BASEADDR(DMA_InitStruct->LinkedListBaseAddr));
+ assert_param(IS_LL_DMA_LINK_ADDR_OFFSET(DMA_InitStruct->LinkedListAddrOffset));
+
+ /* Check DMA instance */
+ if (IS_LL_GPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
+ {
+ assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitStruct->SrcBurstLength));
+ assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitStruct->DestBurstLength));
+ assert_param(IS_LL_DMA_DEST_HALFWORD_EXCHANGE(DMA_InitStruct->DestHWordExchange));
+ assert_param(IS_LL_DMA_DEST_BYTE_EXCHANGE(DMA_InitStruct->DestByteExchange));
+ assert_param(IS_LL_DMA_SRC_BYTE_EXCHANGE(DMA_InitStruct->SrcByteExchange));
+ assert_param(IS_LL_DMA_LINK_ALLOCATED_PORT(DMA_InitStruct->LinkAllocatedPort));
+ assert_param(IS_LL_DMA_SRC_ALLOCATED_PORT(DMA_InitStruct->SrcAllocatedPort));
+ assert_param(IS_LL_DMA_DEST_ALLOCATED_PORT(DMA_InitStruct->DestAllocatedPort));
+ }
+
+ /* Check trigger polarity */
+ if (DMA_InitStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED)
+ {
+ assert_param(IS_LL_DMA_TRIGGER_MODE(DMA_InitStruct->TriggerMode));
+ assert_param(IS_LL_DMA_TRIGGER_SELECTION(DMA_InitStruct->TriggerSelection));
+ }
+
+ /* Check DMA channel */
+ if (IS_LL_DMA_2D_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
+ {
+ assert_param(IS_LL_DMA_BLK_REPEATCOUNT(DMA_InitStruct->BlkRptCount));
+ assert_param(IS_LL_DMA_BURST_SRC_ADDR_UPDATE(DMA_InitStruct->SrcAddrUpdateMode));
+ assert_param(IS_LL_DMA_BURST_DEST_ADDR_UPDATE(DMA_InitStruct->DestAddrUpdateMode));
+ assert_param(IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(DMA_InitStruct->SrcAddrOffset));
+ assert_param(IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(DMA_InitStruct->DestAddrOffset));
+ assert_param(IS_LL_DMA_BLKRPT_SRC_ADDR_UPDATE(DMA_InitStruct->BlkRptSrcAddrUpdateMode));
+ assert_param(IS_LL_DMA_BLKRPT_DEST_ADDR_UPDATE(DMA_InitStruct->BlkRptDestAddrUpdateMode));
+ assert_param(IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(DMA_InitStruct->BlkRptSrcAddrOffset));
+ assert_param(IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(DMA_InitStruct->BlkRptDestAddrOffset));
+ }
+
+ /*-------------------------- DMAx CLBAR Configuration ------------------------
+ * Configure the Transfer linked list address with parameter :
+ * - LinkedListBaseAdd: DMA_CLBAR_LBA[31:16] bits
+ */
+ LL_DMA_SetLinkedListBaseAddr(DMAx, Channel, DMA_InitStruct->LinkedListBaseAddr);
+
+ /*-------------------------- DMAx CCR Configuration --------------------------
+ * Configure the control parameter :
+ * - LinkAllocatedPort: DMA_CCR_LAP bit
+ * LinkAllocatedPort field is not supported by LPDMA channels.
+ * - LinkStepMode: DMA_CCR_LSM bit
+ * - Priority: DMA_CCR_PRIO [23:22] bits
+ */
+ LL_DMA_ConfigControl(DMAx, Channel, DMA_InitStruct->Priority | \
+ DMA_InitStruct->LinkAllocatedPort | \
+ DMA_InitStruct->LinkStepMode);
+
+ /*-------------------------- DMAx CTR1 Configuration -------------------------
+ * Configure the Data transfer parameter :
+ * - DestAllocatedPort: DMA_CTR1_DAP bit
+ * DestAllocatedPort field is not supported by LPDMA channels.
+ * - DestHWordExchange: DMA_CTR1_DHX bit
+ * DestHWordExchange field is not supported by LPDMA channels.
+ * - DestByteExchange: DMA_CTR1_DBX bit
+ * DestByteExchange field is not supported by LPDMA channels.
+ * - DestIncMode: DMA_CTR1_DINC bit
+ * - DestDataWidth: DMA_CTR1_DDW_LOG2 [17:16] bits
+ * - SrcAllocatedPort: DMA_CTR1_SAP bit
+ * SrcAllocatedPort field is not supported by LPDMA channels.
+ * - SrcByteExchange: DMA_CTR1_SBX bit
+ * SrcByteExchange field is not supported by LPDMA channels.
+ * - DataAlignment: DMA_CTR1_PAM [12:11] bits
+ * DataAlignment field is reduced to one bit by LPDMA channels.
+ * - SrcIncMode: DMA_CTR1_SINC bit
+ * - SrcDataWidth: DMA_CTR1_SDW_LOG2 [1:0] bits
+ * - SrcBurstLength: DMA_CTR1_SBL_1 [9:4] bits
+ * SrcBurstLength field is not supported by LPDMA channels.
+ * - DestBurstLength: DMA_CTR1_DBL_1 [25:20] bits
+ * DestBurstLength field is not supported by LPDMA channels.
+ */
+ LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->DestAllocatedPort | \
+ DMA_InitStruct->DestHWordExchange | \
+ DMA_InitStruct->DestByteExchange | \
+ DMA_InitStruct->DestIncMode | \
+ DMA_InitStruct->DestDataWidth | \
+ DMA_InitStruct->SrcAllocatedPort | \
+ DMA_InitStruct->SrcByteExchange | \
+ DMA_InitStruct->DataAlignment | \
+ DMA_InitStruct->SrcIncMode | \
+ DMA_InitStruct->SrcDataWidth);
+ /* Check DMA instance */
+ if (IS_LL_GPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
+ {
+ LL_DMA_ConfigBurstLength(DMAx, Channel, DMA_InitStruct->SrcBurstLength,
+ DMA_InitStruct->DestBurstLength);
+ }
+
+ /*-------------------------- DMAx CTR2 Configuration -------------------------
+ * Configure the channel transfer parameter :
+ * - TransferEventMode: DMA_CTR2_TCEM [31:30] bits
+ * - TriggerPolarity: DMA_CTR2_TRIGPOL [25:24] bits
+ * - TriggerMode: DMA_CTR2_TRIGM [15:14] bits
+ * - BlkHWRequest: DMA_CTR2_BREQ bit
+ * - Direction: DMA_CTR2_DREQ bit
+ * - Direction: DMA_CTR2_SWREQ bit
+ * Direction field is reduced to one bit for LPDMA channels (SWREQ).
+ * - TriggerSelection: DMA_CTR2_TRIGSEL [21:16] bits
+ * TriggerSelection field is reduced to 5 bits for LPDMA channels.
+ * - Request: DMA_CTR2_REQSEL [6:0] bits
+ * Request field is reduced to 5 bits for LPDMA channels.
+ */
+ LL_DMA_ConfigChannelTransfer(DMAx, Channel, DMA_InitStruct->TransferEventMode | \
+ DMA_InitStruct->TriggerPolarity | \
+ DMA_InitStruct->BlkHWRequest | \
+ DMA_InitStruct->Direction);
+
+ /* Check direction */
+ if (DMA_InitStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY)
+ {
+ LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->Request);
+ }
+
+ /* Check trigger polarity */
+ if (DMA_InitStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED)
+ {
+ LL_DMA_SetHWTrigger(DMAx, Channel, DMA_InitStruct->TriggerSelection);
+ LL_DMA_SetTriggerMode(DMAx, Channel, DMA_InitStruct->TriggerMode);
+ }
+
+ /*-------------------------- DMAx CBR1 Configuration -------------------------
+ * Configure the Transfer Block counters and update mode with parameter :
+ * - BlkDataLength: DMA_CBR1_BNDT[15:0] bits
+ * - BlkRptCount: DMA_CBR1_BRC[26:16] bits
+ * BlkRptCount field is supported only by 2D addressing channels.
+ * - BlkRptSrcAddrUpdateMode: DMA_CBR1_BRSDEC bit
+ * BlkRptSrcAddrUpdateMode field is supported only by 2D addressing channels.
+ * - BlkRptDestAddrUpdateMode: DMA_CBR1_BRDDEC bit
+ * BlkRptDestAddrUpdateMode field is supported only by 2D addressing channels.
+ * - SrcAddrUpdateMode: DMA_CBR1_SDEC bit
+ * SrcAddrUpdateMode field is supported only by 2D addressing channels.
+ * - DestAddrUpdateMode: DMA_CBR1_DDEC bit
+ * DestAddrUpdateMode field is supported only by 2D addressing channels.
+ */
+ LL_DMA_SetBlkDataLength(DMAx, Channel, DMA_InitStruct->BlkDataLength);
+
+ /* Check DMA channel */
+ if (IS_LL_DMA_2D_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
+ {
+ LL_DMA_SetBlkRptCount(DMAx, Channel, DMA_InitStruct->BlkRptCount);
+ LL_DMA_ConfigBlkRptAddrUpdate(DMAx, Channel, DMA_InitStruct->BlkRptSrcAddrUpdateMode | \
+ DMA_InitStruct->BlkRptDestAddrUpdateMode | \
+ DMA_InitStruct->SrcAddrUpdateMode | \
+ DMA_InitStruct->DestAddrUpdateMode);
+ }
+
+ /*-------------------------- DMAx CSAR and CDAR Configuration ----------------
+ * Configure the Transfer source address with parameter :
+ * - SrcAddress: DMA_CSAR_SA[31:0] bits
+ * - DestAddress: DMA_CDAR_DA[31:0] bits
+ */
+ LL_DMA_ConfigAddresses(DMAx, Channel, DMA_InitStruct->SrcAddress, DMA_InitStruct->DestAddress);
+
+ /* Check DMA channel */
+ if (IS_LL_DMA_2D_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
+ {
+ /*------------------------ DMAx CTR3 Configuration -------------------------
+ * Configure the Transfer Block counters and update mode with parameter :
+ * - SrcAddrOffset: DMA_CTR3_SAO[28:16] bits
+ * SrcAddrOffset field is supported only by 2D addressing channels.
+ * - DestAddrOffset: DMA_CTR3_DAO[12:0] bits
+ * DestAddrOffset field is supported only by 2D addressing channels.
+ */
+ LL_DMA_ConfigAddrUpdateValue(DMAx, Channel, DMA_InitStruct->SrcAddrOffset, DMA_InitStruct->DestAddrOffset);
+
+ /*------------------------ DMAx CBR2 Configuration -----------------------
+ * Configure the Transfer Block counters and update mode with parameter :
+ * - BlkRptSrcAddrOffset: DMA_CBR2_BRSAO[15:0] bits
+ * BlkRptSrcAddrOffset field is supported only by 2D addressing channels.
+ * - BlkRptDestAddrOffset: DMA_CBR2_BRDAO[31:16] bits
+ * BlkRptDestAddrOffset field is supported only by 2D addressing channels.
+ */
+ LL_DMA_ConfigBlkRptAddrUpdateValue(DMAx, Channel, DMA_InitStruct->BlkRptSrcAddrOffset,
+ DMA_InitStruct->BlkRptDestAddrOffset);
+ }
+
+ /*-------------------------- DMAx CLLR Configuration -------------------------
+ * Configure the Transfer linked list address with parameter :
+ * - DestAddrOffset: DMA_CLLR_LA[15:2] bits
+ */
+ LL_DMA_SetLinkedListAddrOffset(DMAx, Channel, DMA_InitStruct->LinkedListAddrOffset);
+
+ return (uint32_t)SUCCESS;
+}
+
+/**
+ * @brief Set each @ref LL_DMA_InitTypeDef field to default value.
+ * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
+ * @retval None.
+ */
+void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
+{
+ /* Set DMA_InitStruct fields to default values */
+ DMA_InitStruct->SrcAddress = 0x00000000U;
+ DMA_InitStruct->DestAddress = 0x00000000U;
+ DMA_InitStruct->Direction = LL_DMA_DIRECTION_MEMORY_TO_MEMORY;
+ DMA_InitStruct->BlkHWRequest = LL_DMA_HWREQUEST_SINGLEBURST;
+ DMA_InitStruct->DataAlignment = LL_DMA_DATA_ALIGN_ZEROPADD;
+ DMA_InitStruct->SrcBurstLength = 1U;
+ DMA_InitStruct->DestBurstLength = 1U;
+ DMA_InitStruct->SrcDataWidth = LL_DMA_SRC_DATAWIDTH_BYTE;
+ DMA_InitStruct->DestDataWidth = LL_DMA_DEST_DATAWIDTH_BYTE;
+ DMA_InitStruct->SrcIncMode = LL_DMA_SRC_FIXED;
+ DMA_InitStruct->DestIncMode = LL_DMA_DEST_FIXED;
+ DMA_InitStruct->Priority = LL_DMA_LOW_PRIORITY_LOW_WEIGHT;
+ DMA_InitStruct->BlkDataLength = 0x00000000U;
+ DMA_InitStruct->BlkRptCount = 0x00000000U;
+ DMA_InitStruct->TriggerMode = LL_DMA_TRIGM_BLK_TRANSFER;
+ DMA_InitStruct->TriggerPolarity = LL_DMA_TRIG_POLARITY_MASKED;
+ DMA_InitStruct->TriggerSelection = 0x00000000U;
+ DMA_InitStruct->Request = 0x00000000U;
+ DMA_InitStruct->TransferEventMode = LL_DMA_TCEM_BLK_TRANSFER;
+ DMA_InitStruct->DestHWordExchange = LL_DMA_DEST_HALFWORD_PRESERVE;
+ DMA_InitStruct->DestByteExchange = LL_DMA_DEST_BYTE_PRESERVE;
+ DMA_InitStruct->SrcByteExchange = LL_DMA_SRC_BYTE_PRESERVE;
+ DMA_InitStruct->SrcAllocatedPort = LL_DMA_SRC_ALLOCATED_PORT0;
+ DMA_InitStruct->DestAllocatedPort = LL_DMA_DEST_ALLOCATED_PORT0;
+ DMA_InitStruct->LinkAllocatedPort = LL_DMA_LINK_ALLOCATED_PORT0;
+ DMA_InitStruct->LinkStepMode = LL_DMA_LSM_FULL_EXECUTION;
+ DMA_InitStruct->SrcAddrUpdateMode = LL_DMA_BURST_SRC_ADDR_INCREMENT;
+ DMA_InitStruct->DestAddrUpdateMode = LL_DMA_BURST_DEST_ADDR_INCREMENT;
+ DMA_InitStruct->SrcAddrOffset = 0x00000000U;
+ DMA_InitStruct->DestAddrOffset = 0x00000000U;
+ DMA_InitStruct->BlkRptSrcAddrUpdateMode = LL_DMA_BLKRPT_SRC_ADDR_INCREMENT;
+ DMA_InitStruct->BlkRptDestAddrUpdateMode = LL_DMA_BLKRPT_DEST_ADDR_INCREMENT;
+ DMA_InitStruct->BlkRptSrcAddrOffset = 0x00000000U;
+ DMA_InitStruct->BlkRptDestAddrOffset = 0x00000000U;
+ DMA_InitStruct->LinkedListBaseAddr = 0x00000000U;
+ DMA_InitStruct->LinkedListAddrOffset = 0x00000000U;
+};
+
+/**
+ * @brief Set each @ref LL_DMA_InitLinkedListTypeDef field to default value.
+ * @param DMA_InitLinkedListStruct Pointer to
+ * a @ref LL_DMA_InitLinkedListTypeDef structure.
+ * @retval None.
+ */
+void LL_DMA_ListStructInit(LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct)
+{
+ /* Set LL_DMA_InitLinkedListTypeDef fields to default values */
+ DMA_InitLinkedListStruct->Priority = LL_DMA_LOW_PRIORITY_LOW_WEIGHT;
+ DMA_InitLinkedListStruct->LinkStepMode = LL_DMA_LSM_FULL_EXECUTION;
+ DMA_InitLinkedListStruct->TransferEventMode = LL_DMA_TCEM_LAST_LLITEM_TRANSFER;
+ DMA_InitLinkedListStruct->LinkAllocatedPort = LL_DMA_LINK_ALLOCATED_PORT0;
+};
+
+/**
+ * @brief De-initialize the DMA linked list.
+ * @note This API is used for all available DMA channels.
+ * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use
+ * helper macros :
+ * @arg @ref LL_DMA_GET_INSTANCE
+ * @arg @ref LL_DMA_GET_CHANNEL
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS : DMA registers are de-initialized.
+ * - ERROR : DMA registers are not de-initialized.
+ */
+uint32_t LL_DMA_List_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return LL_DMA_DeInit(DMAx, Channel);
+}
+
+/**
+ * @brief Initialize the DMA linked list according to the specified parameters
+ * in LL_DMA_InitLinkedListTypeDef.
+ * @note This API is used for all available DMA channels.
+ * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use
+ * helper macros :
+ * @arg @ref LL_DMA_GET_INSTANCE
+ * @arg @ref LL_DMA_GET_CHANNEL
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_8
+ * @arg @ref LL_DMA_CHANNEL_9
+ * @arg @ref LL_DMA_CHANNEL_10
+ * @arg @ref LL_DMA_CHANNEL_11
+ * @arg @ref LL_DMA_CHANNEL_12
+ * @arg @ref LL_DMA_CHANNEL_13
+ * @arg @ref LL_DMA_CHANNEL_14
+ * @arg @ref LL_DMA_CHANNEL_15
+ * @param DMA_InitLinkedListStruct pointer to
+ * a @ref LL_DMA_InitLinkedListTypeDef structure.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS : DMA registers are initialized.
+ * - ERROR : Not applicable.
+ */
+uint32_t LL_DMA_List_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct)
+{
+ /* Check the DMA Instance DMAx and Channel parameters*/
+ assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
+
+ /* Check the DMA parameters from DMA_InitLinkedListStruct */
+ assert_param(IS_LL_DMA_PRIORITY(DMA_InitLinkedListStruct->Priority));
+ assert_param(IS_LL_DMA_LINK_STEP_MODE(DMA_InitLinkedListStruct->LinkStepMode));
+ assert_param(IS_LL_DMA_TRANSFER_EVENT_MODE(DMA_InitLinkedListStruct->TransferEventMode));
+ /* Check DMA instance */
+ if (IS_LL_GPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
+ {
+ assert_param(IS_LL_DMA_LINK_ALLOCATED_PORT(DMA_InitLinkedListStruct->LinkAllocatedPort));
+ }
+
+ /*-------------------------- DMAx CCR Configuration --------------------------
+ * Configure the control parameter :
+ * - LinkAllocatedPort: DMA_CCR_LAP bit
+ * LinkAllocatedPort field is supported only by GPDMA channels.
+ * - LinkStepMode: DMA_CCR_LSM bit
+ * - Priority: DMA_CCR_PRIO [23:22] bits
+ */
+ LL_DMA_ConfigControl(DMAx, Channel, DMA_InitLinkedListStruct->Priority | \
+ DMA_InitLinkedListStruct->LinkAllocatedPort | \
+ DMA_InitLinkedListStruct->LinkStepMode);
+
+ /*-------------------------- DMAx CTR2 Configuration -------------------------
+ * Configure the channel transfer parameter :
+ * - TransferEventMode: DMA_CTR2_TCEM [31:30] bits
+ */
+ LL_DMA_SetTransferEventMode(DMAx, Channel, DMA_InitLinkedListStruct->TransferEventMode);
+
+ return (uint32_t)SUCCESS;
+}
+
+/**
+ * @brief Set each @ref LL_DMA_InitNodeTypeDef field to default value.
+ * @param DMA_InitNodeStruct Pointer to a @ref LL_DMA_InitNodeTypeDef
+ * structure.
+ * @retval None.
+ */
+void LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct)
+{
+ /* Set DMA_InitNodeStruct fields to default values */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ DMA_InitNodeStruct->DestSecure = LL_DMA_CHANNEL_DEST_NSEC;
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+ DMA_InitNodeStruct->DestAllocatedPort = LL_DMA_DEST_ALLOCATED_PORT0;
+ DMA_InitNodeStruct->DestHWordExchange = LL_DMA_DEST_HALFWORD_PRESERVE;
+ DMA_InitNodeStruct->DestByteExchange = LL_DMA_DEST_BYTE_PRESERVE;
+ DMA_InitNodeStruct->DestBurstLength = 1U;
+ DMA_InitNodeStruct->DestIncMode = LL_DMA_DEST_FIXED;
+ DMA_InitNodeStruct->DestDataWidth = LL_DMA_DEST_DATAWIDTH_BYTE;
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ DMA_InitNodeStruct->SrcSecure = LL_DMA_CHANNEL_SRC_NSEC;
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+ DMA_InitNodeStruct->SrcAllocatedPort = LL_DMA_SRC_ALLOCATED_PORT0;
+ DMA_InitNodeStruct->SrcByteExchange = LL_DMA_SRC_BYTE_PRESERVE;
+ DMA_InitNodeStruct->DataAlignment = LL_DMA_DATA_ALIGN_ZEROPADD;
+ DMA_InitNodeStruct->SrcBurstLength = 1U;
+ DMA_InitNodeStruct->SrcIncMode = LL_DMA_SRC_FIXED;
+ DMA_InitNodeStruct->SrcDataWidth = LL_DMA_SRC_DATAWIDTH_BYTE;
+ DMA_InitNodeStruct->TransferEventMode = LL_DMA_TCEM_BLK_TRANSFER;
+ DMA_InitNodeStruct->TriggerPolarity = LL_DMA_TRIG_POLARITY_MASKED;
+ DMA_InitNodeStruct->TriggerSelection = 0x00000000U;
+ DMA_InitNodeStruct->TriggerMode = LL_DMA_TRIGM_BLK_TRANSFER;
+ DMA_InitNodeStruct->BlkHWRequest = LL_DMA_HWREQUEST_SINGLEBURST;
+ DMA_InitNodeStruct->Direction = LL_DMA_DIRECTION_MEMORY_TO_MEMORY;
+ DMA_InitNodeStruct->Request = 0x00000000U;
+ DMA_InitNodeStruct->BlkRptDestAddrUpdateMode = LL_DMA_BLKRPT_DEST_ADDR_INCREMENT;
+ DMA_InitNodeStruct->BlkRptSrcAddrUpdateMode = LL_DMA_BLKRPT_SRC_ADDR_INCREMENT;
+ DMA_InitNodeStruct->DestAddrUpdateMode = LL_DMA_BURST_DEST_ADDR_INCREMENT;
+ DMA_InitNodeStruct->SrcAddrUpdateMode = LL_DMA_BURST_SRC_ADDR_INCREMENT;
+ DMA_InitNodeStruct->BlkRptCount = 0x00000000U;
+ DMA_InitNodeStruct->BlkDataLength = 0x00000000U;
+ DMA_InitNodeStruct->SrcAddress = 0x00000000U;
+ DMA_InitNodeStruct->DestAddress = 0x00000000U;
+ DMA_InitNodeStruct->DestAddrOffset = 0x00000000U;
+ DMA_InitNodeStruct->SrcAddrOffset = 0x00000000U;
+ DMA_InitNodeStruct->BlkRptDestAddrOffset = 0x00000000U;
+ DMA_InitNodeStruct->BlkRptSrcAddrOffset = 0x00000000U;
+ DMA_InitNodeStruct->UpdateRegisters = (LL_DMA_UPDATE_CTR1 | LL_DMA_UPDATE_CTR2 | \
+ LL_DMA_UPDATE_CBR1 | LL_DMA_UPDATE_CSAR | \
+ LL_DMA_UPDATE_CDAR | LL_DMA_UPDATE_CTR3 | \
+ LL_DMA_UPDATE_CBR2 | LL_DMA_UPDATE_CLLR);
+ DMA_InitNodeStruct->NodeType = LL_DMA_GPDMA_LINEAR_NODE;
+};
+
+/**
+ * @brief Initializes DMA linked list node according to the specified
+ * parameters in the DMA_InitNodeStruct.
+ * @param DMA_InitNodeStruct Pointer to a LL_DMA_InitNodeTypeDef structure
+ * that contains linked list node
+ * registers configurations.
+ * @param pNode Pointer to linked list node to fill according to
+ * LL_DMA_LinkNodeTypeDef parameters.
+ * @retval None
+ */
+uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DMA_LinkNodeTypeDef *pNode)
+{
+ uint32_t reg_counter = 0U;
+
+ /* Check the DMA Node type */
+ assert_param(IS_LL_DMA_LINK_NODETYPE(DMA_InitNodeStruct->NodeType));
+
+ /* Check the DMA parameters from DMA_InitNodeStruct */
+ assert_param(IS_LL_DMA_DIRECTION(DMA_InitNodeStruct->Direction));
+
+ /* Check direction */
+ if (DMA_InitNodeStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY)
+ {
+ assert_param(IS_LL_DMA_REQUEST_SELECTION(DMA_InitNodeStruct->Request));
+ }
+
+ assert_param(IS_LL_DMA_DATA_ALIGNMENT(DMA_InitNodeStruct->DataAlignment));
+ assert_param(IS_LL_DMA_SRC_DATA_WIDTH(DMA_InitNodeStruct->SrcDataWidth));
+ assert_param(IS_LL_DMA_DEST_DATA_WIDTH(DMA_InitNodeStruct->DestDataWidth));
+ assert_param(IS_LL_DMA_SRC_INCREMENT_MODE(DMA_InitNodeStruct->SrcIncMode));
+ assert_param(IS_LL_DMA_DEST_INCREMENT_MODE(DMA_InitNodeStruct->DestIncMode));
+ assert_param(IS_LL_DMA_BLK_DATALENGTH(DMA_InitNodeStruct->BlkDataLength));
+ assert_param(IS_LL_DMA_TRIGGER_POLARITY(DMA_InitNodeStruct->TriggerPolarity));
+ assert_param(IS_LL_DMA_BLKHW_REQUEST(DMA_InitNodeStruct->BlkHWRequest));
+ assert_param(IS_LL_DMA_TRANSFER_EVENT_MODE(DMA_InitNodeStruct->TransferEventMode));
+ assert_param(IS_LL_DMA_LINK_UPDATE_REGISTERS(DMA_InitNodeStruct->UpdateRegisters));
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ assert_param(IS_LL_DMA_CHANNEL_SRC_SEC(DMA_InitNodeStruct->SrcSecure));
+ assert_param(IS_LL_DMA_CHANNEL_DEST_SEC(DMA_InitNodeStruct->DestSecure));
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+ /* Check trigger polarity */
+ if (DMA_InitNodeStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED)
+ {
+ assert_param(IS_LL_DMA_TRIGGER_MODE(DMA_InitNodeStruct->TriggerMode));
+ assert_param(IS_LL_DMA_TRIGGER_SELECTION(DMA_InitNodeStruct->TriggerSelection));
+ }
+
+ /* Check node type */
+ if (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_LINEAR_NODE)
+ {
+ assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitNodeStruct->SrcBurstLength));
+ assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitNodeStruct->DestBurstLength));
+ assert_param(IS_LL_DMA_DEST_HALFWORD_EXCHANGE(DMA_InitNodeStruct->DestHWordExchange));
+ assert_param(IS_LL_DMA_DEST_BYTE_EXCHANGE(DMA_InitNodeStruct->DestByteExchange));
+ assert_param(IS_LL_DMA_SRC_BYTE_EXCHANGE(DMA_InitNodeStruct->SrcByteExchange));
+ assert_param(IS_LL_DMA_SRC_ALLOCATED_PORT(DMA_InitNodeStruct->SrcAllocatedPort));
+ assert_param(IS_LL_DMA_DEST_ALLOCATED_PORT(DMA_InitNodeStruct->DestAllocatedPort));
+ }
+
+ /* Check DMA channel */
+ if (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE)
+ {
+ assert_param(IS_LL_DMA_BLK_REPEATCOUNT(DMA_InitNodeStruct->BlkRptCount));
+ assert_param(IS_LL_DMA_BURST_SRC_ADDR_UPDATE(DMA_InitNodeStruct->SrcAddrUpdateMode));
+ assert_param(IS_LL_DMA_BURST_DEST_ADDR_UPDATE(DMA_InitNodeStruct->DestAddrUpdateMode));
+ assert_param(IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(DMA_InitNodeStruct->SrcAddrOffset));
+ assert_param(IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(DMA_InitNodeStruct->DestAddrOffset));
+ assert_param(IS_LL_DMA_BLKRPT_SRC_ADDR_UPDATE(DMA_InitNodeStruct->BlkRptSrcAddrUpdateMode));
+ assert_param(IS_LL_DMA_BLKRPT_DEST_ADDR_UPDATE(DMA_InitNodeStruct->BlkRptDestAddrUpdateMode));
+ assert_param(IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(DMA_InitNodeStruct->BlkRptSrcAddrOffset));
+ assert_param(IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(DMA_InitNodeStruct->BlkRptDestAddrOffset));
+ }
+
+ /* Check if CTR1 register update is enabled */
+ if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CTR1) == LL_DMA_UPDATE_CTR1)
+ {
+ /*-------------------------- DMAx CTR1 Configuration -----------------------
+ * Configure the Data transfer parameter :
+ * - DestAllocatedPort: DMA_CTR1_DAP bit
+ * DestAllocatedPort field is not supported by LPDMA channels.
+ * - DestHWordExchange: DMA_CTR1_DHX bit
+ * DestHWordExchange field is not supported by LPDMA channels.
+ * - DestByteExchange: DMA_CTR1_DBX bit
+ * DestByteExchange field is not supported by LPDMA channels.
+ * - DestIncMode: DMA_CTR1_DINC bit
+ * - DestDataWidth: DMA_CTR1_DDW_LOG2 [17:16] bits
+ * - SrcAllocatedPort: DMA_CTR1_SAP bit
+ * SrcAllocatedPort field is not supported by LPDMA channels.
+ * - SrcByteExchange: DMA_CTR1_SBX bit
+ * SrcByteExchange field is not supported by LPDMA channels.
+ * - DataAlignment: DMA_CTR1_PAM [12:11] bits
+ * DataAlignment field is reduced to one bit for LPDMA channels.
+ * - SrcIncMode: DMA_CTR1_SINC bit
+ * - SrcDataWidth: DMA_CTR1_SDW_LOG2 [1:0] bits
+ * - SrcBurstLength: DMA_CTR1_SBL_1 [9:4] bits
+ * SrcBurstLength field is not supported by LPDMA channels.
+ * - DestBurstLength: DMA_CTR1_DBL_1 [25:20] bits
+ * DestBurstLength field is not supported by LPDMA channels.
+ */
+
+ pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->DestIncMode | \
+ DMA_InitNodeStruct->DestDataWidth | \
+ DMA_InitNodeStruct->DataAlignment | \
+ DMA_InitNodeStruct->SrcIncMode | \
+ DMA_InitNodeStruct->SrcDataWidth);
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->DestSecure | \
+ DMA_InitNodeStruct->SrcSecure);
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+ /* Update CTR1 register fields for not LPDMA channels */
+ if (DMA_InitNodeStruct->NodeType != LL_DMA_LPDMA_LINEAR_NODE)
+ {
+ pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->DestAllocatedPort | \
+ DMA_InitNodeStruct->DestHWordExchange | \
+ DMA_InitNodeStruct->DestByteExchange | \
+ ((DMA_InitNodeStruct->DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) | \
+ DMA_InitNodeStruct->SrcAllocatedPort | \
+ DMA_InitNodeStruct->SrcByteExchange | \
+ ((DMA_InitNodeStruct->SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos));
+ }
+
+ /* Increment counter for the next register */
+ reg_counter++;
+ }
+
+
+ /* Check if CTR2 register update is enabled */
+ if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CTR2) == LL_DMA_UPDATE_CTR2)
+ {
+ /*-------------------------- DMAx CTR2 Configuration -----------------------
+ * Configure the channel transfer parameter :
+ * - TransferEventMode: DMA_CTR2_TCEM [31:30] bits
+ * - TriggerPolarity: DMA_CTR2_TRIGPOL [25:24] bits
+ * - TriggerMode: DMA_CTR2_TRIGM [15:14] bits
+ * - BlkHWRequest: DMA_CTR2_BREQ bit
+ * - Direction: DMA_CTR2_DREQ bit
+ * - Direction: DMA_CTR2_SWREQ bit
+ * Direction field is reduced to one bit for LPDMA channels (SWREQ).
+ * - TriggerSelection: DMA_CTR2_TRIGSEL [21:16] bits
+ * DataAlignment field is reduced to 5 bits for LPDMA channels.
+ * - Request: DMA_CTR2_REQSEL [6:0] bits
+ * DataAlignment field is reduced to 5 bits for LPDMA channels.
+ */
+ pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->TransferEventMode | \
+ DMA_InitNodeStruct->TriggerPolarity | \
+ DMA_InitNodeStruct->BlkHWRequest | \
+ DMA_InitNodeStruct->Direction);
+
+ /* Check direction */
+ if (DMA_InitNodeStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY)
+ {
+ pNode->LinkRegisters[reg_counter] |= DMA_InitNodeStruct->Request & DMA_CTR2_REQSEL;
+ }
+
+ /* Check trigger polarity */
+ if (DMA_InitNodeStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED)
+ {
+ pNode->LinkRegisters[reg_counter] |= (((DMA_InitNodeStruct->TriggerSelection << DMA_CTR2_TRIGSEL_Pos) & \
+ DMA_CTR2_TRIGSEL) | DMA_InitNodeStruct->TriggerMode);
+ }
+
+ /* Update CTR2 register fields for LPDMA */
+ if (DMA_InitNodeStruct->NodeType == LL_DMA_LPDMA_LINEAR_NODE)
+ {
+ pNode->LinkRegisters[reg_counter] &= (~(1UL << 21U) & ~(3UL << 5U));
+ }
+
+ /* Increment counter for the next register */
+ reg_counter++;
+ }
+
+
+ /* Check if CBR1 register update is enabled */
+ if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CBR1) == LL_DMA_UPDATE_CBR1)
+ {
+ /*-------------------------- DMAx CBR1 Configuration -----------------------
+ * Configure the Transfer Block counters and update mode with parameter :
+ * - BlkDataLength: DMA_CBR1_BNDT[15:0] bits
+ * - BlkRptCount: DMA_CBR1_BRC[26:16] bits
+ * BlkRptCount field is supported only by 2D addressing channels.
+ * - BlkRptSrcAddrUpdateMode: DMA_CBR1_BRSDEC bit
+ * BlkRptSrcAddrUpdateMode field is supported only by 2D addressing channels.
+ * - BlkRptDestAddrUpdateMode: DMA_CBR1_BRDDEC bit
+ * BlkRptDestAddrUpdateMode field is supported only by 2D addressing channels.
+ * - SrcAddrUpdateMode: DMA_CBR1_SDEC bit
+ * SrcAddrUpdateMode field is supported only by 2D addressing channels.
+ * - DestAddrUpdateMode: DMA_CBR1_DDEC bit
+ * DestAddrUpdateMode field is supported only by 2D addressing channels.
+ */
+ pNode->LinkRegisters[reg_counter] = DMA_InitNodeStruct->BlkDataLength;
+
+ /* Update CBR1 register fields for 2D addressing channels */
+ if (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE)
+ {
+ pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->BlkRptDestAddrUpdateMode | \
+ DMA_InitNodeStruct->BlkRptSrcAddrUpdateMode | \
+ DMA_InitNodeStruct->DestAddrUpdateMode | \
+ DMA_InitNodeStruct->SrcAddrUpdateMode | \
+ ((DMA_InitNodeStruct->BlkRptCount << DMA_CBR1_BRC_Pos) & DMA_CBR1_BRC));
+ }
+
+ /* Increment counter for the next register */
+ reg_counter++;
+ }
+
+
+ /* Check if CSAR register update is enabled */
+ if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CSAR) == LL_DMA_UPDATE_CSAR)
+ {
+ /*-------------------------- DMAx CSAR Configuration -----------------------
+ * Configure the Transfer Block counters and update mode with parameter :
+ * - SrcAddress: DMA_CSAR_SA[31:0] bits
+ */
+ pNode->LinkRegisters[reg_counter] = DMA_InitNodeStruct->SrcAddress;
+
+ /* Increment counter for the next register */
+ reg_counter++;
+ }
+
+
+ /* Check if CDAR register update is enabled */
+ if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CDAR) == LL_DMA_UPDATE_CDAR)
+ {
+ /*-------------------------- DMAx CDAR Configuration -----------------------
+ * Configure the Transfer Block counters and update mode with parameter :
+ * - DestAddress: DMA_CDAR_DA[31:0] bits
+ */
+ pNode->LinkRegisters[reg_counter] = DMA_InitNodeStruct->DestAddress;
+
+ /* Increment counter for the next register */
+ reg_counter++;
+ }
+
+
+ /* Update CTR3 register fields for 2D addressing channels */
+ if (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE)
+ {
+ /* Check if CTR3 register update is enabled */
+ if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CTR3) == LL_DMA_UPDATE_CTR3)
+ {
+ /*-------------------------- DMAx CTR3 Configuration ---------------------
+ * Configure the Block counters and update mode with parameter :
+ * - DestAddressOffset: DMA_CTR3_DAO[12:0] bits
+ * DestAddressOffset field is supported only by 2D addressing channels.
+ * - SrcAddressOffset: DMA_CTR3_SAO[12:0] bits
+ * SrcAddressOffset field is supported only by 2D addressing channels.
+ */
+ pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->SrcAddrOffset | \
+ ((DMA_InitNodeStruct->DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO));
+
+ /* Increment counter for the next register */
+ reg_counter++;
+ }
+ }
+
+
+ /* Update CBR2 register fields for 2D addressing channels */
+ if (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE)
+ {
+ /* Check if CBR2 register update is enabled */
+ if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CBR2) == LL_DMA_UPDATE_CBR2)
+ {
+ /*-------------------------- DMAx CBR2 Configuration ---------------------
+ * Configure the Block counters and update mode with parameter :
+ * - BlkRptDestAddrOffset: DMA_CBR2_BRDAO[31:16] bits
+ * BlkRptDestAddrOffset field is supported only by 2D addressing channels.
+ * - BlkRptSrcAddrOffset: DMA_CBR2_BRSAO[15:0] bits
+ * BlkRptSrcAddrOffset field is supported only by 2D addressing channels.
+ */
+ pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->BlkRptSrcAddrOffset | \
+ ((DMA_InitNodeStruct->BlkRptDestAddrOffset << DMA_CBR2_BRDAO_Pos) & \
+ DMA_CBR2_BRDAO));
+
+ /* Increment counter for the next register */
+ reg_counter++;
+ }
+ }
+
+ /* Check if CLLR register update is enabled */
+ if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CLLR) == LL_DMA_UPDATE_CLLR)
+ {
+ /*-------------------------- DMAx CLLR Configuration -----------------------
+ * Configure the Transfer Block counters and update mode with parameter :
+ * - UpdateRegisters DMA_CLLR_UT1 bit
+ * - UpdateRegisters DMA_CLLR_UT2 bit
+ * - UpdateRegisters DMA_CLLR_UB1 bit
+ * - UpdateRegisters DMA_CLLR_USA bit
+ * - UpdateRegisters DMA_CLLR_UDA bit
+ * - UpdateRegisters DMA_CLLR_UT3 bit
+ * DMA_CLLR_UT3 bit is discarded for linear addressing channels.
+ * - UpdateRegisters DMA_CLLR_UB2 bit
+ * DMA_CLLR_UB2 bit is discarded for linear addressing channels.
+ * - UpdateRegisters DMA_CLLR_ULL bit
+ */
+ pNode->LinkRegisters[reg_counter] = ((DMA_InitNodeStruct->UpdateRegisters & (DMA_CLLR_UT1 | DMA_CLLR_UT2 | \
+ DMA_CLLR_UB1 | DMA_CLLR_USA | \
+ DMA_CLLR_UDA | DMA_CLLR_ULL)));
+
+ /* Update CLLR register fields for 2D addressing channels */
+ if (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE)
+ {
+ pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->UpdateRegisters & (DMA_CLLR_UT3 | DMA_CLLR_UB2));
+ }
+ }
+
+ return (uint32_t)SUCCESS;
+}
+
+/**
+ * @brief Connect Linked list Nodes.
+ * @param pPrevLinkNode Pointer to previous linked list node to be connected to new Linked list node.
+ * @param PrevNodeCLLRIdx Offset of Previous Node CLLR register.
+ * This parameter can be a value of @ref DMA_LL_EC_CLLR_OFFSET.
+ * @param pNewLinkNode Pointer to new Linked list.
+ * @param NewNodeCLLRIdx Offset of New Node CLLR register.
+ * This parameter can be a value of @ref DMA_LL_EC_CLLR_OFFSET.
+ * @retval None
+ */
+void LL_DMA_ConnectLinkNode(LL_DMA_LinkNodeTypeDef *pPrevLinkNode, uint32_t PrevNodeCLLRIdx,
+ LL_DMA_LinkNodeTypeDef *pNewLinkNode, uint32_t NewNodeCLLRIdx)
+{
+ pPrevLinkNode->LinkRegisters[PrevNodeCLLRIdx] = (((uint32_t)pNewLinkNode & DMA_CLLR_LA) | \
+ (pNewLinkNode->LinkRegisters[NewNodeCLLRIdx] & (DMA_CLLR_UT1 | \
+ DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | \
+ DMA_CLLR_UT3 | DMA_CLLR_UB2 | DMA_CLLR_ULL)));
+}
+
+/**
+ * @brief Disconnect the next linked list node.
+ * @param pLinkNode Pointer to linked list node to be disconnected from the next one.
+ * @param LinkNodeCLLRIdx Offset of Link Node CLLR register.
+ * @retval None.
+ */
+void LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32_t LinkNodeCLLRIdx)
+{
+ pLinkNode->LinkRegisters[LinkNodeCLLRIdx] = 0;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* (defined (GPDMA1) || defined (LPDMA1)) */
+
+/**
+ * @}
+ */
+
+#endif /* defined (USE_FULL_LL_DRIVER) */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dma2d.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dma2d.c
new file mode 100644
index 00000000..ef330946
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dma2d.c
@@ -0,0 +1,630 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_dma2d.c
+ * @author MCD Application Team
+ * @brief DMA2D LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_ll_dma2d.h"
+#include "stm32u5xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined (DMA2D)
+
+/** @addtogroup DMA2D_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup DMA2D_LL_Private_Constants DMA2D Private Constants
+ * @{
+ */
+#define LL_DMA2D_COLOR 0xFFU /*!< Maximum output color setting */
+#define LL_DMA2D_NUMBEROFLINES DMA2D_NLR_NL /*!< Maximum number of lines */
+#define LL_DMA2D_NUMBEROFPIXELS (DMA2D_NLR_PL >> DMA2D_NLR_PL_Pos) /*!< Maximum number of pixels per lines */
+#define LL_DMA2D_OFFSET_MAX 0x3FFFU /*!< Maximum output line offset expressed in pixels */
+#define LL_DMA2D_CLUTSIZE_MAX 0xFFU /*!< Maximum CLUT size */
+/**
+ * @}
+ */
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup DMA2D_LL_Private_Macros
+ * @{
+ */
+#define IS_LL_DMA2D_MODE(MODE) (((MODE) == LL_DMA2D_MODE_M2M) || \
+ ((MODE) == LL_DMA2D_MODE_M2M_PFC) || \
+ ((MODE) == LL_DMA2D_MODE_M2M_BLEND) || \
+ ((MODE) == LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG) || \
+ ((MODE) == LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG) || \
+ ((MODE) == LL_DMA2D_MODE_R2M))
+
+#define IS_LL_DMA2D_OCMODE(MODE_ARGB) (((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_ARGB8888) || \
+ ((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_RGB888) || \
+ ((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_RGB565) || \
+ ((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_ARGB1555) || \
+ ((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_ARGB4444))
+
+#define IS_LL_DMA2D_GREEN(GREEN) ((GREEN) <= LL_DMA2D_COLOR)
+#define IS_LL_DMA2D_RED(RED) ((RED) <= LL_DMA2D_COLOR)
+#define IS_LL_DMA2D_BLUE(BLUE) ((BLUE) <= LL_DMA2D_COLOR)
+#define IS_LL_DMA2D_ALPHA(ALPHA) ((ALPHA) <= LL_DMA2D_COLOR)
+
+#define IS_LL_DMA2D_OFFSET_MODE(MODE) (((MODE) == LL_DMA2D_LINE_OFFSET_PIXELS) || \
+ ((MODE) == LL_DMA2D_LINE_OFFSET_BYTES))
+
+#define IS_LL_DMA2D_OFFSET(OFFSET) ((OFFSET) <= LL_DMA2D_OFFSET_MAX)
+
+#define IS_LL_DMA2D_LINE(LINES) ((LINES) <= LL_DMA2D_NUMBEROFLINES)
+#define IS_LL_DMA2D_PIXEL(PIXELS) ((PIXELS) <= LL_DMA2D_NUMBEROFPIXELS)
+
+#define IS_LL_DMA2D_SWAP_MODE(MODE) (((MODE) == LL_DMA2D_SWAP_MODE_REGULAR) || \
+ ((MODE) == LL_DMA2D_SWAP_MODE_TWO_BY_TWO))
+
+#define IS_LL_DMA2D_ALPHAINV(ALPHA) (((ALPHA) == LL_DMA2D_ALPHA_REGULAR) || \
+ ((ALPHA) == LL_DMA2D_ALPHA_INVERTED))
+
+#define IS_LL_DMA2D_RBSWAP(RBSWAP) (((RBSWAP) == LL_DMA2D_RB_MODE_REGULAR) || \
+ ((RBSWAP) == LL_DMA2D_RB_MODE_SWAP))
+
+#define IS_LL_DMA2D_LCMODE(MODE_ARGB) (((MODE_ARGB) == LL_DMA2D_INPUT_MODE_ARGB8888) || \
+ ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_RGB888) || \
+ ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_RGB565) || \
+ ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_ARGB1555) || \
+ ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_ARGB4444) || \
+ ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_L8) || \
+ ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_AL44) || \
+ ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_AL88) || \
+ ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_L4) || \
+ ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_A8) || \
+ ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_A4))
+
+#define IS_LL_DMA2D_CLUTCMODE(CLUTCMODE) (((CLUTCMODE) == LL_DMA2D_CLUT_COLOR_MODE_ARGB8888) || \
+ ((CLUTCMODE) == LL_DMA2D_CLUT_COLOR_MODE_RGB888))
+
+#define IS_LL_DMA2D_CLUTSIZE(SIZE) ((SIZE) <= LL_DMA2D_CLUTSIZE_MAX)
+
+#define IS_LL_DMA2D_ALPHAMODE(MODE) (((MODE) == LL_DMA2D_ALPHA_MODE_NO_MODIF) || \
+ ((MODE) == LL_DMA2D_ALPHA_MODE_REPLACE) || \
+ ((MODE) == LL_DMA2D_ALPHA_MODE_COMBINE))
+
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DMA2D_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DMA2D_LL_EF_Init_Functions Initialization and De-initialization Functions
+ * @{
+ */
+
+/**
+ * @brief De-initialize DMA2D registers (registers restored to their default values).
+ * @param DMA2Dx DMA2D Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: DMA2D registers are de-initialized
+ * - ERROR: DMA2D registers are not de-initialized
+ */
+ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
+
+ if (DMA2Dx == DMA2D)
+ {
+ /* Force reset of DMA2D clock */
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2D);
+
+ /* Release reset of DMA2D clock */
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2D);
+ }
+ else
+ {
+ status = ERROR;
+ }
+
+ return (status);
+}
+
+/**
+ * @brief Initialize DMA2D registers according to the specified parameters in DMA2D_InitStruct.
+ * @note DMA2D transfers must be disabled to set initialization bits in configuration registers,
+ * otherwise ERROR result is returned.
+ * @param DMA2Dx DMA2D Instance
+ * @param DMA2D_InitStruct pointer to a LL_DMA2D_InitTypeDef structure
+ * that contains the configuration information for the specified DMA2D peripheral.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: DMA2D registers are initialized according to DMA2D_InitStruct content
+ * - ERROR: Issue occurred during DMA2D registers initialization
+ */
+ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct)
+{
+ ErrorStatus status = ERROR;
+ LL_DMA2D_ColorTypeDef dma2d_colorstruct;
+ uint32_t tmp;
+ uint32_t tmp1;
+ uint32_t tmp2;
+ uint32_t regMask;
+ uint32_t regValue;
+
+ /* Check the parameters */
+ assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
+ assert_param(IS_LL_DMA2D_MODE(DMA2D_InitStruct->Mode));
+ assert_param(IS_LL_DMA2D_OCMODE(DMA2D_InitStruct->ColorMode));
+ assert_param(IS_LL_DMA2D_LINE(DMA2D_InitStruct->NbrOfLines));
+ assert_param(IS_LL_DMA2D_PIXEL(DMA2D_InitStruct->NbrOfPixelsPerLines));
+ assert_param(IS_LL_DMA2D_GREEN(DMA2D_InitStruct->OutputGreen));
+ assert_param(IS_LL_DMA2D_RED(DMA2D_InitStruct->OutputRed));
+ assert_param(IS_LL_DMA2D_BLUE(DMA2D_InitStruct->OutputBlue));
+ assert_param(IS_LL_DMA2D_ALPHA(DMA2D_InitStruct->OutputAlpha));
+ assert_param(IS_LL_DMA2D_SWAP_MODE(DMA2D_InitStruct->OutputSwapMode));
+ assert_param(IS_LL_DMA2D_OFFSET_MODE(DMA2D_InitStruct->LineOffsetMode));
+ assert_param(IS_LL_DMA2D_OFFSET(DMA2D_InitStruct->LineOffset));
+ assert_param(IS_LL_DMA2D_ALPHAINV(DMA2D_InitStruct->AlphaInversionMode));
+ assert_param(IS_LL_DMA2D_RBSWAP(DMA2D_InitStruct->RBSwapMode));
+
+ /* DMA2D transfers must be disabled to configure bits in initialization registers */
+ tmp = LL_DMA2D_IsTransferOngoing(DMA2Dx);
+ tmp1 = LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2Dx);
+ tmp2 = LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2Dx);
+ if ((tmp == 0U) && (tmp1 == 0U) && (tmp2 == 0U))
+ {
+ /* DMA2D CR register configuration -------------------------------------------*/
+ MODIFY_REG(DMA2Dx->CR, (DMA2D_CR_MODE | DMA2D_CR_LOM), \
+ (DMA2D_InitStruct->Mode | DMA2D_InitStruct->LineOffsetMode));
+
+ /* DMA2D OPFCCR register configuration ---------------------------------------*/
+ regMask = DMA2D_OPFCCR_CM;
+ regValue = DMA2D_InitStruct->ColorMode;
+
+ regMask |= DMA2D_OPFCCR_SB;
+ regValue |= DMA2D_InitStruct->OutputSwapMode;
+
+ regMask |= (DMA2D_OPFCCR_RBS | DMA2D_OPFCCR_AI);
+ regValue |= (DMA2D_InitStruct->AlphaInversionMode | DMA2D_InitStruct->RBSwapMode);
+
+
+ MODIFY_REG(DMA2Dx->OPFCCR, regMask, regValue);
+
+ /* DMA2D OOR register configuration ------------------------------------------*/
+ LL_DMA2D_SetLineOffset(DMA2Dx, DMA2D_InitStruct->LineOffset);
+
+ /* DMA2D NLR register configuration ------------------------------------------*/
+ LL_DMA2D_ConfigSize(DMA2Dx, DMA2D_InitStruct->NbrOfLines, DMA2D_InitStruct->NbrOfPixelsPerLines);
+
+ /* DMA2D OMAR register configuration ------------------------------------------*/
+ LL_DMA2D_SetOutputMemAddr(DMA2Dx, DMA2D_InitStruct->OutputMemoryAddress);
+
+ /* DMA2D OCOLR register configuration ------------------------------------------*/
+ dma2d_colorstruct.ColorMode = DMA2D_InitStruct->ColorMode;
+ dma2d_colorstruct.OutputBlue = DMA2D_InitStruct->OutputBlue;
+ dma2d_colorstruct.OutputGreen = DMA2D_InitStruct->OutputGreen;
+ dma2d_colorstruct.OutputRed = DMA2D_InitStruct->OutputRed;
+ dma2d_colorstruct.OutputAlpha = DMA2D_InitStruct->OutputAlpha;
+ LL_DMA2D_ConfigOutputColor(DMA2Dx, &dma2d_colorstruct);
+
+ status = SUCCESS;
+ }
+ /* If DMA2D transfers are not disabled, return ERROR */
+
+ return (status);
+}
+
+/**
+ * @brief Set each @ref LL_DMA2D_InitTypeDef field to default value.
+ * @param DMA2D_InitStruct pointer to a @ref LL_DMA2D_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct)
+{
+ /* Set DMA2D_InitStruct fields to default values */
+ DMA2D_InitStruct->Mode = LL_DMA2D_MODE_M2M;
+ DMA2D_InitStruct->ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB8888;
+ DMA2D_InitStruct->NbrOfLines = 0x0U;
+ DMA2D_InitStruct->NbrOfPixelsPerLines = 0x0U;
+ DMA2D_InitStruct->LineOffsetMode = LL_DMA2D_LINE_OFFSET_PIXELS;
+ DMA2D_InitStruct->LineOffset = 0x0U;
+ DMA2D_InitStruct->OutputBlue = 0x0U;
+ DMA2D_InitStruct->OutputGreen = 0x0U;
+ DMA2D_InitStruct->OutputRed = 0x0U;
+ DMA2D_InitStruct->OutputAlpha = 0x0U;
+ DMA2D_InitStruct->OutputMemoryAddress = 0x0U;
+ DMA2D_InitStruct->OutputSwapMode = LL_DMA2D_SWAP_MODE_REGULAR;
+ DMA2D_InitStruct->AlphaInversionMode = LL_DMA2D_ALPHA_REGULAR;
+ DMA2D_InitStruct->RBSwapMode = LL_DMA2D_RB_MODE_REGULAR;
+}
+
+/**
+ * @brief Configure the foreground or background according to the specified parameters
+ * in the LL_DMA2D_LayerCfgTypeDef structure.
+ * @param DMA2Dx DMA2D Instance
+ * @param DMA2D_LayerCfg pointer to a LL_DMA2D_LayerCfgTypeDef structure that contains
+ * the configuration information for the specified layer.
+ * @param LayerIdx DMA2D Layer index.
+ * This parameter can be one of the following values:
+ * 0(background) / 1(foreground)
+ * @retval None
+ */
+void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx)
+{
+ /* Check the parameters */
+ assert_param(IS_LL_DMA2D_OFFSET(DMA2D_LayerCfg->LineOffset));
+ assert_param(IS_LL_DMA2D_LCMODE(DMA2D_LayerCfg->ColorMode));
+ assert_param(IS_LL_DMA2D_CLUTCMODE(DMA2D_LayerCfg->CLUTColorMode));
+ assert_param(IS_LL_DMA2D_CLUTSIZE(DMA2D_LayerCfg->CLUTSize));
+ assert_param(IS_LL_DMA2D_ALPHAMODE(DMA2D_LayerCfg->AlphaMode));
+ assert_param(IS_LL_DMA2D_GREEN(DMA2D_LayerCfg->Green));
+ assert_param(IS_LL_DMA2D_RED(DMA2D_LayerCfg->Red));
+ assert_param(IS_LL_DMA2D_BLUE(DMA2D_LayerCfg->Blue));
+ assert_param(IS_LL_DMA2D_ALPHA(DMA2D_LayerCfg->Alpha));
+ assert_param(IS_LL_DMA2D_ALPHAINV(DMA2D_LayerCfg->AlphaInversionMode));
+ assert_param(IS_LL_DMA2D_RBSWAP(DMA2D_LayerCfg->RBSwapMode));
+
+
+ if (LayerIdx == 0U)
+ {
+ /* Configure the background memory address */
+ LL_DMA2D_BGND_SetMemAddr(DMA2Dx, DMA2D_LayerCfg->MemoryAddress);
+
+ /* Configure the background line offset */
+ LL_DMA2D_BGND_SetLineOffset(DMA2Dx, DMA2D_LayerCfg->LineOffset);
+
+ /* Configure the background Alpha value, Alpha mode, RB swap, Alpha inversion
+ CLUT size, CLUT Color mode and Color mode */
+ MODIFY_REG(DMA2Dx->BGPFCCR, \
+ (DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_RBS | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_AM | \
+ DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM | DMA2D_BGPFCCR_CM), \
+ ((DMA2D_LayerCfg->Alpha << DMA2D_BGPFCCR_ALPHA_Pos) | DMA2D_LayerCfg->RBSwapMode | \
+ DMA2D_LayerCfg->AlphaInversionMode | DMA2D_LayerCfg->AlphaMode | \
+ (DMA2D_LayerCfg->CLUTSize << DMA2D_BGPFCCR_CS_Pos) | DMA2D_LayerCfg->CLUTColorMode | \
+ DMA2D_LayerCfg->ColorMode));
+
+ /* Configure the background color */
+ LL_DMA2D_BGND_SetColor(DMA2Dx, DMA2D_LayerCfg->Red, DMA2D_LayerCfg->Green, DMA2D_LayerCfg->Blue);
+
+ /* Configure the background CLUT memory address */
+ LL_DMA2D_BGND_SetCLUTMemAddr(DMA2Dx, DMA2D_LayerCfg->CLUTMemoryAddress);
+ }
+ else
+ {
+ /* Configure the foreground memory address */
+ LL_DMA2D_FGND_SetMemAddr(DMA2Dx, DMA2D_LayerCfg->MemoryAddress);
+
+ /* Configure the foreground line offset */
+ LL_DMA2D_FGND_SetLineOffset(DMA2Dx, DMA2D_LayerCfg->LineOffset);
+
+ /* Configure the foreground Alpha value, Alpha mode, RB swap, Alpha inversion
+ CLUT size, CLUT Color mode and Color mode */
+ MODIFY_REG(DMA2Dx->FGPFCCR, \
+ (DMA2D_FGPFCCR_ALPHA | DMA2D_FGPFCCR_RBS | DMA2D_FGPFCCR_AI | DMA2D_FGPFCCR_AM | \
+ DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM | DMA2D_FGPFCCR_CM), \
+ ((DMA2D_LayerCfg->Alpha << DMA2D_FGPFCCR_ALPHA_Pos) | DMA2D_LayerCfg->RBSwapMode | \
+ DMA2D_LayerCfg->AlphaInversionMode | DMA2D_LayerCfg->AlphaMode | \
+ (DMA2D_LayerCfg->CLUTSize << DMA2D_FGPFCCR_CS_Pos) | DMA2D_LayerCfg->CLUTColorMode | \
+ DMA2D_LayerCfg->ColorMode));
+
+ /* Configure the foreground color */
+ LL_DMA2D_FGND_SetColor(DMA2Dx, DMA2D_LayerCfg->Red, DMA2D_LayerCfg->Green, DMA2D_LayerCfg->Blue);
+
+ /* Configure the foreground CLUT memory address */
+ LL_DMA2D_FGND_SetCLUTMemAddr(DMA2Dx, DMA2D_LayerCfg->CLUTMemoryAddress);
+ }
+}
+
+/**
+ * @brief Set each @ref LL_DMA2D_LayerCfgTypeDef field to default value.
+ * @param DMA2D_LayerCfg pointer to a @ref LL_DMA2D_LayerCfgTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg)
+{
+ /* Set DMA2D_LayerCfg fields to default values */
+ DMA2D_LayerCfg->MemoryAddress = 0x0U;
+ DMA2D_LayerCfg->ColorMode = LL_DMA2D_INPUT_MODE_ARGB8888;
+ DMA2D_LayerCfg->LineOffset = 0x0U;
+ DMA2D_LayerCfg->CLUTColorMode = LL_DMA2D_CLUT_COLOR_MODE_ARGB8888;
+ DMA2D_LayerCfg->CLUTSize = 0x0U;
+ DMA2D_LayerCfg->AlphaMode = LL_DMA2D_ALPHA_MODE_NO_MODIF;
+ DMA2D_LayerCfg->Alpha = 0x0U;
+ DMA2D_LayerCfg->Blue = 0x0U;
+ DMA2D_LayerCfg->Green = 0x0U;
+ DMA2D_LayerCfg->Red = 0x0U;
+ DMA2D_LayerCfg->CLUTMemoryAddress = 0x0U;
+ DMA2D_LayerCfg->AlphaInversionMode = LL_DMA2D_ALPHA_REGULAR;
+ DMA2D_LayerCfg->RBSwapMode = LL_DMA2D_RB_MODE_REGULAR;
+}
+
+/**
+ * @brief Initialize DMA2D output color register according to the specified parameters
+ * in DMA2D_ColorStruct.
+ * @param DMA2Dx DMA2D Instance
+ * @param DMA2D_ColorStruct pointer to a LL_DMA2D_ColorTypeDef structure that contains
+ * the color configuration information for the specified DMA2D peripheral.
+ * @retval None
+ */
+void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct)
+{
+ uint32_t outgreen;
+ uint32_t outred;
+ uint32_t outalpha;
+
+ /* Check the parameters */
+ assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
+ assert_param(IS_LL_DMA2D_OCMODE(DMA2D_ColorStruct->ColorMode));
+ assert_param(IS_LL_DMA2D_GREEN(DMA2D_ColorStruct->OutputGreen));
+ assert_param(IS_LL_DMA2D_RED(DMA2D_ColorStruct->OutputRed));
+ assert_param(IS_LL_DMA2D_BLUE(DMA2D_ColorStruct->OutputBlue));
+ assert_param(IS_LL_DMA2D_ALPHA(DMA2D_ColorStruct->OutputAlpha));
+
+ /* DMA2D OCOLR register configuration ------------------------------------------*/
+ if (DMA2D_ColorStruct->ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888)
+ {
+ outgreen = DMA2D_ColorStruct->OutputGreen << 8U;
+ outred = DMA2D_ColorStruct->OutputRed << 16U;
+ outalpha = DMA2D_ColorStruct->OutputAlpha << 24U;
+ }
+ else if (DMA2D_ColorStruct->ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888)
+ {
+ outgreen = DMA2D_ColorStruct->OutputGreen << 8U;
+ outred = DMA2D_ColorStruct->OutputRed << 16U;
+ outalpha = 0x00000000U;
+ }
+ else if (DMA2D_ColorStruct->ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565)
+ {
+ outgreen = DMA2D_ColorStruct->OutputGreen << 5U;
+ outred = DMA2D_ColorStruct->OutputRed << 11U;
+ outalpha = 0x00000000U;
+ }
+ else if (DMA2D_ColorStruct->ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555)
+ {
+ outgreen = DMA2D_ColorStruct->OutputGreen << 5U;
+ outred = DMA2D_ColorStruct->OutputRed << 10U;
+ outalpha = DMA2D_ColorStruct->OutputAlpha << 15U;
+ }
+ else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */
+ {
+ outgreen = DMA2D_ColorStruct->OutputGreen << 4U;
+ outred = DMA2D_ColorStruct->OutputRed << 8U;
+ outalpha = DMA2D_ColorStruct->OutputAlpha << 12U;
+ }
+ LL_DMA2D_SetOutputColor(DMA2Dx, (outgreen | outred | DMA2D_ColorStruct->OutputBlue | outalpha));
+}
+
+/**
+ * @brief Return DMA2D output Blue color.
+ * @param DMA2Dx DMA2D Instance.
+ * @param ColorMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
+ * @retval Output Blue color value between Min_Data=0 and Max_Data=0xFF
+ */
+uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
+{
+ uint32_t color;
+
+ /* Check the parameters */
+ assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
+ assert_param(IS_LL_DMA2D_OCMODE(ColorMode));
+
+ /* DMA2D OCOLR register reading ------------------------------------------*/
+ if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888)
+ {
+ color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFFU));
+ }
+ else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888)
+ {
+ color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFFU));
+ }
+ else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565)
+ {
+ color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x1FU));
+ }
+ else if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555)
+ {
+ color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x1FU));
+ }
+ else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */
+ {
+ color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFU));
+ }
+
+ return color;
+}
+
+/**
+ * @brief Return DMA2D output Green color.
+ * @param DMA2Dx DMA2D Instance.
+ * @param ColorMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
+ * @retval Output Green color value between Min_Data=0 and Max_Data=0xFF
+ */
+uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
+{
+ uint32_t color;
+
+ /* Check the parameters */
+ assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
+ assert_param(IS_LL_DMA2D_OCMODE(ColorMode));
+
+ /* DMA2D OCOLR register reading ------------------------------------------*/
+ if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888)
+ {
+ color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF00U) >> 8U);
+ }
+ else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888)
+ {
+ color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF00U) >> 8U);
+ }
+ else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565)
+ {
+ color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x7E0U) >> 5U);
+ }
+ else if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555)
+ {
+ color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x3E0U) >> 5U);
+ }
+ else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */
+ {
+ color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF0U) >> 4U);
+ }
+
+ return color;
+}
+
+/**
+ * @brief Return DMA2D output Red color.
+ * @param DMA2Dx DMA2D Instance.
+ * @param ColorMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
+ * @retval Output Red color value between Min_Data=0 and Max_Data=0xFF
+ */
+uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
+{
+ uint32_t color;
+
+ /* Check the parameters */
+ assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
+ assert_param(IS_LL_DMA2D_OCMODE(ColorMode));
+
+ /* DMA2D OCOLR register reading ------------------------------------------*/
+ if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888)
+ {
+ color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF0000U) >> 16U);
+ }
+ else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888)
+ {
+ color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF0000U) >> 16U);
+ }
+ else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565)
+ {
+ color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF800U) >> 11U);
+ }
+ else if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555)
+ {
+ color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x7C00U) >> 10U);
+ }
+ else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */
+ {
+ color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF00U) >> 8U);
+ }
+
+ return color;
+}
+
+/**
+ * @brief Return DMA2D output Alpha color.
+ * @param DMA2Dx DMA2D Instance.
+ * @param ColorMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
+ * @retval Output Alpha color value between Min_Data=0 and Max_Data=0xFF
+ */
+uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
+{
+ uint32_t color;
+
+ /* Check the parameters */
+ assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
+ assert_param(IS_LL_DMA2D_OCMODE(ColorMode));
+
+ /* DMA2D OCOLR register reading ------------------------------------------*/
+ if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888)
+ {
+ color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF000000U) >> 24U);
+ }
+ else if ((ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888) || (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565))
+ {
+ color = 0x0U;
+ }
+ else if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555)
+ {
+ color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x8000U) >> 15U);
+ }
+ else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */
+ {
+ color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF000U) >> 12U);
+ }
+
+ return color;
+}
+
+/**
+ * @brief Configure DMA2D transfer size.
+ * @param DMA2Dx DMA2D Instance
+ * @param NbrOfLines Value between Min_Data=0 and Max_Data=0xFFFF
+ * @param NbrOfPixelsPerLines Value between Min_Data=0 and Max_Data=0x3FFF
+ * @retval None
+ */
+void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines)
+{
+ MODIFY_REG(DMA2Dx->NLR, (DMA2D_NLR_PL | DMA2D_NLR_NL), \
+ ((NbrOfPixelsPerLines << DMA2D_NLR_PL_Pos) | NbrOfLines));
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (DMA2D) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_exti.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_exti.c
new file mode 100644
index 00000000..7ca50735
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_exti.c
@@ -0,0 +1,217 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_exti.c
+ * @author MCD Application Team
+ * @brief EXTI LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_ll_exti.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined (EXTI)
+
+/** @defgroup EXTI_LL EXTI
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup EXTI_LL_Private_Macros
+ * @{
+ */
+
+#define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
+
+#define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \
+ || ((__VALUE__) == LL_EXTI_MODE_EVENT) \
+ || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
+
+
+#define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \
+ || ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \
+ || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \
+ || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup EXTI_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup EXTI_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the EXTI registers to their default reset values.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: EXTI registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_EXTI_DeInit(void)
+{
+ /* Interrupt mask register set to default reset values */
+ LL_EXTI_WriteReg(IMR1, 0xFF9E0000U);
+ /* Event mask register set to default reset values */
+ LL_EXTI_WriteReg(EMR1, 0x00000000U);
+ /* Rising Trigger selection register set to default reset values */
+ LL_EXTI_WriteReg(RTSR1, 0x00000000U);
+ /* Falling Trigger selection register set to default reset values */
+ LL_EXTI_WriteReg(FTSR1, 0x00000000U);
+ /* Software interrupt event register set to default reset values */
+ LL_EXTI_WriteReg(SWIER1, 0x00000000U);
+ /* Pending register set to default reset values */
+ LL_EXTI_WriteReg(RPR1, 0xFFFFFFFFU);
+ LL_EXTI_WriteReg(FPR1, 0xFFFFFFFFU);
+ /* Privilege register set to default reset values */
+ LL_EXTI_WriteReg(PRIVCFGR1, 0x00000000U);
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ /* Secure register set to default reset values */
+ LL_EXTI_WriteReg(SECCFGR1, 0x00000000U);
+#endif /* __ARM_FEATURE_CMSE */
+ return SUCCESS;
+}
+
+/**
+ * @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
+ * @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: EXTI registers are initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+ /* Check the parameters */
+ assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
+ assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
+ assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
+
+ /* ENABLE LineCommand */
+ if (EXTI_InitStruct->LineCommand != DISABLE)
+ {
+ assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
+
+ /* Configure EXTI Lines in range from 0 to 31 */
+ if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
+ {
+ switch (EXTI_InitStruct->Mode)
+ {
+ case LL_EXTI_MODE_IT:
+ /* First Disable Event on provided Lines */
+ LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
+ /* Then Enable IT on provided Lines */
+ LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ case LL_EXTI_MODE_EVENT:
+ /* First Disable IT on provided Lines */
+ LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
+ /* Then Enable Event on provided Lines */
+ LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ case LL_EXTI_MODE_IT_EVENT:
+ /* Directly Enable IT & Event on provided Lines */
+ LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
+ LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ default:
+ status = ERROR;
+ break;
+ }
+ if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
+ {
+ switch (EXTI_InitStruct->Trigger)
+ {
+ case LL_EXTI_TRIGGER_RISING:
+ /* First Disable Falling Trigger on provided Lines */
+ LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ /* Then Enable Rising Trigger on provided Lines */
+ LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ case LL_EXTI_TRIGGER_FALLING:
+ /* First Disable Rising Trigger on provided Lines */
+ LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ /* Then Enable Falling Trigger on provided Lines */
+ LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ case LL_EXTI_TRIGGER_RISING_FALLING:
+ LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ default:
+ status = ERROR;
+ break;
+ }
+ }
+ }
+ }
+ /* DISABLE LineCommand */
+ else
+ {
+ /* De-configure EXTI Lines in range from 0 to 31 */
+ LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
+ LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_EXTI_InitTypeDef field to default value.
+ * @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
+ * @retval None
+ */
+void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
+{
+ EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE;
+ EXTI_InitStruct->LineCommand = DISABLE;
+ EXTI_InitStruct->Mode = LL_EXTI_MODE_IT;
+ EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (EXTI) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_fmac.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_fmac.c
new file mode 100644
index 00000000..ecef33c5
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_fmac.c
@@ -0,0 +1,136 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_fmac.c
+ * @author MCD Application Team
+ * @brief Header for stm32u5xx_ll_fmac.c module
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_ll_fmac.h"
+#include "stm32u5xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined(FMAC)
+
+/** @addtogroup FMAC_LL
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Global variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Functions Definition ------------------------------------------------------*/
+/** @addtogroup FMAC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup FMAC_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief Initialize FMAC peripheral registers to their default reset values.
+ * @param FMACx FMAC Instance
+ * @retval ErrorStatus enumeration value:
+ * - SUCCESS: FMAC registers are initialized
+ * - ERROR: FMAC registers are not initialized
+ */
+ErrorStatus LL_FMAC_Init(FMAC_TypeDef *FMACx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_FMAC_ALL_INSTANCE(FMACx));
+
+ if (FMACx == FMAC)
+ {
+ /* Perform the reset */
+ LL_FMAC_EnableReset(FMACx);
+
+ /* Wait until flag is reset */
+ while (LL_FMAC_IsEnabledReset(FMACx) != 0UL)
+ {
+ }
+ }
+ else
+ {
+ status = ERROR;
+ }
+
+ return (status);
+}
+
+/**
+ * @brief De-Initialize FMAC peripheral registers to their default reset values.
+ * @param FMACx FMAC Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: FMAC registers are de-initialized
+ * - ERROR: FMAC registers are not de-initialized
+ */
+ErrorStatus LL_FMAC_DeInit(FMAC_TypeDef *FMACx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_FMAC_ALL_INSTANCE(FMACx));
+
+ if (FMACx == FMAC)
+ {
+ /* Force FMAC reset */
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_FMAC);
+
+ /* Release FMAC reset */
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_FMAC);
+ }
+ else
+ {
+ status = ERROR;
+ }
+
+ return (status);
+}
+
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(FMAC) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_fmc.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_fmc.c
new file mode 100644
index 00000000..9605fab3
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_fmc.c
@@ -0,0 +1,798 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_fmc.c
+ * @author MCD Application Team
+ * @brief FMC Low Layer HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the Flexible Memory Controller (FMC) peripheral memories:
+ * + Initialization/de-initialization functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### FMC peripheral features #####
+ ==============================================================================
+ [..] The Flexible memory controller (FMC) includes following memory controllers:
+ (+) The NOR/PSRAM memory controller
+ (+) The NAND memory controller
+
+ [..] The FMC functional block makes the interface with synchronous and asynchronous static
+ memories. Its main purposes are:
+ (+) to translate AHB transactions into the appropriate external device protocol
+ (+) to meet the access time requirements of the external memory devices
+
+ [..] All external memories share the addresses, data and control signals with the controller.
+ Each external device is accessed by means of a unique Chip Select. The FMC performs
+ only one access at a time to an external device.
+ The main features of the FMC controller are the following:
+ (+) Interface with static-memory mapped devices including:
+ (++) Static random access memory (SRAM)
+ (++) Read-only memory (ROM)
+ (++) NOR Flash memory/OneNAND Flash memory
+ (++) PSRAM (4 memory banks)
+ (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
+ data
+ (+) Independent Chip Select control for each memory bank
+ (+) Independent configuration for each memory bank
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED)
+
+/** @defgroup FMC_LL FMC Low Layer
+ * @brief FMC driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup FMC_LL_Private_Constants FMC Low Layer Private Constants
+ * @{
+ */
+
+/* ----------------------- FMC registers bit mask --------------------------- */
+
+/* --- BCR Register ---*/
+/* BCR register clear mask */
+
+/* --- BTR Register ---*/
+/* BTR register clear mask */
+#define BTR_CLEAR_MASK ((uint32_t)(FMC_BTRx_ADDSET | FMC_BTRx_ADDHLD |\
+ FMC_BTRx_DATAST | FMC_BTRx_BUSTURN |\
+ FMC_BTRx_CLKDIV | FMC_BTRx_DATLAT |\
+ FMC_BTRx_ACCMOD | FMC_BTRx_DATAHLD))
+
+/* --- BWTR Register ---*/
+/* BWTR register clear mask */
+#define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\
+ FMC_BWTRx_DATAST | FMC_BWTRx_BUSTURN |\
+ FMC_BWTRx_ACCMOD | FMC_BWTRx_DATAHLD))
+
+/* --- PCR Register ---*/
+/* PCR register clear mask */
+#define PCR_CLEAR_MASK ((uint32_t)(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | \
+ FMC_PCR_PTYP | FMC_PCR_PWID | \
+ FMC_PCR_ECCEN | FMC_PCR_TCLR | \
+ FMC_PCR_TAR | FMC_PCR_ECCPS))
+/* --- PMEM Register ---*/
+/* PMEM register clear mask */
+#define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEM_MEMSET | FMC_PMEM_MEMWAIT |\
+ FMC_PMEM_MEMHOLD | FMC_PMEM_MEMHIZ))
+
+/* --- PATT Register ---*/
+/* PATT register clear mask */
+#define PATT_CLEAR_MASK ((uint32_t)(FMC_PATT_ATTSET | FMC_PATT_ATTWAIT |\
+ FMC_PATT_ATTHOLD | FMC_PATT_ATTHIZ))
+
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions
+ * @{
+ */
+
+
+/** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions
+ * @brief NORSRAM Controller functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use NORSRAM device driver #####
+ ==============================================================================
+
+ [..]
+ This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
+ to run the NORSRAM external devices.
+
+ (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
+ (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
+ (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
+ (+) FMC NORSRAM bank extended timing configuration using the function
+ FMC_NORSRAM_Extended_Timing_Init()
+ (+) FMC NORSRAM bank enable/disable write operation using the functions
+ FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
+
+@endverbatim
+ * @{
+ */
+
+/** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### Initialization and de_initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the FMC NORSRAM interface
+ (+) De-initialize the FMC NORSRAM interface
+ (+) Configure the FMC clock and associated GPIOs
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the FMC_NORSRAM device according to the specified
+ * control parameters in the FMC_NORSRAM_InitTypeDef
+ * @param Device Pointer to NORSRAM device instance
+ * @param Init Pointer to NORSRAM Initialization structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
+ FMC_NORSRAM_InitTypeDef *Init)
+{
+ uint32_t flashaccess;
+ uint32_t btcr_reg;
+ uint32_t mask;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_NORSRAM_DEVICE(Device));
+ assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
+ assert_param(IS_FMC_MUX(Init->DataAddressMux));
+ assert_param(IS_FMC_MEMORY(Init->MemoryType));
+ assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
+ assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
+ assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
+ assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
+ assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
+ assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
+ assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
+ assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
+ assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
+ assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
+ assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));
+ assert_param(IS_FMC_PAGESIZE(Init->PageSize));
+ assert_param(IS_FMC_NBL_SETUPTIME(Init->NBLSetupTime));
+ assert_param(IS_FUNCTIONAL_STATE(Init->MaxChipSelectPulse));
+
+ /* Disable NORSRAM Device */
+ __FMC_NORSRAM_DISABLE(Device, Init->NSBank);
+
+ /* Set NORSRAM device control parameters */
+ if (Init->MemoryType == FMC_MEMORY_TYPE_NOR)
+ {
+ flashaccess = FMC_NORSRAM_FLASH_ACCESS_ENABLE;
+ }
+ else
+ {
+ flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE;
+ }
+
+ btcr_reg = (flashaccess | \
+ Init->DataAddressMux | \
+ Init->MemoryType | \
+ Init->MemoryDataWidth | \
+ Init->BurstAccessMode | \
+ Init->WaitSignalPolarity | \
+ Init->WaitSignalActive | \
+ Init->WriteOperation | \
+ Init->WaitSignal | \
+ Init->ExtendedMode | \
+ Init->AsynchronousWait | \
+ Init->WriteBurst);
+
+ btcr_reg |= Init->ContinuousClock;
+ btcr_reg |= Init->WriteFifo;
+ btcr_reg |= Init->NBLSetupTime;
+ btcr_reg |= Init->PageSize;
+
+ mask = (FMC_BCRx_MBKEN |
+ FMC_BCRx_MUXEN |
+ FMC_BCRx_MTYP |
+ FMC_BCRx_MWID |
+ FMC_BCRx_FACCEN |
+ FMC_BCRx_BURSTEN |
+ FMC_BCRx_WAITPOL |
+ FMC_BCRx_WAITCFG |
+ FMC_BCRx_WREN |
+ FMC_BCRx_WAITEN |
+ FMC_BCRx_EXTMOD |
+ FMC_BCRx_ASYNCWAIT |
+ FMC_BCRx_CBURSTRW);
+
+ mask |= FMC_BCR1_CCLKEN;
+ mask |= FMC_BCR1_WFDIS;
+ mask |= FMC_BCRx_NBLSET;
+ mask |= FMC_BCRx_CPSIZE;
+
+ MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);
+
+ /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
+ if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
+ {
+ MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock);
+ }
+
+ if (Init->NSBank != FMC_NORSRAM_BANK1)
+ {
+ /* Configure Write FIFO mode when Write Fifo is enabled for bank2..4 */
+ SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo));
+ }
+
+ /* Check PSRAM chip select counter state */
+ if (Init->MaxChipSelectPulse == ENABLE)
+ {
+ /* Check the parameters */
+ assert_param(IS_FMC_MAX_CHIP_SELECT_PULSE_TIME(Init->MaxChipSelectPulseTime));
+
+ /* Configure PSRAM chip select counter value */
+ MODIFY_REG(Device->PCSCNTR, FMC_PCSCNTR_CSCOUNT, (uint32_t)(Init->MaxChipSelectPulseTime));
+
+ /* Enable PSRAM chip select counter for the bank */
+ switch (Init->NSBank)
+ {
+ case FMC_NORSRAM_BANK1 :
+ SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB1EN);
+ break;
+
+ case FMC_NORSRAM_BANK2 :
+ SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB2EN);
+ break;
+
+ case FMC_NORSRAM_BANK3 :
+ SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN);
+ break;
+
+ default :
+ SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN);
+ break;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitialize the FMC_NORSRAM peripheral
+ * @param Device Pointer to NORSRAM device instance
+ * @param ExDevice Pointer to NORSRAM extended mode device instance
+ * @param Bank NORSRAM bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
+ FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NORSRAM_DEVICE(Device));
+ assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
+ assert_param(IS_FMC_NORSRAM_BANK(Bank));
+
+ /* Disable the FMC_NORSRAM device */
+ __FMC_NORSRAM_DISABLE(Device, Bank);
+
+ /* De-initialize the FMC_NORSRAM device */
+ /* FMC_NORSRAM_BANK1 */
+ if (Bank == FMC_NORSRAM_BANK1)
+ {
+ Device->BTCR[Bank] = 0x000030DBU;
+ }
+ /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
+ else
+ {
+ Device->BTCR[Bank] = 0x000030D2U;
+ }
+
+ Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
+ ExDevice->BWTR[Bank] = 0x0FFFFFFFU;
+
+ /* De-initialize PSRAM chip select counter */
+ switch (Bank)
+ {
+ case FMC_NORSRAM_BANK1 :
+ CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB1EN);
+ break;
+
+ case FMC_NORSRAM_BANK2 :
+ CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB2EN);
+ break;
+
+ case FMC_NORSRAM_BANK3 :
+ CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN);
+ break;
+
+ default :
+ CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN);
+ break;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the FMC_NORSRAM Timing according to the specified
+ * parameters in the FMC_NORSRAM_TimingTypeDef
+ * @param Device Pointer to NORSRAM device instance
+ * @param Timing Pointer to NORSRAM Timing structure
+ * @param Bank NORSRAM bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
+ FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
+{
+ uint32_t tmpr;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_NORSRAM_DEVICE(Device));
+ assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
+ assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
+ assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime));
+ assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
+ assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
+ assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
+ assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
+ assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
+ assert_param(IS_FMC_NORSRAM_BANK(Bank));
+
+ /* Set FMC_NORSRAM device timing parameters */
+ MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime |
+ ((Timing->AddressHoldTime) << FMC_BTRx_ADDHLD_Pos) |
+ ((Timing->DataSetupTime) << FMC_BTRx_DATAST_Pos) |
+ ((Timing->DataHoldTime) << FMC_BTRx_DATAHLD_Pos) |
+ ((Timing->BusTurnAroundDuration) << FMC_BTRx_BUSTURN_Pos) |
+ (((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos) |
+ (((Timing->DataLatency) - 2U) << FMC_BTRx_DATLAT_Pos) |
+ (Timing->AccessMode)));
+
+ /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
+ if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
+ {
+ tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos));
+ tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos);
+ MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
+ * parameters in the FMC_NORSRAM_TimingTypeDef
+ * @param Device Pointer to NORSRAM device instance
+ * @param Timing Pointer to NORSRAM Timing structure
+ * @param Bank NORSRAM bank number
+ * @param ExtendedMode FMC Extended Mode
+ * This parameter can be one of the following values:
+ * @arg FMC_EXTENDED_MODE_DISABLE
+ * @arg FMC_EXTENDED_MODE_ENABLE
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
+ FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
+ uint32_t ExtendedMode)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
+
+ /* Set NORSRAM device timing register for write configuration, if extended mode is used */
+ if (ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
+ {
+ /* Check the parameters */
+ assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
+ assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
+ assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
+ assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
+ assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime));
+ assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
+ assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
+ assert_param(IS_FMC_NORSRAM_BANK(Bank));
+
+ /* Set NORSRAM device timing register for write configuration, if extended mode is used */
+ MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime |
+ ((Timing->AddressHoldTime) << FMC_BWTRx_ADDHLD_Pos) |
+ ((Timing->DataSetupTime) << FMC_BWTRx_DATAST_Pos) |
+ ((Timing->DataHoldTime) << FMC_BWTRx_DATAHLD_Pos) |
+ Timing->AccessMode |
+ ((Timing->BusTurnAroundDuration) << FMC_BWTRx_BUSTURN_Pos)));
+ }
+ else
+ {
+ Device->BWTR[Bank] = 0x0FFFFFFFU;
+ }
+
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2
+ * @brief management functions
+ *
+@verbatim
+ ==============================================================================
+ ##### FMC_NORSRAM Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control dynamically
+ the FMC NORSRAM interface.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables dynamically FMC_NORSRAM write operation.
+ * @param Device Pointer to NORSRAM device instance
+ * @param Bank NORSRAM bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NORSRAM_DEVICE(Device));
+ assert_param(IS_FMC_NORSRAM_BANK(Bank));
+
+ /* Enable write operation */
+ SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables dynamically FMC_NORSRAM write operation.
+ * @param Device Pointer to NORSRAM device instance
+ * @param Bank NORSRAM bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NORSRAM_DEVICE(Device));
+ assert_param(IS_FMC_NORSRAM_BANK(Bank));
+
+ /* Disable write operation */
+ CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions
+ * @brief NAND Controller functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use NAND device driver #####
+ ==============================================================================
+ [..]
+ This driver contains a set of APIs to interface with the FMC NAND banks in order
+ to run the NAND external devices.
+
+ (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
+ (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
+ (+) FMC NAND bank common space timing configuration using the function
+ FMC_NAND_CommonSpace_Timing_Init()
+ (+) FMC NAND bank attribute space timing configuration using the function
+ FMC_NAND_AttributeSpace_Timing_Init()
+ (+) FMC NAND bank enable/disable ECC correction feature using the functions
+ FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
+ (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
+
+@endverbatim
+ * @{
+ */
+
+/** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de_initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the FMC NAND interface
+ (+) De-initialize the FMC NAND interface
+ (+) Configure the FMC clock and associated GPIOs
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the FMC_NAND device according to the specified
+ * control parameters in the FMC_NAND_HandleTypeDef
+ * @param Device Pointer to NAND device instance
+ * @param Init Pointer to NAND Initialization structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_NAND_BANK(Init->NandBank));
+ assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
+ assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
+ assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
+ assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
+ assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
+ assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
+
+ /* NAND bank 3 registers configuration */
+ MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature |
+ FMC_PCR_MEMORY_TYPE_NAND |
+ Init->MemoryDataWidth |
+ Init->EccComputation |
+ Init->ECCPageSize |
+ ((Init->TCLRSetupTime) << FMC_PCR_TCLR_Pos) |
+ ((Init->TARSetupTime) << FMC_PCR_TAR_Pos)));
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the FMC_NAND Common space Timing according to the specified
+ * parameters in the FMC_NAND_PCC_TimingTypeDef
+ * @param Device Pointer to NAND device instance
+ * @param Timing Pointer to NAND timing structure
+ * @param Bank NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
+ FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
+ assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
+ assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
+ assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Prevent unused argument(s) compilation warning if no assert_param check */
+ UNUSED(Bank);
+
+ /* NAND bank 3 registers configuration */
+ MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime |
+ ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) |
+ ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD_Pos) |
+ ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos)));
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
+ * parameters in the FMC_NAND_PCC_TimingTypeDef
+ * @param Device Pointer to NAND device instance
+ * @param Timing Pointer to NAND timing structure
+ * @param Bank NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
+ FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
+ assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
+ assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
+ assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Prevent unused argument(s) compilation warning if no assert_param check */
+ UNUSED(Bank);
+
+ /* NAND bank 3 registers configuration */
+ MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime |
+ ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) |
+ ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) |
+ ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ_Pos)));
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the FMC_NAND device
+ * @param Device Pointer to NAND device instance
+ * @param Bank NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Disable the NAND Bank */
+ __FMC_NAND_DISABLE(Device, Bank);
+
+ /* De-initialize the NAND Bank */
+ /* Prevent unused argument(s) compilation warning if no assert_param check */
+ UNUSED(Bank);
+
+ /* Set the FMC_NAND_BANK3 registers to their reset values */
+ WRITE_REG(Device->PCR, 0x00000018U);
+ WRITE_REG(Device->SR, 0x00000040U);
+ WRITE_REG(Device->PMEM, 0xFCFCFCFCU);
+ WRITE_REG(Device->PATT, 0xFCFCFCFCU);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_FMC_NAND_Group2 Peripheral Control functions
+ * @brief management functions
+ *
+@verbatim
+ ==============================================================================
+ ##### FMC_NAND Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control dynamically
+ the FMC NAND interface.
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Enables dynamically FMC_NAND ECC feature.
+ * @param Device Pointer to NAND device instance
+ * @param Bank NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Enable ECC feature */
+ /* Prevent unused argument(s) compilation warning if no assert_param check */
+ UNUSED(Bank);
+
+ SET_BIT(Device->PCR, FMC_PCR_ECCEN);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Disables dynamically FMC_NAND ECC feature.
+ * @param Device Pointer to NAND device instance
+ * @param Bank NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Disable ECC feature */
+ /* Prevent unused argument(s) compilation warning if no assert_param check */
+ UNUSED(Bank);
+
+ CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables dynamically FMC_NAND ECC feature.
+ * @param Device Pointer to NAND device instance
+ * @param ECCval Pointer to ECC value
+ * @param Bank NAND bank number
+ * @param Timeout Timeout wait value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
+ uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until FIFO is empty */
+ while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Prevent unused argument(s) compilation warning if no assert_param check */
+ UNUSED(Bank);
+
+ /* Get the ECCR register value */
+ *ECCval = (uint32_t)Device->ECCR;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_NOR_MODULE_ENABLED */
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_gpio.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_gpio.c
new file mode 100644
index 00000000..787238f5
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_gpio.c
@@ -0,0 +1,292 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_gpio.c
+ * @author MCD Application Team
+ * @brief GPIO LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_ll_gpio.h"
+#include "stm32u5xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || \
+ defined (GPIOG) || defined (GPIOH) || defined (GPIOI)
+
+/** @addtogroup GPIO_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup GPIO_LL_Private_Macros
+ * @{
+ */
+#define IS_LL_GPIO_PIN(__VALUE__) (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
+
+#define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\
+ ((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\
+ ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\
+ ((__VALUE__) == LL_GPIO_MODE_ANALOG))
+
+#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\
+ ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))
+
+#define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\
+ ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\
+ ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH) ||\
+ ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH))
+
+#define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_NO) ||\
+ ((__VALUE__) == LL_GPIO_PULL_UP) ||\
+ ((__VALUE__) == LL_GPIO_PULL_DOWN))
+
+#define IS_LL_GPIO_ALTERNATE(__VALUE__) (((__VALUE__) == LL_GPIO_AF_0 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_1 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_2 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_3 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_4 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_5 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_6 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_7 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_8 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_9 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_10 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_11 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_12 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_13 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_14 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_15 ))
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup GPIO_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup GPIO_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize GPIO registers (Registers restored to their default values).
+ * @param GPIOx GPIO Port
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: GPIO registers are de-initialized
+ * - ERROR: Wrong GPIO Port
+ */
+ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+
+ /* Force and Release reset on clock of GPIOx Port */
+ if (GPIOx == GPIOA)
+ {
+ LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOA);
+ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOA);
+ }
+ else if (GPIOx == GPIOB)
+ {
+ LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOB);
+ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOB);
+ }
+ else if (GPIOx == GPIOC)
+ {
+ LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOC);
+ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOC);
+ }
+#if defined(GPIOD)
+ else if (GPIOx == GPIOD)
+ {
+ LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOD);
+ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOD);
+ }
+#endif /* GPIOD */
+#if defined(GPIOE)
+ else if (GPIOx == GPIOE)
+ {
+ LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOE);
+ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOE);
+ }
+#endif /* GPIOE */
+#if defined(GPIOF)
+ else if (GPIOx == GPIOF)
+ {
+ LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOF);
+ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOF);
+ }
+#endif /* GPIOF */
+#if defined(GPIOG)
+ else if (GPIOx == GPIOG)
+ {
+ LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOG);
+ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOG);
+ }
+#endif /* GPIOG */
+#if defined(GPIOH)
+ else if (GPIOx == GPIOH)
+ {
+ LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOH);
+ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOH);
+ }
+#endif /* GPIOH */
+#if defined(GPIOI)
+ else if (GPIOx == GPIOI)
+ {
+ LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOI);
+ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOI);
+ }
+#endif /* GPIOI */
+ else
+ {
+ status = ERROR;
+ }
+
+ return (status);
+}
+
+/**
+ * @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
+ * @param GPIOx GPIO Port
+ * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure
+ * that contains the configuration information for the specified GPIO peripheral.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
+ * - ERROR: Not applicable
+ */
+ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
+{
+ uint32_t pinpos;
+ uint32_t currentpin;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+ assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));
+ assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
+ assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
+
+ /* ------------------------- Configure the port pins ---------------- */
+ /* Initialize pinpos on first pin set */
+ pinpos = POSITION_VAL(GPIO_InitStruct->Pin);
+
+ /* Configure the port pins */
+ while (((GPIO_InitStruct->Pin) >> pinpos) != 0U)
+ {
+ /* Get current io position */
+ currentpin = (GPIO_InitStruct->Pin) & (1UL << pinpos);
+
+ if (currentpin != 0U)
+ {
+ /* Pin Mode configuration */
+ LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
+
+ if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
+ {
+ /* Check Speed mode parameters */
+ assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed));
+
+ /* Speed mode configuration */
+ LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
+ }
+
+ /* Pull-up Pull down resistor configuration*/
+ LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
+
+ if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)
+ {
+ /* Check Alternate parameter */
+ assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate));
+
+ /* Speed mode configuration */
+ if (POSITION_VAL(currentpin) < 8U)
+ {
+ LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate);
+ }
+ else
+ {
+ LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
+ }
+ }
+ }
+ pinpos++;
+ }
+
+ if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
+ {
+ /* Check Output mode parameters */
+ assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
+
+ /* Output mode configuration*/
+ LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
+
+ }
+ return (SUCCESS);
+}
+
+/**
+ * @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
+ * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+
+void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
+{
+ /* Reset GPIO init structure parameters values */
+ GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL;
+ GPIO_InitStruct->Mode = LL_GPIO_MODE_ANALOG;
+ GPIO_InitStruct->Speed = LL_GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ GPIO_InitStruct->Pull = LL_GPIO_PULL_NO;
+ GPIO_InitStruct->Alternate = LL_GPIO_AF_0;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || \
+ defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_i2c.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_i2c.c
new file mode 100644
index 00000000..a00108a8
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_i2c.c
@@ -0,0 +1,240 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_i2c.c
+ * @author MCD Application Team
+ * @brief I2C LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_ll_i2c.h"
+#include "stm32u5xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4)
+
+/** @defgroup I2C_LL I2C
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup I2C_LL_Private_Macros
+ * @{
+ */
+
+#define IS_LL_I2C_PERIPHERAL_MODE(__VALUE__) (((__VALUE__) == LL_I2C_MODE_I2C) || \
+ ((__VALUE__) == LL_I2C_MODE_SMBUS_HOST) || \
+ ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \
+ ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP))
+
+#define IS_LL_I2C_ANALOG_FILTER(__VALUE__) (((__VALUE__) == LL_I2C_ANALOGFILTER_ENABLE) || \
+ ((__VALUE__) == LL_I2C_ANALOGFILTER_DISABLE))
+
+#define IS_LL_I2C_DIGITAL_FILTER(__VALUE__) ((__VALUE__) <= 0x0000000FU)
+
+#define IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU)
+
+#define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__) (((__VALUE__) == LL_I2C_ACK) || \
+ ((__VALUE__) == LL_I2C_NACK))
+
+#define IS_LL_I2C_OWN_ADDRSIZE(__VALUE__) (((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \
+ ((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT))
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2C_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup I2C_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the I2C registers to their default reset values.
+ * @param I2Cx I2C Instance.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: I2C registers are de-initialized
+ * - ERROR: I2C registers are not de-initialized
+ */
+ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the I2C Instance I2Cx */
+ assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
+
+ if (I2Cx == I2C1)
+ {
+ /* Force reset of I2C clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1);
+
+ /* Release reset of I2C clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1);
+ }
+ else if (I2Cx == I2C2)
+ {
+ /* Force reset of I2C clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2);
+
+ /* Release reset of I2C clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2);
+
+ }
+ else if (I2Cx == I2C3)
+ {
+ /* Force reset of I2C clock */
+ LL_APB3_GRP1_ForceReset(LL_APB3_GRP1_PERIPH_I2C3);
+
+ /* Release reset of I2C clock */
+ LL_APB3_GRP1_ReleaseReset(LL_APB3_GRP1_PERIPH_I2C3);
+ }
+ else if (I2Cx == I2C4)
+ {
+ /* Force reset of I2C clock */
+ LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_I2C4);
+
+ /* Release reset of I2C clock */
+ LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_I2C4);
+ }
+ else
+ {
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
+ * @param I2Cx I2C Instance.
+ * @param I2C_InitStruct pointer to a @ref LL_I2C_InitTypeDef structure.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: I2C registers are initialized
+ * - ERROR: Not applicable
+ */
+ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
+{
+ /* Check the I2C Instance I2Cx */
+ assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
+
+ /* Check the I2C parameters from I2C_InitStruct */
+ assert_param(IS_LL_I2C_PERIPHERAL_MODE(I2C_InitStruct->PeripheralMode));
+ assert_param(IS_LL_I2C_ANALOG_FILTER(I2C_InitStruct->AnalogFilter));
+ assert_param(IS_LL_I2C_DIGITAL_FILTER(I2C_InitStruct->DigitalFilter));
+ assert_param(IS_LL_I2C_OWN_ADDRESS1(I2C_InitStruct->OwnAddress1));
+ assert_param(IS_LL_I2C_TYPE_ACKNOWLEDGE(I2C_InitStruct->TypeAcknowledge));
+ assert_param(IS_LL_I2C_OWN_ADDRSIZE(I2C_InitStruct->OwnAddrSize));
+
+ /* Disable the selected I2Cx Peripheral */
+ LL_I2C_Disable(I2Cx);
+
+ /*---------------------------- I2Cx CR1 Configuration ------------------------
+ * Configure the analog and digital noise filters with parameters :
+ * - AnalogFilter: I2C_CR1_ANFOFF bit
+ * - DigitalFilter: I2C_CR1_DNF[3:0] bits
+ */
+ LL_I2C_ConfigFilters(I2Cx, I2C_InitStruct->AnalogFilter, I2C_InitStruct->DigitalFilter);
+
+ /*---------------------------- I2Cx TIMINGR Configuration --------------------
+ * Configure the SDA setup, hold time and the SCL high, low period with parameter :
+ * - Timing: I2C_TIMINGR_PRESC[3:0], I2C_TIMINGR_SCLDEL[3:0], I2C_TIMINGR_SDADEL[3:0],
+ * I2C_TIMINGR_SCLH[7:0] and I2C_TIMINGR_SCLL[7:0] bits
+ */
+ LL_I2C_SetTiming(I2Cx, I2C_InitStruct->Timing);
+
+ /* Enable the selected I2Cx Peripheral */
+ LL_I2C_Enable(I2Cx);
+
+ /*---------------------------- I2Cx OAR1 Configuration -----------------------
+ * Disable, Configure and Enable I2Cx device own address 1 with parameters :
+ * - OwnAddress1: I2C_OAR1_OA1[9:0] bits
+ * - OwnAddrSize: I2C_OAR1_OA1MODE bit
+ */
+ LL_I2C_DisableOwnAddress1(I2Cx);
+ LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize);
+
+ /* OwnAdress1 == 0 is reserved for General Call address */
+ if (I2C_InitStruct->OwnAddress1 != 0U)
+ {
+ LL_I2C_EnableOwnAddress1(I2Cx);
+ }
+
+ /*---------------------------- I2Cx MODE Configuration -----------------------
+ * Configure I2Cx peripheral mode with parameter :
+ * - PeripheralMode: I2C_CR1_SMBDEN and I2C_CR1_SMBHEN bits
+ */
+ LL_I2C_SetMode(I2Cx, I2C_InitStruct->PeripheralMode);
+
+ /*---------------------------- I2Cx CR2 Configuration ------------------------
+ * Configure the ACKnowledge or Non ACKnowledge condition
+ * after the address receive match code or next received byte with parameter :
+ * - TypeAcknowledge: I2C_CR2_NACK bit
+ */
+ LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set each @ref LL_I2C_InitTypeDef field to default value.
+ * @param I2C_InitStruct Pointer to a @ref LL_I2C_InitTypeDef structure.
+ * @retval None
+ */
+void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct)
+{
+ /* Set I2C_InitStruct fields to default values */
+ I2C_InitStruct->PeripheralMode = LL_I2C_MODE_I2C;
+ I2C_InitStruct->Timing = 0U;
+ I2C_InitStruct->AnalogFilter = LL_I2C_ANALOGFILTER_ENABLE;
+ I2C_InitStruct->DigitalFilter = 0U;
+ I2C_InitStruct->OwnAddress1 = 0U;
+ I2C_InitStruct->TypeAcknowledge = LL_I2C_NACK;
+ I2C_InitStruct->OwnAddrSize = LL_I2C_OWNADDRESS1_7BIT;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* I2C1 || I2C2 || I2C3 || I2C4 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_icache.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_icache.c
new file mode 100644
index 00000000..b8d8c581
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_icache.c
@@ -0,0 +1,139 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_icache.c
+ * @author MCD Application Team
+ * @brief ICACHE LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_ll_icache.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined(ICACHE)
+
+/** @defgroup ICACHE_LL ICACHE
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup ICACHE_LL_Private_Macros
+ * @{
+ */
+
+#define IS_LL_ICACHE_REGION(__VALUE__) (((__VALUE__) == LL_ICACHE_REGION_0) || \
+ ((__VALUE__) == LL_ICACHE_REGION_1) || \
+ ((__VALUE__) == LL_ICACHE_REGION_2) || \
+ ((__VALUE__) == LL_ICACHE_REGION_3))
+
+#define IS_LL_ICACHE_REGION_SIZE(__VALUE__) (((__VALUE__) == LL_ICACHE_REGIONSIZE_2MB) || \
+ ((__VALUE__) == LL_ICACHE_REGIONSIZE_4MB) || \
+ ((__VALUE__) == LL_ICACHE_REGIONSIZE_8MB) || \
+ ((__VALUE__) == LL_ICACHE_REGIONSIZE_16MB) || \
+ ((__VALUE__) == LL_ICACHE_REGIONSIZE_32MB) || \
+ ((__VALUE__) == LL_ICACHE_REGIONSIZE_64MB) || \
+ ((__VALUE__) == LL_ICACHE_REGIONSIZE_128MB))
+
+#define IS_LL_ICACHE_MASTER_PORT(__VALUE__) (((__VALUE__) == LL_ICACHE_MASTER1_PORT) || \
+ ((__VALUE__) == LL_ICACHE_MASTER2_PORT))
+
+#define IS_LL_ICACHE_OUTPUT_BURST(__VALUE__) (((__VALUE__) == LL_ICACHE_OUTPUT_BURST_WRAP) || \
+ ((__VALUE__) == LL_ICACHE_OUTPUT_BURST_INCR))
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ICACHE_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup ICACHE_LL_EF_REGION_Init
+ * @{
+ */
+
+/**
+ * @brief Configure and enable the memory remapped region.
+ * @note The Instruction Cache and corresponding region must be disabled.
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_ICACHE_REGION_0
+ * @arg @ref LL_ICACHE_REGION_1
+ * @arg @ref LL_ICACHE_REGION_2
+ * @arg @ref LL_ICACHE_REGION_3
+ * @param pICACHE_RegionStruct pointer to a @ref LL_ICACHE_RegionTypeDef structure.
+ * @retval None
+ */
+void LL_ICACHE_ConfigRegion(uint32_t Region, const LL_ICACHE_RegionTypeDef *const pICACHE_RegionStruct)
+{
+ __IO uint32_t *p_reg;
+ uint32_t value;
+
+ /* Check the parameters */
+ assert_param(IS_LL_ICACHE_REGION(Region));
+ assert_param(IS_LL_ICACHE_REGION_SIZE(pICACHE_RegionStruct->Size));
+ assert_param(IS_LL_ICACHE_MASTER_PORT(pICACHE_RegionStruct->TrafficRoute));
+ assert_param(IS_LL_ICACHE_OUTPUT_BURST(pICACHE_RegionStruct->OutputBurstType));
+
+ /* Get region control register address */
+ p_reg = &(ICACHE->CRR0) + (1U * Region);
+
+ /* Region 2MB: BaseAddress size 8 bits, RemapAddress size 11 bits */
+ /* Region 4MB: BaseAddress size 7 bits, RemapAddress size 10 bits */
+ /* Region 8MB: BaseAddress size 6 bits, RemapAddress size 9 bits */
+ /* Region 16MB: BaseAddress size 5 bits, RemapAddress size 8 bits */
+ /* Region 32MB: BaseAddress size 4 bits, RemapAddress size 7 bits */
+ /* Region 64MB: BaseAddress size 3 bits, RemapAddress size 6 bits */
+ /* Region 128MB: BaseAddress size 2 bits, RemapAddress size 5 bits */
+ value = ((pICACHE_RegionStruct->BaseAddress & 0x1FFFFFFFU) >> 21U) & \
+ (0xFFU & ~(pICACHE_RegionStruct->Size - 1U));
+ value |= ((pICACHE_RegionStruct->RemapAddress >> 5U) & \
+ ((uint32_t)(0x7FFU & ~(pICACHE_RegionStruct->Size - 1U)) << ICACHE_CRRx_REMAPADDR_Pos));
+ value |= (pICACHE_RegionStruct->Size << ICACHE_CRRx_RSIZE_Pos) | pICACHE_RegionStruct->TrafficRoute | \
+ pICACHE_RegionStruct->OutputBurstType;
+ *p_reg = (value | ICACHE_CRRx_REN); /* Configure and enable region */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* ICACHE */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_lpgpio.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_lpgpio.c
new file mode 100644
index 00000000..2a81d437
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_lpgpio.c
@@ -0,0 +1,165 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_lpgpio.c
+ * @author MCD Application Team
+ * @brief LPGPIO LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_ll_lpgpio.h"
+#include "stm32u5xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined (LPGPIO1)
+
+/** @addtogroup LPGPIO_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup LPGPIO_LL_Private_Macros
+ * @{
+ */
+#define IS_LL_LPGPIO_PIN(__VALUE__) (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_LPGPIO_PIN_ALL)))
+
+#define IS_LL_LPGPIO_MODE(__VALUE__) (((__VALUE__) == LL_LPGPIO_MODE_INPUT) ||\
+ ((__VALUE__) == LL_LPGPIO_MODE_OUTPUT))
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup LPGPIO_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup LPGPIO_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize LPGPIO registers (Registers restored to their default values).
+ * @param LPGPIOx LPGPIO Port
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: LPGPIO registers are de-initialized
+ * - ERROR: Wrong LPGPIO Port
+ */
+ErrorStatus LL_LPGPIO_DeInit(GPIO_TypeDef *LPGPIOx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_LPGPIO_ALL_INSTANCE(LPGPIOx));
+
+ /* Force and Release reset on clock of LPGPIOx Port */
+ if (LPGPIOx == LPGPIO1)
+ {
+ LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_LPGPIO1);
+ LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_LPGPIO1);
+ }
+ else
+ {
+ status = ERROR;
+ }
+
+ return (status);
+}
+
+/**
+ * @brief Initialize LPGPIO registers according to the specified parameters in LPGPIO_InitStruct.
+ * @param LPGPIOx LPGPIO Port
+ * @param LPGPIO_InitStruct: pointer to a @ref LL_LPGPIO_InitTypeDef structure
+ * that contains the configuration information for the specified LPGPIO peripheral.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: LPGPIO registers are initialized according to LPGPIO_InitStruct content
+ * - ERROR: Not applicable
+ */
+ErrorStatus LL_LPGPIO_Init(GPIO_TypeDef *LPGPIOx, const LL_LPGPIO_InitTypeDef *const LPGPIO_InitStruct)
+{
+ uint32_t pinpos;
+ uint32_t currentpin;
+
+ /* Check the parameters */
+ assert_param(IS_LPGPIO_ALL_INSTANCE(LPGPIOx));
+ assert_param(IS_LL_LPGPIO_PIN(LPGPIO_InitStruct->Pin));
+ assert_param(IS_LL_LPGPIO_MODE(LPGPIO_InitStruct->Mode));
+
+ /* ------------------------- Configure the port pins ---------------- */
+ /* Initialize pinpos on first pin set */
+ pinpos = POSITION_VAL(LPGPIO_InitStruct->Pin);
+
+ /* Configure the port pins */
+ while (((LPGPIO_InitStruct->Pin) >> pinpos) != 0U)
+ {
+ /* Get current io position */
+ currentpin = (LPGPIO_InitStruct->Pin) & (1UL << pinpos);
+
+ if (currentpin != 0U)
+ {
+ /* Pin Mode configuration */
+ LL_LPGPIO_SetPinMode(LPGPIOx, currentpin, LPGPIO_InitStruct->Mode);
+ }
+ pinpos++;
+ }
+ return (SUCCESS);
+}
+
+/**
+ * @brief Set each @ref LL_LPGPIO_InitTypeDef field to default value.
+ * @param LPGPIO_InitStruct: pointer to a @ref LL_LPGPIO_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+
+void LL_LPGPIO_StructInit(LL_LPGPIO_InitTypeDef *LPGPIO_InitStruct)
+{
+ /* Reset LPGPIO init structure parameters values */
+ LPGPIO_InitStruct->Pin = LL_LPGPIO_PIN_ALL;
+ LPGPIO_InitStruct->Mode = LL_LPGPIO_MODE_INPUT;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (LPGPIO1) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_lptim.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_lptim.c
new file mode 100644
index 00000000..eb2f4663
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_lptim.c
@@ -0,0 +1,201 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_lptim.c
+ * @author MCD Application Team
+ * @brief LPTIM LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_ll_lptim.h"
+#include "stm32u5xx_ll_bus.h"
+#include "stm32u5xx_ll_rcc.h"
+
+
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3) || defined (LPTIM4)
+
+/** @addtogroup LPTIM_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup LPTIM_LL_Private_Macros
+ * @{
+ */
+#define IS_LL_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \
+ || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL))
+
+#define IS_LL_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128))
+
+#define IS_LL_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \
+ || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE))
+
+/**
+ * @}
+ */
+
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
+ * @{
+ */
+/**
+ * @}
+ */
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup LPTIM_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup LPTIM_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief Set LPTIMx registers to their reset values.
+ * @param LPTIMx LP Timer instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: LPTIMx registers are de-initialized
+ * - ERROR: invalid LPTIMx instance
+ */
+ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx)
+{
+ ErrorStatus result = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(LPTIMx));
+
+ if (LPTIMx == LPTIM1)
+ {
+ LL_APB3_GRP1_ForceReset(LL_APB3_GRP1_PERIPH_LPTIM1);
+ LL_APB3_GRP1_ReleaseReset(LL_APB3_GRP1_PERIPH_LPTIM1);
+ }
+ else if (LPTIMx == LPTIM2)
+ {
+ LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPTIM2);
+ LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPTIM2);
+ }
+ else if (LPTIMx == LPTIM3)
+ {
+ LL_APB3_GRP1_ForceReset(LL_APB3_GRP1_PERIPH_LPTIM3);
+ LL_APB3_GRP1_ReleaseReset(LL_APB3_GRP1_PERIPH_LPTIM3);
+ }
+ else if (LPTIMx == LPTIM4)
+ {
+ LL_APB3_GRP1_ForceReset(LL_APB3_GRP1_PERIPH_LPTIM4);
+ LL_APB3_GRP1_ReleaseReset(LL_APB3_GRP1_PERIPH_LPTIM4);
+ }
+ else
+ {
+ result = ERROR;
+ }
+
+ return result;
+}
+
+/**
+ * @brief Set each fields of the LPTIM_InitStruct structure to its default
+ * value.
+ * @param LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure
+ * @retval None
+ */
+void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
+{
+ /* Set the default configuration */
+ LPTIM_InitStruct->ClockSource = LL_LPTIM_CLK_SOURCE_INTERNAL;
+ LPTIM_InitStruct->Prescaler = LL_LPTIM_PRESCALER_DIV1;
+ LPTIM_InitStruct->Waveform = LL_LPTIM_OUTPUT_WAVEFORM_PWM;
+}
+
+/**
+ * @brief Configure the LPTIMx peripheral according to the specified parameters.
+ * @note LL_LPTIM_Init can only be called when the LPTIM instance is disabled.
+ * @note LPTIMx can be disabled using unitary function @ref LL_LPTIM_Disable().
+ * @param LPTIMx LP Timer Instance
+ * @param LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: LPTIMx instance has been initialized
+ * - ERROR: LPTIMx instance hasn't been initialized
+ */
+ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
+{
+ ErrorStatus result = SUCCESS;
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(LPTIMx));
+ assert_param(IS_LL_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource));
+ assert_param(IS_LL_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler));
+ assert_param(IS_LL_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform));
+
+ /* The LPTIMx_CFGR register must only be modified when the LPTIM is disabled
+ (ENABLE bit is reset to 0).
+ */
+ if (LL_LPTIM_IsEnabled(LPTIMx) == 1UL)
+ {
+ result = ERROR;
+ }
+ else
+ {
+ /* Set CKSEL bitfield according to ClockSource value */
+ /* Set PRESC bitfield according to Prescaler value */
+ /* Set WAVE bitfield according to Waveform value */
+ MODIFY_REG(LPTIMx->CFGR,
+ (LPTIM_CFGR_CKSEL | LPTIM_CFGR_PRESC | LPTIM_CFGR_WAVE),
+ LPTIM_InitStruct->ClockSource | \
+ LPTIM_InitStruct->Prescaler | \
+ LPTIM_InitStruct->Waveform);
+ }
+
+ return result;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* LPTIM1 || LPTIM2 || LPTIM3 || LPTIM4 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_lpuart.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_lpuart.c
new file mode 100644
index 00000000..6d4e0b28
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_lpuart.c
@@ -0,0 +1,282 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_lpuart.c
+ * @author MCD Application Team
+ * @brief LPUART LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_ll_lpuart.h"
+#include "stm32u5xx_ll_rcc.h"
+#include "stm32u5xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined (LPUART1)
+
+/** @addtogroup LPUART_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup LPUART_LL_Private_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup LPUART_LL_Private_Macros
+ * @{
+ */
+
+/* Check of parameters for configuration of LPUART registers */
+
+#define IS_LL_LPUART_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPUART_PRESCALER_DIV1) \
+ || ((__VALUE__) == LL_LPUART_PRESCALER_DIV2) \
+ || ((__VALUE__) == LL_LPUART_PRESCALER_DIV4) \
+ || ((__VALUE__) == LL_LPUART_PRESCALER_DIV6) \
+ || ((__VALUE__) == LL_LPUART_PRESCALER_DIV8) \
+ || ((__VALUE__) == LL_LPUART_PRESCALER_DIV10) \
+ || ((__VALUE__) == LL_LPUART_PRESCALER_DIV12) \
+ || ((__VALUE__) == LL_LPUART_PRESCALER_DIV16) \
+ || ((__VALUE__) == LL_LPUART_PRESCALER_DIV32) \
+ || ((__VALUE__) == LL_LPUART_PRESCALER_DIV64) \
+ || ((__VALUE__) == LL_LPUART_PRESCALER_DIV128) \
+ || ((__VALUE__) == LL_LPUART_PRESCALER_DIV256))
+
+/* __BAUDRATE__ Depending on constraints applicable for LPUART BRR register */
+/* value : */
+/* - fck must be in the range [3 x baudrate, 4096 x baudrate] */
+/* - LPUART_BRR register value should be >= 0x300 */
+/* - LPUART_BRR register value should be <= 0xFFFFF (20 bits) */
+/* Baudrate specified by the user should belong to [8, 33000000].*/
+#define IS_LL_LPUART_BAUDRATE(__BAUDRATE__) (((__BAUDRATE__) <= 33000000U) && ((__BAUDRATE__) >= 8U))
+
+/* __VALUE__ BRR content must be greater than or equal to 0x300. */
+#define IS_LL_LPUART_BRR_MIN(__VALUE__) ((__VALUE__) >= 0x300U)
+
+/* __VALUE__ BRR content must be lower than or equal to 0xFFFFF. */
+#define IS_LL_LPUART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x000FFFFFU)
+
+#define IS_LL_LPUART_DIRECTION(__VALUE__) (((__VALUE__) == LL_LPUART_DIRECTION_NONE) \
+ || ((__VALUE__) == LL_LPUART_DIRECTION_RX) \
+ || ((__VALUE__) == LL_LPUART_DIRECTION_TX) \
+ || ((__VALUE__) == LL_LPUART_DIRECTION_TX_RX))
+
+#define IS_LL_LPUART_PARITY(__VALUE__) (((__VALUE__) == LL_LPUART_PARITY_NONE) \
+ || ((__VALUE__) == LL_LPUART_PARITY_EVEN) \
+ || ((__VALUE__) == LL_LPUART_PARITY_ODD))
+
+#define IS_LL_LPUART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_LPUART_DATAWIDTH_7B) \
+ || ((__VALUE__) == LL_LPUART_DATAWIDTH_8B) \
+ || ((__VALUE__) == LL_LPUART_DATAWIDTH_9B))
+
+#define IS_LL_LPUART_STOPBITS(__VALUE__) (((__VALUE__) == LL_LPUART_STOPBITS_1) \
+ || ((__VALUE__) == LL_LPUART_STOPBITS_2))
+
+#define IS_LL_LPUART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_LPUART_HWCONTROL_NONE) \
+ || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS) \
+ || ((__VALUE__) == LL_LPUART_HWCONTROL_CTS) \
+ || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS_CTS))
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup LPUART_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup LPUART_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize LPUART registers (Registers restored to their default values).
+ * @param LPUARTx LPUART Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: LPUART registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_LPUART_INSTANCE(LPUARTx));
+
+ if (LPUARTx == LPUART1)
+ {
+ /* Force reset of LPUART peripheral */
+ LL_APB3_GRP1_ForceReset(LL_APB3_GRP1_PERIPH_LPUART1);
+
+ /* Release reset of LPUART peripheral */
+ LL_APB3_GRP1_ReleaseReset(LL_APB3_GRP1_PERIPH_LPUART1);
+ }
+ else
+ {
+ status = ERROR;
+ }
+
+ return (status);
+}
+
+/**
+ * @brief Initialize LPUART registers according to the specified
+ * parameters in LPUART_InitStruct.
+ * @note As some bits in LPUART configuration registers can only be written when
+ * the LPUART is disabled (USART_CR1_UE bit =0),
+ * LPUART Peripheral should be in disabled state prior calling this function.
+ * Otherwise, ERROR result will be returned.
+ * @note Baud rate value stored in LPUART_InitStruct BaudRate field, should be valid (different from 0).
+ * @param LPUARTx LPUART Instance
+ * @param LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure
+ * that contains the configuration information for the specified LPUART peripheral.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: LPUART registers are initialized according to LPUART_InitStruct content
+ * - ERROR: Problem occurred during LPUART Registers initialization
+ */
+ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct)
+{
+ ErrorStatus status = ERROR;
+ uint32_t periphclk;
+
+ /* Check the parameters */
+ assert_param(IS_LPUART_INSTANCE(LPUARTx));
+ assert_param(IS_LL_LPUART_PRESCALER(LPUART_InitStruct->PrescalerValue));
+ assert_param(IS_LL_LPUART_BAUDRATE(LPUART_InitStruct->BaudRate));
+ assert_param(IS_LL_LPUART_DATAWIDTH(LPUART_InitStruct->DataWidth));
+ assert_param(IS_LL_LPUART_STOPBITS(LPUART_InitStruct->StopBits));
+ assert_param(IS_LL_LPUART_PARITY(LPUART_InitStruct->Parity));
+ assert_param(IS_LL_LPUART_DIRECTION(LPUART_InitStruct->TransferDirection));
+ assert_param(IS_LL_LPUART_HWCONTROL(LPUART_InitStruct->HardwareFlowControl));
+
+ /* LPUART needs to be in disabled state, in order to be able to configure some bits in
+ CRx registers. Otherwise (LPUART not in Disabled state) => return ERROR */
+ if (LL_LPUART_IsEnabled(LPUARTx) == 0U)
+ {
+ /*---------------------------- LPUART CR1 Configuration -----------------------
+ * Configure LPUARTx CR1 (LPUART Word Length, Parity and Transfer Direction bits) with parameters:
+ * - DataWidth: USART_CR1_M bits according to LPUART_InitStruct->DataWidth value
+ * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to LPUART_InitStruct->Parity value
+ * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to LPUART_InitStruct->TransferDirection value
+ */
+ MODIFY_REG(LPUARTx->CR1,
+ (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE),
+ (LPUART_InitStruct->DataWidth | LPUART_InitStruct->Parity | LPUART_InitStruct->TransferDirection));
+
+ /*---------------------------- LPUART CR2 Configuration -----------------------
+ * Configure LPUARTx CR2 (Stop bits) with parameters:
+ * - Stop Bits: USART_CR2_STOP bits according to LPUART_InitStruct->StopBits value.
+ */
+ LL_LPUART_SetStopBitsLength(LPUARTx, LPUART_InitStruct->StopBits);
+
+ /*---------------------------- LPUART CR3 Configuration -----------------------
+ * Configure LPUARTx CR3 (Hardware Flow Control) with parameters:
+ * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according
+ * to LPUART_InitStruct->HardwareFlowControl value.
+ */
+ LL_LPUART_SetHWFlowCtrl(LPUARTx, LPUART_InitStruct->HardwareFlowControl);
+
+ /*---------------------------- LPUART BRR Configuration -----------------------
+ * Retrieve Clock frequency used for LPUART Peripheral
+ */
+ periphclk = LL_RCC_GetLPUARTClockFreq(LL_RCC_LPUART1_CLKSOURCE);
+
+ /* Configure the LPUART Baud Rate :
+ - prescaler value is required
+ - valid baud rate value (different from 0) is required
+ - Peripheral clock as returned by RCC service, should be valid (different from 0).
+ */
+ if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
+ && (LPUART_InitStruct->BaudRate != 0U))
+ {
+ status = SUCCESS;
+ LL_LPUART_SetBaudRate(LPUARTx,
+ periphclk,
+ LPUART_InitStruct->PrescalerValue,
+ LPUART_InitStruct->BaudRate);
+
+ /* Check BRR is greater than or equal to 0x300 */
+ assert_param(IS_LL_LPUART_BRR_MIN(LPUARTx->BRR));
+
+ /* Check BRR is lower than or equal to 0xFFFFF */
+ assert_param(IS_LL_LPUART_BRR_MAX(LPUARTx->BRR));
+ }
+
+ /*---------------------------- LPUART PRESC Configuration -----------------------
+ * Configure LPUARTx PRESC (Prescaler) with parameters:
+ * - PrescalerValue: LPUART_PRESC_PRESCALER bits according to LPUART_InitStruct->PrescalerValue value.
+ */
+ LL_LPUART_SetPrescaler(LPUARTx, LPUART_InitStruct->PrescalerValue);
+ }
+
+ return (status);
+}
+
+/**
+ * @brief Set each @ref LL_LPUART_InitTypeDef field to default value.
+ * @param LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+
+void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct)
+{
+ /* Set LPUART_InitStruct fields to default values */
+ LPUART_InitStruct->PrescalerValue = LL_LPUART_PRESCALER_DIV1;
+ LPUART_InitStruct->BaudRate = 9600U;
+ LPUART_InitStruct->DataWidth = LL_LPUART_DATAWIDTH_8B;
+ LPUART_InitStruct->StopBits = LL_LPUART_STOPBITS_1;
+ LPUART_InitStruct->Parity = LL_LPUART_PARITY_NONE ;
+ LPUART_InitStruct->TransferDirection = LL_LPUART_DIRECTION_TX_RX;
+ LPUART_InitStruct->HardwareFlowControl = LL_LPUART_HWCONTROL_NONE;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* LPUART1 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_opamp.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_opamp.c
new file mode 100644
index 00000000..bd2c2c81
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_opamp.c
@@ -0,0 +1,232 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_opamp.c
+ * @author MCD Application Team
+ * @brief OPAMP LL module driver
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_ll_opamp.h"
+
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined (OPAMP1) || defined (OPAMP2)
+
+/** @addtogroup OPAMP_LL OPAMP
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup OPAMP_LL_Private_Macros
+ * @{
+ */
+
+/* Check of parameters for configuration of OPAMP hierarchical scope: */
+/* OPAMP instance. */
+
+#define IS_LL_OPAMP_POWER_MODE(__POWER_MODE__) (((__POWER_MODE__) == LL_OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED) ||\
+ ((__POWER_MODE__) == LL_OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED) ||\
+ ((__POWER_MODE__) == LL_OPAMP_POWERMODE_LOWPOWER_NORMALSPEED)||\
+ ((__POWER_MODE__) == LL_OPAMP_POWERMODE_LOWPOWER_HIGHSPEED))
+
+
+
+#define IS_LL_OPAMP_FUNCTIONAL_MODE(__FUNCTIONAL_MODE__) (((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_STANDALONE) ||\
+ ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_FOLLOWER) ||\
+ ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_PGA))
+
+/* Note: Comparator non-inverting inputs parameters are the same on all */
+/* OPAMP instances. */
+/* However, comparator instance kept as macro parameter for */
+/* compatibility with other STM32 families. */
+#define IS_LL_OPAMP_INPUT_NONINVERTING(__OPAMPX__, __INPUT_NONINVERTING__) \
+ ( ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_IO0) \
+ || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINV_DAC1_CH1) \
+ )
+
+/* Note: Comparator non-inverting inputs parameters are the same on all */
+/* OPAMP instances. */
+/* However, comparator instance kept as macro parameter for */
+/* compatibility with other STM32 families. */
+#define IS_LL_OPAMP_INPUT_INVERTING(__OPAMPX__, __INPUT_INVERTING__) \
+ ( ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_IO0) \
+ || ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_IO1) \
+ || ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_CONNECT_NO) \
+ )
+
+/**
+ * @}
+ */
+
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup OPAMP_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup OPAMP_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize registers of the selected OPAMP instance
+ * to their default reset values.
+ * @param OPAMPx OPAMP instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: OPAMP registers are de-initialized
+ * - ERROR: OPAMP registers are not de-initialized
+ */
+ErrorStatus LL_OPAMP_DeInit(OPAMP_TypeDef *OPAMPx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_OPAMP_ALL_INSTANCE(OPAMPx));
+
+ LL_OPAMP_WriteReg(OPAMPx, CSR, 0x00000000U);
+
+ return status;
+}
+
+/**
+ * @brief Initialize some features of OPAMP instance.
+ * @note This function reset bit of calibration mode to ensure
+ * to be in functional mode, in order to have OPAMP parameters
+ * (inputs selection, ...) set with the corresponding OPAMP mode
+ * to be effective.
+ * @note This function configures features of the selected OPAMP instance.
+ * Some features are also available at scope OPAMP common instance
+ * (common to several OPAMP instances).
+ * @param OPAMPx OPAMP instance
+ * @param OPAMP_InitStruct Pointer to a @ref LL_OPAMP_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: OPAMP registers are initialized
+ * - ERROR: OPAMP registers are not initialized
+ */
+ErrorStatus LL_OPAMP_Init(OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_InitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_OPAMP_ALL_INSTANCE(OPAMPx));
+ assert_param(IS_LL_OPAMP_POWER_MODE(OPAMP_InitStruct->PowerMode));
+ assert_param(IS_LL_OPAMP_FUNCTIONAL_MODE(OPAMP_InitStruct->FunctionalMode));
+ assert_param(IS_LL_OPAMP_INPUT_NONINVERTING(OPAMPx, OPAMP_InitStruct->InputNonInverting));
+
+ /* Note: OPAMP inverting input can be used with OPAMP in mode standalone */
+ /* or PGA with external capacitors for filtering circuit. */
+ /* Otherwise (OPAMP in mode follower), OPAMP inverting input is */
+ /* not used (not connected to GPIO pin). */
+ if (OPAMP_InitStruct->FunctionalMode != LL_OPAMP_MODE_FOLLOWER)
+ {
+ assert_param(IS_LL_OPAMP_INPUT_INVERTING(OPAMPx, OPAMP_InitStruct->InputInverting));
+ }
+
+ /* Configuration of OPAMP instance : */
+ /* - PowerMode */
+ /* - Functional mode */
+ /* - Input non-inverting */
+ /* - Input inverting */
+ /* Note: Bit OPAMP_CSR_CALON reset to ensure to be in functional mode. */
+ if (OPAMP_InitStruct->FunctionalMode != LL_OPAMP_MODE_FOLLOWER)
+ {
+ MODIFY_REG(OPAMPx->CSR,
+ OPAMP_CSR_OPALPM
+ | OPAMP_CSR_OPAMODE
+ | OPAMP_CSR_CALON
+ | OPAMP_CSR_VM_SEL
+ | OPAMP_CSR_VP_SEL
+ | OPAMP_CSR_HSM
+ ,
+ OPAMP_InitStruct->PowerMode
+ | OPAMP_InitStruct->FunctionalMode
+ | OPAMP_InitStruct->InputNonInverting
+ | OPAMP_InitStruct->InputInverting
+ );
+ }
+ else
+ {
+ MODIFY_REG(OPAMPx->CSR,
+ OPAMP_CSR_OPALPM
+ | OPAMP_CSR_OPAMODE
+ | OPAMP_CSR_CALON
+ | OPAMP_CSR_VM_SEL
+ | OPAMP_CSR_VP_SEL
+ | OPAMP_CSR_HSM
+ ,
+ OPAMP_InitStruct->PowerMode
+ | LL_OPAMP_MODE_FOLLOWER
+ | OPAMP_InitStruct->InputNonInverting
+ | LL_OPAMP_INPUT_INVERT_CONNECT_NO
+ );
+ }
+
+ /* Set the power supply range to high for performance purpose */
+ /* The OPAMP_CSR_OPARANGE is common configuration for all OPAMPs */
+ /* bit OPAMP_CSR_OPARANGE applies for both OPAMPs */
+ MODIFY_REG(OPAMP1->CSR, OPAMP_CSR_OPARANGE, OPAMP_CSR_OPARANGE);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set each @ref LL_OPAMP_InitTypeDef field to default value.
+ * @param OPAMP_InitStruct pointer to a @ref LL_OPAMP_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_OPAMP_StructInit(LL_OPAMP_InitTypeDef *OPAMP_InitStruct)
+{
+ /* Set OPAMP_InitStruct fields to default values */
+ OPAMP_InitStruct->PowerMode = LL_OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED;
+ OPAMP_InitStruct->FunctionalMode = LL_OPAMP_MODE_FOLLOWER;
+ OPAMP_InitStruct->InputNonInverting = LL_OPAMP_INPUT_NONINVERT_IO0;
+ /* Note: Parameter discarded if OPAMP in functional mode follower, */
+ /* set anyway to its default value. */
+ OPAMP_InitStruct->InputInverting = LL_OPAMP_INPUT_INVERT_CONNECT_NO;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* OPAMP1 || OPAMP2 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_pka.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_pka.c
new file mode 100644
index 00000000..d760c697
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_pka.c
@@ -0,0 +1,165 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_pka.c
+ * @author MCD Application Team
+ * @brief PKA LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_ll_pka.h"
+#include "stm32u5xx_ll_bus.h"
+
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined(PKA)
+
+/** @addtogroup PKA_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PKA_LL_Private_Macros PKA Private Constants
+ * @{
+ */
+#define IS_LL_PKA_MODE(__VALUE__) (((__VALUE__)== LL_PKA_MODE_MODULAR_EXP) ||\
+ ((__VALUE__) == LL_PKA_MODE_MONTGOMERY_PARAM) ||\
+ ((__VALUE__) == LL_PKA_MODE_MODULAR_EXP_FAST) ||\
+ ((__VALUE__) == LL_PKA_MODE_MODULAR_EXP_PROTECT) ||\
+ ((__VALUE__) == LL_PKA_MODE_ECC_MUL) ||\
+ ((__VALUE__) == LL_PKA_MODE_ECC_COMPLETE_ADD) ||\
+ ((__VALUE__) == LL_PKA_MODE_ECDSA_SIGNATURE) ||\
+ ((__VALUE__) == LL_PKA_MODE_ECDSA_VERIFICATION) ||\
+ ((__VALUE__) == LL_PKA_MODE_POINT_CHECK) ||\
+ ((__VALUE__) == LL_PKA_MODE_RSA_CRT_EXP) ||\
+ ((__VALUE__) == LL_PKA_MODE_MODULAR_INV) ||\
+ ((__VALUE__) == LL_PKA_MODE_ARITHMETIC_ADD) ||\
+ ((__VALUE__) == LL_PKA_MODE_ARITHMETIC_SUB) ||\
+ ((__VALUE__) == LL_PKA_MODE_ARITHMETIC_MUL) ||\
+ ((__VALUE__) == LL_PKA_MODE_COMPARISON) ||\
+ ((__VALUE__) == LL_PKA_MODE_MODULAR_REDUC) ||\
+ ((__VALUE__) == LL_PKA_MODE_MODULAR_ADD) ||\
+ ((__VALUE__) == LL_PKA_MODE_MODULAR_SUB) ||\
+ ((__VALUE__) == LL_PKA_MODE_MONTGOMERY_MUL) ||\
+ ((__VALUE__) == LL_PKA_MODE_DOUBLE_BASE_LADDER) ||\
+ ((__VALUE__) == LL_PKA_MODE_ECC_PROJECTIVE_AFF))
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PKA_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup PKA_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize PKA registers (Registers restored to their default values).
+ * @param PKAx PKA Instance.
+ * @retval ErrorStatus
+ * - SUCCESS: PKA registers are de-initialized
+ * - ERROR: PKA registers are not de-initialized
+ */
+ErrorStatus LL_PKA_DeInit(PKA_TypeDef *PKAx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_PKA_ALL_INSTANCE(PKAx));
+
+ if (PKAx == PKA)
+ {
+ /* Force PKA reset */
+ LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_PKA);
+
+ /* Release PKA reset */
+ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_PKA);
+ }
+ else
+ {
+ status = ERROR;
+ }
+
+ return (status);
+}
+
+/**
+ * @brief Initialize PKA registers according to the specified parameters in PKA_InitStruct.
+ * @param PKAx PKA Instance.
+ * @param PKA_InitStruct pointer to a @ref LL_PKA_InitTypeDef structure
+ * that contains the configuration information for the specified PKA peripheral.
+ * @retval ErrorStatus
+ * - SUCCESS: PKA registers are initialized according to PKA_InitStruct content
+ * - ERROR: Not applicable
+ */
+ErrorStatus LL_PKA_Init(PKA_TypeDef *PKAx, LL_PKA_InitTypeDef *PKA_InitStruct)
+{
+ assert_param(IS_PKA_ALL_INSTANCE(PKAx));
+ assert_param(IS_LL_PKA_MODE(PKA_InitStruct->Mode));
+
+ LL_PKA_Config(PKAx, PKA_InitStruct->Mode);
+
+ return (SUCCESS);
+}
+
+/**
+ * @brief Set each @ref LL_PKA_InitTypeDef field to default value.
+ * @param PKA_InitStruct pointer to a @ref LL_PKA_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+
+void LL_PKA_StructInit(LL_PKA_InitTypeDef *PKA_InitStruct)
+{
+ /* Reset PKA init structure parameters values */
+ PKA_InitStruct->Mode = LL_PKA_MODE_MODULAR_EXP;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (PKA) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_pwr.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_pwr.c
new file mode 100644
index 00000000..0e375b95
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_pwr.c
@@ -0,0 +1,93 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_pwr.c
+ * @author MCD Application Team
+ * @brief PWR LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+#if defined (USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_ll_pwr.h"
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined (PWR)
+
+/** @defgroup PWR_LL PWR
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup PWR_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup PWR_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the PWR registers to their default reset values.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS : PWR registers are de-initialized.
+ * - ERROR : not applicable.
+ */
+ErrorStatus LL_PWR_DeInit(void)
+{
+ /* Clear PWR low power flags */
+ LL_PWR_ClearFlag_STOP();
+
+ /* Clear PWR wake up flags */
+ LL_PWR_ClearFlag_WU();
+
+ /* Reset privilege attribute for nsecure attribute */
+ LL_PWR_DisableNSecurePrivilege();
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ /* Reset privilege attribute for nsecure attribute */
+ LL_PWR_DisableSecurePrivilege();
+
+ /* Reset secure attribute */
+ LL_PWR_ConfigSecure(0);
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+ return SUCCESS;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* defined(PWR) */
+/**
+ * @}
+ */
+
+#endif /* defined (USE_FULL_LL_DRIVER) */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_rcc.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_rcc.c
new file mode 100644
index 00000000..6089e8e7
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_rcc.c
@@ -0,0 +1,2030 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_rcc.c
+ * @author MCD Application Team
+ * @brief RCC LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_ll_rcc.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined(RCC)
+
+/** @addtogroup RCC_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCC_LL_Private_Macros
+ * @{
+ */
+#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
+
+#define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE))
+
+#define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE))
+
+#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE))
+
+#define IS_LL_RCC_SPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPI1_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_SPI2_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_SPI3_CLKSOURCE))
+
+#define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_LPTIM34_CLKSOURCE))
+
+#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE))
+
+#define IS_LL_RCC_SDMMC_KERNELCLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC_KERNELCLKSOURCE))
+
+#define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC_CLKSOURCE))
+
+#define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
+
+#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
+
+#define IS_LL_RCC_ADCDAC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADCDAC_CLKSOURCE))
+
+#define IS_LL_RCC_MDF1_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_MDF1_CLKSOURCE))
+
+#define IS_LL_RCC_DAC1_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DAC1_CLKSOURCE))
+
+#define IS_LL_RCC_ADF1_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADF1_CLKSOURCE))
+
+#define IS_LL_RCC_OCTOSPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_OCTOSPI_CLKSOURCE))
+
+#define IS_LL_RCC_SAES_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAES_CLKSOURCE))
+
+#define IS_LL_RCC_FDCAN_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_FDCAN_CLKSOURCE))
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup RCC_LL_Private_Functions RCC Private functions
+ * @{
+ */
+static uint32_t RCC_GetSystemClockFreq(void);
+static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
+static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
+static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
+static uint32_t RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency);
+static uint32_t RCC_PLL1_GetFreqDomain_SYS(void);
+static uint32_t RCC_PLL1_GetFreqDomain_SAI(void);
+static uint32_t RCC_PLL1_GetFreqDomain_48M(void);
+static uint32_t RCC_PLL2_GetFreqDomain_SAI(void);
+static uint32_t RCC_PLL2_GetFreqDomain_48M(void);
+static uint32_t RCC_PLL2_GetFreqDomain_ADC(void);
+static uint32_t RCC_PLL3_GetFreqDomain_SAI(void);
+static uint32_t RCC_PLL3_GetFreqDomain_48M(void);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RCC_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief Reset the RCC clock configuration to the default reset state.
+ * @note The default reset state of the clock configuration is given below:
+ * - MSI ON and used as system clock source
+ * - HSE, HSI, PLL1, PLL2 and PLL3 OFF
+ * - AHB, APB1, APB2 and APB3 prescaler set to 1.
+ * - CSS, MCO OFF
+ * - All interrupts disabled
+ * @note This function doesn't modify the configuration of the
+ * - Peripheral clocks
+ * - LSI, LSE and RTC clocks
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RCC registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_RCC_DeInit(void)
+{
+ uint32_t vl_mask;
+
+ /* Set MSION bit */
+ LL_RCC_MSIS_Enable();
+
+ /* Insure MSIRDY bit is set before writing default MSIRANGE value */
+ while (LL_RCC_MSIS_IsReady() == 0U)
+ {
+ }
+
+ /* Set MSIRANGE default value */
+ LL_RCC_MSIS_SetRange(LL_RCC_MSISRANGE_4);
+
+ /* Set MSITRIM bits to the reset value*/
+ LL_RCC_MSI_SetCalibTrimming(0, LL_RCC_MSI_OSCILLATOR_1);
+
+ /* Set HSITRIM bits to the reset value*/
+ LL_RCC_HSI_SetCalibTrimming(0x40U);
+
+ /* Reset CFGR register */
+ LL_RCC_WriteReg(CFGR1, 0x00000000U);
+ LL_RCC_WriteReg(CFGR2, 0x00000000U);
+ LL_RCC_WriteReg(CFGR3, 0x00000000U);
+
+ /* Read CR register */
+ vl_mask = LL_RCC_ReadReg(CR);
+
+ /* Reset HSION, HSIKERON, HSEON, PLL1ON, PLL2ON and PLL3ON bits */
+ CLEAR_BIT(vl_mask, (RCC_CR_HSION | RCC_CR_HSIKERON | RCC_CR_HSEON |
+ RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON));
+
+ /* Write new mask in CR register */
+ LL_RCC_WriteReg(CR, vl_mask);
+
+ /* Wait for PLL1RDY, PLL2RDY and PLL3RDY bits to be reset */
+ while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY | RCC_CR_PLL2RDY | RCC_CR_PLL3RDY) != 0U)
+ {
+ }
+
+ /* Reset PLL1DIVR register */
+ LL_RCC_WriteReg(PLL1DIVR, 0x01010280U);
+
+ /* Reset PLL2DIVR register */
+ LL_RCC_WriteReg(PLL2DIVR, 0x01010280U);
+
+ /* Reset PLL3DIVR register */
+ LL_RCC_WriteReg(PLL3DIVR, 0x01010280U);
+
+ /* Reset HSEBYP bit */
+ LL_RCC_HSE_DisableBypass();
+
+ /* Disable all interrupts */
+ LL_RCC_WriteReg(CIER, 0x00000000U);
+
+ /* Clear all interrupt flags */
+ vl_mask = RCC_CICR_LSIRDYC | RCC_CICR_LSERDYC | RCC_CICR_MSISRDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC | \
+ RCC_CICR_PLL1RDYC | RCC_CICR_PLL2RDYC | RCC_CICR_PLL3RDYC | RCC_CICR_HSI48RDYC | RCC_CICR_CSSC | \
+ RCC_CICR_MSIKRDYC;
+ LL_RCC_WriteReg(CICR, vl_mask);
+
+ /* Clear reset flags */
+ LL_RCC_ClearResetFlags();
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ /* Reset secure configuration */
+ LL_RCC_ConfigSecure(LL_RCC_ALL_NSEC);
+#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */
+ return SUCCESS;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_LL_EF_Get_Freq
+ * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
+ * and different peripheral clocks available on the device.
+ * @note If SYSCLK source is MSI, function returns values based on MSI_VALUE(*)
+ * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
+ * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
+ * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(***)
+ * or HSI_VALUE(**) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+ * @note (*) MSI_VALUE is a constant defined in this file (default value
+ * 4 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ * @note (**) HSI_VALUE is a constant defined in this file (default value
+ * 16 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ * @note (***) HSE_VALUE is a constant defined in this file (default value
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ * @note The result of this function could be incorrect when using fractional
+ * value for HSE crystal.
+ * @note This function can be used by the user application to compute the
+ * baud-rate for the communication peripherals or configure other parameters.
+ * @{
+ */
+
+/**
+ * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
+ * @note Each time SYSCLK, HCLK, PCLK1, PCLK2 and/or PCLK3 clock changes, this function
+ * must be called to update structure fields. Otherwise, any
+ * configuration based on this function will be incorrect.
+ * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
+ * @retval None
+ */
+void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
+{
+ /* Get SYSCLK frequency */
+ RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
+
+ /* HCLK clock frequency */
+ RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
+
+ /* PCLK1 clock frequency */
+ RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
+
+ /* PCLK2 clock frequency */
+ RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
+
+ /* PCLK3 clock frequency */
+ RCC_Clocks->PCLK3_Frequency = RCC_GetPCLK3ClockFreq(RCC_Clocks->HCLK_Frequency);
+}
+
+/**
+ * @brief Return USARTx clock frequency
+ * @param USARTxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_USART1_CLKSOURCE
+ * @arg @ref LL_RCC_USART2_CLKSOURCE
+ * @arg @ref LL_RCC_USART3_CLKSOURCE
+ * @retval USART clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
+ */
+uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
+{
+ uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
+
+ if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
+ {
+ /* USART1CLK clock frequency */
+ switch (LL_RCC_GetUSARTClockSource(USARTxSource))
+ {
+ case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
+ usart_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady() == 1U)
+ {
+ usart_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */
+ if (LL_RCC_LSE_IsReady() == 1U)
+ {
+ usart_frequency = LSE_VALUE;
+ }
+ break;
+
+ case LL_RCC_USART1_CLKSOURCE_PCLK2: /* USART1 Clock is PCLK2 */
+ usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+
+ default:
+ /* unreachable code */
+ break;
+ }
+ }
+ else if (USARTxSource == LL_RCC_USART2_CLKSOURCE)
+ {
+ /* USART2CLK clock frequency */
+ switch (LL_RCC_GetUSARTClockSource(USARTxSource))
+ {
+ case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */
+ usart_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady() == 1U)
+ {
+ usart_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */
+ if (LL_RCC_LSE_IsReady() == 1U)
+ {
+ usart_frequency = LSE_VALUE;
+ }
+ break;
+
+ case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */
+ usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+
+ default:
+ /* unreachable code */
+ break;
+ }
+ }
+ else if (USARTxSource == LL_RCC_USART3_CLKSOURCE)
+ {
+ /* USART3CLK clock frequency */
+ switch (LL_RCC_GetUSARTClockSource(USARTxSource))
+ {
+ case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */
+ usart_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady() == 1U)
+ {
+ usart_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */
+ if (LL_RCC_LSE_IsReady() == 1U)
+ {
+ usart_frequency = LSE_VALUE;
+ }
+ break;
+
+ case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */
+ usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+
+ default:
+ /* unreachable code */
+ break;
+ }
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+ return usart_frequency;
+}
+
+/**
+ * @brief Return UARTx clock frequency
+ * @param UARTxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_UART4_CLKSOURCE
+ * @arg @ref LL_RCC_UART5_CLKSOURCE
+ * @retval UART clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
+ */
+uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)
+{
+ uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_UART_CLKSOURCE(UARTxSource));
+
+ if (UARTxSource == LL_RCC_UART4_CLKSOURCE)
+ {
+ /* UART4CLK clock frequency */
+ switch (LL_RCC_GetUARTClockSource(UARTxSource))
+ {
+ case LL_RCC_UART4_CLKSOURCE_SYSCLK: /* UART4 Clock is System Clock */
+ uart_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_UART4_CLKSOURCE_HSI: /* UART4 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady() == 1U)
+ {
+ uart_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_UART4_CLKSOURCE_LSE: /* UART4 Clock is LSE Osc. */
+ if (LL_RCC_LSE_IsReady() == 1U)
+ {
+ uart_frequency = LSE_VALUE;
+ }
+ break;
+
+ case LL_RCC_UART4_CLKSOURCE_PCLK1: /* UART4 Clock is PCLK1 */
+ uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+
+ default:
+ /* unreachable code */
+ break;
+ }
+ }
+ else if (UARTxSource == LL_RCC_UART5_CLKSOURCE)
+ {
+ /* UART5CLK clock frequency */
+ switch (LL_RCC_GetUARTClockSource(UARTxSource))
+ {
+ case LL_RCC_UART5_CLKSOURCE_SYSCLK: /* UART5 Clock is System Clock */
+ uart_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_UART5_CLKSOURCE_HSI: /* UART5 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady() == 1U)
+ {
+ uart_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_UART5_CLKSOURCE_LSE: /* UART5 Clock is LSE Osc. */
+ if (LL_RCC_LSE_IsReady() == 1U)
+ {
+ uart_frequency = LSE_VALUE;
+ }
+ break;
+
+ case LL_RCC_UART5_CLKSOURCE_PCLK1: /* UART5 Clock is PCLK1 */
+ uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+
+ default:
+ /* unreachable code */
+ break;
+ }
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+ return uart_frequency;
+}
+
+/**
+ * @brief Return SPIx clock frequency
+ * @param SPIxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SPI1_CLKSOURCE
+ * @arg @ref LL_RCC_SPI2_CLKSOURCE
+ * @arg @ref LL_RCC_SPI3_CLKSOURCE
+ * @retval SPI clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or MSIK) is not ready
+ */
+uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource)
+{
+ uint32_t SPI_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_SPI_CLKSOURCE(SPIxSource));
+
+ if (SPIxSource == LL_RCC_SPI1_CLKSOURCE)
+ {
+ /* SPI1 CLK clock frequency */
+ switch (LL_RCC_GetSPIClockSource(SPIxSource))
+ {
+ case LL_RCC_SPI1_CLKSOURCE_SYSCLK: /* SPI1 Clock is System Clock */
+ SPI_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_SPI1_CLKSOURCE_HSI: /* SPI1 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady() == 1U)
+ {
+ SPI_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_SPI1_CLKSOURCE_MSIK: /* SPI1 Clock is MSIK Osc.*/
+ SPI_frequency = __LL_RCC_CALC_MSIK_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
+ LL_RCC_MSIK_GetRange() :
+ LL_RCC_MSIK_GetRangeAfterStandby()));
+ break;
+
+ case LL_RCC_SPI1_CLKSOURCE_PCLK2: /* SPI1 Clock is PCLK2 */
+ SPI_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+
+ default:
+ /* unreachable code */
+ break;
+ }
+ }
+ else if (SPIxSource == LL_RCC_SPI2_CLKSOURCE)
+ {
+ /* SPI2 CLK clock frequency */
+ switch (LL_RCC_GetSPIClockSource(SPIxSource))
+ {
+ case LL_RCC_SPI2_CLKSOURCE_SYSCLK: /* SPI2 Clock is System Clock */
+ SPI_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_SPI2_CLKSOURCE_HSI: /* SPI2 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady() == 1U)
+ {
+ SPI_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_SPI2_CLKSOURCE_MSIK: /* SPI2 Clock is MSIK Osc.*/
+ SPI_frequency = __LL_RCC_CALC_MSIK_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
+ LL_RCC_MSIK_GetRange() :
+ LL_RCC_MSIK_GetRangeAfterStandby()));
+ break;
+
+ case LL_RCC_SPI2_CLKSOURCE_PCLK1: /* SPI2 Clock is PCLK1 */
+ SPI_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+
+ default:
+ /* unreachable code */
+ break;
+
+ }
+ }
+ else if (SPIxSource == LL_RCC_SPI3_CLKSOURCE)
+ {
+ /* SPI3 CLK clock frequency */
+ switch (LL_RCC_GetSPIClockSource(SPIxSource))
+ {
+ case LL_RCC_SPI3_CLKSOURCE_SYSCLK: /* SPI3 Clock is System Clock */
+ SPI_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_SPI3_CLKSOURCE_HSI: /* SPI3 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady() == 1U)
+ {
+ SPI_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_SPI3_CLKSOURCE_MSIK: /* SPI3 Clock is MSIK Osc. */
+ SPI_frequency = __LL_RCC_CALC_MSIK_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
+ LL_RCC_MSIK_GetRange() :
+ LL_RCC_MSIK_GetRangeAfterStandby()));
+ break;
+
+ case LL_RCC_SPI3_CLKSOURCE_PCLK3: /* SPI3 Clock is PCLK3 */
+ SPI_frequency = RCC_GetPCLK3ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+
+ default:
+ /* unreachable code */
+ break;
+ }
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+ return SPI_frequency;
+}
+
+/**
+ * @brief Return I2Cx clock frequency
+ * @param I2CxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_I2C1_CLKSOURCE
+ * @arg @ref LL_RCC_I2C2_CLKSOURCE
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE
+ * @arg @ref LL_RCC_I2C4_CLKSOURCE
+ * @retval I2C clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or MSIK) is not ready
+ */
+uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
+{
+ uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
+
+ if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
+ {
+ /* I2C1 CLK clock frequency */
+ switch (LL_RCC_GetI2CClockSource(I2CxSource))
+ {
+ case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
+ i2c_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady() == 1U)
+ {
+ i2c_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_I2C1_CLKSOURCE_MSIK: /* I2C1 Clock is MSIK Osc.*/
+ i2c_frequency = __LL_RCC_CALC_MSIK_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
+ LL_RCC_MSIK_GetRange() :
+ LL_RCC_MSIK_GetRangeAfterStandby()));
+ break;
+
+ case LL_RCC_I2C1_CLKSOURCE_PCLK1: /* I2C1 Clock is PCLK1 */
+ i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+
+ default:
+ /* unreachable code */
+ break;
+ }
+ }
+ else if (I2CxSource == LL_RCC_I2C2_CLKSOURCE)
+ {
+ /* I2C2 CLK clock frequency */
+ switch (LL_RCC_GetI2CClockSource(I2CxSource))
+ {
+ case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */
+ i2c_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_I2C2_CLKSOURCE_HSI: /* I2C2 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady() == 1U)
+ {
+ i2c_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_I2C2_CLKSOURCE_MSIK: /* I2C2 Clock is MSIK Osc.*/
+ i2c_frequency = __LL_RCC_CALC_MSIK_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
+ LL_RCC_MSIK_GetRange() :
+ LL_RCC_MSIK_GetRangeAfterStandby()));
+ break;
+ case LL_RCC_I2C2_CLKSOURCE_PCLK1: /* I2C2 Clock is PCLK1 */
+ i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+
+ default:
+ /* unreachable code */
+ break;
+ }
+ }
+ else if (I2CxSource == LL_RCC_I2C3_CLKSOURCE)
+ {
+ /* I2C3 CLK clock frequency */
+ switch (LL_RCC_GetI2CClockSource(I2CxSource))
+ {
+ case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */
+ i2c_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady() == 1U)
+ {
+ i2c_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_I2C3_CLKSOURCE_MSIK: /* I2C3 Clock is MSIK Osc.*/
+ i2c_frequency = __LL_RCC_CALC_MSIK_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
+ LL_RCC_MSIK_GetRange() :
+ LL_RCC_MSIK_GetRangeAfterStandby()));
+ break;
+ case LL_RCC_I2C3_CLKSOURCE_PCLK3: /* I2C3 Clock is PCLK3 */
+ i2c_frequency = RCC_GetPCLK3ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+
+ default:
+ /* unreachable code */
+ break;
+ }
+ }
+ else if (I2CxSource == LL_RCC_I2C4_CLKSOURCE)
+ {
+ /* I2C4 CLK clock frequency */
+ switch (LL_RCC_GetI2CClockSource(I2CxSource))
+ {
+ case LL_RCC_I2C4_CLKSOURCE_SYSCLK: /* I2C4 Clock is System Clock */
+ i2c_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_I2C4_CLKSOURCE_HSI: /* I2C4 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady() == 1U)
+ {
+ i2c_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_I2C4_CLKSOURCE_MSIK: /* I2C4 Clock is MSIK Osc.*/
+ i2c_frequency = __LL_RCC_CALC_MSIK_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
+ LL_RCC_MSIK_GetRange() :
+ LL_RCC_MSIK_GetRangeAfterStandby()));
+ break;
+ case LL_RCC_I2C4_CLKSOURCE_PCLK1: /* I2C4 Clock is PCLK1 */
+ i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+
+ default:
+ /* unreachable code */
+ break;
+ }
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+ return i2c_frequency;
+}
+
+/**
+ * @brief Return LPUARTx clock frequency
+ * @param LPUARTxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_LPUART1_CLKSOURCE
+ * @retval LPUART clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
+ */
+uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)
+{
+ uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_LPUART_CLKSOURCE(LPUARTxSource));
+
+ /* LPUART1CLK clock frequency */
+ switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
+ {
+ case LL_RCC_LPUART1_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */
+ lpuart_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_LPUART1_CLKSOURCE_HSI: /* LPUART1 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady() == 1U)
+ {
+ lpuart_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_LPUART1_CLKSOURCE_LSE: /* LPUART1 Clock is LSE Osc. */
+ if (LL_RCC_LSE_IsReady() == 1U)
+ {
+ lpuart_frequency = LSE_VALUE;
+ }
+ break;
+
+ case LL_RCC_LPUART1_CLKSOURCE_PCLK3: /* LPUART1 Clock is PCLK3 */
+ lpuart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+
+ default:
+ /* unreachable code */
+ break;
+ }
+
+ return lpuart_frequency;
+}
+
+/**
+ * @brief Return LPTIMx clock frequency
+ * @param LPTIMxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
+ * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
+ * @arg @ref LL_RCC_LPTIM34_CLKSOURCE
+ * @retval LPTIM clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready
+ */
+uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
+{
+ uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
+
+ if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)
+ {
+ /* LPTIM1CLK clock frequency */
+ switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
+ {
+ case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */
+ if (LL_RCC_LSI_IsReady() == 1U)
+ {
+ lptim_frequency = LSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady() == 1U)
+ {
+ lptim_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */
+ if (LL_RCC_LSE_IsReady() == 1U)
+ {
+ lptim_frequency = LSE_VALUE;
+ }
+ break;
+
+ case LL_RCC_LPTIM1_CLKSOURCE_MSIK: /* LPTIM1 Clock is MSIK Osc.*/
+ lptim_frequency = __LL_RCC_CALC_MSIK_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
+ LL_RCC_MSIK_GetRange() :
+ LL_RCC_MSIK_GetRangeAfterStandby()));
+ break;
+
+ default:
+ /* unreachable code */
+ break;
+ }
+ }
+ else if (LPTIMxSource == LL_RCC_LPTIM2_CLKSOURCE)
+ {
+ /* LPTIM2CLK clock frequency */
+ switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
+ {
+ case LL_RCC_LPTIM2_CLKSOURCE_LSI: /* LPTIM2 Clock is LSI Osc. */
+ if (LL_RCC_LSI_IsReady() == 1U)
+ {
+ lptim_frequency = LSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_LPTIM2_CLKSOURCE_HSI: /* LPTIM2 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady() == 1U)
+ {
+ lptim_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_LPTIM2_CLKSOURCE_LSE: /* LPTIM2 Clock is LSE Osc. */
+ if (LL_RCC_LSE_IsReady() == 1U)
+ {
+ lptim_frequency = LSE_VALUE;
+ }
+ break;
+
+ case LL_RCC_LPTIM2_CLKSOURCE_PCLK1: /* LPTIM2 Clock is PCLK1 */
+ lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+
+ default:
+ /* unreachable code */
+ break;
+ }
+ }
+ else if (LPTIMxSource == LL_RCC_LPTIM34_CLKSOURCE)
+ {
+ /* LPTIM34CLK clock frequency */
+ switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
+ {
+ case LL_RCC_LPTIM34_CLKSOURCE_LSI: /* LPTIM34 Clock is LSI Osc. */
+ if (LL_RCC_LSI_IsReady() == 1U)
+ {
+ lptim_frequency = LSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_LPTIM34_CLKSOURCE_HSI: /* LPTIM34 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady() == 1U)
+ {
+ lptim_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_LPTIM34_CLKSOURCE_LSE: /* LPTIM34 Clock is LSE Osc. */
+ if (LL_RCC_LSE_IsReady() == 1U)
+ {
+ lptim_frequency = LSE_VALUE;
+ }
+ break;
+
+ case LL_RCC_LPTIM34_CLKSOURCE_MSIK: /* LPTIM34 Clock is MSIK */
+ lptim_frequency = __LL_RCC_CALC_MSIK_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
+ LL_RCC_MSIK_GetRange() :
+ LL_RCC_MSIK_GetRangeAfterStandby()));
+ break;
+
+ default:
+ /* unreachable code */
+ break;
+ }
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+ return lptim_frequency;
+}
+
+/**
+ * @brief Return SAIx clock frequency
+ * @param SAIxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE
+ * @arg @ref LL_RCC_SAI2_CLKSOURCE
+ * @retval SAI clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready
+ */
+uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
+{
+ uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
+
+ if (SAIxSource == LL_RCC_SAI1_CLKSOURCE)
+ {
+ /* SAI1CLK clock frequency */
+ switch (LL_RCC_GetSAIClockSource(SAIxSource))
+ {
+ case LL_RCC_SAI1_CLKSOURCE_PLL2: /* PLL2 clock used as SAI1 clock source */
+ if (LL_RCC_PLL2_IsReady() == 1U)
+ {
+ sai_frequency = RCC_PLL2_GetFreqDomain_SAI();
+ }
+ break;
+
+ case LL_RCC_SAI1_CLKSOURCE_PLL3: /* PLL3 clock used as SAI1 clock source */
+ if (LL_RCC_PLL3_IsReady() == 1U)
+ {
+ sai_frequency = RCC_PLL3_GetFreqDomain_SAI();
+ }
+ break;
+
+ case LL_RCC_SAI1_CLKSOURCE_PLL1: /* PLL1 clock used as SAI1 clock source */
+ if (LL_RCC_PLL1_IsReady() == 1U)
+ {
+ sai_frequency = RCC_PLL1_GetFreqDomain_SAI();
+ }
+ break;
+
+ case LL_RCC_SAI1_CLKSOURCE_PIN: /* External input clock used as SAI1 clock source */
+ sai_frequency = EXTERNAL_SAI1_CLOCK_VALUE;
+ break;
+
+ default:
+ /* unreachable code */
+ break;
+ }
+ }
+ else if (SAIxSource == LL_RCC_SAI2_CLKSOURCE)
+ {
+ /* SAI2CLK clock frequency */
+ switch (LL_RCC_GetSAIClockSource(SAIxSource))
+ {
+ case LL_RCC_SAI2_CLKSOURCE_PLL2: /* PLL2 clock used as SAI2 clock source */
+ if (LL_RCC_PLL2_IsReady() == 1U)
+ {
+ sai_frequency = RCC_PLL2_GetFreqDomain_SAI();
+ }
+ break;
+
+ case LL_RCC_SAI2_CLKSOURCE_PLL3: /* PLL3 clock used as SAI2 clock source */
+ if (LL_RCC_PLL3_IsReady() == 1U)
+ {
+ sai_frequency = RCC_PLL3_GetFreqDomain_SAI();
+ }
+ break;
+
+ case LL_RCC_SAI2_CLKSOURCE_PLL1: /* PLL1 clock used as SAI2 clock source */
+ if (LL_RCC_PLL1_IsReady() == 1U)
+ {
+ sai_frequency = RCC_PLL1_GetFreqDomain_SAI();
+ }
+ break;
+
+ case LL_RCC_SAI2_CLKSOURCE_PIN: /* External input clock used as SAI2 clock source */
+ sai_frequency = EXTERNAL_SAI2_CLOCK_VALUE;
+ break;
+
+ default:
+ /* unreachable code */
+ break;
+ }
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+ return sai_frequency;
+}
+
+/**
+ * @brief Return SDMMCx kernel clock frequency
+ * @param SDMMCxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SDMMC_KERNELCLKSOURCE
+ * @retval SDMMC clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator or PLL is not ready
+ */
+uint32_t LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource)
+{
+ uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_SDMMC_KERNELCLKSOURCE(SDMMCxSource));
+
+ /* SDMMC12CLK kernel clock frequency */
+ switch (LL_RCC_GetSDMMCKernelClockSource(SDMMCxSource))
+ {
+ case LL_RCC_SDMMC12_KERNELCLKSOURCE_48CLK: /* 48MHz clock from internal multiplexor used as SDMMC1/2 clock source */
+ sdmmc_frequency = LL_RCC_GetSDMMCClockFreq(LL_RCC_SDMMC_CLKSOURCE);
+ break;
+
+ case LL_RCC_SDMMC12_KERNELCLKSOURCE_PLL1: /* PLL1 "P" output (PLL1CLK) clock used as SDMMC1/2 clock source */
+ if (LL_RCC_PLL1_IsReady() == 1U)
+ {
+ sdmmc_frequency = RCC_PLL1_GetFreqDomain_SAI();
+ }
+ break;
+
+ default:
+ /* unreachable code */
+ break;
+ }
+
+ return sdmmc_frequency;
+}
+
+/**
+ * @brief Return SDMMCx clock frequency
+ * @param SDMMCxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SDMMC_CLKSOURCE
+ * @retval SDMMC clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI /MSIK /HSI) or PLL is not ready
+ */
+uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)
+{
+ uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_SDMMC_CLKSOURCE(SDMMCxSource));
+
+ /* SDMMC1CLK clock frequency */
+ switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
+ {
+ case LL_RCC_SDMMC12_CLKSOURCE_PLL2: /* PLL2 clock used as SDMMC12 clock source */
+ if (LL_RCC_PLL2_IsReady() == 1U)
+ {
+ sdmmc_frequency = RCC_PLL2_GetFreqDomain_48M();
+ }
+ break;
+
+ case LL_RCC_SDMMC12_CLKSOURCE_PLL1: /* PLL1 clock used as SDMMC12 clock source */
+ if (LL_RCC_PLL1_IsReady() == 1U)
+ {
+ sdmmc_frequency = RCC_PLL1_GetFreqDomain_48M();
+ }
+ break;
+
+ case LL_RCC_SDMMC12_CLKSOURCE_MSIK: /* MSIK clock used as SDMMC12 clock source */
+ if (LL_RCC_MSIS_IsReady() == 1U)
+ {
+ sdmmc_frequency = __LL_RCC_CALC_MSIK_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
+ LL_RCC_MSIK_GetRange() :
+ LL_RCC_MSIK_GetRangeAfterStandby()));
+ }
+ break;
+
+ case LL_RCC_SDMMC12_CLKSOURCE_HSI48: /* HSI48 used as SDMMC1 clock source */
+ if (LL_RCC_HSI48_IsReady() == 1U)
+ {
+ sdmmc_frequency = HSI48_VALUE;
+ }
+ break;
+
+ default:
+ /* unreachable code */
+ break;
+ }
+
+ return sdmmc_frequency;
+}
+
+/**
+ * @brief Return RNGx clock frequency
+ * @param RNGxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_RNG_CLKSOURCE
+ * @retval RNG clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI or HSI48) or PLL is not ready
+ */
+uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
+{
+ uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));
+
+ /* RNGCLK clock frequency */
+ switch (LL_RCC_GetRNGClockSource(RNGxSource))
+ {
+ case LL_RCC_RNG_CLKSOURCE_HSI: /* HSI clock used as RNG clock source */
+ if (LL_RCC_HSI_IsReady() == 1U)
+ {
+ rng_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_RNG_CLKSOURCE_HSI48: /* HSI48 clock used as RNG clock source */
+ if (LL_RCC_HSI48_IsReady() == 1U)
+ {
+ rng_frequency = HSI48_VALUE;
+ }
+ break;
+
+ case LL_RCC_RNG_CLKSOURCE_HSI48_DIV2: /* HSI48DIV2 clock used as RNG clock source */
+ if (LL_RCC_HSI48_IsReady() == 1U)
+ {
+ rng_frequency = (HSI48_VALUE / 2U);
+ }
+ break;
+
+ default:
+ /* unreachable code */
+ break;
+
+ }
+
+ return rng_frequency;
+}
+
+/**
+ * @brief Return USBx clock frequency
+ * @param USBxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_USB_CLKSOURCE
+ * @retval USB clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI /HSI48) or PLL is not ready
+ */
+uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
+{
+ uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
+
+ /* USBCLK clock frequency */
+ switch (LL_RCC_GetUSBClockSource(USBxSource))
+ {
+ case LL_RCC_USB_CLKSOURCE_PLL2: /* PLL2 clock used as USB clock source */
+ if (LL_RCC_PLL2_IsReady() == 1U)
+ {
+ usb_frequency = RCC_PLL2_GetFreqDomain_48M();
+ }
+ break;
+
+ case LL_RCC_USB_CLKSOURCE_PLL1: /* PLL1 clock used as USB clock source */
+ if (LL_RCC_PLL1_IsReady() == 1U)
+ {
+ usb_frequency = RCC_PLL1_GetFreqDomain_48M();
+ }
+ break;
+
+ case LL_RCC_USB_CLKSOURCE_MSIK: /* MSIK clock used as USB clock source */
+ if (LL_RCC_MSIK_IsReady() == 1U)
+ {
+ usb_frequency = __LL_RCC_CALC_MSIK_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
+ LL_RCC_MSIK_GetRange() :
+ LL_RCC_MSIK_GetRangeAfterStandby()));
+ }
+ break;
+
+ case LL_RCC_USB_CLKSOURCE_HSI48: /* HSI48 clock used as USB clock source */
+ if (LL_RCC_HSI48_IsReady() == 1U)
+ {
+ usb_frequency = HSI48_VALUE;
+ }
+ break;
+
+ default:
+ /* unreachable code */
+ break;
+ }
+
+ return usb_frequency;
+}
+
+/**
+ * @brief Return ADCxDAC clock frequency
+ * @param ADCxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_ADCDAC_CLKSOURCE
+ * @retval ADC/DAC clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI /HSI /MSIK) or PLL is not ready
+ */
+uint32_t LL_RCC_GetADCDACClockFreq(uint32_t ADCxSource)
+{
+ uint32_t adcdac_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_ADCDAC_CLKSOURCE(ADCxSource));
+
+ /* ADCCLK clock frequency */
+ switch (LL_RCC_GetADCDACClockSource(ADCxSource))
+ {
+ case LL_RCC_ADCDAC_CLKSOURCE_HCLK: /* ADCDAC Clock is SYSCLK */
+ adcdac_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_ADCDAC_CLKSOURCE_SYSCLK: /* SYSCLK clock used as ADCDAC clock source */
+ adcdac_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_ADCDAC_CLKSOURCE_PLL2: /* PLL2 clock used as ADCDAC clock source */
+ if (LL_RCC_PLL2_IsReady() == 1U)
+ {
+ adcdac_frequency = RCC_PLL2_GetFreqDomain_ADC();
+ }
+ break;
+
+ case LL_RCC_ADCDAC_CLKSOURCE_HSI: /*HSI clock used as ADCDAC clock source */
+ if (LL_RCC_HSI_IsReady() == 1U)
+ {
+ adcdac_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_ADCDAC_CLKSOURCE_HSE: /*HSE clock used as ADCDAC clock source */
+ if (LL_RCC_HSE_IsReady() == 1U)
+ {
+ adcdac_frequency = HSE_VALUE;
+ }
+ break;
+
+ case LL_RCC_ADCDAC_CLKSOURCE_MSIK: /* MSIK clock used as ADCDAC clock source */
+ if (LL_RCC_MSIK_IsReady() == 1U)
+ {
+ adcdac_frequency = __LL_RCC_CALC_MSIK_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
+ LL_RCC_MSIK_GetRange() :
+ LL_RCC_MSIK_GetRangeAfterStandby()));
+ }
+ break;
+
+ default:
+ /* unreachable code */
+ break;
+ }
+
+ return adcdac_frequency;
+}
+
+/**
+ * @brief Return ADF1 clock frequency
+ * @param ADF1Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_ADF1_CLKSOURCE
+ * @retval ADF1 clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSIK) or PLL is not ready
+ */
+uint32_t LL_RCC_GetADF1ClockFreq(uint32_t ADF1Source)
+{
+ uint32_t ADF1_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_ADF1_CLKSOURCE(ADF1Source));
+
+ /* ADF11CLK clock frequency */
+ switch (LL_RCC_GetADF1ClockSource(ADF1Source))
+ {
+ case LL_RCC_ADF1_CLKSOURCE_HCLK: /* ADF1 Clock is SYSCLK */
+ ADF1_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_ADF1_CLKSOURCE_PLL1: /* ADF1 Clock is PLL1 */
+ ADF1_frequency = RCC_PLL1_GetFreqDomain_SAI();
+ break;
+
+ case LL_RCC_ADF1_CLKSOURCE_PLL3: /* ADF1 Clock is PLL3 */
+ ADF1_frequency = RCC_PLL3_GetFreqDomain_48M();
+ break;
+
+ case LL_RCC_ADF1_CLKSOURCE_PIN: /* External input clock used as ADF1 clock source */
+ ADF1_frequency = EXTERNAL_SAI1_CLOCK_VALUE;
+ break;
+
+ case LL_RCC_ADF1_CLKSOURCE_MSIK: /* ADF1 Clock is MSIK */
+ ADF1_frequency = __LL_RCC_CALC_MSIK_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
+ LL_RCC_MSIK_GetRange() :
+ LL_RCC_MSIK_GetRangeAfterStandby()));
+ break;
+
+ default:
+ /* unreachable code */
+ break;
+ }
+
+ return ADF1_frequency;
+}
+
+/**
+ * @brief Return MDF1 clock frequency
+ * @param MDF1Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_MDF1_CLKSOURCE
+ * @retval MDF1 clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSIK) or PLL is not ready
+ */
+uint32_t LL_RCC_GetMDF1ClockFreq(uint32_t MDF1Source)
+{
+ uint32_t MDF1_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_MDF1_CLKSOURCE(MDF1Source));
+
+ /* MDF11CLK clock frequency */
+ switch (LL_RCC_GetMDF1ClockSource(MDF1Source))
+ {
+ case LL_RCC_MDF1_CLKSOURCE_HCLK: /* MDF1 Clock is SYSCLK */
+ MDF1_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_MDF1_CLKSOURCE_PLL1: /* MDF1 Clock is PLL1 */
+ MDF1_frequency = RCC_PLL1_GetFreqDomain_SAI();
+ break;
+
+ case LL_RCC_MDF1_CLKSOURCE_PLL3: /* MDF1 Clock is PLL3 */
+ MDF1_frequency = RCC_PLL3_GetFreqDomain_48M();
+ break;
+
+ case LL_RCC_MDF1_CLKSOURCE_PIN: /* External input clock used as MDF1 clock source */
+ MDF1_frequency = EXTERNAL_SAI1_CLOCK_VALUE;
+ break;
+
+ case LL_RCC_MDF1_CLKSOURCE_MSIK: /* MDF1 Clock is MSIK */
+ MDF1_frequency = __LL_RCC_CALC_MSIK_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
+ LL_RCC_MSIK_GetRange() :
+ LL_RCC_MSIK_GetRangeAfterStandby()));
+ break;
+
+ default:
+ /* unreachable code */
+ break;
+ }
+
+ return MDF1_frequency;
+}
+
+/**
+ * @brief Return DAC1 clock frequency
+ * @param DAC1Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_DAC1_CLKSOURCE
+ * @retval DAC1 clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that LSI or LSE oscillator is not ready
+ */
+uint32_t LL_RCC_GetDAC1ClockFreq(uint32_t DAC1Source)
+{
+ uint32_t DAC1_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_DAC1_CLKSOURCE(DAC1Source));
+
+ /* DAC1CLK clock frequency */
+ switch (LL_RCC_GetDAC1ClockSource(DAC1Source))
+ {
+ case LL_RCC_DAC1_CLKSOURCE_LSI: /* DAC1 Clock is LSI */
+ DAC1_frequency = LSI_VALUE;
+ break;
+
+ case LL_RCC_DAC1_CLKSOURCE_LSE: /* DAC1 Clock is LSE */
+ DAC1_frequency = LSE_VALUE;
+ break;
+
+ default:
+ /* unreachable code */
+ break;
+ }
+
+ return DAC1_frequency;
+}
+
+/**
+ * @brief Return OCTOSPI clock frequency
+ * @param OCTOSPIxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE
+ * @retval OCTOSPI clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator MSIK or PLL is not ready
+ */
+uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource)
+{
+ uint32_t octospi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_OCTOSPI_CLKSOURCE(OCTOSPIxSource));
+
+ /* OCTOSPI clock frequency */
+ switch (LL_RCC_GetOCTOSPIClockSource(OCTOSPIxSource))
+ {
+ case LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK: /* OCTOSPI clock is SYSCLK */
+ octospi_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_OCTOSPI_CLKSOURCE_MSIK: /* MSIk clock used as OCTOSPI clock */
+ if (LL_RCC_MSIK_IsReady() == 1U)
+ {
+ octospi_frequency = __LL_RCC_CALC_MSIK_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
+ LL_RCC_MSIK_GetRange() :
+ LL_RCC_MSIK_GetRangeAfterStandby()));
+ }
+ break;
+
+ case LL_RCC_OCTOSPI_CLKSOURCE_PLL1: /* PLL1 clock used as OCTOSPI source */
+ if (LL_RCC_PLL1_IsReady() == 1U)
+ {
+ octospi_frequency = RCC_PLL1_GetFreqDomain_48M();
+ }
+ break;
+ case LL_RCC_OCTOSPI_CLKSOURCE_PLL2: /* PLL2 clock used as OCTOSPI source */
+ if (LL_RCC_PLL2_IsReady() == 1U)
+ {
+ octospi_frequency = RCC_PLL2_GetFreqDomain_48M();
+ }
+ break;
+
+ default:
+ /* unreachable code */
+ break;
+ }
+
+ return octospi_frequency;
+}
+
+/**
+ * @brief Return SAESx clock frequency
+ * @param SAESxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SAES_CLKSOURCE
+ * @retval SAEx clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator SHSI is not ready
+ */
+uint32_t LL_RCC_GetSAESClockFreq(uint32_t SAESxSource)
+{
+ uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_SAES_CLKSOURCE(SAESxSource));
+
+ /* SAESCLK clock frequency */
+ switch (LL_RCC_GetSAESClockSource(SAESxSource))
+ {
+
+ case LL_RCC_SAES_CLKSOURCE_SHSI: /* SHSI clock used as SAES clock source */
+ if (LL_RCC_SHSI_IsReady() == 1U)
+ {
+ rng_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_SAES_CLKSOURCE_SHSI_DIV2: /* SHSIDIV2 clock used as SAES clock source */
+ if (LL_RCC_SHSI_IsReady() == 1U)
+ {
+ rng_frequency = (HSI_VALUE / 2U);
+ }
+ break;
+
+ default:
+ /* unreachable code */
+ break;
+ }
+
+ return rng_frequency;
+}
+
+/**
+ * @brief Return FDCAN kernel clock frequency
+ * @param FDCANxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_FDCAN_CLKSOURCE
+ * @retval FDCAN kernel clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator HSE or PLL is not ready
+ */
+uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource)
+{
+ uint32_t fdcan_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_FDCAN_CLKSOURCE(FDCANxSource));
+
+ /* FDCAN kernel clock frequency */
+ switch (LL_RCC_GetFDCANClockSource(FDCANxSource))
+ {
+ case LL_RCC_FDCAN_CLKSOURCE_HSE: /* HSE clock used as FDCAN kernel clock */
+ if (LL_RCC_HSE_IsReady() == 1U)
+ {
+ fdcan_frequency = HSE_VALUE;
+ }
+ break;
+
+ case LL_RCC_FDCAN_CLKSOURCE_PLL1: /* PLL2 clock used as FDCAN kernel clock */
+ if (LL_RCC_PLL1_IsReady() == 1U)
+ {
+ fdcan_frequency = RCC_PLL1_GetFreqDomain_48M();
+ }
+ break;
+
+ case LL_RCC_FDCAN_CLKSOURCE_PLL2: /* PLL2 clock used as FDCAN kernel clock */
+ if (LL_RCC_PLL2_IsReady() == 1U)
+ {
+ fdcan_frequency = RCC_PLL2_GetFreqDomain_SAI();
+ }
+ break;
+
+ default:
+ /* unreachable code */
+ break;
+ }
+
+ return fdcan_frequency;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_LL_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Return SYSTEM clock frequency
+ * @retval SYSTEM clock frequency (in Hz)
+ */
+static uint32_t RCC_GetSystemClockFreq(void)
+{
+ uint32_t frequency;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ switch (LL_RCC_GetSysClkSource())
+ {
+ case LL_RCC_SYS_CLKSOURCE_STATUS_MSIS: /* MSIS used as system clock source */
+ frequency = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
+ LL_RCC_MSIS_GetRange() :
+ LL_RCC_MSIS_GetRangeAfterStandby()));
+ break;
+
+ case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
+ frequency = HSI_VALUE;
+ break;
+
+ case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
+ frequency = HSE_VALUE;
+ break;
+
+ case LL_RCC_SYS_CLKSOURCE_STATUS_PLL1: /* PLL1 used as system clock source */
+ frequency = RCC_PLL1_GetFreqDomain_SYS();
+ break;
+
+ default:
+ frequency = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
+ LL_RCC_MSIS_GetRange() :
+ LL_RCC_MSIS_GetRangeAfterStandby()));
+ break;
+ }
+
+ return frequency;
+}
+
+/**
+ * @brief Return HCLK clock frequency
+ * @param SYSCLK_Frequency SYSCLK clock frequency
+ * @retval HCLK clock frequency (in Hz)
+ */
+static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
+{
+ /* HCLK clock frequency */
+ return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
+}
+
+/**
+ * @brief Return PCLK1 clock frequency
+ * @param HCLK_Frequency HCLK clock frequency
+ * @retval PCLK1 clock frequency (in Hz)
+ */
+static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
+{
+ /* PCLK1 clock frequency */
+ return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
+}
+
+/**
+ * @brief Return PCLK2 clock frequency
+ * @param HCLK_Frequency HCLK clock frequency
+ * @retval PCLK2 clock frequency (in Hz)
+ */
+static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
+{
+ /* PCLK2 clock frequency */
+ return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
+}
+
+
+/**
+ * @brief Return PCLK3 clock frequency
+ * @param HCLK_Frequency HCLK clock frequency
+ * @retval PCLK3 clock frequency (in Hz)
+ */
+static uint32_t RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency)
+{
+ /* PCLK2 clock frequency */
+ return __LL_RCC_CALC_PCLK3_FREQ(HCLK_Frequency, LL_RCC_GetAPB3Prescaler());
+}
+
+/**
+ * @brief Return PLL1 clock frequency used for system domain
+ * @retval PLL1 clock frequency (in Hz)
+ */
+static uint32_t RCC_PLL1_GetFreqDomain_SYS(void)
+{
+ uint32_t pllinputfreq;
+ uint32_t pllsource;
+
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+ SYSCLK = PLL_VCO / PLLR
+ */
+ pllsource = LL_RCC_PLL1_GetMainSource();
+
+ switch (pllsource)
+ {
+ case LL_RCC_PLL1SOURCE_MSIS: /* MSIS used as PLL1 clock source */
+ pllinputfreq = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
+ LL_RCC_MSIS_GetRange() :
+ LL_RCC_MSIS_GetRangeAfterStandby()));
+ break;
+
+ case LL_RCC_PLL1SOURCE_HSI: /* HSI used as PLL1 clock source */
+ pllinputfreq = HSI_VALUE;
+ break;
+
+ case LL_RCC_PLL1SOURCE_HSE: /* HSE used as PLL1 clock source */
+ pllinputfreq = HSE_VALUE;
+ break;
+
+ default:
+ pllinputfreq = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
+ LL_RCC_MSIS_GetRange() :
+ LL_RCC_MSIS_GetRangeAfterStandby()));
+ break;
+ }
+ return __LL_RCC_CALC_PLL1CLK_FREQ(pllinputfreq, LL_RCC_PLL1_GetDivider(),
+ LL_RCC_PLL1_GetN(), LL_RCC_PLL1_GetR());
+}
+/**
+ * @brief Return PLL1 clock frequency used for SAI domain
+ * @retval PLL1 clock frequency (in Hz)
+ */
+static uint32_t RCC_PLL1_GetFreqDomain_SAI(void)
+{
+ uint32_t pll1inputfreq;
+ uint32_t pll1outputfreq;
+ uint32_t pll1source;
+ uint32_t pll1n;
+ uint32_t pll1pdiv;
+
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE / PLLM) * PLLN
+ SAI Domain clock = PLL_VCO / PLL1P
+ */
+ pll1source = LL_RCC_PLL1_GetMainSource();
+
+ switch (pll1source)
+ {
+ case LL_RCC_PLL1SOURCE_MSIS: /* MSI used as PLL1 clock source */
+ pll1inputfreq = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
+ LL_RCC_MSIS_GetRange() :
+ LL_RCC_MSIS_GetRangeAfterStandby()));
+ break;
+
+ case LL_RCC_PLL1SOURCE_HSI: /* HSI used as PLL1 clock source */
+ pll1inputfreq = HSI_VALUE;
+ break;
+
+ case LL_RCC_PLL1SOURCE_HSE: /* HSE used as PLL1 clock source */
+ pll1inputfreq = HSE_VALUE;
+ break;
+
+ default:
+ pll1inputfreq = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
+ LL_RCC_MSIS_GetRange() :
+ LL_RCC_MSIS_GetRangeAfterStandby()));
+ break;
+ }
+
+ pll1n = LL_RCC_PLL1_GetN();
+ pll1pdiv = LL_RCC_PLL1_GetP();
+ if ((pll1n >= 8U) && (pll1pdiv >= 2U))
+ {
+ pll1outputfreq = __LL_RCC_CALC_PLL1CLK_SAI_FREQ(pll1inputfreq, LL_RCC_PLL1_GetDivider(),
+ pll1n, pll1pdiv);
+ }
+ else
+ {
+ pll1outputfreq = 0; /* Invalid PLL1N or PLL1PDIV value */
+ }
+ return pll1outputfreq;
+}
+
+/**
+ * @brief Return PLL clock frequency used for 48 MHz domain
+ * @retval PLL clock frequency (in Hz)
+ */
+static uint32_t RCC_PLL1_GetFreqDomain_48M(void)
+{
+ uint32_t pll1inputfreq;
+ uint32_t pll1source;
+
+ /* PLL1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLL1M) * PLL1N
+ 48M Domain clock = PLL1_VCO / PLL1Q
+ */
+ pll1source = LL_RCC_PLL1_GetMainSource();
+
+ switch (pll1source)
+ {
+ case LL_RCC_PLL1SOURCE_MSIS: /* MSI used as PLL1 clock source */
+ pll1inputfreq = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
+ LL_RCC_MSIS_GetRange() :
+ LL_RCC_MSIS_GetRangeAfterStandby()));
+ break;
+
+ case LL_RCC_PLL1SOURCE_HSI: /* HSI used as PLL1 clock source */
+ pll1inputfreq = HSI_VALUE;
+ break;
+
+ case LL_RCC_PLL1SOURCE_HSE: /* HSE used as PLL1 clock source */
+ pll1inputfreq = HSE_VALUE;
+ break;
+
+ default:
+ pll1inputfreq = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
+ LL_RCC_MSIS_GetRange() :
+ LL_RCC_MSIS_GetRangeAfterStandby()));
+ break;
+ }
+ return __LL_RCC_CALC_PLL1CLK_48M_FREQ(pll1inputfreq, LL_RCC_PLL1_GetDivider(),
+ LL_RCC_PLL1_GetN(), LL_RCC_PLL1_GetQ());
+}
+
+/**
+ * @brief Return PLL2 clock frequency used for SAI domain
+ * @retval PLL2 clock frequency (in Hz)
+ */
+static uint32_t RCC_PLL2_GetFreqDomain_SAI(void)
+{
+ uint32_t pll2inputfreq;
+ uint32_t pll2outputfreq;
+ uint32_t pll2source;
+ uint32_t pll2n;
+ uint32_t pll2pdiv;
+
+ /* PLL2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLL2M) * PLL2N */
+ /* SAI Domain clock = PLL2_VCO / PLL2P */
+ pll2source = LL_RCC_PLL2_GetSource();
+
+ switch (pll2source)
+ {
+ case LL_RCC_PLL2SOURCE_MSIS: /* MSI used as PLLSAI1 clock source */
+ pll2inputfreq = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
+ LL_RCC_MSIS_GetRange() :
+ LL_RCC_MSIS_GetRangeAfterStandby()));
+ break;
+
+ case LL_RCC_PLL2SOURCE_HSI: /* HSI used as PLL2 clock source */
+ pll2inputfreq = HSI_VALUE;
+ break;
+
+ case LL_RCC_PLL2SOURCE_HSE: /* HSE used as PLL2 clock source */
+ pll2inputfreq = HSE_VALUE;
+ break;
+
+ default:
+ pll2inputfreq = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
+ LL_RCC_MSIS_GetRange() :
+ LL_RCC_MSIS_GetRangeAfterStandby()));
+ break;
+ }
+
+ pll2n = LL_RCC_PLL2_GetN();
+ pll2pdiv = LL_RCC_PLL2_GetP();
+ if ((pll2n >= 8U) && (pll2pdiv >= 2U))
+ {
+ pll2outputfreq = __LL_RCC_CALC_PLL2CLK_SAI_FREQ(pll2inputfreq, LL_RCC_PLL2_GetDivider(),
+ pll2n, pll2pdiv);
+ }
+ else
+ {
+ pll2outputfreq = 0; /* Invalid PLL2N or PLL2PDIV value */
+ }
+ return pll2outputfreq;
+}
+
+/**
+ * @brief Return PLL2 clock frequency used for 48Mhz domain
+ * @retval PLL2 clock frequency (in Hz)
+ */
+static uint32_t RCC_PLL2_GetFreqDomain_48M(void)
+{
+ uint32_t pll2inputfreq;
+ uint32_t pll2source;
+
+ /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLL2M) * PLL2N */
+ /* 48M Domain clock = PLL2_VCO / PLL2Q */
+ pll2source = LL_RCC_PLL2_GetSource();
+
+ switch (pll2source)
+ {
+ case LL_RCC_PLL2SOURCE_MSIS: /* MSI used as PLL2 clock source */
+ pll2inputfreq = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
+ LL_RCC_MSIS_GetRange() :
+ LL_RCC_MSIS_GetRangeAfterStandby()));
+ break;
+
+ case LL_RCC_PLL2SOURCE_HSI: /* HSI used as PLL2 clock source */
+ pll2inputfreq = HSI_VALUE;
+ break;
+
+ case LL_RCC_PLL2SOURCE_HSE: /* HSE used as PLL2 clock source */
+ pll2inputfreq = HSE_VALUE;
+ break;
+
+ default:
+ pll2inputfreq = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
+ LL_RCC_MSIS_GetRange() :
+ LL_RCC_MSIS_GetRangeAfterStandby()));
+ break;
+ }
+ return __LL_RCC_CALC_PLL2CLK_48M_FREQ(pll2inputfreq, LL_RCC_PLL2_GetDivider(),
+ LL_RCC_PLL2_GetN(), LL_RCC_PLL2_GetQ());
+}
+
+/**
+ * @brief Return PLL2 clock frequency used for ADC domain
+ * @retval PLL2 clock frequency (in Hz)
+ */
+static uint32_t RCC_PLL2_GetFreqDomain_ADC(void)
+{
+ uint32_t pll2inputfreq;
+ uint32_t pll2source;
+
+ /* PLL2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLL2M) * PLL2N */
+ /* 48M Domain clock = PLL2_VCO / PLL2R */
+ pll2source = LL_RCC_PLL2_GetSource();
+
+ switch (pll2source)
+ {
+ case LL_RCC_PLL2SOURCE_MSIS: /* MSI used as PLL2 clock source */
+ pll2inputfreq = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
+ LL_RCC_MSIS_GetRange() :
+ LL_RCC_MSIS_GetRangeAfterStandby()));
+ break;
+
+ case LL_RCC_PLL2SOURCE_HSI: /* HSI used as PLL2 clock source */
+ pll2inputfreq = HSI_VALUE;
+ break;
+
+ case LL_RCC_PLL2SOURCE_HSE: /* HSE used as PLL2 clock source */
+ pll2inputfreq = HSE_VALUE;
+ break;
+
+ default:
+ pll2inputfreq = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
+ LL_RCC_MSIS_GetRange() :
+ LL_RCC_MSIS_GetRangeAfterStandby()));
+ break;
+ }
+ return __LL_RCC_CALC_PLL2CLK_ADC_FREQ(pll2inputfreq, LL_RCC_PLL2_GetDivider(),
+ LL_RCC_PLL2_GetN(), LL_RCC_PLL2_GetR());
+}
+
+/**
+ * @brief Return PLL3 clock frequency used for SAI domain
+ * @retval PLL3 clock frequency (in Hz)
+ */
+static uint32_t RCC_PLL3_GetFreqDomain_SAI(void)
+{
+ uint32_t pll3inputfreq;
+ uint32_t pll3outputfreq;
+ uint32_t pll3source;
+ uint32_t pll3n;
+ uint32_t pll3pdiv;
+
+ /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLL3M) * PLL3N */
+ /* SAI Domain clock = PLL3_VCO / PLL3P */
+ pll3source = LL_RCC_PLL3_GetSource();
+
+ switch (pll3source)
+ {
+ case LL_RCC_PLL3SOURCE_MSIS: /* MSI used as PLL3 clock source */
+ pll3inputfreq = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
+ LL_RCC_MSIS_GetRange() :
+ LL_RCC_MSIS_GetRangeAfterStandby()));
+ break;
+
+ case LL_RCC_PLL3SOURCE_HSI: /* HSI used as PLL3 clock source */
+ pll3inputfreq = HSI_VALUE;
+ break;
+
+ case LL_RCC_PLL3SOURCE_HSE: /* HSE used as PLL3 clock source */
+ pll3inputfreq = HSE_VALUE;
+ break;
+
+ default:
+ pll3inputfreq = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
+ LL_RCC_MSIS_GetRange() :
+ LL_RCC_MSIS_GetRangeAfterStandby()));
+ break;
+ }
+
+ pll3n = LL_RCC_PLL3_GetN();
+ pll3pdiv = LL_RCC_PLL3_GetP();
+ if ((pll3n >= 8U) && (pll3pdiv >= 2U))
+ {
+ pll3outputfreq = __LL_RCC_CALC_PLL3CLK_SAI_FREQ(pll3inputfreq, LL_RCC_PLL3_GetDivider(),
+ pll3n, pll3pdiv);
+ }
+ else
+ {
+ pll3outputfreq = 0; /* Invalid PLL3N or PLL3PDIV value */
+ }
+ return pll3outputfreq;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @brief Return PLL3clock frequency used for 48Mhz domain
+ * @retval PLL3 clock frequency (in Hz)
+ */
+static uint32_t RCC_PLL3_GetFreqDomain_48M(void)
+{
+ uint32_t PLL3inputfreq;
+ uint32_t PLL3source;
+
+ /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLL3M) * PLL3N */
+ /* 48M Domain clock = PLL3_VCO / PLL3Q */
+ PLL3source = LL_RCC_PLL3_GetSource();
+
+ switch (PLL3source)
+ {
+ case LL_RCC_PLL3SOURCE_MSIS: /* MSI used as PLL3 clock source */
+ PLL3inputfreq = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
+ LL_RCC_MSIS_GetRange() :
+ LL_RCC_MSIS_GetRangeAfterStandby()));
+ break;
+
+ case LL_RCC_PLL3SOURCE_HSI: /* HSI used as PLL3 clock source */
+ PLL3inputfreq = HSI_VALUE;
+ break;
+
+ case LL_RCC_PLL3SOURCE_HSE: /* HSE used as PLL3 clock source */
+ PLL3inputfreq = HSE_VALUE;
+ break;
+
+ default:
+ PLL3inputfreq = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
+ LL_RCC_MSIS_GetRange() :
+ LL_RCC_MSIS_GetRangeAfterStandby()));
+ break;
+ }
+ return __LL_RCC_CALC_PLL3CLK_48M_FREQ(PLL3inputfreq, LL_RCC_PLL3_GetDivider(),
+ LL_RCC_PLL3_GetN(), LL_RCC_PLL3_GetQ());
+}
+
+/**
+ * @}
+ */
+
+#endif /* defined(RCC) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_rng.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_rng.c
new file mode 100644
index 00000000..8a2938fb
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_rng.c
@@ -0,0 +1,148 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_rng.c
+ * @author MCD Application Team
+ * @brief RNG LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_ll_rng.h"
+#include "stm32u5xx_ll_bus.h"
+
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined (RNG)
+
+/** @addtogroup RNG_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup RNG_LL_Private_Macros RNG Private Macros
+ * @{
+ */
+#define IS_LL_RNG_CED(__MODE__) (((__MODE__) == LL_RNG_CED_ENABLE) || \
+ ((__MODE__) == LL_RNG_CED_DISABLE))
+
+#define IS_LL_RNG_CLOCK_DIVIDER(__CLOCK_DIV__) ((__CLOCK_DIV__) <=0x0Fu)
+
+
+#define IS_LL_RNG_NIST_COMPLIANCE(__NIST_COMPLIANCE__) (((__NIST_COMPLIANCE__) == LL_RNG_NIST_COMPLIANT) || \
+ ((__NIST_COMPLIANCE__) == LL_RNG_NOTNIST_COMPLIANT))
+
+#define IS_LL_RNG_CONFIG1 (__CONFIG1__) ((__CONFIG1__) <= 0x3FUL)
+
+#define IS_LL_RNG_CONFIG2 (__CONFIG2__) ((__CONFIG2__) <= 0x07UL)
+
+#define IS_LL_RNG_CONFIG3 (__CONFIG3__) ((__CONFIG3__) <= 0xFUL)
+/**
+ * @}
+ */
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RNG_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RNG_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize RNG registers (Registers restored to their default values).
+ * @param RNGx RNG Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RNG registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx)
+{
+ /* Check the parameters */
+ assert_param(IS_RNG_ALL_INSTANCE(RNGx));
+ /* Enable RNG reset state */
+ LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_RNG);
+
+ /* Release RNG from reset state */
+ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_RNG);
+ return (SUCCESS);
+}
+
+/**
+ * @brief Initialize RNG registers according to the specified parameters in RNG_InitStruct.
+ * @param RNGx RNG Instance
+ * @param RNG_InitStruct pointer to a LL_RNG_InitTypeDef structure
+ * that contains the configuration information for the specified RNG peripheral.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RNG registers are initialized according to RNG_InitStruct content
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_RNG_ALL_INSTANCE(RNGx));
+ assert_param(IS_LL_RNG_CED(RNG_InitStruct->ClockErrorDetection));
+
+ /* Clock Error Detection Configuration when CONDRT bit is set to 1 */
+ MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, RNG_InitStruct->ClockErrorDetection | RNG_CR_CONDRST);
+ /* Writing bits CONDRST=0*/
+ CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
+
+ return (SUCCESS);
+}
+
+/**
+ * @brief Set each @ref LL_RNG_InitTypeDef field to default value.
+ * @param RNG_InitStruct pointer to a @ref LL_RNG_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct)
+{
+ /* Set RNG_InitStruct fields to default values */
+ RNG_InitStruct->ClockErrorDetection = LL_RNG_CED_ENABLE;
+
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* RNG */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_rtc.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_rtc.c
new file mode 100644
index 00000000..86112bb4
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_rtc.c
@@ -0,0 +1,882 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_rtc.c
+ * @author MCD Application Team
+ * @brief RTC LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_ll_rtc.h"
+#include "stm32u5xx_ll_cortex.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined(RTC)
+
+/** @addtogroup RTC_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup RTC_LL_Private_Constants
+ * @{
+ */
+/* Default values used for prescaler */
+#define RTC_ASYNCH_PRESC_DEFAULT ((uint32_t) 0x0000007FU)
+#define RTC_SYNCH_PRESC_DEFAULT ((uint32_t) 0x000000FFU)
+
+/* Values used for timeout */
+#define RTC_INITMODE_TIMEOUT ((uint32_t) 1000U) /* 1s when tick set to 1ms */
+#define RTC_SYNCHRO_TIMEOUT ((uint32_t) 1000U) /* 1s when tick set to 1ms */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RTC_LL_Private_Macros
+ * @{
+ */
+
+#define IS_LL_RTC_HOURFORMAT(__VALUE__) (((__VALUE__) == LL_RTC_HOURFORMAT_24HOUR) \
+ || ((__VALUE__) == LL_RTC_HOURFORMAT_AMPM))
+
+#define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FU)
+
+#define IS_LL_RTC_SYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FFFU)
+
+#define IS_LL_RTC_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_FORMAT_BIN) \
+ || ((__VALUE__) == LL_RTC_FORMAT_BCD))
+
+#define IS_LL_RTC_TIME_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_TIME_FORMAT_AM_OR_24) \
+ || ((__VALUE__) == LL_RTC_TIME_FORMAT_PM))
+
+#define IS_LL_RTC_HOUR12(__HOUR__) (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))
+#define IS_LL_RTC_HOUR24(__HOUR__) ((__HOUR__) <= 23U)
+#define IS_LL_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= 59U)
+#define IS_LL_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= 59U)
+
+#define IS_LL_RTC_WEEKDAY(__VALUE__) (((__VALUE__) == LL_RTC_WEEKDAY_MONDAY) \
+ || ((__VALUE__) == LL_RTC_WEEKDAY_TUESDAY) \
+ || ((__VALUE__) == LL_RTC_WEEKDAY_WEDNESDAY) \
+ || ((__VALUE__) == LL_RTC_WEEKDAY_THURSDAY) \
+ || ((__VALUE__) == LL_RTC_WEEKDAY_FRIDAY) \
+ || ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \
+ || ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY))
+
+#define IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= (uint32_t)1U) && ((__DAY__) <= (uint32_t)31U))
+
+#define IS_LL_RTC_MONTH(__VALUE__) (((__VALUE__) == LL_RTC_MONTH_JANUARY) \
+ || ((__VALUE__) == LL_RTC_MONTH_FEBRUARY) \
+ || ((__VALUE__) == LL_RTC_MONTH_MARCH) \
+ || ((__VALUE__) == LL_RTC_MONTH_APRIL) \
+ || ((__VALUE__) == LL_RTC_MONTH_MAY) \
+ || ((__VALUE__) == LL_RTC_MONTH_JUNE) \
+ || ((__VALUE__) == LL_RTC_MONTH_JULY) \
+ || ((__VALUE__) == LL_RTC_MONTH_AUGUST) \
+ || ((__VALUE__) == LL_RTC_MONTH_SEPTEMBER) \
+ || ((__VALUE__) == LL_RTC_MONTH_OCTOBER) \
+ || ((__VALUE__) == LL_RTC_MONTH_NOVEMBER) \
+ || ((__VALUE__) == LL_RTC_MONTH_DECEMBER))
+
+#define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
+
+#define IS_LL_RTC_ALMA_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMA_MASK_NONE) \
+ || ((__VALUE__) == LL_RTC_ALMA_MASK_DATEWEEKDAY) \
+ || ((__VALUE__) == LL_RTC_ALMA_MASK_HOURS) \
+ || ((__VALUE__) == LL_RTC_ALMA_MASK_MINUTES) \
+ || ((__VALUE__) == LL_RTC_ALMA_MASK_SECONDS) \
+ || ((__VALUE__) == LL_RTC_ALMA_MASK_ALL))
+
+#define IS_LL_RTC_ALMB_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMB_MASK_NONE) \
+ || ((__VALUE__) == LL_RTC_ALMB_MASK_DATEWEEKDAY) \
+ || ((__VALUE__) == LL_RTC_ALMB_MASK_HOURS) \
+ || ((__VALUE__) == LL_RTC_ALMB_MASK_MINUTES) \
+ || ((__VALUE__) == LL_RTC_ALMB_MASK_SECONDS) \
+ || ((__VALUE__) == LL_RTC_ALMB_MASK_ALL))
+
+
+#define IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) || \
+ ((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY))
+
+#define IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) || \
+ ((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY))
+
+
+/**
+ * @}
+ */
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RTC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RTC_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-Initializes the RTC registers to their default reset values.
+ * @note This function does not reset the RTC Clock source and RTC Backup Data
+ * registers.
+ * @param RTCx RTC Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC registers are de-initialized
+ * - ERROR: RTC registers are not de-initialized
+ */
+ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the parameter */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+ /* Disable the write protection for RTC registers */
+ LL_RTC_DisableWriteProtection(RTCx);
+
+ /* Set Initialization mode */
+ if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+ {
+ WRITE_REG(RTCx->TR, 0x00000000U);
+ WRITE_REG(RTCx->DR, (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
+ WRITE_REG(RTCx->CR, 0x00000000U);
+ WRITE_REG(RTCx->WUTR, RTC_WUTR_WUT);
+ WRITE_REG(RTCx->PRER, (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT));
+ WRITE_REG(RTCx->ALRMAR, 0x00000000U);
+ WRITE_REG(RTCx->ALRMBR, 0x00000000U);
+ WRITE_REG(RTCx->SHIFTR, 0x00000000U);
+ WRITE_REG(RTCx->CALR, 0x00000000U);
+ WRITE_REG(RTCx->ALRMASSR, 0x00000000U);
+ WRITE_REG(RTCx->ALRMBSSR, 0x00000000U);
+
+ /* Exit Initialization mode */
+ LL_RTC_DisableInitMode(RTCx);
+
+ /* Wait till the RTC RSF flag is set */
+ status = LL_RTC_WaitForSynchro(RTCx);
+ }
+
+ /* Enable the write protection for RTC registers */
+ LL_RTC_EnableWriteProtection(RTCx);
+
+ /* DeInitialization of the TAMP */
+ /* Reset TAMP CR1 and CR2 registers */
+ WRITE_REG(TAMP->CR1, 0x00000000U);
+ WRITE_REG(TAMP->CR2, 0x00000000U);
+#if defined (RTC_OTHER_SUPPORT)
+ WRITE_REG(TAMP->CR3, 0x00000000U);
+ WRITE_REG(TAMP->SECCFGR, 0x00000000U);
+ WRITE_REG(TAMP->PRIVCFGR, 0x00000000U);
+#endif /* RTC_OTHER_SUPPORT */
+ WRITE_REG(TAMP->FLTCR, 0x00000000U);
+#if defined (RTC_ACTIVE_TAMPER_SUPPORT)
+ WRITE_REG(TAMP->ATCR1, 0x00070000U);
+ WRITE_REG(TAMP->ATCR2, 0x00000000U);
+#endif /* RTC_ACTIVE_TAMPER_SUPPORT */
+ WRITE_REG(TAMP->IER, 0x00000000U);
+ WRITE_REG(TAMP->SCR, 0xFFFFFFFFU);
+ WRITE_REG(TAMP->ERCFGR, 0x00000000U);
+
+ return status;
+}
+
+/**
+ * @brief Initializes the RTC registers according to the specified parameters
+ * in RTC_InitStruct.
+ * @param RTCx RTC Instance
+ * @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure that contains
+ * the configuration information for the RTC peripheral.
+ * @note The RTC Prescaler register is write protected and can be written in
+ * initialization mode only.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC registers are initialized
+ * - ERROR: RTC registers are not initialized
+ */
+ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+ assert_param(IS_LL_RTC_HOURFORMAT(RTC_InitStruct->HourFormat));
+ assert_param(IS_LL_RTC_ASYNCH_PREDIV(RTC_InitStruct->AsynchPrescaler));
+ assert_param(IS_LL_RTC_SYNCH_PREDIV(RTC_InitStruct->SynchPrescaler));
+
+ /* Disable the write protection for RTC registers */
+ LL_RTC_DisableWriteProtection(RTCx);
+
+ /* Set Initialization mode */
+ if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+ {
+ /* Set Hour Format */
+ LL_RTC_SetHourFormat(RTCx, RTC_InitStruct->HourFormat);
+
+ /* Configure Synchronous and Asynchronous prescaler factor */
+ LL_RTC_SetSynchPrescaler(RTCx, RTC_InitStruct->SynchPrescaler);
+ LL_RTC_SetAsynchPrescaler(RTCx, RTC_InitStruct->AsynchPrescaler);
+
+ /* Exit Initialization mode */
+ LL_RTC_DisableInitMode(RTCx);
+
+ status = SUCCESS;
+ }
+ /* Enable the write protection for RTC registers */
+ LL_RTC_EnableWriteProtection(RTCx);
+
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_RTC_InitTypeDef field to default value.
+ * @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure which will be initialized.
+ * @retval None
+ */
+void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct)
+{
+ /* Set RTC_InitStruct fields to default values */
+ RTC_InitStruct->HourFormat = LL_RTC_HOURFORMAT_24HOUR;
+ RTC_InitStruct->AsynchPrescaler = RTC_ASYNCH_PRESC_DEFAULT;
+ RTC_InitStruct->SynchPrescaler = RTC_SYNCH_PRESC_DEFAULT;
+}
+
+/**
+ * @brief Set the RTC current time.
+ * @param RTCx RTC Instance
+ * @param RTC_Format This parameter can be one of the following values:
+ * @arg @ref LL_RTC_FORMAT_BIN
+ * @arg @ref LL_RTC_FORMAT_BCD
+ * @param RTC_TimeStruct pointer to a RTC_TimeTypeDef structure that contains
+ * the time configuration information for the RTC.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC Time register is configured
+ * - ERROR: RTC Time register is not configured
+ */
+ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+ assert_param(IS_LL_RTC_FORMAT(RTC_Format));
+
+ if (RTC_Format == LL_RTC_FORMAT_BIN)
+ {
+ if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+ {
+ assert_param(IS_LL_RTC_HOUR12(RTC_TimeStruct->Hours));
+ assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat));
+ }
+ else
+ {
+ RTC_TimeStruct->TimeFormat = 0x00U;
+ assert_param(IS_LL_RTC_HOUR24(RTC_TimeStruct->Hours));
+ }
+ assert_param(IS_LL_RTC_MINUTES(RTC_TimeStruct->Minutes));
+ assert_param(IS_LL_RTC_SECONDS(RTC_TimeStruct->Seconds));
+ }
+ else
+ {
+ if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+ {
+ assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
+ assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat));
+ }
+ else
+ {
+ RTC_TimeStruct->TimeFormat = 0x00U;
+ assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
+ }
+ assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes)));
+ assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds)));
+ }
+
+ /* Disable the write protection for RTC registers */
+ LL_RTC_DisableWriteProtection(RTCx);
+
+ /* Set Initialization mode */
+ if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+ {
+ /* Check the input parameters format */
+ if (RTC_Format != LL_RTC_FORMAT_BIN)
+ {
+ LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, RTC_TimeStruct->Hours,
+ RTC_TimeStruct->Minutes, RTC_TimeStruct->Seconds);
+ }
+ else
+ {
+ LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Hours),
+ __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Minutes),
+ __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Seconds));
+ }
+
+ /* Exit Initialization mode */
+ LL_RTC_DisableInitMode(RTCx);
+
+ /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+ if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
+ {
+ status = LL_RTC_WaitForSynchro(RTCx);
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ /* Enable the write protection for RTC registers */
+ LL_RTC_EnableWriteProtection(RTCx);
+
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
+ * @param RTC_TimeStruct pointer to a @ref LL_RTC_TimeTypeDef structure which will be initialized.
+ * @retval None
+ */
+void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct)
+{
+ /* Time = 00h:00min:00sec */
+ RTC_TimeStruct->TimeFormat = LL_RTC_TIME_FORMAT_AM_OR_24;
+ RTC_TimeStruct->Hours = 0U;
+ RTC_TimeStruct->Minutes = 0U;
+ RTC_TimeStruct->Seconds = 0U;
+}
+
+/**
+ * @brief Set the RTC current date.
+ * @param RTCx RTC Instance
+ * @param RTC_Format This parameter can be one of the following values:
+ * @arg @ref LL_RTC_FORMAT_BIN
+ * @arg @ref LL_RTC_FORMAT_BCD
+ * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains
+ * the date configuration information for the RTC.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC Day register is configured
+ * - ERROR: RTC Day register is not configured
+ */
+ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+ assert_param(IS_LL_RTC_FORMAT(RTC_Format));
+
+ if ((RTC_Format == LL_RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10U) == 0x10U))
+ {
+ RTC_DateStruct->Month = (uint8_t)((uint32_t) RTC_DateStruct->Month & (uint32_t)~(0x10U)) + 0x0AU;
+ }
+ if (RTC_Format == LL_RTC_FORMAT_BIN)
+ {
+ assert_param(IS_LL_RTC_YEAR(RTC_DateStruct->Year));
+ assert_param(IS_LL_RTC_DAY(RTC_DateStruct->Day));
+ }
+ else
+ {
+ assert_param(IS_LL_RTC_YEAR(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Year)));
+ assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Day)));
+ }
+
+ assert_param(IS_LL_RTC_MONTH(RTC_DateStruct->Month));
+ assert_param(IS_LL_RTC_WEEKDAY(RTC_DateStruct->WeekDay));
+
+ /* Disable the write protection for RTC registers */
+ LL_RTC_DisableWriteProtection(RTCx);
+
+ /* Set Initialization mode */
+ if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+ {
+ /* Check the input parameters format */
+ if (RTC_Format != LL_RTC_FORMAT_BIN)
+ {
+ LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, RTC_DateStruct->Day, RTC_DateStruct->Month, \
+ RTC_DateStruct->Year);
+ }
+ else
+ {
+ LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Day),
+ __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Month), \
+ __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Year));
+ }
+
+ /* Exit Initialization mode */
+ LL_RTC_DisableInitMode(RTCx);
+
+ /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+ if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
+ {
+ status = LL_RTC_WaitForSynchro(RTCx);
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ /* Enable the write protection for RTC registers */
+ LL_RTC_EnableWriteProtection(RTCx);
+
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)
+ * @param RTC_DateStruct pointer to a @ref LL_RTC_DateTypeDef structure which will be initialized.
+ * @retval None
+ */
+void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct)
+{
+ /* Monday, January 01 xx00 */
+ RTC_DateStruct->WeekDay = LL_RTC_WEEKDAY_MONDAY;
+ RTC_DateStruct->Day = 1U;
+ RTC_DateStruct->Month = LL_RTC_MONTH_JANUARY;
+ RTC_DateStruct->Year = 0U;
+}
+
+/**
+ * @brief Set the RTC Alarm A.
+ * @note The Alarm register can only be written when the corresponding Alarm
+ * is disabled (Use @ref LL_RTC_ALMA_Disable function).
+ * @param RTCx RTC Instance
+ * @param RTC_Format This parameter can be one of the following values:
+ * @arg @ref LL_RTC_FORMAT_BIN
+ * @arg @ref LL_RTC_FORMAT_BCD
+ * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
+ * contains the alarm configuration parameters.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ALARMA registers are configured
+ * - ERROR: ALARMA registers are not configured
+ */
+ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+ assert_param(IS_LL_RTC_FORMAT(RTC_Format));
+ assert_param(IS_LL_RTC_ALMA_MASK(RTC_AlarmStruct->AlarmMask));
+ assert_param(IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel));
+
+ if (RTC_Format == LL_RTC_FORMAT_BIN)
+ {
+ if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+ {
+ assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours));
+ assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
+ }
+ assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
+ assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
+
+ if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay));
+ }
+ else
+ {
+ assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay));
+ }
+ }
+ else
+ {
+ if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+ {
+ assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
+ assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
+ }
+
+ assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
+ assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
+
+ if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
+ }
+ else
+ {
+ assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
+ }
+ }
+
+ /* Disable the write protection for RTC registers */
+ LL_RTC_DisableWriteProtection(RTCx);
+
+ /* Select weekday selection */
+ if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
+ {
+ /* Set the date for ALARM */
+ LL_RTC_ALMA_DisableWeekday(RTCx);
+ if (RTC_Format != LL_RTC_FORMAT_BIN)
+ {
+ LL_RTC_ALMA_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
+ }
+ else
+ {
+ LL_RTC_ALMA_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay));
+ }
+ }
+ else
+ {
+ /* Set the week day for ALARM */
+ LL_RTC_ALMA_EnableWeekday(RTCx);
+ LL_RTC_ALMA_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
+ }
+
+ /* Configure the Alarm register */
+ if (RTC_Format != LL_RTC_FORMAT_BIN)
+ {
+ LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours,
+ RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds);
+ }
+ else
+ {
+ LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat,
+ __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours),
+ __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes),
+ __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds));
+ }
+ /* Set ALARM mask */
+ LL_RTC_ALMA_SetMask(RTCx, RTC_AlarmStruct->AlarmMask);
+
+ /* Enable the write protection for RTC registers */
+ LL_RTC_EnableWriteProtection(RTCx);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set the RTC Alarm B.
+ * @note The Alarm register can only be written when the corresponding Alarm
+ * is disabled (@ref LL_RTC_ALMB_Disable function).
+ * @param RTCx RTC Instance
+ * @param RTC_Format This parameter can be one of the following values:
+ * @arg @ref LL_RTC_FORMAT_BIN
+ * @arg @ref LL_RTC_FORMAT_BCD
+ * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
+ * contains the alarm configuration parameters.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ALARMB registers are configured
+ * - ERROR: ALARMB registers are not configured
+ */
+ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+ assert_param(IS_LL_RTC_FORMAT(RTC_Format));
+ assert_param(IS_LL_RTC_ALMB_MASK(RTC_AlarmStruct->AlarmMask));
+ assert_param(IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel));
+
+ if (RTC_Format == LL_RTC_FORMAT_BIN)
+ {
+ if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+ {
+ assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours));
+ assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
+ }
+ assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
+ assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
+
+ if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay));
+ }
+ else
+ {
+ assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay));
+ }
+ }
+ else
+ {
+ if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+ {
+ assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
+ assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
+ }
+
+ assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
+ assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
+
+ if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
+ }
+ else
+ {
+ assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
+ }
+ }
+
+ /* Disable the write protection for RTC registers */
+ LL_RTC_DisableWriteProtection(RTCx);
+
+ /* Select weekday selection */
+ if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
+ {
+ /* Set the date for ALARM */
+ LL_RTC_ALMB_DisableWeekday(RTCx);
+ if (RTC_Format != LL_RTC_FORMAT_BIN)
+ {
+ LL_RTC_ALMB_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
+ }
+ else
+ {
+ LL_RTC_ALMB_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay));
+ }
+ }
+ else
+ {
+ /* Set the week day for ALARM */
+ LL_RTC_ALMB_EnableWeekday(RTCx);
+ LL_RTC_ALMB_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
+ }
+
+ /* Configure the Alarm register */
+ if (RTC_Format != LL_RTC_FORMAT_BIN)
+ {
+ LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours,
+ RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds);
+ }
+ else
+ {
+ LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat,
+ __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours),
+ __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes),
+ __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds));
+ }
+ /* Set ALARM mask */
+ LL_RTC_ALMB_SetMask(RTCx, RTC_AlarmStruct->AlarmMask);
+
+ /* Enable the write protection for RTC registers */
+ LL_RTC_EnableWriteProtection(RTCx);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec /
+ * Day = 1st day of the month/Mask = all fields are masked).
+ * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
+ * @retval None
+ */
+void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
+{
+ /* Alarm Time Settings : Time = 00h:00mn:00sec */
+ RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMA_TIME_FORMAT_AM;
+ RTC_AlarmStruct->AlarmTime.Hours = 0U;
+ RTC_AlarmStruct->AlarmTime.Minutes = 0U;
+ RTC_AlarmStruct->AlarmTime.Seconds = 0U;
+
+ /* Alarm Day Settings : Day = 1st day of the month */
+ RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMA_DATEWEEKDAYSEL_DATE;
+ RTC_AlarmStruct->AlarmDateWeekDay = 1U;
+
+ /* Alarm Masks Settings : Mask = all fields are not masked */
+ RTC_AlarmStruct->AlarmMask = LL_RTC_ALMA_MASK_NONE;
+}
+
+/**
+ * @brief Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec /
+ * Day = 1st day of the month/Mask = all fields are masked).
+ * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
+ * @retval None
+ */
+void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
+{
+ /* Alarm Time Settings : Time = 00h:00mn:00sec */
+ RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMB_TIME_FORMAT_AM;
+ RTC_AlarmStruct->AlarmTime.Hours = 0U;
+ RTC_AlarmStruct->AlarmTime.Minutes = 0U;
+ RTC_AlarmStruct->AlarmTime.Seconds = 0U;
+
+ /* Alarm Day Settings : Day = 1st day of the month */
+ RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMB_DATEWEEKDAYSEL_DATE;
+ RTC_AlarmStruct->AlarmDateWeekDay = 1U;
+
+ /* Alarm Masks Settings : Mask = all fields are not masked */
+ RTC_AlarmStruct->AlarmMask = LL_RTC_ALMB_MASK_NONE;
+}
+
+/**
+ * @brief Enters the RTC Initialization mode.
+ * @note The RTC Initialization mode is write protected, use the
+ * @ref LL_RTC_DisableWriteProtection before calling this function.
+ * @param RTCx RTC Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC is in Init mode
+ * - ERROR: RTC is not in Init mode
+ */
+ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx)
+{
+ __IO uint32_t timeout = RTC_INITMODE_TIMEOUT;
+ ErrorStatus status = SUCCESS;
+ uint32_t tmp;
+
+ /* Check the parameter */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+ /* Check if the Initialization mode is set */
+ if (LL_RTC_IsActiveFlag_INIT(RTCx) == 0U)
+ {
+ /* Set the Initialization mode */
+ LL_RTC_EnableInitMode(RTCx);
+
+ /* Wait till RTC is in INIT state and if Time out is reached exit */
+ tmp = LL_RTC_IsActiveFlag_INIT(RTCx);
+ while ((timeout != 0U) && (tmp != 1U))
+ {
+ if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
+ {
+ timeout --;
+ }
+ tmp = LL_RTC_IsActiveFlag_INIT(RTCx);
+ if (timeout == 0U)
+ {
+ status = ERROR;
+ }
+ }
+ }
+ return status;
+}
+
+/**
+ * @brief Exit the RTC Initialization mode.
+ * @note When the initialization sequence is complete, the calendar restarts
+ * counting after 4 RTCCLK cycles.
+ * @note The RTC Initialization mode is write protected, use the
+ * @ref LL_RTC_DisableWriteProtection before calling this function.
+ * @param RTCx RTC Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC exited from in Init mode
+ * - ERROR: Not applicable
+ */
+ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx)
+{
+ /* Check the parameter */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+ /* Disable initialization mode */
+ LL_RTC_DisableInitMode(RTCx);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are
+ * synchronized with RTC APB clock.
+ * @note The RTC Resynchronization mode is write protected, use the
+ * @ref LL_RTC_DisableWriteProtection before calling this function.
+ * @note To read the calendar through the shadow registers after Calendar
+ * initialization, calendar update or after wakeup from low power modes
+ * the software must first clear the RSF flag.
+ * The software must then wait until it is set again before reading
+ * the calendar, which means that the calendar registers have been
+ * correctly copied into the RTC_TR and RTC_DR shadow registers.
+ * @param RTCx RTC Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC registers are synchronised
+ * - ERROR: RTC registers are not synchronised
+ */
+ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx)
+{
+ __IO uint32_t timeout = RTC_SYNCHRO_TIMEOUT;
+ ErrorStatus status = SUCCESS;
+ uint32_t tmp;
+
+ /* Check the parameter */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+ /* Clear RSF flag */
+ LL_RTC_ClearFlag_RS(RTCx);
+
+ /* Wait the registers to be synchronised */
+ tmp = LL_RTC_IsActiveFlag_RS(RTCx);
+ while ((timeout != 0U) && (tmp != 0U))
+ {
+ if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
+ {
+ timeout--;
+ }
+ tmp = LL_RTC_IsActiveFlag_RS(RTCx);
+ if (timeout == 0U)
+ {
+ status = ERROR;
+ }
+ }
+
+ if (status != ERROR)
+ {
+ timeout = RTC_SYNCHRO_TIMEOUT;
+ tmp = LL_RTC_IsActiveFlag_RS(RTCx);
+ while ((timeout != 0U) && (tmp != 1U))
+ {
+ if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
+ {
+ timeout--;
+ }
+ tmp = LL_RTC_IsActiveFlag_RS(RTCx);
+ if (timeout == 0U)
+ {
+ status = ERROR;
+ }
+ }
+ }
+
+ return (status);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(RTC) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_sdmmc.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_sdmmc.c
new file mode 100644
index 00000000..c5af48e3
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_sdmmc.c
@@ -0,0 +1,1854 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_sdmmc.c
+ * @author MCD Application Team
+ * @brief SDMMC Low Layer HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the SDMMC peripheral:
+ * + Initialization/de-initialization functions
+ * + I/O operation functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### SDMMC peripheral features #####
+ ==============================================================================
+ [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the AHB
+ peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDMMC cards and CE-ATA
+ devices.
+
+ [..] The SDMMC features include the following:
+ (+) Full compliance with MultiMediaCard System Specification Version 4.51. Card support
+ for three different databus modes: 1-bit (default), 4-bit and 8-bit.
+ (+) Full compatibility with previous versions of MultiMediaCards (backward compatibility).
+ (+) Full compliance with SD memory card specifications version 4.1.
+ (SDR104 SDMMC_CK speed limited to maximum allowed IO speed, SPI mode and
+ UHS-II mode not supported).
+ (+) Full compliance with SDIO card specification version 4.0. Card support
+ for two different databus modes: 1-bit (default) and 4-bit.
+ (SDR104 SDMMC_CK speed limited to maximum allowed IO speed, SPI mode and
+ UHS-II mode not supported).
+ (+) Data transfer up to 208 Mbyte/s for the 8 bit mode. (depending maximum allowed IO speed).
+ (+) Data and command output enable signals to control external bidirectional drivers
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This driver is a considered as a driver of service for external devices drivers
+ that interfaces with the SDMMC peripheral.
+ According to the device used (SD card/ MMC card / SDMMC card ...), a set of APIs
+ is used in the device's driver to perform SDMMC operations and functionalities.
+
+ This driver is almost transparent for the final user, it is only used to implement other
+ functionalities of the external device.
+
+ [..]
+ (+) The SDMMC clock is coming from output of PLL1_Q or PLL2_R.
+ Before start working with SDMMC peripheral make sure that the PLL is well configured.
+ The SDMMC peripheral uses two clock signals:
+ (++) PLL1_Q bus clock (default after reset)
+ (++) PLL2_R bus clock
+
+ (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDMMC
+ peripheral.
+
+ (+) Enable the Power ON State using the SDMMC_PowerState_ON(SDMMCx)
+ function and disable it using the function SDMMC_PowerState_OFF(SDMMCx).
+
+ (+) Enable/Disable the peripheral interrupts using the macros __SDMMC_ENABLE_IT(hSDMMC, IT)
+ and __SDMMC_DISABLE_IT(hSDMMC, IT) if you need to use interrupt mode.
+
+ (+) When using the DMA mode
+ (++) Configure the IDMA mode (Single buffer or double)
+ (++) Configure the buffer address
+ (++) Configure Data Path State Machine
+
+ (+) To control the CPSM (Command Path State Machine) and send
+ commands to the card use the SDMMC_SendCommand(SDMMCx),
+ SDMMC_GetCommandResponse() and SDMMC_GetResponse() functions. First, user has
+ to fill the command structure (pointer to SDMMC_CmdInitTypeDef) according
+ to the selected command to be sent.
+ The parameters that should be filled are:
+ (++) Command Argument
+ (++) Command Index
+ (++) Command Response type
+ (++) Command Wait
+ (++) CPSM Status (Enable or Disable).
+
+ -@@- To check if the command is well received, read the SDMMC_CMDRESP
+ register using the SDMMC_GetCommandResponse().
+ The SDMMC responses registers (SDMMC_RESP1 to SDMMC_RESP2), use the
+ SDMMC_GetResponse() function.
+
+ (+) To control the DPSM (Data Path State Machine) and send/receive
+ data to/from the card use the SDMMC_DataConfig(), SDMMC_GetDataCounter(),
+ SDMMC_ReadFIFO(), SDMMC_WriteFIFO() and SDMMC_GetFIFOCount() functions.
+
+ *** Read Operations ***
+ =======================
+ [..]
+ (#) First, user has to fill the data structure (pointer to
+ SDMMC_DataInitTypeDef) according to the selected data type to be received.
+ The parameters that should be filled are:
+ (++) Data TimeOut
+ (++) Data Length
+ (++) Data Block size
+ (++) Data Transfer direction: should be from card (To SDMMC)
+ (++) Data Transfer mode
+ (++) DPSM Status (Enable or Disable)
+
+ (#) Configure the SDMMC resources to receive the data from the card
+ according to selected transfer mode (Refer to Step 8, 9 and 10).
+
+ (#) Send the selected Read command (refer to step 11).
+
+ (#) Use the SDMMC flags/interrupts to check the transfer status.
+
+ *** Write Operations ***
+ ========================
+ [..]
+ (#) First, user has to fill the data structure (pointer to
+ SDMMC_DataInitTypeDef) according to the selected data type to be received.
+ The parameters that should be filled are:
+ (++) Data TimeOut
+ (++) Data Length
+ (++) Data Block size
+ (++) Data Transfer direction: should be to card (To CARD)
+ (++) Data Transfer mode
+ (++) DPSM Status (Enable or Disable)
+
+ (#) Configure the SDMMC resources to send the data to the card according to
+ selected transfer mode.
+
+ (#) Send the selected Write command.
+
+ (#) Use the SDMMC flags/interrupts to check the transfer status.
+
+ *** Command management operations ***
+ =====================================
+ [..]
+ (#) The commands used for Read/Write/Erase operations are managed in
+ separate functions.
+ Each function allows to send the needed command with the related argument,
+ then check the response.
+ By the same approach, you could implement a command and check the response.
+
+ @endverbatim
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SDMMC_LL SDMMC Low Layer
+ * @brief Low layer module for SD
+ * @{
+ */
+
+#if defined (HAL_SD_MODULE_ENABLED) || defined (HAL_MMC_MODULE_ENABLED)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx);
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SDMMC_LL_Exported_Functions SDMMC Low Layer Exported Functions
+ * @{
+ */
+
+/** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization/de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the SDMMC according to the specified
+ * parameters in the SDMMC_InitTypeDef and create the associated handle.
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @param Init: SDMMC initialization structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_SDMMC_ALL_INSTANCE(SDMMCx));
+ assert_param(IS_SDMMC_CLOCK_EDGE(Init.ClockEdge));
+ assert_param(IS_SDMMC_CLOCK_POWER_SAVE(Init.ClockPowerSave));
+ assert_param(IS_SDMMC_BUS_WIDE(Init.BusWide));
+ assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));
+ assert_param(IS_SDMMC_CLKDIV(Init.ClockDiv));
+
+ /* Set SDMMC configuration parameters */
+ tmpreg |= (Init.ClockEdge | \
+ Init.ClockPowerSave | \
+ Init.BusWide | \
+ Init.HardwareFlowControl | \
+ Init.ClockDiv
+ );
+
+ /* Write to SDMMC CLKCR */
+ MODIFY_REG(SDMMCx->CLKCR, CLKCR_CLEAR_MASK, tmpreg);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SDMMC_LL_Group2 IO operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### I/O operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the SDMMC data
+ transfers.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Read data (word) from Rx FIFO in blocking mode (polling)
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx)
+{
+ /* Read data from Rx FIFO */
+ return (SDMMCx->FIFO);
+}
+
+/**
+ * @brief Write data (word) to Tx FIFO in blocking mode (polling)
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @param pWriteData: pointer to data to write
+ * @retval HAL status
+ */
+HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData)
+{
+ /* Write data to FIFO */
+ SDMMCx->FIFO = *pWriteData;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions
+ * @brief management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the SDMMC data
+ transfers.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set SDMMC Power state to ON.
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @retval HAL status
+ */
+HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx)
+{
+ /* Set power state to ON */
+ SDMMCx->POWER |= SDMMC_POWER_PWRCTRL;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set SDMMC Power state to Power-Cycle.
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @retval HAL status
+ */
+HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx)
+{
+ /* Set power state to Power Cycle*/
+ SDMMCx->POWER |= SDMMC_POWER_PWRCTRL_1;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set SDMMC Power state to OFF.
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @retval HAL status
+ */
+HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx)
+{
+ /* Set power state to OFF */
+ SDMMCx->POWER &= ~(SDMMC_POWER_PWRCTRL);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get SDMMC Power state.
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @retval Power status of the controller. The returned value can be one of the
+ * following values:
+ * - 0x00: Power OFF
+ * - 0x02: Power UP
+ * - 0x03: Power ON
+ */
+uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx)
+{
+ return (SDMMCx->POWER & SDMMC_POWER_PWRCTRL);
+}
+
+/**
+ * @brief Configure the SDMMC command path according to the specified parameters in
+ * SDMMC_CmdInitTypeDef structure and send the command
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @param Command: pointer to a SDMMC_CmdInitTypeDef structure that contains
+ * the configuration information for the SDMMC command
+ * @retval HAL status
+ */
+HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_SDMMC_CMD_INDEX(Command->CmdIndex));
+ assert_param(IS_SDMMC_RESPONSE(Command->Response));
+ assert_param(IS_SDMMC_WAIT(Command->WaitForInterrupt));
+ assert_param(IS_SDMMC_CPSM(Command->CPSM));
+
+ /* Set the SDMMC Argument value */
+ SDMMCx->ARG = Command->Argument;
+
+ /* Set SDMMC command parameters */
+ tmpreg |= (uint32_t)(Command->CmdIndex | \
+ Command->Response | \
+ Command->WaitForInterrupt | \
+ Command->CPSM);
+
+ /* Write to SDMMC CMD register */
+ MODIFY_REG(SDMMCx->CMD, CMD_CLEAR_MASK, tmpreg);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Return the command index of last command for which response received
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @retval Command index of the last command response received
+ */
+uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx)
+{
+ return (uint8_t)(SDMMCx->RESPCMD);
+}
+
+
+/**
+ * @brief Return the response received from the card for the last command
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @param Response: Specifies the SDMMC response register.
+ * This parameter can be one of the following values:
+ * @arg SDMMC_RESP1: Response Register 1
+ * @arg SDMMC_RESP2: Response Register 2
+ * @arg SDMMC_RESP3: Response Register 3
+ * @arg SDMMC_RESP4: Response Register 4
+ * @retval The Corresponding response register value
+ */
+uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response)
+{
+ uint32_t tmp;
+
+ /* Check the parameters */
+ assert_param(IS_SDMMC_RESP(Response));
+
+ /* Get the response */
+ tmp = (uint32_t)(&(SDMMCx->RESP1)) + Response;
+
+ return (*(__IO uint32_t *) tmp);
+}
+
+/**
+ * @brief Configure the SDMMC data path according to the specified
+ * parameters in the SDMMC_DataInitTypeDef.
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @param Data : pointer to a SDMMC_DataInitTypeDef structure
+ * that contains the configuration information for the SDMMC data.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_SDMMC_DATA_LENGTH(Data->DataLength));
+ assert_param(IS_SDMMC_BLOCK_SIZE(Data->DataBlockSize));
+ assert_param(IS_SDMMC_TRANSFER_DIR(Data->TransferDir));
+ assert_param(IS_SDMMC_TRANSFER_MODE(Data->TransferMode));
+ assert_param(IS_SDMMC_DPSM(Data->DPSM));
+
+ /* Set the SDMMC Data TimeOut value */
+ SDMMCx->DTIMER = Data->DataTimeOut;
+
+ /* Set the SDMMC DataLength value */
+ SDMMCx->DLEN = Data->DataLength;
+
+ /* Set the SDMMC data configuration parameters */
+ tmpreg |= (uint32_t)(Data->DataBlockSize | \
+ Data->TransferDir | \
+ Data->TransferMode | \
+ Data->DPSM);
+
+ /* Write to SDMMC DCTRL */
+ MODIFY_REG(SDMMCx->DCTRL, DCTRL_CLEAR_MASK, tmpreg);
+
+ return HAL_OK;
+
+}
+
+/**
+ * @brief Returns number of remaining data bytes to be transferred.
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @retval Number of remaining data bytes to be transferred
+ */
+uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx)
+{
+ return (SDMMCx->DCOUNT);
+}
+
+/**
+ * @brief Get the FIFO data
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @retval Data received
+ */
+uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx)
+{
+ return (SDMMCx->FIFO);
+}
+
+/**
+ * @brief Sets one of the two options of inserting read wait interval.
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMC_ReadWaitMode: SDMMC Read Wait operation mode.
+ * This parameter can be:
+ * @arg SDMMC_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK
+ * @arg SDMMC_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2
+ * @retval None
+ */
+HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode)
+{
+ /* Check the parameters */
+ assert_param(IS_SDMMC_READWAIT_MODE(SDMMC_ReadWaitMode));
+
+ /* Set SDMMC read wait mode */
+ MODIFY_REG(SDMMCx->DCTRL, SDMMC_DCTRL_RWMOD, SDMMC_ReadWaitMode);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_SDMMC_LL_Group4 Command management functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Commands management functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the needed commands.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Send the Data Block Length command and check the response
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize)
+{
+ SDMMC_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate;
+
+ /* Set Block Size for Card */
+ sdmmc_cmdinit.Argument = (uint32_t)BlockSize;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_BLOCKLEN;
+ sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_BLOCKLEN, SDMMC_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Read Single Block command and check the response
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd)
+{
+ SDMMC_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate;
+
+ /* Set Block Size for Card */
+ sdmmc_cmdinit.Argument = (uint32_t)ReadAdd;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_SINGLE_BLOCK;
+ sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_SINGLE_BLOCK, SDMMC_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Read Multi Block command and check the response
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd)
+{
+ SDMMC_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate;
+
+ /* Set Block Size for Card */
+ sdmmc_cmdinit.Argument = (uint32_t)ReadAdd;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_MULT_BLOCK;
+ sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_MULT_BLOCK, SDMMC_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Write Single Block command and check the response
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd)
+{
+ SDMMC_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate;
+
+ /* Set Block Size for Card */
+ sdmmc_cmdinit.Argument = (uint32_t)WriteAdd;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_SINGLE_BLOCK;
+ sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_SINGLE_BLOCK, SDMMC_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Write Multi Block command and check the response
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd)
+{
+ SDMMC_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate;
+
+ /* Set Block Size for Card */
+ sdmmc_cmdinit.Argument = (uint32_t)WriteAdd;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_MULT_BLOCK;
+ sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_MULT_BLOCK, SDMMC_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Start Address Erase command for SD and check the response
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd)
+{
+ SDMMC_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate;
+
+ /* Set Block Size for Card */
+ sdmmc_cmdinit.Argument = (uint32_t)StartAdd;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_ERASE_GRP_START;
+ sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_ERASE_GRP_START, SDMMC_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the End Address Erase command for SD and check the response
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd)
+{
+ SDMMC_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate;
+
+ /* Set Block Size for Card */
+ sdmmc_cmdinit.Argument = (uint32_t)EndAdd;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_ERASE_GRP_END;
+ sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_ERASE_GRP_END, SDMMC_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Start Address Erase command and check the response
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd)
+{
+ SDMMC_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate;
+
+ /* Set Block Size for Card */
+ sdmmc_cmdinit.Argument = (uint32_t)StartAdd;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE_GRP_START;
+ sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE_GRP_START, SDMMC_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the End Address Erase command and check the response
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd)
+{
+ SDMMC_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate;
+
+ /* Set Block Size for Card */
+ sdmmc_cmdinit.Argument = (uint32_t)EndAdd;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE_GRP_END;
+ sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE_GRP_END, SDMMC_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Erase command and check the response
+ * @param SDMMCx Pointer to SDMMC register base
+ * @param EraseType Type of erase to be performed
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx, uint32_t EraseType)
+{
+ SDMMC_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate;
+
+ /* Set Block Size for Card */
+ sdmmc_cmdinit.Argument = EraseType;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE;
+ sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE, SDMMC_MAXERASETIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Stop Transfer command and check the response.
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx)
+{
+ SDMMC_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate;
+
+ /* Send CMD12 STOP_TRANSMISSION */
+ sdmmc_cmdinit.Argument = 0U;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_STOP_TRANSMISSION;
+ sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
+
+ __SDMMC_CMDSTOP_ENABLE(SDMMCx);
+ __SDMMC_CMDTRANS_DISABLE(SDMMCx);
+
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_STOP_TRANSMISSION, SDMMC_STOPTRANSFERTIMEOUT);
+
+ __SDMMC_CMDSTOP_DISABLE(SDMMCx);
+
+ /* Ignore Address Out Of Range Error, Not relevant at end of memory */
+ if (errorstate == SDMMC_ERROR_ADDR_OUT_OF_RANGE)
+ {
+ errorstate = SDMMC_ERROR_NONE;
+ }
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Select Deselect command and check the response.
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @param addr: Address of the card to be selected
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint32_t Addr)
+{
+ SDMMC_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate;
+
+ /* Send CMD7 SDMMC_SEL_DESEL_CARD */
+ sdmmc_cmdinit.Argument = (uint32_t)Addr;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEL_DESEL_CARD;
+ sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEL_DESEL_CARD, SDMMC_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Go Idle State command and check the response.
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx)
+{
+ SDMMC_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate;
+
+ sdmmc_cmdinit.Argument = 0U;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_GO_IDLE_STATE;
+ sdmmc_cmdinit.Response = SDMMC_RESPONSE_NO;
+ sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdError(SDMMCx);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Operating Condition command and check the response.
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx)
+{
+ SDMMC_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate;
+
+ /* Send CMD8 to verify SD card interface operating condition */
+ /* Argument: - [31:12]: Reserved (shall be set to '0')
+ - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)
+ - [7:0]: Check Pattern (recommended 0xAA) */
+ /* CMD Response: R7 */
+ sdmmc_cmdinit.Argument = SDMMC_CHECK_PATTERN;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD;
+ sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp7(SDMMCx);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Application command to verify that that the next command
+ * is an application specific com-mand rather than a standard command
+ * and check the response.
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @param Argument: Command Argument
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+ SDMMC_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate;
+
+ sdmmc_cmdinit.Argument = (uint32_t)Argument;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_CMD;
+ sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ /* If there is a HAL_ERROR, it is a MMC card, else
+ it is a SD card: SD card 2.0 (voltage range mismatch)
+ or SD card 1.x */
+ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_APP_CMD, SDMMC_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the command asking the accessed card to send its operating
+ * condition register (OCR)
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @param Argument: Command Argument
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+ SDMMC_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate;
+
+ sdmmc_cmdinit.Argument = Argument;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_OP_COND;
+ sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp3(SDMMCx);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Bus Width command and check the response.
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @param BusWidth: BusWidth
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth)
+{
+ SDMMC_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate;
+
+ sdmmc_cmdinit.Argument = (uint32_t)BusWidth;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_SD_SET_BUSWIDTH;
+ sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_APP_SD_SET_BUSWIDTH, SDMMC_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Send SCR command and check the response.
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx)
+{
+ SDMMC_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate;
+
+ /* Send CMD51 SD_APP_SEND_SCR */
+ sdmmc_cmdinit.Argument = 0U;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_SEND_SCR;
+ sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_SEND_SCR, SDMMC_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Send CID command and check the response.
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx)
+{
+ SDMMC_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate;
+
+ /* Send CMD2 ALL_SEND_CID */
+ sdmmc_cmdinit.Argument = 0U;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ALL_SEND_CID;
+ sdmmc_cmdinit.Response = SDMMC_RESPONSE_LONG;
+ sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp2(SDMMCx);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Send CSD command and check the response.
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @param Argument: Command Argument
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+ SDMMC_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate;
+
+ /* Send CMD9 SEND_CSD */
+ sdmmc_cmdinit.Argument = Argument;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_CSD;
+ sdmmc_cmdinit.Response = SDMMC_RESPONSE_LONG;
+ sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp2(SDMMCx);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Send CSD command and check the response.
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @param pRCA: Card RCA
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA)
+{
+ SDMMC_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate;
+
+ /* Send CMD3 SD_CMD_SET_REL_ADDR */
+ sdmmc_cmdinit.Argument = 0U;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR;
+ sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp6(SDMMCx, SDMMC_CMD_SET_REL_ADDR, pRCA);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Set Relative Address command to MMC card (not SD card).
+ * @param SDMMCx Pointer to SDMMC register base
+ * @param RCA Card RCA
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdSetRelAddMmc(SDMMC_TypeDef *SDMMCx, uint16_t RCA)
+{
+ SDMMC_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate;
+
+ /* Send CMD3 SD_CMD_SET_REL_ADDR */
+ sdmmc_cmdinit.Argument = ((uint32_t)RCA << 16U);
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR;
+ sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_REL_ADDR, SDMMC_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Status command and check the response.
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @param Argument: Command Argument
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+ SDMMC_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate;
+
+ sdmmc_cmdinit.Argument = Argument;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_STATUS;
+ sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEND_STATUS, SDMMC_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Status register command and check the response.
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx)
+{
+ SDMMC_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate;
+
+ sdmmc_cmdinit.Argument = 0U;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_STATUS;
+ sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_STATUS, SDMMC_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Sends host capacity support information and activates the card's
+ * initialization process. Send SDMMC_CMD_SEND_OP_COND command
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @parame Argument: Argument used for the command
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+ SDMMC_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate;
+
+ sdmmc_cmdinit.Argument = Argument;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_OP_COND;
+ sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp3(SDMMCx);
+
+ return errorstate;
+}
+
+/**
+ * @brief Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH command
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @parame Argument: Argument used for the command
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+ SDMMC_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate;
+
+ /* Send CMD6 to activate SDR50 Mode and Power Limit 1.44W */
+ /* CMD Response: R1 */
+ sdmmc_cmdinit.Argument = Argument; /* SDMMC_SDR25_SWITCH_PATTERN;*/
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SWITCH;
+ sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_HS_SWITCH, SDMMC_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the command asking the accessed card to send its operating
+ * condition register (OCR)
+ * @param None
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx)
+{
+ SDMMC_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate;
+
+ sdmmc_cmdinit.Argument = 0x00000000;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_VOLTAGE_SWITCH;
+ sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_VOLTAGE_SWITCH, SDMMC_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Send EXT_CSD command and check the response.
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @param Argument: Command Argument
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+ SDMMC_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate;
+
+ /* Send CMD9 SEND_CSD */
+ sdmmc_cmdinit.Argument = Argument;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD;
+ sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_HS_SEND_EXT_CSD, SDMMC_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_SDMMC_LL_Group5 Responses management functions
+ * @brief Responses functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Responses management functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the needed responses.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Checks for error conditions for R1 response.
+ * @param hsd: SD handle
+ * @param SD_CMD: The sent command index
+ * @retval SD Card error state
+ */
+uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout)
+{
+ uint32_t response_r1;
+ uint32_t sta_reg;
+
+ /* 8 is the number of required instructions cycles for the below loop statement.
+ The Timeout is expressed in ms */
+ uint32_t count = Timeout * (SystemCoreClock / 8U / 1000U);
+
+ do
+ {
+ if (count-- == 0U)
+ {
+ return SDMMC_ERROR_TIMEOUT;
+ }
+ sta_reg = SDMMCx->STA;
+ } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT |
+ SDMMC_FLAG_BUSYD0END)) == 0U) || ((sta_reg & SDMMC_FLAG_CMDACT) != 0U));
+
+ if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+ {
+ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
+
+ return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+ }
+ else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
+ {
+ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
+
+ return SDMMC_ERROR_CMD_CRC_FAIL;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Clear all the static flags */
+ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
+
+ /* Check response received is of desired command */
+ if (SDMMC_GetCommandResponse(SDMMCx) != SD_CMD)
+ {
+ return SDMMC_ERROR_CMD_CRC_FAIL;
+ }
+
+ /* We have received response, retrieve it for analysis */
+ response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1);
+
+ if ((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO)
+ {
+ return SDMMC_ERROR_NONE;
+ }
+ else if ((response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE)
+ {
+ return SDMMC_ERROR_ADDR_OUT_OF_RANGE;
+ }
+ else if ((response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED)
+ {
+ return SDMMC_ERROR_ADDR_MISALIGNED;
+ }
+ else if ((response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR)
+ {
+ return SDMMC_ERROR_BLOCK_LEN_ERR;
+ }
+ else if ((response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR)
+ {
+ return SDMMC_ERROR_ERASE_SEQ_ERR;
+ }
+ else if ((response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM)
+ {
+ return SDMMC_ERROR_BAD_ERASE_PARAM;
+ }
+ else if ((response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION)
+ {
+ return SDMMC_ERROR_WRITE_PROT_VIOLATION;
+ }
+ else if ((response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED)
+ {
+ return SDMMC_ERROR_LOCK_UNLOCK_FAILED;
+ }
+ else if ((response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED)
+ {
+ return SDMMC_ERROR_COM_CRC_FAILED;
+ }
+ else if ((response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD)
+ {
+ return SDMMC_ERROR_ILLEGAL_CMD;
+ }
+ else if ((response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED)
+ {
+ return SDMMC_ERROR_CARD_ECC_FAILED;
+ }
+ else if ((response_r1 & SDMMC_OCR_CC_ERROR) == SDMMC_OCR_CC_ERROR)
+ {
+ return SDMMC_ERROR_CC_ERR;
+ }
+ else if ((response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN)
+ {
+ return SDMMC_ERROR_STREAM_READ_UNDERRUN;
+ }
+ else if ((response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN)
+ {
+ return SDMMC_ERROR_STREAM_WRITE_OVERRUN;
+ }
+ else if ((response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE)
+ {
+ return SDMMC_ERROR_CID_CSD_OVERWRITE;
+ }
+ else if ((response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP)
+ {
+ return SDMMC_ERROR_WP_ERASE_SKIP;
+ }
+ else if ((response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED)
+ {
+ return SDMMC_ERROR_CARD_ECC_DISABLED;
+ }
+ else if ((response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET)
+ {
+ return SDMMC_ERROR_ERASE_RESET;
+ }
+ else if ((response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR)
+ {
+ return SDMMC_ERROR_AKE_SEQ_ERR;
+ }
+ else
+ {
+ return SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+ }
+}
+
+/**
+ * @brief Checks for error conditions for R2 (CID or CSD) response.
+ * @param hsd: SD handle
+ * @retval SD Card error state
+ */
+uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx)
+{
+ uint32_t sta_reg;
+ /* 8 is the number of required instructions cycles for the below loop statement.
+ The SDMMC_CMDTIMEOUT is expressed in ms */
+ uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U);
+
+ do
+ {
+ if (count-- == 0U)
+ {
+ return SDMMC_ERROR_TIMEOUT;
+ }
+ sta_reg = SDMMCx->STA;
+ } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+ ((sta_reg & SDMMC_FLAG_CMDACT) != 0U));
+
+ if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+ {
+ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
+
+ return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+ }
+ else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
+ {
+ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
+
+ return SDMMC_ERROR_CMD_CRC_FAIL;
+ }
+ else
+ {
+ /* No error flag set */
+ /* Clear all the static flags */
+ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
+ }
+
+ return SDMMC_ERROR_NONE;
+}
+
+/**
+ * @brief Checks for error conditions for R3 (OCR) response.
+ * @param hsd: SD handle
+ * @retval SD Card error state
+ */
+uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx)
+{
+ uint32_t sta_reg;
+ /* 8 is the number of required instructions cycles for the below loop statement.
+ The SDMMC_CMDTIMEOUT is expressed in ms */
+ uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U);
+
+ do
+ {
+ if (count-- == 0U)
+ {
+ return SDMMC_ERROR_TIMEOUT;
+ }
+ sta_reg = SDMMCx->STA;
+ } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+ ((sta_reg & SDMMC_FLAG_CMDACT) != 0U));
+
+ if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+ {
+ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
+
+ return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+ }
+ else
+ {
+ /* Clear all the static flags */
+ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
+ }
+
+ return SDMMC_ERROR_NONE;
+}
+
+/**
+ * @brief Checks for error conditions for R6 (RCA) response.
+ * @param hsd: SD handle
+ * @param SD_CMD: The sent command index
+ * @param pRCA: Pointer to the variable that will contain the SD card relative
+ * address RCA
+ * @retval SD Card error state
+ */
+uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA)
+{
+ uint32_t response_r1;
+ uint32_t sta_reg;
+
+ /* 8 is the number of required instructions cycles for the below loop statement.
+ The SDMMC_CMDTIMEOUT is expressed in ms */
+ uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U);
+
+ do
+ {
+ if (count-- == 0U)
+ {
+ return SDMMC_ERROR_TIMEOUT;
+ }
+ sta_reg = SDMMCx->STA;
+ } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+ ((sta_reg & SDMMC_FLAG_CMDACT) != 0U));
+
+ if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+ {
+ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
+
+ return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+ }
+ else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
+ {
+ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
+
+ return SDMMC_ERROR_CMD_CRC_FAIL;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Check response received is of desired command */
+ if (SDMMC_GetCommandResponse(SDMMCx) != SD_CMD)
+ {
+ return SDMMC_ERROR_CMD_CRC_FAIL;
+ }
+
+ /* Clear all the static flags */
+ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
+
+ /* We have received response, retrieve it. */
+ response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1);
+
+ if ((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD |
+ SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO)
+ {
+ *pRCA = (uint16_t)(response_r1 >> 16);
+
+ return SDMMC_ERROR_NONE;
+ }
+ else if ((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD)
+ {
+ return SDMMC_ERROR_ILLEGAL_CMD;
+ }
+ else if ((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED)
+ {
+ return SDMMC_ERROR_COM_CRC_FAILED;
+ }
+ else
+ {
+ return SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+ }
+}
+
+/**
+ * @brief Checks for error conditions for R7 response.
+ * @param hsd: SD handle
+ * @retval SD Card error state
+ */
+uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx)
+{
+ uint32_t sta_reg;
+ /* 8 is the number of required instructions cycles for the below loop statement.
+ The SDMMC_CMDTIMEOUT is expressed in ms */
+ uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U);
+
+ do
+ {
+ if (count-- == 0U)
+ {
+ return SDMMC_ERROR_TIMEOUT;
+ }
+ sta_reg = SDMMCx->STA;
+ } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+ ((sta_reg & SDMMC_FLAG_CMDACT) != 0U));
+
+ if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+ {
+ /* Card is SD V2.0 compliant */
+ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
+
+ return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+ }
+
+ else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
+ {
+ /* Card is SD V2.0 compliant */
+ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
+
+ return SDMMC_ERROR_CMD_CRC_FAIL;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDREND))
+ {
+ /* Card is SD V2.0 compliant */
+ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CMDREND);
+ }
+
+ return SDMMC_ERROR_NONE;
+
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_SDMMC_LL_Group6 Linked List functions
+ * @brief Linked List management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Linked List management functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the needed functions.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Build new Linked List node.
+ * @param pNode: Pointer to new node to add.
+ * @param pNodeConf: Pointer to configuration parameters for new node to add.
+ * @retval Error status
+ */
+uint32_t SDMMC_DMALinkedList_BuildNode(SDMMC_DMALinkNodeTypeDef *pNode, SDMMC_DMALinkNodeConfTypeDef *pNodeConf)
+{
+
+ if ((pNode == NULL) || (pNodeConf == NULL))
+ {
+ return SDMMC_ERROR_INVALID_PARAMETER;
+ }
+ /* Configure the Link Node registers*/
+ pNode->IDMABASER = pNodeConf->BufferAddress;
+ pNode->IDMABSIZE = pNodeConf->BufferSize;
+ pNode->IDMALAR = SDMMC_IDMALAR_ULS | SDMMC_IDMALAR_ABR;
+
+ return SDMMC_ERROR_NONE;
+}
+
+/**
+ * @brief Insert new Linked List node.
+ * @param pLinkedList: Pointer to the linkedlist that contains transfer nodes
+ * @param pPrevNode: Pointer to previous node .
+ * @param pNewNode: Pointer to new node to add.
+ * @retval Error status
+ */
+uint32_t SDMMC_DMALinkedList_InsertNode(SDMMC_DMALinkedListTypeDef *pLinkedList, SDMMC_DMALinkNodeTypeDef *pPrevNode,
+ SDMMC_DMALinkNodeTypeDef *pNode)
+{
+ uint32_t link_list_offset;
+ uint32_t node_address = (uint32_t) pNode;
+
+ /* First Node */
+ if (pLinkedList->NodesCounter == 0U)
+ {
+
+ pLinkedList->pHeadNode = pNode;
+ pLinkedList->pTailNode = pNode;
+ pLinkedList->NodesCounter = 1U;
+
+ }
+ else if (pPrevNode == pLinkedList->pTailNode)
+ {
+ if (pNode <= pLinkedList->pHeadNode)
+ {
+ /* Node Address should greater than Head Node Address*/
+ return SDMMC_ERROR_INVALID_PARAMETER;
+ }
+
+ /*Last Node, no next node */
+ MODIFY_REG(pPrevNode->IDMALAR, SDMMC_IDMALAR_ULA, 0U);
+
+ /*link Prev node with new one */
+ MODIFY_REG(pPrevNode->IDMALAR, SDMMC_IDMALAR_ULA, SDMMC_IDMALAR_ULA);
+ MODIFY_REG(pPrevNode->IDMALAR, SDMMC_IDMALAR_IDMALA, (node_address - (uint32_t)pLinkedList->pHeadNode));
+
+ pLinkedList->NodesCounter ++;
+ pLinkedList->pTailNode = pNode;
+
+ }
+ else
+ {
+
+ if (pNode <= pLinkedList->pHeadNode)
+ {
+ /* Node Address should greater than Head Node Address*/
+ return SDMMC_ERROR_INVALID_PARAMETER;
+ }
+
+ /*link New node with Next one */
+ link_list_offset = pNode->IDMALAR;
+ MODIFY_REG(pPrevNode->IDMALAR, SDMMC_IDMALAR_IDMALA, link_list_offset);
+
+ /*link Prev node with new one */
+ MODIFY_REG(pPrevNode->IDMALAR, SDMMC_IDMALAR_ULA, SDMMC_IDMALAR_ULA);
+ MODIFY_REG(pPrevNode->IDMALAR, SDMMC_IDMALAR_IDMALA, (node_address - (uint32_t)pLinkedList->pHeadNode));
+
+ pLinkedList->NodesCounter ++;
+
+ }
+ return SDMMC_ERROR_NONE;
+}
+
+/**
+ * @brief Remove node from the Linked List.
+ * @param pLinkedList: Pointer to the linkedlist that contains transfer nodes
+ * @param pNode: Pointer to new node to add.
+ * @retval Error status
+ */
+uint32_t SDMMC_DMALinkedList_RemoveNode(SDMMC_DMALinkedListTypeDef *pLinkedList, SDMMC_DMALinkNodeTypeDef *pNode)
+{
+ uint32_t count = 0U;
+ uint32_t linked_list_offset;
+ SDMMC_DMALinkNodeTypeDef *prev_node, * curr_node ;
+
+ /* First Node */
+ if (pLinkedList->NodesCounter == 0U)
+ {
+
+ return SDMMC_ERROR_INVALID_PARAMETER;
+ }
+ else
+ {
+ curr_node = pLinkedList->pHeadNode;
+ while ((curr_node != pNode) && (count <= pLinkedList->NodesCounter))
+ {
+ prev_node = curr_node;
+ curr_node = (SDMMC_DMALinkNodeTypeDef *)((prev_node->IDMALAR & SDMMC_IDMALAR_IDMALA) +
+ (uint32_t)pLinkedList->pHeadNode);
+ count++;
+ }
+
+ if ((count == 0U) || (count > pLinkedList->NodesCounter))
+ {
+ /* Node not found in the linked list */
+ return SDMMC_ERROR_INVALID_PARAMETER;
+ }
+
+ pLinkedList->NodesCounter--;
+
+ if (pLinkedList->NodesCounter == 0U)
+ {
+ pLinkedList->pHeadNode = 0U;
+ pLinkedList->pTailNode = 0U;
+ }
+ else
+ {
+ /*link prev node with next one */
+ linked_list_offset = curr_node->IDMALAR;
+ MODIFY_REG(prev_node->IDMALAR, SDMMC_IDMALAR_IDMALA, linked_list_offset);
+ /* Configure the new Link Node registers*/
+ pNode->IDMALAR |= linked_list_offset;
+
+ pLinkedList->pTailNode = prev_node;
+ }
+ }
+ return SDMMC_ERROR_NONE;
+}
+
+/**
+ * @brief Lock Linked List Node
+ * @param pNode: Pointer to node to lock.
+ * @retval Error status
+
+ */
+uint32_t SDMMC_DMALinkedList_LockNode(SDMMC_DMALinkNodeTypeDef *pNode)
+{
+
+ if (pNode == NULL)
+ {
+ return SDMMC_ERROR_INVALID_PARAMETER;
+ }
+
+ MODIFY_REG(pNode->IDMALAR, SDMMC_IDMALAR_ABR, 0U);
+
+ return SDMMC_ERROR_NONE;
+}
+
+/**
+ * @brief Unlock Linked List Node
+ * @param pNode: Pointer to node to unlock.
+ * @retval Error status
+
+ */
+uint32_t SDMMC_DMALinkedList_UnlockNode(SDMMC_DMALinkNodeTypeDef *pNode)
+{
+
+ if (pNode == NULL)
+ {
+ return SDMMC_ERROR_INVALID_PARAMETER;
+ }
+
+ MODIFY_REG(pNode->IDMALAR, SDMMC_IDMALAR_ABR, SDMMC_IDMALAR_ABR);
+
+ return SDMMC_ERROR_NONE;
+}
+
+/**
+ * @brief Enable Linked List circular mode
+ * @param pLinkedList: Pointer to the linkedlist that contains transfer nodes
+ * @retval Error status
+
+ */
+uint32_t SDMMC_DMALinkedList_EnableCircularMode(SDMMC_DMALinkedListTypeDef *pLinkedList)
+{
+
+ if (pLinkedList == NULL)
+ {
+ return SDMMC_ERROR_INVALID_PARAMETER;
+ }
+
+ MODIFY_REG(pLinkedList->pTailNode->IDMALAR, SDMMC_IDMALAR_ULA | SDMMC_IDMALAR_IDMALA, SDMMC_IDMALAR_ULA);
+
+ return SDMMC_ERROR_NONE;
+}
+
+/**
+ * @brief Disable DMA Linked List Circular mode
+ * @param pLinkedList: Pointer to the linkedlist that contains transfer nodes
+ * @retval Error status
+ */
+uint32_t SDMMC_DMALinkedList_DisableCircularMode(SDMMC_DMALinkedListTypeDef *pLinkedList)
+{
+
+ if (pLinkedList == NULL)
+ {
+ return SDMMC_ERROR_INVALID_PARAMETER;
+ }
+
+ MODIFY_REG(pLinkedList->pTailNode->IDMALAR, SDMMC_IDMALAR_ULA, 0U);
+
+ return SDMMC_ERROR_NONE;
+}
+
+/**
+ * @}
+ */
+
+
+/* Private function ----------------------------------------------------------*/
+/** @addtogroup SD_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Checks for error conditions for CMD0.
+ * @param hsd: SD handle
+ * @retval SD Card error state
+ */
+static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx)
+{
+ /* 8 is the number of required instructions cycles for the below loop statement.
+ The SDMMC_CMDTIMEOUT is expressed in ms */
+ uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U);
+
+ do
+ {
+ if (count-- == 0U)
+ {
+ return SDMMC_ERROR_TIMEOUT;
+ }
+
+ } while (!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDSENT));
+
+ /* Clear all the static flags */
+ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
+
+ return SDMMC_ERROR_NONE;
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_SD_MODULE_ENABLED || HAL_MMC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_spi.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_spi.c
new file mode 100644
index 00000000..f2aba96a
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_spi.c
@@ -0,0 +1,460 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_spi.c
+ * @author MCD Application Team
+ * @brief SPI LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_ll_spi.h"
+#include "stm32u5xx_ll_bus.h"
+#include "stm32u5xx_ll_rcc.h"
+#ifdef GENERATOR_I2S_PRESENT
+#include "stm32u5xx_ll_rcc.h"
+#endif /* GENERATOR_I2S_PRESENT*/
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined(SPI1) || defined(SPI2) || defined(SPI3)
+
+/** @addtogroup SPI_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup SPI_LL_Private_Macros
+ * @{
+ */
+
+#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) || \
+ ((__VALUE__) == LL_SPI_MODE_SLAVE))
+
+#define IS_LL_SPI_SS_IDLENESS(__VALUE__) (((__VALUE__) == LL_SPI_SS_IDLENESS_00CYCLE) || \
+ ((__VALUE__) == LL_SPI_SS_IDLENESS_01CYCLE) || \
+ ((__VALUE__) == LL_SPI_SS_IDLENESS_02CYCLE) || \
+ ((__VALUE__) == LL_SPI_SS_IDLENESS_03CYCLE) || \
+ ((__VALUE__) == LL_SPI_SS_IDLENESS_04CYCLE) || \
+ ((__VALUE__) == LL_SPI_SS_IDLENESS_05CYCLE) || \
+ ((__VALUE__) == LL_SPI_SS_IDLENESS_06CYCLE) || \
+ ((__VALUE__) == LL_SPI_SS_IDLENESS_07CYCLE) || \
+ ((__VALUE__) == LL_SPI_SS_IDLENESS_08CYCLE) || \
+ ((__VALUE__) == LL_SPI_SS_IDLENESS_09CYCLE) || \
+ ((__VALUE__) == LL_SPI_SS_IDLENESS_10CYCLE) || \
+ ((__VALUE__) == LL_SPI_SS_IDLENESS_11CYCLE) || \
+ ((__VALUE__) == LL_SPI_SS_IDLENESS_12CYCLE) || \
+ ((__VALUE__) == LL_SPI_SS_IDLENESS_13CYCLE) || \
+ ((__VALUE__) == LL_SPI_SS_IDLENESS_14CYCLE) || \
+ ((__VALUE__) == LL_SPI_SS_IDLENESS_15CYCLE))
+
+#define IS_LL_SPI_ID_IDLENESS(__VALUE__) (((__VALUE__) == LL_SPI_ID_IDLENESS_00CYCLE) || \
+ ((__VALUE__) == LL_SPI_ID_IDLENESS_01CYCLE) || \
+ ((__VALUE__) == LL_SPI_ID_IDLENESS_02CYCLE) || \
+ ((__VALUE__) == LL_SPI_ID_IDLENESS_03CYCLE) || \
+ ((__VALUE__) == LL_SPI_ID_IDLENESS_04CYCLE) || \
+ ((__VALUE__) == LL_SPI_ID_IDLENESS_05CYCLE) || \
+ ((__VALUE__) == LL_SPI_ID_IDLENESS_06CYCLE) || \
+ ((__VALUE__) == LL_SPI_ID_IDLENESS_07CYCLE) || \
+ ((__VALUE__) == LL_SPI_ID_IDLENESS_08CYCLE) || \
+ ((__VALUE__) == LL_SPI_ID_IDLENESS_09CYCLE) || \
+ ((__VALUE__) == LL_SPI_ID_IDLENESS_10CYCLE) || \
+ ((__VALUE__) == LL_SPI_ID_IDLENESS_11CYCLE) || \
+ ((__VALUE__) == LL_SPI_ID_IDLENESS_12CYCLE) || \
+ ((__VALUE__) == LL_SPI_ID_IDLENESS_13CYCLE) || \
+ ((__VALUE__) == LL_SPI_ID_IDLENESS_14CYCLE) || \
+ ((__VALUE__) == LL_SPI_ID_IDLENESS_15CYCLE))
+
+#define IS_LL_SPI_TXCRCINIT_PATTERN(__VALUE__) (((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN) || \
+ ((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ONES_PATTERN))
+
+#define IS_LL_SPI_RXCRCINIT_PATTERN(__VALUE__) (((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN) || \
+ ((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ONES_PATTERN))
+
+#define IS_LL_SPI_UDR_CONFIG_REGISTER(__VALUE__) (((__VALUE__) == LL_SPI_UDR_CONFIG_REGISTER_PATTERN) || \
+ ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_RECEIVED) || \
+ ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_TRANSMITTED))
+
+#define IS_LL_SPI_UDR_DETECT_BEGIN_DATA(__VALUE__) (((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME) || \
+ ((__VALUE__) == LL_SPI_UDR_DETECT_END_DATA_FRAME) || \
+ ((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS))
+
+#define IS_LL_SPI_PROTOCOL(__VALUE__) (((__VALUE__) == LL_SPI_PROTOCOL_MOTOROLA) || \
+ ((__VALUE__) == LL_SPI_PROTOCOL_TI))
+
+#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) || \
+ ((__VALUE__) == LL_SPI_PHASE_2EDGE))
+
+#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) || \
+ ((__VALUE__) == LL_SPI_POLARITY_HIGH))
+
+#define IS_LL_SPI_BAUDRATEPRESCALER(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_BYPASS) || \
+ ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) || \
+ ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) || \
+ ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) || \
+ ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) || \
+ ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) || \
+ ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) || \
+ ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) || \
+ ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
+
+#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) || \
+ ((__VALUE__) == LL_SPI_MSB_FIRST))
+
+#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) || \
+ ((__VALUE__) == LL_SPI_SIMPLEX_TX) || \
+ ((__VALUE__) == LL_SPI_SIMPLEX_RX) || \
+ ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) || \
+ ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
+
+#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_17BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_18BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_19BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_20BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_21BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_22BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_23BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_24BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_25BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_26BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_27BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_28BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_29BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_30BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_31BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_32BIT))
+
+#define IS_LL_SPI_FIFO_TH(__VALUE__) (((__VALUE__) == LL_SPI_FIFO_TH_01DATA) || \
+ ((__VALUE__) == LL_SPI_FIFO_TH_02DATA) || \
+ ((__VALUE__) == LL_SPI_FIFO_TH_03DATA) || \
+ ((__VALUE__) == LL_SPI_FIFO_TH_04DATA) || \
+ ((__VALUE__) == LL_SPI_FIFO_TH_05DATA) || \
+ ((__VALUE__) == LL_SPI_FIFO_TH_06DATA) || \
+ ((__VALUE__) == LL_SPI_FIFO_TH_07DATA) || \
+ ((__VALUE__) == LL_SPI_FIFO_TH_08DATA) || \
+ ((__VALUE__) == LL_SPI_FIFO_TH_09DATA) || \
+ ((__VALUE__) == LL_SPI_FIFO_TH_10DATA) || \
+ ((__VALUE__) == LL_SPI_FIFO_TH_11DATA) || \
+ ((__VALUE__) == LL_SPI_FIFO_TH_12DATA) || \
+ ((__VALUE__) == LL_SPI_FIFO_TH_13DATA) || \
+ ((__VALUE__) == LL_SPI_FIFO_TH_14DATA) || \
+ ((__VALUE__) == LL_SPI_FIFO_TH_15DATA) || \
+ ((__VALUE__) == LL_SPI_FIFO_TH_16DATA))
+
+#define IS_LL_SPI_CRC(__VALUE__) (((__VALUE__) == LL_SPI_CRC_4BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_5BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_6BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_7BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_8BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_9BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_10BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_11BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_12BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_13BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_14BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_15BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_16BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_17BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_18BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_19BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_20BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_21BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_22BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_23BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_24BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_25BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_26BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_27BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_28BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_29BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_30BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_31BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_32BIT))
+
+#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) || \
+ ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) || \
+ ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
+
+#define IS_LL_SPI_RX_FIFO(__VALUE__) (((__VALUE__) == LL_SPI_RX_FIFO_0PACKET) || \
+ ((__VALUE__) == LL_SPI_RX_FIFO_1PACKET) || \
+ ((__VALUE__) == LL_SPI_RX_FIFO_2PACKET) || \
+ ((__VALUE__) == LL_SPI_RX_FIFO_3PACKET))
+
+#define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) || \
+ ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
+
+#define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1UL)
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPI_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup SPI_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the SPI registers to their default reset values.
+ * @param SPIx SPI Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: SPI registers are de-initialized
+ * - ERROR: SPI registers are not de-initialized
+ */
+ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_INSTANCE(SPIx));
+
+#if defined(SPI1)
+ if (SPIx == SPI1)
+ {
+ /* Force reset of SPI clock */
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
+
+ /* Release reset of SPI clock */
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
+
+ /* Update the return status */
+ status = SUCCESS;
+ }
+#endif /* SPI1 */
+#if defined(SPI2)
+ if (SPIx == SPI2)
+ {
+ /* Force reset of SPI clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
+
+ /* Release reset of SPI clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
+
+ /* Update the return status */
+ status = SUCCESS;
+ }
+#endif /* SPI2 */
+#if defined(SPI3)
+ if (SPIx == SPI3)
+ {
+ /* Force reset of SPI clock */
+ LL_APB3_GRP1_ForceReset(LL_APB3_GRP1_PERIPH_SPI3);
+
+ /* Release reset of SPI clock */
+ LL_APB3_GRP1_ReleaseReset(LL_APB3_GRP1_PERIPH_SPI3);
+
+ /* Update the return status */
+ status = SUCCESS;
+ }
+#endif /* SPI3 */
+#if defined(SPI4)
+ if (SPIx == SPI4)
+ {
+ /* Force reset of SPI clock */
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4);
+
+ /* Release reset of SPI clock */
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4);
+
+ /* Update the return status */
+ status = SUCCESS;
+ }
+#endif /* SPI4 */
+#if defined(SPI5)
+ if (SPIx == SPI5)
+ {
+ /* Force reset of SPI clock */
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI5);
+
+ /* Release reset of SPI clock */
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI5);
+
+ /* Update the return status */
+ status = SUCCESS;
+ }
+#endif /* SPI5 */
+#if defined(SPI6)
+ if (SPIx == SPI6)
+ {
+ /* Force reset of SPI clock */
+ LL_APB5_GRP1_ForceReset(LL_APB5_GRP1_PERIPH_SPI6);
+
+ /* Release reset of SPI clock */
+ LL_APB5_GRP1_ReleaseReset(LL_APB5_GRP1_PERIPH_SPI6);
+
+ /* Update the return status */
+ status = SUCCESS;
+ }
+#endif /* SPI6 */
+
+ return status;
+}
+
+/**
+ * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
+ * @note As some bits in SPI configuration registers can only be written when the SPI is disabled
+ * (SPI_CR1_SPE bit =0), SPI IP should be in disabled state prior calling this function.
+ * Otherwise, ERROR result will be returned.
+ * @param SPIx SPI Instance
+ * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
+ */
+ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
+{
+ ErrorStatus status = ERROR;
+ uint32_t tmp_nss;
+ uint32_t tmp_mode;
+
+ /* Check the SPI Instance SPIx*/
+ assert_param(IS_SPI_ALL_INSTANCE(SPIx));
+
+ /* Check the SPI parameters from SPI_InitStruct*/
+ assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
+ assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
+ assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
+ assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
+ assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
+ assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
+ assert_param(IS_LL_SPI_BAUDRATEPRESCALER(SPI_InitStruct->BaudRate));
+ assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
+ assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
+
+ /* Check the SPI instance is not enabled */
+ if (LL_SPI_IsEnabled(SPIx) == 0x00000000UL)
+ {
+ /*---------------------------- SPIx CFG1 Configuration ------------------------
+ * Configure SPIx CFG1 with parameters:
+ * - Master Baud Rate : SPI_CFG1_MBR[2:0] bits & SPI_CFG1_BPASS bit
+ * - CRC Computation Enable : SPI_CFG1_CRCEN bit
+ * - Length of data frame : SPI_CFG1_DSIZE[4:0] bits
+ */
+ MODIFY_REG(SPIx->CFG1, SPI_CFG1_BPASS | SPI_CFG1_MBR | SPI_CFG1_CRCEN | SPI_CFG1_DSIZE,
+ SPI_InitStruct->BaudRate | SPI_InitStruct->CRCCalculation | SPI_InitStruct->DataWidth);
+
+ tmp_nss = SPI_InitStruct->NSS;
+ tmp_mode = SPI_InitStruct->Mode;
+
+ /* Checks to setup Internal SS signal level and avoid a MODF Error */
+ if ((LL_SPI_GetNSSPolarity(SPIx) == LL_SPI_NSS_POLARITY_LOW) && (tmp_nss == LL_SPI_NSS_SOFT) &&
+ (tmp_mode == LL_SPI_MODE_MASTER))
+ {
+ LL_SPI_SetInternalSSLevel(SPIx, LL_SPI_SS_LEVEL_HIGH);
+ }
+
+ /*---------------------------- SPIx CFG2 Configuration ------------------------
+ * Configure SPIx CFG2 with parameters:
+ * - NSS management : SPI_CFG2_SSM, SPI_CFG2_SSOE bits
+ * - ClockPolarity : SPI_CFG2_CPOL bit
+ * - ClockPhase : SPI_CFG2_CPHA bit
+ * - BitOrder : SPI_CFG2_LSBFRST bit
+ * - Master/Slave Mode : SPI_CFG2_MASTER bit
+ * - SPI Mode : SPI_CFG2_COMM[1:0] bits
+ */
+ MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE |
+ SPI_CFG2_CPOL | SPI_CFG2_CPHA |
+ SPI_CFG2_LSBFRST | SPI_CFG2_MASTER | SPI_CFG2_COMM,
+ SPI_InitStruct->NSS | SPI_InitStruct->ClockPolarity |
+ SPI_InitStruct->ClockPhase | SPI_InitStruct->BitOrder |
+ SPI_InitStruct->Mode | (SPI_InitStruct->TransferDirection & SPI_CFG2_COMM));
+
+ /*---------------------------- SPIx CR1 Configuration ------------------------
+ * Configure SPIx CR1 with parameter:
+ * - Half Duplex Direction : SPI_CR1_HDDIR bit
+ */
+ MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, SPI_InitStruct->TransferDirection & SPI_CR1_HDDIR);
+
+ /*---------------------------- SPIx CRCPOLY Configuration ----------------------
+ * Configure SPIx CRCPOLY with parameter:
+ * - CRCPoly : CRCPOLY[31:0] bits
+ */
+ if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
+ {
+ assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
+ LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
+ }
+
+
+ status = SUCCESS;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_SPI_InitTypeDef field to default value.
+ * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
+{
+ /* Set SPI_InitStruct fields to default values */
+ SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
+ SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
+ SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
+ SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
+ SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
+ SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
+ SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
+ SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
+ SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
+ SPI_InitStruct->CRCPoly = 7UL;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(SPI1) || defined(SPI2) || defined(SPI3) */
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_tim.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_tim.c
new file mode 100644
index 00000000..677bef6b
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_tim.c
@@ -0,0 +1,1388 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_tim.c
+ * @author MCD Application Team
+ * @brief TIM LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_ll_tim.h"
+#include "stm32u5xx_ll_bus.h"
+
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined (TIM1) \
+ || defined (TIM2) \
+ || defined (TIM3) \
+ || defined (TIM4) \
+ || defined (TIM5) \
+ || defined (TIM6) \
+ || defined (TIM7) \
+ || defined (TIM8) \
+ || defined (TIM15) \
+ || defined (TIM16) \
+ || defined (TIM17) \
+ || defined (TIM20)
+
+/** @addtogroup TIM_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup TIM_LL_Private_Macros
+ * @{
+ */
+#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
+ || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
+ || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
+ || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
+ || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
+
+#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
+ || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
+ || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
+
+#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
+ || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
+ || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
+ || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
+ || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
+ || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
+ || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
+ || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
+ || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2) \
+ || ((__VALUE__) == LL_TIM_OCMODE_PULSE_ON_COMPARE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_DIRECTION_OUTPUT))
+
+#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
+ || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
+
+#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
+ || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
+
+#define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
+ || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
+
+#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
+ || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
+ || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
+
+#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
+ || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
+ || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
+ || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
+
+#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
+
+#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
+ || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
+ || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
+
+#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
+ || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
+ || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12) \
+ || ((__VALUE__) == LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2) \
+ || ((__VALUE__) == LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1) \
+ || ((__VALUE__) == LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2) \
+ || ((__VALUE__) == LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12) \
+ || ((__VALUE__) == LL_TIM_ENCODERMODE_X1_TI1) \
+ || ((__VALUE__) == LL_TIM_ENCODERMODE_X1_TI2))
+
+#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
+ || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
+
+#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
+ || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
+
+#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
+ || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
+
+#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
+ || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
+ || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
+ || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
+
+#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
+ || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
+
+#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
+ || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
+
+#define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
+
+#define IS_LL_TIM_BREAK_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_AFMODE_INPUT) \
+ || ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL))
+
+#define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
+ || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
+
+#define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
+ || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
+
+#define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
+
+#define IS_LL_TIM_BREAK2_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_AFMODE_INPUT) \
+ || ((__VALUE__) == LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL))
+
+#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
+ || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
+/**
+ * @}
+ */
+
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup TIM_LL_Private_Functions TIM Private Functions
+ * @{
+ */
+static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIM_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup TIM_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief Set TIMx registers to their reset values.
+ * @param TIMx Timer instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: invalid TIMx instance
+ */
+ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
+{
+ ErrorStatus result = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(TIMx));
+
+ if (TIMx == TIM1)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
+ }
+ else if (TIMx == TIM2)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
+ }
+ else if (TIMx == TIM3)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
+ }
+ else if (TIMx == TIM4)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
+ }
+ else if (TIMx == TIM5)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
+ }
+ else if (TIMx == TIM6)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
+ }
+ else if (TIMx == TIM7)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
+ }
+ else if (TIMx == TIM8)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
+ }
+ else if (TIMx == TIM15)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
+ }
+ else if (TIMx == TIM16)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
+ }
+ else if (TIMx == TIM17)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
+ }
+ else
+ {
+ result = ERROR;
+ }
+
+ return result;
+}
+
+/**
+ * @brief Set the fields of the time base unit configuration data structure
+ * to their default values.
+ * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
+ * @retval None
+ */
+void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
+{
+ /* Set the default configuration */
+ TIM_InitStruct->Prescaler = (uint16_t)0x0000;
+ TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
+ TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
+ TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
+ TIM_InitStruct->RepetitionCounter = 0x00000000U;
+}
+
+/**
+ * @brief Configure the TIMx time base unit.
+ * @param TIMx Timer Instance
+ * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
+ * (TIMx time base unit configuration data structure)
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
+{
+ uint32_t tmpcr1;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
+ assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
+
+ tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
+
+ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+ {
+ /* Select the Counter Mode */
+ MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
+ }
+
+ if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+ {
+ /* Set the clock division */
+ MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
+ }
+
+ /* Write to TIMx CR1 */
+ LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
+
+ /* Set the Autoreload value */
+ LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
+
+ /* Set the Prescaler value */
+ LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
+
+ if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
+ {
+ /* Set the Repetition Counter value */
+ LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
+ }
+
+ /* Generate an update event to reload the Prescaler
+ and the repetition counter value (if applicable) immediately */
+ LL_TIM_GenerateEvent_UPDATE(TIMx);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set the fields of the TIMx output channel configuration data
+ * structure to their default values.
+ * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
+ * (the output channel configuration data structure)
+ * @retval None
+ */
+void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
+{
+ /* Set the default configuration */
+ TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
+ TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
+ TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
+ TIM_OC_InitStruct->CompareValue = 0x00000000U;
+ TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
+ TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
+ TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
+ TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
+}
+
+/**
+ * @brief Configure the TIMx output channel.
+ * @param TIMx Timer Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
+ * data structure)
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx output channel is initialized
+ * - ERROR: TIMx output channel is not initialized
+ */
+ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
+{
+ ErrorStatus result = ERROR;
+
+ switch (Channel)
+ {
+ case LL_TIM_CHANNEL_CH1:
+ result = OC1Config(TIMx, TIM_OC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH2:
+ result = OC2Config(TIMx, TIM_OC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH3:
+ result = OC3Config(TIMx, TIM_OC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH4:
+ result = OC4Config(TIMx, TIM_OC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH5:
+ result = OC5Config(TIMx, TIM_OC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH6:
+ result = OC6Config(TIMx, TIM_OC_InitStruct);
+ break;
+ default:
+ break;
+ }
+
+ return result;
+}
+
+/**
+ * @brief Set the fields of the TIMx input channel configuration data
+ * structure to their default values.
+ * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
+ * data structure)
+ * @retval None
+ */
+void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+ /* Set the default configuration */
+ TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
+ TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+ TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
+ TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
+}
+
+/**
+ * @brief Configure the TIMx input channel.
+ * @param TIMx Timer Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
+ * structure)
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx output channel is initialized
+ * - ERROR: TIMx output channel is not initialized
+ */
+ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
+{
+ ErrorStatus result = ERROR;
+
+ switch (Channel)
+ {
+ case LL_TIM_CHANNEL_CH1:
+ result = IC1Config(TIMx, TIM_IC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH2:
+ result = IC2Config(TIMx, TIM_IC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH3:
+ result = IC3Config(TIMx, TIM_IC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH4:
+ result = IC4Config(TIMx, TIM_IC_InitStruct);
+ break;
+ default:
+ break;
+ }
+
+ return result;
+}
+
+/**
+ * @brief Fills each TIM_EncoderInitStruct field with its default value
+ * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
+ * configuration data structure)
+ * @retval None
+ */
+void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
+{
+ /* Set the default configuration */
+ TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
+ TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
+ TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+ TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
+ TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
+ TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
+ TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+ TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
+ TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
+}
+
+/**
+ * @brief Configure the encoder interface of the timer instance.
+ * @param TIMx Timer Instance
+ * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
+ * configuration data structure)
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
+{
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
+ assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
+ assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
+
+ /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
+ TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Configure TI1 */
+ tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
+
+ /* Configure TI2 */
+ tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
+
+ /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
+ tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
+ tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
+ tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+ /* Set encoder mode */
+ LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
+
+ /* Write to TIMx CCMR1 */
+ LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set the fields of the TIMx Hall sensor interface configuration data
+ * structure to their default values.
+ * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface
+ * configuration data structure)
+ * @retval None
+ */
+void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
+{
+ /* Set the default configuration */
+ TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
+ TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
+ TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
+ TIM_HallSensorInitStruct->CommutationDelay = 0U;
+}
+
+/**
+ * @brief Configure the Hall sensor interface of the timer instance.
+ * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
+ * to the TI1 input channel
+ * @note TIMx slave mode controller is configured in reset mode.
+ Selected internal trigger is TI1F_ED.
+ * @note Channel 1 is configured as input, IC1 is mapped on TRC.
+ * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
+ * between 2 changes on the inputs. It gives information about motor speed.
+ * @note Channel 2 is configured in output PWM 2 mode.
+ * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
+ * @note OC2REF is selected as trigger output on TRGO.
+ * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
+ * when TIMx operates in Hall sensor interface mode.
+ * @param TIMx Timer Instance
+ * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor
+ * interface configuration data structure)
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
+{
+ uint32_t tmpcr2;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
+ assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
+
+ /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
+ TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
+
+ /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
+ tmpcr2 |= TIM_CR2_TI1S;
+
+ /* OC2REF signal is used as trigger output (TRGO) */
+ tmpcr2 |= LL_TIM_TRGO_OC2REF;
+
+ /* Configure the slave mode controller */
+ tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
+ tmpsmcr |= LL_TIM_TS_TI1F_ED;
+ tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
+
+ /* Configure input channel 1 */
+ tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
+ tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
+ tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
+ tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
+
+ /* Configure input channel 2 */
+ tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
+ tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
+
+ /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
+ tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
+ tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+ /* Write to TIMx CR2 */
+ LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+ /* Write to TIMx SMCR */
+ LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
+
+ /* Write to TIMx CCMR1 */
+ LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ /* Write to TIMx CCR2 */
+ LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set the fields of the Break and Dead Time configuration data structure
+ * to their default values.
+ * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
+ * data structure)
+ * @retval None
+ */
+void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
+{
+ /* Set the default configuration */
+ TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
+ TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
+ TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
+ TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
+ TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
+ TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
+ TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;
+ TIM_BDTRInitStruct->BreakAFMode = LL_TIM_BREAK_AFMODE_INPUT;
+ TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE;
+ TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW;
+ TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1;
+ TIM_BDTRInitStruct->Break2AFMode = LL_TIM_BREAK2_AFMODE_INPUT;
+ TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
+}
+
+/**
+ * @brief Configure the Break and Dead Time feature of the timer instance.
+ * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
+ * and DTG[7:0] can be write-locked depending on the LOCK configuration, it
+ * can be necessary to configure all of them during the first write access to
+ * the TIMx_BDTR register.
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a second break input.
+ * @param TIMx Timer Instance
+ * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
+ * data structure)
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: Break and Dead Time is initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
+{
+ uint32_t tmpbdtr = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
+ assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
+ assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
+ assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
+ assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
+ assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
+
+ /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
+ the OSSI State, the dead time value and the Automatic Output Enable Bit */
+
+ /* Set the BDTR bits */
+ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
+ if (IS_TIM_ADVANCED_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
+ assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode);
+ }
+
+ if (IS_TIM_BKIN2_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
+ assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
+ assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
+ assert_param(IS_LL_TIM_BREAK2_AFMODE(TIM_BDTRInitStruct->Break2AFMode));
+
+ /* Set the BREAK2 input related BDTR bit-fields */
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, TIM_BDTRInitStruct->Break2AFMode);
+ }
+
+ /* Set TIMx_BDTR */
+ LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
+
+ return SUCCESS;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_LL_Private_Functions TIM Private Functions
+ * @brief Private functions
+ * @{
+ */
+/**
+ * @brief Configure the TIMx output channel 1.
+ * @param TIMx Timer Instance
+ * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+ /* Reset Capture/Compare selection Bits */
+ CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
+
+ /* Set the Output Compare Mode */
+ MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
+
+ /* Set the Output Compare Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
+
+ /* Set the Output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+ /* Set the complementary output Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
+
+ /* Set the complementary output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
+
+ /* Set the Output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
+
+ /* Set the complementary output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
+ }
+
+ /* Write to TIMx CR2 */
+ LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+ /* Write to TIMx CCMR1 */
+ LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+ /* Set the Capture Compare Register value */
+ LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx output channel 2.
+ * @param TIMx Timer Instance
+ * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+ /* Reset Capture/Compare selection Bits */
+ CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
+
+ /* Select the Output Compare Mode */
+ MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
+
+ /* Set the Output Compare Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
+
+ /* Set the Output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+ /* Set the complementary output Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
+
+ /* Set the complementary output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
+
+ /* Set the Output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
+
+ /* Set the complementary output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
+ }
+
+ /* Write to TIMx CR2 */
+ LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+ /* Write to TIMx CCMR1 */
+ LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+ /* Set the Capture Compare Register value */
+ LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx output channel 3.
+ * @param TIMx Timer Instance
+ * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+ uint32_t tmpccmr2;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC3_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+
+ /* Disable the Channel 3: Reset the CC3E Bit */
+ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
+
+ /* Reset Capture/Compare selection Bits */
+ CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
+
+ /* Select the Output Compare Mode */
+ MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
+
+ /* Set the Output Compare Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
+
+ /* Set the Output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+ /* Set the complementary output Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
+
+ /* Set the complementary output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
+
+ /* Set the Output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
+
+ /* Set the complementary output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
+ }
+
+ /* Write to TIMx CR2 */
+ LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+ /* Write to TIMx CCMR2 */
+ LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
+
+ /* Set the Capture Compare Register value */
+ LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx output channel 4.
+ * @param TIMx Timer Instance
+ * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+ uint32_t tmpccmr2;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC4_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
+
+ /* Reset Capture/Compare selection Bits */
+ CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
+
+ /* Select the Output Compare Mode */
+ MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
+
+ /* Set the Output Compare Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
+
+ /* Set the Output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+ /* Set the complementary output Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC4NP, TIM_OCInitStruct->OCNPolarity << 14U);
+
+ /* Set the complementary output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC4NE, TIM_OCInitStruct->OCNState << 14U);
+
+ /* Set the Output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
+
+ /* Set the complementary output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS4N, TIM_OCInitStruct->OCNIdleState << 7U);
+ }
+
+ /* Write to TIMx CR2 */
+ LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+ /* Write to TIMx CCMR2 */
+ LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
+
+ /* Set the Capture Compare Register value */
+ LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx output channel 5.
+ * @param TIMx Timer Instance
+ * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+ uint32_t tmpccmr3;
+ uint32_t tmpccer;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC5_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+
+ /* Disable the Channel 5: Reset the CC5E Bit */
+ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx CCMR3 register value */
+ tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
+
+ /* Select the Output Compare Mode */
+ MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
+
+ /* Set the Output Compare Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
+
+ /* Set the Output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+ /* Set the Output Idle state */
+ MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
+
+ }
+
+ /* Write to TIMx CCMR3 */
+ LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
+
+ /* Set the Capture Compare Register value */
+ LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx output channel 6.
+ * @param TIMx Timer Instance
+ * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+ uint32_t tmpccmr3;
+ uint32_t tmpccer;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC6_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+
+ /* Disable the Channel 5: Reset the CC6E Bit */
+ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx CCMR3 register value */
+ tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
+
+ /* Select the Output Compare Mode */
+ MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
+
+ /* Set the Output Compare Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
+
+ /* Set the Output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+ /* Set the Output Idle state */
+ MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
+ }
+
+ /* Write to TIMx CCMR3 */
+ LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
+
+ /* Set the Capture Compare Register value */
+ LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx input channel 1.
+ * @param TIMx Timer Instance
+ * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
+
+ /* Select the Input and set the filter and the prescaler value */
+ MODIFY_REG(TIMx->CCMR1,
+ (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
+ (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
+
+ /* Select the Polarity and set the CC1E Bit */
+ MODIFY_REG(TIMx->CCER,
+ (TIM_CCER_CC1P | TIM_CCER_CC1NP),
+ (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx input channel 2.
+ * @param TIMx Timer Instance
+ * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
+
+ /* Select the Input and set the filter and the prescaler value */
+ MODIFY_REG(TIMx->CCMR1,
+ (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
+ (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
+
+ /* Select the Polarity and set the CC2E Bit */
+ MODIFY_REG(TIMx->CCER,
+ (TIM_CCER_CC2P | TIM_CCER_CC2NP),
+ ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx input channel 3.
+ * @param TIMx Timer Instance
+ * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC3_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+ /* Disable the Channel 3: Reset the CC3E Bit */
+ TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
+
+ /* Select the Input and set the filter and the prescaler value */
+ MODIFY_REG(TIMx->CCMR2,
+ (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
+ (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
+
+ /* Select the Polarity and set the CC3E Bit */
+ MODIFY_REG(TIMx->CCER,
+ (TIM_CCER_CC3P | TIM_CCER_CC3NP),
+ ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx input channel 4.
+ * @param TIMx Timer Instance
+ * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC4_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
+
+ /* Select the Input and set the filter and the prescaler value */
+ MODIFY_REG(TIMx->CCMR2,
+ (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
+ (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
+
+ /* Select the Polarity and set the CC2E Bit */
+ MODIFY_REG(TIMx->CCER,
+ (TIM_CCER_CC4P | TIM_CCER_CC4NP),
+ ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
+
+ return SUCCESS;
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM15 || TIM16 || TIM17 || TIM20 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_ucpd.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_ucpd.c
new file mode 100644
index 00000000..9c537026
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_ucpd.c
@@ -0,0 +1,169 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_ucpd.c
+ * @author MCD Application Team
+ * @brief UCPD LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_ll_ucpd.h"
+#include "stm32u5xx_ll_bus.h"
+#include "stm32u5xx_ll_rcc.h"
+
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+#if defined (UCPD1)
+/** @addtogroup UCPD_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup UCPD_LL_Private_Constants UCPD Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UCPD_LL_Private_Macros UCPD Private Macros
+ * @{
+ */
+
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UCPD_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup UCPD_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the UCPD registers to their default reset values.
+ * @param UCPDx ucpd Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ucpd registers are de-initialized
+ * - ERROR: ucpd registers are not de-initialized
+ */
+ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_UCPD_ALL_INSTANCE(UCPDx));
+
+ LL_UCPD_Disable(UCPDx);
+
+ if (UCPD1 == UCPDx)
+ {
+ /* Force reset of ucpd clock */
+ LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_UCPD1);
+
+ /* Release reset of ucpd clock */
+ LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_UCPD1);
+
+ /* Disable ucpd clock */
+ LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_UCPD1);
+
+ status = SUCCESS;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initialize the ucpd registers according to the specified parameters in UCPD_InitStruct.
+ * @note As some bits in ucpd configuration registers can only be written when the ucpd is disabled
+ * (ucpd_CR1_SPE bit =0), UCPD peripheral should be in disabled state prior calling this function.
+ * Otherwise, ERROR result will be returned.
+ * @param UCPDx UCPD Instance
+ * @param UCPD_InitStruct pointer to a @ref LL_UCPD_InitTypeDef structure that contains
+ * the configuration information for the UCPD peripheral.
+ * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
+ */
+ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStruct)
+{
+ /* Check the ucpd Instance UCPDx*/
+ assert_param(IS_UCPD_ALL_INSTANCE(UCPDx));
+
+ if (UCPD1 == UCPDx)
+ {
+ LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_UCPD1);
+ }
+
+
+ LL_UCPD_Disable(UCPDx);
+
+ /*---------------------------- UCPDx CFG1 Configuration ------------------------*/
+ MODIFY_REG(UCPDx->CFG1,
+ UCPD_CFG1_PSC_UCPDCLK | UCPD_CFG1_TRANSWIN | UCPD_CFG1_IFRGAP | UCPD_CFG1_HBITCLKDIV,
+ UCPD_InitStruct->psc_ucpdclk | (UCPD_InitStruct->transwin << UCPD_CFG1_TRANSWIN_Pos) |
+ (UCPD_InitStruct->IfrGap << UCPD_CFG1_IFRGAP_Pos) | UCPD_InitStruct->HbitClockDiv);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set each @ref LL_UCPD_InitTypeDef field to default value.
+ * @param UCPD_InitStruct pointer to a @ref LL_UCPD_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_UCPD_StructInit(LL_UCPD_InitTypeDef *UCPD_InitStruct)
+{
+ /* Set UCPD_InitStruct fields to default values */
+ UCPD_InitStruct->psc_ucpdclk = LL_UCPD_PSC_DIV2;
+ UCPD_InitStruct->transwin = 0x7; /* Divide by 8 */
+ UCPD_InitStruct->IfrGap = 0x10; /* Divide by 17 */
+ UCPD_InitStruct->HbitClockDiv = 0x0D; /* Divide by 14 to produce HBITCLK */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* defined (UCPD1) */
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_usart.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_usart.c
new file mode 100644
index 00000000..da03d03c
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_usart.c
@@ -0,0 +1,413 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_usart.c
+ * @author MCD Application Team
+ * @brief USART LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_ll_usart.h"
+#include "stm32u5xx_ll_rcc.h"
+#include "stm32u5xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5)
+
+/** @addtogroup USART_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup USART_LL_Private_Macros
+ * @{
+ */
+
+#define IS_LL_USART_PRESCALER(__VALUE__) (((__VALUE__) == LL_USART_PRESCALER_DIV1) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV2) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV4) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV6) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV8) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV10) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV12) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV16) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV32) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV64) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV128) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV256))
+
+/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
+ * divided by the smallest oversampling used on the USART (i.e. 8) */
+#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 20000000U)
+
+/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
+#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
+
+#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
+ || ((__VALUE__) == LL_USART_DIRECTION_RX) \
+ || ((__VALUE__) == LL_USART_DIRECTION_TX) \
+ || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
+
+#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
+ || ((__VALUE__) == LL_USART_PARITY_EVEN) \
+ || ((__VALUE__) == LL_USART_PARITY_ODD))
+
+#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \
+ || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
+ || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
+
+#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
+ || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
+
+#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
+ || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
+
+#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
+ || ((__VALUE__) == LL_USART_PHASE_2EDGE))
+
+#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
+ || ((__VALUE__) == LL_USART_POLARITY_HIGH))
+
+#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
+ || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
+
+#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
+ || ((__VALUE__) == LL_USART_STOPBITS_1) \
+ || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
+ || ((__VALUE__) == LL_USART_STOPBITS_2))
+
+#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
+ || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
+ || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
+ || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup USART_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup USART_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize USART registers (Registers restored to their default values).
+ * @param USARTx USART Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: USART registers are de-initialized
+ * - ERROR: USART registers are not de-initialized
+ */
+ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(USARTx));
+
+ if (USARTx == USART1)
+ {
+ /* Force reset of USART clock */
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
+
+ /* Release reset of USART clock */
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
+ }
+ else if (USARTx == USART2)
+ {
+ /* Force reset of USART clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
+
+ /* Release reset of USART clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
+ }
+ else if (USARTx == USART3)
+ {
+ /* Force reset of USART clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
+
+ /* Release reset of USART clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
+ }
+ else if (USARTx == UART4)
+ {
+ /* Force reset of UART clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4);
+
+ /* Release reset of UART clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4);
+ }
+ else if (USARTx == UART5)
+ {
+ /* Force reset of UART clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5);
+
+ /* Release reset of UART clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);
+ }
+ else
+ {
+ status = ERROR;
+ }
+
+ return (status);
+}
+
+/**
+ * @brief Initialize USART registers according to the specified
+ * parameters in USART_InitStruct.
+ * @note As some bits in USART configuration registers can only be written when
+ * the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling
+ * this function. Otherwise, ERROR result will be returned.
+ * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
+ * @param USARTx USART Instance
+ * @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure
+ * that contains the configuration information for the specified USART peripheral.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: USART registers are initialized according to USART_InitStruct content
+ * - ERROR: Problem occurred during USART Registers initialization
+ */
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
+{
+ ErrorStatus status = ERROR;
+ uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(USARTx));
+ assert_param(IS_LL_USART_PRESCALER(USART_InitStruct->PrescalerValue));
+ assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
+ assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
+ assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
+ assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
+ assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
+ assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
+ assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
+
+ /* USART needs to be in disabled state, in order to be able to configure some bits in
+ CRx registers */
+ if (LL_USART_IsEnabled(USARTx) == 0U)
+ {
+ /*---------------------------- USART CR1 Configuration ---------------------
+ * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
+ * - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value
+ * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
+ * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
+ * - Oversampling: USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
+ */
+ MODIFY_REG(USARTx->CR1,
+ (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
+ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
+ (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
+ USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
+
+ /*---------------------------- USART CR2 Configuration ---------------------
+ * Configure USARTx CR2 (Stop bits) with parameters:
+ * - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
+ * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
+ */
+ LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
+
+ /*---------------------------- USART CR3 Configuration ---------------------
+ * Configure USARTx CR3 (Hardware Flow Control) with parameters:
+ * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to
+ * USART_InitStruct->HardwareFlowControl value.
+ */
+ LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
+
+ /*---------------------------- USART BRR Configuration ---------------------
+ * Retrieve Clock frequency used for USART Peripheral
+ */
+ if (USARTx == USART1)
+ {
+ periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART1_CLKSOURCE);
+ }
+ else if (USARTx == USART2)
+ {
+ periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART2_CLKSOURCE);
+ }
+ else if (USARTx == USART3)
+ {
+ periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART3_CLKSOURCE);
+ }
+ else if (USARTx == UART4)
+ {
+ periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART4_CLKSOURCE);
+ }
+ else if (USARTx == UART5)
+ {
+ periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART5_CLKSOURCE);
+ }
+ else
+ {
+ /* Nothing to do, as error code is already assigned to ERROR value */
+ }
+
+ /* Configure the USART Baud Rate :
+ - prescaler value is required
+ - valid baud rate value (different from 0) is required
+ - Peripheral clock as returned by RCC service, should be valid (different from 0).
+ */
+ if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
+ && (USART_InitStruct->BaudRate != 0U))
+ {
+ status = SUCCESS;
+ LL_USART_SetBaudRate(USARTx,
+ periphclk,
+ USART_InitStruct->PrescalerValue,
+ USART_InitStruct->OverSampling,
+ USART_InitStruct->BaudRate);
+
+ /* Check BRR is greater than or equal to 16d */
+ assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
+ }
+
+ /*---------------------------- USART PRESC Configuration -----------------------
+ * Configure USARTx PRESC (Prescaler) with parameters:
+ * - PrescalerValue: USART_PRESC_PRESCALER bits according to USART_InitStruct->PrescalerValue value.
+ */
+ LL_USART_SetPrescaler(USARTx, USART_InitStruct->PrescalerValue);
+ }
+ /* Endif (=> USART not in Disabled state => return ERROR) */
+
+ return (status);
+}
+
+/**
+ * @brief Set each @ref LL_USART_InitTypeDef field to default value.
+ * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+
+void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
+{
+ /* Set USART_InitStruct fields to default values */
+ USART_InitStruct->PrescalerValue = LL_USART_PRESCALER_DIV1;
+ USART_InitStruct->BaudRate = 9600U;
+ USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B;
+ USART_InitStruct->StopBits = LL_USART_STOPBITS_1;
+ USART_InitStruct->Parity = LL_USART_PARITY_NONE ;
+ USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX;
+ USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
+ USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16;
+}
+
+/**
+ * @brief Initialize USART Clock related settings according to the
+ * specified parameters in the USART_ClockInitStruct.
+ * @note As some bits in USART configuration registers can only be written when
+ * the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling
+ * this function. Otherwise, ERROR result will be returned.
+ * @param USARTx USART Instance
+ * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
+ * that contains the Clock configuration information for the specified USART peripheral.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: USART registers related to Clock settings are initialized according
+ * to USART_ClockInitStruct content
+ * - ERROR: Problem occurred during USART Registers initialization
+ */
+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check USART Instance and Clock signal output parameters */
+ assert_param(IS_UART_INSTANCE(USARTx));
+ assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
+
+ /* USART needs to be in disabled state, in order to be able to configure some bits in
+ CRx registers */
+ if (LL_USART_IsEnabled(USARTx) == 0U)
+ {
+ /* Ensure USART instance is USART capable */
+ assert_param(IS_USART_INSTANCE(USARTx));
+
+ /* Check clock related parameters */
+ assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
+ assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
+ assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
+
+ /*---------------------------- USART CR2 Configuration -----------------------
+ * Configure USARTx CR2 (Clock signal related bits) with parameters:
+ * - Clock Output: USART_CR2_CLKEN bit according to USART_ClockInitStruct->ClockOutput value
+ * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
+ * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
+ * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
+ */
+ MODIFY_REG(USARTx->CR2,
+ USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
+ USART_ClockInitStruct->ClockOutput | USART_ClockInitStruct->ClockPolarity |
+ USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
+ }
+ /* Else (USART not in Disabled state => return ERROR */
+ else
+ {
+ status = ERROR;
+ }
+
+ return (status);
+}
+
+/**
+ * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
+ * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
+{
+ /* Set LL_USART_ClockInitStruct fields with default values */
+ USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE;
+ USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput =
+ LL_USART_CLOCK_DISABLE */
+ USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput =
+ LL_USART_CLOCK_DISABLE */
+ USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput =
+ LL_USART_CLOCK_DISABLE */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* USART1 || USART2 || USART3 || UART4 || UART5 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_usb.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_usb.c
new file mode 100644
index 00000000..5c341eb2
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_usb.c
@@ -0,0 +1,2088 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_usb.c
+ * @author MCD Application Team
+ * @brief USB Low Layer HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the USB Peripheral Controller:
+ * + Initialization/de-initialization functions
+ * + I/O operation functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.
+
+ (#) Call USB_CoreInit() API to initialize the USB Core peripheral.
+
+ (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
+
+ @endverbatim
+
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup STM32U5xx_LL_USB_DRIVER
+ * @{
+ */
+
+#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED)
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup USB_LL_Exported_Functions USB Low Layer Exported Functions
+ * @{
+ */
+
+/** @defgroup USB_LL_Exported_Functions_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization/de-initialization functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the USB Core
+ * @param USBx USB Instance
+ * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
+ * the configuration information for the specified USBx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
+{
+ HAL_StatusTypeDef ret;
+
+#if defined (STM32U595xx) || defined (STM32U5A5xx) || defined (STM32U599xx) || defined (STM32U5A9xx)
+ if (cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY)
+ {
+ /* Init The UTMI Interface */
+ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
+
+ /* Select vbus source */
+ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
+ }
+
+ /* Reset after a PHY select */
+ ret = USB_CoreReset(USBx);
+
+ if (cfg.dma_enable == 1U)
+ {
+ USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2;
+ USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
+ }
+
+#else
+
+ /* Select FS Embedded PHY */
+ USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
+
+ /* Reset after a PHY select */
+ ret = USB_CoreReset(USBx);
+
+ if (cfg.battery_charging_enable == 0U)
+ {
+ /* Activate the USB Transceiver */
+ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
+ }
+ else
+ {
+ /* Deactivate the USB Transceiver */
+ USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
+ }
+#endif /* defined (STM32U595xx) || defined (STM32U5A5xx) || defined (STM32U599xx) || defined (STM32U5A9xx) */
+
+ return ret;
+}
+
+
+/**
+ * @brief Set the USB turnaround time
+ * @param USBx USB Instance
+ * @param hclk: AHB clock frequency
+ * @retval USB turnaround time In PHY Clocks number
+ */
+HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx,
+ uint32_t hclk, uint8_t speed)
+{
+ uint32_t UsbTrd;
+
+ /* The USBTRD is configured according to the tables below, depending on AHB frequency
+ used by application. In the low AHB frequency range it is used to stretch enough the USB response
+ time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access
+ latency to the Data FIFO */
+ if (speed == USBD_FS_SPEED)
+ {
+ if ((hclk >= 14200000U) && (hclk < 15000000U))
+ {
+ /* hclk Clock Range between 14.2-15 MHz */
+ UsbTrd = 0xFU;
+ }
+ else if ((hclk >= 15000000U) && (hclk < 16000000U))
+ {
+ /* hclk Clock Range between 15-16 MHz */
+ UsbTrd = 0xEU;
+ }
+ else if ((hclk >= 16000000U) && (hclk < 17200000U))
+ {
+ /* hclk Clock Range between 16-17.2 MHz */
+ UsbTrd = 0xDU;
+ }
+ else if ((hclk >= 17200000U) && (hclk < 18500000U))
+ {
+ /* hclk Clock Range between 17.2-18.5 MHz */
+ UsbTrd = 0xCU;
+ }
+ else if ((hclk >= 18500000U) && (hclk < 20000000U))
+ {
+ /* hclk Clock Range between 18.5-20 MHz */
+ UsbTrd = 0xBU;
+ }
+ else if ((hclk >= 20000000U) && (hclk < 21800000U))
+ {
+ /* hclk Clock Range between 20-21.8 MHz */
+ UsbTrd = 0xAU;
+ }
+ else if ((hclk >= 21800000U) && (hclk < 24000000U))
+ {
+ /* hclk Clock Range between 21.8-24 MHz */
+ UsbTrd = 0x9U;
+ }
+ else if ((hclk >= 24000000U) && (hclk < 27700000U))
+ {
+ /* hclk Clock Range between 24-27.7 MHz */
+ UsbTrd = 0x8U;
+ }
+ else if ((hclk >= 27700000U) && (hclk < 32000000U))
+ {
+ /* hclk Clock Range between 27.7-32 MHz */
+ UsbTrd = 0x7U;
+ }
+ else /* if(hclk >= 32000000) */
+ {
+ /* hclk Clock Range between 32-200 MHz */
+ UsbTrd = 0x6U;
+ }
+ }
+ else if (speed == USBD_HS_SPEED)
+ {
+ UsbTrd = USBD_HS_TRDT_VALUE;
+ }
+ else
+ {
+ UsbTrd = USBD_DEFAULT_TRDT_VALUE;
+ }
+
+ USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
+ USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_EnableGlobalInt
+ * Enables the controller's Global Int in the AHB Config reg
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
+{
+ USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_DisableGlobalInt
+ * Disable the controller's Global Int in the AHB Config reg
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
+{
+ USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_SetCurrentMode Set functional mode
+ * @param USBx Selected device
+ * @param mode current core mode
+ * This parameter can be one of these values:
+ * @arg USB_DEVICE_MODE Peripheral mode
+ * @arg USB_HOST_MODE Host mode
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode)
+{
+ uint32_t ms = 0U;
+
+ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
+
+ if (mode == USB_HOST_MODE)
+ {
+ USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
+
+ do
+ {
+ HAL_Delay(1U);
+ ms++;
+ } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < 50U));
+ }
+ else if (mode == USB_DEVICE_MODE)
+ {
+ USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
+
+ do
+ {
+ HAL_Delay(1U);
+ ms++;
+ } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < 50U));
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ if (ms == 50U)
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_DevInit Initializes the USB_OTG controller registers
+ * for device mode
+ * @param USBx Selected device
+ * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
+ * the configuration information for the specified USBx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
+{
+ HAL_StatusTypeDef ret = HAL_OK;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t i;
+
+ for (i = 0U; i < 15U; i++)
+ {
+ USBx->DIEPTXF[i] = 0U;
+ }
+
+ /* VBUS Sensing setup */
+ if (cfg.vbus_sensing_enable == 0U)
+ {
+ USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
+
+ /* Deactivate VBUS Sensing B */
+ USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
+
+ /* B-peripheral session valid override enable */
+#if defined (STM32U595xx) || defined (STM32U5A5xx) || defined (STM32U599xx) || defined (STM32U5A9xx)
+ USBx->GCCFG |= USB_OTG_GCCFG_VBVALEXTOEN;
+ USBx->GCCFG |= USB_OTG_GCCFG_VBVALOVAL;
+#else
+ USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
+ USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
+#endif /* defined (STM32U595xx) || defined (STM32U5A5xx) || defined (STM32U599xx) || defined (STM32U5A9xx) */
+ }
+ else
+ {
+#if defined (STM32U595xx) || defined (STM32U5A5xx) || defined (STM32U599xx) || defined (STM32U5A9xx)
+ /* B-peripheral session valid override disable */
+ USBx->GCCFG &= ~USB_OTG_GCCFG_VBVALEXTOEN;
+ USBx->GCCFG &= ~USB_OTG_GCCFG_VBVALOVAL;
+#endif /* defined (STM32U595xx) || defined (STM32U5A5xx) || defined (STM32U599xx) || defined (STM32U5A9xx) */
+
+ /* Enable HW VBUS sensing */
+ USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
+ }
+
+ /* Restart the Phy Clock */
+ USBx_PCGCCTL = 0U;
+
+ /* Device mode configuration */
+ USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80;
+
+#if defined (STM32U595xx) || defined (STM32U5A5xx) || defined (STM32U599xx) || defined (STM32U5A9xx)
+ if (cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY)
+ {
+ if (cfg.speed == USBD_HS_SPEED)
+ {
+ /* Set Core speed to High speed mode */
+ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH);
+ }
+ else
+ {
+ /* Set Core speed to Full speed mode */
+ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL);
+ }
+ }
+ else
+#endif /* defined (STM32U595xx) || defined (STM32U5A5xx) || defined (STM32U599xx) || defined (STM32U5A9xx) */
+ {
+ /* Set Core speed to Full speed mode */
+ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL);
+ }
+
+ /* Flush the FIFOs */
+ if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
+ {
+ ret = HAL_ERROR;
+ }
+
+ if (USB_FlushRxFifo(USBx) != HAL_OK)
+ {
+ ret = HAL_ERROR;
+ }
+
+ /* Clear all pending Device Interrupts */
+ USBx_DEVICE->DIEPMSK = 0U;
+ USBx_DEVICE->DOEPMSK = 0U;
+ USBx_DEVICE->DAINTMSK = 0U;
+
+ for (i = 0U; i < cfg.dev_endpoints; i++)
+ {
+ if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
+ {
+ if (i == 0U)
+ {
+ USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;
+ }
+ else
+ {
+ USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK;
+ }
+ }
+ else
+ {
+ USBx_INEP(i)->DIEPCTL = 0U;
+ }
+
+ USBx_INEP(i)->DIEPTSIZ = 0U;
+ USBx_INEP(i)->DIEPINT = 0xFB7FU;
+ }
+
+ for (i = 0U; i < cfg.dev_endpoints; i++)
+ {
+ if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
+ {
+ if (i == 0U)
+ {
+ USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;
+ }
+ else
+ {
+ USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK;
+ }
+ }
+ else
+ {
+ USBx_OUTEP(i)->DOEPCTL = 0U;
+ }
+
+ USBx_OUTEP(i)->DOEPTSIZ = 0U;
+ USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
+ }
+
+ USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
+
+ /* Disable all interrupts. */
+ USBx->GINTMSK = 0U;
+
+ /* Clear any pending interrupts */
+ USBx->GINTSTS = 0xBFFFFFFFU;
+
+ /* Enable the common interrupts */
+ if (cfg.dma_enable == 0U)
+ {
+ USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
+ }
+
+ /* Enable interrupts matching to the Device mode ONLY */
+ USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |
+ USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |
+ USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM |
+ USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM;
+
+ if (cfg.Sof_enable != 0U)
+ {
+ USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
+ }
+
+ if (cfg.vbus_sensing_enable == 1U)
+ {
+ USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO
+ * @param USBx Selected device
+ * @param num FIFO number
+ * This parameter can be a value from 1 to 15
+ 15 means Flush all Tx FIFOs
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
+{
+ uint32_t count = 0U;
+
+ USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));
+
+ do
+ {
+ if (++count > 200000U)
+ {
+ return HAL_TIMEOUT;
+ }
+ } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_FlushRxFifo : Flush Rx FIFO
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
+{
+ uint32_t count = 0;
+
+ USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
+
+ do
+ {
+ if (++count > 200000U)
+ {
+ return HAL_TIMEOUT;
+ }
+ } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_SetDevSpeed Initializes the DevSpd field of DCFG register
+ * depending the PHY type and the enumeration speed of the device.
+ * @param USBx Selected device
+ * @param speed device speed
+ * This parameter can be one of these values:
+ * @arg USB_OTG_SPEED_HIGH: High speed mode
+ * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode
+ * @arg USB_OTG_SPEED_FULL: Full speed mode
+ * @retval Hal status
+ */
+HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
+{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+
+ USBx_DEVICE->DCFG |= speed;
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_GetDevSpeed Return the Dev Speed
+ * @param USBx Selected device
+ * @retval speed device speed
+ * This parameter can be one of these values:
+ * @arg USBD_HS_SPEED: High speed mode
+ * @arg USBD_FS_SPEED: Full speed mode
+ */
+uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
+{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint8_t speed;
+ uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD;
+
+ if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)
+ {
+ speed = USBD_HS_SPEED;
+ }
+ else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) ||
+ (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ))
+ {
+ speed = USBD_FS_SPEED;
+ }
+ else
+ {
+ speed = 0xFU;
+ }
+
+ return speed;
+}
+
+/**
+ * @brief Activate and configure an endpoint
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t epnum = (uint32_t)ep->num;
+
+ if (ep->is_in == 1U)
+ {
+ USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK));
+
+ if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U)
+ {
+ USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
+ ((uint32_t)ep->type << 18) | (epnum << 22) |
+ USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
+ USB_OTG_DIEPCTL_USBAEP;
+ }
+ }
+ else
+ {
+ USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16);
+
+ if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
+ {
+ USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
+ ((uint32_t)ep->type << 18) |
+ USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
+ USB_OTG_DOEPCTL_USBAEP;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Activate and configure a dedicated endpoint
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t epnum = (uint32_t)ep->num;
+
+ /* Read DEPCTLn register */
+ if (ep->is_in == 1U)
+ {
+ if (((USBx_INEP(epnum)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U)
+ {
+ USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
+ ((uint32_t)ep->type << 18) | (epnum << 22) |
+ USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
+ USB_OTG_DIEPCTL_USBAEP;
+ }
+
+ USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK));
+ }
+ else
+ {
+ if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
+ {
+ USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
+ ((uint32_t)ep->type << 18) | (epnum << 22) |
+ USB_OTG_DOEPCTL_USBAEP;
+ }
+
+ USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief De-activate and de-initialize an endpoint
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t epnum = (uint32_t)ep->num;
+
+ /* Read DEPCTLn register */
+ if (ep->is_in == 1U)
+ {
+ if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
+ {
+ USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
+ USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS;
+ }
+
+ USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
+ USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
+ USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP |
+ USB_OTG_DIEPCTL_MPSIZ |
+ USB_OTG_DIEPCTL_TXFNUM |
+ USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
+ USB_OTG_DIEPCTL_EPTYP);
+ }
+ else
+ {
+ if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
+ {
+ USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
+ USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS;
+ }
+
+ USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
+ USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
+ USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP |
+ USB_OTG_DOEPCTL_MPSIZ |
+ USB_OTG_DOEPCTL_SD0PID_SEVNFRM |
+ USB_OTG_DOEPCTL_EPTYP);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief De-activate and de-initialize a dedicated endpoint
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t epnum = (uint32_t)ep->num;
+
+ /* Read DEPCTLn register */
+ if (ep->is_in == 1U)
+ {
+ if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
+ {
+ USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
+ USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS;
+ }
+
+ USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
+ USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
+ }
+ else
+ {
+ if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
+ {
+ USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
+ USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS;
+ }
+
+ USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
+ USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_EPStartXfer : setup and starts a transfer over an EP
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
+ * @param dma USB dma enabled or disabled
+ * This parameter can be one of these values:
+ * 0 : DMA feature not used
+ * 1 : DMA feature used
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma)
+{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t epnum = (uint32_t)ep->num;
+ uint16_t pktcnt;
+
+ /* IN endpoint */
+ if (ep->is_in == 1U)
+ {
+ /* Zero Length Packet? */
+ if (ep->xfer_len == 0U)
+ {
+ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
+ USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
+ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
+ }
+ else
+ {
+ /* Program the transfer size and packet count
+ * as follows: xfersize = N * maxpacket +
+ * short_packet pktcnt = N + (short_packet
+ * exist ? 1 : 0)
+ */
+ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
+ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
+ USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT &
+ (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19));
+
+ USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
+
+ if (ep->type == EP_TYPE_ISOC)
+ {
+ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);
+ USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29));
+ }
+ }
+
+ if (dma == 1U)
+ {
+ if ((uint32_t)ep->dma_addr != 0U)
+ {
+ USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);
+ }
+
+ if (ep->type == EP_TYPE_ISOC)
+ {
+ if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
+ {
+ USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
+ }
+ else
+ {
+ USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
+ }
+ }
+
+ /* EP enable, IN data in FIFO */
+ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
+ }
+ else
+ {
+ /* EP enable, IN data in FIFO */
+ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
+
+ if (ep->type != EP_TYPE_ISOC)
+ {
+ /* Enable the Tx FIFO Empty Interrupt for this EP */
+ if (ep->xfer_len > 0U)
+ {
+ USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);
+ }
+ }
+ else
+ {
+ if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
+ {
+ USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
+ }
+ else
+ {
+ USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
+ }
+
+ (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma);
+ }
+ }
+ }
+ else /* OUT endpoint */
+ {
+ /* Program the transfer size and packet count as follows:
+ * pktcnt = N
+ * xfersize = N * maxpacket
+ */
+ USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
+ USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
+
+ if (ep->xfer_len == 0U)
+ {
+ USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);
+ USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
+ }
+ else
+ {
+ pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket);
+ USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19);
+ USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt);
+ }
+
+ if (dma == 1U)
+ {
+ if ((uint32_t)ep->xfer_buff != 0U)
+ {
+ USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff);
+ }
+ }
+
+ if (ep->type == EP_TYPE_ISOC)
+ {
+ if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
+ {
+ USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;
+ }
+ else
+ {
+ USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
+ }
+ }
+ /* EP enable */
+ USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_EP0StartXfer : setup and starts a transfer over the EP 0
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
+ * @param dma USB dma enabled or disabled
+ * This parameter can be one of these values:
+ * 0 : DMA feature not used
+ * 1 : DMA feature used
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma)
+{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t epnum = (uint32_t)ep->num;
+
+ /* IN endpoint */
+ if (ep->is_in == 1U)
+ {
+ /* Zero Length Packet? */
+ if (ep->xfer_len == 0U)
+ {
+ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
+ USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
+ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
+ }
+ else
+ {
+ /* Program the transfer size and packet count
+ * as follows: xfersize = N * maxpacket +
+ * short_packet pktcnt = N + (short_packet
+ * exist ? 1 : 0)
+ */
+ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
+ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
+
+ if (ep->xfer_len > ep->maxpacket)
+ {
+ ep->xfer_len = ep->maxpacket;
+ }
+ USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
+ USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
+ }
+
+ if (dma == 1U)
+ {
+ if ((uint32_t)ep->dma_addr != 0U)
+ {
+ USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);
+ }
+
+ /* EP enable, IN data in FIFO */
+ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
+ }
+ else
+ {
+ /* EP enable, IN data in FIFO */
+ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
+
+ /* Enable the Tx FIFO Empty Interrupt for this EP */
+ if (ep->xfer_len > 0U)
+ {
+ USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);
+ }
+ }
+ }
+ else /* OUT endpoint */
+ {
+ /* Program the transfer size and packet count as follows:
+ * pktcnt = N
+ * xfersize = N * maxpacket
+ */
+ USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
+ USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
+
+ if (ep->xfer_len > 0U)
+ {
+ ep->xfer_len = ep->maxpacket;
+ }
+
+ USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
+ USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket));
+
+ if (dma == 1U)
+ {
+ if ((uint32_t)ep->xfer_buff != 0U)
+ {
+ USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff);
+ }
+ }
+
+ /* EP enable */
+ USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated
+ * with the EP/channel
+ * @param USBx Selected device
+ * @param src pointer to source buffer
+ * @param ch_ep_num endpoint or host channel number
+ * @param len Number of bytes to write
+ * @param dma USB dma enabled or disabled
+ * This parameter can be one of these values:
+ * 0 : DMA feature not used
+ * 1 : DMA feature used
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
+ uint8_t ch_ep_num, uint16_t len, uint8_t dma)
+{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint8_t *pSrc = src;
+ uint32_t count32b;
+ uint32_t i;
+
+ if (dma == 0U)
+ {
+ count32b = ((uint32_t)len + 3U) / 4U;
+ for (i = 0U; i < count32b; i++)
+ {
+ USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc);
+ pSrc++;
+ pSrc++;
+ pSrc++;
+ pSrc++;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_ReadPacket : read a packet from the RX FIFO
+ * @param USBx Selected device
+ * @param dest source pointer
+ * @param len Number of bytes to read
+ * @retval pointer to destination buffer
+ */
+void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
+{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint8_t *pDest = dest;
+ uint32_t pData;
+ uint32_t i;
+ uint32_t count32b = (uint32_t)len >> 2U;
+ uint16_t remaining_bytes = len % 4U;
+
+ for (i = 0U; i < count32b; i++)
+ {
+ __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U));
+ pDest++;
+ pDest++;
+ pDest++;
+ pDest++;
+ }
+
+ /* When Number of data is not word aligned, read the remaining byte */
+ if (remaining_bytes != 0U)
+ {
+ i = 0U;
+ __UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U));
+
+ do
+ {
+ *(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i)));
+ i++;
+ pDest++;
+ remaining_bytes--;
+ } while (remaining_bytes != 0U);
+ }
+
+ return ((void *)pDest);
+}
+
+/**
+ * @brief USB_EPSetStall : set a stall condition over an EP
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t epnum = (uint32_t)ep->num;
+
+ if (ep->is_in == 1U)
+ {
+ if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U))
+ {
+ USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS);
+ }
+ USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;
+ }
+ else
+ {
+ if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U))
+ {
+ USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS);
+ }
+ USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_EPClearStall : Clear a stall condition over an EP
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t epnum = (uint32_t)ep->num;
+
+ if (ep->is_in == 1U)
+ {
+ USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
+ if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
+ {
+ USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
+ }
+ }
+ else
+ {
+ USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
+ if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
+ {
+ USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_StopDevice : Stop the usb device mode
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)
+{
+ HAL_StatusTypeDef ret;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t i;
+
+ /* Clear Pending interrupt */
+ for (i = 0U; i < 15U; i++)
+ {
+ USBx_INEP(i)->DIEPINT = 0xFB7FU;
+ USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
+ }
+
+ /* Clear interrupt masks */
+ USBx_DEVICE->DIEPMSK = 0U;
+ USBx_DEVICE->DOEPMSK = 0U;
+ USBx_DEVICE->DAINTMSK = 0U;
+
+ /* Flush the FIFO */
+ ret = USB_FlushRxFifo(USBx);
+ if (ret != HAL_OK)
+ {
+ return ret;
+ }
+
+ ret = USB_FlushTxFifo(USBx, 0x10U);
+ if (ret != HAL_OK)
+ {
+ return ret;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief USB_SetDevAddress : Stop the usb device mode
+ * @param USBx Selected device
+ * @param address new device address to be assigned
+ * This parameter can be a value from 0 to 255
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address)
+{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+
+ USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD);
+ USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_DevConnect : Connect the USB device by enabling Rpu
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx)
+{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+
+ /* In case phy is stopped, ensure to ungate and restore the phy CLK */
+ USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);
+
+ USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx)
+{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+
+ /* In case phy is stopped, ensure to ungate and restore the phy CLK */
+ USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);
+
+ USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_ReadInterrupts: return the global USB interrupt status
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx)
+{
+ uint32_t tmpreg;
+
+ tmpreg = USBx->GINTSTS;
+ tmpreg &= USBx->GINTMSK;
+
+ return tmpreg;
+}
+
+/**
+ * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
+{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t tmpreg;
+
+ tmpreg = USBx_DEVICE->DAINT;
+ tmpreg &= USBx_DEVICE->DAINTMSK;
+
+ return ((tmpreg & 0xffff0000U) >> 16);
+}
+
+/**
+ * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
+{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t tmpreg;
+
+ tmpreg = USBx_DEVICE->DAINT;
+ tmpreg &= USBx_DEVICE->DAINTMSK;
+
+ return ((tmpreg & 0xFFFFU));
+}
+
+/**
+ * @brief Returns Device OUT EP Interrupt register
+ * @param USBx Selected device
+ * @param epnum endpoint number
+ * This parameter can be a value from 0 to 15
+ * @retval Device OUT EP Interrupt register
+ */
+uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
+{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t tmpreg;
+
+ tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT;
+ tmpreg &= USBx_DEVICE->DOEPMSK;
+
+ return tmpreg;
+}
+
+/**
+ * @brief Returns Device IN EP Interrupt register
+ * @param USBx Selected device
+ * @param epnum endpoint number
+ * This parameter can be a value from 0 to 15
+ * @retval Device IN EP Interrupt register
+ */
+uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
+{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t tmpreg;
+ uint32_t msk;
+ uint32_t emp;
+
+ msk = USBx_DEVICE->DIEPMSK;
+ emp = USBx_DEVICE->DIEPEMPMSK;
+ msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7;
+ tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk;
+
+ return tmpreg;
+}
+
+/**
+ * @brief USB_ClearInterrupts: clear a USB interrupt
+ * @param USBx Selected device
+ * @param interrupt flag
+ * @retval None
+ */
+void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
+{
+ USBx->GINTSTS |= interrupt;
+}
+
+/**
+ * @brief Returns USB core mode
+ * @param USBx Selected device
+ * @retval return core mode : Host or Device
+ * This parameter can be one of these values:
+ * 0 : Host
+ * 1 : Device
+ */
+uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)
+{
+ return ((USBx->GINTSTS) & 0x1U);
+}
+
+/**
+ * @brief Activate EP0 for Setup transactions
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx)
+{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+
+ /* Set the MPS of the IN EP0 to 64 bytes */
+ USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
+
+ USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Prepare the EP0 to start the first control setup
+ * @param USBx Selected device
+ * @param dma USB dma enabled or disabled
+ * This parameter can be one of these values:
+ * 0 : DMA feature not used
+ * 1 : DMA feature used
+ * @param psetup pointer to setup packet
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup)
+{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
+
+ if (gSNPSiD > USB_OTG_CORE_ID_300A)
+ {
+ if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
+ {
+ return HAL_OK;
+ }
+ }
+
+ USBx_OUTEP(0U)->DOEPTSIZ = 0U;
+ USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
+ USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U);
+ USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT;
+
+ if (dma == 1U)
+ {
+ USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup;
+ /* EP enable */
+ USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Reset the USB Core (needed after USB clock settings change)
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
+{
+ uint32_t count = 0U;
+
+ /* Wait for AHB master IDLE state. */
+ do
+ {
+ if (++count > 200000U)
+ {
+ return HAL_TIMEOUT;
+ }
+ } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
+
+ /* Core Soft Reset */
+ count = 0U;
+ USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
+
+ do
+ {
+ if (++count > 200000U)
+ {
+ return HAL_TIMEOUT;
+ }
+ } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_HostInit : Initializes the USB OTG controller registers
+ * for Host mode
+ * @param USBx Selected device
+ * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
+ * the configuration information for the specified USBx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
+{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t i;
+
+ /* Restart the Phy Clock */
+ USBx_PCGCCTL = 0U;
+
+#if defined (STM32U595xx) || defined (STM32U5A5xx) || defined (STM32U599xx) || defined (STM32U5A9xx)
+ /* Disable VBUS override */
+ USBx->GCCFG &= ~(USB_OTG_GCCFG_VBVALOVAL | USB_OTG_GCCFG_VBVALEXTOEN);
+#endif /* defined (STM32U595xx) || defined (STM32U5A5xx) || defined (STM32U599xx) || defined (STM32U5A9xx) */
+
+ /* Disable VBUS sensing */
+ USBx->GCCFG &= ~(USB_OTG_GCCFG_VBDEN);
+#if defined (STM32U575xx) || defined (STM32U585xx)
+ /* Disable Battery chargin detector */
+ USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);
+#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
+
+ if ((USBx->CID & (0x1U << 14)) != 0U)
+ {
+ if (cfg.speed == USBH_FSLS_SPEED)
+ {
+ /* Force Device Enumeration to FS/LS mode only */
+ USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS;
+ }
+ else
+ {
+ /* Set default Max speed support */
+ USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
+ }
+ }
+ else
+ {
+ /* Set default Max speed support */
+ USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
+ }
+
+ /* Make sure the FIFOs are flushed. */
+ (void)USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */
+ (void)USB_FlushRxFifo(USBx);
+
+ /* Clear all pending HC Interrupts */
+ for (i = 0U; i < cfg.Host_channels; i++)
+ {
+ USBx_HC(i)->HCINT = 0xFFFFFFFFU;
+ USBx_HC(i)->HCINTMSK = 0U;
+ }
+
+ /* Disable all interrupts. */
+ USBx->GINTMSK = 0U;
+
+ /* Clear any pending interrupts */
+ USBx->GINTSTS = 0xFFFFFFFFU;
+
+ if ((USBx->CID & (0x1U << 14)) != 0U)
+ {
+ /* set Rx FIFO size */
+ USBx->GRXFSIZ = 0x200U;
+ USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U);
+ USBx->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U);
+ }
+ else
+ {
+ /* set Rx FIFO size */
+ USBx->GRXFSIZ = 0x80U;
+ USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U);
+ USBx->HPTXFSIZ = (uint32_t)(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U);
+ }
+
+ /* Enable the common interrupts */
+ if (cfg.dma_enable == 0U)
+ {
+ USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
+ }
+
+ /* Enable interrupts matching to the Host mode ONLY */
+ USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM | \
+ USB_OTG_GINTMSK_SOFM | USB_OTG_GINTSTS_DISCINT | \
+ USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the
+ * HCFG register on the PHY type and set the right frame interval
+ * @param USBx Selected device
+ * @param freq clock frequency
+ * This parameter can be one of these values:
+ * HCFG_48_MHZ : Full Speed 48 MHz Clock
+ * HCFG_6_MHZ : Low Speed 6 MHz Clock
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq)
+{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+
+ USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS);
+ USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS;
+
+ if (freq == HCFG_48_MHZ)
+ {
+ USBx_HOST->HFIR = 48000U;
+ }
+ else if (freq == HCFG_6_MHZ)
+ {
+ USBx_HOST->HFIR = 6000U;
+ }
+ else
+ {
+ /* ... */
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_OTG_ResetPort : Reset Host Port
+ * @param USBx Selected device
+ * @retval HAL status
+ * @note (1)The application must wait at least 10 ms
+ * before clearing the reset bit.
+ */
+HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
+{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+
+ __IO uint32_t hprt0 = 0U;
+
+ hprt0 = USBx_HPRT0;
+
+ hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |
+ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
+
+ USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0);
+ HAL_Delay(100U); /* See Note #1 */
+ USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0);
+ HAL_Delay(10U);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_DriveVbus : activate or de-activate vbus
+ * @param state VBUS state
+ * This parameter can be one of these values:
+ * 0 : Deactivate VBUS
+ * 1 : Activate VBUS
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state)
+{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ __IO uint32_t hprt0 = 0U;
+
+ hprt0 = USBx_HPRT0;
+
+ hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |
+ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
+
+ if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U))
+ {
+ USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0);
+ }
+ if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U))
+ {
+ USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0);
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Return Host Core speed
+ * @param USBx Selected device
+ * @retval speed : Host speed
+ * This parameter can be one of these values:
+ * @arg HCD_SPEED_HIGH: High speed mode
+ * @arg HCD_SPEED_FULL: Full speed mode
+ * @arg HCD_SPEED_LOW: Low speed mode
+ */
+uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx)
+{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ __IO uint32_t hprt0 = 0U;
+
+ hprt0 = USBx_HPRT0;
+ return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17);
+}
+
+/**
+ * @brief Return Host Current Frame number
+ * @param USBx Selected device
+ * @retval current frame number
+ */
+uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx)
+{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+
+ return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM);
+}
+
+/**
+ * @brief Initialize a host channel
+ * @param USBx Selected device
+ * @param ch_num Channel number
+ * This parameter can be a value from 1 to 15
+ * @param epnum Endpoint number
+ * This parameter can be a value from 1 to 15
+ * @param dev_address Current device address
+ * This parameter can be a value from 0 to 255
+ * @param speed Current device speed
+ * This parameter can be one of these values:
+ * @arg USB_OTG_SPEED_HIGH: High speed mode
+ * @arg USB_OTG_SPEED_FULL: Full speed mode
+ * @arg USB_OTG_SPEED_LOW: Low speed mode
+ * @param ep_type Endpoint Type
+ * This parameter can be one of these values:
+ * @arg EP_TYPE_CTRL: Control type
+ * @arg EP_TYPE_ISOC: Isochronous type
+ * @arg EP_TYPE_BULK: Bulk type
+ * @arg EP_TYPE_INTR: Interrupt type
+ * @param mps Max Packet Size
+ * This parameter can be a value from 0 to 32K
+ * @retval HAL state
+ */
+HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
+ uint8_t epnum, uint8_t dev_address, uint8_t speed,
+ uint8_t ep_type, uint16_t mps)
+{
+ HAL_StatusTypeDef ret = HAL_OK;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t HCcharEpDir;
+ uint32_t HCcharLowSpeed;
+ uint32_t HostCoreSpeed;
+
+ /* Clear old interrupt conditions for this host channel. */
+ USBx_HC((uint32_t)ch_num)->HCINT = 0xFFFFFFFFU;
+
+ /* Enable channel interrupts required for this transfer. */
+ switch (ep_type)
+ {
+ case EP_TYPE_CTRL:
+ case EP_TYPE_BULK:
+ USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |
+ USB_OTG_HCINTMSK_STALLM |
+ USB_OTG_HCINTMSK_TXERRM |
+ USB_OTG_HCINTMSK_DTERRM |
+ USB_OTG_HCINTMSK_AHBERR |
+ USB_OTG_HCINTMSK_NAKM;
+
+ if ((epnum & 0x80U) == 0x80U)
+ {
+ USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
+ }
+ else
+ {
+ if ((USBx->CID & (0x1U << 14)) != 0U)
+ {
+ USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_NYET |
+ USB_OTG_HCINTMSK_ACKM;
+ }
+ }
+ break;
+
+ case EP_TYPE_INTR:
+ USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |
+ USB_OTG_HCINTMSK_STALLM |
+ USB_OTG_HCINTMSK_TXERRM |
+ USB_OTG_HCINTMSK_DTERRM |
+ USB_OTG_HCINTMSK_NAKM |
+ USB_OTG_HCINTMSK_AHBERR |
+ USB_OTG_HCINTMSK_FRMORM;
+
+ if ((epnum & 0x80U) == 0x80U)
+ {
+ USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
+ }
+
+ break;
+
+ case EP_TYPE_ISOC:
+ USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |
+ USB_OTG_HCINTMSK_ACKM |
+ USB_OTG_HCINTMSK_AHBERR |
+ USB_OTG_HCINTMSK_FRMORM;
+
+ if ((epnum & 0x80U) == 0x80U)
+ {
+ USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM);
+ }
+ break;
+
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+
+ /* Enable the top level host channel interrupt. */
+ USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU);
+
+ /* Make sure host channel interrupts are enabled. */
+ USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM;
+
+ /* Program the HCCHAR register */
+ if ((epnum & 0x80U) == 0x80U)
+ {
+ HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR;
+ }
+ else
+ {
+ HCcharEpDir = 0U;
+ }
+
+ HostCoreSpeed = USB_GetHostSpeed(USBx);
+
+ /* LS device plugged to HUB */
+ if ((speed == HPRT0_PRTSPD_LOW_SPEED) && (HostCoreSpeed != HPRT0_PRTSPD_LOW_SPEED))
+ {
+ HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV;
+ }
+ else
+ {
+ HCcharLowSpeed = 0U;
+ }
+
+ USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) |
+ ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) |
+ (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) |
+ ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | HCcharEpDir | HCcharLowSpeed;
+
+ if (ep_type == EP_TYPE_INTR)
+ {
+ USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Start a transfer over a host channel
+ * @param USBx Selected device
+ * @param hc pointer to host channel structure
+ * @param dma USB dma enabled or disabled
+ * This parameter can be one of these values:
+ * 0 : DMA feature not used
+ * 1 : DMA feature used
+ * @retval HAL state
+ */
+HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma)
+{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t ch_num = (uint32_t)hc->ch_num;
+ __IO uint32_t tmpreg;
+ uint8_t is_oddframe;
+ uint16_t len_words;
+ uint16_t num_packets;
+ uint16_t max_hc_pkt_count = 256U;
+
+ if (((USBx->CID & (0x1U << 14)) != 0U) && (hc->speed == USBH_HS_SPEED))
+ {
+ /* in DMA mode host Core automatically issues ping in case of NYET/NAK */
+ if ((dma == 1U) && ((hc->ep_type == EP_TYPE_CTRL) || (hc->ep_type == EP_TYPE_BULK)))
+ {
+ USBx_HC((uint32_t)ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET |
+ USB_OTG_HCINTMSK_ACKM |
+ USB_OTG_HCINTMSK_NAKM);
+ }
+
+ if ((dma == 0U) && (hc->do_ping == 1U))
+ {
+ (void)USB_DoPing(USBx, hc->ch_num);
+ return HAL_OK;
+ }
+
+ }
+
+ /* Compute the expected number of packets associated to the transfer */
+ if (hc->xfer_len > 0U)
+ {
+ num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet);
+
+ if (num_packets > max_hc_pkt_count)
+ {
+ num_packets = max_hc_pkt_count;
+ hc->XferSize = (uint32_t)num_packets * hc->max_packet;
+ }
+ }
+ else
+ {
+ num_packets = 1U;
+ }
+
+ /*
+ * For IN channel HCTSIZ.XferSize is expected to be an integer multiple of
+ * max_packet size.
+ */
+ if (hc->ep_is_in != 0U)
+ {
+ hc->XferSize = (uint32_t)num_packets * hc->max_packet;
+ }
+ else
+ {
+ hc->XferSize = hc->xfer_len;
+ }
+
+ /* Initialize the HCTSIZn register */
+ USBx_HC(ch_num)->HCTSIZ = (hc->XferSize & USB_OTG_HCTSIZ_XFRSIZ) |
+ (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |
+ (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID);
+
+ if (dma != 0U)
+ {
+ /* xfer_buff MUST be 32-bits aligned */
+ USBx_HC(ch_num)->HCDMA = (uint32_t)hc->xfer_buff;
+ }
+
+ is_oddframe = (((uint32_t)USBx_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U;
+ USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;
+ USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29;
+
+ /* Set host channel enable */
+ tmpreg = USBx_HC(ch_num)->HCCHAR;
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+
+ /* make sure to set the correct ep direction */
+ if (hc->ep_is_in != 0U)
+ {
+ tmpreg |= USB_OTG_HCCHAR_EPDIR;
+ }
+ else
+ {
+ tmpreg &= ~USB_OTG_HCCHAR_EPDIR;
+ }
+ tmpreg |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(ch_num)->HCCHAR = tmpreg;
+
+ if (dma != 0U) /* dma mode */
+ {
+ return HAL_OK;
+ }
+
+ if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U))
+ {
+ switch (hc->ep_type)
+ {
+ /* Non periodic transfer */
+ case EP_TYPE_CTRL:
+ case EP_TYPE_BULK:
+
+ len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);
+
+ /* check if there is enough space in FIFO space */
+ if (len_words > (USBx->HNPTXSTS & 0xFFFFU))
+ {
+ /* need to process data in nptxfempty interrupt */
+ USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;
+ }
+ break;
+
+ /* Periodic transfer */
+ case EP_TYPE_INTR:
+ case EP_TYPE_ISOC:
+ len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);
+ /* check if there is enough space in FIFO space */
+ if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */
+ {
+ /* need to process data in ptxfempty interrupt */
+ USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM;
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Write packet into the Tx FIFO. */
+ (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len, 0);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read all host channel interrupts status
+ * @param USBx Selected device
+ * @retval HAL state
+ */
+uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx)
+{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+
+ return ((USBx_HOST->HAINT) & 0xFFFFU);
+}
+
+/**
+ * @brief Halt a host channel
+ * @param USBx Selected device
+ * @param hc_num Host Channel number
+ * This parameter can be a value from 1 to 15
+ * @retval HAL state
+ */
+HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
+{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t hcnum = (uint32_t)hc_num;
+ uint32_t count = 0U;
+ uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18;
+ uint32_t ChannelEna = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31;
+
+ if (((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == USB_OTG_GAHBCFG_DMAEN) &&
+ (ChannelEna == 0U))
+ {
+ return HAL_OK;
+ }
+
+ /* Check for space in the request queue to issue the halt. */
+ if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK))
+ {
+ USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
+
+ if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U)
+ {
+ if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U)
+ {
+ USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
+ USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
+ do
+ {
+ if (++count > 1000U)
+ {
+ break;
+ }
+ } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
+ }
+ else
+ {
+ USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+ }
+ }
+ }
+ else
+ {
+ USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
+
+ if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U)
+ {
+ USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
+ USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
+ do
+ {
+ if (++count > 1000U)
+ {
+ break;
+ }
+ } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
+ }
+ else
+ {
+ USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initiate Do Ping protocol
+ * @param USBx Selected device
+ * @param hc_num Host Channel number
+ * This parameter can be a value from 1 to 15
+ * @retval HAL state
+ */
+HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num)
+{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t chnum = (uint32_t)ch_num;
+ uint32_t num_packets = 1U;
+ uint32_t tmpreg;
+
+ USBx_HC(chnum)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |
+ USB_OTG_HCTSIZ_DOPING;
+
+ /* Set host channel enable */
+ tmpreg = USBx_HC(chnum)->HCCHAR;
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+ tmpreg |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(chnum)->HCCHAR = tmpreg;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop Host Core
+ * @param USBx Selected device
+ * @retval HAL state
+ */
+HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
+{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t count = 0U;
+ uint32_t value;
+ uint32_t i;
+
+ (void)USB_DisableGlobalInt(USBx);
+
+ /* Flush FIFO */
+ (void)USB_FlushTxFifo(USBx, 0x10U);
+ (void)USB_FlushRxFifo(USBx);
+
+ /* Flush out any leftover queued requests. */
+ for (i = 0U; i <= 15U; i++)
+ {
+ value = USBx_HC(i)->HCCHAR;
+ value |= USB_OTG_HCCHAR_CHDIS;
+ value &= ~USB_OTG_HCCHAR_CHENA;
+ value &= ~USB_OTG_HCCHAR_EPDIR;
+ USBx_HC(i)->HCCHAR = value;
+ }
+
+ /* Halt all channels to put them into a known state. */
+ for (i = 0U; i <= 15U; i++)
+ {
+ value = USBx_HC(i)->HCCHAR;
+ value |= USB_OTG_HCCHAR_CHDIS;
+ value |= USB_OTG_HCCHAR_CHENA;
+ value &= ~USB_OTG_HCCHAR_EPDIR;
+ USBx_HC(i)->HCCHAR = value;
+
+ do
+ {
+ if (++count > 1000U)
+ {
+ break;
+ }
+ } while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
+ }
+
+ /* Clear any pending Host interrupts */
+ USBx_HOST->HAINT = 0xFFFFFFFFU;
+ USBx->GINTSTS = 0xFFFFFFFFU;
+
+ (void)USB_EnableGlobalInt(USBx);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_ActivateRemoteWakeup active remote wakeup signalling
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
+{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+
+ if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
+ {
+ /* active Remote wakeup signalling */
+ USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
+{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+
+ /* active Remote wakeup signalling */
+ USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);
+
+ return HAL_OK;
+}
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_utils.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_utils.c
new file mode 100644
index 00000000..75387bb3
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_utils.c
@@ -0,0 +1,821 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_ll_utils.c
+ * @author MCD Application Team
+ * @brief UTILS LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_ll_utils.h"
+#include "stm32u5xx_ll_rcc.h"
+#include "stm32u5xx_ll_system.h"
+#include "stm32u5xx_ll_pwr.h"
+#include
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32U5xx_LL_Driver
+ * @{
+ */
+
+/** @addtogroup UTILS_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Private_Constants
+ * @{
+ */
+#define UTILS_MAX_FREQUENCY_SCALE0 160000000U /*!< Maximum frequency for system clock at power scale0, in Hz */
+#define UTILS_MAX_FREQUENCY_SCALE1 100000000U /*!< Maximum frequency for system clock at power scale1, in Hz */
+#define UTILS_MAX_FREQUENCY_SCALE2 50000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
+#define UTILS_MAX_FREQUENCY_SCALE3 24000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
+
+/* Defines used for PLL range */
+#define UTILS_PLLVCO_INPUT_MIN 4000000U /*!< Frequency min for PLLVCO input, in Hz */
+#define UTILS_PLLVCO_INPUT_MAX 16000000U /*!< Frequency max for PLLVCO input, in Hz */
+#define UTILS_PLLVCO_OUTPUT_MIN 64000000U /*!< Frequency min for PLLVCO output, in Hz */
+#define UTILS_PLLVCO_OUTPUT_MAX 344000000U /*!< Frequency max for PLLVCO output, in Hz */
+
+/* Defines used for HSE range */
+#define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */
+#define UTILS_HSE_FREQUENCY_MAX 50000000U /*!< Frequency max for HSE frequency, in Hz */
+
+/* Defines used for FLASH latency according to HCLK Frequency */
+#define UTILS_SCALE1_LATENCY0_FREQ (32000000U) /*!< HCLK frequency to set FLASH latency 0 in power scale 1 */
+#define UTILS_SCALE1_LATENCY1_FREQ (64000000U) /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
+#define UTILS_SCALE1_LATENCY2_FREQ (96000000U) /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
+#define UTILS_SCALE1_LATENCY3_FREQ (128000000U) /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
+#define UTILS_SCALE1_LATENCY4_FREQ (160000000U) /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
+#define UTILS_SCALE2_LATENCY0_FREQ (25000000U) /*!< HCLK frequency to set FLASH latency 0 in power scale 2 */
+#define UTILS_SCALE2_LATENCY1_FREQ (50000000U) /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
+#define UTILS_SCALE2_LATENCY2_FREQ (75000000U) /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
+#define UTILS_SCALE2_LATENCY3_FREQ (100000000U) /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
+#define UTILS_SCALE3_LATENCY0_FREQ (12.5000000) /*!< HCLK frequency to set FLASH latency 0 in power scale 3 */
+#define UTILS_SCALE3_LATENCY1_FREQ (25000000U) /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
+#define UTILS_SCALE3_LATENCY2_FREQ (37.5000000) /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
+#define UTILS_SCALE3_LATENCY3_FREQ (50000000U) /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */
+#define UTILS_SCALE4_LATENCY0_FREQ (8000000U) /*!< HCLK frequency to set FLASH latency 0 in power scale 4 */
+#define UTILS_SCALE4_LATENCY1_FREQ (16000000U) /*!< HCLK frequency to set FLASH latency 1 in power scale 4 */
+#define UTILS_SCALE4_LATENCY2_FREQ (24000000U) /*!< HCLK frequency to set FLASH latency 2 in power scale 4 */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Private_Macros
+ * @{
+ */
+#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
+
+#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
+ || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
+ || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
+ || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
+ || ((__VALUE__) == LL_RCC_APB1_DIV_16))
+
+#define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
+ || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
+ || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
+ || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
+ || ((__VALUE__) == LL_RCC_APB2_DIV_16))
+
+#define IS_LL_UTILS_APB3_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB3_DIV_1) \
+ || ((__VALUE__) == LL_RCC_APB3_DIV_2) \
+ || ((__VALUE__) == LL_RCC_APB3_DIV_4) \
+ || ((__VALUE__) == LL_RCC_APB3_DIV_8) \
+ || ((__VALUE__) == LL_RCC_APB3_DIV_16))
+
+#define IS_LL_UTILS_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U))
+
+#define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((4U <= (__VALUE__)) && ((__VALUE__) <= 512U))
+
+#define IS_LL_UTILS_PLLR_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 128U))
+
+#define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__))\
+ && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))
+
+#define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__))\
+ && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))
+
+#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE4) ? \
+ ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE0) : \
+ (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? \
+ ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
+ (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? \
+ ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
+ ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))
+
+#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
+ || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
+
+#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN)\
+ && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
+/**
+ * @}
+ */
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Functions UTILS Private functions
+ * @{
+ */
+static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
+ LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
+static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency,
+ LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+static ErrorStatus UTILS_PLL_IsBusy(void);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup UTILS_LL_EF_DELAY
+ * @{
+ */
+
+/**
+ * @brief This function configures the Cortex-M SysTick source to have 1ms time base.
+ * @note When a RTOS is used, it is recommended to avoid changing the Systick
+ * configuration by calling this function, for a delay use rather osDelay RTOS service.
+ * @param HCLKFrequency HCLK frequency in Hz
+ * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
+ * @retval None
+ */
+void LL_Init1msTick(uint32_t HCLKFrequency)
+{
+ /* Use frequency provided in argument */
+ LL_InitTick(HCLKFrequency, 1000U);
+}
+
+/**
+ * @brief This function provides accurate delay (in milliseconds) based
+ * on SysTick counter flag
+ * @note When a RTOS is used, it is recommended to avoid using blocking delay
+ * and use rather osDelay service.
+ * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
+ * will configure Systick to 1ms
+ * @param Delay specifies the delay time length, in milliseconds.
+ * @retval None
+ */
+
+void LL_mDelay(uint32_t Delay)
+{
+ __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
+ uint32_t tmpDelay = Delay;
+
+ /* Add this code to indicate that local variable is not used */
+ ((void)tmp);
+
+ /* Add a period to guaranty minimum wait */
+ if (tmpDelay < LL_MAX_DELAY)
+ {
+ tmpDelay++;
+ }
+
+ while (tmpDelay != 0U)
+ {
+ if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
+ {
+ tmpDelay--;
+ }
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup UTILS_EF_SYSTEM
+ * @brief System Configuration functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### System Configuration functions #####
+ ===============================================================================
+ [..]
+ System, AHB and APB buses clocks configuration
+
+ (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2, PCLK3 is
+ 160000000 Hz.
+ @endverbatim
+ @internal
+ Depending on the device voltage range, the maximum frequency should be
+ adapted accordingly:
+
+ (++) Table 1. HCLK clock frequency for STM32U5 devices
+ (++) +-----------------------------------------------------------------------------------------------+
+ (++) | Latency | HCLK clock frequency (MHz) |
+ (++) | |-----------------------------------------------------------------------------|
+ (++) | | voltage range 1 | voltage range 2 | voltage range 3 | voltage range 4 |
+ (++) | | 1.2 V | 1.1 V | 1.0 V | 0.9 V |
+ (++) |-----------------|-------------------|------------------|------------------|-------------------|
+ (++) |0WS(1 CPU cycles)| 0 < HCLK <= 32 | 0 < HCLK <= 25 | 0 < HCLK <= 12.5| 0 < HCLK <= 8 |
+ (++) |-----------------|-------------------|------------------|------------------|-------------------|
+ (++) |1WS(2 CPU cycles)| 32 < HCLK <= 64 | 25 < HCLK <= 50 | 12.5 < HCLK <= 25| 0 < HCLK <= 16 |
+ (++) |-----------------|-------------------|------------------|------------------|-------------------|
+ (++) |2WS(3 CPU cycles)| 64 < HCLK <= 96 | 50 < HCLK <= 75 | 25 < HCLK <= 37.5| 0 < HCLK <= 24 |
+ (++) |-----------------|-------------------|------------------|------------------|-------------------|
+ (++) |3WS(4 CPU cycles)| 96 < HCLK <= 128 | 75 < HCLK <= 100| 37.5 < HCLK <= 50| |
+ (++) |-----------------|-------------------|------------------|------------------| |
+ (++) |4WS(5 CPU cycles)| 128 < HCLK <= 160| | | |
+ (++) +-----------------+-------------------+------------------+------------------+-------------------+
+
+ @endinternal
+ * @{
+ */
+
+/**
+ * @brief This function sets directly SystemCoreClock CMSIS variable.
+ * @note Variable can be calculated also through SystemCoreClockUpdate function.
+ * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
+ * @retval None
+ */
+void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
+{
+ /* HCLK clock frequency */
+ SystemCoreClock = HCLKFrequency;
+}
+
+/**
+ * @brief Update number of Flash wait states in line with new frequency and current
+ voltage range.
+ * @param HCLK_Frequency HCLK frequency
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: Latency has been modified
+ * - ERROR: Latency cannot be modified
+ */
+ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency)
+{
+ ErrorStatus status = SUCCESS;
+ uint32_t timeout;
+ uint32_t getlatency;
+ uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
+
+ /* Frequency cannot be equal to 0 */
+ if (HCLK_Frequency == 0U)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ if (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
+ {
+ if (HCLK_Frequency <= UTILS_SCALE1_LATENCY0_FREQ)
+ {
+ /* 0 < HCLK <= 32 => 0WS (1 CPU cycles) : Do nothing, keep latency to default LL_FLASH_LATENCY_0 */
+ }
+ else if ((HCLK_Frequency <= UTILS_SCALE1_LATENCY1_FREQ))
+ {
+ /* 32 < HCLK <=64 => 1WS (2 CPU cycles) */
+ latency = LL_FLASH_LATENCY_1;
+ }
+ else if (HCLK_Frequency <= UTILS_SCALE1_LATENCY2_FREQ)
+ {
+ /* 64 < HCLK <= 96 => 2WS (3 CPU cycles) */
+ latency = LL_FLASH_LATENCY_2;
+ }
+ else if (HCLK_Frequency <= UTILS_SCALE1_LATENCY3_FREQ)
+ {
+ /* 96 < HCLK <= 128 => 3WS (4 CPU cycles) */
+ latency = LL_FLASH_LATENCY_3;
+ }
+ else if (HCLK_Frequency <= UTILS_SCALE1_LATENCY4_FREQ)
+ {
+ /* 128 < HCLK <= 160 => 4WS (5 CPU cycles) */
+ latency = LL_FLASH_LATENCY_4;
+ }
+ else
+ {
+ status = ERROR;
+ }
+ /* else HCLK_Frequency <= 10MHz default LL_FLASH_LATENCY_0 0WS */
+ }
+ else if (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2)
+ {
+ if (HCLK_Frequency <= UTILS_SCALE2_LATENCY0_FREQ)
+ {
+ /* 0 < HCLK <= 25 => 0WS (1 CPU cycles) : Do nothing, keep latency to default LL_FLASH_LATENCY_0 */
+ }
+ else if (HCLK_Frequency <= UTILS_SCALE2_LATENCY1_FREQ)
+ {
+ /* 25 < HCLK <= 50 => 1WS (2 CPU cycles) */
+ latency = LL_FLASH_LATENCY_1;
+ }
+ else if (HCLK_Frequency <= UTILS_SCALE2_LATENCY2_FREQ)
+ {
+ /* 50 < HCLK <= 75 => 2WS (3 CPU cycles) */
+ latency = LL_FLASH_LATENCY_2;
+ }
+ else if (HCLK_Frequency <= UTILS_SCALE2_LATENCY3_FREQ)
+ {
+ /* 75 < HCLK <= 100 => 3WS (4 CPU cycles) */
+ latency = LL_FLASH_LATENCY_3;
+ }
+ else
+ {
+ status = ERROR;
+ }
+ /* else HCLK_Frequency <= 10MHz default LL_FLASH_LATENCY_0 0WS */
+ }
+ else if (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE3)
+ {
+ if ((double_t)HCLK_Frequency <= UTILS_SCALE3_LATENCY0_FREQ)
+ {
+ /* 0 < HCLK <= 12.5 => 0WS (1 CPU cycles) : Do nothing, keep latency to default LL_FLASH_LATENCY_0 */
+ }
+ else if (HCLK_Frequency <= UTILS_SCALE3_LATENCY1_FREQ)
+ {
+ /* 12.5 < HCLK <= 25 => 1WS (2 CPU cycles) */
+ latency = LL_FLASH_LATENCY_1;
+ }
+ else if ((double_t)HCLK_Frequency <= UTILS_SCALE3_LATENCY2_FREQ)
+ {
+ /* 25 < HCLK <= 37.5 => 2WS (3 CPU cycles) */
+ latency = LL_FLASH_LATENCY_2;
+ }
+ else if (HCLK_Frequency <= UTILS_SCALE3_LATENCY3_FREQ)
+ {
+ /* 37.5 < HCLK <= 50 => 3WS (4 CPU cycles) */
+ latency = LL_FLASH_LATENCY_3;
+ }
+ else
+ {
+ status = ERROR;
+ }
+ /* else HCLK_Frequency <= 10MHz default LL_FLASH_LATENCY_0 0WS */
+ }
+ else
+ {
+ if (HCLK_Frequency <= UTILS_SCALE4_LATENCY0_FREQ)
+ {
+ /* 0 < HCLK <= 8 => 0WS (1 CPU cycles) : Do nothing, keep latency to default LL_FLASH_LATENCY_0 */
+ }
+ else if (HCLK_Frequency <= UTILS_SCALE4_LATENCY1_FREQ)
+ {
+ /* 8 < HCLK <= 16 => 1WS (2 CPU cycles) */
+ latency = LL_FLASH_LATENCY_1;
+ }
+ else if (HCLK_Frequency <= UTILS_SCALE4_LATENCY2_FREQ)
+ {
+ /* 16 < HCLK <= 24 => 2WS (3 CPU cycles) */
+ latency = LL_FLASH_LATENCY_2;
+ }
+ else
+ {
+ status = ERROR;
+ }
+ /* else HCLK_Frequency <= 10MHz default LL_FLASH_LATENCY_0 0WS */
+ }
+ }
+
+ if(status == SUCCESS)
+ {
+ LL_FLASH_SetLatency(latency);
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ timeout = 2;
+ do
+ {
+ /* Wait for Flash latency to be updated */
+ getlatency = LL_FLASH_GetLatency();
+ timeout--;
+ } while ((getlatency != latency) && (timeout > 0U));
+
+ if(getlatency != latency)
+ {
+ status = ERROR;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief This function configures system clock with MSI as clock source of the PLL
+ * @note The application needs to ensure that PLL1, PLL2 and/or PLL3 are disabled.
+ * @note Function is based on the following formula:
+ * - PLL1 output frequency = (((MSI frequency / PLL1M) * PLL1N) / PLL1R)
+ * - PLL1M: ensure that the VCO input frequency ranges from 1 to 16 MHz (PLL1VCO_input = MSI frequency / PLL1M)
+ * - PLL1N: ensure that the VCO output frequency is between 4 and 512 MHz
+ (PLL1VCO_output = PLL1VCO_input * PLL1N)
+ * - PLL1R: ensure that max frequency at 160 MHz is reached (PLL1VCO_output / PLL1R)
+ * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+ * the configuration information for the PLL1.
+ * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+ * the configuration information for the BUS prescalers.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: Max frequency configuration done
+ * - ERROR: Max frequency configuration not done
+ */
+ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+ LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+ ErrorStatus status = SUCCESS;
+ uint32_t pllfreq;
+ uint32_t msi_range;
+
+ /* Check if one of the PLL is enabled */
+ if (UTILS_PLL_IsBusy() == SUCCESS)
+ {
+ /* Get the current MSI range */
+ if (LL_RCC_MSI_IsEnabledRangeSelect() != 0U)
+ {
+ msi_range = LL_RCC_MSIS_GetRange();
+ switch (msi_range)
+ {
+ case LL_RCC_MSISRANGE_15: /* MSI = 100 kHz */
+ case LL_RCC_MSISRANGE_14: /* MSI = 150 kHz */
+ case LL_RCC_MSISRANGE_13: /* MSI = 200 kHz */
+ case LL_RCC_MSISRANGE_12: /* MSI = 400 kHz */
+ case LL_RCC_MSISRANGE_11: /* MSI = 768 kHz */
+ case LL_RCC_MSISRANGE_10: /* MSI = 1.024 MHz*/
+ case LL_RCC_MSISRANGE_9: /* MSI = 1.536 MHz*/
+ case LL_RCC_MSISRANGE_8: /* MSI = 3.072 MHz*/
+ case LL_RCC_MSISRANGE_7: /* MSI = 1 MHz */
+ case LL_RCC_MSISRANGE_6: /* MSI = 1.5 MHz */
+ case LL_RCC_MSISRANGE_5: /* MSI = 2 MHz */
+ /* PLLVCO input frequency is less then 4 MHz*/
+ status = ERROR;
+ break;
+
+ case LL_RCC_MSISRANGE_0: /* MSI = 48 MHz */
+ case LL_RCC_MSISRANGE_1: /* MSI = 24 MHz */
+ case LL_RCC_MSISRANGE_2: /* MSI = 16 MHz */
+ case LL_RCC_MSISRANGE_3: /* MSI = 12 MHz */
+ case LL_RCC_MSISRANGE_4: /* MSI = 4 MHz */
+ default:
+ break;
+ }
+ }
+ else
+ {
+ msi_range = LL_RCC_MSIS_GetRangeAfterStandby();
+ switch (msi_range)
+ {
+ case LL_RCC_MSISSRANGE_5: /* MSI = 2 MHz */
+ case LL_RCC_MSISSRANGE_6: /* MSI = 1.5 MHz */
+ case LL_RCC_MSISSRANGE_7: /* MSI = 1 MHz */
+ case LL_RCC_MSISSRANGE_8: /* MSI = 3.072 MHz*/
+ /* PLLVCO input frequency is less then 4 MHz */
+ status = ERROR;
+ break;
+
+ case LL_RCC_MSISSRANGE_4: /* MSI = 4 MHz */
+ default:
+ break;
+ }
+ }
+
+ /* Main PLL configuration and activation */
+ if (status != ERROR)
+ {
+ /* Calculate the new PLL output frequency */
+ pllfreq = UTILS_GetPLLOutputFrequency(__LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), msi_range),
+ UTILS_PLLInitStruct);
+
+ /* Enable MSI if not enabled */
+ if (LL_RCC_MSIS_IsReady() != 1U)
+ {
+ LL_RCC_MSIS_Enable();
+ while ((LL_RCC_MSIS_IsReady() != 1U))
+ {
+ /* Wait for MSI ready */
+ }
+ }
+
+ /* Configure PLL1 */
+ LL_RCC_PLL1_ConfigDomain_SYS(LL_RCC_PLL1SOURCE_MSIS, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
+ UTILS_PLLInitStruct->PLLR);
+
+ /* Enable PLL and switch system clock to PLL */
+ status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
+
+ }
+ }
+ else
+ {
+ /* Current PLL configuration cannot be modified */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL
+ * @note The application need to ensure that PLL1, PLL2 and/or PLL3 are disabled.
+ * @note Function is based on the following formula:
+ * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLR)
+ * - PLL1M: ensure that the VCO input frequency ranges from 1 to 16 MHz (PLL1VCO_input = MSI frequency / PLL1M)
+ * - PLL1N: ensure that the VCO output frequency is between 4 and 512 MHz
+ (PLL1VCO_output = PLL1VCO_input * PLL1N)
+ * - PLL1R: ensure that max frequency at 160 MHz is reached (PLL1VCO_output / PLL1R)
+ * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+ * the configuration information for the PLL.
+ * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+ * the configuration information for the BUS prescalers.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: Max frequency configuration done
+ * - ERROR: Max frequency configuration not done
+ */
+ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+ LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+ ErrorStatus status;
+ uint32_t pllfreq;
+
+ /* Check if one of the PLL is enabled */
+ if (UTILS_PLL_IsBusy() == SUCCESS)
+ {
+ /* Calculate the new PLL output frequency */
+ pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
+
+ /* Enable HSI if not enabled */
+ if (LL_RCC_HSI_IsReady() != 1U)
+ {
+ LL_RCC_HSI_Enable();
+ while (LL_RCC_HSI_IsReady() != 1U)
+ {
+ /* Wait for HSI ready */
+ }
+ }
+
+ /* Configure PLL */
+ LL_RCC_PLL1_ConfigDomain_SYS(LL_RCC_PLL1SOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
+ UTILS_PLLInitStruct->PLLR);
+
+ /* Enable PLL and switch system clock to PLL */
+ status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
+ }
+ else
+ {
+ /* Current PLL configuration cannot be modified */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief This function configures system clock with HSE as clock source of the PLL
+ * @note The application need to ensure that PLL, PLLSAI1 and/or PLLSAI2 are disabled.
+ * @note Function is based on the following formula:
+ * - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLR)
+ * - PLL1M: ensure that the VCO input frequency ranges from 1 to 16 MHz (PLL1VCO_input = MSI frequency / PLL1M)
+ * - PLL1N: ensure that the VCO output frequency is between 4 and 512 MHz
+ (PLL1VCO_output = PLL1VCO_input * PLL1N)
+ * - PLL1R: ensure that max frequency at 160 MHz is reached (PLL1VCO_output / PLL1R)
+ * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 50000000
+ * @param HSEBypass This parameter can be one of the following values:
+ * @arg @ref LL_UTILS_HSEBYPASS_ON
+ * @arg @ref LL_UTILS_HSEBYPASS_OFF
+ * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+ * the configuration information for the PLL.
+ * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+ * the configuration information for the BUS prescalers.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: Max frequency configuration done
+ * - ERROR: Max frequency configuration not done
+ */
+ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
+ LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+ LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+ ErrorStatus status;
+ uint32_t pllfreq;
+
+ /* Check the parameters */
+ assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
+ assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
+
+ /* Check if one of the PLL is enabled */
+ if (UTILS_PLL_IsBusy() == SUCCESS)
+ {
+ /* Calculate the new PLL output frequency */
+ pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
+
+ /* Enable HSE if not enabled */
+ if (LL_RCC_HSE_IsReady() != 1U)
+ {
+ /* Check if need to enable HSE bypass feature or not */
+ if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
+ {
+ LL_RCC_HSE_EnableBypass();
+ }
+ else
+ {
+ LL_RCC_HSE_DisableBypass();
+ }
+
+ /* Enable HSE */
+ LL_RCC_HSE_Enable();
+ while (LL_RCC_HSE_IsReady() != 1U)
+ {
+ /* Wait for HSE ready */
+ }
+ }
+
+ /* Configure PLL */
+ LL_RCC_PLL1_ConfigDomain_SYS(LL_RCC_PLL1SOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
+ UTILS_PLLInitStruct->PLLR);
+
+ /* Enable PLL and switch system clock to PLL */
+ status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
+ }
+ else
+ {
+ /* Current PLL configuration cannot be modified */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup UTILS_LL_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Function to check that PLL can be modified
+ * @param PLL_InputFrequency PLL input frequency (in Hz)
+ * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+ * the configuration information for the PLL.
+ * @retval PLL output frequency (in Hz)
+ */
+static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
+{
+ uint32_t pllfreq;
+
+ /* Check the parameters */
+ assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
+ assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
+ assert_param(IS_LL_UTILS_PLLR_VALUE(UTILS_PLLInitStruct->PLLR));
+
+ /* Check different PLL parameters according to RM */
+ /* - PLLM: ensure that the VCO input frequency ranges from 1 to 16 MHz. */
+ pllfreq = PLL_InputFrequency / (UTILS_PLLInitStruct->PLLM);
+ assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq));
+
+ /* - PLLN: ensure that the VCO output frequency is between 4 and 512 MHz.*/
+ pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN);
+ assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));
+
+ /* - PLLR: ensure that max frequency at 160 MHz is reached */
+ pllfreq = pllfreq / (UTILS_PLLInitStruct->PLLR);
+ assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
+
+ return pllfreq;
+}
+
+/**
+ * @brief Function to check that PLL can be modified
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: PLL modification can be done
+ * - ERROR: PLL is busy
+ */
+static ErrorStatus UTILS_PLL_IsBusy(void)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check if PLL1 is busy*/
+ if (LL_RCC_PLL1_IsReady() != 0U)
+ {
+ /* PLL configuration cannot be modified */
+ status = ERROR;
+ }
+
+ /* Check if PLL2 is busy*/
+ if (LL_RCC_PLL2_IsReady() != 0U)
+ {
+ /* PLL2 configuration cannot be modified */
+ status = ERROR;
+ }
+
+ /* Check if PLL3 is busy*/
+ if (LL_RCC_PLL3_IsReady() != 0U)
+ {
+ /* PLL3 configuration cannot be modified */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Function to enable PLL and switch system clock to PLL
+ * @param SYSCLK_Frequency SYSCLK frequency
+ * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+ * the configuration information for the BUS prescalers.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: No problem to switch system to PLL
+ * - ERROR: Problem to switch system to PLL
+ */
+static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency,
+ LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+ ErrorStatus status = SUCCESS;
+ uint32_t hclk_frequency;
+
+ assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
+ assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
+ assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
+ assert_param(IS_LL_UTILS_APB3_DIV(UTILS_ClkInitStruct->APB3CLKDivider));
+
+ /* Calculate HCLK frequency */
+ hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
+
+ /* Increasing the number of wait states because of higher CPU frequency */
+ if (SystemCoreClock < hclk_frequency)
+ {
+ /* Set FLASH latency to highest latency */
+ status = LL_SetFlashLatency(hclk_frequency);
+ }
+
+ /* Update system clock configuration */
+ if (status == SUCCESS)
+ {
+ /* Enable PLL1 */
+ LL_RCC_PLL1_Enable();
+ LL_RCC_PLL1_EnableDomain_SYS();
+ while (LL_RCC_PLL1_IsReady() != 1U)
+ {
+ /* Wait for PLL ready */
+ }
+
+ /* Sysclk activation on the main PLL */
+ LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
+ LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1);
+ while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1)
+ {
+ /* Wait for system clock switch to PLL */
+ }
+
+ /* Set APB1, APB2 & APB3 prescaler*/
+ LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
+ LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
+ LL_RCC_SetAPB3Prescaler(UTILS_ClkInitStruct->APB3CLKDivider);
+ }
+
+ /* Decreasing the number of wait states because of lower CPU frequency */
+ if (SystemCoreClock > hclk_frequency)
+ {
+ /* Set FLASH latency to lowest latency */
+ status = LL_SetFlashLatency(hclk_frequency);
+ }
+
+ /* Update SystemCoreClock variable */
+ if (status == SUCCESS)
+ {
+ LL_SetSystemCoreClock(hclk_frequency);
+ }
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/LICENSE.md b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/LICENSE.md
new file mode 100644
index 00000000..3f81ab29
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/LICENSE.md
@@ -0,0 +1,28 @@
+| Component | Copyright | License |
+|:--------- |:---------- |:------- |
+| CMSIS Core | ARM Limited | Apache License 2.0 |
+| CMSIS Device | ARM Limited, STMicroelectronics | Apache License 2.0 |
+| Drivers HAL/LL | STMicroelectronics | BSD 3-Clause |
+| BSP STM32U575I-EV | STMicroelectronics | BSD 3-Clause |
+| BSP STM32U5xx NUCLEO | STMicroelectronics | BSD 3-Clause |
+| BSP B-U585I-IOT02A | STMicroelectronics | BSD 3-Clause |
+| BSP Components | STMicroelectronics | BSD 3-Clause |
+| BSP MXCHIP | STMicroelectronics | Proprietary |
+| Aure RTOS ThreadX | Microsoft Corporation | Microsoft Software License for Azure RTOS |
+| Aure RTOS NetXDuo | Microsoft Corporation | Microsoft Software License for Azure RTOS |
+| Aure RTOS FileX | Microsoft Corporation | Microsoft Software License for Azure RTOS |
+| Aure RTOS LeveLX | Microsoft Corporation | Microsoft Software License for Azure RTOS |
+| Aure RTOS USBX | Microsoft Corporation | Microsoft Software License for Azure RTOS |
+| STM32 TouchSensing Library | STMicroelectronics | Proprietary |
+| STM32 USBPD Core Library | STMicroelectronics | Proprietary |
+| STM32 USBPD Device Library | STMicroelectronics | Proprietary |
+| OpenBootloader | STMicroelectronics | Proprietary |
+| Network Library | STMicroelectronics, ARM Limited | Proprietary |
+| mbed-crypto | Arm Limited (or its affiliates) | Apache License 2.0 |
+| mcuboot | Linaro Limited, Arm Limited (or its affiliates), JUUL Labs, Nordic Semiconductor ASA, Cypress Semiconductor Corporation, Runtime Inc, Open Source Foundries Limited, Intel Corporation, Wind River Systems, Inc., The Linux Foundation and its contributors, the fiat-crypto authors, Chris Morrison, Kenneth MacKay | Apache License 2.0 |
+| trustedfirmware | ARM Limited, Wind River Systems, Inc., Linaro Limited, Laurence Lundblade, The Linux Foundation, IETF Trust and the persons identified as the document authors | BSD 3-Clause |
+| Utilities | STMicroelectronics | BSD 3-Clause |
+| Utilities/LPBAM | STMicroelectronics | Proprietary |
+| Applications projects | STMicroelectronics | Proprietary |
+| Demonstrations projects | STMicroelectronics | Proprietary |
+| Example Projects | STMicroelectronics | BSD 3-Clause |
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/README.md b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/README.md
new file mode 100644
index 00000000..9bde8a46
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/README.md
@@ -0,0 +1,30 @@
+# STM32CubeU5 MCU Firmware Package
+
+
+
+**STM32Cube** is an STMicroelectronics original initiative to ease the developers life by reducing efforts, time and cost.
+
+**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform (this repo), delivered for each series (such as the STM32CubeU5 for the STM32U5 series).
+ * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product.
+ * The STM32 HAL-LL drivers, an abstraction layer offering a set of APIs ensuring maximized portability across the STM32 portfolio.
+ * The BSP drivers of each evaluation, demonstration or nucleo board provided for this STM32 series.
+ * A consistent set of middleware libraries such as ThreadX, FileX, USBX, NetDuoX, OpenBootloader, USBPD, trustedfirmware, mbed-crypto, mbedTLS, Network Library...
+ * A full set of software projects (basic examples, applications, and demonstrations) for each board provided for this STM32 series.
+ * A new LPBAM utility which is a software helper that assists STM32U5 users in the elaboration of LPBAM scenarios.
+ * A development with three Toolchains and Compilers (IAR Embedded Workbench for ARM (EWARM), RealView Microcontroller Development Kit (MDK-ARM), and STM32CubeIDE).
+
+The **STM32CubeU5 MCU Package** projects are directly running on the STM32U5 series boards. You can find in each Projects/*Board name* directories a set of software projects (Applications, Demonstration, Examples).
+
+## Release note
+
+Details about the content of this release are available in the release note [here](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/STM32CubeU5/blob/main/Release_Notes.html).
+
+## Boards available
+ * STM32U5
+ * [B-U585I-IOT02A](https://www.st.com/en/evaluation-tools/b-u585i-iot02a.html)
+ * [NUCLEO-U575ZI-Q](https://www.st.com/en/evaluation-tools/nucleo-u575zi-q.html)
+ * [STM32U575I-EV](https://www.st.com/en/evaluation-tools/stm32u575i-ev.html)
+
+## Troubleshooting
+
+Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide.
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/netx_driver/mxchip/mx_wifi_azure_rtos.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/netx_driver/mxchip/mx_wifi_azure_rtos.c
new file mode 100644
index 00000000..41ab5c0a
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/netx_driver/mxchip/mx_wifi_azure_rtos.c
@@ -0,0 +1,179 @@
+#include "mx_wifi.h"
+#define NX_DRIVER_SOURCE
+#include "nx_driver_emw3080.h"
+
+
+extern TX_THREAD * _tx_thread_current_ptr;
+
+extern NX_DRIVER_INFORMATION nx_driver_information;
+
+
+#define mx_wifi_byte_pool_size (1024 * 4) /* less than 3k is actually used */
+static ULONG mx_wifi_byte_pool_buffer[mx_wifi_byte_pool_size / sizeof (ULONG)];
+static TX_BYTE_POOL mx_wifi_byte_pool;
+
+UINT mx_wifi_alloc_init()
+{
+ if (tx_byte_pool_create(
+ &mx_wifi_byte_pool,
+ "MX WiFi byte pool",
+ mx_wifi_byte_pool_buffer,
+ mx_wifi_byte_pool_size))
+ {
+ return NX_DRIVER_ERROR;
+ }
+
+ return NX_SUCCESS;
+}
+
+void * mx_wifi_malloc(size_t size)
+{
+ UINT status;
+ void * p = NULL;
+
+ status = tx_byte_allocate(
+ &mx_wifi_byte_pool,
+ &p,
+ size,
+ TX_NO_WAIT);
+ if (status != TX_SUCCESS)
+ {
+ return NULL;
+ }
+
+ MX_ASSERT(p);
+
+ return p;
+}
+
+void mx_wifi_free(void * p)
+{
+ UINT status;
+
+ MX_ASSERT(p);
+
+ status = tx_byte_release(p);
+ MX_ASSERT(status == NX_SUCCESS);
+}
+
+NX_PACKET *mx_net_buffer_alloc(uint32_t n)
+{
+ UINT status;
+ NX_PACKET * packet_ptr;
+
+ if (!nx_driver_information.nx_driver_information_packet_pool_ptr)
+ return NULL;
+
+ if (n > nx_driver_information.nx_driver_information_packet_pool_ptr->nx_packet_pool_payload_size)
+ return NULL;
+
+ status = nx_packet_allocate(
+ nx_driver_information.nx_driver_information_packet_pool_ptr,
+ &packet_ptr,
+ NX_RECEIVE_PACKET,
+ NX_NO_WAIT);
+ if (status != NX_SUCCESS)
+ {
+ MX_STAT_LOG();
+ return NULL;
+ }
+
+ MX_ASSERT(packet_ptr);
+
+ MX_STAT(alloc);
+ packet_ptr->nx_packet_next = NULL;
+ packet_ptr->nx_packet_prepend_ptr += 2;
+ packet_ptr->nx_packet_append_ptr = packet_ptr->nx_packet_prepend_ptr + n;
+ packet_ptr->nx_packet_length = n;
+ MX_ASSERT(packet_ptr->nx_packet_append_ptr <= packet_ptr->nx_packet_data_end);
+
+ return packet_ptr;
+}
+
+void mx_net_buffer_free(NX_PACKET * packet_ptr)
+{
+ UINT status;
+
+ MX_ASSERT(packet_ptr);
+ MX_STAT(free);
+ status = nx_packet_release(packet_ptr);
+ MX_ASSERT(status == NX_SUCCESS);
+}
+
+UINT mx_wifi_thread_init(TX_THREAD * thread_ptr, CHAR *name_ptr, VOID (*entry_function)(ULONG), ULONG entry_input, ULONG stack_size, UINT priority)
+{
+ // Do not worry about alignment, it is handled by tx_thread_create
+ void * stack = mx_wifi_malloc(stack_size);
+ MX_ASSERT(stack);
+ if (!stack)
+ return TX_NO_MEMORY;
+
+ return tx_thread_create(
+ thread_ptr,
+ name_ptr,
+ entry_function, entry_input,
+ stack, stack_size,
+ priority, priority,
+ TX_NO_TIME_SLICE,
+ TX_AUTO_START);
+}
+
+UINT mx_wifi_thread_deinit(TX_THREAD * thread_ptr)
+{
+ MX_ASSERT(thread_ptr);
+ MX_ASSERT(thread_ptr->tx_thread_stack_start);
+
+ mx_wifi_free(thread_ptr->tx_thread_stack_start);
+
+ return tx_thread_delete(thread_ptr);
+}
+
+void mx_wifi_thread_terminate()
+{
+ tx_thread_terminate(_tx_thread_current_ptr);
+}
+
+UINT mx_wifi_fifo_init(TX_QUEUE * queue_ptr, CHAR *name_ptr, ULONG size)
+{
+ void * queue_start = mx_wifi_malloc(size * TX_1_ULONG * sizeof(ULONG));
+ MX_ASSERT(queue_start);
+ if (!queue_start)
+ return TX_NO_MEMORY;
+
+ return tx_queue_create(
+ queue_ptr,
+ name_ptr,
+ TX_1_ULONG,
+ queue_start,
+ size*sizeof(ULONG));
+}
+
+UINT mx_wifi_fifo_deinit(TX_QUEUE * queue_ptr)
+{
+ MX_ASSERT(queue_ptr);
+ MX_ASSERT(queue_ptr->tx_queue_start);
+
+ mx_wifi_free(queue_ptr->tx_queue_start);
+
+ return tx_queue_delete(queue_ptr);
+}
+
+UINT mx_wifi_fifo_push(TX_QUEUE * queue_ptr, void * source_ptr, ULONG wait_option)
+{
+ MX_ASSERT(queue_ptr);
+
+ return tx_queue_send(queue_ptr, source_ptr, wait_option);
+}
+
+void * mx_wifi_fifo_pop(TX_QUEUE * queue_ptr, ULONG wait_option)
+{
+ void * destination_ptr;
+
+ MX_ASSERT(queue_ptr);
+
+ UINT status = tx_queue_receive(queue_ptr, &destination_ptr, wait_option);
+ if (status != TX_SUCCESS)
+ return NULL;
+
+ return destination_ptr;
+}
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/netx_driver/mxchip/mx_wifi_azure_rtos_conf.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/netx_driver/mxchip/mx_wifi_azure_rtos_conf.h
new file mode 100644
index 00000000..1fe4a315
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/netx_driver/mxchip/mx_wifi_azure_rtos_conf.h
@@ -0,0 +1,146 @@
+/**
+ ******************************************************************************
+ * @file mx_wifi_azure_rtos_conf.h
+ * @author MCD Application Team
+ * @brief Header for mx_wifi_azure_rtos module
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
+#include
+
+#include "nx_api.h"
+#include "tx_api.h"
+
+UINT mx_wifi_alloc_init();
+void* mx_wifi_malloc(size_t size);
+void mx_wifi_free(void* p);
+
+#define MX_WIFI_MALLOC(size) mx_wifi_malloc(size)
+#define MX_WIFI_FREE(p) mx_wifi_free(p)
+
+#define NET_MALLOC(size) mx_wifi_malloc(size)
+#define NET_FREE(p) mx_wifi_free(p)
+
+
+typedef NX_PACKET mx_buf_t;
+
+NX_PACKET* mx_net_buffer_alloc(uint32_t n);
+void mx_net_buffer_free(NX_PACKET* nx_packet);
+
+#define MX_NET_BUFFER_ALLOC mx_net_buffer_alloc
+#define MX_NET_BUFFER_FREE mx_net_buffer_free
+#define MX_NET_BUFFER_PAYLOAD(packet_ptr) packet_ptr->nx_packet_prepend_ptr
+#define MX_NET_BUFFER_SET_PAYLOAD_SIZE(packet_ptr, n) \
+ do \
+ { \
+ packet_ptr->nx_packet_length = n; \
+ packet_ptr->nx_packet_append_ptr = packet_ptr->nx_packet_prepend_ptr + n; \
+ } while (0)
+#define MX_NET_BUFFER_GET_PAYLOAD_SIZE(packet_ptr) packet_ptr->nx_packet_length
+#define MX_NET_BUFFER_HIDE_HEADER(packet_ptr, n) \
+ do \
+ { \
+ packet_ptr->nx_packet_prepend_ptr += n; \
+ packet_ptr->nx_packet_length -= n; \
+ } while (0)
+
+#define DELAYms(n) \
+ do \
+ { \
+ if (n == 1) \
+ { \
+ tx_thread_relinquish(); \
+ } \
+ else \
+ { \
+ tx_thread_sleep(TX_TIMER_TICKS_PER_SECOND* n / 1000); \
+ } \
+ } while (0)
+
+#define MX_ASSERT(a) \
+ do \
+ { \
+ } while (!(a))
+
+#define LOCK_DECLARE(A) TX_MUTEX A
+#define LOCK_INIT(A) tx_mutex_create(&A, #A, TX_NO_INHERIT)
+#define LOCK_DEINIT(A) tx_mutex_delete(&A)
+#define LOCK(A) tx_mutex_get(&A, TX_WAIT_FOREVER)
+#define UNLOCK(A) tx_mutex_put(&A)
+
+#define SEM_DECLARE(A) TX_SEMAPHORE A
+#define SEM_INIT(A, COUNT) tx_semaphore_create(&A, #A, 0)
+#define SEM_DEINIT(A) tx_semaphore_delete(&A)
+#define SEM_SIGNAL(A) tx_semaphore_put(&A)
+#define SEM_WAIT(A, TIMEOUT, IDLE_FUNC) tx_semaphore_get(&A, TIMEOUT)
+
+ UINT mx_wifi_thread_init(TX_THREAD* thread_ptr,
+ CHAR* name_ptr,
+ VOID (*entry_function)(ULONG),
+ ULONG entry_input,
+ ULONG stack_size,
+ UINT priority);
+ UINT mx_wifi_thread_deinit(TX_THREAD* thread_ptr);
+ void mx_wifi_thread_terminate();
+
+#define THREAD_CONTEXT_TYPE ULONG
+
+#define OSPRIORITYNORMAL 5
+#define OSPRIORITYABOVENORMAL 4
+#define OSPRIORITYREALTIME 1
+
+#define THREAD_DECLARE(A) TX_THREAD A
+#define THREAD_INIT(A, THREAD_FUNC, THREAD_CONTEXT, STACKSIZE, PRIORITY) \
+ mx_wifi_thread_init(&A, #A, (VOID(*)(ULONG))THREAD_FUNC, (ULONG)THREAD_CONTEXT, STACKSIZE, PRIORITY)
+#define THREAD_DEINIT(A) mx_wifi_thread_deinit(&A)
+#define THREAD_TERMINATE() mx_wifi_thread_terminate()
+
+ UINT mx_wifi_fifo_init(TX_QUEUE* queue_ptr, char* name_ptr, ULONG size);
+ UINT mx_wifi_fifo_deinit(TX_QUEUE* queue_ptr);
+ UINT mx_wifi_fifo_push(TX_QUEUE* queue_ptr, void* source_ptr, ULONG wait_option);
+ void* mx_wifi_fifo_pop(TX_QUEUE* queue_ptr, ULONG wait_option);
+
+#define FIFO_DECLARE(QUEUE) TX_QUEUE QUEUE
+#define FIFO_INIT(QUEUE, QSIZE) mx_wifi_fifo_init(&QUEUE, #QUEUE, QSIZE)
+#define FIFO_DEINIT(QUEUE) mx_wifi_fifo_deinit(&QUEUE)
+#define FIFO_PUSH(QUEUE, VALUE, TIMEOUT, IDLE_FUNC) mx_wifi_fifo_push(&QUEUE, &VALUE, TIMEOUT)
+#define FIFO_POP(QUEUE, TIMEOUT, IDLE_FUNC) mx_wifi_fifo_pop(&QUEUE, TIMEOUT)
+
+#define WAIT_FOREVER TX_WAIT_FOREVER
+#define SEM_OK TX_SUCCESS
+#define THREAD_OK TX_SUCCESS
+#define FIFO_OK TX_SUCCESS
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MX_WIFI_AZURE_RTOS_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/netx_driver/mxchip/nx_driver_emw3080.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/netx_driver/mxchip/nx_driver_emw3080.c
new file mode 100644
index 00000000..7d960391
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/netx_driver/mxchip/nx_driver_emw3080.c
@@ -0,0 +1,240 @@
+#include
+
+#include "nx_api.h"
+#include "mx_wifi.h"
+#ifndef NX_DRIVER_DEFERRED_PROCESSING
+#error The symbol NX_DRIVER_DEFERRED_PROCESSING should be defined
+#endif
+
+#define NX_DRIVER_ENABLE_DEFERRED
+
+/* Indicate that driver source is being compiled. */
+#define NX_DRIVER_SOURCE
+
+#include "nx_driver_emw3080.h"
+#include "nx_driver_framework.c"
+
+
+extern MX_WIFIObject_t * wifi_obj_get(void);
+extern int32_t mxwifi_probe();
+
+static void _nx_netlink_input_callback(mx_buf_t *pbuf,void *user_args);
+static void _nx_mx_wifi_status_changed(uint8_t cate, uint8_t status, void * arg);
+
+static UINT _nx_driver_emw3080_initialize(NX_IP_DRIVER *driver_req_ptr);
+static UINT _nx_driver_emw3080_enable(NX_IP_DRIVER *driver_req_ptr);
+static UINT _nx_driver_emw3080_disable(NX_IP_DRIVER *driver_req_ptr);
+static UINT _nx_driver_emw3080_packet_send(NX_PACKET *packet_ptr);
+static VOID _nx_driver_emw3080_packet_received(VOID);
+
+static volatile bool nx_driver_interface_up = false;
+static volatile bool nx_driver_ip_acquired = false;
+
+
+void nx_driver_emw3080_entry(NX_IP_DRIVER *driver_req_ptr)
+{
+ static bool start = false;
+ if (!start)
+ {
+ nx_driver_hardware_initialize = _nx_driver_emw3080_initialize;
+ nx_driver_hardware_enable = _nx_driver_emw3080_enable;
+ nx_driver_hardware_disable = _nx_driver_emw3080_disable;
+ nx_driver_hardware_packet_send = _nx_driver_emw3080_packet_send;
+ nx_driver_hardware_packet_received = _nx_driver_emw3080_packet_received;
+
+ start = true;
+ }
+
+ nx_driver_framework_entry_default(driver_req_ptr);
+}
+
+void nx_driver_emw3080_interrupt()
+{
+ULONG deffered_events;
+
+ if (!nx_driver_interface_up || !nx_driver_ip_acquired)
+ return; /* not yet running */
+
+ deffered_events = nx_driver_information.nx_driver_information_deferred_events;
+
+ nx_driver_information.nx_driver_information_deferred_events |= NX_DRIVER_DEFERRED_PACKET_RECEIVED;
+
+ if (!deffered_events)
+ {
+ /* Call NetX deferred driver processing. */
+ _nx_ip_driver_deferred_processing(nx_driver_information.nx_driver_information_ip_ptr);
+ }
+}
+
+UINT _nx_driver_emw3080_initialize(NX_IP_DRIVER *driver_req_ptr)
+{
+ MX_WIFIObject_t * pMxWifiObj = wifi_obj_get();
+
+ if (mx_wifi_alloc_init())
+ {
+ return NX_DRIVER_ERROR;
+ }
+
+ if (mxwifi_probe((void **)&pMxWifiObj))
+ {
+ return NX_DRIVER_ERROR;
+ }
+
+ if (MX_WIFI_HardResetModule(pMxWifiObj))
+ {
+ return NX_DRIVER_ERROR;
+ }
+
+ /* wait for mxchip wifi reboot */
+ tx_thread_sleep(TX_TIMER_TICKS_PER_SECOND * 800 / 1000);
+
+ if (MX_WIFI_Init(pMxWifiObj))
+ {
+ return NX_DRIVER_ERROR;
+ }
+
+ nx_driver_update_hardware_address(pMxWifiObj->SysInfo.MAC);
+
+ if (MX_WIFI_RegisterStatusCallback_if(
+ pMxWifiObj,
+ _nx_mx_wifi_status_changed,
+ NULL /* void * arg */,
+ (mwifi_if_t)MC_STATION))
+ {
+ return NX_DRIVER_ERROR;
+ }
+
+ return NX_SUCCESS;
+}
+
+UINT _nx_driver_emw3080_enable(NX_IP_DRIVER *driver_req_ptr)
+{
+ MX_WIFIObject_t *pMxWifiObj = wifi_obj_get();
+
+ if (MX_WIFI_STATUS_OK != MX_WIFI_Network_bypass_mode_set(
+ pMxWifiObj,
+ 1 /* enable */,
+ _nx_netlink_input_callback,
+ NULL /* user arg */))
+ {
+ return NX_DRIVER_ERROR;
+ }
+
+ return NX_SUCCESS;
+}
+
+UINT _nx_driver_emw3080_disable(NX_IP_DRIVER *driver_req_ptr)
+{
+ MX_WIFIObject_t *pMxWifiObj = wifi_obj_get();
+
+ MX_WIFI_Network_bypass_mode_set(
+ pMxWifiObj,
+ 0 /* disable */,
+ NULL,
+ NULL);
+
+ return NX_SUCCESS;
+}
+
+UINT _nx_driver_emw3080_packet_send(NX_PACKET *packet_ptr)
+{
+ MX_WIFIObject_t *pMxWifiObj = wifi_obj_get();
+
+ static int errors = 0;
+
+ // verify that the length matches the size between the pointers
+ if ((int)packet_ptr->nx_packet_length != (packet_ptr->nx_packet_append_ptr - packet_ptr->nx_packet_prepend_ptr))
+ {
+ return NX_DRIVER_ERROR;
+ }
+
+ // TODO: chained packets not currently supported
+ if (packet_ptr->nx_packet_next)
+ {
+ NX_DRIVER_PHYSICAL_HEADER_REMOVE(packet_ptr);
+ nx_packet_transmit_release(packet_ptr);
+ return NX_DRIVER_ERROR;
+ }
+
+ if ((packet_ptr->nx_packet_prepend_ptr - packet_ptr->nx_packet_data_start) < 28)
+ {
+ printf("Uncorrect NX packet ,need at least 28 byte in front of payload , got %d\n",packet_ptr->nx_packet_prepend_ptr - packet_ptr->nx_packet_data_start);
+ }
+
+ if (MX_WIFI_Network_bypass_netlink_output(
+ pMxWifiObj,
+ packet_ptr->nx_packet_prepend_ptr, packet_ptr->nx_packet_length,
+ (int32_t)STATION_IDX))
+ {
+ errors++;
+ }
+
+ NX_DRIVER_PHYSICAL_HEADER_REMOVE(packet_ptr);
+ nx_packet_transmit_release(packet_ptr);
+
+ return NX_SUCCESS;
+}
+
+static void _nx_netlink_input_callback(mx_buf_t *buffer, void *user_args) // (void *pbuf, int32_t size, void *data, int32_t len, void *user_args)
+{
+ NX_PACKET * packet_ptr = buffer;
+
+ /* Avoid starving. */
+ if (packet_ptr -> nx_packet_pool_owner -> nx_packet_pool_available == 0)
+ {
+ nx_packet_release(packet_ptr);
+ return;
+ }
+
+ /* Everything is OK, transfer the packet to NetX. */
+ nx_driver_transfer_to_netx(nx_driver_information.nx_driver_information_ip_ptr, packet_ptr);
+}
+
+static VOID _nx_driver_emw3080_packet_received(VOID)
+{
+ MX_WIFIObject_t *pMxWifiObj = wifi_obj_get();
+
+ MX_WIFI_IO_YIELD(pMxWifiObj, 100 /* timeout */);
+}
+
+static void _nx_mx_wifi_status_changed(uint8_t cate, uint8_t status, void * arg)
+{
+ if ((uint8_t)MC_STATION == cate)
+ {
+ switch (status)
+ {
+ case MWIFI_EVENT_STA_DOWN:
+ nx_driver_interface_up = false;
+ break;
+
+ case MWIFI_EVENT_STA_UP:
+ nx_driver_interface_up = true;
+ break;
+
+ case MWIFI_EVENT_STA_GOT_IP:
+ nx_driver_ip_acquired = true;
+ break;
+
+ default:
+ break;
+ }
+ }
+ else if ((uint8_t)MC_SOFTAP == cate)
+ {
+ switch (status)
+ {
+ case MWIFI_EVENT_AP_DOWN:
+ break;
+
+ case MWIFI_EVENT_AP_UP:
+ break;
+
+ default:
+ break;
+ }
+ }
+ else
+ {
+ /* nothing */
+ }
+}
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/netx_driver/mxchip/nx_driver_emw3080.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/netx_driver/mxchip/nx_driver_emw3080.h
new file mode 100644
index 00000000..8d9cddaa
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/netx_driver/mxchip/nx_driver_emw3080.h
@@ -0,0 +1,45 @@
+/**************************************************************************/
+/* */
+/* Copyright (c) Microsoft Corporation. All rights reserved. */
+/* */
+/* This software is licensed under the Microsoft Software License */
+/* Terms for Microsoft Azure RTOS. Full text of the license can be */
+/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
+/* and in the root directory of this software. */
+/* */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/* */
+/* */
+/* NetX Component */
+/* */
+/* MX CHIP EMW3080 WiFi driver for the STM32 family of microprocessors */
+/* */
+/* */
+/**************************************************************************/
+
+#ifndef NX_DRIVER_EMW3080_H
+#define NX_DRIVER_EMW3080_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Indicate that driver source is being compiled. */
+#define NX_DRIVER_SOURCE
+
+/* Include driver framework include file. */
+#include "nx_driver_framework.h"
+
+/* Public API */
+void nx_driver_emw3080_entry(NX_IP_DRIVER *driver_req_ptr);
+void nx_driver_emw3080_interrupt();
+
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/netx_driver/mxchip/nx_driver_framework.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/netx_driver/mxchip/nx_driver_framework.c
new file mode 100644
index 00000000..860dea14
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/netx_driver/mxchip/nx_driver_framework.c
@@ -0,0 +1,1502 @@
+/**************************************************************************/
+/* */
+/* Copyright (c) Microsoft Corporation. All rights reserved. */
+/* */
+/* This software is licensed under the Microsoft Software License */
+/* Terms for Microsoft Azure RTOS. Full text of the license can be */
+/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
+/* and in the root directory of this software. */
+/* */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/** */
+/** NetX Component */
+/** */
+/** NetX driver framework */
+/** */
+/**************************************************************************/
+/**************************************************************************/
+
+/* Check that this file is included by the driver source and not compiled directly */
+#ifndef NX_DRIVER_SOURCE
+#error This file is included by the driver source, not compiled directly.
+#endif
+
+/* Include driver framework include file. */
+#include "nx_driver_framework.h"
+
+NX_DRIVER_INFORMATION nx_driver_information;
+
+static VOID nx_driver_framework_entry_default(NX_IP_DRIVER *driver_req_ptr);
+
+/* Define the routines for processing each driver entry request. */
+static VOID nx_driver_interface_attach(NX_IP_DRIVER *driver_req_ptr);
+static VOID nx_driver_initialize(NX_IP_DRIVER *driver_req_ptr);
+static VOID nx_driver_enable(NX_IP_DRIVER *driver_req_ptr);
+static VOID nx_driver_disable(NX_IP_DRIVER *driver_req_ptr);
+static VOID nx_driver_disable(NX_IP_DRIVER *driver_req_ptr);
+static VOID nx_driver_packet_send(NX_IP_DRIVER *driver_req_ptr);
+static VOID nx_driver_packet_send(NX_IP_DRIVER *driver_req_ptr);
+static VOID nx_driver_multicast_join(NX_IP_DRIVER *driver_req_ptr);
+static VOID nx_driver_multicast_join(NX_IP_DRIVER *driver_req_ptr);
+static VOID nx_driver_multicast_leave(NX_IP_DRIVER *driver_req_ptr);
+static VOID nx_driver_multicast_leave(NX_IP_DRIVER *driver_req_ptr);
+static VOID nx_driver_get_status(NX_IP_DRIVER *driver_req_ptr);
+static VOID nx_driver_get_status(NX_IP_DRIVER *driver_req_ptr);
+#ifdef NX_ENABLE_INTERFACE_CAPABILITY
+static VOID nx_driver_capability_get(NX_IP_DRIVER *driver_req_ptr);
+static VOID nx_driver_capability_set(NX_IP_DRIVER *driver_req_ptr);
+#endif /* NX_ENABLE_INTERFACE_CAPABILITY */
+#ifdef NX_DRIVER_ENABLE_DEFERRED
+static VOID nx_driver_deferred_processing(NX_IP_DRIVER *driver_req_ptr);
+#endif /* NX_DRIVER_ENABLE_DEFERRED */
+static VOID nx_driver_transfer_to_netx(NX_IP *ip_ptr, NX_PACKET *packet_ptr);
+static VOID nx_driver_update_hardware_address(UCHAR hardware_address[6]);
+#ifdef NX_DRIVER_INTERNAL_TRANSMIT_QUEUE
+static VOID nx_driver_transmit_packet_enqueue(NX_PACKET *packet_ptr)
+static NX_PACKET * nx_driver_transmit_packet_dequeue(VOID)
+#endif /* NX_DRIVER_INTERNAL_TRANSMIT_QUEUE */
+
+
+/* Define the pointers for the hardware implementation of this driver. */
+static UINT (*nx_driver_hardware_initialize)(NX_IP_DRIVER *driver_req_ptr) = NULL;
+static UINT (*nx_driver_hardware_enable)(NX_IP_DRIVER *driver_req_ptr) = NULL;
+static UINT (*nx_driver_hardware_disable)(NX_IP_DRIVER *driver_req_ptr) = NULL;
+static UINT (*nx_driver_hardware_packet_send)(NX_PACKET *packet_ptr) = NULL;
+static UINT (*nx_driver_hardware_multicast_join)(NX_IP_DRIVER *driver_req_ptr) = NULL;
+static UINT (*nx_driver_hardware_multicast_leave)(NX_IP_DRIVER *driver_req_ptr) = NULL;
+static UINT (*nx_driver_hardware_get_status)(NX_IP_DRIVER *driver_req_ptr) = NULL;
+static VOID (*nx_driver_hardware_packet_transmitted)(VOID) = NULL;
+static VOID (*nx_driver_hardware_packet_received)(VOID) = NULL;
+#ifdef NX_ENABLE_INTERFACE_CAPABILITY
+static UINT (*nx_driver_hardware_capability_set)(NX_IP_DRIVER *driver_req_ptr) = NULL;
+#endif /* NX_ENABLE_INTERFACE_CAPABILITY */
+
+
+/**************************************************************************/
+/* */
+/* FUNCTION RELEASE */
+/* */
+/* nx_driver_framework_entry_default PORTABLE C */
+/* 6.x */
+/* AUTHOR */
+/* */
+/* Andres Mlinar, Microsoft Corporation */
+/* */
+/* DESCRIPTION */
+/* */
+/* This is the default entry point processing for the NetX Driver. */
+/* This function should be called by a specific driver to handle */
+/* commands. */
+/* */
+/* INPUT */
+/* */
+/* driver_req_ptr The driver request from the */
+/* IP layer. */
+/* */
+/* OUTPUT */
+/* */
+/* None */
+/* */
+/* CALLS */
+/* */
+/* nx_driver_interface_attach Process attach request */
+/* nx_driver_initialize Process initialize request */
+/* nx_driver_enable Process link enable request */
+/* nx_driver_disable Process link disable request */
+/* nx_driver_packet_send Process send packet requests */
+/* nx_driver_multicast_join Process multicast join request*/
+/* nx_driver_multicast_leave Process multicast leave req */
+/* nx_driver_get_status Process get status request */
+/* nx_driver_deferred_processing Drive deferred processing */
+/* */
+/* CALLED BY */
+/* */
+/* IP layer */
+/* */
+/* RELEASE HISTORY */
+/* */
+/* DATE NAME DESCRIPTION */
+/* */
+/* xx-xx-xxxx Andres Mlinar Initial Version 6.x */
+/* */
+/**************************************************************************/
+VOID nx_driver_framework_entry_default(NX_IP_DRIVER *driver_req_ptr)
+{
+
+ /* Default to successful return. */
+ driver_req_ptr -> nx_ip_driver_status = NX_SUCCESS;
+
+ /* Process according to the driver request type in the IP control block. */
+ switch (driver_req_ptr -> nx_ip_driver_command)
+ {
+
+ case NX_LINK_INTERFACE_ATTACH:
+
+ /* Process link interface attach requests. */
+ nx_driver_interface_attach(driver_req_ptr);
+ break;
+
+ case NX_LINK_INITIALIZE:
+ {
+
+ /* Process link initialize requests. */
+ nx_driver_initialize(driver_req_ptr);
+ break;
+ }
+
+ case NX_LINK_ENABLE:
+ {
+
+ /* Process link enable requests. */
+ nx_driver_enable(driver_req_ptr);
+ break;
+ }
+
+ case NX_LINK_DISABLE:
+ {
+
+ /* Process link disable requests. */
+ nx_driver_disable(driver_req_ptr);
+ break;
+ }
+
+ case NX_LINK_ARP_SEND:
+ case NX_LINK_ARP_RESPONSE_SEND:
+ case NX_LINK_PACKET_BROADCAST:
+ case NX_LINK_RARP_SEND:
+ case NX_LINK_PACKET_SEND:
+ {
+
+ /* Process packet send requests. */
+ nx_driver_packet_send(driver_req_ptr);
+ break;
+ }
+
+ case NX_LINK_MULTICAST_JOIN:
+ {
+
+ /* Process multicast join requests. */
+ nx_driver_multicast_join(driver_req_ptr);
+ break;
+ }
+
+ case NX_LINK_MULTICAST_LEAVE:
+ {
+
+ /* Process multicast leave requests. */
+ nx_driver_multicast_leave(driver_req_ptr);
+ break;
+ }
+
+ case NX_LINK_GET_STATUS:
+ {
+
+ /* Process get status requests. */
+ nx_driver_get_status(driver_req_ptr);
+ break;
+ }
+
+#ifdef NX_DRIVER_ENABLE_DEFERRED
+ case NX_LINK_DEFERRED_PROCESSING:
+ {
+
+ /* Process driver deferred requests. */
+
+ /* Process a device driver function on behave of the IP thread. */
+ nx_driver_deferred_processing(driver_req_ptr);
+
+ break;
+ }
+#endif
+
+#ifdef NX_ENABLE_INTERFACE_CAPABILITY
+ case NX_INTERFACE_CAPABILITY_GET:
+ {
+
+ /* Process get capability requests. */
+ nx_driver_capability_get(driver_req_ptr);
+ break;
+ }
+
+ case NX_INTERFACE_CAPABILITY_SET:
+ {
+
+ /* Process set capability requests. */
+ nx_driver_capability_set(driver_req_ptr);
+ break;
+ }
+#endif /* NX_ENABLE_INTERFACE_CAPABILITY */
+
+ default:
+
+ /* Invalid driver request. */
+
+ /* Return the unhandled command status. */
+ driver_req_ptr -> nx_ip_driver_status = NX_UNHANDLED_COMMAND;
+
+ /* Default to successful return. */
+ driver_req_ptr -> nx_ip_driver_status = NX_DRIVER_ERROR;
+ }
+}
+
+
+/**************************************************************************/
+/* */
+/* FUNCTION RELEASE */
+/* */
+/* nx_driver_interface_attach PORTABLE C */
+/* 6.x */
+/* AUTHOR */
+/* */
+/* Andres Mlinar, Microsoft Corporation */
+/* */
+/* DESCRIPTION */
+/* */
+/* This function processing the interface attach request. */
+/* */
+/* INPUT */
+/* */
+/* driver_req_ptr Driver command from the IP */
+/* thread */
+/* */
+/* OUTPUT */
+/* */
+/* None */
+/* */
+/* CALLS */
+/* */
+/* None */
+/* */
+/* CALLED BY */
+/* */
+/* Driver entry function */
+/* */
+/* RELEASE HISTORY */
+/* */
+/* DATE NAME DESCRIPTION */
+/* */
+/* xx-xx-xxxx Andres Mlinar Initial Version 6.x */
+/* */
+/**************************************************************************/
+static VOID nx_driver_interface_attach(NX_IP_DRIVER *driver_req_ptr)
+{
+
+
+ /*
+ * Setup the driver's interface.
+ * This default implementation is for a simple one-interface driver.
+ * Additional logic is necessary for multiple port devices.
+ */
+ nx_driver_information.nx_driver_information_interface = driver_req_ptr -> nx_ip_driver_interface;
+
+#ifdef NX_ENABLE_INTERFACE_CAPABILITY
+ driver_req_ptr -> nx_ip_driver_interface -> nx_interface_capability_flag = NX_DRIVER_CAPABILITY;
+#endif /* NX_ENABLE_INTERFACE_CAPABILITY */
+
+ /* Return successful status. */
+ driver_req_ptr -> nx_ip_driver_status = NX_SUCCESS;
+}
+
+
+/**************************************************************************/
+/* */
+/* FUNCTION RELEASE */
+/* */
+/* nx_driver_initialize PORTABLE C */
+/* 6.x */
+/* AUTHOR */
+/* */
+/* Andres Mlinar, Microsoft Corporation */
+/* */
+/* DESCRIPTION */
+/* */
+/* This function processing the initialize request. The processing */
+/* in this function is generic. All hardware specific logic goes in */
+/* nx_driver_hardware_initialize. */
+/* */
+/* INPUT */
+/* */
+/* driver_req_ptr Driver command from the IP */
+/* thread */
+/* */
+/* OUTPUT */
+/* */
+/* None */
+/* */
+/* CALLS */
+/* */
+/* nx_driver_hardware_initialize Process initialize request */
+/* */
+/* CALLED BY */
+/* */
+/* Driver entry function */
+/* */
+/* RELEASE HISTORY */
+/* */
+/* DATE NAME DESCRIPTION */
+/* */
+/* xx-xx-xxxx Andres Mlinar Initial Version 6.x */
+/* */
+/**************************************************************************/
+static VOID nx_driver_initialize(NX_IP_DRIVER *driver_req_ptr)
+{
+
+NX_IP *ip_ptr;
+NX_INTERFACE *interface_ptr;
+UINT status;
+
+
+ /* Setup the IP pointer from the driver request. */
+ ip_ptr = driver_req_ptr -> nx_ip_driver_ptr;
+
+ /* Setup interface pointer. */
+ interface_ptr = driver_req_ptr -> nx_ip_driver_interface;
+
+ /* Initialize the driver's information structure. */
+
+ /* Default IP pointer to NULL. */
+ nx_driver_information.nx_driver_information_ip_ptr = NX_NULL;
+
+ /* Setup the driver state to not initialized. */
+ nx_driver_information.nx_driver_information_state = NX_DRIVER_STATE_NOT_INITIALIZED;
+
+ /* Setup the default packet pool for the driver's received packets. */
+ nx_driver_information.nx_driver_information_packet_pool_ptr = ip_ptr -> nx_ip_default_packet_pool;
+
+ /* Clear the deferred events for the driver. */
+ nx_driver_information.nx_driver_information_deferred_events = 0;
+
+#ifdef NX_DRIVER_INTERNAL_TRANSMIT_QUEUE
+
+ /* Clear the transmit queue count and head pointer. */
+ nx_driver_information.nx_driver_transmit_packets_queued = 0;
+ nx_driver_information.nx_driver_transmit_queue_head = NX_NULL;
+ nx_driver_information.nx_driver_transmit_queue_tail = NX_NULL;
+#endif /* NX_DRIVER_INTERNAL_TRANSMIT_QUEUE */
+
+ /* Call the hardware-specific ethernet controller initialization. */
+ if (!nx_driver_hardware_initialize) status = NX_SUCCESS;
+ else status = nx_driver_hardware_initialize(driver_req_ptr);
+
+ /* Determine if the request was successful. */
+ if (status == NX_SUCCESS)
+ {
+
+ /* Successful hardware initialization. */
+
+ /* Setup driver information to point to IP pointer. */
+ nx_driver_information.nx_driver_information_ip_ptr = driver_req_ptr -> nx_ip_driver_ptr;
+
+ /* Setup the link maximum transfer unit. */
+ interface_ptr -> nx_interface_ip_mtu_size = NX_DRIVER_MTU - NX_DRIVER_PHYSICAL_FRAME_SIZE;
+
+ /* Indicate to the IP software that IP to physical mapping
+ is required. */
+ interface_ptr -> nx_interface_address_mapping_needed = NX_TRUE;
+
+ /* Move the driver's state to initialized. */
+ nx_driver_information.nx_driver_information_state = NX_DRIVER_STATE_INITIALIZED;
+
+ /* Indicate successful initialize. */
+ driver_req_ptr -> nx_ip_driver_status = NX_SUCCESS;
+ }
+ else
+ {
+
+ /* Initialization failed. Indicate that the request failed. */
+ driver_req_ptr -> nx_ip_driver_status = NX_DRIVER_ERROR;
+ }
+}
+
+
+/**************************************************************************/
+/* */
+/* FUNCTION RELEASE */
+/* */
+/* nx_driver_enable PORTABLE C */
+/* 6.x */
+/* AUTHOR */
+/* */
+/* Andres Mlinar, Microsoft Corporation */
+/* */
+/* DESCRIPTION */
+/* */
+/* This function processing the initialize request. The processing */
+/* in this function is generic. All hardware specific logic in */
+/* nx_driver_hardware_enable. */
+/* */
+/* INPUT */
+/* */
+/* driver_req_ptr Driver command from the IP */
+/* thread */
+/* */
+/* OUTPUT */
+/* */
+/* None */
+/* */
+/* CALLS */
+/* */
+/* nx_driver_hardware_enable Process enable request */
+/* */
+/* CALLED BY */
+/* */
+/* Driver entry function */
+/* */
+/* RELEASE HISTORY */
+/* */
+/* DATE NAME DESCRIPTION */
+/* */
+/* xx-xx-xxxx Andres Mlinar Initial Version 6.x */
+/* */
+/**************************************************************************/
+static VOID nx_driver_enable(NX_IP_DRIVER *driver_req_ptr)
+{
+
+NX_IP *ip_ptr;
+UINT status;
+
+
+ /* Setup the IP pointer from the driver request. */
+ ip_ptr = driver_req_ptr -> nx_ip_driver_ptr;
+
+ /* See if we can honor the NX_LINK_ENABLE request. */
+ if (nx_driver_information.nx_driver_information_state < NX_DRIVER_STATE_INITIALIZED)
+ {
+
+ /* Mark the request as not successful. */
+ driver_req_ptr -> nx_ip_driver_status = NX_DRIVER_ERROR;
+ return;
+ }
+
+ /* Check if it is enabled by someone already */
+ if (nx_driver_information.nx_driver_information_state >= NX_DRIVER_STATE_LINK_ENABLED)
+ {
+
+ /* Yes, the request has already been made. */
+ driver_req_ptr -> nx_ip_driver_status = NX_ALREADY_ENABLED;
+ return;
+ }
+
+ /* Call hardware specific enable. */
+ if (!nx_driver_hardware_enable) status = NX_SUCCESS;
+ else status = nx_driver_hardware_enable(driver_req_ptr);
+
+ /* Was the hardware enable successful? */
+ if (status == NX_SUCCESS)
+ {
+
+ /* Update the driver state to link enabled. */
+ nx_driver_information.nx_driver_information_state = NX_DRIVER_STATE_LINK_ENABLED;
+
+ /* Mark request as successful. */
+ driver_req_ptr -> nx_ip_driver_status = NX_SUCCESS;
+
+ /* Mark the IP instance as link up. */
+ ip_ptr -> nx_ip_driver_link_up = NX_TRUE;
+ }
+ else
+ {
+
+ /* Enable failed. Indicate that the request failed. */
+ driver_req_ptr -> nx_ip_driver_status = NX_DRIVER_ERROR;
+ }
+}
+
+
+/**************************************************************************/
+/* */
+/* FUNCTION RELEASE */
+/* */
+/* nx_driver_disable PORTABLE C */
+/* 6.x */
+/* AUTHOR */
+/* */
+/* Andres Mlinar, Microsoft Corporation */
+/* */
+/* DESCRIPTION */
+/* */
+/* This function processing the disable request. The processing */
+/* in this function is generic. All hardware specific logic in */
+/* nx_driver_hardware_disable. */
+/* */
+/* INPUT */
+/* */
+/* driver_req_ptr Driver command from the IP */
+/* thread */
+/* */
+/* OUTPUT */
+/* */
+/* None */
+/* */
+/* CALLS */
+/* */
+/* nx_driver_hardware_disable Process disable request */
+/* */
+/* CALLED BY */
+/* */
+/* Driver entry function */
+/* */
+/* RELEASE HISTORY */
+/* */
+/* DATE NAME DESCRIPTION */
+/* */
+/* xx-xx-xxxx Andres Mlinar Initial Version 6.x */
+/* */
+/**************************************************************************/
+static VOID nx_driver_disable(NX_IP_DRIVER *driver_req_ptr)
+{
+
+NX_IP *ip_ptr;
+UINT status;
+
+
+ /* Setup the IP pointer from the driver request. */
+ ip_ptr = driver_req_ptr -> nx_ip_driver_ptr;
+
+ /* Check if the link is enabled. */
+ if (nx_driver_information.nx_driver_information_state != NX_DRIVER_STATE_LINK_ENABLED)
+ {
+
+ /* The link is not enabled, so just return an error. */
+ driver_req_ptr -> nx_ip_driver_status = NX_DRIVER_ERROR;
+ return;
+ }
+
+ /* Call hardware specific disable. */
+ if (!nx_driver_hardware_disable) status = NX_SUCCESS;
+ else status = nx_driver_hardware_disable(driver_req_ptr);
+
+ /* Was the hardware disable successful? */
+ if (status == NX_SUCCESS)
+ {
+
+ /* Mark the IP instance as link down. */
+ ip_ptr -> nx_ip_driver_link_up = NX_FALSE;
+
+ /* Update the driver state back to initialized. */
+ nx_driver_information.nx_driver_information_state = NX_DRIVER_STATE_INITIALIZED;
+
+ /* Mark request as successful. */
+ driver_req_ptr -> nx_ip_driver_status = NX_SUCCESS;
+ }
+ else
+ {
+
+ /* Disable failed, return an error. */
+ driver_req_ptr -> nx_ip_driver_status = NX_DRIVER_ERROR;
+ }
+}
+
+
+/**************************************************************************/
+/* */
+/* FUNCTION RELEASE */
+/* */
+/* nx_driver_packet_send PORTABLE C */
+/* 6.x */
+/* AUTHOR */
+/* */
+/* Andres Mlinar, Microsoft Corporation */
+/* */
+/* DESCRIPTION */
+/* */
+/* This function processing the packet send request. The processing */
+/* in this function is generic. All hardware specific logic is in */
+/* nx_driver_hardware_packet_send. */
+/* */
+/* INPUT */
+/* */
+/* driver_req_ptr Driver command from the IP */
+/* thread */
+/* */
+/* OUTPUT */
+/* */
+/* None */
+/* */
+/* CALLS */
+/* */
+/* nx_driver_hardware_packet_send Process packet send request */
+/* */
+/* CALLED BY */
+/* */
+/* Driver entry function */
+/* */
+/* RELEASE HISTORY */
+/* */
+/* DATE NAME DESCRIPTION */
+/* */
+/* xx-xx-xxxx Andres Mlinar Initial Version 6.x */
+/* */
+/**************************************************************************/
+static VOID nx_driver_packet_send(NX_IP_DRIVER *driver_req_ptr)
+{
+
+NX_IP *ip_ptr;
+NX_PACKET *packet_ptr;
+ULONG *ethernet_frame_ptr;
+UINT status;
+
+
+ /* Setup the IP pointer from the driver request. */
+ ip_ptr = driver_req_ptr -> nx_ip_driver_ptr;
+
+ /* Check to make sure the link is up. */
+ if (nx_driver_information.nx_driver_information_state != NX_DRIVER_STATE_LINK_ENABLED)
+ {
+
+ /* Inidate an unsuccessful packet send. */
+ driver_req_ptr -> nx_ip_driver_status = NX_DRIVER_ERROR;
+
+ /* Link is not up, simply free the packet. */
+ nx_packet_transmit_release(driver_req_ptr -> nx_ip_driver_packet);
+ return;
+ }
+
+ /* Process driver send packet. */
+
+ /* Place the ethernet frame at the front of the packet. */
+ packet_ptr = driver_req_ptr -> nx_ip_driver_packet;
+
+ /* Adjust the prepend pointer. */
+ packet_ptr -> nx_packet_prepend_ptr =
+ packet_ptr -> nx_packet_prepend_ptr - NX_DRIVER_PHYSICAL_FRAME_SIZE;
+
+ /* Adjust the packet length. */
+ packet_ptr -> nx_packet_length = packet_ptr -> nx_packet_length + NX_DRIVER_PHYSICAL_FRAME_SIZE;
+
+ /* Setup the ethernet frame pointer to build the ethernet frame. Backup another 2
+ * bytes to get 32-bit word alignment. */
+ ethernet_frame_ptr = (ULONG *) (packet_ptr -> nx_packet_prepend_ptr - 2);
+
+ /* Set up the hardware addresses in the Ethernet header. */
+ *ethernet_frame_ptr = driver_req_ptr -> nx_ip_driver_physical_address_msw;
+ *(ethernet_frame_ptr + 1) = driver_req_ptr -> nx_ip_driver_physical_address_lsw;
+
+ *(ethernet_frame_ptr + 2) = (ip_ptr -> nx_ip_arp_physical_address_msw << 16) |
+ (ip_ptr -> nx_ip_arp_physical_address_lsw >> 16);
+ *(ethernet_frame_ptr + 3) = (ip_ptr -> nx_ip_arp_physical_address_lsw << 16);
+
+ /* Set up the frame type field in the Ethernet harder. */
+ if ((driver_req_ptr -> nx_ip_driver_command == NX_LINK_ARP_SEND)||
+ (driver_req_ptr -> nx_ip_driver_command == NX_LINK_ARP_RESPONSE_SEND))
+ {
+ *(ethernet_frame_ptr + 3) |= NX_DRIVER_ETHERNET_ARP;
+ }
+ else if(driver_req_ptr -> nx_ip_driver_command == NX_LINK_RARP_SEND)
+ {
+ *(ethernet_frame_ptr + 3) |= NX_DRIVER_ETHERNET_RARP;
+ }
+#ifdef FEATURE_NX_IPV6
+ else if(packet_ptr -> nx_packet_ip_version == NX_IP_VERSION_V6)
+ {
+ *(ethernet_frame_ptr + 3) |= NX_DRIVER_ETHERNET_IPV6;
+ }
+#endif /* FEATURE_NX_IPV6 */
+ else
+ {
+ *(ethernet_frame_ptr + 3) |= NX_DRIVER_ETHERNET_IP;
+ }
+
+ /* Endian swapping if NX_LITTLE_ENDIAN is defined. */
+ NX_CHANGE_ULONG_ENDIAN(*(ethernet_frame_ptr));
+ NX_CHANGE_ULONG_ENDIAN(*(ethernet_frame_ptr + 1));
+ NX_CHANGE_ULONG_ENDIAN(*(ethernet_frame_ptr + 2));
+ NX_CHANGE_ULONG_ENDIAN(*(ethernet_frame_ptr + 3));
+
+ /* Determine if the packet exceeds the driver's MTU. */
+ if (packet_ptr -> nx_packet_length > NX_DRIVER_MTU)
+ {
+
+ /* This packet exceeds the size of the driver's MTU. Simply throw it away! */
+
+ /* Remove the Ethernet header. */
+ NX_DRIVER_PHYSICAL_HEADER_REMOVE(packet_ptr);
+
+ /* Indicate an unsuccessful packet send. */
+ driver_req_ptr -> nx_ip_driver_status = NX_DRIVER_ERROR;
+
+ /* Link is not up, simply free the packet. */
+ nx_packet_transmit_release(packet_ptr);
+ return;
+ }
+
+ /* Transmit the packet through the Ethernet controller low level access routine. */
+ if (!nx_driver_hardware_packet_send)
+ status = NX_DRIVER_ERROR;
+ else status = nx_driver_hardware_packet_send(packet_ptr);
+
+ /* Determine if there was an error. */
+ if (status != NX_SUCCESS)
+ {
+
+ /* Driver's hardware send packet routine failed to send the packet. */
+
+ /* Remove the Ethernet header. */
+ NX_DRIVER_PHYSICAL_HEADER_REMOVE(packet_ptr);
+
+ /* Indicate an unsuccessful packet send. */
+ driver_req_ptr -> nx_ip_driver_status = NX_DRIVER_ERROR;
+
+ /* Link is not up, simply free the packet. */
+ nx_packet_transmit_release(packet_ptr);
+ }
+ else
+ {
+
+ /* Set the status of the request. */
+ driver_req_ptr -> nx_ip_driver_status = NX_SUCCESS;
+ }
+}
+
+
+/**************************************************************************/
+/* */
+/* FUNCTION RELEASE */
+/* */
+/* nx_driver_multicast_join PORTABLE C */
+/* 6.x */
+/* AUTHOR */
+/* */
+/* Andres Mlinar, Microsoft Corporation */
+/* */
+/* DESCRIPTION */
+/* */
+/* This function processing the multicast join request. The processing */
+/* in this function is generic. All hardware specific logic is in */
+/* nx_driver_hardware_multicast_join. */
+/* */
+/* INPUT */
+/* */
+/* driver_req_ptr Driver command from the IP */
+/* thread */
+/* */
+/* OUTPUT */
+/* */
+/* None */
+/* */
+/* CALLS */
+/* */
+/* nx_driver_hardware_multicast_join Process multicast join request*/
+/* */
+/* CALLED BY */
+/* */
+/* Driver entry function */
+/* */
+/* RELEASE HISTORY */
+/* */
+/* DATE NAME DESCRIPTION */
+/* */
+/* xx-xx-xxxx Andres Mlinar Initial Version 6.x */
+/* */
+/**************************************************************************/
+static VOID nx_driver_multicast_join(NX_IP_DRIVER *driver_req_ptr)
+{
+
+UINT status;
+
+
+ /* Call hardware specific multicast join function. */
+ if (!nx_driver_hardware_multicast_join) status = NX_SUCCESS;
+ else status = nx_driver_hardware_multicast_join(driver_req_ptr);
+
+ /* Determine if there was an error. */
+ if (status != NX_SUCCESS)
+ {
+
+ /* Indicate an unsuccessful request. */
+ driver_req_ptr -> nx_ip_driver_status = NX_DRIVER_ERROR;
+ }
+ else
+ {
+
+ /* Indicate the request was successful. */
+ driver_req_ptr -> nx_ip_driver_status = NX_SUCCESS;
+ }
+}
+
+
+/**************************************************************************/
+/* */
+/* FUNCTION RELEASE */
+/* */
+/* nx_driver_multicast_leave PORTABLE C */
+/* 6.x */
+/* AUTHOR */
+/* */
+/* Andres Mlinar, Microsoft Corporation */
+/* */
+/* DESCRIPTION */
+/* */
+/* This function processing the multicast leave request. The code */
+/* in this function is generic. All hardware specific logic is in */
+/* nx_driver_hardware_multicast_leave. */
+/* */
+/* INPUT */
+/* */
+/* driver_req_ptr Driver command from the IP */
+/* thread */
+/* */
+/* OUTPUT */
+/* */
+/* None */
+/* */
+/* CALLS */
+/* */
+/* nx_driver_hardware_multicast_leave Process multicast leave req */
+/* */
+/* CALLED BY */
+/* */
+/* Driver entry function */
+/* */
+/* RELEASE HISTORY */
+/* */
+/* DATE NAME DESCRIPTION */
+/* */
+/* xx-xx-xxxx Andres Mlinar Initial Version 6.x */
+/* */
+/**************************************************************************/
+static VOID nx_driver_multicast_leave(NX_IP_DRIVER *driver_req_ptr)
+{
+
+UINT status;
+
+
+ /* Call hardware specific multicast leave function. */
+ if (!nx_driver_hardware_multicast_leave) status = NX_SUCCESS;
+ else status = nx_driver_hardware_multicast_leave(driver_req_ptr);
+
+ /* Determine if there was an error. */
+ if (status != NX_SUCCESS)
+ {
+
+ /* Indicate an unsuccessful request. */
+ driver_req_ptr -> nx_ip_driver_status = NX_DRIVER_ERROR;
+ }
+ else
+ {
+
+ /* Indicate the request was successful. */
+ driver_req_ptr -> nx_ip_driver_status = NX_SUCCESS;
+ }
+}
+
+
+/**************************************************************************/
+/* */
+/* FUNCTION RELEASE */
+/* */
+/* nx_driver_get_status PORTABLE C */
+/* 6.x */
+/* AUTHOR */
+/* */
+/* Andres Mlinar, Microsoft Corporation */
+/* */
+/* DESCRIPTION */
+/* */
+/* This function processing the get status request. The processing */
+/* in this function is generic. All hardware specific logic is in */
+/* nx_driver_hardware_get_status. */
+/* */
+/* INPUT */
+/* */
+/* driver_req_ptr Driver command from the IP */
+/* thread */
+/* */
+/* OUTPUT */
+/* */
+/* None */
+/* */
+/* CALLS */
+/* */
+/* nx_driver_hardware_get_status Process get status request */
+/* */
+/* CALLED BY */
+/* */
+/* Driver entry function */
+/* */
+/* RELEASE HISTORY */
+/* */
+/* DATE NAME DESCRIPTION */
+/* */
+/* xx-xx-xxxx Andres Mlinar Initial Version 6.x */
+/* */
+/**************************************************************************/
+static VOID nx_driver_get_status(NX_IP_DRIVER *driver_req_ptr)
+{
+
+UINT status;
+
+
+ /* Call hardware specific get status function. */
+ if (!nx_driver_hardware_get_status) status = NX_SUCCESS;
+ else status = nx_driver_hardware_get_status(driver_req_ptr);
+
+ /* Determine if there was an error. */
+ if (status != NX_SUCCESS)
+ {
+
+ /* Indicate an unsuccessful request. */
+ driver_req_ptr -> nx_ip_driver_status = NX_DRIVER_ERROR;
+ }
+ else
+ {
+
+ /* Indicate the request was successful. */
+ driver_req_ptr -> nx_ip_driver_status = NX_SUCCESS;
+ }
+}
+
+
+#ifdef NX_ENABLE_INTERFACE_CAPABILITY
+/**************************************************************************/
+/* */
+/* FUNCTION RELEASE */
+/* */
+/* nx_driver_capability_get PORTABLE C */
+/* 6.x */
+/* AUTHOR */
+/* */
+/* Andres Mlinar, Microsoft Corporation */
+/* */
+/* DESCRIPTION */
+/* */
+/* This function processing the get capability request. */
+/* */
+/* INPUT */
+/* */
+/* driver_req_ptr Driver command from the IP */
+/* thread */
+/* */
+/* OUTPUT */
+/* */
+/* None */
+/* */
+/* CALLS */
+/* */
+/* None */
+/* */
+/* CALLED BY */
+/* */
+/* Driver entry function */
+/* */
+/* RELEASE HISTORY */
+/* */
+/* DATE NAME DESCRIPTION */
+/* */
+/* xx-xx-xxxx Andres Mlinar Initial Version 6.x */
+/* */
+/**************************************************************************/
+static VOID nx_driver_capability_get(NX_IP_DRIVER *driver_req_ptr)
+{
+
+ /* Return the capability of the Ethernet controller. */
+ *(driver_req_ptr -> nx_ip_driver_return_ptr) = NX_DRIVER_CAPABILITY;
+
+ /* Return the success status. */
+ driver_req_ptr -> nx_ip_driver_status = NX_SUCCESS;
+}
+
+
+/**************************************************************************/
+/* */
+/* FUNCTION RELEASE */
+/* */
+/* nx_driver_capability_set PORTABLE C */
+/* 6.x */
+/* AUTHOR */
+/* */
+/* Andres Mlinar, Microsoft Corporation */
+/* */
+/* DESCRIPTION */
+/* */
+/* This function processing the set capability request. */
+/* */
+/* INPUT */
+/* */
+/* driver_req_ptr Driver command from the IP */
+/* thread */
+/* */
+/* OUTPUT */
+/* */
+/* None */
+/* */
+/* CALLS */
+/* */
+/* None */
+/* */
+/* CALLED BY */
+/* */
+/* Driver entry function */
+/* */
+/* RELEASE HISTORY */
+/* */
+/* DATE NAME DESCRIPTION */
+/* */
+/* xx-xx-xxxx Andres Mlinar Initial Version 6.x */
+/* */
+/**************************************************************************/
+static VOID nx_driver_capability_set(NX_IP_DRIVER *driver_req_ptr)
+{
+
+UINT status;
+
+
+ /* Call hardware specific get status function. */
+ if (!nx_driver_hardware_capability_set) status = NX_SUCCESS;
+ else status = nx_driver_hardware_capability_set(driver_req_ptr);
+
+ /* Determine if there was an error. */
+ if (status != NX_SUCCESS)
+ {
+
+ /* Indicate an unsuccessful request. */
+ driver_req_ptr -> nx_ip_driver_status = NX_DRIVER_ERROR;
+ }
+ else
+ {
+
+ /* Indicate the request was successful. */
+ driver_req_ptr -> nx_ip_driver_status = NX_SUCCESS;
+ }
+}
+#endif /* NX_ENABLE_INTERFACE_CAPABILITY */
+
+
+#ifdef NX_DRIVER_ENABLE_DEFERRED
+/**************************************************************************/
+/* */
+/* FUNCTION RELEASE */
+/* */
+/* nx_driver_deferred_processing PORTABLE C */
+/* 6.x */
+/* AUTHOR */
+/* */
+/* Andres Mlinar, Microsoft Corporation */
+/* */
+/* DESCRIPTION */
+/* */
+/* This function processing the deferred ISR action within the context */
+/* of the IP thread. */
+/* */
+/* INPUT */
+/* */
+/* driver_req_ptr Driver command from the IP */
+/* thread */
+/* */
+/* OUTPUT */
+/* */
+/* None */
+/* */
+/* CALLS */
+/* */
+/* nx_driver_packet_transmitted Clean up after transmission */
+/* nx_driver_packet_received Process a received packet */
+/* */
+/* CALLED BY */
+/* */
+/* Driver entry function */
+/* */
+/* RELEASE HISTORY */
+/* */
+/* DATE NAME DESCRIPTION */
+/* */
+/* xx-xx-xxxx Andres Mlinar Initial Version 6.x */
+/* */
+/**************************************************************************/
+static VOID nx_driver_deferred_processing(NX_IP_DRIVER *driver_req_ptr)
+{
+
+TX_INTERRUPT_SAVE_AREA
+
+ULONG deferred_events;
+
+
+ /* Disable interrupts. */
+ TX_DISABLE
+
+ /* Pickup deferred events. */
+ deferred_events = nx_driver_information.nx_driver_information_deferred_events;
+ nx_driver_information.nx_driver_information_deferred_events = 0;
+
+ /* Restore interrupts. */
+ TX_RESTORE
+
+ /* Check for a transmit complete event. */
+ if(deferred_events & NX_DRIVER_DEFERRED_PACKET_TRANSMITTED)
+ {
+
+ /* Process transmitted packet(s). */
+ if (nx_driver_hardware_packet_transmitted)
+ nx_driver_hardware_packet_transmitted();
+ }
+
+ /* Check for recevied packet. */
+ if(deferred_events & NX_DRIVER_DEFERRED_PACKET_RECEIVED)
+ {
+
+ /* Process received packet(s). */
+ if (nx_driver_hardware_packet_received)
+ nx_driver_hardware_packet_received();
+ }
+
+ /* Mark request as successful. */
+ driver_req_ptr->nx_ip_driver_status = NX_SUCCESS;
+}
+#endif /* NX_DRIVER_ENABLE_DEFERRED */
+
+
+/**************************************************************************/
+/* */
+/* FUNCTION RELEASE */
+/* */
+/* nx_driver_transfer_to_netx PORTABLE C */
+/* 6.x */
+/* AUTHOR */
+/* */
+/* Andres Mlinar, Microsoft Corporation */
+/* */
+/* DESCRIPTION */
+/* */
+/* This function processing incoming packets. This routine would */
+/* be called from the driver-specific receive packet processing */
+/* function nx_driver_hardware_packet_received. */
+/* */
+/* INPUT */
+/* */
+/* ip_ptr Pointer to IP protocol block */
+/* packet_ptr Packet pointer */
+/* */
+/* OUTPUT */
+/* */
+/* Error indication */
+/* */
+/* CALLS */
+/* */
+/* _nx_ip_packet_receive NetX IP packet receive */
+/* _nx_ip_packet_deferred_receive NetX IP packet receive */
+/* _nx_arp_packet_deferred_receive NetX ARP packet receive */
+/* _nx_rarp_packet_deferred_receive NetX RARP packet receive */
+/* _nx_packet_release Release packet */
+/* */
+/* CALLED BY */
+/* */
+/* nx_driver_hardware_packet_received Driver packet receive function*/
+/* */
+/* RELEASE HISTORY */
+/* */
+/* DATE NAME DESCRIPTION */
+/* */
+/* xx-xx-xxxx Andres Mlinar Initial Version 6.x */
+/* */
+/**************************************************************************/
+static VOID nx_driver_transfer_to_netx(NX_IP *ip_ptr, NX_PACKET *packet_ptr)
+{
+
+USHORT packet_type;
+
+
+ /* Set the interface for the incoming packet. */
+ packet_ptr -> nx_packet_ip_interface = nx_driver_information.nx_driver_information_interface;
+
+ /* Pickup the packet header to determine where the packet needs to be
+ sent. */
+ packet_type = (USHORT)(((UINT) (*(packet_ptr -> nx_packet_prepend_ptr+12))) << 8) |
+ ((UINT) (*(packet_ptr -> nx_packet_prepend_ptr+13)));
+
+ /* Route the incoming packet according to its ethernet type. */
+ if (packet_type == NX_DRIVER_ETHERNET_IP || packet_type == NX_DRIVER_ETHERNET_IPV6)
+ {
+ /* Note: The length reported by some Ethernet hardware includes
+ bytes after the packet as well as the Ethernet header. In some
+ cases, the actual packet length after the Ethernet header should
+ be derived from the length in the IP header (lower 16 bits of
+ the first 32-bit word). */
+
+ /* Clean off the Ethernet header. */
+ packet_ptr -> nx_packet_prepend_ptr =
+ packet_ptr -> nx_packet_prepend_ptr + NX_DRIVER_PHYSICAL_FRAME_SIZE;
+
+ /* Adjust the packet length. */
+ packet_ptr -> nx_packet_length =
+ packet_ptr -> nx_packet_length - NX_DRIVER_PHYSICAL_FRAME_SIZE;
+
+ /* Route to the ip receive function. */
+#ifdef NX_DRIVER_ENABLE_DEFERRED
+ _nx_ip_packet_deferred_receive(ip_ptr, packet_ptr);
+#else
+ _nx_ip_packet_receive(ip_ptr, packet_ptr);
+#endif /* NX_DRIVER_ENABLE_DEFERRED */
+ }
+ else if (packet_type == NX_DRIVER_ETHERNET_ARP)
+ {
+
+ /* Clean off the Ethernet header. */
+ packet_ptr -> nx_packet_prepend_ptr =
+ packet_ptr -> nx_packet_prepend_ptr + NX_DRIVER_PHYSICAL_FRAME_SIZE;
+
+ /* Adjust the packet length. */
+ packet_ptr -> nx_packet_length =
+ packet_ptr -> nx_packet_length - NX_DRIVER_PHYSICAL_FRAME_SIZE;
+
+ /* Route to the ARP receive function. */
+ _nx_arp_packet_deferred_receive(ip_ptr, packet_ptr);
+ }
+ else if (packet_type == NX_DRIVER_ETHERNET_RARP)
+ {
+
+ /* Clean off the Ethernet header. */
+ packet_ptr -> nx_packet_prepend_ptr =
+ packet_ptr -> nx_packet_prepend_ptr + NX_DRIVER_PHYSICAL_FRAME_SIZE;
+
+ /* Adjust the packet length. */
+ packet_ptr -> nx_packet_length =
+ packet_ptr -> nx_packet_length - NX_DRIVER_PHYSICAL_FRAME_SIZE;
+
+ /* Route to the RARP receive function. */
+ _nx_rarp_packet_deferred_receive(ip_ptr, packet_ptr);
+ }
+ else
+ {
+ /* Invalid ethernet header... release the packet. */
+ nx_packet_release(packet_ptr);
+ }
+}
+
+
+/**************************************************************************/
+/* */
+/* FUNCTION RELEASE */
+/* */
+/* nx_driver_update_hardware_address PORTABLE C */
+/* 6.x */
+/* AUTHOR */
+/* */
+/* Andres Mlinar, Microsoft Corporation */
+/* */
+/* DESCRIPTION */
+/* */
+/* This function updates the hardware address kept by the driver. */
+/* The hardware address is used when constructing send packets and to */
+/* filter incomming packets. */
+/* */
+/* INPUT */
+/* */
+/* hardware_address The new hardware address */
+/* */
+/* OUTPUT */
+/* */
+/* None */
+/* */
+/* CALLS */
+/* */
+/* None */
+/* */
+/* CALLED BY */
+/* */
+/* nx_driver_initialize Driver initialization function*/
+/* */
+/* RELEASE HISTORY */
+/* */
+/* DATE NAME DESCRIPTION */
+/* */
+/* xx-xx-xxxx Andres Mlinar Initial Version 6.x */
+/* */
+/**************************************************************************/
+VOID nx_driver_update_hardware_address(UCHAR hardware_address[6])
+{
+
+NX_INTERFACE *interface_ptr;
+
+
+ /* Setup interface pointer. */
+ interface_ptr = nx_driver_information.nx_driver_information_interface;
+
+ /* Setup the physical address of this IP instance. Increment the
+ physical address lsw to simulate multiple nodes hanging on the
+ ethernet. */
+ interface_ptr -> nx_interface_physical_address_msw =
+ (ULONG)((hardware_address[0] << 8) |
+ (hardware_address[1]));
+ interface_ptr -> nx_interface_physical_address_lsw =
+ (ULONG)((hardware_address[2] << 24) |
+ (hardware_address[3] << 16) |
+ (hardware_address[4] << 8) |
+ (hardware_address[5]));
+}
+
+#ifdef NX_DRIVER_INTERNAL_TRANSMIT_QUEUE
+/**************************************************************************/
+/* */
+/* FUNCTION RELEASE */
+/* */
+/* nx_driver_transmit_packet_enqueue PORTABLE C */
+/* 6.x */
+/* AUTHOR */
+/* */
+/* Andres Mlinar, Microsoft Corporation */
+/* */
+/* DESCRIPTION */
+/* */
+/* This function queues a transmit packet when the hardware transmit */
+/* queue does not have the resources (buffer descriptors, etc.) to */
+/* send the packet. The queue is maintained as a singularly linked- */
+/* list with head and tail pointers. The maximum number of packets on */
+/* the transmit queue is regulated by the constant */
+/* NX_DRIVER_MAX_TRANSMIT_QUEUE_DEPTH. When this number is exceeded, */
+/* the oldest packet is discarded after the new packet is queued. */
+/* */
+/* Note: that it is assumed further driver interrupts are locked out */
+/* during the call to this driver utility. */
+/* */
+/* INPUT */
+/* */
+/* packet_ptr Packet pointer */
+/* */
+/* OUTPUT */
+/* */
+/* None */
+/* */
+/* CALLS */
+/* */
+/* _nx_packet_transmit_release Release packet */
+/* */
+/* CALLED BY */
+/* */
+/* nx_driver_hardware_packet_send Driver packet send function */
+/* */
+/* RELEASE HISTORY */
+/* */
+/* DATE NAME DESCRIPTION */
+/* */
+/* xx-xx-xxxx Andres Mlinar Initial Version 6.x */
+/* */
+/**************************************************************************/
+static VOID nx_driver_transmit_packet_enqueue(NX_PACKET *packet_ptr)
+{
+
+ /* Determine if there is anything on the queue. */
+ if (nx_driver_information.nx_driver_transmit_queue_tail)
+ {
+
+ /* Yes, something is on the transmit queue. Simply add the new packet to the
+ tail. */
+ nx_driver_information.nx_driver_transmit_queue_tail -> nx_packet_queue_next = packet_ptr;
+
+ /* Update the tail pointer. */
+ nx_driver_information.nx_driver_transmit_queue_tail = packet_ptr;
+ }
+ else
+ {
+
+ /* First packet on the transmit queue. */
+
+ /* Setup head pointers. */
+ nx_driver_information.nx_driver_transmit_queue_head = packet_ptr;
+ nx_driver_information.nx_driver_transmit_queue_tail = packet_ptr;
+
+ /* Set the packet's next pointer to NULL. */
+ packet_ptr -> nx_packet_queue_next = NX_NULL;
+ }
+
+ /* Increment the total packets queued. */
+ nx_driver_information.nx_driver_transmit_packets_queued++;
+
+ /* Determine if the total packet queued exceeds the driver's maximum transmit
+ queue depth. */
+ if (nx_driver_information.nx_driver_transmit_packets_queued > NX_DRIVER_MAX_TRANSMIT_QUEUE_DEPTH)
+ {
+
+ /* Yes, remove the head packet (oldest) packet in the transmit queue and release it. */
+ packet_ptr = nx_driver_information.nx_driver_transmit_queue_head;
+
+ /* Adjust the head pointer to the next packet. */
+ nx_driver_information.nx_driver_transmit_queue_head = packet_ptr -> nx_packet_queue_next;
+
+ /* Decrement the transmit packet queued count. */
+ nx_driver_information.nx_driver_transmit_packets_queued--;
+
+ /* Remove the ethernet header. */
+ NX_DRIVER_PHYSICAL_HEADER_REMOVE(packet_ptr);
+
+ /* Release the packet. */
+ nx_packet_transmit_release(packet_ptr);
+ }
+}
+
+
+/**************************************************************************/
+/* */
+/* FUNCTION RELEASE */
+/* */
+/* nx_driver_transmit_packet_dequeue PORTABLE C */
+/* 6.x */
+/* AUTHOR */
+/* */
+/* Andres Mlinar, Microsoft Corporation */
+/* */
+/* DESCRIPTION */
+/* */
+/* This function removes the oldest transmit packet when the hardware */
+/* transmit queue has new resources (usually after a transmit complete */
+/* interrupt) to send the packet. If there are no packets in the */
+/* transmit queue, a NULL is returned. */
+/* */
+/* Note: that it is assumed further driver interrupts are locked out */
+/* during the call to this driver utility. */
+/* */
+/* INPUT */
+/* */
+/* None */
+/* */
+/* OUTPUT */
+/* */
+/* packet_ptr Packet pointer */
+/* */
+/* CALLS */
+/* */
+/* None */
+/* */
+/* CALLED BY */
+/* */
+/* nx_driver_hardware_packet_send Driver packet send function */
+/* */
+/* RELEASE HISTORY */
+/* */
+/* DATE NAME DESCRIPTION */
+/* */
+/* xx-xx-xxxx Andres Mlinar Initial Version 6.x */
+/* */
+/**************************************************************************/
+static NX_PACKET * nx_driver_transmit_packet_dequeue(VOID)
+{
+
+NX_PACKET *packet_ptr;
+
+
+ /* Pickup the head pointer of the tranmit packet queue. */
+ packet_ptr = nx_driver_information.nx_driver_transmit_queue_head;
+
+ /* Determine if there is anything on the queue. */
+ if (packet_ptr)
+ {
+
+ /* Yes, something is on the transmit queue. Simply the packet from the head of the queue. */
+
+ /* Update the head pointer. */
+ nx_driver_information.nx_driver_transmit_queue_head = packet_ptr -> nx_packet_queue_next;
+
+ /* Clear the next pointer in the packet. */
+ packet_ptr -> nx_packet_queue_next = NX_NULL;
+
+ /* Decrement the transmit packet queued count. */
+ nx_driver_information.nx_driver_transmit_packets_queued--;
+ }
+
+ /* Return the packet pointer - NULL if there are no packets queued. */
+ return(packet_ptr);
+}
+#endif /* NX_DRIVER_INTERNAL_TRANSMIT_QUEUE */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/netx_driver/mxchip/nx_driver_framework.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/netx_driver/mxchip/nx_driver_framework.h
new file mode 100644
index 00000000..af8dbf53
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/netx_driver/mxchip/nx_driver_framework.h
@@ -0,0 +1,134 @@
+/**************************************************************************/
+/* */
+/* Copyright (c) Microsoft Corporation. All rights reserved. */
+/* */
+/* This software is licensed under the Microsoft Software License */
+/* Terms for Microsoft Azure RTOS. Full text of the license can be */
+/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
+/* and in the root directory of this software. */
+/* */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/** */
+/** NetX Component */
+/** */
+/** NetX driver framework */
+/** */
+/**************************************************************************/
+/**************************************************************************/
+
+#ifndef NX_DRIVER_FRAMEWORK_H
+#define NX_DRIVER_FRAMEWORK_H
+
+
+#ifdef __cplusplus
+
+/* Yes, C++ compiler is present. Use standard C. */
+extern "C" {
+#endif
+
+
+/* Include ThreadX header file, if not already. */
+
+#ifndef TX_API_H
+#include "tx_api.h"
+#endif
+
+
+/* Include NetX header file, if not already. */
+
+#ifndef NX_API_H
+#include "nx_api.h"
+#endif
+
+
+#define NX_DRIVER_MTU (1514)
+#define NX_DRIVER_PHYSICAL_FRAME_SIZE (14)
+#define NX_DRIVER_PACKET_SIZE (NX_DRIVER_MTU + 28 + 2)
+
+#define NX_DRIVER_PHYSICAL_HEADER_REMOVE(p) \
+ do { \
+ p -> nx_packet_prepend_ptr += NX_DRIVER_PHYSICAL_FRAME_SIZE; \
+ p -> nx_packet_length -= NX_DRIVER_PHYSICAL_FRAME_SIZE; \
+ } while (0)
+
+struct NX_DRIVER_INFORMATION_STRUCT;
+
+
+/* Determine if the driver's source file is being compiled. The constants and typdefs are only valid within
+ the driver's source file compilation. */
+
+#ifdef NX_DRIVER_SOURCE
+
+
+/* Define generic constants and macros for all NetX drivers. */
+
+#define NX_DRIVER_STATE_NOT_INITIALIZED 1
+#define NX_DRIVER_STATE_INITIALIZE_FAILED 2
+#define NX_DRIVER_STATE_INITIALIZED 3
+#define NX_DRIVER_STATE_LINK_ENABLED 4
+
+#ifdef NX_DRIVER_INTERNAL_TRANSMIT_QUEUE
+#ifndef NX_DRIVER_MAX_TRANSMIT_QUEUE_DEPTH
+#define NX_DRIVER_MAX_TRANSMIT_QUEUE_DEPTH 10
+#endif
+#endif
+
+#define NX_DRIVER_DEFERRED_PACKET_RECEIVED 1
+#define NX_DRIVER_DEFERRED_DEVICE_RESET 2
+#define NX_DRIVER_DEFERRED_PACKET_TRANSMITTED 4
+
+#define NX_DRIVER_ERROR 90
+
+#ifndef NX_DRIVER_CAPABILITY
+#define NX_DRIVER_CAPABILITY ( 0 )
+#endif
+
+/* Define generic constants and macros for all NetX Ethernet drivers. */
+
+#define NX_DRIVER_ETHERNET_IP 0x0800
+#define NX_DRIVER_ETHERNET_IPV6 0x86dd
+#define NX_DRIVER_ETHERNET_ARP 0x0806
+#define NX_DRIVER_ETHERNET_RARP 0x8035
+
+
+/* Define basic Ethernet driver information typedef. Note that this typedefs is designed to be used only
+ in the driver's C file. */
+
+typedef struct NX_DRIVER_INFORMATION_STRUCT
+{
+ /* NetX IP instance that this driver is attached to. */
+ NX_IP *nx_driver_information_ip_ptr;
+
+ /* Driver's current state. */
+ ULONG nx_driver_information_state ;
+
+ /* Packet pool used for receiving packets. */
+ NX_PACKET_POOL *nx_driver_information_packet_pool_ptr;
+
+ /* Define the driver interface association. */
+ NX_INTERFACE *nx_driver_information_interface;
+
+ /* Define the deferred event field. This will contain bits representing events
+ deferred from the ISR for processing in the thread context. */
+ ULONG nx_driver_information_deferred_events;
+
+
+} NX_DRIVER_INFORMATION;
+
+#endif
+
+
+/* Define default driver entry function. */
+
+VOID nx_driver_framework_default_entry(NX_IP_DRIVER *driver_req_ptr);
+
+#ifdef __cplusplus
+/* Yes, C++ compiler is present. Use standard C. */
+ }
+#endif
+
+#endif
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/package.xml b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/package.xml
new file mode 100644
index 00000000..84034b55
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/package.xml
@@ -0,0 +1,7 @@
+
+
+
+
+
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/stmcubemx/b_u585i_iot02a_conf.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/stmcubemx/b_u585i_iot02a_conf.h
new file mode 100644
index 00000000..231c6572
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/stmcubemx/b_u585i_iot02a_conf.h
@@ -0,0 +1,88 @@
+/**
+ ******************************************************************************
+ * @file b_u585i_iot02a_conf_template.h
+ * @author MCD Application Team
+ * @brief configuration file.
+ * This file should be copied to the application folder and renamed
+ * to b_u585i_iot02a_conf.h
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef B_U585I_IOT02A_CONF_H
+#define B_U585I_IOT02A_CONF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+
+/** @addtogroup BSP
+ * @{
+ */
+
+/** @addtogroup B_U585I_IOT02A
+ * @{
+ */
+
+/** @defgroup B_U585I_IOT02A_CONFIG Config
+ * @{
+ */
+
+/** @defgroup B_U585I_IOT02A_CONFIG_Exported_Constants Exported Constants
+ * @{
+ */
+
+/* COM define */
+#define USE_BSP_COM_FEATURE 1U
+#define USE_COM_LOG 0U
+
+/* Default EEPROM max trials */
+#define EEPROM_MAX_TRIALS 3000U
+
+/* IRQ priorities */
+#define BSP_BUTTON_USER_IT_PRIORITY 15U /* Default is lowest priority level */
+
+/* CAMERA interrupt priority */
+#define BSP_CAMERA_IT_PRIORITY 14U /* Default is lowest priority level */
+
+/* I2C1 and I2C2 Frequencies in Hz */
+#define BUS_I2C1_FREQUENCY 100000UL /* Frequency of I2C1 = 100 KHz*/
+#define BUS_I2C2_FREQUENCY 100000UL /* Frequency of I2C2 = 100 KHz*/
+
+/* Usage of USBPD PWR TRACE system */
+#define USE_BSP_USBPD_PWR_TRACE 0U /* USBPD BSP trace system is disabled */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* B_U585I_IOT02A_CONF_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/stmcubemx/main.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/stmcubemx/main.h
new file mode 100644
index 00000000..a2f96369
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/stmcubemx/main.h
@@ -0,0 +1,65 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file : main.h
+ * @brief : Header for main.c file.
+ * This file contains the common defines of the application.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "b_u585i_iot02a.h"
+#include "stm32u5xx_hal.h"
+#include "stm32u5xx_hal_def.h"
+
+#include "mx_wifi_conf.h"
+
+/* Define the SPI handler available for the WiFi device. */
+#define MXCHIP_SPI hspi2
+void mxchip_WIFI_ISR(uint16_t pin);
+
+// Private defines
+#define MXCHIP_FLOW_Pin GPIO_PIN_15
+#define MXCHIP_FLOW_GPIO_Port GPIOG
+#define MXCHIP_FLOW_EXTI_IRQn EXTI15_IRQn
+#define MXCHIP_NOTIFY_Pin GPIO_PIN_14
+#define MXCHIP_NOTIFY_GPIO_Port GPIOD
+#define MXCHIP_NOTIFY_EXTI_IRQn EXTI14_IRQn
+#define MXCHIP_NSS_Pin GPIO_PIN_12
+#define MXCHIP_NSS_GPIO_Port GPIOB
+#define MXCHIP_RESET_Pin GPIO_PIN_15
+#define MXCHIP_RESET_GPIO_Port GPIOF
+
+/* External declarations for Mxchip with SPI.*/
+void HAL_SPI_TransferCallback(SPI_HandleTypeDef* hspi);
+extern void mxchip_WIFI_ISR(uint16_t pin);
+extern void nx_driver_emw3080_interrupt();
+
+void Error_Handler(void);
+void Success_Handler(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/stmcubemx/mx_wifi_conf.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/stmcubemx/mx_wifi_conf.h
new file mode 100644
index 00000000..9fd2c8c7
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/stmcubemx/mx_wifi_conf.h
@@ -0,0 +1,203 @@
+/**
+ ******************************************************************************
+ * @file mx_wifi_conf.h
+ * @author MCD Application Team
+ * @brief Header for mx_wifi module
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef MX_WIFI_CONF
+#define MX_WIFI_CONF
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#include
+#include "mx_wifi_azure_rtos_conf.h"
+
+int32_t mxwifi_probe(void **ll_drv_context);
+
+
+/* use SPI interface by default */
+
+#ifndef MX_WIFI_USE_SPI
+#define MX_WIFI_USE_SPI (1)
+#endif /* MX_WIFI_USE_SPI */
+
+/* do not use RTOS but bare metal approach by default */
+#ifndef MX_WIFI_USE_CMSIS_OS
+#define MX_WIFI_USE_CMSIS_OS (0)
+#endif /* MX_WIFI_USE_CMSIS_OS */
+
+/* Use At command mode by default, TCP/IP stack is running on module */
+#ifndef MX_WIFI_NETWORK_BYPASS_MODE
+#define MX_WIFI_NETWORK_BYPASS_MODE (1)
+#endif /* MX_WIFI_NETWORK_BYPASS_MODE */
+
+
+/* Do not copy TX buffer */
+#ifndef MX_WIFI_TX_BUFFER_NO_COPY
+#define MX_WIFI_TX_BUFFER_NO_COPY (1)
+#endif /* MX_WIFI_TX_BUFFER_NO_COPY */
+
+/* DEBUG LOG */
+/* #define MX_WIFI_API_DEBUG */
+/* #define MX_WIFI_IPC_DEBUG */
+/* #define MX_WIFI_HCI_DEBUG */
+/* #define MX_WIFI_SLIP_DEBUG */
+/* #define MX_WIFI_IO_DEBUG */
+
+#define MX_WIFI_PRODUCT_NAME ("MXCHIP-WIFI")
+#define MX_WIFI_PRODUCT_ID ("EMW3080B")
+
+#ifndef MX_WIFI_USE_SPI
+#define MX_WIFI_USE_SPI (0)
+#endif /* MX_WIFI_USE_SPI */
+
+
+#ifndef MX_WIFI_UART_BAUDRATE
+#define MX_WIFI_UART_BAUDRATE (115200*2)
+#endif /* MX_WIFI_UART_BAUDRATE */
+
+#ifndef MX_WIFI_MTU_SIZE
+#define MX_WIFI_MTU_SIZE (1500)
+#endif /* MX_WIFI_MTU_SIZE */
+
+#define MX_WIFI_BYPASS_HEADER_SIZE (28) /* MX_IPC_header(6) + sizeof(bypass_in_t)(22), set with PBUF_LINK_ENCAPSULATION_HLEN */
+#define MX_WIFI_PBUF_LINK_HLEN (14) /* link header (PBUF_LINK_HLEN) set in lwip */
+#if (MX_WIFI_NETWORK_BYPASS_MODE==1)
+#define MX_WIFI_BUFFER_SIZE (MX_WIFI_MTU_SIZE + MX_WIFI_BYPASS_HEADER_SIZE + MX_WIFI_PBUF_LINK_HLEN) /* use lwip PBUF_POOL_BUFSIZE = TCP_MSS+40+PBUF_LINK_ENCAPSULATION_HLEN+PBUF_LINK_HLEN */
+#else
+#define MX_WIFI_BUFFER_SIZE (2500) /* bigger buffer size */
+#endif
+
+#define MX_WIFI_IPC_PAYLOAD_SIZE ((MX_WIFI_BUFFER_SIZE) - 6) /* MX_WIFI_BUFFER_SIZE - MX_IPC_header */
+#define MX_WIFI_SOCKET_DATA_SIZE ((MX_WIFI_IPC_PAYLOAD_SIZE)-12) /* MX_WIFI_IPC_PAYLOAD_SIZE - socket_api_params_header */
+
+#ifndef MX_WIFI_CMD_TIMEOUT
+#define MX_WIFI_CMD_TIMEOUT (10000)
+#endif
+#define MX_WIFI_MAX_SOCKET_NBR (8)
+#define MX_WIFI_MAX_DETECTED_AP (10)
+
+#define MX_WIFI_MAX_SSID_NAME_SIZE 32
+#define MX_WIFI_MAX_PSWD_NAME_SIZE 64
+
+#define MX_WIFI_PRODUCT_NAME_SIZE 32
+#define MX_WIFI_PRODUCT_ID_SIZE 32
+
+#define MX_WIFI_FW_REV_SIZE 24
+#ifndef MX_WIFI_SPI_THREAD_PRIORITY
+#define MX_WIFI_SPI_THREAD_PRIORITY (OSPRIORITYREALTIME)
+#endif /* MX_WIFI_SPI_THREAD_PRIORITY */
+#ifndef MX_WIFI_SPI_THREAD_STACK_SIZE
+#define MX_WIFI_SPI_THREAD_STACK_SIZE (1024)
+#endif /* MX_WIFI_SPI_THREAD_STACK_SIZE */
+
+
+
+#ifndef MX_WIFI_RECEIVED_THREAD_PRIORITY
+#define MX_WIFI_RECEIVED_THREAD_PRIORITY (OSPRIORITYABOVENORMAL)
+#endif /* MX_WIFI_RECEIVED_THREAD_PRIORITY */
+
+#ifndef MX_WIFI_RECEIVED_THREAD_STACK_SIZE
+#define MX_WIFI_RECEIVED_THREAD_STACK_SIZE (1024)
+#endif /* MX_WIFI_RECEIVED_THREAD_STACK_SIZE*/
+
+#ifndef MX_WIFI_TRANSMIT_THREAD_PRIORITY
+#define MX_WIFI_TRANSMIT_THREAD_PRIORITY (OSPRIORITYABOVENORMAL)
+#endif /* MX_WIFI_TRANSMIT_THREAD_PRIORITY */
+
+#ifndef MX_WIFI_TRANSMIT_THREAD_STACK_SIZE
+#define MX_WIFI_TRANSMIT_THREAD_STACK_SIZE (1024)
+#endif /* MX_WIFI_TRANSMIT_THREAD_STACK_SIZE */
+
+
+/* Maximum number of RX buffer that can be queued by Hardware interface (SPI/UART) */
+/* This is used to size internal queue, and avoid to block the IP thread if it can still push some buffers */
+/* Impact on Memory foot print is weak , one single void* per place in the queue */
+#ifndef MX_WIFI_MAX_RX_BUFFER_COUNT
+#define MX_WIFI_MAX_RX_BUFFER_COUNT (2)
+#endif /* MX_WIFI_MAX_RX_BUFFER_COUNT */
+
+
+/* Maximum number of TX buffer that can be queued by IP stack (LwIP or Netx) without blocking the calling thread */
+/* This is used to size internal queue, and avoid to block the IP thread if it can still push some buffers */
+/* Impact on Memory foot print is one single void* per place in the queue, but it may lead to over allocation */
+/* TCP/IP stack (LwIP for instance ) */
+#ifndef MX_WIFI_MAX_TX_BUFFER_COUNT
+#define MX_WIFI_MAX_TX_BUFFER_COUNT (4)
+#endif /* MX_WIFI_MAX_TX_BUFFER_COUNT */
+
+
+
+/* For the TX buffer , by default no-copy feature is enabled , meaning that IP buffer are used in the whole process and should come with */
+/* available room in front of payload to accommodate transport header buffer. This is managed in interface between driver and IP stack */
+/* for LwIP "PBUF_LINK_ENCAPSULATION_HLEN" must be defined as > MX_WIFI_MIN_TX_HEADER_SIZE , see net_mx_wifi/c file for implementation */
+#define MX_WIFI_MIN_TX_HEADER_SIZE (28)
+
+#ifndef MX_WIFI_TX_BUFFER_NO_COPY
+#define MX_WIFI_TX_BUFFER_NO_COPY (1)
+#endif /* MX_WIFI_TX_BUFFER_NO_COPY */
+
+
+/* Sizeof the circular buffer for Uart mode, when buffer is hlaf full data are transmitted to next stage */
+#ifndef MX_CIRCULAR_UART_RX_BUFFER_SIZE
+#define MX_CIRCULAR_UART_RX_BUFFER_SIZE (400)
+#endif /* MX_CIRCULAR_UART_RX_BUFFER_SIZE */
+
+
+
+#ifndef MX_STAT_ON
+#define MX_STAT_ON 1
+#endif /* MX_STAT_ON */
+
+#if MX_STAT_ON == 1
+typedef struct
+{
+ uint32_t alloc;
+ uint32_t free;
+ uint32_t cmd_get_answer;
+ uint32_t callback;
+ uint32_t in_fifo;
+ uint32_t out_fifo;
+}
+mx_stat_t;
+extern mx_stat_t mx_stat;
+
+#define MX_STAT_LOG() (void) printf("Number of allocated buffer for Rx and command answer %lu\n",(ULONG)mx_stat.alloc);\
+ (void) printf("Number of free buffer %lu\n",(ULONG)mx_stat.free);\
+ (void) printf("Number of command answer %lu , callback %lu , sum of both %lu (should match alloc && free)\n", (ULONG)mx_stat.cmd_get_answer,(ULONG)mx_stat.callback,(ULONG)(mx_stat.cmd_get_answer+mx_stat.callback));\
+ (void) printf("Number of posted answer (callback + cmd answer) %lu , processed answer %lu\n",(ULONG)mx_stat.in_fifo,(ULONG)mx_stat.out_fifo);\
+
+#define MX_STAT_INIT() (void) memset((void*)&mx_stat,0,sizeof(mx_stat))
+#define MX_STAT(A) mx_stat.A++
+#define MX_STAT_DECLARE() mx_stat_t mx_stat
+
+#else
+
+#define MX_STAT_INIT()
+#define MX_STAT(A)
+#define MX_STAT_LOG()
+#define MX_STAT_DECLARE()
+
+#endif /* MX_STAT_ON */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MX_WIFI_CONF */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/stmcubemx/stm32u5xx_hal_conf.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/stmcubemx/stm32u5xx_hal_conf.h
new file mode 100644
index 00000000..f17ed036
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/stmcubemx/stm32u5xx_hal_conf.h
@@ -0,0 +1,476 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_conf.h
+ * @author MCD Application Team
+ * @brief HAL configuration file.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_CONF_H
+#define STM32U5xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+
+#define HAL_MODULE_ENABLED
+
+/*#define HAL_ADC_MODULE_ENABLED */
+/*#define HAL_MDF_MODULE_ENABLED */
+/*#define HAL_COMP_MODULE_ENABLED */
+/*#define HAL_CORDIC_MODULE_ENABLED */
+/*#define HAL_CRC_MODULE_ENABLED */
+/*#define HAL_CRYP_MODULE_ENABLED */
+/*#define HAL_DAC_MODULE_ENABLED */
+/*#define HAL_DMA2D_MODULE_ENABLED */
+/*#define HAL_FDCAN_MODULE_ENABLED */
+/*#define HAL_FMAC_MODULE_ENABLED */
+/*#define HAL_GTZC_MODULE_ENABLED */
+/*#define HAL_HASH_MODULE_ENABLED */
+/*#define HAL_HRTIM_MODULE_ENABLED */
+/*#define HAL_IRDA_MODULE_ENABLED */
+/*#define HAL_IWDG_MODULE_ENABLED */
+#define HAL_I2C_MODULE_ENABLED
+/*#define HAL_I2S_MODULE_ENABLED */
+/*#define HAL_LPTIM_MODULE_ENABLED */
+/*#define HAL_NAND_MODULE_ENABLED */
+/*#define HAL_NOR_MODULE_ENABLED */
+/*#define HAL_OPAMP_MODULE_ENABLED */
+/*#define HAL_OSPI_MODULE_ENABLED */
+/*#define HAL_OTFDEC_MODULE_ENABLED */
+/*#define HAL_PCD_MODULE_ENABLED */
+/*#define HAL_PKA_MODULE_ENABLED */
+/*#define HAL_QSPI_MODULE_ENABLED */
+#define HAL_RNG_MODULE_ENABLED
+//#define HAL_RTC_MODULE_ENABLED
+/*#define HAL_SAI_MODULE_ENABLED */
+/*#define HAL_CRYP_MODULE_ENABLED */
+/*#define HAL_SD_MODULE_ENABLED */
+/*#define HAL_MMC_MODULE_ENABLED */
+/*#define HAL_SMARTCARD_MODULE_ENABLED */
+/*#define HAL_SMBUS_MODULE_ENABLED */
+#define HAL_SPI_MODULE_ENABLED
+/*#define HAL_SRAM_MODULE_ENABLED */
+#define HAL_TIM_MODULE_ENABLED
+/*#define HAL_TSC_MODULE_ENABLED */
+/*#define HAL_RAMCFG_MODULE_ENABLED */
+#define HAL_UART_MODULE_ENABLED
+/*#define HAL_USART_MODULE_ENABLED */
+/*#define HAL_WWDG_MODULE_ENABLED */
+/*#define HAL_DCMI_MODULE_ENABLED */
+/*#define HAL_PSSI_MODULE_ENABLED */
+#define HAL_ICACHE_MODULE_ENABLED
+/*#define HAL_DCACHE_MODULE_ENABLED */
+/*#define HAL_PCD_MODULE_ENABLED */
+/*#define HAL_HCD_MODULE_ENABLED */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSE is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE 16000000UL /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSE_STARTUP_TIMEOUT)
+ #define HSE_STARTUP_TIMEOUT 100UL /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal Multiple Speed oscillator (MSI) default value.
+ * This value is the default MSI range value after Reset.
+ */
+#if !defined (MSI_VALUE)
+ #define MSI_VALUE 4000000UL /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSI is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE 16000000UL /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG.
+ * This internal oscillator is mainly dedicated to provide a high precision clock to
+ * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
+ * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
+ * which is subject to manufacturing process variations.
+ */
+#if !defined (HSI48_VALUE)
+ #define HSI48_VALUE 48000000UL /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.
+ The real value my vary depending on manufacturing process variations.*/
+#endif /* HSI48_VALUE */
+
+/**
+ * @brief Internal Low Speed oscillator (LSI) value.
+ */
+#if !defined (LSI_VALUE)
+ #define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
+ The real value may vary depending on the variations
+ in voltage and temperature.*/
+/**
+ * @brief External Low Speed oscillator (LSE) value.
+ * This value is used by the UART, RTC HAL module to compute the system frequency
+ */
+#if !defined (LSE_VALUE)
+ #define LSE_VALUE 32768UL /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined (LSE_STARTUP_TIMEOUT)
+ #define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief External clock source for SAI1 peripheral
+ * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
+ * frequency.
+ */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+ #define EXTERNAL_SAI1_CLOCK_VALUE 48000UL /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+ === you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+ * @brief This is the HAL system configuration section
+ */
+
+#define VDD_VALUE 3300UL /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority (lowest by default) */
+#define USE_RTOS 0U
+#define PREFETCH_ENABLE 1U /*!< Enable prefetch */
+
+/* ########################## Assert Selection ############################## */
+/**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * HAL drivers code
+ */
+
+/* #define USE_FULL_ASSERT 1U */
+
+/* ################## Register callback feature configuration ############### */
+/**
+ * @brief Set below the peripheral configuration to "1U" to add the support
+ * of HAL callback registration/unregistration feature for the HAL
+ * driver(s). This allows user application to provide specific callback
+ * functions thanks to HAL_PPP_RegisterCallback() rather than overwriting
+ * the default weak callback functions (see each stm32u5xx_hal_ppp.h file
+ * for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef
+ * for each PPP peripheral).
+ */
+#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
+#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */
+#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U /* CORDIC register callback disabled */
+#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */
+#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
+#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */
+#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */
+#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */
+#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */
+#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U /* FMAC register callback disabled */
+#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */
+#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */
+#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
+#define USE_HAL_IWDG_REGISTER_CALLBACKS 0U /* IWDG register callback disabled */
+#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */
+#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */
+#define USE_HAL_MDF_REGISTER_CALLBACKS 0U /* MDF register callback disabled */
+#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */
+#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */
+#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */
+#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */
+#define USE_HAL_OTFDEC_REGISTER_CALLBACKS 0U /* OTFDEC register callback disabled */
+#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */
+#define USE_HAL_PKA_REGISTER_CALLBACKS 0U /* PKA register callback disabled */
+#define USE_HAL_RAMCFG_REGISTER_CALLBACKS 0U /* RAMCFG register callback disabled */
+#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */
+#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
+#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */
+#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */
+#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */
+#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
+#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */
+#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
+#define USE_HAL_TSC_REGISTER_CALLBACKS 0U /* TSC register callback disabled */
+#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
+#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
+#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+#define USE_SPI_CRC 0U
+
+/* ################## SDMMC peripheral configuration ######################### */
+
+#define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Include module's header file
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+ #include "stm32u5xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+ #include "stm32u5xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_ICACHE_MODULE_ENABLED
+ #include "stm32u5xx_hal_icache.h"
+#endif /* HAL_ICACHE_MODULE_ENABLED */
+
+#ifdef HAL_DCACHE_MODULE_ENABLED
+ #include "stm32u5xx_hal_dcache.h"
+#endif /* HAL_DCACHE_MODULE_ENABLED */
+
+#ifdef HAL_GTZC_MODULE_ENABLED
+ #include "stm32u5xx_hal_gtzc.h"
+#endif /* HAL_GTZC_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+ #include "stm32u5xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+ #include "stm32u5xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+ #include "stm32u5xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+ #include "stm32u5xx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+ #include "stm32u5xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+ #include "stm32u5xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+ #include "stm32u5xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+ #include "stm32u5xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+ #include "stm32u5xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+ #include "stm32u5xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32u5xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+ #include "stm32u5xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32u5xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+ #include "stm32u5xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+ #include "stm32u5xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32u5xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32u5xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32u5xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+#include "stm32u5xx_hal_opamp.h"
+#endif /* HAL_OPAMP_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32u5xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+ #include "stm32u5xx_hal_ospi.h"
+#endif /* HAL_OSPI_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32u5xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32u5xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32u5xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32u5xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32u5xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32u5xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32u5xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+ #include "stm32u5xx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32u5xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32u5xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32u5xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32u5xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32u5xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32u5xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32u5xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_CORDIC_MODULE_ENABLED
+ #include "stm32u5xx_hal_cordic.h"
+#endif /* HAL_CORDIC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+ #include "stm32u5xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+ #include "stm32u5xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+ #include "stm32u5xx_hal_fdcan.h"
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+
+#ifdef HAL_FMAC_MODULE_ENABLED
+ #include "stm32u5xx_hal_fmac.h"
+#endif /* HAL_FMAC_MODULE_ENABLED */
+
+#ifdef HAL_OTFDEC_MODULE_ENABLED
+ #include "stm32u5xx_hal_otfdec.h"
+#endif /* HAL_OTFDEC_MODULE_ENABLED */
+
+#ifdef HAL_PSSI_MODULE_ENABLED
+ #include "stm32u5xx_hal_pssi.h"
+#endif /* HAL_PSSI_MODULE_ENABLED */
+
+#ifdef HAL_RAMCFG_MODULE_ENABLED
+ #include "stm32u5xx_hal_ramcfg.h"
+#endif /* HAL_RAMCFG_MODULE_ENABLED */
+
+#ifdef HAL_MDF_MODULE_ENABLED
+ #include "stm32u5xx_hal_mdf.h"
+#endif /* HAL_MDF_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_failed(uint8_t *file, uint32_t line);
+#else
+ #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_CONF_H */
+
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/stmcubemx/stm32u5xx_hal_msp.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/stmcubemx/stm32u5xx_hal_msp.c
new file mode 100644
index 00000000..1d74385f
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/stmcubemx/stm32u5xx_hal_msp.c
@@ -0,0 +1,295 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_msp.c
+ * @brief This file provides code for the MSP Initialization
+ * and de-Initialization codes.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+ * Initializes the Global MSP.
+ */
+void HAL_MspInit(void)
+{
+ /* USER CODE BEGIN MspInit 0 */
+
+ /* USER CODE END MspInit 0 */
+
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* System interrupt init*/
+
+ /** Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral
+ */
+ HAL_PWREx_DisableUCPDDeadBattery();
+
+ /* USER CODE BEGIN MspInit 1 */
+
+ /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief RNG MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hrng: RNG handle pointer
+* @retval None
+*/
+void HAL_RNG_MspInit(RNG_HandleTypeDef* hrng)
+{
+ RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+ if(hrng->Instance==RNG)
+ {
+ /* USER CODE BEGIN RNG_MspInit 0 */
+
+ /* USER CODE END RNG_MspInit 0 */
+ /** Initializes the peripherals clock
+ */
+ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RNG;
+ PeriphClkInit.RngClockSelection = RCC_RNGCLKSOURCE_HSI48;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /* Peripheral clock enable */
+ __HAL_RCC_RNG_CLK_ENABLE();
+ /* USER CODE BEGIN RNG_MspInit 1 */
+
+ /* USER CODE END RNG_MspInit 1 */
+ }
+
+}
+
+/**
+* @brief RNG MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hrng: RNG handle pointer
+* @retval None
+*/
+void HAL_RNG_MspDeInit(RNG_HandleTypeDef* hrng)
+{
+ if(hrng->Instance==RNG)
+ {
+ /* USER CODE BEGIN RNG_MspDeInit 0 */
+
+ /* USER CODE END RNG_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __HAL_RCC_RNG_CLK_DISABLE();
+ /* USER CODE BEGIN RNG_MspDeInit 1 */
+
+ /* USER CODE END RNG_MspDeInit 1 */
+ }
+
+}
+
+/**
+* @brief SPI MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hspi: SPI handle pointer
+* @retval None
+*/
+void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
+{
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+ RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+ if(hspi->Instance==SPI2)
+ {
+ /* USER CODE BEGIN SPI2_MspInit 0 */
+
+ /* USER CODE END SPI2_MspInit 0 */
+ /** Initializes the peripherals clock
+ */
+ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SPI2;
+ PeriphClkInit.Spi2ClockSelection = RCC_SPI2CLKSOURCE_PCLK1;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /* Peripheral clock enable */
+ __HAL_RCC_SPI2_CLK_ENABLE();
+
+ __HAL_RCC_GPIOD_CLK_ENABLE();
+ /**SPI2 GPIO Configuration
+ PD4 ------> SPI2_MOSI
+ PD3 ------> SPI2_MISO
+ PD1 ------> SPI2_SCK
+ */
+ GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_3|GPIO_PIN_1;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
+ HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+ /* USER CODE BEGIN SPI2_MspInit 1 */
+
+ /* USER CODE END SPI2_MspInit 1 */
+ }
+
+}
+
+/**
+* @brief SPI MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hspi: SPI handle pointer
+* @retval None
+*/
+void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi)
+{
+ if(hspi->Instance==SPI2)
+ {
+ /* USER CODE BEGIN SPI2_MspDeInit 0 */
+
+ /* USER CODE END SPI2_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __HAL_RCC_SPI2_CLK_DISABLE();
+
+ /**SPI2 GPIO Configuration
+ PD4 ------> SPI2_MOSI
+ PD3 ------> SPI2_MISO
+ PD1 ------> SPI2_SCK
+ */
+ HAL_GPIO_DeInit(GPIOD, GPIO_PIN_4|GPIO_PIN_3|GPIO_PIN_1);
+
+ /* USER CODE BEGIN SPI2_MspDeInit 1 */
+
+ /* USER CODE END SPI2_MspDeInit 1 */
+ }
+
+}
+
+/**
+* @brief UART MSP Initialization
+* This function configures the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+ RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+ if(huart->Instance==USART1)
+ {
+ /* USER CODE BEGIN USART1_MspInit 0 */
+
+ /* USER CODE END USART1_MspInit 0 */
+ /** Initializes the peripherals clock
+ */
+ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1;
+ PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /* Peripheral clock enable */
+ __HAL_RCC_USART1_CLK_ENABLE();
+
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ /**USART1 GPIO Configuration
+ PA10 ------> USART1_RX
+ PA9 ------> USART1_TX
+ */
+ GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_9;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
+ HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+ /* USART1 interrupt Init */
+ HAL_NVIC_SetPriority(USART1_IRQn, 5, 0);
+ HAL_NVIC_EnableIRQ(USART1_IRQn);
+ /* USER CODE BEGIN USART1_MspInit 1 */
+
+ /* USER CODE END USART1_MspInit 1 */
+ }
+
+}
+
+/**
+* @brief UART MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
+{
+ if(huart->Instance==USART1)
+ {
+ /* USER CODE BEGIN USART1_MspDeInit 0 */
+
+ /* USER CODE END USART1_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __HAL_RCC_USART1_CLK_DISABLE();
+
+ /**USART1 GPIO Configuration
+ PA10 ------> USART1_RX
+ PA9 ------> USART1_TX
+ */
+ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_10|GPIO_PIN_9);
+
+ /* USART1 interrupt DeInit */
+ HAL_NVIC_DisableIRQ(USART1_IRQn);
+ /* USER CODE BEGIN USART1_MspDeInit 1 */
+
+ /* USER CODE END USART1_MspDeInit 1 */
+ }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/stmcubemx/stm32u5xx_hal_timebase_tim.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/stmcubemx/stm32u5xx_hal_timebase_tim.c
new file mode 100644
index 00000000..8777d45c
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/stmcubemx/stm32u5xx_hal_timebase_tim.c
@@ -0,0 +1,110 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_timebase_TIM.c
+ * @brief HAL time base based on the hardware TIM.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u5xx_hal.h"
+#include "stm32u5xx_hal_tim.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+TIM_HandleTypeDef htim6;
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @brief This function configures the TIM6 as a time base source.
+ * The time source is configured to have 1ms time base with a dedicated
+ * Tick interrupt priority.
+ * @note This function is called automatically at the beginning of program after
+ * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
+ * @param TickPriority: Tick interrupt priority.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+ RCC_ClkInitTypeDef clkconfig;
+ uint32_t uwTimclock = 0;
+ uint32_t uwPrescalerValue = 0;
+ uint32_t pFLatency;
+ /*Configure the TIM6 IRQ priority */
+ HAL_NVIC_SetPriority(TIM6_IRQn, TickPriority ,0);
+
+ /* Enable the TIM6 global Interrupt */
+ HAL_NVIC_EnableIRQ(TIM6_IRQn);
+
+ /* Enable TIM6 clock */
+ __HAL_RCC_TIM6_CLK_ENABLE();
+
+ /* Get clock configuration */
+ HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
+
+ /* Compute TIM6 clock */
+ uwTimclock = HAL_RCC_GetPCLK1Freq();
+ /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */
+ uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
+
+ /* Initialize TIM6 */
+ htim6.Instance = TIM6;
+
+ /* Initialize TIMx peripheral as follow:
+ + Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base.
+ + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
+ + ClockDivision = 0
+ + Counter direction = Up
+ */
+ htim6.Init.Period = (1000000U / 1000U) - 1U;
+ htim6.Init.Prescaler = uwPrescalerValue;
+ htim6.Init.ClockDivision = 0;
+ htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
+
+ if(HAL_TIM_Base_Init(&htim6) == HAL_OK)
+ {
+ /* Start the TIM time Base generation in interrupt mode */
+ return HAL_TIM_Base_Start_IT(&htim6);
+ }
+
+ /* Return function status */
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Suspend Tick increment.
+ * @note Disable the tick increment by disabling TIM6 update interrupt.
+ * @param None
+ * @retval None
+ */
+void HAL_SuspendTick(void)
+{
+ /* Disable TIM6 update Interrupt */
+ __HAL_TIM_DISABLE_IT(&htim6, TIM_IT_UPDATE);
+}
+
+/**
+ * @brief Resume Tick increment.
+ * @note Enable the tick increment by Enabling TIM6 update interrupt.
+ * @param None
+ * @retval None
+ */
+void HAL_ResumeTick(void)
+{
+ /* Enable TIM6 Update interrupt */
+ __HAL_TIM_ENABLE_IT(&htim6, TIM_IT_UPDATE);
+}
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/stmcubemx/stm32u5xx_it.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/stmcubemx/stm32u5xx_it.c
new file mode 100644
index 00000000..7558b6b0
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/stmcubemx/stm32u5xx_it.c
@@ -0,0 +1,221 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file stm32u5xx_it.c
+ * @brief Interrupt Service Routines.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32u5xx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern UART_HandleTypeDef huart1;
+extern TIM_HandleTypeDef htim6;
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/* Cortex Processor Interruption and Exception Handlers */
+/******************************************************************************/
+/**
+ * @brief This function handles Non maskable interrupt.
+ */
+void NMI_Handler(void)
+{
+ /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+ /* USER CODE END NonMaskableInt_IRQn 0 */
+ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+ while (1)
+ {
+ }
+ /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+ * @brief This function handles Hard fault interrupt.
+ */
+void HardFault_Handler(void)
+{
+ /* USER CODE BEGIN HardFault_IRQn 0 */
+
+ /* USER CODE END HardFault_IRQn 0 */
+ while (1)
+ {
+ /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+ /* USER CODE END W1_HardFault_IRQn 0 */
+ }
+}
+
+/**
+ * @brief This function handles Memory management fault.
+ */
+void MemManage_Handler(void)
+{
+ /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+ /* USER CODE END MemoryManagement_IRQn 0 */
+ while (1)
+ {
+ /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+ /* USER CODE END W1_MemoryManagement_IRQn 0 */
+ }
+}
+
+/**
+ * @brief This function handles Prefetch fault, memory access fault.
+ */
+void BusFault_Handler(void)
+{
+ /* USER CODE BEGIN BusFault_IRQn 0 */
+
+ /* USER CODE END BusFault_IRQn 0 */
+ while (1)
+ {
+ /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+ /* USER CODE END W1_BusFault_IRQn 0 */
+ }
+}
+
+/**
+ * @brief This function handles Undefined instruction or illegal state.
+ */
+void UsageFault_Handler(void)
+{
+ /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+ /* USER CODE END UsageFault_IRQn 0 */
+ while (1)
+ {
+ /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+ /* USER CODE END W1_UsageFault_IRQn 0 */
+ }
+}
+
+/**
+ * @brief This function handles Debug monitor.
+ */
+void DebugMon_Handler(void)
+{
+ /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+ /* USER CODE END DebugMonitor_IRQn 0 */
+ /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+ /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32U5xx Peripheral Interrupt Handlers */
+/* Add here the Interrupt Handlers for the used peripherals. */
+/* For the available peripheral interrupt handler names, */
+/* please refer to the startup file (startup_stm32u5xx.s). */
+/******************************************************************************/
+
+/**
+ * @brief This function handles EXTI Line14 interrupt.
+ */
+void EXTI14_IRQHandler(void)
+{
+ /* USER CODE BEGIN EXTI14_IRQn 0 */
+
+ /* USER CODE END EXTI14_IRQn 0 */
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_14);
+ /* USER CODE BEGIN EXTI14_IRQn 1 */
+
+ /* USER CODE END EXTI14_IRQn 1 */
+}
+
+/**
+ * @brief This function handles EXTI Line15 interrupt.
+ */
+void EXTI15_IRQHandler(void)
+{
+ /* USER CODE BEGIN EXTI15_IRQn 0 */
+
+ /* USER CODE END EXTI15_IRQn 0 */
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_15);
+ /* USER CODE BEGIN EXTI15_IRQn 1 */
+
+ /* USER CODE END EXTI15_IRQn 1 */
+}
+
+/**
+ * @brief This function handles TIM6 global interrupt.
+ */
+void TIM6_IRQHandler(void)
+{
+ /* USER CODE BEGIN TIM6_IRQn 0 */
+
+ /* USER CODE END TIM6_IRQn 0 */
+ HAL_TIM_IRQHandler(&htim6);
+ /* USER CODE BEGIN TIM6_IRQn 1 */
+
+ /* USER CODE END TIM6_IRQn 1 */
+}
+
+/**
+ * @brief This function handles USART1 global interrupt.
+ */
+void USART1_IRQHandler(void)
+{
+ /* USER CODE BEGIN USART1_IRQn 0 */
+
+ /* USER CODE END USART1_IRQn 0 */
+ HAL_UART_IRQHandler(&huart1);
+ /* USER CODE BEGIN USART1_IRQn 1 */
+
+ /* USER CODE END USART1_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/stmcubemx/stm32u5xx_it.h b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/stmcubemx/stm32u5xx_it.h
new file mode 100644
index 00000000..15c42e85
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/stmcubemx/stm32u5xx_it.h
@@ -0,0 +1,67 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file stm32u5xx_it.h
+ * @brief This file contains the headers of the interrupt handlers.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32U5xx_IT_H
+#define __STM32U5xx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void DebugMon_Handler(void);
+void EXTI14_IRQHandler(void);
+void EXTI15_IRQHandler(void);
+void TIM6_IRQHandler(void);
+void USART1_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32U5xx_IT_H */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/stmcubemx/system_stm32u5xx.c b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/stmcubemx/system_stm32u5xx.c
new file mode 100644
index 00000000..8448c940
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/stm32cubeu5/stmcubemx/system_stm32u5xx.c
@@ -0,0 +1,361 @@
+/**
+ ******************************************************************************
+ * @file system_stm32u5xx.c
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File
+ *
+ * This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32u5xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ * After each device reset the MSI (4 MHz) is used as system clock source.
+ * Then SystemInit() function is called, in "startup_stm32u5xx.s" file, to
+ * configure the system clock before to branch to main program.
+ *
+ * This file configures the system clock as follows:
+ *=============================================================================
+ *-----------------------------------------------------------------------------
+ * System Clock source | MSI
+ *-----------------------------------------------------------------------------
+ * SYSCLK(Hz) | 4000000
+ *-----------------------------------------------------------------------------
+ * HCLK(Hz) | 4000000
+ *-----------------------------------------------------------------------------
+ * AHB Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * APB1 Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * APB2 Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * APB3 Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * PLL1_SRC | No clock
+ *-----------------------------------------------------------------------------
+ * PLL1_M | 1
+ *-----------------------------------------------------------------------------
+ * PLL1_N | 8
+ *-----------------------------------------------------------------------------
+ * PLL1_P | 7
+ *-----------------------------------------------------------------------------
+ * PLL1_Q | 2
+ *-----------------------------------------------------------------------------
+ * PLL1_R | 2
+ *-----------------------------------------------------------------------------
+ * PLL2_SRC | NA
+ *-----------------------------------------------------------------------------
+ * PLL2_M | NA
+ *-----------------------------------------------------------------------------
+ * PLL2_N | NA
+ *-----------------------------------------------------------------------------
+ * PLL2_P | NA
+ *-----------------------------------------------------------------------------
+ * PLL2_Q | NA
+ *-----------------------------------------------------------------------------
+ * PLL2_R | NA
+ *-----------------------------------------------------------------------------
+ * PLL3_SRC | NA
+ *-----------------------------------------------------------------------------
+ * PLL3_M | NA
+ *-----------------------------------------------------------------------------
+ * PLL3_N | NA
+ *-----------------------------------------------------------------------------
+ * PLL3_P | NA
+ *-----------------------------------------------------------------------------
+ * Require 48MHz for USB FS, | Disabled
+ * SDIO and RNG clock |
+ *-----------------------------------------------------------------------------
+ *=============================================================================
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup STM32U5xx_system
+ * @{
+ */
+
+/** @addtogroup STM32U5xx_System_Private_Includes
+ * @{
+ */
+
+#include "stm32u5xx.h"
+#include
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U5xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U5xx_System_Private_Defines
+ * @{
+ */
+
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE 16000000U /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (MSI_VALUE)
+ #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+/******************************************************************************/
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U5xx_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U5xx_System_Private_Variables
+ * @{
+ */
+ /* The SystemCoreClock variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+ uint32_t SystemCoreClock = 4000000U;
+
+ const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
+ const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
+ const uint32_t MSIRangeTable[16] = {48000000U,24000000U,16000000U,12000000U, 4000000U, 2000000U, 1500000U,\
+ 1000000U, 3072000U, 1536000U,1024000U, 768000U, 400000U, 200000U, 150000U, 100000U};
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U5xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U5xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system.
+ * @param None
+ * @retval None
+ */
+
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
+ #endif
+
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set MSION bit */
+ RCC->CR = RCC_CR_MSISON;
+
+ /* Reset CFGR register */
+ RCC->CFGR1 = 0U;
+ RCC->CFGR2 = 0U;
+ RCC->CFGR3 = 0U;
+
+ /* Reset HSEON, CSSON , HSION, PLLxON bits */
+ RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON);
+
+ /* Reset PLLCFGR register */
+ RCC->PLL1CFGR = 0U;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= ~(RCC_CR_HSEBYP);
+
+ /* Disable all interrupts */
+ RCC->CIER = 0U;
+
+ /* Configure the Vector Table location add offset address ------------------*/
+ #ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+ #else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+ #endif
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+ * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+ *
+ * (*) MSI_VALUE is a constant defined in stm32u5xx_hal.h file (default value
+ * 4 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSI_VALUE is a constant defined in stm32u5xx_hal.h file (default value
+ * 16 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (***) HSE_VALUE is a constant defined in stm32u5xx_hal.h file (default value
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate(void)
+{
+ uint32_t pllr, pllsource, pllm , tmp, pllfracen, msirange;
+ float_t fracn1, pllvco;
+
+ /* Get MSI Range frequency--------------------------------------------------*/
+ if(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL) == 0U)
+ {
+ /* MSISRANGE from RCC_CSR applies */
+ msirange = (RCC->CSR & RCC_CSR_MSISSRANGE) >> RCC_CSR_MSISSRANGE_Pos;
+ }
+ else
+ {
+ /* MSIRANGE from RCC_CR applies */
+ msirange = (RCC->ICSCR1 & RCC_ICSCR1_MSISRANGE) >> RCC_ICSCR1_MSISRANGE_Pos;
+ }
+
+ /*MSI frequency range in HZ*/
+ msirange = MSIRangeTable[msirange];
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ switch (RCC->CFGR1 & RCC_CFGR1_SWS)
+ {
+ case 0x00: /* MSI used as system clock source */
+ SystemCoreClock = msirange;
+ break;
+
+ case 0x04: /* HSI used as system clock source */
+ SystemCoreClock = HSI_VALUE;
+ break;
+
+ case 0x08: /* HSE used as system clock source */
+ SystemCoreClock = HSE_VALUE;
+ break;
+
+ case 0x0C: /* PLL used as system clock source */
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+ SYSCLK = PLL_VCO / PLLR
+ */
+ pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC);
+ pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M)>> RCC_PLL1CFGR_PLL1M_Pos) + 1U;
+ pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN)>>RCC_PLL1CFGR_PLL1FRACEN_Pos);
+ fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN)>> RCC_PLL1FRACR_PLL1FRACN_Pos));
+
+ switch (pllsource)
+ {
+ case 0x00: /* No clock sent to PLL*/
+ pllvco = (float_t)0U;
+ break;
+
+ case 0x02: /* HSI used as PLL clock source */
+ pllvco = ((float_t)HSI_VALUE / (float_t)pllm);
+ break;
+
+ case 0x03: /* HSE used as PLL clock source */
+ pllvco = ((float_t)HSE_VALUE / (float_t)pllm);
+ break;
+
+ default: /* MSI used as PLL clock source */
+ pllvco = ((float_t)msirange / (float_t)pllm);
+ break;
+ }
+
+ pllvco = pllvco * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + (fracn1/(float_t)0x2000) + (float_t)1U);
+ pllr = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U );
+ SystemCoreClock = (uint32_t)((uint32_t)pllvco/pllr);
+ break;
+
+ default:
+ SystemCoreClock = msirange;
+ break;
+ }
+ /* Compute HCLK clock frequency --------------------------------------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos)];
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMicroelectronics/B-U585I-IOT02A/lib/threadx/tx_user.h b/STMicroelectronics/B-U585I-IOT02A/lib/threadx/tx_user.h
new file mode 100644
index 00000000..62e5a122
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/lib/threadx/tx_user.h
@@ -0,0 +1,246 @@
+/**************************************************************************/
+/* */
+/* Copyright (c) Microsoft Corporation. All rights reserved. */
+/* */
+/* This software is licensed under the Microsoft Software License */
+/* Terms for Microsoft Azure RTOS. Full text of the license can be */
+/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
+/* and in the root directory of this software. */
+/* */
+/**************************************************************************/
+
+/**************************************************************************/
+/**************************************************************************/
+/** */
+/** ThreadX Component */
+/** */
+/** User Specific */
+/** */
+/**************************************************************************/
+/**************************************************************************/
+
+/**************************************************************************/
+/* */
+/* PORT SPECIFIC C INFORMATION RELEASE */
+/* */
+/* tx_user.h PORTABLE C */
+/* 6.0 */
+/* */
+/* AUTHOR */
+/* */
+/* William E. Lamie, Microsoft Corporation */
+/* */
+/* DESCRIPTION */
+/* */
+/* This file contains user defines for configuring ThreadX in specific */
+/* ways. This file will have an effect only if the application and */
+/* ThreadX library are built with TX_INCLUDE_USER_DEFINE_FILE defined. */
+/* Note that all the defines in this file may also be made on the */
+/* command line when building ThreadX library and application objects. */
+/* */
+/* RELEASE HISTORY */
+/* */
+/* DATE NAME DESCRIPTION */
+/* */
+/* 05-19-2020 William E. Lamie Initial Version 6.0 */
+/* */
+/**************************************************************************/
+
+#ifndef TX_USER_H
+#define TX_USER_H
+
+//#define TX_ENABLE_FPU_SUPPORT
+
+#define TX_SINGLE_MODE_SECURE
+
+/* Define various build options for the ThreadX port. The application should either make changes
+ here by commenting or un-commenting the conditional compilation defined OR supply the defines
+ though the compiler's equivalent of the -D option.
+
+ For maximum speed, the following should be defined:
+
+ TX_MAX_PRIORITIES 32
+ TX_DISABLE_PREEMPTION_THRESHOLD
+ TX_DISABLE_REDUNDANT_CLEARING
+ TX_DISABLE_NOTIFY_CALLBACKS
+ TX_NOT_INTERRUPTABLE
+ TX_TIMER_PROCESS_IN_ISR
+ TX_REACTIVATE_INLINE
+ TX_DISABLE_STACK_FILLING
+ TX_INLINE_THREAD_RESUME_SUSPEND
+
+ For minimum size, the following should be defined:
+
+ TX_MAX_PRIORITIES 32
+ TX_DISABLE_PREEMPTION_THRESHOLD
+ TX_DISABLE_REDUNDANT_CLEARING
+ TX_DISABLE_NOTIFY_CALLBACKS
+ TX_NOT_INTERRUPTABLE
+ TX_TIMER_PROCESS_IN_ISR
+
+ Of course, many of these defines reduce functionality and/or change the behavior of the
+ system in ways that may not be worth the trade-off. For example, the TX_TIMER_PROCESS_IN_ISR
+ results in faster and smaller code, however, it increases the amount of processing in the ISR.
+ In addition, some services that are available in timers are not available from ISRs and will
+ therefore return an error if this option is used. This may or may not be desirable for a
+ given application. */
+
+/* Override various options with default values already assigned in tx_port.h. Please also refer
+ to tx_port.h for descriptions on each of these options. */
+
+/*
+#define TX_MAX_PRIORITIES 32
+#define TX_MINIMUM_STACK ????
+#define TX_THREAD_USER_EXTENSION ????
+#define TX_TIMER_THREAD_STACK_SIZE ????
+#define TX_TIMER_THREAD_PRIORITY ????
+*/
+
+/* Determine if timer expirations (application timers, timeouts, and tx_thread_sleep calls
+ should be processed within the a system timer thread or directly in the timer ISR.
+ By default, the timer thread is used. When the following is defined, the timer expiration
+ processing is done directly from the timer ISR, thereby eliminating the timer thread control
+ block, stack, and context switching to activate it. */
+
+/*
+#define TX_TIMER_PROCESS_IN_ISR
+*/
+
+/* Determine if in-line timer reactivation should be used within the timer expiration processing.
+ By default, this is disabled and a function call is used. When the following is defined,
+ reactivating is performed in-line resulting in faster timer processing but slightly larger
+ code size. */
+
+/*
+#define TX_REACTIVATE_INLINE
+*/
+
+/* Determine is stack filling is enabled. By default, ThreadX stack filling is enabled,
+ which places an 0xEF pattern in each byte of each thread's stack. This is used by
+ debuggers with ThreadX-awareness and by the ThreadX run-time stack checking feature. */
+
+/*
+#define TX_DISABLE_STACK_FILLING
+*/
+
+/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is
+ disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack
+ checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
+ define is negated, thereby forcing the stack fill which is necessary for the stack checking
+ logic. */
+
+/*
+#define TX_ENABLE_STACK_CHECKING
+*/
+
+/* Determine if preemption-threshold should be disabled. By default, preemption-threshold is
+ enabled. If the application does not use preemption-threshold, it may be disabled to reduce
+ code size and improve performance. */
+#define TX_DISABLE_PREEMPTION_THRESHOLD
+
+/* Determine if global ThreadX variables should be cleared. If the compiler startup code clears
+ the .bss section prior to ThreadX running, the define can be used to eliminate unnecessary
+ clearing of ThreadX global variables. */
+
+/*
+#define TX_DISABLE_REDUNDANT_CLEARING
+*/
+
+/* Determine if no timer processing is required. This option will help eliminate the timer
+ processing when not needed. The user will also have to comment out the call to
+ tx_timer_interrupt, which is typically made from assembly language in
+ tx_initialize_low_level. Note: if TX_NO_TIMER is used, the define TX_TIMER_PROCESS_IN_ISR
+ must also be used. */
+
+/*
+#define TX_NO_TIMER
+#ifndef TX_TIMER_PROCESS_IN_ISR
+#define TX_TIMER_PROCESS_IN_ISR
+#endif
+*/
+
+/* Determine if the notify callback option should be disabled. By default, notify callbacks are
+ enabled. If the application does not use notify callbacks, they may be disabled to reduce
+ code size and improve performance. */
+#define TX_DISABLE_NOTIFY_CALLBACKS
+
+/* Determine if the tx_thread_resume and tx_thread_suspend services should have their internal
+ code in-line. This results in a larger image, but improves the performance of the thread
+ resume and suspend services. */
+
+/*
+#define TX_INLINE_THREAD_RESUME_SUSPEND
+*/
+
+/* Determine if the internal ThreadX code is non-interruptable. This results in smaller code
+ size and less processing overhead, but increases the interrupt lockout time. */
+
+/*
+#define TX_NOT_INTERRUPTABLE
+*/
+
+/* Determine if the trace event logging code should be enabled. This causes slight increases in
+ code size and overhead, but provides the ability to generate system trace information which
+ is available for viewing in TraceX. */
+
+/*
+#define TX_ENABLE_EVENT_TRACE
+*/
+
+/* Determine if block pool performance gathering is required by the application. When the following is
+ defined, ThreadX gathers various block pool performance information. */
+
+/*
+#define TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO
+*/
+
+/* Determine if byte pool performance gathering is required by the application. When the following is
+ defined, ThreadX gathers various byte pool performance information. */
+
+/*
+#define TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO
+*/
+
+/* Determine if event flags performance gathering is required by the application. When the following is
+ defined, ThreadX gathers various event flags performance information. */
+
+/*
+#define TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO
+*/
+
+/* Determine if mutex performance gathering is required by the application. When the following is
+ defined, ThreadX gathers various mutex performance information. */
+
+/*
+#define TX_MUTEX_ENABLE_PERFORMANCE_INFO
+*/
+
+/* Determine if queue performance gathering is required by the application. When the following is
+ defined, ThreadX gathers various queue performance information. */
+
+/*
+#define TX_QUEUE_ENABLE_PERFORMANCE_INFO
+*/
+
+/* Determine if semaphore performance gathering is required by the application. When the following is
+ defined, ThreadX gathers various semaphore performance information. */
+
+/*
+#define TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO
+*/
+
+/* Determine if thread performance gathering is required by the application. When the following is
+ defined, ThreadX gathers various thread performance information. */
+
+/*
+#define TX_THREAD_ENABLE_PERFORMANCE_INFO
+*/
+
+/* Determine if timer performance gathering is required by the application. When the following is
+ defined, ThreadX gathers various timer performance information. */
+
+/*
+#define TX_TIMER_ENABLE_PERFORMANCE_INFO
+*/
+
+#endif
diff --git a/STMicroelectronics/B-U585I-IOT02A/tools/flash.bat b/STMicroelectronics/B-U585I-IOT02A/tools/flash.bat
new file mode 100644
index 00000000..aee42cc0
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/tools/flash.bat
@@ -0,0 +1,7 @@
+:: Copyright (c) Microsoft Corporation.
+:: Licensed under the MIT License.
+
+setlocal
+cd /d %~dp0\..
+
+openocd -f interface/stlink.cfg -f target/stm32u5x.cfg -c "program build/app/stm32u585_azure_iot.elf verify" -c "reset halt" -c "shutdown"
\ No newline at end of file
diff --git a/STMicroelectronics/B-U585I-IOT02A/tools/rebuild.bat b/STMicroelectronics/B-U585I-IOT02A/tools/rebuild.bat
new file mode 100644
index 00000000..ca14edc4
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/tools/rebuild.bat
@@ -0,0 +1,14 @@
+:: Copyright (c) Microsoft Corporation.
+:: Licensed under the MIT License.
+
+@echo off
+
+setlocal
+cd /d %~dp0\..
+
+IF EXIST build (rd /S /Q build)
+
+cmake -Bbuild -GNinja -DCMAKE_TOOLCHAIN_FILE="../../cmake/arm-gcc-cortex-m33.cmake"
+cmake --build build
+
+IF %0 == "%~0" pause
\ No newline at end of file
diff --git a/STMicroelectronics/B-U585I-IOT02A/vcpkg-configuration.json b/STMicroelectronics/B-U585I-IOT02A/vcpkg-configuration.json
new file mode 100644
index 00000000..b4892136
--- /dev/null
+++ b/STMicroelectronics/B-U585I-IOT02A/vcpkg-configuration.json
@@ -0,0 +1,16 @@
+{
+ "registries": [
+ {
+ "name": "microsoft",
+ "location": "https://aka.ms/vcpkg-ce-default",
+ "kind": "artifact"
+ }
+ ],
+ "requires": {
+ "microsoft:compilers/arm/gcc": "* 2020.10.0",
+ "microsoft:tools/compuphase/termite": "* 3.4.0",
+ "microsoft:tools/microsoft/openocd": "0.11.0-ms2",
+ "microsoft:tools/kitware/cmake": "* 3.20.1",
+ "microsoft:tools/ninja-build/ninja": "* 1.10.2"
+ }
+}
\ No newline at end of file
diff --git a/cmake/arm-gcc-cortex-m33.cmake b/cmake/arm-gcc-cortex-m33.cmake
new file mode 100644
index 00000000..4847956a
--- /dev/null
+++ b/cmake/arm-gcc-cortex-m33.cmake
@@ -0,0 +1,11 @@
+# Copyright (c) Microsoft Corporation.
+# Licensed under the MIT License.
+
+# Define the CPU architecture for Threadx
+set(THREADX_ARCH "cortex_m33")
+set(THREADX_TOOLCHAIN "gnu")
+
+set(MCPU_FLAGS "-mthumb -mcpu=cortex-m33")
+set(VFP_FLAGS "-mfloat-abi=hard -mfpu=fpv5-sp-d16")
+
+include(${CMAKE_CURRENT_LIST_DIR}/arm-gcc-cortex-toolchain.cmake)
diff --git a/cmake/arm-iar-cortex-m33.cmake b/cmake/arm-iar-cortex-m33.cmake
new file mode 100644
index 00000000..02836ab8
--- /dev/null
+++ b/cmake/arm-iar-cortex-m33.cmake
@@ -0,0 +1,11 @@
+# Copyright (c) Microsoft Corporation.
+# Licensed under the MIT License.
+
+# Define the CPU architecture for Threadx
+set(THREADX_ARCH "cortex_m33")
+set(THREADX_TOOLCHAIN "iar")
+
+# Compiler flags needed to compile for this CPU
+set(CPU_FLAGS "--cpu Cortex-M33 --fpu VFPv5_sp")
+
+include(${CMAKE_CURRENT_LIST_DIR}/arm-iar-cortex-toolchain.cmake)
diff --git a/shared/lib/netxduo b/shared/lib/netxduo
index 5a546718..2973652d 160000
--- a/shared/lib/netxduo
+++ b/shared/lib/netxduo
@@ -1 +1 @@
-Subproject commit 5a546718050cf9764ecc02bfaec797cc34910637
+Subproject commit 2973652d801e92615caa285ad9ee13db19a26cb9
diff --git a/shared/lib/threadx b/shared/lib/threadx
index 3e8e85cd..37f6d0b3 160000
--- a/shared/lib/threadx
+++ b/shared/lib/threadx
@@ -1 +1 @@
-Subproject commit 3e8e85cdc1e51f9de577457377a4f9a4f6b9b82f
+Subproject commit 37f6d0b39c970b297c263cbb8388b9060b92e5c9